1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */ 3 4 5 #include "msm_gem.h" 6 #include "msm_mmu.h" 7 #include "msm_gpu_trace.h" 8 #include "a6xx_gpu.h" 9 #include "a6xx_gmu.xml.h" 10 11 #include <linux/bitfield.h> 12 #include <linux/devfreq.h> 13 #include <linux/nvmem-consumer.h> 14 #include <linux/soc/qcom/llcc-qcom.h> 15 16 #define GPU_PAS_ID 13 17 18 static inline bool _a6xx_check_idle(struct msm_gpu *gpu) 19 { 20 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 21 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 22 23 /* Check that the GMU is idle */ 24 if (!a6xx_gmu_isidle(&a6xx_gpu->gmu)) 25 return false; 26 27 /* Check tha the CX master is idle */ 28 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & 29 ~A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER) 30 return false; 31 32 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & 33 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT); 34 } 35 36 static bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 37 { 38 /* wait for CP to drain ringbuffer: */ 39 if (!adreno_idle(gpu, ring)) 40 return false; 41 42 if (spin_until(_a6xx_check_idle(gpu))) { 43 DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n", 44 gpu->name, __builtin_return_address(0), 45 gpu_read(gpu, REG_A6XX_RBBM_STATUS), 46 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS), 47 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), 48 gpu_read(gpu, REG_A6XX_CP_RB_WPTR)); 49 return false; 50 } 51 52 return true; 53 } 54 55 static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 56 { 57 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 58 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 59 60 /* Expanded APRIV doesn't need to issue the WHERE_AM_I opcode */ 61 if (a6xx_gpu->has_whereami && !adreno_gpu->base.hw_apriv) { 62 OUT_PKT7(ring, CP_WHERE_AM_I, 2); 63 OUT_RING(ring, lower_32_bits(shadowptr(a6xx_gpu, ring))); 64 OUT_RING(ring, upper_32_bits(shadowptr(a6xx_gpu, ring))); 65 } 66 } 67 68 static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 69 { 70 uint32_t wptr; 71 unsigned long flags; 72 73 update_shadow_rptr(gpu, ring); 74 75 spin_lock_irqsave(&ring->preempt_lock, flags); 76 77 /* Copy the shadow to the actual register */ 78 ring->cur = ring->next; 79 80 /* Make sure to wrap wptr if we need to */ 81 wptr = get_wptr(ring); 82 83 spin_unlock_irqrestore(&ring->preempt_lock, flags); 84 85 /* Make sure everything is posted before making a decision */ 86 mb(); 87 88 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); 89 } 90 91 static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, 92 u64 iova) 93 { 94 OUT_PKT7(ring, CP_REG_TO_MEM, 3); 95 OUT_RING(ring, CP_REG_TO_MEM_0_REG(counter) | 96 CP_REG_TO_MEM_0_CNT(2) | 97 CP_REG_TO_MEM_0_64B); 98 OUT_RING(ring, lower_32_bits(iova)); 99 OUT_RING(ring, upper_32_bits(iova)); 100 } 101 102 static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, 103 struct msm_ringbuffer *ring, struct msm_file_private *ctx) 104 { 105 phys_addr_t ttbr; 106 u32 asid; 107 u64 memptr = rbmemptr(ring, ttbr0); 108 109 if (ctx->seqno == a6xx_gpu->base.base.cur_ctx_seqno) 110 return; 111 112 if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid)) 113 return; 114 115 /* Execute the table update */ 116 OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4); 117 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr))); 118 119 OUT_RING(ring, 120 CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) | 121 CP_SMMU_TABLE_UPDATE_1_ASID(asid)); 122 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0)); 123 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0)); 124 125 /* 126 * Write the new TTBR0 to the memstore. This is good for debugging. 127 */ 128 OUT_PKT7(ring, CP_MEM_WRITE, 4); 129 OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr))); 130 OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr))); 131 OUT_RING(ring, lower_32_bits(ttbr)); 132 OUT_RING(ring, (asid << 16) | upper_32_bits(ttbr)); 133 134 /* 135 * And finally, trigger a uche flush to be sure there isn't anything 136 * lingering in that part of the GPU 137 */ 138 139 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 140 OUT_RING(ring, 0x31); 141 } 142 143 static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 144 { 145 unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; 146 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 147 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 148 struct msm_ringbuffer *ring = submit->ring; 149 unsigned int i, ibs = 0; 150 151 a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx); 152 153 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0), 154 rbmemptr_stats(ring, index, cpcycles_start)); 155 156 /* 157 * For PM4 the GMU register offsets are calculated from the base of the 158 * GPU registers so we need to add 0x1a800 to the register value on A630 159 * to get the right value from PM4. 160 */ 161 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO, 162 rbmemptr_stats(ring, index, alwayson_start)); 163 164 /* Invalidate CCU depth and color */ 165 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 166 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_DEPTH)); 167 168 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 169 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_COLOR)); 170 171 /* Submit the commands */ 172 for (i = 0; i < submit->nr_cmds; i++) { 173 switch (submit->cmd[i].type) { 174 case MSM_SUBMIT_CMD_IB_TARGET_BUF: 175 break; 176 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: 177 if (gpu->cur_ctx_seqno == submit->queue->ctx->seqno) 178 break; 179 fallthrough; 180 case MSM_SUBMIT_CMD_BUF: 181 OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3); 182 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); 183 OUT_RING(ring, upper_32_bits(submit->cmd[i].iova)); 184 OUT_RING(ring, submit->cmd[i].size); 185 ibs++; 186 break; 187 } 188 189 /* 190 * Periodically update shadow-wptr if needed, so that we 191 * can see partial progress of submits with large # of 192 * cmds.. otherwise we could needlessly stall waiting for 193 * ringbuffer state, simply due to looking at a shadow 194 * rptr value that has not been updated 195 */ 196 if ((ibs % 32) == 0) 197 update_shadow_rptr(gpu, ring); 198 } 199 200 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0), 201 rbmemptr_stats(ring, index, cpcycles_end)); 202 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO, 203 rbmemptr_stats(ring, index, alwayson_end)); 204 205 /* Write the fence to the scratch register */ 206 OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1); 207 OUT_RING(ring, submit->seqno); 208 209 /* 210 * Execute a CACHE_FLUSH_TS event. This will ensure that the 211 * timestamp is written to the memory and then triggers the interrupt 212 */ 213 OUT_PKT7(ring, CP_EVENT_WRITE, 4); 214 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(CACHE_FLUSH_TS) | 215 CP_EVENT_WRITE_0_IRQ); 216 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence))); 217 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); 218 OUT_RING(ring, submit->seqno); 219 220 trace_msm_gpu_submit_flush(submit, 221 gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO, 222 REG_A6XX_CP_ALWAYS_ON_COUNTER_HI)); 223 224 a6xx_flush(gpu, ring); 225 } 226 227 const struct adreno_reglist a630_hwcg[] = { 228 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, 229 {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222}, 230 {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222}, 231 {REG_A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222}, 232 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220}, 233 {REG_A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220}, 234 {REG_A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220}, 235 {REG_A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220}, 236 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 237 {REG_A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080}, 238 {REG_A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080}, 239 {REG_A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080}, 240 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf}, 241 {REG_A6XX_RBBM_CLOCK_HYST_SP1, 0x0000f3cf}, 242 {REG_A6XX_RBBM_CLOCK_HYST_SP2, 0x0000f3cf}, 243 {REG_A6XX_RBBM_CLOCK_HYST_SP3, 0x0000f3cf}, 244 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, 245 {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222}, 246 {REG_A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222}, 247 {REG_A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222}, 248 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 249 {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222}, 250 {REG_A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222}, 251 {REG_A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222}, 252 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 253 {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222}, 254 {REG_A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222}, 255 {REG_A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222}, 256 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 257 {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222}, 258 {REG_A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222}, 259 {REG_A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222}, 260 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 261 {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777}, 262 {REG_A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777}, 263 {REG_A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777}, 264 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 265 {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777}, 266 {REG_A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777}, 267 {REG_A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777}, 268 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 269 {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777}, 270 {REG_A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777}, 271 {REG_A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777}, 272 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 273 {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777}, 274 {REG_A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777}, 275 {REG_A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777}, 276 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 277 {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111}, 278 {REG_A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111}, 279 {REG_A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111}, 280 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 281 {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111}, 282 {REG_A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111}, 283 {REG_A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111}, 284 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 285 {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111}, 286 {REG_A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111}, 287 {REG_A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111}, 288 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 289 {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111}, 290 {REG_A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111}, 291 {REG_A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111}, 292 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 293 {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222}, 294 {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222}, 295 {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222}, 296 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 297 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 298 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 299 {REG_A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222}, 300 {REG_A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222}, 301 {REG_A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222}, 302 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222}, 303 {REG_A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222}, 304 {REG_A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222}, 305 {REG_A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222}, 306 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 307 {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220}, 308 {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220}, 309 {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220}, 310 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00}, 311 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040f00}, 312 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040f00}, 313 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040f00}, 314 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022}, 315 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 316 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 317 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 318 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 319 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 320 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 321 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 322 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 323 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 324 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 325 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 326 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 327 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 328 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 329 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 330 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 331 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 332 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 333 {}, 334 }; 335 336 const struct adreno_reglist a640_hwcg[] = { 337 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, 338 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, 339 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 340 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, 341 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, 342 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 343 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 344 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 345 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 346 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 347 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 348 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 349 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 350 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 351 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 352 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 353 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 354 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, 355 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 356 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, 357 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022}, 358 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 359 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 360 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 361 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 362 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 363 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 364 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 365 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 366 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 367 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 368 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 369 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 370 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 371 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 372 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 373 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, 374 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, 375 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, 376 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000}, 377 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 378 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 379 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 380 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, 381 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, 382 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, 383 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 384 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 385 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 386 {}, 387 }; 388 389 const struct adreno_reglist a650_hwcg[] = { 390 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, 391 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, 392 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 393 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, 394 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, 395 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 396 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 397 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 398 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 399 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 400 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 401 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 402 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 403 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 404 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 405 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 406 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 407 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, 408 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 409 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, 410 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022}, 411 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 412 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 413 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 414 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 415 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 416 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 417 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 418 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 419 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 420 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 421 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 422 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 423 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 424 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 425 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 426 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, 427 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, 428 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, 429 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777}, 430 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 431 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 432 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 433 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, 434 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, 435 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, 436 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 437 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 438 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 439 {}, 440 }; 441 442 const struct adreno_reglist a660_hwcg[] = { 443 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, 444 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, 445 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 446 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, 447 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, 448 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 449 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 450 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 451 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 452 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 453 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 454 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 455 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 456 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 457 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 458 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 459 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 460 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, 461 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 462 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, 463 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022}, 464 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 465 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 466 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 467 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 468 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 469 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 470 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 471 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 472 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 473 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 474 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 475 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 476 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 477 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 478 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 479 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, 480 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, 481 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, 482 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000}, 483 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 484 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 485 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 486 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, 487 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, 488 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, 489 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 490 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 491 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 492 {}, 493 }; 494 495 static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) 496 { 497 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 498 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 499 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 500 const struct adreno_reglist *reg; 501 unsigned int i; 502 u32 val, clock_cntl_on; 503 504 if (!adreno_gpu->info->hwcg) 505 return; 506 507 if (adreno_is_a630(adreno_gpu)) 508 clock_cntl_on = 0x8aa8aa02; 509 else 510 clock_cntl_on = 0x8aa8aa82; 511 512 val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL); 513 514 /* Don't re-program the registers if they are already correct */ 515 if ((!state && !val) || (state && (val == clock_cntl_on))) 516 return; 517 518 /* Disable SP clock before programming HWCG registers */ 519 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); 520 521 for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++) 522 gpu_write(gpu, reg->offset, state ? reg->value : 0); 523 524 /* Enable SP clock */ 525 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); 526 527 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); 528 } 529 530 /* For a615, a616, a618, A619, a630, a640 and a680 */ 531 static const u32 a6xx_protect[] = { 532 A6XX_PROTECT_RDONLY(0x00000, 0x04ff), 533 A6XX_PROTECT_RDONLY(0x00501, 0x0005), 534 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4), 535 A6XX_PROTECT_NORDWR(0x0050e, 0x0000), 536 A6XX_PROTECT_NORDWR(0x00510, 0x0000), 537 A6XX_PROTECT_NORDWR(0x00534, 0x0000), 538 A6XX_PROTECT_NORDWR(0x00800, 0x0082), 539 A6XX_PROTECT_NORDWR(0x008a0, 0x0008), 540 A6XX_PROTECT_NORDWR(0x008ab, 0x0024), 541 A6XX_PROTECT_RDONLY(0x008de, 0x00ae), 542 A6XX_PROTECT_NORDWR(0x00900, 0x004d), 543 A6XX_PROTECT_NORDWR(0x0098d, 0x0272), 544 A6XX_PROTECT_NORDWR(0x00e00, 0x0001), 545 A6XX_PROTECT_NORDWR(0x00e03, 0x000c), 546 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3), 547 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff), 548 A6XX_PROTECT_NORDWR(0x08630, 0x01cf), 549 A6XX_PROTECT_NORDWR(0x08e00, 0x0000), 550 A6XX_PROTECT_NORDWR(0x08e08, 0x0000), 551 A6XX_PROTECT_NORDWR(0x08e50, 0x001f), 552 A6XX_PROTECT_NORDWR(0x09624, 0x01db), 553 A6XX_PROTECT_NORDWR(0x09e70, 0x0001), 554 A6XX_PROTECT_NORDWR(0x09e78, 0x0187), 555 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf), 556 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000), 557 A6XX_PROTECT_NORDWR(0x0ae50, 0x032f), 558 A6XX_PROTECT_NORDWR(0x0b604, 0x0000), 559 A6XX_PROTECT_NORDWR(0x0be02, 0x0001), 560 A6XX_PROTECT_NORDWR(0x0be20, 0x17df), 561 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff), 562 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), 563 A6XX_PROTECT_NORDWR(0x11c00, 0x0000), /* note: infinite range */ 564 }; 565 566 /* These are for a620 and a650 */ 567 static const u32 a650_protect[] = { 568 A6XX_PROTECT_RDONLY(0x00000, 0x04ff), 569 A6XX_PROTECT_RDONLY(0x00501, 0x0005), 570 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4), 571 A6XX_PROTECT_NORDWR(0x0050e, 0x0000), 572 A6XX_PROTECT_NORDWR(0x00510, 0x0000), 573 A6XX_PROTECT_NORDWR(0x00534, 0x0000), 574 A6XX_PROTECT_NORDWR(0x00800, 0x0082), 575 A6XX_PROTECT_NORDWR(0x008a0, 0x0008), 576 A6XX_PROTECT_NORDWR(0x008ab, 0x0024), 577 A6XX_PROTECT_RDONLY(0x008de, 0x00ae), 578 A6XX_PROTECT_NORDWR(0x00900, 0x004d), 579 A6XX_PROTECT_NORDWR(0x0098d, 0x0272), 580 A6XX_PROTECT_NORDWR(0x00e00, 0x0001), 581 A6XX_PROTECT_NORDWR(0x00e03, 0x000c), 582 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3), 583 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff), 584 A6XX_PROTECT_NORDWR(0x08630, 0x01cf), 585 A6XX_PROTECT_NORDWR(0x08e00, 0x0000), 586 A6XX_PROTECT_NORDWR(0x08e08, 0x0000), 587 A6XX_PROTECT_NORDWR(0x08e50, 0x001f), 588 A6XX_PROTECT_NORDWR(0x08e80, 0x027f), 589 A6XX_PROTECT_NORDWR(0x09624, 0x01db), 590 A6XX_PROTECT_NORDWR(0x09e60, 0x0011), 591 A6XX_PROTECT_NORDWR(0x09e78, 0x0187), 592 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf), 593 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000), 594 A6XX_PROTECT_NORDWR(0x0ae50, 0x032f), 595 A6XX_PROTECT_NORDWR(0x0b604, 0x0000), 596 A6XX_PROTECT_NORDWR(0x0b608, 0x0007), 597 A6XX_PROTECT_NORDWR(0x0be02, 0x0001), 598 A6XX_PROTECT_NORDWR(0x0be20, 0x17df), 599 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff), 600 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), 601 A6XX_PROTECT_NORDWR(0x18400, 0x1fff), 602 A6XX_PROTECT_NORDWR(0x1a800, 0x1fff), 603 A6XX_PROTECT_NORDWR(0x1f400, 0x0443), 604 A6XX_PROTECT_RDONLY(0x1f844, 0x007b), 605 A6XX_PROTECT_NORDWR(0x1f887, 0x001b), 606 A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */ 607 }; 608 609 /* These are for a635 and a660 */ 610 static const u32 a660_protect[] = { 611 A6XX_PROTECT_RDONLY(0x00000, 0x04ff), 612 A6XX_PROTECT_RDONLY(0x00501, 0x0005), 613 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4), 614 A6XX_PROTECT_NORDWR(0x0050e, 0x0000), 615 A6XX_PROTECT_NORDWR(0x00510, 0x0000), 616 A6XX_PROTECT_NORDWR(0x00534, 0x0000), 617 A6XX_PROTECT_NORDWR(0x00800, 0x0082), 618 A6XX_PROTECT_NORDWR(0x008a0, 0x0008), 619 A6XX_PROTECT_NORDWR(0x008ab, 0x0024), 620 A6XX_PROTECT_RDONLY(0x008de, 0x00ae), 621 A6XX_PROTECT_NORDWR(0x00900, 0x004d), 622 A6XX_PROTECT_NORDWR(0x0098d, 0x0272), 623 A6XX_PROTECT_NORDWR(0x00e00, 0x0001), 624 A6XX_PROTECT_NORDWR(0x00e03, 0x000c), 625 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3), 626 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff), 627 A6XX_PROTECT_NORDWR(0x08630, 0x01cf), 628 A6XX_PROTECT_NORDWR(0x08e00, 0x0000), 629 A6XX_PROTECT_NORDWR(0x08e08, 0x0000), 630 A6XX_PROTECT_NORDWR(0x08e50, 0x001f), 631 A6XX_PROTECT_NORDWR(0x08e80, 0x027f), 632 A6XX_PROTECT_NORDWR(0x09624, 0x01db), 633 A6XX_PROTECT_NORDWR(0x09e60, 0x0011), 634 A6XX_PROTECT_NORDWR(0x09e78, 0x0187), 635 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf), 636 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000), 637 A6XX_PROTECT_NORDWR(0x0ae50, 0x012f), 638 A6XX_PROTECT_NORDWR(0x0b604, 0x0000), 639 A6XX_PROTECT_NORDWR(0x0b608, 0x0006), 640 A6XX_PROTECT_NORDWR(0x0be02, 0x0001), 641 A6XX_PROTECT_NORDWR(0x0be20, 0x015f), 642 A6XX_PROTECT_NORDWR(0x0d000, 0x05ff), 643 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff), 644 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), 645 A6XX_PROTECT_NORDWR(0x18400, 0x1fff), 646 A6XX_PROTECT_NORDWR(0x1a400, 0x1fff), 647 A6XX_PROTECT_NORDWR(0x1f400, 0x0443), 648 A6XX_PROTECT_RDONLY(0x1f844, 0x007b), 649 A6XX_PROTECT_NORDWR(0x1f860, 0x0000), 650 A6XX_PROTECT_NORDWR(0x1f887, 0x001b), 651 A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */ 652 }; 653 654 static void a6xx_set_cp_protect(struct msm_gpu *gpu) 655 { 656 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 657 const u32 *regs = a6xx_protect; 658 unsigned i, count = ARRAY_SIZE(a6xx_protect), count_max = 32; 659 660 BUILD_BUG_ON(ARRAY_SIZE(a6xx_protect) > 32); 661 BUILD_BUG_ON(ARRAY_SIZE(a650_protect) > 48); 662 663 if (adreno_is_a650(adreno_gpu)) { 664 regs = a650_protect; 665 count = ARRAY_SIZE(a650_protect); 666 count_max = 48; 667 } else if (adreno_is_a660_family(adreno_gpu)) { 668 regs = a660_protect; 669 count = ARRAY_SIZE(a660_protect); 670 count_max = 48; 671 } 672 673 /* 674 * Enable access protection to privileged registers, fault on an access 675 * protect violation and select the last span to protect from the start 676 * address all the way to the end of the register address space 677 */ 678 gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, BIT(0) | BIT(1) | BIT(3)); 679 680 for (i = 0; i < count - 1; i++) 681 gpu_write(gpu, REG_A6XX_CP_PROTECT(i), regs[i]); 682 /* last CP_PROTECT to have "infinite" length on the last entry */ 683 gpu_write(gpu, REG_A6XX_CP_PROTECT(count_max - 1), regs[i]); 684 } 685 686 static void a6xx_set_ubwc_config(struct msm_gpu *gpu) 687 { 688 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 689 u32 lower_bit = 2; 690 u32 amsbc = 0; 691 u32 rgb565_predicator = 0; 692 u32 uavflagprd_inv = 0; 693 694 /* a618 is using the hw default values */ 695 if (adreno_is_a618(adreno_gpu)) 696 return; 697 698 if (adreno_is_a640_family(adreno_gpu)) 699 amsbc = 1; 700 701 if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) { 702 /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ 703 lower_bit = 3; 704 amsbc = 1; 705 rgb565_predicator = 1; 706 uavflagprd_inv = 2; 707 } 708 709 if (adreno_is_7c3(adreno_gpu)) { 710 lower_bit = 1; 711 amsbc = 1; 712 rgb565_predicator = 1; 713 uavflagprd_inv = 2; 714 } 715 716 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 717 rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1); 718 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1); 719 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 720 uavflagprd_inv << 4 | lower_bit << 1); 721 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21); 722 } 723 724 static int a6xx_cp_init(struct msm_gpu *gpu) 725 { 726 struct msm_ringbuffer *ring = gpu->rb[0]; 727 728 OUT_PKT7(ring, CP_ME_INIT, 8); 729 730 OUT_RING(ring, 0x0000002f); 731 732 /* Enable multiple hardware contexts */ 733 OUT_RING(ring, 0x00000003); 734 735 /* Enable error detection */ 736 OUT_RING(ring, 0x20000000); 737 738 /* Don't enable header dump */ 739 OUT_RING(ring, 0x00000000); 740 OUT_RING(ring, 0x00000000); 741 742 /* No workarounds enabled */ 743 OUT_RING(ring, 0x00000000); 744 745 /* Pad rest of the cmds with 0's */ 746 OUT_RING(ring, 0x00000000); 747 OUT_RING(ring, 0x00000000); 748 749 a6xx_flush(gpu, ring); 750 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; 751 } 752 753 /* 754 * Check that the microcode version is new enough to include several key 755 * security fixes. Return true if the ucode is safe. 756 */ 757 static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu, 758 struct drm_gem_object *obj) 759 { 760 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 761 struct msm_gpu *gpu = &adreno_gpu->base; 762 const char *sqe_name = adreno_gpu->info->fw[ADRENO_FW_SQE]; 763 u32 *buf = msm_gem_get_vaddr(obj); 764 bool ret = false; 765 766 if (IS_ERR(buf)) 767 return false; 768 769 /* 770 * Targets up to a640 (a618, a630 and a640) need to check for a 771 * microcode version that is patched to support the whereami opcode or 772 * one that is new enough to include it by default. 773 * 774 * a650 tier targets don't need whereami but still need to be 775 * equal to or newer than 0.95 for other security fixes 776 * 777 * a660 targets have all the critical security fixes from the start 778 */ 779 if (!strcmp(sqe_name, "a630_sqe.fw")) { 780 /* 781 * If the lowest nibble is 0xa that is an indication that this 782 * microcode has been patched. The actual version is in dword 783 * [3] but we only care about the patchlevel which is the lowest 784 * nibble of dword [3] 785 * 786 * Otherwise check that the firmware is greater than or equal 787 * to 1.90 which was the first version that had this fix built 788 * in 789 */ 790 if ((((buf[0] & 0xf) == 0xa) && (buf[2] & 0xf) >= 1) || 791 (buf[0] & 0xfff) >= 0x190) { 792 a6xx_gpu->has_whereami = true; 793 ret = true; 794 goto out; 795 } 796 797 DRM_DEV_ERROR(&gpu->pdev->dev, 798 "a630 SQE ucode is too old. Have version %x need at least %x\n", 799 buf[0] & 0xfff, 0x190); 800 } else if (!strcmp(sqe_name, "a650_sqe.fw")) { 801 if ((buf[0] & 0xfff) >= 0x095) { 802 ret = true; 803 goto out; 804 } 805 806 DRM_DEV_ERROR(&gpu->pdev->dev, 807 "a650 SQE ucode is too old. Have version %x need at least %x\n", 808 buf[0] & 0xfff, 0x095); 809 } else if (!strcmp(sqe_name, "a660_sqe.fw")) { 810 ret = true; 811 } else { 812 DRM_DEV_ERROR(&gpu->pdev->dev, 813 "unknown GPU, add it to a6xx_ucode_check_version()!!\n"); 814 } 815 out: 816 msm_gem_put_vaddr(obj); 817 return ret; 818 } 819 820 static int a6xx_ucode_init(struct msm_gpu *gpu) 821 { 822 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 823 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 824 825 if (!a6xx_gpu->sqe_bo) { 826 a6xx_gpu->sqe_bo = adreno_fw_create_bo(gpu, 827 adreno_gpu->fw[ADRENO_FW_SQE], &a6xx_gpu->sqe_iova); 828 829 if (IS_ERR(a6xx_gpu->sqe_bo)) { 830 int ret = PTR_ERR(a6xx_gpu->sqe_bo); 831 832 a6xx_gpu->sqe_bo = NULL; 833 DRM_DEV_ERROR(&gpu->pdev->dev, 834 "Could not allocate SQE ucode: %d\n", ret); 835 836 return ret; 837 } 838 839 msm_gem_object_set_name(a6xx_gpu->sqe_bo, "sqefw"); 840 if (!a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->sqe_bo)) { 841 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace); 842 drm_gem_object_put(a6xx_gpu->sqe_bo); 843 844 a6xx_gpu->sqe_bo = NULL; 845 return -EPERM; 846 } 847 } 848 849 gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE, 850 REG_A6XX_CP_SQE_INSTR_BASE+1, a6xx_gpu->sqe_iova); 851 852 return 0; 853 } 854 855 static int a6xx_zap_shader_init(struct msm_gpu *gpu) 856 { 857 static bool loaded; 858 int ret; 859 860 if (loaded) 861 return 0; 862 863 ret = adreno_zap_shader_load(gpu, GPU_PAS_ID); 864 865 loaded = !ret; 866 return ret; 867 } 868 869 #define A6XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \ 870 A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \ 871 A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \ 872 A6XX_RBBM_INT_0_MASK_CP_IB2 | \ 873 A6XX_RBBM_INT_0_MASK_CP_IB1 | \ 874 A6XX_RBBM_INT_0_MASK_CP_RB | \ 875 A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \ 876 A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \ 877 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \ 878 A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \ 879 A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR) 880 881 static int hw_init(struct msm_gpu *gpu) 882 { 883 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 884 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 885 int ret; 886 887 /* Make sure the GMU keeps the GPU on while we set it up */ 888 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 889 890 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); 891 892 /* 893 * Disable the trusted memory range - we don't actually supported secure 894 * memory rendering at this point in time and we don't want to block off 895 * part of the virtual memory space. 896 */ 897 gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO, 898 REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x00000000); 899 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); 900 901 /* Turn on 64 bit addressing for all blocks */ 902 gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1); 903 gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1); 904 gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1); 905 gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1); 906 gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1); 907 gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1); 908 gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1); 909 gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1); 910 gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1); 911 gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1); 912 gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1); 913 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1); 914 915 /* enable hardware clockgating */ 916 a6xx_set_hwcg(gpu, true); 917 918 /* VBIF/GBIF start*/ 919 if (adreno_is_a640_family(adreno_gpu) || 920 adreno_is_a650_family(adreno_gpu)) { 921 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); 922 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); 923 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); 924 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); 925 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); 926 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3); 927 } else { 928 gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3); 929 } 930 931 if (adreno_is_a630(adreno_gpu)) 932 gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009); 933 934 /* Make all blocks contribute to the GPU BUSY perf counter */ 935 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff); 936 937 /* Disable L2 bypass in the UCHE */ 938 gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_LO, 0xffffffc0); 939 gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_HI, 0x0001ffff); 940 gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_LO, 0xfffff000); 941 gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_HI, 0x0001ffff); 942 gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000); 943 gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff); 944 945 if (!adreno_is_a650_family(adreno_gpu)) { 946 /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */ 947 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN_LO, 948 REG_A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x00100000); 949 950 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX_LO, 951 REG_A6XX_UCHE_GMEM_RANGE_MAX_HI, 952 0x00100000 + adreno_gpu->gmem - 1); 953 } 954 955 gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804); 956 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4); 957 958 if (adreno_is_a640_family(adreno_gpu) || 959 adreno_is_a650_family(adreno_gpu)) 960 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); 961 else 962 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0); 963 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); 964 965 if (adreno_is_a660_family(adreno_gpu)) 966 gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); 967 968 /* Setting the mem pool size */ 969 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); 970 971 /* Setting the primFifo thresholds default values, 972 * and vccCacheSkipDis=1 bit (0x200) for A640 and newer 973 */ 974 if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) 975 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200); 976 else if (adreno_is_a640_family(adreno_gpu) || adreno_is_7c3(adreno_gpu)) 977 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200); 978 else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) 979 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200); 980 else 981 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00180000); 982 983 /* Set the AHB default slave response to "ERROR" */ 984 gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1); 985 986 /* Turn on performance counters */ 987 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1); 988 989 /* Select CP0 to always count cycles */ 990 gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL(0), PERF_CP_ALWAYS_COUNT); 991 992 a6xx_set_ubwc_config(gpu); 993 994 /* Enable fault detection */ 995 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, 996 (1 << 30) | 0x1fffff); 997 998 gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1); 999 1000 /* Set weights for bicubic filtering */ 1001 if (adreno_is_a650_family(adreno_gpu)) { 1002 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0); 1003 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, 1004 0x3fe05ff4); 1005 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2, 1006 0x3fa0ebee); 1007 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3, 1008 0x3f5193ed); 1009 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4, 1010 0x3f0243f0); 1011 } 1012 1013 /* Protect registers from the CP */ 1014 a6xx_set_cp_protect(gpu); 1015 1016 if (adreno_is_a660_family(adreno_gpu)) { 1017 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1); 1018 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0); 1019 } 1020 1021 /* Set dualQ + disable afull for A660 GPU */ 1022 if (adreno_is_a660(adreno_gpu)) 1023 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x66906); 1024 1025 /* Enable expanded apriv for targets that support it */ 1026 if (gpu->hw_apriv) { 1027 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL, 1028 (1 << 6) | (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1)); 1029 } 1030 1031 /* Enable interrupts */ 1032 gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, A6XX_INT_MASK); 1033 1034 ret = adreno_hw_init(gpu); 1035 if (ret) 1036 goto out; 1037 1038 ret = a6xx_ucode_init(gpu); 1039 if (ret) 1040 goto out; 1041 1042 /* Set the ringbuffer address */ 1043 gpu_write64(gpu, REG_A6XX_CP_RB_BASE, REG_A6XX_CP_RB_BASE_HI, 1044 gpu->rb[0]->iova); 1045 1046 /* Targets that support extended APRIV can use the RPTR shadow from 1047 * hardware but all the other ones need to disable the feature. Targets 1048 * that support the WHERE_AM_I opcode can use that instead 1049 */ 1050 if (adreno_gpu->base.hw_apriv) 1051 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT); 1052 else 1053 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, 1054 MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE); 1055 1056 /* 1057 * Expanded APRIV and targets that support WHERE_AM_I both need a 1058 * privileged buffer to store the RPTR shadow 1059 */ 1060 1061 if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) { 1062 if (!a6xx_gpu->shadow_bo) { 1063 a6xx_gpu->shadow = msm_gem_kernel_new(gpu->dev, 1064 sizeof(u32) * gpu->nr_rings, 1065 MSM_BO_WC | MSM_BO_MAP_PRIV, 1066 gpu->aspace, &a6xx_gpu->shadow_bo, 1067 &a6xx_gpu->shadow_iova); 1068 1069 if (IS_ERR(a6xx_gpu->shadow)) 1070 return PTR_ERR(a6xx_gpu->shadow); 1071 1072 msm_gem_object_set_name(a6xx_gpu->shadow_bo, "shadow"); 1073 } 1074 1075 gpu_write64(gpu, REG_A6XX_CP_RB_RPTR_ADDR_LO, 1076 REG_A6XX_CP_RB_RPTR_ADDR_HI, 1077 shadowptr(a6xx_gpu, gpu->rb[0])); 1078 } 1079 1080 /* Always come up on rb 0 */ 1081 a6xx_gpu->cur_ring = gpu->rb[0]; 1082 1083 gpu->cur_ctx_seqno = 0; 1084 1085 /* Enable the SQE_to start the CP engine */ 1086 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1); 1087 1088 ret = a6xx_cp_init(gpu); 1089 if (ret) 1090 goto out; 1091 1092 /* 1093 * Try to load a zap shader into the secure world. If successful 1094 * we can use the CP to switch out of secure mode. If not then we 1095 * have no resource but to try to switch ourselves out manually. If we 1096 * guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will 1097 * be blocked and a permissions violation will soon follow. 1098 */ 1099 ret = a6xx_zap_shader_init(gpu); 1100 if (!ret) { 1101 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1); 1102 OUT_RING(gpu->rb[0], 0x00000000); 1103 1104 a6xx_flush(gpu, gpu->rb[0]); 1105 if (!a6xx_idle(gpu, gpu->rb[0])) 1106 return -EINVAL; 1107 } else if (ret == -ENODEV) { 1108 /* 1109 * This device does not use zap shader (but print a warning 1110 * just in case someone got their dt wrong.. hopefully they 1111 * have a debug UART to realize the error of their ways... 1112 * if you mess this up you are about to crash horribly) 1113 */ 1114 dev_warn_once(gpu->dev->dev, 1115 "Zap shader not enabled - using SECVID_TRUST_CNTL instead\n"); 1116 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0); 1117 ret = 0; 1118 } else { 1119 return ret; 1120 } 1121 1122 out: 1123 /* 1124 * Tell the GMU that we are done touching the GPU and it can start power 1125 * management 1126 */ 1127 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 1128 1129 if (a6xx_gpu->gmu.legacy) { 1130 /* Take the GMU out of its special boot mode */ 1131 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER); 1132 } 1133 1134 return ret; 1135 } 1136 1137 static int a6xx_hw_init(struct msm_gpu *gpu) 1138 { 1139 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1140 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1141 int ret; 1142 1143 mutex_lock(&a6xx_gpu->gmu.lock); 1144 ret = hw_init(gpu); 1145 mutex_unlock(&a6xx_gpu->gmu.lock); 1146 1147 return ret; 1148 } 1149 1150 static void a6xx_dump(struct msm_gpu *gpu) 1151 { 1152 DRM_DEV_INFO(&gpu->pdev->dev, "status: %08x\n", 1153 gpu_read(gpu, REG_A6XX_RBBM_STATUS)); 1154 adreno_dump(gpu); 1155 } 1156 1157 #define VBIF_RESET_ACK_TIMEOUT 100 1158 #define VBIF_RESET_ACK_MASK 0x00f0 1159 1160 static void a6xx_recover(struct msm_gpu *gpu) 1161 { 1162 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1163 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1164 int i; 1165 1166 adreno_dump_info(gpu); 1167 1168 for (i = 0; i < 8; i++) 1169 DRM_DEV_INFO(&gpu->pdev->dev, "CP_SCRATCH_REG%d: %u\n", i, 1170 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i))); 1171 1172 if (hang_debug) 1173 a6xx_dump(gpu); 1174 1175 /* 1176 * Turn off keep alive that might have been enabled by the hang 1177 * interrupt 1178 */ 1179 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); 1180 1181 gpu->funcs->pm_suspend(gpu); 1182 gpu->funcs->pm_resume(gpu); 1183 1184 msm_gpu_hw_init(gpu); 1185 } 1186 1187 static const char *a6xx_uche_fault_block(struct msm_gpu *gpu, u32 mid) 1188 { 1189 static const char *uche_clients[7] = { 1190 "VFD", "SP", "VSC", "VPC", "HLSQ", "PC", "LRZ", 1191 }; 1192 u32 val; 1193 1194 if (mid < 1 || mid > 3) 1195 return "UNKNOWN"; 1196 1197 /* 1198 * The source of the data depends on the mid ID read from FSYNR1. 1199 * and the client ID read from the UCHE block 1200 */ 1201 val = gpu_read(gpu, REG_A6XX_UCHE_CLIENT_PF); 1202 1203 /* mid = 3 is most precise and refers to only one block per client */ 1204 if (mid == 3) 1205 return uche_clients[val & 7]; 1206 1207 /* For mid=2 the source is TP or VFD except when the client id is 0 */ 1208 if (mid == 2) 1209 return ((val & 7) == 0) ? "TP" : "TP|VFD"; 1210 1211 /* For mid=1 just return "UCHE" as a catchall for everything else */ 1212 return "UCHE"; 1213 } 1214 1215 static const char *a6xx_fault_block(struct msm_gpu *gpu, u32 id) 1216 { 1217 if (id == 0) 1218 return "CP"; 1219 else if (id == 4) 1220 return "CCU"; 1221 else if (id == 6) 1222 return "CDP Prefetch"; 1223 1224 return a6xx_uche_fault_block(gpu, id); 1225 } 1226 1227 #define ARM_SMMU_FSR_TF BIT(1) 1228 #define ARM_SMMU_FSR_PF BIT(3) 1229 #define ARM_SMMU_FSR_EF BIT(4) 1230 1231 static int a6xx_fault_handler(void *arg, unsigned long iova, int flags, void *data) 1232 { 1233 struct msm_gpu *gpu = arg; 1234 struct adreno_smmu_fault_info *info = data; 1235 const char *type = "UNKNOWN"; 1236 const char *block; 1237 bool do_devcoredump = info && !READ_ONCE(gpu->crashstate); 1238 1239 /* 1240 * If we aren't going to be resuming later from fault_worker, then do 1241 * it now. 1242 */ 1243 if (!do_devcoredump) { 1244 gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu); 1245 } 1246 1247 /* 1248 * Print a default message if we couldn't get the data from the 1249 * adreno-smmu-priv 1250 */ 1251 if (!info) { 1252 pr_warn_ratelimited("*** gpu fault: iova=%.16lx flags=%d (%u,%u,%u,%u)\n", 1253 iova, flags, 1254 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)), 1255 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)), 1256 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)), 1257 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7))); 1258 1259 return 0; 1260 } 1261 1262 if (info->fsr & ARM_SMMU_FSR_TF) 1263 type = "TRANSLATION"; 1264 else if (info->fsr & ARM_SMMU_FSR_PF) 1265 type = "PERMISSION"; 1266 else if (info->fsr & ARM_SMMU_FSR_EF) 1267 type = "EXTERNAL"; 1268 1269 block = a6xx_fault_block(gpu, info->fsynr1 & 0xff); 1270 1271 pr_warn_ratelimited("*** gpu fault: ttbr0=%.16llx iova=%.16lx dir=%s type=%s source=%s (%u,%u,%u,%u)\n", 1272 info->ttbr0, iova, 1273 flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ", 1274 type, block, 1275 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)), 1276 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)), 1277 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)), 1278 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7))); 1279 1280 if (do_devcoredump) { 1281 /* Turn off the hangcheck timer to keep it from bothering us */ 1282 del_timer(&gpu->hangcheck_timer); 1283 1284 gpu->fault_info.ttbr0 = info->ttbr0; 1285 gpu->fault_info.iova = iova; 1286 gpu->fault_info.flags = flags; 1287 gpu->fault_info.type = type; 1288 gpu->fault_info.block = block; 1289 1290 kthread_queue_work(gpu->worker, &gpu->fault_work); 1291 } 1292 1293 return 0; 1294 } 1295 1296 static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu) 1297 { 1298 u32 status = gpu_read(gpu, REG_A6XX_CP_INTERRUPT_STATUS); 1299 1300 if (status & A6XX_CP_INT_CP_OPCODE_ERROR) { 1301 u32 val; 1302 1303 gpu_write(gpu, REG_A6XX_CP_SQE_STAT_ADDR, 1); 1304 val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA); 1305 dev_err_ratelimited(&gpu->pdev->dev, 1306 "CP | opcode error | possible opcode=0x%8.8X\n", 1307 val); 1308 } 1309 1310 if (status & A6XX_CP_INT_CP_UCODE_ERROR) 1311 dev_err_ratelimited(&gpu->pdev->dev, 1312 "CP ucode error interrupt\n"); 1313 1314 if (status & A6XX_CP_INT_CP_HW_FAULT_ERROR) 1315 dev_err_ratelimited(&gpu->pdev->dev, "CP | HW fault | status=0x%8.8X\n", 1316 gpu_read(gpu, REG_A6XX_CP_HW_FAULT)); 1317 1318 if (status & A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR) { 1319 u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS); 1320 1321 dev_err_ratelimited(&gpu->pdev->dev, 1322 "CP | protected mode error | %s | addr=0x%8.8X | status=0x%8.8X\n", 1323 val & (1 << 20) ? "READ" : "WRITE", 1324 (val & 0x3ffff), val); 1325 } 1326 1327 if (status & A6XX_CP_INT_CP_AHB_ERROR) 1328 dev_err_ratelimited(&gpu->pdev->dev, "CP AHB error interrupt\n"); 1329 1330 if (status & A6XX_CP_INT_CP_VSD_PARITY_ERROR) 1331 dev_err_ratelimited(&gpu->pdev->dev, "CP VSD decoder parity error\n"); 1332 1333 if (status & A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR) 1334 dev_err_ratelimited(&gpu->pdev->dev, "CP illegal instruction error\n"); 1335 1336 } 1337 1338 static void a6xx_fault_detect_irq(struct msm_gpu *gpu) 1339 { 1340 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1341 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1342 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); 1343 1344 /* 1345 * If stalled on SMMU fault, we could trip the GPU's hang detection, 1346 * but the fault handler will trigger the devcore dump, and we want 1347 * to otherwise resume normally rather than killing the submit, so 1348 * just bail. 1349 */ 1350 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS3) & A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT) 1351 return; 1352 1353 /* 1354 * Force the GPU to stay on until after we finish 1355 * collecting information 1356 */ 1357 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1); 1358 1359 DRM_DEV_ERROR(&gpu->pdev->dev, 1360 "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n", 1361 ring ? ring->id : -1, ring ? ring->seqno : 0, 1362 gpu_read(gpu, REG_A6XX_RBBM_STATUS), 1363 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), 1364 gpu_read(gpu, REG_A6XX_CP_RB_WPTR), 1365 gpu_read64(gpu, REG_A6XX_CP_IB1_BASE, REG_A6XX_CP_IB1_BASE_HI), 1366 gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE), 1367 gpu_read64(gpu, REG_A6XX_CP_IB2_BASE, REG_A6XX_CP_IB2_BASE_HI), 1368 gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE)); 1369 1370 /* Turn off the hangcheck timer to keep it from bothering us */ 1371 del_timer(&gpu->hangcheck_timer); 1372 1373 kthread_queue_work(gpu->worker, &gpu->recover_work); 1374 } 1375 1376 static irqreturn_t a6xx_irq(struct msm_gpu *gpu) 1377 { 1378 struct msm_drm_private *priv = gpu->dev->dev_private; 1379 u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS); 1380 1381 gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status); 1382 1383 if (priv->disable_err_irq) 1384 status &= A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS; 1385 1386 if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT) 1387 a6xx_fault_detect_irq(gpu); 1388 1389 if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR) 1390 dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n"); 1391 1392 if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR) 1393 a6xx_cp_hw_err_irq(gpu); 1394 1395 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW) 1396 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB ASYNC overflow\n"); 1397 1398 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW) 1399 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB bus overflow\n"); 1400 1401 if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS) 1402 dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n"); 1403 1404 if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) 1405 msm_gpu_retire(gpu); 1406 1407 return IRQ_HANDLED; 1408 } 1409 1410 static void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or) 1411 { 1412 return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or); 1413 } 1414 1415 static void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value) 1416 { 1417 return msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2)); 1418 } 1419 1420 static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu) 1421 { 1422 llcc_slice_deactivate(a6xx_gpu->llc_slice); 1423 llcc_slice_deactivate(a6xx_gpu->htw_llc_slice); 1424 } 1425 1426 static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu) 1427 { 1428 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1429 struct msm_gpu *gpu = &adreno_gpu->base; 1430 u32 cntl1_regval = 0; 1431 1432 if (IS_ERR(a6xx_gpu->llc_mmio)) 1433 return; 1434 1435 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { 1436 u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice); 1437 1438 gpu_scid &= 0x1f; 1439 cntl1_regval = (gpu_scid << 0) | (gpu_scid << 5) | (gpu_scid << 10) | 1440 (gpu_scid << 15) | (gpu_scid << 20); 1441 1442 /* On A660, the SCID programming for UCHE traffic is done in 1443 * A6XX_GBIF_SCACHE_CNTL0[14:10] 1444 */ 1445 if (adreno_is_a660_family(adreno_gpu)) 1446 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, (0x1f << 10) | 1447 (1 << 8), (gpu_scid << 10) | (1 << 8)); 1448 } 1449 1450 /* 1451 * For targets with a MMU500, activate the slice but don't program the 1452 * register. The XBL will take care of that. 1453 */ 1454 if (!llcc_slice_activate(a6xx_gpu->htw_llc_slice)) { 1455 if (!a6xx_gpu->have_mmu500) { 1456 u32 gpuhtw_scid = llcc_get_slice_id(a6xx_gpu->htw_llc_slice); 1457 1458 gpuhtw_scid &= 0x1f; 1459 cntl1_regval |= FIELD_PREP(GENMASK(29, 25), gpuhtw_scid); 1460 } 1461 } 1462 1463 if (!cntl1_regval) 1464 return; 1465 1466 /* 1467 * Program the slice IDs for the various GPU blocks and GPU MMU 1468 * pagetables 1469 */ 1470 if (!a6xx_gpu->have_mmu500) { 1471 a6xx_llc_write(a6xx_gpu, 1472 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, cntl1_regval); 1473 1474 /* 1475 * Program cacheability overrides to not allocate cache 1476 * lines on a write miss 1477 */ 1478 a6xx_llc_rmw(a6xx_gpu, 1479 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, 0x03); 1480 return; 1481 } 1482 1483 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, GENMASK(24, 0), cntl1_regval); 1484 } 1485 1486 static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu) 1487 { 1488 llcc_slice_putd(a6xx_gpu->llc_slice); 1489 llcc_slice_putd(a6xx_gpu->htw_llc_slice); 1490 } 1491 1492 static void a6xx_llc_slices_init(struct platform_device *pdev, 1493 struct a6xx_gpu *a6xx_gpu) 1494 { 1495 struct device_node *phandle; 1496 1497 /* 1498 * There is a different programming path for targets with an mmu500 1499 * attached, so detect if that is the case 1500 */ 1501 phandle = of_parse_phandle(pdev->dev.of_node, "iommus", 0); 1502 a6xx_gpu->have_mmu500 = (phandle && 1503 of_device_is_compatible(phandle, "arm,mmu-500")); 1504 of_node_put(phandle); 1505 1506 if (a6xx_gpu->have_mmu500) 1507 a6xx_gpu->llc_mmio = NULL; 1508 else 1509 a6xx_gpu->llc_mmio = msm_ioremap(pdev, "cx_mem", "gpu_cx"); 1510 1511 a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU); 1512 a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW); 1513 1514 if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice)) 1515 a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL); 1516 } 1517 1518 static int a6xx_pm_resume(struct msm_gpu *gpu) 1519 { 1520 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1521 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1522 int ret; 1523 1524 gpu->needs_hw_init = true; 1525 1526 trace_msm_gpu_resume(0); 1527 1528 mutex_lock(&a6xx_gpu->gmu.lock); 1529 ret = a6xx_gmu_resume(a6xx_gpu); 1530 mutex_unlock(&a6xx_gpu->gmu.lock); 1531 if (ret) 1532 return ret; 1533 1534 msm_devfreq_resume(gpu); 1535 1536 a6xx_llc_activate(a6xx_gpu); 1537 1538 return 0; 1539 } 1540 1541 static int a6xx_pm_suspend(struct msm_gpu *gpu) 1542 { 1543 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1544 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1545 int i, ret; 1546 1547 trace_msm_gpu_suspend(0); 1548 1549 a6xx_llc_deactivate(a6xx_gpu); 1550 1551 msm_devfreq_suspend(gpu); 1552 1553 mutex_lock(&a6xx_gpu->gmu.lock); 1554 ret = a6xx_gmu_stop(a6xx_gpu); 1555 mutex_unlock(&a6xx_gpu->gmu.lock); 1556 if (ret) 1557 return ret; 1558 1559 if (a6xx_gpu->shadow_bo) 1560 for (i = 0; i < gpu->nr_rings; i++) 1561 a6xx_gpu->shadow[i] = 0; 1562 1563 return 0; 1564 } 1565 1566 static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) 1567 { 1568 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1569 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1570 1571 mutex_lock(&a6xx_gpu->gmu.lock); 1572 1573 /* Force the GPU power on so we can read this register */ 1574 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); 1575 1576 *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO, 1577 REG_A6XX_CP_ALWAYS_ON_COUNTER_HI); 1578 1579 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); 1580 1581 mutex_unlock(&a6xx_gpu->gmu.lock); 1582 1583 return 0; 1584 } 1585 1586 static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu) 1587 { 1588 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1589 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1590 1591 return a6xx_gpu->cur_ring; 1592 } 1593 1594 static void a6xx_destroy(struct msm_gpu *gpu) 1595 { 1596 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1597 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1598 1599 if (a6xx_gpu->sqe_bo) { 1600 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace); 1601 drm_gem_object_put(a6xx_gpu->sqe_bo); 1602 } 1603 1604 if (a6xx_gpu->shadow_bo) { 1605 msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->aspace); 1606 drm_gem_object_put(a6xx_gpu->shadow_bo); 1607 } 1608 1609 a6xx_llc_slices_destroy(a6xx_gpu); 1610 1611 a6xx_gmu_remove(a6xx_gpu); 1612 1613 adreno_gpu_cleanup(adreno_gpu); 1614 1615 kfree(a6xx_gpu); 1616 } 1617 1618 static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu) 1619 { 1620 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1621 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1622 u64 busy_cycles, busy_time; 1623 1624 1625 /* Only read the gpu busy if the hardware is already active */ 1626 if (pm_runtime_get_if_in_use(a6xx_gpu->gmu.dev) == 0) 1627 return 0; 1628 1629 busy_cycles = gmu_read64(&a6xx_gpu->gmu, 1630 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L, 1631 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H); 1632 1633 busy_time = (busy_cycles - gpu->devfreq.busy_cycles) * 10; 1634 do_div(busy_time, 192); 1635 1636 gpu->devfreq.busy_cycles = busy_cycles; 1637 1638 pm_runtime_put(a6xx_gpu->gmu.dev); 1639 1640 if (WARN_ON(busy_time > ~0LU)) 1641 return ~0LU; 1642 1643 return (unsigned long)busy_time; 1644 } 1645 1646 static void a6xx_gpu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp) 1647 { 1648 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1649 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1650 1651 mutex_lock(&a6xx_gpu->gmu.lock); 1652 a6xx_gmu_set_freq(gpu, opp); 1653 mutex_unlock(&a6xx_gpu->gmu.lock); 1654 } 1655 1656 static struct msm_gem_address_space * 1657 a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) 1658 { 1659 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1660 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1661 struct iommu_domain *iommu; 1662 struct msm_mmu *mmu; 1663 struct msm_gem_address_space *aspace; 1664 u64 start, size; 1665 1666 iommu = iommu_domain_alloc(&platform_bus_type); 1667 if (!iommu) 1668 return NULL; 1669 1670 /* 1671 * This allows GPU to set the bus attributes required to use system 1672 * cache on behalf of the iommu page table walker. 1673 */ 1674 if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice)) 1675 adreno_set_llc_attributes(iommu); 1676 1677 mmu = msm_iommu_new(&pdev->dev, iommu); 1678 if (IS_ERR(mmu)) { 1679 iommu_domain_free(iommu); 1680 return ERR_CAST(mmu); 1681 } 1682 1683 /* 1684 * Use the aperture start or SZ_16M, whichever is greater. This will 1685 * ensure that we align with the allocated pagetable range while still 1686 * allowing room in the lower 32 bits for GMEM and whatnot 1687 */ 1688 start = max_t(u64, SZ_16M, iommu->geometry.aperture_start); 1689 size = iommu->geometry.aperture_end - start + 1; 1690 1691 aspace = msm_gem_address_space_create(mmu, "gpu", 1692 start & GENMASK_ULL(48, 0), size); 1693 1694 if (IS_ERR(aspace) && !IS_ERR(mmu)) 1695 mmu->funcs->destroy(mmu); 1696 1697 return aspace; 1698 } 1699 1700 static struct msm_gem_address_space * 1701 a6xx_create_private_address_space(struct msm_gpu *gpu) 1702 { 1703 struct msm_mmu *mmu; 1704 1705 mmu = msm_iommu_pagetable_create(gpu->aspace->mmu); 1706 1707 if (IS_ERR(mmu)) 1708 return ERR_CAST(mmu); 1709 1710 return msm_gem_address_space_create(mmu, 1711 "gpu", 0x100000000ULL, 0x1ffffffffULL); 1712 } 1713 1714 static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 1715 { 1716 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1717 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1718 1719 if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) 1720 return a6xx_gpu->shadow[ring->id]; 1721 1722 return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR); 1723 } 1724 1725 static u32 a618_get_speed_bin(u32 fuse) 1726 { 1727 if (fuse == 0) 1728 return 0; 1729 else if (fuse == 169) 1730 return 1; 1731 else if (fuse == 174) 1732 return 2; 1733 1734 return UINT_MAX; 1735 } 1736 1737 static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse) 1738 { 1739 u32 val = UINT_MAX; 1740 1741 if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev)) 1742 val = a618_get_speed_bin(fuse); 1743 1744 if (val == UINT_MAX) { 1745 DRM_DEV_ERROR(dev, 1746 "missing support for speed-bin: %u. Some OPPs may not be supported by hardware", 1747 fuse); 1748 return UINT_MAX; 1749 } 1750 1751 return (1 << val); 1752 } 1753 1754 static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev) 1755 { 1756 u32 supp_hw = UINT_MAX; 1757 u32 speedbin; 1758 int ret; 1759 1760 ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", &speedbin); 1761 /* 1762 * -ENOENT means that the platform doesn't support speedbin which is 1763 * fine 1764 */ 1765 if (ret == -ENOENT) { 1766 return 0; 1767 } else if (ret) { 1768 DRM_DEV_ERROR(dev, 1769 "failed to read speed-bin (%d). Some OPPs may not be supported by hardware", 1770 ret); 1771 goto done; 1772 } 1773 1774 supp_hw = fuse_to_supp_hw(dev, rev, speedbin); 1775 1776 done: 1777 ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); 1778 if (ret) 1779 return ret; 1780 1781 return 0; 1782 } 1783 1784 static const struct adreno_gpu_funcs funcs = { 1785 .base = { 1786 .get_param = adreno_get_param, 1787 .hw_init = a6xx_hw_init, 1788 .pm_suspend = a6xx_pm_suspend, 1789 .pm_resume = a6xx_pm_resume, 1790 .recover = a6xx_recover, 1791 .submit = a6xx_submit, 1792 .active_ring = a6xx_active_ring, 1793 .irq = a6xx_irq, 1794 .destroy = a6xx_destroy, 1795 #if defined(CONFIG_DRM_MSM_GPU_STATE) 1796 .show = a6xx_show, 1797 #endif 1798 .gpu_busy = a6xx_gpu_busy, 1799 .gpu_get_freq = a6xx_gmu_get_freq, 1800 .gpu_set_freq = a6xx_gpu_set_freq, 1801 #if defined(CONFIG_DRM_MSM_GPU_STATE) 1802 .gpu_state_get = a6xx_gpu_state_get, 1803 .gpu_state_put = a6xx_gpu_state_put, 1804 #endif 1805 .create_address_space = a6xx_create_address_space, 1806 .create_private_address_space = a6xx_create_private_address_space, 1807 .get_rptr = a6xx_get_rptr, 1808 }, 1809 .get_timestamp = a6xx_get_timestamp, 1810 }; 1811 1812 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) 1813 { 1814 struct msm_drm_private *priv = dev->dev_private; 1815 struct platform_device *pdev = priv->gpu_pdev; 1816 struct adreno_platform_config *config = pdev->dev.platform_data; 1817 const struct adreno_info *info; 1818 struct device_node *node; 1819 struct a6xx_gpu *a6xx_gpu; 1820 struct adreno_gpu *adreno_gpu; 1821 struct msm_gpu *gpu; 1822 int ret; 1823 1824 a6xx_gpu = kzalloc(sizeof(*a6xx_gpu), GFP_KERNEL); 1825 if (!a6xx_gpu) 1826 return ERR_PTR(-ENOMEM); 1827 1828 adreno_gpu = &a6xx_gpu->base; 1829 gpu = &adreno_gpu->base; 1830 1831 adreno_gpu->registers = NULL; 1832 1833 /* 1834 * We need to know the platform type before calling into adreno_gpu_init 1835 * so that the hw_apriv flag can be correctly set. Snoop into the info 1836 * and grab the revision number 1837 */ 1838 info = adreno_info(config->rev); 1839 1840 if (info && (info->revn == 650 || info->revn == 660 || 1841 adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), info->rev))) 1842 adreno_gpu->base.hw_apriv = true; 1843 1844 /* 1845 * For now only clamp to idle freq for devices where this is known not 1846 * to cause power supply issues: 1847 */ 1848 if (info && (info->revn == 618)) 1849 gpu->clamp_to_idle = true; 1850 1851 a6xx_llc_slices_init(pdev, a6xx_gpu); 1852 1853 ret = a6xx_set_supported_hw(&pdev->dev, config->rev); 1854 if (ret) { 1855 a6xx_destroy(&(a6xx_gpu->base.base)); 1856 return ERR_PTR(ret); 1857 } 1858 1859 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); 1860 if (ret) { 1861 a6xx_destroy(&(a6xx_gpu->base.base)); 1862 return ERR_PTR(ret); 1863 } 1864 1865 /* Check if there is a GMU phandle and set it up */ 1866 node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0); 1867 1868 /* FIXME: How do we gracefully handle this? */ 1869 BUG_ON(!node); 1870 1871 ret = a6xx_gmu_init(a6xx_gpu, node); 1872 if (ret) { 1873 a6xx_destroy(&(a6xx_gpu->base.base)); 1874 return ERR_PTR(ret); 1875 } 1876 1877 if (gpu->aspace) 1878 msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, 1879 a6xx_fault_handler); 1880 1881 return gpu; 1882 } 1883