1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */ 3 4 5 #include "msm_gem.h" 6 #include "msm_mmu.h" 7 #include "msm_gpu_trace.h" 8 #include "a6xx_gpu.h" 9 #include "a6xx_gmu.xml.h" 10 11 #include <linux/devfreq.h> 12 13 #define GPU_PAS_ID 13 14 15 static inline bool _a6xx_check_idle(struct msm_gpu *gpu) 16 { 17 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 18 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 19 20 /* Check that the GMU is idle */ 21 if (!a6xx_gmu_isidle(&a6xx_gpu->gmu)) 22 return false; 23 24 /* Check tha the CX master is idle */ 25 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & 26 ~A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER) 27 return false; 28 29 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & 30 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT); 31 } 32 33 bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 34 { 35 /* wait for CP to drain ringbuffer: */ 36 if (!adreno_idle(gpu, ring)) 37 return false; 38 39 if (spin_until(_a6xx_check_idle(gpu))) { 40 DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n", 41 gpu->name, __builtin_return_address(0), 42 gpu_read(gpu, REG_A6XX_RBBM_STATUS), 43 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS), 44 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), 45 gpu_read(gpu, REG_A6XX_CP_RB_WPTR)); 46 return false; 47 } 48 49 return true; 50 } 51 52 static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 53 { 54 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 55 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 56 uint32_t wptr; 57 unsigned long flags; 58 59 /* Expanded APRIV doesn't need to issue the WHERE_AM_I opcode */ 60 if (a6xx_gpu->has_whereami && !adreno_gpu->base.hw_apriv) { 61 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 62 63 OUT_PKT7(ring, CP_WHERE_AM_I, 2); 64 OUT_RING(ring, lower_32_bits(shadowptr(a6xx_gpu, ring))); 65 OUT_RING(ring, upper_32_bits(shadowptr(a6xx_gpu, ring))); 66 } 67 68 spin_lock_irqsave(&ring->lock, flags); 69 70 /* Copy the shadow to the actual register */ 71 ring->cur = ring->next; 72 73 /* Make sure to wrap wptr if we need to */ 74 wptr = get_wptr(ring); 75 76 spin_unlock_irqrestore(&ring->lock, flags); 77 78 /* Make sure everything is posted before making a decision */ 79 mb(); 80 81 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); 82 } 83 84 static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, 85 u64 iova) 86 { 87 OUT_PKT7(ring, CP_REG_TO_MEM, 3); 88 OUT_RING(ring, CP_REG_TO_MEM_0_REG(counter) | 89 CP_REG_TO_MEM_0_CNT(2) | 90 CP_REG_TO_MEM_0_64B); 91 OUT_RING(ring, lower_32_bits(iova)); 92 OUT_RING(ring, upper_32_bits(iova)); 93 } 94 95 static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, 96 struct msm_ringbuffer *ring, struct msm_file_private *ctx) 97 { 98 phys_addr_t ttbr; 99 u32 asid; 100 u64 memptr = rbmemptr(ring, ttbr0); 101 102 if (ctx == a6xx_gpu->cur_ctx) 103 return; 104 105 if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid)) 106 return; 107 108 /* Execute the table update */ 109 OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4); 110 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr))); 111 112 OUT_RING(ring, 113 CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) | 114 CP_SMMU_TABLE_UPDATE_1_ASID(asid)); 115 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0)); 116 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0)); 117 118 /* 119 * Write the new TTBR0 to the memstore. This is good for debugging. 120 */ 121 OUT_PKT7(ring, CP_MEM_WRITE, 4); 122 OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr))); 123 OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr))); 124 OUT_RING(ring, lower_32_bits(ttbr)); 125 OUT_RING(ring, (asid << 16) | upper_32_bits(ttbr)); 126 127 /* 128 * And finally, trigger a uche flush to be sure there isn't anything 129 * lingering in that part of the GPU 130 */ 131 132 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 133 OUT_RING(ring, 0x31); 134 135 a6xx_gpu->cur_ctx = ctx; 136 } 137 138 static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 139 { 140 unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; 141 struct msm_drm_private *priv = gpu->dev->dev_private; 142 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 143 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 144 struct msm_ringbuffer *ring = submit->ring; 145 unsigned int i; 146 147 a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx); 148 149 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO, 150 rbmemptr_stats(ring, index, cpcycles_start)); 151 152 /* 153 * For PM4 the GMU register offsets are calculated from the base of the 154 * GPU registers so we need to add 0x1a800 to the register value on A630 155 * to get the right value from PM4. 156 */ 157 get_stats_counter(ring, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L + 0x1a800, 158 rbmemptr_stats(ring, index, alwayson_start)); 159 160 /* Invalidate CCU depth and color */ 161 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 162 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_DEPTH)); 163 164 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 165 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_COLOR)); 166 167 /* Submit the commands */ 168 for (i = 0; i < submit->nr_cmds; i++) { 169 switch (submit->cmd[i].type) { 170 case MSM_SUBMIT_CMD_IB_TARGET_BUF: 171 break; 172 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: 173 if (priv->lastctx == submit->queue->ctx) 174 break; 175 fallthrough; 176 case MSM_SUBMIT_CMD_BUF: 177 OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3); 178 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); 179 OUT_RING(ring, upper_32_bits(submit->cmd[i].iova)); 180 OUT_RING(ring, submit->cmd[i].size); 181 break; 182 } 183 } 184 185 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO, 186 rbmemptr_stats(ring, index, cpcycles_end)); 187 get_stats_counter(ring, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L + 0x1a800, 188 rbmemptr_stats(ring, index, alwayson_end)); 189 190 /* Write the fence to the scratch register */ 191 OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1); 192 OUT_RING(ring, submit->seqno); 193 194 /* 195 * Execute a CACHE_FLUSH_TS event. This will ensure that the 196 * timestamp is written to the memory and then triggers the interrupt 197 */ 198 OUT_PKT7(ring, CP_EVENT_WRITE, 4); 199 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(CACHE_FLUSH_TS) | 200 CP_EVENT_WRITE_0_IRQ); 201 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence))); 202 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); 203 OUT_RING(ring, submit->seqno); 204 205 trace_msm_gpu_submit_flush(submit, 206 gmu_read64(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L, 207 REG_A6XX_GMU_ALWAYS_ON_COUNTER_H)); 208 209 a6xx_flush(gpu, ring); 210 } 211 212 const struct adreno_reglist a630_hwcg[] = { 213 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, 214 {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222}, 215 {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222}, 216 {REG_A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222}, 217 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220}, 218 {REG_A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220}, 219 {REG_A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220}, 220 {REG_A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220}, 221 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 222 {REG_A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080}, 223 {REG_A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080}, 224 {REG_A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080}, 225 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf}, 226 {REG_A6XX_RBBM_CLOCK_HYST_SP1, 0x0000f3cf}, 227 {REG_A6XX_RBBM_CLOCK_HYST_SP2, 0x0000f3cf}, 228 {REG_A6XX_RBBM_CLOCK_HYST_SP3, 0x0000f3cf}, 229 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, 230 {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222}, 231 {REG_A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222}, 232 {REG_A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222}, 233 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 234 {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222}, 235 {REG_A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222}, 236 {REG_A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222}, 237 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 238 {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222}, 239 {REG_A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222}, 240 {REG_A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222}, 241 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 242 {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222}, 243 {REG_A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222}, 244 {REG_A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222}, 245 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 246 {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777}, 247 {REG_A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777}, 248 {REG_A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777}, 249 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 250 {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777}, 251 {REG_A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777}, 252 {REG_A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777}, 253 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 254 {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777}, 255 {REG_A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777}, 256 {REG_A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777}, 257 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 258 {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777}, 259 {REG_A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777}, 260 {REG_A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777}, 261 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 262 {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111}, 263 {REG_A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111}, 264 {REG_A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111}, 265 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 266 {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111}, 267 {REG_A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111}, 268 {REG_A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111}, 269 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 270 {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111}, 271 {REG_A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111}, 272 {REG_A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111}, 273 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 274 {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111}, 275 {REG_A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111}, 276 {REG_A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111}, 277 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 278 {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222}, 279 {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222}, 280 {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222}, 281 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 282 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 283 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 284 {REG_A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222}, 285 {REG_A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222}, 286 {REG_A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222}, 287 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222}, 288 {REG_A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222}, 289 {REG_A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222}, 290 {REG_A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222}, 291 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 292 {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220}, 293 {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220}, 294 {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220}, 295 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00}, 296 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040f00}, 297 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040f00}, 298 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040f00}, 299 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022}, 300 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 301 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 302 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 303 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 304 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 305 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 306 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 307 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 308 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 309 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 310 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 311 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 312 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 313 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 314 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 315 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 316 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 317 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 318 {}, 319 }; 320 321 const struct adreno_reglist a640_hwcg[] = { 322 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, 323 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, 324 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 325 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, 326 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, 327 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 328 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 329 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 330 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 331 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 332 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 333 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 334 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 335 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 336 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 337 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 338 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 339 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, 340 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 341 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, 342 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022}, 343 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 344 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 345 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 346 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 347 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 348 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 349 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 350 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 351 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 352 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 353 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 354 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 355 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 356 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 357 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 358 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, 359 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, 360 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, 361 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000}, 362 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 363 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 364 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 365 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, 366 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, 367 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, 368 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 369 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 370 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 371 {}, 372 }; 373 374 const struct adreno_reglist a650_hwcg[] = { 375 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, 376 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, 377 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 378 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, 379 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, 380 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 381 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 382 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 383 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 384 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 385 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 386 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 387 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 388 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 389 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 390 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 391 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 392 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, 393 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 394 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, 395 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022}, 396 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 397 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 398 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 399 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 400 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 401 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 402 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 403 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 404 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 405 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 406 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 407 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 408 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 409 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 410 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 411 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, 412 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, 413 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, 414 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777}, 415 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 416 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 417 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 418 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, 419 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, 420 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, 421 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 422 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 423 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 424 {}, 425 }; 426 427 static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) 428 { 429 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 430 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 431 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 432 const struct adreno_reglist *reg; 433 unsigned int i; 434 u32 val, clock_cntl_on; 435 436 if (!adreno_gpu->info->hwcg) 437 return; 438 439 if (adreno_is_a630(adreno_gpu)) 440 clock_cntl_on = 0x8aa8aa02; 441 else 442 clock_cntl_on = 0x8aa8aa82; 443 444 val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL); 445 446 /* Don't re-program the registers if they are already correct */ 447 if ((!state && !val) || (state && (val == clock_cntl_on))) 448 return; 449 450 /* Disable SP clock before programming HWCG registers */ 451 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); 452 453 for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++) 454 gpu_write(gpu, reg->offset, state ? reg->value : 0); 455 456 /* Enable SP clock */ 457 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); 458 459 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); 460 } 461 462 static void a6xx_set_ubwc_config(struct msm_gpu *gpu) 463 { 464 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 465 u32 lower_bit = 2; 466 u32 amsbc = 0; 467 u32 rgb565_predicator = 0; 468 u32 uavflagprd_inv = 0; 469 470 /* a618 is using the hw default values */ 471 if (adreno_is_a618(adreno_gpu)) 472 return; 473 474 if (adreno_is_a640(adreno_gpu)) 475 amsbc = 1; 476 477 if (adreno_is_a650(adreno_gpu)) { 478 /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ 479 lower_bit = 3; 480 amsbc = 1; 481 rgb565_predicator = 1; 482 uavflagprd_inv = 2; 483 } 484 485 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 486 rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1); 487 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1); 488 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 489 uavflagprd_inv >> 4 | lower_bit << 1); 490 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21); 491 } 492 493 static int a6xx_cp_init(struct msm_gpu *gpu) 494 { 495 struct msm_ringbuffer *ring = gpu->rb[0]; 496 497 OUT_PKT7(ring, CP_ME_INIT, 8); 498 499 OUT_RING(ring, 0x0000002f); 500 501 /* Enable multiple hardware contexts */ 502 OUT_RING(ring, 0x00000003); 503 504 /* Enable error detection */ 505 OUT_RING(ring, 0x20000000); 506 507 /* Don't enable header dump */ 508 OUT_RING(ring, 0x00000000); 509 OUT_RING(ring, 0x00000000); 510 511 /* No workarounds enabled */ 512 OUT_RING(ring, 0x00000000); 513 514 /* Pad rest of the cmds with 0's */ 515 OUT_RING(ring, 0x00000000); 516 OUT_RING(ring, 0x00000000); 517 518 a6xx_flush(gpu, ring); 519 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; 520 } 521 522 static void a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu, 523 struct drm_gem_object *obj) 524 { 525 u32 *buf = msm_gem_get_vaddr_active(obj); 526 527 if (IS_ERR(buf)) 528 return; 529 530 /* 531 * If the lowest nibble is 0xa that is an indication that this microcode 532 * has been patched. The actual version is in dword [3] but we only care 533 * about the patchlevel which is the lowest nibble of dword [3] 534 * 535 * Otherwise check that the firmware is greater than or equal to 1.90 536 * which was the first version that had this fix built in 537 */ 538 if (((buf[0] & 0xf) == 0xa) && (buf[2] & 0xf) >= 1) 539 a6xx_gpu->has_whereami = true; 540 else if ((buf[0] & 0xfff) > 0x190) 541 a6xx_gpu->has_whereami = true; 542 543 msm_gem_put_vaddr(obj); 544 } 545 546 static int a6xx_ucode_init(struct msm_gpu *gpu) 547 { 548 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 549 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 550 551 if (!a6xx_gpu->sqe_bo) { 552 a6xx_gpu->sqe_bo = adreno_fw_create_bo(gpu, 553 adreno_gpu->fw[ADRENO_FW_SQE], &a6xx_gpu->sqe_iova); 554 555 if (IS_ERR(a6xx_gpu->sqe_bo)) { 556 int ret = PTR_ERR(a6xx_gpu->sqe_bo); 557 558 a6xx_gpu->sqe_bo = NULL; 559 DRM_DEV_ERROR(&gpu->pdev->dev, 560 "Could not allocate SQE ucode: %d\n", ret); 561 562 return ret; 563 } 564 565 msm_gem_object_set_name(a6xx_gpu->sqe_bo, "sqefw"); 566 a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->sqe_bo); 567 } 568 569 gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE_LO, 570 REG_A6XX_CP_SQE_INSTR_BASE_HI, a6xx_gpu->sqe_iova); 571 572 return 0; 573 } 574 575 static int a6xx_zap_shader_init(struct msm_gpu *gpu) 576 { 577 static bool loaded; 578 int ret; 579 580 if (loaded) 581 return 0; 582 583 ret = adreno_zap_shader_load(gpu, GPU_PAS_ID); 584 585 loaded = !ret; 586 return ret; 587 } 588 589 #define A6XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \ 590 A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \ 591 A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \ 592 A6XX_RBBM_INT_0_MASK_CP_IB2 | \ 593 A6XX_RBBM_INT_0_MASK_CP_IB1 | \ 594 A6XX_RBBM_INT_0_MASK_CP_RB | \ 595 A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \ 596 A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \ 597 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \ 598 A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \ 599 A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR) 600 601 static int a6xx_hw_init(struct msm_gpu *gpu) 602 { 603 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 604 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 605 int ret; 606 607 /* Make sure the GMU keeps the GPU on while we set it up */ 608 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 609 610 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); 611 612 /* 613 * Disable the trusted memory range - we don't actually supported secure 614 * memory rendering at this point in time and we don't want to block off 615 * part of the virtual memory space. 616 */ 617 gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO, 618 REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x00000000); 619 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); 620 621 /* Turn on 64 bit addressing for all blocks */ 622 gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1); 623 gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1); 624 gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1); 625 gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1); 626 gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1); 627 gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1); 628 gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1); 629 gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1); 630 gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1); 631 gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1); 632 gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1); 633 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1); 634 635 /* enable hardware clockgating */ 636 a6xx_set_hwcg(gpu, true); 637 638 /* VBIF/GBIF start*/ 639 if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu)) { 640 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); 641 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); 642 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); 643 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); 644 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); 645 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3); 646 } else { 647 gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3); 648 } 649 650 if (adreno_is_a630(adreno_gpu)) 651 gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009); 652 653 /* Make all blocks contribute to the GPU BUSY perf counter */ 654 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff); 655 656 /* Disable L2 bypass in the UCHE */ 657 gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_LO, 0xffffffc0); 658 gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_HI, 0x0001ffff); 659 gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_LO, 0xfffff000); 660 gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_HI, 0x0001ffff); 661 gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000); 662 gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff); 663 664 if (!adreno_is_a650(adreno_gpu)) { 665 /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */ 666 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN_LO, 667 REG_A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x00100000); 668 669 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX_LO, 670 REG_A6XX_UCHE_GMEM_RANGE_MAX_HI, 671 0x00100000 + adreno_gpu->gmem - 1); 672 } 673 674 gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804); 675 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4); 676 677 if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu)) 678 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); 679 else 680 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0); 681 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); 682 683 /* Setting the mem pool size */ 684 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); 685 686 /* Setting the primFifo thresholds default values */ 687 if (adreno_is_a650(adreno_gpu)) 688 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300000); 689 else if (adreno_is_a640(adreno_gpu)) 690 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200000); 691 else 692 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, (0x300 << 11)); 693 694 /* Set the AHB default slave response to "ERROR" */ 695 gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1); 696 697 /* Turn on performance counters */ 698 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1); 699 700 /* Select CP0 to always count cycles */ 701 gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT); 702 703 a6xx_set_ubwc_config(gpu); 704 705 /* Enable fault detection */ 706 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, 707 (1 << 30) | 0x1fffff); 708 709 gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1); 710 711 /* Set weights for bicubic filtering */ 712 if (adreno_is_a650(adreno_gpu)) { 713 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0); 714 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, 715 0x3fe05ff4); 716 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2, 717 0x3fa0ebee); 718 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3, 719 0x3f5193ed); 720 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4, 721 0x3f0243f0); 722 } 723 724 /* Protect registers from the CP */ 725 gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, 0x00000003); 726 727 gpu_write(gpu, REG_A6XX_CP_PROTECT(0), 728 A6XX_PROTECT_RDONLY(0x600, 0x51)); 729 gpu_write(gpu, REG_A6XX_CP_PROTECT(1), A6XX_PROTECT_RW(0xae50, 0x2)); 730 gpu_write(gpu, REG_A6XX_CP_PROTECT(2), A6XX_PROTECT_RW(0x9624, 0x13)); 731 gpu_write(gpu, REG_A6XX_CP_PROTECT(3), A6XX_PROTECT_RW(0x8630, 0x8)); 732 gpu_write(gpu, REG_A6XX_CP_PROTECT(4), A6XX_PROTECT_RW(0x9e70, 0x1)); 733 gpu_write(gpu, REG_A6XX_CP_PROTECT(5), A6XX_PROTECT_RW(0x9e78, 0x187)); 734 gpu_write(gpu, REG_A6XX_CP_PROTECT(6), A6XX_PROTECT_RW(0xf000, 0x810)); 735 gpu_write(gpu, REG_A6XX_CP_PROTECT(7), 736 A6XX_PROTECT_RDONLY(0xfc00, 0x3)); 737 gpu_write(gpu, REG_A6XX_CP_PROTECT(8), A6XX_PROTECT_RW(0x50e, 0x0)); 738 gpu_write(gpu, REG_A6XX_CP_PROTECT(9), A6XX_PROTECT_RDONLY(0x50f, 0x0)); 739 gpu_write(gpu, REG_A6XX_CP_PROTECT(10), A6XX_PROTECT_RW(0x510, 0x0)); 740 gpu_write(gpu, REG_A6XX_CP_PROTECT(11), 741 A6XX_PROTECT_RDONLY(0x0, 0x4f9)); 742 gpu_write(gpu, REG_A6XX_CP_PROTECT(12), 743 A6XX_PROTECT_RDONLY(0x501, 0xa)); 744 gpu_write(gpu, REG_A6XX_CP_PROTECT(13), 745 A6XX_PROTECT_RDONLY(0x511, 0x44)); 746 gpu_write(gpu, REG_A6XX_CP_PROTECT(14), A6XX_PROTECT_RW(0xe00, 0xe)); 747 gpu_write(gpu, REG_A6XX_CP_PROTECT(15), A6XX_PROTECT_RW(0x8e00, 0x0)); 748 gpu_write(gpu, REG_A6XX_CP_PROTECT(16), A6XX_PROTECT_RW(0x8e50, 0xf)); 749 gpu_write(gpu, REG_A6XX_CP_PROTECT(17), A6XX_PROTECT_RW(0xbe02, 0x0)); 750 gpu_write(gpu, REG_A6XX_CP_PROTECT(18), 751 A6XX_PROTECT_RW(0xbe20, 0x11f3)); 752 gpu_write(gpu, REG_A6XX_CP_PROTECT(19), A6XX_PROTECT_RW(0x800, 0x82)); 753 gpu_write(gpu, REG_A6XX_CP_PROTECT(20), A6XX_PROTECT_RW(0x8a0, 0x8)); 754 gpu_write(gpu, REG_A6XX_CP_PROTECT(21), A6XX_PROTECT_RW(0x8ab, 0x19)); 755 gpu_write(gpu, REG_A6XX_CP_PROTECT(22), A6XX_PROTECT_RW(0x900, 0x4d)); 756 gpu_write(gpu, REG_A6XX_CP_PROTECT(23), A6XX_PROTECT_RW(0x98d, 0x76)); 757 gpu_write(gpu, REG_A6XX_CP_PROTECT(24), 758 A6XX_PROTECT_RDONLY(0x980, 0x4)); 759 gpu_write(gpu, REG_A6XX_CP_PROTECT(25), A6XX_PROTECT_RW(0xa630, 0x0)); 760 761 /* Enable expanded apriv for targets that support it */ 762 if (gpu->hw_apriv) { 763 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL, 764 (1 << 6) | (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1)); 765 } 766 767 /* Enable interrupts */ 768 gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, A6XX_INT_MASK); 769 770 ret = adreno_hw_init(gpu); 771 if (ret) 772 goto out; 773 774 ret = a6xx_ucode_init(gpu); 775 if (ret) 776 goto out; 777 778 /* Set the ringbuffer address */ 779 gpu_write64(gpu, REG_A6XX_CP_RB_BASE, REG_A6XX_CP_RB_BASE_HI, 780 gpu->rb[0]->iova); 781 782 /* Targets that support extended APRIV can use the RPTR shadow from 783 * hardware but all the other ones need to disable the feature. Targets 784 * that support the WHERE_AM_I opcode can use that instead 785 */ 786 if (adreno_gpu->base.hw_apriv) 787 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT); 788 else 789 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, 790 MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE); 791 792 /* 793 * Expanded APRIV and targets that support WHERE_AM_I both need a 794 * privileged buffer to store the RPTR shadow 795 */ 796 797 if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) { 798 if (!a6xx_gpu->shadow_bo) { 799 a6xx_gpu->shadow = msm_gem_kernel_new_locked(gpu->dev, 800 sizeof(u32) * gpu->nr_rings, 801 MSM_BO_UNCACHED | MSM_BO_MAP_PRIV, 802 gpu->aspace, &a6xx_gpu->shadow_bo, 803 &a6xx_gpu->shadow_iova); 804 805 if (IS_ERR(a6xx_gpu->shadow)) 806 return PTR_ERR(a6xx_gpu->shadow); 807 } 808 809 gpu_write64(gpu, REG_A6XX_CP_RB_RPTR_ADDR_LO, 810 REG_A6XX_CP_RB_RPTR_ADDR_HI, 811 shadowptr(a6xx_gpu, gpu->rb[0])); 812 } 813 814 /* Always come up on rb 0 */ 815 a6xx_gpu->cur_ring = gpu->rb[0]; 816 817 a6xx_gpu->cur_ctx = NULL; 818 819 /* Enable the SQE_to start the CP engine */ 820 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1); 821 822 ret = a6xx_cp_init(gpu); 823 if (ret) 824 goto out; 825 826 /* 827 * Try to load a zap shader into the secure world. If successful 828 * we can use the CP to switch out of secure mode. If not then we 829 * have no resource but to try to switch ourselves out manually. If we 830 * guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will 831 * be blocked and a permissions violation will soon follow. 832 */ 833 ret = a6xx_zap_shader_init(gpu); 834 if (!ret) { 835 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1); 836 OUT_RING(gpu->rb[0], 0x00000000); 837 838 a6xx_flush(gpu, gpu->rb[0]); 839 if (!a6xx_idle(gpu, gpu->rb[0])) 840 return -EINVAL; 841 } else if (ret == -ENODEV) { 842 /* 843 * This device does not use zap shader (but print a warning 844 * just in case someone got their dt wrong.. hopefully they 845 * have a debug UART to realize the error of their ways... 846 * if you mess this up you are about to crash horribly) 847 */ 848 dev_warn_once(gpu->dev->dev, 849 "Zap shader not enabled - using SECVID_TRUST_CNTL instead\n"); 850 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0); 851 ret = 0; 852 } else { 853 return ret; 854 } 855 856 out: 857 /* 858 * Tell the GMU that we are done touching the GPU and it can start power 859 * management 860 */ 861 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 862 863 if (a6xx_gpu->gmu.legacy) { 864 /* Take the GMU out of its special boot mode */ 865 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER); 866 } 867 868 return ret; 869 } 870 871 static void a6xx_dump(struct msm_gpu *gpu) 872 { 873 DRM_DEV_INFO(&gpu->pdev->dev, "status: %08x\n", 874 gpu_read(gpu, REG_A6XX_RBBM_STATUS)); 875 adreno_dump(gpu); 876 } 877 878 #define VBIF_RESET_ACK_TIMEOUT 100 879 #define VBIF_RESET_ACK_MASK 0x00f0 880 881 static void a6xx_recover(struct msm_gpu *gpu) 882 { 883 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 884 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 885 int i; 886 887 adreno_dump_info(gpu); 888 889 for (i = 0; i < 8; i++) 890 DRM_DEV_INFO(&gpu->pdev->dev, "CP_SCRATCH_REG%d: %u\n", i, 891 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i))); 892 893 if (hang_debug) 894 a6xx_dump(gpu); 895 896 /* 897 * Turn off keep alive that might have been enabled by the hang 898 * interrupt 899 */ 900 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); 901 902 gpu->funcs->pm_suspend(gpu); 903 gpu->funcs->pm_resume(gpu); 904 905 msm_gpu_hw_init(gpu); 906 } 907 908 static int a6xx_fault_handler(void *arg, unsigned long iova, int flags) 909 { 910 struct msm_gpu *gpu = arg; 911 912 pr_warn_ratelimited("*** gpu fault: iova=%08lx, flags=%d (%u,%u,%u,%u)\n", 913 iova, flags, 914 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)), 915 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)), 916 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)), 917 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7))); 918 919 return -EFAULT; 920 } 921 922 static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu) 923 { 924 u32 status = gpu_read(gpu, REG_A6XX_CP_INTERRUPT_STATUS); 925 926 if (status & A6XX_CP_INT_CP_OPCODE_ERROR) { 927 u32 val; 928 929 gpu_write(gpu, REG_A6XX_CP_SQE_STAT_ADDR, 1); 930 val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA); 931 dev_err_ratelimited(&gpu->pdev->dev, 932 "CP | opcode error | possible opcode=0x%8.8X\n", 933 val); 934 } 935 936 if (status & A6XX_CP_INT_CP_UCODE_ERROR) 937 dev_err_ratelimited(&gpu->pdev->dev, 938 "CP ucode error interrupt\n"); 939 940 if (status & A6XX_CP_INT_CP_HW_FAULT_ERROR) 941 dev_err_ratelimited(&gpu->pdev->dev, "CP | HW fault | status=0x%8.8X\n", 942 gpu_read(gpu, REG_A6XX_CP_HW_FAULT)); 943 944 if (status & A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR) { 945 u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS); 946 947 dev_err_ratelimited(&gpu->pdev->dev, 948 "CP | protected mode error | %s | addr=0x%8.8X | status=0x%8.8X\n", 949 val & (1 << 20) ? "READ" : "WRITE", 950 (val & 0x3ffff), val); 951 } 952 953 if (status & A6XX_CP_INT_CP_AHB_ERROR) 954 dev_err_ratelimited(&gpu->pdev->dev, "CP AHB error interrupt\n"); 955 956 if (status & A6XX_CP_INT_CP_VSD_PARITY_ERROR) 957 dev_err_ratelimited(&gpu->pdev->dev, "CP VSD decoder parity error\n"); 958 959 if (status & A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR) 960 dev_err_ratelimited(&gpu->pdev->dev, "CP illegal instruction error\n"); 961 962 } 963 964 static void a6xx_fault_detect_irq(struct msm_gpu *gpu) 965 { 966 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 967 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 968 struct drm_device *dev = gpu->dev; 969 struct msm_drm_private *priv = dev->dev_private; 970 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); 971 972 /* 973 * Force the GPU to stay on until after we finish 974 * collecting information 975 */ 976 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1); 977 978 DRM_DEV_ERROR(&gpu->pdev->dev, 979 "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n", 980 ring ? ring->id : -1, ring ? ring->seqno : 0, 981 gpu_read(gpu, REG_A6XX_RBBM_STATUS), 982 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), 983 gpu_read(gpu, REG_A6XX_CP_RB_WPTR), 984 gpu_read64(gpu, REG_A6XX_CP_IB1_BASE, REG_A6XX_CP_IB1_BASE_HI), 985 gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE), 986 gpu_read64(gpu, REG_A6XX_CP_IB2_BASE, REG_A6XX_CP_IB2_BASE_HI), 987 gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE)); 988 989 /* Turn off the hangcheck timer to keep it from bothering us */ 990 del_timer(&gpu->hangcheck_timer); 991 992 queue_work(priv->wq, &gpu->recover_work); 993 } 994 995 static irqreturn_t a6xx_irq(struct msm_gpu *gpu) 996 { 997 u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS); 998 999 gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status); 1000 1001 if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT) 1002 a6xx_fault_detect_irq(gpu); 1003 1004 if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR) 1005 dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n"); 1006 1007 if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR) 1008 a6xx_cp_hw_err_irq(gpu); 1009 1010 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW) 1011 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB ASYNC overflow\n"); 1012 1013 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW) 1014 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB bus overflow\n"); 1015 1016 if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS) 1017 dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n"); 1018 1019 if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) 1020 msm_gpu_retire(gpu); 1021 1022 return IRQ_HANDLED; 1023 } 1024 1025 static int a6xx_pm_resume(struct msm_gpu *gpu) 1026 { 1027 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1028 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1029 int ret; 1030 1031 gpu->needs_hw_init = true; 1032 1033 trace_msm_gpu_resume(0); 1034 1035 ret = a6xx_gmu_resume(a6xx_gpu); 1036 if (ret) 1037 return ret; 1038 1039 msm_gpu_resume_devfreq(gpu); 1040 1041 return 0; 1042 } 1043 1044 static int a6xx_pm_suspend(struct msm_gpu *gpu) 1045 { 1046 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1047 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1048 1049 trace_msm_gpu_suspend(0); 1050 1051 devfreq_suspend_device(gpu->devfreq.devfreq); 1052 1053 return a6xx_gmu_stop(a6xx_gpu); 1054 } 1055 1056 static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) 1057 { 1058 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1059 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1060 1061 /* Force the GPU power on so we can read this register */ 1062 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 1063 1064 *value = gpu_read64(gpu, REG_A6XX_RBBM_PERFCTR_CP_0_LO, 1065 REG_A6XX_RBBM_PERFCTR_CP_0_HI); 1066 1067 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 1068 return 0; 1069 } 1070 1071 static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu) 1072 { 1073 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1074 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1075 1076 return a6xx_gpu->cur_ring; 1077 } 1078 1079 static void a6xx_destroy(struct msm_gpu *gpu) 1080 { 1081 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1082 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1083 1084 if (a6xx_gpu->sqe_bo) { 1085 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace); 1086 drm_gem_object_put(a6xx_gpu->sqe_bo); 1087 } 1088 1089 if (a6xx_gpu->shadow_bo) { 1090 msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->aspace); 1091 drm_gem_object_put(a6xx_gpu->shadow_bo); 1092 } 1093 1094 a6xx_gmu_remove(a6xx_gpu); 1095 1096 adreno_gpu_cleanup(adreno_gpu); 1097 kfree(a6xx_gpu); 1098 } 1099 1100 static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu) 1101 { 1102 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1103 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1104 u64 busy_cycles, busy_time; 1105 1106 1107 /* Only read the gpu busy if the hardware is already active */ 1108 if (pm_runtime_get_if_in_use(a6xx_gpu->gmu.dev) == 0) 1109 return 0; 1110 1111 busy_cycles = gmu_read64(&a6xx_gpu->gmu, 1112 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L, 1113 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H); 1114 1115 busy_time = (busy_cycles - gpu->devfreq.busy_cycles) * 10; 1116 do_div(busy_time, 192); 1117 1118 gpu->devfreq.busy_cycles = busy_cycles; 1119 1120 pm_runtime_put(a6xx_gpu->gmu.dev); 1121 1122 if (WARN_ON(busy_time > ~0LU)) 1123 return ~0LU; 1124 1125 return (unsigned long)busy_time; 1126 } 1127 1128 static struct msm_gem_address_space * 1129 a6xx_create_private_address_space(struct msm_gpu *gpu) 1130 { 1131 struct msm_mmu *mmu; 1132 1133 mmu = msm_iommu_pagetable_create(gpu->aspace->mmu); 1134 1135 if (IS_ERR(mmu)) 1136 return ERR_CAST(mmu); 1137 1138 return msm_gem_address_space_create(mmu, 1139 "gpu", 0x100000000ULL, 0x1ffffffffULL); 1140 } 1141 1142 static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 1143 { 1144 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1145 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1146 1147 if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) 1148 return a6xx_gpu->shadow[ring->id]; 1149 1150 return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR); 1151 } 1152 1153 static const struct adreno_gpu_funcs funcs = { 1154 .base = { 1155 .get_param = adreno_get_param, 1156 .hw_init = a6xx_hw_init, 1157 .pm_suspend = a6xx_pm_suspend, 1158 .pm_resume = a6xx_pm_resume, 1159 .recover = a6xx_recover, 1160 .submit = a6xx_submit, 1161 .active_ring = a6xx_active_ring, 1162 .irq = a6xx_irq, 1163 .destroy = a6xx_destroy, 1164 #if defined(CONFIG_DRM_MSM_GPU_STATE) 1165 .show = a6xx_show, 1166 #endif 1167 .gpu_busy = a6xx_gpu_busy, 1168 .gpu_get_freq = a6xx_gmu_get_freq, 1169 .gpu_set_freq = a6xx_gmu_set_freq, 1170 #if defined(CONFIG_DRM_MSM_GPU_STATE) 1171 .gpu_state_get = a6xx_gpu_state_get, 1172 .gpu_state_put = a6xx_gpu_state_put, 1173 #endif 1174 .create_address_space = adreno_iommu_create_address_space, 1175 .create_private_address_space = a6xx_create_private_address_space, 1176 .get_rptr = a6xx_get_rptr, 1177 }, 1178 .get_timestamp = a6xx_get_timestamp, 1179 }; 1180 1181 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) 1182 { 1183 struct msm_drm_private *priv = dev->dev_private; 1184 struct platform_device *pdev = priv->gpu_pdev; 1185 struct adreno_platform_config *config = pdev->dev.platform_data; 1186 const struct adreno_info *info; 1187 struct device_node *node; 1188 struct a6xx_gpu *a6xx_gpu; 1189 struct adreno_gpu *adreno_gpu; 1190 struct msm_gpu *gpu; 1191 int ret; 1192 1193 a6xx_gpu = kzalloc(sizeof(*a6xx_gpu), GFP_KERNEL); 1194 if (!a6xx_gpu) 1195 return ERR_PTR(-ENOMEM); 1196 1197 adreno_gpu = &a6xx_gpu->base; 1198 gpu = &adreno_gpu->base; 1199 1200 adreno_gpu->registers = NULL; 1201 1202 /* 1203 * We need to know the platform type before calling into adreno_gpu_init 1204 * so that the hw_apriv flag can be correctly set. Snoop into the info 1205 * and grab the revision number 1206 */ 1207 info = adreno_info(config->rev); 1208 1209 if (info && info->revn == 650) 1210 adreno_gpu->base.hw_apriv = true; 1211 1212 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); 1213 if (ret) { 1214 a6xx_destroy(&(a6xx_gpu->base.base)); 1215 return ERR_PTR(ret); 1216 } 1217 1218 /* Check if there is a GMU phandle and set it up */ 1219 node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0); 1220 1221 /* FIXME: How do we gracefully handle this? */ 1222 BUG_ON(!node); 1223 1224 ret = a6xx_gmu_init(a6xx_gpu, node); 1225 if (ret) { 1226 a6xx_destroy(&(a6xx_gpu->base.base)); 1227 return ERR_PTR(ret); 1228 } 1229 1230 if (gpu->aspace) 1231 msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, 1232 a6xx_fault_handler); 1233 1234 return gpu; 1235 } 1236