1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */ 3 4 5 #include "msm_gem.h" 6 #include "msm_mmu.h" 7 #include "msm_gpu_trace.h" 8 #include "a6xx_gpu.h" 9 #include "a6xx_gmu.xml.h" 10 11 #include <linux/bitfield.h> 12 #include <linux/devfreq.h> 13 #include <linux/pm_domain.h> 14 #include <linux/soc/qcom/llcc-qcom.h> 15 16 #define GPU_PAS_ID 13 17 18 static inline bool _a6xx_check_idle(struct msm_gpu *gpu) 19 { 20 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 21 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 22 23 /* Check that the GMU is idle */ 24 if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_isidle(&a6xx_gpu->gmu)) 25 return false; 26 27 /* Check tha the CX master is idle */ 28 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & 29 ~A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER) 30 return false; 31 32 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & 33 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT); 34 } 35 36 static bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 37 { 38 /* wait for CP to drain ringbuffer: */ 39 if (!adreno_idle(gpu, ring)) 40 return false; 41 42 if (spin_until(_a6xx_check_idle(gpu))) { 43 DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n", 44 gpu->name, __builtin_return_address(0), 45 gpu_read(gpu, REG_A6XX_RBBM_STATUS), 46 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS), 47 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), 48 gpu_read(gpu, REG_A6XX_CP_RB_WPTR)); 49 return false; 50 } 51 52 return true; 53 } 54 55 static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 56 { 57 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 58 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 59 60 /* Expanded APRIV doesn't need to issue the WHERE_AM_I opcode */ 61 if (a6xx_gpu->has_whereami && !adreno_gpu->base.hw_apriv) { 62 OUT_PKT7(ring, CP_WHERE_AM_I, 2); 63 OUT_RING(ring, lower_32_bits(shadowptr(a6xx_gpu, ring))); 64 OUT_RING(ring, upper_32_bits(shadowptr(a6xx_gpu, ring))); 65 } 66 } 67 68 static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 69 { 70 uint32_t wptr; 71 unsigned long flags; 72 73 update_shadow_rptr(gpu, ring); 74 75 spin_lock_irqsave(&ring->preempt_lock, flags); 76 77 /* Copy the shadow to the actual register */ 78 ring->cur = ring->next; 79 80 /* Make sure to wrap wptr if we need to */ 81 wptr = get_wptr(ring); 82 83 spin_unlock_irqrestore(&ring->preempt_lock, flags); 84 85 /* Make sure everything is posted before making a decision */ 86 mb(); 87 88 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); 89 } 90 91 static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, 92 u64 iova) 93 { 94 OUT_PKT7(ring, CP_REG_TO_MEM, 3); 95 OUT_RING(ring, CP_REG_TO_MEM_0_REG(counter) | 96 CP_REG_TO_MEM_0_CNT(2) | 97 CP_REG_TO_MEM_0_64B); 98 OUT_RING(ring, lower_32_bits(iova)); 99 OUT_RING(ring, upper_32_bits(iova)); 100 } 101 102 static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, 103 struct msm_ringbuffer *ring, struct msm_file_private *ctx) 104 { 105 bool sysprof = refcount_read(&a6xx_gpu->base.base.sysprof_active) > 1; 106 phys_addr_t ttbr; 107 u32 asid; 108 u64 memptr = rbmemptr(ring, ttbr0); 109 110 if (ctx->seqno == a6xx_gpu->base.base.cur_ctx_seqno) 111 return; 112 113 if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid)) 114 return; 115 116 if (!sysprof) { 117 /* Turn off protected mode to write to special registers */ 118 OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); 119 OUT_RING(ring, 0); 120 121 OUT_PKT4(ring, REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD, 1); 122 OUT_RING(ring, 1); 123 } 124 125 /* Execute the table update */ 126 OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4); 127 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr))); 128 129 OUT_RING(ring, 130 CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) | 131 CP_SMMU_TABLE_UPDATE_1_ASID(asid)); 132 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0)); 133 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0)); 134 135 /* 136 * Write the new TTBR0 to the memstore. This is good for debugging. 137 */ 138 OUT_PKT7(ring, CP_MEM_WRITE, 4); 139 OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr))); 140 OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr))); 141 OUT_RING(ring, lower_32_bits(ttbr)); 142 OUT_RING(ring, (asid << 16) | upper_32_bits(ttbr)); 143 144 /* 145 * And finally, trigger a uche flush to be sure there isn't anything 146 * lingering in that part of the GPU 147 */ 148 149 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 150 OUT_RING(ring, CACHE_INVALIDATE); 151 152 if (!sysprof) { 153 /* 154 * Wait for SRAM clear after the pgtable update, so the 155 * two can happen in parallel: 156 */ 157 OUT_PKT7(ring, CP_WAIT_REG_MEM, 6); 158 OUT_RING(ring, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ)); 159 OUT_RING(ring, CP_WAIT_REG_MEM_1_POLL_ADDR_LO( 160 REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS)); 161 OUT_RING(ring, CP_WAIT_REG_MEM_2_POLL_ADDR_HI(0)); 162 OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(0x1)); 163 OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(0x1)); 164 OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(0)); 165 166 /* Re-enable protected mode: */ 167 OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1); 168 OUT_RING(ring, 1); 169 } 170 } 171 172 static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 173 { 174 unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; 175 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 176 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 177 struct msm_ringbuffer *ring = submit->ring; 178 unsigned int i, ibs = 0; 179 180 a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx); 181 182 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0), 183 rbmemptr_stats(ring, index, cpcycles_start)); 184 185 /* 186 * For PM4 the GMU register offsets are calculated from the base of the 187 * GPU registers so we need to add 0x1a800 to the register value on A630 188 * to get the right value from PM4. 189 */ 190 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, 191 rbmemptr_stats(ring, index, alwayson_start)); 192 193 /* Invalidate CCU depth and color */ 194 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 195 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_DEPTH)); 196 197 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 198 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_COLOR)); 199 200 /* Submit the commands */ 201 for (i = 0; i < submit->nr_cmds; i++) { 202 switch (submit->cmd[i].type) { 203 case MSM_SUBMIT_CMD_IB_TARGET_BUF: 204 break; 205 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: 206 if (gpu->cur_ctx_seqno == submit->queue->ctx->seqno) 207 break; 208 fallthrough; 209 case MSM_SUBMIT_CMD_BUF: 210 OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3); 211 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); 212 OUT_RING(ring, upper_32_bits(submit->cmd[i].iova)); 213 OUT_RING(ring, submit->cmd[i].size); 214 ibs++; 215 break; 216 } 217 218 /* 219 * Periodically update shadow-wptr if needed, so that we 220 * can see partial progress of submits with large # of 221 * cmds.. otherwise we could needlessly stall waiting for 222 * ringbuffer state, simply due to looking at a shadow 223 * rptr value that has not been updated 224 */ 225 if ((ibs % 32) == 0) 226 update_shadow_rptr(gpu, ring); 227 } 228 229 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0), 230 rbmemptr_stats(ring, index, cpcycles_end)); 231 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER, 232 rbmemptr_stats(ring, index, alwayson_end)); 233 234 /* Write the fence to the scratch register */ 235 OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1); 236 OUT_RING(ring, submit->seqno); 237 238 /* 239 * Execute a CACHE_FLUSH_TS event. This will ensure that the 240 * timestamp is written to the memory and then triggers the interrupt 241 */ 242 OUT_PKT7(ring, CP_EVENT_WRITE, 4); 243 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(CACHE_FLUSH_TS) | 244 CP_EVENT_WRITE_0_IRQ); 245 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence))); 246 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); 247 OUT_RING(ring, submit->seqno); 248 249 trace_msm_gpu_submit_flush(submit, 250 gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER)); 251 252 a6xx_flush(gpu, ring); 253 } 254 255 const struct adreno_reglist a612_hwcg[] = { 256 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, 257 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, 258 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081}, 259 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf}, 260 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, 261 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 262 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 263 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 264 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 265 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 266 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 267 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 268 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 269 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 270 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 271 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 272 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 273 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222}, 274 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 275 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00}, 276 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022}, 277 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 278 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 279 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 280 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 281 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 282 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222}, 283 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 284 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 285 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 286 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 287 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 288 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 289 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 290 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 291 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 292 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, 293 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 294 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 295 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 296 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, 297 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, 298 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, 299 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 300 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 301 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 302 {}, 303 }; 304 305 /* For a615 family (a615, a616, a618 and a619) */ 306 const struct adreno_reglist a615_hwcg[] = { 307 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, 308 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, 309 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 310 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, 311 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, 312 {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222}, 313 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 314 {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222}, 315 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 316 {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222}, 317 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 318 {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222}, 319 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 320 {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777}, 321 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 322 {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777}, 323 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 324 {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777}, 325 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 326 {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777}, 327 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 328 {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111}, 329 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 330 {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111}, 331 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 332 {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111}, 333 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 334 {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111}, 335 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 336 {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222}, 337 {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222}, 338 {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222}, 339 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 340 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 341 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 342 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222}, 343 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002020}, 344 {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220}, 345 {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220}, 346 {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220}, 347 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, 348 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040F00}, 349 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040F00}, 350 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040F00}, 351 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022}, 352 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 353 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 354 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 355 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 356 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 357 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 358 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 359 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 360 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 361 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 362 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 363 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 364 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 365 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 366 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 367 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 368 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 369 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 370 {}, 371 }; 372 373 const struct adreno_reglist a630_hwcg[] = { 374 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, 375 {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222}, 376 {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222}, 377 {REG_A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222}, 378 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220}, 379 {REG_A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220}, 380 {REG_A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220}, 381 {REG_A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220}, 382 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 383 {REG_A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080}, 384 {REG_A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080}, 385 {REG_A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080}, 386 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf}, 387 {REG_A6XX_RBBM_CLOCK_HYST_SP1, 0x0000f3cf}, 388 {REG_A6XX_RBBM_CLOCK_HYST_SP2, 0x0000f3cf}, 389 {REG_A6XX_RBBM_CLOCK_HYST_SP3, 0x0000f3cf}, 390 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, 391 {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222}, 392 {REG_A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222}, 393 {REG_A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222}, 394 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 395 {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222}, 396 {REG_A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222}, 397 {REG_A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222}, 398 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 399 {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222}, 400 {REG_A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222}, 401 {REG_A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222}, 402 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 403 {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222}, 404 {REG_A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222}, 405 {REG_A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222}, 406 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 407 {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777}, 408 {REG_A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777}, 409 {REG_A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777}, 410 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 411 {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777}, 412 {REG_A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777}, 413 {REG_A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777}, 414 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 415 {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777}, 416 {REG_A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777}, 417 {REG_A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777}, 418 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 419 {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777}, 420 {REG_A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777}, 421 {REG_A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777}, 422 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 423 {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111}, 424 {REG_A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111}, 425 {REG_A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111}, 426 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 427 {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111}, 428 {REG_A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111}, 429 {REG_A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111}, 430 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 431 {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111}, 432 {REG_A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111}, 433 {REG_A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111}, 434 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 435 {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111}, 436 {REG_A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111}, 437 {REG_A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111}, 438 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 439 {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222}, 440 {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222}, 441 {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222}, 442 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 443 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 444 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 445 {REG_A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222}, 446 {REG_A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222}, 447 {REG_A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222}, 448 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222}, 449 {REG_A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222}, 450 {REG_A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222}, 451 {REG_A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222}, 452 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 453 {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220}, 454 {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220}, 455 {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220}, 456 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00}, 457 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040f00}, 458 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040f00}, 459 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040f00}, 460 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022}, 461 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 462 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 463 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 464 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 465 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 466 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 467 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 468 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 469 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 470 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 471 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 472 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 473 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 474 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 475 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 476 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 477 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 478 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 479 {}, 480 }; 481 482 const struct adreno_reglist a640_hwcg[] = { 483 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, 484 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, 485 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 486 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, 487 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, 488 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 489 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 490 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 491 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 492 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 493 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 494 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 495 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 496 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 497 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 498 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 499 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 500 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, 501 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 502 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, 503 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022}, 504 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 505 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 506 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 507 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 508 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 509 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 510 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 511 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 512 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 513 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 514 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 515 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 516 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 517 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 518 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 519 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, 520 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, 521 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, 522 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000}, 523 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 524 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 525 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 526 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, 527 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, 528 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, 529 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 530 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 531 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 532 {}, 533 }; 534 535 const struct adreno_reglist a650_hwcg[] = { 536 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, 537 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, 538 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 539 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, 540 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, 541 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 542 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 543 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 544 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 545 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 546 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 547 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 548 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 549 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 550 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 551 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 552 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 553 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, 554 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 555 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, 556 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022}, 557 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 558 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 559 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 560 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 561 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 562 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 563 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 564 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 565 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 566 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 567 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 568 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 569 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 570 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 571 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 572 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, 573 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, 574 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, 575 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777}, 576 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 577 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 578 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 579 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, 580 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, 581 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, 582 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 583 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 584 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 585 {}, 586 }; 587 588 const struct adreno_reglist a660_hwcg[] = { 589 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, 590 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, 591 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 592 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, 593 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, 594 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 595 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 596 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 597 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 598 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 599 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 600 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 601 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 602 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 603 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 604 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 605 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 606 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, 607 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 608 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, 609 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022}, 610 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 611 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 612 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 613 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 614 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 615 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 616 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 617 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 618 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 619 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 620 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 621 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 622 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 623 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 624 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 625 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, 626 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, 627 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, 628 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000}, 629 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 630 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 631 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 632 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, 633 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, 634 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, 635 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 636 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 637 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 638 {}, 639 }; 640 641 const struct adreno_reglist a690_hwcg[] = { 642 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, 643 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, 644 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 645 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, 646 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, 647 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 648 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 649 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 650 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 651 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 652 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 653 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 654 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 655 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 656 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 657 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 658 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 659 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, 660 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 661 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, 662 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022}, 663 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 664 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 665 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 666 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 667 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 668 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 669 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 670 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 671 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 672 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 673 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 674 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 675 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 676 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 677 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 678 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, 679 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, 680 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, 681 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000}, 682 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 683 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 684 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 685 {REG_A6XX_RBBM_CLOCK_CNTL, 0x8AA8AA82}, 686 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, 687 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, 688 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, 689 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 690 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 691 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 692 {REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 0x20200}, 693 {REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111}, 694 {REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555}, 695 {} 696 }; 697 698 static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) 699 { 700 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 701 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 702 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 703 const struct adreno_reglist *reg; 704 unsigned int i; 705 u32 val, clock_cntl_on; 706 707 if (!adreno_gpu->info->hwcg) 708 return; 709 710 if (adreno_is_a630(adreno_gpu)) 711 clock_cntl_on = 0x8aa8aa02; 712 else if (adreno_is_a610(adreno_gpu)) 713 clock_cntl_on = 0xaaa8aa82; 714 else 715 clock_cntl_on = 0x8aa8aa82; 716 717 val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL); 718 719 /* Don't re-program the registers if they are already correct */ 720 if ((!state && !val) || (state && (val == clock_cntl_on))) 721 return; 722 723 /* Disable SP clock before programming HWCG registers */ 724 if (!adreno_is_a610(adreno_gpu)) 725 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); 726 727 for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++) 728 gpu_write(gpu, reg->offset, state ? reg->value : 0); 729 730 /* Enable SP clock */ 731 if (!adreno_is_a610(adreno_gpu)) 732 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); 733 734 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); 735 } 736 737 /* For a615, a616, a618, a619, a630, a640 and a680 */ 738 static const u32 a6xx_protect[] = { 739 A6XX_PROTECT_RDONLY(0x00000, 0x04ff), 740 A6XX_PROTECT_RDONLY(0x00501, 0x0005), 741 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4), 742 A6XX_PROTECT_NORDWR(0x0050e, 0x0000), 743 A6XX_PROTECT_NORDWR(0x00510, 0x0000), 744 A6XX_PROTECT_NORDWR(0x00534, 0x0000), 745 A6XX_PROTECT_NORDWR(0x00800, 0x0082), 746 A6XX_PROTECT_NORDWR(0x008a0, 0x0008), 747 A6XX_PROTECT_NORDWR(0x008ab, 0x0024), 748 A6XX_PROTECT_RDONLY(0x008de, 0x00ae), 749 A6XX_PROTECT_NORDWR(0x00900, 0x004d), 750 A6XX_PROTECT_NORDWR(0x0098d, 0x0272), 751 A6XX_PROTECT_NORDWR(0x00e00, 0x0001), 752 A6XX_PROTECT_NORDWR(0x00e03, 0x000c), 753 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3), 754 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff), 755 A6XX_PROTECT_NORDWR(0x08630, 0x01cf), 756 A6XX_PROTECT_NORDWR(0x08e00, 0x0000), 757 A6XX_PROTECT_NORDWR(0x08e08, 0x0000), 758 A6XX_PROTECT_NORDWR(0x08e50, 0x001f), 759 A6XX_PROTECT_NORDWR(0x09624, 0x01db), 760 A6XX_PROTECT_NORDWR(0x09e70, 0x0001), 761 A6XX_PROTECT_NORDWR(0x09e78, 0x0187), 762 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf), 763 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000), 764 A6XX_PROTECT_NORDWR(0x0ae50, 0x032f), 765 A6XX_PROTECT_NORDWR(0x0b604, 0x0000), 766 A6XX_PROTECT_NORDWR(0x0be02, 0x0001), 767 A6XX_PROTECT_NORDWR(0x0be20, 0x17df), 768 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff), 769 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), 770 A6XX_PROTECT_NORDWR(0x11c00, 0x0000), /* note: infinite range */ 771 }; 772 773 /* These are for a620 and a650 */ 774 static const u32 a650_protect[] = { 775 A6XX_PROTECT_RDONLY(0x00000, 0x04ff), 776 A6XX_PROTECT_RDONLY(0x00501, 0x0005), 777 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4), 778 A6XX_PROTECT_NORDWR(0x0050e, 0x0000), 779 A6XX_PROTECT_NORDWR(0x00510, 0x0000), 780 A6XX_PROTECT_NORDWR(0x00534, 0x0000), 781 A6XX_PROTECT_NORDWR(0x00800, 0x0082), 782 A6XX_PROTECT_NORDWR(0x008a0, 0x0008), 783 A6XX_PROTECT_NORDWR(0x008ab, 0x0024), 784 A6XX_PROTECT_RDONLY(0x008de, 0x00ae), 785 A6XX_PROTECT_NORDWR(0x00900, 0x004d), 786 A6XX_PROTECT_NORDWR(0x0098d, 0x0272), 787 A6XX_PROTECT_NORDWR(0x00e00, 0x0001), 788 A6XX_PROTECT_NORDWR(0x00e03, 0x000c), 789 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3), 790 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff), 791 A6XX_PROTECT_NORDWR(0x08630, 0x01cf), 792 A6XX_PROTECT_NORDWR(0x08e00, 0x0000), 793 A6XX_PROTECT_NORDWR(0x08e08, 0x0000), 794 A6XX_PROTECT_NORDWR(0x08e50, 0x001f), 795 A6XX_PROTECT_NORDWR(0x08e80, 0x027f), 796 A6XX_PROTECT_NORDWR(0x09624, 0x01db), 797 A6XX_PROTECT_NORDWR(0x09e60, 0x0011), 798 A6XX_PROTECT_NORDWR(0x09e78, 0x0187), 799 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf), 800 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000), 801 A6XX_PROTECT_NORDWR(0x0ae50, 0x032f), 802 A6XX_PROTECT_NORDWR(0x0b604, 0x0000), 803 A6XX_PROTECT_NORDWR(0x0b608, 0x0007), 804 A6XX_PROTECT_NORDWR(0x0be02, 0x0001), 805 A6XX_PROTECT_NORDWR(0x0be20, 0x17df), 806 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff), 807 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), 808 A6XX_PROTECT_NORDWR(0x18400, 0x1fff), 809 A6XX_PROTECT_NORDWR(0x1a800, 0x1fff), 810 A6XX_PROTECT_NORDWR(0x1f400, 0x0443), 811 A6XX_PROTECT_RDONLY(0x1f844, 0x007b), 812 A6XX_PROTECT_NORDWR(0x1f887, 0x001b), 813 A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */ 814 }; 815 816 /* These are for a635 and a660 */ 817 static const u32 a660_protect[] = { 818 A6XX_PROTECT_RDONLY(0x00000, 0x04ff), 819 A6XX_PROTECT_RDONLY(0x00501, 0x0005), 820 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4), 821 A6XX_PROTECT_NORDWR(0x0050e, 0x0000), 822 A6XX_PROTECT_NORDWR(0x00510, 0x0000), 823 A6XX_PROTECT_NORDWR(0x00534, 0x0000), 824 A6XX_PROTECT_NORDWR(0x00800, 0x0082), 825 A6XX_PROTECT_NORDWR(0x008a0, 0x0008), 826 A6XX_PROTECT_NORDWR(0x008ab, 0x0024), 827 A6XX_PROTECT_RDONLY(0x008de, 0x00ae), 828 A6XX_PROTECT_NORDWR(0x00900, 0x004d), 829 A6XX_PROTECT_NORDWR(0x0098d, 0x0272), 830 A6XX_PROTECT_NORDWR(0x00e00, 0x0001), 831 A6XX_PROTECT_NORDWR(0x00e03, 0x000c), 832 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3), 833 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff), 834 A6XX_PROTECT_NORDWR(0x08630, 0x01cf), 835 A6XX_PROTECT_NORDWR(0x08e00, 0x0000), 836 A6XX_PROTECT_NORDWR(0x08e08, 0x0000), 837 A6XX_PROTECT_NORDWR(0x08e50, 0x001f), 838 A6XX_PROTECT_NORDWR(0x08e80, 0x027f), 839 A6XX_PROTECT_NORDWR(0x09624, 0x01db), 840 A6XX_PROTECT_NORDWR(0x09e60, 0x0011), 841 A6XX_PROTECT_NORDWR(0x09e78, 0x0187), 842 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf), 843 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000), 844 A6XX_PROTECT_NORDWR(0x0ae50, 0x012f), 845 A6XX_PROTECT_NORDWR(0x0b604, 0x0000), 846 A6XX_PROTECT_NORDWR(0x0b608, 0x0006), 847 A6XX_PROTECT_NORDWR(0x0be02, 0x0001), 848 A6XX_PROTECT_NORDWR(0x0be20, 0x015f), 849 A6XX_PROTECT_NORDWR(0x0d000, 0x05ff), 850 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff), 851 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), 852 A6XX_PROTECT_NORDWR(0x18400, 0x1fff), 853 A6XX_PROTECT_NORDWR(0x1a400, 0x1fff), 854 A6XX_PROTECT_NORDWR(0x1f400, 0x0443), 855 A6XX_PROTECT_RDONLY(0x1f844, 0x007b), 856 A6XX_PROTECT_NORDWR(0x1f860, 0x0000), 857 A6XX_PROTECT_NORDWR(0x1f887, 0x001b), 858 A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */ 859 }; 860 861 /* These are for a690 */ 862 static const u32 a690_protect[] = { 863 A6XX_PROTECT_RDONLY(0x00000, 0x004ff), 864 A6XX_PROTECT_RDONLY(0x00501, 0x00001), 865 A6XX_PROTECT_RDONLY(0x0050b, 0x002f4), 866 A6XX_PROTECT_NORDWR(0x0050e, 0x00000), 867 A6XX_PROTECT_NORDWR(0x00510, 0x00000), 868 A6XX_PROTECT_NORDWR(0x00534, 0x00000), 869 A6XX_PROTECT_NORDWR(0x00800, 0x00082), 870 A6XX_PROTECT_NORDWR(0x008a0, 0x00008), 871 A6XX_PROTECT_NORDWR(0x008ab, 0x00024), 872 A6XX_PROTECT_RDONLY(0x008de, 0x000ae), 873 A6XX_PROTECT_NORDWR(0x00900, 0x0004d), 874 A6XX_PROTECT_NORDWR(0x0098d, 0x00272), 875 A6XX_PROTECT_NORDWR(0x00e00, 0x00001), 876 A6XX_PROTECT_NORDWR(0x00e03, 0x0000c), 877 A6XX_PROTECT_NORDWR(0x03c00, 0x000c3), 878 A6XX_PROTECT_RDONLY(0x03cc4, 0x01fff), 879 A6XX_PROTECT_NORDWR(0x08630, 0x001cf), 880 A6XX_PROTECT_NORDWR(0x08e00, 0x00000), 881 A6XX_PROTECT_NORDWR(0x08e08, 0x00007), 882 A6XX_PROTECT_NORDWR(0x08e50, 0x0001f), 883 A6XX_PROTECT_NORDWR(0x08e80, 0x0027f), 884 A6XX_PROTECT_NORDWR(0x09624, 0x001db), 885 A6XX_PROTECT_NORDWR(0x09e60, 0x00011), 886 A6XX_PROTECT_NORDWR(0x09e78, 0x00187), 887 A6XX_PROTECT_NORDWR(0x0a630, 0x001cf), 888 A6XX_PROTECT_NORDWR(0x0ae02, 0x00000), 889 A6XX_PROTECT_NORDWR(0x0ae50, 0x0012f), 890 A6XX_PROTECT_NORDWR(0x0b604, 0x00000), 891 A6XX_PROTECT_NORDWR(0x0b608, 0x00006), 892 A6XX_PROTECT_NORDWR(0x0be02, 0x00001), 893 A6XX_PROTECT_NORDWR(0x0be20, 0x0015f), 894 A6XX_PROTECT_NORDWR(0x0d000, 0x005ff), 895 A6XX_PROTECT_NORDWR(0x0f000, 0x00bff), 896 A6XX_PROTECT_RDONLY(0x0fc00, 0x01fff), 897 A6XX_PROTECT_NORDWR(0x11c00, 0x00000), /*note: infiite range */ 898 }; 899 900 static void a6xx_set_cp_protect(struct msm_gpu *gpu) 901 { 902 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 903 const u32 *regs = a6xx_protect; 904 unsigned i, count, count_max; 905 906 if (adreno_is_a650(adreno_gpu)) { 907 regs = a650_protect; 908 count = ARRAY_SIZE(a650_protect); 909 count_max = 48; 910 BUILD_BUG_ON(ARRAY_SIZE(a650_protect) > 48); 911 } else if (adreno_is_a690(adreno_gpu)) { 912 regs = a690_protect; 913 count = ARRAY_SIZE(a690_protect); 914 count_max = 48; 915 BUILD_BUG_ON(ARRAY_SIZE(a690_protect) > 48); 916 } else if (adreno_is_a660_family(adreno_gpu)) { 917 regs = a660_protect; 918 count = ARRAY_SIZE(a660_protect); 919 count_max = 48; 920 BUILD_BUG_ON(ARRAY_SIZE(a660_protect) > 48); 921 } else { 922 regs = a6xx_protect; 923 count = ARRAY_SIZE(a6xx_protect); 924 count_max = 32; 925 BUILD_BUG_ON(ARRAY_SIZE(a6xx_protect) > 32); 926 } 927 928 /* 929 * Enable access protection to privileged registers, fault on an access 930 * protect violation and select the last span to protect from the start 931 * address all the way to the end of the register address space 932 */ 933 gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, BIT(0) | BIT(1) | BIT(3)); 934 935 for (i = 0; i < count - 1; i++) 936 gpu_write(gpu, REG_A6XX_CP_PROTECT(i), regs[i]); 937 /* last CP_PROTECT to have "infinite" length on the last entry */ 938 gpu_write(gpu, REG_A6XX_CP_PROTECT(count_max - 1), regs[i]); 939 } 940 941 static void a6xx_set_ubwc_config(struct msm_gpu *gpu) 942 { 943 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 944 /* Unknown, introduced with A650 family, related to UBWC mode/ver 4 */ 945 u32 rgb565_predicator = 0; 946 /* Unknown, introduced with A650 family */ 947 u32 uavflagprd_inv = 0; 948 /* Whether the minimum access length is 64 bits */ 949 u32 min_acc_len = 0; 950 /* Entirely magic, per-GPU-gen value */ 951 u32 ubwc_mode = 0; 952 /* 953 * The Highest Bank Bit value represents the bit of the highest DDR bank. 954 * We then subtract 13 from it (13 is the minimum value allowed by hw) and 955 * write the lowest two bits of the remaining value as hbb_lo and the 956 * one above it as hbb_hi to the hardware. This should ideally use DRAM 957 * type detection. 958 */ 959 u32 hbb_hi = 0; 960 u32 hbb_lo = 2; 961 /* Unknown, introduced with A640/680 */ 962 u32 amsbc = 0; 963 964 if (adreno_is_a610(adreno_gpu)) { 965 /* HBB = 14 */ 966 hbb_lo = 1; 967 min_acc_len = 1; 968 ubwc_mode = 1; 969 } 970 971 /* a618 is using the hw default values */ 972 if (adreno_is_a618(adreno_gpu)) 973 return; 974 975 if (adreno_is_a619_holi(adreno_gpu)) 976 hbb_lo = 0; 977 978 if (adreno_is_a640_family(adreno_gpu)) 979 amsbc = 1; 980 981 if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) { 982 /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ 983 hbb_lo = 3; 984 amsbc = 1; 985 rgb565_predicator = 1; 986 uavflagprd_inv = 2; 987 } 988 989 if (adreno_is_a690(adreno_gpu)) { 990 hbb_lo = 2; 991 amsbc = 1; 992 rgb565_predicator = 1; 993 uavflagprd_inv = 2; 994 } 995 996 if (adreno_is_7c3(adreno_gpu)) { 997 hbb_lo = 1; 998 amsbc = 1; 999 rgb565_predicator = 1; 1000 uavflagprd_inv = 2; 1001 } 1002 1003 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 1004 rgb565_predicator << 11 | hbb_hi << 10 | amsbc << 4 | 1005 min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); 1006 1007 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, hbb_hi << 4 | 1008 min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); 1009 1010 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, hbb_hi << 10 | 1011 uavflagprd_inv << 4 | min_acc_len << 3 | 1012 hbb_lo << 1 | ubwc_mode); 1013 1014 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, min_acc_len << 23 | hbb_lo << 21); 1015 } 1016 1017 static int a6xx_cp_init(struct msm_gpu *gpu) 1018 { 1019 struct msm_ringbuffer *ring = gpu->rb[0]; 1020 1021 OUT_PKT7(ring, CP_ME_INIT, 8); 1022 1023 OUT_RING(ring, 0x0000002f); 1024 1025 /* Enable multiple hardware contexts */ 1026 OUT_RING(ring, 0x00000003); 1027 1028 /* Enable error detection */ 1029 OUT_RING(ring, 0x20000000); 1030 1031 /* Don't enable header dump */ 1032 OUT_RING(ring, 0x00000000); 1033 OUT_RING(ring, 0x00000000); 1034 1035 /* No workarounds enabled */ 1036 OUT_RING(ring, 0x00000000); 1037 1038 /* Pad rest of the cmds with 0's */ 1039 OUT_RING(ring, 0x00000000); 1040 OUT_RING(ring, 0x00000000); 1041 1042 a6xx_flush(gpu, ring); 1043 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; 1044 } 1045 1046 /* 1047 * Check that the microcode version is new enough to include several key 1048 * security fixes. Return true if the ucode is safe. 1049 */ 1050 static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu, 1051 struct drm_gem_object *obj) 1052 { 1053 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1054 struct msm_gpu *gpu = &adreno_gpu->base; 1055 const char *sqe_name = adreno_gpu->info->fw[ADRENO_FW_SQE]; 1056 u32 *buf = msm_gem_get_vaddr(obj); 1057 bool ret = false; 1058 1059 if (IS_ERR(buf)) 1060 return false; 1061 1062 /* 1063 * Targets up to a640 (a618, a630 and a640) need to check for a 1064 * microcode version that is patched to support the whereami opcode or 1065 * one that is new enough to include it by default. 1066 * 1067 * a650 tier targets don't need whereami but still need to be 1068 * equal to or newer than 0.95 for other security fixes 1069 * 1070 * a660 targets have all the critical security fixes from the start 1071 */ 1072 if (!strcmp(sqe_name, "a630_sqe.fw")) { 1073 /* 1074 * If the lowest nibble is 0xa that is an indication that this 1075 * microcode has been patched. The actual version is in dword 1076 * [3] but we only care about the patchlevel which is the lowest 1077 * nibble of dword [3] 1078 * 1079 * Otherwise check that the firmware is greater than or equal 1080 * to 1.90 which was the first version that had this fix built 1081 * in 1082 */ 1083 if ((((buf[0] & 0xf) == 0xa) && (buf[2] & 0xf) >= 1) || 1084 (buf[0] & 0xfff) >= 0x190) { 1085 a6xx_gpu->has_whereami = true; 1086 ret = true; 1087 goto out; 1088 } 1089 1090 DRM_DEV_ERROR(&gpu->pdev->dev, 1091 "a630 SQE ucode is too old. Have version %x need at least %x\n", 1092 buf[0] & 0xfff, 0x190); 1093 } else if (!strcmp(sqe_name, "a650_sqe.fw")) { 1094 if ((buf[0] & 0xfff) >= 0x095) { 1095 ret = true; 1096 goto out; 1097 } 1098 1099 DRM_DEV_ERROR(&gpu->pdev->dev, 1100 "a650 SQE ucode is too old. Have version %x need at least %x\n", 1101 buf[0] & 0xfff, 0x095); 1102 } else if (!strcmp(sqe_name, "a660_sqe.fw")) { 1103 ret = true; 1104 } else { 1105 DRM_DEV_ERROR(&gpu->pdev->dev, 1106 "unknown GPU, add it to a6xx_ucode_check_version()!!\n"); 1107 } 1108 out: 1109 msm_gem_put_vaddr(obj); 1110 return ret; 1111 } 1112 1113 static int a6xx_ucode_load(struct msm_gpu *gpu) 1114 { 1115 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1116 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1117 1118 if (!a6xx_gpu->sqe_bo) { 1119 a6xx_gpu->sqe_bo = adreno_fw_create_bo(gpu, 1120 adreno_gpu->fw[ADRENO_FW_SQE], &a6xx_gpu->sqe_iova); 1121 1122 if (IS_ERR(a6xx_gpu->sqe_bo)) { 1123 int ret = PTR_ERR(a6xx_gpu->sqe_bo); 1124 1125 a6xx_gpu->sqe_bo = NULL; 1126 DRM_DEV_ERROR(&gpu->pdev->dev, 1127 "Could not allocate SQE ucode: %d\n", ret); 1128 1129 return ret; 1130 } 1131 1132 msm_gem_object_set_name(a6xx_gpu->sqe_bo, "sqefw"); 1133 if (!a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->sqe_bo)) { 1134 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace); 1135 drm_gem_object_put(a6xx_gpu->sqe_bo); 1136 1137 a6xx_gpu->sqe_bo = NULL; 1138 return -EPERM; 1139 } 1140 } 1141 1142 /* 1143 * Expanded APRIV and targets that support WHERE_AM_I both need a 1144 * privileged buffer to store the RPTR shadow 1145 */ 1146 if ((adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) && 1147 !a6xx_gpu->shadow_bo) { 1148 a6xx_gpu->shadow = msm_gem_kernel_new(gpu->dev, 1149 sizeof(u32) * gpu->nr_rings, 1150 MSM_BO_WC | MSM_BO_MAP_PRIV, 1151 gpu->aspace, &a6xx_gpu->shadow_bo, 1152 &a6xx_gpu->shadow_iova); 1153 1154 if (IS_ERR(a6xx_gpu->shadow)) 1155 return PTR_ERR(a6xx_gpu->shadow); 1156 1157 msm_gem_object_set_name(a6xx_gpu->shadow_bo, "shadow"); 1158 } 1159 1160 return 0; 1161 } 1162 1163 static int a6xx_zap_shader_init(struct msm_gpu *gpu) 1164 { 1165 static bool loaded; 1166 int ret; 1167 1168 if (loaded) 1169 return 0; 1170 1171 ret = adreno_zap_shader_load(gpu, GPU_PAS_ID); 1172 1173 loaded = !ret; 1174 return ret; 1175 } 1176 1177 #define A6XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \ 1178 A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \ 1179 A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \ 1180 A6XX_RBBM_INT_0_MASK_CP_IB2 | \ 1181 A6XX_RBBM_INT_0_MASK_CP_IB1 | \ 1182 A6XX_RBBM_INT_0_MASK_CP_RB | \ 1183 A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \ 1184 A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \ 1185 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \ 1186 A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \ 1187 A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR) 1188 1189 static int hw_init(struct msm_gpu *gpu) 1190 { 1191 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1192 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1193 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1194 int ret; 1195 1196 if (!adreno_has_gmu_wrapper(adreno_gpu)) { 1197 /* Make sure the GMU keeps the GPU on while we set it up */ 1198 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 1199 } 1200 1201 /* Clear GBIF halt in case GX domain was not collapsed */ 1202 if (adreno_is_a619_holi(adreno_gpu)) { 1203 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); 1204 gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, 0); 1205 /* Let's make extra sure that the GPU can access the memory.. */ 1206 mb(); 1207 } else if (a6xx_has_gbif(adreno_gpu)) { 1208 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); 1209 gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); 1210 /* Let's make extra sure that the GPU can access the memory.. */ 1211 mb(); 1212 } 1213 1214 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); 1215 1216 if (adreno_is_a619_holi(adreno_gpu)) 1217 a6xx_sptprac_enable(gmu); 1218 1219 /* 1220 * Disable the trusted memory range - we don't actually supported secure 1221 * memory rendering at this point in time and we don't want to block off 1222 * part of the virtual memory space. 1223 */ 1224 gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE, 0x00000000); 1225 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); 1226 1227 /* Turn on 64 bit addressing for all blocks */ 1228 gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1); 1229 gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1); 1230 gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1); 1231 gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1); 1232 gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1); 1233 gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1); 1234 gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1); 1235 gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1); 1236 gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1); 1237 gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1); 1238 gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1); 1239 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1); 1240 1241 /* enable hardware clockgating */ 1242 a6xx_set_hwcg(gpu, true); 1243 1244 /* VBIF/GBIF start*/ 1245 if (adreno_is_a610(adreno_gpu) || 1246 adreno_is_a640_family(adreno_gpu) || 1247 adreno_is_a650_family(adreno_gpu)) { 1248 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); 1249 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); 1250 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); 1251 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); 1252 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3); 1253 } else { 1254 gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3); 1255 } 1256 1257 if (adreno_is_a630(adreno_gpu)) 1258 gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009); 1259 1260 /* Make all blocks contribute to the GPU BUSY perf counter */ 1261 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff); 1262 1263 /* Disable L2 bypass in the UCHE */ 1264 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX, 0x0001ffffffffffc0llu); 1265 gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE, 0x0001fffffffff000llu); 1266 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, 0x0001fffffffff000llu); 1267 1268 if (!adreno_is_a650_family(adreno_gpu)) { 1269 /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */ 1270 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN, 0x00100000); 1271 1272 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX, 1273 0x00100000 + adreno_gpu->gmem - 1); 1274 } 1275 1276 gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804); 1277 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4); 1278 1279 if (adreno_is_a640_family(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) { 1280 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); 1281 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); 1282 } else if (adreno_is_a610(adreno_gpu)) { 1283 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x00800060); 1284 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x40201b16); 1285 } else { 1286 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0); 1287 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); 1288 } 1289 1290 if (adreno_is_a660_family(adreno_gpu)) 1291 gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); 1292 1293 /* Setting the mem pool size */ 1294 if (adreno_is_a610(adreno_gpu)) { 1295 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 48); 1296 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 47); 1297 } else 1298 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); 1299 1300 /* Setting the primFifo thresholds default values, 1301 * and vccCacheSkipDis=1 bit (0x200) for A640 and newer 1302 */ 1303 if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu) || adreno_is_a690(adreno_gpu)) 1304 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200); 1305 else if (adreno_is_a640_family(adreno_gpu) || adreno_is_7c3(adreno_gpu)) 1306 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200); 1307 else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) 1308 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200); 1309 else if (adreno_is_a619(adreno_gpu)) 1310 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00018000); 1311 else if (adreno_is_a610(adreno_gpu)) 1312 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00080000); 1313 else 1314 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00180000); 1315 1316 /* Set the AHB default slave response to "ERROR" */ 1317 gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1); 1318 1319 /* Turn on performance counters */ 1320 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1); 1321 1322 /* Select CP0 to always count cycles */ 1323 gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL(0), PERF_CP_ALWAYS_COUNT); 1324 1325 a6xx_set_ubwc_config(gpu); 1326 1327 /* Enable fault detection */ 1328 if (adreno_is_a619(adreno_gpu)) 1329 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fffff); 1330 else if (adreno_is_a610(adreno_gpu)) 1331 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3ffff); 1332 else 1333 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fffff); 1334 1335 gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1); 1336 1337 /* Set weights for bicubic filtering */ 1338 if (adreno_is_a650_family(adreno_gpu)) { 1339 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0); 1340 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, 1341 0x3fe05ff4); 1342 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2, 1343 0x3fa0ebee); 1344 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3, 1345 0x3f5193ed); 1346 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4, 1347 0x3f0243f0); 1348 } 1349 1350 /* Set up the CX GMU counter 0 to count busy ticks */ 1351 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); 1352 1353 /* Enable the power counter */ 1354 gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, BIT(5)); 1355 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); 1356 1357 /* Protect registers from the CP */ 1358 a6xx_set_cp_protect(gpu); 1359 1360 if (adreno_is_a660_family(adreno_gpu)) { 1361 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1); 1362 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0); 1363 } 1364 1365 /* Set dualQ + disable afull for A660 GPU */ 1366 if (adreno_is_a660(adreno_gpu)) 1367 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x66906); 1368 1369 /* Enable expanded apriv for targets that support it */ 1370 if (gpu->hw_apriv) { 1371 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL, 1372 (1 << 6) | (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1)); 1373 } 1374 1375 /* Enable interrupts */ 1376 gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, A6XX_INT_MASK); 1377 1378 ret = adreno_hw_init(gpu); 1379 if (ret) 1380 goto out; 1381 1382 gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE, a6xx_gpu->sqe_iova); 1383 1384 /* Set the ringbuffer address */ 1385 gpu_write64(gpu, REG_A6XX_CP_RB_BASE, gpu->rb[0]->iova); 1386 1387 /* Targets that support extended APRIV can use the RPTR shadow from 1388 * hardware but all the other ones need to disable the feature. Targets 1389 * that support the WHERE_AM_I opcode can use that instead 1390 */ 1391 if (adreno_gpu->base.hw_apriv) 1392 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT); 1393 else 1394 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, 1395 MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE); 1396 1397 /* Configure the RPTR shadow if needed: */ 1398 if (a6xx_gpu->shadow_bo) { 1399 gpu_write64(gpu, REG_A6XX_CP_RB_RPTR_ADDR, 1400 shadowptr(a6xx_gpu, gpu->rb[0])); 1401 } 1402 1403 /* Always come up on rb 0 */ 1404 a6xx_gpu->cur_ring = gpu->rb[0]; 1405 1406 gpu->cur_ctx_seqno = 0; 1407 1408 /* Enable the SQE_to start the CP engine */ 1409 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1); 1410 1411 ret = a6xx_cp_init(gpu); 1412 if (ret) 1413 goto out; 1414 1415 /* 1416 * Try to load a zap shader into the secure world. If successful 1417 * we can use the CP to switch out of secure mode. If not then we 1418 * have no resource but to try to switch ourselves out manually. If we 1419 * guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will 1420 * be blocked and a permissions violation will soon follow. 1421 */ 1422 ret = a6xx_zap_shader_init(gpu); 1423 if (!ret) { 1424 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1); 1425 OUT_RING(gpu->rb[0], 0x00000000); 1426 1427 a6xx_flush(gpu, gpu->rb[0]); 1428 if (!a6xx_idle(gpu, gpu->rb[0])) 1429 return -EINVAL; 1430 } else if (ret == -ENODEV) { 1431 /* 1432 * This device does not use zap shader (but print a warning 1433 * just in case someone got their dt wrong.. hopefully they 1434 * have a debug UART to realize the error of their ways... 1435 * if you mess this up you are about to crash horribly) 1436 */ 1437 dev_warn_once(gpu->dev->dev, 1438 "Zap shader not enabled - using SECVID_TRUST_CNTL instead\n"); 1439 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0); 1440 ret = 0; 1441 } else { 1442 return ret; 1443 } 1444 1445 out: 1446 if (adreno_has_gmu_wrapper(adreno_gpu)) 1447 return ret; 1448 /* 1449 * Tell the GMU that we are done touching the GPU and it can start power 1450 * management 1451 */ 1452 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 1453 1454 if (a6xx_gpu->gmu.legacy) { 1455 /* Take the GMU out of its special boot mode */ 1456 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER); 1457 } 1458 1459 return ret; 1460 } 1461 1462 static int a6xx_hw_init(struct msm_gpu *gpu) 1463 { 1464 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1465 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1466 int ret; 1467 1468 mutex_lock(&a6xx_gpu->gmu.lock); 1469 ret = hw_init(gpu); 1470 mutex_unlock(&a6xx_gpu->gmu.lock); 1471 1472 return ret; 1473 } 1474 1475 static void a6xx_dump(struct msm_gpu *gpu) 1476 { 1477 DRM_DEV_INFO(&gpu->pdev->dev, "status: %08x\n", 1478 gpu_read(gpu, REG_A6XX_RBBM_STATUS)); 1479 adreno_dump(gpu); 1480 } 1481 1482 static void a6xx_recover(struct msm_gpu *gpu) 1483 { 1484 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1485 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1486 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1487 int i, active_submits; 1488 1489 adreno_dump_info(gpu); 1490 1491 for (i = 0; i < 8; i++) 1492 DRM_DEV_INFO(&gpu->pdev->dev, "CP_SCRATCH_REG%d: %u\n", i, 1493 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i))); 1494 1495 if (hang_debug) 1496 a6xx_dump(gpu); 1497 1498 /* 1499 * To handle recovery specific sequences during the rpm suspend we are 1500 * about to trigger 1501 */ 1502 a6xx_gpu->hung = true; 1503 1504 /* Halt SQE first */ 1505 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 3); 1506 1507 pm_runtime_dont_use_autosuspend(&gpu->pdev->dev); 1508 1509 /* active_submit won't change until we make a submission */ 1510 mutex_lock(&gpu->active_lock); 1511 active_submits = gpu->active_submits; 1512 1513 /* 1514 * Temporarily clear active_submits count to silence a WARN() in the 1515 * runtime suspend cb 1516 */ 1517 gpu->active_submits = 0; 1518 1519 if (adreno_has_gmu_wrapper(adreno_gpu)) { 1520 /* Drain the outstanding traffic on memory buses */ 1521 a6xx_bus_clear_pending_transactions(adreno_gpu, true); 1522 1523 /* Reset the GPU to a clean state */ 1524 a6xx_gpu_sw_reset(gpu, true); 1525 a6xx_gpu_sw_reset(gpu, false); 1526 } 1527 1528 reinit_completion(&gmu->pd_gate); 1529 dev_pm_genpd_add_notifier(gmu->cxpd, &gmu->pd_nb); 1530 dev_pm_genpd_synced_poweroff(gmu->cxpd); 1531 1532 /* Drop the rpm refcount from active submits */ 1533 if (active_submits) 1534 pm_runtime_put(&gpu->pdev->dev); 1535 1536 /* And the final one from recover worker */ 1537 pm_runtime_put_sync(&gpu->pdev->dev); 1538 1539 if (!wait_for_completion_timeout(&gmu->pd_gate, msecs_to_jiffies(1000))) 1540 DRM_DEV_ERROR(&gpu->pdev->dev, "cx gdsc didn't collapse\n"); 1541 1542 dev_pm_genpd_remove_notifier(gmu->cxpd); 1543 1544 pm_runtime_use_autosuspend(&gpu->pdev->dev); 1545 1546 if (active_submits) 1547 pm_runtime_get(&gpu->pdev->dev); 1548 1549 pm_runtime_get_sync(&gpu->pdev->dev); 1550 1551 gpu->active_submits = active_submits; 1552 mutex_unlock(&gpu->active_lock); 1553 1554 msm_gpu_hw_init(gpu); 1555 a6xx_gpu->hung = false; 1556 } 1557 1558 static const char *a6xx_uche_fault_block(struct msm_gpu *gpu, u32 mid) 1559 { 1560 static const char *uche_clients[7] = { 1561 "VFD", "SP", "VSC", "VPC", "HLSQ", "PC", "LRZ", 1562 }; 1563 u32 val; 1564 1565 if (mid < 1 || mid > 3) 1566 return "UNKNOWN"; 1567 1568 /* 1569 * The source of the data depends on the mid ID read from FSYNR1. 1570 * and the client ID read from the UCHE block 1571 */ 1572 val = gpu_read(gpu, REG_A6XX_UCHE_CLIENT_PF); 1573 1574 /* mid = 3 is most precise and refers to only one block per client */ 1575 if (mid == 3) 1576 return uche_clients[val & 7]; 1577 1578 /* For mid=2 the source is TP or VFD except when the client id is 0 */ 1579 if (mid == 2) 1580 return ((val & 7) == 0) ? "TP" : "TP|VFD"; 1581 1582 /* For mid=1 just return "UCHE" as a catchall for everything else */ 1583 return "UCHE"; 1584 } 1585 1586 static const char *a6xx_fault_block(struct msm_gpu *gpu, u32 id) 1587 { 1588 if (id == 0) 1589 return "CP"; 1590 else if (id == 4) 1591 return "CCU"; 1592 else if (id == 6) 1593 return "CDP Prefetch"; 1594 1595 return a6xx_uche_fault_block(gpu, id); 1596 } 1597 1598 static int a6xx_fault_handler(void *arg, unsigned long iova, int flags, void *data) 1599 { 1600 struct msm_gpu *gpu = arg; 1601 struct adreno_smmu_fault_info *info = data; 1602 const char *block = "unknown"; 1603 1604 u32 scratch[] = { 1605 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)), 1606 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)), 1607 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)), 1608 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)), 1609 }; 1610 1611 if (info) 1612 block = a6xx_fault_block(gpu, info->fsynr1 & 0xff); 1613 1614 return adreno_fault_handler(gpu, iova, flags, info, block, scratch); 1615 } 1616 1617 static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu) 1618 { 1619 u32 status = gpu_read(gpu, REG_A6XX_CP_INTERRUPT_STATUS); 1620 1621 if (status & A6XX_CP_INT_CP_OPCODE_ERROR) { 1622 u32 val; 1623 1624 gpu_write(gpu, REG_A6XX_CP_SQE_STAT_ADDR, 1); 1625 val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA); 1626 dev_err_ratelimited(&gpu->pdev->dev, 1627 "CP | opcode error | possible opcode=0x%8.8X\n", 1628 val); 1629 } 1630 1631 if (status & A6XX_CP_INT_CP_UCODE_ERROR) 1632 dev_err_ratelimited(&gpu->pdev->dev, 1633 "CP ucode error interrupt\n"); 1634 1635 if (status & A6XX_CP_INT_CP_HW_FAULT_ERROR) 1636 dev_err_ratelimited(&gpu->pdev->dev, "CP | HW fault | status=0x%8.8X\n", 1637 gpu_read(gpu, REG_A6XX_CP_HW_FAULT)); 1638 1639 if (status & A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR) { 1640 u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS); 1641 1642 dev_err_ratelimited(&gpu->pdev->dev, 1643 "CP | protected mode error | %s | addr=0x%8.8X | status=0x%8.8X\n", 1644 val & (1 << 20) ? "READ" : "WRITE", 1645 (val & 0x3ffff), val); 1646 } 1647 1648 if (status & A6XX_CP_INT_CP_AHB_ERROR) 1649 dev_err_ratelimited(&gpu->pdev->dev, "CP AHB error interrupt\n"); 1650 1651 if (status & A6XX_CP_INT_CP_VSD_PARITY_ERROR) 1652 dev_err_ratelimited(&gpu->pdev->dev, "CP VSD decoder parity error\n"); 1653 1654 if (status & A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR) 1655 dev_err_ratelimited(&gpu->pdev->dev, "CP illegal instruction error\n"); 1656 1657 } 1658 1659 static void a6xx_fault_detect_irq(struct msm_gpu *gpu) 1660 { 1661 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1662 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1663 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); 1664 1665 /* 1666 * If stalled on SMMU fault, we could trip the GPU's hang detection, 1667 * but the fault handler will trigger the devcore dump, and we want 1668 * to otherwise resume normally rather than killing the submit, so 1669 * just bail. 1670 */ 1671 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS3) & A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT) 1672 return; 1673 1674 /* 1675 * Force the GPU to stay on until after we finish 1676 * collecting information 1677 */ 1678 if (!adreno_has_gmu_wrapper(adreno_gpu)) 1679 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1); 1680 1681 DRM_DEV_ERROR(&gpu->pdev->dev, 1682 "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n", 1683 ring ? ring->id : -1, ring ? ring->fctx->last_fence : 0, 1684 gpu_read(gpu, REG_A6XX_RBBM_STATUS), 1685 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), 1686 gpu_read(gpu, REG_A6XX_CP_RB_WPTR), 1687 gpu_read64(gpu, REG_A6XX_CP_IB1_BASE), 1688 gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE), 1689 gpu_read64(gpu, REG_A6XX_CP_IB2_BASE), 1690 gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE)); 1691 1692 /* Turn off the hangcheck timer to keep it from bothering us */ 1693 del_timer(&gpu->hangcheck_timer); 1694 1695 kthread_queue_work(gpu->worker, &gpu->recover_work); 1696 } 1697 1698 static irqreturn_t a6xx_irq(struct msm_gpu *gpu) 1699 { 1700 struct msm_drm_private *priv = gpu->dev->dev_private; 1701 u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS); 1702 1703 gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status); 1704 1705 if (priv->disable_err_irq) 1706 status &= A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS; 1707 1708 if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT) 1709 a6xx_fault_detect_irq(gpu); 1710 1711 if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR) 1712 dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n"); 1713 1714 if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR) 1715 a6xx_cp_hw_err_irq(gpu); 1716 1717 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW) 1718 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB ASYNC overflow\n"); 1719 1720 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW) 1721 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB bus overflow\n"); 1722 1723 if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS) 1724 dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n"); 1725 1726 if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) 1727 msm_gpu_retire(gpu); 1728 1729 return IRQ_HANDLED; 1730 } 1731 1732 static void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or) 1733 { 1734 return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or); 1735 } 1736 1737 static void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value) 1738 { 1739 msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2)); 1740 } 1741 1742 static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu) 1743 { 1744 llcc_slice_deactivate(a6xx_gpu->llc_slice); 1745 llcc_slice_deactivate(a6xx_gpu->htw_llc_slice); 1746 } 1747 1748 static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu) 1749 { 1750 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1751 struct msm_gpu *gpu = &adreno_gpu->base; 1752 u32 cntl1_regval = 0; 1753 1754 if (IS_ERR(a6xx_gpu->llc_mmio)) 1755 return; 1756 1757 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { 1758 u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice); 1759 1760 gpu_scid &= 0x1f; 1761 cntl1_regval = (gpu_scid << 0) | (gpu_scid << 5) | (gpu_scid << 10) | 1762 (gpu_scid << 15) | (gpu_scid << 20); 1763 1764 /* On A660, the SCID programming for UCHE traffic is done in 1765 * A6XX_GBIF_SCACHE_CNTL0[14:10] 1766 */ 1767 if (adreno_is_a660_family(adreno_gpu)) 1768 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, (0x1f << 10) | 1769 (1 << 8), (gpu_scid << 10) | (1 << 8)); 1770 } 1771 1772 /* 1773 * For targets with a MMU500, activate the slice but don't program the 1774 * register. The XBL will take care of that. 1775 */ 1776 if (!llcc_slice_activate(a6xx_gpu->htw_llc_slice)) { 1777 if (!a6xx_gpu->have_mmu500) { 1778 u32 gpuhtw_scid = llcc_get_slice_id(a6xx_gpu->htw_llc_slice); 1779 1780 gpuhtw_scid &= 0x1f; 1781 cntl1_regval |= FIELD_PREP(GENMASK(29, 25), gpuhtw_scid); 1782 } 1783 } 1784 1785 if (!cntl1_regval) 1786 return; 1787 1788 /* 1789 * Program the slice IDs for the various GPU blocks and GPU MMU 1790 * pagetables 1791 */ 1792 if (!a6xx_gpu->have_mmu500) { 1793 a6xx_llc_write(a6xx_gpu, 1794 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, cntl1_regval); 1795 1796 /* 1797 * Program cacheability overrides to not allocate cache 1798 * lines on a write miss 1799 */ 1800 a6xx_llc_rmw(a6xx_gpu, 1801 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, 0x03); 1802 return; 1803 } 1804 1805 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, GENMASK(24, 0), cntl1_regval); 1806 } 1807 1808 static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu) 1809 { 1810 /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ 1811 if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) 1812 return; 1813 1814 llcc_slice_putd(a6xx_gpu->llc_slice); 1815 llcc_slice_putd(a6xx_gpu->htw_llc_slice); 1816 } 1817 1818 static void a6xx_llc_slices_init(struct platform_device *pdev, 1819 struct a6xx_gpu *a6xx_gpu) 1820 { 1821 struct device_node *phandle; 1822 1823 /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ 1824 if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) 1825 return; 1826 1827 /* 1828 * There is a different programming path for targets with an mmu500 1829 * attached, so detect if that is the case 1830 */ 1831 phandle = of_parse_phandle(pdev->dev.of_node, "iommus", 0); 1832 a6xx_gpu->have_mmu500 = (phandle && 1833 of_device_is_compatible(phandle, "arm,mmu-500")); 1834 of_node_put(phandle); 1835 1836 if (a6xx_gpu->have_mmu500) 1837 a6xx_gpu->llc_mmio = NULL; 1838 else 1839 a6xx_gpu->llc_mmio = msm_ioremap(pdev, "cx_mem"); 1840 1841 a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU); 1842 a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW); 1843 1844 if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice)) 1845 a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL); 1846 } 1847 1848 #define GBIF_CLIENT_HALT_MASK BIT(0) 1849 #define GBIF_ARB_HALT_MASK BIT(1) 1850 #define VBIF_XIN_HALT_CTRL0_MASK GENMASK(3, 0) 1851 #define VBIF_RESET_ACK_MASK 0xF0 1852 #define GPR0_GBIF_HALT_REQUEST 0x1E0 1853 1854 void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool gx_off) 1855 { 1856 struct msm_gpu *gpu = &adreno_gpu->base; 1857 1858 if (adreno_is_a619_holi(adreno_gpu)) { 1859 gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, GPR0_GBIF_HALT_REQUEST); 1860 spin_until((gpu_read(gpu, REG_A6XX_RBBM_VBIF_GX_RESET_STATUS) & 1861 (VBIF_RESET_ACK_MASK)) == VBIF_RESET_ACK_MASK); 1862 } else if (!a6xx_has_gbif(adreno_gpu)) { 1863 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, VBIF_XIN_HALT_CTRL0_MASK); 1864 spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & 1865 (VBIF_XIN_HALT_CTRL0_MASK)) == VBIF_XIN_HALT_CTRL0_MASK); 1866 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0); 1867 1868 return; 1869 } 1870 1871 if (gx_off) { 1872 /* Halt the gx side of GBIF */ 1873 gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 1); 1874 spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & 1); 1875 } 1876 1877 /* Halt new client requests on GBIF */ 1878 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK); 1879 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 1880 (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK); 1881 1882 /* Halt all AXI requests on GBIF */ 1883 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK); 1884 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) & 1885 (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK); 1886 1887 /* The GBIF halt needs to be explicitly cleared */ 1888 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0); 1889 } 1890 1891 void a6xx_gpu_sw_reset(struct msm_gpu *gpu, bool assert) 1892 { 1893 /* 11nm chips (e.g. ones with A610) have hw issues with the reset line! */ 1894 if (adreno_is_a610(to_adreno_gpu(gpu))) 1895 return; 1896 1897 gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, assert); 1898 /* Perform a bogus read and add a brief delay to ensure ordering. */ 1899 gpu_read(gpu, REG_A6XX_RBBM_SW_RESET_CMD); 1900 udelay(1); 1901 1902 /* The reset line needs to be asserted for at least 100 us */ 1903 if (assert) 1904 udelay(100); 1905 } 1906 1907 static int a6xx_gmu_pm_resume(struct msm_gpu *gpu) 1908 { 1909 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1910 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1911 int ret; 1912 1913 gpu->needs_hw_init = true; 1914 1915 trace_msm_gpu_resume(0); 1916 1917 mutex_lock(&a6xx_gpu->gmu.lock); 1918 ret = a6xx_gmu_resume(a6xx_gpu); 1919 mutex_unlock(&a6xx_gpu->gmu.lock); 1920 if (ret) 1921 return ret; 1922 1923 msm_devfreq_resume(gpu); 1924 1925 a6xx_llc_activate(a6xx_gpu); 1926 1927 return ret; 1928 } 1929 1930 static int a6xx_pm_resume(struct msm_gpu *gpu) 1931 { 1932 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1933 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1934 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 1935 unsigned long freq = gpu->fast_rate; 1936 struct dev_pm_opp *opp; 1937 int ret; 1938 1939 gpu->needs_hw_init = true; 1940 1941 trace_msm_gpu_resume(0); 1942 1943 mutex_lock(&a6xx_gpu->gmu.lock); 1944 1945 opp = dev_pm_opp_find_freq_ceil(&gpu->pdev->dev, &freq); 1946 if (IS_ERR(opp)) { 1947 ret = PTR_ERR(opp); 1948 goto err_set_opp; 1949 } 1950 dev_pm_opp_put(opp); 1951 1952 /* Set the core clock and bus bw, having VDD scaling in mind */ 1953 dev_pm_opp_set_opp(&gpu->pdev->dev, opp); 1954 1955 pm_runtime_resume_and_get(gmu->dev); 1956 pm_runtime_resume_and_get(gmu->gxpd); 1957 1958 ret = clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); 1959 if (ret) 1960 goto err_bulk_clk; 1961 1962 if (adreno_is_a619_holi(adreno_gpu)) 1963 a6xx_sptprac_enable(gmu); 1964 1965 /* If anything goes south, tear the GPU down piece by piece.. */ 1966 if (ret) { 1967 err_bulk_clk: 1968 pm_runtime_put(gmu->gxpd); 1969 pm_runtime_put(gmu->dev); 1970 dev_pm_opp_set_opp(&gpu->pdev->dev, NULL); 1971 } 1972 err_set_opp: 1973 mutex_unlock(&a6xx_gpu->gmu.lock); 1974 1975 if (!ret) 1976 msm_devfreq_resume(gpu); 1977 1978 return ret; 1979 } 1980 1981 static int a6xx_gmu_pm_suspend(struct msm_gpu *gpu) 1982 { 1983 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1984 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1985 int i, ret; 1986 1987 trace_msm_gpu_suspend(0); 1988 1989 a6xx_llc_deactivate(a6xx_gpu); 1990 1991 msm_devfreq_suspend(gpu); 1992 1993 mutex_lock(&a6xx_gpu->gmu.lock); 1994 ret = a6xx_gmu_stop(a6xx_gpu); 1995 mutex_unlock(&a6xx_gpu->gmu.lock); 1996 if (ret) 1997 return ret; 1998 1999 if (a6xx_gpu->shadow_bo) 2000 for (i = 0; i < gpu->nr_rings; i++) 2001 a6xx_gpu->shadow[i] = 0; 2002 2003 gpu->suspend_count++; 2004 2005 return 0; 2006 } 2007 2008 static int a6xx_pm_suspend(struct msm_gpu *gpu) 2009 { 2010 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2011 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2012 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 2013 int i; 2014 2015 trace_msm_gpu_suspend(0); 2016 2017 msm_devfreq_suspend(gpu); 2018 2019 mutex_lock(&a6xx_gpu->gmu.lock); 2020 2021 /* Drain the outstanding traffic on memory buses */ 2022 a6xx_bus_clear_pending_transactions(adreno_gpu, true); 2023 2024 if (adreno_is_a619_holi(adreno_gpu)) 2025 a6xx_sptprac_disable(gmu); 2026 2027 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); 2028 2029 pm_runtime_put_sync(gmu->gxpd); 2030 dev_pm_opp_set_opp(&gpu->pdev->dev, NULL); 2031 pm_runtime_put_sync(gmu->dev); 2032 2033 mutex_unlock(&a6xx_gpu->gmu.lock); 2034 2035 if (a6xx_gpu->shadow_bo) 2036 for (i = 0; i < gpu->nr_rings; i++) 2037 a6xx_gpu->shadow[i] = 0; 2038 2039 gpu->suspend_count++; 2040 2041 return 0; 2042 } 2043 2044 static int a6xx_gmu_get_timestamp(struct msm_gpu *gpu, uint64_t *value) 2045 { 2046 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2047 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2048 2049 mutex_lock(&a6xx_gpu->gmu.lock); 2050 2051 /* Force the GPU power on so we can read this register */ 2052 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); 2053 2054 *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER); 2055 2056 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET); 2057 2058 mutex_unlock(&a6xx_gpu->gmu.lock); 2059 2060 return 0; 2061 } 2062 2063 static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) 2064 { 2065 *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER); 2066 return 0; 2067 } 2068 2069 static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu) 2070 { 2071 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2072 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2073 2074 return a6xx_gpu->cur_ring; 2075 } 2076 2077 static void a6xx_destroy(struct msm_gpu *gpu) 2078 { 2079 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2080 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2081 2082 if (a6xx_gpu->sqe_bo) { 2083 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace); 2084 drm_gem_object_put(a6xx_gpu->sqe_bo); 2085 } 2086 2087 if (a6xx_gpu->shadow_bo) { 2088 msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->aspace); 2089 drm_gem_object_put(a6xx_gpu->shadow_bo); 2090 } 2091 2092 a6xx_llc_slices_destroy(a6xx_gpu); 2093 2094 mutex_lock(&a6xx_gpu->gmu.lock); 2095 a6xx_gmu_remove(a6xx_gpu); 2096 mutex_unlock(&a6xx_gpu->gmu.lock); 2097 2098 adreno_gpu_cleanup(adreno_gpu); 2099 2100 kfree(a6xx_gpu); 2101 } 2102 2103 static u64 a6xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) 2104 { 2105 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2106 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2107 u64 busy_cycles; 2108 2109 /* 19.2MHz */ 2110 *out_sample_rate = 19200000; 2111 2112 busy_cycles = gmu_read64(&a6xx_gpu->gmu, 2113 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L, 2114 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H); 2115 2116 return busy_cycles; 2117 } 2118 2119 static void a6xx_gpu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, 2120 bool suspended) 2121 { 2122 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2123 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2124 2125 mutex_lock(&a6xx_gpu->gmu.lock); 2126 a6xx_gmu_set_freq(gpu, opp, suspended); 2127 mutex_unlock(&a6xx_gpu->gmu.lock); 2128 } 2129 2130 static struct msm_gem_address_space * 2131 a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) 2132 { 2133 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2134 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2135 unsigned long quirks = 0; 2136 2137 /* 2138 * This allows GPU to set the bus attributes required to use system 2139 * cache on behalf of the iommu page table walker. 2140 */ 2141 if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice) && 2142 !device_iommu_capable(&pdev->dev, IOMMU_CAP_CACHE_COHERENCY)) 2143 quirks |= IO_PGTABLE_QUIRK_ARM_OUTER_WBWA; 2144 2145 return adreno_iommu_create_address_space(gpu, pdev, quirks); 2146 } 2147 2148 static struct msm_gem_address_space * 2149 a6xx_create_private_address_space(struct msm_gpu *gpu) 2150 { 2151 struct msm_mmu *mmu; 2152 2153 mmu = msm_iommu_pagetable_create(gpu->aspace->mmu); 2154 2155 if (IS_ERR(mmu)) 2156 return ERR_CAST(mmu); 2157 2158 return msm_gem_address_space_create(mmu, 2159 "gpu", 0x100000000ULL, 2160 adreno_private_address_space_size(gpu)); 2161 } 2162 2163 static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 2164 { 2165 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 2166 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 2167 2168 if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) 2169 return a6xx_gpu->shadow[ring->id]; 2170 2171 return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR); 2172 } 2173 2174 static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 2175 { 2176 struct msm_cp_state cp_state = { 2177 .ib1_base = gpu_read64(gpu, REG_A6XX_CP_IB1_BASE), 2178 .ib2_base = gpu_read64(gpu, REG_A6XX_CP_IB2_BASE), 2179 .ib1_rem = gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE), 2180 .ib2_rem = gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE), 2181 }; 2182 bool progress; 2183 2184 /* 2185 * Adjust the remaining data to account for what has already been 2186 * fetched from memory, but not yet consumed by the SQE. 2187 * 2188 * This is not *technically* correct, the amount buffered could 2189 * exceed the IB size due to hw prefetching ahead, but: 2190 * 2191 * (1) We aren't trying to find the exact position, just whether 2192 * progress has been made 2193 * (2) The CP_REG_TO_MEM at the end of a submit should be enough 2194 * to prevent prefetching into an unrelated submit. (And 2195 * either way, at some point the ROQ will be full.) 2196 */ 2197 cp_state.ib1_rem += gpu_read(gpu, REG_A6XX_CP_ROQ_AVAIL_IB1) >> 16; 2198 cp_state.ib2_rem += gpu_read(gpu, REG_A6XX_CP_ROQ_AVAIL_IB2) >> 16; 2199 2200 progress = !!memcmp(&cp_state, &ring->last_cp_state, sizeof(cp_state)); 2201 2202 ring->last_cp_state = cp_state; 2203 2204 return progress; 2205 } 2206 2207 static u32 a610_get_speed_bin(u32 fuse) 2208 { 2209 /* 2210 * There are (at least) three SoCs implementing A610: SM6125 (trinket), 2211 * SM6115 (bengal) and SM6225 (khaje). Trinket does not have speedbinning, 2212 * as only a single SKU exists and we don't support khaje upstream yet. 2213 * Hence, this matching table is only valid for bengal and can be easily 2214 * expanded if need be. 2215 */ 2216 2217 if (fuse == 0) 2218 return 0; 2219 else if (fuse == 206) 2220 return 1; 2221 else if (fuse == 200) 2222 return 2; 2223 else if (fuse == 157) 2224 return 3; 2225 else if (fuse == 127) 2226 return 4; 2227 2228 return UINT_MAX; 2229 } 2230 2231 static u32 a618_get_speed_bin(u32 fuse) 2232 { 2233 if (fuse == 0) 2234 return 0; 2235 else if (fuse == 169) 2236 return 1; 2237 else if (fuse == 174) 2238 return 2; 2239 2240 return UINT_MAX; 2241 } 2242 2243 static u32 a619_holi_get_speed_bin(u32 fuse) 2244 { 2245 /* 2246 * There are (at least) two SoCs implementing A619_holi: SM4350 (holi) 2247 * and SM6375 (blair). Limit the fuse matching to the corresponding 2248 * SoC to prevent bogus frequency setting (as improbable as it may be, 2249 * given unexpected fuse values are.. unexpected! But still possible.) 2250 */ 2251 2252 if (fuse == 0) 2253 return 0; 2254 2255 if (of_machine_is_compatible("qcom,sm4350")) { 2256 if (fuse == 138) 2257 return 1; 2258 else if (fuse == 92) 2259 return 2; 2260 } else if (of_machine_is_compatible("qcom,sm6375")) { 2261 if (fuse == 190) 2262 return 1; 2263 else if (fuse == 177) 2264 return 2; 2265 } else 2266 pr_warn("Unknown SoC implementing A619_holi!\n"); 2267 2268 return UINT_MAX; 2269 } 2270 2271 static u32 a619_get_speed_bin(u32 fuse) 2272 { 2273 if (fuse == 0) 2274 return 0; 2275 else if (fuse == 120) 2276 return 4; 2277 else if (fuse == 138) 2278 return 3; 2279 else if (fuse == 169) 2280 return 2; 2281 else if (fuse == 180) 2282 return 1; 2283 2284 return UINT_MAX; 2285 } 2286 2287 static u32 a640_get_speed_bin(u32 fuse) 2288 { 2289 if (fuse == 0) 2290 return 0; 2291 else if (fuse == 1) 2292 return 1; 2293 2294 return UINT_MAX; 2295 } 2296 2297 static u32 a650_get_speed_bin(u32 fuse) 2298 { 2299 if (fuse == 0) 2300 return 0; 2301 else if (fuse == 1) 2302 return 1; 2303 /* Yep, 2 and 3 are swapped! :/ */ 2304 else if (fuse == 2) 2305 return 3; 2306 else if (fuse == 3) 2307 return 2; 2308 2309 return UINT_MAX; 2310 } 2311 2312 static u32 adreno_7c3_get_speed_bin(u32 fuse) 2313 { 2314 if (fuse == 0) 2315 return 0; 2316 else if (fuse == 117) 2317 return 0; 2318 else if (fuse == 190) 2319 return 1; 2320 2321 return UINT_MAX; 2322 } 2323 2324 static u32 fuse_to_supp_hw(struct device *dev, struct adreno_gpu *adreno_gpu, u32 fuse) 2325 { 2326 u32 val = UINT_MAX; 2327 2328 if (adreno_is_a610(adreno_gpu)) 2329 val = a610_get_speed_bin(fuse); 2330 2331 if (adreno_is_a618(adreno_gpu)) 2332 val = a618_get_speed_bin(fuse); 2333 2334 else if (adreno_is_a619_holi(adreno_gpu)) 2335 val = a619_holi_get_speed_bin(fuse); 2336 2337 else if (adreno_is_a619(adreno_gpu)) 2338 val = a619_get_speed_bin(fuse); 2339 2340 else if (adreno_is_7c3(adreno_gpu)) 2341 val = adreno_7c3_get_speed_bin(fuse); 2342 2343 else if (adreno_is_a640(adreno_gpu)) 2344 val = a640_get_speed_bin(fuse); 2345 2346 else if (adreno_is_a650(adreno_gpu)) 2347 val = a650_get_speed_bin(fuse); 2348 2349 if (val == UINT_MAX) { 2350 DRM_DEV_ERROR(dev, 2351 "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", 2352 fuse); 2353 return UINT_MAX; 2354 } 2355 2356 return (1 << val); 2357 } 2358 2359 static int a6xx_set_supported_hw(struct device *dev, struct adreno_gpu *adreno_gpu) 2360 { 2361 u32 supp_hw; 2362 u32 speedbin; 2363 int ret; 2364 2365 ret = adreno_read_speedbin(dev, &speedbin); 2366 /* 2367 * -ENOENT means that the platform doesn't support speedbin which is 2368 * fine 2369 */ 2370 if (ret == -ENOENT) { 2371 return 0; 2372 } else if (ret) { 2373 dev_err_probe(dev, ret, 2374 "failed to read speed-bin. Some OPPs may not be supported by hardware\n"); 2375 return ret; 2376 } 2377 2378 supp_hw = fuse_to_supp_hw(dev, adreno_gpu, speedbin); 2379 2380 ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); 2381 if (ret) 2382 return ret; 2383 2384 return 0; 2385 } 2386 2387 static const struct adreno_gpu_funcs funcs = { 2388 .base = { 2389 .get_param = adreno_get_param, 2390 .set_param = adreno_set_param, 2391 .hw_init = a6xx_hw_init, 2392 .ucode_load = a6xx_ucode_load, 2393 .pm_suspend = a6xx_gmu_pm_suspend, 2394 .pm_resume = a6xx_gmu_pm_resume, 2395 .recover = a6xx_recover, 2396 .submit = a6xx_submit, 2397 .active_ring = a6xx_active_ring, 2398 .irq = a6xx_irq, 2399 .destroy = a6xx_destroy, 2400 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2401 .show = a6xx_show, 2402 #endif 2403 .gpu_busy = a6xx_gpu_busy, 2404 .gpu_get_freq = a6xx_gmu_get_freq, 2405 .gpu_set_freq = a6xx_gpu_set_freq, 2406 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2407 .gpu_state_get = a6xx_gpu_state_get, 2408 .gpu_state_put = a6xx_gpu_state_put, 2409 #endif 2410 .create_address_space = a6xx_create_address_space, 2411 .create_private_address_space = a6xx_create_private_address_space, 2412 .get_rptr = a6xx_get_rptr, 2413 .progress = a6xx_progress, 2414 }, 2415 .get_timestamp = a6xx_gmu_get_timestamp, 2416 }; 2417 2418 static const struct adreno_gpu_funcs funcs_gmuwrapper = { 2419 .base = { 2420 .get_param = adreno_get_param, 2421 .set_param = adreno_set_param, 2422 .hw_init = a6xx_hw_init, 2423 .ucode_load = a6xx_ucode_load, 2424 .pm_suspend = a6xx_pm_suspend, 2425 .pm_resume = a6xx_pm_resume, 2426 .recover = a6xx_recover, 2427 .submit = a6xx_submit, 2428 .active_ring = a6xx_active_ring, 2429 .irq = a6xx_irq, 2430 .destroy = a6xx_destroy, 2431 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2432 .show = a6xx_show, 2433 #endif 2434 .gpu_busy = a6xx_gpu_busy, 2435 #if defined(CONFIG_DRM_MSM_GPU_STATE) 2436 .gpu_state_get = a6xx_gpu_state_get, 2437 .gpu_state_put = a6xx_gpu_state_put, 2438 #endif 2439 .create_address_space = a6xx_create_address_space, 2440 .create_private_address_space = a6xx_create_private_address_space, 2441 .get_rptr = a6xx_get_rptr, 2442 .progress = a6xx_progress, 2443 }, 2444 .get_timestamp = a6xx_get_timestamp, 2445 }; 2446 2447 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) 2448 { 2449 struct msm_drm_private *priv = dev->dev_private; 2450 struct platform_device *pdev = priv->gpu_pdev; 2451 struct adreno_platform_config *config = pdev->dev.platform_data; 2452 const struct adreno_info *info; 2453 struct device_node *node; 2454 struct a6xx_gpu *a6xx_gpu; 2455 struct adreno_gpu *adreno_gpu; 2456 struct msm_gpu *gpu; 2457 int ret; 2458 2459 a6xx_gpu = kzalloc(sizeof(*a6xx_gpu), GFP_KERNEL); 2460 if (!a6xx_gpu) 2461 return ERR_PTR(-ENOMEM); 2462 2463 adreno_gpu = &a6xx_gpu->base; 2464 gpu = &adreno_gpu->base; 2465 2466 mutex_init(&a6xx_gpu->gmu.lock); 2467 2468 adreno_gpu->registers = NULL; 2469 2470 /* Check if there is a GMU phandle and set it up */ 2471 node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0); 2472 /* FIXME: How do we gracefully handle this? */ 2473 BUG_ON(!node); 2474 2475 adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper"); 2476 2477 /* 2478 * We need to know the platform type before calling into adreno_gpu_init 2479 * so that the hw_apriv flag can be correctly set. Snoop into the info 2480 * and grab the revision number 2481 */ 2482 info = adreno_info(config->rev); 2483 if (!info) 2484 return ERR_PTR(-EINVAL); 2485 2486 /* Assign these early so that we can use the is_aXYZ helpers */ 2487 /* Numeric revision IDs (e.g. 630) */ 2488 adreno_gpu->revn = info->revn; 2489 /* New-style ADRENO_REV()-only */ 2490 adreno_gpu->rev = info->rev; 2491 /* Quirk data */ 2492 adreno_gpu->info = info; 2493 2494 if (adreno_is_a650(adreno_gpu) || adreno_is_a660_family(adreno_gpu)) 2495 adreno_gpu->base.hw_apriv = true; 2496 2497 a6xx_llc_slices_init(pdev, a6xx_gpu); 2498 2499 ret = a6xx_set_supported_hw(&pdev->dev, adreno_gpu); 2500 if (ret) { 2501 a6xx_destroy(&(a6xx_gpu->base.base)); 2502 return ERR_PTR(ret); 2503 } 2504 2505 if (adreno_has_gmu_wrapper(adreno_gpu)) 2506 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_gmuwrapper, 1); 2507 else 2508 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); 2509 if (ret) { 2510 a6xx_destroy(&(a6xx_gpu->base.base)); 2511 return ERR_PTR(ret); 2512 } 2513 2514 /* 2515 * For now only clamp to idle freq for devices where this is known not 2516 * to cause power supply issues: 2517 */ 2518 if (adreno_is_a618(adreno_gpu) || adreno_is_7c3(adreno_gpu)) 2519 priv->gpu_clamp_to_idle = true; 2520 2521 if (adreno_has_gmu_wrapper(adreno_gpu)) 2522 ret = a6xx_gmu_wrapper_init(a6xx_gpu, node); 2523 else 2524 ret = a6xx_gmu_init(a6xx_gpu, node); 2525 of_node_put(node); 2526 if (ret) { 2527 a6xx_destroy(&(a6xx_gpu->base.base)); 2528 return ERR_PTR(ret); 2529 } 2530 2531 if (gpu->aspace) 2532 msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, 2533 a6xx_fault_handler); 2534 2535 return gpu; 2536 } 2537