1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. */ 3 4 5 #include "msm_gem.h" 6 #include "msm_mmu.h" 7 #include "msm_gpu_trace.h" 8 #include "a6xx_gpu.h" 9 #include "a6xx_gmu.xml.h" 10 11 #include <linux/devfreq.h> 12 13 static inline bool _a6xx_check_idle(struct msm_gpu *gpu) 14 { 15 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 16 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 17 18 /* Check that the GMU is idle */ 19 if (!a6xx_gmu_isidle(&a6xx_gpu->gmu)) 20 return false; 21 22 /* Check tha the CX master is idle */ 23 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & 24 ~A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER) 25 return false; 26 27 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & 28 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT); 29 } 30 31 bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 32 { 33 /* wait for CP to drain ringbuffer: */ 34 if (!adreno_idle(gpu, ring)) 35 return false; 36 37 if (spin_until(_a6xx_check_idle(gpu))) { 38 DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n", 39 gpu->name, __builtin_return_address(0), 40 gpu_read(gpu, REG_A6XX_RBBM_STATUS), 41 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS), 42 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), 43 gpu_read(gpu, REG_A6XX_CP_RB_WPTR)); 44 return false; 45 } 46 47 return true; 48 } 49 50 static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 51 { 52 uint32_t wptr; 53 unsigned long flags; 54 55 spin_lock_irqsave(&ring->lock, flags); 56 57 /* Copy the shadow to the actual register */ 58 ring->cur = ring->next; 59 60 /* Make sure to wrap wptr if we need to */ 61 wptr = get_wptr(ring); 62 63 spin_unlock_irqrestore(&ring->lock, flags); 64 65 /* Make sure everything is posted before making a decision */ 66 mb(); 67 68 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); 69 } 70 71 static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, 72 u64 iova) 73 { 74 OUT_PKT7(ring, CP_REG_TO_MEM, 3); 75 OUT_RING(ring, counter | (1 << 30) | (2 << 18)); 76 OUT_RING(ring, lower_32_bits(iova)); 77 OUT_RING(ring, upper_32_bits(iova)); 78 } 79 80 static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, 81 struct msm_file_private *ctx) 82 { 83 unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; 84 struct msm_drm_private *priv = gpu->dev->dev_private; 85 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 86 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 87 struct msm_ringbuffer *ring = submit->ring; 88 unsigned int i; 89 90 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO, 91 rbmemptr_stats(ring, index, cpcycles_start)); 92 93 /* 94 * For PM4 the GMU register offsets are calculated from the base of the 95 * GPU registers so we need to add 0x1a800 to the register value on A630 96 * to get the right value from PM4. 97 */ 98 get_stats_counter(ring, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L + 0x1a800, 99 rbmemptr_stats(ring, index, alwayson_start)); 100 101 /* Invalidate CCU depth and color */ 102 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 103 OUT_RING(ring, PC_CCU_INVALIDATE_DEPTH); 104 105 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 106 OUT_RING(ring, PC_CCU_INVALIDATE_COLOR); 107 108 /* Submit the commands */ 109 for (i = 0; i < submit->nr_cmds; i++) { 110 switch (submit->cmd[i].type) { 111 case MSM_SUBMIT_CMD_IB_TARGET_BUF: 112 break; 113 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: 114 if (priv->lastctx == ctx) 115 break; 116 case MSM_SUBMIT_CMD_BUF: 117 OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3); 118 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); 119 OUT_RING(ring, upper_32_bits(submit->cmd[i].iova)); 120 OUT_RING(ring, submit->cmd[i].size); 121 break; 122 } 123 } 124 125 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO, 126 rbmemptr_stats(ring, index, cpcycles_end)); 127 get_stats_counter(ring, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L + 0x1a800, 128 rbmemptr_stats(ring, index, alwayson_end)); 129 130 /* Write the fence to the scratch register */ 131 OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1); 132 OUT_RING(ring, submit->seqno); 133 134 /* 135 * Execute a CACHE_FLUSH_TS event. This will ensure that the 136 * timestamp is written to the memory and then triggers the interrupt 137 */ 138 OUT_PKT7(ring, CP_EVENT_WRITE, 4); 139 OUT_RING(ring, CACHE_FLUSH_TS | (1 << 31)); 140 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence))); 141 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); 142 OUT_RING(ring, submit->seqno); 143 144 trace_msm_gpu_submit_flush(submit, 145 gmu_read64(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L, 146 REG_A6XX_GMU_ALWAYS_ON_COUNTER_H)); 147 148 a6xx_flush(gpu, ring); 149 } 150 151 static const struct { 152 u32 offset; 153 u32 value; 154 } a6xx_hwcg[] = { 155 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, 156 {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222}, 157 {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222}, 158 {REG_A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222}, 159 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220}, 160 {REG_A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220}, 161 {REG_A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220}, 162 {REG_A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220}, 163 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 164 {REG_A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080}, 165 {REG_A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080}, 166 {REG_A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080}, 167 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf}, 168 {REG_A6XX_RBBM_CLOCK_HYST_SP1, 0x0000f3cf}, 169 {REG_A6XX_RBBM_CLOCK_HYST_SP2, 0x0000f3cf}, 170 {REG_A6XX_RBBM_CLOCK_HYST_SP3, 0x0000f3cf}, 171 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, 172 {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222}, 173 {REG_A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222}, 174 {REG_A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222}, 175 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 176 {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222}, 177 {REG_A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222}, 178 {REG_A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222}, 179 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 180 {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222}, 181 {REG_A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222}, 182 {REG_A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222}, 183 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 184 {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222}, 185 {REG_A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222}, 186 {REG_A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222}, 187 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 188 {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777}, 189 {REG_A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777}, 190 {REG_A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777}, 191 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 192 {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777}, 193 {REG_A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777}, 194 {REG_A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777}, 195 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 196 {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777}, 197 {REG_A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777}, 198 {REG_A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777}, 199 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 200 {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777}, 201 {REG_A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777}, 202 {REG_A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777}, 203 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 204 {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111}, 205 {REG_A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111}, 206 {REG_A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111}, 207 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 208 {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111}, 209 {REG_A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111}, 210 {REG_A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111}, 211 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 212 {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111}, 213 {REG_A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111}, 214 {REG_A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111}, 215 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 216 {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111}, 217 {REG_A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111}, 218 {REG_A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111}, 219 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 220 {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222}, 221 {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222}, 222 {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222}, 223 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 224 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 225 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 226 {REG_A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222}, 227 {REG_A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222}, 228 {REG_A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222}, 229 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222}, 230 {REG_A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222}, 231 {REG_A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222}, 232 {REG_A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222}, 233 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 234 {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220}, 235 {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220}, 236 {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220}, 237 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00}, 238 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040f00}, 239 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040f00}, 240 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040f00}, 241 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022}, 242 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 243 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 244 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 245 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 246 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 247 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 248 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 249 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 250 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 251 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 252 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 253 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 254 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 255 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 256 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 257 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 258 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 259 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555} 260 }; 261 262 static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) 263 { 264 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 265 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 266 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 267 unsigned int i; 268 u32 val; 269 270 val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL); 271 272 /* Don't re-program the registers if they are already correct */ 273 if ((!state && !val) || (state && (val == 0x8aa8aa02))) 274 return; 275 276 /* Disable SP clock before programming HWCG registers */ 277 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); 278 279 for (i = 0; i < ARRAY_SIZE(a6xx_hwcg); i++) 280 gpu_write(gpu, a6xx_hwcg[i].offset, 281 state ? a6xx_hwcg[i].value : 0); 282 283 /* Enable SP clock */ 284 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); 285 286 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? 0x8aa8aa02 : 0); 287 } 288 289 static int a6xx_cp_init(struct msm_gpu *gpu) 290 { 291 struct msm_ringbuffer *ring = gpu->rb[0]; 292 293 OUT_PKT7(ring, CP_ME_INIT, 8); 294 295 OUT_RING(ring, 0x0000002f); 296 297 /* Enable multiple hardware contexts */ 298 OUT_RING(ring, 0x00000003); 299 300 /* Enable error detection */ 301 OUT_RING(ring, 0x20000000); 302 303 /* Don't enable header dump */ 304 OUT_RING(ring, 0x00000000); 305 OUT_RING(ring, 0x00000000); 306 307 /* No workarounds enabled */ 308 OUT_RING(ring, 0x00000000); 309 310 /* Pad rest of the cmds with 0's */ 311 OUT_RING(ring, 0x00000000); 312 OUT_RING(ring, 0x00000000); 313 314 a6xx_flush(gpu, ring); 315 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; 316 } 317 318 static int a6xx_ucode_init(struct msm_gpu *gpu) 319 { 320 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 321 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 322 323 if (!a6xx_gpu->sqe_bo) { 324 a6xx_gpu->sqe_bo = adreno_fw_create_bo(gpu, 325 adreno_gpu->fw[ADRENO_FW_SQE], &a6xx_gpu->sqe_iova); 326 327 if (IS_ERR(a6xx_gpu->sqe_bo)) { 328 int ret = PTR_ERR(a6xx_gpu->sqe_bo); 329 330 a6xx_gpu->sqe_bo = NULL; 331 DRM_DEV_ERROR(&gpu->pdev->dev, 332 "Could not allocate SQE ucode: %d\n", ret); 333 334 return ret; 335 } 336 337 msm_gem_object_set_name(a6xx_gpu->sqe_bo, "sqefw"); 338 } 339 340 gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE_LO, 341 REG_A6XX_CP_SQE_INSTR_BASE_HI, a6xx_gpu->sqe_iova); 342 343 return 0; 344 } 345 346 #define A6XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \ 347 A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \ 348 A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \ 349 A6XX_RBBM_INT_0_MASK_CP_IB2 | \ 350 A6XX_RBBM_INT_0_MASK_CP_IB1 | \ 351 A6XX_RBBM_INT_0_MASK_CP_RB | \ 352 A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \ 353 A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \ 354 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \ 355 A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \ 356 A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR) 357 358 static int a6xx_hw_init(struct msm_gpu *gpu) 359 { 360 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 361 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 362 int ret; 363 364 /* Make sure the GMU keeps the GPU on while we set it up */ 365 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 366 367 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); 368 369 /* 370 * Disable the trusted memory range - we don't actually supported secure 371 * memory rendering at this point in time and we don't want to block off 372 * part of the virtual memory space. 373 */ 374 gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO, 375 REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x00000000); 376 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); 377 378 /* enable hardware clockgating */ 379 a6xx_set_hwcg(gpu, true); 380 381 /* VBIF start */ 382 gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009); 383 gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3); 384 385 /* Make all blocks contribute to the GPU BUSY perf counter */ 386 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff); 387 388 /* Disable L2 bypass in the UCHE */ 389 gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_LO, 0xffffffc0); 390 gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_HI, 0x0001ffff); 391 gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_LO, 0xfffff000); 392 gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_HI, 0x0001ffff); 393 gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000); 394 gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff); 395 396 /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */ 397 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN_LO, 398 REG_A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x00100000); 399 400 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX_LO, 401 REG_A6XX_UCHE_GMEM_RANGE_MAX_HI, 402 0x00100000 + adreno_gpu->gmem - 1); 403 404 gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804); 405 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4); 406 407 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0); 408 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); 409 410 /* Setting the mem pool size */ 411 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); 412 413 /* Setting the primFifo thresholds default values */ 414 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, (0x300 << 11)); 415 416 /* Set the AHB default slave response to "ERROR" */ 417 gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1); 418 419 /* Turn on performance counters */ 420 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1); 421 422 /* Select CP0 to always count cycles */ 423 gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT); 424 425 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 2 << 1); 426 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 2 << 1); 427 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 2 << 1); 428 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 2 << 21); 429 430 /* Enable fault detection */ 431 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, 432 (1 << 30) | 0x1fffff); 433 434 gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1); 435 436 /* Protect registers from the CP */ 437 gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, 0x00000003); 438 439 gpu_write(gpu, REG_A6XX_CP_PROTECT(0), 440 A6XX_PROTECT_RDONLY(0x600, 0x51)); 441 gpu_write(gpu, REG_A6XX_CP_PROTECT(1), A6XX_PROTECT_RW(0xae50, 0x2)); 442 gpu_write(gpu, REG_A6XX_CP_PROTECT(2), A6XX_PROTECT_RW(0x9624, 0x13)); 443 gpu_write(gpu, REG_A6XX_CP_PROTECT(3), A6XX_PROTECT_RW(0x8630, 0x8)); 444 gpu_write(gpu, REG_A6XX_CP_PROTECT(4), A6XX_PROTECT_RW(0x9e70, 0x1)); 445 gpu_write(gpu, REG_A6XX_CP_PROTECT(5), A6XX_PROTECT_RW(0x9e78, 0x187)); 446 gpu_write(gpu, REG_A6XX_CP_PROTECT(6), A6XX_PROTECT_RW(0xf000, 0x810)); 447 gpu_write(gpu, REG_A6XX_CP_PROTECT(7), 448 A6XX_PROTECT_RDONLY(0xfc00, 0x3)); 449 gpu_write(gpu, REG_A6XX_CP_PROTECT(8), A6XX_PROTECT_RW(0x50e, 0x0)); 450 gpu_write(gpu, REG_A6XX_CP_PROTECT(9), A6XX_PROTECT_RDONLY(0x50f, 0x0)); 451 gpu_write(gpu, REG_A6XX_CP_PROTECT(10), A6XX_PROTECT_RW(0x510, 0x0)); 452 gpu_write(gpu, REG_A6XX_CP_PROTECT(11), 453 A6XX_PROTECT_RDONLY(0x0, 0x4f9)); 454 gpu_write(gpu, REG_A6XX_CP_PROTECT(12), 455 A6XX_PROTECT_RDONLY(0x501, 0xa)); 456 gpu_write(gpu, REG_A6XX_CP_PROTECT(13), 457 A6XX_PROTECT_RDONLY(0x511, 0x44)); 458 gpu_write(gpu, REG_A6XX_CP_PROTECT(14), A6XX_PROTECT_RW(0xe00, 0xe)); 459 gpu_write(gpu, REG_A6XX_CP_PROTECT(15), A6XX_PROTECT_RW(0x8e00, 0x0)); 460 gpu_write(gpu, REG_A6XX_CP_PROTECT(16), A6XX_PROTECT_RW(0x8e50, 0xf)); 461 gpu_write(gpu, REG_A6XX_CP_PROTECT(17), A6XX_PROTECT_RW(0xbe02, 0x0)); 462 gpu_write(gpu, REG_A6XX_CP_PROTECT(18), 463 A6XX_PROTECT_RW(0xbe20, 0x11f3)); 464 gpu_write(gpu, REG_A6XX_CP_PROTECT(19), A6XX_PROTECT_RW(0x800, 0x82)); 465 gpu_write(gpu, REG_A6XX_CP_PROTECT(20), A6XX_PROTECT_RW(0x8a0, 0x8)); 466 gpu_write(gpu, REG_A6XX_CP_PROTECT(21), A6XX_PROTECT_RW(0x8ab, 0x19)); 467 gpu_write(gpu, REG_A6XX_CP_PROTECT(22), A6XX_PROTECT_RW(0x900, 0x4d)); 468 gpu_write(gpu, REG_A6XX_CP_PROTECT(23), A6XX_PROTECT_RW(0x98d, 0x76)); 469 gpu_write(gpu, REG_A6XX_CP_PROTECT(24), 470 A6XX_PROTECT_RDONLY(0x980, 0x4)); 471 gpu_write(gpu, REG_A6XX_CP_PROTECT(25), A6XX_PROTECT_RW(0xa630, 0x0)); 472 473 /* Enable interrupts */ 474 gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, A6XX_INT_MASK); 475 476 ret = adreno_hw_init(gpu); 477 if (ret) 478 goto out; 479 480 ret = a6xx_ucode_init(gpu); 481 if (ret) 482 goto out; 483 484 /* Always come up on rb 0 */ 485 a6xx_gpu->cur_ring = gpu->rb[0]; 486 487 /* Enable the SQE_to start the CP engine */ 488 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1); 489 490 ret = a6xx_cp_init(gpu); 491 if (ret) 492 goto out; 493 494 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0); 495 496 out: 497 /* 498 * Tell the GMU that we are done touching the GPU and it can start power 499 * management 500 */ 501 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 502 503 /* Take the GMU out of its special boot mode */ 504 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER); 505 506 return ret; 507 } 508 509 static void a6xx_dump(struct msm_gpu *gpu) 510 { 511 DRM_DEV_INFO(&gpu->pdev->dev, "status: %08x\n", 512 gpu_read(gpu, REG_A6XX_RBBM_STATUS)); 513 adreno_dump(gpu); 514 } 515 516 #define VBIF_RESET_ACK_TIMEOUT 100 517 #define VBIF_RESET_ACK_MASK 0x00f0 518 519 static void a6xx_recover(struct msm_gpu *gpu) 520 { 521 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 522 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 523 int i; 524 525 adreno_dump_info(gpu); 526 527 for (i = 0; i < 8; i++) 528 DRM_DEV_INFO(&gpu->pdev->dev, "CP_SCRATCH_REG%d: %u\n", i, 529 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i))); 530 531 if (hang_debug) 532 a6xx_dump(gpu); 533 534 /* 535 * Turn off keep alive that might have been enabled by the hang 536 * interrupt 537 */ 538 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); 539 540 gpu->funcs->pm_suspend(gpu); 541 gpu->funcs->pm_resume(gpu); 542 543 msm_gpu_hw_init(gpu); 544 } 545 546 static int a6xx_fault_handler(void *arg, unsigned long iova, int flags) 547 { 548 struct msm_gpu *gpu = arg; 549 550 pr_warn_ratelimited("*** gpu fault: iova=%08lx, flags=%d (%u,%u,%u,%u)\n", 551 iova, flags, 552 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)), 553 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)), 554 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)), 555 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7))); 556 557 return -EFAULT; 558 } 559 560 static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu) 561 { 562 u32 status = gpu_read(gpu, REG_A6XX_CP_INTERRUPT_STATUS); 563 564 if (status & A6XX_CP_INT_CP_OPCODE_ERROR) { 565 u32 val; 566 567 gpu_write(gpu, REG_A6XX_CP_SQE_STAT_ADDR, 1); 568 val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA); 569 dev_err_ratelimited(&gpu->pdev->dev, 570 "CP | opcode error | possible opcode=0x%8.8X\n", 571 val); 572 } 573 574 if (status & A6XX_CP_INT_CP_UCODE_ERROR) 575 dev_err_ratelimited(&gpu->pdev->dev, 576 "CP ucode error interrupt\n"); 577 578 if (status & A6XX_CP_INT_CP_HW_FAULT_ERROR) 579 dev_err_ratelimited(&gpu->pdev->dev, "CP | HW fault | status=0x%8.8X\n", 580 gpu_read(gpu, REG_A6XX_CP_HW_FAULT)); 581 582 if (status & A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR) { 583 u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS); 584 585 dev_err_ratelimited(&gpu->pdev->dev, 586 "CP | protected mode error | %s | addr=0x%8.8X | status=0x%8.8X\n", 587 val & (1 << 20) ? "READ" : "WRITE", 588 (val & 0x3ffff), val); 589 } 590 591 if (status & A6XX_CP_INT_CP_AHB_ERROR) 592 dev_err_ratelimited(&gpu->pdev->dev, "CP AHB error interrupt\n"); 593 594 if (status & A6XX_CP_INT_CP_VSD_PARITY_ERROR) 595 dev_err_ratelimited(&gpu->pdev->dev, "CP VSD decoder parity error\n"); 596 597 if (status & A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR) 598 dev_err_ratelimited(&gpu->pdev->dev, "CP illegal instruction error\n"); 599 600 } 601 602 static void a6xx_fault_detect_irq(struct msm_gpu *gpu) 603 { 604 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 605 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 606 struct drm_device *dev = gpu->dev; 607 struct msm_drm_private *priv = dev->dev_private; 608 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); 609 610 /* 611 * Force the GPU to stay on until after we finish 612 * collecting information 613 */ 614 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1); 615 616 DRM_DEV_ERROR(&gpu->pdev->dev, 617 "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n", 618 ring ? ring->id : -1, ring ? ring->seqno : 0, 619 gpu_read(gpu, REG_A6XX_RBBM_STATUS), 620 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), 621 gpu_read(gpu, REG_A6XX_CP_RB_WPTR), 622 gpu_read64(gpu, REG_A6XX_CP_IB1_BASE, REG_A6XX_CP_IB1_BASE_HI), 623 gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE), 624 gpu_read64(gpu, REG_A6XX_CP_IB2_BASE, REG_A6XX_CP_IB2_BASE_HI), 625 gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE)); 626 627 /* Turn off the hangcheck timer to keep it from bothering us */ 628 del_timer(&gpu->hangcheck_timer); 629 630 queue_work(priv->wq, &gpu->recover_work); 631 } 632 633 static irqreturn_t a6xx_irq(struct msm_gpu *gpu) 634 { 635 u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS); 636 637 gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status); 638 639 if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT) 640 a6xx_fault_detect_irq(gpu); 641 642 if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR) 643 dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n"); 644 645 if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR) 646 a6xx_cp_hw_err_irq(gpu); 647 648 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW) 649 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB ASYNC overflow\n"); 650 651 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW) 652 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB bus overflow\n"); 653 654 if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS) 655 dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n"); 656 657 if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) 658 msm_gpu_retire(gpu); 659 660 return IRQ_HANDLED; 661 } 662 663 static const u32 a6xx_register_offsets[REG_ADRENO_REGISTER_MAX] = { 664 REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE, REG_A6XX_CP_RB_BASE), 665 REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE_HI, REG_A6XX_CP_RB_BASE_HI), 666 REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR, 667 REG_A6XX_CP_RB_RPTR_ADDR_LO), 668 REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR_HI, 669 REG_A6XX_CP_RB_RPTR_ADDR_HI), 670 REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR, REG_A6XX_CP_RB_RPTR), 671 REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_WPTR, REG_A6XX_CP_RB_WPTR), 672 REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_A6XX_CP_RB_CNTL), 673 }; 674 675 static int a6xx_pm_resume(struct msm_gpu *gpu) 676 { 677 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 678 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 679 int ret; 680 681 ret = a6xx_gmu_resume(a6xx_gpu); 682 683 gpu->needs_hw_init = true; 684 685 msm_gpu_resume_devfreq(gpu); 686 687 return ret; 688 } 689 690 static int a6xx_pm_suspend(struct msm_gpu *gpu) 691 { 692 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 693 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 694 695 devfreq_suspend_device(gpu->devfreq.devfreq); 696 697 /* 698 * Make sure the GMU is idle before continuing (because some transitions 699 * may use VBIF 700 */ 701 a6xx_gmu_wait_for_idle(a6xx_gpu); 702 703 /* Clear the VBIF pipe before shutting down */ 704 /* FIXME: This accesses the GPU - do we need to make sure it is on? */ 705 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf); 706 spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & 0xf) == 0xf); 707 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0); 708 709 return a6xx_gmu_stop(a6xx_gpu); 710 } 711 712 static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) 713 { 714 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 715 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 716 717 /* Force the GPU power on so we can read this register */ 718 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 719 720 *value = gpu_read64(gpu, REG_A6XX_RBBM_PERFCTR_CP_0_LO, 721 REG_A6XX_RBBM_PERFCTR_CP_0_HI); 722 723 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 724 return 0; 725 } 726 727 static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu) 728 { 729 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 730 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 731 732 return a6xx_gpu->cur_ring; 733 } 734 735 static void a6xx_destroy(struct msm_gpu *gpu) 736 { 737 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 738 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 739 740 if (a6xx_gpu->sqe_bo) { 741 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace); 742 drm_gem_object_put_unlocked(a6xx_gpu->sqe_bo); 743 } 744 745 a6xx_gmu_remove(a6xx_gpu); 746 747 adreno_gpu_cleanup(adreno_gpu); 748 kfree(a6xx_gpu); 749 } 750 751 static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu) 752 { 753 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 754 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 755 u64 busy_cycles, busy_time; 756 757 busy_cycles = gmu_read64(&a6xx_gpu->gmu, 758 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L, 759 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H); 760 761 busy_time = (busy_cycles - gpu->devfreq.busy_cycles) * 10; 762 do_div(busy_time, 192); 763 764 gpu->devfreq.busy_cycles = busy_cycles; 765 766 if (WARN_ON(busy_time > ~0LU)) 767 return ~0LU; 768 769 return (unsigned long)busy_time; 770 } 771 772 static const struct adreno_gpu_funcs funcs = { 773 .base = { 774 .get_param = adreno_get_param, 775 .hw_init = a6xx_hw_init, 776 .pm_suspend = a6xx_pm_suspend, 777 .pm_resume = a6xx_pm_resume, 778 .recover = a6xx_recover, 779 .submit = a6xx_submit, 780 .flush = a6xx_flush, 781 .active_ring = a6xx_active_ring, 782 .irq = a6xx_irq, 783 .destroy = a6xx_destroy, 784 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) 785 .show = a6xx_show, 786 #endif 787 .gpu_busy = a6xx_gpu_busy, 788 .gpu_get_freq = a6xx_gmu_get_freq, 789 .gpu_set_freq = a6xx_gmu_set_freq, 790 .gpu_state_get = a6xx_gpu_state_get, 791 .gpu_state_put = a6xx_gpu_state_put, 792 }, 793 .get_timestamp = a6xx_get_timestamp, 794 }; 795 796 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) 797 { 798 struct msm_drm_private *priv = dev->dev_private; 799 struct platform_device *pdev = priv->gpu_pdev; 800 struct device_node *node; 801 struct a6xx_gpu *a6xx_gpu; 802 struct adreno_gpu *adreno_gpu; 803 struct msm_gpu *gpu; 804 int ret; 805 806 a6xx_gpu = kzalloc(sizeof(*a6xx_gpu), GFP_KERNEL); 807 if (!a6xx_gpu) 808 return ERR_PTR(-ENOMEM); 809 810 adreno_gpu = &a6xx_gpu->base; 811 gpu = &adreno_gpu->base; 812 813 adreno_gpu->registers = NULL; 814 adreno_gpu->reg_offsets = a6xx_register_offsets; 815 816 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); 817 if (ret) { 818 a6xx_destroy(&(a6xx_gpu->base.base)); 819 return ERR_PTR(ret); 820 } 821 822 /* Check if there is a GMU phandle and set it up */ 823 node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0); 824 825 /* FIXME: How do we gracefully handle this? */ 826 BUG_ON(!node); 827 828 ret = a6xx_gmu_probe(a6xx_gpu, node); 829 if (ret) { 830 a6xx_destroy(&(a6xx_gpu->base.base)); 831 return ERR_PTR(ret); 832 } 833 834 if (gpu->aspace) 835 msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, 836 a6xx_fault_handler); 837 838 return gpu; 839 } 840