1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */ 3 4 5 #include "msm_gem.h" 6 #include "msm_mmu.h" 7 #include "msm_gpu_trace.h" 8 #include "a6xx_gpu.h" 9 #include "a6xx_gmu.xml.h" 10 11 #include <linux/bitfield.h> 12 #include <linux/devfreq.h> 13 #include <linux/soc/qcom/llcc-qcom.h> 14 15 #define GPU_PAS_ID 13 16 17 static inline bool _a6xx_check_idle(struct msm_gpu *gpu) 18 { 19 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 20 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 21 22 /* Check that the GMU is idle */ 23 if (!a6xx_gmu_isidle(&a6xx_gpu->gmu)) 24 return false; 25 26 /* Check tha the CX master is idle */ 27 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & 28 ~A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER) 29 return false; 30 31 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & 32 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT); 33 } 34 35 static bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 36 { 37 /* wait for CP to drain ringbuffer: */ 38 if (!adreno_idle(gpu, ring)) 39 return false; 40 41 if (spin_until(_a6xx_check_idle(gpu))) { 42 DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n", 43 gpu->name, __builtin_return_address(0), 44 gpu_read(gpu, REG_A6XX_RBBM_STATUS), 45 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS), 46 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), 47 gpu_read(gpu, REG_A6XX_CP_RB_WPTR)); 48 return false; 49 } 50 51 return true; 52 } 53 54 static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 55 { 56 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 57 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 58 uint32_t wptr; 59 unsigned long flags; 60 61 /* Expanded APRIV doesn't need to issue the WHERE_AM_I opcode */ 62 if (a6xx_gpu->has_whereami && !adreno_gpu->base.hw_apriv) { 63 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 64 65 OUT_PKT7(ring, CP_WHERE_AM_I, 2); 66 OUT_RING(ring, lower_32_bits(shadowptr(a6xx_gpu, ring))); 67 OUT_RING(ring, upper_32_bits(shadowptr(a6xx_gpu, ring))); 68 } 69 70 spin_lock_irqsave(&ring->preempt_lock, flags); 71 72 /* Copy the shadow to the actual register */ 73 ring->cur = ring->next; 74 75 /* Make sure to wrap wptr if we need to */ 76 wptr = get_wptr(ring); 77 78 spin_unlock_irqrestore(&ring->preempt_lock, flags); 79 80 /* Make sure everything is posted before making a decision */ 81 mb(); 82 83 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); 84 } 85 86 static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, 87 u64 iova) 88 { 89 OUT_PKT7(ring, CP_REG_TO_MEM, 3); 90 OUT_RING(ring, CP_REG_TO_MEM_0_REG(counter) | 91 CP_REG_TO_MEM_0_CNT(2) | 92 CP_REG_TO_MEM_0_64B); 93 OUT_RING(ring, lower_32_bits(iova)); 94 OUT_RING(ring, upper_32_bits(iova)); 95 } 96 97 static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, 98 struct msm_ringbuffer *ring, struct msm_file_private *ctx) 99 { 100 phys_addr_t ttbr; 101 u32 asid; 102 u64 memptr = rbmemptr(ring, ttbr0); 103 104 if (ctx == a6xx_gpu->cur_ctx) 105 return; 106 107 if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid)) 108 return; 109 110 /* Execute the table update */ 111 OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4); 112 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr))); 113 114 OUT_RING(ring, 115 CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) | 116 CP_SMMU_TABLE_UPDATE_1_ASID(asid)); 117 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0)); 118 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0)); 119 120 /* 121 * Write the new TTBR0 to the memstore. This is good for debugging. 122 */ 123 OUT_PKT7(ring, CP_MEM_WRITE, 4); 124 OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr))); 125 OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr))); 126 OUT_RING(ring, lower_32_bits(ttbr)); 127 OUT_RING(ring, (asid << 16) | upper_32_bits(ttbr)); 128 129 /* 130 * And finally, trigger a uche flush to be sure there isn't anything 131 * lingering in that part of the GPU 132 */ 133 134 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 135 OUT_RING(ring, 0x31); 136 137 a6xx_gpu->cur_ctx = ctx; 138 } 139 140 static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 141 { 142 unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; 143 struct msm_drm_private *priv = gpu->dev->dev_private; 144 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 145 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 146 struct msm_ringbuffer *ring = submit->ring; 147 unsigned int i; 148 149 a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx); 150 151 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO, 152 rbmemptr_stats(ring, index, cpcycles_start)); 153 154 /* 155 * For PM4 the GMU register offsets are calculated from the base of the 156 * GPU registers so we need to add 0x1a800 to the register value on A630 157 * to get the right value from PM4. 158 */ 159 get_stats_counter(ring, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L + 0x1a800, 160 rbmemptr_stats(ring, index, alwayson_start)); 161 162 /* Invalidate CCU depth and color */ 163 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 164 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_DEPTH)); 165 166 OUT_PKT7(ring, CP_EVENT_WRITE, 1); 167 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_COLOR)); 168 169 /* Submit the commands */ 170 for (i = 0; i < submit->nr_cmds; i++) { 171 switch (submit->cmd[i].type) { 172 case MSM_SUBMIT_CMD_IB_TARGET_BUF: 173 break; 174 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF: 175 if (priv->lastctx == submit->queue->ctx) 176 break; 177 fallthrough; 178 case MSM_SUBMIT_CMD_BUF: 179 OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3); 180 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); 181 OUT_RING(ring, upper_32_bits(submit->cmd[i].iova)); 182 OUT_RING(ring, submit->cmd[i].size); 183 break; 184 } 185 } 186 187 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO, 188 rbmemptr_stats(ring, index, cpcycles_end)); 189 get_stats_counter(ring, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L + 0x1a800, 190 rbmemptr_stats(ring, index, alwayson_end)); 191 192 /* Write the fence to the scratch register */ 193 OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1); 194 OUT_RING(ring, submit->seqno); 195 196 /* 197 * Execute a CACHE_FLUSH_TS event. This will ensure that the 198 * timestamp is written to the memory and then triggers the interrupt 199 */ 200 OUT_PKT7(ring, CP_EVENT_WRITE, 4); 201 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(CACHE_FLUSH_TS) | 202 CP_EVENT_WRITE_0_IRQ); 203 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence))); 204 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence))); 205 OUT_RING(ring, submit->seqno); 206 207 trace_msm_gpu_submit_flush(submit, 208 gmu_read64(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L, 209 REG_A6XX_GMU_ALWAYS_ON_COUNTER_H)); 210 211 a6xx_flush(gpu, ring); 212 } 213 214 const struct adreno_reglist a630_hwcg[] = { 215 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, 216 {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222}, 217 {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222}, 218 {REG_A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222}, 219 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220}, 220 {REG_A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220}, 221 {REG_A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220}, 222 {REG_A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220}, 223 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 224 {REG_A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080}, 225 {REG_A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080}, 226 {REG_A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080}, 227 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf}, 228 {REG_A6XX_RBBM_CLOCK_HYST_SP1, 0x0000f3cf}, 229 {REG_A6XX_RBBM_CLOCK_HYST_SP2, 0x0000f3cf}, 230 {REG_A6XX_RBBM_CLOCK_HYST_SP3, 0x0000f3cf}, 231 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, 232 {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222}, 233 {REG_A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222}, 234 {REG_A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222}, 235 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 236 {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222}, 237 {REG_A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222}, 238 {REG_A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222}, 239 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 240 {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222}, 241 {REG_A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222}, 242 {REG_A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222}, 243 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 244 {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222}, 245 {REG_A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222}, 246 {REG_A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222}, 247 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 248 {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777}, 249 {REG_A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777}, 250 {REG_A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777}, 251 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 252 {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777}, 253 {REG_A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777}, 254 {REG_A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777}, 255 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 256 {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777}, 257 {REG_A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777}, 258 {REG_A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777}, 259 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 260 {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777}, 261 {REG_A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777}, 262 {REG_A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777}, 263 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 264 {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111}, 265 {REG_A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111}, 266 {REG_A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111}, 267 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 268 {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111}, 269 {REG_A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111}, 270 {REG_A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111}, 271 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 272 {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111}, 273 {REG_A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111}, 274 {REG_A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111}, 275 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 276 {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111}, 277 {REG_A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111}, 278 {REG_A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111}, 279 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 280 {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222}, 281 {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222}, 282 {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222}, 283 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 284 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 285 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 286 {REG_A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222}, 287 {REG_A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222}, 288 {REG_A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222}, 289 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222}, 290 {REG_A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222}, 291 {REG_A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222}, 292 {REG_A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222}, 293 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 294 {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220}, 295 {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220}, 296 {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220}, 297 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00}, 298 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040f00}, 299 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040f00}, 300 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040f00}, 301 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022}, 302 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 303 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 304 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 305 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 306 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 307 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 308 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 309 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 310 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 311 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 312 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 313 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 314 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 315 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 316 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 317 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 318 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 319 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 320 {}, 321 }; 322 323 const struct adreno_reglist a640_hwcg[] = { 324 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, 325 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, 326 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 327 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, 328 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, 329 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 330 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 331 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 332 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 333 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 334 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 335 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 336 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 337 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 338 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 339 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 340 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 341 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, 342 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 343 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, 344 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022}, 345 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 346 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 347 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 348 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 349 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 350 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 351 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 352 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 353 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 354 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 355 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 356 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 357 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 358 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 359 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 360 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, 361 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, 362 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, 363 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000}, 364 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 365 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 366 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 367 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, 368 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, 369 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, 370 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 371 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 372 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 373 {}, 374 }; 375 376 const struct adreno_reglist a650_hwcg[] = { 377 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, 378 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, 379 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, 380 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, 381 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, 382 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, 383 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, 384 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, 385 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, 386 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, 387 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, 388 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, 389 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, 390 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, 391 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, 392 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, 393 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, 394 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, 395 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, 396 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, 397 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022}, 398 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, 399 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, 400 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, 401 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, 402 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, 403 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, 404 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, 405 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, 406 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, 407 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, 408 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, 409 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, 410 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, 411 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, 412 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, 413 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, 414 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, 415 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, 416 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777}, 417 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, 418 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, 419 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, 420 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, 421 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, 422 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, 423 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, 424 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, 425 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, 426 {}, 427 }; 428 429 static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) 430 { 431 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 432 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 433 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 434 const struct adreno_reglist *reg; 435 unsigned int i; 436 u32 val, clock_cntl_on; 437 438 if (!adreno_gpu->info->hwcg) 439 return; 440 441 if (adreno_is_a630(adreno_gpu)) 442 clock_cntl_on = 0x8aa8aa02; 443 else 444 clock_cntl_on = 0x8aa8aa82; 445 446 val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL); 447 448 /* Don't re-program the registers if they are already correct */ 449 if ((!state && !val) || (state && (val == clock_cntl_on))) 450 return; 451 452 /* Disable SP clock before programming HWCG registers */ 453 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); 454 455 for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++) 456 gpu_write(gpu, reg->offset, state ? reg->value : 0); 457 458 /* Enable SP clock */ 459 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); 460 461 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); 462 } 463 464 static void a6xx_set_ubwc_config(struct msm_gpu *gpu) 465 { 466 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 467 u32 lower_bit = 2; 468 u32 amsbc = 0; 469 u32 rgb565_predicator = 0; 470 u32 uavflagprd_inv = 0; 471 472 /* a618 is using the hw default values */ 473 if (adreno_is_a618(adreno_gpu)) 474 return; 475 476 if (adreno_is_a640(adreno_gpu)) 477 amsbc = 1; 478 479 if (adreno_is_a650(adreno_gpu)) { 480 /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ 481 lower_bit = 3; 482 amsbc = 1; 483 rgb565_predicator = 1; 484 uavflagprd_inv = 2; 485 } 486 487 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 488 rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1); 489 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1); 490 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 491 uavflagprd_inv >> 4 | lower_bit << 1); 492 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21); 493 } 494 495 static int a6xx_cp_init(struct msm_gpu *gpu) 496 { 497 struct msm_ringbuffer *ring = gpu->rb[0]; 498 499 OUT_PKT7(ring, CP_ME_INIT, 8); 500 501 OUT_RING(ring, 0x0000002f); 502 503 /* Enable multiple hardware contexts */ 504 OUT_RING(ring, 0x00000003); 505 506 /* Enable error detection */ 507 OUT_RING(ring, 0x20000000); 508 509 /* Don't enable header dump */ 510 OUT_RING(ring, 0x00000000); 511 OUT_RING(ring, 0x00000000); 512 513 /* No workarounds enabled */ 514 OUT_RING(ring, 0x00000000); 515 516 /* Pad rest of the cmds with 0's */ 517 OUT_RING(ring, 0x00000000); 518 OUT_RING(ring, 0x00000000); 519 520 a6xx_flush(gpu, ring); 521 return a6xx_idle(gpu, ring) ? 0 : -EINVAL; 522 } 523 524 static void a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu, 525 struct drm_gem_object *obj) 526 { 527 u32 *buf = msm_gem_get_vaddr(obj); 528 529 if (IS_ERR(buf)) 530 return; 531 532 /* 533 * If the lowest nibble is 0xa that is an indication that this microcode 534 * has been patched. The actual version is in dword [3] but we only care 535 * about the patchlevel which is the lowest nibble of dword [3] 536 * 537 * Otherwise check that the firmware is greater than or equal to 1.90 538 * which was the first version that had this fix built in 539 */ 540 if (((buf[0] & 0xf) == 0xa) && (buf[2] & 0xf) >= 1) 541 a6xx_gpu->has_whereami = true; 542 else if ((buf[0] & 0xfff) > 0x190) 543 a6xx_gpu->has_whereami = true; 544 545 msm_gem_put_vaddr(obj); 546 } 547 548 static int a6xx_ucode_init(struct msm_gpu *gpu) 549 { 550 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 551 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 552 553 if (!a6xx_gpu->sqe_bo) { 554 a6xx_gpu->sqe_bo = adreno_fw_create_bo(gpu, 555 adreno_gpu->fw[ADRENO_FW_SQE], &a6xx_gpu->sqe_iova); 556 557 if (IS_ERR(a6xx_gpu->sqe_bo)) { 558 int ret = PTR_ERR(a6xx_gpu->sqe_bo); 559 560 a6xx_gpu->sqe_bo = NULL; 561 DRM_DEV_ERROR(&gpu->pdev->dev, 562 "Could not allocate SQE ucode: %d\n", ret); 563 564 return ret; 565 } 566 567 msm_gem_object_set_name(a6xx_gpu->sqe_bo, "sqefw"); 568 a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->sqe_bo); 569 } 570 571 gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE_LO, 572 REG_A6XX_CP_SQE_INSTR_BASE_HI, a6xx_gpu->sqe_iova); 573 574 return 0; 575 } 576 577 static int a6xx_zap_shader_init(struct msm_gpu *gpu) 578 { 579 static bool loaded; 580 int ret; 581 582 if (loaded) 583 return 0; 584 585 ret = adreno_zap_shader_load(gpu, GPU_PAS_ID); 586 587 loaded = !ret; 588 return ret; 589 } 590 591 #define A6XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \ 592 A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \ 593 A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \ 594 A6XX_RBBM_INT_0_MASK_CP_IB2 | \ 595 A6XX_RBBM_INT_0_MASK_CP_IB1 | \ 596 A6XX_RBBM_INT_0_MASK_CP_RB | \ 597 A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \ 598 A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \ 599 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \ 600 A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \ 601 A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR) 602 603 static int a6xx_hw_init(struct msm_gpu *gpu) 604 { 605 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 606 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 607 int ret; 608 609 /* Make sure the GMU keeps the GPU on while we set it up */ 610 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 611 612 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); 613 614 /* 615 * Disable the trusted memory range - we don't actually supported secure 616 * memory rendering at this point in time and we don't want to block off 617 * part of the virtual memory space. 618 */ 619 gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO, 620 REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x00000000); 621 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); 622 623 /* Turn on 64 bit addressing for all blocks */ 624 gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1); 625 gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1); 626 gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1); 627 gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1); 628 gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1); 629 gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1); 630 gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1); 631 gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1); 632 gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1); 633 gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1); 634 gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1); 635 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1); 636 637 /* enable hardware clockgating */ 638 a6xx_set_hwcg(gpu, true); 639 640 /* VBIF/GBIF start*/ 641 if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu)) { 642 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); 643 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); 644 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); 645 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); 646 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); 647 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3); 648 } else { 649 gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3); 650 } 651 652 if (adreno_is_a630(adreno_gpu)) 653 gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009); 654 655 /* Make all blocks contribute to the GPU BUSY perf counter */ 656 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff); 657 658 /* Disable L2 bypass in the UCHE */ 659 gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_LO, 0xffffffc0); 660 gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_HI, 0x0001ffff); 661 gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_LO, 0xfffff000); 662 gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_HI, 0x0001ffff); 663 gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000); 664 gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff); 665 666 if (!adreno_is_a650(adreno_gpu)) { 667 /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */ 668 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN_LO, 669 REG_A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x00100000); 670 671 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX_LO, 672 REG_A6XX_UCHE_GMEM_RANGE_MAX_HI, 673 0x00100000 + adreno_gpu->gmem - 1); 674 } 675 676 gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804); 677 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4); 678 679 if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu)) 680 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); 681 else 682 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0); 683 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); 684 685 /* Setting the mem pool size */ 686 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); 687 688 /* Setting the primFifo thresholds default values */ 689 if (adreno_is_a650(adreno_gpu)) 690 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300000); 691 else if (adreno_is_a640(adreno_gpu)) 692 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200000); 693 else 694 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, (0x300 << 11)); 695 696 /* Set the AHB default slave response to "ERROR" */ 697 gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1); 698 699 /* Turn on performance counters */ 700 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1); 701 702 /* Select CP0 to always count cycles */ 703 gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT); 704 705 a6xx_set_ubwc_config(gpu); 706 707 /* Enable fault detection */ 708 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, 709 (1 << 30) | 0x1fffff); 710 711 gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1); 712 713 /* Set weights for bicubic filtering */ 714 if (adreno_is_a650(adreno_gpu)) { 715 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0); 716 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, 717 0x3fe05ff4); 718 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2, 719 0x3fa0ebee); 720 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3, 721 0x3f5193ed); 722 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4, 723 0x3f0243f0); 724 } 725 726 /* Protect registers from the CP */ 727 gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, 0x00000003); 728 729 gpu_write(gpu, REG_A6XX_CP_PROTECT(0), 730 A6XX_PROTECT_RDONLY(0x600, 0x51)); 731 gpu_write(gpu, REG_A6XX_CP_PROTECT(1), A6XX_PROTECT_RW(0xae50, 0x2)); 732 gpu_write(gpu, REG_A6XX_CP_PROTECT(2), A6XX_PROTECT_RW(0x9624, 0x13)); 733 gpu_write(gpu, REG_A6XX_CP_PROTECT(3), A6XX_PROTECT_RW(0x8630, 0x8)); 734 gpu_write(gpu, REG_A6XX_CP_PROTECT(4), A6XX_PROTECT_RW(0x9e70, 0x1)); 735 gpu_write(gpu, REG_A6XX_CP_PROTECT(5), A6XX_PROTECT_RW(0x9e78, 0x187)); 736 gpu_write(gpu, REG_A6XX_CP_PROTECT(6), A6XX_PROTECT_RW(0xf000, 0x810)); 737 gpu_write(gpu, REG_A6XX_CP_PROTECT(7), 738 A6XX_PROTECT_RDONLY(0xfc00, 0x3)); 739 gpu_write(gpu, REG_A6XX_CP_PROTECT(8), A6XX_PROTECT_RW(0x50e, 0x0)); 740 gpu_write(gpu, REG_A6XX_CP_PROTECT(9), A6XX_PROTECT_RDONLY(0x50f, 0x0)); 741 gpu_write(gpu, REG_A6XX_CP_PROTECT(10), A6XX_PROTECT_RW(0x510, 0x0)); 742 gpu_write(gpu, REG_A6XX_CP_PROTECT(11), 743 A6XX_PROTECT_RDONLY(0x0, 0x4f9)); 744 gpu_write(gpu, REG_A6XX_CP_PROTECT(12), 745 A6XX_PROTECT_RDONLY(0x501, 0xa)); 746 gpu_write(gpu, REG_A6XX_CP_PROTECT(13), 747 A6XX_PROTECT_RDONLY(0x511, 0x44)); 748 gpu_write(gpu, REG_A6XX_CP_PROTECT(14), A6XX_PROTECT_RW(0xe00, 0xe)); 749 gpu_write(gpu, REG_A6XX_CP_PROTECT(15), A6XX_PROTECT_RW(0x8e00, 0x0)); 750 gpu_write(gpu, REG_A6XX_CP_PROTECT(16), A6XX_PROTECT_RW(0x8e50, 0xf)); 751 gpu_write(gpu, REG_A6XX_CP_PROTECT(17), A6XX_PROTECT_RW(0xbe02, 0x0)); 752 gpu_write(gpu, REG_A6XX_CP_PROTECT(18), 753 A6XX_PROTECT_RW(0xbe20, 0x11f3)); 754 gpu_write(gpu, REG_A6XX_CP_PROTECT(19), A6XX_PROTECT_RW(0x800, 0x82)); 755 gpu_write(gpu, REG_A6XX_CP_PROTECT(20), A6XX_PROTECT_RW(0x8a0, 0x8)); 756 gpu_write(gpu, REG_A6XX_CP_PROTECT(21), A6XX_PROTECT_RW(0x8ab, 0x19)); 757 gpu_write(gpu, REG_A6XX_CP_PROTECT(22), A6XX_PROTECT_RW(0x900, 0x4d)); 758 gpu_write(gpu, REG_A6XX_CP_PROTECT(23), A6XX_PROTECT_RW(0x98d, 0x76)); 759 gpu_write(gpu, REG_A6XX_CP_PROTECT(24), 760 A6XX_PROTECT_RDONLY(0x980, 0x4)); 761 gpu_write(gpu, REG_A6XX_CP_PROTECT(25), A6XX_PROTECT_RW(0xa630, 0x0)); 762 763 /* Enable expanded apriv for targets that support it */ 764 if (gpu->hw_apriv) { 765 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL, 766 (1 << 6) | (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1)); 767 } 768 769 /* Enable interrupts */ 770 gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, A6XX_INT_MASK); 771 772 ret = adreno_hw_init(gpu); 773 if (ret) 774 goto out; 775 776 ret = a6xx_ucode_init(gpu); 777 if (ret) 778 goto out; 779 780 /* Set the ringbuffer address */ 781 gpu_write64(gpu, REG_A6XX_CP_RB_BASE, REG_A6XX_CP_RB_BASE_HI, 782 gpu->rb[0]->iova); 783 784 /* Targets that support extended APRIV can use the RPTR shadow from 785 * hardware but all the other ones need to disable the feature. Targets 786 * that support the WHERE_AM_I opcode can use that instead 787 */ 788 if (adreno_gpu->base.hw_apriv) 789 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT); 790 else 791 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, 792 MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE); 793 794 /* 795 * Expanded APRIV and targets that support WHERE_AM_I both need a 796 * privileged buffer to store the RPTR shadow 797 */ 798 799 if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) { 800 if (!a6xx_gpu->shadow_bo) { 801 a6xx_gpu->shadow = msm_gem_kernel_new_locked(gpu->dev, 802 sizeof(u32) * gpu->nr_rings, 803 MSM_BO_UNCACHED | MSM_BO_MAP_PRIV, 804 gpu->aspace, &a6xx_gpu->shadow_bo, 805 &a6xx_gpu->shadow_iova); 806 807 if (IS_ERR(a6xx_gpu->shadow)) 808 return PTR_ERR(a6xx_gpu->shadow); 809 } 810 811 gpu_write64(gpu, REG_A6XX_CP_RB_RPTR_ADDR_LO, 812 REG_A6XX_CP_RB_RPTR_ADDR_HI, 813 shadowptr(a6xx_gpu, gpu->rb[0])); 814 } 815 816 /* Always come up on rb 0 */ 817 a6xx_gpu->cur_ring = gpu->rb[0]; 818 819 a6xx_gpu->cur_ctx = NULL; 820 821 /* Enable the SQE_to start the CP engine */ 822 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1); 823 824 ret = a6xx_cp_init(gpu); 825 if (ret) 826 goto out; 827 828 /* 829 * Try to load a zap shader into the secure world. If successful 830 * we can use the CP to switch out of secure mode. If not then we 831 * have no resource but to try to switch ourselves out manually. If we 832 * guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will 833 * be blocked and a permissions violation will soon follow. 834 */ 835 ret = a6xx_zap_shader_init(gpu); 836 if (!ret) { 837 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1); 838 OUT_RING(gpu->rb[0], 0x00000000); 839 840 a6xx_flush(gpu, gpu->rb[0]); 841 if (!a6xx_idle(gpu, gpu->rb[0])) 842 return -EINVAL; 843 } else if (ret == -ENODEV) { 844 /* 845 * This device does not use zap shader (but print a warning 846 * just in case someone got their dt wrong.. hopefully they 847 * have a debug UART to realize the error of their ways... 848 * if you mess this up you are about to crash horribly) 849 */ 850 dev_warn_once(gpu->dev->dev, 851 "Zap shader not enabled - using SECVID_TRUST_CNTL instead\n"); 852 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0); 853 ret = 0; 854 } else { 855 return ret; 856 } 857 858 out: 859 /* 860 * Tell the GMU that we are done touching the GPU and it can start power 861 * management 862 */ 863 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 864 865 if (a6xx_gpu->gmu.legacy) { 866 /* Take the GMU out of its special boot mode */ 867 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER); 868 } 869 870 return ret; 871 } 872 873 static void a6xx_dump(struct msm_gpu *gpu) 874 { 875 DRM_DEV_INFO(&gpu->pdev->dev, "status: %08x\n", 876 gpu_read(gpu, REG_A6XX_RBBM_STATUS)); 877 adreno_dump(gpu); 878 } 879 880 #define VBIF_RESET_ACK_TIMEOUT 100 881 #define VBIF_RESET_ACK_MASK 0x00f0 882 883 static void a6xx_recover(struct msm_gpu *gpu) 884 { 885 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 886 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 887 int i; 888 889 adreno_dump_info(gpu); 890 891 for (i = 0; i < 8; i++) 892 DRM_DEV_INFO(&gpu->pdev->dev, "CP_SCRATCH_REG%d: %u\n", i, 893 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i))); 894 895 if (hang_debug) 896 a6xx_dump(gpu); 897 898 /* 899 * Turn off keep alive that might have been enabled by the hang 900 * interrupt 901 */ 902 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0); 903 904 gpu->funcs->pm_suspend(gpu); 905 gpu->funcs->pm_resume(gpu); 906 907 msm_gpu_hw_init(gpu); 908 } 909 910 static int a6xx_fault_handler(void *arg, unsigned long iova, int flags) 911 { 912 struct msm_gpu *gpu = arg; 913 914 pr_warn_ratelimited("*** gpu fault: iova=%08lx, flags=%d (%u,%u,%u,%u)\n", 915 iova, flags, 916 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)), 917 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)), 918 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)), 919 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7))); 920 921 return -EFAULT; 922 } 923 924 static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu) 925 { 926 u32 status = gpu_read(gpu, REG_A6XX_CP_INTERRUPT_STATUS); 927 928 if (status & A6XX_CP_INT_CP_OPCODE_ERROR) { 929 u32 val; 930 931 gpu_write(gpu, REG_A6XX_CP_SQE_STAT_ADDR, 1); 932 val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA); 933 dev_err_ratelimited(&gpu->pdev->dev, 934 "CP | opcode error | possible opcode=0x%8.8X\n", 935 val); 936 } 937 938 if (status & A6XX_CP_INT_CP_UCODE_ERROR) 939 dev_err_ratelimited(&gpu->pdev->dev, 940 "CP ucode error interrupt\n"); 941 942 if (status & A6XX_CP_INT_CP_HW_FAULT_ERROR) 943 dev_err_ratelimited(&gpu->pdev->dev, "CP | HW fault | status=0x%8.8X\n", 944 gpu_read(gpu, REG_A6XX_CP_HW_FAULT)); 945 946 if (status & A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR) { 947 u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS); 948 949 dev_err_ratelimited(&gpu->pdev->dev, 950 "CP | protected mode error | %s | addr=0x%8.8X | status=0x%8.8X\n", 951 val & (1 << 20) ? "READ" : "WRITE", 952 (val & 0x3ffff), val); 953 } 954 955 if (status & A6XX_CP_INT_CP_AHB_ERROR) 956 dev_err_ratelimited(&gpu->pdev->dev, "CP AHB error interrupt\n"); 957 958 if (status & A6XX_CP_INT_CP_VSD_PARITY_ERROR) 959 dev_err_ratelimited(&gpu->pdev->dev, "CP VSD decoder parity error\n"); 960 961 if (status & A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR) 962 dev_err_ratelimited(&gpu->pdev->dev, "CP illegal instruction error\n"); 963 964 } 965 966 static void a6xx_fault_detect_irq(struct msm_gpu *gpu) 967 { 968 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 969 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 970 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); 971 972 /* 973 * Force the GPU to stay on until after we finish 974 * collecting information 975 */ 976 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1); 977 978 DRM_DEV_ERROR(&gpu->pdev->dev, 979 "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n", 980 ring ? ring->id : -1, ring ? ring->seqno : 0, 981 gpu_read(gpu, REG_A6XX_RBBM_STATUS), 982 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), 983 gpu_read(gpu, REG_A6XX_CP_RB_WPTR), 984 gpu_read64(gpu, REG_A6XX_CP_IB1_BASE, REG_A6XX_CP_IB1_BASE_HI), 985 gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE), 986 gpu_read64(gpu, REG_A6XX_CP_IB2_BASE, REG_A6XX_CP_IB2_BASE_HI), 987 gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE)); 988 989 /* Turn off the hangcheck timer to keep it from bothering us */ 990 del_timer(&gpu->hangcheck_timer); 991 992 kthread_queue_work(gpu->worker, &gpu->recover_work); 993 } 994 995 static irqreturn_t a6xx_irq(struct msm_gpu *gpu) 996 { 997 u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS); 998 999 gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status); 1000 1001 if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT) 1002 a6xx_fault_detect_irq(gpu); 1003 1004 if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR) 1005 dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n"); 1006 1007 if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR) 1008 a6xx_cp_hw_err_irq(gpu); 1009 1010 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW) 1011 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB ASYNC overflow\n"); 1012 1013 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW) 1014 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB bus overflow\n"); 1015 1016 if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS) 1017 dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n"); 1018 1019 if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS) 1020 msm_gpu_retire(gpu); 1021 1022 return IRQ_HANDLED; 1023 } 1024 1025 static void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or) 1026 { 1027 return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or); 1028 } 1029 1030 static void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value) 1031 { 1032 return msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2)); 1033 } 1034 1035 static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu) 1036 { 1037 llcc_slice_deactivate(a6xx_gpu->llc_slice); 1038 llcc_slice_deactivate(a6xx_gpu->htw_llc_slice); 1039 } 1040 1041 static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu) 1042 { 1043 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 1044 struct msm_gpu *gpu = &adreno_gpu->base; 1045 u32 cntl1_regval = 0; 1046 1047 if (IS_ERR(a6xx_gpu->llc_mmio)) 1048 return; 1049 1050 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { 1051 u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice); 1052 1053 gpu_scid &= 0x1f; 1054 cntl1_regval = (gpu_scid << 0) | (gpu_scid << 5) | (gpu_scid << 10) | 1055 (gpu_scid << 15) | (gpu_scid << 20); 1056 } 1057 1058 /* 1059 * For targets with a MMU500, activate the slice but don't program the 1060 * register. The XBL will take care of that. 1061 */ 1062 if (!llcc_slice_activate(a6xx_gpu->htw_llc_slice)) { 1063 if (!a6xx_gpu->have_mmu500) { 1064 u32 gpuhtw_scid = llcc_get_slice_id(a6xx_gpu->htw_llc_slice); 1065 1066 gpuhtw_scid &= 0x1f; 1067 cntl1_regval |= FIELD_PREP(GENMASK(29, 25), gpuhtw_scid); 1068 } 1069 } 1070 1071 if (cntl1_regval) { 1072 /* 1073 * Program the slice IDs for the various GPU blocks and GPU MMU 1074 * pagetables 1075 */ 1076 if (a6xx_gpu->have_mmu500) 1077 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, GENMASK(24, 0), 1078 cntl1_regval); 1079 else { 1080 a6xx_llc_write(a6xx_gpu, 1081 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, cntl1_regval); 1082 1083 /* 1084 * Program cacheability overrides to not allocate cache 1085 * lines on a write miss 1086 */ 1087 a6xx_llc_rmw(a6xx_gpu, 1088 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, 0x03); 1089 } 1090 } 1091 } 1092 1093 static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu) 1094 { 1095 llcc_slice_putd(a6xx_gpu->llc_slice); 1096 llcc_slice_putd(a6xx_gpu->htw_llc_slice); 1097 } 1098 1099 static void a6xx_llc_slices_init(struct platform_device *pdev, 1100 struct a6xx_gpu *a6xx_gpu) 1101 { 1102 struct device_node *phandle; 1103 1104 a6xx_gpu->llc_mmio = msm_ioremap(pdev, "cx_mem", "gpu_cx"); 1105 if (IS_ERR(a6xx_gpu->llc_mmio)) 1106 return; 1107 1108 /* 1109 * There is a different programming path for targets with an mmu500 1110 * attached, so detect if that is the case 1111 */ 1112 phandle = of_parse_phandle(pdev->dev.of_node, "iommus", 0); 1113 a6xx_gpu->have_mmu500 = (phandle && 1114 of_device_is_compatible(phandle, "arm,mmu-500")); 1115 of_node_put(phandle); 1116 1117 a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU); 1118 a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW); 1119 1120 if (IS_ERR(a6xx_gpu->llc_slice) && IS_ERR(a6xx_gpu->htw_llc_slice)) 1121 a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL); 1122 } 1123 1124 static int a6xx_pm_resume(struct msm_gpu *gpu) 1125 { 1126 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1127 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1128 int ret; 1129 1130 gpu->needs_hw_init = true; 1131 1132 trace_msm_gpu_resume(0); 1133 1134 ret = a6xx_gmu_resume(a6xx_gpu); 1135 if (ret) 1136 return ret; 1137 1138 msm_gpu_resume_devfreq(gpu); 1139 1140 a6xx_llc_activate(a6xx_gpu); 1141 1142 return 0; 1143 } 1144 1145 static int a6xx_pm_suspend(struct msm_gpu *gpu) 1146 { 1147 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1148 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1149 int i, ret; 1150 1151 trace_msm_gpu_suspend(0); 1152 1153 a6xx_llc_deactivate(a6xx_gpu); 1154 1155 devfreq_suspend_device(gpu->devfreq.devfreq); 1156 1157 ret = a6xx_gmu_stop(a6xx_gpu); 1158 if (ret) 1159 return ret; 1160 1161 if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) 1162 for (i = 0; i < gpu->nr_rings; i++) 1163 a6xx_gpu->shadow[i] = 0; 1164 1165 return 0; 1166 } 1167 1168 static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) 1169 { 1170 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1171 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1172 1173 /* Force the GPU power on so we can read this register */ 1174 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 1175 1176 *value = gpu_read64(gpu, REG_A6XX_RBBM_PERFCTR_CP_0_LO, 1177 REG_A6XX_RBBM_PERFCTR_CP_0_HI); 1178 1179 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 1180 return 0; 1181 } 1182 1183 static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu) 1184 { 1185 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1186 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1187 1188 return a6xx_gpu->cur_ring; 1189 } 1190 1191 static void a6xx_destroy(struct msm_gpu *gpu) 1192 { 1193 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1194 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1195 1196 if (a6xx_gpu->sqe_bo) { 1197 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace); 1198 drm_gem_object_put(a6xx_gpu->sqe_bo); 1199 } 1200 1201 if (a6xx_gpu->shadow_bo) { 1202 msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->aspace); 1203 drm_gem_object_put(a6xx_gpu->shadow_bo); 1204 } 1205 1206 a6xx_llc_slices_destroy(a6xx_gpu); 1207 1208 a6xx_gmu_remove(a6xx_gpu); 1209 1210 adreno_gpu_cleanup(adreno_gpu); 1211 kfree(a6xx_gpu); 1212 } 1213 1214 static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu) 1215 { 1216 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1217 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1218 u64 busy_cycles, busy_time; 1219 1220 1221 /* Only read the gpu busy if the hardware is already active */ 1222 if (pm_runtime_get_if_in_use(a6xx_gpu->gmu.dev) == 0) 1223 return 0; 1224 1225 busy_cycles = gmu_read64(&a6xx_gpu->gmu, 1226 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L, 1227 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H); 1228 1229 busy_time = (busy_cycles - gpu->devfreq.busy_cycles) * 10; 1230 do_div(busy_time, 192); 1231 1232 gpu->devfreq.busy_cycles = busy_cycles; 1233 1234 pm_runtime_put(a6xx_gpu->gmu.dev); 1235 1236 if (WARN_ON(busy_time > ~0LU)) 1237 return ~0LU; 1238 1239 return (unsigned long)busy_time; 1240 } 1241 1242 static struct msm_gem_address_space * 1243 a6xx_create_private_address_space(struct msm_gpu *gpu) 1244 { 1245 struct msm_mmu *mmu; 1246 1247 mmu = msm_iommu_pagetable_create(gpu->aspace->mmu); 1248 1249 if (IS_ERR(mmu)) 1250 return ERR_CAST(mmu); 1251 1252 return msm_gem_address_space_create(mmu, 1253 "gpu", 0x100000000ULL, 0x1ffffffffULL); 1254 } 1255 1256 static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 1257 { 1258 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 1259 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 1260 1261 if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) 1262 return a6xx_gpu->shadow[ring->id]; 1263 1264 return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR); 1265 } 1266 1267 static const struct adreno_gpu_funcs funcs = { 1268 .base = { 1269 .get_param = adreno_get_param, 1270 .hw_init = a6xx_hw_init, 1271 .pm_suspend = a6xx_pm_suspend, 1272 .pm_resume = a6xx_pm_resume, 1273 .recover = a6xx_recover, 1274 .submit = a6xx_submit, 1275 .active_ring = a6xx_active_ring, 1276 .irq = a6xx_irq, 1277 .destroy = a6xx_destroy, 1278 #if defined(CONFIG_DRM_MSM_GPU_STATE) 1279 .show = a6xx_show, 1280 #endif 1281 .gpu_busy = a6xx_gpu_busy, 1282 .gpu_get_freq = a6xx_gmu_get_freq, 1283 .gpu_set_freq = a6xx_gmu_set_freq, 1284 #if defined(CONFIG_DRM_MSM_GPU_STATE) 1285 .gpu_state_get = a6xx_gpu_state_get, 1286 .gpu_state_put = a6xx_gpu_state_put, 1287 #endif 1288 .create_address_space = adreno_iommu_create_address_space, 1289 .create_private_address_space = a6xx_create_private_address_space, 1290 .get_rptr = a6xx_get_rptr, 1291 }, 1292 .get_timestamp = a6xx_get_timestamp, 1293 }; 1294 1295 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) 1296 { 1297 struct msm_drm_private *priv = dev->dev_private; 1298 struct platform_device *pdev = priv->gpu_pdev; 1299 struct adreno_platform_config *config = pdev->dev.platform_data; 1300 const struct adreno_info *info; 1301 struct device_node *node; 1302 struct a6xx_gpu *a6xx_gpu; 1303 struct adreno_gpu *adreno_gpu; 1304 struct msm_gpu *gpu; 1305 int ret; 1306 1307 a6xx_gpu = kzalloc(sizeof(*a6xx_gpu), GFP_KERNEL); 1308 if (!a6xx_gpu) 1309 return ERR_PTR(-ENOMEM); 1310 1311 adreno_gpu = &a6xx_gpu->base; 1312 gpu = &adreno_gpu->base; 1313 1314 adreno_gpu->registers = NULL; 1315 1316 /* 1317 * We need to know the platform type before calling into adreno_gpu_init 1318 * so that the hw_apriv flag can be correctly set. Snoop into the info 1319 * and grab the revision number 1320 */ 1321 info = adreno_info(config->rev); 1322 1323 if (info && info->revn == 650) 1324 adreno_gpu->base.hw_apriv = true; 1325 1326 a6xx_llc_slices_init(pdev, a6xx_gpu); 1327 1328 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); 1329 if (ret) { 1330 a6xx_destroy(&(a6xx_gpu->base.base)); 1331 return ERR_PTR(ret); 1332 } 1333 1334 /* Check if there is a GMU phandle and set it up */ 1335 node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0); 1336 1337 /* FIXME: How do we gracefully handle this? */ 1338 BUG_ON(!node); 1339 1340 ret = a6xx_gmu_init(a6xx_gpu, node); 1341 if (ret) { 1342 a6xx_destroy(&(a6xx_gpu->base.base)); 1343 return ERR_PTR(ret); 1344 } 1345 1346 if (gpu->aspace) 1347 msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, 1348 a6xx_fault_handler); 1349 1350 return gpu; 1351 } 1352