1 #ifndef A6XX_GMU_XML 2 #define A6XX_GMU_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13) 12 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13) 13 - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13) 14 - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13) 15 - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42585 bytes, from 2018-10-04 19:06:37) 16 - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13) 17 - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13) 18 - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-10-04 19:06:37) 19 - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 139581 bytes, from 2018-10-04 19:06:42) 20 - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07) 21 - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13) 22 23 Copyright (C) 2013-2018 by the following authors: 24 - Rob Clark <robdclark@gmail.com> (robclark) 25 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 26 27 Permission is hereby granted, free of charge, to any person obtaining 28 a copy of this software and associated documentation files (the 29 "Software"), to deal in the Software without restriction, including 30 without limitation the rights to use, copy, modify, merge, publish, 31 distribute, sublicense, and/or sell copies of the Software, and to 32 permit persons to whom the Software is furnished to do so, subject to 33 the following conditions: 34 35 The above copyright notice and this permission notice (including the 36 next paragraph) shall be included in all copies or substantial 37 portions of the Software. 38 39 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 40 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 41 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 42 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 43 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 44 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 45 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48 49 #define A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB 0x00800000 50 #define A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB 0x40000000 51 #define A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK 0x00400000 52 #define A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK 0x40000000 53 #define A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK 0x40000000 54 #define A6XX_GMU_OOB_DCVS_SET_MASK 0x00800000 55 #define A6XX_GMU_OOB_DCVS_CHECK_MASK 0x80000000 56 #define A6XX_GMU_OOB_DCVS_CLEAR_MASK 0x80000000 57 #define A6XX_GMU_OOB_GPU_SET_MASK 0x00040000 58 #define A6XX_GMU_OOB_GPU_CHECK_MASK 0x04000000 59 #define A6XX_GMU_OOB_GPU_CLEAR_MASK 0x04000000 60 #define A6XX_GMU_OOB_PERFCNTR_SET_MASK 0x00020000 61 #define A6XX_GMU_OOB_PERFCNTR_CHECK_MASK 0x02000000 62 #define A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK 0x02000000 63 #define A6XX_HFI_IRQ_MSGQ_MASK 0x00000001 64 #define A6XX_HFI_IRQ_DSGQ_MASK 0x00000002 65 #define A6XX_HFI_IRQ_BLOCKED_MSG_MASK 0x00000004 66 #define A6XX_HFI_IRQ_CM3_FAULT_MASK 0x00800000 67 #define A6XX_HFI_IRQ_GMU_ERR_MASK__MASK 0x007f0000 68 #define A6XX_HFI_IRQ_GMU_ERR_MASK__SHIFT 16 69 static inline uint32_t A6XX_HFI_IRQ_GMU_ERR_MASK(uint32_t val) 70 { 71 return ((val) << A6XX_HFI_IRQ_GMU_ERR_MASK__SHIFT) & A6XX_HFI_IRQ_GMU_ERR_MASK__MASK; 72 } 73 #define A6XX_HFI_IRQ_OOB_MASK__MASK 0xff000000 74 #define A6XX_HFI_IRQ_OOB_MASK__SHIFT 24 75 static inline uint32_t A6XX_HFI_IRQ_OOB_MASK(uint32_t val) 76 { 77 return ((val) << A6XX_HFI_IRQ_OOB_MASK__SHIFT) & A6XX_HFI_IRQ_OOB_MASK__MASK; 78 } 79 #define A6XX_HFI_H2F_IRQ_MASK_BIT 0x00000001 80 #define REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL 0x00000080 81 82 #define REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL 0x00000081 83 84 #define REG_A6XX_GMU_CM3_ITCM_START 0x00000c00 85 86 #define REG_A6XX_GMU_CM3_DTCM_START 0x00001c00 87 88 #define REG_A6XX_GMU_NMI_CONTROL_STATUS 0x000023f0 89 90 #define REG_A6XX_GMU_BOOT_SLUMBER_OPTION 0x000023f8 91 92 #define REG_A6XX_GMU_GX_VOTE_IDX 0x000023f9 93 94 #define REG_A6XX_GMU_MX_VOTE_IDX 0x000023fa 95 96 #define REG_A6XX_GMU_DCVS_ACK_OPTION 0x000023fc 97 98 #define REG_A6XX_GMU_DCVS_PERF_SETTING 0x000023fd 99 100 #define REG_A6XX_GMU_DCVS_BW_SETTING 0x000023fe 101 102 #define REG_A6XX_GMU_DCVS_RETURN 0x000023ff 103 104 #define REG_A6XX_GMU_SYS_BUS_CONFIG 0x00004c0f 105 106 #define REG_A6XX_GMU_CM3_SYSRESET 0x00005000 107 108 #define REG_A6XX_GMU_CM3_BOOT_CONFIG 0x00005001 109 110 #define REG_A6XX_GMU_CM3_FW_BUSY 0x0000501a 111 112 #define REG_A6XX_GMU_CM3_FW_INIT_RESULT 0x0000501c 113 114 #define REG_A6XX_GMU_CM3_CFG 0x0000502d 115 116 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE 0x00005040 117 118 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0 0x00005041 119 120 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1 0x00005042 121 122 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L 0x00005044 123 124 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H 0x00005045 125 126 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L 0x00005046 127 128 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H 0x00005047 129 130 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L 0x00005048 131 132 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H 0x00005049 133 134 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L 0x0000504a 135 136 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H 0x0000504b 137 138 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L 0x0000504c 139 140 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H 0x0000504d 141 142 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L 0x0000504e 143 144 #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H 0x0000504f 145 146 #define REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL 0x000050c0 147 #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE 0x00000001 148 #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE 0x00000002 149 #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE 0x00000004 150 #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__MASK 0x00003c00 151 #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__SHIFT 10 152 static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS(uint32_t val) 153 { 154 return ((val) << A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__SHIFT) & A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__MASK; 155 } 156 #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__MASK 0xffffc000 157 #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__SHIFT 14 158 static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH(uint32_t val) 159 { 160 return ((val) << A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__SHIFT) & A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__MASK; 161 } 162 163 #define REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST 0x000050c1 164 165 #define REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST 0x000050c2 166 167 #define REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS 0x000050d0 168 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_OFF 0x00000001 169 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_ON 0x00000002 170 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF 0x00000004 171 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_ON 0x00000008 172 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF 0x00000010 173 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GMU_UP_POWER_STATE 0x00000020 174 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF 0x00000040 175 #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF 0x00000080 176 177 #define REG_A6XX_GMU_GPU_NAP_CTRL 0x000050e4 178 #define A6XX_GMU_GPU_NAP_CTRL_HW_NAP_ENABLE 0x00000001 179 #define A6XX_GMU_GPU_NAP_CTRL_SID__MASK 0x000001f0 180 #define A6XX_GMU_GPU_NAP_CTRL_SID__SHIFT 4 181 static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val) 182 { 183 return ((val) << A6XX_GMU_GPU_NAP_CTRL_SID__SHIFT) & A6XX_GMU_GPU_NAP_CTRL_SID__MASK; 184 } 185 186 #define REG_A6XX_GMU_RPMH_CTRL 0x000050e8 187 #define A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE 0x00000001 188 #define A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE 0x00000010 189 #define A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE 0x00000100 190 #define A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE 0x00000200 191 #define A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE 0x00000400 192 #define A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE 0x00000800 193 #define A6XX_GMU_RPMH_CTRL_DDR_MIN_VOTE_ENABLE 0x00001000 194 #define A6XX_GMU_RPMH_CTRL_MX_MIN_VOTE_ENABLE 0x00002000 195 #define A6XX_GMU_RPMH_CTRL_CX_MIN_VOTE_ENABLE 0x00004000 196 #define A6XX_GMU_RPMH_CTRL_GFX_MIN_VOTE_ENABLE 0x00008000 197 198 #define REG_A6XX_GMU_RPMH_HYST_CTRL 0x000050e9 199 200 #define REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE 0x000050ec 201 202 #define REG_A6XX_GMU_BOOT_KMD_LM_HANDSHAKE 0x000051f0 203 204 #define REG_A6XX_GMU_LLM_GLM_SLEEP_CTRL 0x00005157 205 206 #define REG_A6XX_GMU_LLM_GLM_SLEEP_STATUS 0x00005158 207 208 #define REG_A6XX_GMU_ALWAYS_ON_COUNTER_L 0x00005088 209 210 #define REG_A6XX_GMU_ALWAYS_ON_COUNTER_H 0x00005089 211 212 #define REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE 0x000050c3 213 214 #define REG_A6XX_GMU_HFI_CTRL_STATUS 0x00005180 215 216 #define REG_A6XX_GMU_HFI_VERSION_INFO 0x00005181 217 218 #define REG_A6XX_GMU_HFI_SFR_ADDR 0x00005182 219 220 #define REG_A6XX_GMU_HFI_MMAP_ADDR 0x00005183 221 222 #define REG_A6XX_GMU_HFI_QTBL_INFO 0x00005184 223 224 #define REG_A6XX_GMU_HFI_QTBL_ADDR 0x00005185 225 226 #define REG_A6XX_GMU_HFI_CTRL_INIT 0x00005186 227 228 #define REG_A6XX_GMU_GMU2HOST_INTR_SET 0x00005190 229 230 #define REG_A6XX_GMU_GMU2HOST_INTR_CLR 0x00005191 231 232 #define REG_A6XX_GMU_GMU2HOST_INTR_INFO 0x00005192 233 #define A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ 0x00000001 234 #define A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT 0x00800000 235 236 #define REG_A6XX_GMU_GMU2HOST_INTR_MASK 0x00005193 237 238 #define REG_A6XX_GMU_HOST2GMU_INTR_SET 0x00005194 239 240 #define REG_A6XX_GMU_HOST2GMU_INTR_CLR 0x00005195 241 242 #define REG_A6XX_GMU_HOST2GMU_INTR_RAW_INFO 0x00005196 243 244 #define REG_A6XX_GMU_HOST2GMU_INTR_EN_0 0x00005197 245 246 #define REG_A6XX_GMU_HOST2GMU_INTR_EN_1 0x00005198 247 248 #define REG_A6XX_GMU_HOST2GMU_INTR_EN_2 0x00005199 249 250 #define REG_A6XX_GMU_HOST2GMU_INTR_EN_3 0x0000519a 251 252 #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_0 0x0000519b 253 254 #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_1 0x0000519c 255 256 #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_2 0x0000519d 257 258 #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_3 0x0000519e 259 260 #define REG_A6XX_GMU_GENERAL_1 0x000051c6 261 262 #define REG_A6XX_GMU_GENERAL_7 0x000051cc 263 264 #define REG_A6XX_GMU_ISENSE_CTRL 0x0000515d 265 266 #define REG_A6XX_GPU_CS_ENABLE_REG 0x00008920 267 268 #define REG_A6XX_GPU_GMU_CX_GMU_ISENSE_CTRL 0x0000515d 269 270 #define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL3 0x00008578 271 272 #define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL2 0x00008558 273 274 #define REG_A6XX_GPU_CS_A_SENSOR_CTRL_0 0x00008580 275 276 #define REG_A6XX_GPU_CS_A_SENSOR_CTRL_2 0x00027ada 277 278 #define REG_A6XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000881a 279 280 #define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x00008957 281 282 #define REG_A6XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000881a 283 284 #define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 0x0000881d 285 286 #define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 0x0000881f 287 288 #define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 0x00008821 289 290 #define REG_A6XX_GPU_CS_AMP_CALIBRATION_DONE 0x00008965 291 292 #define REG_A6XX_GPU_CS_AMP_PERIOD_CTRL 0x0000896d 293 294 #define REG_A6XX_GPU_CS_AMP_CALIBRATION_DONE 0x00008965 295 296 #define REG_A6XX_GPU_GMU_CX_GMU_PWR_THRESHOLD 0x0000514d 297 298 #define REG_A6XX_GMU_AO_INTERRUPT_EN 0x00009303 299 300 #define REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR 0x00009304 301 302 #define REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS 0x00009305 303 #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE 0x00000001 304 #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_RSCC_COMP 0x00000002 305 #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_VDROOP 0x00000004 306 #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR 0x00000008 307 #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_DBD_WAKEUP 0x00000010 308 #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR 0x00000020 309 310 #define REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK 0x00009306 311 312 #define REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL 0x00009309 313 314 #define REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL 0x0000930a 315 316 #define REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL 0x0000930b 317 318 #define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS 0x0000930c 319 #define A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB 0x00800000 320 321 #define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2 0x0000930d 322 323 #define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK 0x0000930e 324 325 #define REG_A6XX_GMU_AO_AHB_FENCE_CTRL 0x00009310 326 327 #define REG_A6XX_GMU_AHB_FENCE_STATUS 0x00009313 328 329 #define REG_A6XX_GMU_RBBM_INT_UNMASKED_STATUS 0x00009315 330 331 #define REG_A6XX_GMU_AO_SPARE_CNTL 0x00009316 332 333 #define REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0 0x00008c04 334 335 #define REG_A6XX_GMU_RSCC_CONTROL_REQ 0x00009307 336 337 #define REG_A6XX_GMU_RSCC_CONTROL_ACK 0x00009308 338 339 #define REG_A6XX_GMU_AHB_FENCE_RANGE_0 0x00009311 340 341 #define REG_A6XX_GMU_AHB_FENCE_RANGE_1 0x00009312 342 343 #define REG_A6XX_GPU_CC_GX_GDSCR 0x00009c03 344 345 #define REG_A6XX_GPU_CC_GX_DOMAIN_MISC 0x00009d42 346 347 #define REG_A6XX_RSCC_PDC_SEQ_START_ADDR 0x00008c08 348 349 #define REG_A6XX_RSCC_PDC_MATCH_VALUE_LO 0x00008c09 350 351 #define REG_A6XX_RSCC_PDC_MATCH_VALUE_HI 0x00008c0a 352 353 #define REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0 0x00008c0b 354 355 #define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR 0x00008c0d 356 357 #define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA 0x00008c0e 358 359 #define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0 0x00008c82 360 361 #define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0 0x00008c83 362 363 #define REG_A6XX_RSCC_TIMESTAMP_UNIT1_EN_DRV0 0x00008c89 364 365 #define REG_A6XX_RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0 0x00008c8c 366 367 #define REG_A6XX_RSCC_OVERRIDE_START_ADDR 0x00008d00 368 369 #define REG_A6XX_RSCC_SEQ_BUSY_DRV0 0x00008d01 370 371 #define REG_A6XX_RSCC_SEQ_MEM_0_DRV0 0x00008d80 372 373 #define REG_A6XX_RSCC_TCS0_DRV0_STATUS 0x00008f46 374 375 #define REG_A6XX_RSCC_TCS1_DRV0_STATUS 0x000090ae 376 377 #define REG_A6XX_RSCC_TCS2_DRV0_STATUS 0x00009216 378 379 #define REG_A6XX_RSCC_TCS3_DRV0_STATUS 0x0000937e 380 381 382 #endif /* A6XX_GMU_XML */ 383