12d756322SRob Clark #ifndef A6XX_GMU_XML 22d756322SRob Clark #define A6XX_GMU_XML 32d756322SRob Clark 42d756322SRob Clark /* Autogenerated file, DO NOT EDIT manually! 52d756322SRob Clark 62d756322SRob Clark This file was generated by the rules-ng-ng headergen tool in this git repository: 72d756322SRob Clark http://github.com/freedreno/envytools/ 82d756322SRob Clark git clone https://github.com/freedreno/envytools.git 92d756322SRob Clark 102d756322SRob Clark The rules-ng-ng source files this header was generated from are: 11*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44) 12*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) 13*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44) 14*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44) 15*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57) 16*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44) 17*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44) 18*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02) 19*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19) 20*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08) 21*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44) 22*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36) 23*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13) 242d756322SRob Clark 25*cc4c26d4SRob Clark Copyright (C) 2013-2021 by the following authors: 262d756322SRob Clark - Rob Clark <robdclark@gmail.com> (robclark) 272d756322SRob Clark - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 282d756322SRob Clark 292d756322SRob Clark Permission is hereby granted, free of charge, to any person obtaining 302d756322SRob Clark a copy of this software and associated documentation files (the 312d756322SRob Clark "Software"), to deal in the Software without restriction, including 322d756322SRob Clark without limitation the rights to use, copy, modify, merge, publish, 332d756322SRob Clark distribute, sublicense, and/or sell copies of the Software, and to 342d756322SRob Clark permit persons to whom the Software is furnished to do so, subject to 352d756322SRob Clark the following conditions: 362d756322SRob Clark 372d756322SRob Clark The above copyright notice and this permission notice (including the 382d756322SRob Clark next paragraph) shall be included in all copies or substantial 392d756322SRob Clark portions of the Software. 402d756322SRob Clark 412d756322SRob Clark THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 422d756322SRob Clark EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 432d756322SRob Clark MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 442d756322SRob Clark IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 452d756322SRob Clark LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 462d756322SRob Clark OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 472d756322SRob Clark WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 482d756322SRob Clark */ 492d756322SRob Clark 502d756322SRob Clark 51c28c82e9SRob Clark #define A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB__MASK 0x00800000 52c28c82e9SRob Clark #define A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB__SHIFT 23 53c28c82e9SRob Clark static inline uint32_t A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB(uint32_t val) 54c28c82e9SRob Clark { 55c28c82e9SRob Clark return ((val) << A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB__SHIFT) & A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB__MASK; 56c28c82e9SRob Clark } 57c28c82e9SRob Clark #define A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB__MASK 0x40000000 58c28c82e9SRob Clark #define A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB__SHIFT 30 59c28c82e9SRob Clark static inline uint32_t A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB(uint32_t val) 60c28c82e9SRob Clark { 61c28c82e9SRob Clark return ((val) << A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB__SHIFT) & A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB__MASK; 62c28c82e9SRob Clark } 63c28c82e9SRob Clark #define A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK__MASK 0x00400000 64c28c82e9SRob Clark #define A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK__SHIFT 22 65c28c82e9SRob Clark static inline uint32_t A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK(uint32_t val) 66c28c82e9SRob Clark { 67c28c82e9SRob Clark return ((val) << A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK__SHIFT) & A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK__MASK; 68c28c82e9SRob Clark } 69c28c82e9SRob Clark #define A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK__MASK 0x40000000 70c28c82e9SRob Clark #define A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK__SHIFT 30 71c28c82e9SRob Clark static inline uint32_t A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK(uint32_t val) 72c28c82e9SRob Clark { 73c28c82e9SRob Clark return ((val) << A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK__SHIFT) & A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK__MASK; 74c28c82e9SRob Clark } 75c28c82e9SRob Clark #define A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK__MASK 0x40000000 76c28c82e9SRob Clark #define A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK__SHIFT 30 77c28c82e9SRob Clark static inline uint32_t A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK(uint32_t val) 78c28c82e9SRob Clark { 79c28c82e9SRob Clark return ((val) << A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK__SHIFT) & A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK__MASK; 80c28c82e9SRob Clark } 81c28c82e9SRob Clark #define A6XX_GMU_OOB_DCVS_SET_MASK__MASK 0x00800000 82c28c82e9SRob Clark #define A6XX_GMU_OOB_DCVS_SET_MASK__SHIFT 23 83c28c82e9SRob Clark static inline uint32_t A6XX_GMU_OOB_DCVS_SET_MASK(uint32_t val) 84c28c82e9SRob Clark { 85c28c82e9SRob Clark return ((val) << A6XX_GMU_OOB_DCVS_SET_MASK__SHIFT) & A6XX_GMU_OOB_DCVS_SET_MASK__MASK; 86c28c82e9SRob Clark } 87c28c82e9SRob Clark #define A6XX_GMU_OOB_DCVS_CHECK_MASK__MASK 0x80000000 88c28c82e9SRob Clark #define A6XX_GMU_OOB_DCVS_CHECK_MASK__SHIFT 31 89c28c82e9SRob Clark static inline uint32_t A6XX_GMU_OOB_DCVS_CHECK_MASK(uint32_t val) 90c28c82e9SRob Clark { 91c28c82e9SRob Clark return ((val) << A6XX_GMU_OOB_DCVS_CHECK_MASK__SHIFT) & A6XX_GMU_OOB_DCVS_CHECK_MASK__MASK; 92c28c82e9SRob Clark } 93c28c82e9SRob Clark #define A6XX_GMU_OOB_DCVS_CLEAR_MASK__MASK 0x80000000 94c28c82e9SRob Clark #define A6XX_GMU_OOB_DCVS_CLEAR_MASK__SHIFT 31 95c28c82e9SRob Clark static inline uint32_t A6XX_GMU_OOB_DCVS_CLEAR_MASK(uint32_t val) 96c28c82e9SRob Clark { 97c28c82e9SRob Clark return ((val) << A6XX_GMU_OOB_DCVS_CLEAR_MASK__SHIFT) & A6XX_GMU_OOB_DCVS_CLEAR_MASK__MASK; 98c28c82e9SRob Clark } 99c28c82e9SRob Clark #define A6XX_GMU_OOB_GPU_SET_MASK__MASK 0x00040000 100c28c82e9SRob Clark #define A6XX_GMU_OOB_GPU_SET_MASK__SHIFT 18 101c28c82e9SRob Clark static inline uint32_t A6XX_GMU_OOB_GPU_SET_MASK(uint32_t val) 102c28c82e9SRob Clark { 103c28c82e9SRob Clark return ((val) << A6XX_GMU_OOB_GPU_SET_MASK__SHIFT) & A6XX_GMU_OOB_GPU_SET_MASK__MASK; 104c28c82e9SRob Clark } 105c28c82e9SRob Clark #define A6XX_GMU_OOB_GPU_CHECK_MASK__MASK 0x04000000 106c28c82e9SRob Clark #define A6XX_GMU_OOB_GPU_CHECK_MASK__SHIFT 26 107c28c82e9SRob Clark static inline uint32_t A6XX_GMU_OOB_GPU_CHECK_MASK(uint32_t val) 108c28c82e9SRob Clark { 109c28c82e9SRob Clark return ((val) << A6XX_GMU_OOB_GPU_CHECK_MASK__SHIFT) & A6XX_GMU_OOB_GPU_CHECK_MASK__MASK; 110c28c82e9SRob Clark } 111c28c82e9SRob Clark #define A6XX_GMU_OOB_GPU_CLEAR_MASK__MASK 0x04000000 112c28c82e9SRob Clark #define A6XX_GMU_OOB_GPU_CLEAR_MASK__SHIFT 26 113c28c82e9SRob Clark static inline uint32_t A6XX_GMU_OOB_GPU_CLEAR_MASK(uint32_t val) 114c28c82e9SRob Clark { 115c28c82e9SRob Clark return ((val) << A6XX_GMU_OOB_GPU_CLEAR_MASK__SHIFT) & A6XX_GMU_OOB_GPU_CLEAR_MASK__MASK; 116c28c82e9SRob Clark } 117c28c82e9SRob Clark #define A6XX_GMU_OOB_PERFCNTR_SET_MASK__MASK 0x00020000 118c28c82e9SRob Clark #define A6XX_GMU_OOB_PERFCNTR_SET_MASK__SHIFT 17 119c28c82e9SRob Clark static inline uint32_t A6XX_GMU_OOB_PERFCNTR_SET_MASK(uint32_t val) 120c28c82e9SRob Clark { 121c28c82e9SRob Clark return ((val) << A6XX_GMU_OOB_PERFCNTR_SET_MASK__SHIFT) & A6XX_GMU_OOB_PERFCNTR_SET_MASK__MASK; 122c28c82e9SRob Clark } 123c28c82e9SRob Clark #define A6XX_GMU_OOB_PERFCNTR_CHECK_MASK__MASK 0x02000000 124c28c82e9SRob Clark #define A6XX_GMU_OOB_PERFCNTR_CHECK_MASK__SHIFT 25 125c28c82e9SRob Clark static inline uint32_t A6XX_GMU_OOB_PERFCNTR_CHECK_MASK(uint32_t val) 126c28c82e9SRob Clark { 127c28c82e9SRob Clark return ((val) << A6XX_GMU_OOB_PERFCNTR_CHECK_MASK__SHIFT) & A6XX_GMU_OOB_PERFCNTR_CHECK_MASK__MASK; 128c28c82e9SRob Clark } 129c28c82e9SRob Clark #define A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK__MASK 0x02000000 130c28c82e9SRob Clark #define A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK__SHIFT 25 131c28c82e9SRob Clark static inline uint32_t A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK(uint32_t val) 132c28c82e9SRob Clark { 133c28c82e9SRob Clark return ((val) << A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK__SHIFT) & A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK__MASK; 134c28c82e9SRob Clark } 1352d756322SRob Clark #define A6XX_HFI_IRQ_MSGQ_MASK 0x00000001 136c28c82e9SRob Clark #define A6XX_HFI_IRQ_DSGQ_MASK__MASK 0x00000002 137c28c82e9SRob Clark #define A6XX_HFI_IRQ_DSGQ_MASK__SHIFT 1 138c28c82e9SRob Clark static inline uint32_t A6XX_HFI_IRQ_DSGQ_MASK(uint32_t val) 139c28c82e9SRob Clark { 140c28c82e9SRob Clark return ((val) << A6XX_HFI_IRQ_DSGQ_MASK__SHIFT) & A6XX_HFI_IRQ_DSGQ_MASK__MASK; 141c28c82e9SRob Clark } 142c28c82e9SRob Clark #define A6XX_HFI_IRQ_BLOCKED_MSG_MASK__MASK 0x00000004 143c28c82e9SRob Clark #define A6XX_HFI_IRQ_BLOCKED_MSG_MASK__SHIFT 2 144c28c82e9SRob Clark static inline uint32_t A6XX_HFI_IRQ_BLOCKED_MSG_MASK(uint32_t val) 145c28c82e9SRob Clark { 146c28c82e9SRob Clark return ((val) << A6XX_HFI_IRQ_BLOCKED_MSG_MASK__SHIFT) & A6XX_HFI_IRQ_BLOCKED_MSG_MASK__MASK; 147c28c82e9SRob Clark } 148c28c82e9SRob Clark #define A6XX_HFI_IRQ_CM3_FAULT_MASK__MASK 0x00800000 149c28c82e9SRob Clark #define A6XX_HFI_IRQ_CM3_FAULT_MASK__SHIFT 23 150c28c82e9SRob Clark static inline uint32_t A6XX_HFI_IRQ_CM3_FAULT_MASK(uint32_t val) 151c28c82e9SRob Clark { 152c28c82e9SRob Clark return ((val) << A6XX_HFI_IRQ_CM3_FAULT_MASK__SHIFT) & A6XX_HFI_IRQ_CM3_FAULT_MASK__MASK; 153c28c82e9SRob Clark } 1542d756322SRob Clark #define A6XX_HFI_IRQ_GMU_ERR_MASK__MASK 0x007f0000 1552d756322SRob Clark #define A6XX_HFI_IRQ_GMU_ERR_MASK__SHIFT 16 1562d756322SRob Clark static inline uint32_t A6XX_HFI_IRQ_GMU_ERR_MASK(uint32_t val) 1572d756322SRob Clark { 1582d756322SRob Clark return ((val) << A6XX_HFI_IRQ_GMU_ERR_MASK__SHIFT) & A6XX_HFI_IRQ_GMU_ERR_MASK__MASK; 1592d756322SRob Clark } 1602d756322SRob Clark #define A6XX_HFI_IRQ_OOB_MASK__MASK 0xff000000 1612d756322SRob Clark #define A6XX_HFI_IRQ_OOB_MASK__SHIFT 24 1622d756322SRob Clark static inline uint32_t A6XX_HFI_IRQ_OOB_MASK(uint32_t val) 1632d756322SRob Clark { 1642d756322SRob Clark return ((val) << A6XX_HFI_IRQ_OOB_MASK__SHIFT) & A6XX_HFI_IRQ_OOB_MASK__MASK; 1652d756322SRob Clark } 1662d756322SRob Clark #define A6XX_HFI_H2F_IRQ_MASK_BIT 0x00000001 1672d756322SRob Clark #define REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL 0x00000080 1682d756322SRob Clark 1692d756322SRob Clark #define REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL 0x00000081 1702d756322SRob Clark 1712d756322SRob Clark #define REG_A6XX_GMU_CM3_ITCM_START 0x00000c00 1722d756322SRob Clark 1732d756322SRob Clark #define REG_A6XX_GMU_CM3_DTCM_START 0x00001c00 1742d756322SRob Clark 1752d756322SRob Clark #define REG_A6XX_GMU_NMI_CONTROL_STATUS 0x000023f0 1762d756322SRob Clark 1772d756322SRob Clark #define REG_A6XX_GMU_BOOT_SLUMBER_OPTION 0x000023f8 1782d756322SRob Clark 1792d756322SRob Clark #define REG_A6XX_GMU_GX_VOTE_IDX 0x000023f9 1802d756322SRob Clark 1812d756322SRob Clark #define REG_A6XX_GMU_MX_VOTE_IDX 0x000023fa 1822d756322SRob Clark 1832d756322SRob Clark #define REG_A6XX_GMU_DCVS_ACK_OPTION 0x000023fc 1842d756322SRob Clark 1852d756322SRob Clark #define REG_A6XX_GMU_DCVS_PERF_SETTING 0x000023fd 1862d756322SRob Clark 1872d756322SRob Clark #define REG_A6XX_GMU_DCVS_BW_SETTING 0x000023fe 1882d756322SRob Clark 1892d756322SRob Clark #define REG_A6XX_GMU_DCVS_RETURN 0x000023ff 1902d756322SRob Clark 191c6ed04f8SJonathan Marek #define REG_A6XX_GMU_ICACHE_CONFIG 0x00004c00 192c6ed04f8SJonathan Marek 193c6ed04f8SJonathan Marek #define REG_A6XX_GMU_DCACHE_CONFIG 0x00004c01 194c6ed04f8SJonathan Marek 1952d756322SRob Clark #define REG_A6XX_GMU_SYS_BUS_CONFIG 0x00004c0f 1962d756322SRob Clark 1972d756322SRob Clark #define REG_A6XX_GMU_CM3_SYSRESET 0x00005000 1982d756322SRob Clark 1992d756322SRob Clark #define REG_A6XX_GMU_CM3_BOOT_CONFIG 0x00005001 2002d756322SRob Clark 2012d756322SRob Clark #define REG_A6XX_GMU_CM3_FW_BUSY 0x0000501a 2022d756322SRob Clark 2032d756322SRob Clark #define REG_A6XX_GMU_CM3_FW_INIT_RESULT 0x0000501c 2042d756322SRob Clark 2052d756322SRob Clark #define REG_A6XX_GMU_CM3_CFG 0x0000502d 2062d756322SRob Clark 2072d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE 0x00005040 2082d756322SRob Clark 2092d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0 0x00005041 2102d756322SRob Clark 2112d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1 0x00005042 2122d756322SRob Clark 2132d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L 0x00005044 2142d756322SRob Clark 2152d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H 0x00005045 2162d756322SRob Clark 2172d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L 0x00005046 2182d756322SRob Clark 2192d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H 0x00005047 2202d756322SRob Clark 2212d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L 0x00005048 2222d756322SRob Clark 2232d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H 0x00005049 2242d756322SRob Clark 2252d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L 0x0000504a 2262d756322SRob Clark 2272d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H 0x0000504b 2282d756322SRob Clark 2292d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L 0x0000504c 2302d756322SRob Clark 2312d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H 0x0000504d 2322d756322SRob Clark 2332d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L 0x0000504e 2342d756322SRob Clark 2352d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H 0x0000504f 2362d756322SRob Clark 2372d756322SRob Clark #define REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL 0x000050c0 2382d756322SRob Clark #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE 0x00000001 2392d756322SRob Clark #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE 0x00000002 2402d756322SRob Clark #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE 0x00000004 2412d756322SRob Clark #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__MASK 0x00003c00 2422d756322SRob Clark #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__SHIFT 10 2432d756322SRob Clark static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS(uint32_t val) 2442d756322SRob Clark { 2452d756322SRob Clark return ((val) << A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__SHIFT) & A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__MASK; 2462d756322SRob Clark } 2472d756322SRob Clark #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__MASK 0xffffc000 2482d756322SRob Clark #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__SHIFT 14 2492d756322SRob Clark static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH(uint32_t val) 2502d756322SRob Clark { 2512d756322SRob Clark return ((val) << A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__SHIFT) & A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__MASK; 2522d756322SRob Clark } 2532d756322SRob Clark 2542d756322SRob Clark #define REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST 0x000050c1 2552d756322SRob Clark 2562d756322SRob Clark #define REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST 0x000050c2 2572d756322SRob Clark 2582d756322SRob Clark #define REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS 0x000050d0 2592d756322SRob Clark #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_OFF 0x00000001 2602d756322SRob Clark #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_ON 0x00000002 261a69c5ed2SRob Clark #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF 0x00000004 262a69c5ed2SRob Clark #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_ON 0x00000008 2632d756322SRob Clark #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF 0x00000010 2642d756322SRob Clark #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GMU_UP_POWER_STATE 0x00000020 2652d756322SRob Clark #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF 0x00000040 2662d756322SRob Clark #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF 0x00000080 2672d756322SRob Clark 2682d756322SRob Clark #define REG_A6XX_GMU_GPU_NAP_CTRL 0x000050e4 2692d756322SRob Clark #define A6XX_GMU_GPU_NAP_CTRL_HW_NAP_ENABLE 0x00000001 2702d756322SRob Clark #define A6XX_GMU_GPU_NAP_CTRL_SID__MASK 0x000001f0 2712d756322SRob Clark #define A6XX_GMU_GPU_NAP_CTRL_SID__SHIFT 4 2722d756322SRob Clark static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val) 2732d756322SRob Clark { 2742d756322SRob Clark return ((val) << A6XX_GMU_GPU_NAP_CTRL_SID__SHIFT) & A6XX_GMU_GPU_NAP_CTRL_SID__MASK; 2752d756322SRob Clark } 2762d756322SRob Clark 2772d756322SRob Clark #define REG_A6XX_GMU_RPMH_CTRL 0x000050e8 2782d756322SRob Clark #define A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE 0x00000001 2792d756322SRob Clark #define A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE 0x00000010 2802d756322SRob Clark #define A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE 0x00000100 2812d756322SRob Clark #define A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE 0x00000200 2822d756322SRob Clark #define A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE 0x00000400 2832d756322SRob Clark #define A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE 0x00000800 2842d756322SRob Clark #define A6XX_GMU_RPMH_CTRL_DDR_MIN_VOTE_ENABLE 0x00001000 2852d756322SRob Clark #define A6XX_GMU_RPMH_CTRL_MX_MIN_VOTE_ENABLE 0x00002000 2862d756322SRob Clark #define A6XX_GMU_RPMH_CTRL_CX_MIN_VOTE_ENABLE 0x00004000 2872d756322SRob Clark #define A6XX_GMU_RPMH_CTRL_GFX_MIN_VOTE_ENABLE 0x00008000 2882d756322SRob Clark 2892d756322SRob Clark #define REG_A6XX_GMU_RPMH_HYST_CTRL 0x000050e9 2902d756322SRob Clark 2912d756322SRob Clark #define REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE 0x000050ec 2922d756322SRob Clark 293c6ed04f8SJonathan Marek #define REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF 0x000050f0 294c6ed04f8SJonathan Marek 295*cc4c26d4SRob Clark #define REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF 0x000050f1 296*cc4c26d4SRob Clark 297ad4968d5SJonathan Marek #define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG 0x00005100 298ad4968d5SJonathan Marek 299ad4968d5SJonathan Marek #define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP 0x00005101 300ad4968d5SJonathan Marek 3012d756322SRob Clark #define REG_A6XX_GMU_BOOT_KMD_LM_HANDSHAKE 0x000051f0 3022d756322SRob Clark 3032d756322SRob Clark #define REG_A6XX_GMU_LLM_GLM_SLEEP_CTRL 0x00005157 3042d756322SRob Clark 3052d756322SRob Clark #define REG_A6XX_GMU_LLM_GLM_SLEEP_STATUS 0x00005158 3062d756322SRob Clark 3072d756322SRob Clark #define REG_A6XX_GMU_ALWAYS_ON_COUNTER_L 0x00005088 3082d756322SRob Clark 3092d756322SRob Clark #define REG_A6XX_GMU_ALWAYS_ON_COUNTER_H 0x00005089 3102d756322SRob Clark 3112d756322SRob Clark #define REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE 0x000050c3 3122d756322SRob Clark 3132d756322SRob Clark #define REG_A6XX_GMU_HFI_CTRL_STATUS 0x00005180 3142d756322SRob Clark 3152d756322SRob Clark #define REG_A6XX_GMU_HFI_VERSION_INFO 0x00005181 3162d756322SRob Clark 3172d756322SRob Clark #define REG_A6XX_GMU_HFI_SFR_ADDR 0x00005182 3182d756322SRob Clark 3192d756322SRob Clark #define REG_A6XX_GMU_HFI_MMAP_ADDR 0x00005183 3202d756322SRob Clark 3212d756322SRob Clark #define REG_A6XX_GMU_HFI_QTBL_INFO 0x00005184 3222d756322SRob Clark 3232d756322SRob Clark #define REG_A6XX_GMU_HFI_QTBL_ADDR 0x00005185 3242d756322SRob Clark 3252d756322SRob Clark #define REG_A6XX_GMU_HFI_CTRL_INIT 0x00005186 3262d756322SRob Clark 3272d756322SRob Clark #define REG_A6XX_GMU_GMU2HOST_INTR_SET 0x00005190 3282d756322SRob Clark 3292d756322SRob Clark #define REG_A6XX_GMU_GMU2HOST_INTR_CLR 0x00005191 3302d756322SRob Clark 3312d756322SRob Clark #define REG_A6XX_GMU_GMU2HOST_INTR_INFO 0x00005192 3322d756322SRob Clark #define A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ 0x00000001 3332d756322SRob Clark #define A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT 0x00800000 3342d756322SRob Clark 3352d756322SRob Clark #define REG_A6XX_GMU_GMU2HOST_INTR_MASK 0x00005193 3362d756322SRob Clark 3372d756322SRob Clark #define REG_A6XX_GMU_HOST2GMU_INTR_SET 0x00005194 3382d756322SRob Clark 3392d756322SRob Clark #define REG_A6XX_GMU_HOST2GMU_INTR_CLR 0x00005195 3402d756322SRob Clark 3412d756322SRob Clark #define REG_A6XX_GMU_HOST2GMU_INTR_RAW_INFO 0x00005196 3422d756322SRob Clark 3432d756322SRob Clark #define REG_A6XX_GMU_HOST2GMU_INTR_EN_0 0x00005197 3442d756322SRob Clark 3452d756322SRob Clark #define REG_A6XX_GMU_HOST2GMU_INTR_EN_1 0x00005198 3462d756322SRob Clark 3472d756322SRob Clark #define REG_A6XX_GMU_HOST2GMU_INTR_EN_2 0x00005199 3482d756322SRob Clark 3492d756322SRob Clark #define REG_A6XX_GMU_HOST2GMU_INTR_EN_3 0x0000519a 3502d756322SRob Clark 3512d756322SRob Clark #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_0 0x0000519b 3522d756322SRob Clark 3532d756322SRob Clark #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_1 0x0000519c 3542d756322SRob Clark 3552d756322SRob Clark #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_2 0x0000519d 3562d756322SRob Clark 3572d756322SRob Clark #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_3 0x0000519e 3582d756322SRob Clark 3592d756322SRob Clark #define REG_A6XX_GMU_GENERAL_1 0x000051c6 3602d756322SRob Clark 3612d756322SRob Clark #define REG_A6XX_GMU_GENERAL_7 0x000051cc 3622d756322SRob Clark 3632d756322SRob Clark #define REG_A6XX_GMU_ISENSE_CTRL 0x0000515d 3642d756322SRob Clark 3652d756322SRob Clark #define REG_A6XX_GPU_CS_ENABLE_REG 0x00008920 3662d756322SRob Clark 3672d756322SRob Clark #define REG_A6XX_GPU_GMU_CX_GMU_ISENSE_CTRL 0x0000515d 3682d756322SRob Clark 3692d756322SRob Clark #define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL3 0x00008578 3702d756322SRob Clark 3712d756322SRob Clark #define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL2 0x00008558 3722d756322SRob Clark 3732d756322SRob Clark #define REG_A6XX_GPU_CS_A_SENSOR_CTRL_0 0x00008580 3742d756322SRob Clark 3752d756322SRob Clark #define REG_A6XX_GPU_CS_A_SENSOR_CTRL_2 0x00027ada 3762d756322SRob Clark 3772d756322SRob Clark #define REG_A6XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000881a 3782d756322SRob Clark 3792d756322SRob Clark #define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x00008957 3802d756322SRob Clark 3812d756322SRob Clark #define REG_A6XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000881a 3822d756322SRob Clark 3832d756322SRob Clark #define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 0x0000881d 3842d756322SRob Clark 3852d756322SRob Clark #define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 0x0000881f 3862d756322SRob Clark 3872d756322SRob Clark #define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 0x00008821 3882d756322SRob Clark 3892d756322SRob Clark #define REG_A6XX_GPU_CS_AMP_CALIBRATION_DONE 0x00008965 3902d756322SRob Clark 3912d756322SRob Clark #define REG_A6XX_GPU_CS_AMP_PERIOD_CTRL 0x0000896d 3922d756322SRob Clark 3932d756322SRob Clark #define REG_A6XX_GPU_CS_AMP_CALIBRATION_DONE 0x00008965 3942d756322SRob Clark 3952d756322SRob Clark #define REG_A6XX_GPU_GMU_CX_GMU_PWR_THRESHOLD 0x0000514d 3962d756322SRob Clark 3972d756322SRob Clark #define REG_A6XX_GMU_AO_INTERRUPT_EN 0x00009303 3982d756322SRob Clark 3992d756322SRob Clark #define REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR 0x00009304 4002d756322SRob Clark 4012d756322SRob Clark #define REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS 0x00009305 4022d756322SRob Clark #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE 0x00000001 4032d756322SRob Clark #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_RSCC_COMP 0x00000002 4042d756322SRob Clark #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_VDROOP 0x00000004 4052d756322SRob Clark #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR 0x00000008 4062d756322SRob Clark #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_DBD_WAKEUP 0x00000010 4072d756322SRob Clark #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR 0x00000020 4082d756322SRob Clark 4092d756322SRob Clark #define REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK 0x00009306 4102d756322SRob Clark 4112d756322SRob Clark #define REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL 0x00009309 4122d756322SRob Clark 4132d756322SRob Clark #define REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL 0x0000930a 4142d756322SRob Clark 4152d756322SRob Clark #define REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL 0x0000930b 4162d756322SRob Clark 4172d756322SRob Clark #define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS 0x0000930c 4182d756322SRob Clark #define A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB 0x00800000 4192d756322SRob Clark 4202d756322SRob Clark #define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2 0x0000930d 4212d756322SRob Clark 4222d756322SRob Clark #define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK 0x0000930e 4232d756322SRob Clark 4242d756322SRob Clark #define REG_A6XX_GMU_AO_AHB_FENCE_CTRL 0x00009310 4252d756322SRob Clark 4262d756322SRob Clark #define REG_A6XX_GMU_AHB_FENCE_STATUS 0x00009313 4272d756322SRob Clark 4282d756322SRob Clark #define REG_A6XX_GMU_RBBM_INT_UNMASKED_STATUS 0x00009315 4292d756322SRob Clark 4302d756322SRob Clark #define REG_A6XX_GMU_AO_SPARE_CNTL 0x00009316 4312d756322SRob Clark 4322d756322SRob Clark #define REG_A6XX_GMU_RSCC_CONTROL_REQ 0x00009307 4332d756322SRob Clark 4342d756322SRob Clark #define REG_A6XX_GMU_RSCC_CONTROL_ACK 0x00009308 4352d756322SRob Clark 4362d756322SRob Clark #define REG_A6XX_GMU_AHB_FENCE_RANGE_0 0x00009311 4372d756322SRob Clark 4382d756322SRob Clark #define REG_A6XX_GMU_AHB_FENCE_RANGE_1 0x00009312 4392d756322SRob Clark 4402d756322SRob Clark #define REG_A6XX_GPU_CC_GX_GDSCR 0x00009c03 4412d756322SRob Clark 4422d756322SRob Clark #define REG_A6XX_GPU_CC_GX_DOMAIN_MISC 0x00009d42 4432d756322SRob Clark 444*cc4c26d4SRob Clark #define REG_A6XX_GPU_CPR_FSM_CTL 0x0000c001 445*cc4c26d4SRob Clark 44602ef80c5SJonathan Marek #define REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0 0x00000004 4472d756322SRob Clark 44802ef80c5SJonathan Marek #define REG_A6XX_RSCC_PDC_SEQ_START_ADDR 0x00000008 4492d756322SRob Clark 45002ef80c5SJonathan Marek #define REG_A6XX_RSCC_PDC_MATCH_VALUE_LO 0x00000009 4512d756322SRob Clark 45202ef80c5SJonathan Marek #define REG_A6XX_RSCC_PDC_MATCH_VALUE_HI 0x0000000a 4532d756322SRob Clark 45402ef80c5SJonathan Marek #define REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0 0x0000000b 4552d756322SRob Clark 45602ef80c5SJonathan Marek #define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR 0x0000000d 4572d756322SRob Clark 45802ef80c5SJonathan Marek #define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA 0x0000000e 4592d756322SRob Clark 46002ef80c5SJonathan Marek #define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0 0x00000082 4612d756322SRob Clark 46202ef80c5SJonathan Marek #define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0 0x00000083 4632d756322SRob Clark 46402ef80c5SJonathan Marek #define REG_A6XX_RSCC_TIMESTAMP_UNIT1_EN_DRV0 0x00000089 4652d756322SRob Clark 46602ef80c5SJonathan Marek #define REG_A6XX_RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0 0x0000008c 4672d756322SRob Clark 46802ef80c5SJonathan Marek #define REG_A6XX_RSCC_OVERRIDE_START_ADDR 0x00000100 4692d756322SRob Clark 47002ef80c5SJonathan Marek #define REG_A6XX_RSCC_SEQ_BUSY_DRV0 0x00000101 4712d756322SRob Clark 47202ef80c5SJonathan Marek #define REG_A6XX_RSCC_SEQ_MEM_0_DRV0 0x00000180 4732d756322SRob Clark 47402ef80c5SJonathan Marek #define REG_A6XX_RSCC_TCS0_DRV0_STATUS 0x00000346 4752d756322SRob Clark 47602ef80c5SJonathan Marek #define REG_A6XX_RSCC_TCS1_DRV0_STATUS 0x000003ee 4772d756322SRob Clark 47802ef80c5SJonathan Marek #define REG_A6XX_RSCC_TCS2_DRV0_STATUS 0x00000496 47902ef80c5SJonathan Marek 48002ef80c5SJonathan Marek #define REG_A6XX_RSCC_TCS3_DRV0_STATUS 0x0000053e 4812d756322SRob Clark 4822d756322SRob Clark 4832d756322SRob Clark #endif /* A6XX_GMU_XML */ 484