12d756322SRob Clark #ifndef A6XX_GMU_XML 22d756322SRob Clark #define A6XX_GMU_XML 32d756322SRob Clark 42d756322SRob Clark /* Autogenerated file, DO NOT EDIT manually! 52d756322SRob Clark 62d756322SRob Clark This file was generated by the rules-ng-ng headergen tool in this git repository: 72d756322SRob Clark http://github.com/freedreno/envytools/ 82d756322SRob Clark git clone https://github.com/freedreno/envytools.git 92d756322SRob Clark 102d756322SRob Clark The rules-ng-ng source files this header was generated from are: 112d756322SRob Clark - /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13) 122d756322SRob Clark - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13) 13ccdf7e28SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03) 14ccdf7e28SRob Clark - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14201 bytes, from 2018-12-02 17:29:54) 15ccdf7e28SRob Clark - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-02 17:29:54) 162d756322SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13) 172d756322SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13) 18ccdf7e28SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54) 19ccdf7e28SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54) 20a69c5ed2SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07) 212d756322SRob Clark - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13) 222d756322SRob Clark 232d756322SRob Clark Copyright (C) 2013-2018 by the following authors: 242d756322SRob Clark - Rob Clark <robdclark@gmail.com> (robclark) 252d756322SRob Clark - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 262d756322SRob Clark 272d756322SRob Clark Permission is hereby granted, free of charge, to any person obtaining 282d756322SRob Clark a copy of this software and associated documentation files (the 292d756322SRob Clark "Software"), to deal in the Software without restriction, including 302d756322SRob Clark without limitation the rights to use, copy, modify, merge, publish, 312d756322SRob Clark distribute, sublicense, and/or sell copies of the Software, and to 322d756322SRob Clark permit persons to whom the Software is furnished to do so, subject to 332d756322SRob Clark the following conditions: 342d756322SRob Clark 352d756322SRob Clark The above copyright notice and this permission notice (including the 362d756322SRob Clark next paragraph) shall be included in all copies or substantial 372d756322SRob Clark portions of the Software. 382d756322SRob Clark 392d756322SRob Clark THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 402d756322SRob Clark EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 412d756322SRob Clark MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 422d756322SRob Clark IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 432d756322SRob Clark LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 442d756322SRob Clark OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 452d756322SRob Clark WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 462d756322SRob Clark */ 472d756322SRob Clark 482d756322SRob Clark 492d756322SRob Clark #define A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB 0x00800000 502d756322SRob Clark #define A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB 0x40000000 512d756322SRob Clark #define A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK 0x00400000 522d756322SRob Clark #define A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK 0x40000000 532d756322SRob Clark #define A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK 0x40000000 542d756322SRob Clark #define A6XX_GMU_OOB_DCVS_SET_MASK 0x00800000 552d756322SRob Clark #define A6XX_GMU_OOB_DCVS_CHECK_MASK 0x80000000 562d756322SRob Clark #define A6XX_GMU_OOB_DCVS_CLEAR_MASK 0x80000000 572d756322SRob Clark #define A6XX_GMU_OOB_GPU_SET_MASK 0x00040000 582d756322SRob Clark #define A6XX_GMU_OOB_GPU_CHECK_MASK 0x04000000 592d756322SRob Clark #define A6XX_GMU_OOB_GPU_CLEAR_MASK 0x04000000 602d756322SRob Clark #define A6XX_GMU_OOB_PERFCNTR_SET_MASK 0x00020000 612d756322SRob Clark #define A6XX_GMU_OOB_PERFCNTR_CHECK_MASK 0x02000000 622d756322SRob Clark #define A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK 0x02000000 632d756322SRob Clark #define A6XX_HFI_IRQ_MSGQ_MASK 0x00000001 642d756322SRob Clark #define A6XX_HFI_IRQ_DSGQ_MASK 0x00000002 652d756322SRob Clark #define A6XX_HFI_IRQ_BLOCKED_MSG_MASK 0x00000004 662d756322SRob Clark #define A6XX_HFI_IRQ_CM3_FAULT_MASK 0x00800000 672d756322SRob Clark #define A6XX_HFI_IRQ_GMU_ERR_MASK__MASK 0x007f0000 682d756322SRob Clark #define A6XX_HFI_IRQ_GMU_ERR_MASK__SHIFT 16 692d756322SRob Clark static inline uint32_t A6XX_HFI_IRQ_GMU_ERR_MASK(uint32_t val) 702d756322SRob Clark { 712d756322SRob Clark return ((val) << A6XX_HFI_IRQ_GMU_ERR_MASK__SHIFT) & A6XX_HFI_IRQ_GMU_ERR_MASK__MASK; 722d756322SRob Clark } 732d756322SRob Clark #define A6XX_HFI_IRQ_OOB_MASK__MASK 0xff000000 742d756322SRob Clark #define A6XX_HFI_IRQ_OOB_MASK__SHIFT 24 752d756322SRob Clark static inline uint32_t A6XX_HFI_IRQ_OOB_MASK(uint32_t val) 762d756322SRob Clark { 772d756322SRob Clark return ((val) << A6XX_HFI_IRQ_OOB_MASK__SHIFT) & A6XX_HFI_IRQ_OOB_MASK__MASK; 782d756322SRob Clark } 792d756322SRob Clark #define A6XX_HFI_H2F_IRQ_MASK_BIT 0x00000001 802d756322SRob Clark #define REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL 0x00000080 812d756322SRob Clark 822d756322SRob Clark #define REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL 0x00000081 832d756322SRob Clark 842d756322SRob Clark #define REG_A6XX_GMU_CM3_ITCM_START 0x00000c00 852d756322SRob Clark 862d756322SRob Clark #define REG_A6XX_GMU_CM3_DTCM_START 0x00001c00 872d756322SRob Clark 882d756322SRob Clark #define REG_A6XX_GMU_NMI_CONTROL_STATUS 0x000023f0 892d756322SRob Clark 902d756322SRob Clark #define REG_A6XX_GMU_BOOT_SLUMBER_OPTION 0x000023f8 912d756322SRob Clark 922d756322SRob Clark #define REG_A6XX_GMU_GX_VOTE_IDX 0x000023f9 932d756322SRob Clark 942d756322SRob Clark #define REG_A6XX_GMU_MX_VOTE_IDX 0x000023fa 952d756322SRob Clark 962d756322SRob Clark #define REG_A6XX_GMU_DCVS_ACK_OPTION 0x000023fc 972d756322SRob Clark 982d756322SRob Clark #define REG_A6XX_GMU_DCVS_PERF_SETTING 0x000023fd 992d756322SRob Clark 1002d756322SRob Clark #define REG_A6XX_GMU_DCVS_BW_SETTING 0x000023fe 1012d756322SRob Clark 1022d756322SRob Clark #define REG_A6XX_GMU_DCVS_RETURN 0x000023ff 1032d756322SRob Clark 104c6ed04f8SJonathan Marek #define REG_A6XX_GMU_ICACHE_CONFIG 0x00004c00 105c6ed04f8SJonathan Marek 106c6ed04f8SJonathan Marek #define REG_A6XX_GMU_DCACHE_CONFIG 0x00004c01 107c6ed04f8SJonathan Marek 1082d756322SRob Clark #define REG_A6XX_GMU_SYS_BUS_CONFIG 0x00004c0f 1092d756322SRob Clark 1102d756322SRob Clark #define REG_A6XX_GMU_CM3_SYSRESET 0x00005000 1112d756322SRob Clark 1122d756322SRob Clark #define REG_A6XX_GMU_CM3_BOOT_CONFIG 0x00005001 1132d756322SRob Clark 1142d756322SRob Clark #define REG_A6XX_GMU_CM3_FW_BUSY 0x0000501a 1152d756322SRob Clark 1162d756322SRob Clark #define REG_A6XX_GMU_CM3_FW_INIT_RESULT 0x0000501c 1172d756322SRob Clark 1182d756322SRob Clark #define REG_A6XX_GMU_CM3_CFG 0x0000502d 1192d756322SRob Clark 1202d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE 0x00005040 1212d756322SRob Clark 1222d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0 0x00005041 1232d756322SRob Clark 1242d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1 0x00005042 1252d756322SRob Clark 1262d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L 0x00005044 1272d756322SRob Clark 1282d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H 0x00005045 1292d756322SRob Clark 1302d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L 0x00005046 1312d756322SRob Clark 1322d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H 0x00005047 1332d756322SRob Clark 1342d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L 0x00005048 1352d756322SRob Clark 1362d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H 0x00005049 1372d756322SRob Clark 1382d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L 0x0000504a 1392d756322SRob Clark 1402d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H 0x0000504b 1412d756322SRob Clark 1422d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L 0x0000504c 1432d756322SRob Clark 1442d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H 0x0000504d 1452d756322SRob Clark 1462d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L 0x0000504e 1472d756322SRob Clark 1482d756322SRob Clark #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H 0x0000504f 1492d756322SRob Clark 1502d756322SRob Clark #define REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL 0x000050c0 1512d756322SRob Clark #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE 0x00000001 1522d756322SRob Clark #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE 0x00000002 1532d756322SRob Clark #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE 0x00000004 1542d756322SRob Clark #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__MASK 0x00003c00 1552d756322SRob Clark #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__SHIFT 10 1562d756322SRob Clark static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS(uint32_t val) 1572d756322SRob Clark { 1582d756322SRob Clark return ((val) << A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__SHIFT) & A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__MASK; 1592d756322SRob Clark } 1602d756322SRob Clark #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__MASK 0xffffc000 1612d756322SRob Clark #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__SHIFT 14 1622d756322SRob Clark static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH(uint32_t val) 1632d756322SRob Clark { 1642d756322SRob Clark return ((val) << A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__SHIFT) & A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__MASK; 1652d756322SRob Clark } 1662d756322SRob Clark 1672d756322SRob Clark #define REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST 0x000050c1 1682d756322SRob Clark 1692d756322SRob Clark #define REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST 0x000050c2 1702d756322SRob Clark 1712d756322SRob Clark #define REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS 0x000050d0 1722d756322SRob Clark #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_OFF 0x00000001 1732d756322SRob Clark #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_ON 0x00000002 174a69c5ed2SRob Clark #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF 0x00000004 175a69c5ed2SRob Clark #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_ON 0x00000008 1762d756322SRob Clark #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF 0x00000010 1772d756322SRob Clark #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GMU_UP_POWER_STATE 0x00000020 1782d756322SRob Clark #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF 0x00000040 1792d756322SRob Clark #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF 0x00000080 1802d756322SRob Clark 1812d756322SRob Clark #define REG_A6XX_GMU_GPU_NAP_CTRL 0x000050e4 1822d756322SRob Clark #define A6XX_GMU_GPU_NAP_CTRL_HW_NAP_ENABLE 0x00000001 1832d756322SRob Clark #define A6XX_GMU_GPU_NAP_CTRL_SID__MASK 0x000001f0 1842d756322SRob Clark #define A6XX_GMU_GPU_NAP_CTRL_SID__SHIFT 4 1852d756322SRob Clark static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val) 1862d756322SRob Clark { 1872d756322SRob Clark return ((val) << A6XX_GMU_GPU_NAP_CTRL_SID__SHIFT) & A6XX_GMU_GPU_NAP_CTRL_SID__MASK; 1882d756322SRob Clark } 1892d756322SRob Clark 1902d756322SRob Clark #define REG_A6XX_GMU_RPMH_CTRL 0x000050e8 1912d756322SRob Clark #define A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE 0x00000001 1922d756322SRob Clark #define A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE 0x00000010 1932d756322SRob Clark #define A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE 0x00000100 1942d756322SRob Clark #define A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE 0x00000200 1952d756322SRob Clark #define A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE 0x00000400 1962d756322SRob Clark #define A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE 0x00000800 1972d756322SRob Clark #define A6XX_GMU_RPMH_CTRL_DDR_MIN_VOTE_ENABLE 0x00001000 1982d756322SRob Clark #define A6XX_GMU_RPMH_CTRL_MX_MIN_VOTE_ENABLE 0x00002000 1992d756322SRob Clark #define A6XX_GMU_RPMH_CTRL_CX_MIN_VOTE_ENABLE 0x00004000 2002d756322SRob Clark #define A6XX_GMU_RPMH_CTRL_GFX_MIN_VOTE_ENABLE 0x00008000 2012d756322SRob Clark 2022d756322SRob Clark #define REG_A6XX_GMU_RPMH_HYST_CTRL 0x000050e9 2032d756322SRob Clark 2042d756322SRob Clark #define REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE 0x000050ec 2052d756322SRob Clark 206c6ed04f8SJonathan Marek #define REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF 0x000050f0 207c6ed04f8SJonathan Marek 2082d756322SRob Clark #define REG_A6XX_GMU_BOOT_KMD_LM_HANDSHAKE 0x000051f0 2092d756322SRob Clark 2102d756322SRob Clark #define REG_A6XX_GMU_LLM_GLM_SLEEP_CTRL 0x00005157 2112d756322SRob Clark 2122d756322SRob Clark #define REG_A6XX_GMU_LLM_GLM_SLEEP_STATUS 0x00005158 2132d756322SRob Clark 2142d756322SRob Clark #define REG_A6XX_GMU_ALWAYS_ON_COUNTER_L 0x00005088 2152d756322SRob Clark 2162d756322SRob Clark #define REG_A6XX_GMU_ALWAYS_ON_COUNTER_H 0x00005089 2172d756322SRob Clark 2182d756322SRob Clark #define REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE 0x000050c3 2192d756322SRob Clark 2202d756322SRob Clark #define REG_A6XX_GMU_HFI_CTRL_STATUS 0x00005180 2212d756322SRob Clark 2222d756322SRob Clark #define REG_A6XX_GMU_HFI_VERSION_INFO 0x00005181 2232d756322SRob Clark 2242d756322SRob Clark #define REG_A6XX_GMU_HFI_SFR_ADDR 0x00005182 2252d756322SRob Clark 2262d756322SRob Clark #define REG_A6XX_GMU_HFI_MMAP_ADDR 0x00005183 2272d756322SRob Clark 2282d756322SRob Clark #define REG_A6XX_GMU_HFI_QTBL_INFO 0x00005184 2292d756322SRob Clark 2302d756322SRob Clark #define REG_A6XX_GMU_HFI_QTBL_ADDR 0x00005185 2312d756322SRob Clark 2322d756322SRob Clark #define REG_A6XX_GMU_HFI_CTRL_INIT 0x00005186 2332d756322SRob Clark 2342d756322SRob Clark #define REG_A6XX_GMU_GMU2HOST_INTR_SET 0x00005190 2352d756322SRob Clark 2362d756322SRob Clark #define REG_A6XX_GMU_GMU2HOST_INTR_CLR 0x00005191 2372d756322SRob Clark 2382d756322SRob Clark #define REG_A6XX_GMU_GMU2HOST_INTR_INFO 0x00005192 2392d756322SRob Clark #define A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ 0x00000001 2402d756322SRob Clark #define A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT 0x00800000 2412d756322SRob Clark 2422d756322SRob Clark #define REG_A6XX_GMU_GMU2HOST_INTR_MASK 0x00005193 2432d756322SRob Clark 2442d756322SRob Clark #define REG_A6XX_GMU_HOST2GMU_INTR_SET 0x00005194 2452d756322SRob Clark 2462d756322SRob Clark #define REG_A6XX_GMU_HOST2GMU_INTR_CLR 0x00005195 2472d756322SRob Clark 2482d756322SRob Clark #define REG_A6XX_GMU_HOST2GMU_INTR_RAW_INFO 0x00005196 2492d756322SRob Clark 2502d756322SRob Clark #define REG_A6XX_GMU_HOST2GMU_INTR_EN_0 0x00005197 2512d756322SRob Clark 2522d756322SRob Clark #define REG_A6XX_GMU_HOST2GMU_INTR_EN_1 0x00005198 2532d756322SRob Clark 2542d756322SRob Clark #define REG_A6XX_GMU_HOST2GMU_INTR_EN_2 0x00005199 2552d756322SRob Clark 2562d756322SRob Clark #define REG_A6XX_GMU_HOST2GMU_INTR_EN_3 0x0000519a 2572d756322SRob Clark 2582d756322SRob Clark #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_0 0x0000519b 2592d756322SRob Clark 2602d756322SRob Clark #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_1 0x0000519c 2612d756322SRob Clark 2622d756322SRob Clark #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_2 0x0000519d 2632d756322SRob Clark 2642d756322SRob Clark #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_3 0x0000519e 2652d756322SRob Clark 2662d756322SRob Clark #define REG_A6XX_GMU_GENERAL_1 0x000051c6 2672d756322SRob Clark 2682d756322SRob Clark #define REG_A6XX_GMU_GENERAL_7 0x000051cc 2692d756322SRob Clark 2702d756322SRob Clark #define REG_A6XX_GMU_ISENSE_CTRL 0x0000515d 2712d756322SRob Clark 2722d756322SRob Clark #define REG_A6XX_GPU_CS_ENABLE_REG 0x00008920 2732d756322SRob Clark 2742d756322SRob Clark #define REG_A6XX_GPU_GMU_CX_GMU_ISENSE_CTRL 0x0000515d 2752d756322SRob Clark 2762d756322SRob Clark #define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL3 0x00008578 2772d756322SRob Clark 2782d756322SRob Clark #define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL2 0x00008558 2792d756322SRob Clark 2802d756322SRob Clark #define REG_A6XX_GPU_CS_A_SENSOR_CTRL_0 0x00008580 2812d756322SRob Clark 2822d756322SRob Clark #define REG_A6XX_GPU_CS_A_SENSOR_CTRL_2 0x00027ada 2832d756322SRob Clark 2842d756322SRob Clark #define REG_A6XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000881a 2852d756322SRob Clark 2862d756322SRob Clark #define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x00008957 2872d756322SRob Clark 2882d756322SRob Clark #define REG_A6XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000881a 2892d756322SRob Clark 2902d756322SRob Clark #define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 0x0000881d 2912d756322SRob Clark 2922d756322SRob Clark #define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 0x0000881f 2932d756322SRob Clark 2942d756322SRob Clark #define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 0x00008821 2952d756322SRob Clark 2962d756322SRob Clark #define REG_A6XX_GPU_CS_AMP_CALIBRATION_DONE 0x00008965 2972d756322SRob Clark 2982d756322SRob Clark #define REG_A6XX_GPU_CS_AMP_PERIOD_CTRL 0x0000896d 2992d756322SRob Clark 3002d756322SRob Clark #define REG_A6XX_GPU_CS_AMP_CALIBRATION_DONE 0x00008965 3012d756322SRob Clark 3022d756322SRob Clark #define REG_A6XX_GPU_GMU_CX_GMU_PWR_THRESHOLD 0x0000514d 3032d756322SRob Clark 3042d756322SRob Clark #define REG_A6XX_GMU_AO_INTERRUPT_EN 0x00009303 3052d756322SRob Clark 3062d756322SRob Clark #define REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR 0x00009304 3072d756322SRob Clark 3082d756322SRob Clark #define REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS 0x00009305 3092d756322SRob Clark #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE 0x00000001 3102d756322SRob Clark #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_RSCC_COMP 0x00000002 3112d756322SRob Clark #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_VDROOP 0x00000004 3122d756322SRob Clark #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR 0x00000008 3132d756322SRob Clark #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_DBD_WAKEUP 0x00000010 3142d756322SRob Clark #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR 0x00000020 3152d756322SRob Clark 3162d756322SRob Clark #define REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK 0x00009306 3172d756322SRob Clark 3182d756322SRob Clark #define REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL 0x00009309 3192d756322SRob Clark 3202d756322SRob Clark #define REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL 0x0000930a 3212d756322SRob Clark 3222d756322SRob Clark #define REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL 0x0000930b 3232d756322SRob Clark 3242d756322SRob Clark #define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS 0x0000930c 3252d756322SRob Clark #define A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB 0x00800000 3262d756322SRob Clark 3272d756322SRob Clark #define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2 0x0000930d 3282d756322SRob Clark 3292d756322SRob Clark #define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK 0x0000930e 3302d756322SRob Clark 3312d756322SRob Clark #define REG_A6XX_GMU_AO_AHB_FENCE_CTRL 0x00009310 3322d756322SRob Clark 3332d756322SRob Clark #define REG_A6XX_GMU_AHB_FENCE_STATUS 0x00009313 3342d756322SRob Clark 3352d756322SRob Clark #define REG_A6XX_GMU_RBBM_INT_UNMASKED_STATUS 0x00009315 3362d756322SRob Clark 3372d756322SRob Clark #define REG_A6XX_GMU_AO_SPARE_CNTL 0x00009316 3382d756322SRob Clark 3392d756322SRob Clark #define REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0 0x00008c04 3402d756322SRob Clark 3412d756322SRob Clark #define REG_A6XX_GMU_RSCC_CONTROL_REQ 0x00009307 3422d756322SRob Clark 3432d756322SRob Clark #define REG_A6XX_GMU_RSCC_CONTROL_ACK 0x00009308 3442d756322SRob Clark 3452d756322SRob Clark #define REG_A6XX_GMU_AHB_FENCE_RANGE_0 0x00009311 3462d756322SRob Clark 3472d756322SRob Clark #define REG_A6XX_GMU_AHB_FENCE_RANGE_1 0x00009312 3482d756322SRob Clark 3492d756322SRob Clark #define REG_A6XX_GPU_CC_GX_GDSCR 0x00009c03 3502d756322SRob Clark 3512d756322SRob Clark #define REG_A6XX_GPU_CC_GX_DOMAIN_MISC 0x00009d42 3522d756322SRob Clark 3532d756322SRob Clark #define REG_A6XX_RSCC_PDC_SEQ_START_ADDR 0x00008c08 3542d756322SRob Clark 3552d756322SRob Clark #define REG_A6XX_RSCC_PDC_MATCH_VALUE_LO 0x00008c09 3562d756322SRob Clark 3572d756322SRob Clark #define REG_A6XX_RSCC_PDC_MATCH_VALUE_HI 0x00008c0a 3582d756322SRob Clark 3592d756322SRob Clark #define REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0 0x00008c0b 3602d756322SRob Clark 3612d756322SRob Clark #define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR 0x00008c0d 3622d756322SRob Clark 3632d756322SRob Clark #define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA 0x00008c0e 3642d756322SRob Clark 3652d756322SRob Clark #define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0 0x00008c82 3662d756322SRob Clark 3672d756322SRob Clark #define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0 0x00008c83 3682d756322SRob Clark 3692d756322SRob Clark #define REG_A6XX_RSCC_TIMESTAMP_UNIT1_EN_DRV0 0x00008c89 3702d756322SRob Clark 3712d756322SRob Clark #define REG_A6XX_RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0 0x00008c8c 3722d756322SRob Clark 3732d756322SRob Clark #define REG_A6XX_RSCC_OVERRIDE_START_ADDR 0x00008d00 3742d756322SRob Clark 3752d756322SRob Clark #define REG_A6XX_RSCC_SEQ_BUSY_DRV0 0x00008d01 3762d756322SRob Clark 3772d756322SRob Clark #define REG_A6XX_RSCC_SEQ_MEM_0_DRV0 0x00008d80 3782d756322SRob Clark 3792d756322SRob Clark #define REG_A6XX_RSCC_TCS0_DRV0_STATUS 0x00008f46 3802d756322SRob Clark 3812d756322SRob Clark #define REG_A6XX_RSCC_TCS1_DRV0_STATUS 0x000090ae 3822d756322SRob Clark 3832d756322SRob Clark #define REG_A6XX_RSCC_TCS2_DRV0_STATUS 0x00009216 3842d756322SRob Clark 3852d756322SRob Clark #define REG_A6XX_RSCC_TCS3_DRV0_STATUS 0x0000937e 3862d756322SRob Clark 3872d756322SRob Clark 3882d756322SRob Clark #endif /* A6XX_GMU_XML */ 389