1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2017 The Linux Foundation. All rights reserved. */ 3 4 #ifndef _A6XX_GMU_H_ 5 #define _A6XX_GMU_H_ 6 7 #include <linux/iopoll.h> 8 #include <linux/interrupt.h> 9 #include "msm_drv.h" 10 #include "a6xx_hfi.h" 11 12 struct a6xx_gmu_bo { 13 struct drm_gem_object *obj; 14 void *virt; 15 size_t size; 16 u64 iova; 17 }; 18 19 /* 20 * These define the different GMU wake up options - these define how both the 21 * CPU and the GMU bring up the hardware 22 */ 23 24 /* THe GMU has already been booted and the rentention registers are active */ 25 #define GMU_WARM_BOOT 0 26 27 /* the GMU is coming up for the first time or back from a power collapse */ 28 #define GMU_COLD_BOOT 1 29 30 /* 31 * These define the level of control that the GMU has - the higher the number 32 * the more things that the GMU hardware controls on its own. 33 */ 34 35 /* The GMU does not do any idle state management */ 36 #define GMU_IDLE_STATE_ACTIVE 0 37 38 /* The GMU manages SPTP power collapse */ 39 #define GMU_IDLE_STATE_SPTP 2 40 41 /* The GMU does automatic IFPC (intra-frame power collapse) */ 42 #define GMU_IDLE_STATE_IFPC 3 43 44 struct a6xx_gmu { 45 struct device *dev; 46 47 struct msm_gem_address_space *aspace; 48 49 void * __iomem mmio; 50 void * __iomem rscc; 51 52 int hfi_irq; 53 int gmu_irq; 54 55 struct device *gxpd; 56 57 int idle_level; 58 59 struct a6xx_gmu_bo hfi; 60 struct a6xx_gmu_bo debug; 61 struct a6xx_gmu_bo icache; 62 struct a6xx_gmu_bo dcache; 63 struct a6xx_gmu_bo dummy; 64 struct a6xx_gmu_bo log; 65 66 int nr_clocks; 67 struct clk_bulk_data *clocks; 68 struct clk *core_clk; 69 struct clk *hub_clk; 70 71 /* current performance index set externally */ 72 int current_perf_index; 73 74 int nr_gpu_freqs; 75 unsigned long gpu_freqs[16]; 76 u32 gx_arc_votes[16]; 77 78 int nr_gmu_freqs; 79 unsigned long gmu_freqs[4]; 80 u32 cx_arc_votes[4]; 81 82 unsigned long freq; 83 84 struct a6xx_hfi_queue queues[2]; 85 86 bool initialized; 87 bool hung; 88 bool legacy; /* a618 or a630 */ 89 }; 90 91 static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset) 92 { 93 return msm_readl(gmu->mmio + (offset << 2)); 94 } 95 96 static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value) 97 { 98 return msm_writel(value, gmu->mmio + (offset << 2)); 99 } 100 101 static inline void 102 gmu_write_bulk(struct a6xx_gmu *gmu, u32 offset, const u32 *data, u32 size) 103 { 104 memcpy_toio(gmu->mmio + (offset << 2), data, size); 105 wmb(); 106 } 107 108 static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or) 109 { 110 u32 val = gmu_read(gmu, reg); 111 112 val &= ~mask; 113 114 gmu_write(gmu, reg, val | or); 115 } 116 117 static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi) 118 { 119 u64 val; 120 121 val = (u64) msm_readl(gmu->mmio + (lo << 2)); 122 val |= ((u64) msm_readl(gmu->mmio + (hi << 2)) << 32); 123 124 return val; 125 } 126 127 #define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) \ 128 readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \ 129 interval, timeout) 130 131 static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset) 132 { 133 return msm_readl(gmu->rscc + (offset << 2)); 134 } 135 136 static inline void gmu_write_rscc(struct a6xx_gmu *gmu, u32 offset, u32 value) 137 { 138 return msm_writel(value, gmu->rscc + (offset << 2)); 139 } 140 141 #define gmu_poll_timeout_rscc(gmu, addr, val, cond, interval, timeout) \ 142 readl_poll_timeout((gmu)->rscc + ((addr) << 2), val, cond, \ 143 interval, timeout) 144 145 /* 146 * These are the available OOB (out of band requests) to the GMU where "out of 147 * band" means that the CPU talks to the GMU directly and not through HFI. 148 * Normally this works by writing a ITCM/DTCM register and then triggering a 149 * interrupt (the "request" bit) and waiting for an acknowledgment (the "ack" 150 * bit). The state is cleared by writing the "clear' bit to the GMU interrupt. 151 * 152 * These are used to force the GMU/GPU to stay on during a critical sequence or 153 * for hardware workarounds. 154 */ 155 156 enum a6xx_gmu_oob_state { 157 /* 158 * Let the GMU know that a boot or slumber operation has started. The value in 159 * REG_A6XX_GMU_BOOT_SLUMBER_OPTION lets the GMU know which operation we are 160 * doing 161 */ 162 GMU_OOB_BOOT_SLUMBER = 0, 163 /* 164 * Let the GMU know to not turn off any GPU registers while the CPU is in a 165 * critical section 166 */ 167 GMU_OOB_GPU_SET, 168 /* 169 * Set a new power level for the GPU when the CPU is doing frequency scaling 170 */ 171 GMU_OOB_DCVS_SET, 172 /* 173 * Used to keep the GPU on for CPU-side reads of performance counters. 174 */ 175 GMU_OOB_PERFCOUNTER_SET, 176 }; 177 178 void a6xx_hfi_init(struct a6xx_gmu *gmu); 179 int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state); 180 void a6xx_hfi_stop(struct a6xx_gmu *gmu); 181 int a6xx_hfi_send_prep_slumber(struct a6xx_gmu *gmu); 182 int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, int index); 183 184 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu); 185 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu); 186 187 #endif 188