1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2017 The Linux Foundation. All rights reserved. */ 3 4 #ifndef _A6XX_GMU_H_ 5 #define _A6XX_GMU_H_ 6 7 #include <linux/iopoll.h> 8 #include <linux/interrupt.h> 9 #include "msm_drv.h" 10 #include "a6xx_hfi.h" 11 12 struct a6xx_gmu_bo { 13 void *virt; 14 size_t size; 15 u64 iova; 16 struct page **pages; 17 }; 18 19 /* 20 * These define the different GMU wake up options - these define how both the 21 * CPU and the GMU bring up the hardware 22 */ 23 24 /* THe GMU has already been booted and the rentention registers are active */ 25 #define GMU_WARM_BOOT 0 26 27 /* the GMU is coming up for the first time or back from a power collapse */ 28 #define GMU_COLD_BOOT 1 29 30 /* The GMU is being soft reset after a fault */ 31 #define GMU_RESET 2 32 33 /* 34 * These define the level of control that the GMU has - the higher the number 35 * the more things that the GMU hardware controls on its own. 36 */ 37 38 /* The GMU does not do any idle state management */ 39 #define GMU_IDLE_STATE_ACTIVE 0 40 41 /* The GMU manages SPTP power collapse */ 42 #define GMU_IDLE_STATE_SPTP 2 43 44 /* The GMU does automatic IFPC (intra-frame power collapse) */ 45 #define GMU_IDLE_STATE_IFPC 3 46 47 struct a6xx_gmu { 48 struct device *dev; 49 50 void * __iomem mmio; 51 52 int hfi_irq; 53 int gmu_irq; 54 55 struct iommu_domain *domain; 56 u64 uncached_iova_base; 57 58 struct device *gxpd; 59 60 int idle_level; 61 62 struct a6xx_gmu_bo *hfi; 63 struct a6xx_gmu_bo *debug; 64 65 int nr_clocks; 66 struct clk_bulk_data *clocks; 67 struct clk *core_clk; 68 69 int nr_gpu_freqs; 70 unsigned long gpu_freqs[16]; 71 u32 gx_arc_votes[16]; 72 73 int nr_gmu_freqs; 74 unsigned long gmu_freqs[4]; 75 u32 cx_arc_votes[4]; 76 77 unsigned long freq; 78 79 struct a6xx_hfi_queue queues[2]; 80 81 struct tasklet_struct hfi_tasklet; 82 }; 83 84 static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset) 85 { 86 return msm_readl(gmu->mmio + (offset << 2)); 87 } 88 89 static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value) 90 { 91 return msm_writel(value, gmu->mmio + (offset << 2)); 92 } 93 94 static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or) 95 { 96 u32 val = gmu_read(gmu, reg); 97 98 val &= ~mask; 99 100 gmu_write(gmu, reg, val | or); 101 } 102 103 static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi) 104 { 105 u64 val; 106 107 val = (u64) msm_readl(gmu->mmio + (lo << 2)); 108 val |= ((u64) msm_readl(gmu->mmio + (hi << 2)) << 32); 109 110 return val; 111 } 112 113 #define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) \ 114 readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \ 115 interval, timeout) 116 117 /* 118 * These are the available OOB (out of band requests) to the GMU where "out of 119 * band" means that the CPU talks to the GMU directly and not through HFI. 120 * Normally this works by writing a ITCM/DTCM register and then triggering a 121 * interrupt (the "request" bit) and waiting for an acknowledgment (the "ack" 122 * bit). The state is cleared by writing the "clear' bit to the GMU interrupt. 123 * 124 * These are used to force the GMU/GPU to stay on during a critical sequence or 125 * for hardware workarounds. 126 */ 127 128 enum a6xx_gmu_oob_state { 129 GMU_OOB_BOOT_SLUMBER = 0, 130 GMU_OOB_GPU_SET, 131 GMU_OOB_DCVS_SET, 132 }; 133 134 /* These are the interrupt / ack bits for each OOB request that are set 135 * in a6xx_gmu_set_oob and a6xx_clear_oob 136 */ 137 138 /* 139 * Let the GMU know that a boot or slumber operation has started. The value in 140 * REG_A6XX_GMU_BOOT_SLUMBER_OPTION lets the GMU know which operation we are 141 * doing 142 */ 143 #define GMU_OOB_BOOT_SLUMBER_REQUEST 22 144 #define GMU_OOB_BOOT_SLUMBER_ACK 30 145 #define GMU_OOB_BOOT_SLUMBER_CLEAR 30 146 147 /* 148 * Set a new power level for the GPU when the CPU is doing frequency scaling 149 */ 150 #define GMU_OOB_DCVS_REQUEST 23 151 #define GMU_OOB_DCVS_ACK 31 152 #define GMU_OOB_DCVS_CLEAR 31 153 154 /* 155 * Let the GMU know to not turn off any GPU registers while the CPU is in a 156 * critical section 157 */ 158 #define GMU_OOB_GPU_SET_REQUEST 16 159 #define GMU_OOB_GPU_SET_ACK 24 160 #define GMU_OOB_GPU_SET_CLEAR 24 161 162 163 void a6xx_hfi_init(struct a6xx_gmu *gmu); 164 int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state); 165 void a6xx_hfi_stop(struct a6xx_gmu *gmu); 166 167 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu); 168 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu); 169 170 #endif 171