1 #ifndef A6XX_XML 2 #define A6XX_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2023-03-10 18:32:52) 12 - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46) 13 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 91929 bytes, from 2023-02-28 23:52:27) 14 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from 2023-03-10 18:32:53) 15 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 74995 bytes, from 2023-03-20 18:06:23) 16 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2022-08-02 16:38:43) 17 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113474 bytes, from 2022-08-02 16:38:43) 18 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149590 bytes, from 2023-02-14 19:37:12) 19 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 198949 bytes, from 2023-03-20 18:06:23) 20 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11404 bytes, from 2023-03-10 18:32:53) 21 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2022-08-02 16:38:43) 22 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 9055 bytes, from 2023-03-10 18:32:52) 23 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2976 bytes, from 2023-03-10 18:32:52) 24 25 Copyright (C) 2013-2023 by the following authors: 26 - Rob Clark <robdclark@gmail.com> (robclark) 27 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 28 29 Permission is hereby granted, free of charge, to any person obtaining 30 a copy of this software and associated documentation files (the 31 "Software"), to deal in the Software without restriction, including 32 without limitation the rights to use, copy, modify, merge, publish, 33 distribute, sublicense, and/or sell copies of the Software, and to 34 permit persons to whom the Software is furnished to do so, subject to 35 the following conditions: 36 37 The above copyright notice and this permission notice (including the 38 next paragraph) shall be included in all copies or substantial 39 portions of the Software. 40 41 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 42 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 43 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 44 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 45 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 46 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 47 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 48 */ 49 50 51 enum a6xx_tile_mode { 52 TILE6_LINEAR = 0, 53 TILE6_2 = 2, 54 TILE6_3 = 3, 55 }; 56 57 enum a6xx_format { 58 FMT6_A8_UNORM = 2, 59 FMT6_8_UNORM = 3, 60 FMT6_8_SNORM = 4, 61 FMT6_8_UINT = 5, 62 FMT6_8_SINT = 6, 63 FMT6_4_4_4_4_UNORM = 8, 64 FMT6_5_5_5_1_UNORM = 10, 65 FMT6_1_5_5_5_UNORM = 12, 66 FMT6_5_6_5_UNORM = 14, 67 FMT6_8_8_UNORM = 15, 68 FMT6_8_8_SNORM = 16, 69 FMT6_8_8_UINT = 17, 70 FMT6_8_8_SINT = 18, 71 FMT6_L8_A8_UNORM = 19, 72 FMT6_16_UNORM = 21, 73 FMT6_16_SNORM = 22, 74 FMT6_16_FLOAT = 23, 75 FMT6_16_UINT = 24, 76 FMT6_16_SINT = 25, 77 FMT6_8_8_8_UNORM = 33, 78 FMT6_8_8_8_SNORM = 34, 79 FMT6_8_8_8_UINT = 35, 80 FMT6_8_8_8_SINT = 36, 81 FMT6_8_8_8_8_UNORM = 48, 82 FMT6_8_8_8_X8_UNORM = 49, 83 FMT6_8_8_8_8_SNORM = 50, 84 FMT6_8_8_8_8_UINT = 51, 85 FMT6_8_8_8_8_SINT = 52, 86 FMT6_9_9_9_E5_FLOAT = 53, 87 FMT6_10_10_10_2_UNORM = 54, 88 FMT6_10_10_10_2_UNORM_DEST = 55, 89 FMT6_10_10_10_2_SNORM = 57, 90 FMT6_10_10_10_2_UINT = 58, 91 FMT6_10_10_10_2_SINT = 59, 92 FMT6_11_11_10_FLOAT = 66, 93 FMT6_16_16_UNORM = 67, 94 FMT6_16_16_SNORM = 68, 95 FMT6_16_16_FLOAT = 69, 96 FMT6_16_16_UINT = 70, 97 FMT6_16_16_SINT = 71, 98 FMT6_32_UNORM = 72, 99 FMT6_32_SNORM = 73, 100 FMT6_32_FLOAT = 74, 101 FMT6_32_UINT = 75, 102 FMT6_32_SINT = 76, 103 FMT6_32_FIXED = 77, 104 FMT6_16_16_16_UNORM = 88, 105 FMT6_16_16_16_SNORM = 89, 106 FMT6_16_16_16_FLOAT = 90, 107 FMT6_16_16_16_UINT = 91, 108 FMT6_16_16_16_SINT = 92, 109 FMT6_16_16_16_16_UNORM = 96, 110 FMT6_16_16_16_16_SNORM = 97, 111 FMT6_16_16_16_16_FLOAT = 98, 112 FMT6_16_16_16_16_UINT = 99, 113 FMT6_16_16_16_16_SINT = 100, 114 FMT6_32_32_UNORM = 101, 115 FMT6_32_32_SNORM = 102, 116 FMT6_32_32_FLOAT = 103, 117 FMT6_32_32_UINT = 104, 118 FMT6_32_32_SINT = 105, 119 FMT6_32_32_FIXED = 106, 120 FMT6_32_32_32_UNORM = 112, 121 FMT6_32_32_32_SNORM = 113, 122 FMT6_32_32_32_UINT = 114, 123 FMT6_32_32_32_SINT = 115, 124 FMT6_32_32_32_FLOAT = 116, 125 FMT6_32_32_32_FIXED = 117, 126 FMT6_32_32_32_32_UNORM = 128, 127 FMT6_32_32_32_32_SNORM = 129, 128 FMT6_32_32_32_32_FLOAT = 130, 129 FMT6_32_32_32_32_UINT = 131, 130 FMT6_32_32_32_32_SINT = 132, 131 FMT6_32_32_32_32_FIXED = 133, 132 FMT6_G8R8B8R8_422_UNORM = 140, 133 FMT6_R8G8R8B8_422_UNORM = 141, 134 FMT6_R8_G8B8_2PLANE_420_UNORM = 142, 135 FMT6_NV21 = 143, 136 FMT6_R8_G8_B8_3PLANE_420_UNORM = 144, 137 FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 = 145, 138 FMT6_NV12_Y = 148, 139 FMT6_NV12_UV = 149, 140 FMT6_NV12_VU = 150, 141 FMT6_NV12_4R = 151, 142 FMT6_NV12_4R_Y = 152, 143 FMT6_NV12_4R_UV = 153, 144 FMT6_P010 = 154, 145 FMT6_P010_Y = 155, 146 FMT6_P010_UV = 156, 147 FMT6_TP10 = 157, 148 FMT6_TP10_Y = 158, 149 FMT6_TP10_UV = 159, 150 FMT6_Z24_UNORM_S8_UINT = 160, 151 FMT6_ETC2_RG11_UNORM = 171, 152 FMT6_ETC2_RG11_SNORM = 172, 153 FMT6_ETC2_R11_UNORM = 173, 154 FMT6_ETC2_R11_SNORM = 174, 155 FMT6_ETC1 = 175, 156 FMT6_ETC2_RGB8 = 176, 157 FMT6_ETC2_RGBA8 = 177, 158 FMT6_ETC2_RGB8A1 = 178, 159 FMT6_DXT1 = 179, 160 FMT6_DXT3 = 180, 161 FMT6_DXT5 = 181, 162 FMT6_RGTC1_UNORM = 183, 163 FMT6_RGTC1_SNORM = 184, 164 FMT6_RGTC2_UNORM = 187, 165 FMT6_RGTC2_SNORM = 188, 166 FMT6_BPTC_UFLOAT = 190, 167 FMT6_BPTC_FLOAT = 191, 168 FMT6_BPTC = 192, 169 FMT6_ASTC_4x4 = 193, 170 FMT6_ASTC_5x4 = 194, 171 FMT6_ASTC_5x5 = 195, 172 FMT6_ASTC_6x5 = 196, 173 FMT6_ASTC_6x6 = 197, 174 FMT6_ASTC_8x5 = 198, 175 FMT6_ASTC_8x6 = 199, 176 FMT6_ASTC_8x8 = 200, 177 FMT6_ASTC_10x5 = 201, 178 FMT6_ASTC_10x6 = 202, 179 FMT6_ASTC_10x8 = 203, 180 FMT6_ASTC_10x10 = 204, 181 FMT6_ASTC_12x10 = 205, 182 FMT6_ASTC_12x12 = 206, 183 FMT6_Z24_UINT_S8_UINT = 234, 184 FMT6_NONE = 255, 185 }; 186 187 enum a6xx_polygon_mode { 188 POLYMODE6_POINTS = 1, 189 POLYMODE6_LINES = 2, 190 POLYMODE6_TRIANGLES = 3, 191 }; 192 193 enum a6xx_depth_format { 194 DEPTH6_NONE = 0, 195 DEPTH6_16 = 1, 196 DEPTH6_24_8 = 2, 197 DEPTH6_32 = 4, 198 }; 199 200 enum a6xx_shader_id { 201 A6XX_TP0_TMO_DATA = 9, 202 A6XX_TP0_SMO_DATA = 10, 203 A6XX_TP0_MIPMAP_BASE_DATA = 11, 204 A6XX_TP1_TMO_DATA = 25, 205 A6XX_TP1_SMO_DATA = 26, 206 A6XX_TP1_MIPMAP_BASE_DATA = 27, 207 A6XX_SP_INST_DATA = 41, 208 A6XX_SP_LB_0_DATA = 42, 209 A6XX_SP_LB_1_DATA = 43, 210 A6XX_SP_LB_2_DATA = 44, 211 A6XX_SP_LB_3_DATA = 45, 212 A6XX_SP_LB_4_DATA = 46, 213 A6XX_SP_LB_5_DATA = 47, 214 A6XX_SP_CB_BINDLESS_DATA = 48, 215 A6XX_SP_CB_LEGACY_DATA = 49, 216 A6XX_SP_UAV_DATA = 50, 217 A6XX_SP_INST_TAG = 51, 218 A6XX_SP_CB_BINDLESS_TAG = 52, 219 A6XX_SP_TMO_UMO_TAG = 53, 220 A6XX_SP_SMO_TAG = 54, 221 A6XX_SP_STATE_DATA = 55, 222 A6XX_HLSQ_CHUNK_CVS_RAM = 73, 223 A6XX_HLSQ_CHUNK_CPS_RAM = 74, 224 A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75, 225 A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76, 226 A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77, 227 A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78, 228 A6XX_HLSQ_CVS_MISC_RAM = 80, 229 A6XX_HLSQ_CPS_MISC_RAM = 81, 230 A6XX_HLSQ_INST_RAM = 82, 231 A6XX_HLSQ_GFX_CVS_CONST_RAM = 83, 232 A6XX_HLSQ_GFX_CPS_CONST_RAM = 84, 233 A6XX_HLSQ_CVS_MISC_RAM_TAG = 85, 234 A6XX_HLSQ_CPS_MISC_RAM_TAG = 86, 235 A6XX_HLSQ_INST_RAM_TAG = 87, 236 A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88, 237 A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89, 238 A6XX_HLSQ_PWR_REST_RAM = 90, 239 A6XX_HLSQ_PWR_REST_TAG = 91, 240 A6XX_HLSQ_DATAPATH_META = 96, 241 A6XX_HLSQ_FRONTEND_META = 97, 242 A6XX_HLSQ_INDIRECT_META = 98, 243 A6XX_HLSQ_BACKEND_META = 99, 244 A6XX_SP_LB_6_DATA = 112, 245 A6XX_SP_LB_7_DATA = 113, 246 A6XX_HLSQ_INST_RAM_1 = 115, 247 }; 248 249 enum a6xx_debugbus_id { 250 A6XX_DBGBUS_CP = 1, 251 A6XX_DBGBUS_RBBM = 2, 252 A6XX_DBGBUS_VBIF = 3, 253 A6XX_DBGBUS_HLSQ = 4, 254 A6XX_DBGBUS_UCHE = 5, 255 A6XX_DBGBUS_DPM = 6, 256 A6XX_DBGBUS_TESS = 7, 257 A6XX_DBGBUS_PC = 8, 258 A6XX_DBGBUS_VFDP = 9, 259 A6XX_DBGBUS_VPC = 10, 260 A6XX_DBGBUS_TSE = 11, 261 A6XX_DBGBUS_RAS = 12, 262 A6XX_DBGBUS_VSC = 13, 263 A6XX_DBGBUS_COM = 14, 264 A6XX_DBGBUS_LRZ = 16, 265 A6XX_DBGBUS_A2D = 17, 266 A6XX_DBGBUS_CCUFCHE = 18, 267 A6XX_DBGBUS_GMU_CX = 19, 268 A6XX_DBGBUS_RBP = 20, 269 A6XX_DBGBUS_DCS = 21, 270 A6XX_DBGBUS_DBGC = 22, 271 A6XX_DBGBUS_CX = 23, 272 A6XX_DBGBUS_GMU_GX = 24, 273 A6XX_DBGBUS_TPFCHE = 25, 274 A6XX_DBGBUS_GBIF_GX = 26, 275 A6XX_DBGBUS_GPC = 29, 276 A6XX_DBGBUS_LARC = 30, 277 A6XX_DBGBUS_HLSQ_SPTP = 31, 278 A6XX_DBGBUS_RB_0 = 32, 279 A6XX_DBGBUS_RB_1 = 33, 280 A6XX_DBGBUS_RB_2 = 34, 281 A6XX_DBGBUS_UCHE_WRAPPER = 36, 282 A6XX_DBGBUS_CCU_0 = 40, 283 A6XX_DBGBUS_CCU_1 = 41, 284 A6XX_DBGBUS_CCU_2 = 42, 285 A6XX_DBGBUS_VFD_0 = 56, 286 A6XX_DBGBUS_VFD_1 = 57, 287 A6XX_DBGBUS_VFD_2 = 58, 288 A6XX_DBGBUS_VFD_3 = 59, 289 A6XX_DBGBUS_VFD_4 = 60, 290 A6XX_DBGBUS_VFD_5 = 61, 291 A6XX_DBGBUS_SP_0 = 64, 292 A6XX_DBGBUS_SP_1 = 65, 293 A6XX_DBGBUS_SP_2 = 66, 294 A6XX_DBGBUS_TPL1_0 = 72, 295 A6XX_DBGBUS_TPL1_1 = 73, 296 A6XX_DBGBUS_TPL1_2 = 74, 297 A6XX_DBGBUS_TPL1_3 = 75, 298 A6XX_DBGBUS_TPL1_4 = 76, 299 A6XX_DBGBUS_TPL1_5 = 77, 300 A6XX_DBGBUS_SPTP_0 = 88, 301 A6XX_DBGBUS_SPTP_1 = 89, 302 A6XX_DBGBUS_SPTP_2 = 90, 303 A6XX_DBGBUS_SPTP_3 = 91, 304 A6XX_DBGBUS_SPTP_4 = 92, 305 A6XX_DBGBUS_SPTP_5 = 93, 306 }; 307 308 enum a6xx_cp_perfcounter_select { 309 PERF_CP_ALWAYS_COUNT = 0, 310 PERF_CP_BUSY_GFX_CORE_IDLE = 1, 311 PERF_CP_BUSY_CYCLES = 2, 312 PERF_CP_NUM_PREEMPTIONS = 3, 313 PERF_CP_PREEMPTION_REACTION_DELAY = 4, 314 PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 5, 315 PERF_CP_PREEMPTION_SWITCH_IN_TIME = 6, 316 PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 7, 317 PERF_CP_PREDICATED_DRAWS_KILLED = 8, 318 PERF_CP_MODE_SWITCH = 9, 319 PERF_CP_ZPASS_DONE = 10, 320 PERF_CP_CONTEXT_DONE = 11, 321 PERF_CP_CACHE_FLUSH = 12, 322 PERF_CP_LONG_PREEMPTIONS = 13, 323 PERF_CP_SQE_I_CACHE_STARVE = 14, 324 PERF_CP_SQE_IDLE = 15, 325 PERF_CP_SQE_PM4_STARVE_RB_IB = 16, 326 PERF_CP_SQE_PM4_STARVE_SDS = 17, 327 PERF_CP_SQE_MRB_STARVE = 18, 328 PERF_CP_SQE_RRB_STARVE = 19, 329 PERF_CP_SQE_VSD_STARVE = 20, 330 PERF_CP_VSD_DECODE_STARVE = 21, 331 PERF_CP_SQE_PIPE_OUT_STALL = 22, 332 PERF_CP_SQE_SYNC_STALL = 23, 333 PERF_CP_SQE_PM4_WFI_STALL = 24, 334 PERF_CP_SQE_SYS_WFI_STALL = 25, 335 PERF_CP_SQE_T4_EXEC = 26, 336 PERF_CP_SQE_LOAD_STATE_EXEC = 27, 337 PERF_CP_SQE_SAVE_SDS_STATE = 28, 338 PERF_CP_SQE_DRAW_EXEC = 29, 339 PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 30, 340 PERF_CP_SQE_EXEC_PROFILED = 31, 341 PERF_CP_MEMORY_POOL_EMPTY = 32, 342 PERF_CP_MEMORY_POOL_SYNC_STALL = 33, 343 PERF_CP_MEMORY_POOL_ABOVE_THRESH = 34, 344 PERF_CP_AHB_WR_STALL_PRE_DRAWS = 35, 345 PERF_CP_AHB_STALL_SQE_GMU = 36, 346 PERF_CP_AHB_STALL_SQE_WR_OTHER = 37, 347 PERF_CP_AHB_STALL_SQE_RD_OTHER = 38, 348 PERF_CP_CLUSTER0_EMPTY = 39, 349 PERF_CP_CLUSTER1_EMPTY = 40, 350 PERF_CP_CLUSTER2_EMPTY = 41, 351 PERF_CP_CLUSTER3_EMPTY = 42, 352 PERF_CP_CLUSTER4_EMPTY = 43, 353 PERF_CP_CLUSTER5_EMPTY = 44, 354 PERF_CP_PM4_DATA = 45, 355 PERF_CP_PM4_HEADERS = 46, 356 PERF_CP_VBIF_READ_BEATS = 47, 357 PERF_CP_VBIF_WRITE_BEATS = 48, 358 PERF_CP_SQE_INSTR_COUNTER = 49, 359 }; 360 361 enum a6xx_rbbm_perfcounter_select { 362 PERF_RBBM_ALWAYS_COUNT = 0, 363 PERF_RBBM_ALWAYS_ON = 1, 364 PERF_RBBM_TSE_BUSY = 2, 365 PERF_RBBM_RAS_BUSY = 3, 366 PERF_RBBM_PC_DCALL_BUSY = 4, 367 PERF_RBBM_PC_VSD_BUSY = 5, 368 PERF_RBBM_STATUS_MASKED = 6, 369 PERF_RBBM_COM_BUSY = 7, 370 PERF_RBBM_DCOM_BUSY = 8, 371 PERF_RBBM_VBIF_BUSY = 9, 372 PERF_RBBM_VSC_BUSY = 10, 373 PERF_RBBM_TESS_BUSY = 11, 374 PERF_RBBM_UCHE_BUSY = 12, 375 PERF_RBBM_HLSQ_BUSY = 13, 376 }; 377 378 enum a6xx_pc_perfcounter_select { 379 PERF_PC_BUSY_CYCLES = 0, 380 PERF_PC_WORKING_CYCLES = 1, 381 PERF_PC_STALL_CYCLES_VFD = 2, 382 PERF_PC_STALL_CYCLES_TSE = 3, 383 PERF_PC_STALL_CYCLES_VPC = 4, 384 PERF_PC_STALL_CYCLES_UCHE = 5, 385 PERF_PC_STALL_CYCLES_TESS = 6, 386 PERF_PC_STALL_CYCLES_TSE_ONLY = 7, 387 PERF_PC_STALL_CYCLES_VPC_ONLY = 8, 388 PERF_PC_PASS1_TF_STALL_CYCLES = 9, 389 PERF_PC_STARVE_CYCLES_FOR_INDEX = 10, 390 PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11, 391 PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12, 392 PERF_PC_STARVE_CYCLES_FOR_POSITION = 13, 393 PERF_PC_STARVE_CYCLES_DI = 14, 394 PERF_PC_VIS_STREAMS_LOADED = 15, 395 PERF_PC_INSTANCES = 16, 396 PERF_PC_VPC_PRIMITIVES = 17, 397 PERF_PC_DEAD_PRIM = 18, 398 PERF_PC_LIVE_PRIM = 19, 399 PERF_PC_VERTEX_HITS = 20, 400 PERF_PC_IA_VERTICES = 21, 401 PERF_PC_IA_PRIMITIVES = 22, 402 PERF_PC_GS_PRIMITIVES = 23, 403 PERF_PC_HS_INVOCATIONS = 24, 404 PERF_PC_DS_INVOCATIONS = 25, 405 PERF_PC_VS_INVOCATIONS = 26, 406 PERF_PC_GS_INVOCATIONS = 27, 407 PERF_PC_DS_PRIMITIVES = 28, 408 PERF_PC_VPC_POS_DATA_TRANSACTION = 29, 409 PERF_PC_3D_DRAWCALLS = 30, 410 PERF_PC_2D_DRAWCALLS = 31, 411 PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32, 412 PERF_TESS_BUSY_CYCLES = 33, 413 PERF_TESS_WORKING_CYCLES = 34, 414 PERF_TESS_STALL_CYCLES_PC = 35, 415 PERF_TESS_STARVE_CYCLES_PC = 36, 416 PERF_PC_TSE_TRANSACTION = 37, 417 PERF_PC_TSE_VERTEX = 38, 418 PERF_PC_TESS_PC_UV_TRANS = 39, 419 PERF_PC_TESS_PC_UV_PATCHES = 40, 420 PERF_PC_TESS_FACTOR_TRANS = 41, 421 }; 422 423 enum a6xx_vfd_perfcounter_select { 424 PERF_VFD_BUSY_CYCLES = 0, 425 PERF_VFD_STALL_CYCLES_UCHE = 1, 426 PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2, 427 PERF_VFD_STALL_CYCLES_SP_INFO = 3, 428 PERF_VFD_STALL_CYCLES_SP_ATTR = 4, 429 PERF_VFD_STARVE_CYCLES_UCHE = 5, 430 PERF_VFD_RBUFFER_FULL = 6, 431 PERF_VFD_ATTR_INFO_FIFO_FULL = 7, 432 PERF_VFD_DECODED_ATTRIBUTE_BYTES = 8, 433 PERF_VFD_NUM_ATTRIBUTES = 9, 434 PERF_VFD_UPPER_SHADER_FIBERS = 10, 435 PERF_VFD_LOWER_SHADER_FIBERS = 11, 436 PERF_VFD_MODE_0_FIBERS = 12, 437 PERF_VFD_MODE_1_FIBERS = 13, 438 PERF_VFD_MODE_2_FIBERS = 14, 439 PERF_VFD_MODE_3_FIBERS = 15, 440 PERF_VFD_MODE_4_FIBERS = 16, 441 PERF_VFD_TOTAL_VERTICES = 17, 442 PERF_VFDP_STALL_CYCLES_VFD = 18, 443 PERF_VFDP_STALL_CYCLES_VFD_INDEX = 19, 444 PERF_VFDP_STALL_CYCLES_VFD_PROG = 20, 445 PERF_VFDP_STARVE_CYCLES_PC = 21, 446 PERF_VFDP_VS_STAGE_WAVES = 22, 447 }; 448 449 enum a6xx_hlsq_perfcounter_select { 450 PERF_HLSQ_BUSY_CYCLES = 0, 451 PERF_HLSQ_STALL_CYCLES_UCHE = 1, 452 PERF_HLSQ_STALL_CYCLES_SP_STATE = 2, 453 PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3, 454 PERF_HLSQ_UCHE_LATENCY_CYCLES = 4, 455 PERF_HLSQ_UCHE_LATENCY_COUNT = 5, 456 PERF_HLSQ_FS_STAGE_1X_WAVES = 6, 457 PERF_HLSQ_FS_STAGE_2X_WAVES = 7, 458 PERF_HLSQ_QUADS = 8, 459 PERF_HLSQ_CS_INVOCATIONS = 9, 460 PERF_HLSQ_COMPUTE_DRAWCALLS = 10, 461 PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11, 462 PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12, 463 PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13, 464 PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14, 465 PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15, 466 PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16, 467 PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17, 468 PERF_HLSQ_STALL_CYCLES_VPC = 18, 469 PERF_HLSQ_PIXELS = 19, 470 PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = 20, 471 }; 472 473 enum a6xx_vpc_perfcounter_select { 474 PERF_VPC_BUSY_CYCLES = 0, 475 PERF_VPC_WORKING_CYCLES = 1, 476 PERF_VPC_STALL_CYCLES_UCHE = 2, 477 PERF_VPC_STALL_CYCLES_VFD_WACK = 3, 478 PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4, 479 PERF_VPC_STALL_CYCLES_PC = 5, 480 PERF_VPC_STALL_CYCLES_SP_LM = 6, 481 PERF_VPC_STARVE_CYCLES_SP = 7, 482 PERF_VPC_STARVE_CYCLES_LRZ = 8, 483 PERF_VPC_PC_PRIMITIVES = 9, 484 PERF_VPC_SP_COMPONENTS = 10, 485 PERF_VPC_STALL_CYCLES_VPCRAM_POS = 11, 486 PERF_VPC_LRZ_ASSIGN_PRIMITIVES = 12, 487 PERF_VPC_RB_VISIBLE_PRIMITIVES = 13, 488 PERF_VPC_LM_TRANSACTION = 14, 489 PERF_VPC_STREAMOUT_TRANSACTION = 15, 490 PERF_VPC_VS_BUSY_CYCLES = 16, 491 PERF_VPC_PS_BUSY_CYCLES = 17, 492 PERF_VPC_VS_WORKING_CYCLES = 18, 493 PERF_VPC_PS_WORKING_CYCLES = 19, 494 PERF_VPC_STARVE_CYCLES_RB = 20, 495 PERF_VPC_NUM_VPCRAM_READ_POS = 21, 496 PERF_VPC_WIT_FULL_CYCLES = 22, 497 PERF_VPC_VPCRAM_FULL_CYCLES = 23, 498 PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = 24, 499 PERF_VPC_NUM_VPCRAM_WRITE = 25, 500 PERF_VPC_NUM_VPCRAM_READ_SO = 26, 501 PERF_VPC_NUM_ATTR_REQ_LM = 27, 502 }; 503 504 enum a6xx_tse_perfcounter_select { 505 PERF_TSE_BUSY_CYCLES = 0, 506 PERF_TSE_CLIPPING_CYCLES = 1, 507 PERF_TSE_STALL_CYCLES_RAS = 2, 508 PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3, 509 PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4, 510 PERF_TSE_STARVE_CYCLES_PC = 5, 511 PERF_TSE_INPUT_PRIM = 6, 512 PERF_TSE_INPUT_NULL_PRIM = 7, 513 PERF_TSE_TRIVAL_REJ_PRIM = 8, 514 PERF_TSE_CLIPPED_PRIM = 9, 515 PERF_TSE_ZERO_AREA_PRIM = 10, 516 PERF_TSE_FACENESS_CULLED_PRIM = 11, 517 PERF_TSE_ZERO_PIXEL_PRIM = 12, 518 PERF_TSE_OUTPUT_NULL_PRIM = 13, 519 PERF_TSE_OUTPUT_VISIBLE_PRIM = 14, 520 PERF_TSE_CINVOCATION = 15, 521 PERF_TSE_CPRIMITIVES = 16, 522 PERF_TSE_2D_INPUT_PRIM = 17, 523 PERF_TSE_2D_ALIVE_CYCLES = 18, 524 PERF_TSE_CLIP_PLANES = 19, 525 }; 526 527 enum a6xx_ras_perfcounter_select { 528 PERF_RAS_BUSY_CYCLES = 0, 529 PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1, 530 PERF_RAS_STALL_CYCLES_LRZ = 2, 531 PERF_RAS_STARVE_CYCLES_TSE = 3, 532 PERF_RAS_SUPER_TILES = 4, 533 PERF_RAS_8X4_TILES = 5, 534 PERF_RAS_MASKGEN_ACTIVE = 6, 535 PERF_RAS_FULLY_COVERED_SUPER_TILES = 7, 536 PERF_RAS_FULLY_COVERED_8X4_TILES = 8, 537 PERF_RAS_PRIM_KILLED_INVISILBE = 9, 538 PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 10, 539 PERF_RAS_LRZ_INTF_WORKING_CYCLES = 11, 540 PERF_RAS_BLOCKS = 12, 541 }; 542 543 enum a6xx_uche_perfcounter_select { 544 PERF_UCHE_BUSY_CYCLES = 0, 545 PERF_UCHE_STALL_CYCLES_ARBITER = 1, 546 PERF_UCHE_VBIF_LATENCY_CYCLES = 2, 547 PERF_UCHE_VBIF_LATENCY_SAMPLES = 3, 548 PERF_UCHE_VBIF_READ_BEATS_TP = 4, 549 PERF_UCHE_VBIF_READ_BEATS_VFD = 5, 550 PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6, 551 PERF_UCHE_VBIF_READ_BEATS_LRZ = 7, 552 PERF_UCHE_VBIF_READ_BEATS_SP = 8, 553 PERF_UCHE_READ_REQUESTS_TP = 9, 554 PERF_UCHE_READ_REQUESTS_VFD = 10, 555 PERF_UCHE_READ_REQUESTS_HLSQ = 11, 556 PERF_UCHE_READ_REQUESTS_LRZ = 12, 557 PERF_UCHE_READ_REQUESTS_SP = 13, 558 PERF_UCHE_WRITE_REQUESTS_LRZ = 14, 559 PERF_UCHE_WRITE_REQUESTS_SP = 15, 560 PERF_UCHE_WRITE_REQUESTS_VPC = 16, 561 PERF_UCHE_WRITE_REQUESTS_VSC = 17, 562 PERF_UCHE_EVICTS = 18, 563 PERF_UCHE_BANK_REQ0 = 19, 564 PERF_UCHE_BANK_REQ1 = 20, 565 PERF_UCHE_BANK_REQ2 = 21, 566 PERF_UCHE_BANK_REQ3 = 22, 567 PERF_UCHE_BANK_REQ4 = 23, 568 PERF_UCHE_BANK_REQ5 = 24, 569 PERF_UCHE_BANK_REQ6 = 25, 570 PERF_UCHE_BANK_REQ7 = 26, 571 PERF_UCHE_VBIF_READ_BEATS_CH0 = 27, 572 PERF_UCHE_VBIF_READ_BEATS_CH1 = 28, 573 PERF_UCHE_GMEM_READ_BEATS = 29, 574 PERF_UCHE_TPH_REF_FULL = 30, 575 PERF_UCHE_TPH_VICTIM_FULL = 31, 576 PERF_UCHE_TPH_EXT_FULL = 32, 577 PERF_UCHE_VBIF_STALL_WRITE_DATA = 33, 578 PERF_UCHE_DCMP_LATENCY_SAMPLES = 34, 579 PERF_UCHE_DCMP_LATENCY_CYCLES = 35, 580 PERF_UCHE_VBIF_READ_BEATS_PC = 36, 581 PERF_UCHE_READ_REQUESTS_PC = 37, 582 PERF_UCHE_RAM_READ_REQ = 38, 583 PERF_UCHE_RAM_WRITE_REQ = 39, 584 }; 585 586 enum a6xx_tp_perfcounter_select { 587 PERF_TP_BUSY_CYCLES = 0, 588 PERF_TP_STALL_CYCLES_UCHE = 1, 589 PERF_TP_LATENCY_CYCLES = 2, 590 PERF_TP_LATENCY_TRANS = 3, 591 PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4, 592 PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5, 593 PERF_TP_L1_CACHELINE_REQUESTS = 6, 594 PERF_TP_L1_CACHELINE_MISSES = 7, 595 PERF_TP_SP_TP_TRANS = 8, 596 PERF_TP_TP_SP_TRANS = 9, 597 PERF_TP_OUTPUT_PIXELS = 10, 598 PERF_TP_FILTER_WORKLOAD_16BIT = 11, 599 PERF_TP_FILTER_WORKLOAD_32BIT = 12, 600 PERF_TP_QUADS_RECEIVED = 13, 601 PERF_TP_QUADS_OFFSET = 14, 602 PERF_TP_QUADS_SHADOW = 15, 603 PERF_TP_QUADS_ARRAY = 16, 604 PERF_TP_QUADS_GRADIENT = 17, 605 PERF_TP_QUADS_1D = 18, 606 PERF_TP_QUADS_2D = 19, 607 PERF_TP_QUADS_BUFFER = 20, 608 PERF_TP_QUADS_3D = 21, 609 PERF_TP_QUADS_CUBE = 22, 610 PERF_TP_DIVERGENT_QUADS_RECEIVED = 23, 611 PERF_TP_PRT_NON_RESIDENT_EVENTS = 24, 612 PERF_TP_OUTPUT_PIXELS_POINT = 25, 613 PERF_TP_OUTPUT_PIXELS_BILINEAR = 26, 614 PERF_TP_OUTPUT_PIXELS_MIP = 27, 615 PERF_TP_OUTPUT_PIXELS_ANISO = 28, 616 PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 29, 617 PERF_TP_FLAG_CACHE_REQUESTS = 30, 618 PERF_TP_FLAG_CACHE_MISSES = 31, 619 PERF_TP_L1_5_L2_REQUESTS = 32, 620 PERF_TP_2D_OUTPUT_PIXELS = 33, 621 PERF_TP_2D_OUTPUT_PIXELS_POINT = 34, 622 PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 35, 623 PERF_TP_2D_FILTER_WORKLOAD_16BIT = 36, 624 PERF_TP_2D_FILTER_WORKLOAD_32BIT = 37, 625 PERF_TP_TPA2TPC_TRANS = 38, 626 PERF_TP_L1_MISSES_ASTC_1TILE = 39, 627 PERF_TP_L1_MISSES_ASTC_2TILE = 40, 628 PERF_TP_L1_MISSES_ASTC_4TILE = 41, 629 PERF_TP_L1_5_L2_COMPRESS_REQS = 42, 630 PERF_TP_L1_5_L2_COMPRESS_MISS = 43, 631 PERF_TP_L1_BANK_CONFLICT = 44, 632 PERF_TP_L1_5_MISS_LATENCY_CYCLES = 45, 633 PERF_TP_L1_5_MISS_LATENCY_TRANS = 46, 634 PERF_TP_QUADS_CONSTANT_MULTIPLIED = 47, 635 PERF_TP_FRONTEND_WORKING_CYCLES = 48, 636 PERF_TP_L1_TAG_WORKING_CYCLES = 49, 637 PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 50, 638 PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 51, 639 PERF_TP_BACKEND_WORKING_CYCLES = 52, 640 PERF_TP_FLAG_CACHE_WORKING_CYCLES = 53, 641 PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54, 642 PERF_TP_STARVE_CYCLES_SP = 55, 643 PERF_TP_STARVE_CYCLES_UCHE = 56, 644 }; 645 646 enum a6xx_sp_perfcounter_select { 647 PERF_SP_BUSY_CYCLES = 0, 648 PERF_SP_ALU_WORKING_CYCLES = 1, 649 PERF_SP_EFU_WORKING_CYCLES = 2, 650 PERF_SP_STALL_CYCLES_VPC = 3, 651 PERF_SP_STALL_CYCLES_TP = 4, 652 PERF_SP_STALL_CYCLES_UCHE = 5, 653 PERF_SP_STALL_CYCLES_RB = 6, 654 PERF_SP_NON_EXECUTION_CYCLES = 7, 655 PERF_SP_WAVE_CONTEXTS = 8, 656 PERF_SP_WAVE_CONTEXT_CYCLES = 9, 657 PERF_SP_FS_STAGE_WAVE_CYCLES = 10, 658 PERF_SP_FS_STAGE_WAVE_SAMPLES = 11, 659 PERF_SP_VS_STAGE_WAVE_CYCLES = 12, 660 PERF_SP_VS_STAGE_WAVE_SAMPLES = 13, 661 PERF_SP_FS_STAGE_DURATION_CYCLES = 14, 662 PERF_SP_VS_STAGE_DURATION_CYCLES = 15, 663 PERF_SP_WAVE_CTRL_CYCLES = 16, 664 PERF_SP_WAVE_LOAD_CYCLES = 17, 665 PERF_SP_WAVE_EMIT_CYCLES = 18, 666 PERF_SP_WAVE_NOP_CYCLES = 19, 667 PERF_SP_WAVE_WAIT_CYCLES = 20, 668 PERF_SP_WAVE_FETCH_CYCLES = 21, 669 PERF_SP_WAVE_IDLE_CYCLES = 22, 670 PERF_SP_WAVE_END_CYCLES = 23, 671 PERF_SP_WAVE_LONG_SYNC_CYCLES = 24, 672 PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25, 673 PERF_SP_WAVE_JOIN_CYCLES = 26, 674 PERF_SP_LM_LOAD_INSTRUCTIONS = 27, 675 PERF_SP_LM_STORE_INSTRUCTIONS = 28, 676 PERF_SP_LM_ATOMICS = 29, 677 PERF_SP_GM_LOAD_INSTRUCTIONS = 30, 678 PERF_SP_GM_STORE_INSTRUCTIONS = 31, 679 PERF_SP_GM_ATOMICS = 32, 680 PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33, 681 PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34, 682 PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35, 683 PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36, 684 PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37, 685 PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38, 686 PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39, 687 PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40, 688 PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41, 689 PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42, 690 PERF_SP_VS_INSTRUCTIONS = 43, 691 PERF_SP_FS_INSTRUCTIONS = 44, 692 PERF_SP_ADDR_LOCK_COUNT = 45, 693 PERF_SP_UCHE_READ_TRANS = 46, 694 PERF_SP_UCHE_WRITE_TRANS = 47, 695 PERF_SP_EXPORT_VPC_TRANS = 48, 696 PERF_SP_EXPORT_RB_TRANS = 49, 697 PERF_SP_PIXELS_KILLED = 50, 698 PERF_SP_ICL1_REQUESTS = 51, 699 PERF_SP_ICL1_MISSES = 52, 700 PERF_SP_HS_INSTRUCTIONS = 53, 701 PERF_SP_DS_INSTRUCTIONS = 54, 702 PERF_SP_GS_INSTRUCTIONS = 55, 703 PERF_SP_CS_INSTRUCTIONS = 56, 704 PERF_SP_GPR_READ = 57, 705 PERF_SP_GPR_WRITE = 58, 706 PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59, 707 PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60, 708 PERF_SP_LM_BANK_CONFLICTS = 61, 709 PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62, 710 PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63, 711 PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64, 712 PERF_SP_LM_WORKING_CYCLES = 65, 713 PERF_SP_DISPATCHER_WORKING_CYCLES = 66, 714 PERF_SP_SEQUENCER_WORKING_CYCLES = 67, 715 PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68, 716 PERF_SP_STARVE_CYCLES_HLSQ = 69, 717 PERF_SP_NON_EXECUTION_LS_CYCLES = 70, 718 PERF_SP_WORKING_EU = 71, 719 PERF_SP_ANY_EU_WORKING = 72, 720 PERF_SP_WORKING_EU_FS_STAGE = 73, 721 PERF_SP_ANY_EU_WORKING_FS_STAGE = 74, 722 PERF_SP_WORKING_EU_VS_STAGE = 75, 723 PERF_SP_ANY_EU_WORKING_VS_STAGE = 76, 724 PERF_SP_WORKING_EU_CS_STAGE = 77, 725 PERF_SP_ANY_EU_WORKING_CS_STAGE = 78, 726 PERF_SP_GPR_READ_PREFETCH = 79, 727 PERF_SP_GPR_READ_CONFLICT = 80, 728 PERF_SP_GPR_WRITE_CONFLICT = 81, 729 PERF_SP_GM_LOAD_LATENCY_CYCLES = 82, 730 PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83, 731 PERF_SP_EXECUTABLE_WAVES = 84, 732 }; 733 734 enum a6xx_rb_perfcounter_select { 735 PERF_RB_BUSY_CYCLES = 0, 736 PERF_RB_STALL_CYCLES_HLSQ = 1, 737 PERF_RB_STALL_CYCLES_FIFO0_FULL = 2, 738 PERF_RB_STALL_CYCLES_FIFO1_FULL = 3, 739 PERF_RB_STALL_CYCLES_FIFO2_FULL = 4, 740 PERF_RB_STARVE_CYCLES_SP = 5, 741 PERF_RB_STARVE_CYCLES_LRZ_TILE = 6, 742 PERF_RB_STARVE_CYCLES_CCU = 7, 743 PERF_RB_STARVE_CYCLES_Z_PLANE = 8, 744 PERF_RB_STARVE_CYCLES_BARY_PLANE = 9, 745 PERF_RB_Z_WORKLOAD = 10, 746 PERF_RB_HLSQ_ACTIVE = 11, 747 PERF_RB_Z_READ = 12, 748 PERF_RB_Z_WRITE = 13, 749 PERF_RB_C_READ = 14, 750 PERF_RB_C_WRITE = 15, 751 PERF_RB_TOTAL_PASS = 16, 752 PERF_RB_Z_PASS = 17, 753 PERF_RB_Z_FAIL = 18, 754 PERF_RB_S_FAIL = 19, 755 PERF_RB_BLENDED_FXP_COMPONENTS = 20, 756 PERF_RB_BLENDED_FP16_COMPONENTS = 21, 757 PERF_RB_PS_INVOCATIONS = 22, 758 PERF_RB_2D_ALIVE_CYCLES = 23, 759 PERF_RB_2D_STALL_CYCLES_A2D = 24, 760 PERF_RB_2D_STARVE_CYCLES_SRC = 25, 761 PERF_RB_2D_STARVE_CYCLES_SP = 26, 762 PERF_RB_2D_STARVE_CYCLES_DST = 27, 763 PERF_RB_2D_VALID_PIXELS = 28, 764 PERF_RB_3D_PIXELS = 29, 765 PERF_RB_BLENDER_WORKING_CYCLES = 30, 766 PERF_RB_ZPROC_WORKING_CYCLES = 31, 767 PERF_RB_CPROC_WORKING_CYCLES = 32, 768 PERF_RB_SAMPLER_WORKING_CYCLES = 33, 769 PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 34, 770 PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 35, 771 PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 36, 772 PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 37, 773 PERF_RB_STALL_CYCLES_VPC = 38, 774 PERF_RB_2D_INPUT_TRANS = 39, 775 PERF_RB_2D_OUTPUT_RB_DST_TRANS = 40, 776 PERF_RB_2D_OUTPUT_RB_SRC_TRANS = 41, 777 PERF_RB_BLENDED_FP32_COMPONENTS = 42, 778 PERF_RB_COLOR_PIX_TILES = 43, 779 PERF_RB_STALL_CYCLES_CCU = 44, 780 PERF_RB_EARLY_Z_ARB3_GRANT = 45, 781 PERF_RB_LATE_Z_ARB3_GRANT = 46, 782 PERF_RB_EARLY_Z_SKIP_GRANT = 47, 783 }; 784 785 enum a6xx_vsc_perfcounter_select { 786 PERF_VSC_BUSY_CYCLES = 0, 787 PERF_VSC_WORKING_CYCLES = 1, 788 PERF_VSC_STALL_CYCLES_UCHE = 2, 789 PERF_VSC_EOT_NUM = 3, 790 PERF_VSC_INPUT_TILES = 4, 791 }; 792 793 enum a6xx_ccu_perfcounter_select { 794 PERF_CCU_BUSY_CYCLES = 0, 795 PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1, 796 PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2, 797 PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3, 798 PERF_CCU_DEPTH_BLOCKS = 4, 799 PERF_CCU_COLOR_BLOCKS = 5, 800 PERF_CCU_DEPTH_BLOCK_HIT = 6, 801 PERF_CCU_COLOR_BLOCK_HIT = 7, 802 PERF_CCU_PARTIAL_BLOCK_READ = 8, 803 PERF_CCU_GMEM_READ = 9, 804 PERF_CCU_GMEM_WRITE = 10, 805 PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11, 806 PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12, 807 PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13, 808 PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14, 809 PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15, 810 PERF_CCU_DEPTH_READ_FLAG5_COUNT = 16, 811 PERF_CCU_DEPTH_READ_FLAG6_COUNT = 17, 812 PERF_CCU_DEPTH_READ_FLAG8_COUNT = 18, 813 PERF_CCU_COLOR_READ_FLAG0_COUNT = 19, 814 PERF_CCU_COLOR_READ_FLAG1_COUNT = 20, 815 PERF_CCU_COLOR_READ_FLAG2_COUNT = 21, 816 PERF_CCU_COLOR_READ_FLAG3_COUNT = 22, 817 PERF_CCU_COLOR_READ_FLAG4_COUNT = 23, 818 PERF_CCU_COLOR_READ_FLAG5_COUNT = 24, 819 PERF_CCU_COLOR_READ_FLAG6_COUNT = 25, 820 PERF_CCU_COLOR_READ_FLAG8_COUNT = 26, 821 PERF_CCU_2D_RD_REQ = 27, 822 PERF_CCU_2D_WR_REQ = 28, 823 }; 824 825 enum a6xx_lrz_perfcounter_select { 826 PERF_LRZ_BUSY_CYCLES = 0, 827 PERF_LRZ_STARVE_CYCLES_RAS = 1, 828 PERF_LRZ_STALL_CYCLES_RB = 2, 829 PERF_LRZ_STALL_CYCLES_VSC = 3, 830 PERF_LRZ_STALL_CYCLES_VPC = 4, 831 PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5, 832 PERF_LRZ_STALL_CYCLES_UCHE = 6, 833 PERF_LRZ_LRZ_READ = 7, 834 PERF_LRZ_LRZ_WRITE = 8, 835 PERF_LRZ_READ_LATENCY = 9, 836 PERF_LRZ_MERGE_CACHE_UPDATING = 10, 837 PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11, 838 PERF_LRZ_PRIM_KILLED_BY_LRZ = 12, 839 PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13, 840 PERF_LRZ_FULL_8X8_TILES = 14, 841 PERF_LRZ_PARTIAL_8X8_TILES = 15, 842 PERF_LRZ_TILE_KILLED = 16, 843 PERF_LRZ_TOTAL_PIXEL = 17, 844 PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18, 845 PERF_LRZ_FULLY_COVERED_TILES = 19, 846 PERF_LRZ_PARTIAL_COVERED_TILES = 20, 847 PERF_LRZ_FEEDBACK_ACCEPT = 21, 848 PERF_LRZ_FEEDBACK_DISCARD = 22, 849 PERF_LRZ_FEEDBACK_STALL = 23, 850 PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 24, 851 PERF_LRZ_STALL_CYCLES_RB_BPLANE = 25, 852 PERF_LRZ_STALL_CYCLES_VC = 26, 853 PERF_LRZ_RAS_MASK_TRANS = 27, 854 }; 855 856 enum a6xx_cmp_perfcounter_select { 857 PERF_CMPDECMP_STALL_CYCLES_ARB = 0, 858 PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1, 859 PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2, 860 PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3, 861 PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4, 862 PERF_CMPDECMP_VBIF_READ_REQUEST = 5, 863 PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6, 864 PERF_CMPDECMP_VBIF_READ_DATA = 7, 865 PERF_CMPDECMP_VBIF_WRITE_DATA = 8, 866 PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9, 867 PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10, 868 PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11, 869 PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12, 870 PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13, 871 PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14, 872 PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 15, 873 PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 16, 874 PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 17, 875 PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 18, 876 PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 19, 877 PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 20, 878 PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 21, 879 PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 22, 880 PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 23, 881 PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 24, 882 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 25, 883 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 26, 884 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 27, 885 PERF_CMPDECMP_2D_RD_DATA = 28, 886 PERF_CMPDECMP_2D_WR_DATA = 29, 887 PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 30, 888 PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 31, 889 PERF_CMPDECMP_2D_OUTPUT_TRANS = 32, 890 PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 33, 891 PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 34, 892 PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 35, 893 PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 36, 894 PERF_CMPDECMP_2D_BUSY_CYCLES = 37, 895 PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = 38, 896 PERF_CMPDECMP_2D_PIXELS = 39, 897 }; 898 899 enum a6xx_2d_ifmt { 900 R2D_UNORM8 = 16, 901 R2D_INT32 = 7, 902 R2D_INT16 = 6, 903 R2D_INT8 = 5, 904 R2D_FLOAT32 = 4, 905 R2D_FLOAT16 = 3, 906 R2D_UNORM8_SRGB = 1, 907 R2D_RAW = 0, 908 }; 909 910 enum a6xx_ztest_mode { 911 A6XX_EARLY_Z = 0, 912 A6XX_LATE_Z = 1, 913 A6XX_EARLY_LRZ_LATE_Z = 2, 914 A6XX_INVALID_ZTEST = 3, 915 }; 916 917 enum a6xx_sequenced_thread_dist { 918 DIST_SCREEN_COORD = 0, 919 DIST_ALL_TO_RB0 = 1, 920 }; 921 922 enum a6xx_single_prim_mode { 923 NO_FLUSH = 0, 924 FLUSH_PER_OVERLAP_AND_OVERWRITE = 1, 925 FLUSH_PER_OVERLAP = 3, 926 }; 927 928 enum a6xx_raster_mode { 929 TYPE_TILED = 0, 930 TYPE_WRITER = 1, 931 }; 932 933 enum a6xx_raster_direction { 934 LR_TB = 0, 935 RL_TB = 1, 936 LR_BT = 2, 937 RB_BT = 3, 938 }; 939 940 enum a6xx_render_mode { 941 RENDERING_PASS = 0, 942 BINNING_PASS = 1, 943 }; 944 945 enum a6xx_buffers_location { 946 BUFFERS_IN_GMEM = 0, 947 BUFFERS_IN_SYSMEM = 3, 948 }; 949 950 enum a6xx_lrz_dir_status { 951 LRZ_DIR_LE = 1, 952 LRZ_DIR_GE = 2, 953 LRZ_DIR_INVALID = 3, 954 }; 955 956 enum a6xx_fragcoord_sample_mode { 957 FRAGCOORD_CENTER = 0, 958 FRAGCOORD_SAMPLE = 3, 959 }; 960 961 enum a6xx_rotation { 962 ROTATE_0 = 0, 963 ROTATE_90 = 1, 964 ROTATE_180 = 2, 965 ROTATE_270 = 3, 966 ROTATE_HFLIP = 4, 967 ROTATE_VFLIP = 5, 968 }; 969 970 enum a6xx_tess_spacing { 971 TESS_EQUAL = 0, 972 TESS_FRACTIONAL_ODD = 2, 973 TESS_FRACTIONAL_EVEN = 3, 974 }; 975 976 enum a6xx_tess_output { 977 TESS_POINTS = 0, 978 TESS_LINES = 1, 979 TESS_CW_TRIS = 2, 980 TESS_CCW_TRIS = 3, 981 }; 982 983 enum a6xx_threadsize { 984 THREAD64 = 0, 985 THREAD128 = 1, 986 }; 987 988 enum a6xx_bindless_descriptor_size { 989 BINDLESS_DESCRIPTOR_16B = 1, 990 BINDLESS_DESCRIPTOR_64B = 3, 991 }; 992 993 enum a6xx_isam_mode { 994 ISAMMODE_GL = 2, 995 }; 996 997 enum a6xx_tex_filter { 998 A6XX_TEX_NEAREST = 0, 999 A6XX_TEX_LINEAR = 1, 1000 A6XX_TEX_ANISO = 2, 1001 A6XX_TEX_CUBIC = 3, 1002 }; 1003 1004 enum a6xx_tex_clamp { 1005 A6XX_TEX_REPEAT = 0, 1006 A6XX_TEX_CLAMP_TO_EDGE = 1, 1007 A6XX_TEX_MIRROR_REPEAT = 2, 1008 A6XX_TEX_CLAMP_TO_BORDER = 3, 1009 A6XX_TEX_MIRROR_CLAMP = 4, 1010 }; 1011 1012 enum a6xx_tex_aniso { 1013 A6XX_TEX_ANISO_1 = 0, 1014 A6XX_TEX_ANISO_2 = 1, 1015 A6XX_TEX_ANISO_4 = 2, 1016 A6XX_TEX_ANISO_8 = 3, 1017 A6XX_TEX_ANISO_16 = 4, 1018 }; 1019 1020 enum a6xx_reduction_mode { 1021 A6XX_REDUCTION_MODE_AVERAGE = 0, 1022 A6XX_REDUCTION_MODE_MIN = 1, 1023 A6XX_REDUCTION_MODE_MAX = 2, 1024 }; 1025 1026 enum a6xx_tex_swiz { 1027 A6XX_TEX_X = 0, 1028 A6XX_TEX_Y = 1, 1029 A6XX_TEX_Z = 2, 1030 A6XX_TEX_W = 3, 1031 A6XX_TEX_ZERO = 4, 1032 A6XX_TEX_ONE = 5, 1033 }; 1034 1035 enum a6xx_tex_type { 1036 A6XX_TEX_1D = 0, 1037 A6XX_TEX_2D = 1, 1038 A6XX_TEX_CUBE = 2, 1039 A6XX_TEX_3D = 3, 1040 A6XX_TEX_BUFFER = 4, 1041 }; 1042 1043 #define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001 1044 #define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR 0x00000002 1045 #define A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_0 0x00000010 1046 #define A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_1 0x00000020 1047 #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW 0x00000040 1048 #define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080 1049 #define A6XX_RBBM_INT_0_MASK_CP_SW 0x00000100 1050 #define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200 1051 #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400 1052 #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800 1053 #define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000 1054 #define A6XX_RBBM_INT_0_MASK_CP_IB2 0x00002000 1055 #define A6XX_RBBM_INT_0_MASK_CP_IB1 0x00004000 1056 #define A6XX_RBBM_INT_0_MASK_CP_RB 0x00008000 1057 #define A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPT 0x00008000 1058 #define A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPTLPAC 0x00010000 1059 #define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000 1060 #define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000 1061 #define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000 1062 #define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS_LPAC 0x00200000 1063 #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000 1064 #define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT 0x00800000 1065 #define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000 1066 #define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000 1067 #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000 1068 #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000 1069 #define A6XX_RBBM_INT_0_MASK_TSBWRITEERROR 0x10000000 1070 #define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000 1071 #define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000 1072 #define A6XX_CP_INT_CP_OPCODE_ERROR 0x00000001 1073 #define A6XX_CP_INT_CP_UCODE_ERROR 0x00000002 1074 #define A6XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004 1075 #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010 1076 #define A6XX_CP_INT_CP_AHB_ERROR 0x00000020 1077 #define A6XX_CP_INT_CP_VSD_PARITY_ERROR 0x00000040 1078 #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR 0x00000080 1079 #define A6XX_CP_INT_CP_OPCODE_ERROR_LPAC 0x00000100 1080 #define A6XX_CP_INT_CP_UCODE_ERROR_LPAC 0x00000200 1081 #define A6XX_CP_INT_CP_HW_FAULT_ERROR_LPAC 0x00000400 1082 #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_LPAC 0x00000800 1083 #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_LPAC 0x00001000 1084 #define A6XX_CP_INT_CP_OPCODE_ERROR_BV 0x00002000 1085 #define A6XX_CP_INT_CP_UCODE_ERROR_BV 0x00004000 1086 #define A6XX_CP_INT_CP_HW_FAULT_ERROR_BV 0x00008000 1087 #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_BV 0x00010000 1088 #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_BV 0x00020000 1089 #define REG_A6XX_CP_RB_BASE 0x00000800 1090 1091 #define REG_A6XX_CP_RB_CNTL 0x00000802 1092 1093 #define REG_A6XX_CP_RB_RPTR_ADDR 0x00000804 1094 1095 #define REG_A6XX_CP_RB_RPTR 0x00000806 1096 1097 #define REG_A6XX_CP_RB_WPTR 0x00000807 1098 1099 #define REG_A6XX_CP_SQE_CNTL 0x00000808 1100 1101 #define REG_A6XX_CP_CP2GMU_STATUS 0x00000812 1102 #define A6XX_CP_CP2GMU_STATUS_IFPC 0x00000001 1103 1104 #define REG_A6XX_CP_HW_FAULT 0x00000821 1105 1106 #define REG_A6XX_CP_INTERRUPT_STATUS 0x00000823 1107 1108 #define REG_A6XX_CP_PROTECT_STATUS 0x00000824 1109 1110 #define REG_A6XX_CP_STATUS_1 0x00000825 1111 1112 #define REG_A6XX_CP_SQE_INSTR_BASE 0x00000830 1113 1114 #define REG_A6XX_CP_MISC_CNTL 0x00000840 1115 1116 #define REG_A6XX_CP_APRIV_CNTL 0x00000844 1117 1118 #define REG_A6XX_CP_PREEMPT_THRESHOLD 0x000008c0 1119 1120 #define REG_A6XX_CP_ROQ_THRESHOLDS_1 0x000008c1 1121 #define A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK 0x000000ff 1122 #define A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT 0 1123 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_MRB_START(uint32_t val) 1124 { 1125 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK; 1126 } 1127 #define A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK 0x0000ff00 1128 #define A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT 8 1129 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_VSD_START(uint32_t val) 1130 { 1131 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK; 1132 } 1133 #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK 0x00ff0000 1134 #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT 16 1135 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val) 1136 { 1137 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK; 1138 } 1139 #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK 0xff000000 1140 #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT 24 1141 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val) 1142 { 1143 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK; 1144 } 1145 1146 #define REG_A6XX_CP_ROQ_THRESHOLDS_2 0x000008c2 1147 #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK 0x000001ff 1148 #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT 0 1149 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val) 1150 { 1151 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK; 1152 } 1153 #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK 0xffff0000 1154 #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT 16 1155 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val) 1156 { 1157 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK; 1158 } 1159 1160 #define REG_A6XX_CP_MEM_POOL_SIZE 0x000008c3 1161 1162 #define REG_A6XX_CP_CHICKEN_DBG 0x00000841 1163 1164 #define REG_A6XX_CP_ADDR_MODE_CNTL 0x00000842 1165 1166 #define REG_A6XX_CP_DBG_ECO_CNTL 0x00000843 1167 1168 #define REG_A6XX_CP_PROTECT_CNTL 0x0000084f 1169 1170 static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; } 1171 1172 static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; } 1173 1174 static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; } 1175 1176 static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; } 1177 #define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0003ffff 1178 #define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0 1179 static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) 1180 { 1181 return ((val) << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK; 1182 } 1183 #define A6XX_CP_PROTECT_REG_MASK_LEN__MASK 0x7ffc0000 1184 #define A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT 18 1185 static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) 1186 { 1187 return ((val) << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK; 1188 } 1189 #define A6XX_CP_PROTECT_REG_READ 0x80000000 1190 1191 #define REG_A6XX_CP_CONTEXT_SWITCH_CNTL 0x000008a0 1192 1193 #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO 0x000008a1 1194 1195 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR 0x000008a3 1196 1197 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR 0x000008a5 1198 1199 #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR 0x000008a7 1200 1201 #define REG_A7XX_CP_CONTEXT_SWITCH_LEVEL_STATUS 0x000008ab 1202 1203 static inline uint32_t REG_A6XX_CP_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008d0 + 0x1*i0; } 1204 1205 static inline uint32_t REG_A7XX_CP_BV_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008e0 + 0x1*i0; } 1206 1207 #define REG_A6XX_CP_CRASH_SCRIPT_BASE 0x00000900 1208 1209 #define REG_A6XX_CP_CRASH_DUMP_CNTL 0x00000902 1210 1211 #define REG_A6XX_CP_CRASH_DUMP_STATUS 0x00000903 1212 1213 #define REG_A6XX_CP_SQE_STAT_ADDR 0x00000908 1214 1215 #define REG_A6XX_CP_SQE_STAT_DATA 0x00000909 1216 1217 #define REG_A6XX_CP_DRAW_STATE_ADDR 0x0000090a 1218 1219 #define REG_A6XX_CP_DRAW_STATE_DATA 0x0000090b 1220 1221 #define REG_A6XX_CP_ROQ_DBG_ADDR 0x0000090c 1222 1223 #define REG_A6XX_CP_ROQ_DBG_DATA 0x0000090d 1224 1225 #define REG_A6XX_CP_MEM_POOL_DBG_ADDR 0x0000090e 1226 1227 #define REG_A6XX_CP_MEM_POOL_DBG_DATA 0x0000090f 1228 1229 #define REG_A6XX_CP_SQE_UCODE_DBG_ADDR 0x00000910 1230 1231 #define REG_A6XX_CP_SQE_UCODE_DBG_DATA 0x00000911 1232 1233 #define REG_A6XX_CP_IB1_BASE 0x00000928 1234 1235 #define REG_A6XX_CP_IB1_REM_SIZE 0x0000092a 1236 1237 #define REG_A6XX_CP_IB2_BASE 0x0000092b 1238 1239 #define REG_A6XX_CP_IB2_REM_SIZE 0x0000092d 1240 1241 #define REG_A6XX_CP_SDS_BASE 0x0000092e 1242 1243 #define REG_A6XX_CP_SDS_REM_SIZE 0x00000930 1244 1245 #define REG_A6XX_CP_MRB_BASE 0x00000931 1246 1247 #define REG_A6XX_CP_MRB_REM_SIZE 0x00000933 1248 1249 #define REG_A6XX_CP_VSD_BASE 0x00000934 1250 1251 #define REG_A6XX_CP_ROQ_RB_STAT 0x00000939 1252 #define A6XX_CP_ROQ_RB_STAT_RPTR__MASK 0x000003ff 1253 #define A6XX_CP_ROQ_RB_STAT_RPTR__SHIFT 0 1254 static inline uint32_t A6XX_CP_ROQ_RB_STAT_RPTR(uint32_t val) 1255 { 1256 return ((val) << A6XX_CP_ROQ_RB_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_RB_STAT_RPTR__MASK; 1257 } 1258 #define A6XX_CP_ROQ_RB_STAT_WPTR__MASK 0x03ff0000 1259 #define A6XX_CP_ROQ_RB_STAT_WPTR__SHIFT 16 1260 static inline uint32_t A6XX_CP_ROQ_RB_STAT_WPTR(uint32_t val) 1261 { 1262 return ((val) << A6XX_CP_ROQ_RB_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_RB_STAT_WPTR__MASK; 1263 } 1264 1265 #define REG_A6XX_CP_ROQ_IB1_STAT 0x0000093a 1266 #define A6XX_CP_ROQ_IB1_STAT_RPTR__MASK 0x000003ff 1267 #define A6XX_CP_ROQ_IB1_STAT_RPTR__SHIFT 0 1268 static inline uint32_t A6XX_CP_ROQ_IB1_STAT_RPTR(uint32_t val) 1269 { 1270 return ((val) << A6XX_CP_ROQ_IB1_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_IB1_STAT_RPTR__MASK; 1271 } 1272 #define A6XX_CP_ROQ_IB1_STAT_WPTR__MASK 0x03ff0000 1273 #define A6XX_CP_ROQ_IB1_STAT_WPTR__SHIFT 16 1274 static inline uint32_t A6XX_CP_ROQ_IB1_STAT_WPTR(uint32_t val) 1275 { 1276 return ((val) << A6XX_CP_ROQ_IB1_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_IB1_STAT_WPTR__MASK; 1277 } 1278 1279 #define REG_A6XX_CP_ROQ_IB2_STAT 0x0000093b 1280 #define A6XX_CP_ROQ_IB2_STAT_RPTR__MASK 0x000003ff 1281 #define A6XX_CP_ROQ_IB2_STAT_RPTR__SHIFT 0 1282 static inline uint32_t A6XX_CP_ROQ_IB2_STAT_RPTR(uint32_t val) 1283 { 1284 return ((val) << A6XX_CP_ROQ_IB2_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_IB2_STAT_RPTR__MASK; 1285 } 1286 #define A6XX_CP_ROQ_IB2_STAT_WPTR__MASK 0x03ff0000 1287 #define A6XX_CP_ROQ_IB2_STAT_WPTR__SHIFT 16 1288 static inline uint32_t A6XX_CP_ROQ_IB2_STAT_WPTR(uint32_t val) 1289 { 1290 return ((val) << A6XX_CP_ROQ_IB2_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_IB2_STAT_WPTR__MASK; 1291 } 1292 1293 #define REG_A6XX_CP_ROQ_SDS_STAT 0x0000093c 1294 #define A6XX_CP_ROQ_SDS_STAT_RPTR__MASK 0x000003ff 1295 #define A6XX_CP_ROQ_SDS_STAT_RPTR__SHIFT 0 1296 static inline uint32_t A6XX_CP_ROQ_SDS_STAT_RPTR(uint32_t val) 1297 { 1298 return ((val) << A6XX_CP_ROQ_SDS_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_SDS_STAT_RPTR__MASK; 1299 } 1300 #define A6XX_CP_ROQ_SDS_STAT_WPTR__MASK 0x03ff0000 1301 #define A6XX_CP_ROQ_SDS_STAT_WPTR__SHIFT 16 1302 static inline uint32_t A6XX_CP_ROQ_SDS_STAT_WPTR(uint32_t val) 1303 { 1304 return ((val) << A6XX_CP_ROQ_SDS_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_SDS_STAT_WPTR__MASK; 1305 } 1306 1307 #define REG_A6XX_CP_ROQ_MRB_STAT 0x0000093d 1308 #define A6XX_CP_ROQ_MRB_STAT_RPTR__MASK 0x000003ff 1309 #define A6XX_CP_ROQ_MRB_STAT_RPTR__SHIFT 0 1310 static inline uint32_t A6XX_CP_ROQ_MRB_STAT_RPTR(uint32_t val) 1311 { 1312 return ((val) << A6XX_CP_ROQ_MRB_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_MRB_STAT_RPTR__MASK; 1313 } 1314 #define A6XX_CP_ROQ_MRB_STAT_WPTR__MASK 0x03ff0000 1315 #define A6XX_CP_ROQ_MRB_STAT_WPTR__SHIFT 16 1316 static inline uint32_t A6XX_CP_ROQ_MRB_STAT_WPTR(uint32_t val) 1317 { 1318 return ((val) << A6XX_CP_ROQ_MRB_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_MRB_STAT_WPTR__MASK; 1319 } 1320 1321 #define REG_A6XX_CP_ROQ_VSD_STAT 0x0000093e 1322 #define A6XX_CP_ROQ_VSD_STAT_RPTR__MASK 0x000003ff 1323 #define A6XX_CP_ROQ_VSD_STAT_RPTR__SHIFT 0 1324 static inline uint32_t A6XX_CP_ROQ_VSD_STAT_RPTR(uint32_t val) 1325 { 1326 return ((val) << A6XX_CP_ROQ_VSD_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_VSD_STAT_RPTR__MASK; 1327 } 1328 #define A6XX_CP_ROQ_VSD_STAT_WPTR__MASK 0x03ff0000 1329 #define A6XX_CP_ROQ_VSD_STAT_WPTR__SHIFT 16 1330 static inline uint32_t A6XX_CP_ROQ_VSD_STAT_WPTR(uint32_t val) 1331 { 1332 return ((val) << A6XX_CP_ROQ_VSD_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_VSD_STAT_WPTR__MASK; 1333 } 1334 1335 #define REG_A6XX_CP_IB1_DWORDS 0x00000943 1336 1337 #define REG_A6XX_CP_IB2_DWORDS 0x00000944 1338 1339 #define REG_A6XX_CP_SDS_DWORDS 0x00000945 1340 1341 #define REG_A6XX_CP_MRB_DWORDS 0x00000946 1342 1343 #define REG_A6XX_CP_VSD_DWORDS 0x00000947 1344 1345 #define REG_A6XX_CP_ROQ_AVAIL_RB 0x00000948 1346 #define A6XX_CP_ROQ_AVAIL_RB_REM__MASK 0xffff0000 1347 #define A6XX_CP_ROQ_AVAIL_RB_REM__SHIFT 16 1348 static inline uint32_t A6XX_CP_ROQ_AVAIL_RB_REM(uint32_t val) 1349 { 1350 return ((val) << A6XX_CP_ROQ_AVAIL_RB_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_RB_REM__MASK; 1351 } 1352 1353 #define REG_A6XX_CP_ROQ_AVAIL_IB1 0x00000949 1354 #define A6XX_CP_ROQ_AVAIL_IB1_REM__MASK 0xffff0000 1355 #define A6XX_CP_ROQ_AVAIL_IB1_REM__SHIFT 16 1356 static inline uint32_t A6XX_CP_ROQ_AVAIL_IB1_REM(uint32_t val) 1357 { 1358 return ((val) << A6XX_CP_ROQ_AVAIL_IB1_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_IB1_REM__MASK; 1359 } 1360 1361 #define REG_A6XX_CP_ROQ_AVAIL_IB2 0x0000094a 1362 #define A6XX_CP_ROQ_AVAIL_IB2_REM__MASK 0xffff0000 1363 #define A6XX_CP_ROQ_AVAIL_IB2_REM__SHIFT 16 1364 static inline uint32_t A6XX_CP_ROQ_AVAIL_IB2_REM(uint32_t val) 1365 { 1366 return ((val) << A6XX_CP_ROQ_AVAIL_IB2_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_IB2_REM__MASK; 1367 } 1368 1369 #define REG_A6XX_CP_ROQ_AVAIL_SDS 0x0000094b 1370 #define A6XX_CP_ROQ_AVAIL_SDS_REM__MASK 0xffff0000 1371 #define A6XX_CP_ROQ_AVAIL_SDS_REM__SHIFT 16 1372 static inline uint32_t A6XX_CP_ROQ_AVAIL_SDS_REM(uint32_t val) 1373 { 1374 return ((val) << A6XX_CP_ROQ_AVAIL_SDS_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_SDS_REM__MASK; 1375 } 1376 1377 #define REG_A6XX_CP_ROQ_AVAIL_MRB 0x0000094c 1378 #define A6XX_CP_ROQ_AVAIL_MRB_REM__MASK 0xffff0000 1379 #define A6XX_CP_ROQ_AVAIL_MRB_REM__SHIFT 16 1380 static inline uint32_t A6XX_CP_ROQ_AVAIL_MRB_REM(uint32_t val) 1381 { 1382 return ((val) << A6XX_CP_ROQ_AVAIL_MRB_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_MRB_REM__MASK; 1383 } 1384 1385 #define REG_A6XX_CP_ROQ_AVAIL_VSD 0x0000094d 1386 #define A6XX_CP_ROQ_AVAIL_VSD_REM__MASK 0xffff0000 1387 #define A6XX_CP_ROQ_AVAIL_VSD_REM__SHIFT 16 1388 static inline uint32_t A6XX_CP_ROQ_AVAIL_VSD_REM(uint32_t val) 1389 { 1390 return ((val) << A6XX_CP_ROQ_AVAIL_VSD_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_VSD_REM__MASK; 1391 } 1392 1393 #define REG_A6XX_CP_ALWAYS_ON_COUNTER 0x00000980 1394 1395 #define REG_A6XX_CP_AHB_CNTL 0x0000098d 1396 1397 #define REG_A6XX_CP_APERTURE_CNTL_HOST 0x00000a00 1398 1399 #define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03 1400 1401 #define REG_A7XX_CP_BV_PROTECT_STATUS 0x00000a61 1402 1403 #define REG_A7XX_CP_BV_HW_FAULT 0x00000a64 1404 1405 #define REG_A7XX_CP_BV_DRAW_STATE_ADDR 0x00000a81 1406 1407 #define REG_A7XX_CP_BV_DRAW_STATE_DATA 0x00000a82 1408 1409 #define REG_A7XX_CP_BV_ROQ_DBG_ADDR 0x00000a83 1410 1411 #define REG_A7XX_CP_BV_ROQ_DBG_DATA 0x00000a84 1412 1413 #define REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR 0x00000a85 1414 1415 #define REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA 0x00000a86 1416 1417 #define REG_A7XX_CP_BV_SQE_STAT_ADDR 0x00000a87 1418 1419 #define REG_A7XX_CP_BV_SQE_STAT_DATA 0x00000a88 1420 1421 #define REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR 0x00000a96 1422 1423 #define REG_A7XX_CP_BV_MEM_POOL_DBG_DATA 0x00000a97 1424 1425 #define REG_A7XX_CP_BV_RB_RPTR_ADDR 0x00000a98 1426 1427 #define REG_A7XX_CP_RESOURCE_TBL_DBG_ADDR 0x00000a9a 1428 1429 #define REG_A7XX_CP_RESOURCE_TBL_DBG_DATA 0x00000a9b 1430 1431 #define REG_A7XX_CP_BV_APRIV_CNTL 0x00000ad0 1432 1433 #define REG_A7XX_CP_BV_CHICKEN_DBG 0x00000ada 1434 1435 #define REG_A7XX_CP_LPAC_DRAW_STATE_ADDR 0x00000b0a 1436 1437 #define REG_A7XX_CP_LPAC_DRAW_STATE_DATA 0x00000b0b 1438 1439 #define REG_A7XX_CP_LPAC_ROQ_DBG_ADDR 0x00000b0c 1440 1441 #define REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR 0x00000b27 1442 1443 #define REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA 0x00000b28 1444 1445 #define REG_A7XX_CP_SQE_AC_STAT_ADDR 0x00000b29 1446 1447 #define REG_A7XX_CP_SQE_AC_STAT_DATA 0x00000b2a 1448 1449 #define REG_A7XX_CP_LPAC_APRIV_CNTL 0x00000b31 1450 1451 #define REG_A6XX_CP_LPAC_PROG_FIFO_SIZE 0x00000b34 1452 1453 #define REG_A7XX_CP_LPAC_ROQ_DBG_DATA 0x00000b35 1454 1455 #define REG_A7XX_CP_LPAC_FIFO_DBG_DATA 0x00000b36 1456 1457 #define REG_A7XX_CP_LPAC_FIFO_DBG_ADDR 0x00000b40 1458 1459 #define REG_A6XX_CP_LPAC_SQE_INSTR_BASE 0x00000b82 1460 1461 #define REG_A6XX_VSC_ADDR_MODE_CNTL 0x00000c01 1462 1463 #define REG_A6XX_RBBM_GPR0_CNTL 0x00000018 1464 1465 #define REG_A6XX_RBBM_INT_0_STATUS 0x00000201 1466 1467 #define REG_A6XX_RBBM_STATUS 0x00000210 1468 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x00800000 1469 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x00400000 1470 #define A6XX_RBBM_STATUS_HLSQ_BUSY 0x00200000 1471 #define A6XX_RBBM_STATUS_VSC_BUSY 0x00100000 1472 #define A6XX_RBBM_STATUS_TPL1_BUSY 0x00080000 1473 #define A6XX_RBBM_STATUS_SP_BUSY 0x00040000 1474 #define A6XX_RBBM_STATUS_UCHE_BUSY 0x00020000 1475 #define A6XX_RBBM_STATUS_VPC_BUSY 0x00010000 1476 #define A6XX_RBBM_STATUS_VFD_BUSY 0x00008000 1477 #define A6XX_RBBM_STATUS_TESS_BUSY 0x00004000 1478 #define A6XX_RBBM_STATUS_PC_VSD_BUSY 0x00002000 1479 #define A6XX_RBBM_STATUS_PC_DCALL_BUSY 0x00001000 1480 #define A6XX_RBBM_STATUS_COM_DCOM_BUSY 0x00000800 1481 #define A6XX_RBBM_STATUS_LRZ_BUSY 0x00000400 1482 #define A6XX_RBBM_STATUS_A2D_BUSY 0x00000200 1483 #define A6XX_RBBM_STATUS_CCU_BUSY 0x00000100 1484 #define A6XX_RBBM_STATUS_RB_BUSY 0x00000080 1485 #define A6XX_RBBM_STATUS_RAS_BUSY 0x00000040 1486 #define A6XX_RBBM_STATUS_TSE_BUSY 0x00000020 1487 #define A6XX_RBBM_STATUS_VBIF_BUSY 0x00000010 1488 #define A6XX_RBBM_STATUS_GFX_DBGC_BUSY 0x00000008 1489 #define A6XX_RBBM_STATUS_CP_BUSY 0x00000004 1490 #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER 0x00000002 1491 #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER 0x00000001 1492 1493 #define REG_A6XX_RBBM_STATUS1 0x00000211 1494 1495 #define REG_A6XX_RBBM_STATUS2 0x00000212 1496 1497 #define REG_A6XX_RBBM_STATUS3 0x00000213 1498 #define A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT 0x01000000 1499 1500 #define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215 1501 1502 #define REG_A7XX_RBBM_CLOCK_MODE_CP 0x00000260 1503 1504 #define REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ 0x00000284 1505 1506 #define REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS 0x00000285 1507 1508 #define REG_A7XX_RBBM_CLOCK_MODE2_GRAS 0x00000286 1509 1510 #define REG_A7XX_RBBM_CLOCK_MODE_BV_VFD 0x00000287 1511 1512 #define REG_A7XX_RBBM_CLOCK_MODE_BV_GPC 0x00000288 1513 1514 static inline uint32_t REG_A6XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000400 + 0x2*i0; } 1515 1516 static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000041c + 0x2*i0; } 1517 1518 static inline uint32_t REG_A6XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000424 + 0x2*i0; } 1519 1520 static inline uint32_t REG_A6XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000434 + 0x2*i0; } 1521 1522 static inline uint32_t REG_A6XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000444 + 0x2*i0; } 1523 1524 static inline uint32_t REG_A6XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000450 + 0x2*i0; } 1525 1526 static inline uint32_t REG_A6XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000045c + 0x2*i0; } 1527 1528 static inline uint32_t REG_A6XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000466 + 0x2*i0; } 1529 1530 static inline uint32_t REG_A6XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000046e + 0x2*i0; } 1531 1532 static inline uint32_t REG_A6XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000476 + 0x2*i0; } 1533 1534 static inline uint32_t REG_A6XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000048e + 0x2*i0; } 1535 1536 static inline uint32_t REG_A6XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000004a6 + 0x2*i0; } 1537 1538 static inline uint32_t REG_A6XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000004d6 + 0x2*i0; } 1539 1540 static inline uint32_t REG_A6XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000004e6 + 0x2*i0; } 1541 1542 static inline uint32_t REG_A6XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000004ea + 0x2*i0; } 1543 1544 static inline uint32_t REG_A6XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000004f2 + 0x2*i0; } 1545 1546 static inline uint32_t REG_A7XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000300 + 0x2*i0; } 1547 1548 static inline uint32_t REG_A7XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000031c + 0x2*i0; } 1549 1550 static inline uint32_t REG_A7XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000324 + 0x2*i0; } 1551 1552 static inline uint32_t REG_A7XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000334 + 0x2*i0; } 1553 1554 static inline uint32_t REG_A7XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000344 + 0x2*i0; } 1555 1556 static inline uint32_t REG_A7XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000350 + 0x2*i0; } 1557 1558 static inline uint32_t REG_A7XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000035c + 0x2*i0; } 1559 1560 static inline uint32_t REG_A7XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000366 + 0x2*i0; } 1561 1562 static inline uint32_t REG_A7XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000036e + 0x2*i0; } 1563 1564 static inline uint32_t REG_A7XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000376 + 0x2*i0; } 1565 1566 static inline uint32_t REG_A7XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000038e + 0x2*i0; } 1567 1568 static inline uint32_t REG_A7XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000003a6 + 0x2*i0; } 1569 1570 static inline uint32_t REG_A7XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000003d6 + 0x2*i0; } 1571 1572 static inline uint32_t REG_A7XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000003e6 + 0x2*i0; } 1573 1574 static inline uint32_t REG_A7XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000003ea + 0x2*i0; } 1575 1576 static inline uint32_t REG_A7XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000003f2 + 0x2*i0; } 1577 1578 static inline uint32_t REG_A7XX_RBBM_PERFCTR_UFC(uint32_t i0) { return 0x000003fa + 0x2*i0; } 1579 1580 static inline uint32_t REG_A7XX_RBBM_PERFCTR2_HLSQ(uint32_t i0) { return 0x00000410 + 0x2*i0; } 1581 1582 static inline uint32_t REG_A7XX_RBBM_PERFCTR2_CP(uint32_t i0) { return 0x0000041c + 0x2*i0; } 1583 1584 static inline uint32_t REG_A7XX_RBBM_PERFCTR2_SP(uint32_t i0) { return 0x0000042a + 0x2*i0; } 1585 1586 static inline uint32_t REG_A7XX_RBBM_PERFCTR2_TP(uint32_t i0) { return 0x00000442 + 0x2*i0; } 1587 1588 static inline uint32_t REG_A7XX_RBBM_PERFCTR2_UFC(uint32_t i0) { return 0x0000044e + 0x2*i0; } 1589 1590 static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_PC(uint32_t i0) { return 0x00000460 + 0x2*i0; } 1591 1592 static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_VFD(uint32_t i0) { return 0x00000470 + 0x2*i0; } 1593 1594 static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_VPC(uint32_t i0) { return 0x00000480 + 0x2*i0; } 1595 1596 static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_TSE(uint32_t i0) { return 0x0000048c + 0x2*i0; } 1597 1598 static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_RAS(uint32_t i0) { return 0x00000494 + 0x2*i0; } 1599 1600 static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_LRZ(uint32_t i0) { return 0x0000049c + 0x2*i0; } 1601 1602 #define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500 1603 1604 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 0x00000501 1605 1606 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 0x00000502 1607 1608 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 0x00000503 1609 1610 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 0x00000504 1611 1612 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000505 1613 1614 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506 1615 1616 static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00000507 + 0x1*i0; } 1617 1618 #define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b 1619 1620 #define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD 0x0000050e 1621 1622 #define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS 0x0000050f 1623 1624 #define REG_A6XX_RBBM_ISDB_CNT 0x00000533 1625 1626 #define REG_A7XX_RBBM_NC_MODE_CNTL 0x00000534 1627 1628 #define REG_A7XX_RBBM_SNAPSHOT_STATUS 0x00000535 1629 1630 #define REG_A6XX_RBBM_PRIMCTR_0_LO 0x00000540 1631 1632 #define REG_A6XX_RBBM_PRIMCTR_0_HI 0x00000541 1633 1634 #define REG_A6XX_RBBM_PRIMCTR_1_LO 0x00000542 1635 1636 #define REG_A6XX_RBBM_PRIMCTR_1_HI 0x00000543 1637 1638 #define REG_A6XX_RBBM_PRIMCTR_2_LO 0x00000544 1639 1640 #define REG_A6XX_RBBM_PRIMCTR_2_HI 0x00000545 1641 1642 #define REG_A6XX_RBBM_PRIMCTR_3_LO 0x00000546 1643 1644 #define REG_A6XX_RBBM_PRIMCTR_3_HI 0x00000547 1645 1646 #define REG_A6XX_RBBM_PRIMCTR_4_LO 0x00000548 1647 1648 #define REG_A6XX_RBBM_PRIMCTR_4_HI 0x00000549 1649 1650 #define REG_A6XX_RBBM_PRIMCTR_5_LO 0x0000054a 1651 1652 #define REG_A6XX_RBBM_PRIMCTR_5_HI 0x0000054b 1653 1654 #define REG_A6XX_RBBM_PRIMCTR_6_LO 0x0000054c 1655 1656 #define REG_A6XX_RBBM_PRIMCTR_6_HI 0x0000054d 1657 1658 #define REG_A6XX_RBBM_PRIMCTR_7_LO 0x0000054e 1659 1660 #define REG_A6XX_RBBM_PRIMCTR_7_HI 0x0000054f 1661 1662 #define REG_A6XX_RBBM_PRIMCTR_8_LO 0x00000550 1663 1664 #define REG_A6XX_RBBM_PRIMCTR_8_HI 0x00000551 1665 1666 #define REG_A6XX_RBBM_PRIMCTR_9_LO 0x00000552 1667 1668 #define REG_A6XX_RBBM_PRIMCTR_9_HI 0x00000553 1669 1670 #define REG_A6XX_RBBM_PRIMCTR_10_LO 0x00000554 1671 1672 #define REG_A6XX_RBBM_PRIMCTR_10_HI 0x00000555 1673 1674 #define REG_A6XX_RBBM_SECVID_TRUST_CNTL 0x0000f400 1675 1676 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE 0x0000f800 1677 1678 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802 1679 1680 #define REG_A6XX_RBBM_SECVID_TSB_CNTL 0x0000f803 1681 1682 #define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810 1683 1684 #define REG_A7XX_RBBM_SECVID_TSB_STATUS 0x0000fc00 1685 1686 #define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL 0x00000010 1687 1688 #define REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL 0x00000011 1689 1690 #define REG_A6XX_RBBM_GBIF_HALT 0x00000016 1691 1692 #define REG_A6XX_RBBM_GBIF_HALT_ACK 0x00000017 1693 1694 #define REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD 0x0000001c 1695 #define A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE 0x00000001 1696 1697 #define REG_A7XX_RBBM_GBIF_HALT 0x00000016 1698 1699 #define REG_A7XX_RBBM_GBIF_HALT_ACK 0x00000017 1700 1701 #define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000001f 1702 1703 #define REG_A6XX_RBBM_INT_CLEAR_CMD 0x00000037 1704 1705 #define REG_A6XX_RBBM_INT_0_MASK 0x00000038 1706 1707 #define REG_A7XX_RBBM_INT_2_MASK 0x0000003a 1708 1709 #define REG_A6XX_RBBM_SP_HYST_CNT 0x00000042 1710 1711 #define REG_A6XX_RBBM_SW_RESET_CMD 0x00000043 1712 1713 #define REG_A6XX_RBBM_RAC_THRESHOLD_CNT 0x00000044 1714 1715 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 1716 1717 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046 1718 1719 #define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae 1720 1721 #define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0 1722 1723 #define REG_A6XX_RBBM_CLOCK_CNTL_SP1 0x000000b1 1724 1725 #define REG_A6XX_RBBM_CLOCK_CNTL_SP2 0x000000b2 1726 1727 #define REG_A6XX_RBBM_CLOCK_CNTL_SP3 0x000000b3 1728 1729 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP0 0x000000b4 1730 1731 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP1 0x000000b5 1732 1733 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP2 0x000000b6 1734 1735 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP3 0x000000b7 1736 1737 #define REG_A6XX_RBBM_CLOCK_DELAY_SP0 0x000000b8 1738 1739 #define REG_A6XX_RBBM_CLOCK_DELAY_SP1 0x000000b9 1740 1741 #define REG_A6XX_RBBM_CLOCK_DELAY_SP2 0x000000ba 1742 1743 #define REG_A6XX_RBBM_CLOCK_DELAY_SP3 0x000000bb 1744 1745 #define REG_A6XX_RBBM_CLOCK_HYST_SP0 0x000000bc 1746 1747 #define REG_A6XX_RBBM_CLOCK_HYST_SP1 0x000000bd 1748 1749 #define REG_A6XX_RBBM_CLOCK_HYST_SP2 0x000000be 1750 1751 #define REG_A6XX_RBBM_CLOCK_HYST_SP3 0x000000bf 1752 1753 #define REG_A6XX_RBBM_CLOCK_CNTL_TP0 0x000000c0 1754 1755 #define REG_A6XX_RBBM_CLOCK_CNTL_TP1 0x000000c1 1756 1757 #define REG_A6XX_RBBM_CLOCK_CNTL_TP2 0x000000c2 1758 1759 #define REG_A6XX_RBBM_CLOCK_CNTL_TP3 0x000000c3 1760 1761 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP0 0x000000c4 1762 1763 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP1 0x000000c5 1764 1765 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP2 0x000000c6 1766 1767 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP3 0x000000c7 1768 1769 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP0 0x000000c8 1770 1771 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP1 0x000000c9 1772 1773 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP2 0x000000ca 1774 1775 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP3 0x000000cb 1776 1777 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP0 0x000000cc 1778 1779 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP1 0x000000cd 1780 1781 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP2 0x000000ce 1782 1783 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP3 0x000000cf 1784 1785 #define REG_A6XX_RBBM_CLOCK_DELAY_TP0 0x000000d0 1786 1787 #define REG_A6XX_RBBM_CLOCK_DELAY_TP1 0x000000d1 1788 1789 #define REG_A6XX_RBBM_CLOCK_DELAY_TP2 0x000000d2 1790 1791 #define REG_A6XX_RBBM_CLOCK_DELAY_TP3 0x000000d3 1792 1793 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP0 0x000000d4 1794 1795 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP1 0x000000d5 1796 1797 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP2 0x000000d6 1798 1799 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP3 0x000000d7 1800 1801 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP0 0x000000d8 1802 1803 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP1 0x000000d9 1804 1805 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP2 0x000000da 1806 1807 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP3 0x000000db 1808 1809 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP0 0x000000dc 1810 1811 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP1 0x000000dd 1812 1813 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP2 0x000000de 1814 1815 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP3 0x000000df 1816 1817 #define REG_A6XX_RBBM_CLOCK_HYST_TP0 0x000000e0 1818 1819 #define REG_A6XX_RBBM_CLOCK_HYST_TP1 0x000000e1 1820 1821 #define REG_A6XX_RBBM_CLOCK_HYST_TP2 0x000000e2 1822 1823 #define REG_A6XX_RBBM_CLOCK_HYST_TP3 0x000000e3 1824 1825 #define REG_A6XX_RBBM_CLOCK_HYST2_TP0 0x000000e4 1826 1827 #define REG_A6XX_RBBM_CLOCK_HYST2_TP1 0x000000e5 1828 1829 #define REG_A6XX_RBBM_CLOCK_HYST2_TP2 0x000000e6 1830 1831 #define REG_A6XX_RBBM_CLOCK_HYST2_TP3 0x000000e7 1832 1833 #define REG_A6XX_RBBM_CLOCK_HYST3_TP0 0x000000e8 1834 1835 #define REG_A6XX_RBBM_CLOCK_HYST3_TP1 0x000000e9 1836 1837 #define REG_A6XX_RBBM_CLOCK_HYST3_TP2 0x000000ea 1838 1839 #define REG_A6XX_RBBM_CLOCK_HYST3_TP3 0x000000eb 1840 1841 #define REG_A6XX_RBBM_CLOCK_HYST4_TP0 0x000000ec 1842 1843 #define REG_A6XX_RBBM_CLOCK_HYST4_TP1 0x000000ed 1844 1845 #define REG_A6XX_RBBM_CLOCK_HYST4_TP2 0x000000ee 1846 1847 #define REG_A6XX_RBBM_CLOCK_HYST4_TP3 0x000000ef 1848 1849 #define REG_A6XX_RBBM_CLOCK_CNTL_RB0 0x000000f0 1850 1851 #define REG_A6XX_RBBM_CLOCK_CNTL_RB1 0x000000f1 1852 1853 #define REG_A6XX_RBBM_CLOCK_CNTL_RB2 0x000000f2 1854 1855 #define REG_A6XX_RBBM_CLOCK_CNTL_RB3 0x000000f3 1856 1857 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB0 0x000000f4 1858 1859 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB1 0x000000f5 1860 1861 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB2 0x000000f6 1862 1863 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB3 0x000000f7 1864 1865 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU0 0x000000f8 1866 1867 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU1 0x000000f9 1868 1869 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU2 0x000000fa 1870 1871 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU3 0x000000fb 1872 1873 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000100 1874 1875 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000101 1876 1877 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000102 1878 1879 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000103 1880 1881 #define REG_A6XX_RBBM_CLOCK_CNTL_RAC 0x00000104 1882 1883 #define REG_A6XX_RBBM_CLOCK_CNTL2_RAC 0x00000105 1884 1885 #define REG_A6XX_RBBM_CLOCK_DELAY_RAC 0x00000106 1886 1887 #define REG_A6XX_RBBM_CLOCK_HYST_RAC 0x00000107 1888 1889 #define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000108 1890 1891 #define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000109 1892 1893 #define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000010a 1894 1895 #define REG_A6XX_RBBM_CLOCK_CNTL_UCHE 0x0000010b 1896 1897 #define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE 0x0000010c 1898 1899 #define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE 0x0000010d 1900 1901 #define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE 0x0000010e 1902 1903 #define REG_A6XX_RBBM_CLOCK_DELAY_UCHE 0x0000010f 1904 1905 #define REG_A6XX_RBBM_CLOCK_HYST_UCHE 0x00000110 1906 1907 #define REG_A6XX_RBBM_CLOCK_MODE_VFD 0x00000111 1908 1909 #define REG_A6XX_RBBM_CLOCK_DELAY_VFD 0x00000112 1910 1911 #define REG_A6XX_RBBM_CLOCK_HYST_VFD 0x00000113 1912 1913 #define REG_A6XX_RBBM_CLOCK_MODE_GPC 0x00000114 1914 1915 #define REG_A6XX_RBBM_CLOCK_DELAY_GPC 0x00000115 1916 1917 #define REG_A6XX_RBBM_CLOCK_HYST_GPC 0x00000116 1918 1919 #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2 0x00000117 1920 1921 #define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX 0x00000118 1922 1923 #define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX 0x00000119 1924 1925 #define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX 0x0000011a 1926 1927 #define REG_A6XX_RBBM_CLOCK_MODE_HLSQ 0x0000011b 1928 1929 #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ 0x0000011c 1930 1931 #define REG_A6XX_RBBM_CLOCK_HYST_HLSQ 0x0000011d 1932 1933 #define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE 0x00000120 1934 1935 #define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE 0x00000121 1936 1937 #define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122 1938 1939 #define REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL 0x000005ff 1940 1941 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A 0x00000600 1942 1943 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B 0x00000601 1944 1945 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C 0x00000602 1946 1947 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D 0x00000603 1948 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK 0x000000ff 1949 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT 0 1950 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val) 1951 { 1952 return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK; 1953 } 1954 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK 0x0000ff00 1955 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT 8 1956 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val) 1957 { 1958 return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK; 1959 } 1960 1961 #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT 0x00000604 1962 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f 1963 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0 1964 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) 1965 { 1966 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; 1967 } 1968 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000 1969 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12 1970 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) 1971 { 1972 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; 1973 } 1974 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000 1975 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28 1976 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) 1977 { 1978 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; 1979 } 1980 1981 #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM 0x00000605 1982 #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000 1983 #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24 1984 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) 1985 { 1986 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; 1987 } 1988 1989 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 0x00000608 1990 1991 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 0x00000609 1992 1993 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 0x0000060a 1994 1995 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 0x0000060b 1996 1997 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 0x0000060c 1998 1999 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 0x0000060d 2000 2001 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 0x0000060e 2002 2003 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 0x0000060f 2004 2005 #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000610 2006 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f 2007 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0 2008 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) 2009 { 2010 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; 2011 } 2012 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0 2013 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4 2014 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) 2015 { 2016 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; 2017 } 2018 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00 2019 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8 2020 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) 2021 { 2022 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; 2023 } 2024 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000 2025 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12 2026 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) 2027 { 2028 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; 2029 } 2030 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000 2031 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16 2032 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) 2033 { 2034 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; 2035 } 2036 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000 2037 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20 2038 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) 2039 { 2040 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; 2041 } 2042 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000 2043 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24 2044 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) 2045 { 2046 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; 2047 } 2048 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000 2049 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28 2050 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) 2051 { 2052 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; 2053 } 2054 2055 #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000611 2056 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f 2057 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0 2058 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) 2059 { 2060 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; 2061 } 2062 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0 2063 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4 2064 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) 2065 { 2066 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; 2067 } 2068 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00 2069 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8 2070 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) 2071 { 2072 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; 2073 } 2074 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000 2075 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12 2076 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) 2077 { 2078 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; 2079 } 2080 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000 2081 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16 2082 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) 2083 { 2084 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; 2085 } 2086 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000 2087 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20 2088 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) 2089 { 2090 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; 2091 } 2092 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000 2093 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24 2094 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) 2095 { 2096 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; 2097 } 2098 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000 2099 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28 2100 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) 2101 { 2102 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; 2103 } 2104 2105 #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000062f 2106 2107 #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630 2108 2109 static inline uint32_t REG_A6XX_VSC_PERFCTR_VSC_SEL(uint32_t i0) { return 0x00000cd8 + 0x1*i0; } 2110 2111 #define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800 2112 2113 #define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000 2114 2115 #define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00 2116 2117 #define REG_A6XX_UCHE_MODE_CNTL 0x00000e01 2118 2119 #define REG_A6XX_UCHE_WRITE_RANGE_MAX 0x00000e05 2120 2121 #define REG_A6XX_UCHE_WRITE_THRU_BASE 0x00000e07 2122 2123 #define REG_A6XX_UCHE_TRAP_BASE 0x00000e09 2124 2125 #define REG_A6XX_UCHE_GMEM_RANGE_MIN 0x00000e0b 2126 2127 #define REG_A6XX_UCHE_GMEM_RANGE_MAX 0x00000e0d 2128 2129 #define REG_A6XX_UCHE_CACHE_WAYS 0x00000e17 2130 2131 #define REG_A6XX_UCHE_FILTER_CNTL 0x00000e18 2132 2133 #define REG_A6XX_UCHE_CLIENT_PF 0x00000e19 2134 #define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK 0x000000ff 2135 #define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT 0 2136 static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val) 2137 { 2138 return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK; 2139 } 2140 2141 static inline uint32_t REG_A6XX_UCHE_PERFCTR_UCHE_SEL(uint32_t i0) { return 0x00000e1c + 0x1*i0; } 2142 2143 #define REG_A6XX_UCHE_GBIF_GX_CONFIG 0x00000e3a 2144 2145 #define REG_A6XX_UCHE_CMDQ_CONFIG 0x00000e3c 2146 2147 #define REG_A6XX_VBIF_VERSION 0x00003000 2148 2149 #define REG_A6XX_VBIF_CLKON 0x00003001 2150 #define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000002 2151 2152 #define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 2153 2154 #define REG_A6XX_VBIF_XIN_HALT_CTRL0 0x00003080 2155 2156 #define REG_A6XX_VBIF_XIN_HALT_CTRL1 0x00003081 2157 2158 #define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084 2159 2160 #define REG_A6XX_VBIF_TEST_BUS1_CTRL0 0x00003085 2161 2162 #define REG_A6XX_VBIF_TEST_BUS1_CTRL1 0x00003086 2163 #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK 0x0000000f 2164 #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT 0 2165 static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val) 2166 { 2167 return ((val) << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK; 2168 } 2169 2170 #define REG_A6XX_VBIF_TEST_BUS2_CTRL0 0x00003087 2171 2172 #define REG_A6XX_VBIF_TEST_BUS2_CTRL1 0x00003088 2173 #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK 0x000001ff 2174 #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT 0 2175 static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val) 2176 { 2177 return ((val) << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK; 2178 } 2179 2180 #define REG_A6XX_VBIF_TEST_BUS_OUT 0x0000308c 2181 2182 #define REG_A6XX_VBIF_PERF_CNT_SEL0 0x000030d0 2183 2184 #define REG_A6XX_VBIF_PERF_CNT_SEL1 0x000030d1 2185 2186 #define REG_A6XX_VBIF_PERF_CNT_SEL2 0x000030d2 2187 2188 #define REG_A6XX_VBIF_PERF_CNT_SEL3 0x000030d3 2189 2190 #define REG_A6XX_VBIF_PERF_CNT_LOW0 0x000030d8 2191 2192 #define REG_A6XX_VBIF_PERF_CNT_LOW1 0x000030d9 2193 2194 #define REG_A6XX_VBIF_PERF_CNT_LOW2 0x000030da 2195 2196 #define REG_A6XX_VBIF_PERF_CNT_LOW3 0x000030db 2197 2198 #define REG_A6XX_VBIF_PERF_CNT_HIGH0 0x000030e0 2199 2200 #define REG_A6XX_VBIF_PERF_CNT_HIGH1 0x000030e1 2201 2202 #define REG_A6XX_VBIF_PERF_CNT_HIGH2 0x000030e2 2203 2204 #define REG_A6XX_VBIF_PERF_CNT_HIGH3 0x000030e3 2205 2206 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN0 0x00003100 2207 2208 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN1 0x00003101 2209 2210 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN2 0x00003102 2211 2212 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110 2213 2214 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111 2215 2216 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112 2217 2218 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118 2219 2220 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119 2221 2222 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a 2223 2224 #define REG_A6XX_GBIF_SCACHE_CNTL0 0x00003c01 2225 2226 #define REG_A6XX_GBIF_SCACHE_CNTL1 0x00003c02 2227 2228 #define REG_A6XX_GBIF_QSB_SIDE0 0x00003c03 2229 2230 #define REG_A6XX_GBIF_QSB_SIDE1 0x00003c04 2231 2232 #define REG_A6XX_GBIF_QSB_SIDE2 0x00003c05 2233 2234 #define REG_A6XX_GBIF_QSB_SIDE3 0x00003c06 2235 2236 #define REG_A6XX_GBIF_HALT 0x00003c45 2237 2238 #define REG_A6XX_GBIF_HALT_ACK 0x00003c46 2239 2240 #define REG_A6XX_GBIF_PERF_PWR_CNT_EN 0x00003cc0 2241 2242 #define REG_A6XX_GBIF_PERF_PWR_CNT_CLR 0x00003cc1 2243 2244 #define REG_A6XX_GBIF_PERF_CNT_SEL 0x00003cc2 2245 2246 #define REG_A6XX_GBIF_PERF_PWR_CNT_SEL 0x00003cc3 2247 2248 #define REG_A6XX_GBIF_PERF_CNT_LOW0 0x00003cc4 2249 2250 #define REG_A6XX_GBIF_PERF_CNT_LOW1 0x00003cc5 2251 2252 #define REG_A6XX_GBIF_PERF_CNT_LOW2 0x00003cc6 2253 2254 #define REG_A6XX_GBIF_PERF_CNT_LOW3 0x00003cc7 2255 2256 #define REG_A6XX_GBIF_PERF_CNT_HIGH0 0x00003cc8 2257 2258 #define REG_A6XX_GBIF_PERF_CNT_HIGH1 0x00003cc9 2259 2260 #define REG_A6XX_GBIF_PERF_CNT_HIGH2 0x00003cca 2261 2262 #define REG_A6XX_GBIF_PERF_CNT_HIGH3 0x00003ccb 2263 2264 #define REG_A6XX_GBIF_PWR_CNT_LOW0 0x00003ccc 2265 2266 #define REG_A6XX_GBIF_PWR_CNT_LOW1 0x00003ccd 2267 2268 #define REG_A6XX_GBIF_PWR_CNT_LOW2 0x00003cce 2269 2270 #define REG_A6XX_GBIF_PWR_CNT_HIGH0 0x00003ccf 2271 2272 #define REG_A6XX_GBIF_PWR_CNT_HIGH1 0x00003cd0 2273 2274 #define REG_A6XX_GBIF_PWR_CNT_HIGH2 0x00003cd1 2275 2276 #define REG_A6XX_VSC_DBG_ECO_CNTL 0x00000c00 2277 2278 #define REG_A6XX_VSC_BIN_SIZE 0x00000c02 2279 #define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff 2280 #define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 2281 static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 2282 { 2283 return ((val >> 5) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK; 2284 } 2285 #define A6XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001ff00 2286 #define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT 8 2287 static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 2288 { 2289 return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK; 2290 } 2291 2292 #define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS 0x00000c03 2293 2294 #define REG_A6XX_VSC_BIN_COUNT 0x00000c06 2295 #define A6XX_VSC_BIN_COUNT_NX__MASK 0x000007fe 2296 #define A6XX_VSC_BIN_COUNT_NX__SHIFT 1 2297 static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val) 2298 { 2299 return ((val) << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK; 2300 } 2301 #define A6XX_VSC_BIN_COUNT_NY__MASK 0x001ff800 2302 #define A6XX_VSC_BIN_COUNT_NY__SHIFT 11 2303 static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val) 2304 { 2305 return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK; 2306 } 2307 2308 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 2309 2310 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 2311 #define A6XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff 2312 #define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0 2313 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) 2314 { 2315 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK; 2316 } 2317 #define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00 2318 #define A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10 2319 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) 2320 { 2321 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK; 2322 } 2323 #define A6XX_VSC_PIPE_CONFIG_REG_W__MASK 0x03f00000 2324 #define A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20 2325 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) 2326 { 2327 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK; 2328 } 2329 #define A6XX_VSC_PIPE_CONFIG_REG_H__MASK 0xfc000000 2330 #define A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT 26 2331 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) 2332 { 2333 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK; 2334 } 2335 2336 #define REG_A6XX_VSC_PRIM_STRM_ADDRESS 0x00000c30 2337 2338 #define REG_A6XX_VSC_PRIM_STRM_PITCH 0x00000c32 2339 2340 #define REG_A6XX_VSC_PRIM_STRM_LIMIT 0x00000c33 2341 2342 #define REG_A6XX_VSC_DRAW_STRM_ADDRESS 0x00000c34 2343 2344 #define REG_A6XX_VSC_DRAW_STRM_PITCH 0x00000c36 2345 2346 #define REG_A6XX_VSC_DRAW_STRM_LIMIT 0x00000c37 2347 2348 static inline uint32_t REG_A6XX_VSC_STATE(uint32_t i0) { return 0x00000c38 + 0x1*i0; } 2349 2350 static inline uint32_t REG_A6XX_VSC_STATE_REG(uint32_t i0) { return 0x00000c38 + 0x1*i0; } 2351 2352 static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE(uint32_t i0) { return 0x00000c58 + 0x1*i0; } 2353 2354 static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0) { return 0x00000c58 + 0x1*i0; } 2355 2356 static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; } 2357 2358 static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; } 2359 2360 #define REG_A6XX_UCHE_UNKNOWN_0E12 0x00000e12 2361 2362 #define REG_A6XX_GRAS_CL_CNTL 0x00008000 2363 #define A6XX_GRAS_CL_CNTL_CLIP_DISABLE 0x00000001 2364 #define A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE 0x00000002 2365 #define A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE 0x00000004 2366 #define A6XX_GRAS_CL_CNTL_Z_CLAMP_ENABLE 0x00000020 2367 #define A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040 2368 #define A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE 0x00000080 2369 #define A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE 0x00000100 2370 #define A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE 0x00000200 2371 2372 #define REG_A6XX_GRAS_VS_CL_CNTL 0x00008001 2373 #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK 0x000000ff 2374 #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT 0 2375 static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val) 2376 { 2377 return ((val) << A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK; 2378 } 2379 #define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK 0x0000ff00 2380 #define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT 8 2381 static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val) 2382 { 2383 return ((val) << A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK; 2384 } 2385 2386 #define REG_A6XX_GRAS_DS_CL_CNTL 0x00008002 2387 #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK 0x000000ff 2388 #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT 0 2389 static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(uint32_t val) 2390 { 2391 return ((val) << A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK; 2392 } 2393 #define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK 0x0000ff00 2394 #define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT 8 2395 static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CULL_MASK(uint32_t val) 2396 { 2397 return ((val) << A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK; 2398 } 2399 2400 #define REG_A6XX_GRAS_GS_CL_CNTL 0x00008003 2401 #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK 0x000000ff 2402 #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT 0 2403 static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(uint32_t val) 2404 { 2405 return ((val) << A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK; 2406 } 2407 #define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK 0x0000ff00 2408 #define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT 8 2409 static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CULL_MASK(uint32_t val) 2410 { 2411 return ((val) << A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK; 2412 } 2413 2414 #define REG_A6XX_GRAS_MAX_LAYER_INDEX 0x00008004 2415 2416 #define REG_A6XX_GRAS_CNTL 0x00008005 2417 #define A6XX_GRAS_CNTL_IJ_PERSP_PIXEL 0x00000001 2418 #define A6XX_GRAS_CNTL_IJ_PERSP_CENTROID 0x00000002 2419 #define A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE 0x00000004 2420 #define A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL 0x00000008 2421 #define A6XX_GRAS_CNTL_IJ_LINEAR_CENTROID 0x00000010 2422 #define A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE 0x00000020 2423 #define A6XX_GRAS_CNTL_COORD_MASK__MASK 0x000003c0 2424 #define A6XX_GRAS_CNTL_COORD_MASK__SHIFT 6 2425 static inline uint32_t A6XX_GRAS_CNTL_COORD_MASK(uint32_t val) 2426 { 2427 return ((val) << A6XX_GRAS_CNTL_COORD_MASK__SHIFT) & A6XX_GRAS_CNTL_COORD_MASK__MASK; 2428 } 2429 2430 #define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x00008006 2431 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000001ff 2432 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0 2433 static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val) 2434 { 2435 return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK; 2436 } 2437 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x0007fc00 2438 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10 2439 static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) 2440 { 2441 return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK; 2442 } 2443 2444 static inline uint32_t REG_A6XX_GRAS_CL_VPORT(uint32_t i0) { return 0x00008010 + 0x6*i0; } 2445 2446 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0) { return 0x00008010 + 0x6*i0; } 2447 #define A6XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff 2448 #define A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0 2449 static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET(float val) 2450 { 2451 return ((fui(val)) << A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET__MASK; 2452 } 2453 2454 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XSCALE(uint32_t i0) { return 0x00008011 + 0x6*i0; } 2455 #define A6XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff 2456 #define A6XX_GRAS_CL_VPORT_XSCALE__SHIFT 0 2457 static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE(float val) 2458 { 2459 return ((fui(val)) << A6XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE__MASK; 2460 } 2461 2462 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YOFFSET(uint32_t i0) { return 0x00008012 + 0x6*i0; } 2463 #define A6XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff 2464 #define A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0 2465 static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET(float val) 2466 { 2467 return ((fui(val)) << A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET__MASK; 2468 } 2469 2470 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YSCALE(uint32_t i0) { return 0x00008013 + 0x6*i0; } 2471 #define A6XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff 2472 #define A6XX_GRAS_CL_VPORT_YSCALE__SHIFT 0 2473 static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE(float val) 2474 { 2475 return ((fui(val)) << A6XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE__MASK; 2476 } 2477 2478 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZOFFSET(uint32_t i0) { return 0x00008014 + 0x6*i0; } 2479 #define A6XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff 2480 #define A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0 2481 static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET(float val) 2482 { 2483 return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET__MASK; 2484 } 2485 2486 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZSCALE(uint32_t i0) { return 0x00008015 + 0x6*i0; } 2487 #define A6XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff 2488 #define A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0 2489 static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE(float val) 2490 { 2491 return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE__MASK; 2492 } 2493 2494 static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP(uint32_t i0) { return 0x00008070 + 0x2*i0; } 2495 2496 static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0) { return 0x00008070 + 0x2*i0; } 2497 #define A6XX_GRAS_CL_Z_CLAMP_MIN__MASK 0xffffffff 2498 #define A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT 0 2499 static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MIN(float val) 2500 { 2501 return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MIN__MASK; 2502 } 2503 2504 static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MAX(uint32_t i0) { return 0x00008071 + 0x2*i0; } 2505 #define A6XX_GRAS_CL_Z_CLAMP_MAX__MASK 0xffffffff 2506 #define A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT 0 2507 static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MAX(float val) 2508 { 2509 return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MAX__MASK; 2510 } 2511 2512 #define REG_A6XX_GRAS_SU_CNTL 0x00008090 2513 #define A6XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001 2514 #define A6XX_GRAS_SU_CNTL_CULL_BACK 0x00000002 2515 #define A6XX_GRAS_SU_CNTL_FRONT_CW 0x00000004 2516 #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8 2517 #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3 2518 static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) 2519 { 2520 return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK; 2521 } 2522 #define A6XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800 2523 #define A6XX_GRAS_SU_CNTL_UNK12__MASK 0x00001000 2524 #define A6XX_GRAS_SU_CNTL_UNK12__SHIFT 12 2525 static inline uint32_t A6XX_GRAS_SU_CNTL_UNK12(uint32_t val) 2526 { 2527 return ((val) << A6XX_GRAS_SU_CNTL_UNK12__SHIFT) & A6XX_GRAS_SU_CNTL_UNK12__MASK; 2528 } 2529 #define A6XX_GRAS_SU_CNTL_LINE_MODE__MASK 0x00002000 2530 #define A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT 13 2531 static inline uint32_t A6XX_GRAS_SU_CNTL_LINE_MODE(enum a5xx_line_mode val) 2532 { 2533 return ((val) << A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT) & A6XX_GRAS_SU_CNTL_LINE_MODE__MASK; 2534 } 2535 #define A6XX_GRAS_SU_CNTL_UNK15__MASK 0x00018000 2536 #define A6XX_GRAS_SU_CNTL_UNK15__SHIFT 15 2537 static inline uint32_t A6XX_GRAS_SU_CNTL_UNK15(uint32_t val) 2538 { 2539 return ((val) << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK; 2540 } 2541 #define A6XX_GRAS_SU_CNTL_UNK17 0x00020000 2542 #define A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE 0x00040000 2543 #define A6XX_GRAS_SU_CNTL_UNK19__MASK 0x00780000 2544 #define A6XX_GRAS_SU_CNTL_UNK19__SHIFT 19 2545 static inline uint32_t A6XX_GRAS_SU_CNTL_UNK19(uint32_t val) 2546 { 2547 return ((val) << A6XX_GRAS_SU_CNTL_UNK19__SHIFT) & A6XX_GRAS_SU_CNTL_UNK19__MASK; 2548 } 2549 2550 #define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091 2551 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 2552 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 2553 static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val) 2554 { 2555 return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 2556 } 2557 #define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 2558 #define A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 2559 static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MAX(float val) 2560 { 2561 return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 2562 } 2563 2564 #define REG_A6XX_GRAS_SU_POINT_SIZE 0x00008092 2565 #define A6XX_GRAS_SU_POINT_SIZE__MASK 0x0000ffff 2566 #define A6XX_GRAS_SU_POINT_SIZE__SHIFT 0 2567 static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val) 2568 { 2569 return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK; 2570 } 2571 2572 #define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL 0x00008094 2573 #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003 2574 #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0 2575 static inline uint32_t A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val) 2576 { 2577 return ((val) << A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK; 2578 } 2579 2580 #define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE 0x00008095 2581 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff 2582 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 2583 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val) 2584 { 2585 return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; 2586 } 2587 2588 #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00008096 2589 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 2590 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 2591 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 2592 { 2593 return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 2594 } 2595 2596 #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x00008097 2597 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff 2598 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0 2599 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val) 2600 { 2601 return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK; 2602 } 2603 2604 #define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO 0x00008098 2605 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 2606 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 2607 static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) 2608 { 2609 return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; 2610 } 2611 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000008 2612 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT 3 2613 static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3(uint32_t val) 2614 { 2615 return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK; 2616 } 2617 2618 #define REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x00008099 2619 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN 0x00000001 2620 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK 0x00000006 2621 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT 1 2622 static inline uint32_t A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT(uint32_t val) 2623 { 2624 return ((val) << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK; 2625 } 2626 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_INNERCONSERVATIVERASEN 0x00000008 2627 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK 0x00000030 2628 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT 4 2629 static inline uint32_t A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4(uint32_t val) 2630 { 2631 return ((val) << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK; 2632 } 2633 2634 #define REG_A6XX_GRAS_SU_PATH_RENDERING_CNTL 0x0000809a 2635 #define A6XX_GRAS_SU_PATH_RENDERING_CNTL_UNK0 0x00000001 2636 #define A6XX_GRAS_SU_PATH_RENDERING_CNTL_LINELENGTHEN 0x00000002 2637 2638 #define REG_A6XX_GRAS_VS_LAYER_CNTL 0x0000809b 2639 #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER 0x00000001 2640 #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW 0x00000002 2641 2642 #define REG_A6XX_GRAS_GS_LAYER_CNTL 0x0000809c 2643 #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER 0x00000001 2644 #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW 0x00000002 2645 2646 #define REG_A6XX_GRAS_DS_LAYER_CNTL 0x0000809d 2647 #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER 0x00000001 2648 #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW 0x00000002 2649 2650 #define REG_A6XX_GRAS_SC_CNTL 0x000080a0 2651 #define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK 0x00000007 2652 #define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT 0 2653 static inline uint32_t A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(uint32_t val) 2654 { 2655 return ((val) << A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK; 2656 } 2657 #define A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK 0x00000018 2658 #define A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT 3 2659 static inline uint32_t A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE(enum a6xx_single_prim_mode val) 2660 { 2661 return ((val) << A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK; 2662 } 2663 #define A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK 0x00000020 2664 #define A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT 5 2665 static inline uint32_t A6XX_GRAS_SC_CNTL_RASTER_MODE(enum a6xx_raster_mode val) 2666 { 2667 return ((val) << A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK; 2668 } 2669 #define A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK 0x000000c0 2670 #define A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT 6 2671 static inline uint32_t A6XX_GRAS_SC_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val) 2672 { 2673 return ((val) << A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK; 2674 } 2675 #define A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK 0x00000100 2676 #define A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT 8 2677 static inline uint32_t A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION(enum a6xx_sequenced_thread_dist val) 2678 { 2679 return ((val) << A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT) & A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK; 2680 } 2681 #define A6XX_GRAS_SC_CNTL_UNK9 0x00000200 2682 #define A6XX_GRAS_SC_CNTL_ROTATION__MASK 0x00000c00 2683 #define A6XX_GRAS_SC_CNTL_ROTATION__SHIFT 10 2684 static inline uint32_t A6XX_GRAS_SC_CNTL_ROTATION(uint32_t val) 2685 { 2686 return ((val) << A6XX_GRAS_SC_CNTL_ROTATION__SHIFT) & A6XX_GRAS_SC_CNTL_ROTATION__MASK; 2687 } 2688 #define A6XX_GRAS_SC_CNTL_EARLYVIZOUTEN 0x00001000 2689 2690 #define REG_A6XX_GRAS_BIN_CONTROL 0x000080a1 2691 #define A6XX_GRAS_BIN_CONTROL_BINW__MASK 0x0000003f 2692 #define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT 0 2693 static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val) 2694 { 2695 return ((val >> 5) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK; 2696 } 2697 #define A6XX_GRAS_BIN_CONTROL_BINH__MASK 0x00007f00 2698 #define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT 8 2699 static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val) 2700 { 2701 return ((val >> 4) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK; 2702 } 2703 #define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000 2704 #define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT 18 2705 static inline uint32_t A6XX_GRAS_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val) 2706 { 2707 return ((val) << A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK; 2708 } 2709 #define A6XX_GRAS_BIN_CONTROL_FORCE_LRZ_WRITE_DIS 0x00200000 2710 #define A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK 0x00c00000 2711 #define A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT 22 2712 static inline uint32_t A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val) 2713 { 2714 return ((val) << A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK; 2715 } 2716 #define A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK 0x07000000 2717 #define A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT 24 2718 static inline uint32_t A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val) 2719 { 2720 return ((val) << A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK; 2721 } 2722 #define A6XX_GRAS_BIN_CONTROL_UNK27__MASK 0x08000000 2723 #define A6XX_GRAS_BIN_CONTROL_UNK27__SHIFT 27 2724 static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK27(uint32_t val) 2725 { 2726 return ((val) << A6XX_GRAS_BIN_CONTROL_UNK27__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK27__MASK; 2727 } 2728 2729 #define REG_A6XX_GRAS_RAS_MSAA_CNTL 0x000080a2 2730 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 2731 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 2732 static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 2733 { 2734 return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK; 2735 } 2736 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK 0x00000004 2737 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT 2 2738 static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK2(uint32_t val) 2739 { 2740 return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK; 2741 } 2742 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK 0x00000008 2743 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT 3 2744 static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK3(uint32_t val) 2745 { 2746 return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK; 2747 } 2748 2749 #define REG_A6XX_GRAS_DEST_MSAA_CNTL 0x000080a3 2750 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 2751 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 2752 static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 2753 { 2754 return ((val) << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK; 2755 } 2756 #define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 2757 2758 #define REG_A6XX_GRAS_SAMPLE_CONFIG 0x000080a4 2759 #define A6XX_GRAS_SAMPLE_CONFIG_UNK0 0x00000001 2760 #define A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002 2761 2762 #define REG_A6XX_GRAS_SAMPLE_LOCATION_0 0x000080a5 2763 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f 2764 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 2765 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) 2766 { 2767 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; 2768 } 2769 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 2770 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 2771 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) 2772 { 2773 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; 2774 } 2775 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 2776 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 2777 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) 2778 { 2779 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; 2780 } 2781 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 2782 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 2783 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) 2784 { 2785 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; 2786 } 2787 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 2788 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 2789 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) 2790 { 2791 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; 2792 } 2793 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 2794 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 2795 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) 2796 { 2797 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; 2798 } 2799 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 2800 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 2801 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) 2802 { 2803 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; 2804 } 2805 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 2806 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 2807 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) 2808 { 2809 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; 2810 } 2811 2812 #define REG_A6XX_GRAS_SAMPLE_LOCATION_1 0x000080a6 2813 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f 2814 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 2815 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) 2816 { 2817 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; 2818 } 2819 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 2820 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 2821 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) 2822 { 2823 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; 2824 } 2825 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 2826 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 2827 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) 2828 { 2829 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; 2830 } 2831 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 2832 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 2833 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) 2834 { 2835 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; 2836 } 2837 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 2838 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 2839 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) 2840 { 2841 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; 2842 } 2843 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 2844 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 2845 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) 2846 { 2847 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; 2848 } 2849 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 2850 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 2851 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) 2852 { 2853 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; 2854 } 2855 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 2856 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 2857 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) 2858 { 2859 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; 2860 } 2861 2862 #define REG_A6XX_GRAS_UNKNOWN_80AF 0x000080af 2863 2864 static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR(uint32_t i0) { return 0x000080b0 + 0x2*i0; } 2865 2866 static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0) { return 0x000080b0 + 0x2*i0; } 2867 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x0000ffff 2868 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 2869 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 2870 { 2871 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; 2872 } 2873 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0xffff0000 2874 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 2875 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 2876 { 2877 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; 2878 } 2879 2880 static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR(uint32_t i0) { return 0x000080b1 + 0x2*i0; } 2881 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x0000ffff 2882 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 2883 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 2884 { 2885 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; 2886 } 2887 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0xffff0000 2888 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 2889 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 2890 { 2891 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; 2892 } 2893 2894 static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(uint32_t i0) { return 0x000080d0 + 0x2*i0; } 2895 2896 static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0) { return 0x000080d0 + 0x2*i0; } 2897 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK 0x0000ffff 2898 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT 0 2899 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(uint32_t val) 2900 { 2901 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK; 2902 } 2903 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK 0xffff0000 2904 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT 16 2905 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(uint32_t val) 2906 { 2907 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK; 2908 } 2909 2910 static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(uint32_t i0) { return 0x000080d1 + 0x2*i0; } 2911 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK 0x0000ffff 2912 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT 0 2913 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X(uint32_t val) 2914 { 2915 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK; 2916 } 2917 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK 0xffff0000 2918 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT 16 2919 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y(uint32_t val) 2920 { 2921 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK; 2922 } 2923 2924 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL 0x000080f0 2925 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00003fff 2926 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 2927 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 2928 { 2929 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 2930 } 2931 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x3fff0000 2932 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 2933 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 2934 { 2935 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 2936 } 2937 2938 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR 0x000080f1 2939 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00003fff 2940 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 2941 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 2942 { 2943 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 2944 } 2945 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x3fff0000 2946 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 2947 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 2948 { 2949 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 2950 } 2951 2952 #define REG_A6XX_GRAS_LRZ_CNTL 0x00008100 2953 #define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001 2954 #define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002 2955 #define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004 2956 #define A6XX_GRAS_LRZ_CNTL_FC_ENABLE 0x00000008 2957 #define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE 0x00000010 2958 #define A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE 0x00000020 2959 #define A6XX_GRAS_LRZ_CNTL_DIR__MASK 0x000000c0 2960 #define A6XX_GRAS_LRZ_CNTL_DIR__SHIFT 6 2961 static inline uint32_t A6XX_GRAS_LRZ_CNTL_DIR(enum a6xx_lrz_dir_status val) 2962 { 2963 return ((val) << A6XX_GRAS_LRZ_CNTL_DIR__SHIFT) & A6XX_GRAS_LRZ_CNTL_DIR__MASK; 2964 } 2965 #define A6XX_GRAS_LRZ_CNTL_DIR_WRITE 0x00000100 2966 #define A6XX_GRAS_LRZ_CNTL_DISABLE_ON_WRONG_DIR 0x00000200 2967 2968 #define REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL 0x00008101 2969 #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_SAMPLEID 0x00000001 2970 #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK 0x00000006 2971 #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT 1 2972 static inline uint32_t A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val) 2973 { 2974 return ((val) << A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK; 2975 } 2976 2977 #define REG_A6XX_GRAS_LRZ_MRT_BUF_INFO_0 0x00008102 2978 #define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK 0x000000ff 2979 #define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT 0 2980 static inline uint32_t A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT(enum a6xx_format val) 2981 { 2982 return ((val) << A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT) & A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK; 2983 } 2984 2985 #define REG_A6XX_GRAS_LRZ_BUFFER_BASE 0x00008103 2986 #define A6XX_GRAS_LRZ_BUFFER_BASE__MASK 0xffffffff 2987 #define A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT 0 2988 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_BASE(uint32_t val) 2989 { 2990 return ((val) << A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_BUFFER_BASE__MASK; 2991 } 2992 2993 #define REG_A6XX_GRAS_LRZ_BUFFER_PITCH 0x00008105 2994 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK 0x000000ff 2995 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT 0 2996 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val) 2997 { 2998 return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK; 2999 } 3000 #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffffc00 3001 #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT 10 3002 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 3003 { 3004 return ((val >> 4) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK; 3005 } 3006 3007 #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE 0x00008106 3008 #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK 0xffffffff 3009 #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT 0 3010 static inline uint32_t A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(uint32_t val) 3011 { 3012 return ((val) << A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK; 3013 } 3014 3015 #define REG_A6XX_GRAS_SAMPLE_CNTL 0x00008109 3016 #define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001 3017 3018 #define REG_A6XX_GRAS_LRZ_DEPTH_VIEW 0x0000810a 3019 #define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__MASK 0x000007ff 3020 #define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__SHIFT 0 3021 static inline uint32_t A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER(uint32_t val) 3022 { 3023 return ((val) << A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__MASK; 3024 } 3025 #define A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__MASK 0x07ff0000 3026 #define A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__SHIFT 16 3027 static inline uint32_t A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT(uint32_t val) 3028 { 3029 return ((val) << A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__MASK; 3030 } 3031 #define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__MASK 0xf0000000 3032 #define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__SHIFT 28 3033 static inline uint32_t A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL(uint32_t val) 3034 { 3035 return ((val) << A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__MASK; 3036 } 3037 3038 #define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110 3039 3040 #define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400 3041 #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK 0x00000007 3042 #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT 0 3043 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val) 3044 { 3045 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK; 3046 } 3047 #define A6XX_GRAS_2D_BLIT_CNTL_OVERWRITEEN 0x00000008 3048 #define A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK 0x00000070 3049 #define A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT 4 3050 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK4(uint32_t val) 3051 { 3052 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK; 3053 } 3054 #define A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR 0x00000080 3055 #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00 3056 #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8 3057 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val) 3058 { 3059 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK; 3060 } 3061 #define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR 0x00010000 3062 #define A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK 0x00060000 3063 #define A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT 17 3064 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK17(uint32_t val) 3065 { 3066 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK; 3067 } 3068 #define A6XX_GRAS_2D_BLIT_CNTL_D24S8 0x00080000 3069 #define A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK 0x00f00000 3070 #define A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT 20 3071 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_MASK(uint32_t val) 3072 { 3073 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK; 3074 } 3075 #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK 0x1f000000 3076 #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT 24 3077 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val) 3078 { 3079 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK; 3080 } 3081 #define A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK 0x20000000 3082 #define A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT 29 3083 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val) 3084 { 3085 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK; 3086 } 3087 3088 #define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401 3089 3090 #define REG_A6XX_GRAS_2D_SRC_BR_X 0x00008402 3091 3092 #define REG_A6XX_GRAS_2D_SRC_TL_Y 0x00008403 3093 3094 #define REG_A6XX_GRAS_2D_SRC_BR_Y 0x00008404 3095 3096 #define REG_A6XX_GRAS_2D_DST_TL 0x00008405 3097 #define A6XX_GRAS_2D_DST_TL_X__MASK 0x00003fff 3098 #define A6XX_GRAS_2D_DST_TL_X__SHIFT 0 3099 static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val) 3100 { 3101 return ((val) << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK; 3102 } 3103 #define A6XX_GRAS_2D_DST_TL_Y__MASK 0x3fff0000 3104 #define A6XX_GRAS_2D_DST_TL_Y__SHIFT 16 3105 static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val) 3106 { 3107 return ((val) << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK; 3108 } 3109 3110 #define REG_A6XX_GRAS_2D_DST_BR 0x00008406 3111 #define A6XX_GRAS_2D_DST_BR_X__MASK 0x00003fff 3112 #define A6XX_GRAS_2D_DST_BR_X__SHIFT 0 3113 static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val) 3114 { 3115 return ((val) << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK; 3116 } 3117 #define A6XX_GRAS_2D_DST_BR_Y__MASK 0x3fff0000 3118 #define A6XX_GRAS_2D_DST_BR_Y__SHIFT 16 3119 static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val) 3120 { 3121 return ((val) << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK; 3122 } 3123 3124 #define REG_A6XX_GRAS_2D_UNKNOWN_8407 0x00008407 3125 3126 #define REG_A6XX_GRAS_2D_UNKNOWN_8408 0x00008408 3127 3128 #define REG_A6XX_GRAS_2D_UNKNOWN_8409 0x00008409 3129 3130 #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_1 0x0000840a 3131 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK 0x00003fff 3132 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT 0 3133 static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_X(uint32_t val) 3134 { 3135 return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK; 3136 } 3137 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK 0x3fff0000 3138 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT 16 3139 static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(uint32_t val) 3140 { 3141 return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK; 3142 } 3143 3144 #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_2 0x0000840b 3145 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK 0x00003fff 3146 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT 0 3147 static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_X(uint32_t val) 3148 { 3149 return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK; 3150 } 3151 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK 0x3fff0000 3152 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT 16 3153 static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val) 3154 { 3155 return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK; 3156 } 3157 3158 #define REG_A6XX_GRAS_DBG_ECO_CNTL 0x00008600 3159 #define A6XX_GRAS_DBG_ECO_CNTL_UNK7 0x00000080 3160 #define A6XX_GRAS_DBG_ECO_CNTL_LRZCACHELOCKDIS 0x00000800 3161 3162 #define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601 3163 3164 #define REG_A7XX_GRAS_NC_MODE_CNTL 0x00008602 3165 3166 static inline uint32_t REG_A6XX_GRAS_PERFCTR_TSE_SEL(uint32_t i0) { return 0x00008610 + 0x1*i0; } 3167 3168 static inline uint32_t REG_A6XX_GRAS_PERFCTR_RAS_SEL(uint32_t i0) { return 0x00008614 + 0x1*i0; } 3169 3170 static inline uint32_t REG_A6XX_GRAS_PERFCTR_LRZ_SEL(uint32_t i0) { return 0x00008618 + 0x1*i0; } 3171 3172 #define REG_A6XX_RB_BIN_CONTROL 0x00008800 3173 #define A6XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f 3174 #define A6XX_RB_BIN_CONTROL_BINW__SHIFT 0 3175 static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val) 3176 { 3177 return ((val >> 5) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK; 3178 } 3179 #define A6XX_RB_BIN_CONTROL_BINH__MASK 0x00007f00 3180 #define A6XX_RB_BIN_CONTROL_BINH__SHIFT 8 3181 static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val) 3182 { 3183 return ((val >> 4) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK; 3184 } 3185 #define A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000 3186 #define A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT 18 3187 static inline uint32_t A6XX_RB_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val) 3188 { 3189 return ((val) << A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK; 3190 } 3191 #define A6XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS 0x00200000 3192 #define A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK 0x00c00000 3193 #define A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT 22 3194 static inline uint32_t A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val) 3195 { 3196 return ((val) << A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK; 3197 } 3198 #define A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK 0x07000000 3199 #define A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT 24 3200 static inline uint32_t A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val) 3201 { 3202 return ((val) << A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK; 3203 } 3204 3205 #define REG_A6XX_RB_RENDER_CNTL 0x00008801 3206 #define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK 0x00000038 3207 #define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT 3 3208 static inline uint32_t A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE(uint32_t val) 3209 { 3210 return ((val) << A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK; 3211 } 3212 #define A6XX_RB_RENDER_CNTL_EARLYVIZOUTEN 0x00000040 3213 #define A6XX_RB_RENDER_CNTL_BINNING 0x00000080 3214 #define A6XX_RB_RENDER_CNTL_UNK8__MASK 0x00000700 3215 #define A6XX_RB_RENDER_CNTL_UNK8__SHIFT 8 3216 static inline uint32_t A6XX_RB_RENDER_CNTL_UNK8(uint32_t val) 3217 { 3218 return ((val) << A6XX_RB_RENDER_CNTL_UNK8__SHIFT) & A6XX_RB_RENDER_CNTL_UNK8__MASK; 3219 } 3220 #define A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK 0x00000100 3221 #define A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT 8 3222 static inline uint32_t A6XX_RB_RENDER_CNTL_RASTER_MODE(enum a6xx_raster_mode val) 3223 { 3224 return ((val) << A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK; 3225 } 3226 #define A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK 0x00000600 3227 #define A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT 9 3228 static inline uint32_t A6XX_RB_RENDER_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val) 3229 { 3230 return ((val) << A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK; 3231 } 3232 #define A6XX_RB_RENDER_CNTL_CONSERVATIVERASEN 0x00000800 3233 #define A6XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN 0x00001000 3234 #define A6XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000 3235 #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000 3236 #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16 3237 static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val) 3238 { 3239 return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK; 3240 } 3241 3242 #define REG_A6XX_RB_RAS_MSAA_CNTL 0x00008802 3243 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 3244 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 3245 static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 3246 { 3247 return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK; 3248 } 3249 #define A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK 0x00000004 3250 #define A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT 2 3251 static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK2(uint32_t val) 3252 { 3253 return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK; 3254 } 3255 #define A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK 0x00000008 3256 #define A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT 3 3257 static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK3(uint32_t val) 3258 { 3259 return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK; 3260 } 3261 3262 #define REG_A6XX_RB_DEST_MSAA_CNTL 0x00008803 3263 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 3264 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 3265 static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 3266 { 3267 return ((val) << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK; 3268 } 3269 #define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 3270 3271 #define REG_A6XX_RB_SAMPLE_CONFIG 0x00008804 3272 #define A6XX_RB_SAMPLE_CONFIG_UNK0 0x00000001 3273 #define A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002 3274 3275 #define REG_A6XX_RB_SAMPLE_LOCATION_0 0x00008805 3276 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f 3277 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 3278 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) 3279 { 3280 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; 3281 } 3282 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 3283 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 3284 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) 3285 { 3286 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; 3287 } 3288 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 3289 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 3290 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) 3291 { 3292 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; 3293 } 3294 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 3295 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 3296 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) 3297 { 3298 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; 3299 } 3300 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 3301 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 3302 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) 3303 { 3304 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; 3305 } 3306 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 3307 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 3308 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) 3309 { 3310 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; 3311 } 3312 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 3313 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 3314 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) 3315 { 3316 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; 3317 } 3318 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 3319 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 3320 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) 3321 { 3322 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; 3323 } 3324 3325 #define REG_A6XX_RB_SAMPLE_LOCATION_1 0x00008806 3326 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f 3327 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 3328 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) 3329 { 3330 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; 3331 } 3332 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 3333 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 3334 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) 3335 { 3336 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; 3337 } 3338 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 3339 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 3340 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) 3341 { 3342 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; 3343 } 3344 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 3345 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 3346 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) 3347 { 3348 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; 3349 } 3350 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 3351 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 3352 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) 3353 { 3354 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; 3355 } 3356 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 3357 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 3358 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) 3359 { 3360 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; 3361 } 3362 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 3363 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 3364 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) 3365 { 3366 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; 3367 } 3368 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 3369 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 3370 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) 3371 { 3372 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; 3373 } 3374 3375 #define REG_A6XX_RB_RENDER_CONTROL0 0x00008809 3376 #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL 0x00000001 3377 #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID 0x00000002 3378 #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE 0x00000004 3379 #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL 0x00000008 3380 #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID 0x00000010 3381 #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE 0x00000020 3382 #define A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK 0x000003c0 3383 #define A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT 6 3384 static inline uint32_t A6XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val) 3385 { 3386 return ((val) << A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK; 3387 } 3388 #define A6XX_RB_RENDER_CONTROL0_UNK10 0x00000400 3389 3390 #define REG_A6XX_RB_RENDER_CONTROL1 0x0000880a 3391 #define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001 3392 #define A6XX_RB_RENDER_CONTROL1_POSTDEPTHCOVERAGE 0x00000002 3393 #define A6XX_RB_RENDER_CONTROL1_FACENESS 0x00000004 3394 #define A6XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000008 3395 #define A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK 0x00000030 3396 #define A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT 4 3397 static inline uint32_t A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val) 3398 { 3399 return ((val) << A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK; 3400 } 3401 #define A6XX_RB_RENDER_CONTROL1_CENTERRHW 0x00000040 3402 #define A6XX_RB_RENDER_CONTROL1_LINELENGTHEN 0x00000080 3403 #define A6XX_RB_RENDER_CONTROL1_FOVEATION 0x00000100 3404 3405 #define REG_A6XX_RB_FS_OUTPUT_CNTL0 0x0000880b 3406 #define A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001 3407 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z 0x00000002 3408 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK 0x00000004 3409 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF 0x00000008 3410 3411 #define REG_A6XX_RB_FS_OUTPUT_CNTL1 0x0000880c 3412 #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f 3413 #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT 0 3414 static inline uint32_t A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val) 3415 { 3416 return ((val) << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK; 3417 } 3418 3419 #define REG_A6XX_RB_RENDER_COMPONENTS 0x0000880d 3420 #define A6XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f 3421 #define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0 3422 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) 3423 { 3424 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK; 3425 } 3426 #define A6XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0 3427 #define A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4 3428 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) 3429 { 3430 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK; 3431 } 3432 #define A6XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00 3433 #define A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8 3434 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) 3435 { 3436 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK; 3437 } 3438 #define A6XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000 3439 #define A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12 3440 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) 3441 { 3442 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK; 3443 } 3444 #define A6XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000 3445 #define A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16 3446 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) 3447 { 3448 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK; 3449 } 3450 #define A6XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000 3451 #define A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20 3452 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) 3453 { 3454 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK; 3455 } 3456 #define A6XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000 3457 #define A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24 3458 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) 3459 { 3460 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK; 3461 } 3462 #define A6XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000 3463 #define A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28 3464 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) 3465 { 3466 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK; 3467 } 3468 3469 #define REG_A6XX_RB_DITHER_CNTL 0x0000880e 3470 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK 0x00000003 3471 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT 0 3472 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val) 3473 { 3474 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK; 3475 } 3476 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK 0x0000000c 3477 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT 2 3478 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val) 3479 { 3480 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK; 3481 } 3482 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK 0x00000030 3483 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT 4 3484 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val) 3485 { 3486 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK; 3487 } 3488 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK 0x000000c0 3489 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT 6 3490 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val) 3491 { 3492 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK; 3493 } 3494 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK 0x00000300 3495 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT 8 3496 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val) 3497 { 3498 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK; 3499 } 3500 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK 0x00000c00 3501 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT 10 3502 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val) 3503 { 3504 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK; 3505 } 3506 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK 0x00001000 3507 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT 12 3508 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val) 3509 { 3510 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK; 3511 } 3512 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK 0x0000c000 3513 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT 14 3514 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val) 3515 { 3516 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK; 3517 } 3518 3519 #define REG_A6XX_RB_SRGB_CNTL 0x0000880f 3520 #define A6XX_RB_SRGB_CNTL_SRGB_MRT0 0x00000001 3521 #define A6XX_RB_SRGB_CNTL_SRGB_MRT1 0x00000002 3522 #define A6XX_RB_SRGB_CNTL_SRGB_MRT2 0x00000004 3523 #define A6XX_RB_SRGB_CNTL_SRGB_MRT3 0x00000008 3524 #define A6XX_RB_SRGB_CNTL_SRGB_MRT4 0x00000010 3525 #define A6XX_RB_SRGB_CNTL_SRGB_MRT5 0x00000020 3526 #define A6XX_RB_SRGB_CNTL_SRGB_MRT6 0x00000040 3527 #define A6XX_RB_SRGB_CNTL_SRGB_MRT7 0x00000080 3528 3529 #define REG_A6XX_RB_SAMPLE_CNTL 0x00008810 3530 #define A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001 3531 3532 #define REG_A6XX_RB_UNKNOWN_8811 0x00008811 3533 3534 #define REG_A6XX_RB_UNKNOWN_8818 0x00008818 3535 3536 #define REG_A6XX_RB_UNKNOWN_8819 0x00008819 3537 3538 #define REG_A6XX_RB_UNKNOWN_881A 0x0000881a 3539 3540 #define REG_A6XX_RB_UNKNOWN_881B 0x0000881b 3541 3542 #define REG_A6XX_RB_UNKNOWN_881C 0x0000881c 3543 3544 #define REG_A6XX_RB_UNKNOWN_881D 0x0000881d 3545 3546 #define REG_A6XX_RB_UNKNOWN_881E 0x0000881e 3547 3548 static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; } 3549 3550 static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; } 3551 #define A6XX_RB_MRT_CONTROL_BLEND 0x00000001 3552 #define A6XX_RB_MRT_CONTROL_BLEND2 0x00000002 3553 #define A6XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004 3554 #define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078 3555 #define A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3 3556 static inline uint32_t A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) 3557 { 3558 return ((val) << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK; 3559 } 3560 #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780 3561 #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7 3562 static inline uint32_t A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 3563 { 3564 return ((val) << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 3565 } 3566 3567 static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; } 3568 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 3569 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 3570 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 3571 { 3572 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 3573 } 3574 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 3575 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 3576 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 3577 { 3578 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 3579 } 3580 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 3581 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 3582 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 3583 { 3584 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 3585 } 3586 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 3587 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 3588 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 3589 { 3590 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 3591 } 3592 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 3593 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 3594 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 3595 { 3596 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 3597 } 3598 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 3599 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 3600 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 3601 { 3602 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 3603 } 3604 3605 static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; } 3606 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff 3607 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 3608 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val) 3609 { 3610 return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 3611 } 3612 #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300 3613 #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8 3614 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val) 3615 { 3616 return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 3617 } 3618 #define A6XX_RB_MRT_BUF_INFO_UNK10__MASK 0x00000400 3619 #define A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT 10 3620 static inline uint32_t A6XX_RB_MRT_BUF_INFO_UNK10(uint32_t val) 3621 { 3622 return ((val) << A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT) & A6XX_RB_MRT_BUF_INFO_UNK10__MASK; 3623 } 3624 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000 3625 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13 3626 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 3627 { 3628 return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 3629 } 3630 3631 static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; } 3632 #define A6XX_RB_MRT_PITCH__MASK 0x0000ffff 3633 #define A6XX_RB_MRT_PITCH__SHIFT 0 3634 static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val) 3635 { 3636 return ((val >> 6) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK; 3637 } 3638 3639 static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; } 3640 #define A6XX_RB_MRT_ARRAY_PITCH__MASK 0x1fffffff 3641 #define A6XX_RB_MRT_ARRAY_PITCH__SHIFT 0 3642 static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val) 3643 { 3644 return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK; 3645 } 3646 3647 static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; } 3648 #define A6XX_RB_MRT_BASE__MASK 0xffffffff 3649 #define A6XX_RB_MRT_BASE__SHIFT 0 3650 static inline uint32_t A6XX_RB_MRT_BASE(uint32_t val) 3651 { 3652 return ((val) << A6XX_RB_MRT_BASE__SHIFT) & A6XX_RB_MRT_BASE__MASK; 3653 } 3654 3655 static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; } 3656 #define A6XX_RB_MRT_BASE_GMEM__MASK 0xfffff000 3657 #define A6XX_RB_MRT_BASE_GMEM__SHIFT 12 3658 static inline uint32_t A6XX_RB_MRT_BASE_GMEM(uint32_t val) 3659 { 3660 return ((val >> 12) << A6XX_RB_MRT_BASE_GMEM__SHIFT) & A6XX_RB_MRT_BASE_GMEM__MASK; 3661 } 3662 3663 #define REG_A6XX_RB_BLEND_RED_F32 0x00008860 3664 #define A6XX_RB_BLEND_RED_F32__MASK 0xffffffff 3665 #define A6XX_RB_BLEND_RED_F32__SHIFT 0 3666 static inline uint32_t A6XX_RB_BLEND_RED_F32(float val) 3667 { 3668 return ((fui(val)) << A6XX_RB_BLEND_RED_F32__SHIFT) & A6XX_RB_BLEND_RED_F32__MASK; 3669 } 3670 3671 #define REG_A6XX_RB_BLEND_GREEN_F32 0x00008861 3672 #define A6XX_RB_BLEND_GREEN_F32__MASK 0xffffffff 3673 #define A6XX_RB_BLEND_GREEN_F32__SHIFT 0 3674 static inline uint32_t A6XX_RB_BLEND_GREEN_F32(float val) 3675 { 3676 return ((fui(val)) << A6XX_RB_BLEND_GREEN_F32__SHIFT) & A6XX_RB_BLEND_GREEN_F32__MASK; 3677 } 3678 3679 #define REG_A6XX_RB_BLEND_BLUE_F32 0x00008862 3680 #define A6XX_RB_BLEND_BLUE_F32__MASK 0xffffffff 3681 #define A6XX_RB_BLEND_BLUE_F32__SHIFT 0 3682 static inline uint32_t A6XX_RB_BLEND_BLUE_F32(float val) 3683 { 3684 return ((fui(val)) << A6XX_RB_BLEND_BLUE_F32__SHIFT) & A6XX_RB_BLEND_BLUE_F32__MASK; 3685 } 3686 3687 #define REG_A6XX_RB_BLEND_ALPHA_F32 0x00008863 3688 #define A6XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff 3689 #define A6XX_RB_BLEND_ALPHA_F32__SHIFT 0 3690 static inline uint32_t A6XX_RB_BLEND_ALPHA_F32(float val) 3691 { 3692 return ((fui(val)) << A6XX_RB_BLEND_ALPHA_F32__SHIFT) & A6XX_RB_BLEND_ALPHA_F32__MASK; 3693 } 3694 3695 #define REG_A6XX_RB_ALPHA_CONTROL 0x00008864 3696 #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff 3697 #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 3698 static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) 3699 { 3700 return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; 3701 } 3702 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 3703 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 3704 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 3705 static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 3706 { 3707 return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; 3708 } 3709 3710 #define REG_A6XX_RB_BLEND_CNTL 0x00008865 3711 #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff 3712 #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 3713 static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val) 3714 { 3715 return ((val) << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK; 3716 } 3717 #define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100 3718 #define A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200 3719 #define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 3720 #define A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE 0x00000800 3721 #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000 3722 #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16 3723 static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val) 3724 { 3725 return ((val) << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK; 3726 } 3727 3728 #define REG_A6XX_RB_DEPTH_PLANE_CNTL 0x00008870 3729 #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003 3730 #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0 3731 static inline uint32_t A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val) 3732 { 3733 return ((val) << A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK; 3734 } 3735 3736 #define REG_A6XX_RB_DEPTH_CNTL 0x00008871 3737 #define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000001 3738 #define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002 3739 #define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c 3740 #define A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2 3741 static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) 3742 { 3743 return ((val) << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK; 3744 } 3745 #define A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE 0x00000020 3746 #define A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE 0x00000040 3747 #define A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE 0x00000080 3748 3749 #define REG_A6XX_RB_DEPTH_BUFFER_INFO 0x00008872 3750 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 3751 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 3752 static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) 3753 { 3754 return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; 3755 } 3756 #define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000018 3757 #define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT 3 3758 static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val) 3759 { 3760 return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK; 3761 } 3762 3763 #define REG_A6XX_RB_DEPTH_BUFFER_PITCH 0x00008873 3764 #define A6XX_RB_DEPTH_BUFFER_PITCH__MASK 0x00003fff 3765 #define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0 3766 static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) 3767 { 3768 return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK; 3769 } 3770 3771 #define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x00008874 3772 #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0x0fffffff 3773 #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0 3774 static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) 3775 { 3776 return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; 3777 } 3778 3779 #define REG_A6XX_RB_DEPTH_BUFFER_BASE 0x00008875 3780 #define A6XX_RB_DEPTH_BUFFER_BASE__MASK 0xffffffff 3781 #define A6XX_RB_DEPTH_BUFFER_BASE__SHIFT 0 3782 static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE(uint32_t val) 3783 { 3784 return ((val) << A6XX_RB_DEPTH_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE__MASK; 3785 } 3786 3787 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM 0x00008877 3788 #define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK 0xfffff000 3789 #define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT 12 3790 static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE_GMEM(uint32_t val) 3791 { 3792 return ((val >> 12) << A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK; 3793 } 3794 3795 #define REG_A6XX_RB_Z_BOUNDS_MIN 0x00008878 3796 #define A6XX_RB_Z_BOUNDS_MIN__MASK 0xffffffff 3797 #define A6XX_RB_Z_BOUNDS_MIN__SHIFT 0 3798 static inline uint32_t A6XX_RB_Z_BOUNDS_MIN(float val) 3799 { 3800 return ((fui(val)) << A6XX_RB_Z_BOUNDS_MIN__SHIFT) & A6XX_RB_Z_BOUNDS_MIN__MASK; 3801 } 3802 3803 #define REG_A6XX_RB_Z_BOUNDS_MAX 0x00008879 3804 #define A6XX_RB_Z_BOUNDS_MAX__MASK 0xffffffff 3805 #define A6XX_RB_Z_BOUNDS_MAX__SHIFT 0 3806 static inline uint32_t A6XX_RB_Z_BOUNDS_MAX(float val) 3807 { 3808 return ((fui(val)) << A6XX_RB_Z_BOUNDS_MAX__SHIFT) & A6XX_RB_Z_BOUNDS_MAX__MASK; 3809 } 3810 3811 #define REG_A6XX_RB_STENCIL_CONTROL 0x00008880 3812 #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 3813 #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 3814 #define A6XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 3815 #define A6XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 3816 #define A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 3817 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 3818 { 3819 return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC__MASK; 3820 } 3821 #define A6XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 3822 #define A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 3823 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 3824 { 3825 return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL__MASK; 3826 } 3827 #define A6XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 3828 #define A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 3829 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 3830 { 3831 return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK; 3832 } 3833 #define A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 3834 #define A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 3835 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 3836 { 3837 return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 3838 } 3839 #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 3840 #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 3841 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 3842 { 3843 return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 3844 } 3845 #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 3846 #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 3847 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 3848 { 3849 return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 3850 } 3851 #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 3852 #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 3853 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 3854 { 3855 return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 3856 } 3857 #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 3858 #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 3859 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 3860 { 3861 return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 3862 } 3863 3864 #define REG_A6XX_RB_STENCIL_INFO 0x00008881 3865 #define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 3866 #define A6XX_RB_STENCIL_INFO_UNK1 0x00000002 3867 3868 #define REG_A6XX_RB_STENCIL_BUFFER_PITCH 0x00008882 3869 #define A6XX_RB_STENCIL_BUFFER_PITCH__MASK 0x00000fff 3870 #define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT 0 3871 static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val) 3872 { 3873 return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK; 3874 } 3875 3876 #define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH 0x00008883 3877 #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK 0x00ffffff 3878 #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT 0 3879 static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val) 3880 { 3881 return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK; 3882 } 3883 3884 #define REG_A6XX_RB_STENCIL_BUFFER_BASE 0x00008884 3885 #define A6XX_RB_STENCIL_BUFFER_BASE__MASK 0xffffffff 3886 #define A6XX_RB_STENCIL_BUFFER_BASE__SHIFT 0 3887 static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE(uint32_t val) 3888 { 3889 return ((val) << A6XX_RB_STENCIL_BUFFER_BASE__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE__MASK; 3890 } 3891 3892 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM 0x00008886 3893 #define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK 0xfffff000 3894 #define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT 12 3895 static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE_GMEM(uint32_t val) 3896 { 3897 return ((val >> 12) << A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK; 3898 } 3899 3900 #define REG_A6XX_RB_STENCILREF 0x00008887 3901 #define A6XX_RB_STENCILREF_REF__MASK 0x000000ff 3902 #define A6XX_RB_STENCILREF_REF__SHIFT 0 3903 static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val) 3904 { 3905 return ((val) << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK; 3906 } 3907 #define A6XX_RB_STENCILREF_BFREF__MASK 0x0000ff00 3908 #define A6XX_RB_STENCILREF_BFREF__SHIFT 8 3909 static inline uint32_t A6XX_RB_STENCILREF_BFREF(uint32_t val) 3910 { 3911 return ((val) << A6XX_RB_STENCILREF_BFREF__SHIFT) & A6XX_RB_STENCILREF_BFREF__MASK; 3912 } 3913 3914 #define REG_A6XX_RB_STENCILMASK 0x00008888 3915 #define A6XX_RB_STENCILMASK_MASK__MASK 0x000000ff 3916 #define A6XX_RB_STENCILMASK_MASK__SHIFT 0 3917 static inline uint32_t A6XX_RB_STENCILMASK_MASK(uint32_t val) 3918 { 3919 return ((val) << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK; 3920 } 3921 #define A6XX_RB_STENCILMASK_BFMASK__MASK 0x0000ff00 3922 #define A6XX_RB_STENCILMASK_BFMASK__SHIFT 8 3923 static inline uint32_t A6XX_RB_STENCILMASK_BFMASK(uint32_t val) 3924 { 3925 return ((val) << A6XX_RB_STENCILMASK_BFMASK__SHIFT) & A6XX_RB_STENCILMASK_BFMASK__MASK; 3926 } 3927 3928 #define REG_A6XX_RB_STENCILWRMASK 0x00008889 3929 #define A6XX_RB_STENCILWRMASK_WRMASK__MASK 0x000000ff 3930 #define A6XX_RB_STENCILWRMASK_WRMASK__SHIFT 0 3931 static inline uint32_t A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val) 3932 { 3933 return ((val) << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK; 3934 } 3935 #define A6XX_RB_STENCILWRMASK_BFWRMASK__MASK 0x0000ff00 3936 #define A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT 8 3937 static inline uint32_t A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val) 3938 { 3939 return ((val) << A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_BFWRMASK__MASK; 3940 } 3941 3942 #define REG_A6XX_RB_WINDOW_OFFSET 0x00008890 3943 #define A6XX_RB_WINDOW_OFFSET_X__MASK 0x00003fff 3944 #define A6XX_RB_WINDOW_OFFSET_X__SHIFT 0 3945 static inline uint32_t A6XX_RB_WINDOW_OFFSET_X(uint32_t val) 3946 { 3947 return ((val) << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK; 3948 } 3949 #define A6XX_RB_WINDOW_OFFSET_Y__MASK 0x3fff0000 3950 #define A6XX_RB_WINDOW_OFFSET_Y__SHIFT 16 3951 static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val) 3952 { 3953 return ((val) << A6XX_RB_WINDOW_OFFSET_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET_Y__MASK; 3954 } 3955 3956 #define REG_A6XX_RB_SAMPLE_COUNT_CONTROL 0x00008891 3957 #define A6XX_RB_SAMPLE_COUNT_CONTROL_DISABLE 0x00000001 3958 #define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 3959 3960 #define REG_A6XX_RB_LRZ_CNTL 0x00008898 3961 #define A6XX_RB_LRZ_CNTL_ENABLE 0x00000001 3962 3963 #define REG_A6XX_RB_Z_CLAMP_MIN 0x000088c0 3964 #define A6XX_RB_Z_CLAMP_MIN__MASK 0xffffffff 3965 #define A6XX_RB_Z_CLAMP_MIN__SHIFT 0 3966 static inline uint32_t A6XX_RB_Z_CLAMP_MIN(float val) 3967 { 3968 return ((fui(val)) << A6XX_RB_Z_CLAMP_MIN__SHIFT) & A6XX_RB_Z_CLAMP_MIN__MASK; 3969 } 3970 3971 #define REG_A6XX_RB_Z_CLAMP_MAX 0x000088c1 3972 #define A6XX_RB_Z_CLAMP_MAX__MASK 0xffffffff 3973 #define A6XX_RB_Z_CLAMP_MAX__SHIFT 0 3974 static inline uint32_t A6XX_RB_Z_CLAMP_MAX(float val) 3975 { 3976 return ((fui(val)) << A6XX_RB_Z_CLAMP_MAX__SHIFT) & A6XX_RB_Z_CLAMP_MAX__MASK; 3977 } 3978 3979 #define REG_A6XX_RB_UNKNOWN_88D0 0x000088d0 3980 #define A6XX_RB_UNKNOWN_88D0_UNK0__MASK 0x00001fff 3981 #define A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT 0 3982 static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK0(uint32_t val) 3983 { 3984 return ((val) << A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK0__MASK; 3985 } 3986 #define A6XX_RB_UNKNOWN_88D0_UNK16__MASK 0x07ff0000 3987 #define A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT 16 3988 static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK16(uint32_t val) 3989 { 3990 return ((val) << A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK16__MASK; 3991 } 3992 3993 #define REG_A6XX_RB_BLIT_SCISSOR_TL 0x000088d1 3994 #define A6XX_RB_BLIT_SCISSOR_TL_X__MASK 0x00003fff 3995 #define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT 0 3996 static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val) 3997 { 3998 return ((val) << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK; 3999 } 4000 #define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK 0x3fff0000 4001 #define A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT 16 4002 static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val) 4003 { 4004 return ((val) << A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_Y__MASK; 4005 } 4006 4007 #define REG_A6XX_RB_BLIT_SCISSOR_BR 0x000088d2 4008 #define A6XX_RB_BLIT_SCISSOR_BR_X__MASK 0x00003fff 4009 #define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT 0 4010 static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val) 4011 { 4012 return ((val) << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK; 4013 } 4014 #define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK 0x3fff0000 4015 #define A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT 16 4016 static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val) 4017 { 4018 return ((val) << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK; 4019 } 4020 4021 #define REG_A6XX_RB_BIN_CONTROL2 0x000088d3 4022 #define A6XX_RB_BIN_CONTROL2_BINW__MASK 0x0000003f 4023 #define A6XX_RB_BIN_CONTROL2_BINW__SHIFT 0 4024 static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val) 4025 { 4026 return ((val >> 5) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK; 4027 } 4028 #define A6XX_RB_BIN_CONTROL2_BINH__MASK 0x00007f00 4029 #define A6XX_RB_BIN_CONTROL2_BINH__SHIFT 8 4030 static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val) 4031 { 4032 return ((val >> 4) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK; 4033 } 4034 4035 #define REG_A6XX_RB_WINDOW_OFFSET2 0x000088d4 4036 #define A6XX_RB_WINDOW_OFFSET2_X__MASK 0x00003fff 4037 #define A6XX_RB_WINDOW_OFFSET2_X__SHIFT 0 4038 static inline uint32_t A6XX_RB_WINDOW_OFFSET2_X(uint32_t val) 4039 { 4040 return ((val) << A6XX_RB_WINDOW_OFFSET2_X__SHIFT) & A6XX_RB_WINDOW_OFFSET2_X__MASK; 4041 } 4042 #define A6XX_RB_WINDOW_OFFSET2_Y__MASK 0x3fff0000 4043 #define A6XX_RB_WINDOW_OFFSET2_Y__SHIFT 16 4044 static inline uint32_t A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val) 4045 { 4046 return ((val) << A6XX_RB_WINDOW_OFFSET2_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET2_Y__MASK; 4047 } 4048 4049 #define REG_A6XX_RB_BLIT_GMEM_MSAA_CNTL 0x000088d5 4050 #define A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__MASK 0x00000018 4051 #define A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__SHIFT 3 4052 static inline uint32_t A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 4053 { 4054 return ((val) << A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__MASK; 4055 } 4056 4057 #define REG_A6XX_RB_BLIT_BASE_GMEM 0x000088d6 4058 #define A6XX_RB_BLIT_BASE_GMEM__MASK 0xfffff000 4059 #define A6XX_RB_BLIT_BASE_GMEM__SHIFT 12 4060 static inline uint32_t A6XX_RB_BLIT_BASE_GMEM(uint32_t val) 4061 { 4062 return ((val >> 12) << A6XX_RB_BLIT_BASE_GMEM__SHIFT) & A6XX_RB_BLIT_BASE_GMEM__MASK; 4063 } 4064 4065 #define REG_A6XX_RB_BLIT_DST_INFO 0x000088d7 4066 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK 0x00000003 4067 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT 0 4068 static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) 4069 { 4070 return ((val) << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK; 4071 } 4072 #define A6XX_RB_BLIT_DST_INFO_FLAGS 0x00000004 4073 #define A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK 0x00000018 4074 #define A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT 3 4075 static inline uint32_t A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) 4076 { 4077 return ((val) << A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK; 4078 } 4079 #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK 0x00000060 4080 #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT 5 4081 static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) 4082 { 4083 return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK; 4084 } 4085 #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK 0x00007f80 4086 #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT 7 4087 static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_format val) 4088 { 4089 return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK; 4090 } 4091 #define A6XX_RB_BLIT_DST_INFO_UNK15 0x00008000 4092 4093 #define REG_A6XX_RB_BLIT_DST 0x000088d8 4094 #define A6XX_RB_BLIT_DST__MASK 0xffffffff 4095 #define A6XX_RB_BLIT_DST__SHIFT 0 4096 static inline uint32_t A6XX_RB_BLIT_DST(uint32_t val) 4097 { 4098 return ((val) << A6XX_RB_BLIT_DST__SHIFT) & A6XX_RB_BLIT_DST__MASK; 4099 } 4100 4101 #define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da 4102 #define A6XX_RB_BLIT_DST_PITCH__MASK 0x0000ffff 4103 #define A6XX_RB_BLIT_DST_PITCH__SHIFT 0 4104 static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val) 4105 { 4106 return ((val >> 6) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK; 4107 } 4108 4109 #define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH 0x000088db 4110 #define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0x1fffffff 4111 #define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0 4112 static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) 4113 { 4114 return ((val >> 6) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK; 4115 } 4116 4117 #define REG_A6XX_RB_BLIT_FLAG_DST 0x000088dc 4118 #define A6XX_RB_BLIT_FLAG_DST__MASK 0xffffffff 4119 #define A6XX_RB_BLIT_FLAG_DST__SHIFT 0 4120 static inline uint32_t A6XX_RB_BLIT_FLAG_DST(uint32_t val) 4121 { 4122 return ((val) << A6XX_RB_BLIT_FLAG_DST__SHIFT) & A6XX_RB_BLIT_FLAG_DST__MASK; 4123 } 4124 4125 #define REG_A6XX_RB_BLIT_FLAG_DST_PITCH 0x000088de 4126 #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK 0x000007ff 4127 #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT 0 4128 static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val) 4129 { 4130 return ((val >> 6) << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK; 4131 } 4132 #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK 0x0ffff800 4133 #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT 11 4134 static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val) 4135 { 4136 return ((val >> 7) << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK; 4137 } 4138 4139 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 0x000088df 4140 4141 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1 0x000088e0 4142 4143 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2 0x000088e1 4144 4145 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3 0x000088e2 4146 4147 #define REG_A6XX_RB_BLIT_INFO 0x000088e3 4148 #define A6XX_RB_BLIT_INFO_UNK0 0x00000001 4149 #define A6XX_RB_BLIT_INFO_GMEM 0x00000002 4150 #define A6XX_RB_BLIT_INFO_SAMPLE_0 0x00000004 4151 #define A6XX_RB_BLIT_INFO_DEPTH 0x00000008 4152 #define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK 0x000000f0 4153 #define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT 4 4154 static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val) 4155 { 4156 return ((val) << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK; 4157 } 4158 #define A6XX_RB_BLIT_INFO_LAST__MASK 0x00000300 4159 #define A6XX_RB_BLIT_INFO_LAST__SHIFT 8 4160 static inline uint32_t A6XX_RB_BLIT_INFO_LAST(uint32_t val) 4161 { 4162 return ((val) << A6XX_RB_BLIT_INFO_LAST__SHIFT) & A6XX_RB_BLIT_INFO_LAST__MASK; 4163 } 4164 #define A6XX_RB_BLIT_INFO_BUFFER_ID__MASK 0x0000f000 4165 #define A6XX_RB_BLIT_INFO_BUFFER_ID__SHIFT 12 4166 static inline uint32_t A6XX_RB_BLIT_INFO_BUFFER_ID(uint32_t val) 4167 { 4168 return ((val) << A6XX_RB_BLIT_INFO_BUFFER_ID__SHIFT) & A6XX_RB_BLIT_INFO_BUFFER_ID__MASK; 4169 } 4170 4171 #define REG_A6XX_RB_UNKNOWN_88F0 0x000088f0 4172 4173 #define REG_A6XX_RB_UNK_FLAG_BUFFER_BASE 0x000088f1 4174 #define A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK 0xffffffff 4175 #define A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT 0 4176 static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_BASE(uint32_t val) 4177 { 4178 return ((val) << A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK; 4179 } 4180 4181 #define REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH 0x000088f3 4182 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff 4183 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 4184 static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(uint32_t val) 4185 { 4186 return ((val >> 6) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK; 4187 } 4188 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x00fff800 4189 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 4190 static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 4191 { 4192 return ((val >> 7) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; 4193 } 4194 4195 #define REG_A6XX_RB_UNKNOWN_88F4 0x000088f4 4196 4197 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE 0x00008900 4198 #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK 0xffffffff 4199 #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT 0 4200 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_BASE(uint32_t val) 4201 { 4202 return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK; 4203 } 4204 4205 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x00008902 4206 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK 0x0000007f 4207 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 4208 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val) 4209 { 4210 return ((val >> 6) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK; 4211 } 4212 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK 0x00000700 4213 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT 8 4214 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8(uint32_t val) 4215 { 4216 return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK; 4217 } 4218 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x0ffff800 4219 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 4220 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 4221 { 4222 return ((val >> 7) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; 4223 } 4224 4225 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; } 4226 4227 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; } 4228 #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK 0xffffffff 4229 #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT 0 4230 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t val) 4231 { 4232 return ((val) << A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK; 4233 } 4234 4235 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; } 4236 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff 4237 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 4238 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val) 4239 { 4240 return ((val >> 6) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK; 4241 } 4242 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffff800 4243 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 4244 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 4245 { 4246 return ((val >> 7) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; 4247 } 4248 4249 #define REG_A6XX_RB_SAMPLE_COUNT_ADDR 0x00008927 4250 #define A6XX_RB_SAMPLE_COUNT_ADDR__MASK 0xffffffff 4251 #define A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT 0 4252 static inline uint32_t A6XX_RB_SAMPLE_COUNT_ADDR(uint32_t val) 4253 { 4254 return ((val) << A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT) & A6XX_RB_SAMPLE_COUNT_ADDR__MASK; 4255 } 4256 4257 #define REG_A6XX_RB_UNKNOWN_8A00 0x00008a00 4258 4259 #define REG_A6XX_RB_UNKNOWN_8A10 0x00008a10 4260 4261 #define REG_A6XX_RB_UNKNOWN_8A20 0x00008a20 4262 4263 #define REG_A6XX_RB_UNKNOWN_8A30 0x00008a30 4264 4265 #define REG_A6XX_RB_2D_BLIT_CNTL 0x00008c00 4266 #define A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK 0x00000007 4267 #define A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT 0 4268 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val) 4269 { 4270 return ((val) << A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK; 4271 } 4272 #define A6XX_RB_2D_BLIT_CNTL_OVERWRITEEN 0x00000008 4273 #define A6XX_RB_2D_BLIT_CNTL_UNK4__MASK 0x00000070 4274 #define A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT 4 4275 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK4(uint32_t val) 4276 { 4277 return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK4__MASK; 4278 } 4279 #define A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR 0x00000080 4280 #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00 4281 #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8 4282 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val) 4283 { 4284 return ((val) << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK; 4285 } 4286 #define A6XX_RB_2D_BLIT_CNTL_SCISSOR 0x00010000 4287 #define A6XX_RB_2D_BLIT_CNTL_UNK17__MASK 0x00060000 4288 #define A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT 17 4289 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK17(uint32_t val) 4290 { 4291 return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK17__MASK; 4292 } 4293 #define A6XX_RB_2D_BLIT_CNTL_D24S8 0x00080000 4294 #define A6XX_RB_2D_BLIT_CNTL_MASK__MASK 0x00f00000 4295 #define A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT 20 4296 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_MASK(uint32_t val) 4297 { 4298 return ((val) << A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_RB_2D_BLIT_CNTL_MASK__MASK; 4299 } 4300 #define A6XX_RB_2D_BLIT_CNTL_IFMT__MASK 0x1f000000 4301 #define A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT 24 4302 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val) 4303 { 4304 return ((val) << A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_IFMT__MASK; 4305 } 4306 #define A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK 0x20000000 4307 #define A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT 29 4308 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val) 4309 { 4310 return ((val) << A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK; 4311 } 4312 4313 #define REG_A6XX_RB_2D_UNKNOWN_8C01 0x00008c01 4314 4315 #define REG_A6XX_RB_2D_DST_INFO 0x00008c17 4316 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff 4317 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0 4318 static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_format val) 4319 { 4320 return ((val) << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK; 4321 } 4322 #define A6XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300 4323 #define A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8 4324 static inline uint32_t A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) 4325 { 4326 return ((val) << A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_2D_DST_INFO_TILE_MODE__MASK; 4327 } 4328 #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00 4329 #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10 4330 static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) 4331 { 4332 return ((val) << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK; 4333 } 4334 #define A6XX_RB_2D_DST_INFO_FLAGS 0x00001000 4335 #define A6XX_RB_2D_DST_INFO_SRGB 0x00002000 4336 #define A6XX_RB_2D_DST_INFO_SAMPLES__MASK 0x0000c000 4337 #define A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT 14 4338 static inline uint32_t A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) 4339 { 4340 return ((val) << A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_2D_DST_INFO_SAMPLES__MASK; 4341 } 4342 #define A6XX_RB_2D_DST_INFO_FILTER 0x00010000 4343 #define A6XX_RB_2D_DST_INFO_UNK17 0x00020000 4344 #define A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE 0x00040000 4345 #define A6XX_RB_2D_DST_INFO_UNK19 0x00080000 4346 #define A6XX_RB_2D_DST_INFO_UNK20 0x00100000 4347 #define A6XX_RB_2D_DST_INFO_UNK21 0x00200000 4348 #define A6XX_RB_2D_DST_INFO_UNK22 0x00400000 4349 #define A6XX_RB_2D_DST_INFO_UNK23__MASK 0x07800000 4350 #define A6XX_RB_2D_DST_INFO_UNK23__SHIFT 23 4351 static inline uint32_t A6XX_RB_2D_DST_INFO_UNK23(uint32_t val) 4352 { 4353 return ((val) << A6XX_RB_2D_DST_INFO_UNK23__SHIFT) & A6XX_RB_2D_DST_INFO_UNK23__MASK; 4354 } 4355 #define A6XX_RB_2D_DST_INFO_UNK28 0x10000000 4356 4357 #define REG_A6XX_RB_2D_DST 0x00008c18 4358 #define A6XX_RB_2D_DST__MASK 0xffffffff 4359 #define A6XX_RB_2D_DST__SHIFT 0 4360 static inline uint32_t A6XX_RB_2D_DST(uint32_t val) 4361 { 4362 return ((val) << A6XX_RB_2D_DST__SHIFT) & A6XX_RB_2D_DST__MASK; 4363 } 4364 4365 #define REG_A6XX_RB_2D_DST_PITCH 0x00008c1a 4366 #define A6XX_RB_2D_DST_PITCH__MASK 0x0000ffff 4367 #define A6XX_RB_2D_DST_PITCH__SHIFT 0 4368 static inline uint32_t A6XX_RB_2D_DST_PITCH(uint32_t val) 4369 { 4370 return ((val >> 6) << A6XX_RB_2D_DST_PITCH__SHIFT) & A6XX_RB_2D_DST_PITCH__MASK; 4371 } 4372 4373 #define REG_A6XX_RB_2D_DST_PLANE1 0x00008c1b 4374 #define A6XX_RB_2D_DST_PLANE1__MASK 0xffffffff 4375 #define A6XX_RB_2D_DST_PLANE1__SHIFT 0 4376 static inline uint32_t A6XX_RB_2D_DST_PLANE1(uint32_t val) 4377 { 4378 return ((val) << A6XX_RB_2D_DST_PLANE1__SHIFT) & A6XX_RB_2D_DST_PLANE1__MASK; 4379 } 4380 4381 #define REG_A6XX_RB_2D_DST_PLANE_PITCH 0x00008c1d 4382 #define A6XX_RB_2D_DST_PLANE_PITCH__MASK 0x0000ffff 4383 #define A6XX_RB_2D_DST_PLANE_PITCH__SHIFT 0 4384 static inline uint32_t A6XX_RB_2D_DST_PLANE_PITCH(uint32_t val) 4385 { 4386 return ((val >> 6) << A6XX_RB_2D_DST_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_PLANE_PITCH__MASK; 4387 } 4388 4389 #define REG_A6XX_RB_2D_DST_PLANE2 0x00008c1e 4390 #define A6XX_RB_2D_DST_PLANE2__MASK 0xffffffff 4391 #define A6XX_RB_2D_DST_PLANE2__SHIFT 0 4392 static inline uint32_t A6XX_RB_2D_DST_PLANE2(uint32_t val) 4393 { 4394 return ((val) << A6XX_RB_2D_DST_PLANE2__SHIFT) & A6XX_RB_2D_DST_PLANE2__MASK; 4395 } 4396 4397 #define REG_A6XX_RB_2D_DST_FLAGS 0x00008c20 4398 #define A6XX_RB_2D_DST_FLAGS__MASK 0xffffffff 4399 #define A6XX_RB_2D_DST_FLAGS__SHIFT 0 4400 static inline uint32_t A6XX_RB_2D_DST_FLAGS(uint32_t val) 4401 { 4402 return ((val) << A6XX_RB_2D_DST_FLAGS__SHIFT) & A6XX_RB_2D_DST_FLAGS__MASK; 4403 } 4404 4405 #define REG_A6XX_RB_2D_DST_FLAGS_PITCH 0x00008c22 4406 #define A6XX_RB_2D_DST_FLAGS_PITCH__MASK 0x000000ff 4407 #define A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT 0 4408 static inline uint32_t A6XX_RB_2D_DST_FLAGS_PITCH(uint32_t val) 4409 { 4410 return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH__MASK; 4411 } 4412 4413 #define REG_A6XX_RB_2D_DST_FLAGS_PLANE 0x00008c23 4414 #define A6XX_RB_2D_DST_FLAGS_PLANE__MASK 0xffffffff 4415 #define A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT 0 4416 static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE(uint32_t val) 4417 { 4418 return ((val) << A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE__MASK; 4419 } 4420 4421 #define REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH 0x00008c25 4422 #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK 0x000000ff 4423 #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT 0 4424 static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(uint32_t val) 4425 { 4426 return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK; 4427 } 4428 4429 #define REG_A6XX_RB_2D_SRC_SOLID_C0 0x00008c2c 4430 4431 #define REG_A6XX_RB_2D_SRC_SOLID_C1 0x00008c2d 4432 4433 #define REG_A6XX_RB_2D_SRC_SOLID_C2 0x00008c2e 4434 4435 #define REG_A6XX_RB_2D_SRC_SOLID_C3 0x00008c2f 4436 4437 #define REG_A6XX_RB_UNKNOWN_8E01 0x00008e01 4438 4439 #define REG_A6XX_RB_DBG_ECO_CNTL 0x00008e04 4440 4441 #define REG_A6XX_RB_ADDR_MODE_CNTL 0x00008e05 4442 4443 #define REG_A6XX_RB_CCU_CNTL 0x00008e07 4444 #define A6XX_RB_CCU_CNTL_CONCURRENT_RESOLVE 0x00000004 4445 #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__MASK 0x00000080 4446 #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__SHIFT 7 4447 static inline uint32_t A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI(uint32_t val) 4448 { 4449 return ((val) << A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__MASK; 4450 } 4451 #define A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__MASK 0x00000200 4452 #define A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__SHIFT 9 4453 static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI(uint32_t val) 4454 { 4455 return ((val) << A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__MASK; 4456 } 4457 #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK 0x001ff000 4458 #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT 12 4459 static inline uint32_t A6XX_RB_CCU_CNTL_DEPTH_OFFSET(uint32_t val) 4460 { 4461 return ((val >> 12) << A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK; 4462 } 4463 #define A6XX_RB_CCU_CNTL_GMEM 0x00400000 4464 #define A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK 0xff800000 4465 #define A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT 23 4466 static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_OFFSET(uint32_t val) 4467 { 4468 return ((val >> 12) << A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK; 4469 } 4470 4471 #define REG_A6XX_RB_NC_MODE_CNTL 0x00008e08 4472 #define A6XX_RB_NC_MODE_CNTL_MODE 0x00000001 4473 #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006 4474 #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT 1 4475 static inline uint32_t A6XX_RB_NC_MODE_CNTL_LOWER_BIT(uint32_t val) 4476 { 4477 return ((val) << A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK; 4478 } 4479 #define A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008 4480 #define A6XX_RB_NC_MODE_CNTL_AMSBC 0x00000010 4481 #define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000400 4482 #define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT 10 4483 static inline uint32_t A6XX_RB_NC_MODE_CNTL_UPPER_BIT(uint32_t val) 4484 { 4485 return ((val) << A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK; 4486 } 4487 #define A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR 0x00000800 4488 #define A6XX_RB_NC_MODE_CNTL_UNK12__MASK 0x00003000 4489 #define A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT 12 4490 static inline uint32_t A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val) 4491 { 4492 return ((val) << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK; 4493 } 4494 4495 static inline uint32_t REG_A6XX_RB_PERFCTR_RB_SEL(uint32_t i0) { return 0x00008e10 + 0x1*i0; } 4496 4497 static inline uint32_t REG_A6XX_RB_PERFCTR_CCU_SEL(uint32_t i0) { return 0x00008e18 + 0x1*i0; } 4498 4499 #define REG_A6XX_RB_UNKNOWN_8E28 0x00008e28 4500 4501 static inline uint32_t REG_A6XX_RB_PERFCTR_CMP_SEL(uint32_t i0) { return 0x00008e2c + 0x1*i0; } 4502 4503 static inline uint32_t REG_A7XX_RB_PERFCTR_UFC_SEL(uint32_t i0) { return 0x00008e30 + 0x1*i0; } 4504 4505 #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST 0x00008e3b 4506 4507 #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD 0x00008e3d 4508 4509 #define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x00008e50 4510 4511 #define REG_A6XX_RB_UNKNOWN_8E51 0x00008e51 4512 #define A6XX_RB_UNKNOWN_8E51__MASK 0xffffffff 4513 #define A6XX_RB_UNKNOWN_8E51__SHIFT 0 4514 static inline uint32_t A6XX_RB_UNKNOWN_8E51(uint32_t val) 4515 { 4516 return ((val) << A6XX_RB_UNKNOWN_8E51__SHIFT) & A6XX_RB_UNKNOWN_8E51__MASK; 4517 } 4518 4519 #define REG_A6XX_VPC_GS_PARAM 0x00009100 4520 #define A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK 0x000000ff 4521 #define A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT 0 4522 static inline uint32_t A6XX_VPC_GS_PARAM_LINELENGTHLOC(uint32_t val) 4523 { 4524 return ((val) << A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT) & A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK; 4525 } 4526 4527 #define REG_A6XX_VPC_VS_CLIP_CNTL 0x00009101 4528 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff 4529 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT 0 4530 static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(uint32_t val) 4531 { 4532 return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK; 4533 } 4534 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00 4535 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8 4536 static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) 4537 { 4538 return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK; 4539 } 4540 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000 4541 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16 4542 static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) 4543 { 4544 return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; 4545 } 4546 4547 #define REG_A6XX_VPC_GS_CLIP_CNTL 0x00009102 4548 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff 4549 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT 0 4550 static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK(uint32_t val) 4551 { 4552 return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK; 4553 } 4554 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00 4555 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8 4556 static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) 4557 { 4558 return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK; 4559 } 4560 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000 4561 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16 4562 static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) 4563 { 4564 return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; 4565 } 4566 4567 #define REG_A6XX_VPC_DS_CLIP_CNTL 0x00009103 4568 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff 4569 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT 0 4570 static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK(uint32_t val) 4571 { 4572 return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK; 4573 } 4574 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00 4575 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8 4576 static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) 4577 { 4578 return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK; 4579 } 4580 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000 4581 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16 4582 static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) 4583 { 4584 return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; 4585 } 4586 4587 #define REG_A6XX_VPC_VS_LAYER_CNTL 0x00009104 4588 #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff 4589 #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT 0 4590 static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(uint32_t val) 4591 { 4592 return ((val) << A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK; 4593 } 4594 #define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00 4595 #define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT 8 4596 static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(uint32_t val) 4597 { 4598 return ((val) << A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK; 4599 } 4600 4601 #define REG_A6XX_VPC_GS_LAYER_CNTL 0x00009105 4602 #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff 4603 #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT 0 4604 static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(uint32_t val) 4605 { 4606 return ((val) << A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK; 4607 } 4608 #define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00 4609 #define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT 8 4610 static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(uint32_t val) 4611 { 4612 return ((val) << A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK; 4613 } 4614 4615 #define REG_A6XX_VPC_DS_LAYER_CNTL 0x00009106 4616 #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff 4617 #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT 0 4618 static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_LAYERLOC(uint32_t val) 4619 { 4620 return ((val) << A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK; 4621 } 4622 #define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00 4623 #define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT 8 4624 static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val) 4625 { 4626 return ((val) << A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK; 4627 } 4628 4629 #define REG_A6XX_VPC_UNKNOWN_9107 0x00009107 4630 #define A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD 0x00000001 4631 #define A6XX_VPC_UNKNOWN_9107_UNK2 0x00000004 4632 4633 #define REG_A6XX_VPC_POLYGON_MODE 0x00009108 4634 #define A6XX_VPC_POLYGON_MODE_MODE__MASK 0x00000003 4635 #define A6XX_VPC_POLYGON_MODE_MODE__SHIFT 0 4636 static inline uint32_t A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) 4637 { 4638 return ((val) << A6XX_VPC_POLYGON_MODE_MODE__SHIFT) & A6XX_VPC_POLYGON_MODE_MODE__MASK; 4639 } 4640 4641 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; } 4642 4643 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; } 4644 4645 static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; } 4646 4647 static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; } 4648 4649 #define REG_A6XX_VPC_UNKNOWN_9210 0x00009210 4650 4651 #define REG_A6XX_VPC_UNKNOWN_9211 0x00009211 4652 4653 static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; } 4654 4655 static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; } 4656 4657 #define REG_A6XX_VPC_SO_CNTL 0x00009216 4658 #define A6XX_VPC_SO_CNTL_ADDR__MASK 0x000000ff 4659 #define A6XX_VPC_SO_CNTL_ADDR__SHIFT 0 4660 static inline uint32_t A6XX_VPC_SO_CNTL_ADDR(uint32_t val) 4661 { 4662 return ((val) << A6XX_VPC_SO_CNTL_ADDR__SHIFT) & A6XX_VPC_SO_CNTL_ADDR__MASK; 4663 } 4664 #define A6XX_VPC_SO_CNTL_RESET 0x00010000 4665 4666 #define REG_A6XX_VPC_SO_PROG 0x00009217 4667 #define A6XX_VPC_SO_PROG_A_BUF__MASK 0x00000003 4668 #define A6XX_VPC_SO_PROG_A_BUF__SHIFT 0 4669 static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val) 4670 { 4671 return ((val) << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK; 4672 } 4673 #define A6XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc 4674 #define A6XX_VPC_SO_PROG_A_OFF__SHIFT 2 4675 static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val) 4676 { 4677 return ((val >> 2) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK; 4678 } 4679 #define A6XX_VPC_SO_PROG_A_EN 0x00000800 4680 #define A6XX_VPC_SO_PROG_B_BUF__MASK 0x00003000 4681 #define A6XX_VPC_SO_PROG_B_BUF__SHIFT 12 4682 static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val) 4683 { 4684 return ((val) << A6XX_VPC_SO_PROG_B_BUF__SHIFT) & A6XX_VPC_SO_PROG_B_BUF__MASK; 4685 } 4686 #define A6XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000 4687 #define A6XX_VPC_SO_PROG_B_OFF__SHIFT 14 4688 static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val) 4689 { 4690 return ((val >> 2) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK; 4691 } 4692 #define A6XX_VPC_SO_PROG_B_EN 0x00800000 4693 4694 #define REG_A6XX_VPC_SO_STREAM_COUNTS 0x00009218 4695 #define A6XX_VPC_SO_STREAM_COUNTS__MASK 0xffffffff 4696 #define A6XX_VPC_SO_STREAM_COUNTS__SHIFT 0 4697 static inline uint32_t A6XX_VPC_SO_STREAM_COUNTS(uint32_t val) 4698 { 4699 return ((val) << A6XX_VPC_SO_STREAM_COUNTS__SHIFT) & A6XX_VPC_SO_STREAM_COUNTS__MASK; 4700 } 4701 4702 static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; } 4703 4704 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0) { return 0x0000921a + 0x7*i0; } 4705 #define A6XX_VPC_SO_BUFFER_BASE__MASK 0xffffffff 4706 #define A6XX_VPC_SO_BUFFER_BASE__SHIFT 0 4707 static inline uint32_t A6XX_VPC_SO_BUFFER_BASE(uint32_t val) 4708 { 4709 return ((val) << A6XX_VPC_SO_BUFFER_BASE__SHIFT) & A6XX_VPC_SO_BUFFER_BASE__MASK; 4710 } 4711 4712 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; } 4713 #define A6XX_VPC_SO_BUFFER_SIZE__MASK 0xfffffffc 4714 #define A6XX_VPC_SO_BUFFER_SIZE__SHIFT 2 4715 static inline uint32_t A6XX_VPC_SO_BUFFER_SIZE(uint32_t val) 4716 { 4717 return ((val >> 2) << A6XX_VPC_SO_BUFFER_SIZE__SHIFT) & A6XX_VPC_SO_BUFFER_SIZE__MASK; 4718 } 4719 4720 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_STRIDE(uint32_t i0) { return 0x0000921d + 0x7*i0; } 4721 #define A6XX_VPC_SO_BUFFER_STRIDE__MASK 0x000003ff 4722 #define A6XX_VPC_SO_BUFFER_STRIDE__SHIFT 0 4723 static inline uint32_t A6XX_VPC_SO_BUFFER_STRIDE(uint32_t val) 4724 { 4725 return ((val >> 2) << A6XX_VPC_SO_BUFFER_STRIDE__SHIFT) & A6XX_VPC_SO_BUFFER_STRIDE__MASK; 4726 } 4727 4728 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; } 4729 #define A6XX_VPC_SO_BUFFER_OFFSET__MASK 0xfffffffc 4730 #define A6XX_VPC_SO_BUFFER_OFFSET__SHIFT 2 4731 static inline uint32_t A6XX_VPC_SO_BUFFER_OFFSET(uint32_t val) 4732 { 4733 return ((val >> 2) << A6XX_VPC_SO_BUFFER_OFFSET__SHIFT) & A6XX_VPC_SO_BUFFER_OFFSET__MASK; 4734 } 4735 4736 static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0) { return 0x0000921f + 0x7*i0; } 4737 #define A6XX_VPC_SO_FLUSH_BASE__MASK 0xffffffff 4738 #define A6XX_VPC_SO_FLUSH_BASE__SHIFT 0 4739 static inline uint32_t A6XX_VPC_SO_FLUSH_BASE(uint32_t val) 4740 { 4741 return ((val) << A6XX_VPC_SO_FLUSH_BASE__SHIFT) & A6XX_VPC_SO_FLUSH_BASE__MASK; 4742 } 4743 4744 #define REG_A6XX_VPC_POINT_COORD_INVERT 0x00009236 4745 #define A6XX_VPC_POINT_COORD_INVERT_INVERT 0x00000001 4746 4747 #define REG_A6XX_VPC_UNKNOWN_9300 0x00009300 4748 4749 #define REG_A6XX_VPC_VS_PACK 0x00009301 4750 #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK 0x000000ff 4751 #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT 0 4752 static inline uint32_t A6XX_VPC_VS_PACK_STRIDE_IN_VPC(uint32_t val) 4753 { 4754 return ((val) << A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK; 4755 } 4756 #define A6XX_VPC_VS_PACK_POSITIONLOC__MASK 0x0000ff00 4757 #define A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT 8 4758 static inline uint32_t A6XX_VPC_VS_PACK_POSITIONLOC(uint32_t val) 4759 { 4760 return ((val) << A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_VS_PACK_POSITIONLOC__MASK; 4761 } 4762 #define A6XX_VPC_VS_PACK_PSIZELOC__MASK 0x00ff0000 4763 #define A6XX_VPC_VS_PACK_PSIZELOC__SHIFT 16 4764 static inline uint32_t A6XX_VPC_VS_PACK_PSIZELOC(uint32_t val) 4765 { 4766 return ((val) << A6XX_VPC_VS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_VS_PACK_PSIZELOC__MASK; 4767 } 4768 #define A6XX_VPC_VS_PACK_EXTRAPOS__MASK 0x0f000000 4769 #define A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT 24 4770 static inline uint32_t A6XX_VPC_VS_PACK_EXTRAPOS(uint32_t val) 4771 { 4772 return ((val) << A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_VS_PACK_EXTRAPOS__MASK; 4773 } 4774 4775 #define REG_A6XX_VPC_GS_PACK 0x00009302 4776 #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK 0x000000ff 4777 #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT 0 4778 static inline uint32_t A6XX_VPC_GS_PACK_STRIDE_IN_VPC(uint32_t val) 4779 { 4780 return ((val) << A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK; 4781 } 4782 #define A6XX_VPC_GS_PACK_POSITIONLOC__MASK 0x0000ff00 4783 #define A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT 8 4784 static inline uint32_t A6XX_VPC_GS_PACK_POSITIONLOC(uint32_t val) 4785 { 4786 return ((val) << A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_GS_PACK_POSITIONLOC__MASK; 4787 } 4788 #define A6XX_VPC_GS_PACK_PSIZELOC__MASK 0x00ff0000 4789 #define A6XX_VPC_GS_PACK_PSIZELOC__SHIFT 16 4790 static inline uint32_t A6XX_VPC_GS_PACK_PSIZELOC(uint32_t val) 4791 { 4792 return ((val) << A6XX_VPC_GS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_GS_PACK_PSIZELOC__MASK; 4793 } 4794 #define A6XX_VPC_GS_PACK_EXTRAPOS__MASK 0x0f000000 4795 #define A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT 24 4796 static inline uint32_t A6XX_VPC_GS_PACK_EXTRAPOS(uint32_t val) 4797 { 4798 return ((val) << A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_GS_PACK_EXTRAPOS__MASK; 4799 } 4800 4801 #define REG_A6XX_VPC_DS_PACK 0x00009303 4802 #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK 0x000000ff 4803 #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT 0 4804 static inline uint32_t A6XX_VPC_DS_PACK_STRIDE_IN_VPC(uint32_t val) 4805 { 4806 return ((val) << A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK; 4807 } 4808 #define A6XX_VPC_DS_PACK_POSITIONLOC__MASK 0x0000ff00 4809 #define A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT 8 4810 static inline uint32_t A6XX_VPC_DS_PACK_POSITIONLOC(uint32_t val) 4811 { 4812 return ((val) << A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_DS_PACK_POSITIONLOC__MASK; 4813 } 4814 #define A6XX_VPC_DS_PACK_PSIZELOC__MASK 0x00ff0000 4815 #define A6XX_VPC_DS_PACK_PSIZELOC__SHIFT 16 4816 static inline uint32_t A6XX_VPC_DS_PACK_PSIZELOC(uint32_t val) 4817 { 4818 return ((val) << A6XX_VPC_DS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_DS_PACK_PSIZELOC__MASK; 4819 } 4820 #define A6XX_VPC_DS_PACK_EXTRAPOS__MASK 0x0f000000 4821 #define A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT 24 4822 static inline uint32_t A6XX_VPC_DS_PACK_EXTRAPOS(uint32_t val) 4823 { 4824 return ((val) << A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_DS_PACK_EXTRAPOS__MASK; 4825 } 4826 4827 #define REG_A6XX_VPC_CNTL_0 0x00009304 4828 #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK 0x000000ff 4829 #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT 0 4830 static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val) 4831 { 4832 return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK; 4833 } 4834 #define A6XX_VPC_CNTL_0_PRIMIDLOC__MASK 0x0000ff00 4835 #define A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT 8 4836 static inline uint32_t A6XX_VPC_CNTL_0_PRIMIDLOC(uint32_t val) 4837 { 4838 return ((val) << A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT) & A6XX_VPC_CNTL_0_PRIMIDLOC__MASK; 4839 } 4840 #define A6XX_VPC_CNTL_0_VARYING 0x00010000 4841 #define A6XX_VPC_CNTL_0_VIEWIDLOC__MASK 0xff000000 4842 #define A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT 24 4843 static inline uint32_t A6XX_VPC_CNTL_0_VIEWIDLOC(uint32_t val) 4844 { 4845 return ((val) << A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT) & A6XX_VPC_CNTL_0_VIEWIDLOC__MASK; 4846 } 4847 4848 #define REG_A6XX_VPC_SO_STREAM_CNTL 0x00009305 4849 #define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK 0x00000007 4850 #define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT 0 4851 static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(uint32_t val) 4852 { 4853 return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK; 4854 } 4855 #define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK 0x00000038 4856 #define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT 3 4857 static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(uint32_t val) 4858 { 4859 return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK; 4860 } 4861 #define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK 0x000001c0 4862 #define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT 6 4863 static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(uint32_t val) 4864 { 4865 return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK; 4866 } 4867 #define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK 0x00000e00 4868 #define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT 9 4869 static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(uint32_t val) 4870 { 4871 return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK; 4872 } 4873 #define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK 0x00078000 4874 #define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT 15 4875 static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val) 4876 { 4877 return ((val) << A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK; 4878 } 4879 4880 #define REG_A6XX_VPC_SO_DISABLE 0x00009306 4881 #define A6XX_VPC_SO_DISABLE_DISABLE 0x00000001 4882 4883 #define REG_A6XX_VPC_DBG_ECO_CNTL 0x00009600 4884 4885 #define REG_A6XX_VPC_ADDR_MODE_CNTL 0x00009601 4886 4887 #define REG_A6XX_VPC_UNKNOWN_9602 0x00009602 4888 4889 #define REG_A6XX_VPC_UNKNOWN_9603 0x00009603 4890 4891 static inline uint32_t REG_A6XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) { return 0x00009604 + 0x1*i0; } 4892 4893 static inline uint32_t REG_A7XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) { return 0x0000960b + 0x1*i0; } 4894 4895 #define REG_A6XX_PC_TESS_NUM_VERTEX 0x00009800 4896 4897 #define REG_A6XX_PC_HS_INPUT_SIZE 0x00009801 4898 #define A6XX_PC_HS_INPUT_SIZE_SIZE__MASK 0x000007ff 4899 #define A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT 0 4900 static inline uint32_t A6XX_PC_HS_INPUT_SIZE_SIZE(uint32_t val) 4901 { 4902 return ((val) << A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT) & A6XX_PC_HS_INPUT_SIZE_SIZE__MASK; 4903 } 4904 #define A6XX_PC_HS_INPUT_SIZE_UNK13__MASK 0x00002000 4905 #define A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT 13 4906 static inline uint32_t A6XX_PC_HS_INPUT_SIZE_UNK13(uint32_t val) 4907 { 4908 return ((val) << A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT) & A6XX_PC_HS_INPUT_SIZE_UNK13__MASK; 4909 } 4910 4911 #define REG_A6XX_PC_TESS_CNTL 0x00009802 4912 #define A6XX_PC_TESS_CNTL_SPACING__MASK 0x00000003 4913 #define A6XX_PC_TESS_CNTL_SPACING__SHIFT 0 4914 static inline uint32_t A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val) 4915 { 4916 return ((val) << A6XX_PC_TESS_CNTL_SPACING__SHIFT) & A6XX_PC_TESS_CNTL_SPACING__MASK; 4917 } 4918 #define A6XX_PC_TESS_CNTL_OUTPUT__MASK 0x0000000c 4919 #define A6XX_PC_TESS_CNTL_OUTPUT__SHIFT 2 4920 static inline uint32_t A6XX_PC_TESS_CNTL_OUTPUT(enum a6xx_tess_output val) 4921 { 4922 return ((val) << A6XX_PC_TESS_CNTL_OUTPUT__SHIFT) & A6XX_PC_TESS_CNTL_OUTPUT__MASK; 4923 } 4924 4925 #define REG_A6XX_PC_RESTART_INDEX 0x00009803 4926 4927 #define REG_A6XX_PC_MODE_CNTL 0x00009804 4928 4929 #define REG_A6XX_PC_POWER_CNTL 0x00009805 4930 4931 #define REG_A6XX_PC_PRIMID_PASSTHRU 0x00009806 4932 4933 #define REG_A6XX_PC_SO_STREAM_CNTL 0x00009808 4934 #define A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__MASK 0x00078000 4935 #define A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT 15 4936 static inline uint32_t A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val) 4937 { 4938 return ((val) << A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__MASK; 4939 } 4940 4941 #define REG_A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL 0x0000980a 4942 #define A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN 0x00000001 4943 4944 #define REG_A6XX_PC_DRAW_CMD 0x00009840 4945 #define A6XX_PC_DRAW_CMD_STATE_ID__MASK 0x000000ff 4946 #define A6XX_PC_DRAW_CMD_STATE_ID__SHIFT 0 4947 static inline uint32_t A6XX_PC_DRAW_CMD_STATE_ID(uint32_t val) 4948 { 4949 return ((val) << A6XX_PC_DRAW_CMD_STATE_ID__SHIFT) & A6XX_PC_DRAW_CMD_STATE_ID__MASK; 4950 } 4951 4952 #define REG_A6XX_PC_DISPATCH_CMD 0x00009841 4953 #define A6XX_PC_DISPATCH_CMD_STATE_ID__MASK 0x000000ff 4954 #define A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT 0 4955 static inline uint32_t A6XX_PC_DISPATCH_CMD_STATE_ID(uint32_t val) 4956 { 4957 return ((val) << A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_PC_DISPATCH_CMD_STATE_ID__MASK; 4958 } 4959 4960 #define REG_A6XX_PC_EVENT_CMD 0x00009842 4961 #define A6XX_PC_EVENT_CMD_STATE_ID__MASK 0x00ff0000 4962 #define A6XX_PC_EVENT_CMD_STATE_ID__SHIFT 16 4963 static inline uint32_t A6XX_PC_EVENT_CMD_STATE_ID(uint32_t val) 4964 { 4965 return ((val) << A6XX_PC_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_EVENT_CMD_STATE_ID__MASK; 4966 } 4967 #define A6XX_PC_EVENT_CMD_EVENT__MASK 0x0000007f 4968 #define A6XX_PC_EVENT_CMD_EVENT__SHIFT 0 4969 static inline uint32_t A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val) 4970 { 4971 return ((val) << A6XX_PC_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_EVENT_CMD_EVENT__MASK; 4972 } 4973 4974 #define REG_A6XX_PC_MARKER 0x00009880 4975 4976 #define REG_A6XX_PC_POLYGON_MODE 0x00009981 4977 #define A6XX_PC_POLYGON_MODE_MODE__MASK 0x00000003 4978 #define A6XX_PC_POLYGON_MODE_MODE__SHIFT 0 4979 static inline uint32_t A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) 4980 { 4981 return ((val) << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK; 4982 } 4983 4984 #define REG_A6XX_PC_RASTER_CNTL 0x00009980 4985 #define A6XX_PC_RASTER_CNTL_STREAM__MASK 0x00000003 4986 #define A6XX_PC_RASTER_CNTL_STREAM__SHIFT 0 4987 static inline uint32_t A6XX_PC_RASTER_CNTL_STREAM(uint32_t val) 4988 { 4989 return ((val) << A6XX_PC_RASTER_CNTL_STREAM__SHIFT) & A6XX_PC_RASTER_CNTL_STREAM__MASK; 4990 } 4991 #define A6XX_PC_RASTER_CNTL_DISCARD 0x00000004 4992 4993 #define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00 4994 #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001 4995 #define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002 4996 #define A6XX_PC_PRIMITIVE_CNTL_0_TESS_UPPER_LEFT_DOMAIN_ORIGIN 0x00000004 4997 #define A6XX_PC_PRIMITIVE_CNTL_0_UNK3 0x00000008 4998 4999 #define REG_A6XX_PC_VS_OUT_CNTL 0x00009b01 5000 #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff 5001 #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 5002 static inline uint32_t A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) 5003 { 5004 return ((val) << A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK; 5005 } 5006 #define A6XX_PC_VS_OUT_CNTL_PSIZE 0x00000100 5007 #define A6XX_PC_VS_OUT_CNTL_LAYER 0x00000200 5008 #define A6XX_PC_VS_OUT_CNTL_VIEW 0x00000400 5009 #define A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID 0x00000800 5010 #define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 5011 #define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT 16 5012 static inline uint32_t A6XX_PC_VS_OUT_CNTL_CLIP_MASK(uint32_t val) 5013 { 5014 return ((val) << A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK; 5015 } 5016 5017 #define REG_A6XX_PC_GS_OUT_CNTL 0x00009b02 5018 #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff 5019 #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 5020 static inline uint32_t A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) 5021 { 5022 return ((val) << A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK; 5023 } 5024 #define A6XX_PC_GS_OUT_CNTL_PSIZE 0x00000100 5025 #define A6XX_PC_GS_OUT_CNTL_LAYER 0x00000200 5026 #define A6XX_PC_GS_OUT_CNTL_VIEW 0x00000400 5027 #define A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID 0x00000800 5028 #define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 5029 #define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT 16 5030 static inline uint32_t A6XX_PC_GS_OUT_CNTL_CLIP_MASK(uint32_t val) 5031 { 5032 return ((val) << A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK; 5033 } 5034 5035 #define REG_A6XX_PC_HS_OUT_CNTL 0x00009b03 5036 #define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff 5037 #define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 5038 static inline uint32_t A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) 5039 { 5040 return ((val) << A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK; 5041 } 5042 #define A6XX_PC_HS_OUT_CNTL_PSIZE 0x00000100 5043 #define A6XX_PC_HS_OUT_CNTL_LAYER 0x00000200 5044 #define A6XX_PC_HS_OUT_CNTL_VIEW 0x00000400 5045 #define A6XX_PC_HS_OUT_CNTL_PRIMITIVE_ID 0x00000800 5046 #define A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 5047 #define A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT 16 5048 static inline uint32_t A6XX_PC_HS_OUT_CNTL_CLIP_MASK(uint32_t val) 5049 { 5050 return ((val) << A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK; 5051 } 5052 5053 #define REG_A6XX_PC_DS_OUT_CNTL 0x00009b04 5054 #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff 5055 #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 5056 static inline uint32_t A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) 5057 { 5058 return ((val) << A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK; 5059 } 5060 #define A6XX_PC_DS_OUT_CNTL_PSIZE 0x00000100 5061 #define A6XX_PC_DS_OUT_CNTL_LAYER 0x00000200 5062 #define A6XX_PC_DS_OUT_CNTL_VIEW 0x00000400 5063 #define A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID 0x00000800 5064 #define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 5065 #define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT 16 5066 static inline uint32_t A6XX_PC_DS_OUT_CNTL_CLIP_MASK(uint32_t val) 5067 { 5068 return ((val) << A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK; 5069 } 5070 5071 #define REG_A6XX_PC_PRIMITIVE_CNTL_5 0x00009b05 5072 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK 0x000000ff 5073 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT 0 5074 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val) 5075 { 5076 return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK; 5077 } 5078 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK 0x00007c00 5079 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT 10 5080 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val) 5081 { 5082 return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK; 5083 } 5084 #define A6XX_PC_PRIMITIVE_CNTL_5_LINELENGTHEN 0x00008000 5085 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK 0x00030000 5086 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT 16 5087 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val) 5088 { 5089 return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK; 5090 } 5091 #define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK 0x00040000 5092 #define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT 18 5093 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_UNK18(uint32_t val) 5094 { 5095 return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK; 5096 } 5097 5098 #define REG_A6XX_PC_PRIMITIVE_CNTL_6 0x00009b06 5099 #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK 0x000007ff 5100 #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT 0 5101 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(uint32_t val) 5102 { 5103 return ((val) << A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK; 5104 } 5105 5106 #define REG_A6XX_PC_MULTIVIEW_CNTL 0x00009b07 5107 #define A6XX_PC_MULTIVIEW_CNTL_ENABLE 0x00000001 5108 #define A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002 5109 #define A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c 5110 #define A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT 2 5111 static inline uint32_t A6XX_PC_MULTIVIEW_CNTL_VIEWS(uint32_t val) 5112 { 5113 return ((val) << A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK; 5114 } 5115 5116 #define REG_A6XX_PC_MULTIVIEW_MASK 0x00009b08 5117 5118 #define REG_A6XX_PC_2D_EVENT_CMD 0x00009c00 5119 #define A6XX_PC_2D_EVENT_CMD_EVENT__MASK 0x0000007f 5120 #define A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT 0 5121 static inline uint32_t A6XX_PC_2D_EVENT_CMD_EVENT(enum vgt_event_type val) 5122 { 5123 return ((val) << A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_2D_EVENT_CMD_EVENT__MASK; 5124 } 5125 #define A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00 5126 #define A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT 8 5127 static inline uint32_t A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val) 5128 { 5129 return ((val) << A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK; 5130 } 5131 5132 #define REG_A6XX_PC_DBG_ECO_CNTL 0x00009e00 5133 5134 #define REG_A6XX_PC_ADDR_MODE_CNTL 0x00009e01 5135 5136 #define REG_A6XX_PC_DRAW_INDX_BASE 0x00009e04 5137 5138 #define REG_A6XX_PC_DRAW_FIRST_INDX 0x00009e06 5139 5140 #define REG_A6XX_PC_DRAW_MAX_INDICES 0x00009e07 5141 5142 #define REG_A6XX_PC_TESSFACTOR_ADDR 0x00009e08 5143 #define A6XX_PC_TESSFACTOR_ADDR__MASK 0xffffffff 5144 #define A6XX_PC_TESSFACTOR_ADDR__SHIFT 0 5145 static inline uint32_t A6XX_PC_TESSFACTOR_ADDR(uint32_t val) 5146 { 5147 return ((val) << A6XX_PC_TESSFACTOR_ADDR__SHIFT) & A6XX_PC_TESSFACTOR_ADDR__MASK; 5148 } 5149 5150 #define REG_A6XX_PC_DRAW_INITIATOR 0x00009e0b 5151 #define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f 5152 #define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 5153 static inline uint32_t A6XX_PC_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) 5154 { 5155 return ((val) << A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK; 5156 } 5157 #define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 5158 #define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 5159 static inline uint32_t A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) 5160 { 5161 return ((val) << A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK; 5162 } 5163 #define A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK 0x00000300 5164 #define A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT 8 5165 static inline uint32_t A6XX_PC_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) 5166 { 5167 return ((val) << A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT) & A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK; 5168 } 5169 #define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000c00 5170 #define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT 10 5171 static inline uint32_t A6XX_PC_DRAW_INITIATOR_INDEX_SIZE(enum a4xx_index_size val) 5172 { 5173 return ((val) << A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK; 5174 } 5175 #define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK 0x00003000 5176 #define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT 12 5177 static inline uint32_t A6XX_PC_DRAW_INITIATOR_PATCH_TYPE(enum a6xx_patch_type val) 5178 { 5179 return ((val) << A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK; 5180 } 5181 #define A6XX_PC_DRAW_INITIATOR_GS_ENABLE 0x00010000 5182 #define A6XX_PC_DRAW_INITIATOR_TESS_ENABLE 0x00020000 5183 5184 #define REG_A6XX_PC_DRAW_NUM_INSTANCES 0x00009e0c 5185 5186 #define REG_A6XX_PC_DRAW_NUM_INDICES 0x00009e0d 5187 5188 #define REG_A6XX_PC_VSTREAM_CONTROL 0x00009e11 5189 #define A6XX_PC_VSTREAM_CONTROL_UNK0__MASK 0x0000ffff 5190 #define A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT 0 5191 static inline uint32_t A6XX_PC_VSTREAM_CONTROL_UNK0(uint32_t val) 5192 { 5193 return ((val) << A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT) & A6XX_PC_VSTREAM_CONTROL_UNK0__MASK; 5194 } 5195 #define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK 0x003f0000 5196 #define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT 16 5197 static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_SIZE(uint32_t val) 5198 { 5199 return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK; 5200 } 5201 #define A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK 0x07c00000 5202 #define A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT 22 5203 static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_N(uint32_t val) 5204 { 5205 return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK; 5206 } 5207 5208 #define REG_A6XX_PC_BIN_PRIM_STRM 0x00009e12 5209 #define A6XX_PC_BIN_PRIM_STRM__MASK 0xffffffff 5210 #define A6XX_PC_BIN_PRIM_STRM__SHIFT 0 5211 static inline uint32_t A6XX_PC_BIN_PRIM_STRM(uint32_t val) 5212 { 5213 return ((val) << A6XX_PC_BIN_PRIM_STRM__SHIFT) & A6XX_PC_BIN_PRIM_STRM__MASK; 5214 } 5215 5216 #define REG_A6XX_PC_BIN_DRAW_STRM 0x00009e14 5217 #define A6XX_PC_BIN_DRAW_STRM__MASK 0xffffffff 5218 #define A6XX_PC_BIN_DRAW_STRM__SHIFT 0 5219 static inline uint32_t A6XX_PC_BIN_DRAW_STRM(uint32_t val) 5220 { 5221 return ((val) << A6XX_PC_BIN_DRAW_STRM__SHIFT) & A6XX_PC_BIN_DRAW_STRM__MASK; 5222 } 5223 5224 #define REG_A6XX_PC_VISIBILITY_OVERRIDE 0x00009e1c 5225 #define A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE 0x00000001 5226 5227 static inline uint32_t REG_A6XX_PC_PERFCTR_PC_SEL(uint32_t i0) { return 0x00009e34 + 0x1*i0; } 5228 5229 static inline uint32_t REG_A7XX_PC_PERFCTR_PC_SEL(uint32_t i0) { return 0x00009e42 + 0x1*i0; } 5230 5231 #define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72 5232 5233 #define REG_A6XX_VFD_CONTROL_0 0x0000a000 5234 #define A6XX_VFD_CONTROL_0_FETCH_CNT__MASK 0x0000003f 5235 #define A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT 0 5236 static inline uint32_t A6XX_VFD_CONTROL_0_FETCH_CNT(uint32_t val) 5237 { 5238 return ((val) << A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT) & A6XX_VFD_CONTROL_0_FETCH_CNT__MASK; 5239 } 5240 #define A6XX_VFD_CONTROL_0_DECODE_CNT__MASK 0x00003f00 5241 #define A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT 8 5242 static inline uint32_t A6XX_VFD_CONTROL_0_DECODE_CNT(uint32_t val) 5243 { 5244 return ((val) << A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT) & A6XX_VFD_CONTROL_0_DECODE_CNT__MASK; 5245 } 5246 5247 #define REG_A6XX_VFD_CONTROL_1 0x0000a001 5248 #define A6XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff 5249 #define A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0 5250 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 5251 { 5252 return ((val) << A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VTX__MASK; 5253 } 5254 #define A6XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00 5255 #define A6XX_VFD_CONTROL_1_REGID4INST__SHIFT 8 5256 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 5257 { 5258 return ((val) << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK; 5259 } 5260 #define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000 5261 #define A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16 5262 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val) 5263 { 5264 return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK; 5265 } 5266 #define A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK 0xff000000 5267 #define A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT 24 5268 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VIEWID(uint32_t val) 5269 { 5270 return ((val) << A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK; 5271 } 5272 5273 #define REG_A6XX_VFD_CONTROL_2 0x0000a002 5274 #define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK 0x000000ff 5275 #define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT 0 5276 static inline uint32_t A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID(uint32_t val) 5277 { 5278 return ((val) << A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK; 5279 } 5280 #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK 0x0000ff00 5281 #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT 8 5282 static inline uint32_t A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val) 5283 { 5284 return ((val) << A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK; 5285 } 5286 5287 #define REG_A6XX_VFD_CONTROL_3 0x0000a003 5288 #define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK 0x000000ff 5289 #define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT 0 5290 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPRIMID(uint32_t val) 5291 { 5292 return ((val) << A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK; 5293 } 5294 #define A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK 0x0000ff00 5295 #define A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT 8 5296 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID(uint32_t val) 5297 { 5298 return ((val) << A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK; 5299 } 5300 #define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000 5301 #define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16 5302 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) 5303 { 5304 return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSX__MASK; 5305 } 5306 #define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000 5307 #define A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24 5308 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) 5309 { 5310 return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK; 5311 } 5312 5313 #define REG_A6XX_VFD_CONTROL_4 0x0000a004 5314 #define A6XX_VFD_CONTROL_4_UNK0__MASK 0x000000ff 5315 #define A6XX_VFD_CONTROL_4_UNK0__SHIFT 0 5316 static inline uint32_t A6XX_VFD_CONTROL_4_UNK0(uint32_t val) 5317 { 5318 return ((val) << A6XX_VFD_CONTROL_4_UNK0__SHIFT) & A6XX_VFD_CONTROL_4_UNK0__MASK; 5319 } 5320 5321 #define REG_A6XX_VFD_CONTROL_5 0x0000a005 5322 #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK 0x000000ff 5323 #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT 0 5324 static inline uint32_t A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val) 5325 { 5326 return ((val) << A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT) & A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK; 5327 } 5328 #define A6XX_VFD_CONTROL_5_UNK8__MASK 0x0000ff00 5329 #define A6XX_VFD_CONTROL_5_UNK8__SHIFT 8 5330 static inline uint32_t A6XX_VFD_CONTROL_5_UNK8(uint32_t val) 5331 { 5332 return ((val) << A6XX_VFD_CONTROL_5_UNK8__SHIFT) & A6XX_VFD_CONTROL_5_UNK8__MASK; 5333 } 5334 5335 #define REG_A6XX_VFD_CONTROL_6 0x0000a006 5336 #define A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU 0x00000001 5337 5338 #define REG_A6XX_VFD_MODE_CNTL 0x0000a007 5339 #define A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK 0x00000007 5340 #define A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT 0 5341 static inline uint32_t A6XX_VFD_MODE_CNTL_RENDER_MODE(enum a6xx_render_mode val) 5342 { 5343 return ((val) << A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT) & A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK; 5344 } 5345 5346 #define REG_A6XX_VFD_MULTIVIEW_CNTL 0x0000a008 5347 #define A6XX_VFD_MULTIVIEW_CNTL_ENABLE 0x00000001 5348 #define A6XX_VFD_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002 5349 #define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c 5350 #define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT 2 5351 static inline uint32_t A6XX_VFD_MULTIVIEW_CNTL_VIEWS(uint32_t val) 5352 { 5353 return ((val) << A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK; 5354 } 5355 5356 #define REG_A6XX_VFD_ADD_OFFSET 0x0000a009 5357 #define A6XX_VFD_ADD_OFFSET_VERTEX 0x00000001 5358 #define A6XX_VFD_ADD_OFFSET_INSTANCE 0x00000002 5359 5360 #define REG_A6XX_VFD_INDEX_OFFSET 0x0000a00e 5361 5362 #define REG_A6XX_VFD_INSTANCE_START_OFFSET 0x0000a00f 5363 5364 static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; } 5365 5366 static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; } 5367 #define A6XX_VFD_FETCH_BASE__MASK 0xffffffff 5368 #define A6XX_VFD_FETCH_BASE__SHIFT 0 5369 static inline uint32_t A6XX_VFD_FETCH_BASE(uint32_t val) 5370 { 5371 return ((val) << A6XX_VFD_FETCH_BASE__SHIFT) & A6XX_VFD_FETCH_BASE__MASK; 5372 } 5373 5374 static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; } 5375 5376 static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; } 5377 5378 static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; } 5379 5380 static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; } 5381 #define A6XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f 5382 #define A6XX_VFD_DECODE_INSTR_IDX__SHIFT 0 5383 static inline uint32_t A6XX_VFD_DECODE_INSTR_IDX(uint32_t val) 5384 { 5385 return ((val) << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK; 5386 } 5387 #define A6XX_VFD_DECODE_INSTR_OFFSET__MASK 0x0001ffe0 5388 #define A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT 5 5389 static inline uint32_t A6XX_VFD_DECODE_INSTR_OFFSET(uint32_t val) 5390 { 5391 return ((val) << A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT) & A6XX_VFD_DECODE_INSTR_OFFSET__MASK; 5392 } 5393 #define A6XX_VFD_DECODE_INSTR_INSTANCED 0x00020000 5394 #define A6XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000 5395 #define A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20 5396 static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_format val) 5397 { 5398 return ((val) << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK; 5399 } 5400 #define A6XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000 5401 #define A6XX_VFD_DECODE_INSTR_SWAP__SHIFT 28 5402 static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 5403 { 5404 return ((val) << A6XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A6XX_VFD_DECODE_INSTR_SWAP__MASK; 5405 } 5406 #define A6XX_VFD_DECODE_INSTR_UNK30 0x40000000 5407 #define A6XX_VFD_DECODE_INSTR_FLOAT 0x80000000 5408 5409 static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; } 5410 5411 static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } 5412 5413 static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } 5414 #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f 5415 #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0 5416 static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val) 5417 { 5418 return ((val) << A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK; 5419 } 5420 #define A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0 5421 #define A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4 5422 static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) 5423 { 5424 return ((val) << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK; 5425 } 5426 5427 #define REG_A6XX_VFD_POWER_CNTL 0x0000a0f8 5428 5429 #define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601 5430 5431 static inline uint32_t REG_A6XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) { return 0x0000a610 + 0x1*i0; } 5432 5433 static inline uint32_t REG_A7XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) { return 0x0000a610 + 0x1*i0; } 5434 5435 #define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800 5436 #define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x00100000 5437 #define A6XX_SP_VS_CTRL_REG0_EARLYPREAMBLE 0x00200000 5438 #define A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 5439 #define A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 5440 static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 5441 { 5442 return ((val) << A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK; 5443 } 5444 #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 5445 #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 5446 static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 5447 { 5448 return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 5449 } 5450 #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 5451 #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 5452 static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 5453 { 5454 return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 5455 } 5456 #define A6XX_SP_VS_CTRL_REG0_UNK13 0x00002000 5457 #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 5458 #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14 5459 static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val) 5460 { 5461 return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK; 5462 } 5463 5464 #define REG_A6XX_SP_VS_BRANCH_COND 0x0000a801 5465 5466 #define REG_A6XX_SP_VS_PRIMITIVE_CNTL 0x0000a802 5467 #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f 5468 #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT 0 5469 static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_OUT(uint32_t val) 5470 { 5471 return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK; 5472 } 5473 #define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0 5474 #define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6 5475 static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) 5476 { 5477 return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; 5478 } 5479 5480 static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; } 5481 5482 static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; } 5483 #define A6XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff 5484 #define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 5485 static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 5486 { 5487 return ((val) << A6XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_A_REGID__MASK; 5488 } 5489 #define A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00 5490 #define A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8 5491 static inline uint32_t A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 5492 { 5493 return ((val) << A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 5494 } 5495 #define A6XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000 5496 #define A6XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 5497 static inline uint32_t A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 5498 { 5499 return ((val) << A6XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_B_REGID__MASK; 5500 } 5501 #define A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000 5502 #define A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24 5503 static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 5504 { 5505 return ((val) << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 5506 } 5507 5508 static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; } 5509 5510 static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; } 5511 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 5512 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 5513 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 5514 { 5515 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 5516 } 5517 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 5518 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 5519 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 5520 { 5521 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 5522 } 5523 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 5524 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 5525 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 5526 { 5527 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 5528 } 5529 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 5530 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 5531 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 5532 { 5533 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 5534 } 5535 5536 #define REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET 0x0000a81b 5537 5538 #define REG_A6XX_SP_VS_OBJ_START 0x0000a81c 5539 #define A6XX_SP_VS_OBJ_START__MASK 0xffffffff 5540 #define A6XX_SP_VS_OBJ_START__SHIFT 0 5541 static inline uint32_t A6XX_SP_VS_OBJ_START(uint32_t val) 5542 { 5543 return ((val) << A6XX_SP_VS_OBJ_START__SHIFT) & A6XX_SP_VS_OBJ_START__MASK; 5544 } 5545 5546 #define REG_A6XX_SP_VS_PVT_MEM_PARAM 0x0000a81e 5547 #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 5548 #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 5549 static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 5550 { 5551 return ((val >> 9) << A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 5552 } 5553 #define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 5554 #define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 5555 static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 5556 { 5557 return ((val) << A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 5558 } 5559 5560 #define REG_A6XX_SP_VS_PVT_MEM_ADDR 0x0000a81f 5561 #define A6XX_SP_VS_PVT_MEM_ADDR__MASK 0xffffffff 5562 #define A6XX_SP_VS_PVT_MEM_ADDR__SHIFT 0 5563 static inline uint32_t A6XX_SP_VS_PVT_MEM_ADDR(uint32_t val) 5564 { 5565 return ((val) << A6XX_SP_VS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_VS_PVT_MEM_ADDR__MASK; 5566 } 5567 5568 #define REG_A6XX_SP_VS_PVT_MEM_SIZE 0x0000a821 5569 #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 5570 #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 5571 static inline uint32_t A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 5572 { 5573 return ((val >> 12) << A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 5574 } 5575 #define A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 5576 5577 #define REG_A6XX_SP_VS_TEX_COUNT 0x0000a822 5578 5579 #define REG_A6XX_SP_VS_CONFIG 0x0000a823 5580 #define A6XX_SP_VS_CONFIG_BINDLESS_TEX 0x00000001 5581 #define A6XX_SP_VS_CONFIG_BINDLESS_SAMP 0x00000002 5582 #define A6XX_SP_VS_CONFIG_BINDLESS_IBO 0x00000004 5583 #define A6XX_SP_VS_CONFIG_BINDLESS_UBO 0x00000008 5584 #define A6XX_SP_VS_CONFIG_ENABLED 0x00000100 5585 #define A6XX_SP_VS_CONFIG_NTEX__MASK 0x0001fe00 5586 #define A6XX_SP_VS_CONFIG_NTEX__SHIFT 9 5587 static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val) 5588 { 5589 return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK; 5590 } 5591 #define A6XX_SP_VS_CONFIG_NSAMP__MASK 0x003e0000 5592 #define A6XX_SP_VS_CONFIG_NSAMP__SHIFT 17 5593 static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val) 5594 { 5595 return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK; 5596 } 5597 #define A6XX_SP_VS_CONFIG_NIBO__MASK 0x1fc00000 5598 #define A6XX_SP_VS_CONFIG_NIBO__SHIFT 22 5599 static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val) 5600 { 5601 return ((val) << A6XX_SP_VS_CONFIG_NIBO__SHIFT) & A6XX_SP_VS_CONFIG_NIBO__MASK; 5602 } 5603 5604 #define REG_A6XX_SP_VS_INSTRLEN 0x0000a824 5605 5606 #define REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET 0x0000a825 5607 #define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 5608 #define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 5609 static inline uint32_t A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 5610 { 5611 return ((val >> 11) << A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 5612 } 5613 5614 #define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830 5615 #define A6XX_SP_HS_CTRL_REG0_EARLYPREAMBLE 0x00100000 5616 #define A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK 0x00000001 5617 #define A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT 0 5618 static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 5619 { 5620 return ((val) << A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK; 5621 } 5622 #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 5623 #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 5624 static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 5625 { 5626 return ((val) << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 5627 } 5628 #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 5629 #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 5630 static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 5631 { 5632 return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 5633 } 5634 #define A6XX_SP_HS_CTRL_REG0_UNK13 0x00002000 5635 #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 5636 #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 14 5637 static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val) 5638 { 5639 return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK; 5640 } 5641 5642 #define REG_A6XX_SP_HS_WAVE_INPUT_SIZE 0x0000a831 5643 5644 #define REG_A6XX_SP_HS_BRANCH_COND 0x0000a832 5645 5646 #define REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET 0x0000a833 5647 5648 #define REG_A6XX_SP_HS_OBJ_START 0x0000a834 5649 #define A6XX_SP_HS_OBJ_START__MASK 0xffffffff 5650 #define A6XX_SP_HS_OBJ_START__SHIFT 0 5651 static inline uint32_t A6XX_SP_HS_OBJ_START(uint32_t val) 5652 { 5653 return ((val) << A6XX_SP_HS_OBJ_START__SHIFT) & A6XX_SP_HS_OBJ_START__MASK; 5654 } 5655 5656 #define REG_A6XX_SP_HS_PVT_MEM_PARAM 0x0000a836 5657 #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 5658 #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 5659 static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 5660 { 5661 return ((val >> 9) << A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 5662 } 5663 #define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 5664 #define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 5665 static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 5666 { 5667 return ((val) << A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 5668 } 5669 5670 #define REG_A6XX_SP_HS_PVT_MEM_ADDR 0x0000a837 5671 #define A6XX_SP_HS_PVT_MEM_ADDR__MASK 0xffffffff 5672 #define A6XX_SP_HS_PVT_MEM_ADDR__SHIFT 0 5673 static inline uint32_t A6XX_SP_HS_PVT_MEM_ADDR(uint32_t val) 5674 { 5675 return ((val) << A6XX_SP_HS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_HS_PVT_MEM_ADDR__MASK; 5676 } 5677 5678 #define REG_A6XX_SP_HS_PVT_MEM_SIZE 0x0000a839 5679 #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 5680 #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 5681 static inline uint32_t A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 5682 { 5683 return ((val >> 12) << A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 5684 } 5685 #define A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 5686 5687 #define REG_A6XX_SP_HS_TEX_COUNT 0x0000a83a 5688 5689 #define REG_A6XX_SP_HS_CONFIG 0x0000a83b 5690 #define A6XX_SP_HS_CONFIG_BINDLESS_TEX 0x00000001 5691 #define A6XX_SP_HS_CONFIG_BINDLESS_SAMP 0x00000002 5692 #define A6XX_SP_HS_CONFIG_BINDLESS_IBO 0x00000004 5693 #define A6XX_SP_HS_CONFIG_BINDLESS_UBO 0x00000008 5694 #define A6XX_SP_HS_CONFIG_ENABLED 0x00000100 5695 #define A6XX_SP_HS_CONFIG_NTEX__MASK 0x0001fe00 5696 #define A6XX_SP_HS_CONFIG_NTEX__SHIFT 9 5697 static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val) 5698 { 5699 return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK; 5700 } 5701 #define A6XX_SP_HS_CONFIG_NSAMP__MASK 0x003e0000 5702 #define A6XX_SP_HS_CONFIG_NSAMP__SHIFT 17 5703 static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val) 5704 { 5705 return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK; 5706 } 5707 #define A6XX_SP_HS_CONFIG_NIBO__MASK 0x1fc00000 5708 #define A6XX_SP_HS_CONFIG_NIBO__SHIFT 22 5709 static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val) 5710 { 5711 return ((val) << A6XX_SP_HS_CONFIG_NIBO__SHIFT) & A6XX_SP_HS_CONFIG_NIBO__MASK; 5712 } 5713 5714 #define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c 5715 5716 #define REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET 0x0000a83d 5717 #define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 5718 #define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 5719 static inline uint32_t A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 5720 { 5721 return ((val >> 11) << A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 5722 } 5723 5724 #define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840 5725 #define A6XX_SP_DS_CTRL_REG0_EARLYPREAMBLE 0x00100000 5726 #define A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK 0x00000001 5727 #define A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT 0 5728 static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 5729 { 5730 return ((val) << A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK; 5731 } 5732 #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 5733 #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 5734 static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 5735 { 5736 return ((val) << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 5737 } 5738 #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 5739 #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 5740 static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 5741 { 5742 return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 5743 } 5744 #define A6XX_SP_DS_CTRL_REG0_UNK13 0x00002000 5745 #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 5746 #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 14 5747 static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val) 5748 { 5749 return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK; 5750 } 5751 5752 #define REG_A6XX_SP_DS_BRANCH_COND 0x0000a841 5753 5754 #define REG_A6XX_SP_DS_PRIMITIVE_CNTL 0x0000a842 5755 #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f 5756 #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT 0 5757 static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_OUT(uint32_t val) 5758 { 5759 return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK; 5760 } 5761 #define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0 5762 #define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6 5763 static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) 5764 { 5765 return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; 5766 } 5767 5768 static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; } 5769 5770 static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000a843 + 0x1*i0; } 5771 #define A6XX_SP_DS_OUT_REG_A_REGID__MASK 0x000000ff 5772 #define A6XX_SP_DS_OUT_REG_A_REGID__SHIFT 0 5773 static inline uint32_t A6XX_SP_DS_OUT_REG_A_REGID(uint32_t val) 5774 { 5775 return ((val) << A6XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_A_REGID__MASK; 5776 } 5777 #define A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00000f00 5778 #define A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 8 5779 static inline uint32_t A6XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val) 5780 { 5781 return ((val) << A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK; 5782 } 5783 #define A6XX_SP_DS_OUT_REG_B_REGID__MASK 0x00ff0000 5784 #define A6XX_SP_DS_OUT_REG_B_REGID__SHIFT 16 5785 static inline uint32_t A6XX_SP_DS_OUT_REG_B_REGID(uint32_t val) 5786 { 5787 return ((val) << A6XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_B_REGID__MASK; 5788 } 5789 #define A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x0f000000 5790 #define A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 24 5791 static inline uint32_t A6XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val) 5792 { 5793 return ((val) << A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK; 5794 } 5795 5796 static inline uint32_t REG_A6XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000a853 + 0x1*i0; } 5797 5798 static inline uint32_t REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000a853 + 0x1*i0; } 5799 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 5800 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0 5801 static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val) 5802 { 5803 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK; 5804 } 5805 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 5806 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8 5807 static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val) 5808 { 5809 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK; 5810 } 5811 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 5812 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16 5813 static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val) 5814 { 5815 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK; 5816 } 5817 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 5818 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24 5819 static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) 5820 { 5821 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK; 5822 } 5823 5824 #define REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET 0x0000a85b 5825 5826 #define REG_A6XX_SP_DS_OBJ_START 0x0000a85c 5827 #define A6XX_SP_DS_OBJ_START__MASK 0xffffffff 5828 #define A6XX_SP_DS_OBJ_START__SHIFT 0 5829 static inline uint32_t A6XX_SP_DS_OBJ_START(uint32_t val) 5830 { 5831 return ((val) << A6XX_SP_DS_OBJ_START__SHIFT) & A6XX_SP_DS_OBJ_START__MASK; 5832 } 5833 5834 #define REG_A6XX_SP_DS_PVT_MEM_PARAM 0x0000a85e 5835 #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 5836 #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 5837 static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 5838 { 5839 return ((val >> 9) << A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 5840 } 5841 #define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 5842 #define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 5843 static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 5844 { 5845 return ((val) << A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 5846 } 5847 5848 #define REG_A6XX_SP_DS_PVT_MEM_ADDR 0x0000a85f 5849 #define A6XX_SP_DS_PVT_MEM_ADDR__MASK 0xffffffff 5850 #define A6XX_SP_DS_PVT_MEM_ADDR__SHIFT 0 5851 static inline uint32_t A6XX_SP_DS_PVT_MEM_ADDR(uint32_t val) 5852 { 5853 return ((val) << A6XX_SP_DS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_DS_PVT_MEM_ADDR__MASK; 5854 } 5855 5856 #define REG_A6XX_SP_DS_PVT_MEM_SIZE 0x0000a861 5857 #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 5858 #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 5859 static inline uint32_t A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 5860 { 5861 return ((val >> 12) << A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 5862 } 5863 #define A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 5864 5865 #define REG_A6XX_SP_DS_TEX_COUNT 0x0000a862 5866 5867 #define REG_A6XX_SP_DS_CONFIG 0x0000a863 5868 #define A6XX_SP_DS_CONFIG_BINDLESS_TEX 0x00000001 5869 #define A6XX_SP_DS_CONFIG_BINDLESS_SAMP 0x00000002 5870 #define A6XX_SP_DS_CONFIG_BINDLESS_IBO 0x00000004 5871 #define A6XX_SP_DS_CONFIG_BINDLESS_UBO 0x00000008 5872 #define A6XX_SP_DS_CONFIG_ENABLED 0x00000100 5873 #define A6XX_SP_DS_CONFIG_NTEX__MASK 0x0001fe00 5874 #define A6XX_SP_DS_CONFIG_NTEX__SHIFT 9 5875 static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val) 5876 { 5877 return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK; 5878 } 5879 #define A6XX_SP_DS_CONFIG_NSAMP__MASK 0x003e0000 5880 #define A6XX_SP_DS_CONFIG_NSAMP__SHIFT 17 5881 static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val) 5882 { 5883 return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK; 5884 } 5885 #define A6XX_SP_DS_CONFIG_NIBO__MASK 0x1fc00000 5886 #define A6XX_SP_DS_CONFIG_NIBO__SHIFT 22 5887 static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val) 5888 { 5889 return ((val) << A6XX_SP_DS_CONFIG_NIBO__SHIFT) & A6XX_SP_DS_CONFIG_NIBO__MASK; 5890 } 5891 5892 #define REG_A6XX_SP_DS_INSTRLEN 0x0000a864 5893 5894 #define REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET 0x0000a865 5895 #define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 5896 #define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 5897 static inline uint32_t A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 5898 { 5899 return ((val >> 11) << A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 5900 } 5901 5902 #define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870 5903 #define A6XX_SP_GS_CTRL_REG0_EARLYPREAMBLE 0x00100000 5904 #define A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK 0x00000001 5905 #define A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT 0 5906 static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 5907 { 5908 return ((val) << A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK; 5909 } 5910 #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 5911 #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 5912 static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 5913 { 5914 return ((val) << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 5915 } 5916 #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 5917 #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 5918 static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 5919 { 5920 return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 5921 } 5922 #define A6XX_SP_GS_CTRL_REG0_UNK13 0x00002000 5923 #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 5924 #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 14 5925 static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val) 5926 { 5927 return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK; 5928 } 5929 5930 #define REG_A6XX_SP_GS_PRIM_SIZE 0x0000a871 5931 5932 #define REG_A6XX_SP_GS_BRANCH_COND 0x0000a872 5933 5934 #define REG_A6XX_SP_GS_PRIMITIVE_CNTL 0x0000a873 5935 #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f 5936 #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT 0 5937 static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_OUT(uint32_t val) 5938 { 5939 return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK; 5940 } 5941 #define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0 5942 #define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6 5943 static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) 5944 { 5945 return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; 5946 } 5947 5948 static inline uint32_t REG_A6XX_SP_GS_OUT(uint32_t i0) { return 0x0000a874 + 0x1*i0; } 5949 5950 static inline uint32_t REG_A6XX_SP_GS_OUT_REG(uint32_t i0) { return 0x0000a874 + 0x1*i0; } 5951 #define A6XX_SP_GS_OUT_REG_A_REGID__MASK 0x000000ff 5952 #define A6XX_SP_GS_OUT_REG_A_REGID__SHIFT 0 5953 static inline uint32_t A6XX_SP_GS_OUT_REG_A_REGID(uint32_t val) 5954 { 5955 return ((val) << A6XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_A_REGID__MASK; 5956 } 5957 #define A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00000f00 5958 #define A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 8 5959 static inline uint32_t A6XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val) 5960 { 5961 return ((val) << A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK; 5962 } 5963 #define A6XX_SP_GS_OUT_REG_B_REGID__MASK 0x00ff0000 5964 #define A6XX_SP_GS_OUT_REG_B_REGID__SHIFT 16 5965 static inline uint32_t A6XX_SP_GS_OUT_REG_B_REGID(uint32_t val) 5966 { 5967 return ((val) << A6XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_B_REGID__MASK; 5968 } 5969 #define A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x0f000000 5970 #define A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 24 5971 static inline uint32_t A6XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val) 5972 { 5973 return ((val) << A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK; 5974 } 5975 5976 static inline uint32_t REG_A6XX_SP_GS_VPC_DST(uint32_t i0) { return 0x0000a884 + 0x1*i0; } 5977 5978 static inline uint32_t REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x0000a884 + 0x1*i0; } 5979 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 5980 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0 5981 static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val) 5982 { 5983 return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK; 5984 } 5985 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 5986 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8 5987 static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val) 5988 { 5989 return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK; 5990 } 5991 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 5992 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16 5993 static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val) 5994 { 5995 return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK; 5996 } 5997 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 5998 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24 5999 static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) 6000 { 6001 return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK; 6002 } 6003 6004 #define REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET 0x0000a88c 6005 6006 #define REG_A6XX_SP_GS_OBJ_START 0x0000a88d 6007 #define A6XX_SP_GS_OBJ_START__MASK 0xffffffff 6008 #define A6XX_SP_GS_OBJ_START__SHIFT 0 6009 static inline uint32_t A6XX_SP_GS_OBJ_START(uint32_t val) 6010 { 6011 return ((val) << A6XX_SP_GS_OBJ_START__SHIFT) & A6XX_SP_GS_OBJ_START__MASK; 6012 } 6013 6014 #define REG_A6XX_SP_GS_PVT_MEM_PARAM 0x0000a88f 6015 #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 6016 #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 6017 static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 6018 { 6019 return ((val >> 9) << A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 6020 } 6021 #define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 6022 #define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 6023 static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 6024 { 6025 return ((val) << A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 6026 } 6027 6028 #define REG_A6XX_SP_GS_PVT_MEM_ADDR 0x0000a890 6029 #define A6XX_SP_GS_PVT_MEM_ADDR__MASK 0xffffffff 6030 #define A6XX_SP_GS_PVT_MEM_ADDR__SHIFT 0 6031 static inline uint32_t A6XX_SP_GS_PVT_MEM_ADDR(uint32_t val) 6032 { 6033 return ((val) << A6XX_SP_GS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_GS_PVT_MEM_ADDR__MASK; 6034 } 6035 6036 #define REG_A6XX_SP_GS_PVT_MEM_SIZE 0x0000a892 6037 #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 6038 #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 6039 static inline uint32_t A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 6040 { 6041 return ((val >> 12) << A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 6042 } 6043 #define A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 6044 6045 #define REG_A6XX_SP_GS_TEX_COUNT 0x0000a893 6046 6047 #define REG_A6XX_SP_GS_CONFIG 0x0000a894 6048 #define A6XX_SP_GS_CONFIG_BINDLESS_TEX 0x00000001 6049 #define A6XX_SP_GS_CONFIG_BINDLESS_SAMP 0x00000002 6050 #define A6XX_SP_GS_CONFIG_BINDLESS_IBO 0x00000004 6051 #define A6XX_SP_GS_CONFIG_BINDLESS_UBO 0x00000008 6052 #define A6XX_SP_GS_CONFIG_ENABLED 0x00000100 6053 #define A6XX_SP_GS_CONFIG_NTEX__MASK 0x0001fe00 6054 #define A6XX_SP_GS_CONFIG_NTEX__SHIFT 9 6055 static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val) 6056 { 6057 return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK; 6058 } 6059 #define A6XX_SP_GS_CONFIG_NSAMP__MASK 0x003e0000 6060 #define A6XX_SP_GS_CONFIG_NSAMP__SHIFT 17 6061 static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val) 6062 { 6063 return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK; 6064 } 6065 #define A6XX_SP_GS_CONFIG_NIBO__MASK 0x1fc00000 6066 #define A6XX_SP_GS_CONFIG_NIBO__SHIFT 22 6067 static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val) 6068 { 6069 return ((val) << A6XX_SP_GS_CONFIG_NIBO__SHIFT) & A6XX_SP_GS_CONFIG_NIBO__MASK; 6070 } 6071 6072 #define REG_A6XX_SP_GS_INSTRLEN 0x0000a895 6073 6074 #define REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET 0x0000a896 6075 #define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 6076 #define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 6077 static inline uint32_t A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 6078 { 6079 return ((val >> 11) << A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 6080 } 6081 6082 #define REG_A6XX_SP_VS_TEX_SAMP 0x0000a8a0 6083 #define A6XX_SP_VS_TEX_SAMP__MASK 0xffffffff 6084 #define A6XX_SP_VS_TEX_SAMP__SHIFT 0 6085 static inline uint32_t A6XX_SP_VS_TEX_SAMP(uint32_t val) 6086 { 6087 return ((val) << A6XX_SP_VS_TEX_SAMP__SHIFT) & A6XX_SP_VS_TEX_SAMP__MASK; 6088 } 6089 6090 #define REG_A6XX_SP_HS_TEX_SAMP 0x0000a8a2 6091 #define A6XX_SP_HS_TEX_SAMP__MASK 0xffffffff 6092 #define A6XX_SP_HS_TEX_SAMP__SHIFT 0 6093 static inline uint32_t A6XX_SP_HS_TEX_SAMP(uint32_t val) 6094 { 6095 return ((val) << A6XX_SP_HS_TEX_SAMP__SHIFT) & A6XX_SP_HS_TEX_SAMP__MASK; 6096 } 6097 6098 #define REG_A6XX_SP_DS_TEX_SAMP 0x0000a8a4 6099 #define A6XX_SP_DS_TEX_SAMP__MASK 0xffffffff 6100 #define A6XX_SP_DS_TEX_SAMP__SHIFT 0 6101 static inline uint32_t A6XX_SP_DS_TEX_SAMP(uint32_t val) 6102 { 6103 return ((val) << A6XX_SP_DS_TEX_SAMP__SHIFT) & A6XX_SP_DS_TEX_SAMP__MASK; 6104 } 6105 6106 #define REG_A6XX_SP_GS_TEX_SAMP 0x0000a8a6 6107 #define A6XX_SP_GS_TEX_SAMP__MASK 0xffffffff 6108 #define A6XX_SP_GS_TEX_SAMP__SHIFT 0 6109 static inline uint32_t A6XX_SP_GS_TEX_SAMP(uint32_t val) 6110 { 6111 return ((val) << A6XX_SP_GS_TEX_SAMP__SHIFT) & A6XX_SP_GS_TEX_SAMP__MASK; 6112 } 6113 6114 #define REG_A6XX_SP_VS_TEX_CONST 0x0000a8a8 6115 #define A6XX_SP_VS_TEX_CONST__MASK 0xffffffff 6116 #define A6XX_SP_VS_TEX_CONST__SHIFT 0 6117 static inline uint32_t A6XX_SP_VS_TEX_CONST(uint32_t val) 6118 { 6119 return ((val) << A6XX_SP_VS_TEX_CONST__SHIFT) & A6XX_SP_VS_TEX_CONST__MASK; 6120 } 6121 6122 #define REG_A6XX_SP_HS_TEX_CONST 0x0000a8aa 6123 #define A6XX_SP_HS_TEX_CONST__MASK 0xffffffff 6124 #define A6XX_SP_HS_TEX_CONST__SHIFT 0 6125 static inline uint32_t A6XX_SP_HS_TEX_CONST(uint32_t val) 6126 { 6127 return ((val) << A6XX_SP_HS_TEX_CONST__SHIFT) & A6XX_SP_HS_TEX_CONST__MASK; 6128 } 6129 6130 #define REG_A6XX_SP_DS_TEX_CONST 0x0000a8ac 6131 #define A6XX_SP_DS_TEX_CONST__MASK 0xffffffff 6132 #define A6XX_SP_DS_TEX_CONST__SHIFT 0 6133 static inline uint32_t A6XX_SP_DS_TEX_CONST(uint32_t val) 6134 { 6135 return ((val) << A6XX_SP_DS_TEX_CONST__SHIFT) & A6XX_SP_DS_TEX_CONST__MASK; 6136 } 6137 6138 #define REG_A6XX_SP_GS_TEX_CONST 0x0000a8ae 6139 #define A6XX_SP_GS_TEX_CONST__MASK 0xffffffff 6140 #define A6XX_SP_GS_TEX_CONST__SHIFT 0 6141 static inline uint32_t A6XX_SP_GS_TEX_CONST(uint32_t val) 6142 { 6143 return ((val) << A6XX_SP_GS_TEX_CONST__SHIFT) & A6XX_SP_GS_TEX_CONST__MASK; 6144 } 6145 6146 #define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980 6147 #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 6148 #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 6149 static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) 6150 { 6151 return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 6152 } 6153 #define A6XX_SP_FS_CTRL_REG0_UNK21 0x00200000 6154 #define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000 6155 #define A6XX_SP_FS_CTRL_REG0_DIFF_FINE 0x00800000 6156 #define A6XX_SP_FS_CTRL_REG0_UNK24 0x01000000 6157 #define A6XX_SP_FS_CTRL_REG0_UNK25 0x02000000 6158 #define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000 6159 #define A6XX_SP_FS_CTRL_REG0_UNK27 0x08000000 6160 #define A6XX_SP_FS_CTRL_REG0_EARLYPREAMBLE 0x10000000 6161 #define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000 6162 #define A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 6163 #define A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 6164 static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 6165 { 6166 return ((val) << A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK; 6167 } 6168 #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 6169 #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 6170 static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 6171 { 6172 return ((val) << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 6173 } 6174 #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 6175 #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 6176 static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 6177 { 6178 return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 6179 } 6180 #define A6XX_SP_FS_CTRL_REG0_UNK13 0x00002000 6181 #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 6182 #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 14 6183 static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) 6184 { 6185 return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK; 6186 } 6187 6188 #define REG_A6XX_SP_FS_BRANCH_COND 0x0000a981 6189 6190 #define REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET 0x0000a982 6191 6192 #define REG_A6XX_SP_FS_OBJ_START 0x0000a983 6193 #define A6XX_SP_FS_OBJ_START__MASK 0xffffffff 6194 #define A6XX_SP_FS_OBJ_START__SHIFT 0 6195 static inline uint32_t A6XX_SP_FS_OBJ_START(uint32_t val) 6196 { 6197 return ((val) << A6XX_SP_FS_OBJ_START__SHIFT) & A6XX_SP_FS_OBJ_START__MASK; 6198 } 6199 6200 #define REG_A6XX_SP_FS_PVT_MEM_PARAM 0x0000a985 6201 #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 6202 #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 6203 static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 6204 { 6205 return ((val >> 9) << A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 6206 } 6207 #define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 6208 #define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 6209 static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 6210 { 6211 return ((val) << A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 6212 } 6213 6214 #define REG_A6XX_SP_FS_PVT_MEM_ADDR 0x0000a986 6215 #define A6XX_SP_FS_PVT_MEM_ADDR__MASK 0xffffffff 6216 #define A6XX_SP_FS_PVT_MEM_ADDR__SHIFT 0 6217 static inline uint32_t A6XX_SP_FS_PVT_MEM_ADDR(uint32_t val) 6218 { 6219 return ((val) << A6XX_SP_FS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_FS_PVT_MEM_ADDR__MASK; 6220 } 6221 6222 #define REG_A6XX_SP_FS_PVT_MEM_SIZE 0x0000a988 6223 #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 6224 #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 6225 static inline uint32_t A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 6226 { 6227 return ((val >> 12) << A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 6228 } 6229 #define A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 6230 6231 #define REG_A6XX_SP_BLEND_CNTL 0x0000a989 6232 #define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff 6233 #define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 6234 static inline uint32_t A6XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val) 6235 { 6236 return ((val) << A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK; 6237 } 6238 #define A6XX_SP_BLEND_CNTL_UNK8 0x00000100 6239 #define A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200 6240 #define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 6241 6242 #define REG_A6XX_SP_SRGB_CNTL 0x0000a98a 6243 #define A6XX_SP_SRGB_CNTL_SRGB_MRT0 0x00000001 6244 #define A6XX_SP_SRGB_CNTL_SRGB_MRT1 0x00000002 6245 #define A6XX_SP_SRGB_CNTL_SRGB_MRT2 0x00000004 6246 #define A6XX_SP_SRGB_CNTL_SRGB_MRT3 0x00000008 6247 #define A6XX_SP_SRGB_CNTL_SRGB_MRT4 0x00000010 6248 #define A6XX_SP_SRGB_CNTL_SRGB_MRT5 0x00000020 6249 #define A6XX_SP_SRGB_CNTL_SRGB_MRT6 0x00000040 6250 #define A6XX_SP_SRGB_CNTL_SRGB_MRT7 0x00000080 6251 6252 #define REG_A6XX_SP_FS_RENDER_COMPONENTS 0x0000a98b 6253 #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK 0x0000000f 6254 #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT 0 6255 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val) 6256 { 6257 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK; 6258 } 6259 #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK 0x000000f0 6260 #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT 4 6261 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val) 6262 { 6263 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK; 6264 } 6265 #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK 0x00000f00 6266 #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT 8 6267 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val) 6268 { 6269 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK; 6270 } 6271 #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK 0x0000f000 6272 #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT 12 6273 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val) 6274 { 6275 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK; 6276 } 6277 #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK 0x000f0000 6278 #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT 16 6279 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val) 6280 { 6281 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK; 6282 } 6283 #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK 0x00f00000 6284 #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT 20 6285 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val) 6286 { 6287 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK; 6288 } 6289 #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK 0x0f000000 6290 #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT 24 6291 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val) 6292 { 6293 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK; 6294 } 6295 #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK 0xf0000000 6296 #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT 28 6297 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val) 6298 { 6299 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK; 6300 } 6301 6302 #define REG_A6XX_SP_FS_OUTPUT_CNTL0 0x0000a98c 6303 #define A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001 6304 #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK 0x0000ff00 6305 #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT 8 6306 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val) 6307 { 6308 return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK; 6309 } 6310 #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK 0x00ff0000 6311 #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT 16 6312 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(uint32_t val) 6313 { 6314 return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK; 6315 } 6316 #define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK 0xff000000 6317 #define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT 24 6318 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(uint32_t val) 6319 { 6320 return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK; 6321 } 6322 6323 #define REG_A6XX_SP_FS_OUTPUT_CNTL1 0x0000a98d 6324 #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f 6325 #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT 0 6326 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val) 6327 { 6328 return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK; 6329 } 6330 6331 static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; } 6332 6333 static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; } 6334 #define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff 6335 #define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0 6336 static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) 6337 { 6338 return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK; 6339 } 6340 #define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100 6341 6342 static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; } 6343 6344 static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; } 6345 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff 6346 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0 6347 static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val) 6348 { 6349 return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK; 6350 } 6351 #define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100 6352 #define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200 6353 #define A6XX_SP_FS_MRT_REG_UNK10 0x00000400 6354 6355 #define REG_A6XX_SP_FS_PREFETCH_CNTL 0x0000a99e 6356 #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK 0x00000007 6357 #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT 0 6358 static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_COUNT(uint32_t val) 6359 { 6360 return ((val) << A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK; 6361 } 6362 #define A6XX_SP_FS_PREFETCH_CNTL_IJ_WRITE_DISABLE 0x00000008 6363 #define A6XX_SP_FS_PREFETCH_CNTL_UNK4 0x00000010 6364 #define A6XX_SP_FS_PREFETCH_CNTL_WRITE_COLOR_TO_OUTPUT 0x00000020 6365 #define A6XX_SP_FS_PREFETCH_CNTL_UNK6__MASK 0x00007fc0 6366 #define A6XX_SP_FS_PREFETCH_CNTL_UNK6__SHIFT 6 6367 static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK6(uint32_t val) 6368 { 6369 return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK6__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK6__MASK; 6370 } 6371 6372 static inline uint32_t REG_A6XX_SP_FS_PREFETCH(uint32_t i0) { return 0x0000a99f + 0x1*i0; } 6373 6374 static inline uint32_t REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; } 6375 #define A6XX_SP_FS_PREFETCH_CMD_SRC__MASK 0x0000007f 6376 #define A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT 0 6377 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val) 6378 { 6379 return ((val) << A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SRC__MASK; 6380 } 6381 #define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK 0x00000780 6382 #define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT 7 6383 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val) 6384 { 6385 return ((val) << A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK; 6386 } 6387 #define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK 0x0000f800 6388 #define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT 11 6389 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val) 6390 { 6391 return ((val) << A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK; 6392 } 6393 #define A6XX_SP_FS_PREFETCH_CMD_DST__MASK 0x003f0000 6394 #define A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT 16 6395 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_DST(uint32_t val) 6396 { 6397 return ((val) << A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_DST__MASK; 6398 } 6399 #define A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK 0x03c00000 6400 #define A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT 22 6401 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val) 6402 { 6403 return ((val) << A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK; 6404 } 6405 #define A6XX_SP_FS_PREFETCH_CMD_HALF 0x04000000 6406 #define A6XX_SP_FS_PREFETCH_CMD_UNK27 0x08000000 6407 #define A6XX_SP_FS_PREFETCH_CMD_BINDLESS 0x10000000 6408 #define A6XX_SP_FS_PREFETCH_CMD_CMD__MASK 0xe0000000 6409 #define A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT 29 6410 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_CMD(enum a6xx_tex_prefetch_cmd val) 6411 { 6412 return ((val) << A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_CMD__MASK; 6413 } 6414 6415 static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; } 6416 6417 static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; } 6418 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK 0x0000ffff 6419 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT 0 6420 static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val) 6421 { 6422 return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK; 6423 } 6424 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK 0xffff0000 6425 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT 16 6426 static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val) 6427 { 6428 return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK; 6429 } 6430 6431 #define REG_A6XX_SP_FS_TEX_COUNT 0x0000a9a7 6432 6433 #define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8 6434 6435 #define REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET 0x0000a9a9 6436 #define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 6437 #define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 6438 static inline uint32_t A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 6439 { 6440 return ((val >> 11) << A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 6441 } 6442 6443 #define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0 6444 #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000 6445 #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20 6446 static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) 6447 { 6448 return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK; 6449 } 6450 #define A6XX_SP_CS_CTRL_REG0_UNK21 0x00200000 6451 #define A6XX_SP_CS_CTRL_REG0_UNK22 0x00400000 6452 #define A6XX_SP_CS_CTRL_REG0_EARLYPREAMBLE 0x00800000 6453 #define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000 6454 #define A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK 0x00000001 6455 #define A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT 0 6456 static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 6457 { 6458 return ((val) << A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK; 6459 } 6460 #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 6461 #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 6462 static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 6463 { 6464 return ((val) << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 6465 } 6466 #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 6467 #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 6468 static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 6469 { 6470 return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 6471 } 6472 #define A6XX_SP_CS_CTRL_REG0_UNK13 0x00002000 6473 #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 6474 #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 14 6475 static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val) 6476 { 6477 return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK; 6478 } 6479 6480 #define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1 6481 #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK 0x0000001f 6482 #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT 0 6483 static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(uint32_t val) 6484 { 6485 return ((val) << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK; 6486 } 6487 #define A6XX_SP_CS_UNKNOWN_A9B1_UNK5 0x00000020 6488 #define A6XX_SP_CS_UNKNOWN_A9B1_UNK6 0x00000040 6489 6490 #define REG_A6XX_SP_CS_BRANCH_COND 0x0000a9b2 6491 6492 #define REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET 0x0000a9b3 6493 6494 #define REG_A6XX_SP_CS_OBJ_START 0x0000a9b4 6495 #define A6XX_SP_CS_OBJ_START__MASK 0xffffffff 6496 #define A6XX_SP_CS_OBJ_START__SHIFT 0 6497 static inline uint32_t A6XX_SP_CS_OBJ_START(uint32_t val) 6498 { 6499 return ((val) << A6XX_SP_CS_OBJ_START__SHIFT) & A6XX_SP_CS_OBJ_START__MASK; 6500 } 6501 6502 #define REG_A6XX_SP_CS_PVT_MEM_PARAM 0x0000a9b6 6503 #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 6504 #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 6505 static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 6506 { 6507 return ((val >> 9) << A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 6508 } 6509 #define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 6510 #define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 6511 static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 6512 { 6513 return ((val) << A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 6514 } 6515 6516 #define REG_A6XX_SP_CS_PVT_MEM_ADDR 0x0000a9b7 6517 #define A6XX_SP_CS_PVT_MEM_ADDR__MASK 0xffffffff 6518 #define A6XX_SP_CS_PVT_MEM_ADDR__SHIFT 0 6519 static inline uint32_t A6XX_SP_CS_PVT_MEM_ADDR(uint32_t val) 6520 { 6521 return ((val) << A6XX_SP_CS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_CS_PVT_MEM_ADDR__MASK; 6522 } 6523 6524 #define REG_A6XX_SP_CS_PVT_MEM_SIZE 0x0000a9b9 6525 #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 6526 #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 6527 static inline uint32_t A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 6528 { 6529 return ((val >> 12) << A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 6530 } 6531 #define A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 6532 6533 #define REG_A6XX_SP_CS_TEX_COUNT 0x0000a9ba 6534 6535 #define REG_A6XX_SP_CS_CONFIG 0x0000a9bb 6536 #define A6XX_SP_CS_CONFIG_BINDLESS_TEX 0x00000001 6537 #define A6XX_SP_CS_CONFIG_BINDLESS_SAMP 0x00000002 6538 #define A6XX_SP_CS_CONFIG_BINDLESS_IBO 0x00000004 6539 #define A6XX_SP_CS_CONFIG_BINDLESS_UBO 0x00000008 6540 #define A6XX_SP_CS_CONFIG_ENABLED 0x00000100 6541 #define A6XX_SP_CS_CONFIG_NTEX__MASK 0x0001fe00 6542 #define A6XX_SP_CS_CONFIG_NTEX__SHIFT 9 6543 static inline uint32_t A6XX_SP_CS_CONFIG_NTEX(uint32_t val) 6544 { 6545 return ((val) << A6XX_SP_CS_CONFIG_NTEX__SHIFT) & A6XX_SP_CS_CONFIG_NTEX__MASK; 6546 } 6547 #define A6XX_SP_CS_CONFIG_NSAMP__MASK 0x003e0000 6548 #define A6XX_SP_CS_CONFIG_NSAMP__SHIFT 17 6549 static inline uint32_t A6XX_SP_CS_CONFIG_NSAMP(uint32_t val) 6550 { 6551 return ((val) << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK; 6552 } 6553 #define A6XX_SP_CS_CONFIG_NIBO__MASK 0x1fc00000 6554 #define A6XX_SP_CS_CONFIG_NIBO__SHIFT 22 6555 static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val) 6556 { 6557 return ((val) << A6XX_SP_CS_CONFIG_NIBO__SHIFT) & A6XX_SP_CS_CONFIG_NIBO__MASK; 6558 } 6559 6560 #define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc 6561 6562 #define REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET 0x0000a9bd 6563 #define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 6564 #define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 6565 static inline uint32_t A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 6566 { 6567 return ((val >> 11) << A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 6568 } 6569 6570 #define REG_A6XX_SP_CS_CNTL_0 0x0000a9c2 6571 #define A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff 6572 #define A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT 0 6573 static inline uint32_t A6XX_SP_CS_CNTL_0_WGIDCONSTID(uint32_t val) 6574 { 6575 return ((val) << A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK; 6576 } 6577 #define A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK 0x0000ff00 6578 #define A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT 8 6579 static inline uint32_t A6XX_SP_CS_CNTL_0_WGSIZECONSTID(uint32_t val) 6580 { 6581 return ((val) << A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK; 6582 } 6583 #define A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK 0x00ff0000 6584 #define A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT 16 6585 static inline uint32_t A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val) 6586 { 6587 return ((val) << A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK; 6588 } 6589 #define A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000 6590 #define A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT 24 6591 static inline uint32_t A6XX_SP_CS_CNTL_0_LOCALIDREGID(uint32_t val) 6592 { 6593 return ((val) << A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK; 6594 } 6595 6596 #define REG_A6XX_SP_CS_CNTL_1 0x0000a9c3 6597 #define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff 6598 #define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0 6599 static inline uint32_t A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) 6600 { 6601 return ((val) << A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK; 6602 } 6603 #define A6XX_SP_CS_CNTL_1_SINGLE_SP_CORE 0x00000100 6604 #define A6XX_SP_CS_CNTL_1_THREADSIZE__MASK 0x00000200 6605 #define A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT 9 6606 static inline uint32_t A6XX_SP_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) 6607 { 6608 return ((val) << A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_SP_CS_CNTL_1_THREADSIZE__MASK; 6609 } 6610 #define A6XX_SP_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400 6611 6612 #define REG_A6XX_SP_FS_TEX_SAMP 0x0000a9e0 6613 #define A6XX_SP_FS_TEX_SAMP__MASK 0xffffffff 6614 #define A6XX_SP_FS_TEX_SAMP__SHIFT 0 6615 static inline uint32_t A6XX_SP_FS_TEX_SAMP(uint32_t val) 6616 { 6617 return ((val) << A6XX_SP_FS_TEX_SAMP__SHIFT) & A6XX_SP_FS_TEX_SAMP__MASK; 6618 } 6619 6620 #define REG_A6XX_SP_CS_TEX_SAMP 0x0000a9e2 6621 #define A6XX_SP_CS_TEX_SAMP__MASK 0xffffffff 6622 #define A6XX_SP_CS_TEX_SAMP__SHIFT 0 6623 static inline uint32_t A6XX_SP_CS_TEX_SAMP(uint32_t val) 6624 { 6625 return ((val) << A6XX_SP_CS_TEX_SAMP__SHIFT) & A6XX_SP_CS_TEX_SAMP__MASK; 6626 } 6627 6628 #define REG_A6XX_SP_FS_TEX_CONST 0x0000a9e4 6629 #define A6XX_SP_FS_TEX_CONST__MASK 0xffffffff 6630 #define A6XX_SP_FS_TEX_CONST__SHIFT 0 6631 static inline uint32_t A6XX_SP_FS_TEX_CONST(uint32_t val) 6632 { 6633 return ((val) << A6XX_SP_FS_TEX_CONST__SHIFT) & A6XX_SP_FS_TEX_CONST__MASK; 6634 } 6635 6636 #define REG_A6XX_SP_CS_TEX_CONST 0x0000a9e6 6637 #define A6XX_SP_CS_TEX_CONST__MASK 0xffffffff 6638 #define A6XX_SP_CS_TEX_CONST__SHIFT 0 6639 static inline uint32_t A6XX_SP_CS_TEX_CONST(uint32_t val) 6640 { 6641 return ((val) << A6XX_SP_CS_TEX_CONST__SHIFT) & A6XX_SP_CS_TEX_CONST__MASK; 6642 } 6643 6644 static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; } 6645 6646 static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; } 6647 #define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 6648 #define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0 6649 static inline uint32_t A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) 6650 { 6651 return ((val) << A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; 6652 } 6653 #define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffc 6654 #define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 6655 static inline uint32_t A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val) 6656 { 6657 return ((val >> 2) << A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; 6658 } 6659 6660 #define REG_A6XX_SP_CS_IBO 0x0000a9f2 6661 #define A6XX_SP_CS_IBO__MASK 0xffffffff 6662 #define A6XX_SP_CS_IBO__SHIFT 0 6663 static inline uint32_t A6XX_SP_CS_IBO(uint32_t val) 6664 { 6665 return ((val) << A6XX_SP_CS_IBO__SHIFT) & A6XX_SP_CS_IBO__MASK; 6666 } 6667 6668 #define REG_A6XX_SP_CS_IBO_COUNT 0x0000aa00 6669 6670 #define REG_A6XX_SP_MODE_CONTROL 0x0000ab00 6671 #define A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE 0x00000001 6672 #define A6XX_SP_MODE_CONTROL_ISAMMODE__MASK 0x00000006 6673 #define A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT 1 6674 static inline uint32_t A6XX_SP_MODE_CONTROL_ISAMMODE(enum a6xx_isam_mode val) 6675 { 6676 return ((val) << A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT) & A6XX_SP_MODE_CONTROL_ISAMMODE__MASK; 6677 } 6678 #define A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE 0x00000008 6679 6680 #define REG_A6XX_SP_FS_CONFIG 0x0000ab04 6681 #define A6XX_SP_FS_CONFIG_BINDLESS_TEX 0x00000001 6682 #define A6XX_SP_FS_CONFIG_BINDLESS_SAMP 0x00000002 6683 #define A6XX_SP_FS_CONFIG_BINDLESS_IBO 0x00000004 6684 #define A6XX_SP_FS_CONFIG_BINDLESS_UBO 0x00000008 6685 #define A6XX_SP_FS_CONFIG_ENABLED 0x00000100 6686 #define A6XX_SP_FS_CONFIG_NTEX__MASK 0x0001fe00 6687 #define A6XX_SP_FS_CONFIG_NTEX__SHIFT 9 6688 static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val) 6689 { 6690 return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK; 6691 } 6692 #define A6XX_SP_FS_CONFIG_NSAMP__MASK 0x003e0000 6693 #define A6XX_SP_FS_CONFIG_NSAMP__SHIFT 17 6694 static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val) 6695 { 6696 return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK; 6697 } 6698 #define A6XX_SP_FS_CONFIG_NIBO__MASK 0x1fc00000 6699 #define A6XX_SP_FS_CONFIG_NIBO__SHIFT 22 6700 static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val) 6701 { 6702 return ((val) << A6XX_SP_FS_CONFIG_NIBO__SHIFT) & A6XX_SP_FS_CONFIG_NIBO__MASK; 6703 } 6704 6705 #define REG_A6XX_SP_FS_INSTRLEN 0x0000ab05 6706 6707 static inline uint32_t REG_A6XX_SP_BINDLESS_BASE(uint32_t i0) { return 0x0000ab10 + 0x2*i0; } 6708 6709 static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; } 6710 #define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 6711 #define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0 6712 static inline uint32_t A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) 6713 { 6714 return ((val) << A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; 6715 } 6716 #define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffc 6717 #define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 6718 static inline uint32_t A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val) 6719 { 6720 return ((val >> 2) << A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; 6721 } 6722 6723 #define REG_A6XX_SP_IBO 0x0000ab1a 6724 #define A6XX_SP_IBO__MASK 0xffffffff 6725 #define A6XX_SP_IBO__SHIFT 0 6726 static inline uint32_t A6XX_SP_IBO(uint32_t val) 6727 { 6728 return ((val) << A6XX_SP_IBO__SHIFT) & A6XX_SP_IBO__MASK; 6729 } 6730 6731 #define REG_A6XX_SP_IBO_COUNT 0x0000ab20 6732 6733 #define REG_A6XX_SP_2D_DST_FORMAT 0x0000acc0 6734 #define A6XX_SP_2D_DST_FORMAT_NORM 0x00000001 6735 #define A6XX_SP_2D_DST_FORMAT_SINT 0x00000002 6736 #define A6XX_SP_2D_DST_FORMAT_UINT 0x00000004 6737 #define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK 0x000007f8 6738 #define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT 3 6739 static inline uint32_t A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val) 6740 { 6741 return ((val) << A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT) & A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK; 6742 } 6743 #define A6XX_SP_2D_DST_FORMAT_SRGB 0x00000800 6744 #define A6XX_SP_2D_DST_FORMAT_MASK__MASK 0x0000f000 6745 #define A6XX_SP_2D_DST_FORMAT_MASK__SHIFT 12 6746 static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val) 6747 { 6748 return ((val) << A6XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A6XX_SP_2D_DST_FORMAT_MASK__MASK; 6749 } 6750 6751 #define REG_A6XX_SP_DBG_ECO_CNTL 0x0000ae00 6752 6753 #define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01 6754 6755 #define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02 6756 6757 #define REG_A6XX_SP_CHICKEN_BITS 0x0000ae03 6758 6759 #define REG_A6XX_SP_FLOAT_CNTL 0x0000ae04 6760 #define A6XX_SP_FLOAT_CNTL_F16_NO_INF 0x00000008 6761 6762 #define REG_A6XX_SP_PERFCTR_ENABLE 0x0000ae0f 6763 #define A6XX_SP_PERFCTR_ENABLE_VS 0x00000001 6764 #define A6XX_SP_PERFCTR_ENABLE_HS 0x00000002 6765 #define A6XX_SP_PERFCTR_ENABLE_DS 0x00000004 6766 #define A6XX_SP_PERFCTR_ENABLE_GS 0x00000008 6767 #define A6XX_SP_PERFCTR_ENABLE_FS 0x00000010 6768 #define A6XX_SP_PERFCTR_ENABLE_CS 0x00000020 6769 6770 static inline uint32_t REG_A6XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae10 + 0x1*i0; } 6771 6772 static inline uint32_t REG_A7XX_SP_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000ae60 + 0x1*i0; } 6773 6774 #define REG_A7XX_SP_READ_SEL 0x0000ae6d 6775 6776 static inline uint32_t REG_A7XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae80 + 0x1*i0; } 6777 6778 #define REG_A6XX_SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE 0x0000be22 6779 6780 #define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR 0x0000b180 6781 #define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff 6782 #define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0 6783 static inline uint32_t A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(uint32_t val) 6784 { 6785 return ((val) << A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK; 6786 } 6787 6788 #define REG_A6XX_SP_UNKNOWN_B182 0x0000b182 6789 6790 #define REG_A6XX_SP_UNKNOWN_B183 0x0000b183 6791 6792 #define REG_A6XX_SP_UNKNOWN_B190 0x0000b190 6793 6794 #define REG_A6XX_SP_UNKNOWN_B191 0x0000b191 6795 6796 #define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300 6797 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 6798 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 6799 static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 6800 { 6801 return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK; 6802 } 6803 #define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK 0x0000000c 6804 #define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT 2 6805 static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_UNK2(uint32_t val) 6806 { 6807 return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK; 6808 } 6809 6810 #define REG_A6XX_SP_TP_DEST_MSAA_CNTL 0x0000b301 6811 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 6812 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 6813 static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 6814 { 6815 return ((val) << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK; 6816 } 6817 #define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 6818 6819 #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR 0x0000b302 6820 #define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff 6821 #define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0 6822 static inline uint32_t A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(uint32_t val) 6823 { 6824 return ((val) << A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK; 6825 } 6826 6827 #define REG_A6XX_SP_TP_SAMPLE_CONFIG 0x0000b304 6828 #define A6XX_SP_TP_SAMPLE_CONFIG_UNK0 0x00000001 6829 #define A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002 6830 6831 #define REG_A6XX_SP_TP_SAMPLE_LOCATION_0 0x0000b305 6832 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f 6833 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 6834 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) 6835 { 6836 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; 6837 } 6838 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 6839 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 6840 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) 6841 { 6842 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; 6843 } 6844 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 6845 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 6846 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) 6847 { 6848 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; 6849 } 6850 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 6851 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 6852 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) 6853 { 6854 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; 6855 } 6856 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 6857 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 6858 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) 6859 { 6860 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; 6861 } 6862 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 6863 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 6864 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) 6865 { 6866 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; 6867 } 6868 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 6869 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 6870 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) 6871 { 6872 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; 6873 } 6874 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 6875 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 6876 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) 6877 { 6878 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; 6879 } 6880 6881 #define REG_A6XX_SP_TP_SAMPLE_LOCATION_1 0x0000b306 6882 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f 6883 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 6884 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) 6885 { 6886 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; 6887 } 6888 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 6889 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 6890 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) 6891 { 6892 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; 6893 } 6894 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 6895 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 6896 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) 6897 { 6898 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; 6899 } 6900 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 6901 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 6902 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) 6903 { 6904 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; 6905 } 6906 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 6907 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 6908 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) 6909 { 6910 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; 6911 } 6912 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 6913 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 6914 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) 6915 { 6916 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; 6917 } 6918 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 6919 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 6920 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) 6921 { 6922 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; 6923 } 6924 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 6925 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 6926 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) 6927 { 6928 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; 6929 } 6930 6931 #define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307 6932 #define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00003fff 6933 #define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0 6934 static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val) 6935 { 6936 return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK; 6937 } 6938 #define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x3fff0000 6939 #define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16 6940 static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val) 6941 { 6942 return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK; 6943 } 6944 6945 #define REG_A6XX_SP_TP_MODE_CNTL 0x0000b309 6946 #define A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK 0x00000003 6947 #define A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT 0 6948 static inline uint32_t A6XX_SP_TP_MODE_CNTL_ISAMMODE(enum a6xx_isam_mode val) 6949 { 6950 return ((val) << A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT) & A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK; 6951 } 6952 #define A6XX_SP_TP_MODE_CNTL_UNK3__MASK 0x000000fc 6953 #define A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT 2 6954 static inline uint32_t A6XX_SP_TP_MODE_CNTL_UNK3(uint32_t val) 6955 { 6956 return ((val) << A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT) & A6XX_SP_TP_MODE_CNTL_UNK3__MASK; 6957 } 6958 6959 #define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0 6960 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff 6961 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 6962 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val) 6963 { 6964 return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK; 6965 } 6966 #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300 6967 #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT 8 6968 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val) 6969 { 6970 return ((val) << A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK; 6971 } 6972 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00 6973 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10 6974 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) 6975 { 6976 return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK; 6977 } 6978 #define A6XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000 6979 #define A6XX_SP_PS_2D_SRC_INFO_SRGB 0x00002000 6980 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK 0x0000c000 6981 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT 14 6982 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val) 6983 { 6984 return ((val) << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK; 6985 } 6986 #define A6XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000 6987 #define A6XX_SP_PS_2D_SRC_INFO_UNK17 0x00020000 6988 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE 0x00040000 6989 #define A6XX_SP_PS_2D_SRC_INFO_UNK19 0x00080000 6990 #define A6XX_SP_PS_2D_SRC_INFO_UNK20 0x00100000 6991 #define A6XX_SP_PS_2D_SRC_INFO_UNK21 0x00200000 6992 #define A6XX_SP_PS_2D_SRC_INFO_UNK22 0x00400000 6993 #define A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK 0x07800000 6994 #define A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT 23 6995 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val) 6996 { 6997 return ((val) << A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK; 6998 } 6999 #define A6XX_SP_PS_2D_SRC_INFO_UNK28 0x10000000 7000 7001 #define REG_A6XX_SP_PS_2D_SRC_SIZE 0x0000b4c1 7002 #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff 7003 #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT 0 7004 static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val) 7005 { 7006 return ((val) << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK; 7007 } 7008 #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK 0x3fff8000 7009 #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT 15 7010 static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val) 7011 { 7012 return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK; 7013 } 7014 7015 #define REG_A6XX_SP_PS_2D_SRC 0x0000b4c2 7016 #define A6XX_SP_PS_2D_SRC__MASK 0xffffffff 7017 #define A6XX_SP_PS_2D_SRC__SHIFT 0 7018 static inline uint32_t A6XX_SP_PS_2D_SRC(uint32_t val) 7019 { 7020 return ((val) << A6XX_SP_PS_2D_SRC__SHIFT) & A6XX_SP_PS_2D_SRC__MASK; 7021 } 7022 7023 #define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4 7024 #define A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK 0x000001ff 7025 #define A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT 0 7026 static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val) 7027 { 7028 return ((val) << A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK; 7029 } 7030 #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x00fffe00 7031 #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9 7032 static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val) 7033 { 7034 return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK; 7035 } 7036 7037 #define REG_A6XX_SP_PS_2D_SRC_PLANE1 0x0000b4c5 7038 #define A6XX_SP_PS_2D_SRC_PLANE1__MASK 0xffffffff 7039 #define A6XX_SP_PS_2D_SRC_PLANE1__SHIFT 0 7040 static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE1(uint32_t val) 7041 { 7042 return ((val) << A6XX_SP_PS_2D_SRC_PLANE1__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE1__MASK; 7043 } 7044 7045 #define REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH 0x0000b4c7 7046 #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK 0x00000fff 7047 #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT 0 7048 static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val) 7049 { 7050 return ((val >> 6) << A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK; 7051 } 7052 7053 #define REG_A6XX_SP_PS_2D_SRC_PLANE2 0x0000b4c8 7054 #define A6XX_SP_PS_2D_SRC_PLANE2__MASK 0xffffffff 7055 #define A6XX_SP_PS_2D_SRC_PLANE2__SHIFT 0 7056 static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE2(uint32_t val) 7057 { 7058 return ((val) << A6XX_SP_PS_2D_SRC_PLANE2__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE2__MASK; 7059 } 7060 7061 #define REG_A6XX_SP_PS_2D_SRC_FLAGS 0x0000b4ca 7062 #define A6XX_SP_PS_2D_SRC_FLAGS__MASK 0xffffffff 7063 #define A6XX_SP_PS_2D_SRC_FLAGS__SHIFT 0 7064 static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS(uint32_t val) 7065 { 7066 return ((val) << A6XX_SP_PS_2D_SRC_FLAGS__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS__MASK; 7067 } 7068 7069 #define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b4cc 7070 #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK 0x000000ff 7071 #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT 0 7072 static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val) 7073 { 7074 return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK; 7075 } 7076 7077 #define REG_A6XX_SP_PS_UNKNOWN_B4CD 0x0000b4cd 7078 7079 #define REG_A6XX_SP_PS_UNKNOWN_B4CE 0x0000b4ce 7080 7081 #define REG_A6XX_SP_PS_UNKNOWN_B4CF 0x0000b4cf 7082 7083 #define REG_A6XX_SP_PS_UNKNOWN_B4D0 0x0000b4d0 7084 7085 #define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1 7086 #define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00003fff 7087 #define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0 7088 static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val) 7089 { 7090 return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK; 7091 } 7092 #define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x3fff0000 7093 #define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16 7094 static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val) 7095 { 7096 return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK; 7097 } 7098 7099 #define REG_A6XX_TPL1_DBG_ECO_CNTL 0x0000b600 7100 7101 #define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601 7102 7103 #define REG_A6XX_TPL1_UNKNOWN_B602 0x0000b602 7104 7105 #define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604 7106 #define A6XX_TPL1_NC_MODE_CNTL_MODE 0x00000001 7107 #define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006 7108 #define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT 1 7109 static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT(uint32_t val) 7110 { 7111 return ((val) << A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK; 7112 } 7113 #define A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008 7114 #define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000010 7115 #define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT 4 7116 static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT(uint32_t val) 7117 { 7118 return ((val) << A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK; 7119 } 7120 #define A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK 0x000000c0 7121 #define A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT 6 7122 static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UNK6(uint32_t val) 7123 { 7124 return ((val) << A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK; 7125 } 7126 7127 #define REG_A6XX_TPL1_UNKNOWN_B605 0x0000b605 7128 7129 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608 7130 7131 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609 7132 7133 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a 7134 7135 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b 7136 7137 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c 7138 7139 static inline uint32_t REG_A6XX_TPL1_PERFCTR_TP_SEL(uint32_t i0) { return 0x0000b610 + 0x1*i0; } 7140 7141 #define REG_A6XX_HLSQ_VS_CNTL 0x0000b800 7142 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff 7143 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0 7144 static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val) 7145 { 7146 return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK; 7147 } 7148 #define A6XX_HLSQ_VS_CNTL_ENABLED 0x00000100 7149 7150 #define REG_A6XX_HLSQ_HS_CNTL 0x0000b801 7151 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff 7152 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0 7153 static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val) 7154 { 7155 return ((val >> 2) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK; 7156 } 7157 #define A6XX_HLSQ_HS_CNTL_ENABLED 0x00000100 7158 7159 #define REG_A6XX_HLSQ_DS_CNTL 0x0000b802 7160 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff 7161 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0 7162 static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val) 7163 { 7164 return ((val >> 2) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK; 7165 } 7166 #define A6XX_HLSQ_DS_CNTL_ENABLED 0x00000100 7167 7168 #define REG_A6XX_HLSQ_GS_CNTL 0x0000b803 7169 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff 7170 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0 7171 static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val) 7172 { 7173 return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK; 7174 } 7175 #define A6XX_HLSQ_GS_CNTL_ENABLED 0x00000100 7176 7177 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD 0x0000b820 7178 7179 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR 0x0000b821 7180 #define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK 0xffffffff 7181 #define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT 0 7182 static inline uint32_t A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR(uint32_t val) 7183 { 7184 return ((val) << A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK; 7185 } 7186 7187 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA 0x0000b823 7188 7189 #define REG_A6XX_HLSQ_FS_CNTL_0 0x0000b980 7190 #define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK 0x00000001 7191 #define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT 0 7192 static inline uint32_t A6XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val) 7193 { 7194 return ((val) << A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK; 7195 } 7196 #define A6XX_HLSQ_FS_CNTL_0_VARYINGS 0x00000002 7197 #define A6XX_HLSQ_FS_CNTL_0_UNK2__MASK 0x00000ffc 7198 #define A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT 2 7199 static inline uint32_t A6XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val) 7200 { 7201 return ((val) << A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A6XX_HLSQ_FS_CNTL_0_UNK2__MASK; 7202 } 7203 7204 #define REG_A6XX_HLSQ_UNKNOWN_B981 0x0000b981 7205 7206 #define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982 7207 7208 #define REG_A7XX_HLSQ_CONTROL_1_REG 0x0000a9c7 7209 7210 #define REG_A6XX_HLSQ_CONTROL_2_REG 0x0000b983 7211 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff 7212 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0 7213 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) 7214 { 7215 return ((val) << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; 7216 } 7217 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00 7218 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8 7219 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) 7220 { 7221 return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK; 7222 } 7223 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000 7224 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16 7225 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) 7226 { 7227 return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK; 7228 } 7229 #define A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK 0xff000000 7230 #define A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT 24 7231 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val) 7232 { 7233 return ((val) << A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK; 7234 } 7235 7236 #define REG_A7XX_HLSQ_CONTROL_2_REG 0x0000a9c8 7237 #define A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff 7238 #define A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0 7239 static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) 7240 { 7241 return ((val) << A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; 7242 } 7243 #define A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00 7244 #define A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8 7245 static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) 7246 { 7247 return ((val) << A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK; 7248 } 7249 #define A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000 7250 #define A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16 7251 static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) 7252 { 7253 return ((val) << A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK; 7254 } 7255 #define A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK 0xff000000 7256 #define A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT 24 7257 static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val) 7258 { 7259 return ((val) << A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK; 7260 } 7261 7262 #define REG_A6XX_HLSQ_CONTROL_3_REG 0x0000b984 7263 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff 7264 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0 7265 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val) 7266 { 7267 return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK; 7268 } 7269 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00 7270 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8 7271 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val) 7272 { 7273 return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK; 7274 } 7275 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000 7276 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16 7277 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val) 7278 { 7279 return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK; 7280 } 7281 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000 7282 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24 7283 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) 7284 { 7285 return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK; 7286 } 7287 7288 #define REG_A7XX_HLSQ_CONTROL_3_REG 0x0000a9c9 7289 #define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff 7290 #define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0 7291 static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val) 7292 { 7293 return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK; 7294 } 7295 #define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00 7296 #define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8 7297 static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val) 7298 { 7299 return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK; 7300 } 7301 #define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000 7302 #define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16 7303 static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val) 7304 { 7305 return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK; 7306 } 7307 #define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000 7308 #define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24 7309 static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) 7310 { 7311 return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK; 7312 } 7313 7314 #define REG_A6XX_HLSQ_CONTROL_4_REG 0x0000b985 7315 #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff 7316 #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0 7317 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val) 7318 { 7319 return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK; 7320 } 7321 #define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00 7322 #define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8 7323 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val) 7324 { 7325 return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK; 7326 } 7327 #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000 7328 #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16 7329 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) 7330 { 7331 return ((val) << A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK; 7332 } 7333 #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000 7334 #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24 7335 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) 7336 { 7337 return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; 7338 } 7339 7340 #define REG_A7XX_HLSQ_CONTROL_4_REG 0x0000a9ca 7341 #define A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff 7342 #define A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0 7343 static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val) 7344 { 7345 return ((val) << A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK; 7346 } 7347 #define A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00 7348 #define A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8 7349 static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val) 7350 { 7351 return ((val) << A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK; 7352 } 7353 #define A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000 7354 #define A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16 7355 static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) 7356 { 7357 return ((val) << A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK; 7358 } 7359 #define A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000 7360 #define A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24 7361 static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) 7362 { 7363 return ((val) << A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; 7364 } 7365 7366 #define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986 7367 #define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK 0x000000ff 7368 #define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT 0 7369 static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val) 7370 { 7371 return ((val) << A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK; 7372 } 7373 #define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK 0x0000ff00 7374 #define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT 8 7375 static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val) 7376 { 7377 return ((val) << A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK; 7378 } 7379 7380 #define REG_A7XX_HLSQ_CONTROL_5_REG 0x0000a9cb 7381 #define A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK 0x000000ff 7382 #define A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT 0 7383 static inline uint32_t A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val) 7384 { 7385 return ((val) << A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK; 7386 } 7387 #define A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK 0x0000ff00 7388 #define A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT 8 7389 static inline uint32_t A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val) 7390 { 7391 return ((val) << A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK; 7392 } 7393 7394 #define REG_A6XX_HLSQ_CS_CNTL 0x0000b987 7395 #define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff 7396 #define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0 7397 static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val) 7398 { 7399 return ((val >> 2) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK; 7400 } 7401 #define A6XX_HLSQ_CS_CNTL_ENABLED 0x00000100 7402 7403 #define REG_A6XX_HLSQ_CS_NDRANGE_0 0x0000b990 7404 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003 7405 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0 7406 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) 7407 { 7408 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK; 7409 } 7410 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc 7411 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2 7412 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) 7413 { 7414 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK; 7415 } 7416 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000 7417 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12 7418 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) 7419 { 7420 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK; 7421 } 7422 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000 7423 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22 7424 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) 7425 { 7426 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK; 7427 } 7428 7429 #define REG_A6XX_HLSQ_CS_NDRANGE_1 0x0000b991 7430 #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff 7431 #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0 7432 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val) 7433 { 7434 return ((val) << A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK; 7435 } 7436 7437 #define REG_A6XX_HLSQ_CS_NDRANGE_2 0x0000b992 7438 #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff 7439 #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0 7440 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val) 7441 { 7442 return ((val) << A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK; 7443 } 7444 7445 #define REG_A6XX_HLSQ_CS_NDRANGE_3 0x0000b993 7446 #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff 7447 #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0 7448 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val) 7449 { 7450 return ((val) << A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK; 7451 } 7452 7453 #define REG_A6XX_HLSQ_CS_NDRANGE_4 0x0000b994 7454 #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff 7455 #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0 7456 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val) 7457 { 7458 return ((val) << A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK; 7459 } 7460 7461 #define REG_A6XX_HLSQ_CS_NDRANGE_5 0x0000b995 7462 #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff 7463 #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0 7464 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val) 7465 { 7466 return ((val) << A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK; 7467 } 7468 7469 #define REG_A6XX_HLSQ_CS_NDRANGE_6 0x0000b996 7470 #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff 7471 #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0 7472 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val) 7473 { 7474 return ((val) << A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK; 7475 } 7476 7477 #define REG_A6XX_HLSQ_CS_CNTL_0 0x0000b997 7478 #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff 7479 #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0 7480 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val) 7481 { 7482 return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK; 7483 } 7484 #define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK 0x0000ff00 7485 #define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT 8 7486 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(uint32_t val) 7487 { 7488 return ((val) << A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK; 7489 } 7490 #define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK 0x00ff0000 7491 #define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT 16 7492 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val) 7493 { 7494 return ((val) << A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK; 7495 } 7496 #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000 7497 #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24 7498 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) 7499 { 7500 return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK; 7501 } 7502 7503 #define REG_A6XX_HLSQ_CS_CNTL_1 0x0000b998 7504 #define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff 7505 #define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0 7506 static inline uint32_t A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) 7507 { 7508 return ((val) << A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK; 7509 } 7510 #define A6XX_HLSQ_CS_CNTL_1_SINGLE_SP_CORE 0x00000100 7511 #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK 0x00000200 7512 #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT 9 7513 static inline uint32_t A6XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) 7514 { 7515 return ((val) << A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK; 7516 } 7517 #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400 7518 7519 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X 0x0000b999 7520 7521 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000b99a 7522 7523 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000b99b 7524 7525 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD 0x0000b9a0 7526 7527 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR 0x0000b9a1 7528 #define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK 0xffffffff 7529 #define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT 0 7530 static inline uint32_t A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR(uint32_t val) 7531 { 7532 return ((val) << A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK; 7533 } 7534 7535 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA 0x0000b9a3 7536 7537 static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; } 7538 7539 static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; } 7540 #define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 7541 #define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0 7542 static inline uint32_t A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) 7543 { 7544 return ((val) << A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; 7545 } 7546 #define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffc 7547 #define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 7548 static inline uint32_t A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val) 7549 { 7550 return ((val >> 2) << A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; 7551 } 7552 7553 #define REG_A6XX_HLSQ_CS_UNKNOWN_B9D0 0x0000b9d0 7554 #define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK 0x0000001f 7555 #define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT 0 7556 static inline uint32_t A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE(uint32_t val) 7557 { 7558 return ((val) << A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT) & A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK; 7559 } 7560 #define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK5 0x00000020 7561 #define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK6 0x00000040 7562 7563 #define REG_A6XX_HLSQ_DRAW_CMD 0x0000bb00 7564 #define A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK 0x000000ff 7565 #define A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT 0 7566 static inline uint32_t A6XX_HLSQ_DRAW_CMD_STATE_ID(uint32_t val) 7567 { 7568 return ((val) << A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK; 7569 } 7570 7571 #define REG_A6XX_HLSQ_DISPATCH_CMD 0x0000bb01 7572 #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK 0x000000ff 7573 #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT 0 7574 static inline uint32_t A6XX_HLSQ_DISPATCH_CMD_STATE_ID(uint32_t val) 7575 { 7576 return ((val) << A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK; 7577 } 7578 7579 #define REG_A6XX_HLSQ_EVENT_CMD 0x0000bb02 7580 #define A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK 0x00ff0000 7581 #define A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT 16 7582 static inline uint32_t A6XX_HLSQ_EVENT_CMD_STATE_ID(uint32_t val) 7583 { 7584 return ((val) << A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK; 7585 } 7586 #define A6XX_HLSQ_EVENT_CMD_EVENT__MASK 0x0000007f 7587 #define A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT 0 7588 static inline uint32_t A6XX_HLSQ_EVENT_CMD_EVENT(enum vgt_event_type val) 7589 { 7590 return ((val) << A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_EVENT_CMD_EVENT__MASK; 7591 } 7592 7593 #define REG_A6XX_HLSQ_INVALIDATE_CMD 0x0000bb08 7594 #define A6XX_HLSQ_INVALIDATE_CMD_VS_STATE 0x00000001 7595 #define A6XX_HLSQ_INVALIDATE_CMD_HS_STATE 0x00000002 7596 #define A6XX_HLSQ_INVALIDATE_CMD_DS_STATE 0x00000004 7597 #define A6XX_HLSQ_INVALIDATE_CMD_GS_STATE 0x00000008 7598 #define A6XX_HLSQ_INVALIDATE_CMD_FS_STATE 0x00000010 7599 #define A6XX_HLSQ_INVALIDATE_CMD_CS_STATE 0x00000020 7600 #define A6XX_HLSQ_INVALIDATE_CMD_CS_IBO 0x00000040 7601 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO 0x00000080 7602 #define A6XX_HLSQ_INVALIDATE_CMD_CS_SHARED_CONST 0x00080000 7603 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_SHARED_CONST 0x00000100 7604 #define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK 0x00003e00 7605 #define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT 9 7606 static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val) 7607 { 7608 return ((val) << A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK; 7609 } 7610 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK 0x0007c000 7611 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT 14 7612 static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val) 7613 { 7614 return ((val) << A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK; 7615 } 7616 7617 #define REG_A6XX_HLSQ_FS_CNTL 0x0000bb10 7618 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff 7619 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0 7620 static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val) 7621 { 7622 return ((val >> 2) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK; 7623 } 7624 #define A6XX_HLSQ_FS_CNTL_ENABLED 0x00000100 7625 7626 #define REG_A6XX_HLSQ_SHARED_CONSTS 0x0000bb11 7627 #define A6XX_HLSQ_SHARED_CONSTS_ENABLE 0x00000001 7628 7629 static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE(uint32_t i0) { return 0x0000bb20 + 0x2*i0; } 7630 7631 static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000bb20 + 0x2*i0; } 7632 #define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 7633 #define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0 7634 static inline uint32_t A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) 7635 { 7636 return ((val) << A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; 7637 } 7638 #define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffc 7639 #define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 7640 static inline uint32_t A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val) 7641 { 7642 return ((val >> 2) << A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; 7643 } 7644 7645 #define REG_A6XX_HLSQ_2D_EVENT_CMD 0x0000bd80 7646 #define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00 7647 #define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT 8 7648 static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_STATE_ID(uint32_t val) 7649 { 7650 return ((val) << A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK; 7651 } 7652 #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK 0x0000007f 7653 #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT 0 7654 static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val) 7655 { 7656 return ((val) << A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK; 7657 } 7658 7659 #define REG_A6XX_HLSQ_UNKNOWN_BE00 0x0000be00 7660 7661 #define REG_A6XX_HLSQ_UNKNOWN_BE01 0x0000be01 7662 7663 #define REG_A6XX_HLSQ_DBG_ECO_CNTL 0x0000be04 7664 7665 #define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05 7666 7667 #define REG_A6XX_HLSQ_UNKNOWN_BE08 0x0000be08 7668 7669 static inline uint32_t REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000be10 + 0x1*i0; } 7670 7671 #define REG_A6XX_HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE 0x0000be22 7672 7673 #define REG_A7XX_SP_AHB_READ_APERTURE 0x0000c000 7674 7675 #define REG_A6XX_CP_EVENT_START 0x0000d600 7676 #define A6XX_CP_EVENT_START_STATE_ID__MASK 0x000000ff 7677 #define A6XX_CP_EVENT_START_STATE_ID__SHIFT 0 7678 static inline uint32_t A6XX_CP_EVENT_START_STATE_ID(uint32_t val) 7679 { 7680 return ((val) << A6XX_CP_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_EVENT_START_STATE_ID__MASK; 7681 } 7682 7683 #define REG_A6XX_CP_EVENT_END 0x0000d601 7684 #define A6XX_CP_EVENT_END_STATE_ID__MASK 0x000000ff 7685 #define A6XX_CP_EVENT_END_STATE_ID__SHIFT 0 7686 static inline uint32_t A6XX_CP_EVENT_END_STATE_ID(uint32_t val) 7687 { 7688 return ((val) << A6XX_CP_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_EVENT_END_STATE_ID__MASK; 7689 } 7690 7691 #define REG_A6XX_CP_2D_EVENT_START 0x0000d700 7692 #define A6XX_CP_2D_EVENT_START_STATE_ID__MASK 0x000000ff 7693 #define A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT 0 7694 static inline uint32_t A6XX_CP_2D_EVENT_START_STATE_ID(uint32_t val) 7695 { 7696 return ((val) << A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_START_STATE_ID__MASK; 7697 } 7698 7699 #define REG_A6XX_CP_2D_EVENT_END 0x0000d701 7700 #define A6XX_CP_2D_EVENT_END_STATE_ID__MASK 0x000000ff 7701 #define A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT 0 7702 static inline uint32_t A6XX_CP_2D_EVENT_END_STATE_ID(uint32_t val) 7703 { 7704 return ((val) << A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_END_STATE_ID__MASK; 7705 } 7706 7707 #define REG_A6XX_TEX_SAMP_0 0x00000000 7708 #define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 7709 #define A6XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 7710 #define A6XX_TEX_SAMP_0_XY_MAG__SHIFT 1 7711 static inline uint32_t A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val) 7712 { 7713 return ((val) << A6XX_TEX_SAMP_0_XY_MAG__SHIFT) & A6XX_TEX_SAMP_0_XY_MAG__MASK; 7714 } 7715 #define A6XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 7716 #define A6XX_TEX_SAMP_0_XY_MIN__SHIFT 3 7717 static inline uint32_t A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val) 7718 { 7719 return ((val) << A6XX_TEX_SAMP_0_XY_MIN__SHIFT) & A6XX_TEX_SAMP_0_XY_MIN__MASK; 7720 } 7721 #define A6XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 7722 #define A6XX_TEX_SAMP_0_WRAP_S__SHIFT 5 7723 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val) 7724 { 7725 return ((val) << A6XX_TEX_SAMP_0_WRAP_S__SHIFT) & A6XX_TEX_SAMP_0_WRAP_S__MASK; 7726 } 7727 #define A6XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 7728 #define A6XX_TEX_SAMP_0_WRAP_T__SHIFT 8 7729 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val) 7730 { 7731 return ((val) << A6XX_TEX_SAMP_0_WRAP_T__SHIFT) & A6XX_TEX_SAMP_0_WRAP_T__MASK; 7732 } 7733 #define A6XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 7734 #define A6XX_TEX_SAMP_0_WRAP_R__SHIFT 11 7735 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val) 7736 { 7737 return ((val) << A6XX_TEX_SAMP_0_WRAP_R__SHIFT) & A6XX_TEX_SAMP_0_WRAP_R__MASK; 7738 } 7739 #define A6XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 7740 #define A6XX_TEX_SAMP_0_ANISO__SHIFT 14 7741 static inline uint32_t A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val) 7742 { 7743 return ((val) << A6XX_TEX_SAMP_0_ANISO__SHIFT) & A6XX_TEX_SAMP_0_ANISO__MASK; 7744 } 7745 #define A6XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000 7746 #define A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19 7747 static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val) 7748 { 7749 return ((((int32_t)(val * 256.0))) << A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A6XX_TEX_SAMP_0_LOD_BIAS__MASK; 7750 } 7751 7752 #define REG_A6XX_TEX_SAMP_1 0x00000001 7753 #define A6XX_TEX_SAMP_1_CLAMPENABLE 0x00000001 7754 #define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e 7755 #define A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 7756 static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) 7757 { 7758 return ((val) << A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK; 7759 } 7760 #define A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010 7761 #define A6XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 7762 #define A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 7763 #define A6XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 7764 #define A6XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 7765 static inline uint32_t A6XX_TEX_SAMP_1_MAX_LOD(float val) 7766 { 7767 return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK; 7768 } 7769 #define A6XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 7770 #define A6XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 7771 static inline uint32_t A6XX_TEX_SAMP_1_MIN_LOD(float val) 7772 { 7773 return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK; 7774 } 7775 7776 #define REG_A6XX_TEX_SAMP_2 0x00000002 7777 #define A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK 0x00000003 7778 #define A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT 0 7779 static inline uint32_t A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode val) 7780 { 7781 return ((val) << A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT) & A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK; 7782 } 7783 #define A6XX_TEX_SAMP_2_CHROMA_LINEAR 0x00000020 7784 #define A6XX_TEX_SAMP_2_BCOLOR__MASK 0xffffff80 7785 #define A6XX_TEX_SAMP_2_BCOLOR__SHIFT 7 7786 static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR(uint32_t val) 7787 { 7788 return ((val) << A6XX_TEX_SAMP_2_BCOLOR__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR__MASK; 7789 } 7790 7791 #define REG_A6XX_TEX_SAMP_3 0x00000003 7792 7793 #define REG_A6XX_TEX_CONST_0 0x00000000 7794 #define A6XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003 7795 #define A6XX_TEX_CONST_0_TILE_MODE__SHIFT 0 7796 static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val) 7797 { 7798 return ((val) << A6XX_TEX_CONST_0_TILE_MODE__SHIFT) & A6XX_TEX_CONST_0_TILE_MODE__MASK; 7799 } 7800 #define A6XX_TEX_CONST_0_SRGB 0x00000004 7801 #define A6XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 7802 #define A6XX_TEX_CONST_0_SWIZ_X__SHIFT 4 7803 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val) 7804 { 7805 return ((val) << A6XX_TEX_CONST_0_SWIZ_X__SHIFT) & A6XX_TEX_CONST_0_SWIZ_X__MASK; 7806 } 7807 #define A6XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 7808 #define A6XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 7809 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val) 7810 { 7811 return ((val) << A6XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Y__MASK; 7812 } 7813 #define A6XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 7814 #define A6XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 7815 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val) 7816 { 7817 return ((val) << A6XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Z__MASK; 7818 } 7819 #define A6XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 7820 #define A6XX_TEX_CONST_0_SWIZ_W__SHIFT 13 7821 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val) 7822 { 7823 return ((val) << A6XX_TEX_CONST_0_SWIZ_W__SHIFT) & A6XX_TEX_CONST_0_SWIZ_W__MASK; 7824 } 7825 #define A6XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 7826 #define A6XX_TEX_CONST_0_MIPLVLS__SHIFT 16 7827 static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val) 7828 { 7829 return ((val) << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK; 7830 } 7831 #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X 0x00010000 7832 #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y 0x00040000 7833 #define A6XX_TEX_CONST_0_SAMPLES__MASK 0x00300000 7834 #define A6XX_TEX_CONST_0_SAMPLES__SHIFT 20 7835 static inline uint32_t A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val) 7836 { 7837 return ((val) << A6XX_TEX_CONST_0_SAMPLES__SHIFT) & A6XX_TEX_CONST_0_SAMPLES__MASK; 7838 } 7839 #define A6XX_TEX_CONST_0_FMT__MASK 0x3fc00000 7840 #define A6XX_TEX_CONST_0_FMT__SHIFT 22 7841 static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_format val) 7842 { 7843 return ((val) << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK; 7844 } 7845 #define A6XX_TEX_CONST_0_SWAP__MASK 0xc0000000 7846 #define A6XX_TEX_CONST_0_SWAP__SHIFT 30 7847 static inline uint32_t A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val) 7848 { 7849 return ((val) << A6XX_TEX_CONST_0_SWAP__SHIFT) & A6XX_TEX_CONST_0_SWAP__MASK; 7850 } 7851 7852 #define REG_A6XX_TEX_CONST_1 0x00000001 7853 #define A6XX_TEX_CONST_1_WIDTH__MASK 0x00007fff 7854 #define A6XX_TEX_CONST_1_WIDTH__SHIFT 0 7855 static inline uint32_t A6XX_TEX_CONST_1_WIDTH(uint32_t val) 7856 { 7857 return ((val) << A6XX_TEX_CONST_1_WIDTH__SHIFT) & A6XX_TEX_CONST_1_WIDTH__MASK; 7858 } 7859 #define A6XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000 7860 #define A6XX_TEX_CONST_1_HEIGHT__SHIFT 15 7861 static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val) 7862 { 7863 return ((val) << A6XX_TEX_CONST_1_HEIGHT__SHIFT) & A6XX_TEX_CONST_1_HEIGHT__MASK; 7864 } 7865 7866 #define REG_A6XX_TEX_CONST_2 0x00000002 7867 #define A6XX_TEX_CONST_2_STRUCTSIZETEXELS__MASK 0x0000fff0 7868 #define A6XX_TEX_CONST_2_STRUCTSIZETEXELS__SHIFT 4 7869 static inline uint32_t A6XX_TEX_CONST_2_STRUCTSIZETEXELS(uint32_t val) 7870 { 7871 return ((val) << A6XX_TEX_CONST_2_STRUCTSIZETEXELS__SHIFT) & A6XX_TEX_CONST_2_STRUCTSIZETEXELS__MASK; 7872 } 7873 #define A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK 0x003f0000 7874 #define A6XX_TEX_CONST_2_STARTOFFSETTEXELS__SHIFT 16 7875 static inline uint32_t A6XX_TEX_CONST_2_STARTOFFSETTEXELS(uint32_t val) 7876 { 7877 return ((val) << A6XX_TEX_CONST_2_STARTOFFSETTEXELS__SHIFT) & A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK; 7878 } 7879 #define A6XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f 7880 #define A6XX_TEX_CONST_2_PITCHALIGN__SHIFT 0 7881 static inline uint32_t A6XX_TEX_CONST_2_PITCHALIGN(uint32_t val) 7882 { 7883 return ((val) << A6XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A6XX_TEX_CONST_2_PITCHALIGN__MASK; 7884 } 7885 #define A6XX_TEX_CONST_2_PITCH__MASK 0x1fffff80 7886 #define A6XX_TEX_CONST_2_PITCH__SHIFT 7 7887 static inline uint32_t A6XX_TEX_CONST_2_PITCH(uint32_t val) 7888 { 7889 return ((val) << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK; 7890 } 7891 #define A6XX_TEX_CONST_2_TYPE__MASK 0xe0000000 7892 #define A6XX_TEX_CONST_2_TYPE__SHIFT 29 7893 static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val) 7894 { 7895 return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK; 7896 } 7897 7898 #define REG_A6XX_TEX_CONST_3 0x00000003 7899 #define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff 7900 #define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0 7901 static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) 7902 { 7903 return ((val >> 12) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK; 7904 } 7905 #define A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000 7906 #define A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23 7907 static inline uint32_t A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val) 7908 { 7909 return ((val >> 12) << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK; 7910 } 7911 #define A6XX_TEX_CONST_3_TILE_ALL 0x08000000 7912 #define A6XX_TEX_CONST_3_FLAG 0x10000000 7913 7914 #define REG_A6XX_TEX_CONST_4 0x00000004 7915 #define A6XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0 7916 #define A6XX_TEX_CONST_4_BASE_LO__SHIFT 5 7917 static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val) 7918 { 7919 return ((val >> 5) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK; 7920 } 7921 7922 #define REG_A6XX_TEX_CONST_5 0x00000005 7923 #define A6XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff 7924 #define A6XX_TEX_CONST_5_BASE_HI__SHIFT 0 7925 static inline uint32_t A6XX_TEX_CONST_5_BASE_HI(uint32_t val) 7926 { 7927 return ((val) << A6XX_TEX_CONST_5_BASE_HI__SHIFT) & A6XX_TEX_CONST_5_BASE_HI__MASK; 7928 } 7929 #define A6XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000 7930 #define A6XX_TEX_CONST_5_DEPTH__SHIFT 17 7931 static inline uint32_t A6XX_TEX_CONST_5_DEPTH(uint32_t val) 7932 { 7933 return ((val) << A6XX_TEX_CONST_5_DEPTH__SHIFT) & A6XX_TEX_CONST_5_DEPTH__MASK; 7934 } 7935 7936 #define REG_A6XX_TEX_CONST_6 0x00000006 7937 #define A6XX_TEX_CONST_6_MIN_LOD_CLAMP__MASK 0x00000fff 7938 #define A6XX_TEX_CONST_6_MIN_LOD_CLAMP__SHIFT 0 7939 static inline uint32_t A6XX_TEX_CONST_6_MIN_LOD_CLAMP(float val) 7940 { 7941 return ((((uint32_t)(val * 256.0))) << A6XX_TEX_CONST_6_MIN_LOD_CLAMP__SHIFT) & A6XX_TEX_CONST_6_MIN_LOD_CLAMP__MASK; 7942 } 7943 #define A6XX_TEX_CONST_6_PLANE_PITCH__MASK 0xffffff00 7944 #define A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT 8 7945 static inline uint32_t A6XX_TEX_CONST_6_PLANE_PITCH(uint32_t val) 7946 { 7947 return ((val) << A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT) & A6XX_TEX_CONST_6_PLANE_PITCH__MASK; 7948 } 7949 7950 #define REG_A6XX_TEX_CONST_7 0x00000007 7951 #define A6XX_TEX_CONST_7_FLAG_LO__MASK 0xffffffe0 7952 #define A6XX_TEX_CONST_7_FLAG_LO__SHIFT 5 7953 static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val) 7954 { 7955 return ((val >> 5) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK; 7956 } 7957 7958 #define REG_A6XX_TEX_CONST_8 0x00000008 7959 #define A6XX_TEX_CONST_8_FLAG_HI__MASK 0x0001ffff 7960 #define A6XX_TEX_CONST_8_FLAG_HI__SHIFT 0 7961 static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val) 7962 { 7963 return ((val) << A6XX_TEX_CONST_8_FLAG_HI__SHIFT) & A6XX_TEX_CONST_8_FLAG_HI__MASK; 7964 } 7965 7966 #define REG_A6XX_TEX_CONST_9 0x00000009 7967 #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff 7968 #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0 7969 static inline uint32_t A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) 7970 { 7971 return ((val >> 4) << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK; 7972 } 7973 7974 #define REG_A6XX_TEX_CONST_10 0x0000000a 7975 #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK 0x0000007f 7976 #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT 0 7977 static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val) 7978 { 7979 return ((val >> 6) << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK; 7980 } 7981 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK 0x00000f00 7982 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT 8 7983 static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(uint32_t val) 7984 { 7985 return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK; 7986 } 7987 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK 0x0000f000 7988 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT 12 7989 static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(uint32_t val) 7990 { 7991 return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK; 7992 } 7993 7994 #define REG_A6XX_TEX_CONST_11 0x0000000b 7995 7996 #define REG_A6XX_TEX_CONST_12 0x0000000c 7997 7998 #define REG_A6XX_TEX_CONST_13 0x0000000d 7999 8000 #define REG_A6XX_TEX_CONST_14 0x0000000e 8001 8002 #define REG_A6XX_TEX_CONST_15 0x0000000f 8003 8004 #define REG_A6XX_UBO_0 0x00000000 8005 #define A6XX_UBO_0_BASE_LO__MASK 0xffffffff 8006 #define A6XX_UBO_0_BASE_LO__SHIFT 0 8007 static inline uint32_t A6XX_UBO_0_BASE_LO(uint32_t val) 8008 { 8009 return ((val) << A6XX_UBO_0_BASE_LO__SHIFT) & A6XX_UBO_0_BASE_LO__MASK; 8010 } 8011 8012 #define REG_A6XX_UBO_1 0x00000001 8013 #define A6XX_UBO_1_BASE_HI__MASK 0x0001ffff 8014 #define A6XX_UBO_1_BASE_HI__SHIFT 0 8015 static inline uint32_t A6XX_UBO_1_BASE_HI(uint32_t val) 8016 { 8017 return ((val) << A6XX_UBO_1_BASE_HI__SHIFT) & A6XX_UBO_1_BASE_HI__MASK; 8018 } 8019 #define A6XX_UBO_1_SIZE__MASK 0xfffe0000 8020 #define A6XX_UBO_1_SIZE__SHIFT 17 8021 static inline uint32_t A6XX_UBO_1_SIZE(uint32_t val) 8022 { 8023 return ((val) << A6XX_UBO_1_SIZE__SHIFT) & A6XX_UBO_1_SIZE__MASK; 8024 } 8025 8026 #define REG_A6XX_PDC_GPU_ENABLE_PDC 0x00001140 8027 8028 #define REG_A6XX_PDC_GPU_SEQ_START_ADDR 0x00001148 8029 8030 #define REG_A6XX_PDC_GPU_TCS0_CONTROL 0x00001540 8031 8032 #define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK 0x00001541 8033 8034 #define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK 0x00001542 8035 8036 #define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID 0x00001543 8037 8038 #define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR 0x00001544 8039 8040 #define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA 0x00001545 8041 8042 #define REG_A6XX_PDC_GPU_TCS1_CONTROL 0x00001572 8043 8044 #define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK 0x00001573 8045 8046 #define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK 0x00001574 8047 8048 #define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID 0x00001575 8049 8050 #define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR 0x00001576 8051 8052 #define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA 0x00001577 8053 8054 #define REG_A6XX_PDC_GPU_TCS2_CONTROL 0x000015a4 8055 8056 #define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK 0x000015a5 8057 8058 #define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK 0x000015a6 8059 8060 #define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID 0x000015a7 8061 8062 #define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR 0x000015a8 8063 8064 #define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA 0x000015a9 8065 8066 #define REG_A6XX_PDC_GPU_TCS3_CONTROL 0x000015d6 8067 8068 #define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK 0x000015d7 8069 8070 #define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK 0x000015d8 8071 8072 #define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID 0x000015d9 8073 8074 #define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR 0x000015da 8075 8076 #define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA 0x000015db 8077 8078 #define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x00000000 8079 8080 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A 0x00000000 8081 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK 0x000000ff 8082 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT 0 8083 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val) 8084 { 8085 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK; 8086 } 8087 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK 0x0000ff00 8088 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT 8 8089 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val) 8090 { 8091 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK; 8092 } 8093 8094 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B 0x00000001 8095 8096 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C 0x00000002 8097 8098 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D 0x00000003 8099 8100 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT 0x00000004 8101 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f 8102 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0 8103 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) 8104 { 8105 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; 8106 } 8107 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000 8108 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12 8109 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) 8110 { 8111 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; 8112 } 8113 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000 8114 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28 8115 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) 8116 { 8117 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; 8118 } 8119 8120 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM 0x00000005 8121 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000 8122 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24 8123 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) 8124 { 8125 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; 8126 } 8127 8128 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 0x00000008 8129 8130 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 0x00000009 8131 8132 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 0x0000000a 8133 8134 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 0x0000000b 8135 8136 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 0x0000000c 8137 8138 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 0x0000000d 8139 8140 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 0x0000000e 8141 8142 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 0x0000000f 8143 8144 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000010 8145 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f 8146 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0 8147 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) 8148 { 8149 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; 8150 } 8151 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0 8152 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4 8153 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) 8154 { 8155 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; 8156 } 8157 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00 8158 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8 8159 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) 8160 { 8161 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; 8162 } 8163 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000 8164 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12 8165 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) 8166 { 8167 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; 8168 } 8169 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000 8170 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16 8171 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) 8172 { 8173 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; 8174 } 8175 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000 8176 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20 8177 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) 8178 { 8179 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; 8180 } 8181 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000 8182 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24 8183 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) 8184 { 8185 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; 8186 } 8187 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000 8188 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28 8189 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) 8190 { 8191 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; 8192 } 8193 8194 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000011 8195 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f 8196 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0 8197 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) 8198 { 8199 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; 8200 } 8201 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0 8202 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4 8203 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) 8204 { 8205 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; 8206 } 8207 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00 8208 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8 8209 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) 8210 { 8211 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; 8212 } 8213 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000 8214 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12 8215 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) 8216 { 8217 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; 8218 } 8219 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000 8220 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16 8221 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) 8222 { 8223 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; 8224 } 8225 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000 8226 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20 8227 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) 8228 { 8229 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; 8230 } 8231 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000 8232 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24 8233 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) 8234 { 8235 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; 8236 } 8237 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000 8238 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28 8239 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) 8240 { 8241 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; 8242 } 8243 8244 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000002f 8245 8246 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000030 8247 8248 #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 0x00000001 8249 8250 #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 0x00000002 8251 8252 8253 #endif /* A6XX_XML */ 8254