1 #ifndef A6XX_XML 2 #define A6XX_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-01-30 18:25:22) 12 - /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2020-12-31 19:26:32) 13 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-06-21 15:24:24) 14 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14609 bytes, from 2021-11-24 23:05:10) 15 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 69086 bytes, from 2022-03-03 16:41:33) 16 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2021-11-24 23:05:10) 17 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113358 bytes, from 2022-01-31 23:06:21) 18 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149512 bytes, from 2022-01-31 23:06:21) 19 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx.xml ( 184954 bytes, from 2022-03-03 16:41:33) 20 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-07-22 15:21:56) 21 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-01-30 18:25:22) 22 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-07-22 15:21:56) 23 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-07-22 15:21:56) 24 25 Copyright (C) 2013-2022 by the following authors: 26 - Rob Clark <robdclark@gmail.com> (robclark) 27 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 28 29 Permission is hereby granted, free of charge, to any person obtaining 30 a copy of this software and associated documentation files (the 31 "Software"), to deal in the Software without restriction, including 32 without limitation the rights to use, copy, modify, merge, publish, 33 distribute, sublicense, and/or sell copies of the Software, and to 34 permit persons to whom the Software is furnished to do so, subject to 35 the following conditions: 36 37 The above copyright notice and this permission notice (including the 38 next paragraph) shall be included in all copies or substantial 39 portions of the Software. 40 41 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 42 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 43 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 44 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 45 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 46 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 47 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 48 */ 49 50 51 enum a6xx_tile_mode { 52 TILE6_LINEAR = 0, 53 TILE6_2 = 2, 54 TILE6_3 = 3, 55 }; 56 57 enum a6xx_format { 58 FMT6_A8_UNORM = 2, 59 FMT6_8_UNORM = 3, 60 FMT6_8_SNORM = 4, 61 FMT6_8_UINT = 5, 62 FMT6_8_SINT = 6, 63 FMT6_4_4_4_4_UNORM = 8, 64 FMT6_5_5_5_1_UNORM = 10, 65 FMT6_1_5_5_5_UNORM = 12, 66 FMT6_5_6_5_UNORM = 14, 67 FMT6_8_8_UNORM = 15, 68 FMT6_8_8_SNORM = 16, 69 FMT6_8_8_UINT = 17, 70 FMT6_8_8_SINT = 18, 71 FMT6_L8_A8_UNORM = 19, 72 FMT6_16_UNORM = 21, 73 FMT6_16_SNORM = 22, 74 FMT6_16_FLOAT = 23, 75 FMT6_16_UINT = 24, 76 FMT6_16_SINT = 25, 77 FMT6_8_8_8_UNORM = 33, 78 FMT6_8_8_8_SNORM = 34, 79 FMT6_8_8_8_UINT = 35, 80 FMT6_8_8_8_SINT = 36, 81 FMT6_8_8_8_8_UNORM = 48, 82 FMT6_8_8_8_X8_UNORM = 49, 83 FMT6_8_8_8_8_SNORM = 50, 84 FMT6_8_8_8_8_UINT = 51, 85 FMT6_8_8_8_8_SINT = 52, 86 FMT6_9_9_9_E5_FLOAT = 53, 87 FMT6_10_10_10_2_UNORM = 54, 88 FMT6_10_10_10_2_UNORM_DEST = 55, 89 FMT6_10_10_10_2_SNORM = 57, 90 FMT6_10_10_10_2_UINT = 58, 91 FMT6_10_10_10_2_SINT = 59, 92 FMT6_11_11_10_FLOAT = 66, 93 FMT6_16_16_UNORM = 67, 94 FMT6_16_16_SNORM = 68, 95 FMT6_16_16_FLOAT = 69, 96 FMT6_16_16_UINT = 70, 97 FMT6_16_16_SINT = 71, 98 FMT6_32_UNORM = 72, 99 FMT6_32_SNORM = 73, 100 FMT6_32_FLOAT = 74, 101 FMT6_32_UINT = 75, 102 FMT6_32_SINT = 76, 103 FMT6_32_FIXED = 77, 104 FMT6_16_16_16_UNORM = 88, 105 FMT6_16_16_16_SNORM = 89, 106 FMT6_16_16_16_FLOAT = 90, 107 FMT6_16_16_16_UINT = 91, 108 FMT6_16_16_16_SINT = 92, 109 FMT6_16_16_16_16_UNORM = 96, 110 FMT6_16_16_16_16_SNORM = 97, 111 FMT6_16_16_16_16_FLOAT = 98, 112 FMT6_16_16_16_16_UINT = 99, 113 FMT6_16_16_16_16_SINT = 100, 114 FMT6_32_32_UNORM = 101, 115 FMT6_32_32_SNORM = 102, 116 FMT6_32_32_FLOAT = 103, 117 FMT6_32_32_UINT = 104, 118 FMT6_32_32_SINT = 105, 119 FMT6_32_32_FIXED = 106, 120 FMT6_32_32_32_UNORM = 112, 121 FMT6_32_32_32_SNORM = 113, 122 FMT6_32_32_32_UINT = 114, 123 FMT6_32_32_32_SINT = 115, 124 FMT6_32_32_32_FLOAT = 116, 125 FMT6_32_32_32_FIXED = 117, 126 FMT6_32_32_32_32_UNORM = 128, 127 FMT6_32_32_32_32_SNORM = 129, 128 FMT6_32_32_32_32_FLOAT = 130, 129 FMT6_32_32_32_32_UINT = 131, 130 FMT6_32_32_32_32_SINT = 132, 131 FMT6_32_32_32_32_FIXED = 133, 132 FMT6_G8R8B8R8_422_UNORM = 140, 133 FMT6_R8G8R8B8_422_UNORM = 141, 134 FMT6_R8_G8B8_2PLANE_420_UNORM = 142, 135 FMT6_NV21 = 143, 136 FMT6_R8_G8_B8_3PLANE_420_UNORM = 144, 137 FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 = 145, 138 FMT6_NV12_Y = 148, 139 FMT6_NV12_UV = 149, 140 FMT6_NV12_VU = 150, 141 FMT6_NV12_4R = 151, 142 FMT6_NV12_4R_Y = 152, 143 FMT6_NV12_4R_UV = 153, 144 FMT6_P010 = 154, 145 FMT6_P010_Y = 155, 146 FMT6_P010_UV = 156, 147 FMT6_TP10 = 157, 148 FMT6_TP10_Y = 158, 149 FMT6_TP10_UV = 159, 150 FMT6_Z24_UNORM_S8_UINT = 160, 151 FMT6_ETC2_RG11_UNORM = 171, 152 FMT6_ETC2_RG11_SNORM = 172, 153 FMT6_ETC2_R11_UNORM = 173, 154 FMT6_ETC2_R11_SNORM = 174, 155 FMT6_ETC1 = 175, 156 FMT6_ETC2_RGB8 = 176, 157 FMT6_ETC2_RGBA8 = 177, 158 FMT6_ETC2_RGB8A1 = 178, 159 FMT6_DXT1 = 179, 160 FMT6_DXT3 = 180, 161 FMT6_DXT5 = 181, 162 FMT6_RGTC1_UNORM = 183, 163 FMT6_RGTC1_SNORM = 184, 164 FMT6_RGTC2_UNORM = 187, 165 FMT6_RGTC2_SNORM = 188, 166 FMT6_BPTC_UFLOAT = 190, 167 FMT6_BPTC_FLOAT = 191, 168 FMT6_BPTC = 192, 169 FMT6_ASTC_4x4 = 193, 170 FMT6_ASTC_5x4 = 194, 171 FMT6_ASTC_5x5 = 195, 172 FMT6_ASTC_6x5 = 196, 173 FMT6_ASTC_6x6 = 197, 174 FMT6_ASTC_8x5 = 198, 175 FMT6_ASTC_8x6 = 199, 176 FMT6_ASTC_8x8 = 200, 177 FMT6_ASTC_10x5 = 201, 178 FMT6_ASTC_10x6 = 202, 179 FMT6_ASTC_10x8 = 203, 180 FMT6_ASTC_10x10 = 204, 181 FMT6_ASTC_12x10 = 205, 182 FMT6_ASTC_12x12 = 206, 183 FMT6_Z24_UINT_S8_UINT = 234, 184 FMT6_NONE = 255, 185 }; 186 187 enum a6xx_polygon_mode { 188 POLYMODE6_POINTS = 1, 189 POLYMODE6_LINES = 2, 190 POLYMODE6_TRIANGLES = 3, 191 }; 192 193 enum a6xx_depth_format { 194 DEPTH6_NONE = 0, 195 DEPTH6_16 = 1, 196 DEPTH6_24_8 = 2, 197 DEPTH6_32 = 4, 198 }; 199 200 enum a6xx_shader_id { 201 A6XX_TP0_TMO_DATA = 9, 202 A6XX_TP0_SMO_DATA = 10, 203 A6XX_TP0_MIPMAP_BASE_DATA = 11, 204 A6XX_TP1_TMO_DATA = 25, 205 A6XX_TP1_SMO_DATA = 26, 206 A6XX_TP1_MIPMAP_BASE_DATA = 27, 207 A6XX_SP_INST_DATA = 41, 208 A6XX_SP_LB_0_DATA = 42, 209 A6XX_SP_LB_1_DATA = 43, 210 A6XX_SP_LB_2_DATA = 44, 211 A6XX_SP_LB_3_DATA = 45, 212 A6XX_SP_LB_4_DATA = 46, 213 A6XX_SP_LB_5_DATA = 47, 214 A6XX_SP_CB_BINDLESS_DATA = 48, 215 A6XX_SP_CB_LEGACY_DATA = 49, 216 A6XX_SP_UAV_DATA = 50, 217 A6XX_SP_INST_TAG = 51, 218 A6XX_SP_CB_BINDLESS_TAG = 52, 219 A6XX_SP_TMO_UMO_TAG = 53, 220 A6XX_SP_SMO_TAG = 54, 221 A6XX_SP_STATE_DATA = 55, 222 A6XX_HLSQ_CHUNK_CVS_RAM = 73, 223 A6XX_HLSQ_CHUNK_CPS_RAM = 74, 224 A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75, 225 A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76, 226 A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77, 227 A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78, 228 A6XX_HLSQ_CVS_MISC_RAM = 80, 229 A6XX_HLSQ_CPS_MISC_RAM = 81, 230 A6XX_HLSQ_INST_RAM = 82, 231 A6XX_HLSQ_GFX_CVS_CONST_RAM = 83, 232 A6XX_HLSQ_GFX_CPS_CONST_RAM = 84, 233 A6XX_HLSQ_CVS_MISC_RAM_TAG = 85, 234 A6XX_HLSQ_CPS_MISC_RAM_TAG = 86, 235 A6XX_HLSQ_INST_RAM_TAG = 87, 236 A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88, 237 A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89, 238 A6XX_HLSQ_PWR_REST_RAM = 90, 239 A6XX_HLSQ_PWR_REST_TAG = 91, 240 A6XX_HLSQ_DATAPATH_META = 96, 241 A6XX_HLSQ_FRONTEND_META = 97, 242 A6XX_HLSQ_INDIRECT_META = 98, 243 A6XX_HLSQ_BACKEND_META = 99, 244 A6XX_SP_LB_6_DATA = 112, 245 A6XX_SP_LB_7_DATA = 113, 246 A6XX_HLSQ_INST_RAM_1 = 115, 247 }; 248 249 enum a6xx_debugbus_id { 250 A6XX_DBGBUS_CP = 1, 251 A6XX_DBGBUS_RBBM = 2, 252 A6XX_DBGBUS_VBIF = 3, 253 A6XX_DBGBUS_HLSQ = 4, 254 A6XX_DBGBUS_UCHE = 5, 255 A6XX_DBGBUS_DPM = 6, 256 A6XX_DBGBUS_TESS = 7, 257 A6XX_DBGBUS_PC = 8, 258 A6XX_DBGBUS_VFDP = 9, 259 A6XX_DBGBUS_VPC = 10, 260 A6XX_DBGBUS_TSE = 11, 261 A6XX_DBGBUS_RAS = 12, 262 A6XX_DBGBUS_VSC = 13, 263 A6XX_DBGBUS_COM = 14, 264 A6XX_DBGBUS_LRZ = 16, 265 A6XX_DBGBUS_A2D = 17, 266 A6XX_DBGBUS_CCUFCHE = 18, 267 A6XX_DBGBUS_GMU_CX = 19, 268 A6XX_DBGBUS_RBP = 20, 269 A6XX_DBGBUS_DCS = 21, 270 A6XX_DBGBUS_DBGC = 22, 271 A6XX_DBGBUS_CX = 23, 272 A6XX_DBGBUS_GMU_GX = 24, 273 A6XX_DBGBUS_TPFCHE = 25, 274 A6XX_DBGBUS_GBIF_GX = 26, 275 A6XX_DBGBUS_GPC = 29, 276 A6XX_DBGBUS_LARC = 30, 277 A6XX_DBGBUS_HLSQ_SPTP = 31, 278 A6XX_DBGBUS_RB_0 = 32, 279 A6XX_DBGBUS_RB_1 = 33, 280 A6XX_DBGBUS_RB_2 = 34, 281 A6XX_DBGBUS_UCHE_WRAPPER = 36, 282 A6XX_DBGBUS_CCU_0 = 40, 283 A6XX_DBGBUS_CCU_1 = 41, 284 A6XX_DBGBUS_CCU_2 = 42, 285 A6XX_DBGBUS_VFD_0 = 56, 286 A6XX_DBGBUS_VFD_1 = 57, 287 A6XX_DBGBUS_VFD_2 = 58, 288 A6XX_DBGBUS_VFD_3 = 59, 289 A6XX_DBGBUS_VFD_4 = 60, 290 A6XX_DBGBUS_VFD_5 = 61, 291 A6XX_DBGBUS_SP_0 = 64, 292 A6XX_DBGBUS_SP_1 = 65, 293 A6XX_DBGBUS_SP_2 = 66, 294 A6XX_DBGBUS_TPL1_0 = 72, 295 A6XX_DBGBUS_TPL1_1 = 73, 296 A6XX_DBGBUS_TPL1_2 = 74, 297 A6XX_DBGBUS_TPL1_3 = 75, 298 A6XX_DBGBUS_TPL1_4 = 76, 299 A6XX_DBGBUS_TPL1_5 = 77, 300 A6XX_DBGBUS_SPTP_0 = 88, 301 A6XX_DBGBUS_SPTP_1 = 89, 302 A6XX_DBGBUS_SPTP_2 = 90, 303 A6XX_DBGBUS_SPTP_3 = 91, 304 A6XX_DBGBUS_SPTP_4 = 92, 305 A6XX_DBGBUS_SPTP_5 = 93, 306 }; 307 308 enum a6xx_cp_perfcounter_select { 309 PERF_CP_ALWAYS_COUNT = 0, 310 PERF_CP_BUSY_GFX_CORE_IDLE = 1, 311 PERF_CP_BUSY_CYCLES = 2, 312 PERF_CP_NUM_PREEMPTIONS = 3, 313 PERF_CP_PREEMPTION_REACTION_DELAY = 4, 314 PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 5, 315 PERF_CP_PREEMPTION_SWITCH_IN_TIME = 6, 316 PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 7, 317 PERF_CP_PREDICATED_DRAWS_KILLED = 8, 318 PERF_CP_MODE_SWITCH = 9, 319 PERF_CP_ZPASS_DONE = 10, 320 PERF_CP_CONTEXT_DONE = 11, 321 PERF_CP_CACHE_FLUSH = 12, 322 PERF_CP_LONG_PREEMPTIONS = 13, 323 PERF_CP_SQE_I_CACHE_STARVE = 14, 324 PERF_CP_SQE_IDLE = 15, 325 PERF_CP_SQE_PM4_STARVE_RB_IB = 16, 326 PERF_CP_SQE_PM4_STARVE_SDS = 17, 327 PERF_CP_SQE_MRB_STARVE = 18, 328 PERF_CP_SQE_RRB_STARVE = 19, 329 PERF_CP_SQE_VSD_STARVE = 20, 330 PERF_CP_VSD_DECODE_STARVE = 21, 331 PERF_CP_SQE_PIPE_OUT_STALL = 22, 332 PERF_CP_SQE_SYNC_STALL = 23, 333 PERF_CP_SQE_PM4_WFI_STALL = 24, 334 PERF_CP_SQE_SYS_WFI_STALL = 25, 335 PERF_CP_SQE_T4_EXEC = 26, 336 PERF_CP_SQE_LOAD_STATE_EXEC = 27, 337 PERF_CP_SQE_SAVE_SDS_STATE = 28, 338 PERF_CP_SQE_DRAW_EXEC = 29, 339 PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 30, 340 PERF_CP_SQE_EXEC_PROFILED = 31, 341 PERF_CP_MEMORY_POOL_EMPTY = 32, 342 PERF_CP_MEMORY_POOL_SYNC_STALL = 33, 343 PERF_CP_MEMORY_POOL_ABOVE_THRESH = 34, 344 PERF_CP_AHB_WR_STALL_PRE_DRAWS = 35, 345 PERF_CP_AHB_STALL_SQE_GMU = 36, 346 PERF_CP_AHB_STALL_SQE_WR_OTHER = 37, 347 PERF_CP_AHB_STALL_SQE_RD_OTHER = 38, 348 PERF_CP_CLUSTER0_EMPTY = 39, 349 PERF_CP_CLUSTER1_EMPTY = 40, 350 PERF_CP_CLUSTER2_EMPTY = 41, 351 PERF_CP_CLUSTER3_EMPTY = 42, 352 PERF_CP_CLUSTER4_EMPTY = 43, 353 PERF_CP_CLUSTER5_EMPTY = 44, 354 PERF_CP_PM4_DATA = 45, 355 PERF_CP_PM4_HEADERS = 46, 356 PERF_CP_VBIF_READ_BEATS = 47, 357 PERF_CP_VBIF_WRITE_BEATS = 48, 358 PERF_CP_SQE_INSTR_COUNTER = 49, 359 }; 360 361 enum a6xx_rbbm_perfcounter_select { 362 PERF_RBBM_ALWAYS_COUNT = 0, 363 PERF_RBBM_ALWAYS_ON = 1, 364 PERF_RBBM_TSE_BUSY = 2, 365 PERF_RBBM_RAS_BUSY = 3, 366 PERF_RBBM_PC_DCALL_BUSY = 4, 367 PERF_RBBM_PC_VSD_BUSY = 5, 368 PERF_RBBM_STATUS_MASKED = 6, 369 PERF_RBBM_COM_BUSY = 7, 370 PERF_RBBM_DCOM_BUSY = 8, 371 PERF_RBBM_VBIF_BUSY = 9, 372 PERF_RBBM_VSC_BUSY = 10, 373 PERF_RBBM_TESS_BUSY = 11, 374 PERF_RBBM_UCHE_BUSY = 12, 375 PERF_RBBM_HLSQ_BUSY = 13, 376 }; 377 378 enum a6xx_pc_perfcounter_select { 379 PERF_PC_BUSY_CYCLES = 0, 380 PERF_PC_WORKING_CYCLES = 1, 381 PERF_PC_STALL_CYCLES_VFD = 2, 382 PERF_PC_STALL_CYCLES_TSE = 3, 383 PERF_PC_STALL_CYCLES_VPC = 4, 384 PERF_PC_STALL_CYCLES_UCHE = 5, 385 PERF_PC_STALL_CYCLES_TESS = 6, 386 PERF_PC_STALL_CYCLES_TSE_ONLY = 7, 387 PERF_PC_STALL_CYCLES_VPC_ONLY = 8, 388 PERF_PC_PASS1_TF_STALL_CYCLES = 9, 389 PERF_PC_STARVE_CYCLES_FOR_INDEX = 10, 390 PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11, 391 PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12, 392 PERF_PC_STARVE_CYCLES_FOR_POSITION = 13, 393 PERF_PC_STARVE_CYCLES_DI = 14, 394 PERF_PC_VIS_STREAMS_LOADED = 15, 395 PERF_PC_INSTANCES = 16, 396 PERF_PC_VPC_PRIMITIVES = 17, 397 PERF_PC_DEAD_PRIM = 18, 398 PERF_PC_LIVE_PRIM = 19, 399 PERF_PC_VERTEX_HITS = 20, 400 PERF_PC_IA_VERTICES = 21, 401 PERF_PC_IA_PRIMITIVES = 22, 402 PERF_PC_GS_PRIMITIVES = 23, 403 PERF_PC_HS_INVOCATIONS = 24, 404 PERF_PC_DS_INVOCATIONS = 25, 405 PERF_PC_VS_INVOCATIONS = 26, 406 PERF_PC_GS_INVOCATIONS = 27, 407 PERF_PC_DS_PRIMITIVES = 28, 408 PERF_PC_VPC_POS_DATA_TRANSACTION = 29, 409 PERF_PC_3D_DRAWCALLS = 30, 410 PERF_PC_2D_DRAWCALLS = 31, 411 PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32, 412 PERF_TESS_BUSY_CYCLES = 33, 413 PERF_TESS_WORKING_CYCLES = 34, 414 PERF_TESS_STALL_CYCLES_PC = 35, 415 PERF_TESS_STARVE_CYCLES_PC = 36, 416 PERF_PC_TSE_TRANSACTION = 37, 417 PERF_PC_TSE_VERTEX = 38, 418 PERF_PC_TESS_PC_UV_TRANS = 39, 419 PERF_PC_TESS_PC_UV_PATCHES = 40, 420 PERF_PC_TESS_FACTOR_TRANS = 41, 421 }; 422 423 enum a6xx_vfd_perfcounter_select { 424 PERF_VFD_BUSY_CYCLES = 0, 425 PERF_VFD_STALL_CYCLES_UCHE = 1, 426 PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2, 427 PERF_VFD_STALL_CYCLES_SP_INFO = 3, 428 PERF_VFD_STALL_CYCLES_SP_ATTR = 4, 429 PERF_VFD_STARVE_CYCLES_UCHE = 5, 430 PERF_VFD_RBUFFER_FULL = 6, 431 PERF_VFD_ATTR_INFO_FIFO_FULL = 7, 432 PERF_VFD_DECODED_ATTRIBUTE_BYTES = 8, 433 PERF_VFD_NUM_ATTRIBUTES = 9, 434 PERF_VFD_UPPER_SHADER_FIBERS = 10, 435 PERF_VFD_LOWER_SHADER_FIBERS = 11, 436 PERF_VFD_MODE_0_FIBERS = 12, 437 PERF_VFD_MODE_1_FIBERS = 13, 438 PERF_VFD_MODE_2_FIBERS = 14, 439 PERF_VFD_MODE_3_FIBERS = 15, 440 PERF_VFD_MODE_4_FIBERS = 16, 441 PERF_VFD_TOTAL_VERTICES = 17, 442 PERF_VFDP_STALL_CYCLES_VFD = 18, 443 PERF_VFDP_STALL_CYCLES_VFD_INDEX = 19, 444 PERF_VFDP_STALL_CYCLES_VFD_PROG = 20, 445 PERF_VFDP_STARVE_CYCLES_PC = 21, 446 PERF_VFDP_VS_STAGE_WAVES = 22, 447 }; 448 449 enum a6xx_hlsq_perfcounter_select { 450 PERF_HLSQ_BUSY_CYCLES = 0, 451 PERF_HLSQ_STALL_CYCLES_UCHE = 1, 452 PERF_HLSQ_STALL_CYCLES_SP_STATE = 2, 453 PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3, 454 PERF_HLSQ_UCHE_LATENCY_CYCLES = 4, 455 PERF_HLSQ_UCHE_LATENCY_COUNT = 5, 456 PERF_HLSQ_FS_STAGE_1X_WAVES = 6, 457 PERF_HLSQ_FS_STAGE_2X_WAVES = 7, 458 PERF_HLSQ_QUADS = 8, 459 PERF_HLSQ_CS_INVOCATIONS = 9, 460 PERF_HLSQ_COMPUTE_DRAWCALLS = 10, 461 PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11, 462 PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12, 463 PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13, 464 PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14, 465 PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15, 466 PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16, 467 PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17, 468 PERF_HLSQ_STALL_CYCLES_VPC = 18, 469 PERF_HLSQ_PIXELS = 19, 470 PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = 20, 471 }; 472 473 enum a6xx_vpc_perfcounter_select { 474 PERF_VPC_BUSY_CYCLES = 0, 475 PERF_VPC_WORKING_CYCLES = 1, 476 PERF_VPC_STALL_CYCLES_UCHE = 2, 477 PERF_VPC_STALL_CYCLES_VFD_WACK = 3, 478 PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4, 479 PERF_VPC_STALL_CYCLES_PC = 5, 480 PERF_VPC_STALL_CYCLES_SP_LM = 6, 481 PERF_VPC_STARVE_CYCLES_SP = 7, 482 PERF_VPC_STARVE_CYCLES_LRZ = 8, 483 PERF_VPC_PC_PRIMITIVES = 9, 484 PERF_VPC_SP_COMPONENTS = 10, 485 PERF_VPC_STALL_CYCLES_VPCRAM_POS = 11, 486 PERF_VPC_LRZ_ASSIGN_PRIMITIVES = 12, 487 PERF_VPC_RB_VISIBLE_PRIMITIVES = 13, 488 PERF_VPC_LM_TRANSACTION = 14, 489 PERF_VPC_STREAMOUT_TRANSACTION = 15, 490 PERF_VPC_VS_BUSY_CYCLES = 16, 491 PERF_VPC_PS_BUSY_CYCLES = 17, 492 PERF_VPC_VS_WORKING_CYCLES = 18, 493 PERF_VPC_PS_WORKING_CYCLES = 19, 494 PERF_VPC_STARVE_CYCLES_RB = 20, 495 PERF_VPC_NUM_VPCRAM_READ_POS = 21, 496 PERF_VPC_WIT_FULL_CYCLES = 22, 497 PERF_VPC_VPCRAM_FULL_CYCLES = 23, 498 PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = 24, 499 PERF_VPC_NUM_VPCRAM_WRITE = 25, 500 PERF_VPC_NUM_VPCRAM_READ_SO = 26, 501 PERF_VPC_NUM_ATTR_REQ_LM = 27, 502 }; 503 504 enum a6xx_tse_perfcounter_select { 505 PERF_TSE_BUSY_CYCLES = 0, 506 PERF_TSE_CLIPPING_CYCLES = 1, 507 PERF_TSE_STALL_CYCLES_RAS = 2, 508 PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3, 509 PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4, 510 PERF_TSE_STARVE_CYCLES_PC = 5, 511 PERF_TSE_INPUT_PRIM = 6, 512 PERF_TSE_INPUT_NULL_PRIM = 7, 513 PERF_TSE_TRIVAL_REJ_PRIM = 8, 514 PERF_TSE_CLIPPED_PRIM = 9, 515 PERF_TSE_ZERO_AREA_PRIM = 10, 516 PERF_TSE_FACENESS_CULLED_PRIM = 11, 517 PERF_TSE_ZERO_PIXEL_PRIM = 12, 518 PERF_TSE_OUTPUT_NULL_PRIM = 13, 519 PERF_TSE_OUTPUT_VISIBLE_PRIM = 14, 520 PERF_TSE_CINVOCATION = 15, 521 PERF_TSE_CPRIMITIVES = 16, 522 PERF_TSE_2D_INPUT_PRIM = 17, 523 PERF_TSE_2D_ALIVE_CYCLES = 18, 524 PERF_TSE_CLIP_PLANES = 19, 525 }; 526 527 enum a6xx_ras_perfcounter_select { 528 PERF_RAS_BUSY_CYCLES = 0, 529 PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1, 530 PERF_RAS_STALL_CYCLES_LRZ = 2, 531 PERF_RAS_STARVE_CYCLES_TSE = 3, 532 PERF_RAS_SUPER_TILES = 4, 533 PERF_RAS_8X4_TILES = 5, 534 PERF_RAS_MASKGEN_ACTIVE = 6, 535 PERF_RAS_FULLY_COVERED_SUPER_TILES = 7, 536 PERF_RAS_FULLY_COVERED_8X4_TILES = 8, 537 PERF_RAS_PRIM_KILLED_INVISILBE = 9, 538 PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 10, 539 PERF_RAS_LRZ_INTF_WORKING_CYCLES = 11, 540 PERF_RAS_BLOCKS = 12, 541 }; 542 543 enum a6xx_uche_perfcounter_select { 544 PERF_UCHE_BUSY_CYCLES = 0, 545 PERF_UCHE_STALL_CYCLES_ARBITER = 1, 546 PERF_UCHE_VBIF_LATENCY_CYCLES = 2, 547 PERF_UCHE_VBIF_LATENCY_SAMPLES = 3, 548 PERF_UCHE_VBIF_READ_BEATS_TP = 4, 549 PERF_UCHE_VBIF_READ_BEATS_VFD = 5, 550 PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6, 551 PERF_UCHE_VBIF_READ_BEATS_LRZ = 7, 552 PERF_UCHE_VBIF_READ_BEATS_SP = 8, 553 PERF_UCHE_READ_REQUESTS_TP = 9, 554 PERF_UCHE_READ_REQUESTS_VFD = 10, 555 PERF_UCHE_READ_REQUESTS_HLSQ = 11, 556 PERF_UCHE_READ_REQUESTS_LRZ = 12, 557 PERF_UCHE_READ_REQUESTS_SP = 13, 558 PERF_UCHE_WRITE_REQUESTS_LRZ = 14, 559 PERF_UCHE_WRITE_REQUESTS_SP = 15, 560 PERF_UCHE_WRITE_REQUESTS_VPC = 16, 561 PERF_UCHE_WRITE_REQUESTS_VSC = 17, 562 PERF_UCHE_EVICTS = 18, 563 PERF_UCHE_BANK_REQ0 = 19, 564 PERF_UCHE_BANK_REQ1 = 20, 565 PERF_UCHE_BANK_REQ2 = 21, 566 PERF_UCHE_BANK_REQ3 = 22, 567 PERF_UCHE_BANK_REQ4 = 23, 568 PERF_UCHE_BANK_REQ5 = 24, 569 PERF_UCHE_BANK_REQ6 = 25, 570 PERF_UCHE_BANK_REQ7 = 26, 571 PERF_UCHE_VBIF_READ_BEATS_CH0 = 27, 572 PERF_UCHE_VBIF_READ_BEATS_CH1 = 28, 573 PERF_UCHE_GMEM_READ_BEATS = 29, 574 PERF_UCHE_TPH_REF_FULL = 30, 575 PERF_UCHE_TPH_VICTIM_FULL = 31, 576 PERF_UCHE_TPH_EXT_FULL = 32, 577 PERF_UCHE_VBIF_STALL_WRITE_DATA = 33, 578 PERF_UCHE_DCMP_LATENCY_SAMPLES = 34, 579 PERF_UCHE_DCMP_LATENCY_CYCLES = 35, 580 PERF_UCHE_VBIF_READ_BEATS_PC = 36, 581 PERF_UCHE_READ_REQUESTS_PC = 37, 582 PERF_UCHE_RAM_READ_REQ = 38, 583 PERF_UCHE_RAM_WRITE_REQ = 39, 584 }; 585 586 enum a6xx_tp_perfcounter_select { 587 PERF_TP_BUSY_CYCLES = 0, 588 PERF_TP_STALL_CYCLES_UCHE = 1, 589 PERF_TP_LATENCY_CYCLES = 2, 590 PERF_TP_LATENCY_TRANS = 3, 591 PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4, 592 PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5, 593 PERF_TP_L1_CACHELINE_REQUESTS = 6, 594 PERF_TP_L1_CACHELINE_MISSES = 7, 595 PERF_TP_SP_TP_TRANS = 8, 596 PERF_TP_TP_SP_TRANS = 9, 597 PERF_TP_OUTPUT_PIXELS = 10, 598 PERF_TP_FILTER_WORKLOAD_16BIT = 11, 599 PERF_TP_FILTER_WORKLOAD_32BIT = 12, 600 PERF_TP_QUADS_RECEIVED = 13, 601 PERF_TP_QUADS_OFFSET = 14, 602 PERF_TP_QUADS_SHADOW = 15, 603 PERF_TP_QUADS_ARRAY = 16, 604 PERF_TP_QUADS_GRADIENT = 17, 605 PERF_TP_QUADS_1D = 18, 606 PERF_TP_QUADS_2D = 19, 607 PERF_TP_QUADS_BUFFER = 20, 608 PERF_TP_QUADS_3D = 21, 609 PERF_TP_QUADS_CUBE = 22, 610 PERF_TP_DIVERGENT_QUADS_RECEIVED = 23, 611 PERF_TP_PRT_NON_RESIDENT_EVENTS = 24, 612 PERF_TP_OUTPUT_PIXELS_POINT = 25, 613 PERF_TP_OUTPUT_PIXELS_BILINEAR = 26, 614 PERF_TP_OUTPUT_PIXELS_MIP = 27, 615 PERF_TP_OUTPUT_PIXELS_ANISO = 28, 616 PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 29, 617 PERF_TP_FLAG_CACHE_REQUESTS = 30, 618 PERF_TP_FLAG_CACHE_MISSES = 31, 619 PERF_TP_L1_5_L2_REQUESTS = 32, 620 PERF_TP_2D_OUTPUT_PIXELS = 33, 621 PERF_TP_2D_OUTPUT_PIXELS_POINT = 34, 622 PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 35, 623 PERF_TP_2D_FILTER_WORKLOAD_16BIT = 36, 624 PERF_TP_2D_FILTER_WORKLOAD_32BIT = 37, 625 PERF_TP_TPA2TPC_TRANS = 38, 626 PERF_TP_L1_MISSES_ASTC_1TILE = 39, 627 PERF_TP_L1_MISSES_ASTC_2TILE = 40, 628 PERF_TP_L1_MISSES_ASTC_4TILE = 41, 629 PERF_TP_L1_5_L2_COMPRESS_REQS = 42, 630 PERF_TP_L1_5_L2_COMPRESS_MISS = 43, 631 PERF_TP_L1_BANK_CONFLICT = 44, 632 PERF_TP_L1_5_MISS_LATENCY_CYCLES = 45, 633 PERF_TP_L1_5_MISS_LATENCY_TRANS = 46, 634 PERF_TP_QUADS_CONSTANT_MULTIPLIED = 47, 635 PERF_TP_FRONTEND_WORKING_CYCLES = 48, 636 PERF_TP_L1_TAG_WORKING_CYCLES = 49, 637 PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 50, 638 PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 51, 639 PERF_TP_BACKEND_WORKING_CYCLES = 52, 640 PERF_TP_FLAG_CACHE_WORKING_CYCLES = 53, 641 PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54, 642 PERF_TP_STARVE_CYCLES_SP = 55, 643 PERF_TP_STARVE_CYCLES_UCHE = 56, 644 }; 645 646 enum a6xx_sp_perfcounter_select { 647 PERF_SP_BUSY_CYCLES = 0, 648 PERF_SP_ALU_WORKING_CYCLES = 1, 649 PERF_SP_EFU_WORKING_CYCLES = 2, 650 PERF_SP_STALL_CYCLES_VPC = 3, 651 PERF_SP_STALL_CYCLES_TP = 4, 652 PERF_SP_STALL_CYCLES_UCHE = 5, 653 PERF_SP_STALL_CYCLES_RB = 6, 654 PERF_SP_NON_EXECUTION_CYCLES = 7, 655 PERF_SP_WAVE_CONTEXTS = 8, 656 PERF_SP_WAVE_CONTEXT_CYCLES = 9, 657 PERF_SP_FS_STAGE_WAVE_CYCLES = 10, 658 PERF_SP_FS_STAGE_WAVE_SAMPLES = 11, 659 PERF_SP_VS_STAGE_WAVE_CYCLES = 12, 660 PERF_SP_VS_STAGE_WAVE_SAMPLES = 13, 661 PERF_SP_FS_STAGE_DURATION_CYCLES = 14, 662 PERF_SP_VS_STAGE_DURATION_CYCLES = 15, 663 PERF_SP_WAVE_CTRL_CYCLES = 16, 664 PERF_SP_WAVE_LOAD_CYCLES = 17, 665 PERF_SP_WAVE_EMIT_CYCLES = 18, 666 PERF_SP_WAVE_NOP_CYCLES = 19, 667 PERF_SP_WAVE_WAIT_CYCLES = 20, 668 PERF_SP_WAVE_FETCH_CYCLES = 21, 669 PERF_SP_WAVE_IDLE_CYCLES = 22, 670 PERF_SP_WAVE_END_CYCLES = 23, 671 PERF_SP_WAVE_LONG_SYNC_CYCLES = 24, 672 PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25, 673 PERF_SP_WAVE_JOIN_CYCLES = 26, 674 PERF_SP_LM_LOAD_INSTRUCTIONS = 27, 675 PERF_SP_LM_STORE_INSTRUCTIONS = 28, 676 PERF_SP_LM_ATOMICS = 29, 677 PERF_SP_GM_LOAD_INSTRUCTIONS = 30, 678 PERF_SP_GM_STORE_INSTRUCTIONS = 31, 679 PERF_SP_GM_ATOMICS = 32, 680 PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33, 681 PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34, 682 PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35, 683 PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36, 684 PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37, 685 PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38, 686 PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39, 687 PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40, 688 PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41, 689 PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42, 690 PERF_SP_VS_INSTRUCTIONS = 43, 691 PERF_SP_FS_INSTRUCTIONS = 44, 692 PERF_SP_ADDR_LOCK_COUNT = 45, 693 PERF_SP_UCHE_READ_TRANS = 46, 694 PERF_SP_UCHE_WRITE_TRANS = 47, 695 PERF_SP_EXPORT_VPC_TRANS = 48, 696 PERF_SP_EXPORT_RB_TRANS = 49, 697 PERF_SP_PIXELS_KILLED = 50, 698 PERF_SP_ICL1_REQUESTS = 51, 699 PERF_SP_ICL1_MISSES = 52, 700 PERF_SP_HS_INSTRUCTIONS = 53, 701 PERF_SP_DS_INSTRUCTIONS = 54, 702 PERF_SP_GS_INSTRUCTIONS = 55, 703 PERF_SP_CS_INSTRUCTIONS = 56, 704 PERF_SP_GPR_READ = 57, 705 PERF_SP_GPR_WRITE = 58, 706 PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59, 707 PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60, 708 PERF_SP_LM_BANK_CONFLICTS = 61, 709 PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62, 710 PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63, 711 PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64, 712 PERF_SP_LM_WORKING_CYCLES = 65, 713 PERF_SP_DISPATCHER_WORKING_CYCLES = 66, 714 PERF_SP_SEQUENCER_WORKING_CYCLES = 67, 715 PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68, 716 PERF_SP_STARVE_CYCLES_HLSQ = 69, 717 PERF_SP_NON_EXECUTION_LS_CYCLES = 70, 718 PERF_SP_WORKING_EU = 71, 719 PERF_SP_ANY_EU_WORKING = 72, 720 PERF_SP_WORKING_EU_FS_STAGE = 73, 721 PERF_SP_ANY_EU_WORKING_FS_STAGE = 74, 722 PERF_SP_WORKING_EU_VS_STAGE = 75, 723 PERF_SP_ANY_EU_WORKING_VS_STAGE = 76, 724 PERF_SP_WORKING_EU_CS_STAGE = 77, 725 PERF_SP_ANY_EU_WORKING_CS_STAGE = 78, 726 PERF_SP_GPR_READ_PREFETCH = 79, 727 PERF_SP_GPR_READ_CONFLICT = 80, 728 PERF_SP_GPR_WRITE_CONFLICT = 81, 729 PERF_SP_GM_LOAD_LATENCY_CYCLES = 82, 730 PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83, 731 PERF_SP_EXECUTABLE_WAVES = 84, 732 }; 733 734 enum a6xx_rb_perfcounter_select { 735 PERF_RB_BUSY_CYCLES = 0, 736 PERF_RB_STALL_CYCLES_HLSQ = 1, 737 PERF_RB_STALL_CYCLES_FIFO0_FULL = 2, 738 PERF_RB_STALL_CYCLES_FIFO1_FULL = 3, 739 PERF_RB_STALL_CYCLES_FIFO2_FULL = 4, 740 PERF_RB_STARVE_CYCLES_SP = 5, 741 PERF_RB_STARVE_CYCLES_LRZ_TILE = 6, 742 PERF_RB_STARVE_CYCLES_CCU = 7, 743 PERF_RB_STARVE_CYCLES_Z_PLANE = 8, 744 PERF_RB_STARVE_CYCLES_BARY_PLANE = 9, 745 PERF_RB_Z_WORKLOAD = 10, 746 PERF_RB_HLSQ_ACTIVE = 11, 747 PERF_RB_Z_READ = 12, 748 PERF_RB_Z_WRITE = 13, 749 PERF_RB_C_READ = 14, 750 PERF_RB_C_WRITE = 15, 751 PERF_RB_TOTAL_PASS = 16, 752 PERF_RB_Z_PASS = 17, 753 PERF_RB_Z_FAIL = 18, 754 PERF_RB_S_FAIL = 19, 755 PERF_RB_BLENDED_FXP_COMPONENTS = 20, 756 PERF_RB_BLENDED_FP16_COMPONENTS = 21, 757 PERF_RB_PS_INVOCATIONS = 22, 758 PERF_RB_2D_ALIVE_CYCLES = 23, 759 PERF_RB_2D_STALL_CYCLES_A2D = 24, 760 PERF_RB_2D_STARVE_CYCLES_SRC = 25, 761 PERF_RB_2D_STARVE_CYCLES_SP = 26, 762 PERF_RB_2D_STARVE_CYCLES_DST = 27, 763 PERF_RB_2D_VALID_PIXELS = 28, 764 PERF_RB_3D_PIXELS = 29, 765 PERF_RB_BLENDER_WORKING_CYCLES = 30, 766 PERF_RB_ZPROC_WORKING_CYCLES = 31, 767 PERF_RB_CPROC_WORKING_CYCLES = 32, 768 PERF_RB_SAMPLER_WORKING_CYCLES = 33, 769 PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 34, 770 PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 35, 771 PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 36, 772 PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 37, 773 PERF_RB_STALL_CYCLES_VPC = 38, 774 PERF_RB_2D_INPUT_TRANS = 39, 775 PERF_RB_2D_OUTPUT_RB_DST_TRANS = 40, 776 PERF_RB_2D_OUTPUT_RB_SRC_TRANS = 41, 777 PERF_RB_BLENDED_FP32_COMPONENTS = 42, 778 PERF_RB_COLOR_PIX_TILES = 43, 779 PERF_RB_STALL_CYCLES_CCU = 44, 780 PERF_RB_EARLY_Z_ARB3_GRANT = 45, 781 PERF_RB_LATE_Z_ARB3_GRANT = 46, 782 PERF_RB_EARLY_Z_SKIP_GRANT = 47, 783 }; 784 785 enum a6xx_vsc_perfcounter_select { 786 PERF_VSC_BUSY_CYCLES = 0, 787 PERF_VSC_WORKING_CYCLES = 1, 788 PERF_VSC_STALL_CYCLES_UCHE = 2, 789 PERF_VSC_EOT_NUM = 3, 790 PERF_VSC_INPUT_TILES = 4, 791 }; 792 793 enum a6xx_ccu_perfcounter_select { 794 PERF_CCU_BUSY_CYCLES = 0, 795 PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1, 796 PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2, 797 PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3, 798 PERF_CCU_DEPTH_BLOCKS = 4, 799 PERF_CCU_COLOR_BLOCKS = 5, 800 PERF_CCU_DEPTH_BLOCK_HIT = 6, 801 PERF_CCU_COLOR_BLOCK_HIT = 7, 802 PERF_CCU_PARTIAL_BLOCK_READ = 8, 803 PERF_CCU_GMEM_READ = 9, 804 PERF_CCU_GMEM_WRITE = 10, 805 PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11, 806 PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12, 807 PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13, 808 PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14, 809 PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15, 810 PERF_CCU_DEPTH_READ_FLAG5_COUNT = 16, 811 PERF_CCU_DEPTH_READ_FLAG6_COUNT = 17, 812 PERF_CCU_DEPTH_READ_FLAG8_COUNT = 18, 813 PERF_CCU_COLOR_READ_FLAG0_COUNT = 19, 814 PERF_CCU_COLOR_READ_FLAG1_COUNT = 20, 815 PERF_CCU_COLOR_READ_FLAG2_COUNT = 21, 816 PERF_CCU_COLOR_READ_FLAG3_COUNT = 22, 817 PERF_CCU_COLOR_READ_FLAG4_COUNT = 23, 818 PERF_CCU_COLOR_READ_FLAG5_COUNT = 24, 819 PERF_CCU_COLOR_READ_FLAG6_COUNT = 25, 820 PERF_CCU_COLOR_READ_FLAG8_COUNT = 26, 821 PERF_CCU_2D_RD_REQ = 27, 822 PERF_CCU_2D_WR_REQ = 28, 823 }; 824 825 enum a6xx_lrz_perfcounter_select { 826 PERF_LRZ_BUSY_CYCLES = 0, 827 PERF_LRZ_STARVE_CYCLES_RAS = 1, 828 PERF_LRZ_STALL_CYCLES_RB = 2, 829 PERF_LRZ_STALL_CYCLES_VSC = 3, 830 PERF_LRZ_STALL_CYCLES_VPC = 4, 831 PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5, 832 PERF_LRZ_STALL_CYCLES_UCHE = 6, 833 PERF_LRZ_LRZ_READ = 7, 834 PERF_LRZ_LRZ_WRITE = 8, 835 PERF_LRZ_READ_LATENCY = 9, 836 PERF_LRZ_MERGE_CACHE_UPDATING = 10, 837 PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11, 838 PERF_LRZ_PRIM_KILLED_BY_LRZ = 12, 839 PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13, 840 PERF_LRZ_FULL_8X8_TILES = 14, 841 PERF_LRZ_PARTIAL_8X8_TILES = 15, 842 PERF_LRZ_TILE_KILLED = 16, 843 PERF_LRZ_TOTAL_PIXEL = 17, 844 PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18, 845 PERF_LRZ_FULLY_COVERED_TILES = 19, 846 PERF_LRZ_PARTIAL_COVERED_TILES = 20, 847 PERF_LRZ_FEEDBACK_ACCEPT = 21, 848 PERF_LRZ_FEEDBACK_DISCARD = 22, 849 PERF_LRZ_FEEDBACK_STALL = 23, 850 PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 24, 851 PERF_LRZ_STALL_CYCLES_RB_BPLANE = 25, 852 PERF_LRZ_STALL_CYCLES_VC = 26, 853 PERF_LRZ_RAS_MASK_TRANS = 27, 854 }; 855 856 enum a6xx_cmp_perfcounter_select { 857 PERF_CMPDECMP_STALL_CYCLES_ARB = 0, 858 PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1, 859 PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2, 860 PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3, 861 PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4, 862 PERF_CMPDECMP_VBIF_READ_REQUEST = 5, 863 PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6, 864 PERF_CMPDECMP_VBIF_READ_DATA = 7, 865 PERF_CMPDECMP_VBIF_WRITE_DATA = 8, 866 PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9, 867 PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10, 868 PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11, 869 PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12, 870 PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13, 871 PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14, 872 PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 15, 873 PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 16, 874 PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 17, 875 PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 18, 876 PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 19, 877 PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 20, 878 PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 21, 879 PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 22, 880 PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 23, 881 PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 24, 882 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 25, 883 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 26, 884 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 27, 885 PERF_CMPDECMP_2D_RD_DATA = 28, 886 PERF_CMPDECMP_2D_WR_DATA = 29, 887 PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 30, 888 PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 31, 889 PERF_CMPDECMP_2D_OUTPUT_TRANS = 32, 890 PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 33, 891 PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 34, 892 PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 35, 893 PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 36, 894 PERF_CMPDECMP_2D_BUSY_CYCLES = 37, 895 PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = 38, 896 PERF_CMPDECMP_2D_PIXELS = 39, 897 }; 898 899 enum a6xx_2d_ifmt { 900 R2D_UNORM8 = 16, 901 R2D_INT32 = 7, 902 R2D_INT16 = 6, 903 R2D_INT8 = 5, 904 R2D_FLOAT32 = 4, 905 R2D_FLOAT16 = 3, 906 R2D_UNORM8_SRGB = 1, 907 R2D_RAW = 0, 908 }; 909 910 enum a6xx_ztest_mode { 911 A6XX_EARLY_Z = 0, 912 A6XX_LATE_Z = 1, 913 A6XX_EARLY_LRZ_LATE_Z = 2, 914 }; 915 916 enum a6xx_sequenced_thread_dist { 917 DIST_SCREEN_COORD = 0, 918 DIST_ALL_TO_RB0 = 1, 919 }; 920 921 enum a6xx_single_prim_mode { 922 NO_FLUSH = 0, 923 FLUSH_PER_OVERLAP_AND_OVERWRITE = 1, 924 FLUSH_PER_OVERLAP = 3, 925 }; 926 927 enum a6xx_raster_mode { 928 TYPE_TILED = 0, 929 TYPE_WRITER = 1, 930 }; 931 932 enum a6xx_raster_direction { 933 LR_TB = 0, 934 RL_TB = 1, 935 LR_BT = 2, 936 RB_BT = 3, 937 }; 938 939 enum a6xx_render_mode { 940 RENDERING_PASS = 0, 941 BINNING_PASS = 1, 942 }; 943 944 enum a6xx_buffers_location { 945 BUFFERS_IN_GMEM = 0, 946 BUFFERS_IN_SYSMEM = 3, 947 }; 948 949 enum a6xx_fragcoord_sample_mode { 950 FRAGCOORD_CENTER = 0, 951 FRAGCOORD_SAMPLE = 3, 952 }; 953 954 enum a6xx_rotation { 955 ROTATE_0 = 0, 956 ROTATE_90 = 1, 957 ROTATE_180 = 2, 958 ROTATE_270 = 3, 959 ROTATE_HFLIP = 4, 960 ROTATE_VFLIP = 5, 961 }; 962 963 enum a6xx_tess_spacing { 964 TESS_EQUAL = 0, 965 TESS_FRACTIONAL_ODD = 2, 966 TESS_FRACTIONAL_EVEN = 3, 967 }; 968 969 enum a6xx_tess_output { 970 TESS_POINTS = 0, 971 TESS_LINES = 1, 972 TESS_CW_TRIS = 2, 973 TESS_CCW_TRIS = 3, 974 }; 975 976 enum a6xx_threadsize { 977 THREAD64 = 0, 978 THREAD128 = 1, 979 }; 980 981 enum a6xx_isam_mode { 982 ISAMMODE_GL = 2, 983 }; 984 985 enum a6xx_tex_filter { 986 A6XX_TEX_NEAREST = 0, 987 A6XX_TEX_LINEAR = 1, 988 A6XX_TEX_ANISO = 2, 989 A6XX_TEX_CUBIC = 3, 990 }; 991 992 enum a6xx_tex_clamp { 993 A6XX_TEX_REPEAT = 0, 994 A6XX_TEX_CLAMP_TO_EDGE = 1, 995 A6XX_TEX_MIRROR_REPEAT = 2, 996 A6XX_TEX_CLAMP_TO_BORDER = 3, 997 A6XX_TEX_MIRROR_CLAMP = 4, 998 }; 999 1000 enum a6xx_tex_aniso { 1001 A6XX_TEX_ANISO_1 = 0, 1002 A6XX_TEX_ANISO_2 = 1, 1003 A6XX_TEX_ANISO_4 = 2, 1004 A6XX_TEX_ANISO_8 = 3, 1005 A6XX_TEX_ANISO_16 = 4, 1006 }; 1007 1008 enum a6xx_reduction_mode { 1009 A6XX_REDUCTION_MODE_AVERAGE = 0, 1010 A6XX_REDUCTION_MODE_MIN = 1, 1011 A6XX_REDUCTION_MODE_MAX = 2, 1012 }; 1013 1014 enum a6xx_tex_swiz { 1015 A6XX_TEX_X = 0, 1016 A6XX_TEX_Y = 1, 1017 A6XX_TEX_Z = 2, 1018 A6XX_TEX_W = 3, 1019 A6XX_TEX_ZERO = 4, 1020 A6XX_TEX_ONE = 5, 1021 }; 1022 1023 enum a6xx_tex_type { 1024 A6XX_TEX_1D = 0, 1025 A6XX_TEX_2D = 1, 1026 A6XX_TEX_CUBE = 2, 1027 A6XX_TEX_3D = 3, 1028 A6XX_TEX_BUFFER = 4, 1029 }; 1030 1031 #define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001 1032 #define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR 0x00000002 1033 #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW 0x00000040 1034 #define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080 1035 #define A6XX_RBBM_INT_0_MASK_CP_SW 0x00000100 1036 #define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200 1037 #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400 1038 #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800 1039 #define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000 1040 #define A6XX_RBBM_INT_0_MASK_CP_IB2 0x00002000 1041 #define A6XX_RBBM_INT_0_MASK_CP_IB1 0x00004000 1042 #define A6XX_RBBM_INT_0_MASK_CP_RB 0x00008000 1043 #define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000 1044 #define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000 1045 #define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000 1046 #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000 1047 #define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT 0x00800000 1048 #define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000 1049 #define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000 1050 #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000 1051 #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000 1052 #define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000 1053 #define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000 1054 #define A6XX_CP_INT_CP_OPCODE_ERROR 0x00000001 1055 #define A6XX_CP_INT_CP_UCODE_ERROR 0x00000002 1056 #define A6XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004 1057 #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010 1058 #define A6XX_CP_INT_CP_AHB_ERROR 0x00000020 1059 #define A6XX_CP_INT_CP_VSD_PARITY_ERROR 0x00000040 1060 #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR 0x00000080 1061 #define REG_A6XX_CP_RB_BASE 0x00000800 1062 1063 #define REG_A6XX_CP_RB_BASE_HI 0x00000801 1064 1065 #define REG_A6XX_CP_RB_CNTL 0x00000802 1066 1067 #define REG_A6XX_CP_RB_RPTR_ADDR_LO 0x00000804 1068 1069 #define REG_A6XX_CP_RB_RPTR_ADDR_HI 0x00000805 1070 1071 #define REG_A6XX_CP_RB_RPTR 0x00000806 1072 1073 #define REG_A6XX_CP_RB_WPTR 0x00000807 1074 1075 #define REG_A6XX_CP_SQE_CNTL 0x00000808 1076 1077 #define REG_A6XX_CP_CP2GMU_STATUS 0x00000812 1078 #define A6XX_CP_CP2GMU_STATUS_IFPC 0x00000001 1079 1080 #define REG_A6XX_CP_HW_FAULT 0x00000821 1081 1082 #define REG_A6XX_CP_INTERRUPT_STATUS 0x00000823 1083 1084 #define REG_A6XX_CP_PROTECT_STATUS 0x00000824 1085 1086 #define REG_A6XX_CP_SQE_INSTR_BASE 0x00000830 1087 1088 #define REG_A6XX_CP_MISC_CNTL 0x00000840 1089 1090 #define REG_A6XX_CP_CHICKEN_DBG 0x00000841 1091 1092 #define REG_A6XX_CP_APRIV_CNTL 0x00000844 1093 1094 #define REG_A6XX_CP_ROQ_THRESHOLDS_1 0x000008c1 1095 #define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK 0x000000ff 1096 #define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT 0 1097 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_LO(uint32_t val) 1098 { 1099 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK; 1100 } 1101 #define A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MASK 0x0000ff00 1102 #define A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__SHIFT 8 1103 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_HI(uint32_t val) 1104 { 1105 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MASK; 1106 } 1107 #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK 0x00ff0000 1108 #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT 16 1109 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val) 1110 { 1111 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK; 1112 } 1113 #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK 0xff000000 1114 #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT 24 1115 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val) 1116 { 1117 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK; 1118 } 1119 1120 #define REG_A6XX_CP_ROQ_THRESHOLDS_2 0x000008c2 1121 #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK 0x000001ff 1122 #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT 0 1123 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val) 1124 { 1125 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK; 1126 } 1127 #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK 0xffff0000 1128 #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT 16 1129 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val) 1130 { 1131 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK; 1132 } 1133 1134 #define REG_A6XX_CP_MEM_POOL_SIZE 0x000008c3 1135 1136 #define REG_A6XX_CP_CHICKEN_DBG 0x00000841 1137 1138 #define REG_A6XX_CP_ADDR_MODE_CNTL 0x00000842 1139 1140 #define REG_A6XX_CP_DBG_ECO_CNTL 0x00000843 1141 1142 #define REG_A6XX_CP_PROTECT_CNTL 0x0000084f 1143 1144 static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; } 1145 1146 static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; } 1147 1148 static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; } 1149 1150 static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; } 1151 #define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0003ffff 1152 #define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0 1153 static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) 1154 { 1155 return ((val) << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK; 1156 } 1157 #define A6XX_CP_PROTECT_REG_MASK_LEN__MASK 0x7ffc0000 1158 #define A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT 18 1159 static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) 1160 { 1161 return ((val) << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK; 1162 } 1163 #define A6XX_CP_PROTECT_REG_READ 0x80000000 1164 1165 #define REG_A6XX_CP_CONTEXT_SWITCH_CNTL 0x000008a0 1166 1167 #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x000008a1 1168 1169 #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x000008a2 1170 1171 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO 0x000008a3 1172 1173 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI 0x000008a4 1174 1175 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO 0x000008a5 1176 1177 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI 0x000008a6 1178 1179 #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO 0x000008a7 1180 1181 #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI 0x000008a8 1182 1183 static inline uint32_t REG_A6XX_CP_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008d0 + 0x1*i0; } 1184 1185 #define REG_A6XX_CP_CRASH_SCRIPT_BASE_LO 0x00000900 1186 1187 #define REG_A6XX_CP_CRASH_SCRIPT_BASE_HI 0x00000901 1188 1189 #define REG_A6XX_CP_CRASH_DUMP_CNTL 0x00000902 1190 1191 #define REG_A6XX_CP_CRASH_DUMP_STATUS 0x00000903 1192 1193 #define REG_A6XX_CP_SQE_STAT_ADDR 0x00000908 1194 1195 #define REG_A6XX_CP_SQE_STAT_DATA 0x00000909 1196 1197 #define REG_A6XX_CP_DRAW_STATE_ADDR 0x0000090a 1198 1199 #define REG_A6XX_CP_DRAW_STATE_DATA 0x0000090b 1200 1201 #define REG_A6XX_CP_ROQ_DBG_ADDR 0x0000090c 1202 1203 #define REG_A6XX_CP_ROQ_DBG_DATA 0x0000090d 1204 1205 #define REG_A6XX_CP_MEM_POOL_DBG_ADDR 0x0000090e 1206 1207 #define REG_A6XX_CP_MEM_POOL_DBG_DATA 0x0000090f 1208 1209 #define REG_A6XX_CP_SQE_UCODE_DBG_ADDR 0x00000910 1210 1211 #define REG_A6XX_CP_SQE_UCODE_DBG_DATA 0x00000911 1212 1213 #define REG_A6XX_CP_IB1_BASE 0x00000928 1214 1215 #define REG_A6XX_CP_IB1_BASE_HI 0x00000929 1216 1217 #define REG_A6XX_CP_IB1_REM_SIZE 0x0000092a 1218 1219 #define REG_A6XX_CP_IB2_BASE 0x0000092b 1220 1221 #define REG_A6XX_CP_IB2_BASE_HI 0x0000092c 1222 1223 #define REG_A6XX_CP_IB2_REM_SIZE 0x0000092d 1224 1225 #define REG_A6XX_CP_SDS_BASE 0x0000092e 1226 1227 #define REG_A6XX_CP_SDS_BASE_HI 0x0000092f 1228 1229 #define REG_A6XX_CP_SDS_REM_SIZE 0x00000930 1230 1231 #define REG_A6XX_CP_MRB_BASE 0x00000931 1232 1233 #define REG_A6XX_CP_MRB_BASE_HI 0x00000932 1234 1235 #define REG_A6XX_CP_MRB_REM_SIZE 0x00000933 1236 1237 #define REG_A6XX_CP_VSD_BASE 0x00000934 1238 1239 #define REG_A6XX_CP_VSD_BASE_HI 0x00000935 1240 1241 #define REG_A6XX_CP_MRB_DWORDS 0x00000946 1242 1243 #define REG_A6XX_CP_VSD_DWORDS 0x00000947 1244 1245 #define REG_A6XX_CP_CSQ_IB1_STAT 0x00000949 1246 #define A6XX_CP_CSQ_IB1_STAT_REM__MASK 0xffff0000 1247 #define A6XX_CP_CSQ_IB1_STAT_REM__SHIFT 16 1248 static inline uint32_t A6XX_CP_CSQ_IB1_STAT_REM(uint32_t val) 1249 { 1250 return ((val) << A6XX_CP_CSQ_IB1_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB1_STAT_REM__MASK; 1251 } 1252 1253 #define REG_A6XX_CP_CSQ_IB2_STAT 0x0000094a 1254 #define A6XX_CP_CSQ_IB2_STAT_REM__MASK 0xffff0000 1255 #define A6XX_CP_CSQ_IB2_STAT_REM__SHIFT 16 1256 static inline uint32_t A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val) 1257 { 1258 return ((val) << A6XX_CP_CSQ_IB2_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB2_STAT_REM__MASK; 1259 } 1260 1261 #define REG_A6XX_CP_MRQ_MRB_STAT 0x0000094c 1262 #define A6XX_CP_MRQ_MRB_STAT_REM__MASK 0xffff0000 1263 #define A6XX_CP_MRQ_MRB_STAT_REM__SHIFT 16 1264 static inline uint32_t A6XX_CP_MRQ_MRB_STAT_REM(uint32_t val) 1265 { 1266 return ((val) << A6XX_CP_MRQ_MRB_STAT_REM__SHIFT) & A6XX_CP_MRQ_MRB_STAT_REM__MASK; 1267 } 1268 1269 #define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO 0x00000980 1270 1271 #define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI 0x00000981 1272 1273 #define REG_A6XX_CP_AHB_CNTL 0x0000098d 1274 1275 #define REG_A6XX_CP_APERTURE_CNTL_HOST 0x00000a00 1276 1277 #define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03 1278 1279 #define REG_A6XX_CP_LPAC_PROG_FIFO_SIZE 0x00000b34 1280 1281 #define REG_A6XX_CP_LPAC_SQE_INSTR_BASE 0x00000b82 1282 1283 #define REG_A6XX_VSC_ADDR_MODE_CNTL 0x00000c01 1284 1285 #define REG_A6XX_RBBM_INT_0_STATUS 0x00000201 1286 1287 #define REG_A6XX_RBBM_STATUS 0x00000210 1288 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x00800000 1289 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x00400000 1290 #define A6XX_RBBM_STATUS_HLSQ_BUSY 0x00200000 1291 #define A6XX_RBBM_STATUS_VSC_BUSY 0x00100000 1292 #define A6XX_RBBM_STATUS_TPL1_BUSY 0x00080000 1293 #define A6XX_RBBM_STATUS_SP_BUSY 0x00040000 1294 #define A6XX_RBBM_STATUS_UCHE_BUSY 0x00020000 1295 #define A6XX_RBBM_STATUS_VPC_BUSY 0x00010000 1296 #define A6XX_RBBM_STATUS_VFD_BUSY 0x00008000 1297 #define A6XX_RBBM_STATUS_TESS_BUSY 0x00004000 1298 #define A6XX_RBBM_STATUS_PC_VSD_BUSY 0x00002000 1299 #define A6XX_RBBM_STATUS_PC_DCALL_BUSY 0x00001000 1300 #define A6XX_RBBM_STATUS_COM_DCOM_BUSY 0x00000800 1301 #define A6XX_RBBM_STATUS_LRZ_BUSY 0x00000400 1302 #define A6XX_RBBM_STATUS_A2D_BUSY 0x00000200 1303 #define A6XX_RBBM_STATUS_CCU_BUSY 0x00000100 1304 #define A6XX_RBBM_STATUS_RB_BUSY 0x00000080 1305 #define A6XX_RBBM_STATUS_RAS_BUSY 0x00000040 1306 #define A6XX_RBBM_STATUS_TSE_BUSY 0x00000020 1307 #define A6XX_RBBM_STATUS_VBIF_BUSY 0x00000010 1308 #define A6XX_RBBM_STATUS_GFX_DBGC_BUSY 0x00000008 1309 #define A6XX_RBBM_STATUS_CP_BUSY 0x00000004 1310 #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER 0x00000002 1311 #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER 0x00000001 1312 1313 #define REG_A6XX_RBBM_STATUS3 0x00000213 1314 #define A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT 0x01000000 1315 1316 #define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215 1317 1318 static inline uint32_t REG_A6XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000400 + 0x2*i0; } 1319 1320 static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000041c + 0x2*i0; } 1321 1322 static inline uint32_t REG_A6XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000424 + 0x2*i0; } 1323 1324 static inline uint32_t REG_A6XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000434 + 0x2*i0; } 1325 1326 static inline uint32_t REG_A6XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000444 + 0x2*i0; } 1327 1328 static inline uint32_t REG_A6XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000450 + 0x2*i0; } 1329 1330 static inline uint32_t REG_A6XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000045c + 0x2*i0; } 1331 1332 static inline uint32_t REG_A6XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000466 + 0x2*i0; } 1333 1334 static inline uint32_t REG_A6XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000046e + 0x2*i0; } 1335 1336 static inline uint32_t REG_A6XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000476 + 0x2*i0; } 1337 1338 static inline uint32_t REG_A6XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000048e + 0x2*i0; } 1339 1340 static inline uint32_t REG_A6XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000004a6 + 0x2*i0; } 1341 1342 static inline uint32_t REG_A6XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000004d6 + 0x2*i0; } 1343 1344 static inline uint32_t REG_A6XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000004e6 + 0x2*i0; } 1345 1346 static inline uint32_t REG_A6XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000004ea + 0x2*i0; } 1347 1348 static inline uint32_t REG_A6XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000004f2 + 0x2*i0; } 1349 1350 #define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500 1351 1352 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 0x00000501 1353 1354 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 0x00000502 1355 1356 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 0x00000503 1357 1358 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 0x00000504 1359 1360 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000505 1361 1362 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506 1363 1364 static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00000507 + 0x1*i0; } 1365 1366 #define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b 1367 1368 #define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD 0x0000050e 1369 1370 #define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS 0x0000050f 1371 1372 #define REG_A6XX_RBBM_ISDB_CNT 0x00000533 1373 1374 #define REG_A6XX_RBBM_PRIMCTR_0_LO 0x00000540 1375 1376 #define REG_A6XX_RBBM_PRIMCTR_0_HI 0x00000541 1377 1378 #define REG_A6XX_RBBM_PRIMCTR_1_LO 0x00000542 1379 1380 #define REG_A6XX_RBBM_PRIMCTR_1_HI 0x00000543 1381 1382 #define REG_A6XX_RBBM_PRIMCTR_2_LO 0x00000544 1383 1384 #define REG_A6XX_RBBM_PRIMCTR_2_HI 0x00000545 1385 1386 #define REG_A6XX_RBBM_PRIMCTR_3_LO 0x00000546 1387 1388 #define REG_A6XX_RBBM_PRIMCTR_3_HI 0x00000547 1389 1390 #define REG_A6XX_RBBM_PRIMCTR_4_LO 0x00000548 1391 1392 #define REG_A6XX_RBBM_PRIMCTR_4_HI 0x00000549 1393 1394 #define REG_A6XX_RBBM_PRIMCTR_5_LO 0x0000054a 1395 1396 #define REG_A6XX_RBBM_PRIMCTR_5_HI 0x0000054b 1397 1398 #define REG_A6XX_RBBM_PRIMCTR_6_LO 0x0000054c 1399 1400 #define REG_A6XX_RBBM_PRIMCTR_6_HI 0x0000054d 1401 1402 #define REG_A6XX_RBBM_PRIMCTR_7_LO 0x0000054e 1403 1404 #define REG_A6XX_RBBM_PRIMCTR_7_HI 0x0000054f 1405 1406 #define REG_A6XX_RBBM_PRIMCTR_8_LO 0x00000550 1407 1408 #define REG_A6XX_RBBM_PRIMCTR_8_HI 0x00000551 1409 1410 #define REG_A6XX_RBBM_PRIMCTR_9_LO 0x00000552 1411 1412 #define REG_A6XX_RBBM_PRIMCTR_9_HI 0x00000553 1413 1414 #define REG_A6XX_RBBM_PRIMCTR_10_LO 0x00000554 1415 1416 #define REG_A6XX_RBBM_PRIMCTR_10_HI 0x00000555 1417 1418 #define REG_A6XX_RBBM_SECVID_TRUST_CNTL 0x0000f400 1419 1420 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800 1421 1422 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801 1423 1424 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802 1425 1426 #define REG_A6XX_RBBM_SECVID_TSB_CNTL 0x0000f803 1427 1428 #define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810 1429 1430 #define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL 0x00000010 1431 1432 #define REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL 0x00000011 1433 1434 #define REG_A6XX_RBBM_GBIF_HALT 0x00000016 1435 1436 #define REG_A6XX_RBBM_GBIF_HALT_ACK 0x00000017 1437 1438 #define REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD 0x0000001c 1439 #define A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE 0x00000001 1440 1441 #define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000001f 1442 1443 #define REG_A6XX_RBBM_INT_CLEAR_CMD 0x00000037 1444 1445 #define REG_A6XX_RBBM_INT_0_MASK 0x00000038 1446 1447 #define REG_A6XX_RBBM_SP_HYST_CNT 0x00000042 1448 1449 #define REG_A6XX_RBBM_SW_RESET_CMD 0x00000043 1450 1451 #define REG_A6XX_RBBM_RAC_THRESHOLD_CNT 0x00000044 1452 1453 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 1454 1455 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046 1456 1457 #define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae 1458 1459 #define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0 1460 1461 #define REG_A6XX_RBBM_CLOCK_CNTL_SP1 0x000000b1 1462 1463 #define REG_A6XX_RBBM_CLOCK_CNTL_SP2 0x000000b2 1464 1465 #define REG_A6XX_RBBM_CLOCK_CNTL_SP3 0x000000b3 1466 1467 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP0 0x000000b4 1468 1469 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP1 0x000000b5 1470 1471 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP2 0x000000b6 1472 1473 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP3 0x000000b7 1474 1475 #define REG_A6XX_RBBM_CLOCK_DELAY_SP0 0x000000b8 1476 1477 #define REG_A6XX_RBBM_CLOCK_DELAY_SP1 0x000000b9 1478 1479 #define REG_A6XX_RBBM_CLOCK_DELAY_SP2 0x000000ba 1480 1481 #define REG_A6XX_RBBM_CLOCK_DELAY_SP3 0x000000bb 1482 1483 #define REG_A6XX_RBBM_CLOCK_HYST_SP0 0x000000bc 1484 1485 #define REG_A6XX_RBBM_CLOCK_HYST_SP1 0x000000bd 1486 1487 #define REG_A6XX_RBBM_CLOCK_HYST_SP2 0x000000be 1488 1489 #define REG_A6XX_RBBM_CLOCK_HYST_SP3 0x000000bf 1490 1491 #define REG_A6XX_RBBM_CLOCK_CNTL_TP0 0x000000c0 1492 1493 #define REG_A6XX_RBBM_CLOCK_CNTL_TP1 0x000000c1 1494 1495 #define REG_A6XX_RBBM_CLOCK_CNTL_TP2 0x000000c2 1496 1497 #define REG_A6XX_RBBM_CLOCK_CNTL_TP3 0x000000c3 1498 1499 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP0 0x000000c4 1500 1501 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP1 0x000000c5 1502 1503 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP2 0x000000c6 1504 1505 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP3 0x000000c7 1506 1507 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP0 0x000000c8 1508 1509 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP1 0x000000c9 1510 1511 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP2 0x000000ca 1512 1513 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP3 0x000000cb 1514 1515 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP0 0x000000cc 1516 1517 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP1 0x000000cd 1518 1519 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP2 0x000000ce 1520 1521 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP3 0x000000cf 1522 1523 #define REG_A6XX_RBBM_CLOCK_DELAY_TP0 0x000000d0 1524 1525 #define REG_A6XX_RBBM_CLOCK_DELAY_TP1 0x000000d1 1526 1527 #define REG_A6XX_RBBM_CLOCK_DELAY_TP2 0x000000d2 1528 1529 #define REG_A6XX_RBBM_CLOCK_DELAY_TP3 0x000000d3 1530 1531 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP0 0x000000d4 1532 1533 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP1 0x000000d5 1534 1535 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP2 0x000000d6 1536 1537 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP3 0x000000d7 1538 1539 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP0 0x000000d8 1540 1541 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP1 0x000000d9 1542 1543 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP2 0x000000da 1544 1545 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP3 0x000000db 1546 1547 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP0 0x000000dc 1548 1549 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP1 0x000000dd 1550 1551 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP2 0x000000de 1552 1553 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP3 0x000000df 1554 1555 #define REG_A6XX_RBBM_CLOCK_HYST_TP0 0x000000e0 1556 1557 #define REG_A6XX_RBBM_CLOCK_HYST_TP1 0x000000e1 1558 1559 #define REG_A6XX_RBBM_CLOCK_HYST_TP2 0x000000e2 1560 1561 #define REG_A6XX_RBBM_CLOCK_HYST_TP3 0x000000e3 1562 1563 #define REG_A6XX_RBBM_CLOCK_HYST2_TP0 0x000000e4 1564 1565 #define REG_A6XX_RBBM_CLOCK_HYST2_TP1 0x000000e5 1566 1567 #define REG_A6XX_RBBM_CLOCK_HYST2_TP2 0x000000e6 1568 1569 #define REG_A6XX_RBBM_CLOCK_HYST2_TP3 0x000000e7 1570 1571 #define REG_A6XX_RBBM_CLOCK_HYST3_TP0 0x000000e8 1572 1573 #define REG_A6XX_RBBM_CLOCK_HYST3_TP1 0x000000e9 1574 1575 #define REG_A6XX_RBBM_CLOCK_HYST3_TP2 0x000000ea 1576 1577 #define REG_A6XX_RBBM_CLOCK_HYST3_TP3 0x000000eb 1578 1579 #define REG_A6XX_RBBM_CLOCK_HYST4_TP0 0x000000ec 1580 1581 #define REG_A6XX_RBBM_CLOCK_HYST4_TP1 0x000000ed 1582 1583 #define REG_A6XX_RBBM_CLOCK_HYST4_TP2 0x000000ee 1584 1585 #define REG_A6XX_RBBM_CLOCK_HYST4_TP3 0x000000ef 1586 1587 #define REG_A6XX_RBBM_CLOCK_CNTL_RB0 0x000000f0 1588 1589 #define REG_A6XX_RBBM_CLOCK_CNTL_RB1 0x000000f1 1590 1591 #define REG_A6XX_RBBM_CLOCK_CNTL_RB2 0x000000f2 1592 1593 #define REG_A6XX_RBBM_CLOCK_CNTL_RB3 0x000000f3 1594 1595 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB0 0x000000f4 1596 1597 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB1 0x000000f5 1598 1599 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB2 0x000000f6 1600 1601 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB3 0x000000f7 1602 1603 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU0 0x000000f8 1604 1605 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU1 0x000000f9 1606 1607 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU2 0x000000fa 1608 1609 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU3 0x000000fb 1610 1611 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000100 1612 1613 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000101 1614 1615 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000102 1616 1617 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000103 1618 1619 #define REG_A6XX_RBBM_CLOCK_CNTL_RAC 0x00000104 1620 1621 #define REG_A6XX_RBBM_CLOCK_CNTL2_RAC 0x00000105 1622 1623 #define REG_A6XX_RBBM_CLOCK_DELAY_RAC 0x00000106 1624 1625 #define REG_A6XX_RBBM_CLOCK_HYST_RAC 0x00000107 1626 1627 #define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000108 1628 1629 #define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000109 1630 1631 #define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000010a 1632 1633 #define REG_A6XX_RBBM_CLOCK_CNTL_UCHE 0x0000010b 1634 1635 #define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE 0x0000010c 1636 1637 #define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE 0x0000010d 1638 1639 #define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE 0x0000010e 1640 1641 #define REG_A6XX_RBBM_CLOCK_DELAY_UCHE 0x0000010f 1642 1643 #define REG_A6XX_RBBM_CLOCK_HYST_UCHE 0x00000110 1644 1645 #define REG_A6XX_RBBM_CLOCK_MODE_VFD 0x00000111 1646 1647 #define REG_A6XX_RBBM_CLOCK_DELAY_VFD 0x00000112 1648 1649 #define REG_A6XX_RBBM_CLOCK_HYST_VFD 0x00000113 1650 1651 #define REG_A6XX_RBBM_CLOCK_MODE_GPC 0x00000114 1652 1653 #define REG_A6XX_RBBM_CLOCK_DELAY_GPC 0x00000115 1654 1655 #define REG_A6XX_RBBM_CLOCK_HYST_GPC 0x00000116 1656 1657 #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2 0x00000117 1658 1659 #define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX 0x00000118 1660 1661 #define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX 0x00000119 1662 1663 #define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX 0x0000011a 1664 1665 #define REG_A6XX_RBBM_CLOCK_MODE_HLSQ 0x0000011b 1666 1667 #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ 0x0000011c 1668 1669 #define REG_A6XX_RBBM_CLOCK_HYST_HLSQ 0x0000011d 1670 1671 #define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE 0x00000120 1672 1673 #define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE 0x00000121 1674 1675 #define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122 1676 1677 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A 0x00000600 1678 1679 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B 0x00000601 1680 1681 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C 0x00000602 1682 1683 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D 0x00000603 1684 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK 0x000000ff 1685 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT 0 1686 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val) 1687 { 1688 return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK; 1689 } 1690 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK 0x0000ff00 1691 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT 8 1692 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val) 1693 { 1694 return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK; 1695 } 1696 1697 #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT 0x00000604 1698 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f 1699 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0 1700 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) 1701 { 1702 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; 1703 } 1704 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000 1705 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12 1706 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) 1707 { 1708 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; 1709 } 1710 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000 1711 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28 1712 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) 1713 { 1714 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; 1715 } 1716 1717 #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM 0x00000605 1718 #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000 1719 #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24 1720 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) 1721 { 1722 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; 1723 } 1724 1725 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 0x00000608 1726 1727 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 0x00000609 1728 1729 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 0x0000060a 1730 1731 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 0x0000060b 1732 1733 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 0x0000060c 1734 1735 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 0x0000060d 1736 1737 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 0x0000060e 1738 1739 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 0x0000060f 1740 1741 #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000610 1742 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f 1743 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0 1744 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) 1745 { 1746 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; 1747 } 1748 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0 1749 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4 1750 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) 1751 { 1752 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; 1753 } 1754 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00 1755 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8 1756 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) 1757 { 1758 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; 1759 } 1760 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000 1761 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12 1762 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) 1763 { 1764 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; 1765 } 1766 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000 1767 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16 1768 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) 1769 { 1770 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; 1771 } 1772 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000 1773 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20 1774 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) 1775 { 1776 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; 1777 } 1778 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000 1779 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24 1780 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) 1781 { 1782 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; 1783 } 1784 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000 1785 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28 1786 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) 1787 { 1788 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; 1789 } 1790 1791 #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000611 1792 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f 1793 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0 1794 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) 1795 { 1796 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; 1797 } 1798 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0 1799 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4 1800 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) 1801 { 1802 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; 1803 } 1804 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00 1805 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8 1806 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) 1807 { 1808 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; 1809 } 1810 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000 1811 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12 1812 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) 1813 { 1814 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; 1815 } 1816 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000 1817 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16 1818 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) 1819 { 1820 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; 1821 } 1822 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000 1823 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20 1824 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) 1825 { 1826 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; 1827 } 1828 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000 1829 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24 1830 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) 1831 { 1832 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; 1833 } 1834 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000 1835 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28 1836 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) 1837 { 1838 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; 1839 } 1840 1841 #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000062f 1842 1843 #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630 1844 1845 static inline uint32_t REG_A6XX_VSC_PERFCTR_VSC_SEL(uint32_t i0) { return 0x00000cd8 + 0x1*i0; } 1846 1847 #define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800 1848 1849 #define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000 1850 1851 #define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00 1852 1853 #define REG_A6XX_UCHE_MODE_CNTL 0x00000e01 1854 1855 #define REG_A6XX_UCHE_WRITE_RANGE_MAX_LO 0x00000e05 1856 1857 #define REG_A6XX_UCHE_WRITE_RANGE_MAX_HI 0x00000e06 1858 1859 #define REG_A6XX_UCHE_WRITE_THRU_BASE_LO 0x00000e07 1860 1861 #define REG_A6XX_UCHE_WRITE_THRU_BASE_HI 0x00000e08 1862 1863 #define REG_A6XX_UCHE_TRAP_BASE_LO 0x00000e09 1864 1865 #define REG_A6XX_UCHE_TRAP_BASE_HI 0x00000e0a 1866 1867 #define REG_A6XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e0b 1868 1869 #define REG_A6XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e0c 1870 1871 #define REG_A6XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e0d 1872 1873 #define REG_A6XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e0e 1874 1875 #define REG_A6XX_UCHE_CACHE_WAYS 0x00000e17 1876 1877 #define REG_A6XX_UCHE_FILTER_CNTL 0x00000e18 1878 1879 #define REG_A6XX_UCHE_CLIENT_PF 0x00000e19 1880 #define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK 0x000000ff 1881 #define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT 0 1882 static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val) 1883 { 1884 return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK; 1885 } 1886 1887 static inline uint32_t REG_A6XX_UCHE_PERFCTR_UCHE_SEL(uint32_t i0) { return 0x00000e1c + 0x1*i0; } 1888 1889 #define REG_A6XX_UCHE_CMDQ_CONFIG 0x00000e3c 1890 1891 #define REG_A6XX_VBIF_VERSION 0x00003000 1892 1893 #define REG_A6XX_VBIF_CLKON 0x00003001 1894 #define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000002 1895 1896 #define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 1897 1898 #define REG_A6XX_VBIF_XIN_HALT_CTRL0 0x00003080 1899 1900 #define REG_A6XX_VBIF_XIN_HALT_CTRL1 0x00003081 1901 1902 #define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084 1903 1904 #define REG_A6XX_VBIF_TEST_BUS1_CTRL0 0x00003085 1905 1906 #define REG_A6XX_VBIF_TEST_BUS1_CTRL1 0x00003086 1907 #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK 0x0000000f 1908 #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT 0 1909 static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val) 1910 { 1911 return ((val) << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK; 1912 } 1913 1914 #define REG_A6XX_VBIF_TEST_BUS2_CTRL0 0x00003087 1915 1916 #define REG_A6XX_VBIF_TEST_BUS2_CTRL1 0x00003088 1917 #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK 0x000001ff 1918 #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT 0 1919 static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val) 1920 { 1921 return ((val) << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK; 1922 } 1923 1924 #define REG_A6XX_VBIF_TEST_BUS_OUT 0x0000308c 1925 1926 #define REG_A6XX_VBIF_PERF_CNT_SEL0 0x000030d0 1927 1928 #define REG_A6XX_VBIF_PERF_CNT_SEL1 0x000030d1 1929 1930 #define REG_A6XX_VBIF_PERF_CNT_SEL2 0x000030d2 1931 1932 #define REG_A6XX_VBIF_PERF_CNT_SEL3 0x000030d3 1933 1934 #define REG_A6XX_VBIF_PERF_CNT_LOW0 0x000030d8 1935 1936 #define REG_A6XX_VBIF_PERF_CNT_LOW1 0x000030d9 1937 1938 #define REG_A6XX_VBIF_PERF_CNT_LOW2 0x000030da 1939 1940 #define REG_A6XX_VBIF_PERF_CNT_LOW3 0x000030db 1941 1942 #define REG_A6XX_VBIF_PERF_CNT_HIGH0 0x000030e0 1943 1944 #define REG_A6XX_VBIF_PERF_CNT_HIGH1 0x000030e1 1945 1946 #define REG_A6XX_VBIF_PERF_CNT_HIGH2 0x000030e2 1947 1948 #define REG_A6XX_VBIF_PERF_CNT_HIGH3 0x000030e3 1949 1950 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN0 0x00003100 1951 1952 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN1 0x00003101 1953 1954 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN2 0x00003102 1955 1956 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110 1957 1958 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111 1959 1960 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112 1961 1962 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118 1963 1964 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119 1965 1966 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a 1967 1968 #define REG_A6XX_GBIF_SCACHE_CNTL0 0x00003c01 1969 1970 #define REG_A6XX_GBIF_SCACHE_CNTL1 0x00003c02 1971 1972 #define REG_A6XX_GBIF_QSB_SIDE0 0x00003c03 1973 1974 #define REG_A6XX_GBIF_QSB_SIDE1 0x00003c04 1975 1976 #define REG_A6XX_GBIF_QSB_SIDE2 0x00003c05 1977 1978 #define REG_A6XX_GBIF_QSB_SIDE3 0x00003c06 1979 1980 #define REG_A6XX_GBIF_HALT 0x00003c45 1981 1982 #define REG_A6XX_GBIF_HALT_ACK 0x00003c46 1983 1984 #define REG_A6XX_GBIF_PERF_PWR_CNT_EN 0x00003cc0 1985 1986 #define REG_A6XX_GBIF_PERF_CNT_SEL 0x00003cc2 1987 1988 #define REG_A6XX_GBIF_PERF_PWR_CNT_SEL 0x00003cc3 1989 1990 #define REG_A6XX_GBIF_PERF_CNT_LOW0 0x00003cc4 1991 1992 #define REG_A6XX_GBIF_PERF_CNT_LOW1 0x00003cc5 1993 1994 #define REG_A6XX_GBIF_PERF_CNT_LOW2 0x00003cc6 1995 1996 #define REG_A6XX_GBIF_PERF_CNT_LOW3 0x00003cc7 1997 1998 #define REG_A6XX_GBIF_PERF_CNT_HIGH0 0x00003cc8 1999 2000 #define REG_A6XX_GBIF_PERF_CNT_HIGH1 0x00003cc9 2001 2002 #define REG_A6XX_GBIF_PERF_CNT_HIGH2 0x00003cca 2003 2004 #define REG_A6XX_GBIF_PERF_CNT_HIGH3 0x00003ccb 2005 2006 #define REG_A6XX_GBIF_PWR_CNT_LOW0 0x00003ccc 2007 2008 #define REG_A6XX_GBIF_PWR_CNT_LOW1 0x00003ccd 2009 2010 #define REG_A6XX_GBIF_PWR_CNT_LOW2 0x00003cce 2011 2012 #define REG_A6XX_GBIF_PWR_CNT_HIGH0 0x00003ccf 2013 2014 #define REG_A6XX_GBIF_PWR_CNT_HIGH1 0x00003cd0 2015 2016 #define REG_A6XX_GBIF_PWR_CNT_HIGH2 0x00003cd1 2017 2018 #define REG_A6XX_VSC_DBG_ECO_CNTL 0x00000c00 2019 2020 #define REG_A6XX_VSC_BIN_SIZE 0x00000c02 2021 #define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff 2022 #define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 2023 static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 2024 { 2025 return ((val >> 5) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK; 2026 } 2027 #define A6XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001ff00 2028 #define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT 8 2029 static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 2030 { 2031 return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK; 2032 } 2033 2034 #define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS 0x00000c03 2035 2036 #define REG_A6XX_VSC_BIN_COUNT 0x00000c06 2037 #define A6XX_VSC_BIN_COUNT_NX__MASK 0x000007fe 2038 #define A6XX_VSC_BIN_COUNT_NX__SHIFT 1 2039 static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val) 2040 { 2041 return ((val) << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK; 2042 } 2043 #define A6XX_VSC_BIN_COUNT_NY__MASK 0x001ff800 2044 #define A6XX_VSC_BIN_COUNT_NY__SHIFT 11 2045 static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val) 2046 { 2047 return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK; 2048 } 2049 2050 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 2051 2052 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 2053 #define A6XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff 2054 #define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0 2055 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) 2056 { 2057 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK; 2058 } 2059 #define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00 2060 #define A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10 2061 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) 2062 { 2063 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK; 2064 } 2065 #define A6XX_VSC_PIPE_CONFIG_REG_W__MASK 0x03f00000 2066 #define A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20 2067 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) 2068 { 2069 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK; 2070 } 2071 #define A6XX_VSC_PIPE_CONFIG_REG_H__MASK 0xfc000000 2072 #define A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT 26 2073 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) 2074 { 2075 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK; 2076 } 2077 2078 #define REG_A6XX_VSC_PRIM_STRM_ADDRESS 0x00000c30 2079 2080 #define REG_A6XX_VSC_PRIM_STRM_PITCH 0x00000c32 2081 2082 #define REG_A6XX_VSC_PRIM_STRM_LIMIT 0x00000c33 2083 2084 #define REG_A6XX_VSC_DRAW_STRM_ADDRESS 0x00000c34 2085 2086 #define REG_A6XX_VSC_DRAW_STRM_PITCH 0x00000c36 2087 2088 #define REG_A6XX_VSC_DRAW_STRM_LIMIT 0x00000c37 2089 2090 static inline uint32_t REG_A6XX_VSC_STATE(uint32_t i0) { return 0x00000c38 + 0x1*i0; } 2091 2092 static inline uint32_t REG_A6XX_VSC_STATE_REG(uint32_t i0) { return 0x00000c38 + 0x1*i0; } 2093 2094 static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE(uint32_t i0) { return 0x00000c58 + 0x1*i0; } 2095 2096 static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0) { return 0x00000c58 + 0x1*i0; } 2097 2098 static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; } 2099 2100 static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; } 2101 2102 #define REG_A6XX_UCHE_UNKNOWN_0E12 0x00000e12 2103 2104 #define REG_A6XX_GRAS_CL_CNTL 0x00008000 2105 #define A6XX_GRAS_CL_CNTL_CLIP_DISABLE 0x00000001 2106 #define A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE 0x00000002 2107 #define A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE 0x00000004 2108 #define A6XX_GRAS_CL_CNTL_UNK5 0x00000020 2109 #define A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040 2110 #define A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE 0x00000080 2111 #define A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE 0x00000100 2112 #define A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE 0x00000200 2113 2114 #define REG_A6XX_GRAS_VS_CL_CNTL 0x00008001 2115 #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK 0x000000ff 2116 #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT 0 2117 static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val) 2118 { 2119 return ((val) << A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK; 2120 } 2121 #define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK 0x0000ff00 2122 #define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT 8 2123 static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val) 2124 { 2125 return ((val) << A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK; 2126 } 2127 2128 #define REG_A6XX_GRAS_DS_CL_CNTL 0x00008002 2129 #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK 0x000000ff 2130 #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT 0 2131 static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(uint32_t val) 2132 { 2133 return ((val) << A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK; 2134 } 2135 #define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK 0x0000ff00 2136 #define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT 8 2137 static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CULL_MASK(uint32_t val) 2138 { 2139 return ((val) << A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK; 2140 } 2141 2142 #define REG_A6XX_GRAS_GS_CL_CNTL 0x00008003 2143 #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK 0x000000ff 2144 #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT 0 2145 static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(uint32_t val) 2146 { 2147 return ((val) << A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK; 2148 } 2149 #define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK 0x0000ff00 2150 #define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT 8 2151 static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CULL_MASK(uint32_t val) 2152 { 2153 return ((val) << A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK; 2154 } 2155 2156 #define REG_A6XX_GRAS_MAX_LAYER_INDEX 0x00008004 2157 2158 #define REG_A6XX_GRAS_CNTL 0x00008005 2159 #define A6XX_GRAS_CNTL_IJ_PERSP_PIXEL 0x00000001 2160 #define A6XX_GRAS_CNTL_IJ_PERSP_CENTROID 0x00000002 2161 #define A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE 0x00000004 2162 #define A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL 0x00000008 2163 #define A6XX_GRAS_CNTL_IJ_LINEAR_CENTROID 0x00000010 2164 #define A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE 0x00000020 2165 #define A6XX_GRAS_CNTL_COORD_MASK__MASK 0x000003c0 2166 #define A6XX_GRAS_CNTL_COORD_MASK__SHIFT 6 2167 static inline uint32_t A6XX_GRAS_CNTL_COORD_MASK(uint32_t val) 2168 { 2169 return ((val) << A6XX_GRAS_CNTL_COORD_MASK__SHIFT) & A6XX_GRAS_CNTL_COORD_MASK__MASK; 2170 } 2171 2172 #define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x00008006 2173 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000001ff 2174 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0 2175 static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val) 2176 { 2177 return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK; 2178 } 2179 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x0007fc00 2180 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10 2181 static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) 2182 { 2183 return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK; 2184 } 2185 2186 static inline uint32_t REG_A6XX_GRAS_CL_VPORT(uint32_t i0) { return 0x00008010 + 0x6*i0; } 2187 2188 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0) { return 0x00008010 + 0x6*i0; } 2189 #define A6XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff 2190 #define A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0 2191 static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET(float val) 2192 { 2193 return ((fui(val)) << A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET__MASK; 2194 } 2195 2196 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XSCALE(uint32_t i0) { return 0x00008011 + 0x6*i0; } 2197 #define A6XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff 2198 #define A6XX_GRAS_CL_VPORT_XSCALE__SHIFT 0 2199 static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE(float val) 2200 { 2201 return ((fui(val)) << A6XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE__MASK; 2202 } 2203 2204 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YOFFSET(uint32_t i0) { return 0x00008012 + 0x6*i0; } 2205 #define A6XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff 2206 #define A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0 2207 static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET(float val) 2208 { 2209 return ((fui(val)) << A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET__MASK; 2210 } 2211 2212 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YSCALE(uint32_t i0) { return 0x00008013 + 0x6*i0; } 2213 #define A6XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff 2214 #define A6XX_GRAS_CL_VPORT_YSCALE__SHIFT 0 2215 static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE(float val) 2216 { 2217 return ((fui(val)) << A6XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE__MASK; 2218 } 2219 2220 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZOFFSET(uint32_t i0) { return 0x00008014 + 0x6*i0; } 2221 #define A6XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff 2222 #define A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0 2223 static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET(float val) 2224 { 2225 return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET__MASK; 2226 } 2227 2228 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZSCALE(uint32_t i0) { return 0x00008015 + 0x6*i0; } 2229 #define A6XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff 2230 #define A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0 2231 static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE(float val) 2232 { 2233 return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE__MASK; 2234 } 2235 2236 static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP(uint32_t i0) { return 0x00008070 + 0x2*i0; } 2237 2238 static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0) { return 0x00008070 + 0x2*i0; } 2239 #define A6XX_GRAS_CL_Z_CLAMP_MIN__MASK 0xffffffff 2240 #define A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT 0 2241 static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MIN(float val) 2242 { 2243 return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MIN__MASK; 2244 } 2245 2246 static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MAX(uint32_t i0) { return 0x00008071 + 0x2*i0; } 2247 #define A6XX_GRAS_CL_Z_CLAMP_MAX__MASK 0xffffffff 2248 #define A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT 0 2249 static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MAX(float val) 2250 { 2251 return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MAX__MASK; 2252 } 2253 2254 #define REG_A6XX_GRAS_SU_CNTL 0x00008090 2255 #define A6XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001 2256 #define A6XX_GRAS_SU_CNTL_CULL_BACK 0x00000002 2257 #define A6XX_GRAS_SU_CNTL_FRONT_CW 0x00000004 2258 #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8 2259 #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3 2260 static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) 2261 { 2262 return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK; 2263 } 2264 #define A6XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800 2265 #define A6XX_GRAS_SU_CNTL_UNK12__MASK 0x00001000 2266 #define A6XX_GRAS_SU_CNTL_UNK12__SHIFT 12 2267 static inline uint32_t A6XX_GRAS_SU_CNTL_UNK12(uint32_t val) 2268 { 2269 return ((val) << A6XX_GRAS_SU_CNTL_UNK12__SHIFT) & A6XX_GRAS_SU_CNTL_UNK12__MASK; 2270 } 2271 #define A6XX_GRAS_SU_CNTL_LINE_MODE__MASK 0x00002000 2272 #define A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT 13 2273 static inline uint32_t A6XX_GRAS_SU_CNTL_LINE_MODE(enum a5xx_line_mode val) 2274 { 2275 return ((val) << A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT) & A6XX_GRAS_SU_CNTL_LINE_MODE__MASK; 2276 } 2277 #define A6XX_GRAS_SU_CNTL_UNK15__MASK 0x00018000 2278 #define A6XX_GRAS_SU_CNTL_UNK15__SHIFT 15 2279 static inline uint32_t A6XX_GRAS_SU_CNTL_UNK15(uint32_t val) 2280 { 2281 return ((val) << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK; 2282 } 2283 #define A6XX_GRAS_SU_CNTL_UNK17 0x00020000 2284 #define A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE 0x00040000 2285 #define A6XX_GRAS_SU_CNTL_UNK19__MASK 0x00780000 2286 #define A6XX_GRAS_SU_CNTL_UNK19__SHIFT 19 2287 static inline uint32_t A6XX_GRAS_SU_CNTL_UNK19(uint32_t val) 2288 { 2289 return ((val) << A6XX_GRAS_SU_CNTL_UNK19__SHIFT) & A6XX_GRAS_SU_CNTL_UNK19__MASK; 2290 } 2291 2292 #define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091 2293 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 2294 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 2295 static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val) 2296 { 2297 return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 2298 } 2299 #define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 2300 #define A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 2301 static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MAX(float val) 2302 { 2303 return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 2304 } 2305 2306 #define REG_A6XX_GRAS_SU_POINT_SIZE 0x00008092 2307 #define A6XX_GRAS_SU_POINT_SIZE__MASK 0x0000ffff 2308 #define A6XX_GRAS_SU_POINT_SIZE__SHIFT 0 2309 static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val) 2310 { 2311 return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK; 2312 } 2313 2314 #define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL 0x00008094 2315 #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003 2316 #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0 2317 static inline uint32_t A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val) 2318 { 2319 return ((val) << A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK; 2320 } 2321 2322 #define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE 0x00008095 2323 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff 2324 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 2325 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val) 2326 { 2327 return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; 2328 } 2329 2330 #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00008096 2331 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 2332 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 2333 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 2334 { 2335 return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 2336 } 2337 2338 #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x00008097 2339 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff 2340 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0 2341 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val) 2342 { 2343 return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK; 2344 } 2345 2346 #define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO 0x00008098 2347 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 2348 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 2349 static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) 2350 { 2351 return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; 2352 } 2353 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000008 2354 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT 3 2355 static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3(uint32_t val) 2356 { 2357 return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK; 2358 } 2359 2360 #define REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x00008099 2361 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN 0x00000001 2362 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK 0x00000006 2363 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT 1 2364 static inline uint32_t A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT(uint32_t val) 2365 { 2366 return ((val) << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK; 2367 } 2368 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_INNERCONSERVATIVERASEN 0x00000008 2369 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK 0x00000030 2370 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT 4 2371 static inline uint32_t A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4(uint32_t val) 2372 { 2373 return ((val) << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK; 2374 } 2375 2376 #define REG_A6XX_GRAS_SU_PATH_RENDERING_CNTL 0x0000809a 2377 #define A6XX_GRAS_SU_PATH_RENDERING_CNTL_UNK0 0x00000001 2378 #define A6XX_GRAS_SU_PATH_RENDERING_CNTL_LINELENGTHEN 0x00000002 2379 2380 #define REG_A6XX_GRAS_VS_LAYER_CNTL 0x0000809b 2381 #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER 0x00000001 2382 #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW 0x00000002 2383 2384 #define REG_A6XX_GRAS_GS_LAYER_CNTL 0x0000809c 2385 #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER 0x00000001 2386 #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW 0x00000002 2387 2388 #define REG_A6XX_GRAS_DS_LAYER_CNTL 0x0000809d 2389 #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER 0x00000001 2390 #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW 0x00000002 2391 2392 #define REG_A6XX_GRAS_SC_CNTL 0x000080a0 2393 #define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK 0x00000007 2394 #define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT 0 2395 static inline uint32_t A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(uint32_t val) 2396 { 2397 return ((val) << A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK; 2398 } 2399 #define A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK 0x00000018 2400 #define A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT 3 2401 static inline uint32_t A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE(enum a6xx_single_prim_mode val) 2402 { 2403 return ((val) << A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK; 2404 } 2405 #define A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK 0x00000020 2406 #define A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT 5 2407 static inline uint32_t A6XX_GRAS_SC_CNTL_RASTER_MODE(enum a6xx_raster_mode val) 2408 { 2409 return ((val) << A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK; 2410 } 2411 #define A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK 0x000000c0 2412 #define A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT 6 2413 static inline uint32_t A6XX_GRAS_SC_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val) 2414 { 2415 return ((val) << A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK; 2416 } 2417 #define A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK 0x00000100 2418 #define A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT 8 2419 static inline uint32_t A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION(enum a6xx_sequenced_thread_dist val) 2420 { 2421 return ((val) << A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT) & A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK; 2422 } 2423 #define A6XX_GRAS_SC_CNTL_UNK9__MASK 0x00000e00 2424 #define A6XX_GRAS_SC_CNTL_UNK9__SHIFT 9 2425 static inline uint32_t A6XX_GRAS_SC_CNTL_UNK9(uint32_t val) 2426 { 2427 return ((val) << A6XX_GRAS_SC_CNTL_UNK9__SHIFT) & A6XX_GRAS_SC_CNTL_UNK9__MASK; 2428 } 2429 #define A6XX_GRAS_SC_CNTL_EARLYVIZOUTEN 0x00001000 2430 2431 #define REG_A6XX_GRAS_BIN_CONTROL 0x000080a1 2432 #define A6XX_GRAS_BIN_CONTROL_BINW__MASK 0x0000003f 2433 #define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT 0 2434 static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val) 2435 { 2436 return ((val >> 5) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK; 2437 } 2438 #define A6XX_GRAS_BIN_CONTROL_BINH__MASK 0x00007f00 2439 #define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT 8 2440 static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val) 2441 { 2442 return ((val >> 4) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK; 2443 } 2444 #define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000 2445 #define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT 18 2446 static inline uint32_t A6XX_GRAS_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val) 2447 { 2448 return ((val) << A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK; 2449 } 2450 #define A6XX_GRAS_BIN_CONTROL_FORCE_LRZ_WRITE_DIS 0x00200000 2451 #define A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK 0x00c00000 2452 #define A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT 22 2453 static inline uint32_t A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val) 2454 { 2455 return ((val) << A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK; 2456 } 2457 #define A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK 0x07000000 2458 #define A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT 24 2459 static inline uint32_t A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val) 2460 { 2461 return ((val) << A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK; 2462 } 2463 #define A6XX_GRAS_BIN_CONTROL_UNK27__MASK 0x08000000 2464 #define A6XX_GRAS_BIN_CONTROL_UNK27__SHIFT 27 2465 static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK27(uint32_t val) 2466 { 2467 return ((val) << A6XX_GRAS_BIN_CONTROL_UNK27__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK27__MASK; 2468 } 2469 2470 #define REG_A6XX_GRAS_RAS_MSAA_CNTL 0x000080a2 2471 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 2472 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 2473 static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 2474 { 2475 return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK; 2476 } 2477 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK 0x00000004 2478 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT 2 2479 static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK2(uint32_t val) 2480 { 2481 return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK; 2482 } 2483 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK 0x00000008 2484 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT 3 2485 static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK3(uint32_t val) 2486 { 2487 return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK; 2488 } 2489 2490 #define REG_A6XX_GRAS_DEST_MSAA_CNTL 0x000080a3 2491 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 2492 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 2493 static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 2494 { 2495 return ((val) << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK; 2496 } 2497 #define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 2498 2499 #define REG_A6XX_GRAS_SAMPLE_CONFIG 0x000080a4 2500 #define A6XX_GRAS_SAMPLE_CONFIG_UNK0 0x00000001 2501 #define A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002 2502 2503 #define REG_A6XX_GRAS_SAMPLE_LOCATION_0 0x000080a5 2504 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f 2505 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 2506 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) 2507 { 2508 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; 2509 } 2510 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 2511 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 2512 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) 2513 { 2514 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; 2515 } 2516 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 2517 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 2518 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) 2519 { 2520 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; 2521 } 2522 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 2523 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 2524 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) 2525 { 2526 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; 2527 } 2528 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 2529 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 2530 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) 2531 { 2532 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; 2533 } 2534 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 2535 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 2536 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) 2537 { 2538 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; 2539 } 2540 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 2541 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 2542 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) 2543 { 2544 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; 2545 } 2546 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 2547 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 2548 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) 2549 { 2550 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; 2551 } 2552 2553 #define REG_A6XX_GRAS_SAMPLE_LOCATION_1 0x000080a6 2554 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f 2555 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 2556 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) 2557 { 2558 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; 2559 } 2560 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 2561 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 2562 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) 2563 { 2564 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; 2565 } 2566 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 2567 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 2568 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) 2569 { 2570 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; 2571 } 2572 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 2573 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 2574 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) 2575 { 2576 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; 2577 } 2578 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 2579 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 2580 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) 2581 { 2582 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; 2583 } 2584 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 2585 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 2586 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) 2587 { 2588 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; 2589 } 2590 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 2591 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 2592 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) 2593 { 2594 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; 2595 } 2596 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 2597 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 2598 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) 2599 { 2600 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; 2601 } 2602 2603 #define REG_A6XX_GRAS_UNKNOWN_80AF 0x000080af 2604 2605 static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR(uint32_t i0) { return 0x000080b0 + 0x2*i0; } 2606 2607 static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0) { return 0x000080b0 + 0x2*i0; } 2608 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x0000ffff 2609 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 2610 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 2611 { 2612 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; 2613 } 2614 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0xffff0000 2615 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 2616 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 2617 { 2618 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; 2619 } 2620 2621 static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR(uint32_t i0) { return 0x000080b1 + 0x2*i0; } 2622 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x0000ffff 2623 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 2624 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 2625 { 2626 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; 2627 } 2628 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0xffff0000 2629 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 2630 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 2631 { 2632 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; 2633 } 2634 2635 static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(uint32_t i0) { return 0x000080d0 + 0x2*i0; } 2636 2637 static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0) { return 0x000080d0 + 0x2*i0; } 2638 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK 0x0000ffff 2639 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT 0 2640 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(uint32_t val) 2641 { 2642 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK; 2643 } 2644 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK 0xffff0000 2645 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT 16 2646 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(uint32_t val) 2647 { 2648 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK; 2649 } 2650 2651 static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(uint32_t i0) { return 0x000080d1 + 0x2*i0; } 2652 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK 0x0000ffff 2653 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT 0 2654 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X(uint32_t val) 2655 { 2656 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK; 2657 } 2658 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK 0xffff0000 2659 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT 16 2660 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y(uint32_t val) 2661 { 2662 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK; 2663 } 2664 2665 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL 0x000080f0 2666 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00003fff 2667 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 2668 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 2669 { 2670 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 2671 } 2672 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x3fff0000 2673 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 2674 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 2675 { 2676 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 2677 } 2678 2679 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR 0x000080f1 2680 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00003fff 2681 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 2682 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 2683 { 2684 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 2685 } 2686 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x3fff0000 2687 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 2688 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 2689 { 2690 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 2691 } 2692 2693 #define REG_A6XX_GRAS_LRZ_CNTL 0x00008100 2694 #define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001 2695 #define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002 2696 #define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004 2697 #define A6XX_GRAS_LRZ_CNTL_FC_ENABLE 0x00000008 2698 #define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE 0x00000010 2699 #define A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE 0x00000020 2700 #define A6XX_GRAS_LRZ_CNTL_UNK6__MASK 0x000003c0 2701 #define A6XX_GRAS_LRZ_CNTL_UNK6__SHIFT 6 2702 static inline uint32_t A6XX_GRAS_LRZ_CNTL_UNK6(uint32_t val) 2703 { 2704 return ((val) << A6XX_GRAS_LRZ_CNTL_UNK6__SHIFT) & A6XX_GRAS_LRZ_CNTL_UNK6__MASK; 2705 } 2706 2707 #define REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL 0x00008101 2708 #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_SAMPLEID 0x00000001 2709 #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK 0x00000006 2710 #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT 1 2711 static inline uint32_t A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val) 2712 { 2713 return ((val) << A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK; 2714 } 2715 2716 #define REG_A6XX_GRAS_LRZ_MRT_BUF_INFO_0 0x00008102 2717 #define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK 0x000000ff 2718 #define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT 0 2719 static inline uint32_t A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT(enum a6xx_format val) 2720 { 2721 return ((val) << A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT) & A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK; 2722 } 2723 2724 #define REG_A6XX_GRAS_LRZ_BUFFER_BASE 0x00008103 2725 #define A6XX_GRAS_LRZ_BUFFER_BASE__MASK 0xffffffff 2726 #define A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT 0 2727 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_BASE(uint32_t val) 2728 { 2729 return ((val) << A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_BUFFER_BASE__MASK; 2730 } 2731 2732 #define REG_A6XX_GRAS_LRZ_BUFFER_PITCH 0x00008105 2733 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK 0x000000ff 2734 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT 0 2735 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val) 2736 { 2737 return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK; 2738 } 2739 #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffffc00 2740 #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT 10 2741 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 2742 { 2743 return ((val >> 4) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK; 2744 } 2745 2746 #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE 0x00008106 2747 #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK 0xffffffff 2748 #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT 0 2749 static inline uint32_t A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(uint32_t val) 2750 { 2751 return ((val) << A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK; 2752 } 2753 2754 #define REG_A6XX_GRAS_SAMPLE_CNTL 0x00008109 2755 #define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001 2756 2757 #define REG_A6XX_GRAS_UNKNOWN_810A 0x0000810a 2758 #define A6XX_GRAS_UNKNOWN_810A_UNK0__MASK 0x000007ff 2759 #define A6XX_GRAS_UNKNOWN_810A_UNK0__SHIFT 0 2760 static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK0(uint32_t val) 2761 { 2762 return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK0__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK0__MASK; 2763 } 2764 #define A6XX_GRAS_UNKNOWN_810A_UNK16__MASK 0x07ff0000 2765 #define A6XX_GRAS_UNKNOWN_810A_UNK16__SHIFT 16 2766 static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK16(uint32_t val) 2767 { 2768 return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK16__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK16__MASK; 2769 } 2770 #define A6XX_GRAS_UNKNOWN_810A_UNK28__MASK 0xf0000000 2771 #define A6XX_GRAS_UNKNOWN_810A_UNK28__SHIFT 28 2772 static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK28(uint32_t val) 2773 { 2774 return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK28__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK28__MASK; 2775 } 2776 2777 #define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110 2778 2779 #define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400 2780 #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK 0x00000007 2781 #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT 0 2782 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val) 2783 { 2784 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK; 2785 } 2786 #define A6XX_GRAS_2D_BLIT_CNTL_OVERWRITEEN 0x00000008 2787 #define A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK 0x00000070 2788 #define A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT 4 2789 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK4(uint32_t val) 2790 { 2791 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK; 2792 } 2793 #define A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR 0x00000080 2794 #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00 2795 #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8 2796 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val) 2797 { 2798 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK; 2799 } 2800 #define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR 0x00010000 2801 #define A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK 0x00060000 2802 #define A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT 17 2803 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK17(uint32_t val) 2804 { 2805 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK; 2806 } 2807 #define A6XX_GRAS_2D_BLIT_CNTL_D24S8 0x00080000 2808 #define A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK 0x00f00000 2809 #define A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT 20 2810 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_MASK(uint32_t val) 2811 { 2812 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK; 2813 } 2814 #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK 0x1f000000 2815 #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT 24 2816 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val) 2817 { 2818 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK; 2819 } 2820 #define A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK 0x20000000 2821 #define A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT 29 2822 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val) 2823 { 2824 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK; 2825 } 2826 2827 #define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401 2828 2829 #define REG_A6XX_GRAS_2D_SRC_BR_X 0x00008402 2830 2831 #define REG_A6XX_GRAS_2D_SRC_TL_Y 0x00008403 2832 2833 #define REG_A6XX_GRAS_2D_SRC_BR_Y 0x00008404 2834 2835 #define REG_A6XX_GRAS_2D_DST_TL 0x00008405 2836 #define A6XX_GRAS_2D_DST_TL_X__MASK 0x00003fff 2837 #define A6XX_GRAS_2D_DST_TL_X__SHIFT 0 2838 static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val) 2839 { 2840 return ((val) << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK; 2841 } 2842 #define A6XX_GRAS_2D_DST_TL_Y__MASK 0x3fff0000 2843 #define A6XX_GRAS_2D_DST_TL_Y__SHIFT 16 2844 static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val) 2845 { 2846 return ((val) << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK; 2847 } 2848 2849 #define REG_A6XX_GRAS_2D_DST_BR 0x00008406 2850 #define A6XX_GRAS_2D_DST_BR_X__MASK 0x00003fff 2851 #define A6XX_GRAS_2D_DST_BR_X__SHIFT 0 2852 static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val) 2853 { 2854 return ((val) << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK; 2855 } 2856 #define A6XX_GRAS_2D_DST_BR_Y__MASK 0x3fff0000 2857 #define A6XX_GRAS_2D_DST_BR_Y__SHIFT 16 2858 static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val) 2859 { 2860 return ((val) << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK; 2861 } 2862 2863 #define REG_A6XX_GRAS_2D_UNKNOWN_8407 0x00008407 2864 2865 #define REG_A6XX_GRAS_2D_UNKNOWN_8408 0x00008408 2866 2867 #define REG_A6XX_GRAS_2D_UNKNOWN_8409 0x00008409 2868 2869 #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_1 0x0000840a 2870 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK 0x00003fff 2871 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT 0 2872 static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_X(uint32_t val) 2873 { 2874 return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK; 2875 } 2876 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK 0x3fff0000 2877 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT 16 2878 static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(uint32_t val) 2879 { 2880 return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK; 2881 } 2882 2883 #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_2 0x0000840b 2884 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK 0x00003fff 2885 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT 0 2886 static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_X(uint32_t val) 2887 { 2888 return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK; 2889 } 2890 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK 0x3fff0000 2891 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT 16 2892 static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val) 2893 { 2894 return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK; 2895 } 2896 2897 #define REG_A6XX_GRAS_DBG_ECO_CNTL 0x00008600 2898 #define A6XX_GRAS_DBG_ECO_CNTL_UNK7 0x00000080 2899 #define A6XX_GRAS_DBG_ECO_CNTL_LRZCACHELOCKDIS 0x00000800 2900 2901 #define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601 2902 2903 static inline uint32_t REG_A6XX_GRAS_PERFCTR_TSE_SEL(uint32_t i0) { return 0x00008610 + 0x1*i0; } 2904 2905 static inline uint32_t REG_A6XX_GRAS_PERFCTR_RAS_SEL(uint32_t i0) { return 0x00008614 + 0x1*i0; } 2906 2907 static inline uint32_t REG_A6XX_GRAS_PERFCTR_LRZ_SEL(uint32_t i0) { return 0x00008618 + 0x1*i0; } 2908 2909 #define REG_A6XX_RB_BIN_CONTROL 0x00008800 2910 #define A6XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f 2911 #define A6XX_RB_BIN_CONTROL_BINW__SHIFT 0 2912 static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val) 2913 { 2914 return ((val >> 5) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK; 2915 } 2916 #define A6XX_RB_BIN_CONTROL_BINH__MASK 0x00007f00 2917 #define A6XX_RB_BIN_CONTROL_BINH__SHIFT 8 2918 static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val) 2919 { 2920 return ((val >> 4) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK; 2921 } 2922 #define A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000 2923 #define A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT 18 2924 static inline uint32_t A6XX_RB_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val) 2925 { 2926 return ((val) << A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK; 2927 } 2928 #define A6XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS 0x00200000 2929 #define A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK 0x00c00000 2930 #define A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT 22 2931 static inline uint32_t A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val) 2932 { 2933 return ((val) << A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK; 2934 } 2935 #define A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK 0x07000000 2936 #define A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT 24 2937 static inline uint32_t A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val) 2938 { 2939 return ((val) << A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK; 2940 } 2941 2942 #define REG_A6XX_RB_RENDER_CNTL 0x00008801 2943 #define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK 0x00000038 2944 #define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT 3 2945 static inline uint32_t A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE(uint32_t val) 2946 { 2947 return ((val) << A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK; 2948 } 2949 #define A6XX_RB_RENDER_CNTL_EARLYVIZOUTEN 0x00000040 2950 #define A6XX_RB_RENDER_CNTL_BINNING 0x00000080 2951 #define A6XX_RB_RENDER_CNTL_UNK8__MASK 0x00000700 2952 #define A6XX_RB_RENDER_CNTL_UNK8__SHIFT 8 2953 static inline uint32_t A6XX_RB_RENDER_CNTL_UNK8(uint32_t val) 2954 { 2955 return ((val) << A6XX_RB_RENDER_CNTL_UNK8__SHIFT) & A6XX_RB_RENDER_CNTL_UNK8__MASK; 2956 } 2957 #define A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK 0x00000100 2958 #define A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT 8 2959 static inline uint32_t A6XX_RB_RENDER_CNTL_RASTER_MODE(enum a6xx_raster_mode val) 2960 { 2961 return ((val) << A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK; 2962 } 2963 #define A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK 0x00000600 2964 #define A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT 9 2965 static inline uint32_t A6XX_RB_RENDER_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val) 2966 { 2967 return ((val) << A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK; 2968 } 2969 #define A6XX_RB_RENDER_CNTL_CONSERVATIVERASEN 0x00000800 2970 #define A6XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN 0x00001000 2971 #define A6XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000 2972 #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000 2973 #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16 2974 static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val) 2975 { 2976 return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK; 2977 } 2978 2979 #define REG_A6XX_RB_RAS_MSAA_CNTL 0x00008802 2980 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 2981 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 2982 static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 2983 { 2984 return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK; 2985 } 2986 #define A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK 0x00000004 2987 #define A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT 2 2988 static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK2(uint32_t val) 2989 { 2990 return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK; 2991 } 2992 #define A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK 0x00000008 2993 #define A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT 3 2994 static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK3(uint32_t val) 2995 { 2996 return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK; 2997 } 2998 2999 #define REG_A6XX_RB_DEST_MSAA_CNTL 0x00008803 3000 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 3001 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 3002 static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 3003 { 3004 return ((val) << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK; 3005 } 3006 #define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 3007 3008 #define REG_A6XX_RB_SAMPLE_CONFIG 0x00008804 3009 #define A6XX_RB_SAMPLE_CONFIG_UNK0 0x00000001 3010 #define A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002 3011 3012 #define REG_A6XX_RB_SAMPLE_LOCATION_0 0x00008805 3013 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f 3014 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 3015 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) 3016 { 3017 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; 3018 } 3019 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 3020 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 3021 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) 3022 { 3023 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; 3024 } 3025 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 3026 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 3027 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) 3028 { 3029 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; 3030 } 3031 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 3032 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 3033 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) 3034 { 3035 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; 3036 } 3037 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 3038 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 3039 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) 3040 { 3041 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; 3042 } 3043 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 3044 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 3045 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) 3046 { 3047 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; 3048 } 3049 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 3050 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 3051 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) 3052 { 3053 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; 3054 } 3055 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 3056 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 3057 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) 3058 { 3059 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; 3060 } 3061 3062 #define REG_A6XX_RB_SAMPLE_LOCATION_1 0x00008806 3063 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f 3064 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 3065 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) 3066 { 3067 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; 3068 } 3069 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 3070 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 3071 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) 3072 { 3073 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; 3074 } 3075 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 3076 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 3077 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) 3078 { 3079 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; 3080 } 3081 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 3082 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 3083 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) 3084 { 3085 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; 3086 } 3087 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 3088 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 3089 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) 3090 { 3091 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; 3092 } 3093 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 3094 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 3095 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) 3096 { 3097 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; 3098 } 3099 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 3100 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 3101 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) 3102 { 3103 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; 3104 } 3105 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 3106 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 3107 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) 3108 { 3109 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; 3110 } 3111 3112 #define REG_A6XX_RB_RENDER_CONTROL0 0x00008809 3113 #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL 0x00000001 3114 #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID 0x00000002 3115 #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE 0x00000004 3116 #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL 0x00000008 3117 #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID 0x00000010 3118 #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE 0x00000020 3119 #define A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK 0x000003c0 3120 #define A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT 6 3121 static inline uint32_t A6XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val) 3122 { 3123 return ((val) << A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK; 3124 } 3125 #define A6XX_RB_RENDER_CONTROL0_UNK10 0x00000400 3126 3127 #define REG_A6XX_RB_RENDER_CONTROL1 0x0000880a 3128 #define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001 3129 #define A6XX_RB_RENDER_CONTROL1_UNK1 0x00000002 3130 #define A6XX_RB_RENDER_CONTROL1_FACENESS 0x00000004 3131 #define A6XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000008 3132 #define A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK 0x00000030 3133 #define A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT 4 3134 static inline uint32_t A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val) 3135 { 3136 return ((val) << A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK; 3137 } 3138 #define A6XX_RB_RENDER_CONTROL1_SIZE 0x00000040 3139 #define A6XX_RB_RENDER_CONTROL1_LINELENGTHEN 0x00000080 3140 #define A6XX_RB_RENDER_CONTROL1_FOVEATION 0x00000100 3141 3142 #define REG_A6XX_RB_FS_OUTPUT_CNTL0 0x0000880b 3143 #define A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001 3144 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z 0x00000002 3145 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK 0x00000004 3146 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF 0x00000008 3147 3148 #define REG_A6XX_RB_FS_OUTPUT_CNTL1 0x0000880c 3149 #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f 3150 #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT 0 3151 static inline uint32_t A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val) 3152 { 3153 return ((val) << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK; 3154 } 3155 3156 #define REG_A6XX_RB_RENDER_COMPONENTS 0x0000880d 3157 #define A6XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f 3158 #define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0 3159 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) 3160 { 3161 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK; 3162 } 3163 #define A6XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0 3164 #define A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4 3165 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) 3166 { 3167 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK; 3168 } 3169 #define A6XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00 3170 #define A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8 3171 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) 3172 { 3173 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK; 3174 } 3175 #define A6XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000 3176 #define A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12 3177 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) 3178 { 3179 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK; 3180 } 3181 #define A6XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000 3182 #define A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16 3183 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) 3184 { 3185 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK; 3186 } 3187 #define A6XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000 3188 #define A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20 3189 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) 3190 { 3191 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK; 3192 } 3193 #define A6XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000 3194 #define A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24 3195 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) 3196 { 3197 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK; 3198 } 3199 #define A6XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000 3200 #define A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28 3201 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) 3202 { 3203 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK; 3204 } 3205 3206 #define REG_A6XX_RB_DITHER_CNTL 0x0000880e 3207 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK 0x00000003 3208 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT 0 3209 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val) 3210 { 3211 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK; 3212 } 3213 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK 0x0000000c 3214 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT 2 3215 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val) 3216 { 3217 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK; 3218 } 3219 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK 0x00000030 3220 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT 4 3221 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val) 3222 { 3223 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK; 3224 } 3225 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK 0x000000c0 3226 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT 6 3227 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val) 3228 { 3229 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK; 3230 } 3231 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK 0x00000300 3232 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT 8 3233 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val) 3234 { 3235 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK; 3236 } 3237 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK 0x00000c00 3238 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT 10 3239 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val) 3240 { 3241 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK; 3242 } 3243 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK 0x00001000 3244 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT 12 3245 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val) 3246 { 3247 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK; 3248 } 3249 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK 0x0000c000 3250 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT 14 3251 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val) 3252 { 3253 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK; 3254 } 3255 3256 #define REG_A6XX_RB_SRGB_CNTL 0x0000880f 3257 #define A6XX_RB_SRGB_CNTL_SRGB_MRT0 0x00000001 3258 #define A6XX_RB_SRGB_CNTL_SRGB_MRT1 0x00000002 3259 #define A6XX_RB_SRGB_CNTL_SRGB_MRT2 0x00000004 3260 #define A6XX_RB_SRGB_CNTL_SRGB_MRT3 0x00000008 3261 #define A6XX_RB_SRGB_CNTL_SRGB_MRT4 0x00000010 3262 #define A6XX_RB_SRGB_CNTL_SRGB_MRT5 0x00000020 3263 #define A6XX_RB_SRGB_CNTL_SRGB_MRT6 0x00000040 3264 #define A6XX_RB_SRGB_CNTL_SRGB_MRT7 0x00000080 3265 3266 #define REG_A6XX_RB_SAMPLE_CNTL 0x00008810 3267 #define A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001 3268 3269 #define REG_A6XX_RB_UNKNOWN_8811 0x00008811 3270 3271 #define REG_A6XX_RB_UNKNOWN_8818 0x00008818 3272 3273 #define REG_A6XX_RB_UNKNOWN_8819 0x00008819 3274 3275 #define REG_A6XX_RB_UNKNOWN_881A 0x0000881a 3276 3277 #define REG_A6XX_RB_UNKNOWN_881B 0x0000881b 3278 3279 #define REG_A6XX_RB_UNKNOWN_881C 0x0000881c 3280 3281 #define REG_A6XX_RB_UNKNOWN_881D 0x0000881d 3282 3283 #define REG_A6XX_RB_UNKNOWN_881E 0x0000881e 3284 3285 static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; } 3286 3287 static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; } 3288 #define A6XX_RB_MRT_CONTROL_BLEND 0x00000001 3289 #define A6XX_RB_MRT_CONTROL_BLEND2 0x00000002 3290 #define A6XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004 3291 #define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078 3292 #define A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3 3293 static inline uint32_t A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) 3294 { 3295 return ((val) << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK; 3296 } 3297 #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780 3298 #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7 3299 static inline uint32_t A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 3300 { 3301 return ((val) << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 3302 } 3303 3304 static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; } 3305 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 3306 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 3307 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 3308 { 3309 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 3310 } 3311 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 3312 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 3313 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 3314 { 3315 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 3316 } 3317 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 3318 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 3319 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 3320 { 3321 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 3322 } 3323 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 3324 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 3325 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 3326 { 3327 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 3328 } 3329 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 3330 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 3331 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 3332 { 3333 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 3334 } 3335 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 3336 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 3337 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 3338 { 3339 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 3340 } 3341 3342 static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; } 3343 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff 3344 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 3345 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val) 3346 { 3347 return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 3348 } 3349 #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300 3350 #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8 3351 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val) 3352 { 3353 return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 3354 } 3355 #define A6XX_RB_MRT_BUF_INFO_UNK10__MASK 0x00000400 3356 #define A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT 10 3357 static inline uint32_t A6XX_RB_MRT_BUF_INFO_UNK10(uint32_t val) 3358 { 3359 return ((val) << A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT) & A6XX_RB_MRT_BUF_INFO_UNK10__MASK; 3360 } 3361 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000 3362 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13 3363 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 3364 { 3365 return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 3366 } 3367 3368 static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; } 3369 #define A6XX_RB_MRT_PITCH__MASK 0x0000ffff 3370 #define A6XX_RB_MRT_PITCH__SHIFT 0 3371 static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val) 3372 { 3373 return ((val >> 6) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK; 3374 } 3375 3376 static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; } 3377 #define A6XX_RB_MRT_ARRAY_PITCH__MASK 0x1fffffff 3378 #define A6XX_RB_MRT_ARRAY_PITCH__SHIFT 0 3379 static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val) 3380 { 3381 return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK; 3382 } 3383 3384 static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; } 3385 #define A6XX_RB_MRT_BASE__MASK 0xffffffff 3386 #define A6XX_RB_MRT_BASE__SHIFT 0 3387 static inline uint32_t A6XX_RB_MRT_BASE(uint32_t val) 3388 { 3389 return ((val) << A6XX_RB_MRT_BASE__SHIFT) & A6XX_RB_MRT_BASE__MASK; 3390 } 3391 3392 static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; } 3393 #define A6XX_RB_MRT_BASE_GMEM__MASK 0xfffff000 3394 #define A6XX_RB_MRT_BASE_GMEM__SHIFT 12 3395 static inline uint32_t A6XX_RB_MRT_BASE_GMEM(uint32_t val) 3396 { 3397 return ((val >> 12) << A6XX_RB_MRT_BASE_GMEM__SHIFT) & A6XX_RB_MRT_BASE_GMEM__MASK; 3398 } 3399 3400 #define REG_A6XX_RB_BLEND_RED_F32 0x00008860 3401 #define A6XX_RB_BLEND_RED_F32__MASK 0xffffffff 3402 #define A6XX_RB_BLEND_RED_F32__SHIFT 0 3403 static inline uint32_t A6XX_RB_BLEND_RED_F32(float val) 3404 { 3405 return ((fui(val)) << A6XX_RB_BLEND_RED_F32__SHIFT) & A6XX_RB_BLEND_RED_F32__MASK; 3406 } 3407 3408 #define REG_A6XX_RB_BLEND_GREEN_F32 0x00008861 3409 #define A6XX_RB_BLEND_GREEN_F32__MASK 0xffffffff 3410 #define A6XX_RB_BLEND_GREEN_F32__SHIFT 0 3411 static inline uint32_t A6XX_RB_BLEND_GREEN_F32(float val) 3412 { 3413 return ((fui(val)) << A6XX_RB_BLEND_GREEN_F32__SHIFT) & A6XX_RB_BLEND_GREEN_F32__MASK; 3414 } 3415 3416 #define REG_A6XX_RB_BLEND_BLUE_F32 0x00008862 3417 #define A6XX_RB_BLEND_BLUE_F32__MASK 0xffffffff 3418 #define A6XX_RB_BLEND_BLUE_F32__SHIFT 0 3419 static inline uint32_t A6XX_RB_BLEND_BLUE_F32(float val) 3420 { 3421 return ((fui(val)) << A6XX_RB_BLEND_BLUE_F32__SHIFT) & A6XX_RB_BLEND_BLUE_F32__MASK; 3422 } 3423 3424 #define REG_A6XX_RB_BLEND_ALPHA_F32 0x00008863 3425 #define A6XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff 3426 #define A6XX_RB_BLEND_ALPHA_F32__SHIFT 0 3427 static inline uint32_t A6XX_RB_BLEND_ALPHA_F32(float val) 3428 { 3429 return ((fui(val)) << A6XX_RB_BLEND_ALPHA_F32__SHIFT) & A6XX_RB_BLEND_ALPHA_F32__MASK; 3430 } 3431 3432 #define REG_A6XX_RB_ALPHA_CONTROL 0x00008864 3433 #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff 3434 #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 3435 static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) 3436 { 3437 return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; 3438 } 3439 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 3440 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 3441 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 3442 static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 3443 { 3444 return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; 3445 } 3446 3447 #define REG_A6XX_RB_BLEND_CNTL 0x00008865 3448 #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff 3449 #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 3450 static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val) 3451 { 3452 return ((val) << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK; 3453 } 3454 #define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100 3455 #define A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200 3456 #define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 3457 #define A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE 0x00000800 3458 #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000 3459 #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16 3460 static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val) 3461 { 3462 return ((val) << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK; 3463 } 3464 3465 #define REG_A6XX_RB_DEPTH_PLANE_CNTL 0x00008870 3466 #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003 3467 #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0 3468 static inline uint32_t A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val) 3469 { 3470 return ((val) << A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK; 3471 } 3472 3473 #define REG_A6XX_RB_DEPTH_CNTL 0x00008871 3474 #define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000001 3475 #define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002 3476 #define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c 3477 #define A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2 3478 static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) 3479 { 3480 return ((val) << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK; 3481 } 3482 #define A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE 0x00000020 3483 #define A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE 0x00000040 3484 #define A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE 0x00000080 3485 3486 #define REG_A6XX_RB_DEPTH_BUFFER_INFO 0x00008872 3487 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 3488 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 3489 static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) 3490 { 3491 return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; 3492 } 3493 #define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000018 3494 #define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT 3 3495 static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val) 3496 { 3497 return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK; 3498 } 3499 3500 #define REG_A6XX_RB_DEPTH_BUFFER_PITCH 0x00008873 3501 #define A6XX_RB_DEPTH_BUFFER_PITCH__MASK 0x00003fff 3502 #define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0 3503 static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) 3504 { 3505 return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK; 3506 } 3507 3508 #define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x00008874 3509 #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0x0fffffff 3510 #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0 3511 static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) 3512 { 3513 return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; 3514 } 3515 3516 #define REG_A6XX_RB_DEPTH_BUFFER_BASE 0x00008875 3517 #define A6XX_RB_DEPTH_BUFFER_BASE__MASK 0xffffffff 3518 #define A6XX_RB_DEPTH_BUFFER_BASE__SHIFT 0 3519 static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE(uint32_t val) 3520 { 3521 return ((val) << A6XX_RB_DEPTH_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE__MASK; 3522 } 3523 3524 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM 0x00008877 3525 #define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK 0xfffff000 3526 #define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT 12 3527 static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE_GMEM(uint32_t val) 3528 { 3529 return ((val >> 12) << A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK; 3530 } 3531 3532 #define REG_A6XX_RB_Z_BOUNDS_MIN 0x00008878 3533 #define A6XX_RB_Z_BOUNDS_MIN__MASK 0xffffffff 3534 #define A6XX_RB_Z_BOUNDS_MIN__SHIFT 0 3535 static inline uint32_t A6XX_RB_Z_BOUNDS_MIN(float val) 3536 { 3537 return ((fui(val)) << A6XX_RB_Z_BOUNDS_MIN__SHIFT) & A6XX_RB_Z_BOUNDS_MIN__MASK; 3538 } 3539 3540 #define REG_A6XX_RB_Z_BOUNDS_MAX 0x00008879 3541 #define A6XX_RB_Z_BOUNDS_MAX__MASK 0xffffffff 3542 #define A6XX_RB_Z_BOUNDS_MAX__SHIFT 0 3543 static inline uint32_t A6XX_RB_Z_BOUNDS_MAX(float val) 3544 { 3545 return ((fui(val)) << A6XX_RB_Z_BOUNDS_MAX__SHIFT) & A6XX_RB_Z_BOUNDS_MAX__MASK; 3546 } 3547 3548 #define REG_A6XX_RB_STENCIL_CONTROL 0x00008880 3549 #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 3550 #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 3551 #define A6XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 3552 #define A6XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 3553 #define A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 3554 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 3555 { 3556 return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC__MASK; 3557 } 3558 #define A6XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 3559 #define A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 3560 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 3561 { 3562 return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL__MASK; 3563 } 3564 #define A6XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 3565 #define A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 3566 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 3567 { 3568 return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK; 3569 } 3570 #define A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 3571 #define A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 3572 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 3573 { 3574 return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 3575 } 3576 #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 3577 #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 3578 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 3579 { 3580 return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 3581 } 3582 #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 3583 #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 3584 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 3585 { 3586 return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 3587 } 3588 #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 3589 #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 3590 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 3591 { 3592 return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 3593 } 3594 #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 3595 #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 3596 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 3597 { 3598 return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 3599 } 3600 3601 #define REG_A6XX_RB_STENCIL_INFO 0x00008881 3602 #define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 3603 #define A6XX_RB_STENCIL_INFO_UNK1 0x00000002 3604 3605 #define REG_A6XX_RB_STENCIL_BUFFER_PITCH 0x00008882 3606 #define A6XX_RB_STENCIL_BUFFER_PITCH__MASK 0x00000fff 3607 #define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT 0 3608 static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val) 3609 { 3610 return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK; 3611 } 3612 3613 #define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH 0x00008883 3614 #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK 0x00ffffff 3615 #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT 0 3616 static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val) 3617 { 3618 return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK; 3619 } 3620 3621 #define REG_A6XX_RB_STENCIL_BUFFER_BASE 0x00008884 3622 #define A6XX_RB_STENCIL_BUFFER_BASE__MASK 0xffffffff 3623 #define A6XX_RB_STENCIL_BUFFER_BASE__SHIFT 0 3624 static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE(uint32_t val) 3625 { 3626 return ((val) << A6XX_RB_STENCIL_BUFFER_BASE__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE__MASK; 3627 } 3628 3629 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM 0x00008886 3630 #define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK 0xfffff000 3631 #define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT 12 3632 static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE_GMEM(uint32_t val) 3633 { 3634 return ((val >> 12) << A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK; 3635 } 3636 3637 #define REG_A6XX_RB_STENCILREF 0x00008887 3638 #define A6XX_RB_STENCILREF_REF__MASK 0x000000ff 3639 #define A6XX_RB_STENCILREF_REF__SHIFT 0 3640 static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val) 3641 { 3642 return ((val) << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK; 3643 } 3644 #define A6XX_RB_STENCILREF_BFREF__MASK 0x0000ff00 3645 #define A6XX_RB_STENCILREF_BFREF__SHIFT 8 3646 static inline uint32_t A6XX_RB_STENCILREF_BFREF(uint32_t val) 3647 { 3648 return ((val) << A6XX_RB_STENCILREF_BFREF__SHIFT) & A6XX_RB_STENCILREF_BFREF__MASK; 3649 } 3650 3651 #define REG_A6XX_RB_STENCILMASK 0x00008888 3652 #define A6XX_RB_STENCILMASK_MASK__MASK 0x000000ff 3653 #define A6XX_RB_STENCILMASK_MASK__SHIFT 0 3654 static inline uint32_t A6XX_RB_STENCILMASK_MASK(uint32_t val) 3655 { 3656 return ((val) << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK; 3657 } 3658 #define A6XX_RB_STENCILMASK_BFMASK__MASK 0x0000ff00 3659 #define A6XX_RB_STENCILMASK_BFMASK__SHIFT 8 3660 static inline uint32_t A6XX_RB_STENCILMASK_BFMASK(uint32_t val) 3661 { 3662 return ((val) << A6XX_RB_STENCILMASK_BFMASK__SHIFT) & A6XX_RB_STENCILMASK_BFMASK__MASK; 3663 } 3664 3665 #define REG_A6XX_RB_STENCILWRMASK 0x00008889 3666 #define A6XX_RB_STENCILWRMASK_WRMASK__MASK 0x000000ff 3667 #define A6XX_RB_STENCILWRMASK_WRMASK__SHIFT 0 3668 static inline uint32_t A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val) 3669 { 3670 return ((val) << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK; 3671 } 3672 #define A6XX_RB_STENCILWRMASK_BFWRMASK__MASK 0x0000ff00 3673 #define A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT 8 3674 static inline uint32_t A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val) 3675 { 3676 return ((val) << A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_BFWRMASK__MASK; 3677 } 3678 3679 #define REG_A6XX_RB_WINDOW_OFFSET 0x00008890 3680 #define A6XX_RB_WINDOW_OFFSET_X__MASK 0x00003fff 3681 #define A6XX_RB_WINDOW_OFFSET_X__SHIFT 0 3682 static inline uint32_t A6XX_RB_WINDOW_OFFSET_X(uint32_t val) 3683 { 3684 return ((val) << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK; 3685 } 3686 #define A6XX_RB_WINDOW_OFFSET_Y__MASK 0x3fff0000 3687 #define A6XX_RB_WINDOW_OFFSET_Y__SHIFT 16 3688 static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val) 3689 { 3690 return ((val) << A6XX_RB_WINDOW_OFFSET_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET_Y__MASK; 3691 } 3692 3693 #define REG_A6XX_RB_SAMPLE_COUNT_CONTROL 0x00008891 3694 #define A6XX_RB_SAMPLE_COUNT_CONTROL_UNK0 0x00000001 3695 #define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 3696 3697 #define REG_A6XX_RB_LRZ_CNTL 0x00008898 3698 #define A6XX_RB_LRZ_CNTL_ENABLE 0x00000001 3699 3700 #define REG_A6XX_RB_Z_CLAMP_MIN 0x000088c0 3701 #define A6XX_RB_Z_CLAMP_MIN__MASK 0xffffffff 3702 #define A6XX_RB_Z_CLAMP_MIN__SHIFT 0 3703 static inline uint32_t A6XX_RB_Z_CLAMP_MIN(float val) 3704 { 3705 return ((fui(val)) << A6XX_RB_Z_CLAMP_MIN__SHIFT) & A6XX_RB_Z_CLAMP_MIN__MASK; 3706 } 3707 3708 #define REG_A6XX_RB_Z_CLAMP_MAX 0x000088c1 3709 #define A6XX_RB_Z_CLAMP_MAX__MASK 0xffffffff 3710 #define A6XX_RB_Z_CLAMP_MAX__SHIFT 0 3711 static inline uint32_t A6XX_RB_Z_CLAMP_MAX(float val) 3712 { 3713 return ((fui(val)) << A6XX_RB_Z_CLAMP_MAX__SHIFT) & A6XX_RB_Z_CLAMP_MAX__MASK; 3714 } 3715 3716 #define REG_A6XX_RB_UNKNOWN_88D0 0x000088d0 3717 #define A6XX_RB_UNKNOWN_88D0_UNK0__MASK 0x00001fff 3718 #define A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT 0 3719 static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK0(uint32_t val) 3720 { 3721 return ((val) << A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK0__MASK; 3722 } 3723 #define A6XX_RB_UNKNOWN_88D0_UNK16__MASK 0x07ff0000 3724 #define A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT 16 3725 static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK16(uint32_t val) 3726 { 3727 return ((val) << A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK16__MASK; 3728 } 3729 3730 #define REG_A6XX_RB_BLIT_SCISSOR_TL 0x000088d1 3731 #define A6XX_RB_BLIT_SCISSOR_TL_X__MASK 0x00003fff 3732 #define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT 0 3733 static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val) 3734 { 3735 return ((val) << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK; 3736 } 3737 #define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK 0x3fff0000 3738 #define A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT 16 3739 static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val) 3740 { 3741 return ((val) << A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_Y__MASK; 3742 } 3743 3744 #define REG_A6XX_RB_BLIT_SCISSOR_BR 0x000088d2 3745 #define A6XX_RB_BLIT_SCISSOR_BR_X__MASK 0x00003fff 3746 #define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT 0 3747 static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val) 3748 { 3749 return ((val) << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK; 3750 } 3751 #define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK 0x3fff0000 3752 #define A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT 16 3753 static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val) 3754 { 3755 return ((val) << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK; 3756 } 3757 3758 #define REG_A6XX_RB_BIN_CONTROL2 0x000088d3 3759 #define A6XX_RB_BIN_CONTROL2_BINW__MASK 0x0000003f 3760 #define A6XX_RB_BIN_CONTROL2_BINW__SHIFT 0 3761 static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val) 3762 { 3763 return ((val >> 5) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK; 3764 } 3765 #define A6XX_RB_BIN_CONTROL2_BINH__MASK 0x00007f00 3766 #define A6XX_RB_BIN_CONTROL2_BINH__SHIFT 8 3767 static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val) 3768 { 3769 return ((val >> 4) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK; 3770 } 3771 3772 #define REG_A6XX_RB_WINDOW_OFFSET2 0x000088d4 3773 #define A6XX_RB_WINDOW_OFFSET2_X__MASK 0x00003fff 3774 #define A6XX_RB_WINDOW_OFFSET2_X__SHIFT 0 3775 static inline uint32_t A6XX_RB_WINDOW_OFFSET2_X(uint32_t val) 3776 { 3777 return ((val) << A6XX_RB_WINDOW_OFFSET2_X__SHIFT) & A6XX_RB_WINDOW_OFFSET2_X__MASK; 3778 } 3779 #define A6XX_RB_WINDOW_OFFSET2_Y__MASK 0x3fff0000 3780 #define A6XX_RB_WINDOW_OFFSET2_Y__SHIFT 16 3781 static inline uint32_t A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val) 3782 { 3783 return ((val) << A6XX_RB_WINDOW_OFFSET2_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET2_Y__MASK; 3784 } 3785 3786 #define REG_A6XX_RB_MSAA_CNTL 0x000088d5 3787 #define A6XX_RB_MSAA_CNTL_SAMPLES__MASK 0x00000018 3788 #define A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT 3 3789 static inline uint32_t A6XX_RB_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 3790 { 3791 return ((val) << A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_MSAA_CNTL_SAMPLES__MASK; 3792 } 3793 3794 #define REG_A6XX_RB_BLIT_BASE_GMEM 0x000088d6 3795 #define A6XX_RB_BLIT_BASE_GMEM__MASK 0xfffff000 3796 #define A6XX_RB_BLIT_BASE_GMEM__SHIFT 12 3797 static inline uint32_t A6XX_RB_BLIT_BASE_GMEM(uint32_t val) 3798 { 3799 return ((val >> 12) << A6XX_RB_BLIT_BASE_GMEM__SHIFT) & A6XX_RB_BLIT_BASE_GMEM__MASK; 3800 } 3801 3802 #define REG_A6XX_RB_BLIT_DST_INFO 0x000088d7 3803 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK 0x00000003 3804 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT 0 3805 static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) 3806 { 3807 return ((val) << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK; 3808 } 3809 #define A6XX_RB_BLIT_DST_INFO_FLAGS 0x00000004 3810 #define A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK 0x00000018 3811 #define A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT 3 3812 static inline uint32_t A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) 3813 { 3814 return ((val) << A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK; 3815 } 3816 #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK 0x00000060 3817 #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT 5 3818 static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) 3819 { 3820 return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK; 3821 } 3822 #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK 0x00007f80 3823 #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT 7 3824 static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_format val) 3825 { 3826 return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK; 3827 } 3828 #define A6XX_RB_BLIT_DST_INFO_UNK15 0x00008000 3829 3830 #define REG_A6XX_RB_BLIT_DST 0x000088d8 3831 #define A6XX_RB_BLIT_DST__MASK 0xffffffff 3832 #define A6XX_RB_BLIT_DST__SHIFT 0 3833 static inline uint32_t A6XX_RB_BLIT_DST(uint32_t val) 3834 { 3835 return ((val) << A6XX_RB_BLIT_DST__SHIFT) & A6XX_RB_BLIT_DST__MASK; 3836 } 3837 3838 #define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da 3839 #define A6XX_RB_BLIT_DST_PITCH__MASK 0x0000ffff 3840 #define A6XX_RB_BLIT_DST_PITCH__SHIFT 0 3841 static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val) 3842 { 3843 return ((val >> 6) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK; 3844 } 3845 3846 #define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH 0x000088db 3847 #define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0x1fffffff 3848 #define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0 3849 static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) 3850 { 3851 return ((val >> 6) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK; 3852 } 3853 3854 #define REG_A6XX_RB_BLIT_FLAG_DST 0x000088dc 3855 #define A6XX_RB_BLIT_FLAG_DST__MASK 0xffffffff 3856 #define A6XX_RB_BLIT_FLAG_DST__SHIFT 0 3857 static inline uint32_t A6XX_RB_BLIT_FLAG_DST(uint32_t val) 3858 { 3859 return ((val) << A6XX_RB_BLIT_FLAG_DST__SHIFT) & A6XX_RB_BLIT_FLAG_DST__MASK; 3860 } 3861 3862 #define REG_A6XX_RB_BLIT_FLAG_DST_PITCH 0x000088de 3863 #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK 0x000007ff 3864 #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT 0 3865 static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val) 3866 { 3867 return ((val >> 6) << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK; 3868 } 3869 #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK 0x0ffff800 3870 #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT 11 3871 static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val) 3872 { 3873 return ((val >> 7) << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK; 3874 } 3875 3876 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 0x000088df 3877 3878 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1 0x000088e0 3879 3880 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2 0x000088e1 3881 3882 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3 0x000088e2 3883 3884 #define REG_A6XX_RB_BLIT_INFO 0x000088e3 3885 #define A6XX_RB_BLIT_INFO_UNK0 0x00000001 3886 #define A6XX_RB_BLIT_INFO_GMEM 0x00000002 3887 #define A6XX_RB_BLIT_INFO_SAMPLE_0 0x00000004 3888 #define A6XX_RB_BLIT_INFO_DEPTH 0x00000008 3889 #define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK 0x000000f0 3890 #define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT 4 3891 static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val) 3892 { 3893 return ((val) << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK; 3894 } 3895 #define A6XX_RB_BLIT_INFO_UNK8__MASK 0x00000300 3896 #define A6XX_RB_BLIT_INFO_UNK8__SHIFT 8 3897 static inline uint32_t A6XX_RB_BLIT_INFO_UNK8(uint32_t val) 3898 { 3899 return ((val) << A6XX_RB_BLIT_INFO_UNK8__SHIFT) & A6XX_RB_BLIT_INFO_UNK8__MASK; 3900 } 3901 #define A6XX_RB_BLIT_INFO_UNK12__MASK 0x0000f000 3902 #define A6XX_RB_BLIT_INFO_UNK12__SHIFT 12 3903 static inline uint32_t A6XX_RB_BLIT_INFO_UNK12(uint32_t val) 3904 { 3905 return ((val) << A6XX_RB_BLIT_INFO_UNK12__SHIFT) & A6XX_RB_BLIT_INFO_UNK12__MASK; 3906 } 3907 3908 #define REG_A6XX_RB_UNKNOWN_88F0 0x000088f0 3909 3910 #define REG_A6XX_RB_UNK_FLAG_BUFFER_BASE 0x000088f1 3911 #define A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK 0xffffffff 3912 #define A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT 0 3913 static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_BASE(uint32_t val) 3914 { 3915 return ((val) << A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK; 3916 } 3917 3918 #define REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH 0x000088f3 3919 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff 3920 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 3921 static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(uint32_t val) 3922 { 3923 return ((val >> 6) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK; 3924 } 3925 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x00fff800 3926 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 3927 static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 3928 { 3929 return ((val >> 7) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; 3930 } 3931 3932 #define REG_A6XX_RB_UNKNOWN_88F4 0x000088f4 3933 3934 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE 0x00008900 3935 #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK 0xffffffff 3936 #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT 0 3937 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_BASE(uint32_t val) 3938 { 3939 return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK; 3940 } 3941 3942 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x00008902 3943 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK 0x0000007f 3944 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 3945 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val) 3946 { 3947 return ((val >> 6) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK; 3948 } 3949 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK 0x00000700 3950 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT 8 3951 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8(uint32_t val) 3952 { 3953 return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK; 3954 } 3955 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x0ffff800 3956 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 3957 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 3958 { 3959 return ((val >> 7) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; 3960 } 3961 3962 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; } 3963 3964 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; } 3965 #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK 0xffffffff 3966 #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT 0 3967 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t val) 3968 { 3969 return ((val) << A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK; 3970 } 3971 3972 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; } 3973 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff 3974 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 3975 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val) 3976 { 3977 return ((val >> 6) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK; 3978 } 3979 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffff800 3980 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 3981 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 3982 { 3983 return ((val >> 7) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; 3984 } 3985 3986 #define REG_A6XX_RB_SAMPLE_COUNT_ADDR 0x00008927 3987 #define A6XX_RB_SAMPLE_COUNT_ADDR__MASK 0xffffffff 3988 #define A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT 0 3989 static inline uint32_t A6XX_RB_SAMPLE_COUNT_ADDR(uint32_t val) 3990 { 3991 return ((val) << A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT) & A6XX_RB_SAMPLE_COUNT_ADDR__MASK; 3992 } 3993 3994 #define REG_A6XX_RB_UNKNOWN_8A00 0x00008a00 3995 3996 #define REG_A6XX_RB_UNKNOWN_8A10 0x00008a10 3997 3998 #define REG_A6XX_RB_UNKNOWN_8A20 0x00008a20 3999 4000 #define REG_A6XX_RB_UNKNOWN_8A30 0x00008a30 4001 4002 #define REG_A6XX_RB_2D_BLIT_CNTL 0x00008c00 4003 #define A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK 0x00000007 4004 #define A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT 0 4005 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val) 4006 { 4007 return ((val) << A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK; 4008 } 4009 #define A6XX_RB_2D_BLIT_CNTL_OVERWRITEEN 0x00000008 4010 #define A6XX_RB_2D_BLIT_CNTL_UNK4__MASK 0x00000070 4011 #define A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT 4 4012 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK4(uint32_t val) 4013 { 4014 return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK4__MASK; 4015 } 4016 #define A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR 0x00000080 4017 #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00 4018 #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8 4019 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val) 4020 { 4021 return ((val) << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK; 4022 } 4023 #define A6XX_RB_2D_BLIT_CNTL_SCISSOR 0x00010000 4024 #define A6XX_RB_2D_BLIT_CNTL_UNK17__MASK 0x00060000 4025 #define A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT 17 4026 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK17(uint32_t val) 4027 { 4028 return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK17__MASK; 4029 } 4030 #define A6XX_RB_2D_BLIT_CNTL_D24S8 0x00080000 4031 #define A6XX_RB_2D_BLIT_CNTL_MASK__MASK 0x00f00000 4032 #define A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT 20 4033 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_MASK(uint32_t val) 4034 { 4035 return ((val) << A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_RB_2D_BLIT_CNTL_MASK__MASK; 4036 } 4037 #define A6XX_RB_2D_BLIT_CNTL_IFMT__MASK 0x1f000000 4038 #define A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT 24 4039 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val) 4040 { 4041 return ((val) << A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_IFMT__MASK; 4042 } 4043 #define A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK 0x20000000 4044 #define A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT 29 4045 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val) 4046 { 4047 return ((val) << A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK; 4048 } 4049 4050 #define REG_A6XX_RB_2D_UNKNOWN_8C01 0x00008c01 4051 4052 #define REG_A6XX_RB_2D_DST_INFO 0x00008c17 4053 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff 4054 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0 4055 static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_format val) 4056 { 4057 return ((val) << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK; 4058 } 4059 #define A6XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300 4060 #define A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8 4061 static inline uint32_t A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) 4062 { 4063 return ((val) << A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_2D_DST_INFO_TILE_MODE__MASK; 4064 } 4065 #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00 4066 #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10 4067 static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) 4068 { 4069 return ((val) << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK; 4070 } 4071 #define A6XX_RB_2D_DST_INFO_FLAGS 0x00001000 4072 #define A6XX_RB_2D_DST_INFO_SRGB 0x00002000 4073 #define A6XX_RB_2D_DST_INFO_SAMPLES__MASK 0x0000c000 4074 #define A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT 14 4075 static inline uint32_t A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) 4076 { 4077 return ((val) << A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_2D_DST_INFO_SAMPLES__MASK; 4078 } 4079 #define A6XX_RB_2D_DST_INFO_FILTER 0x00010000 4080 #define A6XX_RB_2D_DST_INFO_UNK17 0x00020000 4081 #define A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE 0x00040000 4082 #define A6XX_RB_2D_DST_INFO_UNK19 0x00080000 4083 #define A6XX_RB_2D_DST_INFO_UNK20 0x00100000 4084 #define A6XX_RB_2D_DST_INFO_UNK21 0x00200000 4085 #define A6XX_RB_2D_DST_INFO_UNK22 0x00400000 4086 #define A6XX_RB_2D_DST_INFO_UNK23__MASK 0x07800000 4087 #define A6XX_RB_2D_DST_INFO_UNK23__SHIFT 23 4088 static inline uint32_t A6XX_RB_2D_DST_INFO_UNK23(uint32_t val) 4089 { 4090 return ((val) << A6XX_RB_2D_DST_INFO_UNK23__SHIFT) & A6XX_RB_2D_DST_INFO_UNK23__MASK; 4091 } 4092 #define A6XX_RB_2D_DST_INFO_UNK28 0x10000000 4093 4094 #define REG_A6XX_RB_2D_DST 0x00008c18 4095 #define A6XX_RB_2D_DST__MASK 0xffffffff 4096 #define A6XX_RB_2D_DST__SHIFT 0 4097 static inline uint32_t A6XX_RB_2D_DST(uint32_t val) 4098 { 4099 return ((val) << A6XX_RB_2D_DST__SHIFT) & A6XX_RB_2D_DST__MASK; 4100 } 4101 4102 #define REG_A6XX_RB_2D_DST_PITCH 0x00008c1a 4103 #define A6XX_RB_2D_DST_PITCH__MASK 0x0000ffff 4104 #define A6XX_RB_2D_DST_PITCH__SHIFT 0 4105 static inline uint32_t A6XX_RB_2D_DST_PITCH(uint32_t val) 4106 { 4107 return ((val >> 6) << A6XX_RB_2D_DST_PITCH__SHIFT) & A6XX_RB_2D_DST_PITCH__MASK; 4108 } 4109 4110 #define REG_A6XX_RB_2D_DST_PLANE1 0x00008c1b 4111 #define A6XX_RB_2D_DST_PLANE1__MASK 0xffffffff 4112 #define A6XX_RB_2D_DST_PLANE1__SHIFT 0 4113 static inline uint32_t A6XX_RB_2D_DST_PLANE1(uint32_t val) 4114 { 4115 return ((val) << A6XX_RB_2D_DST_PLANE1__SHIFT) & A6XX_RB_2D_DST_PLANE1__MASK; 4116 } 4117 4118 #define REG_A6XX_RB_2D_DST_PLANE_PITCH 0x00008c1d 4119 #define A6XX_RB_2D_DST_PLANE_PITCH__MASK 0x0000ffff 4120 #define A6XX_RB_2D_DST_PLANE_PITCH__SHIFT 0 4121 static inline uint32_t A6XX_RB_2D_DST_PLANE_PITCH(uint32_t val) 4122 { 4123 return ((val >> 6) << A6XX_RB_2D_DST_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_PLANE_PITCH__MASK; 4124 } 4125 4126 #define REG_A6XX_RB_2D_DST_PLANE2 0x00008c1e 4127 #define A6XX_RB_2D_DST_PLANE2__MASK 0xffffffff 4128 #define A6XX_RB_2D_DST_PLANE2__SHIFT 0 4129 static inline uint32_t A6XX_RB_2D_DST_PLANE2(uint32_t val) 4130 { 4131 return ((val) << A6XX_RB_2D_DST_PLANE2__SHIFT) & A6XX_RB_2D_DST_PLANE2__MASK; 4132 } 4133 4134 #define REG_A6XX_RB_2D_DST_FLAGS 0x00008c20 4135 #define A6XX_RB_2D_DST_FLAGS__MASK 0xffffffff 4136 #define A6XX_RB_2D_DST_FLAGS__SHIFT 0 4137 static inline uint32_t A6XX_RB_2D_DST_FLAGS(uint32_t val) 4138 { 4139 return ((val) << A6XX_RB_2D_DST_FLAGS__SHIFT) & A6XX_RB_2D_DST_FLAGS__MASK; 4140 } 4141 4142 #define REG_A6XX_RB_2D_DST_FLAGS_PITCH 0x00008c22 4143 #define A6XX_RB_2D_DST_FLAGS_PITCH__MASK 0x000000ff 4144 #define A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT 0 4145 static inline uint32_t A6XX_RB_2D_DST_FLAGS_PITCH(uint32_t val) 4146 { 4147 return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH__MASK; 4148 } 4149 4150 #define REG_A6XX_RB_2D_DST_FLAGS_PLANE 0x00008c23 4151 #define A6XX_RB_2D_DST_FLAGS_PLANE__MASK 0xffffffff 4152 #define A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT 0 4153 static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE(uint32_t val) 4154 { 4155 return ((val) << A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE__MASK; 4156 } 4157 4158 #define REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH 0x00008c25 4159 #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK 0x000000ff 4160 #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT 0 4161 static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(uint32_t val) 4162 { 4163 return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK; 4164 } 4165 4166 #define REG_A6XX_RB_2D_SRC_SOLID_C0 0x00008c2c 4167 4168 #define REG_A6XX_RB_2D_SRC_SOLID_C1 0x00008c2d 4169 4170 #define REG_A6XX_RB_2D_SRC_SOLID_C2 0x00008c2e 4171 4172 #define REG_A6XX_RB_2D_SRC_SOLID_C3 0x00008c2f 4173 4174 #define REG_A6XX_RB_UNKNOWN_8E01 0x00008e01 4175 4176 #define REG_A6XX_RB_UNKNOWN_8E04 0x00008e04 4177 4178 #define REG_A6XX_RB_ADDR_MODE_CNTL 0x00008e05 4179 4180 #define REG_A6XX_RB_CCU_CNTL 0x00008e07 4181 #define A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK 0xff800000 4182 #define A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT 23 4183 static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_OFFSET(uint32_t val) 4184 { 4185 return ((val >> 12) << A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK; 4186 } 4187 #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK 0x001ff000 4188 #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT 12 4189 static inline uint32_t A6XX_RB_CCU_CNTL_DEPTH_OFFSET(uint32_t val) 4190 { 4191 return ((val >> 12) << A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK; 4192 } 4193 #define A6XX_RB_CCU_CNTL_GMEM 0x00400000 4194 #define A6XX_RB_CCU_CNTL_UNK2 0x00000004 4195 4196 #define REG_A6XX_RB_NC_MODE_CNTL 0x00008e08 4197 #define A6XX_RB_NC_MODE_CNTL_MODE 0x00000001 4198 #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006 4199 #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT 1 4200 static inline uint32_t A6XX_RB_NC_MODE_CNTL_LOWER_BIT(uint32_t val) 4201 { 4202 return ((val) << A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK; 4203 } 4204 #define A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008 4205 #define A6XX_RB_NC_MODE_CNTL_AMSBC 0x00000010 4206 #define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000400 4207 #define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT 10 4208 static inline uint32_t A6XX_RB_NC_MODE_CNTL_UPPER_BIT(uint32_t val) 4209 { 4210 return ((val) << A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK; 4211 } 4212 #define A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR 0x00000800 4213 #define A6XX_RB_NC_MODE_CNTL_UNK12__MASK 0x00003000 4214 #define A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT 12 4215 static inline uint32_t A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val) 4216 { 4217 return ((val) << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK; 4218 } 4219 4220 static inline uint32_t REG_A6XX_RB_PERFCTR_RB_SEL(uint32_t i0) { return 0x00008e10 + 0x1*i0; } 4221 4222 static inline uint32_t REG_A6XX_RB_PERFCTR_CCU_SEL(uint32_t i0) { return 0x00008e18 + 0x1*i0; } 4223 4224 #define REG_A6XX_RB_UNKNOWN_8E28 0x00008e28 4225 4226 static inline uint32_t REG_A6XX_RB_PERFCTR_CMP_SEL(uint32_t i0) { return 0x00008e2c + 0x1*i0; } 4227 4228 #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST 0x00008e3b 4229 4230 #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD 0x00008e3d 4231 4232 #define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x00008e50 4233 4234 #define REG_A6XX_RB_UNKNOWN_8E51 0x00008e51 4235 #define A6XX_RB_UNKNOWN_8E51__MASK 0xffffffff 4236 #define A6XX_RB_UNKNOWN_8E51__SHIFT 0 4237 static inline uint32_t A6XX_RB_UNKNOWN_8E51(uint32_t val) 4238 { 4239 return ((val) << A6XX_RB_UNKNOWN_8E51__SHIFT) & A6XX_RB_UNKNOWN_8E51__MASK; 4240 } 4241 4242 #define REG_A6XX_VPC_GS_PARAM 0x00009100 4243 #define A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK 0x000000ff 4244 #define A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT 0 4245 static inline uint32_t A6XX_VPC_GS_PARAM_LINELENGTHLOC(uint32_t val) 4246 { 4247 return ((val) << A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT) & A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK; 4248 } 4249 4250 #define REG_A6XX_VPC_VS_CLIP_CNTL 0x00009101 4251 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff 4252 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT 0 4253 static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(uint32_t val) 4254 { 4255 return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK; 4256 } 4257 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00 4258 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8 4259 static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) 4260 { 4261 return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK; 4262 } 4263 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000 4264 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16 4265 static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) 4266 { 4267 return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; 4268 } 4269 4270 #define REG_A6XX_VPC_GS_CLIP_CNTL 0x00009102 4271 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff 4272 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT 0 4273 static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK(uint32_t val) 4274 { 4275 return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK; 4276 } 4277 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00 4278 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8 4279 static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) 4280 { 4281 return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK; 4282 } 4283 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000 4284 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16 4285 static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) 4286 { 4287 return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; 4288 } 4289 4290 #define REG_A6XX_VPC_DS_CLIP_CNTL 0x00009103 4291 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff 4292 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT 0 4293 static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK(uint32_t val) 4294 { 4295 return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK; 4296 } 4297 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00 4298 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8 4299 static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) 4300 { 4301 return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK; 4302 } 4303 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000 4304 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16 4305 static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) 4306 { 4307 return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; 4308 } 4309 4310 #define REG_A6XX_VPC_VS_LAYER_CNTL 0x00009104 4311 #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff 4312 #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT 0 4313 static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(uint32_t val) 4314 { 4315 return ((val) << A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK; 4316 } 4317 #define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00 4318 #define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT 8 4319 static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(uint32_t val) 4320 { 4321 return ((val) << A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK; 4322 } 4323 4324 #define REG_A6XX_VPC_GS_LAYER_CNTL 0x00009105 4325 #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff 4326 #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT 0 4327 static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(uint32_t val) 4328 { 4329 return ((val) << A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK; 4330 } 4331 #define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00 4332 #define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT 8 4333 static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(uint32_t val) 4334 { 4335 return ((val) << A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK; 4336 } 4337 4338 #define REG_A6XX_VPC_DS_LAYER_CNTL 0x00009106 4339 #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff 4340 #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT 0 4341 static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_LAYERLOC(uint32_t val) 4342 { 4343 return ((val) << A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK; 4344 } 4345 #define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00 4346 #define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT 8 4347 static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val) 4348 { 4349 return ((val) << A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK; 4350 } 4351 4352 #define REG_A6XX_VPC_UNKNOWN_9107 0x00009107 4353 #define A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD 0x00000001 4354 #define A6XX_VPC_UNKNOWN_9107_UNK2 0x00000004 4355 4356 #define REG_A6XX_VPC_POLYGON_MODE 0x00009108 4357 #define A6XX_VPC_POLYGON_MODE_MODE__MASK 0x00000003 4358 #define A6XX_VPC_POLYGON_MODE_MODE__SHIFT 0 4359 static inline uint32_t A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) 4360 { 4361 return ((val) << A6XX_VPC_POLYGON_MODE_MODE__SHIFT) & A6XX_VPC_POLYGON_MODE_MODE__MASK; 4362 } 4363 4364 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; } 4365 4366 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; } 4367 4368 static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; } 4369 4370 static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; } 4371 4372 #define REG_A6XX_VPC_UNKNOWN_9210 0x00009210 4373 4374 #define REG_A6XX_VPC_UNKNOWN_9211 0x00009211 4375 4376 static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; } 4377 4378 static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; } 4379 4380 #define REG_A6XX_VPC_SO_CNTL 0x00009216 4381 #define A6XX_VPC_SO_CNTL_ADDR__MASK 0x000000ff 4382 #define A6XX_VPC_SO_CNTL_ADDR__SHIFT 0 4383 static inline uint32_t A6XX_VPC_SO_CNTL_ADDR(uint32_t val) 4384 { 4385 return ((val) << A6XX_VPC_SO_CNTL_ADDR__SHIFT) & A6XX_VPC_SO_CNTL_ADDR__MASK; 4386 } 4387 #define A6XX_VPC_SO_CNTL_RESET 0x00010000 4388 4389 #define REG_A6XX_VPC_SO_PROG 0x00009217 4390 #define A6XX_VPC_SO_PROG_A_BUF__MASK 0x00000003 4391 #define A6XX_VPC_SO_PROG_A_BUF__SHIFT 0 4392 static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val) 4393 { 4394 return ((val) << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK; 4395 } 4396 #define A6XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc 4397 #define A6XX_VPC_SO_PROG_A_OFF__SHIFT 2 4398 static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val) 4399 { 4400 return ((val >> 2) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK; 4401 } 4402 #define A6XX_VPC_SO_PROG_A_EN 0x00000800 4403 #define A6XX_VPC_SO_PROG_B_BUF__MASK 0x00003000 4404 #define A6XX_VPC_SO_PROG_B_BUF__SHIFT 12 4405 static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val) 4406 { 4407 return ((val) << A6XX_VPC_SO_PROG_B_BUF__SHIFT) & A6XX_VPC_SO_PROG_B_BUF__MASK; 4408 } 4409 #define A6XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000 4410 #define A6XX_VPC_SO_PROG_B_OFF__SHIFT 14 4411 static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val) 4412 { 4413 return ((val >> 2) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK; 4414 } 4415 #define A6XX_VPC_SO_PROG_B_EN 0x00800000 4416 4417 #define REG_A6XX_VPC_SO_STREAM_COUNTS 0x00009218 4418 #define A6XX_VPC_SO_STREAM_COUNTS__MASK 0xffffffff 4419 #define A6XX_VPC_SO_STREAM_COUNTS__SHIFT 0 4420 static inline uint32_t A6XX_VPC_SO_STREAM_COUNTS(uint32_t val) 4421 { 4422 return ((val) << A6XX_VPC_SO_STREAM_COUNTS__SHIFT) & A6XX_VPC_SO_STREAM_COUNTS__MASK; 4423 } 4424 4425 static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; } 4426 4427 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0) { return 0x0000921a + 0x7*i0; } 4428 #define A6XX_VPC_SO_BUFFER_BASE__MASK 0xffffffff 4429 #define A6XX_VPC_SO_BUFFER_BASE__SHIFT 0 4430 static inline uint32_t A6XX_VPC_SO_BUFFER_BASE(uint32_t val) 4431 { 4432 return ((val) << A6XX_VPC_SO_BUFFER_BASE__SHIFT) & A6XX_VPC_SO_BUFFER_BASE__MASK; 4433 } 4434 4435 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; } 4436 #define A6XX_VPC_SO_BUFFER_SIZE__MASK 0xfffffffc 4437 #define A6XX_VPC_SO_BUFFER_SIZE__SHIFT 2 4438 static inline uint32_t A6XX_VPC_SO_BUFFER_SIZE(uint32_t val) 4439 { 4440 return ((val >> 2) << A6XX_VPC_SO_BUFFER_SIZE__SHIFT) & A6XX_VPC_SO_BUFFER_SIZE__MASK; 4441 } 4442 4443 static inline uint32_t REG_A6XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000921d + 0x7*i0; } 4444 4445 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; } 4446 #define A6XX_VPC_SO_BUFFER_OFFSET__MASK 0xfffffffc 4447 #define A6XX_VPC_SO_BUFFER_OFFSET__SHIFT 2 4448 static inline uint32_t A6XX_VPC_SO_BUFFER_OFFSET(uint32_t val) 4449 { 4450 return ((val >> 2) << A6XX_VPC_SO_BUFFER_OFFSET__SHIFT) & A6XX_VPC_SO_BUFFER_OFFSET__MASK; 4451 } 4452 4453 static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0) { return 0x0000921f + 0x7*i0; } 4454 #define A6XX_VPC_SO_FLUSH_BASE__MASK 0xffffffff 4455 #define A6XX_VPC_SO_FLUSH_BASE__SHIFT 0 4456 static inline uint32_t A6XX_VPC_SO_FLUSH_BASE(uint32_t val) 4457 { 4458 return ((val) << A6XX_VPC_SO_FLUSH_BASE__SHIFT) & A6XX_VPC_SO_FLUSH_BASE__MASK; 4459 } 4460 4461 #define REG_A6XX_VPC_POINT_COORD_INVERT 0x00009236 4462 #define A6XX_VPC_POINT_COORD_INVERT_INVERT 0x00000001 4463 4464 #define REG_A6XX_VPC_UNKNOWN_9300 0x00009300 4465 4466 #define REG_A6XX_VPC_VS_PACK 0x00009301 4467 #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK 0x000000ff 4468 #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT 0 4469 static inline uint32_t A6XX_VPC_VS_PACK_STRIDE_IN_VPC(uint32_t val) 4470 { 4471 return ((val) << A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK; 4472 } 4473 #define A6XX_VPC_VS_PACK_POSITIONLOC__MASK 0x0000ff00 4474 #define A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT 8 4475 static inline uint32_t A6XX_VPC_VS_PACK_POSITIONLOC(uint32_t val) 4476 { 4477 return ((val) << A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_VS_PACK_POSITIONLOC__MASK; 4478 } 4479 #define A6XX_VPC_VS_PACK_PSIZELOC__MASK 0x00ff0000 4480 #define A6XX_VPC_VS_PACK_PSIZELOC__SHIFT 16 4481 static inline uint32_t A6XX_VPC_VS_PACK_PSIZELOC(uint32_t val) 4482 { 4483 return ((val) << A6XX_VPC_VS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_VS_PACK_PSIZELOC__MASK; 4484 } 4485 #define A6XX_VPC_VS_PACK_EXTRAPOS__MASK 0x0f000000 4486 #define A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT 24 4487 static inline uint32_t A6XX_VPC_VS_PACK_EXTRAPOS(uint32_t val) 4488 { 4489 return ((val) << A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_VS_PACK_EXTRAPOS__MASK; 4490 } 4491 4492 #define REG_A6XX_VPC_GS_PACK 0x00009302 4493 #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK 0x000000ff 4494 #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT 0 4495 static inline uint32_t A6XX_VPC_GS_PACK_STRIDE_IN_VPC(uint32_t val) 4496 { 4497 return ((val) << A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK; 4498 } 4499 #define A6XX_VPC_GS_PACK_POSITIONLOC__MASK 0x0000ff00 4500 #define A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT 8 4501 static inline uint32_t A6XX_VPC_GS_PACK_POSITIONLOC(uint32_t val) 4502 { 4503 return ((val) << A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_GS_PACK_POSITIONLOC__MASK; 4504 } 4505 #define A6XX_VPC_GS_PACK_PSIZELOC__MASK 0x00ff0000 4506 #define A6XX_VPC_GS_PACK_PSIZELOC__SHIFT 16 4507 static inline uint32_t A6XX_VPC_GS_PACK_PSIZELOC(uint32_t val) 4508 { 4509 return ((val) << A6XX_VPC_GS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_GS_PACK_PSIZELOC__MASK; 4510 } 4511 #define A6XX_VPC_GS_PACK_EXTRAPOS__MASK 0x0f000000 4512 #define A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT 24 4513 static inline uint32_t A6XX_VPC_GS_PACK_EXTRAPOS(uint32_t val) 4514 { 4515 return ((val) << A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_GS_PACK_EXTRAPOS__MASK; 4516 } 4517 4518 #define REG_A6XX_VPC_DS_PACK 0x00009303 4519 #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK 0x000000ff 4520 #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT 0 4521 static inline uint32_t A6XX_VPC_DS_PACK_STRIDE_IN_VPC(uint32_t val) 4522 { 4523 return ((val) << A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK; 4524 } 4525 #define A6XX_VPC_DS_PACK_POSITIONLOC__MASK 0x0000ff00 4526 #define A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT 8 4527 static inline uint32_t A6XX_VPC_DS_PACK_POSITIONLOC(uint32_t val) 4528 { 4529 return ((val) << A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_DS_PACK_POSITIONLOC__MASK; 4530 } 4531 #define A6XX_VPC_DS_PACK_PSIZELOC__MASK 0x00ff0000 4532 #define A6XX_VPC_DS_PACK_PSIZELOC__SHIFT 16 4533 static inline uint32_t A6XX_VPC_DS_PACK_PSIZELOC(uint32_t val) 4534 { 4535 return ((val) << A6XX_VPC_DS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_DS_PACK_PSIZELOC__MASK; 4536 } 4537 #define A6XX_VPC_DS_PACK_EXTRAPOS__MASK 0x0f000000 4538 #define A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT 24 4539 static inline uint32_t A6XX_VPC_DS_PACK_EXTRAPOS(uint32_t val) 4540 { 4541 return ((val) << A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_DS_PACK_EXTRAPOS__MASK; 4542 } 4543 4544 #define REG_A6XX_VPC_CNTL_0 0x00009304 4545 #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK 0x000000ff 4546 #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT 0 4547 static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val) 4548 { 4549 return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK; 4550 } 4551 #define A6XX_VPC_CNTL_0_PRIMIDLOC__MASK 0x0000ff00 4552 #define A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT 8 4553 static inline uint32_t A6XX_VPC_CNTL_0_PRIMIDLOC(uint32_t val) 4554 { 4555 return ((val) << A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT) & A6XX_VPC_CNTL_0_PRIMIDLOC__MASK; 4556 } 4557 #define A6XX_VPC_CNTL_0_VARYING 0x00010000 4558 #define A6XX_VPC_CNTL_0_VIEWIDLOC__MASK 0xff000000 4559 #define A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT 24 4560 static inline uint32_t A6XX_VPC_CNTL_0_VIEWIDLOC(uint32_t val) 4561 { 4562 return ((val) << A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT) & A6XX_VPC_CNTL_0_VIEWIDLOC__MASK; 4563 } 4564 4565 #define REG_A6XX_VPC_SO_STREAM_CNTL 0x00009305 4566 #define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK 0x00000007 4567 #define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT 0 4568 static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(uint32_t val) 4569 { 4570 return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK; 4571 } 4572 #define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK 0x00000038 4573 #define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT 3 4574 static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(uint32_t val) 4575 { 4576 return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK; 4577 } 4578 #define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK 0x000001c0 4579 #define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT 6 4580 static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(uint32_t val) 4581 { 4582 return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK; 4583 } 4584 #define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK 0x00000e00 4585 #define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT 9 4586 static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(uint32_t val) 4587 { 4588 return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK; 4589 } 4590 #define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK 0x00078000 4591 #define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT 15 4592 static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val) 4593 { 4594 return ((val) << A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK; 4595 } 4596 4597 #define REG_A6XX_VPC_SO_DISABLE 0x00009306 4598 #define A6XX_VPC_SO_DISABLE_DISABLE 0x00000001 4599 4600 #define REG_A6XX_VPC_UNKNOWN_9600 0x00009600 4601 4602 #define REG_A6XX_VPC_ADDR_MODE_CNTL 0x00009601 4603 4604 #define REG_A6XX_VPC_UNKNOWN_9602 0x00009602 4605 4606 #define REG_A6XX_VPC_UNKNOWN_9603 0x00009603 4607 4608 static inline uint32_t REG_A6XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) { return 0x00009604 + 0x1*i0; } 4609 4610 #define REG_A6XX_PC_TESS_NUM_VERTEX 0x00009800 4611 4612 #define REG_A6XX_PC_HS_INPUT_SIZE 0x00009801 4613 #define A6XX_PC_HS_INPUT_SIZE_SIZE__MASK 0x000007ff 4614 #define A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT 0 4615 static inline uint32_t A6XX_PC_HS_INPUT_SIZE_SIZE(uint32_t val) 4616 { 4617 return ((val) << A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT) & A6XX_PC_HS_INPUT_SIZE_SIZE__MASK; 4618 } 4619 #define A6XX_PC_HS_INPUT_SIZE_UNK13__MASK 0x00002000 4620 #define A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT 13 4621 static inline uint32_t A6XX_PC_HS_INPUT_SIZE_UNK13(uint32_t val) 4622 { 4623 return ((val) << A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT) & A6XX_PC_HS_INPUT_SIZE_UNK13__MASK; 4624 } 4625 4626 #define REG_A6XX_PC_TESS_CNTL 0x00009802 4627 #define A6XX_PC_TESS_CNTL_SPACING__MASK 0x00000003 4628 #define A6XX_PC_TESS_CNTL_SPACING__SHIFT 0 4629 static inline uint32_t A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val) 4630 { 4631 return ((val) << A6XX_PC_TESS_CNTL_SPACING__SHIFT) & A6XX_PC_TESS_CNTL_SPACING__MASK; 4632 } 4633 #define A6XX_PC_TESS_CNTL_OUTPUT__MASK 0x0000000c 4634 #define A6XX_PC_TESS_CNTL_OUTPUT__SHIFT 2 4635 static inline uint32_t A6XX_PC_TESS_CNTL_OUTPUT(enum a6xx_tess_output val) 4636 { 4637 return ((val) << A6XX_PC_TESS_CNTL_OUTPUT__SHIFT) & A6XX_PC_TESS_CNTL_OUTPUT__MASK; 4638 } 4639 4640 #define REG_A6XX_PC_RESTART_INDEX 0x00009803 4641 4642 #define REG_A6XX_PC_MODE_CNTL 0x00009804 4643 4644 #define REG_A6XX_PC_POWER_CNTL 0x00009805 4645 4646 #define REG_A6XX_PC_PRIMID_PASSTHRU 0x00009806 4647 4648 #define REG_A6XX_PC_SO_STREAM_CNTL 0x00009808 4649 #define A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE 0x00008000 4650 4651 #define REG_A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL 0x0000980a 4652 #define A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN 0x00000001 4653 4654 #define REG_A6XX_PC_DRAW_CMD 0x00009840 4655 #define A6XX_PC_DRAW_CMD_STATE_ID__MASK 0x000000ff 4656 #define A6XX_PC_DRAW_CMD_STATE_ID__SHIFT 0 4657 static inline uint32_t A6XX_PC_DRAW_CMD_STATE_ID(uint32_t val) 4658 { 4659 return ((val) << A6XX_PC_DRAW_CMD_STATE_ID__SHIFT) & A6XX_PC_DRAW_CMD_STATE_ID__MASK; 4660 } 4661 4662 #define REG_A6XX_PC_DISPATCH_CMD 0x00009841 4663 #define A6XX_PC_DISPATCH_CMD_STATE_ID__MASK 0x000000ff 4664 #define A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT 0 4665 static inline uint32_t A6XX_PC_DISPATCH_CMD_STATE_ID(uint32_t val) 4666 { 4667 return ((val) << A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_PC_DISPATCH_CMD_STATE_ID__MASK; 4668 } 4669 4670 #define REG_A6XX_PC_EVENT_CMD 0x00009842 4671 #define A6XX_PC_EVENT_CMD_STATE_ID__MASK 0x00ff0000 4672 #define A6XX_PC_EVENT_CMD_STATE_ID__SHIFT 16 4673 static inline uint32_t A6XX_PC_EVENT_CMD_STATE_ID(uint32_t val) 4674 { 4675 return ((val) << A6XX_PC_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_EVENT_CMD_STATE_ID__MASK; 4676 } 4677 #define A6XX_PC_EVENT_CMD_EVENT__MASK 0x0000007f 4678 #define A6XX_PC_EVENT_CMD_EVENT__SHIFT 0 4679 static inline uint32_t A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val) 4680 { 4681 return ((val) << A6XX_PC_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_EVENT_CMD_EVENT__MASK; 4682 } 4683 4684 #define REG_A6XX_PC_MARKER 0x00009880 4685 4686 #define REG_A6XX_PC_POLYGON_MODE 0x00009981 4687 #define A6XX_PC_POLYGON_MODE_MODE__MASK 0x00000003 4688 #define A6XX_PC_POLYGON_MODE_MODE__SHIFT 0 4689 static inline uint32_t A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) 4690 { 4691 return ((val) << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK; 4692 } 4693 4694 #define REG_A6XX_PC_RASTER_CNTL 0x00009980 4695 #define A6XX_PC_RASTER_CNTL_STREAM__MASK 0x00000003 4696 #define A6XX_PC_RASTER_CNTL_STREAM__SHIFT 0 4697 static inline uint32_t A6XX_PC_RASTER_CNTL_STREAM(uint32_t val) 4698 { 4699 return ((val) << A6XX_PC_RASTER_CNTL_STREAM__SHIFT) & A6XX_PC_RASTER_CNTL_STREAM__MASK; 4700 } 4701 #define A6XX_PC_RASTER_CNTL_DISCARD 0x00000004 4702 4703 #define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00 4704 #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001 4705 #define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002 4706 #define A6XX_PC_PRIMITIVE_CNTL_0_TESS_UPPER_LEFT_DOMAIN_ORIGIN 0x00000004 4707 #define A6XX_PC_PRIMITIVE_CNTL_0_UNK3 0x00000008 4708 4709 #define REG_A6XX_PC_VS_OUT_CNTL 0x00009b01 4710 #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff 4711 #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 4712 static inline uint32_t A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) 4713 { 4714 return ((val) << A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK; 4715 } 4716 #define A6XX_PC_VS_OUT_CNTL_PSIZE 0x00000100 4717 #define A6XX_PC_VS_OUT_CNTL_LAYER 0x00000200 4718 #define A6XX_PC_VS_OUT_CNTL_VIEW 0x00000400 4719 #define A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID 0x00000800 4720 #define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 4721 #define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT 16 4722 static inline uint32_t A6XX_PC_VS_OUT_CNTL_CLIP_MASK(uint32_t val) 4723 { 4724 return ((val) << A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK; 4725 } 4726 4727 #define REG_A6XX_PC_GS_OUT_CNTL 0x00009b02 4728 #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff 4729 #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 4730 static inline uint32_t A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) 4731 { 4732 return ((val) << A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK; 4733 } 4734 #define A6XX_PC_GS_OUT_CNTL_PSIZE 0x00000100 4735 #define A6XX_PC_GS_OUT_CNTL_LAYER 0x00000200 4736 #define A6XX_PC_GS_OUT_CNTL_VIEW 0x00000400 4737 #define A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID 0x00000800 4738 #define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 4739 #define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT 16 4740 static inline uint32_t A6XX_PC_GS_OUT_CNTL_CLIP_MASK(uint32_t val) 4741 { 4742 return ((val) << A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK; 4743 } 4744 4745 #define REG_A6XX_PC_HS_OUT_CNTL 0x00009b03 4746 #define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff 4747 #define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 4748 static inline uint32_t A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) 4749 { 4750 return ((val) << A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK; 4751 } 4752 #define A6XX_PC_HS_OUT_CNTL_PSIZE 0x00000100 4753 #define A6XX_PC_HS_OUT_CNTL_LAYER 0x00000200 4754 #define A6XX_PC_HS_OUT_CNTL_VIEW 0x00000400 4755 #define A6XX_PC_HS_OUT_CNTL_PRIMITIVE_ID 0x00000800 4756 #define A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 4757 #define A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT 16 4758 static inline uint32_t A6XX_PC_HS_OUT_CNTL_CLIP_MASK(uint32_t val) 4759 { 4760 return ((val) << A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK; 4761 } 4762 4763 #define REG_A6XX_PC_DS_OUT_CNTL 0x00009b04 4764 #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff 4765 #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 4766 static inline uint32_t A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) 4767 { 4768 return ((val) << A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK; 4769 } 4770 #define A6XX_PC_DS_OUT_CNTL_PSIZE 0x00000100 4771 #define A6XX_PC_DS_OUT_CNTL_LAYER 0x00000200 4772 #define A6XX_PC_DS_OUT_CNTL_VIEW 0x00000400 4773 #define A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID 0x00000800 4774 #define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 4775 #define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT 16 4776 static inline uint32_t A6XX_PC_DS_OUT_CNTL_CLIP_MASK(uint32_t val) 4777 { 4778 return ((val) << A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK; 4779 } 4780 4781 #define REG_A6XX_PC_PRIMITIVE_CNTL_5 0x00009b05 4782 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK 0x000000ff 4783 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT 0 4784 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val) 4785 { 4786 return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK; 4787 } 4788 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK 0x00007c00 4789 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT 10 4790 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val) 4791 { 4792 return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK; 4793 } 4794 #define A6XX_PC_PRIMITIVE_CNTL_5_LINELENGTHEN 0x00008000 4795 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK 0x00030000 4796 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT 16 4797 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val) 4798 { 4799 return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK; 4800 } 4801 #define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK 0x00040000 4802 #define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT 18 4803 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_UNK18(uint32_t val) 4804 { 4805 return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK; 4806 } 4807 4808 #define REG_A6XX_PC_PRIMITIVE_CNTL_6 0x00009b06 4809 #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK 0x000007ff 4810 #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT 0 4811 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(uint32_t val) 4812 { 4813 return ((val) << A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK; 4814 } 4815 4816 #define REG_A6XX_PC_MULTIVIEW_CNTL 0x00009b07 4817 #define A6XX_PC_MULTIVIEW_CNTL_ENABLE 0x00000001 4818 #define A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002 4819 #define A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c 4820 #define A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT 2 4821 static inline uint32_t A6XX_PC_MULTIVIEW_CNTL_VIEWS(uint32_t val) 4822 { 4823 return ((val) << A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK; 4824 } 4825 4826 #define REG_A6XX_PC_MULTIVIEW_MASK 0x00009b08 4827 4828 #define REG_A6XX_PC_2D_EVENT_CMD 0x00009c00 4829 #define A6XX_PC_2D_EVENT_CMD_EVENT__MASK 0x0000007f 4830 #define A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT 0 4831 static inline uint32_t A6XX_PC_2D_EVENT_CMD_EVENT(enum vgt_event_type val) 4832 { 4833 return ((val) << A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_2D_EVENT_CMD_EVENT__MASK; 4834 } 4835 #define A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00 4836 #define A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT 8 4837 static inline uint32_t A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val) 4838 { 4839 return ((val) << A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK; 4840 } 4841 4842 #define REG_A6XX_PC_DBG_ECO_CNTL 0x00009e00 4843 4844 #define REG_A6XX_PC_ADDR_MODE_CNTL 0x00009e01 4845 4846 #define REG_A6XX_PC_DRAW_INDX_BASE 0x00009e04 4847 4848 #define REG_A6XX_PC_DRAW_FIRST_INDX 0x00009e06 4849 4850 #define REG_A6XX_PC_DRAW_MAX_INDICES 0x00009e07 4851 4852 #define REG_A6XX_PC_TESSFACTOR_ADDR 0x00009e08 4853 #define A6XX_PC_TESSFACTOR_ADDR__MASK 0xffffffff 4854 #define A6XX_PC_TESSFACTOR_ADDR__SHIFT 0 4855 static inline uint32_t A6XX_PC_TESSFACTOR_ADDR(uint32_t val) 4856 { 4857 return ((val) << A6XX_PC_TESSFACTOR_ADDR__SHIFT) & A6XX_PC_TESSFACTOR_ADDR__MASK; 4858 } 4859 4860 #define REG_A6XX_PC_DRAW_INITIATOR 0x00009e0b 4861 #define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f 4862 #define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 4863 static inline uint32_t A6XX_PC_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) 4864 { 4865 return ((val) << A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK; 4866 } 4867 #define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 4868 #define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 4869 static inline uint32_t A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) 4870 { 4871 return ((val) << A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK; 4872 } 4873 #define A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK 0x00000300 4874 #define A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT 8 4875 static inline uint32_t A6XX_PC_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) 4876 { 4877 return ((val) << A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT) & A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK; 4878 } 4879 #define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000c00 4880 #define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT 10 4881 static inline uint32_t A6XX_PC_DRAW_INITIATOR_INDEX_SIZE(enum a4xx_index_size val) 4882 { 4883 return ((val) << A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK; 4884 } 4885 #define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK 0x00003000 4886 #define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT 12 4887 static inline uint32_t A6XX_PC_DRAW_INITIATOR_PATCH_TYPE(enum a6xx_patch_type val) 4888 { 4889 return ((val) << A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK; 4890 } 4891 #define A6XX_PC_DRAW_INITIATOR_GS_ENABLE 0x00010000 4892 #define A6XX_PC_DRAW_INITIATOR_TESS_ENABLE 0x00020000 4893 4894 #define REG_A6XX_PC_DRAW_NUM_INSTANCES 0x00009e0c 4895 4896 #define REG_A6XX_PC_DRAW_NUM_INDICES 0x00009e0d 4897 4898 #define REG_A6XX_PC_VSTREAM_CONTROL 0x00009e11 4899 #define A6XX_PC_VSTREAM_CONTROL_UNK0__MASK 0x0000ffff 4900 #define A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT 0 4901 static inline uint32_t A6XX_PC_VSTREAM_CONTROL_UNK0(uint32_t val) 4902 { 4903 return ((val) << A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT) & A6XX_PC_VSTREAM_CONTROL_UNK0__MASK; 4904 } 4905 #define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK 0x003f0000 4906 #define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT 16 4907 static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_SIZE(uint32_t val) 4908 { 4909 return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK; 4910 } 4911 #define A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK 0x07c00000 4912 #define A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT 22 4913 static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_N(uint32_t val) 4914 { 4915 return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK; 4916 } 4917 4918 #define REG_A6XX_PC_BIN_PRIM_STRM 0x00009e12 4919 #define A6XX_PC_BIN_PRIM_STRM__MASK 0xffffffff 4920 #define A6XX_PC_BIN_PRIM_STRM__SHIFT 0 4921 static inline uint32_t A6XX_PC_BIN_PRIM_STRM(uint32_t val) 4922 { 4923 return ((val) << A6XX_PC_BIN_PRIM_STRM__SHIFT) & A6XX_PC_BIN_PRIM_STRM__MASK; 4924 } 4925 4926 #define REG_A6XX_PC_BIN_DRAW_STRM 0x00009e14 4927 #define A6XX_PC_BIN_DRAW_STRM__MASK 0xffffffff 4928 #define A6XX_PC_BIN_DRAW_STRM__SHIFT 0 4929 static inline uint32_t A6XX_PC_BIN_DRAW_STRM(uint32_t val) 4930 { 4931 return ((val) << A6XX_PC_BIN_DRAW_STRM__SHIFT) & A6XX_PC_BIN_DRAW_STRM__MASK; 4932 } 4933 4934 #define REG_A6XX_PC_VISIBILITY_OVERRIDE 0x00009e1c 4935 #define A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE 0x00000001 4936 4937 static inline uint32_t REG_A6XX_PC_PERFCTR_PC_SEL(uint32_t i0) { return 0x00009e34 + 0x1*i0; } 4938 4939 #define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72 4940 4941 #define REG_A6XX_VFD_CONTROL_0 0x0000a000 4942 #define A6XX_VFD_CONTROL_0_FETCH_CNT__MASK 0x0000003f 4943 #define A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT 0 4944 static inline uint32_t A6XX_VFD_CONTROL_0_FETCH_CNT(uint32_t val) 4945 { 4946 return ((val) << A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT) & A6XX_VFD_CONTROL_0_FETCH_CNT__MASK; 4947 } 4948 #define A6XX_VFD_CONTROL_0_DECODE_CNT__MASK 0x00003f00 4949 #define A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT 8 4950 static inline uint32_t A6XX_VFD_CONTROL_0_DECODE_CNT(uint32_t val) 4951 { 4952 return ((val) << A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT) & A6XX_VFD_CONTROL_0_DECODE_CNT__MASK; 4953 } 4954 4955 #define REG_A6XX_VFD_CONTROL_1 0x0000a001 4956 #define A6XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff 4957 #define A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0 4958 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 4959 { 4960 return ((val) << A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VTX__MASK; 4961 } 4962 #define A6XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00 4963 #define A6XX_VFD_CONTROL_1_REGID4INST__SHIFT 8 4964 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 4965 { 4966 return ((val) << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK; 4967 } 4968 #define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000 4969 #define A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16 4970 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val) 4971 { 4972 return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK; 4973 } 4974 #define A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK 0xff000000 4975 #define A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT 24 4976 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VIEWID(uint32_t val) 4977 { 4978 return ((val) << A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK; 4979 } 4980 4981 #define REG_A6XX_VFD_CONTROL_2 0x0000a002 4982 #define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK 0x000000ff 4983 #define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT 0 4984 static inline uint32_t A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID(uint32_t val) 4985 { 4986 return ((val) << A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK; 4987 } 4988 #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK 0x0000ff00 4989 #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT 8 4990 static inline uint32_t A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val) 4991 { 4992 return ((val) << A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK; 4993 } 4994 4995 #define REG_A6XX_VFD_CONTROL_3 0x0000a003 4996 #define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK 0x000000ff 4997 #define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT 0 4998 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPRIMID(uint32_t val) 4999 { 5000 return ((val) << A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK; 5001 } 5002 #define A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK 0x0000ff00 5003 #define A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT 8 5004 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID(uint32_t val) 5005 { 5006 return ((val) << A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK; 5007 } 5008 #define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000 5009 #define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16 5010 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) 5011 { 5012 return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSX__MASK; 5013 } 5014 #define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000 5015 #define A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24 5016 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) 5017 { 5018 return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK; 5019 } 5020 5021 #define REG_A6XX_VFD_CONTROL_4 0x0000a004 5022 #define A6XX_VFD_CONTROL_4_UNK0__MASK 0x000000ff 5023 #define A6XX_VFD_CONTROL_4_UNK0__SHIFT 0 5024 static inline uint32_t A6XX_VFD_CONTROL_4_UNK0(uint32_t val) 5025 { 5026 return ((val) << A6XX_VFD_CONTROL_4_UNK0__SHIFT) & A6XX_VFD_CONTROL_4_UNK0__MASK; 5027 } 5028 5029 #define REG_A6XX_VFD_CONTROL_5 0x0000a005 5030 #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK 0x000000ff 5031 #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT 0 5032 static inline uint32_t A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val) 5033 { 5034 return ((val) << A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT) & A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK; 5035 } 5036 #define A6XX_VFD_CONTROL_5_UNK8__MASK 0x0000ff00 5037 #define A6XX_VFD_CONTROL_5_UNK8__SHIFT 8 5038 static inline uint32_t A6XX_VFD_CONTROL_5_UNK8(uint32_t val) 5039 { 5040 return ((val) << A6XX_VFD_CONTROL_5_UNK8__SHIFT) & A6XX_VFD_CONTROL_5_UNK8__MASK; 5041 } 5042 5043 #define REG_A6XX_VFD_CONTROL_6 0x0000a006 5044 #define A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU 0x00000001 5045 5046 #define REG_A6XX_VFD_MODE_CNTL 0x0000a007 5047 #define A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK 0x00000007 5048 #define A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT 0 5049 static inline uint32_t A6XX_VFD_MODE_CNTL_RENDER_MODE(enum a6xx_render_mode val) 5050 { 5051 return ((val) << A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT) & A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK; 5052 } 5053 5054 #define REG_A6XX_VFD_MULTIVIEW_CNTL 0x0000a008 5055 #define A6XX_VFD_MULTIVIEW_CNTL_ENABLE 0x00000001 5056 #define A6XX_VFD_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002 5057 #define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c 5058 #define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT 2 5059 static inline uint32_t A6XX_VFD_MULTIVIEW_CNTL_VIEWS(uint32_t val) 5060 { 5061 return ((val) << A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK; 5062 } 5063 5064 #define REG_A6XX_VFD_ADD_OFFSET 0x0000a009 5065 #define A6XX_VFD_ADD_OFFSET_VERTEX 0x00000001 5066 #define A6XX_VFD_ADD_OFFSET_INSTANCE 0x00000002 5067 5068 #define REG_A6XX_VFD_INDEX_OFFSET 0x0000a00e 5069 5070 #define REG_A6XX_VFD_INSTANCE_START_OFFSET 0x0000a00f 5071 5072 static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; } 5073 5074 static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; } 5075 #define A6XX_VFD_FETCH_BASE__MASK 0xffffffff 5076 #define A6XX_VFD_FETCH_BASE__SHIFT 0 5077 static inline uint32_t A6XX_VFD_FETCH_BASE(uint32_t val) 5078 { 5079 return ((val) << A6XX_VFD_FETCH_BASE__SHIFT) & A6XX_VFD_FETCH_BASE__MASK; 5080 } 5081 5082 static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; } 5083 5084 static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; } 5085 5086 static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; } 5087 5088 static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; } 5089 #define A6XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f 5090 #define A6XX_VFD_DECODE_INSTR_IDX__SHIFT 0 5091 static inline uint32_t A6XX_VFD_DECODE_INSTR_IDX(uint32_t val) 5092 { 5093 return ((val) << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK; 5094 } 5095 #define A6XX_VFD_DECODE_INSTR_OFFSET__MASK 0x0001ffe0 5096 #define A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT 5 5097 static inline uint32_t A6XX_VFD_DECODE_INSTR_OFFSET(uint32_t val) 5098 { 5099 return ((val) << A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT) & A6XX_VFD_DECODE_INSTR_OFFSET__MASK; 5100 } 5101 #define A6XX_VFD_DECODE_INSTR_INSTANCED 0x00020000 5102 #define A6XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000 5103 #define A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20 5104 static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_format val) 5105 { 5106 return ((val) << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK; 5107 } 5108 #define A6XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000 5109 #define A6XX_VFD_DECODE_INSTR_SWAP__SHIFT 28 5110 static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 5111 { 5112 return ((val) << A6XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A6XX_VFD_DECODE_INSTR_SWAP__MASK; 5113 } 5114 #define A6XX_VFD_DECODE_INSTR_UNK30 0x40000000 5115 #define A6XX_VFD_DECODE_INSTR_FLOAT 0x80000000 5116 5117 static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; } 5118 5119 static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } 5120 5121 static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } 5122 #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f 5123 #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0 5124 static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val) 5125 { 5126 return ((val) << A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK; 5127 } 5128 #define A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0 5129 #define A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4 5130 static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) 5131 { 5132 return ((val) << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK; 5133 } 5134 5135 #define REG_A6XX_VFD_POWER_CNTL 0x0000a0f8 5136 5137 #define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601 5138 5139 static inline uint32_t REG_A6XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) { return 0x0000a610 + 0x1*i0; } 5140 5141 #define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800 5142 #define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x00100000 5143 #define A6XX_SP_VS_CTRL_REG0_UNK21 0x00200000 5144 #define A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 5145 #define A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 5146 static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 5147 { 5148 return ((val) << A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK; 5149 } 5150 #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 5151 #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 5152 static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 5153 { 5154 return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 5155 } 5156 #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 5157 #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 5158 static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 5159 { 5160 return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 5161 } 5162 #define A6XX_SP_VS_CTRL_REG0_UNK13 0x00002000 5163 #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 5164 #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14 5165 static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val) 5166 { 5167 return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK; 5168 } 5169 5170 #define REG_A6XX_SP_VS_BRANCH_COND 0x0000a801 5171 5172 #define REG_A6XX_SP_VS_PRIMITIVE_CNTL 0x0000a802 5173 #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f 5174 #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT 0 5175 static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_OUT(uint32_t val) 5176 { 5177 return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK; 5178 } 5179 #define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0 5180 #define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6 5181 static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) 5182 { 5183 return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; 5184 } 5185 5186 static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; } 5187 5188 static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; } 5189 #define A6XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff 5190 #define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 5191 static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 5192 { 5193 return ((val) << A6XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_A_REGID__MASK; 5194 } 5195 #define A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00 5196 #define A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8 5197 static inline uint32_t A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 5198 { 5199 return ((val) << A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 5200 } 5201 #define A6XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000 5202 #define A6XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 5203 static inline uint32_t A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 5204 { 5205 return ((val) << A6XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_B_REGID__MASK; 5206 } 5207 #define A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000 5208 #define A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24 5209 static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 5210 { 5211 return ((val) << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 5212 } 5213 5214 static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; } 5215 5216 static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; } 5217 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 5218 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 5219 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 5220 { 5221 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 5222 } 5223 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 5224 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 5225 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 5226 { 5227 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 5228 } 5229 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 5230 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 5231 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 5232 { 5233 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 5234 } 5235 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 5236 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 5237 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 5238 { 5239 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 5240 } 5241 5242 #define REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET 0x0000a81b 5243 5244 #define REG_A6XX_SP_VS_OBJ_START 0x0000a81c 5245 #define A6XX_SP_VS_OBJ_START__MASK 0xffffffff 5246 #define A6XX_SP_VS_OBJ_START__SHIFT 0 5247 static inline uint32_t A6XX_SP_VS_OBJ_START(uint32_t val) 5248 { 5249 return ((val) << A6XX_SP_VS_OBJ_START__SHIFT) & A6XX_SP_VS_OBJ_START__MASK; 5250 } 5251 5252 #define REG_A6XX_SP_VS_PVT_MEM_PARAM 0x0000a81e 5253 #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 5254 #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 5255 static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 5256 { 5257 return ((val >> 9) << A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 5258 } 5259 #define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 5260 #define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 5261 static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 5262 { 5263 return ((val) << A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 5264 } 5265 5266 #define REG_A6XX_SP_VS_PVT_MEM_ADDR 0x0000a81f 5267 #define A6XX_SP_VS_PVT_MEM_ADDR__MASK 0xffffffff 5268 #define A6XX_SP_VS_PVT_MEM_ADDR__SHIFT 0 5269 static inline uint32_t A6XX_SP_VS_PVT_MEM_ADDR(uint32_t val) 5270 { 5271 return ((val) << A6XX_SP_VS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_VS_PVT_MEM_ADDR__MASK; 5272 } 5273 5274 #define REG_A6XX_SP_VS_PVT_MEM_SIZE 0x0000a821 5275 #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 5276 #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 5277 static inline uint32_t A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 5278 { 5279 return ((val >> 12) << A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 5280 } 5281 #define A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 5282 5283 #define REG_A6XX_SP_VS_TEX_COUNT 0x0000a822 5284 5285 #define REG_A6XX_SP_VS_CONFIG 0x0000a823 5286 #define A6XX_SP_VS_CONFIG_BINDLESS_TEX 0x00000001 5287 #define A6XX_SP_VS_CONFIG_BINDLESS_SAMP 0x00000002 5288 #define A6XX_SP_VS_CONFIG_BINDLESS_IBO 0x00000004 5289 #define A6XX_SP_VS_CONFIG_BINDLESS_UBO 0x00000008 5290 #define A6XX_SP_VS_CONFIG_ENABLED 0x00000100 5291 #define A6XX_SP_VS_CONFIG_NTEX__MASK 0x0001fe00 5292 #define A6XX_SP_VS_CONFIG_NTEX__SHIFT 9 5293 static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val) 5294 { 5295 return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK; 5296 } 5297 #define A6XX_SP_VS_CONFIG_NSAMP__MASK 0x003e0000 5298 #define A6XX_SP_VS_CONFIG_NSAMP__SHIFT 17 5299 static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val) 5300 { 5301 return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK; 5302 } 5303 #define A6XX_SP_VS_CONFIG_NIBO__MASK 0x1fc00000 5304 #define A6XX_SP_VS_CONFIG_NIBO__SHIFT 22 5305 static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val) 5306 { 5307 return ((val) << A6XX_SP_VS_CONFIG_NIBO__SHIFT) & A6XX_SP_VS_CONFIG_NIBO__MASK; 5308 } 5309 5310 #define REG_A6XX_SP_VS_INSTRLEN 0x0000a824 5311 5312 #define REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET 0x0000a825 5313 #define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 5314 #define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 5315 static inline uint32_t A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 5316 { 5317 return ((val >> 11) << A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 5318 } 5319 5320 #define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830 5321 #define A6XX_SP_HS_CTRL_REG0_UNK20 0x00100000 5322 #define A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK 0x00000001 5323 #define A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT 0 5324 static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 5325 { 5326 return ((val) << A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK; 5327 } 5328 #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 5329 #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 5330 static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 5331 { 5332 return ((val) << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 5333 } 5334 #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 5335 #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 5336 static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 5337 { 5338 return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 5339 } 5340 #define A6XX_SP_HS_CTRL_REG0_UNK13 0x00002000 5341 #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 5342 #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 14 5343 static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val) 5344 { 5345 return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK; 5346 } 5347 5348 #define REG_A6XX_SP_HS_WAVE_INPUT_SIZE 0x0000a831 5349 5350 #define REG_A6XX_SP_HS_BRANCH_COND 0x0000a832 5351 5352 #define REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET 0x0000a833 5353 5354 #define REG_A6XX_SP_HS_OBJ_START 0x0000a834 5355 #define A6XX_SP_HS_OBJ_START__MASK 0xffffffff 5356 #define A6XX_SP_HS_OBJ_START__SHIFT 0 5357 static inline uint32_t A6XX_SP_HS_OBJ_START(uint32_t val) 5358 { 5359 return ((val) << A6XX_SP_HS_OBJ_START__SHIFT) & A6XX_SP_HS_OBJ_START__MASK; 5360 } 5361 5362 #define REG_A6XX_SP_HS_PVT_MEM_PARAM 0x0000a836 5363 #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 5364 #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 5365 static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 5366 { 5367 return ((val >> 9) << A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 5368 } 5369 #define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 5370 #define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 5371 static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 5372 { 5373 return ((val) << A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 5374 } 5375 5376 #define REG_A6XX_SP_HS_PVT_MEM_ADDR 0x0000a837 5377 #define A6XX_SP_HS_PVT_MEM_ADDR__MASK 0xffffffff 5378 #define A6XX_SP_HS_PVT_MEM_ADDR__SHIFT 0 5379 static inline uint32_t A6XX_SP_HS_PVT_MEM_ADDR(uint32_t val) 5380 { 5381 return ((val) << A6XX_SP_HS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_HS_PVT_MEM_ADDR__MASK; 5382 } 5383 5384 #define REG_A6XX_SP_HS_PVT_MEM_SIZE 0x0000a839 5385 #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 5386 #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 5387 static inline uint32_t A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 5388 { 5389 return ((val >> 12) << A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 5390 } 5391 #define A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 5392 5393 #define REG_A6XX_SP_HS_TEX_COUNT 0x0000a83a 5394 5395 #define REG_A6XX_SP_HS_CONFIG 0x0000a83b 5396 #define A6XX_SP_HS_CONFIG_BINDLESS_TEX 0x00000001 5397 #define A6XX_SP_HS_CONFIG_BINDLESS_SAMP 0x00000002 5398 #define A6XX_SP_HS_CONFIG_BINDLESS_IBO 0x00000004 5399 #define A6XX_SP_HS_CONFIG_BINDLESS_UBO 0x00000008 5400 #define A6XX_SP_HS_CONFIG_ENABLED 0x00000100 5401 #define A6XX_SP_HS_CONFIG_NTEX__MASK 0x0001fe00 5402 #define A6XX_SP_HS_CONFIG_NTEX__SHIFT 9 5403 static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val) 5404 { 5405 return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK; 5406 } 5407 #define A6XX_SP_HS_CONFIG_NSAMP__MASK 0x003e0000 5408 #define A6XX_SP_HS_CONFIG_NSAMP__SHIFT 17 5409 static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val) 5410 { 5411 return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK; 5412 } 5413 #define A6XX_SP_HS_CONFIG_NIBO__MASK 0x1fc00000 5414 #define A6XX_SP_HS_CONFIG_NIBO__SHIFT 22 5415 static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val) 5416 { 5417 return ((val) << A6XX_SP_HS_CONFIG_NIBO__SHIFT) & A6XX_SP_HS_CONFIG_NIBO__MASK; 5418 } 5419 5420 #define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c 5421 5422 #define REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET 0x0000a83d 5423 #define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 5424 #define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 5425 static inline uint32_t A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 5426 { 5427 return ((val >> 11) << A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 5428 } 5429 5430 #define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840 5431 #define A6XX_SP_DS_CTRL_REG0_MERGEDREGS 0x00100000 5432 #define A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK 0x00000001 5433 #define A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT 0 5434 static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 5435 { 5436 return ((val) << A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK; 5437 } 5438 #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 5439 #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 5440 static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 5441 { 5442 return ((val) << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 5443 } 5444 #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 5445 #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 5446 static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 5447 { 5448 return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 5449 } 5450 #define A6XX_SP_DS_CTRL_REG0_UNK13 0x00002000 5451 #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 5452 #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 14 5453 static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val) 5454 { 5455 return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK; 5456 } 5457 5458 #define REG_A6XX_SP_DS_BRANCH_COND 0x0000a841 5459 5460 #define REG_A6XX_SP_DS_PRIMITIVE_CNTL 0x0000a842 5461 #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f 5462 #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT 0 5463 static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_OUT(uint32_t val) 5464 { 5465 return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK; 5466 } 5467 #define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0 5468 #define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6 5469 static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) 5470 { 5471 return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; 5472 } 5473 5474 static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; } 5475 5476 static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000a843 + 0x1*i0; } 5477 #define A6XX_SP_DS_OUT_REG_A_REGID__MASK 0x000000ff 5478 #define A6XX_SP_DS_OUT_REG_A_REGID__SHIFT 0 5479 static inline uint32_t A6XX_SP_DS_OUT_REG_A_REGID(uint32_t val) 5480 { 5481 return ((val) << A6XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_A_REGID__MASK; 5482 } 5483 #define A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00000f00 5484 #define A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 8 5485 static inline uint32_t A6XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val) 5486 { 5487 return ((val) << A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK; 5488 } 5489 #define A6XX_SP_DS_OUT_REG_B_REGID__MASK 0x00ff0000 5490 #define A6XX_SP_DS_OUT_REG_B_REGID__SHIFT 16 5491 static inline uint32_t A6XX_SP_DS_OUT_REG_B_REGID(uint32_t val) 5492 { 5493 return ((val) << A6XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_B_REGID__MASK; 5494 } 5495 #define A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x0f000000 5496 #define A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 24 5497 static inline uint32_t A6XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val) 5498 { 5499 return ((val) << A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK; 5500 } 5501 5502 static inline uint32_t REG_A6XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000a853 + 0x1*i0; } 5503 5504 static inline uint32_t REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000a853 + 0x1*i0; } 5505 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 5506 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0 5507 static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val) 5508 { 5509 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK; 5510 } 5511 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 5512 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8 5513 static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val) 5514 { 5515 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK; 5516 } 5517 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 5518 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16 5519 static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val) 5520 { 5521 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK; 5522 } 5523 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 5524 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24 5525 static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) 5526 { 5527 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK; 5528 } 5529 5530 #define REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET 0x0000a85b 5531 5532 #define REG_A6XX_SP_DS_OBJ_START 0x0000a85c 5533 #define A6XX_SP_DS_OBJ_START__MASK 0xffffffff 5534 #define A6XX_SP_DS_OBJ_START__SHIFT 0 5535 static inline uint32_t A6XX_SP_DS_OBJ_START(uint32_t val) 5536 { 5537 return ((val) << A6XX_SP_DS_OBJ_START__SHIFT) & A6XX_SP_DS_OBJ_START__MASK; 5538 } 5539 5540 #define REG_A6XX_SP_DS_PVT_MEM_PARAM 0x0000a85e 5541 #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 5542 #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 5543 static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 5544 { 5545 return ((val >> 9) << A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 5546 } 5547 #define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 5548 #define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 5549 static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 5550 { 5551 return ((val) << A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 5552 } 5553 5554 #define REG_A6XX_SP_DS_PVT_MEM_ADDR 0x0000a85f 5555 #define A6XX_SP_DS_PVT_MEM_ADDR__MASK 0xffffffff 5556 #define A6XX_SP_DS_PVT_MEM_ADDR__SHIFT 0 5557 static inline uint32_t A6XX_SP_DS_PVT_MEM_ADDR(uint32_t val) 5558 { 5559 return ((val) << A6XX_SP_DS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_DS_PVT_MEM_ADDR__MASK; 5560 } 5561 5562 #define REG_A6XX_SP_DS_PVT_MEM_SIZE 0x0000a861 5563 #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 5564 #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 5565 static inline uint32_t A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 5566 { 5567 return ((val >> 12) << A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 5568 } 5569 #define A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 5570 5571 #define REG_A6XX_SP_DS_TEX_COUNT 0x0000a862 5572 5573 #define REG_A6XX_SP_DS_CONFIG 0x0000a863 5574 #define A6XX_SP_DS_CONFIG_BINDLESS_TEX 0x00000001 5575 #define A6XX_SP_DS_CONFIG_BINDLESS_SAMP 0x00000002 5576 #define A6XX_SP_DS_CONFIG_BINDLESS_IBO 0x00000004 5577 #define A6XX_SP_DS_CONFIG_BINDLESS_UBO 0x00000008 5578 #define A6XX_SP_DS_CONFIG_ENABLED 0x00000100 5579 #define A6XX_SP_DS_CONFIG_NTEX__MASK 0x0001fe00 5580 #define A6XX_SP_DS_CONFIG_NTEX__SHIFT 9 5581 static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val) 5582 { 5583 return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK; 5584 } 5585 #define A6XX_SP_DS_CONFIG_NSAMP__MASK 0x003e0000 5586 #define A6XX_SP_DS_CONFIG_NSAMP__SHIFT 17 5587 static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val) 5588 { 5589 return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK; 5590 } 5591 #define A6XX_SP_DS_CONFIG_NIBO__MASK 0x1fc00000 5592 #define A6XX_SP_DS_CONFIG_NIBO__SHIFT 22 5593 static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val) 5594 { 5595 return ((val) << A6XX_SP_DS_CONFIG_NIBO__SHIFT) & A6XX_SP_DS_CONFIG_NIBO__MASK; 5596 } 5597 5598 #define REG_A6XX_SP_DS_INSTRLEN 0x0000a864 5599 5600 #define REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET 0x0000a865 5601 #define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 5602 #define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 5603 static inline uint32_t A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 5604 { 5605 return ((val >> 11) << A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 5606 } 5607 5608 #define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870 5609 #define A6XX_SP_GS_CTRL_REG0_UNK20 0x00100000 5610 #define A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK 0x00000001 5611 #define A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT 0 5612 static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 5613 { 5614 return ((val) << A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK; 5615 } 5616 #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 5617 #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 5618 static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 5619 { 5620 return ((val) << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 5621 } 5622 #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 5623 #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 5624 static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 5625 { 5626 return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 5627 } 5628 #define A6XX_SP_GS_CTRL_REG0_UNK13 0x00002000 5629 #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 5630 #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 14 5631 static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val) 5632 { 5633 return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK; 5634 } 5635 5636 #define REG_A6XX_SP_GS_PRIM_SIZE 0x0000a871 5637 5638 #define REG_A6XX_SP_GS_BRANCH_COND 0x0000a872 5639 5640 #define REG_A6XX_SP_GS_PRIMITIVE_CNTL 0x0000a873 5641 #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f 5642 #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT 0 5643 static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_OUT(uint32_t val) 5644 { 5645 return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK; 5646 } 5647 #define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0 5648 #define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6 5649 static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) 5650 { 5651 return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; 5652 } 5653 5654 static inline uint32_t REG_A6XX_SP_GS_OUT(uint32_t i0) { return 0x0000a874 + 0x1*i0; } 5655 5656 static inline uint32_t REG_A6XX_SP_GS_OUT_REG(uint32_t i0) { return 0x0000a874 + 0x1*i0; } 5657 #define A6XX_SP_GS_OUT_REG_A_REGID__MASK 0x000000ff 5658 #define A6XX_SP_GS_OUT_REG_A_REGID__SHIFT 0 5659 static inline uint32_t A6XX_SP_GS_OUT_REG_A_REGID(uint32_t val) 5660 { 5661 return ((val) << A6XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_A_REGID__MASK; 5662 } 5663 #define A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00000f00 5664 #define A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 8 5665 static inline uint32_t A6XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val) 5666 { 5667 return ((val) << A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK; 5668 } 5669 #define A6XX_SP_GS_OUT_REG_B_REGID__MASK 0x00ff0000 5670 #define A6XX_SP_GS_OUT_REG_B_REGID__SHIFT 16 5671 static inline uint32_t A6XX_SP_GS_OUT_REG_B_REGID(uint32_t val) 5672 { 5673 return ((val) << A6XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_B_REGID__MASK; 5674 } 5675 #define A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x0f000000 5676 #define A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 24 5677 static inline uint32_t A6XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val) 5678 { 5679 return ((val) << A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK; 5680 } 5681 5682 static inline uint32_t REG_A6XX_SP_GS_VPC_DST(uint32_t i0) { return 0x0000a884 + 0x1*i0; } 5683 5684 static inline uint32_t REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x0000a884 + 0x1*i0; } 5685 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 5686 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0 5687 static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val) 5688 { 5689 return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK; 5690 } 5691 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 5692 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8 5693 static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val) 5694 { 5695 return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK; 5696 } 5697 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 5698 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16 5699 static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val) 5700 { 5701 return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK; 5702 } 5703 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 5704 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24 5705 static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) 5706 { 5707 return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK; 5708 } 5709 5710 #define REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET 0x0000a88c 5711 5712 #define REG_A6XX_SP_GS_OBJ_START 0x0000a88d 5713 #define A6XX_SP_GS_OBJ_START__MASK 0xffffffff 5714 #define A6XX_SP_GS_OBJ_START__SHIFT 0 5715 static inline uint32_t A6XX_SP_GS_OBJ_START(uint32_t val) 5716 { 5717 return ((val) << A6XX_SP_GS_OBJ_START__SHIFT) & A6XX_SP_GS_OBJ_START__MASK; 5718 } 5719 5720 #define REG_A6XX_SP_GS_PVT_MEM_PARAM 0x0000a88f 5721 #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 5722 #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 5723 static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 5724 { 5725 return ((val >> 9) << A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 5726 } 5727 #define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 5728 #define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 5729 static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 5730 { 5731 return ((val) << A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 5732 } 5733 5734 #define REG_A6XX_SP_GS_PVT_MEM_ADDR 0x0000a890 5735 #define A6XX_SP_GS_PVT_MEM_ADDR__MASK 0xffffffff 5736 #define A6XX_SP_GS_PVT_MEM_ADDR__SHIFT 0 5737 static inline uint32_t A6XX_SP_GS_PVT_MEM_ADDR(uint32_t val) 5738 { 5739 return ((val) << A6XX_SP_GS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_GS_PVT_MEM_ADDR__MASK; 5740 } 5741 5742 #define REG_A6XX_SP_GS_PVT_MEM_SIZE 0x0000a892 5743 #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 5744 #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 5745 static inline uint32_t A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 5746 { 5747 return ((val >> 12) << A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 5748 } 5749 #define A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 5750 5751 #define REG_A6XX_SP_GS_TEX_COUNT 0x0000a893 5752 5753 #define REG_A6XX_SP_GS_CONFIG 0x0000a894 5754 #define A6XX_SP_GS_CONFIG_BINDLESS_TEX 0x00000001 5755 #define A6XX_SP_GS_CONFIG_BINDLESS_SAMP 0x00000002 5756 #define A6XX_SP_GS_CONFIG_BINDLESS_IBO 0x00000004 5757 #define A6XX_SP_GS_CONFIG_BINDLESS_UBO 0x00000008 5758 #define A6XX_SP_GS_CONFIG_ENABLED 0x00000100 5759 #define A6XX_SP_GS_CONFIG_NTEX__MASK 0x0001fe00 5760 #define A6XX_SP_GS_CONFIG_NTEX__SHIFT 9 5761 static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val) 5762 { 5763 return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK; 5764 } 5765 #define A6XX_SP_GS_CONFIG_NSAMP__MASK 0x003e0000 5766 #define A6XX_SP_GS_CONFIG_NSAMP__SHIFT 17 5767 static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val) 5768 { 5769 return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK; 5770 } 5771 #define A6XX_SP_GS_CONFIG_NIBO__MASK 0x1fc00000 5772 #define A6XX_SP_GS_CONFIG_NIBO__SHIFT 22 5773 static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val) 5774 { 5775 return ((val) << A6XX_SP_GS_CONFIG_NIBO__SHIFT) & A6XX_SP_GS_CONFIG_NIBO__MASK; 5776 } 5777 5778 #define REG_A6XX_SP_GS_INSTRLEN 0x0000a895 5779 5780 #define REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET 0x0000a896 5781 #define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 5782 #define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 5783 static inline uint32_t A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 5784 { 5785 return ((val >> 11) << A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 5786 } 5787 5788 #define REG_A6XX_SP_VS_TEX_SAMP 0x0000a8a0 5789 #define A6XX_SP_VS_TEX_SAMP__MASK 0xffffffff 5790 #define A6XX_SP_VS_TEX_SAMP__SHIFT 0 5791 static inline uint32_t A6XX_SP_VS_TEX_SAMP(uint32_t val) 5792 { 5793 return ((val) << A6XX_SP_VS_TEX_SAMP__SHIFT) & A6XX_SP_VS_TEX_SAMP__MASK; 5794 } 5795 5796 #define REG_A6XX_SP_HS_TEX_SAMP 0x0000a8a2 5797 #define A6XX_SP_HS_TEX_SAMP__MASK 0xffffffff 5798 #define A6XX_SP_HS_TEX_SAMP__SHIFT 0 5799 static inline uint32_t A6XX_SP_HS_TEX_SAMP(uint32_t val) 5800 { 5801 return ((val) << A6XX_SP_HS_TEX_SAMP__SHIFT) & A6XX_SP_HS_TEX_SAMP__MASK; 5802 } 5803 5804 #define REG_A6XX_SP_DS_TEX_SAMP 0x0000a8a4 5805 #define A6XX_SP_DS_TEX_SAMP__MASK 0xffffffff 5806 #define A6XX_SP_DS_TEX_SAMP__SHIFT 0 5807 static inline uint32_t A6XX_SP_DS_TEX_SAMP(uint32_t val) 5808 { 5809 return ((val) << A6XX_SP_DS_TEX_SAMP__SHIFT) & A6XX_SP_DS_TEX_SAMP__MASK; 5810 } 5811 5812 #define REG_A6XX_SP_GS_TEX_SAMP 0x0000a8a6 5813 #define A6XX_SP_GS_TEX_SAMP__MASK 0xffffffff 5814 #define A6XX_SP_GS_TEX_SAMP__SHIFT 0 5815 static inline uint32_t A6XX_SP_GS_TEX_SAMP(uint32_t val) 5816 { 5817 return ((val) << A6XX_SP_GS_TEX_SAMP__SHIFT) & A6XX_SP_GS_TEX_SAMP__MASK; 5818 } 5819 5820 #define REG_A6XX_SP_VS_TEX_CONST 0x0000a8a8 5821 #define A6XX_SP_VS_TEX_CONST__MASK 0xffffffff 5822 #define A6XX_SP_VS_TEX_CONST__SHIFT 0 5823 static inline uint32_t A6XX_SP_VS_TEX_CONST(uint32_t val) 5824 { 5825 return ((val) << A6XX_SP_VS_TEX_CONST__SHIFT) & A6XX_SP_VS_TEX_CONST__MASK; 5826 } 5827 5828 #define REG_A6XX_SP_HS_TEX_CONST 0x0000a8aa 5829 #define A6XX_SP_HS_TEX_CONST__MASK 0xffffffff 5830 #define A6XX_SP_HS_TEX_CONST__SHIFT 0 5831 static inline uint32_t A6XX_SP_HS_TEX_CONST(uint32_t val) 5832 { 5833 return ((val) << A6XX_SP_HS_TEX_CONST__SHIFT) & A6XX_SP_HS_TEX_CONST__MASK; 5834 } 5835 5836 #define REG_A6XX_SP_DS_TEX_CONST 0x0000a8ac 5837 #define A6XX_SP_DS_TEX_CONST__MASK 0xffffffff 5838 #define A6XX_SP_DS_TEX_CONST__SHIFT 0 5839 static inline uint32_t A6XX_SP_DS_TEX_CONST(uint32_t val) 5840 { 5841 return ((val) << A6XX_SP_DS_TEX_CONST__SHIFT) & A6XX_SP_DS_TEX_CONST__MASK; 5842 } 5843 5844 #define REG_A6XX_SP_GS_TEX_CONST 0x0000a8ae 5845 #define A6XX_SP_GS_TEX_CONST__MASK 0xffffffff 5846 #define A6XX_SP_GS_TEX_CONST__SHIFT 0 5847 static inline uint32_t A6XX_SP_GS_TEX_CONST(uint32_t val) 5848 { 5849 return ((val) << A6XX_SP_GS_TEX_CONST__SHIFT) & A6XX_SP_GS_TEX_CONST__MASK; 5850 } 5851 5852 #define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980 5853 #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 5854 #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 5855 static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) 5856 { 5857 return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 5858 } 5859 #define A6XX_SP_FS_CTRL_REG0_UNK21 0x00200000 5860 #define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000 5861 #define A6XX_SP_FS_CTRL_REG0_DIFF_FINE 0x00800000 5862 #define A6XX_SP_FS_CTRL_REG0_UNK24 0x01000000 5863 #define A6XX_SP_FS_CTRL_REG0_UNK25 0x02000000 5864 #define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000 5865 #define A6XX_SP_FS_CTRL_REG0_UNK27__MASK 0x18000000 5866 #define A6XX_SP_FS_CTRL_REG0_UNK27__SHIFT 27 5867 static inline uint32_t A6XX_SP_FS_CTRL_REG0_UNK27(uint32_t val) 5868 { 5869 return ((val) << A6XX_SP_FS_CTRL_REG0_UNK27__SHIFT) & A6XX_SP_FS_CTRL_REG0_UNK27__MASK; 5870 } 5871 #define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000 5872 #define A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 5873 #define A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 5874 static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 5875 { 5876 return ((val) << A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK; 5877 } 5878 #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 5879 #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 5880 static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 5881 { 5882 return ((val) << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 5883 } 5884 #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 5885 #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 5886 static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 5887 { 5888 return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 5889 } 5890 #define A6XX_SP_FS_CTRL_REG0_UNK13 0x00002000 5891 #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 5892 #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 14 5893 static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) 5894 { 5895 return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK; 5896 } 5897 5898 #define REG_A6XX_SP_FS_BRANCH_COND 0x0000a981 5899 5900 #define REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET 0x0000a982 5901 5902 #define REG_A6XX_SP_FS_OBJ_START 0x0000a983 5903 #define A6XX_SP_FS_OBJ_START__MASK 0xffffffff 5904 #define A6XX_SP_FS_OBJ_START__SHIFT 0 5905 static inline uint32_t A6XX_SP_FS_OBJ_START(uint32_t val) 5906 { 5907 return ((val) << A6XX_SP_FS_OBJ_START__SHIFT) & A6XX_SP_FS_OBJ_START__MASK; 5908 } 5909 5910 #define REG_A6XX_SP_FS_PVT_MEM_PARAM 0x0000a985 5911 #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 5912 #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 5913 static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 5914 { 5915 return ((val >> 9) << A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 5916 } 5917 #define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 5918 #define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 5919 static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 5920 { 5921 return ((val) << A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 5922 } 5923 5924 #define REG_A6XX_SP_FS_PVT_MEM_ADDR 0x0000a986 5925 #define A6XX_SP_FS_PVT_MEM_ADDR__MASK 0xffffffff 5926 #define A6XX_SP_FS_PVT_MEM_ADDR__SHIFT 0 5927 static inline uint32_t A6XX_SP_FS_PVT_MEM_ADDR(uint32_t val) 5928 { 5929 return ((val) << A6XX_SP_FS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_FS_PVT_MEM_ADDR__MASK; 5930 } 5931 5932 #define REG_A6XX_SP_FS_PVT_MEM_SIZE 0x0000a988 5933 #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 5934 #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 5935 static inline uint32_t A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 5936 { 5937 return ((val >> 12) << A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 5938 } 5939 #define A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 5940 5941 #define REG_A6XX_SP_BLEND_CNTL 0x0000a989 5942 #define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff 5943 #define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 5944 static inline uint32_t A6XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val) 5945 { 5946 return ((val) << A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK; 5947 } 5948 #define A6XX_SP_BLEND_CNTL_UNK8 0x00000100 5949 #define A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200 5950 #define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 5951 5952 #define REG_A6XX_SP_SRGB_CNTL 0x0000a98a 5953 #define A6XX_SP_SRGB_CNTL_SRGB_MRT0 0x00000001 5954 #define A6XX_SP_SRGB_CNTL_SRGB_MRT1 0x00000002 5955 #define A6XX_SP_SRGB_CNTL_SRGB_MRT2 0x00000004 5956 #define A6XX_SP_SRGB_CNTL_SRGB_MRT3 0x00000008 5957 #define A6XX_SP_SRGB_CNTL_SRGB_MRT4 0x00000010 5958 #define A6XX_SP_SRGB_CNTL_SRGB_MRT5 0x00000020 5959 #define A6XX_SP_SRGB_CNTL_SRGB_MRT6 0x00000040 5960 #define A6XX_SP_SRGB_CNTL_SRGB_MRT7 0x00000080 5961 5962 #define REG_A6XX_SP_FS_RENDER_COMPONENTS 0x0000a98b 5963 #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK 0x0000000f 5964 #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT 0 5965 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val) 5966 { 5967 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK; 5968 } 5969 #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK 0x000000f0 5970 #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT 4 5971 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val) 5972 { 5973 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK; 5974 } 5975 #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK 0x00000f00 5976 #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT 8 5977 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val) 5978 { 5979 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK; 5980 } 5981 #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK 0x0000f000 5982 #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT 12 5983 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val) 5984 { 5985 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK; 5986 } 5987 #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK 0x000f0000 5988 #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT 16 5989 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val) 5990 { 5991 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK; 5992 } 5993 #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK 0x00f00000 5994 #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT 20 5995 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val) 5996 { 5997 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK; 5998 } 5999 #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK 0x0f000000 6000 #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT 24 6001 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val) 6002 { 6003 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK; 6004 } 6005 #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK 0xf0000000 6006 #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT 28 6007 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val) 6008 { 6009 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK; 6010 } 6011 6012 #define REG_A6XX_SP_FS_OUTPUT_CNTL0 0x0000a98c 6013 #define A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001 6014 #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK 0x0000ff00 6015 #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT 8 6016 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val) 6017 { 6018 return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK; 6019 } 6020 #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK 0x00ff0000 6021 #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT 16 6022 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(uint32_t val) 6023 { 6024 return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK; 6025 } 6026 #define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK 0xff000000 6027 #define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT 24 6028 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(uint32_t val) 6029 { 6030 return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK; 6031 } 6032 6033 #define REG_A6XX_SP_FS_OUTPUT_CNTL1 0x0000a98d 6034 #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f 6035 #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT 0 6036 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val) 6037 { 6038 return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK; 6039 } 6040 6041 static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; } 6042 6043 static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; } 6044 #define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff 6045 #define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0 6046 static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) 6047 { 6048 return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK; 6049 } 6050 #define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100 6051 6052 static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; } 6053 6054 static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; } 6055 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff 6056 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0 6057 static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val) 6058 { 6059 return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK; 6060 } 6061 #define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100 6062 #define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200 6063 #define A6XX_SP_FS_MRT_REG_UNK10 0x00000400 6064 6065 #define REG_A6XX_SP_FS_PREFETCH_CNTL 0x0000a99e 6066 #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK 0x00000007 6067 #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT 0 6068 static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_COUNT(uint32_t val) 6069 { 6070 return ((val) << A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK; 6071 } 6072 #define A6XX_SP_FS_PREFETCH_CNTL_UNK3 0x00000008 6073 #define A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK 0x00000ff0 6074 #define A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT 4 6075 static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK4(uint32_t val) 6076 { 6077 return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK; 6078 } 6079 #define A6XX_SP_FS_PREFETCH_CNTL_UNK12__MASK 0x00007000 6080 #define A6XX_SP_FS_PREFETCH_CNTL_UNK12__SHIFT 12 6081 static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK12(uint32_t val) 6082 { 6083 return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK12__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK12__MASK; 6084 } 6085 6086 static inline uint32_t REG_A6XX_SP_FS_PREFETCH(uint32_t i0) { return 0x0000a99f + 0x1*i0; } 6087 6088 static inline uint32_t REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; } 6089 #define A6XX_SP_FS_PREFETCH_CMD_SRC__MASK 0x0000007f 6090 #define A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT 0 6091 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val) 6092 { 6093 return ((val) << A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SRC__MASK; 6094 } 6095 #define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK 0x00000780 6096 #define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT 7 6097 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val) 6098 { 6099 return ((val) << A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK; 6100 } 6101 #define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK 0x0000f800 6102 #define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT 11 6103 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val) 6104 { 6105 return ((val) << A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK; 6106 } 6107 #define A6XX_SP_FS_PREFETCH_CMD_DST__MASK 0x003f0000 6108 #define A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT 16 6109 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_DST(uint32_t val) 6110 { 6111 return ((val) << A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_DST__MASK; 6112 } 6113 #define A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK 0x03c00000 6114 #define A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT 22 6115 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val) 6116 { 6117 return ((val) << A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK; 6118 } 6119 #define A6XX_SP_FS_PREFETCH_CMD_HALF 0x04000000 6120 #define A6XX_SP_FS_PREFETCH_CMD_CMD__MASK 0xf8000000 6121 #define A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT 27 6122 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_CMD(uint32_t val) 6123 { 6124 return ((val) << A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_CMD__MASK; 6125 } 6126 6127 static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; } 6128 6129 static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; } 6130 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK 0x0000ffff 6131 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT 0 6132 static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val) 6133 { 6134 return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK; 6135 } 6136 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK 0xffff0000 6137 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT 16 6138 static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val) 6139 { 6140 return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK; 6141 } 6142 6143 #define REG_A6XX_SP_FS_TEX_COUNT 0x0000a9a7 6144 6145 #define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8 6146 6147 #define REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET 0x0000a9a9 6148 #define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 6149 #define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 6150 static inline uint32_t A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 6151 { 6152 return ((val >> 11) << A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 6153 } 6154 6155 #define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0 6156 #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000 6157 #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20 6158 static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) 6159 { 6160 return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK; 6161 } 6162 #define A6XX_SP_CS_CTRL_REG0_UNK21 0x00200000 6163 #define A6XX_SP_CS_CTRL_REG0_UNK22 0x00400000 6164 #define A6XX_SP_CS_CTRL_REG0_SEPARATEPROLOG 0x00800000 6165 #define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000 6166 #define A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK 0x00000001 6167 #define A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT 0 6168 static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 6169 { 6170 return ((val) << A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK; 6171 } 6172 #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 6173 #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 6174 static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 6175 { 6176 return ((val) << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 6177 } 6178 #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 6179 #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 6180 static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 6181 { 6182 return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 6183 } 6184 #define A6XX_SP_CS_CTRL_REG0_UNK13 0x00002000 6185 #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 6186 #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 14 6187 static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val) 6188 { 6189 return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK; 6190 } 6191 6192 #define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1 6193 #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK 0x0000001f 6194 #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT 0 6195 static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(uint32_t val) 6196 { 6197 return ((val) << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK; 6198 } 6199 #define A6XX_SP_CS_UNKNOWN_A9B1_UNK5 0x00000020 6200 #define A6XX_SP_CS_UNKNOWN_A9B1_UNK6 0x00000040 6201 6202 #define REG_A6XX_SP_CS_BRANCH_COND 0x0000a9b2 6203 6204 #define REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET 0x0000a9b3 6205 6206 #define REG_A6XX_SP_CS_OBJ_START 0x0000a9b4 6207 #define A6XX_SP_CS_OBJ_START__MASK 0xffffffff 6208 #define A6XX_SP_CS_OBJ_START__SHIFT 0 6209 static inline uint32_t A6XX_SP_CS_OBJ_START(uint32_t val) 6210 { 6211 return ((val) << A6XX_SP_CS_OBJ_START__SHIFT) & A6XX_SP_CS_OBJ_START__MASK; 6212 } 6213 6214 #define REG_A6XX_SP_CS_PVT_MEM_PARAM 0x0000a9b6 6215 #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 6216 #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 6217 static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 6218 { 6219 return ((val >> 9) << A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 6220 } 6221 #define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 6222 #define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 6223 static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 6224 { 6225 return ((val) << A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 6226 } 6227 6228 #define REG_A6XX_SP_CS_PVT_MEM_ADDR 0x0000a9b7 6229 #define A6XX_SP_CS_PVT_MEM_ADDR__MASK 0xffffffff 6230 #define A6XX_SP_CS_PVT_MEM_ADDR__SHIFT 0 6231 static inline uint32_t A6XX_SP_CS_PVT_MEM_ADDR(uint32_t val) 6232 { 6233 return ((val) << A6XX_SP_CS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_CS_PVT_MEM_ADDR__MASK; 6234 } 6235 6236 #define REG_A6XX_SP_CS_PVT_MEM_SIZE 0x0000a9b9 6237 #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 6238 #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 6239 static inline uint32_t A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 6240 { 6241 return ((val >> 12) << A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 6242 } 6243 #define A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 6244 6245 #define REG_A6XX_SP_CS_TEX_COUNT 0x0000a9ba 6246 6247 #define REG_A6XX_SP_CS_CONFIG 0x0000a9bb 6248 #define A6XX_SP_CS_CONFIG_BINDLESS_TEX 0x00000001 6249 #define A6XX_SP_CS_CONFIG_BINDLESS_SAMP 0x00000002 6250 #define A6XX_SP_CS_CONFIG_BINDLESS_IBO 0x00000004 6251 #define A6XX_SP_CS_CONFIG_BINDLESS_UBO 0x00000008 6252 #define A6XX_SP_CS_CONFIG_ENABLED 0x00000100 6253 #define A6XX_SP_CS_CONFIG_NTEX__MASK 0x0001fe00 6254 #define A6XX_SP_CS_CONFIG_NTEX__SHIFT 9 6255 static inline uint32_t A6XX_SP_CS_CONFIG_NTEX(uint32_t val) 6256 { 6257 return ((val) << A6XX_SP_CS_CONFIG_NTEX__SHIFT) & A6XX_SP_CS_CONFIG_NTEX__MASK; 6258 } 6259 #define A6XX_SP_CS_CONFIG_NSAMP__MASK 0x003e0000 6260 #define A6XX_SP_CS_CONFIG_NSAMP__SHIFT 17 6261 static inline uint32_t A6XX_SP_CS_CONFIG_NSAMP(uint32_t val) 6262 { 6263 return ((val) << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK; 6264 } 6265 #define A6XX_SP_CS_CONFIG_NIBO__MASK 0x1fc00000 6266 #define A6XX_SP_CS_CONFIG_NIBO__SHIFT 22 6267 static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val) 6268 { 6269 return ((val) << A6XX_SP_CS_CONFIG_NIBO__SHIFT) & A6XX_SP_CS_CONFIG_NIBO__MASK; 6270 } 6271 6272 #define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc 6273 6274 #define REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET 0x0000a9bd 6275 #define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 6276 #define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 6277 static inline uint32_t A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 6278 { 6279 return ((val >> 11) << A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 6280 } 6281 6282 #define REG_A6XX_SP_CS_CNTL_0 0x0000a9c2 6283 #define A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff 6284 #define A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT 0 6285 static inline uint32_t A6XX_SP_CS_CNTL_0_WGIDCONSTID(uint32_t val) 6286 { 6287 return ((val) << A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK; 6288 } 6289 #define A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK 0x0000ff00 6290 #define A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT 8 6291 static inline uint32_t A6XX_SP_CS_CNTL_0_WGSIZECONSTID(uint32_t val) 6292 { 6293 return ((val) << A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK; 6294 } 6295 #define A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK 0x00ff0000 6296 #define A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT 16 6297 static inline uint32_t A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val) 6298 { 6299 return ((val) << A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK; 6300 } 6301 #define A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000 6302 #define A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT 24 6303 static inline uint32_t A6XX_SP_CS_CNTL_0_LOCALIDREGID(uint32_t val) 6304 { 6305 return ((val) << A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK; 6306 } 6307 6308 #define REG_A6XX_SP_CS_CNTL_1 0x0000a9c3 6309 #define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff 6310 #define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0 6311 static inline uint32_t A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) 6312 { 6313 return ((val) << A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK; 6314 } 6315 #define A6XX_SP_CS_CNTL_1_SINGLE_SP_CORE 0x00000100 6316 #define A6XX_SP_CS_CNTL_1_THREADSIZE__MASK 0x00000200 6317 #define A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT 9 6318 static inline uint32_t A6XX_SP_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) 6319 { 6320 return ((val) << A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_SP_CS_CNTL_1_THREADSIZE__MASK; 6321 } 6322 #define A6XX_SP_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400 6323 6324 #define REG_A6XX_SP_FS_TEX_SAMP 0x0000a9e0 6325 #define A6XX_SP_FS_TEX_SAMP__MASK 0xffffffff 6326 #define A6XX_SP_FS_TEX_SAMP__SHIFT 0 6327 static inline uint32_t A6XX_SP_FS_TEX_SAMP(uint32_t val) 6328 { 6329 return ((val) << A6XX_SP_FS_TEX_SAMP__SHIFT) & A6XX_SP_FS_TEX_SAMP__MASK; 6330 } 6331 6332 #define REG_A6XX_SP_CS_TEX_SAMP 0x0000a9e2 6333 #define A6XX_SP_CS_TEX_SAMP__MASK 0xffffffff 6334 #define A6XX_SP_CS_TEX_SAMP__SHIFT 0 6335 static inline uint32_t A6XX_SP_CS_TEX_SAMP(uint32_t val) 6336 { 6337 return ((val) << A6XX_SP_CS_TEX_SAMP__SHIFT) & A6XX_SP_CS_TEX_SAMP__MASK; 6338 } 6339 6340 #define REG_A6XX_SP_FS_TEX_CONST 0x0000a9e4 6341 #define A6XX_SP_FS_TEX_CONST__MASK 0xffffffff 6342 #define A6XX_SP_FS_TEX_CONST__SHIFT 0 6343 static inline uint32_t A6XX_SP_FS_TEX_CONST(uint32_t val) 6344 { 6345 return ((val) << A6XX_SP_FS_TEX_CONST__SHIFT) & A6XX_SP_FS_TEX_CONST__MASK; 6346 } 6347 6348 #define REG_A6XX_SP_CS_TEX_CONST 0x0000a9e6 6349 #define A6XX_SP_CS_TEX_CONST__MASK 0xffffffff 6350 #define A6XX_SP_CS_TEX_CONST__SHIFT 0 6351 static inline uint32_t A6XX_SP_CS_TEX_CONST(uint32_t val) 6352 { 6353 return ((val) << A6XX_SP_CS_TEX_CONST__SHIFT) & A6XX_SP_CS_TEX_CONST__MASK; 6354 } 6355 6356 static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; } 6357 6358 static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; } 6359 6360 #define REG_A6XX_SP_CS_IBO 0x0000a9f2 6361 #define A6XX_SP_CS_IBO__MASK 0xffffffff 6362 #define A6XX_SP_CS_IBO__SHIFT 0 6363 static inline uint32_t A6XX_SP_CS_IBO(uint32_t val) 6364 { 6365 return ((val) << A6XX_SP_CS_IBO__SHIFT) & A6XX_SP_CS_IBO__MASK; 6366 } 6367 6368 #define REG_A6XX_SP_CS_IBO_COUNT 0x0000aa00 6369 6370 #define REG_A6XX_SP_MODE_CONTROL 0x0000ab00 6371 #define A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE 0x00000001 6372 #define A6XX_SP_MODE_CONTROL_ISAMMODE__MASK 0x00000006 6373 #define A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT 1 6374 static inline uint32_t A6XX_SP_MODE_CONTROL_ISAMMODE(enum a6xx_isam_mode val) 6375 { 6376 return ((val) << A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT) & A6XX_SP_MODE_CONTROL_ISAMMODE__MASK; 6377 } 6378 #define A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE 0x00000008 6379 6380 #define REG_A6XX_SP_FS_CONFIG 0x0000ab04 6381 #define A6XX_SP_FS_CONFIG_BINDLESS_TEX 0x00000001 6382 #define A6XX_SP_FS_CONFIG_BINDLESS_SAMP 0x00000002 6383 #define A6XX_SP_FS_CONFIG_BINDLESS_IBO 0x00000004 6384 #define A6XX_SP_FS_CONFIG_BINDLESS_UBO 0x00000008 6385 #define A6XX_SP_FS_CONFIG_ENABLED 0x00000100 6386 #define A6XX_SP_FS_CONFIG_NTEX__MASK 0x0001fe00 6387 #define A6XX_SP_FS_CONFIG_NTEX__SHIFT 9 6388 static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val) 6389 { 6390 return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK; 6391 } 6392 #define A6XX_SP_FS_CONFIG_NSAMP__MASK 0x003e0000 6393 #define A6XX_SP_FS_CONFIG_NSAMP__SHIFT 17 6394 static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val) 6395 { 6396 return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK; 6397 } 6398 #define A6XX_SP_FS_CONFIG_NIBO__MASK 0x1fc00000 6399 #define A6XX_SP_FS_CONFIG_NIBO__SHIFT 22 6400 static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val) 6401 { 6402 return ((val) << A6XX_SP_FS_CONFIG_NIBO__SHIFT) & A6XX_SP_FS_CONFIG_NIBO__MASK; 6403 } 6404 6405 #define REG_A6XX_SP_FS_INSTRLEN 0x0000ab05 6406 6407 static inline uint32_t REG_A6XX_SP_BINDLESS_BASE(uint32_t i0) { return 0x0000ab10 + 0x2*i0; } 6408 6409 static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; } 6410 6411 #define REG_A6XX_SP_IBO 0x0000ab1a 6412 #define A6XX_SP_IBO__MASK 0xffffffff 6413 #define A6XX_SP_IBO__SHIFT 0 6414 static inline uint32_t A6XX_SP_IBO(uint32_t val) 6415 { 6416 return ((val) << A6XX_SP_IBO__SHIFT) & A6XX_SP_IBO__MASK; 6417 } 6418 6419 #define REG_A6XX_SP_IBO_COUNT 0x0000ab20 6420 6421 #define REG_A6XX_SP_2D_DST_FORMAT 0x0000acc0 6422 #define A6XX_SP_2D_DST_FORMAT_NORM 0x00000001 6423 #define A6XX_SP_2D_DST_FORMAT_SINT 0x00000002 6424 #define A6XX_SP_2D_DST_FORMAT_UINT 0x00000004 6425 #define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK 0x000007f8 6426 #define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT 3 6427 static inline uint32_t A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val) 6428 { 6429 return ((val) << A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT) & A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK; 6430 } 6431 #define A6XX_SP_2D_DST_FORMAT_SRGB 0x00000800 6432 #define A6XX_SP_2D_DST_FORMAT_MASK__MASK 0x0000f000 6433 #define A6XX_SP_2D_DST_FORMAT_MASK__SHIFT 12 6434 static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val) 6435 { 6436 return ((val) << A6XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A6XX_SP_2D_DST_FORMAT_MASK__MASK; 6437 } 6438 6439 #define REG_A6XX_SP_UNKNOWN_AE00 0x0000ae00 6440 6441 #define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01 6442 6443 #define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02 6444 6445 #define REG_A6XX_SP_CHICKEN_BITS 0x0000ae03 6446 6447 #define REG_A6XX_SP_FLOAT_CNTL 0x0000ae04 6448 #define A6XX_SP_FLOAT_CNTL_F16_NO_INF 0x00000008 6449 6450 #define REG_A6XX_SP_PERFCTR_ENABLE 0x0000ae0f 6451 #define A6XX_SP_PERFCTR_ENABLE_VS 0x00000001 6452 #define A6XX_SP_PERFCTR_ENABLE_HS 0x00000002 6453 #define A6XX_SP_PERFCTR_ENABLE_DS 0x00000004 6454 #define A6XX_SP_PERFCTR_ENABLE_GS 0x00000008 6455 #define A6XX_SP_PERFCTR_ENABLE_FS 0x00000010 6456 #define A6XX_SP_PERFCTR_ENABLE_CS 0x00000020 6457 6458 static inline uint32_t REG_A6XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae10 + 0x1*i0; } 6459 6460 #define REG_A6XX_SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE 0x0000be22 6461 6462 #define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR 0x0000b180 6463 #define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff 6464 #define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0 6465 static inline uint32_t A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(uint32_t val) 6466 { 6467 return ((val) << A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK; 6468 } 6469 6470 #define REG_A6XX_SP_UNKNOWN_B182 0x0000b182 6471 6472 #define REG_A6XX_SP_UNKNOWN_B183 0x0000b183 6473 6474 #define REG_A6XX_SP_UNKNOWN_B190 0x0000b190 6475 6476 #define REG_A6XX_SP_UNKNOWN_B191 0x0000b191 6477 6478 #define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300 6479 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 6480 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 6481 static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 6482 { 6483 return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK; 6484 } 6485 #define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK 0x0000000c 6486 #define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT 2 6487 static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_UNK2(uint32_t val) 6488 { 6489 return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK; 6490 } 6491 6492 #define REG_A6XX_SP_TP_DEST_MSAA_CNTL 0x0000b301 6493 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 6494 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 6495 static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 6496 { 6497 return ((val) << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK; 6498 } 6499 #define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 6500 6501 #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR 0x0000b302 6502 #define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff 6503 #define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0 6504 static inline uint32_t A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(uint32_t val) 6505 { 6506 return ((val) << A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK; 6507 } 6508 6509 #define REG_A6XX_SP_TP_SAMPLE_CONFIG 0x0000b304 6510 #define A6XX_SP_TP_SAMPLE_CONFIG_UNK0 0x00000001 6511 #define A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002 6512 6513 #define REG_A6XX_SP_TP_SAMPLE_LOCATION_0 0x0000b305 6514 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f 6515 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 6516 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) 6517 { 6518 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; 6519 } 6520 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 6521 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 6522 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) 6523 { 6524 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; 6525 } 6526 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 6527 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 6528 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) 6529 { 6530 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; 6531 } 6532 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 6533 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 6534 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) 6535 { 6536 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; 6537 } 6538 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 6539 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 6540 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) 6541 { 6542 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; 6543 } 6544 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 6545 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 6546 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) 6547 { 6548 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; 6549 } 6550 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 6551 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 6552 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) 6553 { 6554 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; 6555 } 6556 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 6557 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 6558 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) 6559 { 6560 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; 6561 } 6562 6563 #define REG_A6XX_SP_TP_SAMPLE_LOCATION_1 0x0000b306 6564 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f 6565 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 6566 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) 6567 { 6568 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; 6569 } 6570 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 6571 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 6572 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) 6573 { 6574 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; 6575 } 6576 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 6577 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 6578 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) 6579 { 6580 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; 6581 } 6582 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 6583 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 6584 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) 6585 { 6586 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; 6587 } 6588 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 6589 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 6590 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) 6591 { 6592 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; 6593 } 6594 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 6595 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 6596 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) 6597 { 6598 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; 6599 } 6600 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 6601 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 6602 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) 6603 { 6604 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; 6605 } 6606 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 6607 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 6608 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) 6609 { 6610 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; 6611 } 6612 6613 #define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307 6614 #define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00003fff 6615 #define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0 6616 static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val) 6617 { 6618 return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK; 6619 } 6620 #define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x3fff0000 6621 #define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16 6622 static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val) 6623 { 6624 return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK; 6625 } 6626 6627 #define REG_A6XX_SP_TP_MODE_CNTL 0x0000b309 6628 #define A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK 0x00000003 6629 #define A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT 0 6630 static inline uint32_t A6XX_SP_TP_MODE_CNTL_ISAMMODE(enum a6xx_isam_mode val) 6631 { 6632 return ((val) << A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT) & A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK; 6633 } 6634 #define A6XX_SP_TP_MODE_CNTL_UNK3__MASK 0x000000fc 6635 #define A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT 2 6636 static inline uint32_t A6XX_SP_TP_MODE_CNTL_UNK3(uint32_t val) 6637 { 6638 return ((val) << A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT) & A6XX_SP_TP_MODE_CNTL_UNK3__MASK; 6639 } 6640 6641 #define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0 6642 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff 6643 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 6644 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val) 6645 { 6646 return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK; 6647 } 6648 #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300 6649 #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT 8 6650 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val) 6651 { 6652 return ((val) << A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK; 6653 } 6654 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00 6655 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10 6656 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) 6657 { 6658 return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK; 6659 } 6660 #define A6XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000 6661 #define A6XX_SP_PS_2D_SRC_INFO_SRGB 0x00002000 6662 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK 0x0000c000 6663 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT 14 6664 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val) 6665 { 6666 return ((val) << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK; 6667 } 6668 #define A6XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000 6669 #define A6XX_SP_PS_2D_SRC_INFO_UNK17 0x00020000 6670 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE 0x00040000 6671 #define A6XX_SP_PS_2D_SRC_INFO_UNK19 0x00080000 6672 #define A6XX_SP_PS_2D_SRC_INFO_UNK20 0x00100000 6673 #define A6XX_SP_PS_2D_SRC_INFO_UNK21 0x00200000 6674 #define A6XX_SP_PS_2D_SRC_INFO_UNK22 0x00400000 6675 #define A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK 0x07800000 6676 #define A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT 23 6677 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val) 6678 { 6679 return ((val) << A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK; 6680 } 6681 #define A6XX_SP_PS_2D_SRC_INFO_UNK28 0x10000000 6682 6683 #define REG_A6XX_SP_PS_2D_SRC_SIZE 0x0000b4c1 6684 #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff 6685 #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT 0 6686 static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val) 6687 { 6688 return ((val) << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK; 6689 } 6690 #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK 0x3fff8000 6691 #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT 15 6692 static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val) 6693 { 6694 return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK; 6695 } 6696 6697 #define REG_A6XX_SP_PS_2D_SRC 0x0000b4c2 6698 #define A6XX_SP_PS_2D_SRC__MASK 0xffffffff 6699 #define A6XX_SP_PS_2D_SRC__SHIFT 0 6700 static inline uint32_t A6XX_SP_PS_2D_SRC(uint32_t val) 6701 { 6702 return ((val) << A6XX_SP_PS_2D_SRC__SHIFT) & A6XX_SP_PS_2D_SRC__MASK; 6703 } 6704 6705 #define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4 6706 #define A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK 0x000001ff 6707 #define A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT 0 6708 static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val) 6709 { 6710 return ((val) << A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK; 6711 } 6712 #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x00fffe00 6713 #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9 6714 static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val) 6715 { 6716 return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK; 6717 } 6718 6719 #define REG_A6XX_SP_PS_2D_SRC_PLANE1 0x0000b4c5 6720 #define A6XX_SP_PS_2D_SRC_PLANE1__MASK 0xffffffff 6721 #define A6XX_SP_PS_2D_SRC_PLANE1__SHIFT 0 6722 static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE1(uint32_t val) 6723 { 6724 return ((val) << A6XX_SP_PS_2D_SRC_PLANE1__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE1__MASK; 6725 } 6726 6727 #define REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH 0x0000b4c7 6728 #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK 0x00000fff 6729 #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT 0 6730 static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val) 6731 { 6732 return ((val >> 6) << A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK; 6733 } 6734 6735 #define REG_A6XX_SP_PS_2D_SRC_PLANE2 0x0000b4c8 6736 #define A6XX_SP_PS_2D_SRC_PLANE2__MASK 0xffffffff 6737 #define A6XX_SP_PS_2D_SRC_PLANE2__SHIFT 0 6738 static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE2(uint32_t val) 6739 { 6740 return ((val) << A6XX_SP_PS_2D_SRC_PLANE2__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE2__MASK; 6741 } 6742 6743 #define REG_A6XX_SP_PS_2D_SRC_FLAGS 0x0000b4ca 6744 #define A6XX_SP_PS_2D_SRC_FLAGS__MASK 0xffffffff 6745 #define A6XX_SP_PS_2D_SRC_FLAGS__SHIFT 0 6746 static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS(uint32_t val) 6747 { 6748 return ((val) << A6XX_SP_PS_2D_SRC_FLAGS__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS__MASK; 6749 } 6750 6751 #define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b4cc 6752 #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK 0x000000ff 6753 #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT 0 6754 static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val) 6755 { 6756 return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK; 6757 } 6758 6759 #define REG_A6XX_SP_PS_UNKNOWN_B4CD 0x0000b4cd 6760 6761 #define REG_A6XX_SP_PS_UNKNOWN_B4CE 0x0000b4ce 6762 6763 #define REG_A6XX_SP_PS_UNKNOWN_B4CF 0x0000b4cf 6764 6765 #define REG_A6XX_SP_PS_UNKNOWN_B4D0 0x0000b4d0 6766 6767 #define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1 6768 #define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00003fff 6769 #define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0 6770 static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val) 6771 { 6772 return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK; 6773 } 6774 #define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x3fff0000 6775 #define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16 6776 static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val) 6777 { 6778 return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK; 6779 } 6780 6781 #define REG_A6XX_TPL1_DBG_ECO_CNTL 0x0000b600 6782 6783 #define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601 6784 6785 #define REG_A6XX_TPL1_UNKNOWN_B602 0x0000b602 6786 6787 #define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604 6788 #define A6XX_TPL1_NC_MODE_CNTL_MODE 0x00000001 6789 #define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006 6790 #define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT 1 6791 static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT(uint32_t val) 6792 { 6793 return ((val) << A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK; 6794 } 6795 #define A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008 6796 #define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000010 6797 #define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT 4 6798 static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT(uint32_t val) 6799 { 6800 return ((val) << A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK; 6801 } 6802 #define A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK 0x000000c0 6803 #define A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT 6 6804 static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UNK6(uint32_t val) 6805 { 6806 return ((val) << A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK; 6807 } 6808 6809 #define REG_A6XX_TPL1_UNKNOWN_B605 0x0000b605 6810 6811 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608 6812 6813 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609 6814 6815 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a 6816 6817 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b 6818 6819 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c 6820 6821 static inline uint32_t REG_A6XX_TPL1_PERFCTR_TP_SEL(uint32_t i0) { return 0x0000b610 + 0x1*i0; } 6822 6823 #define REG_A6XX_HLSQ_VS_CNTL 0x0000b800 6824 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff 6825 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0 6826 static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val) 6827 { 6828 return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK; 6829 } 6830 #define A6XX_HLSQ_VS_CNTL_ENABLED 0x00000100 6831 6832 #define REG_A6XX_HLSQ_HS_CNTL 0x0000b801 6833 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff 6834 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0 6835 static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val) 6836 { 6837 return ((val >> 2) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK; 6838 } 6839 #define A6XX_HLSQ_HS_CNTL_ENABLED 0x00000100 6840 6841 #define REG_A6XX_HLSQ_DS_CNTL 0x0000b802 6842 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff 6843 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0 6844 static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val) 6845 { 6846 return ((val >> 2) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK; 6847 } 6848 #define A6XX_HLSQ_DS_CNTL_ENABLED 0x00000100 6849 6850 #define REG_A6XX_HLSQ_GS_CNTL 0x0000b803 6851 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff 6852 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0 6853 static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val) 6854 { 6855 return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK; 6856 } 6857 #define A6XX_HLSQ_GS_CNTL_ENABLED 0x00000100 6858 6859 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD 0x0000b820 6860 6861 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR 0x0000b821 6862 #define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK 0xffffffff 6863 #define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT 0 6864 static inline uint32_t A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR(uint32_t val) 6865 { 6866 return ((val) << A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK; 6867 } 6868 6869 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA 0x0000b823 6870 6871 #define REG_A6XX_HLSQ_FS_CNTL_0 0x0000b980 6872 #define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK 0x00000001 6873 #define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT 0 6874 static inline uint32_t A6XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val) 6875 { 6876 return ((val) << A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK; 6877 } 6878 #define A6XX_HLSQ_FS_CNTL_0_VARYINGS 0x00000002 6879 #define A6XX_HLSQ_FS_CNTL_0_UNK2__MASK 0x00000ffc 6880 #define A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT 2 6881 static inline uint32_t A6XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val) 6882 { 6883 return ((val) << A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A6XX_HLSQ_FS_CNTL_0_UNK2__MASK; 6884 } 6885 6886 #define REG_A6XX_HLSQ_UNKNOWN_B981 0x0000b981 6887 6888 #define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982 6889 6890 #define REG_A6XX_HLSQ_CONTROL_2_REG 0x0000b983 6891 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff 6892 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0 6893 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) 6894 { 6895 return ((val) << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; 6896 } 6897 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00 6898 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8 6899 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) 6900 { 6901 return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK; 6902 } 6903 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000 6904 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16 6905 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) 6906 { 6907 return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK; 6908 } 6909 #define A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK 0xff000000 6910 #define A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT 24 6911 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SIZE(uint32_t val) 6912 { 6913 return ((val) << A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK; 6914 } 6915 6916 #define REG_A6XX_HLSQ_CONTROL_3_REG 0x0000b984 6917 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff 6918 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0 6919 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val) 6920 { 6921 return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK; 6922 } 6923 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00 6924 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8 6925 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val) 6926 { 6927 return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK; 6928 } 6929 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000 6930 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16 6931 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val) 6932 { 6933 return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK; 6934 } 6935 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000 6936 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24 6937 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) 6938 { 6939 return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK; 6940 } 6941 6942 #define REG_A6XX_HLSQ_CONTROL_4_REG 0x0000b985 6943 #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff 6944 #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0 6945 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val) 6946 { 6947 return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK; 6948 } 6949 #define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00 6950 #define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8 6951 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val) 6952 { 6953 return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK; 6954 } 6955 #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000 6956 #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16 6957 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) 6958 { 6959 return ((val) << A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK; 6960 } 6961 #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000 6962 #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24 6963 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) 6964 { 6965 return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; 6966 } 6967 6968 #define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986 6969 #define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK 0x000000ff 6970 #define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT 0 6971 static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val) 6972 { 6973 return ((val) << A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK; 6974 } 6975 #define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK 0x0000ff00 6976 #define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT 8 6977 static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val) 6978 { 6979 return ((val) << A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK; 6980 } 6981 6982 #define REG_A6XX_HLSQ_CS_CNTL 0x0000b987 6983 #define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff 6984 #define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0 6985 static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val) 6986 { 6987 return ((val >> 2) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK; 6988 } 6989 #define A6XX_HLSQ_CS_CNTL_ENABLED 0x00000100 6990 6991 #define REG_A6XX_HLSQ_CS_NDRANGE_0 0x0000b990 6992 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003 6993 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0 6994 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) 6995 { 6996 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK; 6997 } 6998 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc 6999 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2 7000 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) 7001 { 7002 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK; 7003 } 7004 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000 7005 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12 7006 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) 7007 { 7008 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK; 7009 } 7010 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000 7011 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22 7012 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) 7013 { 7014 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK; 7015 } 7016 7017 #define REG_A6XX_HLSQ_CS_NDRANGE_1 0x0000b991 7018 #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff 7019 #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0 7020 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val) 7021 { 7022 return ((val) << A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK; 7023 } 7024 7025 #define REG_A6XX_HLSQ_CS_NDRANGE_2 0x0000b992 7026 #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff 7027 #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0 7028 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val) 7029 { 7030 return ((val) << A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK; 7031 } 7032 7033 #define REG_A6XX_HLSQ_CS_NDRANGE_3 0x0000b993 7034 #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff 7035 #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0 7036 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val) 7037 { 7038 return ((val) << A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK; 7039 } 7040 7041 #define REG_A6XX_HLSQ_CS_NDRANGE_4 0x0000b994 7042 #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff 7043 #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0 7044 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val) 7045 { 7046 return ((val) << A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK; 7047 } 7048 7049 #define REG_A6XX_HLSQ_CS_NDRANGE_5 0x0000b995 7050 #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff 7051 #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0 7052 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val) 7053 { 7054 return ((val) << A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK; 7055 } 7056 7057 #define REG_A6XX_HLSQ_CS_NDRANGE_6 0x0000b996 7058 #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff 7059 #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0 7060 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val) 7061 { 7062 return ((val) << A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK; 7063 } 7064 7065 #define REG_A6XX_HLSQ_CS_CNTL_0 0x0000b997 7066 #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff 7067 #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0 7068 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val) 7069 { 7070 return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK; 7071 } 7072 #define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK 0x0000ff00 7073 #define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT 8 7074 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(uint32_t val) 7075 { 7076 return ((val) << A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK; 7077 } 7078 #define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK 0x00ff0000 7079 #define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT 16 7080 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val) 7081 { 7082 return ((val) << A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK; 7083 } 7084 #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000 7085 #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24 7086 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) 7087 { 7088 return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK; 7089 } 7090 7091 #define REG_A6XX_HLSQ_CS_CNTL_1 0x0000b998 7092 #define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff 7093 #define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0 7094 static inline uint32_t A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) 7095 { 7096 return ((val) << A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK; 7097 } 7098 #define A6XX_HLSQ_CS_CNTL_1_SINGLE_SP_CORE 0x00000100 7099 #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK 0x00000200 7100 #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT 9 7101 static inline uint32_t A6XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) 7102 { 7103 return ((val) << A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK; 7104 } 7105 #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400 7106 7107 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X 0x0000b999 7108 7109 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000b99a 7110 7111 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000b99b 7112 7113 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD 0x0000b9a0 7114 7115 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR 0x0000b9a1 7116 #define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK 0xffffffff 7117 #define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT 0 7118 static inline uint32_t A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR(uint32_t val) 7119 { 7120 return ((val) << A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK; 7121 } 7122 7123 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA 0x0000b9a3 7124 7125 static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; } 7126 7127 static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; } 7128 7129 #define REG_A6XX_HLSQ_CS_UNKNOWN_B9D0 0x0000b9d0 7130 #define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK 0x0000001f 7131 #define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT 0 7132 static inline uint32_t A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE(uint32_t val) 7133 { 7134 return ((val) << A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT) & A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK; 7135 } 7136 #define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK5 0x00000020 7137 #define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK6 0x00000040 7138 7139 #define REG_A6XX_HLSQ_DRAW_CMD 0x0000bb00 7140 #define A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK 0x000000ff 7141 #define A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT 0 7142 static inline uint32_t A6XX_HLSQ_DRAW_CMD_STATE_ID(uint32_t val) 7143 { 7144 return ((val) << A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK; 7145 } 7146 7147 #define REG_A6XX_HLSQ_DISPATCH_CMD 0x0000bb01 7148 #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK 0x000000ff 7149 #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT 0 7150 static inline uint32_t A6XX_HLSQ_DISPATCH_CMD_STATE_ID(uint32_t val) 7151 { 7152 return ((val) << A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK; 7153 } 7154 7155 #define REG_A6XX_HLSQ_EVENT_CMD 0x0000bb02 7156 #define A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK 0x00ff0000 7157 #define A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT 16 7158 static inline uint32_t A6XX_HLSQ_EVENT_CMD_STATE_ID(uint32_t val) 7159 { 7160 return ((val) << A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK; 7161 } 7162 #define A6XX_HLSQ_EVENT_CMD_EVENT__MASK 0x0000007f 7163 #define A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT 0 7164 static inline uint32_t A6XX_HLSQ_EVENT_CMD_EVENT(enum vgt_event_type val) 7165 { 7166 return ((val) << A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_EVENT_CMD_EVENT__MASK; 7167 } 7168 7169 #define REG_A6XX_HLSQ_INVALIDATE_CMD 0x0000bb08 7170 #define A6XX_HLSQ_INVALIDATE_CMD_VS_STATE 0x00000001 7171 #define A6XX_HLSQ_INVALIDATE_CMD_HS_STATE 0x00000002 7172 #define A6XX_HLSQ_INVALIDATE_CMD_DS_STATE 0x00000004 7173 #define A6XX_HLSQ_INVALIDATE_CMD_GS_STATE 0x00000008 7174 #define A6XX_HLSQ_INVALIDATE_CMD_FS_STATE 0x00000010 7175 #define A6XX_HLSQ_INVALIDATE_CMD_CS_STATE 0x00000020 7176 #define A6XX_HLSQ_INVALIDATE_CMD_CS_IBO 0x00000040 7177 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO 0x00000080 7178 #define A6XX_HLSQ_INVALIDATE_CMD_CS_SHARED_CONST 0x00080000 7179 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_SHARED_CONST 0x00000100 7180 #define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK 0x00003e00 7181 #define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT 9 7182 static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val) 7183 { 7184 return ((val) << A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK; 7185 } 7186 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK 0x0007c000 7187 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT 14 7188 static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val) 7189 { 7190 return ((val) << A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK; 7191 } 7192 7193 #define REG_A6XX_HLSQ_FS_CNTL 0x0000bb10 7194 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff 7195 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0 7196 static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val) 7197 { 7198 return ((val >> 2) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK; 7199 } 7200 #define A6XX_HLSQ_FS_CNTL_ENABLED 0x00000100 7201 7202 #define REG_A6XX_HLSQ_SHARED_CONSTS 0x0000bb11 7203 #define A6XX_HLSQ_SHARED_CONSTS_ENABLE 0x00000001 7204 7205 static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE(uint32_t i0) { return 0x0000bb20 + 0x2*i0; } 7206 7207 static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000bb20 + 0x2*i0; } 7208 7209 #define REG_A6XX_HLSQ_2D_EVENT_CMD 0x0000bd80 7210 #define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00 7211 #define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT 8 7212 static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_STATE_ID(uint32_t val) 7213 { 7214 return ((val) << A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK; 7215 } 7216 #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK 0x0000007f 7217 #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT 0 7218 static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val) 7219 { 7220 return ((val) << A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK; 7221 } 7222 7223 #define REG_A6XX_HLSQ_UNKNOWN_BE00 0x0000be00 7224 7225 #define REG_A6XX_HLSQ_UNKNOWN_BE01 0x0000be01 7226 7227 #define REG_A6XX_HLSQ_UNKNOWN_BE04 0x0000be04 7228 7229 #define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05 7230 7231 #define REG_A6XX_HLSQ_UNKNOWN_BE08 0x0000be08 7232 7233 static inline uint32_t REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000be10 + 0x1*i0; } 7234 7235 #define REG_A6XX_HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE 0x0000be22 7236 7237 #define REG_A6XX_CP_EVENT_START 0x0000d600 7238 #define A6XX_CP_EVENT_START_STATE_ID__MASK 0x000000ff 7239 #define A6XX_CP_EVENT_START_STATE_ID__SHIFT 0 7240 static inline uint32_t A6XX_CP_EVENT_START_STATE_ID(uint32_t val) 7241 { 7242 return ((val) << A6XX_CP_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_EVENT_START_STATE_ID__MASK; 7243 } 7244 7245 #define REG_A6XX_CP_EVENT_END 0x0000d601 7246 #define A6XX_CP_EVENT_END_STATE_ID__MASK 0x000000ff 7247 #define A6XX_CP_EVENT_END_STATE_ID__SHIFT 0 7248 static inline uint32_t A6XX_CP_EVENT_END_STATE_ID(uint32_t val) 7249 { 7250 return ((val) << A6XX_CP_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_EVENT_END_STATE_ID__MASK; 7251 } 7252 7253 #define REG_A6XX_CP_2D_EVENT_START 0x0000d700 7254 #define A6XX_CP_2D_EVENT_START_STATE_ID__MASK 0x000000ff 7255 #define A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT 0 7256 static inline uint32_t A6XX_CP_2D_EVENT_START_STATE_ID(uint32_t val) 7257 { 7258 return ((val) << A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_START_STATE_ID__MASK; 7259 } 7260 7261 #define REG_A6XX_CP_2D_EVENT_END 0x0000d701 7262 #define A6XX_CP_2D_EVENT_END_STATE_ID__MASK 0x000000ff 7263 #define A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT 0 7264 static inline uint32_t A6XX_CP_2D_EVENT_END_STATE_ID(uint32_t val) 7265 { 7266 return ((val) << A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_END_STATE_ID__MASK; 7267 } 7268 7269 #define REG_A6XX_TEX_SAMP_0 0x00000000 7270 #define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 7271 #define A6XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 7272 #define A6XX_TEX_SAMP_0_XY_MAG__SHIFT 1 7273 static inline uint32_t A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val) 7274 { 7275 return ((val) << A6XX_TEX_SAMP_0_XY_MAG__SHIFT) & A6XX_TEX_SAMP_0_XY_MAG__MASK; 7276 } 7277 #define A6XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 7278 #define A6XX_TEX_SAMP_0_XY_MIN__SHIFT 3 7279 static inline uint32_t A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val) 7280 { 7281 return ((val) << A6XX_TEX_SAMP_0_XY_MIN__SHIFT) & A6XX_TEX_SAMP_0_XY_MIN__MASK; 7282 } 7283 #define A6XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 7284 #define A6XX_TEX_SAMP_0_WRAP_S__SHIFT 5 7285 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val) 7286 { 7287 return ((val) << A6XX_TEX_SAMP_0_WRAP_S__SHIFT) & A6XX_TEX_SAMP_0_WRAP_S__MASK; 7288 } 7289 #define A6XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 7290 #define A6XX_TEX_SAMP_0_WRAP_T__SHIFT 8 7291 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val) 7292 { 7293 return ((val) << A6XX_TEX_SAMP_0_WRAP_T__SHIFT) & A6XX_TEX_SAMP_0_WRAP_T__MASK; 7294 } 7295 #define A6XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 7296 #define A6XX_TEX_SAMP_0_WRAP_R__SHIFT 11 7297 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val) 7298 { 7299 return ((val) << A6XX_TEX_SAMP_0_WRAP_R__SHIFT) & A6XX_TEX_SAMP_0_WRAP_R__MASK; 7300 } 7301 #define A6XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 7302 #define A6XX_TEX_SAMP_0_ANISO__SHIFT 14 7303 static inline uint32_t A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val) 7304 { 7305 return ((val) << A6XX_TEX_SAMP_0_ANISO__SHIFT) & A6XX_TEX_SAMP_0_ANISO__MASK; 7306 } 7307 #define A6XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000 7308 #define A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19 7309 static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val) 7310 { 7311 return ((((int32_t)(val * 256.0))) << A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A6XX_TEX_SAMP_0_LOD_BIAS__MASK; 7312 } 7313 7314 #define REG_A6XX_TEX_SAMP_1 0x00000001 7315 #define A6XX_TEX_SAMP_1_CLAMPENABLE 0x00000001 7316 #define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e 7317 #define A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 7318 static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) 7319 { 7320 return ((val) << A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK; 7321 } 7322 #define A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010 7323 #define A6XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 7324 #define A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 7325 #define A6XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 7326 #define A6XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 7327 static inline uint32_t A6XX_TEX_SAMP_1_MAX_LOD(float val) 7328 { 7329 return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK; 7330 } 7331 #define A6XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 7332 #define A6XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 7333 static inline uint32_t A6XX_TEX_SAMP_1_MIN_LOD(float val) 7334 { 7335 return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK; 7336 } 7337 7338 #define REG_A6XX_TEX_SAMP_2 0x00000002 7339 #define A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK 0x00000003 7340 #define A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT 0 7341 static inline uint32_t A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode val) 7342 { 7343 return ((val) << A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT) & A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK; 7344 } 7345 #define A6XX_TEX_SAMP_2_CHROMA_LINEAR 0x00000020 7346 #define A6XX_TEX_SAMP_2_BCOLOR__MASK 0xffffff80 7347 #define A6XX_TEX_SAMP_2_BCOLOR__SHIFT 7 7348 static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR(uint32_t val) 7349 { 7350 return ((val) << A6XX_TEX_SAMP_2_BCOLOR__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR__MASK; 7351 } 7352 7353 #define REG_A6XX_TEX_SAMP_3 0x00000003 7354 7355 #define REG_A6XX_TEX_CONST_0 0x00000000 7356 #define A6XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003 7357 #define A6XX_TEX_CONST_0_TILE_MODE__SHIFT 0 7358 static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val) 7359 { 7360 return ((val) << A6XX_TEX_CONST_0_TILE_MODE__SHIFT) & A6XX_TEX_CONST_0_TILE_MODE__MASK; 7361 } 7362 #define A6XX_TEX_CONST_0_SRGB 0x00000004 7363 #define A6XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 7364 #define A6XX_TEX_CONST_0_SWIZ_X__SHIFT 4 7365 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val) 7366 { 7367 return ((val) << A6XX_TEX_CONST_0_SWIZ_X__SHIFT) & A6XX_TEX_CONST_0_SWIZ_X__MASK; 7368 } 7369 #define A6XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 7370 #define A6XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 7371 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val) 7372 { 7373 return ((val) << A6XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Y__MASK; 7374 } 7375 #define A6XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 7376 #define A6XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 7377 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val) 7378 { 7379 return ((val) << A6XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Z__MASK; 7380 } 7381 #define A6XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 7382 #define A6XX_TEX_CONST_0_SWIZ_W__SHIFT 13 7383 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val) 7384 { 7385 return ((val) << A6XX_TEX_CONST_0_SWIZ_W__SHIFT) & A6XX_TEX_CONST_0_SWIZ_W__MASK; 7386 } 7387 #define A6XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 7388 #define A6XX_TEX_CONST_0_MIPLVLS__SHIFT 16 7389 static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val) 7390 { 7391 return ((val) << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK; 7392 } 7393 #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X 0x00010000 7394 #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y 0x00040000 7395 #define A6XX_TEX_CONST_0_SAMPLES__MASK 0x00300000 7396 #define A6XX_TEX_CONST_0_SAMPLES__SHIFT 20 7397 static inline uint32_t A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val) 7398 { 7399 return ((val) << A6XX_TEX_CONST_0_SAMPLES__SHIFT) & A6XX_TEX_CONST_0_SAMPLES__MASK; 7400 } 7401 #define A6XX_TEX_CONST_0_FMT__MASK 0x3fc00000 7402 #define A6XX_TEX_CONST_0_FMT__SHIFT 22 7403 static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_format val) 7404 { 7405 return ((val) << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK; 7406 } 7407 #define A6XX_TEX_CONST_0_SWAP__MASK 0xc0000000 7408 #define A6XX_TEX_CONST_0_SWAP__SHIFT 30 7409 static inline uint32_t A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val) 7410 { 7411 return ((val) << A6XX_TEX_CONST_0_SWAP__SHIFT) & A6XX_TEX_CONST_0_SWAP__MASK; 7412 } 7413 7414 #define REG_A6XX_TEX_CONST_1 0x00000001 7415 #define A6XX_TEX_CONST_1_WIDTH__MASK 0x00007fff 7416 #define A6XX_TEX_CONST_1_WIDTH__SHIFT 0 7417 static inline uint32_t A6XX_TEX_CONST_1_WIDTH(uint32_t val) 7418 { 7419 return ((val) << A6XX_TEX_CONST_1_WIDTH__SHIFT) & A6XX_TEX_CONST_1_WIDTH__MASK; 7420 } 7421 #define A6XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000 7422 #define A6XX_TEX_CONST_1_HEIGHT__SHIFT 15 7423 static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val) 7424 { 7425 return ((val) << A6XX_TEX_CONST_1_HEIGHT__SHIFT) & A6XX_TEX_CONST_1_HEIGHT__MASK; 7426 } 7427 7428 #define REG_A6XX_TEX_CONST_2 0x00000002 7429 #define A6XX_TEX_CONST_2_BUFFER 0x00000010 7430 #define A6XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f 7431 #define A6XX_TEX_CONST_2_PITCHALIGN__SHIFT 0 7432 static inline uint32_t A6XX_TEX_CONST_2_PITCHALIGN(uint32_t val) 7433 { 7434 return ((val) << A6XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A6XX_TEX_CONST_2_PITCHALIGN__MASK; 7435 } 7436 #define A6XX_TEX_CONST_2_PITCH__MASK 0x1fffff80 7437 #define A6XX_TEX_CONST_2_PITCH__SHIFT 7 7438 static inline uint32_t A6XX_TEX_CONST_2_PITCH(uint32_t val) 7439 { 7440 return ((val) << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK; 7441 } 7442 #define A6XX_TEX_CONST_2_TYPE__MASK 0xe0000000 7443 #define A6XX_TEX_CONST_2_TYPE__SHIFT 29 7444 static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val) 7445 { 7446 return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK; 7447 } 7448 7449 #define REG_A6XX_TEX_CONST_3 0x00000003 7450 #define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff 7451 #define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0 7452 static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) 7453 { 7454 return ((val >> 12) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK; 7455 } 7456 #define A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000 7457 #define A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23 7458 static inline uint32_t A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val) 7459 { 7460 return ((val >> 12) << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK; 7461 } 7462 #define A6XX_TEX_CONST_3_TILE_ALL 0x08000000 7463 #define A6XX_TEX_CONST_3_FLAG 0x10000000 7464 7465 #define REG_A6XX_TEX_CONST_4 0x00000004 7466 #define A6XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0 7467 #define A6XX_TEX_CONST_4_BASE_LO__SHIFT 5 7468 static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val) 7469 { 7470 return ((val >> 5) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK; 7471 } 7472 7473 #define REG_A6XX_TEX_CONST_5 0x00000005 7474 #define A6XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff 7475 #define A6XX_TEX_CONST_5_BASE_HI__SHIFT 0 7476 static inline uint32_t A6XX_TEX_CONST_5_BASE_HI(uint32_t val) 7477 { 7478 return ((val) << A6XX_TEX_CONST_5_BASE_HI__SHIFT) & A6XX_TEX_CONST_5_BASE_HI__MASK; 7479 } 7480 #define A6XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000 7481 #define A6XX_TEX_CONST_5_DEPTH__SHIFT 17 7482 static inline uint32_t A6XX_TEX_CONST_5_DEPTH(uint32_t val) 7483 { 7484 return ((val) << A6XX_TEX_CONST_5_DEPTH__SHIFT) & A6XX_TEX_CONST_5_DEPTH__MASK; 7485 } 7486 7487 #define REG_A6XX_TEX_CONST_6 0x00000006 7488 #define A6XX_TEX_CONST_6_PLANE_PITCH__MASK 0xffffff00 7489 #define A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT 8 7490 static inline uint32_t A6XX_TEX_CONST_6_PLANE_PITCH(uint32_t val) 7491 { 7492 return ((val) << A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT) & A6XX_TEX_CONST_6_PLANE_PITCH__MASK; 7493 } 7494 7495 #define REG_A6XX_TEX_CONST_7 0x00000007 7496 #define A6XX_TEX_CONST_7_FLAG_LO__MASK 0xffffffe0 7497 #define A6XX_TEX_CONST_7_FLAG_LO__SHIFT 5 7498 static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val) 7499 { 7500 return ((val >> 5) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK; 7501 } 7502 7503 #define REG_A6XX_TEX_CONST_8 0x00000008 7504 #define A6XX_TEX_CONST_8_FLAG_HI__MASK 0x0001ffff 7505 #define A6XX_TEX_CONST_8_FLAG_HI__SHIFT 0 7506 static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val) 7507 { 7508 return ((val) << A6XX_TEX_CONST_8_FLAG_HI__SHIFT) & A6XX_TEX_CONST_8_FLAG_HI__MASK; 7509 } 7510 7511 #define REG_A6XX_TEX_CONST_9 0x00000009 7512 #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff 7513 #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0 7514 static inline uint32_t A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) 7515 { 7516 return ((val >> 4) << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK; 7517 } 7518 7519 #define REG_A6XX_TEX_CONST_10 0x0000000a 7520 #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK 0x0000007f 7521 #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT 0 7522 static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val) 7523 { 7524 return ((val >> 6) << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK; 7525 } 7526 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK 0x00000f00 7527 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT 8 7528 static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(uint32_t val) 7529 { 7530 return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK; 7531 } 7532 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK 0x0000f000 7533 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT 12 7534 static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(uint32_t val) 7535 { 7536 return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK; 7537 } 7538 7539 #define REG_A6XX_TEX_CONST_11 0x0000000b 7540 7541 #define REG_A6XX_TEX_CONST_12 0x0000000c 7542 7543 #define REG_A6XX_TEX_CONST_13 0x0000000d 7544 7545 #define REG_A6XX_TEX_CONST_14 0x0000000e 7546 7547 #define REG_A6XX_TEX_CONST_15 0x0000000f 7548 7549 #define REG_A6XX_UBO_0 0x00000000 7550 #define A6XX_UBO_0_BASE_LO__MASK 0xffffffff 7551 #define A6XX_UBO_0_BASE_LO__SHIFT 0 7552 static inline uint32_t A6XX_UBO_0_BASE_LO(uint32_t val) 7553 { 7554 return ((val) << A6XX_UBO_0_BASE_LO__SHIFT) & A6XX_UBO_0_BASE_LO__MASK; 7555 } 7556 7557 #define REG_A6XX_UBO_1 0x00000001 7558 #define A6XX_UBO_1_BASE_HI__MASK 0x0001ffff 7559 #define A6XX_UBO_1_BASE_HI__SHIFT 0 7560 static inline uint32_t A6XX_UBO_1_BASE_HI(uint32_t val) 7561 { 7562 return ((val) << A6XX_UBO_1_BASE_HI__SHIFT) & A6XX_UBO_1_BASE_HI__MASK; 7563 } 7564 #define A6XX_UBO_1_SIZE__MASK 0xfffe0000 7565 #define A6XX_UBO_1_SIZE__SHIFT 17 7566 static inline uint32_t A6XX_UBO_1_SIZE(uint32_t val) 7567 { 7568 return ((val) << A6XX_UBO_1_SIZE__SHIFT) & A6XX_UBO_1_SIZE__MASK; 7569 } 7570 7571 #define REG_A6XX_PDC_GPU_ENABLE_PDC 0x00001140 7572 7573 #define REG_A6XX_PDC_GPU_SEQ_START_ADDR 0x00001148 7574 7575 #define REG_A6XX_PDC_GPU_TCS0_CONTROL 0x00001540 7576 7577 #define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK 0x00001541 7578 7579 #define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK 0x00001542 7580 7581 #define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID 0x00001543 7582 7583 #define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR 0x00001544 7584 7585 #define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA 0x00001545 7586 7587 #define REG_A6XX_PDC_GPU_TCS1_CONTROL 0x00001572 7588 7589 #define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK 0x00001573 7590 7591 #define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK 0x00001574 7592 7593 #define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID 0x00001575 7594 7595 #define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR 0x00001576 7596 7597 #define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA 0x00001577 7598 7599 #define REG_A6XX_PDC_GPU_TCS2_CONTROL 0x000015a4 7600 7601 #define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK 0x000015a5 7602 7603 #define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK 0x000015a6 7604 7605 #define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID 0x000015a7 7606 7607 #define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR 0x000015a8 7608 7609 #define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA 0x000015a9 7610 7611 #define REG_A6XX_PDC_GPU_TCS3_CONTROL 0x000015d6 7612 7613 #define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK 0x000015d7 7614 7615 #define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK 0x000015d8 7616 7617 #define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID 0x000015d9 7618 7619 #define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR 0x000015da 7620 7621 #define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA 0x000015db 7622 7623 #define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x00000000 7624 7625 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A 0x00000000 7626 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK 0x000000ff 7627 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT 0 7628 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val) 7629 { 7630 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK; 7631 } 7632 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK 0x0000ff00 7633 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT 8 7634 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val) 7635 { 7636 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK; 7637 } 7638 7639 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B 0x00000001 7640 7641 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C 0x00000002 7642 7643 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D 0x00000003 7644 7645 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT 0x00000004 7646 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f 7647 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0 7648 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) 7649 { 7650 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; 7651 } 7652 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000 7653 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12 7654 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) 7655 { 7656 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; 7657 } 7658 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000 7659 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28 7660 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) 7661 { 7662 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; 7663 } 7664 7665 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM 0x00000005 7666 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000 7667 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24 7668 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) 7669 { 7670 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; 7671 } 7672 7673 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 0x00000008 7674 7675 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 0x00000009 7676 7677 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 0x0000000a 7678 7679 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 0x0000000b 7680 7681 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 0x0000000c 7682 7683 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 0x0000000d 7684 7685 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 0x0000000e 7686 7687 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 0x0000000f 7688 7689 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000010 7690 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f 7691 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0 7692 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) 7693 { 7694 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; 7695 } 7696 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0 7697 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4 7698 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) 7699 { 7700 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; 7701 } 7702 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00 7703 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8 7704 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) 7705 { 7706 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; 7707 } 7708 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000 7709 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12 7710 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) 7711 { 7712 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; 7713 } 7714 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000 7715 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16 7716 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) 7717 { 7718 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; 7719 } 7720 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000 7721 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20 7722 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) 7723 { 7724 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; 7725 } 7726 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000 7727 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24 7728 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) 7729 { 7730 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; 7731 } 7732 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000 7733 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28 7734 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) 7735 { 7736 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; 7737 } 7738 7739 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000011 7740 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f 7741 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0 7742 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) 7743 { 7744 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; 7745 } 7746 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0 7747 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4 7748 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) 7749 { 7750 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; 7751 } 7752 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00 7753 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8 7754 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) 7755 { 7756 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; 7757 } 7758 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000 7759 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12 7760 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) 7761 { 7762 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; 7763 } 7764 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000 7765 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16 7766 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) 7767 { 7768 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; 7769 } 7770 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000 7771 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20 7772 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) 7773 { 7774 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; 7775 } 7776 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000 7777 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24 7778 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) 7779 { 7780 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; 7781 } 7782 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000 7783 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28 7784 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) 7785 { 7786 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; 7787 } 7788 7789 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000002f 7790 7791 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000030 7792 7793 #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 0x00000001 7794 7795 #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 0x00000002 7796 7797 7798 #endif /* A6XX_XML */ 7799