1 #ifndef A6XX_XML
2 #define A6XX_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2023-03-10 18:32:52)
12 - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
13 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 91929 bytes, from 2023-02-28 23:52:27)
14 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from 2023-03-10 18:32:53)
15 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 74995 bytes, from 2023-03-20 18:06:23)
16 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2022-08-02 16:38:43)
17 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113474 bytes, from 2022-08-02 16:38:43)
18 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149590 bytes, from 2023-02-14 19:37:12)
19 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 198949 bytes, from 2023-03-20 18:06:23)
20 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11404 bytes, from 2023-03-10 18:32:53)
21 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2022-08-02 16:38:43)
22 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 9055 bytes, from 2023-03-10 18:32:52)
23 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2976 bytes, from 2023-03-10 18:32:52)
24
25 Copyright (C) 2013-2023 by the following authors:
26 - Rob Clark <robdclark@gmail.com> (robclark)
27 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
28
29 Permission is hereby granted, free of charge, to any person obtaining
30 a copy of this software and associated documentation files (the
31 "Software"), to deal in the Software without restriction, including
32 without limitation the rights to use, copy, modify, merge, publish,
33 distribute, sublicense, and/or sell copies of the Software, and to
34 permit persons to whom the Software is furnished to do so, subject to
35 the following conditions:
36
37 The above copyright notice and this permission notice (including the
38 next paragraph) shall be included in all copies or substantial
39 portions of the Software.
40
41 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
42 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
43 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
44 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
45 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
46 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
47 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
48 */
49
50
51 enum a6xx_tile_mode {
52 TILE6_LINEAR = 0,
53 TILE6_2 = 2,
54 TILE6_3 = 3,
55 };
56
57 enum a6xx_format {
58 FMT6_A8_UNORM = 2,
59 FMT6_8_UNORM = 3,
60 FMT6_8_SNORM = 4,
61 FMT6_8_UINT = 5,
62 FMT6_8_SINT = 6,
63 FMT6_4_4_4_4_UNORM = 8,
64 FMT6_5_5_5_1_UNORM = 10,
65 FMT6_1_5_5_5_UNORM = 12,
66 FMT6_5_6_5_UNORM = 14,
67 FMT6_8_8_UNORM = 15,
68 FMT6_8_8_SNORM = 16,
69 FMT6_8_8_UINT = 17,
70 FMT6_8_8_SINT = 18,
71 FMT6_L8_A8_UNORM = 19,
72 FMT6_16_UNORM = 21,
73 FMT6_16_SNORM = 22,
74 FMT6_16_FLOAT = 23,
75 FMT6_16_UINT = 24,
76 FMT6_16_SINT = 25,
77 FMT6_8_8_8_UNORM = 33,
78 FMT6_8_8_8_SNORM = 34,
79 FMT6_8_8_8_UINT = 35,
80 FMT6_8_8_8_SINT = 36,
81 FMT6_8_8_8_8_UNORM = 48,
82 FMT6_8_8_8_X8_UNORM = 49,
83 FMT6_8_8_8_8_SNORM = 50,
84 FMT6_8_8_8_8_UINT = 51,
85 FMT6_8_8_8_8_SINT = 52,
86 FMT6_9_9_9_E5_FLOAT = 53,
87 FMT6_10_10_10_2_UNORM = 54,
88 FMT6_10_10_10_2_UNORM_DEST = 55,
89 FMT6_10_10_10_2_SNORM = 57,
90 FMT6_10_10_10_2_UINT = 58,
91 FMT6_10_10_10_2_SINT = 59,
92 FMT6_11_11_10_FLOAT = 66,
93 FMT6_16_16_UNORM = 67,
94 FMT6_16_16_SNORM = 68,
95 FMT6_16_16_FLOAT = 69,
96 FMT6_16_16_UINT = 70,
97 FMT6_16_16_SINT = 71,
98 FMT6_32_UNORM = 72,
99 FMT6_32_SNORM = 73,
100 FMT6_32_FLOAT = 74,
101 FMT6_32_UINT = 75,
102 FMT6_32_SINT = 76,
103 FMT6_32_FIXED = 77,
104 FMT6_16_16_16_UNORM = 88,
105 FMT6_16_16_16_SNORM = 89,
106 FMT6_16_16_16_FLOAT = 90,
107 FMT6_16_16_16_UINT = 91,
108 FMT6_16_16_16_SINT = 92,
109 FMT6_16_16_16_16_UNORM = 96,
110 FMT6_16_16_16_16_SNORM = 97,
111 FMT6_16_16_16_16_FLOAT = 98,
112 FMT6_16_16_16_16_UINT = 99,
113 FMT6_16_16_16_16_SINT = 100,
114 FMT6_32_32_UNORM = 101,
115 FMT6_32_32_SNORM = 102,
116 FMT6_32_32_FLOAT = 103,
117 FMT6_32_32_UINT = 104,
118 FMT6_32_32_SINT = 105,
119 FMT6_32_32_FIXED = 106,
120 FMT6_32_32_32_UNORM = 112,
121 FMT6_32_32_32_SNORM = 113,
122 FMT6_32_32_32_UINT = 114,
123 FMT6_32_32_32_SINT = 115,
124 FMT6_32_32_32_FLOAT = 116,
125 FMT6_32_32_32_FIXED = 117,
126 FMT6_32_32_32_32_UNORM = 128,
127 FMT6_32_32_32_32_SNORM = 129,
128 FMT6_32_32_32_32_FLOAT = 130,
129 FMT6_32_32_32_32_UINT = 131,
130 FMT6_32_32_32_32_SINT = 132,
131 FMT6_32_32_32_32_FIXED = 133,
132 FMT6_G8R8B8R8_422_UNORM = 140,
133 FMT6_R8G8R8B8_422_UNORM = 141,
134 FMT6_R8_G8B8_2PLANE_420_UNORM = 142,
135 FMT6_NV21 = 143,
136 FMT6_R8_G8_B8_3PLANE_420_UNORM = 144,
137 FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 = 145,
138 FMT6_NV12_Y = 148,
139 FMT6_NV12_UV = 149,
140 FMT6_NV12_VU = 150,
141 FMT6_NV12_4R = 151,
142 FMT6_NV12_4R_Y = 152,
143 FMT6_NV12_4R_UV = 153,
144 FMT6_P010 = 154,
145 FMT6_P010_Y = 155,
146 FMT6_P010_UV = 156,
147 FMT6_TP10 = 157,
148 FMT6_TP10_Y = 158,
149 FMT6_TP10_UV = 159,
150 FMT6_Z24_UNORM_S8_UINT = 160,
151 FMT6_ETC2_RG11_UNORM = 171,
152 FMT6_ETC2_RG11_SNORM = 172,
153 FMT6_ETC2_R11_UNORM = 173,
154 FMT6_ETC2_R11_SNORM = 174,
155 FMT6_ETC1 = 175,
156 FMT6_ETC2_RGB8 = 176,
157 FMT6_ETC2_RGBA8 = 177,
158 FMT6_ETC2_RGB8A1 = 178,
159 FMT6_DXT1 = 179,
160 FMT6_DXT3 = 180,
161 FMT6_DXT5 = 181,
162 FMT6_RGTC1_UNORM = 183,
163 FMT6_RGTC1_SNORM = 184,
164 FMT6_RGTC2_UNORM = 187,
165 FMT6_RGTC2_SNORM = 188,
166 FMT6_BPTC_UFLOAT = 190,
167 FMT6_BPTC_FLOAT = 191,
168 FMT6_BPTC = 192,
169 FMT6_ASTC_4x4 = 193,
170 FMT6_ASTC_5x4 = 194,
171 FMT6_ASTC_5x5 = 195,
172 FMT6_ASTC_6x5 = 196,
173 FMT6_ASTC_6x6 = 197,
174 FMT6_ASTC_8x5 = 198,
175 FMT6_ASTC_8x6 = 199,
176 FMT6_ASTC_8x8 = 200,
177 FMT6_ASTC_10x5 = 201,
178 FMT6_ASTC_10x6 = 202,
179 FMT6_ASTC_10x8 = 203,
180 FMT6_ASTC_10x10 = 204,
181 FMT6_ASTC_12x10 = 205,
182 FMT6_ASTC_12x12 = 206,
183 FMT6_Z24_UINT_S8_UINT = 234,
184 FMT6_NONE = 255,
185 };
186
187 enum a6xx_polygon_mode {
188 POLYMODE6_POINTS = 1,
189 POLYMODE6_LINES = 2,
190 POLYMODE6_TRIANGLES = 3,
191 };
192
193 enum a6xx_depth_format {
194 DEPTH6_NONE = 0,
195 DEPTH6_16 = 1,
196 DEPTH6_24_8 = 2,
197 DEPTH6_32 = 4,
198 };
199
200 enum a6xx_shader_id {
201 A6XX_TP0_TMO_DATA = 9,
202 A6XX_TP0_SMO_DATA = 10,
203 A6XX_TP0_MIPMAP_BASE_DATA = 11,
204 A6XX_TP1_TMO_DATA = 25,
205 A6XX_TP1_SMO_DATA = 26,
206 A6XX_TP1_MIPMAP_BASE_DATA = 27,
207 A6XX_SP_INST_DATA = 41,
208 A6XX_SP_LB_0_DATA = 42,
209 A6XX_SP_LB_1_DATA = 43,
210 A6XX_SP_LB_2_DATA = 44,
211 A6XX_SP_LB_3_DATA = 45,
212 A6XX_SP_LB_4_DATA = 46,
213 A6XX_SP_LB_5_DATA = 47,
214 A6XX_SP_CB_BINDLESS_DATA = 48,
215 A6XX_SP_CB_LEGACY_DATA = 49,
216 A6XX_SP_UAV_DATA = 50,
217 A6XX_SP_INST_TAG = 51,
218 A6XX_SP_CB_BINDLESS_TAG = 52,
219 A6XX_SP_TMO_UMO_TAG = 53,
220 A6XX_SP_SMO_TAG = 54,
221 A6XX_SP_STATE_DATA = 55,
222 A6XX_HLSQ_CHUNK_CVS_RAM = 73,
223 A6XX_HLSQ_CHUNK_CPS_RAM = 74,
224 A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75,
225 A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76,
226 A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77,
227 A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78,
228 A6XX_HLSQ_CVS_MISC_RAM = 80,
229 A6XX_HLSQ_CPS_MISC_RAM = 81,
230 A6XX_HLSQ_INST_RAM = 82,
231 A6XX_HLSQ_GFX_CVS_CONST_RAM = 83,
232 A6XX_HLSQ_GFX_CPS_CONST_RAM = 84,
233 A6XX_HLSQ_CVS_MISC_RAM_TAG = 85,
234 A6XX_HLSQ_CPS_MISC_RAM_TAG = 86,
235 A6XX_HLSQ_INST_RAM_TAG = 87,
236 A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88,
237 A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89,
238 A6XX_HLSQ_PWR_REST_RAM = 90,
239 A6XX_HLSQ_PWR_REST_TAG = 91,
240 A6XX_HLSQ_DATAPATH_META = 96,
241 A6XX_HLSQ_FRONTEND_META = 97,
242 A6XX_HLSQ_INDIRECT_META = 98,
243 A6XX_HLSQ_BACKEND_META = 99,
244 A6XX_SP_LB_6_DATA = 112,
245 A6XX_SP_LB_7_DATA = 113,
246 A6XX_HLSQ_INST_RAM_1 = 115,
247 };
248
249 enum a6xx_debugbus_id {
250 A6XX_DBGBUS_CP = 1,
251 A6XX_DBGBUS_RBBM = 2,
252 A6XX_DBGBUS_VBIF = 3,
253 A6XX_DBGBUS_HLSQ = 4,
254 A6XX_DBGBUS_UCHE = 5,
255 A6XX_DBGBUS_DPM = 6,
256 A6XX_DBGBUS_TESS = 7,
257 A6XX_DBGBUS_PC = 8,
258 A6XX_DBGBUS_VFDP = 9,
259 A6XX_DBGBUS_VPC = 10,
260 A6XX_DBGBUS_TSE = 11,
261 A6XX_DBGBUS_RAS = 12,
262 A6XX_DBGBUS_VSC = 13,
263 A6XX_DBGBUS_COM = 14,
264 A6XX_DBGBUS_LRZ = 16,
265 A6XX_DBGBUS_A2D = 17,
266 A6XX_DBGBUS_CCUFCHE = 18,
267 A6XX_DBGBUS_GMU_CX = 19,
268 A6XX_DBGBUS_RBP = 20,
269 A6XX_DBGBUS_DCS = 21,
270 A6XX_DBGBUS_DBGC = 22,
271 A6XX_DBGBUS_CX = 23,
272 A6XX_DBGBUS_GMU_GX = 24,
273 A6XX_DBGBUS_TPFCHE = 25,
274 A6XX_DBGBUS_GBIF_GX = 26,
275 A6XX_DBGBUS_GPC = 29,
276 A6XX_DBGBUS_LARC = 30,
277 A6XX_DBGBUS_HLSQ_SPTP = 31,
278 A6XX_DBGBUS_RB_0 = 32,
279 A6XX_DBGBUS_RB_1 = 33,
280 A6XX_DBGBUS_RB_2 = 34,
281 A6XX_DBGBUS_UCHE_WRAPPER = 36,
282 A6XX_DBGBUS_CCU_0 = 40,
283 A6XX_DBGBUS_CCU_1 = 41,
284 A6XX_DBGBUS_CCU_2 = 42,
285 A6XX_DBGBUS_VFD_0 = 56,
286 A6XX_DBGBUS_VFD_1 = 57,
287 A6XX_DBGBUS_VFD_2 = 58,
288 A6XX_DBGBUS_VFD_3 = 59,
289 A6XX_DBGBUS_VFD_4 = 60,
290 A6XX_DBGBUS_VFD_5 = 61,
291 A6XX_DBGBUS_SP_0 = 64,
292 A6XX_DBGBUS_SP_1 = 65,
293 A6XX_DBGBUS_SP_2 = 66,
294 A6XX_DBGBUS_TPL1_0 = 72,
295 A6XX_DBGBUS_TPL1_1 = 73,
296 A6XX_DBGBUS_TPL1_2 = 74,
297 A6XX_DBGBUS_TPL1_3 = 75,
298 A6XX_DBGBUS_TPL1_4 = 76,
299 A6XX_DBGBUS_TPL1_5 = 77,
300 A6XX_DBGBUS_SPTP_0 = 88,
301 A6XX_DBGBUS_SPTP_1 = 89,
302 A6XX_DBGBUS_SPTP_2 = 90,
303 A6XX_DBGBUS_SPTP_3 = 91,
304 A6XX_DBGBUS_SPTP_4 = 92,
305 A6XX_DBGBUS_SPTP_5 = 93,
306 };
307
308 enum a6xx_cp_perfcounter_select {
309 PERF_CP_ALWAYS_COUNT = 0,
310 PERF_CP_BUSY_GFX_CORE_IDLE = 1,
311 PERF_CP_BUSY_CYCLES = 2,
312 PERF_CP_NUM_PREEMPTIONS = 3,
313 PERF_CP_PREEMPTION_REACTION_DELAY = 4,
314 PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 5,
315 PERF_CP_PREEMPTION_SWITCH_IN_TIME = 6,
316 PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 7,
317 PERF_CP_PREDICATED_DRAWS_KILLED = 8,
318 PERF_CP_MODE_SWITCH = 9,
319 PERF_CP_ZPASS_DONE = 10,
320 PERF_CP_CONTEXT_DONE = 11,
321 PERF_CP_CACHE_FLUSH = 12,
322 PERF_CP_LONG_PREEMPTIONS = 13,
323 PERF_CP_SQE_I_CACHE_STARVE = 14,
324 PERF_CP_SQE_IDLE = 15,
325 PERF_CP_SQE_PM4_STARVE_RB_IB = 16,
326 PERF_CP_SQE_PM4_STARVE_SDS = 17,
327 PERF_CP_SQE_MRB_STARVE = 18,
328 PERF_CP_SQE_RRB_STARVE = 19,
329 PERF_CP_SQE_VSD_STARVE = 20,
330 PERF_CP_VSD_DECODE_STARVE = 21,
331 PERF_CP_SQE_PIPE_OUT_STALL = 22,
332 PERF_CP_SQE_SYNC_STALL = 23,
333 PERF_CP_SQE_PM4_WFI_STALL = 24,
334 PERF_CP_SQE_SYS_WFI_STALL = 25,
335 PERF_CP_SQE_T4_EXEC = 26,
336 PERF_CP_SQE_LOAD_STATE_EXEC = 27,
337 PERF_CP_SQE_SAVE_SDS_STATE = 28,
338 PERF_CP_SQE_DRAW_EXEC = 29,
339 PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 30,
340 PERF_CP_SQE_EXEC_PROFILED = 31,
341 PERF_CP_MEMORY_POOL_EMPTY = 32,
342 PERF_CP_MEMORY_POOL_SYNC_STALL = 33,
343 PERF_CP_MEMORY_POOL_ABOVE_THRESH = 34,
344 PERF_CP_AHB_WR_STALL_PRE_DRAWS = 35,
345 PERF_CP_AHB_STALL_SQE_GMU = 36,
346 PERF_CP_AHB_STALL_SQE_WR_OTHER = 37,
347 PERF_CP_AHB_STALL_SQE_RD_OTHER = 38,
348 PERF_CP_CLUSTER0_EMPTY = 39,
349 PERF_CP_CLUSTER1_EMPTY = 40,
350 PERF_CP_CLUSTER2_EMPTY = 41,
351 PERF_CP_CLUSTER3_EMPTY = 42,
352 PERF_CP_CLUSTER4_EMPTY = 43,
353 PERF_CP_CLUSTER5_EMPTY = 44,
354 PERF_CP_PM4_DATA = 45,
355 PERF_CP_PM4_HEADERS = 46,
356 PERF_CP_VBIF_READ_BEATS = 47,
357 PERF_CP_VBIF_WRITE_BEATS = 48,
358 PERF_CP_SQE_INSTR_COUNTER = 49,
359 };
360
361 enum a6xx_rbbm_perfcounter_select {
362 PERF_RBBM_ALWAYS_COUNT = 0,
363 PERF_RBBM_ALWAYS_ON = 1,
364 PERF_RBBM_TSE_BUSY = 2,
365 PERF_RBBM_RAS_BUSY = 3,
366 PERF_RBBM_PC_DCALL_BUSY = 4,
367 PERF_RBBM_PC_VSD_BUSY = 5,
368 PERF_RBBM_STATUS_MASKED = 6,
369 PERF_RBBM_COM_BUSY = 7,
370 PERF_RBBM_DCOM_BUSY = 8,
371 PERF_RBBM_VBIF_BUSY = 9,
372 PERF_RBBM_VSC_BUSY = 10,
373 PERF_RBBM_TESS_BUSY = 11,
374 PERF_RBBM_UCHE_BUSY = 12,
375 PERF_RBBM_HLSQ_BUSY = 13,
376 };
377
378 enum a6xx_pc_perfcounter_select {
379 PERF_PC_BUSY_CYCLES = 0,
380 PERF_PC_WORKING_CYCLES = 1,
381 PERF_PC_STALL_CYCLES_VFD = 2,
382 PERF_PC_STALL_CYCLES_TSE = 3,
383 PERF_PC_STALL_CYCLES_VPC = 4,
384 PERF_PC_STALL_CYCLES_UCHE = 5,
385 PERF_PC_STALL_CYCLES_TESS = 6,
386 PERF_PC_STALL_CYCLES_TSE_ONLY = 7,
387 PERF_PC_STALL_CYCLES_VPC_ONLY = 8,
388 PERF_PC_PASS1_TF_STALL_CYCLES = 9,
389 PERF_PC_STARVE_CYCLES_FOR_INDEX = 10,
390 PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11,
391 PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12,
392 PERF_PC_STARVE_CYCLES_FOR_POSITION = 13,
393 PERF_PC_STARVE_CYCLES_DI = 14,
394 PERF_PC_VIS_STREAMS_LOADED = 15,
395 PERF_PC_INSTANCES = 16,
396 PERF_PC_VPC_PRIMITIVES = 17,
397 PERF_PC_DEAD_PRIM = 18,
398 PERF_PC_LIVE_PRIM = 19,
399 PERF_PC_VERTEX_HITS = 20,
400 PERF_PC_IA_VERTICES = 21,
401 PERF_PC_IA_PRIMITIVES = 22,
402 PERF_PC_GS_PRIMITIVES = 23,
403 PERF_PC_HS_INVOCATIONS = 24,
404 PERF_PC_DS_INVOCATIONS = 25,
405 PERF_PC_VS_INVOCATIONS = 26,
406 PERF_PC_GS_INVOCATIONS = 27,
407 PERF_PC_DS_PRIMITIVES = 28,
408 PERF_PC_VPC_POS_DATA_TRANSACTION = 29,
409 PERF_PC_3D_DRAWCALLS = 30,
410 PERF_PC_2D_DRAWCALLS = 31,
411 PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32,
412 PERF_TESS_BUSY_CYCLES = 33,
413 PERF_TESS_WORKING_CYCLES = 34,
414 PERF_TESS_STALL_CYCLES_PC = 35,
415 PERF_TESS_STARVE_CYCLES_PC = 36,
416 PERF_PC_TSE_TRANSACTION = 37,
417 PERF_PC_TSE_VERTEX = 38,
418 PERF_PC_TESS_PC_UV_TRANS = 39,
419 PERF_PC_TESS_PC_UV_PATCHES = 40,
420 PERF_PC_TESS_FACTOR_TRANS = 41,
421 };
422
423 enum a6xx_vfd_perfcounter_select {
424 PERF_VFD_BUSY_CYCLES = 0,
425 PERF_VFD_STALL_CYCLES_UCHE = 1,
426 PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2,
427 PERF_VFD_STALL_CYCLES_SP_INFO = 3,
428 PERF_VFD_STALL_CYCLES_SP_ATTR = 4,
429 PERF_VFD_STARVE_CYCLES_UCHE = 5,
430 PERF_VFD_RBUFFER_FULL = 6,
431 PERF_VFD_ATTR_INFO_FIFO_FULL = 7,
432 PERF_VFD_DECODED_ATTRIBUTE_BYTES = 8,
433 PERF_VFD_NUM_ATTRIBUTES = 9,
434 PERF_VFD_UPPER_SHADER_FIBERS = 10,
435 PERF_VFD_LOWER_SHADER_FIBERS = 11,
436 PERF_VFD_MODE_0_FIBERS = 12,
437 PERF_VFD_MODE_1_FIBERS = 13,
438 PERF_VFD_MODE_2_FIBERS = 14,
439 PERF_VFD_MODE_3_FIBERS = 15,
440 PERF_VFD_MODE_4_FIBERS = 16,
441 PERF_VFD_TOTAL_VERTICES = 17,
442 PERF_VFDP_STALL_CYCLES_VFD = 18,
443 PERF_VFDP_STALL_CYCLES_VFD_INDEX = 19,
444 PERF_VFDP_STALL_CYCLES_VFD_PROG = 20,
445 PERF_VFDP_STARVE_CYCLES_PC = 21,
446 PERF_VFDP_VS_STAGE_WAVES = 22,
447 };
448
449 enum a6xx_hlsq_perfcounter_select {
450 PERF_HLSQ_BUSY_CYCLES = 0,
451 PERF_HLSQ_STALL_CYCLES_UCHE = 1,
452 PERF_HLSQ_STALL_CYCLES_SP_STATE = 2,
453 PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3,
454 PERF_HLSQ_UCHE_LATENCY_CYCLES = 4,
455 PERF_HLSQ_UCHE_LATENCY_COUNT = 5,
456 PERF_HLSQ_FS_STAGE_1X_WAVES = 6,
457 PERF_HLSQ_FS_STAGE_2X_WAVES = 7,
458 PERF_HLSQ_QUADS = 8,
459 PERF_HLSQ_CS_INVOCATIONS = 9,
460 PERF_HLSQ_COMPUTE_DRAWCALLS = 10,
461 PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11,
462 PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12,
463 PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13,
464 PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14,
465 PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15,
466 PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16,
467 PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17,
468 PERF_HLSQ_STALL_CYCLES_VPC = 18,
469 PERF_HLSQ_PIXELS = 19,
470 PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = 20,
471 };
472
473 enum a6xx_vpc_perfcounter_select {
474 PERF_VPC_BUSY_CYCLES = 0,
475 PERF_VPC_WORKING_CYCLES = 1,
476 PERF_VPC_STALL_CYCLES_UCHE = 2,
477 PERF_VPC_STALL_CYCLES_VFD_WACK = 3,
478 PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4,
479 PERF_VPC_STALL_CYCLES_PC = 5,
480 PERF_VPC_STALL_CYCLES_SP_LM = 6,
481 PERF_VPC_STARVE_CYCLES_SP = 7,
482 PERF_VPC_STARVE_CYCLES_LRZ = 8,
483 PERF_VPC_PC_PRIMITIVES = 9,
484 PERF_VPC_SP_COMPONENTS = 10,
485 PERF_VPC_STALL_CYCLES_VPCRAM_POS = 11,
486 PERF_VPC_LRZ_ASSIGN_PRIMITIVES = 12,
487 PERF_VPC_RB_VISIBLE_PRIMITIVES = 13,
488 PERF_VPC_LM_TRANSACTION = 14,
489 PERF_VPC_STREAMOUT_TRANSACTION = 15,
490 PERF_VPC_VS_BUSY_CYCLES = 16,
491 PERF_VPC_PS_BUSY_CYCLES = 17,
492 PERF_VPC_VS_WORKING_CYCLES = 18,
493 PERF_VPC_PS_WORKING_CYCLES = 19,
494 PERF_VPC_STARVE_CYCLES_RB = 20,
495 PERF_VPC_NUM_VPCRAM_READ_POS = 21,
496 PERF_VPC_WIT_FULL_CYCLES = 22,
497 PERF_VPC_VPCRAM_FULL_CYCLES = 23,
498 PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = 24,
499 PERF_VPC_NUM_VPCRAM_WRITE = 25,
500 PERF_VPC_NUM_VPCRAM_READ_SO = 26,
501 PERF_VPC_NUM_ATTR_REQ_LM = 27,
502 };
503
504 enum a6xx_tse_perfcounter_select {
505 PERF_TSE_BUSY_CYCLES = 0,
506 PERF_TSE_CLIPPING_CYCLES = 1,
507 PERF_TSE_STALL_CYCLES_RAS = 2,
508 PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3,
509 PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4,
510 PERF_TSE_STARVE_CYCLES_PC = 5,
511 PERF_TSE_INPUT_PRIM = 6,
512 PERF_TSE_INPUT_NULL_PRIM = 7,
513 PERF_TSE_TRIVAL_REJ_PRIM = 8,
514 PERF_TSE_CLIPPED_PRIM = 9,
515 PERF_TSE_ZERO_AREA_PRIM = 10,
516 PERF_TSE_FACENESS_CULLED_PRIM = 11,
517 PERF_TSE_ZERO_PIXEL_PRIM = 12,
518 PERF_TSE_OUTPUT_NULL_PRIM = 13,
519 PERF_TSE_OUTPUT_VISIBLE_PRIM = 14,
520 PERF_TSE_CINVOCATION = 15,
521 PERF_TSE_CPRIMITIVES = 16,
522 PERF_TSE_2D_INPUT_PRIM = 17,
523 PERF_TSE_2D_ALIVE_CYCLES = 18,
524 PERF_TSE_CLIP_PLANES = 19,
525 };
526
527 enum a6xx_ras_perfcounter_select {
528 PERF_RAS_BUSY_CYCLES = 0,
529 PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1,
530 PERF_RAS_STALL_CYCLES_LRZ = 2,
531 PERF_RAS_STARVE_CYCLES_TSE = 3,
532 PERF_RAS_SUPER_TILES = 4,
533 PERF_RAS_8X4_TILES = 5,
534 PERF_RAS_MASKGEN_ACTIVE = 6,
535 PERF_RAS_FULLY_COVERED_SUPER_TILES = 7,
536 PERF_RAS_FULLY_COVERED_8X4_TILES = 8,
537 PERF_RAS_PRIM_KILLED_INVISILBE = 9,
538 PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 10,
539 PERF_RAS_LRZ_INTF_WORKING_CYCLES = 11,
540 PERF_RAS_BLOCKS = 12,
541 };
542
543 enum a6xx_uche_perfcounter_select {
544 PERF_UCHE_BUSY_CYCLES = 0,
545 PERF_UCHE_STALL_CYCLES_ARBITER = 1,
546 PERF_UCHE_VBIF_LATENCY_CYCLES = 2,
547 PERF_UCHE_VBIF_LATENCY_SAMPLES = 3,
548 PERF_UCHE_VBIF_READ_BEATS_TP = 4,
549 PERF_UCHE_VBIF_READ_BEATS_VFD = 5,
550 PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6,
551 PERF_UCHE_VBIF_READ_BEATS_LRZ = 7,
552 PERF_UCHE_VBIF_READ_BEATS_SP = 8,
553 PERF_UCHE_READ_REQUESTS_TP = 9,
554 PERF_UCHE_READ_REQUESTS_VFD = 10,
555 PERF_UCHE_READ_REQUESTS_HLSQ = 11,
556 PERF_UCHE_READ_REQUESTS_LRZ = 12,
557 PERF_UCHE_READ_REQUESTS_SP = 13,
558 PERF_UCHE_WRITE_REQUESTS_LRZ = 14,
559 PERF_UCHE_WRITE_REQUESTS_SP = 15,
560 PERF_UCHE_WRITE_REQUESTS_VPC = 16,
561 PERF_UCHE_WRITE_REQUESTS_VSC = 17,
562 PERF_UCHE_EVICTS = 18,
563 PERF_UCHE_BANK_REQ0 = 19,
564 PERF_UCHE_BANK_REQ1 = 20,
565 PERF_UCHE_BANK_REQ2 = 21,
566 PERF_UCHE_BANK_REQ3 = 22,
567 PERF_UCHE_BANK_REQ4 = 23,
568 PERF_UCHE_BANK_REQ5 = 24,
569 PERF_UCHE_BANK_REQ6 = 25,
570 PERF_UCHE_BANK_REQ7 = 26,
571 PERF_UCHE_VBIF_READ_BEATS_CH0 = 27,
572 PERF_UCHE_VBIF_READ_BEATS_CH1 = 28,
573 PERF_UCHE_GMEM_READ_BEATS = 29,
574 PERF_UCHE_TPH_REF_FULL = 30,
575 PERF_UCHE_TPH_VICTIM_FULL = 31,
576 PERF_UCHE_TPH_EXT_FULL = 32,
577 PERF_UCHE_VBIF_STALL_WRITE_DATA = 33,
578 PERF_UCHE_DCMP_LATENCY_SAMPLES = 34,
579 PERF_UCHE_DCMP_LATENCY_CYCLES = 35,
580 PERF_UCHE_VBIF_READ_BEATS_PC = 36,
581 PERF_UCHE_READ_REQUESTS_PC = 37,
582 PERF_UCHE_RAM_READ_REQ = 38,
583 PERF_UCHE_RAM_WRITE_REQ = 39,
584 };
585
586 enum a6xx_tp_perfcounter_select {
587 PERF_TP_BUSY_CYCLES = 0,
588 PERF_TP_STALL_CYCLES_UCHE = 1,
589 PERF_TP_LATENCY_CYCLES = 2,
590 PERF_TP_LATENCY_TRANS = 3,
591 PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4,
592 PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5,
593 PERF_TP_L1_CACHELINE_REQUESTS = 6,
594 PERF_TP_L1_CACHELINE_MISSES = 7,
595 PERF_TP_SP_TP_TRANS = 8,
596 PERF_TP_TP_SP_TRANS = 9,
597 PERF_TP_OUTPUT_PIXELS = 10,
598 PERF_TP_FILTER_WORKLOAD_16BIT = 11,
599 PERF_TP_FILTER_WORKLOAD_32BIT = 12,
600 PERF_TP_QUADS_RECEIVED = 13,
601 PERF_TP_QUADS_OFFSET = 14,
602 PERF_TP_QUADS_SHADOW = 15,
603 PERF_TP_QUADS_ARRAY = 16,
604 PERF_TP_QUADS_GRADIENT = 17,
605 PERF_TP_QUADS_1D = 18,
606 PERF_TP_QUADS_2D = 19,
607 PERF_TP_QUADS_BUFFER = 20,
608 PERF_TP_QUADS_3D = 21,
609 PERF_TP_QUADS_CUBE = 22,
610 PERF_TP_DIVERGENT_QUADS_RECEIVED = 23,
611 PERF_TP_PRT_NON_RESIDENT_EVENTS = 24,
612 PERF_TP_OUTPUT_PIXELS_POINT = 25,
613 PERF_TP_OUTPUT_PIXELS_BILINEAR = 26,
614 PERF_TP_OUTPUT_PIXELS_MIP = 27,
615 PERF_TP_OUTPUT_PIXELS_ANISO = 28,
616 PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 29,
617 PERF_TP_FLAG_CACHE_REQUESTS = 30,
618 PERF_TP_FLAG_CACHE_MISSES = 31,
619 PERF_TP_L1_5_L2_REQUESTS = 32,
620 PERF_TP_2D_OUTPUT_PIXELS = 33,
621 PERF_TP_2D_OUTPUT_PIXELS_POINT = 34,
622 PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 35,
623 PERF_TP_2D_FILTER_WORKLOAD_16BIT = 36,
624 PERF_TP_2D_FILTER_WORKLOAD_32BIT = 37,
625 PERF_TP_TPA2TPC_TRANS = 38,
626 PERF_TP_L1_MISSES_ASTC_1TILE = 39,
627 PERF_TP_L1_MISSES_ASTC_2TILE = 40,
628 PERF_TP_L1_MISSES_ASTC_4TILE = 41,
629 PERF_TP_L1_5_L2_COMPRESS_REQS = 42,
630 PERF_TP_L1_5_L2_COMPRESS_MISS = 43,
631 PERF_TP_L1_BANK_CONFLICT = 44,
632 PERF_TP_L1_5_MISS_LATENCY_CYCLES = 45,
633 PERF_TP_L1_5_MISS_LATENCY_TRANS = 46,
634 PERF_TP_QUADS_CONSTANT_MULTIPLIED = 47,
635 PERF_TP_FRONTEND_WORKING_CYCLES = 48,
636 PERF_TP_L1_TAG_WORKING_CYCLES = 49,
637 PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 50,
638 PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 51,
639 PERF_TP_BACKEND_WORKING_CYCLES = 52,
640 PERF_TP_FLAG_CACHE_WORKING_CYCLES = 53,
641 PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54,
642 PERF_TP_STARVE_CYCLES_SP = 55,
643 PERF_TP_STARVE_CYCLES_UCHE = 56,
644 };
645
646 enum a6xx_sp_perfcounter_select {
647 PERF_SP_BUSY_CYCLES = 0,
648 PERF_SP_ALU_WORKING_CYCLES = 1,
649 PERF_SP_EFU_WORKING_CYCLES = 2,
650 PERF_SP_STALL_CYCLES_VPC = 3,
651 PERF_SP_STALL_CYCLES_TP = 4,
652 PERF_SP_STALL_CYCLES_UCHE = 5,
653 PERF_SP_STALL_CYCLES_RB = 6,
654 PERF_SP_NON_EXECUTION_CYCLES = 7,
655 PERF_SP_WAVE_CONTEXTS = 8,
656 PERF_SP_WAVE_CONTEXT_CYCLES = 9,
657 PERF_SP_FS_STAGE_WAVE_CYCLES = 10,
658 PERF_SP_FS_STAGE_WAVE_SAMPLES = 11,
659 PERF_SP_VS_STAGE_WAVE_CYCLES = 12,
660 PERF_SP_VS_STAGE_WAVE_SAMPLES = 13,
661 PERF_SP_FS_STAGE_DURATION_CYCLES = 14,
662 PERF_SP_VS_STAGE_DURATION_CYCLES = 15,
663 PERF_SP_WAVE_CTRL_CYCLES = 16,
664 PERF_SP_WAVE_LOAD_CYCLES = 17,
665 PERF_SP_WAVE_EMIT_CYCLES = 18,
666 PERF_SP_WAVE_NOP_CYCLES = 19,
667 PERF_SP_WAVE_WAIT_CYCLES = 20,
668 PERF_SP_WAVE_FETCH_CYCLES = 21,
669 PERF_SP_WAVE_IDLE_CYCLES = 22,
670 PERF_SP_WAVE_END_CYCLES = 23,
671 PERF_SP_WAVE_LONG_SYNC_CYCLES = 24,
672 PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25,
673 PERF_SP_WAVE_JOIN_CYCLES = 26,
674 PERF_SP_LM_LOAD_INSTRUCTIONS = 27,
675 PERF_SP_LM_STORE_INSTRUCTIONS = 28,
676 PERF_SP_LM_ATOMICS = 29,
677 PERF_SP_GM_LOAD_INSTRUCTIONS = 30,
678 PERF_SP_GM_STORE_INSTRUCTIONS = 31,
679 PERF_SP_GM_ATOMICS = 32,
680 PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33,
681 PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34,
682 PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35,
683 PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36,
684 PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37,
685 PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38,
686 PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39,
687 PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40,
688 PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41,
689 PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42,
690 PERF_SP_VS_INSTRUCTIONS = 43,
691 PERF_SP_FS_INSTRUCTIONS = 44,
692 PERF_SP_ADDR_LOCK_COUNT = 45,
693 PERF_SP_UCHE_READ_TRANS = 46,
694 PERF_SP_UCHE_WRITE_TRANS = 47,
695 PERF_SP_EXPORT_VPC_TRANS = 48,
696 PERF_SP_EXPORT_RB_TRANS = 49,
697 PERF_SP_PIXELS_KILLED = 50,
698 PERF_SP_ICL1_REQUESTS = 51,
699 PERF_SP_ICL1_MISSES = 52,
700 PERF_SP_HS_INSTRUCTIONS = 53,
701 PERF_SP_DS_INSTRUCTIONS = 54,
702 PERF_SP_GS_INSTRUCTIONS = 55,
703 PERF_SP_CS_INSTRUCTIONS = 56,
704 PERF_SP_GPR_READ = 57,
705 PERF_SP_GPR_WRITE = 58,
706 PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59,
707 PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60,
708 PERF_SP_LM_BANK_CONFLICTS = 61,
709 PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62,
710 PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63,
711 PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64,
712 PERF_SP_LM_WORKING_CYCLES = 65,
713 PERF_SP_DISPATCHER_WORKING_CYCLES = 66,
714 PERF_SP_SEQUENCER_WORKING_CYCLES = 67,
715 PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68,
716 PERF_SP_STARVE_CYCLES_HLSQ = 69,
717 PERF_SP_NON_EXECUTION_LS_CYCLES = 70,
718 PERF_SP_WORKING_EU = 71,
719 PERF_SP_ANY_EU_WORKING = 72,
720 PERF_SP_WORKING_EU_FS_STAGE = 73,
721 PERF_SP_ANY_EU_WORKING_FS_STAGE = 74,
722 PERF_SP_WORKING_EU_VS_STAGE = 75,
723 PERF_SP_ANY_EU_WORKING_VS_STAGE = 76,
724 PERF_SP_WORKING_EU_CS_STAGE = 77,
725 PERF_SP_ANY_EU_WORKING_CS_STAGE = 78,
726 PERF_SP_GPR_READ_PREFETCH = 79,
727 PERF_SP_GPR_READ_CONFLICT = 80,
728 PERF_SP_GPR_WRITE_CONFLICT = 81,
729 PERF_SP_GM_LOAD_LATENCY_CYCLES = 82,
730 PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83,
731 PERF_SP_EXECUTABLE_WAVES = 84,
732 };
733
734 enum a6xx_rb_perfcounter_select {
735 PERF_RB_BUSY_CYCLES = 0,
736 PERF_RB_STALL_CYCLES_HLSQ = 1,
737 PERF_RB_STALL_CYCLES_FIFO0_FULL = 2,
738 PERF_RB_STALL_CYCLES_FIFO1_FULL = 3,
739 PERF_RB_STALL_CYCLES_FIFO2_FULL = 4,
740 PERF_RB_STARVE_CYCLES_SP = 5,
741 PERF_RB_STARVE_CYCLES_LRZ_TILE = 6,
742 PERF_RB_STARVE_CYCLES_CCU = 7,
743 PERF_RB_STARVE_CYCLES_Z_PLANE = 8,
744 PERF_RB_STARVE_CYCLES_BARY_PLANE = 9,
745 PERF_RB_Z_WORKLOAD = 10,
746 PERF_RB_HLSQ_ACTIVE = 11,
747 PERF_RB_Z_READ = 12,
748 PERF_RB_Z_WRITE = 13,
749 PERF_RB_C_READ = 14,
750 PERF_RB_C_WRITE = 15,
751 PERF_RB_TOTAL_PASS = 16,
752 PERF_RB_Z_PASS = 17,
753 PERF_RB_Z_FAIL = 18,
754 PERF_RB_S_FAIL = 19,
755 PERF_RB_BLENDED_FXP_COMPONENTS = 20,
756 PERF_RB_BLENDED_FP16_COMPONENTS = 21,
757 PERF_RB_PS_INVOCATIONS = 22,
758 PERF_RB_2D_ALIVE_CYCLES = 23,
759 PERF_RB_2D_STALL_CYCLES_A2D = 24,
760 PERF_RB_2D_STARVE_CYCLES_SRC = 25,
761 PERF_RB_2D_STARVE_CYCLES_SP = 26,
762 PERF_RB_2D_STARVE_CYCLES_DST = 27,
763 PERF_RB_2D_VALID_PIXELS = 28,
764 PERF_RB_3D_PIXELS = 29,
765 PERF_RB_BLENDER_WORKING_CYCLES = 30,
766 PERF_RB_ZPROC_WORKING_CYCLES = 31,
767 PERF_RB_CPROC_WORKING_CYCLES = 32,
768 PERF_RB_SAMPLER_WORKING_CYCLES = 33,
769 PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 34,
770 PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 35,
771 PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 36,
772 PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 37,
773 PERF_RB_STALL_CYCLES_VPC = 38,
774 PERF_RB_2D_INPUT_TRANS = 39,
775 PERF_RB_2D_OUTPUT_RB_DST_TRANS = 40,
776 PERF_RB_2D_OUTPUT_RB_SRC_TRANS = 41,
777 PERF_RB_BLENDED_FP32_COMPONENTS = 42,
778 PERF_RB_COLOR_PIX_TILES = 43,
779 PERF_RB_STALL_CYCLES_CCU = 44,
780 PERF_RB_EARLY_Z_ARB3_GRANT = 45,
781 PERF_RB_LATE_Z_ARB3_GRANT = 46,
782 PERF_RB_EARLY_Z_SKIP_GRANT = 47,
783 };
784
785 enum a6xx_vsc_perfcounter_select {
786 PERF_VSC_BUSY_CYCLES = 0,
787 PERF_VSC_WORKING_CYCLES = 1,
788 PERF_VSC_STALL_CYCLES_UCHE = 2,
789 PERF_VSC_EOT_NUM = 3,
790 PERF_VSC_INPUT_TILES = 4,
791 };
792
793 enum a6xx_ccu_perfcounter_select {
794 PERF_CCU_BUSY_CYCLES = 0,
795 PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1,
796 PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2,
797 PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3,
798 PERF_CCU_DEPTH_BLOCKS = 4,
799 PERF_CCU_COLOR_BLOCKS = 5,
800 PERF_CCU_DEPTH_BLOCK_HIT = 6,
801 PERF_CCU_COLOR_BLOCK_HIT = 7,
802 PERF_CCU_PARTIAL_BLOCK_READ = 8,
803 PERF_CCU_GMEM_READ = 9,
804 PERF_CCU_GMEM_WRITE = 10,
805 PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11,
806 PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12,
807 PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13,
808 PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14,
809 PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15,
810 PERF_CCU_DEPTH_READ_FLAG5_COUNT = 16,
811 PERF_CCU_DEPTH_READ_FLAG6_COUNT = 17,
812 PERF_CCU_DEPTH_READ_FLAG8_COUNT = 18,
813 PERF_CCU_COLOR_READ_FLAG0_COUNT = 19,
814 PERF_CCU_COLOR_READ_FLAG1_COUNT = 20,
815 PERF_CCU_COLOR_READ_FLAG2_COUNT = 21,
816 PERF_CCU_COLOR_READ_FLAG3_COUNT = 22,
817 PERF_CCU_COLOR_READ_FLAG4_COUNT = 23,
818 PERF_CCU_COLOR_READ_FLAG5_COUNT = 24,
819 PERF_CCU_COLOR_READ_FLAG6_COUNT = 25,
820 PERF_CCU_COLOR_READ_FLAG8_COUNT = 26,
821 PERF_CCU_2D_RD_REQ = 27,
822 PERF_CCU_2D_WR_REQ = 28,
823 };
824
825 enum a6xx_lrz_perfcounter_select {
826 PERF_LRZ_BUSY_CYCLES = 0,
827 PERF_LRZ_STARVE_CYCLES_RAS = 1,
828 PERF_LRZ_STALL_CYCLES_RB = 2,
829 PERF_LRZ_STALL_CYCLES_VSC = 3,
830 PERF_LRZ_STALL_CYCLES_VPC = 4,
831 PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5,
832 PERF_LRZ_STALL_CYCLES_UCHE = 6,
833 PERF_LRZ_LRZ_READ = 7,
834 PERF_LRZ_LRZ_WRITE = 8,
835 PERF_LRZ_READ_LATENCY = 9,
836 PERF_LRZ_MERGE_CACHE_UPDATING = 10,
837 PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11,
838 PERF_LRZ_PRIM_KILLED_BY_LRZ = 12,
839 PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13,
840 PERF_LRZ_FULL_8X8_TILES = 14,
841 PERF_LRZ_PARTIAL_8X8_TILES = 15,
842 PERF_LRZ_TILE_KILLED = 16,
843 PERF_LRZ_TOTAL_PIXEL = 17,
844 PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18,
845 PERF_LRZ_FULLY_COVERED_TILES = 19,
846 PERF_LRZ_PARTIAL_COVERED_TILES = 20,
847 PERF_LRZ_FEEDBACK_ACCEPT = 21,
848 PERF_LRZ_FEEDBACK_DISCARD = 22,
849 PERF_LRZ_FEEDBACK_STALL = 23,
850 PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 24,
851 PERF_LRZ_STALL_CYCLES_RB_BPLANE = 25,
852 PERF_LRZ_STALL_CYCLES_VC = 26,
853 PERF_LRZ_RAS_MASK_TRANS = 27,
854 };
855
856 enum a6xx_cmp_perfcounter_select {
857 PERF_CMPDECMP_STALL_CYCLES_ARB = 0,
858 PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1,
859 PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2,
860 PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3,
861 PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4,
862 PERF_CMPDECMP_VBIF_READ_REQUEST = 5,
863 PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6,
864 PERF_CMPDECMP_VBIF_READ_DATA = 7,
865 PERF_CMPDECMP_VBIF_WRITE_DATA = 8,
866 PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9,
867 PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10,
868 PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11,
869 PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12,
870 PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13,
871 PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14,
872 PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 15,
873 PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 16,
874 PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 17,
875 PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 18,
876 PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 19,
877 PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 20,
878 PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 21,
879 PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 22,
880 PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 23,
881 PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 24,
882 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 25,
883 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 26,
884 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 27,
885 PERF_CMPDECMP_2D_RD_DATA = 28,
886 PERF_CMPDECMP_2D_WR_DATA = 29,
887 PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 30,
888 PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 31,
889 PERF_CMPDECMP_2D_OUTPUT_TRANS = 32,
890 PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 33,
891 PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 34,
892 PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 35,
893 PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 36,
894 PERF_CMPDECMP_2D_BUSY_CYCLES = 37,
895 PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = 38,
896 PERF_CMPDECMP_2D_PIXELS = 39,
897 };
898
899 enum a6xx_2d_ifmt {
900 R2D_UNORM8 = 16,
901 R2D_INT32 = 7,
902 R2D_INT16 = 6,
903 R2D_INT8 = 5,
904 R2D_FLOAT32 = 4,
905 R2D_FLOAT16 = 3,
906 R2D_UNORM8_SRGB = 1,
907 R2D_RAW = 0,
908 };
909
910 enum a6xx_ztest_mode {
911 A6XX_EARLY_Z = 0,
912 A6XX_LATE_Z = 1,
913 A6XX_EARLY_LRZ_LATE_Z = 2,
914 A6XX_INVALID_ZTEST = 3,
915 };
916
917 enum a6xx_sequenced_thread_dist {
918 DIST_SCREEN_COORD = 0,
919 DIST_ALL_TO_RB0 = 1,
920 };
921
922 enum a6xx_single_prim_mode {
923 NO_FLUSH = 0,
924 FLUSH_PER_OVERLAP_AND_OVERWRITE = 1,
925 FLUSH_PER_OVERLAP = 3,
926 };
927
928 enum a6xx_raster_mode {
929 TYPE_TILED = 0,
930 TYPE_WRITER = 1,
931 };
932
933 enum a6xx_raster_direction {
934 LR_TB = 0,
935 RL_TB = 1,
936 LR_BT = 2,
937 RB_BT = 3,
938 };
939
940 enum a6xx_render_mode {
941 RENDERING_PASS = 0,
942 BINNING_PASS = 1,
943 };
944
945 enum a6xx_buffers_location {
946 BUFFERS_IN_GMEM = 0,
947 BUFFERS_IN_SYSMEM = 3,
948 };
949
950 enum a6xx_lrz_dir_status {
951 LRZ_DIR_LE = 1,
952 LRZ_DIR_GE = 2,
953 LRZ_DIR_INVALID = 3,
954 };
955
956 enum a6xx_fragcoord_sample_mode {
957 FRAGCOORD_CENTER = 0,
958 FRAGCOORD_SAMPLE = 3,
959 };
960
961 enum a6xx_rotation {
962 ROTATE_0 = 0,
963 ROTATE_90 = 1,
964 ROTATE_180 = 2,
965 ROTATE_270 = 3,
966 ROTATE_HFLIP = 4,
967 ROTATE_VFLIP = 5,
968 };
969
970 enum a6xx_tess_spacing {
971 TESS_EQUAL = 0,
972 TESS_FRACTIONAL_ODD = 2,
973 TESS_FRACTIONAL_EVEN = 3,
974 };
975
976 enum a6xx_tess_output {
977 TESS_POINTS = 0,
978 TESS_LINES = 1,
979 TESS_CW_TRIS = 2,
980 TESS_CCW_TRIS = 3,
981 };
982
983 enum a6xx_threadsize {
984 THREAD64 = 0,
985 THREAD128 = 1,
986 };
987
988 enum a6xx_bindless_descriptor_size {
989 BINDLESS_DESCRIPTOR_16B = 1,
990 BINDLESS_DESCRIPTOR_64B = 3,
991 };
992
993 enum a6xx_isam_mode {
994 ISAMMODE_GL = 2,
995 };
996
997 enum a6xx_tex_filter {
998 A6XX_TEX_NEAREST = 0,
999 A6XX_TEX_LINEAR = 1,
1000 A6XX_TEX_ANISO = 2,
1001 A6XX_TEX_CUBIC = 3,
1002 };
1003
1004 enum a6xx_tex_clamp {
1005 A6XX_TEX_REPEAT = 0,
1006 A6XX_TEX_CLAMP_TO_EDGE = 1,
1007 A6XX_TEX_MIRROR_REPEAT = 2,
1008 A6XX_TEX_CLAMP_TO_BORDER = 3,
1009 A6XX_TEX_MIRROR_CLAMP = 4,
1010 };
1011
1012 enum a6xx_tex_aniso {
1013 A6XX_TEX_ANISO_1 = 0,
1014 A6XX_TEX_ANISO_2 = 1,
1015 A6XX_TEX_ANISO_4 = 2,
1016 A6XX_TEX_ANISO_8 = 3,
1017 A6XX_TEX_ANISO_16 = 4,
1018 };
1019
1020 enum a6xx_reduction_mode {
1021 A6XX_REDUCTION_MODE_AVERAGE = 0,
1022 A6XX_REDUCTION_MODE_MIN = 1,
1023 A6XX_REDUCTION_MODE_MAX = 2,
1024 };
1025
1026 enum a6xx_tex_swiz {
1027 A6XX_TEX_X = 0,
1028 A6XX_TEX_Y = 1,
1029 A6XX_TEX_Z = 2,
1030 A6XX_TEX_W = 3,
1031 A6XX_TEX_ZERO = 4,
1032 A6XX_TEX_ONE = 5,
1033 };
1034
1035 enum a6xx_tex_type {
1036 A6XX_TEX_1D = 0,
1037 A6XX_TEX_2D = 1,
1038 A6XX_TEX_CUBE = 2,
1039 A6XX_TEX_3D = 3,
1040 A6XX_TEX_BUFFER = 4,
1041 };
1042
1043 #define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001
1044 #define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR 0x00000002
1045 #define A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_0 0x00000010
1046 #define A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_1 0x00000020
1047 #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW 0x00000040
1048 #define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080
1049 #define A6XX_RBBM_INT_0_MASK_CP_SW 0x00000100
1050 #define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200
1051 #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400
1052 #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800
1053 #define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000
1054 #define A6XX_RBBM_INT_0_MASK_CP_IB2 0x00002000
1055 #define A6XX_RBBM_INT_0_MASK_CP_IB1 0x00004000
1056 #define A6XX_RBBM_INT_0_MASK_CP_RB 0x00008000
1057 #define A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPT 0x00008000
1058 #define A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPTLPAC 0x00010000
1059 #define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000
1060 #define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000
1061 #define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000
1062 #define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS_LPAC 0x00200000
1063 #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000
1064 #define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT 0x00800000
1065 #define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000
1066 #define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000
1067 #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000
1068 #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000
1069 #define A6XX_RBBM_INT_0_MASK_TSBWRITEERROR 0x10000000
1070 #define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000
1071 #define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000
1072 #define A6XX_CP_INT_CP_OPCODE_ERROR 0x00000001
1073 #define A6XX_CP_INT_CP_UCODE_ERROR 0x00000002
1074 #define A6XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004
1075 #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010
1076 #define A6XX_CP_INT_CP_AHB_ERROR 0x00000020
1077 #define A6XX_CP_INT_CP_VSD_PARITY_ERROR 0x00000040
1078 #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR 0x00000080
1079 #define A6XX_CP_INT_CP_OPCODE_ERROR_LPAC 0x00000100
1080 #define A6XX_CP_INT_CP_UCODE_ERROR_LPAC 0x00000200
1081 #define A6XX_CP_INT_CP_HW_FAULT_ERROR_LPAC 0x00000400
1082 #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_LPAC 0x00000800
1083 #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_LPAC 0x00001000
1084 #define A6XX_CP_INT_CP_OPCODE_ERROR_BV 0x00002000
1085 #define A6XX_CP_INT_CP_UCODE_ERROR_BV 0x00004000
1086 #define A6XX_CP_INT_CP_HW_FAULT_ERROR_BV 0x00008000
1087 #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_BV 0x00010000
1088 #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_BV 0x00020000
1089 #define REG_A6XX_CP_RB_BASE 0x00000800
1090
1091 #define REG_A6XX_CP_RB_CNTL 0x00000802
1092
1093 #define REG_A6XX_CP_RB_RPTR_ADDR 0x00000804
1094
1095 #define REG_A6XX_CP_RB_RPTR 0x00000806
1096
1097 #define REG_A6XX_CP_RB_WPTR 0x00000807
1098
1099 #define REG_A6XX_CP_SQE_CNTL 0x00000808
1100
1101 #define REG_A6XX_CP_CP2GMU_STATUS 0x00000812
1102 #define A6XX_CP_CP2GMU_STATUS_IFPC 0x00000001
1103
1104 #define REG_A6XX_CP_HW_FAULT 0x00000821
1105
1106 #define REG_A6XX_CP_INTERRUPT_STATUS 0x00000823
1107
1108 #define REG_A6XX_CP_PROTECT_STATUS 0x00000824
1109
1110 #define REG_A6XX_CP_STATUS_1 0x00000825
1111
1112 #define REG_A6XX_CP_SQE_INSTR_BASE 0x00000830
1113
1114 #define REG_A6XX_CP_MISC_CNTL 0x00000840
1115
1116 #define REG_A6XX_CP_APRIV_CNTL 0x00000844
1117
1118 #define REG_A6XX_CP_PREEMPT_THRESHOLD 0x000008c0
1119
1120 #define REG_A6XX_CP_ROQ_THRESHOLDS_1 0x000008c1
1121 #define A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK 0x000000ff
1122 #define A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT 0
A6XX_CP_ROQ_THRESHOLDS_1_MRB_START(uint32_t val)1123 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_MRB_START(uint32_t val)
1124 {
1125 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK;
1126 }
1127 #define A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK 0x0000ff00
1128 #define A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT 8
A6XX_CP_ROQ_THRESHOLDS_1_VSD_START(uint32_t val)1129 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_VSD_START(uint32_t val)
1130 {
1131 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK;
1132 }
1133 #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK 0x00ff0000
1134 #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT 16
A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val)1135 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val)
1136 {
1137 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK;
1138 }
1139 #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK 0xff000000
1140 #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT 24
A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val)1141 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val)
1142 {
1143 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK;
1144 }
1145
1146 #define REG_A6XX_CP_ROQ_THRESHOLDS_2 0x000008c2
1147 #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK 0x000001ff
1148 #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT 0
A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val)1149 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val)
1150 {
1151 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK;
1152 }
1153 #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK 0xffff0000
1154 #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT 16
A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val)1155 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val)
1156 {
1157 return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK;
1158 }
1159
1160 #define REG_A6XX_CP_MEM_POOL_SIZE 0x000008c3
1161
1162 #define REG_A6XX_CP_CHICKEN_DBG 0x00000841
1163
1164 #define REG_A6XX_CP_ADDR_MODE_CNTL 0x00000842
1165
1166 #define REG_A6XX_CP_DBG_ECO_CNTL 0x00000843
1167
1168 #define REG_A6XX_CP_PROTECT_CNTL 0x0000084f
1169 #define A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE 0x00000008
1170 #define A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN 0x00000002
1171 #define A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN 0x00000001
1172
REG_A6XX_CP_SCRATCH(uint32_t i0)1173 static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; }
1174
REG_A6XX_CP_SCRATCH_REG(uint32_t i0)1175 static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; }
1176
REG_A6XX_CP_PROTECT(uint32_t i0)1177 static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; }
1178
REG_A6XX_CP_PROTECT_REG(uint32_t i0)1179 static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; }
1180 #define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0003ffff
1181 #define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0
A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)1182 static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
1183 {
1184 return ((val) << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK;
1185 }
1186 #define A6XX_CP_PROTECT_REG_MASK_LEN__MASK 0x7ffc0000
1187 #define A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT 18
A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)1188 static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
1189 {
1190 return ((val) << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK;
1191 }
1192 #define A6XX_CP_PROTECT_REG_READ 0x80000000
1193
1194 #define REG_A6XX_CP_CONTEXT_SWITCH_CNTL 0x000008a0
1195
1196 #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO 0x000008a1
1197
1198 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR 0x000008a3
1199
1200 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR 0x000008a5
1201
1202 #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR 0x000008a7
1203
1204 #define REG_A7XX_CP_CONTEXT_SWITCH_LEVEL_STATUS 0x000008ab
1205
REG_A6XX_CP_PERFCTR_CP_SEL(uint32_t i0)1206 static inline uint32_t REG_A6XX_CP_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008d0 + 0x1*i0; }
1207
REG_A7XX_CP_BV_PERFCTR_CP_SEL(uint32_t i0)1208 static inline uint32_t REG_A7XX_CP_BV_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008e0 + 0x1*i0; }
1209
1210 #define REG_A6XX_CP_CRASH_SCRIPT_BASE 0x00000900
1211
1212 #define REG_A6XX_CP_CRASH_DUMP_CNTL 0x00000902
1213
1214 #define REG_A6XX_CP_CRASH_DUMP_STATUS 0x00000903
1215
1216 #define REG_A6XX_CP_SQE_STAT_ADDR 0x00000908
1217
1218 #define REG_A6XX_CP_SQE_STAT_DATA 0x00000909
1219
1220 #define REG_A6XX_CP_DRAW_STATE_ADDR 0x0000090a
1221
1222 #define REG_A6XX_CP_DRAW_STATE_DATA 0x0000090b
1223
1224 #define REG_A6XX_CP_ROQ_DBG_ADDR 0x0000090c
1225
1226 #define REG_A6XX_CP_ROQ_DBG_DATA 0x0000090d
1227
1228 #define REG_A6XX_CP_MEM_POOL_DBG_ADDR 0x0000090e
1229
1230 #define REG_A6XX_CP_MEM_POOL_DBG_DATA 0x0000090f
1231
1232 #define REG_A6XX_CP_SQE_UCODE_DBG_ADDR 0x00000910
1233
1234 #define REG_A6XX_CP_SQE_UCODE_DBG_DATA 0x00000911
1235
1236 #define REG_A6XX_CP_IB1_BASE 0x00000928
1237
1238 #define REG_A6XX_CP_IB1_REM_SIZE 0x0000092a
1239
1240 #define REG_A6XX_CP_IB2_BASE 0x0000092b
1241
1242 #define REG_A6XX_CP_IB2_REM_SIZE 0x0000092d
1243
1244 #define REG_A6XX_CP_SDS_BASE 0x0000092e
1245
1246 #define REG_A6XX_CP_SDS_REM_SIZE 0x00000930
1247
1248 #define REG_A6XX_CP_MRB_BASE 0x00000931
1249
1250 #define REG_A6XX_CP_MRB_REM_SIZE 0x00000933
1251
1252 #define REG_A6XX_CP_VSD_BASE 0x00000934
1253
1254 #define REG_A6XX_CP_ROQ_RB_STAT 0x00000939
1255 #define A6XX_CP_ROQ_RB_STAT_RPTR__MASK 0x000003ff
1256 #define A6XX_CP_ROQ_RB_STAT_RPTR__SHIFT 0
A6XX_CP_ROQ_RB_STAT_RPTR(uint32_t val)1257 static inline uint32_t A6XX_CP_ROQ_RB_STAT_RPTR(uint32_t val)
1258 {
1259 return ((val) << A6XX_CP_ROQ_RB_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_RB_STAT_RPTR__MASK;
1260 }
1261 #define A6XX_CP_ROQ_RB_STAT_WPTR__MASK 0x03ff0000
1262 #define A6XX_CP_ROQ_RB_STAT_WPTR__SHIFT 16
A6XX_CP_ROQ_RB_STAT_WPTR(uint32_t val)1263 static inline uint32_t A6XX_CP_ROQ_RB_STAT_WPTR(uint32_t val)
1264 {
1265 return ((val) << A6XX_CP_ROQ_RB_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_RB_STAT_WPTR__MASK;
1266 }
1267
1268 #define REG_A6XX_CP_ROQ_IB1_STAT 0x0000093a
1269 #define A6XX_CP_ROQ_IB1_STAT_RPTR__MASK 0x000003ff
1270 #define A6XX_CP_ROQ_IB1_STAT_RPTR__SHIFT 0
A6XX_CP_ROQ_IB1_STAT_RPTR(uint32_t val)1271 static inline uint32_t A6XX_CP_ROQ_IB1_STAT_RPTR(uint32_t val)
1272 {
1273 return ((val) << A6XX_CP_ROQ_IB1_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_IB1_STAT_RPTR__MASK;
1274 }
1275 #define A6XX_CP_ROQ_IB1_STAT_WPTR__MASK 0x03ff0000
1276 #define A6XX_CP_ROQ_IB1_STAT_WPTR__SHIFT 16
A6XX_CP_ROQ_IB1_STAT_WPTR(uint32_t val)1277 static inline uint32_t A6XX_CP_ROQ_IB1_STAT_WPTR(uint32_t val)
1278 {
1279 return ((val) << A6XX_CP_ROQ_IB1_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_IB1_STAT_WPTR__MASK;
1280 }
1281
1282 #define REG_A6XX_CP_ROQ_IB2_STAT 0x0000093b
1283 #define A6XX_CP_ROQ_IB2_STAT_RPTR__MASK 0x000003ff
1284 #define A6XX_CP_ROQ_IB2_STAT_RPTR__SHIFT 0
A6XX_CP_ROQ_IB2_STAT_RPTR(uint32_t val)1285 static inline uint32_t A6XX_CP_ROQ_IB2_STAT_RPTR(uint32_t val)
1286 {
1287 return ((val) << A6XX_CP_ROQ_IB2_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_IB2_STAT_RPTR__MASK;
1288 }
1289 #define A6XX_CP_ROQ_IB2_STAT_WPTR__MASK 0x03ff0000
1290 #define A6XX_CP_ROQ_IB2_STAT_WPTR__SHIFT 16
A6XX_CP_ROQ_IB2_STAT_WPTR(uint32_t val)1291 static inline uint32_t A6XX_CP_ROQ_IB2_STAT_WPTR(uint32_t val)
1292 {
1293 return ((val) << A6XX_CP_ROQ_IB2_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_IB2_STAT_WPTR__MASK;
1294 }
1295
1296 #define REG_A6XX_CP_ROQ_SDS_STAT 0x0000093c
1297 #define A6XX_CP_ROQ_SDS_STAT_RPTR__MASK 0x000003ff
1298 #define A6XX_CP_ROQ_SDS_STAT_RPTR__SHIFT 0
A6XX_CP_ROQ_SDS_STAT_RPTR(uint32_t val)1299 static inline uint32_t A6XX_CP_ROQ_SDS_STAT_RPTR(uint32_t val)
1300 {
1301 return ((val) << A6XX_CP_ROQ_SDS_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_SDS_STAT_RPTR__MASK;
1302 }
1303 #define A6XX_CP_ROQ_SDS_STAT_WPTR__MASK 0x03ff0000
1304 #define A6XX_CP_ROQ_SDS_STAT_WPTR__SHIFT 16
A6XX_CP_ROQ_SDS_STAT_WPTR(uint32_t val)1305 static inline uint32_t A6XX_CP_ROQ_SDS_STAT_WPTR(uint32_t val)
1306 {
1307 return ((val) << A6XX_CP_ROQ_SDS_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_SDS_STAT_WPTR__MASK;
1308 }
1309
1310 #define REG_A6XX_CP_ROQ_MRB_STAT 0x0000093d
1311 #define A6XX_CP_ROQ_MRB_STAT_RPTR__MASK 0x000003ff
1312 #define A6XX_CP_ROQ_MRB_STAT_RPTR__SHIFT 0
A6XX_CP_ROQ_MRB_STAT_RPTR(uint32_t val)1313 static inline uint32_t A6XX_CP_ROQ_MRB_STAT_RPTR(uint32_t val)
1314 {
1315 return ((val) << A6XX_CP_ROQ_MRB_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_MRB_STAT_RPTR__MASK;
1316 }
1317 #define A6XX_CP_ROQ_MRB_STAT_WPTR__MASK 0x03ff0000
1318 #define A6XX_CP_ROQ_MRB_STAT_WPTR__SHIFT 16
A6XX_CP_ROQ_MRB_STAT_WPTR(uint32_t val)1319 static inline uint32_t A6XX_CP_ROQ_MRB_STAT_WPTR(uint32_t val)
1320 {
1321 return ((val) << A6XX_CP_ROQ_MRB_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_MRB_STAT_WPTR__MASK;
1322 }
1323
1324 #define REG_A6XX_CP_ROQ_VSD_STAT 0x0000093e
1325 #define A6XX_CP_ROQ_VSD_STAT_RPTR__MASK 0x000003ff
1326 #define A6XX_CP_ROQ_VSD_STAT_RPTR__SHIFT 0
A6XX_CP_ROQ_VSD_STAT_RPTR(uint32_t val)1327 static inline uint32_t A6XX_CP_ROQ_VSD_STAT_RPTR(uint32_t val)
1328 {
1329 return ((val) << A6XX_CP_ROQ_VSD_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_VSD_STAT_RPTR__MASK;
1330 }
1331 #define A6XX_CP_ROQ_VSD_STAT_WPTR__MASK 0x03ff0000
1332 #define A6XX_CP_ROQ_VSD_STAT_WPTR__SHIFT 16
A6XX_CP_ROQ_VSD_STAT_WPTR(uint32_t val)1333 static inline uint32_t A6XX_CP_ROQ_VSD_STAT_WPTR(uint32_t val)
1334 {
1335 return ((val) << A6XX_CP_ROQ_VSD_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_VSD_STAT_WPTR__MASK;
1336 }
1337
1338 #define REG_A6XX_CP_IB1_DWORDS 0x00000943
1339
1340 #define REG_A6XX_CP_IB2_DWORDS 0x00000944
1341
1342 #define REG_A6XX_CP_SDS_DWORDS 0x00000945
1343
1344 #define REG_A6XX_CP_MRB_DWORDS 0x00000946
1345
1346 #define REG_A6XX_CP_VSD_DWORDS 0x00000947
1347
1348 #define REG_A6XX_CP_ROQ_AVAIL_RB 0x00000948
1349 #define A6XX_CP_ROQ_AVAIL_RB_REM__MASK 0xffff0000
1350 #define A6XX_CP_ROQ_AVAIL_RB_REM__SHIFT 16
A6XX_CP_ROQ_AVAIL_RB_REM(uint32_t val)1351 static inline uint32_t A6XX_CP_ROQ_AVAIL_RB_REM(uint32_t val)
1352 {
1353 return ((val) << A6XX_CP_ROQ_AVAIL_RB_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_RB_REM__MASK;
1354 }
1355
1356 #define REG_A6XX_CP_ROQ_AVAIL_IB1 0x00000949
1357 #define A6XX_CP_ROQ_AVAIL_IB1_REM__MASK 0xffff0000
1358 #define A6XX_CP_ROQ_AVAIL_IB1_REM__SHIFT 16
A6XX_CP_ROQ_AVAIL_IB1_REM(uint32_t val)1359 static inline uint32_t A6XX_CP_ROQ_AVAIL_IB1_REM(uint32_t val)
1360 {
1361 return ((val) << A6XX_CP_ROQ_AVAIL_IB1_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_IB1_REM__MASK;
1362 }
1363
1364 #define REG_A6XX_CP_ROQ_AVAIL_IB2 0x0000094a
1365 #define A6XX_CP_ROQ_AVAIL_IB2_REM__MASK 0xffff0000
1366 #define A6XX_CP_ROQ_AVAIL_IB2_REM__SHIFT 16
A6XX_CP_ROQ_AVAIL_IB2_REM(uint32_t val)1367 static inline uint32_t A6XX_CP_ROQ_AVAIL_IB2_REM(uint32_t val)
1368 {
1369 return ((val) << A6XX_CP_ROQ_AVAIL_IB2_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_IB2_REM__MASK;
1370 }
1371
1372 #define REG_A6XX_CP_ROQ_AVAIL_SDS 0x0000094b
1373 #define A6XX_CP_ROQ_AVAIL_SDS_REM__MASK 0xffff0000
1374 #define A6XX_CP_ROQ_AVAIL_SDS_REM__SHIFT 16
A6XX_CP_ROQ_AVAIL_SDS_REM(uint32_t val)1375 static inline uint32_t A6XX_CP_ROQ_AVAIL_SDS_REM(uint32_t val)
1376 {
1377 return ((val) << A6XX_CP_ROQ_AVAIL_SDS_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_SDS_REM__MASK;
1378 }
1379
1380 #define REG_A6XX_CP_ROQ_AVAIL_MRB 0x0000094c
1381 #define A6XX_CP_ROQ_AVAIL_MRB_REM__MASK 0xffff0000
1382 #define A6XX_CP_ROQ_AVAIL_MRB_REM__SHIFT 16
A6XX_CP_ROQ_AVAIL_MRB_REM(uint32_t val)1383 static inline uint32_t A6XX_CP_ROQ_AVAIL_MRB_REM(uint32_t val)
1384 {
1385 return ((val) << A6XX_CP_ROQ_AVAIL_MRB_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_MRB_REM__MASK;
1386 }
1387
1388 #define REG_A6XX_CP_ROQ_AVAIL_VSD 0x0000094d
1389 #define A6XX_CP_ROQ_AVAIL_VSD_REM__MASK 0xffff0000
1390 #define A6XX_CP_ROQ_AVAIL_VSD_REM__SHIFT 16
A6XX_CP_ROQ_AVAIL_VSD_REM(uint32_t val)1391 static inline uint32_t A6XX_CP_ROQ_AVAIL_VSD_REM(uint32_t val)
1392 {
1393 return ((val) << A6XX_CP_ROQ_AVAIL_VSD_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_VSD_REM__MASK;
1394 }
1395
1396 #define REG_A6XX_CP_ALWAYS_ON_COUNTER 0x00000980
1397
1398 #define REG_A6XX_CP_AHB_CNTL 0x0000098d
1399
1400 #define REG_A6XX_CP_APERTURE_CNTL_HOST 0x00000a00
1401
1402 #define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03
1403
1404 #define REG_A7XX_CP_BV_PROTECT_STATUS 0x00000a61
1405
1406 #define REG_A7XX_CP_BV_HW_FAULT 0x00000a64
1407
1408 #define REG_A7XX_CP_BV_DRAW_STATE_ADDR 0x00000a81
1409
1410 #define REG_A7XX_CP_BV_DRAW_STATE_DATA 0x00000a82
1411
1412 #define REG_A7XX_CP_BV_ROQ_DBG_ADDR 0x00000a83
1413
1414 #define REG_A7XX_CP_BV_ROQ_DBG_DATA 0x00000a84
1415
1416 #define REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR 0x00000a85
1417
1418 #define REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA 0x00000a86
1419
1420 #define REG_A7XX_CP_BV_SQE_STAT_ADDR 0x00000a87
1421
1422 #define REG_A7XX_CP_BV_SQE_STAT_DATA 0x00000a88
1423
1424 #define REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR 0x00000a96
1425
1426 #define REG_A7XX_CP_BV_MEM_POOL_DBG_DATA 0x00000a97
1427
1428 #define REG_A7XX_CP_BV_RB_RPTR_ADDR 0x00000a98
1429
1430 #define REG_A7XX_CP_RESOURCE_TBL_DBG_ADDR 0x00000a9a
1431
1432 #define REG_A7XX_CP_RESOURCE_TBL_DBG_DATA 0x00000a9b
1433
1434 #define REG_A7XX_CP_BV_APRIV_CNTL 0x00000ad0
1435
1436 #define REG_A7XX_CP_BV_CHICKEN_DBG 0x00000ada
1437
1438 #define REG_A7XX_CP_LPAC_DRAW_STATE_ADDR 0x00000b0a
1439
1440 #define REG_A7XX_CP_LPAC_DRAW_STATE_DATA 0x00000b0b
1441
1442 #define REG_A7XX_CP_LPAC_ROQ_DBG_ADDR 0x00000b0c
1443
1444 #define REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR 0x00000b27
1445
1446 #define REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA 0x00000b28
1447
1448 #define REG_A7XX_CP_SQE_AC_STAT_ADDR 0x00000b29
1449
1450 #define REG_A7XX_CP_SQE_AC_STAT_DATA 0x00000b2a
1451
1452 #define REG_A7XX_CP_LPAC_APRIV_CNTL 0x00000b31
1453
1454 #define REG_A6XX_CP_LPAC_PROG_FIFO_SIZE 0x00000b34
1455
1456 #define REG_A7XX_CP_LPAC_ROQ_DBG_DATA 0x00000b35
1457
1458 #define REG_A7XX_CP_LPAC_FIFO_DBG_DATA 0x00000b36
1459
1460 #define REG_A7XX_CP_LPAC_FIFO_DBG_ADDR 0x00000b40
1461
1462 #define REG_A6XX_CP_LPAC_SQE_INSTR_BASE 0x00000b82
1463
1464 #define REG_A6XX_VSC_ADDR_MODE_CNTL 0x00000c01
1465
1466 #define REG_A6XX_RBBM_GPR0_CNTL 0x00000018
1467
1468 #define REG_A6XX_RBBM_INT_0_STATUS 0x00000201
1469
1470 #define REG_A6XX_RBBM_STATUS 0x00000210
1471 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x00800000
1472 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x00400000
1473 #define A6XX_RBBM_STATUS_HLSQ_BUSY 0x00200000
1474 #define A6XX_RBBM_STATUS_VSC_BUSY 0x00100000
1475 #define A6XX_RBBM_STATUS_TPL1_BUSY 0x00080000
1476 #define A6XX_RBBM_STATUS_SP_BUSY 0x00040000
1477 #define A6XX_RBBM_STATUS_UCHE_BUSY 0x00020000
1478 #define A6XX_RBBM_STATUS_VPC_BUSY 0x00010000
1479 #define A6XX_RBBM_STATUS_VFD_BUSY 0x00008000
1480 #define A6XX_RBBM_STATUS_TESS_BUSY 0x00004000
1481 #define A6XX_RBBM_STATUS_PC_VSD_BUSY 0x00002000
1482 #define A6XX_RBBM_STATUS_PC_DCALL_BUSY 0x00001000
1483 #define A6XX_RBBM_STATUS_COM_DCOM_BUSY 0x00000800
1484 #define A6XX_RBBM_STATUS_LRZ_BUSY 0x00000400
1485 #define A6XX_RBBM_STATUS_A2D_BUSY 0x00000200
1486 #define A6XX_RBBM_STATUS_CCU_BUSY 0x00000100
1487 #define A6XX_RBBM_STATUS_RB_BUSY 0x00000080
1488 #define A6XX_RBBM_STATUS_RAS_BUSY 0x00000040
1489 #define A6XX_RBBM_STATUS_TSE_BUSY 0x00000020
1490 #define A6XX_RBBM_STATUS_VBIF_BUSY 0x00000010
1491 #define A6XX_RBBM_STATUS_GFX_DBGC_BUSY 0x00000008
1492 #define A6XX_RBBM_STATUS_CP_BUSY 0x00000004
1493 #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER 0x00000002
1494 #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER 0x00000001
1495
1496 #define REG_A6XX_RBBM_STATUS1 0x00000211
1497
1498 #define REG_A6XX_RBBM_STATUS2 0x00000212
1499
1500 #define REG_A6XX_RBBM_STATUS3 0x00000213
1501 #define A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT 0x01000000
1502
1503 #define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215
1504
1505 #define REG_A7XX_RBBM_CLOCK_MODE_CP 0x00000260
1506
1507 #define REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ 0x00000284
1508
1509 #define REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS 0x00000285
1510
1511 #define REG_A7XX_RBBM_CLOCK_MODE2_GRAS 0x00000286
1512
1513 #define REG_A7XX_RBBM_CLOCK_MODE_BV_VFD 0x00000287
1514
1515 #define REG_A7XX_RBBM_CLOCK_MODE_BV_GPC 0x00000288
1516
REG_A6XX_RBBM_PERFCTR_CP(uint32_t i0)1517 static inline uint32_t REG_A6XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000400 + 0x2*i0; }
1518
REG_A6XX_RBBM_PERFCTR_RBBM(uint32_t i0)1519 static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000041c + 0x2*i0; }
1520
REG_A6XX_RBBM_PERFCTR_PC(uint32_t i0)1521 static inline uint32_t REG_A6XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000424 + 0x2*i0; }
1522
REG_A6XX_RBBM_PERFCTR_VFD(uint32_t i0)1523 static inline uint32_t REG_A6XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000434 + 0x2*i0; }
1524
REG_A6XX_RBBM_PERFCTR_HLSQ(uint32_t i0)1525 static inline uint32_t REG_A6XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000444 + 0x2*i0; }
1526
REG_A6XX_RBBM_PERFCTR_VPC(uint32_t i0)1527 static inline uint32_t REG_A6XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000450 + 0x2*i0; }
1528
REG_A6XX_RBBM_PERFCTR_CCU(uint32_t i0)1529 static inline uint32_t REG_A6XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000045c + 0x2*i0; }
1530
REG_A6XX_RBBM_PERFCTR_TSE(uint32_t i0)1531 static inline uint32_t REG_A6XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000466 + 0x2*i0; }
1532
REG_A6XX_RBBM_PERFCTR_RAS(uint32_t i0)1533 static inline uint32_t REG_A6XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000046e + 0x2*i0; }
1534
REG_A6XX_RBBM_PERFCTR_UCHE(uint32_t i0)1535 static inline uint32_t REG_A6XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000476 + 0x2*i0; }
1536
REG_A6XX_RBBM_PERFCTR_TP(uint32_t i0)1537 static inline uint32_t REG_A6XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000048e + 0x2*i0; }
1538
REG_A6XX_RBBM_PERFCTR_SP(uint32_t i0)1539 static inline uint32_t REG_A6XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000004a6 + 0x2*i0; }
1540
REG_A6XX_RBBM_PERFCTR_RB(uint32_t i0)1541 static inline uint32_t REG_A6XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000004d6 + 0x2*i0; }
1542
REG_A6XX_RBBM_PERFCTR_VSC(uint32_t i0)1543 static inline uint32_t REG_A6XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000004e6 + 0x2*i0; }
1544
REG_A6XX_RBBM_PERFCTR_LRZ(uint32_t i0)1545 static inline uint32_t REG_A6XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000004ea + 0x2*i0; }
1546
REG_A6XX_RBBM_PERFCTR_CMP(uint32_t i0)1547 static inline uint32_t REG_A6XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000004f2 + 0x2*i0; }
1548
REG_A7XX_RBBM_PERFCTR_CP(uint32_t i0)1549 static inline uint32_t REG_A7XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000300 + 0x2*i0; }
1550
REG_A7XX_RBBM_PERFCTR_RBBM(uint32_t i0)1551 static inline uint32_t REG_A7XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000031c + 0x2*i0; }
1552
REG_A7XX_RBBM_PERFCTR_PC(uint32_t i0)1553 static inline uint32_t REG_A7XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000324 + 0x2*i0; }
1554
REG_A7XX_RBBM_PERFCTR_VFD(uint32_t i0)1555 static inline uint32_t REG_A7XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000334 + 0x2*i0; }
1556
REG_A7XX_RBBM_PERFCTR_HLSQ(uint32_t i0)1557 static inline uint32_t REG_A7XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000344 + 0x2*i0; }
1558
REG_A7XX_RBBM_PERFCTR_VPC(uint32_t i0)1559 static inline uint32_t REG_A7XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000350 + 0x2*i0; }
1560
REG_A7XX_RBBM_PERFCTR_CCU(uint32_t i0)1561 static inline uint32_t REG_A7XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000035c + 0x2*i0; }
1562
REG_A7XX_RBBM_PERFCTR_TSE(uint32_t i0)1563 static inline uint32_t REG_A7XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000366 + 0x2*i0; }
1564
REG_A7XX_RBBM_PERFCTR_RAS(uint32_t i0)1565 static inline uint32_t REG_A7XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000036e + 0x2*i0; }
1566
REG_A7XX_RBBM_PERFCTR_UCHE(uint32_t i0)1567 static inline uint32_t REG_A7XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000376 + 0x2*i0; }
1568
REG_A7XX_RBBM_PERFCTR_TP(uint32_t i0)1569 static inline uint32_t REG_A7XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000038e + 0x2*i0; }
1570
REG_A7XX_RBBM_PERFCTR_SP(uint32_t i0)1571 static inline uint32_t REG_A7XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000003a6 + 0x2*i0; }
1572
REG_A7XX_RBBM_PERFCTR_RB(uint32_t i0)1573 static inline uint32_t REG_A7XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000003d6 + 0x2*i0; }
1574
REG_A7XX_RBBM_PERFCTR_VSC(uint32_t i0)1575 static inline uint32_t REG_A7XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000003e6 + 0x2*i0; }
1576
REG_A7XX_RBBM_PERFCTR_LRZ(uint32_t i0)1577 static inline uint32_t REG_A7XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000003ea + 0x2*i0; }
1578
REG_A7XX_RBBM_PERFCTR_CMP(uint32_t i0)1579 static inline uint32_t REG_A7XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000003f2 + 0x2*i0; }
1580
REG_A7XX_RBBM_PERFCTR_UFC(uint32_t i0)1581 static inline uint32_t REG_A7XX_RBBM_PERFCTR_UFC(uint32_t i0) { return 0x000003fa + 0x2*i0; }
1582
REG_A7XX_RBBM_PERFCTR2_HLSQ(uint32_t i0)1583 static inline uint32_t REG_A7XX_RBBM_PERFCTR2_HLSQ(uint32_t i0) { return 0x00000410 + 0x2*i0; }
1584
REG_A7XX_RBBM_PERFCTR2_CP(uint32_t i0)1585 static inline uint32_t REG_A7XX_RBBM_PERFCTR2_CP(uint32_t i0) { return 0x0000041c + 0x2*i0; }
1586
REG_A7XX_RBBM_PERFCTR2_SP(uint32_t i0)1587 static inline uint32_t REG_A7XX_RBBM_PERFCTR2_SP(uint32_t i0) { return 0x0000042a + 0x2*i0; }
1588
REG_A7XX_RBBM_PERFCTR2_TP(uint32_t i0)1589 static inline uint32_t REG_A7XX_RBBM_PERFCTR2_TP(uint32_t i0) { return 0x00000442 + 0x2*i0; }
1590
REG_A7XX_RBBM_PERFCTR2_UFC(uint32_t i0)1591 static inline uint32_t REG_A7XX_RBBM_PERFCTR2_UFC(uint32_t i0) { return 0x0000044e + 0x2*i0; }
1592
REG_A7XX_RBBM_PERFCTR_BV_PC(uint32_t i0)1593 static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_PC(uint32_t i0) { return 0x00000460 + 0x2*i0; }
1594
REG_A7XX_RBBM_PERFCTR_BV_VFD(uint32_t i0)1595 static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_VFD(uint32_t i0) { return 0x00000470 + 0x2*i0; }
1596
REG_A7XX_RBBM_PERFCTR_BV_VPC(uint32_t i0)1597 static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_VPC(uint32_t i0) { return 0x00000480 + 0x2*i0; }
1598
REG_A7XX_RBBM_PERFCTR_BV_TSE(uint32_t i0)1599 static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_TSE(uint32_t i0) { return 0x0000048c + 0x2*i0; }
1600
REG_A7XX_RBBM_PERFCTR_BV_RAS(uint32_t i0)1601 static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_RAS(uint32_t i0) { return 0x00000494 + 0x2*i0; }
1602
REG_A7XX_RBBM_PERFCTR_BV_LRZ(uint32_t i0)1603 static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_LRZ(uint32_t i0) { return 0x0000049c + 0x2*i0; }
1604
1605 #define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500
1606
1607 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 0x00000501
1608
1609 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 0x00000502
1610
1611 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 0x00000503
1612
1613 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 0x00000504
1614
1615 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000505
1616
1617 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506
1618
REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0)1619 static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00000507 + 0x1*i0; }
1620
1621 #define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b
1622
1623 #define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD 0x0000050e
1624
1625 #define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS 0x0000050f
1626
1627 #define REG_A6XX_RBBM_ISDB_CNT 0x00000533
1628
1629 #define REG_A7XX_RBBM_NC_MODE_CNTL 0x00000534
1630
1631 #define REG_A7XX_RBBM_SNAPSHOT_STATUS 0x00000535
1632
1633 #define REG_A6XX_RBBM_PRIMCTR_0_LO 0x00000540
1634
1635 #define REG_A6XX_RBBM_PRIMCTR_0_HI 0x00000541
1636
1637 #define REG_A6XX_RBBM_PRIMCTR_1_LO 0x00000542
1638
1639 #define REG_A6XX_RBBM_PRIMCTR_1_HI 0x00000543
1640
1641 #define REG_A6XX_RBBM_PRIMCTR_2_LO 0x00000544
1642
1643 #define REG_A6XX_RBBM_PRIMCTR_2_HI 0x00000545
1644
1645 #define REG_A6XX_RBBM_PRIMCTR_3_LO 0x00000546
1646
1647 #define REG_A6XX_RBBM_PRIMCTR_3_HI 0x00000547
1648
1649 #define REG_A6XX_RBBM_PRIMCTR_4_LO 0x00000548
1650
1651 #define REG_A6XX_RBBM_PRIMCTR_4_HI 0x00000549
1652
1653 #define REG_A6XX_RBBM_PRIMCTR_5_LO 0x0000054a
1654
1655 #define REG_A6XX_RBBM_PRIMCTR_5_HI 0x0000054b
1656
1657 #define REG_A6XX_RBBM_PRIMCTR_6_LO 0x0000054c
1658
1659 #define REG_A6XX_RBBM_PRIMCTR_6_HI 0x0000054d
1660
1661 #define REG_A6XX_RBBM_PRIMCTR_7_LO 0x0000054e
1662
1663 #define REG_A6XX_RBBM_PRIMCTR_7_HI 0x0000054f
1664
1665 #define REG_A6XX_RBBM_PRIMCTR_8_LO 0x00000550
1666
1667 #define REG_A6XX_RBBM_PRIMCTR_8_HI 0x00000551
1668
1669 #define REG_A6XX_RBBM_PRIMCTR_9_LO 0x00000552
1670
1671 #define REG_A6XX_RBBM_PRIMCTR_9_HI 0x00000553
1672
1673 #define REG_A6XX_RBBM_PRIMCTR_10_LO 0x00000554
1674
1675 #define REG_A6XX_RBBM_PRIMCTR_10_HI 0x00000555
1676
1677 #define REG_A6XX_RBBM_SECVID_TRUST_CNTL 0x0000f400
1678
1679 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE 0x0000f800
1680
1681 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802
1682
1683 #define REG_A6XX_RBBM_SECVID_TSB_CNTL 0x0000f803
1684
1685 #define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810
1686
1687 #define REG_A7XX_RBBM_SECVID_TSB_STATUS 0x0000fc00
1688
1689 #define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL 0x00000010
1690
1691 #define REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL 0x00000011
1692
1693 #define REG_A6XX_RBBM_GBIF_HALT 0x00000016
1694
1695 #define REG_A6XX_RBBM_GBIF_HALT_ACK 0x00000017
1696
1697 #define REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD 0x0000001c
1698 #define A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE 0x00000001
1699
1700 #define REG_A7XX_RBBM_GBIF_HALT 0x00000016
1701
1702 #define REG_A7XX_RBBM_GBIF_HALT_ACK 0x00000017
1703
1704 #define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000001f
1705
1706 #define REG_A6XX_RBBM_INT_CLEAR_CMD 0x00000037
1707
1708 #define REG_A6XX_RBBM_INT_0_MASK 0x00000038
1709
1710 #define REG_A7XX_RBBM_INT_2_MASK 0x0000003a
1711
1712 #define REG_A6XX_RBBM_SP_HYST_CNT 0x00000042
1713
1714 #define REG_A6XX_RBBM_SW_RESET_CMD 0x00000043
1715
1716 #define REG_A6XX_RBBM_RAC_THRESHOLD_CNT 0x00000044
1717
1718 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
1719
1720 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046
1721
1722 #define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae
1723
1724 #define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0
1725
1726 #define REG_A6XX_RBBM_CLOCK_CNTL_SP1 0x000000b1
1727
1728 #define REG_A6XX_RBBM_CLOCK_CNTL_SP2 0x000000b2
1729
1730 #define REG_A6XX_RBBM_CLOCK_CNTL_SP3 0x000000b3
1731
1732 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP0 0x000000b4
1733
1734 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP1 0x000000b5
1735
1736 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP2 0x000000b6
1737
1738 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP3 0x000000b7
1739
1740 #define REG_A6XX_RBBM_CLOCK_DELAY_SP0 0x000000b8
1741
1742 #define REG_A6XX_RBBM_CLOCK_DELAY_SP1 0x000000b9
1743
1744 #define REG_A6XX_RBBM_CLOCK_DELAY_SP2 0x000000ba
1745
1746 #define REG_A6XX_RBBM_CLOCK_DELAY_SP3 0x000000bb
1747
1748 #define REG_A6XX_RBBM_CLOCK_HYST_SP0 0x000000bc
1749
1750 #define REG_A6XX_RBBM_CLOCK_HYST_SP1 0x000000bd
1751
1752 #define REG_A6XX_RBBM_CLOCK_HYST_SP2 0x000000be
1753
1754 #define REG_A6XX_RBBM_CLOCK_HYST_SP3 0x000000bf
1755
1756 #define REG_A6XX_RBBM_CLOCK_CNTL_TP0 0x000000c0
1757
1758 #define REG_A6XX_RBBM_CLOCK_CNTL_TP1 0x000000c1
1759
1760 #define REG_A6XX_RBBM_CLOCK_CNTL_TP2 0x000000c2
1761
1762 #define REG_A6XX_RBBM_CLOCK_CNTL_TP3 0x000000c3
1763
1764 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP0 0x000000c4
1765
1766 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP1 0x000000c5
1767
1768 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP2 0x000000c6
1769
1770 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP3 0x000000c7
1771
1772 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP0 0x000000c8
1773
1774 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP1 0x000000c9
1775
1776 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP2 0x000000ca
1777
1778 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP3 0x000000cb
1779
1780 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP0 0x000000cc
1781
1782 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP1 0x000000cd
1783
1784 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP2 0x000000ce
1785
1786 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP3 0x000000cf
1787
1788 #define REG_A6XX_RBBM_CLOCK_DELAY_TP0 0x000000d0
1789
1790 #define REG_A6XX_RBBM_CLOCK_DELAY_TP1 0x000000d1
1791
1792 #define REG_A6XX_RBBM_CLOCK_DELAY_TP2 0x000000d2
1793
1794 #define REG_A6XX_RBBM_CLOCK_DELAY_TP3 0x000000d3
1795
1796 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP0 0x000000d4
1797
1798 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP1 0x000000d5
1799
1800 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP2 0x000000d6
1801
1802 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP3 0x000000d7
1803
1804 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP0 0x000000d8
1805
1806 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP1 0x000000d9
1807
1808 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP2 0x000000da
1809
1810 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP3 0x000000db
1811
1812 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP0 0x000000dc
1813
1814 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP1 0x000000dd
1815
1816 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP2 0x000000de
1817
1818 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP3 0x000000df
1819
1820 #define REG_A6XX_RBBM_CLOCK_HYST_TP0 0x000000e0
1821
1822 #define REG_A6XX_RBBM_CLOCK_HYST_TP1 0x000000e1
1823
1824 #define REG_A6XX_RBBM_CLOCK_HYST_TP2 0x000000e2
1825
1826 #define REG_A6XX_RBBM_CLOCK_HYST_TP3 0x000000e3
1827
1828 #define REG_A6XX_RBBM_CLOCK_HYST2_TP0 0x000000e4
1829
1830 #define REG_A6XX_RBBM_CLOCK_HYST2_TP1 0x000000e5
1831
1832 #define REG_A6XX_RBBM_CLOCK_HYST2_TP2 0x000000e6
1833
1834 #define REG_A6XX_RBBM_CLOCK_HYST2_TP3 0x000000e7
1835
1836 #define REG_A6XX_RBBM_CLOCK_HYST3_TP0 0x000000e8
1837
1838 #define REG_A6XX_RBBM_CLOCK_HYST3_TP1 0x000000e9
1839
1840 #define REG_A6XX_RBBM_CLOCK_HYST3_TP2 0x000000ea
1841
1842 #define REG_A6XX_RBBM_CLOCK_HYST3_TP3 0x000000eb
1843
1844 #define REG_A6XX_RBBM_CLOCK_HYST4_TP0 0x000000ec
1845
1846 #define REG_A6XX_RBBM_CLOCK_HYST4_TP1 0x000000ed
1847
1848 #define REG_A6XX_RBBM_CLOCK_HYST4_TP2 0x000000ee
1849
1850 #define REG_A6XX_RBBM_CLOCK_HYST4_TP3 0x000000ef
1851
1852 #define REG_A6XX_RBBM_CLOCK_CNTL_RB0 0x000000f0
1853
1854 #define REG_A6XX_RBBM_CLOCK_CNTL_RB1 0x000000f1
1855
1856 #define REG_A6XX_RBBM_CLOCK_CNTL_RB2 0x000000f2
1857
1858 #define REG_A6XX_RBBM_CLOCK_CNTL_RB3 0x000000f3
1859
1860 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB0 0x000000f4
1861
1862 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB1 0x000000f5
1863
1864 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB2 0x000000f6
1865
1866 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB3 0x000000f7
1867
1868 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU0 0x000000f8
1869
1870 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU1 0x000000f9
1871
1872 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU2 0x000000fa
1873
1874 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU3 0x000000fb
1875
1876 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000100
1877
1878 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000101
1879
1880 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000102
1881
1882 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000103
1883
1884 #define REG_A6XX_RBBM_CLOCK_CNTL_RAC 0x00000104
1885
1886 #define REG_A6XX_RBBM_CLOCK_CNTL2_RAC 0x00000105
1887
1888 #define REG_A6XX_RBBM_CLOCK_DELAY_RAC 0x00000106
1889
1890 #define REG_A6XX_RBBM_CLOCK_HYST_RAC 0x00000107
1891
1892 #define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000108
1893
1894 #define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000109
1895
1896 #define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000010a
1897
1898 #define REG_A6XX_RBBM_CLOCK_CNTL_UCHE 0x0000010b
1899
1900 #define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE 0x0000010c
1901
1902 #define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE 0x0000010d
1903
1904 #define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE 0x0000010e
1905
1906 #define REG_A6XX_RBBM_CLOCK_DELAY_UCHE 0x0000010f
1907
1908 #define REG_A6XX_RBBM_CLOCK_HYST_UCHE 0x00000110
1909
1910 #define REG_A6XX_RBBM_CLOCK_MODE_VFD 0x00000111
1911
1912 #define REG_A6XX_RBBM_CLOCK_DELAY_VFD 0x00000112
1913
1914 #define REG_A6XX_RBBM_CLOCK_HYST_VFD 0x00000113
1915
1916 #define REG_A6XX_RBBM_CLOCK_MODE_GPC 0x00000114
1917
1918 #define REG_A6XX_RBBM_CLOCK_DELAY_GPC 0x00000115
1919
1920 #define REG_A6XX_RBBM_CLOCK_HYST_GPC 0x00000116
1921
1922 #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2 0x00000117
1923
1924 #define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX 0x00000118
1925
1926 #define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX 0x00000119
1927
1928 #define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX 0x0000011a
1929
1930 #define REG_A6XX_RBBM_CLOCK_MODE_HLSQ 0x0000011b
1931
1932 #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ 0x0000011c
1933
1934 #define REG_A6XX_RBBM_CLOCK_HYST_HLSQ 0x0000011d
1935
1936 #define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE 0x00000120
1937
1938 #define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE 0x00000121
1939
1940 #define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122
1941
1942 #define REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL 0x000005ff
1943
1944 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A 0x00000600
1945
1946 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B 0x00000601
1947
1948 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C 0x00000602
1949
1950 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D 0x00000603
1951 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK 0x000000ff
1952 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT 0
A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val)1953 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val)
1954 {
1955 return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK;
1956 }
1957 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK 0x0000ff00
1958 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT 8
A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val)1959 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val)
1960 {
1961 return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK;
1962 }
1963
1964 #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT 0x00000604
1965 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f
1966 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0
A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)1967 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
1968 {
1969 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK;
1970 }
1971 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000
1972 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12
A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)1973 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
1974 {
1975 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK;
1976 }
1977 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000
1978 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28
A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)1979 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
1980 {
1981 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK;
1982 }
1983
1984 #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM 0x00000605
1985 #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000
1986 #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24
A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)1987 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
1988 {
1989 return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK;
1990 }
1991
1992 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 0x00000608
1993
1994 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 0x00000609
1995
1996 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 0x0000060a
1997
1998 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 0x0000060b
1999
2000 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 0x0000060c
2001
2002 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 0x0000060d
2003
2004 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 0x0000060e
2005
2006 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 0x0000060f
2007
2008 #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000610
2009 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f
2010 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)2011 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
2012 {
2013 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK;
2014 }
2015 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0
2016 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)2017 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
2018 {
2019 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK;
2020 }
2021 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00
2022 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)2023 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
2024 {
2025 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK;
2026 }
2027 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000
2028 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)2029 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
2030 {
2031 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK;
2032 }
2033 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000
2034 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)2035 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
2036 {
2037 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK;
2038 }
2039 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000
2040 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)2041 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
2042 {
2043 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK;
2044 }
2045 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000
2046 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)2047 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
2048 {
2049 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK;
2050 }
2051 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000
2052 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)2053 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
2054 {
2055 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK;
2056 }
2057
2058 #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000611
2059 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f
2060 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)2061 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
2062 {
2063 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK;
2064 }
2065 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0
2066 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)2067 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
2068 {
2069 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK;
2070 }
2071 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00
2072 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)2073 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
2074 {
2075 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK;
2076 }
2077 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000
2078 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)2079 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
2080 {
2081 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK;
2082 }
2083 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000
2084 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)2085 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
2086 {
2087 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK;
2088 }
2089 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000
2090 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)2091 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
2092 {
2093 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK;
2094 }
2095 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000
2096 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)2097 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
2098 {
2099 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK;
2100 }
2101 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000
2102 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)2103 static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
2104 {
2105 return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
2106 }
2107
2108 #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000062f
2109
2110 #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630
2111
REG_A6XX_VSC_PERFCTR_VSC_SEL(uint32_t i0)2112 static inline uint32_t REG_A6XX_VSC_PERFCTR_VSC_SEL(uint32_t i0) { return 0x00000cd8 + 0x1*i0; }
2113
2114 #define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800
2115
2116 #define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000
2117
2118 #define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00
2119
2120 #define REG_A6XX_UCHE_MODE_CNTL 0x00000e01
2121
2122 #define REG_A6XX_UCHE_WRITE_RANGE_MAX 0x00000e05
2123
2124 #define REG_A6XX_UCHE_WRITE_THRU_BASE 0x00000e07
2125
2126 #define REG_A6XX_UCHE_TRAP_BASE 0x00000e09
2127
2128 #define REG_A6XX_UCHE_GMEM_RANGE_MIN 0x00000e0b
2129
2130 #define REG_A6XX_UCHE_GMEM_RANGE_MAX 0x00000e0d
2131
2132 #define REG_A6XX_UCHE_CACHE_WAYS 0x00000e17
2133
2134 #define REG_A6XX_UCHE_FILTER_CNTL 0x00000e18
2135
2136 #define REG_A6XX_UCHE_CLIENT_PF 0x00000e19
2137 #define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK 0x000000ff
2138 #define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT 0
A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val)2139 static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val)
2140 {
2141 return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK;
2142 }
2143
REG_A6XX_UCHE_PERFCTR_UCHE_SEL(uint32_t i0)2144 static inline uint32_t REG_A6XX_UCHE_PERFCTR_UCHE_SEL(uint32_t i0) { return 0x00000e1c + 0x1*i0; }
2145
2146 #define REG_A6XX_UCHE_GBIF_GX_CONFIG 0x00000e3a
2147
2148 #define REG_A6XX_UCHE_CMDQ_CONFIG 0x00000e3c
2149
2150 #define REG_A6XX_VBIF_VERSION 0x00003000
2151
2152 #define REG_A6XX_VBIF_CLKON 0x00003001
2153 #define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000002
2154
2155 #define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
2156
2157 #define REG_A6XX_VBIF_XIN_HALT_CTRL0 0x00003080
2158
2159 #define REG_A6XX_VBIF_XIN_HALT_CTRL1 0x00003081
2160
2161 #define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084
2162
2163 #define REG_A6XX_VBIF_TEST_BUS1_CTRL0 0x00003085
2164
2165 #define REG_A6XX_VBIF_TEST_BUS1_CTRL1 0x00003086
2166 #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK 0x0000000f
2167 #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT 0
A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val)2168 static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val)
2169 {
2170 return ((val) << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK;
2171 }
2172
2173 #define REG_A6XX_VBIF_TEST_BUS2_CTRL0 0x00003087
2174
2175 #define REG_A6XX_VBIF_TEST_BUS2_CTRL1 0x00003088
2176 #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK 0x000001ff
2177 #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT 0
A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val)2178 static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val)
2179 {
2180 return ((val) << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK;
2181 }
2182
2183 #define REG_A6XX_VBIF_TEST_BUS_OUT 0x0000308c
2184
2185 #define REG_A6XX_VBIF_PERF_CNT_SEL0 0x000030d0
2186
2187 #define REG_A6XX_VBIF_PERF_CNT_SEL1 0x000030d1
2188
2189 #define REG_A6XX_VBIF_PERF_CNT_SEL2 0x000030d2
2190
2191 #define REG_A6XX_VBIF_PERF_CNT_SEL3 0x000030d3
2192
2193 #define REG_A6XX_VBIF_PERF_CNT_LOW0 0x000030d8
2194
2195 #define REG_A6XX_VBIF_PERF_CNT_LOW1 0x000030d9
2196
2197 #define REG_A6XX_VBIF_PERF_CNT_LOW2 0x000030da
2198
2199 #define REG_A6XX_VBIF_PERF_CNT_LOW3 0x000030db
2200
2201 #define REG_A6XX_VBIF_PERF_CNT_HIGH0 0x000030e0
2202
2203 #define REG_A6XX_VBIF_PERF_CNT_HIGH1 0x000030e1
2204
2205 #define REG_A6XX_VBIF_PERF_CNT_HIGH2 0x000030e2
2206
2207 #define REG_A6XX_VBIF_PERF_CNT_HIGH3 0x000030e3
2208
2209 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN0 0x00003100
2210
2211 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN1 0x00003101
2212
2213 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN2 0x00003102
2214
2215 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110
2216
2217 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111
2218
2219 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112
2220
2221 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118
2222
2223 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119
2224
2225 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a
2226
2227 #define REG_A6XX_GBIF_SCACHE_CNTL0 0x00003c01
2228
2229 #define REG_A6XX_GBIF_SCACHE_CNTL1 0x00003c02
2230
2231 #define REG_A6XX_GBIF_QSB_SIDE0 0x00003c03
2232
2233 #define REG_A6XX_GBIF_QSB_SIDE1 0x00003c04
2234
2235 #define REG_A6XX_GBIF_QSB_SIDE2 0x00003c05
2236
2237 #define REG_A6XX_GBIF_QSB_SIDE3 0x00003c06
2238
2239 #define REG_A6XX_GBIF_HALT 0x00003c45
2240
2241 #define REG_A6XX_GBIF_HALT_ACK 0x00003c46
2242
2243 #define REG_A6XX_GBIF_PERF_PWR_CNT_EN 0x00003cc0
2244
2245 #define REG_A6XX_GBIF_PERF_PWR_CNT_CLR 0x00003cc1
2246
2247 #define REG_A6XX_GBIF_PERF_CNT_SEL 0x00003cc2
2248
2249 #define REG_A6XX_GBIF_PERF_PWR_CNT_SEL 0x00003cc3
2250
2251 #define REG_A6XX_GBIF_PERF_CNT_LOW0 0x00003cc4
2252
2253 #define REG_A6XX_GBIF_PERF_CNT_LOW1 0x00003cc5
2254
2255 #define REG_A6XX_GBIF_PERF_CNT_LOW2 0x00003cc6
2256
2257 #define REG_A6XX_GBIF_PERF_CNT_LOW3 0x00003cc7
2258
2259 #define REG_A6XX_GBIF_PERF_CNT_HIGH0 0x00003cc8
2260
2261 #define REG_A6XX_GBIF_PERF_CNT_HIGH1 0x00003cc9
2262
2263 #define REG_A6XX_GBIF_PERF_CNT_HIGH2 0x00003cca
2264
2265 #define REG_A6XX_GBIF_PERF_CNT_HIGH3 0x00003ccb
2266
2267 #define REG_A6XX_GBIF_PWR_CNT_LOW0 0x00003ccc
2268
2269 #define REG_A6XX_GBIF_PWR_CNT_LOW1 0x00003ccd
2270
2271 #define REG_A6XX_GBIF_PWR_CNT_LOW2 0x00003cce
2272
2273 #define REG_A6XX_GBIF_PWR_CNT_HIGH0 0x00003ccf
2274
2275 #define REG_A6XX_GBIF_PWR_CNT_HIGH1 0x00003cd0
2276
2277 #define REG_A6XX_GBIF_PWR_CNT_HIGH2 0x00003cd1
2278
2279 #define REG_A6XX_VSC_DBG_ECO_CNTL 0x00000c00
2280
2281 #define REG_A6XX_VSC_BIN_SIZE 0x00000c02
2282 #define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff
2283 #define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val)2284 static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
2285 {
2286 return ((val >> 5) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK;
2287 }
2288 #define A6XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001ff00
2289 #define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT 8
A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)2290 static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
2291 {
2292 return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK;
2293 }
2294
2295 #define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS 0x00000c03
2296
2297 #define REG_A6XX_VSC_BIN_COUNT 0x00000c06
2298 #define A6XX_VSC_BIN_COUNT_NX__MASK 0x000007fe
2299 #define A6XX_VSC_BIN_COUNT_NX__SHIFT 1
A6XX_VSC_BIN_COUNT_NX(uint32_t val)2300 static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val)
2301 {
2302 return ((val) << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK;
2303 }
2304 #define A6XX_VSC_BIN_COUNT_NY__MASK 0x001ff800
2305 #define A6XX_VSC_BIN_COUNT_NY__SHIFT 11
A6XX_VSC_BIN_COUNT_NY(uint32_t val)2306 static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val)
2307 {
2308 return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK;
2309 }
2310
REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0)2311 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
2312
REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0)2313 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
2314 #define A6XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
2315 #define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)2316 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
2317 {
2318 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK;
2319 }
2320 #define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
2321 #define A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)2322 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
2323 {
2324 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK;
2325 }
2326 #define A6XX_VSC_PIPE_CONFIG_REG_W__MASK 0x03f00000
2327 #define A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)2328 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
2329 {
2330 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK;
2331 }
2332 #define A6XX_VSC_PIPE_CONFIG_REG_H__MASK 0xfc000000
2333 #define A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT 26
A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)2334 static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
2335 {
2336 return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK;
2337 }
2338
2339 #define REG_A6XX_VSC_PRIM_STRM_ADDRESS 0x00000c30
2340
2341 #define REG_A6XX_VSC_PRIM_STRM_PITCH 0x00000c32
2342
2343 #define REG_A6XX_VSC_PRIM_STRM_LIMIT 0x00000c33
2344
2345 #define REG_A6XX_VSC_DRAW_STRM_ADDRESS 0x00000c34
2346
2347 #define REG_A6XX_VSC_DRAW_STRM_PITCH 0x00000c36
2348
2349 #define REG_A6XX_VSC_DRAW_STRM_LIMIT 0x00000c37
2350
REG_A6XX_VSC_STATE(uint32_t i0)2351 static inline uint32_t REG_A6XX_VSC_STATE(uint32_t i0) { return 0x00000c38 + 0x1*i0; }
2352
REG_A6XX_VSC_STATE_REG(uint32_t i0)2353 static inline uint32_t REG_A6XX_VSC_STATE_REG(uint32_t i0) { return 0x00000c38 + 0x1*i0; }
2354
REG_A6XX_VSC_PRIM_STRM_SIZE(uint32_t i0)2355 static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE(uint32_t i0) { return 0x00000c58 + 0x1*i0; }
2356
REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0)2357 static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0) { return 0x00000c58 + 0x1*i0; }
2358
REG_A6XX_VSC_DRAW_STRM_SIZE(uint32_t i0)2359 static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
2360
REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0)2361 static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
2362
2363 #define REG_A6XX_UCHE_UNKNOWN_0E12 0x00000e12
2364
2365 #define REG_A6XX_GRAS_CL_CNTL 0x00008000
2366 #define A6XX_GRAS_CL_CNTL_CLIP_DISABLE 0x00000001
2367 #define A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE 0x00000002
2368 #define A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE 0x00000004
2369 #define A6XX_GRAS_CL_CNTL_Z_CLAMP_ENABLE 0x00000020
2370 #define A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040
2371 #define A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE 0x00000080
2372 #define A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE 0x00000100
2373 #define A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE 0x00000200
2374
2375 #define REG_A6XX_GRAS_VS_CL_CNTL 0x00008001
2376 #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK 0x000000ff
2377 #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT 0
A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val)2378 static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val)
2379 {
2380 return ((val) << A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK;
2381 }
2382 #define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK 0x0000ff00
2383 #define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT 8
A6XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val)2384 static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val)
2385 {
2386 return ((val) << A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK;
2387 }
2388
2389 #define REG_A6XX_GRAS_DS_CL_CNTL 0x00008002
2390 #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK 0x000000ff
2391 #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT 0
A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(uint32_t val)2392 static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(uint32_t val)
2393 {
2394 return ((val) << A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK;
2395 }
2396 #define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK 0x0000ff00
2397 #define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT 8
A6XX_GRAS_DS_CL_CNTL_CULL_MASK(uint32_t val)2398 static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CULL_MASK(uint32_t val)
2399 {
2400 return ((val) << A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK;
2401 }
2402
2403 #define REG_A6XX_GRAS_GS_CL_CNTL 0x00008003
2404 #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK 0x000000ff
2405 #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT 0
A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(uint32_t val)2406 static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(uint32_t val)
2407 {
2408 return ((val) << A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK;
2409 }
2410 #define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK 0x0000ff00
2411 #define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT 8
A6XX_GRAS_GS_CL_CNTL_CULL_MASK(uint32_t val)2412 static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CULL_MASK(uint32_t val)
2413 {
2414 return ((val) << A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK;
2415 }
2416
2417 #define REG_A6XX_GRAS_MAX_LAYER_INDEX 0x00008004
2418
2419 #define REG_A6XX_GRAS_CNTL 0x00008005
2420 #define A6XX_GRAS_CNTL_IJ_PERSP_PIXEL 0x00000001
2421 #define A6XX_GRAS_CNTL_IJ_PERSP_CENTROID 0x00000002
2422 #define A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE 0x00000004
2423 #define A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL 0x00000008
2424 #define A6XX_GRAS_CNTL_IJ_LINEAR_CENTROID 0x00000010
2425 #define A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE 0x00000020
2426 #define A6XX_GRAS_CNTL_COORD_MASK__MASK 0x000003c0
2427 #define A6XX_GRAS_CNTL_COORD_MASK__SHIFT 6
A6XX_GRAS_CNTL_COORD_MASK(uint32_t val)2428 static inline uint32_t A6XX_GRAS_CNTL_COORD_MASK(uint32_t val)
2429 {
2430 return ((val) << A6XX_GRAS_CNTL_COORD_MASK__SHIFT) & A6XX_GRAS_CNTL_COORD_MASK__MASK;
2431 }
2432
2433 #define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x00008006
2434 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000001ff
2435 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0
A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)2436 static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)
2437 {
2438 return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK;
2439 }
2440 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x0007fc00
2441 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10
A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)2442 static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)
2443 {
2444 return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK;
2445 }
2446
REG_A6XX_GRAS_CL_VPORT(uint32_t i0)2447 static inline uint32_t REG_A6XX_GRAS_CL_VPORT(uint32_t i0) { return 0x00008010 + 0x6*i0; }
2448
REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0)2449 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0) { return 0x00008010 + 0x6*i0; }
2450 #define A6XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff
2451 #define A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0
A6XX_GRAS_CL_VPORT_XOFFSET(float val)2452 static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET(float val)
2453 {
2454 return ((fui(val)) << A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET__MASK;
2455 }
2456
REG_A6XX_GRAS_CL_VPORT_XSCALE(uint32_t i0)2457 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XSCALE(uint32_t i0) { return 0x00008011 + 0x6*i0; }
2458 #define A6XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff
2459 #define A6XX_GRAS_CL_VPORT_XSCALE__SHIFT 0
A6XX_GRAS_CL_VPORT_XSCALE(float val)2460 static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE(float val)
2461 {
2462 return ((fui(val)) << A6XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE__MASK;
2463 }
2464
REG_A6XX_GRAS_CL_VPORT_YOFFSET(uint32_t i0)2465 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YOFFSET(uint32_t i0) { return 0x00008012 + 0x6*i0; }
2466 #define A6XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff
2467 #define A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0
A6XX_GRAS_CL_VPORT_YOFFSET(float val)2468 static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET(float val)
2469 {
2470 return ((fui(val)) << A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET__MASK;
2471 }
2472
REG_A6XX_GRAS_CL_VPORT_YSCALE(uint32_t i0)2473 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YSCALE(uint32_t i0) { return 0x00008013 + 0x6*i0; }
2474 #define A6XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff
2475 #define A6XX_GRAS_CL_VPORT_YSCALE__SHIFT 0
A6XX_GRAS_CL_VPORT_YSCALE(float val)2476 static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE(float val)
2477 {
2478 return ((fui(val)) << A6XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE__MASK;
2479 }
2480
REG_A6XX_GRAS_CL_VPORT_ZOFFSET(uint32_t i0)2481 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZOFFSET(uint32_t i0) { return 0x00008014 + 0x6*i0; }
2482 #define A6XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff
2483 #define A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0
A6XX_GRAS_CL_VPORT_ZOFFSET(float val)2484 static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET(float val)
2485 {
2486 return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET__MASK;
2487 }
2488
REG_A6XX_GRAS_CL_VPORT_ZSCALE(uint32_t i0)2489 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZSCALE(uint32_t i0) { return 0x00008015 + 0x6*i0; }
2490 #define A6XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff
2491 #define A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0
A6XX_GRAS_CL_VPORT_ZSCALE(float val)2492 static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE(float val)
2493 {
2494 return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE__MASK;
2495 }
2496
REG_A6XX_GRAS_CL_Z_CLAMP(uint32_t i0)2497 static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP(uint32_t i0) { return 0x00008070 + 0x2*i0; }
2498
REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0)2499 static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0) { return 0x00008070 + 0x2*i0; }
2500 #define A6XX_GRAS_CL_Z_CLAMP_MIN__MASK 0xffffffff
2501 #define A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT 0
A6XX_GRAS_CL_Z_CLAMP_MIN(float val)2502 static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MIN(float val)
2503 {
2504 return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MIN__MASK;
2505 }
2506
REG_A6XX_GRAS_CL_Z_CLAMP_MAX(uint32_t i0)2507 static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MAX(uint32_t i0) { return 0x00008071 + 0x2*i0; }
2508 #define A6XX_GRAS_CL_Z_CLAMP_MAX__MASK 0xffffffff
2509 #define A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT 0
A6XX_GRAS_CL_Z_CLAMP_MAX(float val)2510 static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MAX(float val)
2511 {
2512 return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MAX__MASK;
2513 }
2514
2515 #define REG_A6XX_GRAS_SU_CNTL 0x00008090
2516 #define A6XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001
2517 #define A6XX_GRAS_SU_CNTL_CULL_BACK 0x00000002
2518 #define A6XX_GRAS_SU_CNTL_FRONT_CW 0x00000004
2519 #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8
2520 #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3
A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)2521 static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)
2522 {
2523 return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
2524 }
2525 #define A6XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800
2526 #define A6XX_GRAS_SU_CNTL_UNK12__MASK 0x00001000
2527 #define A6XX_GRAS_SU_CNTL_UNK12__SHIFT 12
A6XX_GRAS_SU_CNTL_UNK12(uint32_t val)2528 static inline uint32_t A6XX_GRAS_SU_CNTL_UNK12(uint32_t val)
2529 {
2530 return ((val) << A6XX_GRAS_SU_CNTL_UNK12__SHIFT) & A6XX_GRAS_SU_CNTL_UNK12__MASK;
2531 }
2532 #define A6XX_GRAS_SU_CNTL_LINE_MODE__MASK 0x00002000
2533 #define A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT 13
A6XX_GRAS_SU_CNTL_LINE_MODE(enum a5xx_line_mode val)2534 static inline uint32_t A6XX_GRAS_SU_CNTL_LINE_MODE(enum a5xx_line_mode val)
2535 {
2536 return ((val) << A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT) & A6XX_GRAS_SU_CNTL_LINE_MODE__MASK;
2537 }
2538 #define A6XX_GRAS_SU_CNTL_UNK15__MASK 0x00018000
2539 #define A6XX_GRAS_SU_CNTL_UNK15__SHIFT 15
A6XX_GRAS_SU_CNTL_UNK15(uint32_t val)2540 static inline uint32_t A6XX_GRAS_SU_CNTL_UNK15(uint32_t val)
2541 {
2542 return ((val) << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK;
2543 }
2544 #define A6XX_GRAS_SU_CNTL_UNK17 0x00020000
2545 #define A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE 0x00040000
2546 #define A6XX_GRAS_SU_CNTL_UNK19__MASK 0x00780000
2547 #define A6XX_GRAS_SU_CNTL_UNK19__SHIFT 19
A6XX_GRAS_SU_CNTL_UNK19(uint32_t val)2548 static inline uint32_t A6XX_GRAS_SU_CNTL_UNK19(uint32_t val)
2549 {
2550 return ((val) << A6XX_GRAS_SU_CNTL_UNK19__SHIFT) & A6XX_GRAS_SU_CNTL_UNK19__MASK;
2551 }
2552
2553 #define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091
2554 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
2555 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
A6XX_GRAS_SU_POINT_MINMAX_MIN(float val)2556 static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val)
2557 {
2558 return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
2559 }
2560 #define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
2561 #define A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
A6XX_GRAS_SU_POINT_MINMAX_MAX(float val)2562 static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MAX(float val)
2563 {
2564 return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
2565 }
2566
2567 #define REG_A6XX_GRAS_SU_POINT_SIZE 0x00008092
2568 #define A6XX_GRAS_SU_POINT_SIZE__MASK 0x0000ffff
2569 #define A6XX_GRAS_SU_POINT_SIZE__SHIFT 0
A6XX_GRAS_SU_POINT_SIZE(float val)2570 static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val)
2571 {
2572 return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK;
2573 }
2574
2575 #define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL 0x00008094
2576 #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003
2577 #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0
A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val)2578 static inline uint32_t A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val)
2579 {
2580 return ((val) << A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK;
2581 }
2582
2583 #define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE 0x00008095
2584 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
2585 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val)2586 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
2587 {
2588 return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
2589 }
2590
2591 #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00008096
2592 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
2593 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)2594 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
2595 {
2596 return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
2597 }
2598
2599 #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x00008097
2600 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff
2601 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0
A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)2602 static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)
2603 {
2604 return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK;
2605 }
2606
2607 #define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO 0x00008098
2608 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
2609 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)2610 static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)
2611 {
2612 return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
2613 }
2614 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000008
2615 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT 3
A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3(uint32_t val)2616 static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3(uint32_t val)
2617 {
2618 return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK;
2619 }
2620
2621 #define REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x00008099
2622 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN 0x00000001
2623 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK 0x00000006
2624 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT 1
A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT(uint32_t val)2625 static inline uint32_t A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT(uint32_t val)
2626 {
2627 return ((val) << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK;
2628 }
2629 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_INNERCONSERVATIVERASEN 0x00000008
2630 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK 0x00000030
2631 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT 4
A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4(uint32_t val)2632 static inline uint32_t A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4(uint32_t val)
2633 {
2634 return ((val) << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK;
2635 }
2636
2637 #define REG_A6XX_GRAS_SU_PATH_RENDERING_CNTL 0x0000809a
2638 #define A6XX_GRAS_SU_PATH_RENDERING_CNTL_UNK0 0x00000001
2639 #define A6XX_GRAS_SU_PATH_RENDERING_CNTL_LINELENGTHEN 0x00000002
2640
2641 #define REG_A6XX_GRAS_VS_LAYER_CNTL 0x0000809b
2642 #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER 0x00000001
2643 #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW 0x00000002
2644
2645 #define REG_A6XX_GRAS_GS_LAYER_CNTL 0x0000809c
2646 #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER 0x00000001
2647 #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW 0x00000002
2648
2649 #define REG_A6XX_GRAS_DS_LAYER_CNTL 0x0000809d
2650 #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER 0x00000001
2651 #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW 0x00000002
2652
2653 #define REG_A6XX_GRAS_SC_CNTL 0x000080a0
2654 #define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK 0x00000007
2655 #define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT 0
A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(uint32_t val)2656 static inline uint32_t A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(uint32_t val)
2657 {
2658 return ((val) << A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK;
2659 }
2660 #define A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK 0x00000018
2661 #define A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT 3
A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE(enum a6xx_single_prim_mode val)2662 static inline uint32_t A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE(enum a6xx_single_prim_mode val)
2663 {
2664 return ((val) << A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK;
2665 }
2666 #define A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK 0x00000020
2667 #define A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT 5
A6XX_GRAS_SC_CNTL_RASTER_MODE(enum a6xx_raster_mode val)2668 static inline uint32_t A6XX_GRAS_SC_CNTL_RASTER_MODE(enum a6xx_raster_mode val)
2669 {
2670 return ((val) << A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK;
2671 }
2672 #define A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK 0x000000c0
2673 #define A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT 6
A6XX_GRAS_SC_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val)2674 static inline uint32_t A6XX_GRAS_SC_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val)
2675 {
2676 return ((val) << A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK;
2677 }
2678 #define A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK 0x00000100
2679 #define A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT 8
A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION(enum a6xx_sequenced_thread_dist val)2680 static inline uint32_t A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION(enum a6xx_sequenced_thread_dist val)
2681 {
2682 return ((val) << A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT) & A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK;
2683 }
2684 #define A6XX_GRAS_SC_CNTL_UNK9 0x00000200
2685 #define A6XX_GRAS_SC_CNTL_ROTATION__MASK 0x00000c00
2686 #define A6XX_GRAS_SC_CNTL_ROTATION__SHIFT 10
A6XX_GRAS_SC_CNTL_ROTATION(uint32_t val)2687 static inline uint32_t A6XX_GRAS_SC_CNTL_ROTATION(uint32_t val)
2688 {
2689 return ((val) << A6XX_GRAS_SC_CNTL_ROTATION__SHIFT) & A6XX_GRAS_SC_CNTL_ROTATION__MASK;
2690 }
2691 #define A6XX_GRAS_SC_CNTL_EARLYVIZOUTEN 0x00001000
2692
2693 #define REG_A6XX_GRAS_BIN_CONTROL 0x000080a1
2694 #define A6XX_GRAS_BIN_CONTROL_BINW__MASK 0x0000003f
2695 #define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT 0
A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val)2696 static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val)
2697 {
2698 return ((val >> 5) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK;
2699 }
2700 #define A6XX_GRAS_BIN_CONTROL_BINH__MASK 0x00007f00
2701 #define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT 8
A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val)2702 static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val)
2703 {
2704 return ((val >> 4) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK;
2705 }
2706 #define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000
2707 #define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT 18
A6XX_GRAS_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val)2708 static inline uint32_t A6XX_GRAS_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val)
2709 {
2710 return ((val) << A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK;
2711 }
2712 #define A6XX_GRAS_BIN_CONTROL_FORCE_LRZ_WRITE_DIS 0x00200000
2713 #define A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK 0x00c00000
2714 #define A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT 22
A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val)2715 static inline uint32_t A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val)
2716 {
2717 return ((val) << A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK;
2718 }
2719 #define A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK 0x07000000
2720 #define A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT 24
A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val)2721 static inline uint32_t A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val)
2722 {
2723 return ((val) << A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK;
2724 }
2725 #define A6XX_GRAS_BIN_CONTROL_UNK27__MASK 0x08000000
2726 #define A6XX_GRAS_BIN_CONTROL_UNK27__SHIFT 27
A6XX_GRAS_BIN_CONTROL_UNK27(uint32_t val)2727 static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK27(uint32_t val)
2728 {
2729 return ((val) << A6XX_GRAS_BIN_CONTROL_UNK27__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK27__MASK;
2730 }
2731
2732 #define REG_A6XX_GRAS_RAS_MSAA_CNTL 0x000080a2
2733 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
2734 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)2735 static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2736 {
2737 return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK;
2738 }
2739 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK 0x00000004
2740 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT 2
A6XX_GRAS_RAS_MSAA_CNTL_UNK2(uint32_t val)2741 static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK2(uint32_t val)
2742 {
2743 return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK;
2744 }
2745 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK 0x00000008
2746 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT 3
A6XX_GRAS_RAS_MSAA_CNTL_UNK3(uint32_t val)2747 static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK3(uint32_t val)
2748 {
2749 return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK;
2750 }
2751
2752 #define REG_A6XX_GRAS_DEST_MSAA_CNTL 0x000080a3
2753 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
2754 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)2755 static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2756 {
2757 return ((val) << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK;
2758 }
2759 #define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
2760
2761 #define REG_A6XX_GRAS_SAMPLE_CONFIG 0x000080a4
2762 #define A6XX_GRAS_SAMPLE_CONFIG_UNK0 0x00000001
2763 #define A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002
2764
2765 #define REG_A6XX_GRAS_SAMPLE_LOCATION_0 0x000080a5
2766 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f
2767 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)2768 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
2769 {
2770 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
2771 }
2772 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0
2773 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)2774 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
2775 {
2776 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
2777 }
2778 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00
2779 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)2780 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
2781 {
2782 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
2783 }
2784 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000
2785 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)2786 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
2787 {
2788 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
2789 }
2790 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000
2791 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)2792 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
2793 {
2794 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
2795 }
2796 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000
2797 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)2798 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
2799 {
2800 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
2801 }
2802 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000
2803 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)2804 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
2805 {
2806 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
2807 }
2808 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000
2809 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)2810 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
2811 {
2812 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
2813 }
2814
2815 #define REG_A6XX_GRAS_SAMPLE_LOCATION_1 0x000080a6
2816 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f
2817 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)2818 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
2819 {
2820 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
2821 }
2822 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0
2823 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)2824 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
2825 {
2826 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
2827 }
2828 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00
2829 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)2830 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
2831 {
2832 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
2833 }
2834 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000
2835 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)2836 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
2837 {
2838 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
2839 }
2840 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000
2841 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)2842 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
2843 {
2844 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
2845 }
2846 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000
2847 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)2848 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
2849 {
2850 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
2851 }
2852 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000
2853 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)2854 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
2855 {
2856 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
2857 }
2858 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000
2859 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)2860 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
2861 {
2862 return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
2863 }
2864
2865 #define REG_A6XX_GRAS_UNKNOWN_80AF 0x000080af
2866
REG_A6XX_GRAS_SC_SCREEN_SCISSOR(uint32_t i0)2867 static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR(uint32_t i0) { return 0x000080b0 + 0x2*i0; }
2868
REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0)2869 static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0) { return 0x000080b0 + 0x2*i0; }
2870 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x0000ffff
2871 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0
A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)2872 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
2873 {
2874 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
2875 }
2876 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0xffff0000
2877 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16
A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)2878 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
2879 {
2880 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
2881 }
2882
REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR(uint32_t i0)2883 static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR(uint32_t i0) { return 0x000080b1 + 0x2*i0; }
2884 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x0000ffff
2885 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0
A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)2886 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
2887 {
2888 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
2889 }
2890 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0xffff0000
2891 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16
A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)2892 static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
2893 {
2894 return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
2895 }
2896
REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(uint32_t i0)2897 static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(uint32_t i0) { return 0x000080d0 + 0x2*i0; }
2898
REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0)2899 static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0) { return 0x000080d0 + 0x2*i0; }
2900 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK 0x0000ffff
2901 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT 0
A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(uint32_t val)2902 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(uint32_t val)
2903 {
2904 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK;
2905 }
2906 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK 0xffff0000
2907 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT 16
A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(uint32_t val)2908 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(uint32_t val)
2909 {
2910 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK;
2911 }
2912
REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(uint32_t i0)2913 static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(uint32_t i0) { return 0x000080d1 + 0x2*i0; }
2914 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK 0x0000ffff
2915 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT 0
A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X(uint32_t val)2916 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X(uint32_t val)
2917 {
2918 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK;
2919 }
2920 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK 0xffff0000
2921 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT 16
A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y(uint32_t val)2922 static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y(uint32_t val)
2923 {
2924 return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK;
2925 }
2926
2927 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL 0x000080f0
2928 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00003fff
2929 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)2930 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
2931 {
2932 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
2933 }
2934 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x3fff0000
2935 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)2936 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
2937 {
2938 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
2939 }
2940
2941 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR 0x000080f1
2942 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00003fff
2943 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)2944 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
2945 {
2946 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
2947 }
2948 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x3fff0000
2949 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)2950 static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
2951 {
2952 return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
2953 }
2954
2955 #define REG_A6XX_GRAS_LRZ_CNTL 0x00008100
2956 #define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001
2957 #define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002
2958 #define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004
2959 #define A6XX_GRAS_LRZ_CNTL_FC_ENABLE 0x00000008
2960 #define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE 0x00000010
2961 #define A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE 0x00000020
2962 #define A6XX_GRAS_LRZ_CNTL_DIR__MASK 0x000000c0
2963 #define A6XX_GRAS_LRZ_CNTL_DIR__SHIFT 6
A6XX_GRAS_LRZ_CNTL_DIR(enum a6xx_lrz_dir_status val)2964 static inline uint32_t A6XX_GRAS_LRZ_CNTL_DIR(enum a6xx_lrz_dir_status val)
2965 {
2966 return ((val) << A6XX_GRAS_LRZ_CNTL_DIR__SHIFT) & A6XX_GRAS_LRZ_CNTL_DIR__MASK;
2967 }
2968 #define A6XX_GRAS_LRZ_CNTL_DIR_WRITE 0x00000100
2969 #define A6XX_GRAS_LRZ_CNTL_DISABLE_ON_WRONG_DIR 0x00000200
2970
2971 #define REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL 0x00008101
2972 #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_SAMPLEID 0x00000001
2973 #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK 0x00000006
2974 #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT 1
A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val)2975 static inline uint32_t A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val)
2976 {
2977 return ((val) << A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK;
2978 }
2979
2980 #define REG_A6XX_GRAS_LRZ_MRT_BUF_INFO_0 0x00008102
2981 #define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK 0x000000ff
2982 #define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT 0
A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT(enum a6xx_format val)2983 static inline uint32_t A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT(enum a6xx_format val)
2984 {
2985 return ((val) << A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT) & A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK;
2986 }
2987
2988 #define REG_A6XX_GRAS_LRZ_BUFFER_BASE 0x00008103
2989 #define A6XX_GRAS_LRZ_BUFFER_BASE__MASK 0xffffffff
2990 #define A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT 0
A6XX_GRAS_LRZ_BUFFER_BASE(uint32_t val)2991 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_BASE(uint32_t val)
2992 {
2993 return ((val) << A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_BUFFER_BASE__MASK;
2994 }
2995
2996 #define REG_A6XX_GRAS_LRZ_BUFFER_PITCH 0x00008105
2997 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK 0x000000ff
2998 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT 0
A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val)2999 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val)
3000 {
3001 return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK;
3002 }
3003 #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffffc00
3004 #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT 10
A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)3005 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
3006 {
3007 return ((val >> 4) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK;
3008 }
3009
3010 #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE 0x00008106
3011 #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK 0xffffffff
3012 #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT 0
A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(uint32_t val)3013 static inline uint32_t A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(uint32_t val)
3014 {
3015 return ((val) << A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK;
3016 }
3017
3018 #define REG_A6XX_GRAS_SAMPLE_CNTL 0x00008109
3019 #define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001
3020
3021 #define REG_A6XX_GRAS_LRZ_DEPTH_VIEW 0x0000810a
3022 #define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__MASK 0x000007ff
3023 #define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__SHIFT 0
A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER(uint32_t val)3024 static inline uint32_t A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER(uint32_t val)
3025 {
3026 return ((val) << A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__MASK;
3027 }
3028 #define A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__MASK 0x07ff0000
3029 #define A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__SHIFT 16
A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT(uint32_t val)3030 static inline uint32_t A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT(uint32_t val)
3031 {
3032 return ((val) << A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__MASK;
3033 }
3034 #define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__MASK 0xf0000000
3035 #define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__SHIFT 28
A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL(uint32_t val)3036 static inline uint32_t A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL(uint32_t val)
3037 {
3038 return ((val) << A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__MASK;
3039 }
3040
3041 #define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110
3042
3043 #define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400
3044 #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK 0x00000007
3045 #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT 0
A6XX_GRAS_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val)3046 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val)
3047 {
3048 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK;
3049 }
3050 #define A6XX_GRAS_2D_BLIT_CNTL_OVERWRITEEN 0x00000008
3051 #define A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK 0x00000070
3052 #define A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT 4
A6XX_GRAS_2D_BLIT_CNTL_UNK4(uint32_t val)3053 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK4(uint32_t val)
3054 {
3055 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK;
3056 }
3057 #define A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR 0x00000080
3058 #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00
3059 #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8
A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val)3060 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val)
3061 {
3062 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK;
3063 }
3064 #define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR 0x00010000
3065 #define A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK 0x00060000
3066 #define A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT 17
A6XX_GRAS_2D_BLIT_CNTL_UNK17(uint32_t val)3067 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK17(uint32_t val)
3068 {
3069 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK;
3070 }
3071 #define A6XX_GRAS_2D_BLIT_CNTL_D24S8 0x00080000
3072 #define A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK 0x00f00000
3073 #define A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT 20
A6XX_GRAS_2D_BLIT_CNTL_MASK(uint32_t val)3074 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_MASK(uint32_t val)
3075 {
3076 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK;
3077 }
3078 #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK 0x1f000000
3079 #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT 24
A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)3080 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)
3081 {
3082 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK;
3083 }
3084 #define A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK 0x20000000
3085 #define A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT 29
A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val)3086 static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val)
3087 {
3088 return ((val) << A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK;
3089 }
3090
3091 #define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401
3092
3093 #define REG_A6XX_GRAS_2D_SRC_BR_X 0x00008402
3094
3095 #define REG_A6XX_GRAS_2D_SRC_TL_Y 0x00008403
3096
3097 #define REG_A6XX_GRAS_2D_SRC_BR_Y 0x00008404
3098
3099 #define REG_A6XX_GRAS_2D_DST_TL 0x00008405
3100 #define A6XX_GRAS_2D_DST_TL_X__MASK 0x00003fff
3101 #define A6XX_GRAS_2D_DST_TL_X__SHIFT 0
A6XX_GRAS_2D_DST_TL_X(uint32_t val)3102 static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val)
3103 {
3104 return ((val) << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK;
3105 }
3106 #define A6XX_GRAS_2D_DST_TL_Y__MASK 0x3fff0000
3107 #define A6XX_GRAS_2D_DST_TL_Y__SHIFT 16
A6XX_GRAS_2D_DST_TL_Y(uint32_t val)3108 static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val)
3109 {
3110 return ((val) << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK;
3111 }
3112
3113 #define REG_A6XX_GRAS_2D_DST_BR 0x00008406
3114 #define A6XX_GRAS_2D_DST_BR_X__MASK 0x00003fff
3115 #define A6XX_GRAS_2D_DST_BR_X__SHIFT 0
A6XX_GRAS_2D_DST_BR_X(uint32_t val)3116 static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val)
3117 {
3118 return ((val) << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK;
3119 }
3120 #define A6XX_GRAS_2D_DST_BR_Y__MASK 0x3fff0000
3121 #define A6XX_GRAS_2D_DST_BR_Y__SHIFT 16
A6XX_GRAS_2D_DST_BR_Y(uint32_t val)3122 static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val)
3123 {
3124 return ((val) << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK;
3125 }
3126
3127 #define REG_A6XX_GRAS_2D_UNKNOWN_8407 0x00008407
3128
3129 #define REG_A6XX_GRAS_2D_UNKNOWN_8408 0x00008408
3130
3131 #define REG_A6XX_GRAS_2D_UNKNOWN_8409 0x00008409
3132
3133 #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_1 0x0000840a
3134 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK 0x00003fff
3135 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT 0
A6XX_GRAS_2D_RESOLVE_CNTL_1_X(uint32_t val)3136 static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_X(uint32_t val)
3137 {
3138 return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK;
3139 }
3140 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK 0x3fff0000
3141 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT 16
A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(uint32_t val)3142 static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(uint32_t val)
3143 {
3144 return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK;
3145 }
3146
3147 #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_2 0x0000840b
3148 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK 0x00003fff
3149 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT 0
A6XX_GRAS_2D_RESOLVE_CNTL_2_X(uint32_t val)3150 static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_X(uint32_t val)
3151 {
3152 return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK;
3153 }
3154 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK 0x3fff0000
3155 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT 16
A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val)3156 static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val)
3157 {
3158 return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK;
3159 }
3160
3161 #define REG_A6XX_GRAS_DBG_ECO_CNTL 0x00008600
3162 #define A6XX_GRAS_DBG_ECO_CNTL_UNK7 0x00000080
3163 #define A6XX_GRAS_DBG_ECO_CNTL_LRZCACHELOCKDIS 0x00000800
3164
3165 #define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601
3166
3167 #define REG_A7XX_GRAS_NC_MODE_CNTL 0x00008602
3168
REG_A6XX_GRAS_PERFCTR_TSE_SEL(uint32_t i0)3169 static inline uint32_t REG_A6XX_GRAS_PERFCTR_TSE_SEL(uint32_t i0) { return 0x00008610 + 0x1*i0; }
3170
REG_A6XX_GRAS_PERFCTR_RAS_SEL(uint32_t i0)3171 static inline uint32_t REG_A6XX_GRAS_PERFCTR_RAS_SEL(uint32_t i0) { return 0x00008614 + 0x1*i0; }
3172
REG_A6XX_GRAS_PERFCTR_LRZ_SEL(uint32_t i0)3173 static inline uint32_t REG_A6XX_GRAS_PERFCTR_LRZ_SEL(uint32_t i0) { return 0x00008618 + 0x1*i0; }
3174
3175 #define REG_A6XX_RB_BIN_CONTROL 0x00008800
3176 #define A6XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f
3177 #define A6XX_RB_BIN_CONTROL_BINW__SHIFT 0
A6XX_RB_BIN_CONTROL_BINW(uint32_t val)3178 static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val)
3179 {
3180 return ((val >> 5) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK;
3181 }
3182 #define A6XX_RB_BIN_CONTROL_BINH__MASK 0x00007f00
3183 #define A6XX_RB_BIN_CONTROL_BINH__SHIFT 8
A6XX_RB_BIN_CONTROL_BINH(uint32_t val)3184 static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val)
3185 {
3186 return ((val >> 4) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK;
3187 }
3188 #define A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000
3189 #define A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT 18
A6XX_RB_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val)3190 static inline uint32_t A6XX_RB_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val)
3191 {
3192 return ((val) << A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK;
3193 }
3194 #define A6XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS 0x00200000
3195 #define A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK 0x00c00000
3196 #define A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT 22
A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val)3197 static inline uint32_t A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val)
3198 {
3199 return ((val) << A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK;
3200 }
3201 #define A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK 0x07000000
3202 #define A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT 24
A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val)3203 static inline uint32_t A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val)
3204 {
3205 return ((val) << A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK;
3206 }
3207
3208 #define REG_A6XX_RB_RENDER_CNTL 0x00008801
3209 #define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK 0x00000038
3210 #define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT 3
A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE(uint32_t val)3211 static inline uint32_t A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE(uint32_t val)
3212 {
3213 return ((val) << A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK;
3214 }
3215 #define A6XX_RB_RENDER_CNTL_EARLYVIZOUTEN 0x00000040
3216 #define A6XX_RB_RENDER_CNTL_BINNING 0x00000080
3217 #define A6XX_RB_RENDER_CNTL_UNK8__MASK 0x00000700
3218 #define A6XX_RB_RENDER_CNTL_UNK8__SHIFT 8
A6XX_RB_RENDER_CNTL_UNK8(uint32_t val)3219 static inline uint32_t A6XX_RB_RENDER_CNTL_UNK8(uint32_t val)
3220 {
3221 return ((val) << A6XX_RB_RENDER_CNTL_UNK8__SHIFT) & A6XX_RB_RENDER_CNTL_UNK8__MASK;
3222 }
3223 #define A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK 0x00000100
3224 #define A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT 8
A6XX_RB_RENDER_CNTL_RASTER_MODE(enum a6xx_raster_mode val)3225 static inline uint32_t A6XX_RB_RENDER_CNTL_RASTER_MODE(enum a6xx_raster_mode val)
3226 {
3227 return ((val) << A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK;
3228 }
3229 #define A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK 0x00000600
3230 #define A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT 9
A6XX_RB_RENDER_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val)3231 static inline uint32_t A6XX_RB_RENDER_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val)
3232 {
3233 return ((val) << A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK;
3234 }
3235 #define A6XX_RB_RENDER_CNTL_CONSERVATIVERASEN 0x00000800
3236 #define A6XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN 0x00001000
3237 #define A6XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000
3238 #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000
3239 #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16
A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)3240 static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)
3241 {
3242 return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK;
3243 }
3244
3245 #define REG_A6XX_RB_RAS_MSAA_CNTL 0x00008802
3246 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
3247 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)3248 static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3249 {
3250 return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK;
3251 }
3252 #define A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK 0x00000004
3253 #define A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT 2
A6XX_RB_RAS_MSAA_CNTL_UNK2(uint32_t val)3254 static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK2(uint32_t val)
3255 {
3256 return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK;
3257 }
3258 #define A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK 0x00000008
3259 #define A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT 3
A6XX_RB_RAS_MSAA_CNTL_UNK3(uint32_t val)3260 static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK3(uint32_t val)
3261 {
3262 return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK;
3263 }
3264
3265 #define REG_A6XX_RB_DEST_MSAA_CNTL 0x00008803
3266 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
3267 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)3268 static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3269 {
3270 return ((val) << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK;
3271 }
3272 #define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
3273
3274 #define REG_A6XX_RB_SAMPLE_CONFIG 0x00008804
3275 #define A6XX_RB_SAMPLE_CONFIG_UNK0 0x00000001
3276 #define A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002
3277
3278 #define REG_A6XX_RB_SAMPLE_LOCATION_0 0x00008805
3279 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f
3280 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)3281 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
3282 {
3283 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
3284 }
3285 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0
3286 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)3287 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
3288 {
3289 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
3290 }
3291 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00
3292 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)3293 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
3294 {
3295 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
3296 }
3297 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000
3298 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)3299 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
3300 {
3301 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
3302 }
3303 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000
3304 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)3305 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
3306 {
3307 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
3308 }
3309 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000
3310 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)3311 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
3312 {
3313 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
3314 }
3315 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000
3316 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)3317 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
3318 {
3319 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
3320 }
3321 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000
3322 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)3323 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
3324 {
3325 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
3326 }
3327
3328 #define REG_A6XX_RB_SAMPLE_LOCATION_1 0x00008806
3329 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f
3330 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)3331 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
3332 {
3333 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
3334 }
3335 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0
3336 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)3337 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
3338 {
3339 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
3340 }
3341 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00
3342 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)3343 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
3344 {
3345 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
3346 }
3347 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000
3348 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)3349 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
3350 {
3351 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
3352 }
3353 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000
3354 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)3355 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
3356 {
3357 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
3358 }
3359 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000
3360 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)3361 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
3362 {
3363 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
3364 }
3365 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000
3366 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)3367 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
3368 {
3369 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
3370 }
3371 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000
3372 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)3373 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
3374 {
3375 return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
3376 }
3377
3378 #define REG_A6XX_RB_RENDER_CONTROL0 0x00008809
3379 #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL 0x00000001
3380 #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID 0x00000002
3381 #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE 0x00000004
3382 #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL 0x00000008
3383 #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID 0x00000010
3384 #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE 0x00000020
3385 #define A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK 0x000003c0
3386 #define A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT 6
A6XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val)3387 static inline uint32_t A6XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val)
3388 {
3389 return ((val) << A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK;
3390 }
3391 #define A6XX_RB_RENDER_CONTROL0_UNK10 0x00000400
3392
3393 #define REG_A6XX_RB_RENDER_CONTROL1 0x0000880a
3394 #define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001
3395 #define A6XX_RB_RENDER_CONTROL1_POSTDEPTHCOVERAGE 0x00000002
3396 #define A6XX_RB_RENDER_CONTROL1_FACENESS 0x00000004
3397 #define A6XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000008
3398 #define A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK 0x00000030
3399 #define A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT 4
A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val)3400 static inline uint32_t A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val)
3401 {
3402 return ((val) << A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK;
3403 }
3404 #define A6XX_RB_RENDER_CONTROL1_CENTERRHW 0x00000040
3405 #define A6XX_RB_RENDER_CONTROL1_LINELENGTHEN 0x00000080
3406 #define A6XX_RB_RENDER_CONTROL1_FOVEATION 0x00000100
3407
3408 #define REG_A6XX_RB_FS_OUTPUT_CNTL0 0x0000880b
3409 #define A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001
3410 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z 0x00000002
3411 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK 0x00000004
3412 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF 0x00000008
3413
3414 #define REG_A6XX_RB_FS_OUTPUT_CNTL1 0x0000880c
3415 #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f
3416 #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT 0
A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val)3417 static inline uint32_t A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val)
3418 {
3419 return ((val) << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK;
3420 }
3421
3422 #define REG_A6XX_RB_RENDER_COMPONENTS 0x0000880d
3423 #define A6XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
3424 #define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)3425 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
3426 {
3427 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK;
3428 }
3429 #define A6XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
3430 #define A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)3431 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
3432 {
3433 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK;
3434 }
3435 #define A6XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
3436 #define A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)3437 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
3438 {
3439 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK;
3440 }
3441 #define A6XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
3442 #define A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)3443 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
3444 {
3445 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK;
3446 }
3447 #define A6XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
3448 #define A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)3449 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
3450 {
3451 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK;
3452 }
3453 #define A6XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
3454 #define A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)3455 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
3456 {
3457 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK;
3458 }
3459 #define A6XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
3460 #define A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)3461 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
3462 {
3463 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK;
3464 }
3465 #define A6XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
3466 #define A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)3467 static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
3468 {
3469 return ((val) << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK;
3470 }
3471
3472 #define REG_A6XX_RB_DITHER_CNTL 0x0000880e
3473 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK 0x00000003
3474 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT 0
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val)3475 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val)
3476 {
3477 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK;
3478 }
3479 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK 0x0000000c
3480 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT 2
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val)3481 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val)
3482 {
3483 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK;
3484 }
3485 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK 0x00000030
3486 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT 4
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val)3487 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val)
3488 {
3489 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK;
3490 }
3491 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK 0x000000c0
3492 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT 6
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val)3493 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val)
3494 {
3495 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK;
3496 }
3497 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK 0x00000300
3498 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT 8
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val)3499 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val)
3500 {
3501 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK;
3502 }
3503 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK 0x00000c00
3504 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT 10
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val)3505 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val)
3506 {
3507 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK;
3508 }
3509 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK 0x00001000
3510 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT 12
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val)3511 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val)
3512 {
3513 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK;
3514 }
3515 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK 0x0000c000
3516 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT 14
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val)3517 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val)
3518 {
3519 return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK;
3520 }
3521
3522 #define REG_A6XX_RB_SRGB_CNTL 0x0000880f
3523 #define A6XX_RB_SRGB_CNTL_SRGB_MRT0 0x00000001
3524 #define A6XX_RB_SRGB_CNTL_SRGB_MRT1 0x00000002
3525 #define A6XX_RB_SRGB_CNTL_SRGB_MRT2 0x00000004
3526 #define A6XX_RB_SRGB_CNTL_SRGB_MRT3 0x00000008
3527 #define A6XX_RB_SRGB_CNTL_SRGB_MRT4 0x00000010
3528 #define A6XX_RB_SRGB_CNTL_SRGB_MRT5 0x00000020
3529 #define A6XX_RB_SRGB_CNTL_SRGB_MRT6 0x00000040
3530 #define A6XX_RB_SRGB_CNTL_SRGB_MRT7 0x00000080
3531
3532 #define REG_A6XX_RB_SAMPLE_CNTL 0x00008810
3533 #define A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001
3534
3535 #define REG_A6XX_RB_UNKNOWN_8811 0x00008811
3536
3537 #define REG_A6XX_RB_UNKNOWN_8818 0x00008818
3538
3539 #define REG_A6XX_RB_UNKNOWN_8819 0x00008819
3540
3541 #define REG_A6XX_RB_UNKNOWN_881A 0x0000881a
3542
3543 #define REG_A6XX_RB_UNKNOWN_881B 0x0000881b
3544
3545 #define REG_A6XX_RB_UNKNOWN_881C 0x0000881c
3546
3547 #define REG_A6XX_RB_UNKNOWN_881D 0x0000881d
3548
3549 #define REG_A6XX_RB_UNKNOWN_881E 0x0000881e
3550
REG_A6XX_RB_MRT(uint32_t i0)3551 static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; }
3552
REG_A6XX_RB_MRT_CONTROL(uint32_t i0)3553 static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; }
3554 #define A6XX_RB_MRT_CONTROL_BLEND 0x00000001
3555 #define A6XX_RB_MRT_CONTROL_BLEND2 0x00000002
3556 #define A6XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004
3557 #define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078
3558 #define A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3
A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)3559 static inline uint32_t A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
3560 {
3561 return ((val) << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK;
3562 }
3563 #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780
3564 #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7
A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)3565 static inline uint32_t A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
3566 {
3567 return ((val) << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
3568 }
3569
REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0)3570 static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; }
3571 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
3572 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)3573 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
3574 {
3575 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
3576 }
3577 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
3578 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)3579 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3580 {
3581 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
3582 }
3583 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
3584 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)3585 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
3586 {
3587 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
3588 }
3589 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
3590 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)3591 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
3592 {
3593 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
3594 }
3595 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
3596 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)3597 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3598 {
3599 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
3600 }
3601 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
3602 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)3603 static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
3604 {
3605 return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
3606 }
3607
REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0)3608 static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; }
3609 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff
3610 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val)3611 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val)
3612 {
3613 return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
3614 }
3615 #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300
3616 #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8
A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val)3617 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val)
3618 {
3619 return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
3620 }
3621 #define A6XX_RB_MRT_BUF_INFO_UNK10__MASK 0x00000400
3622 #define A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT 10
A6XX_RB_MRT_BUF_INFO_UNK10(uint32_t val)3623 static inline uint32_t A6XX_RB_MRT_BUF_INFO_UNK10(uint32_t val)
3624 {
3625 return ((val) << A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT) & A6XX_RB_MRT_BUF_INFO_UNK10__MASK;
3626 }
3627 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000
3628 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13
A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)3629 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3630 {
3631 return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
3632 }
3633
REG_A6XX_RB_MRT_PITCH(uint32_t i0)3634 static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; }
3635 #define A6XX_RB_MRT_PITCH__MASK 0x0000ffff
3636 #define A6XX_RB_MRT_PITCH__SHIFT 0
A6XX_RB_MRT_PITCH(uint32_t val)3637 static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val)
3638 {
3639 return ((val >> 6) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK;
3640 }
3641
REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0)3642 static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; }
3643 #define A6XX_RB_MRT_ARRAY_PITCH__MASK 0x1fffffff
3644 #define A6XX_RB_MRT_ARRAY_PITCH__SHIFT 0
A6XX_RB_MRT_ARRAY_PITCH(uint32_t val)3645 static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val)
3646 {
3647 return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK;
3648 }
3649
REG_A6XX_RB_MRT_BASE(uint32_t i0)3650 static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; }
3651 #define A6XX_RB_MRT_BASE__MASK 0xffffffff
3652 #define A6XX_RB_MRT_BASE__SHIFT 0
A6XX_RB_MRT_BASE(uint32_t val)3653 static inline uint32_t A6XX_RB_MRT_BASE(uint32_t val)
3654 {
3655 return ((val) << A6XX_RB_MRT_BASE__SHIFT) & A6XX_RB_MRT_BASE__MASK;
3656 }
3657
REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0)3658 static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; }
3659 #define A6XX_RB_MRT_BASE_GMEM__MASK 0xfffff000
3660 #define A6XX_RB_MRT_BASE_GMEM__SHIFT 12
A6XX_RB_MRT_BASE_GMEM(uint32_t val)3661 static inline uint32_t A6XX_RB_MRT_BASE_GMEM(uint32_t val)
3662 {
3663 return ((val >> 12) << A6XX_RB_MRT_BASE_GMEM__SHIFT) & A6XX_RB_MRT_BASE_GMEM__MASK;
3664 }
3665
3666 #define REG_A6XX_RB_BLEND_RED_F32 0x00008860
3667 #define A6XX_RB_BLEND_RED_F32__MASK 0xffffffff
3668 #define A6XX_RB_BLEND_RED_F32__SHIFT 0
A6XX_RB_BLEND_RED_F32(float val)3669 static inline uint32_t A6XX_RB_BLEND_RED_F32(float val)
3670 {
3671 return ((fui(val)) << A6XX_RB_BLEND_RED_F32__SHIFT) & A6XX_RB_BLEND_RED_F32__MASK;
3672 }
3673
3674 #define REG_A6XX_RB_BLEND_GREEN_F32 0x00008861
3675 #define A6XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
3676 #define A6XX_RB_BLEND_GREEN_F32__SHIFT 0
A6XX_RB_BLEND_GREEN_F32(float val)3677 static inline uint32_t A6XX_RB_BLEND_GREEN_F32(float val)
3678 {
3679 return ((fui(val)) << A6XX_RB_BLEND_GREEN_F32__SHIFT) & A6XX_RB_BLEND_GREEN_F32__MASK;
3680 }
3681
3682 #define REG_A6XX_RB_BLEND_BLUE_F32 0x00008862
3683 #define A6XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
3684 #define A6XX_RB_BLEND_BLUE_F32__SHIFT 0
A6XX_RB_BLEND_BLUE_F32(float val)3685 static inline uint32_t A6XX_RB_BLEND_BLUE_F32(float val)
3686 {
3687 return ((fui(val)) << A6XX_RB_BLEND_BLUE_F32__SHIFT) & A6XX_RB_BLEND_BLUE_F32__MASK;
3688 }
3689
3690 #define REG_A6XX_RB_BLEND_ALPHA_F32 0x00008863
3691 #define A6XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
3692 #define A6XX_RB_BLEND_ALPHA_F32__SHIFT 0
A6XX_RB_BLEND_ALPHA_F32(float val)3693 static inline uint32_t A6XX_RB_BLEND_ALPHA_F32(float val)
3694 {
3695 return ((fui(val)) << A6XX_RB_BLEND_ALPHA_F32__SHIFT) & A6XX_RB_BLEND_ALPHA_F32__MASK;
3696 }
3697
3698 #define REG_A6XX_RB_ALPHA_CONTROL 0x00008864
3699 #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
3700 #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)3701 static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
3702 {
3703 return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
3704 }
3705 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
3706 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
3707 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)3708 static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
3709 {
3710 return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
3711 }
3712
3713 #define REG_A6XX_RB_BLEND_CNTL 0x00008865
3714 #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
3715 #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)3716 static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
3717 {
3718 return ((val) << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK;
3719 }
3720 #define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100
3721 #define A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200
3722 #define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
3723 #define A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE 0x00000800
3724 #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000
3725 #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16
A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)3726 static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
3727 {
3728 return ((val) << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK;
3729 }
3730
3731 #define REG_A6XX_RB_DEPTH_PLANE_CNTL 0x00008870
3732 #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003
3733 #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0
A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val)3734 static inline uint32_t A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val)
3735 {
3736 return ((val) << A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK;
3737 }
3738
3739 #define REG_A6XX_RB_DEPTH_CNTL 0x00008871
3740 #define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000001
3741 #define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002
3742 #define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c
3743 #define A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2
A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)3744 static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)
3745 {
3746 return ((val) << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK;
3747 }
3748 #define A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE 0x00000020
3749 #define A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE 0x00000040
3750 #define A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE 0x00000080
3751
3752 #define REG_A6XX_RB_DEPTH_BUFFER_INFO 0x00008872
3753 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
3754 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)3755 static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)
3756 {
3757 return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
3758 }
3759 #define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000018
3760 #define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT 3
A6XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val)3761 static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val)
3762 {
3763 return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK;
3764 }
3765
3766 #define REG_A6XX_RB_DEPTH_BUFFER_PITCH 0x00008873
3767 #define A6XX_RB_DEPTH_BUFFER_PITCH__MASK 0x00003fff
3768 #define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0
A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)3769 static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
3770 {
3771 return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK;
3772 }
3773
3774 #define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x00008874
3775 #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0x0fffffff
3776 #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0
A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)3777 static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
3778 {
3779 return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
3780 }
3781
3782 #define REG_A6XX_RB_DEPTH_BUFFER_BASE 0x00008875
3783 #define A6XX_RB_DEPTH_BUFFER_BASE__MASK 0xffffffff
3784 #define A6XX_RB_DEPTH_BUFFER_BASE__SHIFT 0
A6XX_RB_DEPTH_BUFFER_BASE(uint32_t val)3785 static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE(uint32_t val)
3786 {
3787 return ((val) << A6XX_RB_DEPTH_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE__MASK;
3788 }
3789
3790 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM 0x00008877
3791 #define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK 0xfffff000
3792 #define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT 12
A6XX_RB_DEPTH_BUFFER_BASE_GMEM(uint32_t val)3793 static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE_GMEM(uint32_t val)
3794 {
3795 return ((val >> 12) << A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK;
3796 }
3797
3798 #define REG_A6XX_RB_Z_BOUNDS_MIN 0x00008878
3799 #define A6XX_RB_Z_BOUNDS_MIN__MASK 0xffffffff
3800 #define A6XX_RB_Z_BOUNDS_MIN__SHIFT 0
A6XX_RB_Z_BOUNDS_MIN(float val)3801 static inline uint32_t A6XX_RB_Z_BOUNDS_MIN(float val)
3802 {
3803 return ((fui(val)) << A6XX_RB_Z_BOUNDS_MIN__SHIFT) & A6XX_RB_Z_BOUNDS_MIN__MASK;
3804 }
3805
3806 #define REG_A6XX_RB_Z_BOUNDS_MAX 0x00008879
3807 #define A6XX_RB_Z_BOUNDS_MAX__MASK 0xffffffff
3808 #define A6XX_RB_Z_BOUNDS_MAX__SHIFT 0
A6XX_RB_Z_BOUNDS_MAX(float val)3809 static inline uint32_t A6XX_RB_Z_BOUNDS_MAX(float val)
3810 {
3811 return ((fui(val)) << A6XX_RB_Z_BOUNDS_MAX__SHIFT) & A6XX_RB_Z_BOUNDS_MAX__MASK;
3812 }
3813
3814 #define REG_A6XX_RB_STENCIL_CONTROL 0x00008880
3815 #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
3816 #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
3817 #define A6XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
3818 #define A6XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
3819 #define A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)3820 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
3821 {
3822 return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC__MASK;
3823 }
3824 #define A6XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
3825 #define A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)3826 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
3827 {
3828 return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL__MASK;
3829 }
3830 #define A6XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
3831 #define A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)3832 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
3833 {
3834 return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK;
3835 }
3836 #define A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
3837 #define A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)3838 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
3839 {
3840 return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
3841 }
3842 #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
3843 #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)3844 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
3845 {
3846 return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
3847 }
3848 #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
3849 #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)3850 static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
3851 {
3852 return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
3853 }
3854 #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
3855 #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)3856 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
3857 {
3858 return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
3859 }
3860 #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
3861 #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)3862 static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
3863 {
3864 return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
3865 }
3866
3867 #define REG_A6XX_RB_STENCIL_INFO 0x00008881
3868 #define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
3869 #define A6XX_RB_STENCIL_INFO_UNK1 0x00000002
3870
3871 #define REG_A6XX_RB_STENCIL_BUFFER_PITCH 0x00008882
3872 #define A6XX_RB_STENCIL_BUFFER_PITCH__MASK 0x00000fff
3873 #define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT 0
A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val)3874 static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val)
3875 {
3876 return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK;
3877 }
3878
3879 #define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH 0x00008883
3880 #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK 0x00ffffff
3881 #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT 0
A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val)3882 static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val)
3883 {
3884 return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK;
3885 }
3886
3887 #define REG_A6XX_RB_STENCIL_BUFFER_BASE 0x00008884
3888 #define A6XX_RB_STENCIL_BUFFER_BASE__MASK 0xffffffff
3889 #define A6XX_RB_STENCIL_BUFFER_BASE__SHIFT 0
A6XX_RB_STENCIL_BUFFER_BASE(uint32_t val)3890 static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE(uint32_t val)
3891 {
3892 return ((val) << A6XX_RB_STENCIL_BUFFER_BASE__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE__MASK;
3893 }
3894
3895 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM 0x00008886
3896 #define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK 0xfffff000
3897 #define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT 12
A6XX_RB_STENCIL_BUFFER_BASE_GMEM(uint32_t val)3898 static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE_GMEM(uint32_t val)
3899 {
3900 return ((val >> 12) << A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK;
3901 }
3902
3903 #define REG_A6XX_RB_STENCILREF 0x00008887
3904 #define A6XX_RB_STENCILREF_REF__MASK 0x000000ff
3905 #define A6XX_RB_STENCILREF_REF__SHIFT 0
A6XX_RB_STENCILREF_REF(uint32_t val)3906 static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val)
3907 {
3908 return ((val) << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK;
3909 }
3910 #define A6XX_RB_STENCILREF_BFREF__MASK 0x0000ff00
3911 #define A6XX_RB_STENCILREF_BFREF__SHIFT 8
A6XX_RB_STENCILREF_BFREF(uint32_t val)3912 static inline uint32_t A6XX_RB_STENCILREF_BFREF(uint32_t val)
3913 {
3914 return ((val) << A6XX_RB_STENCILREF_BFREF__SHIFT) & A6XX_RB_STENCILREF_BFREF__MASK;
3915 }
3916
3917 #define REG_A6XX_RB_STENCILMASK 0x00008888
3918 #define A6XX_RB_STENCILMASK_MASK__MASK 0x000000ff
3919 #define A6XX_RB_STENCILMASK_MASK__SHIFT 0
A6XX_RB_STENCILMASK_MASK(uint32_t val)3920 static inline uint32_t A6XX_RB_STENCILMASK_MASK(uint32_t val)
3921 {
3922 return ((val) << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK;
3923 }
3924 #define A6XX_RB_STENCILMASK_BFMASK__MASK 0x0000ff00
3925 #define A6XX_RB_STENCILMASK_BFMASK__SHIFT 8
A6XX_RB_STENCILMASK_BFMASK(uint32_t val)3926 static inline uint32_t A6XX_RB_STENCILMASK_BFMASK(uint32_t val)
3927 {
3928 return ((val) << A6XX_RB_STENCILMASK_BFMASK__SHIFT) & A6XX_RB_STENCILMASK_BFMASK__MASK;
3929 }
3930
3931 #define REG_A6XX_RB_STENCILWRMASK 0x00008889
3932 #define A6XX_RB_STENCILWRMASK_WRMASK__MASK 0x000000ff
3933 #define A6XX_RB_STENCILWRMASK_WRMASK__SHIFT 0
A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val)3934 static inline uint32_t A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val)
3935 {
3936 return ((val) << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK;
3937 }
3938 #define A6XX_RB_STENCILWRMASK_BFWRMASK__MASK 0x0000ff00
3939 #define A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT 8
A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val)3940 static inline uint32_t A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val)
3941 {
3942 return ((val) << A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_BFWRMASK__MASK;
3943 }
3944
3945 #define REG_A6XX_RB_WINDOW_OFFSET 0x00008890
3946 #define A6XX_RB_WINDOW_OFFSET_X__MASK 0x00003fff
3947 #define A6XX_RB_WINDOW_OFFSET_X__SHIFT 0
A6XX_RB_WINDOW_OFFSET_X(uint32_t val)3948 static inline uint32_t A6XX_RB_WINDOW_OFFSET_X(uint32_t val)
3949 {
3950 return ((val) << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK;
3951 }
3952 #define A6XX_RB_WINDOW_OFFSET_Y__MASK 0x3fff0000
3953 #define A6XX_RB_WINDOW_OFFSET_Y__SHIFT 16
A6XX_RB_WINDOW_OFFSET_Y(uint32_t val)3954 static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val)
3955 {
3956 return ((val) << A6XX_RB_WINDOW_OFFSET_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET_Y__MASK;
3957 }
3958
3959 #define REG_A6XX_RB_SAMPLE_COUNT_CONTROL 0x00008891
3960 #define A6XX_RB_SAMPLE_COUNT_CONTROL_DISABLE 0x00000001
3961 #define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
3962
3963 #define REG_A6XX_RB_LRZ_CNTL 0x00008898
3964 #define A6XX_RB_LRZ_CNTL_ENABLE 0x00000001
3965
3966 #define REG_A6XX_RB_Z_CLAMP_MIN 0x000088c0
3967 #define A6XX_RB_Z_CLAMP_MIN__MASK 0xffffffff
3968 #define A6XX_RB_Z_CLAMP_MIN__SHIFT 0
A6XX_RB_Z_CLAMP_MIN(float val)3969 static inline uint32_t A6XX_RB_Z_CLAMP_MIN(float val)
3970 {
3971 return ((fui(val)) << A6XX_RB_Z_CLAMP_MIN__SHIFT) & A6XX_RB_Z_CLAMP_MIN__MASK;
3972 }
3973
3974 #define REG_A6XX_RB_Z_CLAMP_MAX 0x000088c1
3975 #define A6XX_RB_Z_CLAMP_MAX__MASK 0xffffffff
3976 #define A6XX_RB_Z_CLAMP_MAX__SHIFT 0
A6XX_RB_Z_CLAMP_MAX(float val)3977 static inline uint32_t A6XX_RB_Z_CLAMP_MAX(float val)
3978 {
3979 return ((fui(val)) << A6XX_RB_Z_CLAMP_MAX__SHIFT) & A6XX_RB_Z_CLAMP_MAX__MASK;
3980 }
3981
3982 #define REG_A6XX_RB_UNKNOWN_88D0 0x000088d0
3983 #define A6XX_RB_UNKNOWN_88D0_UNK0__MASK 0x00001fff
3984 #define A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT 0
A6XX_RB_UNKNOWN_88D0_UNK0(uint32_t val)3985 static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK0(uint32_t val)
3986 {
3987 return ((val) << A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK0__MASK;
3988 }
3989 #define A6XX_RB_UNKNOWN_88D0_UNK16__MASK 0x07ff0000
3990 #define A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT 16
A6XX_RB_UNKNOWN_88D0_UNK16(uint32_t val)3991 static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK16(uint32_t val)
3992 {
3993 return ((val) << A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK16__MASK;
3994 }
3995
3996 #define REG_A6XX_RB_BLIT_SCISSOR_TL 0x000088d1
3997 #define A6XX_RB_BLIT_SCISSOR_TL_X__MASK 0x00003fff
3998 #define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT 0
A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val)3999 static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val)
4000 {
4001 return ((val) << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK;
4002 }
4003 #define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK 0x3fff0000
4004 #define A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT 16
A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val)4005 static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val)
4006 {
4007 return ((val) << A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_Y__MASK;
4008 }
4009
4010 #define REG_A6XX_RB_BLIT_SCISSOR_BR 0x000088d2
4011 #define A6XX_RB_BLIT_SCISSOR_BR_X__MASK 0x00003fff
4012 #define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT 0
A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val)4013 static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val)
4014 {
4015 return ((val) << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK;
4016 }
4017 #define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK 0x3fff0000
4018 #define A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT 16
A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val)4019 static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val)
4020 {
4021 return ((val) << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK;
4022 }
4023
4024 #define REG_A6XX_RB_BIN_CONTROL2 0x000088d3
4025 #define A6XX_RB_BIN_CONTROL2_BINW__MASK 0x0000003f
4026 #define A6XX_RB_BIN_CONTROL2_BINW__SHIFT 0
A6XX_RB_BIN_CONTROL2_BINW(uint32_t val)4027 static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val)
4028 {
4029 return ((val >> 5) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK;
4030 }
4031 #define A6XX_RB_BIN_CONTROL2_BINH__MASK 0x00007f00
4032 #define A6XX_RB_BIN_CONTROL2_BINH__SHIFT 8
A6XX_RB_BIN_CONTROL2_BINH(uint32_t val)4033 static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val)
4034 {
4035 return ((val >> 4) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK;
4036 }
4037
4038 #define REG_A6XX_RB_WINDOW_OFFSET2 0x000088d4
4039 #define A6XX_RB_WINDOW_OFFSET2_X__MASK 0x00003fff
4040 #define A6XX_RB_WINDOW_OFFSET2_X__SHIFT 0
A6XX_RB_WINDOW_OFFSET2_X(uint32_t val)4041 static inline uint32_t A6XX_RB_WINDOW_OFFSET2_X(uint32_t val)
4042 {
4043 return ((val) << A6XX_RB_WINDOW_OFFSET2_X__SHIFT) & A6XX_RB_WINDOW_OFFSET2_X__MASK;
4044 }
4045 #define A6XX_RB_WINDOW_OFFSET2_Y__MASK 0x3fff0000
4046 #define A6XX_RB_WINDOW_OFFSET2_Y__SHIFT 16
A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val)4047 static inline uint32_t A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val)
4048 {
4049 return ((val) << A6XX_RB_WINDOW_OFFSET2_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET2_Y__MASK;
4050 }
4051
4052 #define REG_A6XX_RB_BLIT_GMEM_MSAA_CNTL 0x000088d5
4053 #define A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__MASK 0x00000018
4054 #define A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__SHIFT 3
A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)4055 static inline uint32_t A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
4056 {
4057 return ((val) << A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__MASK;
4058 }
4059
4060 #define REG_A6XX_RB_BLIT_BASE_GMEM 0x000088d6
4061 #define A6XX_RB_BLIT_BASE_GMEM__MASK 0xfffff000
4062 #define A6XX_RB_BLIT_BASE_GMEM__SHIFT 12
A6XX_RB_BLIT_BASE_GMEM(uint32_t val)4063 static inline uint32_t A6XX_RB_BLIT_BASE_GMEM(uint32_t val)
4064 {
4065 return ((val >> 12) << A6XX_RB_BLIT_BASE_GMEM__SHIFT) & A6XX_RB_BLIT_BASE_GMEM__MASK;
4066 }
4067
4068 #define REG_A6XX_RB_BLIT_DST_INFO 0x000088d7
4069 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK 0x00000003
4070 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT 0
A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)4071 static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)
4072 {
4073 return ((val) << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK;
4074 }
4075 #define A6XX_RB_BLIT_DST_INFO_FLAGS 0x00000004
4076 #define A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK 0x00000018
4077 #define A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT 3
A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)4078 static inline uint32_t A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)
4079 {
4080 return ((val) << A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK;
4081 }
4082 #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK 0x00000060
4083 #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT 5
A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)4084 static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
4085 {
4086 return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK;
4087 }
4088 #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK 0x00007f80
4089 #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT 7
A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_format val)4090 static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_format val)
4091 {
4092 return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK;
4093 }
4094 #define A6XX_RB_BLIT_DST_INFO_UNK15 0x00008000
4095
4096 #define REG_A6XX_RB_BLIT_DST 0x000088d8
4097 #define A6XX_RB_BLIT_DST__MASK 0xffffffff
4098 #define A6XX_RB_BLIT_DST__SHIFT 0
A6XX_RB_BLIT_DST(uint32_t val)4099 static inline uint32_t A6XX_RB_BLIT_DST(uint32_t val)
4100 {
4101 return ((val) << A6XX_RB_BLIT_DST__SHIFT) & A6XX_RB_BLIT_DST__MASK;
4102 }
4103
4104 #define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da
4105 #define A6XX_RB_BLIT_DST_PITCH__MASK 0x0000ffff
4106 #define A6XX_RB_BLIT_DST_PITCH__SHIFT 0
A6XX_RB_BLIT_DST_PITCH(uint32_t val)4107 static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val)
4108 {
4109 return ((val >> 6) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK;
4110 }
4111
4112 #define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH 0x000088db
4113 #define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0x1fffffff
4114 #define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0
A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)4115 static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
4116 {
4117 return ((val >> 6) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK;
4118 }
4119
4120 #define REG_A6XX_RB_BLIT_FLAG_DST 0x000088dc
4121 #define A6XX_RB_BLIT_FLAG_DST__MASK 0xffffffff
4122 #define A6XX_RB_BLIT_FLAG_DST__SHIFT 0
A6XX_RB_BLIT_FLAG_DST(uint32_t val)4123 static inline uint32_t A6XX_RB_BLIT_FLAG_DST(uint32_t val)
4124 {
4125 return ((val) << A6XX_RB_BLIT_FLAG_DST__SHIFT) & A6XX_RB_BLIT_FLAG_DST__MASK;
4126 }
4127
4128 #define REG_A6XX_RB_BLIT_FLAG_DST_PITCH 0x000088de
4129 #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK 0x000007ff
4130 #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT 0
A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val)4131 static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val)
4132 {
4133 return ((val >> 6) << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK;
4134 }
4135 #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK 0x0ffff800
4136 #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT 11
A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val)4137 static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val)
4138 {
4139 return ((val >> 7) << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK;
4140 }
4141
4142 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 0x000088df
4143
4144 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1 0x000088e0
4145
4146 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2 0x000088e1
4147
4148 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3 0x000088e2
4149
4150 #define REG_A6XX_RB_BLIT_INFO 0x000088e3
4151 #define A6XX_RB_BLIT_INFO_UNK0 0x00000001
4152 #define A6XX_RB_BLIT_INFO_GMEM 0x00000002
4153 #define A6XX_RB_BLIT_INFO_SAMPLE_0 0x00000004
4154 #define A6XX_RB_BLIT_INFO_DEPTH 0x00000008
4155 #define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK 0x000000f0
4156 #define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT 4
A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val)4157 static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val)
4158 {
4159 return ((val) << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK;
4160 }
4161 #define A6XX_RB_BLIT_INFO_LAST__MASK 0x00000300
4162 #define A6XX_RB_BLIT_INFO_LAST__SHIFT 8
A6XX_RB_BLIT_INFO_LAST(uint32_t val)4163 static inline uint32_t A6XX_RB_BLIT_INFO_LAST(uint32_t val)
4164 {
4165 return ((val) << A6XX_RB_BLIT_INFO_LAST__SHIFT) & A6XX_RB_BLIT_INFO_LAST__MASK;
4166 }
4167 #define A6XX_RB_BLIT_INFO_BUFFER_ID__MASK 0x0000f000
4168 #define A6XX_RB_BLIT_INFO_BUFFER_ID__SHIFT 12
A6XX_RB_BLIT_INFO_BUFFER_ID(uint32_t val)4169 static inline uint32_t A6XX_RB_BLIT_INFO_BUFFER_ID(uint32_t val)
4170 {
4171 return ((val) << A6XX_RB_BLIT_INFO_BUFFER_ID__SHIFT) & A6XX_RB_BLIT_INFO_BUFFER_ID__MASK;
4172 }
4173
4174 #define REG_A6XX_RB_UNKNOWN_88F0 0x000088f0
4175
4176 #define REG_A6XX_RB_UNK_FLAG_BUFFER_BASE 0x000088f1
4177 #define A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK 0xffffffff
4178 #define A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT 0
A6XX_RB_UNK_FLAG_BUFFER_BASE(uint32_t val)4179 static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_BASE(uint32_t val)
4180 {
4181 return ((val) << A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK;
4182 }
4183
4184 #define REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH 0x000088f3
4185 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff
4186 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT 0
A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(uint32_t val)4187 static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
4188 {
4189 return ((val >> 6) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK;
4190 }
4191 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x00fff800
4192 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)4193 static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
4194 {
4195 return ((val >> 7) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
4196 }
4197
4198 #define REG_A6XX_RB_UNKNOWN_88F4 0x000088f4
4199
4200 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE 0x00008900
4201 #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK 0xffffffff
4202 #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT 0
A6XX_RB_DEPTH_FLAG_BUFFER_BASE(uint32_t val)4203 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_BASE(uint32_t val)
4204 {
4205 return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK;
4206 }
4207
4208 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x00008902
4209 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK 0x0000007f
4210 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT 0
A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val)4211 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
4212 {
4213 return ((val >> 6) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK;
4214 }
4215 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK 0x00000700
4216 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT 8
A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8(uint32_t val)4217 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8(uint32_t val)
4218 {
4219 return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK;
4220 }
4221 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x0ffff800
4222 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)4223 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
4224 {
4225 return ((val >> 7) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
4226 }
4227
REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0)4228 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; }
4229
REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0)4230 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; }
4231 #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK 0xffffffff
4232 #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT 0
A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t val)4233 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t val)
4234 {
4235 return ((val) << A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK;
4236 }
4237
REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0)4238 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; }
4239 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff
4240 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT 0
A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val)4241 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
4242 {
4243 return ((val >> 6) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK;
4244 }
4245 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffff800
4246 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)4247 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
4248 {
4249 return ((val >> 7) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
4250 }
4251
4252 #define REG_A6XX_RB_SAMPLE_COUNT_ADDR 0x00008927
4253 #define A6XX_RB_SAMPLE_COUNT_ADDR__MASK 0xffffffff
4254 #define A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT 0
A6XX_RB_SAMPLE_COUNT_ADDR(uint32_t val)4255 static inline uint32_t A6XX_RB_SAMPLE_COUNT_ADDR(uint32_t val)
4256 {
4257 return ((val) << A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT) & A6XX_RB_SAMPLE_COUNT_ADDR__MASK;
4258 }
4259
4260 #define REG_A6XX_RB_UNKNOWN_8A00 0x00008a00
4261
4262 #define REG_A6XX_RB_UNKNOWN_8A10 0x00008a10
4263
4264 #define REG_A6XX_RB_UNKNOWN_8A20 0x00008a20
4265
4266 #define REG_A6XX_RB_UNKNOWN_8A30 0x00008a30
4267
4268 #define REG_A6XX_RB_2D_BLIT_CNTL 0x00008c00
4269 #define A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK 0x00000007
4270 #define A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT 0
A6XX_RB_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val)4271 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val)
4272 {
4273 return ((val) << A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK;
4274 }
4275 #define A6XX_RB_2D_BLIT_CNTL_OVERWRITEEN 0x00000008
4276 #define A6XX_RB_2D_BLIT_CNTL_UNK4__MASK 0x00000070
4277 #define A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT 4
A6XX_RB_2D_BLIT_CNTL_UNK4(uint32_t val)4278 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK4(uint32_t val)
4279 {
4280 return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK4__MASK;
4281 }
4282 #define A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR 0x00000080
4283 #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00
4284 #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8
A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val)4285 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val)
4286 {
4287 return ((val) << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK;
4288 }
4289 #define A6XX_RB_2D_BLIT_CNTL_SCISSOR 0x00010000
4290 #define A6XX_RB_2D_BLIT_CNTL_UNK17__MASK 0x00060000
4291 #define A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT 17
A6XX_RB_2D_BLIT_CNTL_UNK17(uint32_t val)4292 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK17(uint32_t val)
4293 {
4294 return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK17__MASK;
4295 }
4296 #define A6XX_RB_2D_BLIT_CNTL_D24S8 0x00080000
4297 #define A6XX_RB_2D_BLIT_CNTL_MASK__MASK 0x00f00000
4298 #define A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT 20
A6XX_RB_2D_BLIT_CNTL_MASK(uint32_t val)4299 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_MASK(uint32_t val)
4300 {
4301 return ((val) << A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_RB_2D_BLIT_CNTL_MASK__MASK;
4302 }
4303 #define A6XX_RB_2D_BLIT_CNTL_IFMT__MASK 0x1f000000
4304 #define A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT 24
A6XX_RB_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)4305 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)
4306 {
4307 return ((val) << A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_IFMT__MASK;
4308 }
4309 #define A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK 0x20000000
4310 #define A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT 29
A6XX_RB_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val)4311 static inline uint32_t A6XX_RB_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val)
4312 {
4313 return ((val) << A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK;
4314 }
4315
4316 #define REG_A6XX_RB_2D_UNKNOWN_8C01 0x00008c01
4317
4318 #define REG_A6XX_RB_2D_DST_INFO 0x00008c17
4319 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
4320 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_format val)4321 static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_format val)
4322 {
4323 return ((val) << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK;
4324 }
4325 #define A6XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300
4326 #define A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8
A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)4327 static inline uint32_t A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)
4328 {
4329 return ((val) << A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_2D_DST_INFO_TILE_MODE__MASK;
4330 }
4331 #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
4332 #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10
A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)4333 static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
4334 {
4335 return ((val) << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK;
4336 }
4337 #define A6XX_RB_2D_DST_INFO_FLAGS 0x00001000
4338 #define A6XX_RB_2D_DST_INFO_SRGB 0x00002000
4339 #define A6XX_RB_2D_DST_INFO_SAMPLES__MASK 0x0000c000
4340 #define A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT 14
A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)4341 static inline uint32_t A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)
4342 {
4343 return ((val) << A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_2D_DST_INFO_SAMPLES__MASK;
4344 }
4345 #define A6XX_RB_2D_DST_INFO_FILTER 0x00010000
4346 #define A6XX_RB_2D_DST_INFO_UNK17 0x00020000
4347 #define A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE 0x00040000
4348 #define A6XX_RB_2D_DST_INFO_UNK19 0x00080000
4349 #define A6XX_RB_2D_DST_INFO_UNK20 0x00100000
4350 #define A6XX_RB_2D_DST_INFO_UNK21 0x00200000
4351 #define A6XX_RB_2D_DST_INFO_UNK22 0x00400000
4352 #define A6XX_RB_2D_DST_INFO_UNK23__MASK 0x07800000
4353 #define A6XX_RB_2D_DST_INFO_UNK23__SHIFT 23
A6XX_RB_2D_DST_INFO_UNK23(uint32_t val)4354 static inline uint32_t A6XX_RB_2D_DST_INFO_UNK23(uint32_t val)
4355 {
4356 return ((val) << A6XX_RB_2D_DST_INFO_UNK23__SHIFT) & A6XX_RB_2D_DST_INFO_UNK23__MASK;
4357 }
4358 #define A6XX_RB_2D_DST_INFO_UNK28 0x10000000
4359
4360 #define REG_A6XX_RB_2D_DST 0x00008c18
4361 #define A6XX_RB_2D_DST__MASK 0xffffffff
4362 #define A6XX_RB_2D_DST__SHIFT 0
A6XX_RB_2D_DST(uint32_t val)4363 static inline uint32_t A6XX_RB_2D_DST(uint32_t val)
4364 {
4365 return ((val) << A6XX_RB_2D_DST__SHIFT) & A6XX_RB_2D_DST__MASK;
4366 }
4367
4368 #define REG_A6XX_RB_2D_DST_PITCH 0x00008c1a
4369 #define A6XX_RB_2D_DST_PITCH__MASK 0x0000ffff
4370 #define A6XX_RB_2D_DST_PITCH__SHIFT 0
A6XX_RB_2D_DST_PITCH(uint32_t val)4371 static inline uint32_t A6XX_RB_2D_DST_PITCH(uint32_t val)
4372 {
4373 return ((val >> 6) << A6XX_RB_2D_DST_PITCH__SHIFT) & A6XX_RB_2D_DST_PITCH__MASK;
4374 }
4375
4376 #define REG_A6XX_RB_2D_DST_PLANE1 0x00008c1b
4377 #define A6XX_RB_2D_DST_PLANE1__MASK 0xffffffff
4378 #define A6XX_RB_2D_DST_PLANE1__SHIFT 0
A6XX_RB_2D_DST_PLANE1(uint32_t val)4379 static inline uint32_t A6XX_RB_2D_DST_PLANE1(uint32_t val)
4380 {
4381 return ((val) << A6XX_RB_2D_DST_PLANE1__SHIFT) & A6XX_RB_2D_DST_PLANE1__MASK;
4382 }
4383
4384 #define REG_A6XX_RB_2D_DST_PLANE_PITCH 0x00008c1d
4385 #define A6XX_RB_2D_DST_PLANE_PITCH__MASK 0x0000ffff
4386 #define A6XX_RB_2D_DST_PLANE_PITCH__SHIFT 0
A6XX_RB_2D_DST_PLANE_PITCH(uint32_t val)4387 static inline uint32_t A6XX_RB_2D_DST_PLANE_PITCH(uint32_t val)
4388 {
4389 return ((val >> 6) << A6XX_RB_2D_DST_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_PLANE_PITCH__MASK;
4390 }
4391
4392 #define REG_A6XX_RB_2D_DST_PLANE2 0x00008c1e
4393 #define A6XX_RB_2D_DST_PLANE2__MASK 0xffffffff
4394 #define A6XX_RB_2D_DST_PLANE2__SHIFT 0
A6XX_RB_2D_DST_PLANE2(uint32_t val)4395 static inline uint32_t A6XX_RB_2D_DST_PLANE2(uint32_t val)
4396 {
4397 return ((val) << A6XX_RB_2D_DST_PLANE2__SHIFT) & A6XX_RB_2D_DST_PLANE2__MASK;
4398 }
4399
4400 #define REG_A6XX_RB_2D_DST_FLAGS 0x00008c20
4401 #define A6XX_RB_2D_DST_FLAGS__MASK 0xffffffff
4402 #define A6XX_RB_2D_DST_FLAGS__SHIFT 0
A6XX_RB_2D_DST_FLAGS(uint32_t val)4403 static inline uint32_t A6XX_RB_2D_DST_FLAGS(uint32_t val)
4404 {
4405 return ((val) << A6XX_RB_2D_DST_FLAGS__SHIFT) & A6XX_RB_2D_DST_FLAGS__MASK;
4406 }
4407
4408 #define REG_A6XX_RB_2D_DST_FLAGS_PITCH 0x00008c22
4409 #define A6XX_RB_2D_DST_FLAGS_PITCH__MASK 0x000000ff
4410 #define A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT 0
A6XX_RB_2D_DST_FLAGS_PITCH(uint32_t val)4411 static inline uint32_t A6XX_RB_2D_DST_FLAGS_PITCH(uint32_t val)
4412 {
4413 return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH__MASK;
4414 }
4415
4416 #define REG_A6XX_RB_2D_DST_FLAGS_PLANE 0x00008c23
4417 #define A6XX_RB_2D_DST_FLAGS_PLANE__MASK 0xffffffff
4418 #define A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT 0
A6XX_RB_2D_DST_FLAGS_PLANE(uint32_t val)4419 static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE(uint32_t val)
4420 {
4421 return ((val) << A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE__MASK;
4422 }
4423
4424 #define REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH 0x00008c25
4425 #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK 0x000000ff
4426 #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT 0
A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(uint32_t val)4427 static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(uint32_t val)
4428 {
4429 return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK;
4430 }
4431
4432 #define REG_A6XX_RB_2D_SRC_SOLID_C0 0x00008c2c
4433
4434 #define REG_A6XX_RB_2D_SRC_SOLID_C1 0x00008c2d
4435
4436 #define REG_A6XX_RB_2D_SRC_SOLID_C2 0x00008c2e
4437
4438 #define REG_A6XX_RB_2D_SRC_SOLID_C3 0x00008c2f
4439
4440 #define REG_A6XX_RB_UNKNOWN_8E01 0x00008e01
4441
4442 #define REG_A6XX_RB_DBG_ECO_CNTL 0x00008e04
4443
4444 #define REG_A6XX_RB_ADDR_MODE_CNTL 0x00008e05
4445
4446 #define REG_A6XX_RB_CCU_CNTL 0x00008e07
4447 #define A6XX_RB_CCU_CNTL_CONCURRENT_RESOLVE 0x00000004
4448 #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__MASK 0x00000080
4449 #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__SHIFT 7
A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI(uint32_t val)4450 static inline uint32_t A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI(uint32_t val)
4451 {
4452 return ((val) << A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__MASK;
4453 }
4454 #define A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__MASK 0x00000200
4455 #define A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__SHIFT 9
A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI(uint32_t val)4456 static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI(uint32_t val)
4457 {
4458 return ((val) << A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__MASK;
4459 }
4460 #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK 0x001ff000
4461 #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT 12
A6XX_RB_CCU_CNTL_DEPTH_OFFSET(uint32_t val)4462 static inline uint32_t A6XX_RB_CCU_CNTL_DEPTH_OFFSET(uint32_t val)
4463 {
4464 return ((val >> 12) << A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK;
4465 }
4466 #define A6XX_RB_CCU_CNTL_GMEM 0x00400000
4467 #define A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK 0xff800000
4468 #define A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT 23
A6XX_RB_CCU_CNTL_COLOR_OFFSET(uint32_t val)4469 static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_OFFSET(uint32_t val)
4470 {
4471 return ((val >> 12) << A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK;
4472 }
4473
4474 #define REG_A6XX_RB_NC_MODE_CNTL 0x00008e08
4475 #define A6XX_RB_NC_MODE_CNTL_MODE 0x00000001
4476 #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006
4477 #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT 1
A6XX_RB_NC_MODE_CNTL_LOWER_BIT(uint32_t val)4478 static inline uint32_t A6XX_RB_NC_MODE_CNTL_LOWER_BIT(uint32_t val)
4479 {
4480 return ((val) << A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK;
4481 }
4482 #define A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008
4483 #define A6XX_RB_NC_MODE_CNTL_AMSBC 0x00000010
4484 #define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000400
4485 #define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT 10
A6XX_RB_NC_MODE_CNTL_UPPER_BIT(uint32_t val)4486 static inline uint32_t A6XX_RB_NC_MODE_CNTL_UPPER_BIT(uint32_t val)
4487 {
4488 return ((val) << A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK;
4489 }
4490 #define A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR 0x00000800
4491 #define A6XX_RB_NC_MODE_CNTL_UNK12__MASK 0x00003000
4492 #define A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT 12
A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val)4493 static inline uint32_t A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val)
4494 {
4495 return ((val) << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK;
4496 }
4497
REG_A6XX_RB_PERFCTR_RB_SEL(uint32_t i0)4498 static inline uint32_t REG_A6XX_RB_PERFCTR_RB_SEL(uint32_t i0) { return 0x00008e10 + 0x1*i0; }
4499
REG_A6XX_RB_PERFCTR_CCU_SEL(uint32_t i0)4500 static inline uint32_t REG_A6XX_RB_PERFCTR_CCU_SEL(uint32_t i0) { return 0x00008e18 + 0x1*i0; }
4501
4502 #define REG_A6XX_RB_UNKNOWN_8E28 0x00008e28
4503
REG_A6XX_RB_PERFCTR_CMP_SEL(uint32_t i0)4504 static inline uint32_t REG_A6XX_RB_PERFCTR_CMP_SEL(uint32_t i0) { return 0x00008e2c + 0x1*i0; }
4505
REG_A7XX_RB_PERFCTR_UFC_SEL(uint32_t i0)4506 static inline uint32_t REG_A7XX_RB_PERFCTR_UFC_SEL(uint32_t i0) { return 0x00008e30 + 0x1*i0; }
4507
4508 #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST 0x00008e3b
4509
4510 #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD 0x00008e3d
4511
4512 #define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x00008e50
4513
4514 #define REG_A6XX_RB_UNKNOWN_8E51 0x00008e51
4515 #define A6XX_RB_UNKNOWN_8E51__MASK 0xffffffff
4516 #define A6XX_RB_UNKNOWN_8E51__SHIFT 0
A6XX_RB_UNKNOWN_8E51(uint32_t val)4517 static inline uint32_t A6XX_RB_UNKNOWN_8E51(uint32_t val)
4518 {
4519 return ((val) << A6XX_RB_UNKNOWN_8E51__SHIFT) & A6XX_RB_UNKNOWN_8E51__MASK;
4520 }
4521
4522 #define REG_A6XX_VPC_GS_PARAM 0x00009100
4523 #define A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK 0x000000ff
4524 #define A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT 0
A6XX_VPC_GS_PARAM_LINELENGTHLOC(uint32_t val)4525 static inline uint32_t A6XX_VPC_GS_PARAM_LINELENGTHLOC(uint32_t val)
4526 {
4527 return ((val) << A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT) & A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK;
4528 }
4529
4530 #define REG_A6XX_VPC_VS_CLIP_CNTL 0x00009101
4531 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
4532 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT 0
A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(uint32_t val)4533 static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(uint32_t val)
4534 {
4535 return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK;
4536 }
4537 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00
4538 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8
A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)4539 static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
4540 {
4541 return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
4542 }
4543 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000
4544 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16
A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)4545 static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
4546 {
4547 return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
4548 }
4549
4550 #define REG_A6XX_VPC_GS_CLIP_CNTL 0x00009102
4551 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
4552 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT 0
A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK(uint32_t val)4553 static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK(uint32_t val)
4554 {
4555 return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK;
4556 }
4557 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00
4558 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8
A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)4559 static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
4560 {
4561 return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
4562 }
4563 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000
4564 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16
A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)4565 static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
4566 {
4567 return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
4568 }
4569
4570 #define REG_A6XX_VPC_DS_CLIP_CNTL 0x00009103
4571 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
4572 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT 0
A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK(uint32_t val)4573 static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK(uint32_t val)
4574 {
4575 return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK;
4576 }
4577 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00
4578 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8
A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)4579 static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
4580 {
4581 return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
4582 }
4583 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000
4584 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16
A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)4585 static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
4586 {
4587 return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
4588 }
4589
4590 #define REG_A6XX_VPC_VS_LAYER_CNTL 0x00009104
4591 #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff
4592 #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT 0
A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(uint32_t val)4593 static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(uint32_t val)
4594 {
4595 return ((val) << A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK;
4596 }
4597 #define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00
4598 #define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT 8
A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(uint32_t val)4599 static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(uint32_t val)
4600 {
4601 return ((val) << A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK;
4602 }
4603
4604 #define REG_A6XX_VPC_GS_LAYER_CNTL 0x00009105
4605 #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff
4606 #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT 0
A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(uint32_t val)4607 static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(uint32_t val)
4608 {
4609 return ((val) << A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK;
4610 }
4611 #define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00
4612 #define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT 8
A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(uint32_t val)4613 static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(uint32_t val)
4614 {
4615 return ((val) << A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK;
4616 }
4617
4618 #define REG_A6XX_VPC_DS_LAYER_CNTL 0x00009106
4619 #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff
4620 #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT 0
A6XX_VPC_DS_LAYER_CNTL_LAYERLOC(uint32_t val)4621 static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_LAYERLOC(uint32_t val)
4622 {
4623 return ((val) << A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK;
4624 }
4625 #define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00
4626 #define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT 8
A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val)4627 static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val)
4628 {
4629 return ((val) << A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK;
4630 }
4631
4632 #define REG_A6XX_VPC_UNKNOWN_9107 0x00009107
4633 #define A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD 0x00000001
4634 #define A6XX_VPC_UNKNOWN_9107_UNK2 0x00000004
4635
4636 #define REG_A6XX_VPC_POLYGON_MODE 0x00009108
4637 #define A6XX_VPC_POLYGON_MODE_MODE__MASK 0x00000003
4638 #define A6XX_VPC_POLYGON_MODE_MODE__SHIFT 0
A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)4639 static inline uint32_t A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)
4640 {
4641 return ((val) << A6XX_VPC_POLYGON_MODE_MODE__SHIFT) & A6XX_VPC_POLYGON_MODE_MODE__MASK;
4642 }
4643
REG_A6XX_VPC_VARYING_INTERP(uint32_t i0)4644 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; }
4645
REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0)4646 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; }
4647
REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0)4648 static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; }
4649
REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0)4650 static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; }
4651
4652 #define REG_A6XX_VPC_UNKNOWN_9210 0x00009210
4653
4654 #define REG_A6XX_VPC_UNKNOWN_9211 0x00009211
4655
REG_A6XX_VPC_VAR(uint32_t i0)4656 static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; }
4657
REG_A6XX_VPC_VAR_DISABLE(uint32_t i0)4658 static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; }
4659
4660 #define REG_A6XX_VPC_SO_CNTL 0x00009216
4661 #define A6XX_VPC_SO_CNTL_ADDR__MASK 0x000000ff
4662 #define A6XX_VPC_SO_CNTL_ADDR__SHIFT 0
A6XX_VPC_SO_CNTL_ADDR(uint32_t val)4663 static inline uint32_t A6XX_VPC_SO_CNTL_ADDR(uint32_t val)
4664 {
4665 return ((val) << A6XX_VPC_SO_CNTL_ADDR__SHIFT) & A6XX_VPC_SO_CNTL_ADDR__MASK;
4666 }
4667 #define A6XX_VPC_SO_CNTL_RESET 0x00010000
4668
4669 #define REG_A6XX_VPC_SO_PROG 0x00009217
4670 #define A6XX_VPC_SO_PROG_A_BUF__MASK 0x00000003
4671 #define A6XX_VPC_SO_PROG_A_BUF__SHIFT 0
A6XX_VPC_SO_PROG_A_BUF(uint32_t val)4672 static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val)
4673 {
4674 return ((val) << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK;
4675 }
4676 #define A6XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc
4677 #define A6XX_VPC_SO_PROG_A_OFF__SHIFT 2
A6XX_VPC_SO_PROG_A_OFF(uint32_t val)4678 static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val)
4679 {
4680 return ((val >> 2) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK;
4681 }
4682 #define A6XX_VPC_SO_PROG_A_EN 0x00000800
4683 #define A6XX_VPC_SO_PROG_B_BUF__MASK 0x00003000
4684 #define A6XX_VPC_SO_PROG_B_BUF__SHIFT 12
A6XX_VPC_SO_PROG_B_BUF(uint32_t val)4685 static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val)
4686 {
4687 return ((val) << A6XX_VPC_SO_PROG_B_BUF__SHIFT) & A6XX_VPC_SO_PROG_B_BUF__MASK;
4688 }
4689 #define A6XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000
4690 #define A6XX_VPC_SO_PROG_B_OFF__SHIFT 14
A6XX_VPC_SO_PROG_B_OFF(uint32_t val)4691 static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val)
4692 {
4693 return ((val >> 2) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK;
4694 }
4695 #define A6XX_VPC_SO_PROG_B_EN 0x00800000
4696
4697 #define REG_A6XX_VPC_SO_STREAM_COUNTS 0x00009218
4698 #define A6XX_VPC_SO_STREAM_COUNTS__MASK 0xffffffff
4699 #define A6XX_VPC_SO_STREAM_COUNTS__SHIFT 0
A6XX_VPC_SO_STREAM_COUNTS(uint32_t val)4700 static inline uint32_t A6XX_VPC_SO_STREAM_COUNTS(uint32_t val)
4701 {
4702 return ((val) << A6XX_VPC_SO_STREAM_COUNTS__SHIFT) & A6XX_VPC_SO_STREAM_COUNTS__MASK;
4703 }
4704
REG_A6XX_VPC_SO(uint32_t i0)4705 static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; }
4706
REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0)4707 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0) { return 0x0000921a + 0x7*i0; }
4708 #define A6XX_VPC_SO_BUFFER_BASE__MASK 0xffffffff
4709 #define A6XX_VPC_SO_BUFFER_BASE__SHIFT 0
A6XX_VPC_SO_BUFFER_BASE(uint32_t val)4710 static inline uint32_t A6XX_VPC_SO_BUFFER_BASE(uint32_t val)
4711 {
4712 return ((val) << A6XX_VPC_SO_BUFFER_BASE__SHIFT) & A6XX_VPC_SO_BUFFER_BASE__MASK;
4713 }
4714
REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0)4715 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; }
4716 #define A6XX_VPC_SO_BUFFER_SIZE__MASK 0xfffffffc
4717 #define A6XX_VPC_SO_BUFFER_SIZE__SHIFT 2
A6XX_VPC_SO_BUFFER_SIZE(uint32_t val)4718 static inline uint32_t A6XX_VPC_SO_BUFFER_SIZE(uint32_t val)
4719 {
4720 return ((val >> 2) << A6XX_VPC_SO_BUFFER_SIZE__SHIFT) & A6XX_VPC_SO_BUFFER_SIZE__MASK;
4721 }
4722
REG_A6XX_VPC_SO_BUFFER_STRIDE(uint32_t i0)4723 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_STRIDE(uint32_t i0) { return 0x0000921d + 0x7*i0; }
4724 #define A6XX_VPC_SO_BUFFER_STRIDE__MASK 0x000003ff
4725 #define A6XX_VPC_SO_BUFFER_STRIDE__SHIFT 0
A6XX_VPC_SO_BUFFER_STRIDE(uint32_t val)4726 static inline uint32_t A6XX_VPC_SO_BUFFER_STRIDE(uint32_t val)
4727 {
4728 return ((val >> 2) << A6XX_VPC_SO_BUFFER_STRIDE__SHIFT) & A6XX_VPC_SO_BUFFER_STRIDE__MASK;
4729 }
4730
REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0)4731 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; }
4732 #define A6XX_VPC_SO_BUFFER_OFFSET__MASK 0xfffffffc
4733 #define A6XX_VPC_SO_BUFFER_OFFSET__SHIFT 2
A6XX_VPC_SO_BUFFER_OFFSET(uint32_t val)4734 static inline uint32_t A6XX_VPC_SO_BUFFER_OFFSET(uint32_t val)
4735 {
4736 return ((val >> 2) << A6XX_VPC_SO_BUFFER_OFFSET__SHIFT) & A6XX_VPC_SO_BUFFER_OFFSET__MASK;
4737 }
4738
REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0)4739 static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0) { return 0x0000921f + 0x7*i0; }
4740 #define A6XX_VPC_SO_FLUSH_BASE__MASK 0xffffffff
4741 #define A6XX_VPC_SO_FLUSH_BASE__SHIFT 0
A6XX_VPC_SO_FLUSH_BASE(uint32_t val)4742 static inline uint32_t A6XX_VPC_SO_FLUSH_BASE(uint32_t val)
4743 {
4744 return ((val) << A6XX_VPC_SO_FLUSH_BASE__SHIFT) & A6XX_VPC_SO_FLUSH_BASE__MASK;
4745 }
4746
4747 #define REG_A6XX_VPC_POINT_COORD_INVERT 0x00009236
4748 #define A6XX_VPC_POINT_COORD_INVERT_INVERT 0x00000001
4749
4750 #define REG_A6XX_VPC_UNKNOWN_9300 0x00009300
4751
4752 #define REG_A6XX_VPC_VS_PACK 0x00009301
4753 #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK 0x000000ff
4754 #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT 0
A6XX_VPC_VS_PACK_STRIDE_IN_VPC(uint32_t val)4755 static inline uint32_t A6XX_VPC_VS_PACK_STRIDE_IN_VPC(uint32_t val)
4756 {
4757 return ((val) << A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK;
4758 }
4759 #define A6XX_VPC_VS_PACK_POSITIONLOC__MASK 0x0000ff00
4760 #define A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT 8
A6XX_VPC_VS_PACK_POSITIONLOC(uint32_t val)4761 static inline uint32_t A6XX_VPC_VS_PACK_POSITIONLOC(uint32_t val)
4762 {
4763 return ((val) << A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_VS_PACK_POSITIONLOC__MASK;
4764 }
4765 #define A6XX_VPC_VS_PACK_PSIZELOC__MASK 0x00ff0000
4766 #define A6XX_VPC_VS_PACK_PSIZELOC__SHIFT 16
A6XX_VPC_VS_PACK_PSIZELOC(uint32_t val)4767 static inline uint32_t A6XX_VPC_VS_PACK_PSIZELOC(uint32_t val)
4768 {
4769 return ((val) << A6XX_VPC_VS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_VS_PACK_PSIZELOC__MASK;
4770 }
4771 #define A6XX_VPC_VS_PACK_EXTRAPOS__MASK 0x0f000000
4772 #define A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT 24
A6XX_VPC_VS_PACK_EXTRAPOS(uint32_t val)4773 static inline uint32_t A6XX_VPC_VS_PACK_EXTRAPOS(uint32_t val)
4774 {
4775 return ((val) << A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_VS_PACK_EXTRAPOS__MASK;
4776 }
4777
4778 #define REG_A6XX_VPC_GS_PACK 0x00009302
4779 #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK 0x000000ff
4780 #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT 0
A6XX_VPC_GS_PACK_STRIDE_IN_VPC(uint32_t val)4781 static inline uint32_t A6XX_VPC_GS_PACK_STRIDE_IN_VPC(uint32_t val)
4782 {
4783 return ((val) << A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK;
4784 }
4785 #define A6XX_VPC_GS_PACK_POSITIONLOC__MASK 0x0000ff00
4786 #define A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT 8
A6XX_VPC_GS_PACK_POSITIONLOC(uint32_t val)4787 static inline uint32_t A6XX_VPC_GS_PACK_POSITIONLOC(uint32_t val)
4788 {
4789 return ((val) << A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_GS_PACK_POSITIONLOC__MASK;
4790 }
4791 #define A6XX_VPC_GS_PACK_PSIZELOC__MASK 0x00ff0000
4792 #define A6XX_VPC_GS_PACK_PSIZELOC__SHIFT 16
A6XX_VPC_GS_PACK_PSIZELOC(uint32_t val)4793 static inline uint32_t A6XX_VPC_GS_PACK_PSIZELOC(uint32_t val)
4794 {
4795 return ((val) << A6XX_VPC_GS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_GS_PACK_PSIZELOC__MASK;
4796 }
4797 #define A6XX_VPC_GS_PACK_EXTRAPOS__MASK 0x0f000000
4798 #define A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT 24
A6XX_VPC_GS_PACK_EXTRAPOS(uint32_t val)4799 static inline uint32_t A6XX_VPC_GS_PACK_EXTRAPOS(uint32_t val)
4800 {
4801 return ((val) << A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_GS_PACK_EXTRAPOS__MASK;
4802 }
4803
4804 #define REG_A6XX_VPC_DS_PACK 0x00009303
4805 #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK 0x000000ff
4806 #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT 0
A6XX_VPC_DS_PACK_STRIDE_IN_VPC(uint32_t val)4807 static inline uint32_t A6XX_VPC_DS_PACK_STRIDE_IN_VPC(uint32_t val)
4808 {
4809 return ((val) << A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK;
4810 }
4811 #define A6XX_VPC_DS_PACK_POSITIONLOC__MASK 0x0000ff00
4812 #define A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT 8
A6XX_VPC_DS_PACK_POSITIONLOC(uint32_t val)4813 static inline uint32_t A6XX_VPC_DS_PACK_POSITIONLOC(uint32_t val)
4814 {
4815 return ((val) << A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_DS_PACK_POSITIONLOC__MASK;
4816 }
4817 #define A6XX_VPC_DS_PACK_PSIZELOC__MASK 0x00ff0000
4818 #define A6XX_VPC_DS_PACK_PSIZELOC__SHIFT 16
A6XX_VPC_DS_PACK_PSIZELOC(uint32_t val)4819 static inline uint32_t A6XX_VPC_DS_PACK_PSIZELOC(uint32_t val)
4820 {
4821 return ((val) << A6XX_VPC_DS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_DS_PACK_PSIZELOC__MASK;
4822 }
4823 #define A6XX_VPC_DS_PACK_EXTRAPOS__MASK 0x0f000000
4824 #define A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT 24
A6XX_VPC_DS_PACK_EXTRAPOS(uint32_t val)4825 static inline uint32_t A6XX_VPC_DS_PACK_EXTRAPOS(uint32_t val)
4826 {
4827 return ((val) << A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_DS_PACK_EXTRAPOS__MASK;
4828 }
4829
4830 #define REG_A6XX_VPC_CNTL_0 0x00009304
4831 #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK 0x000000ff
4832 #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT 0
A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val)4833 static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val)
4834 {
4835 return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK;
4836 }
4837 #define A6XX_VPC_CNTL_0_PRIMIDLOC__MASK 0x0000ff00
4838 #define A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT 8
A6XX_VPC_CNTL_0_PRIMIDLOC(uint32_t val)4839 static inline uint32_t A6XX_VPC_CNTL_0_PRIMIDLOC(uint32_t val)
4840 {
4841 return ((val) << A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT) & A6XX_VPC_CNTL_0_PRIMIDLOC__MASK;
4842 }
4843 #define A6XX_VPC_CNTL_0_VARYING 0x00010000
4844 #define A6XX_VPC_CNTL_0_VIEWIDLOC__MASK 0xff000000
4845 #define A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT 24
A6XX_VPC_CNTL_0_VIEWIDLOC(uint32_t val)4846 static inline uint32_t A6XX_VPC_CNTL_0_VIEWIDLOC(uint32_t val)
4847 {
4848 return ((val) << A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT) & A6XX_VPC_CNTL_0_VIEWIDLOC__MASK;
4849 }
4850
4851 #define REG_A6XX_VPC_SO_STREAM_CNTL 0x00009305
4852 #define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK 0x00000007
4853 #define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT 0
A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(uint32_t val)4854 static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(uint32_t val)
4855 {
4856 return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK;
4857 }
4858 #define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK 0x00000038
4859 #define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT 3
A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(uint32_t val)4860 static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(uint32_t val)
4861 {
4862 return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK;
4863 }
4864 #define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK 0x000001c0
4865 #define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT 6
A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(uint32_t val)4866 static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(uint32_t val)
4867 {
4868 return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK;
4869 }
4870 #define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK 0x00000e00
4871 #define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT 9
A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(uint32_t val)4872 static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(uint32_t val)
4873 {
4874 return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK;
4875 }
4876 #define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK 0x00078000
4877 #define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT 15
A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val)4878 static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val)
4879 {
4880 return ((val) << A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK;
4881 }
4882
4883 #define REG_A6XX_VPC_SO_DISABLE 0x00009306
4884 #define A6XX_VPC_SO_DISABLE_DISABLE 0x00000001
4885
4886 #define REG_A6XX_VPC_DBG_ECO_CNTL 0x00009600
4887
4888 #define REG_A6XX_VPC_ADDR_MODE_CNTL 0x00009601
4889
4890 #define REG_A6XX_VPC_UNKNOWN_9602 0x00009602
4891
4892 #define REG_A6XX_VPC_UNKNOWN_9603 0x00009603
4893
REG_A6XX_VPC_PERFCTR_VPC_SEL(uint32_t i0)4894 static inline uint32_t REG_A6XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) { return 0x00009604 + 0x1*i0; }
4895
REG_A7XX_VPC_PERFCTR_VPC_SEL(uint32_t i0)4896 static inline uint32_t REG_A7XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) { return 0x0000960b + 0x1*i0; }
4897
4898 #define REG_A6XX_PC_TESS_NUM_VERTEX 0x00009800
4899
4900 #define REG_A6XX_PC_HS_INPUT_SIZE 0x00009801
4901 #define A6XX_PC_HS_INPUT_SIZE_SIZE__MASK 0x000007ff
4902 #define A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT 0
A6XX_PC_HS_INPUT_SIZE_SIZE(uint32_t val)4903 static inline uint32_t A6XX_PC_HS_INPUT_SIZE_SIZE(uint32_t val)
4904 {
4905 return ((val) << A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT) & A6XX_PC_HS_INPUT_SIZE_SIZE__MASK;
4906 }
4907 #define A6XX_PC_HS_INPUT_SIZE_UNK13__MASK 0x00002000
4908 #define A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT 13
A6XX_PC_HS_INPUT_SIZE_UNK13(uint32_t val)4909 static inline uint32_t A6XX_PC_HS_INPUT_SIZE_UNK13(uint32_t val)
4910 {
4911 return ((val) << A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT) & A6XX_PC_HS_INPUT_SIZE_UNK13__MASK;
4912 }
4913
4914 #define REG_A6XX_PC_TESS_CNTL 0x00009802
4915 #define A6XX_PC_TESS_CNTL_SPACING__MASK 0x00000003
4916 #define A6XX_PC_TESS_CNTL_SPACING__SHIFT 0
A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val)4917 static inline uint32_t A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val)
4918 {
4919 return ((val) << A6XX_PC_TESS_CNTL_SPACING__SHIFT) & A6XX_PC_TESS_CNTL_SPACING__MASK;
4920 }
4921 #define A6XX_PC_TESS_CNTL_OUTPUT__MASK 0x0000000c
4922 #define A6XX_PC_TESS_CNTL_OUTPUT__SHIFT 2
A6XX_PC_TESS_CNTL_OUTPUT(enum a6xx_tess_output val)4923 static inline uint32_t A6XX_PC_TESS_CNTL_OUTPUT(enum a6xx_tess_output val)
4924 {
4925 return ((val) << A6XX_PC_TESS_CNTL_OUTPUT__SHIFT) & A6XX_PC_TESS_CNTL_OUTPUT__MASK;
4926 }
4927
4928 #define REG_A6XX_PC_RESTART_INDEX 0x00009803
4929
4930 #define REG_A6XX_PC_MODE_CNTL 0x00009804
4931
4932 #define REG_A6XX_PC_POWER_CNTL 0x00009805
4933
4934 #define REG_A6XX_PC_PRIMID_PASSTHRU 0x00009806
4935
4936 #define REG_A6XX_PC_SO_STREAM_CNTL 0x00009808
4937 #define A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__MASK 0x00078000
4938 #define A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT 15
A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val)4939 static inline uint32_t A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val)
4940 {
4941 return ((val) << A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__MASK;
4942 }
4943
4944 #define REG_A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL 0x0000980a
4945 #define A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN 0x00000001
4946
4947 #define REG_A6XX_PC_DRAW_CMD 0x00009840
4948 #define A6XX_PC_DRAW_CMD_STATE_ID__MASK 0x000000ff
4949 #define A6XX_PC_DRAW_CMD_STATE_ID__SHIFT 0
A6XX_PC_DRAW_CMD_STATE_ID(uint32_t val)4950 static inline uint32_t A6XX_PC_DRAW_CMD_STATE_ID(uint32_t val)
4951 {
4952 return ((val) << A6XX_PC_DRAW_CMD_STATE_ID__SHIFT) & A6XX_PC_DRAW_CMD_STATE_ID__MASK;
4953 }
4954
4955 #define REG_A6XX_PC_DISPATCH_CMD 0x00009841
4956 #define A6XX_PC_DISPATCH_CMD_STATE_ID__MASK 0x000000ff
4957 #define A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT 0
A6XX_PC_DISPATCH_CMD_STATE_ID(uint32_t val)4958 static inline uint32_t A6XX_PC_DISPATCH_CMD_STATE_ID(uint32_t val)
4959 {
4960 return ((val) << A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_PC_DISPATCH_CMD_STATE_ID__MASK;
4961 }
4962
4963 #define REG_A6XX_PC_EVENT_CMD 0x00009842
4964 #define A6XX_PC_EVENT_CMD_STATE_ID__MASK 0x00ff0000
4965 #define A6XX_PC_EVENT_CMD_STATE_ID__SHIFT 16
A6XX_PC_EVENT_CMD_STATE_ID(uint32_t val)4966 static inline uint32_t A6XX_PC_EVENT_CMD_STATE_ID(uint32_t val)
4967 {
4968 return ((val) << A6XX_PC_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_EVENT_CMD_STATE_ID__MASK;
4969 }
4970 #define A6XX_PC_EVENT_CMD_EVENT__MASK 0x0000007f
4971 #define A6XX_PC_EVENT_CMD_EVENT__SHIFT 0
A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val)4972 static inline uint32_t A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val)
4973 {
4974 return ((val) << A6XX_PC_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_EVENT_CMD_EVENT__MASK;
4975 }
4976
4977 #define REG_A6XX_PC_MARKER 0x00009880
4978
4979 #define REG_A6XX_PC_POLYGON_MODE 0x00009981
4980 #define A6XX_PC_POLYGON_MODE_MODE__MASK 0x00000003
4981 #define A6XX_PC_POLYGON_MODE_MODE__SHIFT 0
A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)4982 static inline uint32_t A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)
4983 {
4984 return ((val) << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK;
4985 }
4986
4987 #define REG_A6XX_PC_RASTER_CNTL 0x00009980
4988 #define A6XX_PC_RASTER_CNTL_STREAM__MASK 0x00000003
4989 #define A6XX_PC_RASTER_CNTL_STREAM__SHIFT 0
A6XX_PC_RASTER_CNTL_STREAM(uint32_t val)4990 static inline uint32_t A6XX_PC_RASTER_CNTL_STREAM(uint32_t val)
4991 {
4992 return ((val) << A6XX_PC_RASTER_CNTL_STREAM__SHIFT) & A6XX_PC_RASTER_CNTL_STREAM__MASK;
4993 }
4994 #define A6XX_PC_RASTER_CNTL_DISCARD 0x00000004
4995
4996 #define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00
4997 #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001
4998 #define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002
4999 #define A6XX_PC_PRIMITIVE_CNTL_0_TESS_UPPER_LEFT_DOMAIN_ORIGIN 0x00000004
5000 #define A6XX_PC_PRIMITIVE_CNTL_0_UNK3 0x00000008
5001
5002 #define REG_A6XX_PC_VS_OUT_CNTL 0x00009b01
5003 #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff
5004 #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0
A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)5005 static inline uint32_t A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
5006 {
5007 return ((val) << A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK;
5008 }
5009 #define A6XX_PC_VS_OUT_CNTL_PSIZE 0x00000100
5010 #define A6XX_PC_VS_OUT_CNTL_LAYER 0x00000200
5011 #define A6XX_PC_VS_OUT_CNTL_VIEW 0x00000400
5012 #define A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID 0x00000800
5013 #define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000
5014 #define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT 16
A6XX_PC_VS_OUT_CNTL_CLIP_MASK(uint32_t val)5015 static inline uint32_t A6XX_PC_VS_OUT_CNTL_CLIP_MASK(uint32_t val)
5016 {
5017 return ((val) << A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK;
5018 }
5019
5020 #define REG_A6XX_PC_GS_OUT_CNTL 0x00009b02
5021 #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff
5022 #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0
A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)5023 static inline uint32_t A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
5024 {
5025 return ((val) << A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK;
5026 }
5027 #define A6XX_PC_GS_OUT_CNTL_PSIZE 0x00000100
5028 #define A6XX_PC_GS_OUT_CNTL_LAYER 0x00000200
5029 #define A6XX_PC_GS_OUT_CNTL_VIEW 0x00000400
5030 #define A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID 0x00000800
5031 #define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000
5032 #define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT 16
A6XX_PC_GS_OUT_CNTL_CLIP_MASK(uint32_t val)5033 static inline uint32_t A6XX_PC_GS_OUT_CNTL_CLIP_MASK(uint32_t val)
5034 {
5035 return ((val) << A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK;
5036 }
5037
5038 #define REG_A6XX_PC_HS_OUT_CNTL 0x00009b03
5039 #define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff
5040 #define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0
A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)5041 static inline uint32_t A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
5042 {
5043 return ((val) << A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK;
5044 }
5045 #define A6XX_PC_HS_OUT_CNTL_PSIZE 0x00000100
5046 #define A6XX_PC_HS_OUT_CNTL_LAYER 0x00000200
5047 #define A6XX_PC_HS_OUT_CNTL_VIEW 0x00000400
5048 #define A6XX_PC_HS_OUT_CNTL_PRIMITIVE_ID 0x00000800
5049 #define A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000
5050 #define A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT 16
A6XX_PC_HS_OUT_CNTL_CLIP_MASK(uint32_t val)5051 static inline uint32_t A6XX_PC_HS_OUT_CNTL_CLIP_MASK(uint32_t val)
5052 {
5053 return ((val) << A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK;
5054 }
5055
5056 #define REG_A6XX_PC_DS_OUT_CNTL 0x00009b04
5057 #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff
5058 #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0
A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)5059 static inline uint32_t A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
5060 {
5061 return ((val) << A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK;
5062 }
5063 #define A6XX_PC_DS_OUT_CNTL_PSIZE 0x00000100
5064 #define A6XX_PC_DS_OUT_CNTL_LAYER 0x00000200
5065 #define A6XX_PC_DS_OUT_CNTL_VIEW 0x00000400
5066 #define A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID 0x00000800
5067 #define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000
5068 #define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT 16
A6XX_PC_DS_OUT_CNTL_CLIP_MASK(uint32_t val)5069 static inline uint32_t A6XX_PC_DS_OUT_CNTL_CLIP_MASK(uint32_t val)
5070 {
5071 return ((val) << A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK;
5072 }
5073
5074 #define REG_A6XX_PC_PRIMITIVE_CNTL_5 0x00009b05
5075 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK 0x000000ff
5076 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT 0
A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val)5077 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val)
5078 {
5079 return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK;
5080 }
5081 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK 0x00007c00
5082 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT 10
A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val)5083 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val)
5084 {
5085 return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK;
5086 }
5087 #define A6XX_PC_PRIMITIVE_CNTL_5_LINELENGTHEN 0x00008000
5088 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK 0x00030000
5089 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT 16
A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val)5090 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val)
5091 {
5092 return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK;
5093 }
5094 #define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK 0x00040000
5095 #define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT 18
A6XX_PC_PRIMITIVE_CNTL_5_UNK18(uint32_t val)5096 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_UNK18(uint32_t val)
5097 {
5098 return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK;
5099 }
5100
5101 #define REG_A6XX_PC_PRIMITIVE_CNTL_6 0x00009b06
5102 #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK 0x000007ff
5103 #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT 0
A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(uint32_t val)5104 static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(uint32_t val)
5105 {
5106 return ((val) << A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK;
5107 }
5108
5109 #define REG_A6XX_PC_MULTIVIEW_CNTL 0x00009b07
5110 #define A6XX_PC_MULTIVIEW_CNTL_ENABLE 0x00000001
5111 #define A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002
5112 #define A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c
5113 #define A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT 2
A6XX_PC_MULTIVIEW_CNTL_VIEWS(uint32_t val)5114 static inline uint32_t A6XX_PC_MULTIVIEW_CNTL_VIEWS(uint32_t val)
5115 {
5116 return ((val) << A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK;
5117 }
5118
5119 #define REG_A6XX_PC_MULTIVIEW_MASK 0x00009b08
5120
5121 #define REG_A6XX_PC_2D_EVENT_CMD 0x00009c00
5122 #define A6XX_PC_2D_EVENT_CMD_EVENT__MASK 0x0000007f
5123 #define A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT 0
A6XX_PC_2D_EVENT_CMD_EVENT(enum vgt_event_type val)5124 static inline uint32_t A6XX_PC_2D_EVENT_CMD_EVENT(enum vgt_event_type val)
5125 {
5126 return ((val) << A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_2D_EVENT_CMD_EVENT__MASK;
5127 }
5128 #define A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00
5129 #define A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT 8
A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val)5130 static inline uint32_t A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val)
5131 {
5132 return ((val) << A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK;
5133 }
5134
5135 #define REG_A6XX_PC_DBG_ECO_CNTL 0x00009e00
5136
5137 #define REG_A6XX_PC_ADDR_MODE_CNTL 0x00009e01
5138
5139 #define REG_A6XX_PC_DRAW_INDX_BASE 0x00009e04
5140
5141 #define REG_A6XX_PC_DRAW_FIRST_INDX 0x00009e06
5142
5143 #define REG_A6XX_PC_DRAW_MAX_INDICES 0x00009e07
5144
5145 #define REG_A6XX_PC_TESSFACTOR_ADDR 0x00009e08
5146 #define A6XX_PC_TESSFACTOR_ADDR__MASK 0xffffffff
5147 #define A6XX_PC_TESSFACTOR_ADDR__SHIFT 0
A6XX_PC_TESSFACTOR_ADDR(uint32_t val)5148 static inline uint32_t A6XX_PC_TESSFACTOR_ADDR(uint32_t val)
5149 {
5150 return ((val) << A6XX_PC_TESSFACTOR_ADDR__SHIFT) & A6XX_PC_TESSFACTOR_ADDR__MASK;
5151 }
5152
5153 #define REG_A6XX_PC_DRAW_INITIATOR 0x00009e0b
5154 #define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f
5155 #define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0
A6XX_PC_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)5156 static inline uint32_t A6XX_PC_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
5157 {
5158 return ((val) << A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK;
5159 }
5160 #define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0
5161 #define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6
A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)5162 static inline uint32_t A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
5163 {
5164 return ((val) << A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK;
5165 }
5166 #define A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK 0x00000300
5167 #define A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT 8
A6XX_PC_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)5168 static inline uint32_t A6XX_PC_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
5169 {
5170 return ((val) << A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT) & A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK;
5171 }
5172 #define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000c00
5173 #define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT 10
A6XX_PC_DRAW_INITIATOR_INDEX_SIZE(enum a4xx_index_size val)5174 static inline uint32_t A6XX_PC_DRAW_INITIATOR_INDEX_SIZE(enum a4xx_index_size val)
5175 {
5176 return ((val) << A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK;
5177 }
5178 #define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK 0x00003000
5179 #define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT 12
A6XX_PC_DRAW_INITIATOR_PATCH_TYPE(enum a6xx_patch_type val)5180 static inline uint32_t A6XX_PC_DRAW_INITIATOR_PATCH_TYPE(enum a6xx_patch_type val)
5181 {
5182 return ((val) << A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK;
5183 }
5184 #define A6XX_PC_DRAW_INITIATOR_GS_ENABLE 0x00010000
5185 #define A6XX_PC_DRAW_INITIATOR_TESS_ENABLE 0x00020000
5186
5187 #define REG_A6XX_PC_DRAW_NUM_INSTANCES 0x00009e0c
5188
5189 #define REG_A6XX_PC_DRAW_NUM_INDICES 0x00009e0d
5190
5191 #define REG_A6XX_PC_VSTREAM_CONTROL 0x00009e11
5192 #define A6XX_PC_VSTREAM_CONTROL_UNK0__MASK 0x0000ffff
5193 #define A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT 0
A6XX_PC_VSTREAM_CONTROL_UNK0(uint32_t val)5194 static inline uint32_t A6XX_PC_VSTREAM_CONTROL_UNK0(uint32_t val)
5195 {
5196 return ((val) << A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT) & A6XX_PC_VSTREAM_CONTROL_UNK0__MASK;
5197 }
5198 #define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK 0x003f0000
5199 #define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT 16
A6XX_PC_VSTREAM_CONTROL_VSC_SIZE(uint32_t val)5200 static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_SIZE(uint32_t val)
5201 {
5202 return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK;
5203 }
5204 #define A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK 0x07c00000
5205 #define A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT 22
A6XX_PC_VSTREAM_CONTROL_VSC_N(uint32_t val)5206 static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_N(uint32_t val)
5207 {
5208 return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK;
5209 }
5210
5211 #define REG_A6XX_PC_BIN_PRIM_STRM 0x00009e12
5212 #define A6XX_PC_BIN_PRIM_STRM__MASK 0xffffffff
5213 #define A6XX_PC_BIN_PRIM_STRM__SHIFT 0
A6XX_PC_BIN_PRIM_STRM(uint32_t val)5214 static inline uint32_t A6XX_PC_BIN_PRIM_STRM(uint32_t val)
5215 {
5216 return ((val) << A6XX_PC_BIN_PRIM_STRM__SHIFT) & A6XX_PC_BIN_PRIM_STRM__MASK;
5217 }
5218
5219 #define REG_A6XX_PC_BIN_DRAW_STRM 0x00009e14
5220 #define A6XX_PC_BIN_DRAW_STRM__MASK 0xffffffff
5221 #define A6XX_PC_BIN_DRAW_STRM__SHIFT 0
A6XX_PC_BIN_DRAW_STRM(uint32_t val)5222 static inline uint32_t A6XX_PC_BIN_DRAW_STRM(uint32_t val)
5223 {
5224 return ((val) << A6XX_PC_BIN_DRAW_STRM__SHIFT) & A6XX_PC_BIN_DRAW_STRM__MASK;
5225 }
5226
5227 #define REG_A6XX_PC_VISIBILITY_OVERRIDE 0x00009e1c
5228 #define A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE 0x00000001
5229
REG_A6XX_PC_PERFCTR_PC_SEL(uint32_t i0)5230 static inline uint32_t REG_A6XX_PC_PERFCTR_PC_SEL(uint32_t i0) { return 0x00009e34 + 0x1*i0; }
5231
REG_A7XX_PC_PERFCTR_PC_SEL(uint32_t i0)5232 static inline uint32_t REG_A7XX_PC_PERFCTR_PC_SEL(uint32_t i0) { return 0x00009e42 + 0x1*i0; }
5233
5234 #define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72
5235
5236 #define REG_A6XX_VFD_CONTROL_0 0x0000a000
5237 #define A6XX_VFD_CONTROL_0_FETCH_CNT__MASK 0x0000003f
5238 #define A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT 0
A6XX_VFD_CONTROL_0_FETCH_CNT(uint32_t val)5239 static inline uint32_t A6XX_VFD_CONTROL_0_FETCH_CNT(uint32_t val)
5240 {
5241 return ((val) << A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT) & A6XX_VFD_CONTROL_0_FETCH_CNT__MASK;
5242 }
5243 #define A6XX_VFD_CONTROL_0_DECODE_CNT__MASK 0x00003f00
5244 #define A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT 8
A6XX_VFD_CONTROL_0_DECODE_CNT(uint32_t val)5245 static inline uint32_t A6XX_VFD_CONTROL_0_DECODE_CNT(uint32_t val)
5246 {
5247 return ((val) << A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT) & A6XX_VFD_CONTROL_0_DECODE_CNT__MASK;
5248 }
5249
5250 #define REG_A6XX_VFD_CONTROL_1 0x0000a001
5251 #define A6XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff
5252 #define A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0
A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)5253 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
5254 {
5255 return ((val) << A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VTX__MASK;
5256 }
5257 #define A6XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00
5258 #define A6XX_VFD_CONTROL_1_REGID4INST__SHIFT 8
A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val)5259 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
5260 {
5261 return ((val) << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK;
5262 }
5263 #define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000
5264 #define A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16
A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val)5265 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val)
5266 {
5267 return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK;
5268 }
5269 #define A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK 0xff000000
5270 #define A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT 24
A6XX_VFD_CONTROL_1_REGID4VIEWID(uint32_t val)5271 static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VIEWID(uint32_t val)
5272 {
5273 return ((val) << A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK;
5274 }
5275
5276 #define REG_A6XX_VFD_CONTROL_2 0x0000a002
5277 #define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK 0x000000ff
5278 #define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT 0
A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID(uint32_t val)5279 static inline uint32_t A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID(uint32_t val)
5280 {
5281 return ((val) << A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK;
5282 }
5283 #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK 0x0000ff00
5284 #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT 8
A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val)5285 static inline uint32_t A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val)
5286 {
5287 return ((val) << A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK;
5288 }
5289
5290 #define REG_A6XX_VFD_CONTROL_3 0x0000a003
5291 #define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK 0x000000ff
5292 #define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT 0
A6XX_VFD_CONTROL_3_REGID_DSPRIMID(uint32_t val)5293 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPRIMID(uint32_t val)
5294 {
5295 return ((val) << A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK;
5296 }
5297 #define A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK 0x0000ff00
5298 #define A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT 8
A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID(uint32_t val)5299 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID(uint32_t val)
5300 {
5301 return ((val) << A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK;
5302 }
5303 #define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
5304 #define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)5305 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
5306 {
5307 return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSX__MASK;
5308 }
5309 #define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
5310 #define A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24
A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)5311 static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
5312 {
5313 return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK;
5314 }
5315
5316 #define REG_A6XX_VFD_CONTROL_4 0x0000a004
5317 #define A6XX_VFD_CONTROL_4_UNK0__MASK 0x000000ff
5318 #define A6XX_VFD_CONTROL_4_UNK0__SHIFT 0
A6XX_VFD_CONTROL_4_UNK0(uint32_t val)5319 static inline uint32_t A6XX_VFD_CONTROL_4_UNK0(uint32_t val)
5320 {
5321 return ((val) << A6XX_VFD_CONTROL_4_UNK0__SHIFT) & A6XX_VFD_CONTROL_4_UNK0__MASK;
5322 }
5323
5324 #define REG_A6XX_VFD_CONTROL_5 0x0000a005
5325 #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK 0x000000ff
5326 #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT 0
A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val)5327 static inline uint32_t A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val)
5328 {
5329 return ((val) << A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT) & A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK;
5330 }
5331 #define A6XX_VFD_CONTROL_5_UNK8__MASK 0x0000ff00
5332 #define A6XX_VFD_CONTROL_5_UNK8__SHIFT 8
A6XX_VFD_CONTROL_5_UNK8(uint32_t val)5333 static inline uint32_t A6XX_VFD_CONTROL_5_UNK8(uint32_t val)
5334 {
5335 return ((val) << A6XX_VFD_CONTROL_5_UNK8__SHIFT) & A6XX_VFD_CONTROL_5_UNK8__MASK;
5336 }
5337
5338 #define REG_A6XX_VFD_CONTROL_6 0x0000a006
5339 #define A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU 0x00000001
5340
5341 #define REG_A6XX_VFD_MODE_CNTL 0x0000a007
5342 #define A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK 0x00000007
5343 #define A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT 0
A6XX_VFD_MODE_CNTL_RENDER_MODE(enum a6xx_render_mode val)5344 static inline uint32_t A6XX_VFD_MODE_CNTL_RENDER_MODE(enum a6xx_render_mode val)
5345 {
5346 return ((val) << A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT) & A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK;
5347 }
5348
5349 #define REG_A6XX_VFD_MULTIVIEW_CNTL 0x0000a008
5350 #define A6XX_VFD_MULTIVIEW_CNTL_ENABLE 0x00000001
5351 #define A6XX_VFD_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002
5352 #define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c
5353 #define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT 2
A6XX_VFD_MULTIVIEW_CNTL_VIEWS(uint32_t val)5354 static inline uint32_t A6XX_VFD_MULTIVIEW_CNTL_VIEWS(uint32_t val)
5355 {
5356 return ((val) << A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK;
5357 }
5358
5359 #define REG_A6XX_VFD_ADD_OFFSET 0x0000a009
5360 #define A6XX_VFD_ADD_OFFSET_VERTEX 0x00000001
5361 #define A6XX_VFD_ADD_OFFSET_INSTANCE 0x00000002
5362
5363 #define REG_A6XX_VFD_INDEX_OFFSET 0x0000a00e
5364
5365 #define REG_A6XX_VFD_INSTANCE_START_OFFSET 0x0000a00f
5366
REG_A6XX_VFD_FETCH(uint32_t i0)5367 static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
5368
REG_A6XX_VFD_FETCH_BASE(uint32_t i0)5369 static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
5370 #define A6XX_VFD_FETCH_BASE__MASK 0xffffffff
5371 #define A6XX_VFD_FETCH_BASE__SHIFT 0
A6XX_VFD_FETCH_BASE(uint32_t val)5372 static inline uint32_t A6XX_VFD_FETCH_BASE(uint32_t val)
5373 {
5374 return ((val) << A6XX_VFD_FETCH_BASE__SHIFT) & A6XX_VFD_FETCH_BASE__MASK;
5375 }
5376
REG_A6XX_VFD_FETCH_SIZE(uint32_t i0)5377 static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; }
5378
REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0)5379 static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; }
5380
REG_A6XX_VFD_DECODE(uint32_t i0)5381 static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
5382
REG_A6XX_VFD_DECODE_INSTR(uint32_t i0)5383 static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
5384 #define A6XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f
5385 #define A6XX_VFD_DECODE_INSTR_IDX__SHIFT 0
A6XX_VFD_DECODE_INSTR_IDX(uint32_t val)5386 static inline uint32_t A6XX_VFD_DECODE_INSTR_IDX(uint32_t val)
5387 {
5388 return ((val) << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK;
5389 }
5390 #define A6XX_VFD_DECODE_INSTR_OFFSET__MASK 0x0001ffe0
5391 #define A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT 5
A6XX_VFD_DECODE_INSTR_OFFSET(uint32_t val)5392 static inline uint32_t A6XX_VFD_DECODE_INSTR_OFFSET(uint32_t val)
5393 {
5394 return ((val) << A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT) & A6XX_VFD_DECODE_INSTR_OFFSET__MASK;
5395 }
5396 #define A6XX_VFD_DECODE_INSTR_INSTANCED 0x00020000
5397 #define A6XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000
5398 #define A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20
A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_format val)5399 static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_format val)
5400 {
5401 return ((val) << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK;
5402 }
5403 #define A6XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000
5404 #define A6XX_VFD_DECODE_INSTR_SWAP__SHIFT 28
A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)5405 static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
5406 {
5407 return ((val) << A6XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A6XX_VFD_DECODE_INSTR_SWAP__MASK;
5408 }
5409 #define A6XX_VFD_DECODE_INSTR_UNK30 0x40000000
5410 #define A6XX_VFD_DECODE_INSTR_FLOAT 0x80000000
5411
REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0)5412 static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; }
5413
REG_A6XX_VFD_DEST_CNTL(uint32_t i0)5414 static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }
5415
REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0)5416 static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }
5417 #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f
5418 #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0
A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val)5419 static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val)
5420 {
5421 return ((val) << A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK;
5422 }
5423 #define A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0
5424 #define A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4
A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)5425 static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
5426 {
5427 return ((val) << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK;
5428 }
5429
5430 #define REG_A6XX_VFD_POWER_CNTL 0x0000a0f8
5431
5432 #define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601
5433
REG_A6XX_VFD_PERFCTR_VFD_SEL(uint32_t i0)5434 static inline uint32_t REG_A6XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) { return 0x0000a610 + 0x1*i0; }
5435
REG_A7XX_VFD_PERFCTR_VFD_SEL(uint32_t i0)5436 static inline uint32_t REG_A7XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) { return 0x0000a610 + 0x1*i0; }
5437
5438 #define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800
5439 #define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x00100000
5440 #define A6XX_SP_VS_CTRL_REG0_EARLYPREAMBLE 0x00200000
5441 #define A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001
5442 #define A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0
A6XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)5443 static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5444 {
5445 return ((val) << A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
5446 }
5447 #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5448 #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)5449 static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5450 {
5451 return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5452 }
5453 #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
5454 #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)5455 static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5456 {
5457 return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5458 }
5459 #define A6XX_SP_VS_CTRL_REG0_UNK13 0x00002000
5460 #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5461 #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14
A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)5462 static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5463 {
5464 return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
5465 }
5466
5467 #define REG_A6XX_SP_VS_BRANCH_COND 0x0000a801
5468
5469 #define REG_A6XX_SP_VS_PRIMITIVE_CNTL 0x0000a802
5470 #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f
5471 #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT 0
A6XX_SP_VS_PRIMITIVE_CNTL_OUT(uint32_t val)5472 static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_OUT(uint32_t val)
5473 {
5474 return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK;
5475 }
5476 #define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0
5477 #define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6
A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)5478 static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)
5479 {
5480 return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK;
5481 }
5482
REG_A6XX_SP_VS_OUT(uint32_t i0)5483 static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
5484
REG_A6XX_SP_VS_OUT_REG(uint32_t i0)5485 static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
5486 #define A6XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff
5487 #define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val)5488 static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
5489 {
5490 return ((val) << A6XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_A_REGID__MASK;
5491 }
5492 #define A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00
5493 #define A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8
A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)5494 static inline uint32_t A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
5495 {
5496 return ((val) << A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
5497 }
5498 #define A6XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000
5499 #define A6XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val)5500 static inline uint32_t A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
5501 {
5502 return ((val) << A6XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_B_REGID__MASK;
5503 }
5504 #define A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000
5505 #define A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24
A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)5506 static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
5507 {
5508 return ((val) << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
5509 }
5510
REG_A6XX_SP_VS_VPC_DST(uint32_t i0)5511 static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; }
5512
REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0)5513 static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; }
5514 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
5515 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)5516 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
5517 {
5518 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
5519 }
5520 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
5521 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)5522 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
5523 {
5524 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
5525 }
5526 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
5527 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)5528 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
5529 {
5530 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
5531 }
5532 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
5533 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)5534 static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
5535 {
5536 return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
5537 }
5538
5539 #define REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET 0x0000a81b
5540
5541 #define REG_A6XX_SP_VS_OBJ_START 0x0000a81c
5542 #define A6XX_SP_VS_OBJ_START__MASK 0xffffffff
5543 #define A6XX_SP_VS_OBJ_START__SHIFT 0
A6XX_SP_VS_OBJ_START(uint32_t val)5544 static inline uint32_t A6XX_SP_VS_OBJ_START(uint32_t val)
5545 {
5546 return ((val) << A6XX_SP_VS_OBJ_START__SHIFT) & A6XX_SP_VS_OBJ_START__MASK;
5547 }
5548
5549 #define REG_A6XX_SP_VS_PVT_MEM_PARAM 0x0000a81e
5550 #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5551 #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)5552 static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5553 {
5554 return ((val >> 9) << A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5555 }
5556 #define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5557 #define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)5558 static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5559 {
5560 return ((val) << A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5561 }
5562
5563 #define REG_A6XX_SP_VS_PVT_MEM_ADDR 0x0000a81f
5564 #define A6XX_SP_VS_PVT_MEM_ADDR__MASK 0xffffffff
5565 #define A6XX_SP_VS_PVT_MEM_ADDR__SHIFT 0
A6XX_SP_VS_PVT_MEM_ADDR(uint32_t val)5566 static inline uint32_t A6XX_SP_VS_PVT_MEM_ADDR(uint32_t val)
5567 {
5568 return ((val) << A6XX_SP_VS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_VS_PVT_MEM_ADDR__MASK;
5569 }
5570
5571 #define REG_A6XX_SP_VS_PVT_MEM_SIZE 0x0000a821
5572 #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
5573 #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)5574 static inline uint32_t A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5575 {
5576 return ((val >> 12) << A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5577 }
5578 #define A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
5579
5580 #define REG_A6XX_SP_VS_TEX_COUNT 0x0000a822
5581
5582 #define REG_A6XX_SP_VS_CONFIG 0x0000a823
5583 #define A6XX_SP_VS_CONFIG_BINDLESS_TEX 0x00000001
5584 #define A6XX_SP_VS_CONFIG_BINDLESS_SAMP 0x00000002
5585 #define A6XX_SP_VS_CONFIG_BINDLESS_IBO 0x00000004
5586 #define A6XX_SP_VS_CONFIG_BINDLESS_UBO 0x00000008
5587 #define A6XX_SP_VS_CONFIG_ENABLED 0x00000100
5588 #define A6XX_SP_VS_CONFIG_NTEX__MASK 0x0001fe00
5589 #define A6XX_SP_VS_CONFIG_NTEX__SHIFT 9
A6XX_SP_VS_CONFIG_NTEX(uint32_t val)5590 static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val)
5591 {
5592 return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK;
5593 }
5594 #define A6XX_SP_VS_CONFIG_NSAMP__MASK 0x003e0000
5595 #define A6XX_SP_VS_CONFIG_NSAMP__SHIFT 17
A6XX_SP_VS_CONFIG_NSAMP(uint32_t val)5596 static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val)
5597 {
5598 return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK;
5599 }
5600 #define A6XX_SP_VS_CONFIG_NIBO__MASK 0x1fc00000
5601 #define A6XX_SP_VS_CONFIG_NIBO__SHIFT 22
A6XX_SP_VS_CONFIG_NIBO(uint32_t val)5602 static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val)
5603 {
5604 return ((val) << A6XX_SP_VS_CONFIG_NIBO__SHIFT) & A6XX_SP_VS_CONFIG_NIBO__MASK;
5605 }
5606
5607 #define REG_A6XX_SP_VS_INSTRLEN 0x0000a824
5608
5609 #define REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET 0x0000a825
5610 #define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff
5611 #define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)5612 static inline uint32_t A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
5613 {
5614 return ((val >> 11) << A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
5615 }
5616
5617 #define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830
5618 #define A6XX_SP_HS_CTRL_REG0_EARLYPREAMBLE 0x00100000
5619 #define A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK 0x00000001
5620 #define A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT 0
A6XX_SP_HS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)5621 static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5622 {
5623 return ((val) << A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK;
5624 }
5625 #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5626 #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)5627 static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5628 {
5629 return ((val) << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5630 }
5631 #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
5632 #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)5633 static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5634 {
5635 return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5636 }
5637 #define A6XX_SP_HS_CTRL_REG0_UNK13 0x00002000
5638 #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5639 #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 14
A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)5640 static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5641 {
5642 return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK;
5643 }
5644
5645 #define REG_A6XX_SP_HS_WAVE_INPUT_SIZE 0x0000a831
5646
5647 #define REG_A6XX_SP_HS_BRANCH_COND 0x0000a832
5648
5649 #define REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET 0x0000a833
5650
5651 #define REG_A6XX_SP_HS_OBJ_START 0x0000a834
5652 #define A6XX_SP_HS_OBJ_START__MASK 0xffffffff
5653 #define A6XX_SP_HS_OBJ_START__SHIFT 0
A6XX_SP_HS_OBJ_START(uint32_t val)5654 static inline uint32_t A6XX_SP_HS_OBJ_START(uint32_t val)
5655 {
5656 return ((val) << A6XX_SP_HS_OBJ_START__SHIFT) & A6XX_SP_HS_OBJ_START__MASK;
5657 }
5658
5659 #define REG_A6XX_SP_HS_PVT_MEM_PARAM 0x0000a836
5660 #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5661 #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)5662 static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5663 {
5664 return ((val >> 9) << A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5665 }
5666 #define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5667 #define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)5668 static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5669 {
5670 return ((val) << A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5671 }
5672
5673 #define REG_A6XX_SP_HS_PVT_MEM_ADDR 0x0000a837
5674 #define A6XX_SP_HS_PVT_MEM_ADDR__MASK 0xffffffff
5675 #define A6XX_SP_HS_PVT_MEM_ADDR__SHIFT 0
A6XX_SP_HS_PVT_MEM_ADDR(uint32_t val)5676 static inline uint32_t A6XX_SP_HS_PVT_MEM_ADDR(uint32_t val)
5677 {
5678 return ((val) << A6XX_SP_HS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_HS_PVT_MEM_ADDR__MASK;
5679 }
5680
5681 #define REG_A6XX_SP_HS_PVT_MEM_SIZE 0x0000a839
5682 #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
5683 #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)5684 static inline uint32_t A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5685 {
5686 return ((val >> 12) << A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5687 }
5688 #define A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
5689
5690 #define REG_A6XX_SP_HS_TEX_COUNT 0x0000a83a
5691
5692 #define REG_A6XX_SP_HS_CONFIG 0x0000a83b
5693 #define A6XX_SP_HS_CONFIG_BINDLESS_TEX 0x00000001
5694 #define A6XX_SP_HS_CONFIG_BINDLESS_SAMP 0x00000002
5695 #define A6XX_SP_HS_CONFIG_BINDLESS_IBO 0x00000004
5696 #define A6XX_SP_HS_CONFIG_BINDLESS_UBO 0x00000008
5697 #define A6XX_SP_HS_CONFIG_ENABLED 0x00000100
5698 #define A6XX_SP_HS_CONFIG_NTEX__MASK 0x0001fe00
5699 #define A6XX_SP_HS_CONFIG_NTEX__SHIFT 9
A6XX_SP_HS_CONFIG_NTEX(uint32_t val)5700 static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val)
5701 {
5702 return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK;
5703 }
5704 #define A6XX_SP_HS_CONFIG_NSAMP__MASK 0x003e0000
5705 #define A6XX_SP_HS_CONFIG_NSAMP__SHIFT 17
A6XX_SP_HS_CONFIG_NSAMP(uint32_t val)5706 static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val)
5707 {
5708 return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK;
5709 }
5710 #define A6XX_SP_HS_CONFIG_NIBO__MASK 0x1fc00000
5711 #define A6XX_SP_HS_CONFIG_NIBO__SHIFT 22
A6XX_SP_HS_CONFIG_NIBO(uint32_t val)5712 static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val)
5713 {
5714 return ((val) << A6XX_SP_HS_CONFIG_NIBO__SHIFT) & A6XX_SP_HS_CONFIG_NIBO__MASK;
5715 }
5716
5717 #define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c
5718
5719 #define REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET 0x0000a83d
5720 #define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff
5721 #define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)5722 static inline uint32_t A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
5723 {
5724 return ((val >> 11) << A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
5725 }
5726
5727 #define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840
5728 #define A6XX_SP_DS_CTRL_REG0_EARLYPREAMBLE 0x00100000
5729 #define A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK 0x00000001
5730 #define A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT 0
A6XX_SP_DS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)5731 static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5732 {
5733 return ((val) << A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK;
5734 }
5735 #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5736 #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)5737 static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5738 {
5739 return ((val) << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5740 }
5741 #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
5742 #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)5743 static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5744 {
5745 return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5746 }
5747 #define A6XX_SP_DS_CTRL_REG0_UNK13 0x00002000
5748 #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5749 #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 14
A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)5750 static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5751 {
5752 return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK;
5753 }
5754
5755 #define REG_A6XX_SP_DS_BRANCH_COND 0x0000a841
5756
5757 #define REG_A6XX_SP_DS_PRIMITIVE_CNTL 0x0000a842
5758 #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f
5759 #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT 0
A6XX_SP_DS_PRIMITIVE_CNTL_OUT(uint32_t val)5760 static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_OUT(uint32_t val)
5761 {
5762 return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK;
5763 }
5764 #define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0
5765 #define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6
A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)5766 static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)
5767 {
5768 return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK;
5769 }
5770
REG_A6XX_SP_DS_OUT(uint32_t i0)5771 static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
5772
REG_A6XX_SP_DS_OUT_REG(uint32_t i0)5773 static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
5774 #define A6XX_SP_DS_OUT_REG_A_REGID__MASK 0x000000ff
5775 #define A6XX_SP_DS_OUT_REG_A_REGID__SHIFT 0
A6XX_SP_DS_OUT_REG_A_REGID(uint32_t val)5776 static inline uint32_t A6XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
5777 {
5778 return ((val) << A6XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_A_REGID__MASK;
5779 }
5780 #define A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00000f00
5781 #define A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 8
A6XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)5782 static inline uint32_t A6XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)
5783 {
5784 return ((val) << A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK;
5785 }
5786 #define A6XX_SP_DS_OUT_REG_B_REGID__MASK 0x00ff0000
5787 #define A6XX_SP_DS_OUT_REG_B_REGID__SHIFT 16
A6XX_SP_DS_OUT_REG_B_REGID(uint32_t val)5788 static inline uint32_t A6XX_SP_DS_OUT_REG_B_REGID(uint32_t val)
5789 {
5790 return ((val) << A6XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_B_REGID__MASK;
5791 }
5792 #define A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x0f000000
5793 #define A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 24
A6XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)5794 static inline uint32_t A6XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)
5795 {
5796 return ((val) << A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK;
5797 }
5798
REG_A6XX_SP_DS_VPC_DST(uint32_t i0)5799 static inline uint32_t REG_A6XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000a853 + 0x1*i0; }
5800
REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0)5801 static inline uint32_t REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000a853 + 0x1*i0; }
5802 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
5803 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0
A6XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)5804 static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)
5805 {
5806 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK;
5807 }
5808 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
5809 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8
A6XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)5810 static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)
5811 {
5812 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK;
5813 }
5814 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
5815 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16
A6XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)5816 static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)
5817 {
5818 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK;
5819 }
5820 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
5821 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24
A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)5822 static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
5823 {
5824 return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
5825 }
5826
5827 #define REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET 0x0000a85b
5828
5829 #define REG_A6XX_SP_DS_OBJ_START 0x0000a85c
5830 #define A6XX_SP_DS_OBJ_START__MASK 0xffffffff
5831 #define A6XX_SP_DS_OBJ_START__SHIFT 0
A6XX_SP_DS_OBJ_START(uint32_t val)5832 static inline uint32_t A6XX_SP_DS_OBJ_START(uint32_t val)
5833 {
5834 return ((val) << A6XX_SP_DS_OBJ_START__SHIFT) & A6XX_SP_DS_OBJ_START__MASK;
5835 }
5836
5837 #define REG_A6XX_SP_DS_PVT_MEM_PARAM 0x0000a85e
5838 #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
5839 #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)5840 static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
5841 {
5842 return ((val >> 9) << A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
5843 }
5844 #define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
5845 #define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)5846 static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
5847 {
5848 return ((val) << A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
5849 }
5850
5851 #define REG_A6XX_SP_DS_PVT_MEM_ADDR 0x0000a85f
5852 #define A6XX_SP_DS_PVT_MEM_ADDR__MASK 0xffffffff
5853 #define A6XX_SP_DS_PVT_MEM_ADDR__SHIFT 0
A6XX_SP_DS_PVT_MEM_ADDR(uint32_t val)5854 static inline uint32_t A6XX_SP_DS_PVT_MEM_ADDR(uint32_t val)
5855 {
5856 return ((val) << A6XX_SP_DS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_DS_PVT_MEM_ADDR__MASK;
5857 }
5858
5859 #define REG_A6XX_SP_DS_PVT_MEM_SIZE 0x0000a861
5860 #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
5861 #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)5862 static inline uint32_t A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
5863 {
5864 return ((val >> 12) << A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
5865 }
5866 #define A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
5867
5868 #define REG_A6XX_SP_DS_TEX_COUNT 0x0000a862
5869
5870 #define REG_A6XX_SP_DS_CONFIG 0x0000a863
5871 #define A6XX_SP_DS_CONFIG_BINDLESS_TEX 0x00000001
5872 #define A6XX_SP_DS_CONFIG_BINDLESS_SAMP 0x00000002
5873 #define A6XX_SP_DS_CONFIG_BINDLESS_IBO 0x00000004
5874 #define A6XX_SP_DS_CONFIG_BINDLESS_UBO 0x00000008
5875 #define A6XX_SP_DS_CONFIG_ENABLED 0x00000100
5876 #define A6XX_SP_DS_CONFIG_NTEX__MASK 0x0001fe00
5877 #define A6XX_SP_DS_CONFIG_NTEX__SHIFT 9
A6XX_SP_DS_CONFIG_NTEX(uint32_t val)5878 static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val)
5879 {
5880 return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK;
5881 }
5882 #define A6XX_SP_DS_CONFIG_NSAMP__MASK 0x003e0000
5883 #define A6XX_SP_DS_CONFIG_NSAMP__SHIFT 17
A6XX_SP_DS_CONFIG_NSAMP(uint32_t val)5884 static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val)
5885 {
5886 return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK;
5887 }
5888 #define A6XX_SP_DS_CONFIG_NIBO__MASK 0x1fc00000
5889 #define A6XX_SP_DS_CONFIG_NIBO__SHIFT 22
A6XX_SP_DS_CONFIG_NIBO(uint32_t val)5890 static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val)
5891 {
5892 return ((val) << A6XX_SP_DS_CONFIG_NIBO__SHIFT) & A6XX_SP_DS_CONFIG_NIBO__MASK;
5893 }
5894
5895 #define REG_A6XX_SP_DS_INSTRLEN 0x0000a864
5896
5897 #define REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET 0x0000a865
5898 #define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff
5899 #define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)5900 static inline uint32_t A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
5901 {
5902 return ((val >> 11) << A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
5903 }
5904
5905 #define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870
5906 #define A6XX_SP_GS_CTRL_REG0_EARLYPREAMBLE 0x00100000
5907 #define A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK 0x00000001
5908 #define A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT 0
A6XX_SP_GS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)5909 static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
5910 {
5911 return ((val) << A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK;
5912 }
5913 #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
5914 #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)5915 static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
5916 {
5917 return ((val) << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
5918 }
5919 #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
5920 #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)5921 static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
5922 {
5923 return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
5924 }
5925 #define A6XX_SP_GS_CTRL_REG0_UNK13 0x00002000
5926 #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
5927 #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 14
A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)5928 static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)
5929 {
5930 return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK;
5931 }
5932
5933 #define REG_A6XX_SP_GS_PRIM_SIZE 0x0000a871
5934
5935 #define REG_A6XX_SP_GS_BRANCH_COND 0x0000a872
5936
5937 #define REG_A6XX_SP_GS_PRIMITIVE_CNTL 0x0000a873
5938 #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f
5939 #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT 0
A6XX_SP_GS_PRIMITIVE_CNTL_OUT(uint32_t val)5940 static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_OUT(uint32_t val)
5941 {
5942 return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK;
5943 }
5944 #define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0
5945 #define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6
A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)5946 static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)
5947 {
5948 return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK;
5949 }
5950
REG_A6XX_SP_GS_OUT(uint32_t i0)5951 static inline uint32_t REG_A6XX_SP_GS_OUT(uint32_t i0) { return 0x0000a874 + 0x1*i0; }
5952
REG_A6XX_SP_GS_OUT_REG(uint32_t i0)5953 static inline uint32_t REG_A6XX_SP_GS_OUT_REG(uint32_t i0) { return 0x0000a874 + 0x1*i0; }
5954 #define A6XX_SP_GS_OUT_REG_A_REGID__MASK 0x000000ff
5955 #define A6XX_SP_GS_OUT_REG_A_REGID__SHIFT 0
A6XX_SP_GS_OUT_REG_A_REGID(uint32_t val)5956 static inline uint32_t A6XX_SP_GS_OUT_REG_A_REGID(uint32_t val)
5957 {
5958 return ((val) << A6XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_A_REGID__MASK;
5959 }
5960 #define A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00000f00
5961 #define A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 8
A6XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)5962 static inline uint32_t A6XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)
5963 {
5964 return ((val) << A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK;
5965 }
5966 #define A6XX_SP_GS_OUT_REG_B_REGID__MASK 0x00ff0000
5967 #define A6XX_SP_GS_OUT_REG_B_REGID__SHIFT 16
A6XX_SP_GS_OUT_REG_B_REGID(uint32_t val)5968 static inline uint32_t A6XX_SP_GS_OUT_REG_B_REGID(uint32_t val)
5969 {
5970 return ((val) << A6XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_B_REGID__MASK;
5971 }
5972 #define A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x0f000000
5973 #define A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 24
A6XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)5974 static inline uint32_t A6XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)
5975 {
5976 return ((val) << A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK;
5977 }
5978
REG_A6XX_SP_GS_VPC_DST(uint32_t i0)5979 static inline uint32_t REG_A6XX_SP_GS_VPC_DST(uint32_t i0) { return 0x0000a884 + 0x1*i0; }
5980
REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0)5981 static inline uint32_t REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x0000a884 + 0x1*i0; }
5982 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
5983 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0
A6XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)5984 static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)
5985 {
5986 return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK;
5987 }
5988 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
5989 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8
A6XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)5990 static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)
5991 {
5992 return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK;
5993 }
5994 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
5995 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16
A6XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)5996 static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)
5997 {
5998 return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK;
5999 }
6000 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
6001 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24
A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)6002 static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)
6003 {
6004 return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;
6005 }
6006
6007 #define REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET 0x0000a88c
6008
6009 #define REG_A6XX_SP_GS_OBJ_START 0x0000a88d
6010 #define A6XX_SP_GS_OBJ_START__MASK 0xffffffff
6011 #define A6XX_SP_GS_OBJ_START__SHIFT 0
A6XX_SP_GS_OBJ_START(uint32_t val)6012 static inline uint32_t A6XX_SP_GS_OBJ_START(uint32_t val)
6013 {
6014 return ((val) << A6XX_SP_GS_OBJ_START__SHIFT) & A6XX_SP_GS_OBJ_START__MASK;
6015 }
6016
6017 #define REG_A6XX_SP_GS_PVT_MEM_PARAM 0x0000a88f
6018 #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
6019 #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)6020 static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
6021 {
6022 return ((val >> 9) << A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
6023 }
6024 #define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
6025 #define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)6026 static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
6027 {
6028 return ((val) << A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
6029 }
6030
6031 #define REG_A6XX_SP_GS_PVT_MEM_ADDR 0x0000a890
6032 #define A6XX_SP_GS_PVT_MEM_ADDR__MASK 0xffffffff
6033 #define A6XX_SP_GS_PVT_MEM_ADDR__SHIFT 0
A6XX_SP_GS_PVT_MEM_ADDR(uint32_t val)6034 static inline uint32_t A6XX_SP_GS_PVT_MEM_ADDR(uint32_t val)
6035 {
6036 return ((val) << A6XX_SP_GS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_GS_PVT_MEM_ADDR__MASK;
6037 }
6038
6039 #define REG_A6XX_SP_GS_PVT_MEM_SIZE 0x0000a892
6040 #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
6041 #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)6042 static inline uint32_t A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
6043 {
6044 return ((val >> 12) << A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
6045 }
6046 #define A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
6047
6048 #define REG_A6XX_SP_GS_TEX_COUNT 0x0000a893
6049
6050 #define REG_A6XX_SP_GS_CONFIG 0x0000a894
6051 #define A6XX_SP_GS_CONFIG_BINDLESS_TEX 0x00000001
6052 #define A6XX_SP_GS_CONFIG_BINDLESS_SAMP 0x00000002
6053 #define A6XX_SP_GS_CONFIG_BINDLESS_IBO 0x00000004
6054 #define A6XX_SP_GS_CONFIG_BINDLESS_UBO 0x00000008
6055 #define A6XX_SP_GS_CONFIG_ENABLED 0x00000100
6056 #define A6XX_SP_GS_CONFIG_NTEX__MASK 0x0001fe00
6057 #define A6XX_SP_GS_CONFIG_NTEX__SHIFT 9
A6XX_SP_GS_CONFIG_NTEX(uint32_t val)6058 static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val)
6059 {
6060 return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK;
6061 }
6062 #define A6XX_SP_GS_CONFIG_NSAMP__MASK 0x003e0000
6063 #define A6XX_SP_GS_CONFIG_NSAMP__SHIFT 17
A6XX_SP_GS_CONFIG_NSAMP(uint32_t val)6064 static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val)
6065 {
6066 return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK;
6067 }
6068 #define A6XX_SP_GS_CONFIG_NIBO__MASK 0x1fc00000
6069 #define A6XX_SP_GS_CONFIG_NIBO__SHIFT 22
A6XX_SP_GS_CONFIG_NIBO(uint32_t val)6070 static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val)
6071 {
6072 return ((val) << A6XX_SP_GS_CONFIG_NIBO__SHIFT) & A6XX_SP_GS_CONFIG_NIBO__MASK;
6073 }
6074
6075 #define REG_A6XX_SP_GS_INSTRLEN 0x0000a895
6076
6077 #define REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET 0x0000a896
6078 #define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff
6079 #define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)6080 static inline uint32_t A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
6081 {
6082 return ((val >> 11) << A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
6083 }
6084
6085 #define REG_A6XX_SP_VS_TEX_SAMP 0x0000a8a0
6086 #define A6XX_SP_VS_TEX_SAMP__MASK 0xffffffff
6087 #define A6XX_SP_VS_TEX_SAMP__SHIFT 0
A6XX_SP_VS_TEX_SAMP(uint32_t val)6088 static inline uint32_t A6XX_SP_VS_TEX_SAMP(uint32_t val)
6089 {
6090 return ((val) << A6XX_SP_VS_TEX_SAMP__SHIFT) & A6XX_SP_VS_TEX_SAMP__MASK;
6091 }
6092
6093 #define REG_A6XX_SP_HS_TEX_SAMP 0x0000a8a2
6094 #define A6XX_SP_HS_TEX_SAMP__MASK 0xffffffff
6095 #define A6XX_SP_HS_TEX_SAMP__SHIFT 0
A6XX_SP_HS_TEX_SAMP(uint32_t val)6096 static inline uint32_t A6XX_SP_HS_TEX_SAMP(uint32_t val)
6097 {
6098 return ((val) << A6XX_SP_HS_TEX_SAMP__SHIFT) & A6XX_SP_HS_TEX_SAMP__MASK;
6099 }
6100
6101 #define REG_A6XX_SP_DS_TEX_SAMP 0x0000a8a4
6102 #define A6XX_SP_DS_TEX_SAMP__MASK 0xffffffff
6103 #define A6XX_SP_DS_TEX_SAMP__SHIFT 0
A6XX_SP_DS_TEX_SAMP(uint32_t val)6104 static inline uint32_t A6XX_SP_DS_TEX_SAMP(uint32_t val)
6105 {
6106 return ((val) << A6XX_SP_DS_TEX_SAMP__SHIFT) & A6XX_SP_DS_TEX_SAMP__MASK;
6107 }
6108
6109 #define REG_A6XX_SP_GS_TEX_SAMP 0x0000a8a6
6110 #define A6XX_SP_GS_TEX_SAMP__MASK 0xffffffff
6111 #define A6XX_SP_GS_TEX_SAMP__SHIFT 0
A6XX_SP_GS_TEX_SAMP(uint32_t val)6112 static inline uint32_t A6XX_SP_GS_TEX_SAMP(uint32_t val)
6113 {
6114 return ((val) << A6XX_SP_GS_TEX_SAMP__SHIFT) & A6XX_SP_GS_TEX_SAMP__MASK;
6115 }
6116
6117 #define REG_A6XX_SP_VS_TEX_CONST 0x0000a8a8
6118 #define A6XX_SP_VS_TEX_CONST__MASK 0xffffffff
6119 #define A6XX_SP_VS_TEX_CONST__SHIFT 0
A6XX_SP_VS_TEX_CONST(uint32_t val)6120 static inline uint32_t A6XX_SP_VS_TEX_CONST(uint32_t val)
6121 {
6122 return ((val) << A6XX_SP_VS_TEX_CONST__SHIFT) & A6XX_SP_VS_TEX_CONST__MASK;
6123 }
6124
6125 #define REG_A6XX_SP_HS_TEX_CONST 0x0000a8aa
6126 #define A6XX_SP_HS_TEX_CONST__MASK 0xffffffff
6127 #define A6XX_SP_HS_TEX_CONST__SHIFT 0
A6XX_SP_HS_TEX_CONST(uint32_t val)6128 static inline uint32_t A6XX_SP_HS_TEX_CONST(uint32_t val)
6129 {
6130 return ((val) << A6XX_SP_HS_TEX_CONST__SHIFT) & A6XX_SP_HS_TEX_CONST__MASK;
6131 }
6132
6133 #define REG_A6XX_SP_DS_TEX_CONST 0x0000a8ac
6134 #define A6XX_SP_DS_TEX_CONST__MASK 0xffffffff
6135 #define A6XX_SP_DS_TEX_CONST__SHIFT 0
A6XX_SP_DS_TEX_CONST(uint32_t val)6136 static inline uint32_t A6XX_SP_DS_TEX_CONST(uint32_t val)
6137 {
6138 return ((val) << A6XX_SP_DS_TEX_CONST__SHIFT) & A6XX_SP_DS_TEX_CONST__MASK;
6139 }
6140
6141 #define REG_A6XX_SP_GS_TEX_CONST 0x0000a8ae
6142 #define A6XX_SP_GS_TEX_CONST__MASK 0xffffffff
6143 #define A6XX_SP_GS_TEX_CONST__SHIFT 0
A6XX_SP_GS_TEX_CONST(uint32_t val)6144 static inline uint32_t A6XX_SP_GS_TEX_CONST(uint32_t val)
6145 {
6146 return ((val) << A6XX_SP_GS_TEX_CONST__SHIFT) & A6XX_SP_GS_TEX_CONST__MASK;
6147 }
6148
6149 #define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980
6150 #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
6151 #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val)6152 static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val)
6153 {
6154 return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
6155 }
6156 #define A6XX_SP_FS_CTRL_REG0_UNK21 0x00200000
6157 #define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000
6158 #define A6XX_SP_FS_CTRL_REG0_DIFF_FINE 0x00800000
6159 #define A6XX_SP_FS_CTRL_REG0_UNK24 0x01000000
6160 #define A6XX_SP_FS_CTRL_REG0_UNK25 0x02000000
6161 #define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000
6162 #define A6XX_SP_FS_CTRL_REG0_UNK27 0x08000000
6163 #define A6XX_SP_FS_CTRL_REG0_EARLYPREAMBLE 0x10000000
6164 #define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000
6165 #define A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001
6166 #define A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0
A6XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)6167 static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
6168 {
6169 return ((val) << A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
6170 }
6171 #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
6172 #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)6173 static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
6174 {
6175 return ((val) << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
6176 }
6177 #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
6178 #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)6179 static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
6180 {
6181 return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
6182 }
6183 #define A6XX_SP_FS_CTRL_REG0_UNK13 0x00002000
6184 #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
6185 #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 14
A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)6186 static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
6187 {
6188 return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK;
6189 }
6190
6191 #define REG_A6XX_SP_FS_BRANCH_COND 0x0000a981
6192
6193 #define REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET 0x0000a982
6194
6195 #define REG_A6XX_SP_FS_OBJ_START 0x0000a983
6196 #define A6XX_SP_FS_OBJ_START__MASK 0xffffffff
6197 #define A6XX_SP_FS_OBJ_START__SHIFT 0
A6XX_SP_FS_OBJ_START(uint32_t val)6198 static inline uint32_t A6XX_SP_FS_OBJ_START(uint32_t val)
6199 {
6200 return ((val) << A6XX_SP_FS_OBJ_START__SHIFT) & A6XX_SP_FS_OBJ_START__MASK;
6201 }
6202
6203 #define REG_A6XX_SP_FS_PVT_MEM_PARAM 0x0000a985
6204 #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
6205 #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)6206 static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
6207 {
6208 return ((val >> 9) << A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
6209 }
6210 #define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
6211 #define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)6212 static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
6213 {
6214 return ((val) << A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
6215 }
6216
6217 #define REG_A6XX_SP_FS_PVT_MEM_ADDR 0x0000a986
6218 #define A6XX_SP_FS_PVT_MEM_ADDR__MASK 0xffffffff
6219 #define A6XX_SP_FS_PVT_MEM_ADDR__SHIFT 0
A6XX_SP_FS_PVT_MEM_ADDR(uint32_t val)6220 static inline uint32_t A6XX_SP_FS_PVT_MEM_ADDR(uint32_t val)
6221 {
6222 return ((val) << A6XX_SP_FS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_FS_PVT_MEM_ADDR__MASK;
6223 }
6224
6225 #define REG_A6XX_SP_FS_PVT_MEM_SIZE 0x0000a988
6226 #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
6227 #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)6228 static inline uint32_t A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
6229 {
6230 return ((val >> 12) << A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
6231 }
6232 #define A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
6233
6234 #define REG_A6XX_SP_BLEND_CNTL 0x0000a989
6235 #define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
6236 #define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
A6XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val)6237 static inline uint32_t A6XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
6238 {
6239 return ((val) << A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK;
6240 }
6241 #define A6XX_SP_BLEND_CNTL_UNK8 0x00000100
6242 #define A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200
6243 #define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
6244
6245 #define REG_A6XX_SP_SRGB_CNTL 0x0000a98a
6246 #define A6XX_SP_SRGB_CNTL_SRGB_MRT0 0x00000001
6247 #define A6XX_SP_SRGB_CNTL_SRGB_MRT1 0x00000002
6248 #define A6XX_SP_SRGB_CNTL_SRGB_MRT2 0x00000004
6249 #define A6XX_SP_SRGB_CNTL_SRGB_MRT3 0x00000008
6250 #define A6XX_SP_SRGB_CNTL_SRGB_MRT4 0x00000010
6251 #define A6XX_SP_SRGB_CNTL_SRGB_MRT5 0x00000020
6252 #define A6XX_SP_SRGB_CNTL_SRGB_MRT6 0x00000040
6253 #define A6XX_SP_SRGB_CNTL_SRGB_MRT7 0x00000080
6254
6255 #define REG_A6XX_SP_FS_RENDER_COMPONENTS 0x0000a98b
6256 #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK 0x0000000f
6257 #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT 0
A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val)6258 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val)
6259 {
6260 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK;
6261 }
6262 #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK 0x000000f0
6263 #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT 4
A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val)6264 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val)
6265 {
6266 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK;
6267 }
6268 #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK 0x00000f00
6269 #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT 8
A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val)6270 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val)
6271 {
6272 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK;
6273 }
6274 #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK 0x0000f000
6275 #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT 12
A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val)6276 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val)
6277 {
6278 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK;
6279 }
6280 #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK 0x000f0000
6281 #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT 16
A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val)6282 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val)
6283 {
6284 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK;
6285 }
6286 #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK 0x00f00000
6287 #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT 20
A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val)6288 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val)
6289 {
6290 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK;
6291 }
6292 #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK 0x0f000000
6293 #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT 24
A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val)6294 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val)
6295 {
6296 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK;
6297 }
6298 #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK 0xf0000000
6299 #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT 28
A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val)6300 static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val)
6301 {
6302 return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK;
6303 }
6304
6305 #define REG_A6XX_SP_FS_OUTPUT_CNTL0 0x0000a98c
6306 #define A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001
6307 #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK 0x0000ff00
6308 #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT 8
A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val)6309 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val)
6310 {
6311 return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK;
6312 }
6313 #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK 0x00ff0000
6314 #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT 16
A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(uint32_t val)6315 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(uint32_t val)
6316 {
6317 return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK;
6318 }
6319 #define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK 0xff000000
6320 #define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT 24
A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(uint32_t val)6321 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(uint32_t val)
6322 {
6323 return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK;
6324 }
6325
6326 #define REG_A6XX_SP_FS_OUTPUT_CNTL1 0x0000a98d
6327 #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f
6328 #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT 0
A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val)6329 static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val)
6330 {
6331 return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK;
6332 }
6333
REG_A6XX_SP_FS_OUTPUT(uint32_t i0)6334 static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
6335
REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0)6336 static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
6337 #define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff
6338 #define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0
A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)6339 static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
6340 {
6341 return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK;
6342 }
6343 #define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100
6344
REG_A6XX_SP_FS_MRT(uint32_t i0)6345 static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
6346
REG_A6XX_SP_FS_MRT_REG(uint32_t i0)6347 static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
6348 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff
6349 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0
A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val)6350 static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val)
6351 {
6352 return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
6353 }
6354 #define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100
6355 #define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200
6356 #define A6XX_SP_FS_MRT_REG_UNK10 0x00000400
6357
6358 #define REG_A6XX_SP_FS_PREFETCH_CNTL 0x0000a99e
6359 #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK 0x00000007
6360 #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT 0
A6XX_SP_FS_PREFETCH_CNTL_COUNT(uint32_t val)6361 static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_COUNT(uint32_t val)
6362 {
6363 return ((val) << A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK;
6364 }
6365 #define A6XX_SP_FS_PREFETCH_CNTL_IJ_WRITE_DISABLE 0x00000008
6366 #define A6XX_SP_FS_PREFETCH_CNTL_UNK4 0x00000010
6367 #define A6XX_SP_FS_PREFETCH_CNTL_WRITE_COLOR_TO_OUTPUT 0x00000020
6368 #define A6XX_SP_FS_PREFETCH_CNTL_UNK6__MASK 0x00007fc0
6369 #define A6XX_SP_FS_PREFETCH_CNTL_UNK6__SHIFT 6
A6XX_SP_FS_PREFETCH_CNTL_UNK6(uint32_t val)6370 static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK6(uint32_t val)
6371 {
6372 return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK6__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK6__MASK;
6373 }
6374
REG_A6XX_SP_FS_PREFETCH(uint32_t i0)6375 static inline uint32_t REG_A6XX_SP_FS_PREFETCH(uint32_t i0) { return 0x0000a99f + 0x1*i0; }
6376
REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0)6377 static inline uint32_t REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; }
6378 #define A6XX_SP_FS_PREFETCH_CMD_SRC__MASK 0x0000007f
6379 #define A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT 0
A6XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val)6380 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val)
6381 {
6382 return ((val) << A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SRC__MASK;
6383 }
6384 #define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK 0x00000780
6385 #define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT 7
A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val)6386 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val)
6387 {
6388 return ((val) << A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK;
6389 }
6390 #define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK 0x0000f800
6391 #define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT 11
A6XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val)6392 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val)
6393 {
6394 return ((val) << A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK;
6395 }
6396 #define A6XX_SP_FS_PREFETCH_CMD_DST__MASK 0x003f0000
6397 #define A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT 16
A6XX_SP_FS_PREFETCH_CMD_DST(uint32_t val)6398 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_DST(uint32_t val)
6399 {
6400 return ((val) << A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_DST__MASK;
6401 }
6402 #define A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK 0x03c00000
6403 #define A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT 22
A6XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val)6404 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val)
6405 {
6406 return ((val) << A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK;
6407 }
6408 #define A6XX_SP_FS_PREFETCH_CMD_HALF 0x04000000
6409 #define A6XX_SP_FS_PREFETCH_CMD_UNK27 0x08000000
6410 #define A6XX_SP_FS_PREFETCH_CMD_BINDLESS 0x10000000
6411 #define A6XX_SP_FS_PREFETCH_CMD_CMD__MASK 0xe0000000
6412 #define A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT 29
A6XX_SP_FS_PREFETCH_CMD_CMD(enum a6xx_tex_prefetch_cmd val)6413 static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_CMD(enum a6xx_tex_prefetch_cmd val)
6414 {
6415 return ((val) << A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_CMD__MASK;
6416 }
6417
REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0)6418 static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
6419
REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0)6420 static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
6421 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK 0x0000ffff
6422 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT 0
A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val)6423 static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val)
6424 {
6425 return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK;
6426 }
6427 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK 0xffff0000
6428 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT 16
A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val)6429 static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val)
6430 {
6431 return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK;
6432 }
6433
6434 #define REG_A6XX_SP_FS_TEX_COUNT 0x0000a9a7
6435
6436 #define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8
6437
6438 #define REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET 0x0000a9a9
6439 #define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff
6440 #define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)6441 static inline uint32_t A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
6442 {
6443 return ((val >> 11) << A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
6444 }
6445
6446 #define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0
6447 #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000
6448 #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20
A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val)6449 static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val)
6450 {
6451 return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
6452 }
6453 #define A6XX_SP_CS_CTRL_REG0_UNK21 0x00200000
6454 #define A6XX_SP_CS_CTRL_REG0_UNK22 0x00400000
6455 #define A6XX_SP_CS_CTRL_REG0_EARLYPREAMBLE 0x00800000
6456 #define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000
6457 #define A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK 0x00000001
6458 #define A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT 0
A6XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)6459 static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
6460 {
6461 return ((val) << A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK;
6462 }
6463 #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
6464 #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)6465 static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
6466 {
6467 return ((val) << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
6468 }
6469 #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
6470 #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)6471 static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
6472 {
6473 return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
6474 }
6475 #define A6XX_SP_CS_CTRL_REG0_UNK13 0x00002000
6476 #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
6477 #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 14
A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)6478 static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
6479 {
6480 return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
6481 }
6482
6483 #define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1
6484 #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK 0x0000001f
6485 #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT 0
A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(uint32_t val)6486 static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(uint32_t val)
6487 {
6488 return ((val) << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK;
6489 }
6490 #define A6XX_SP_CS_UNKNOWN_A9B1_UNK5 0x00000020
6491 #define A6XX_SP_CS_UNKNOWN_A9B1_UNK6 0x00000040
6492
6493 #define REG_A6XX_SP_CS_BRANCH_COND 0x0000a9b2
6494
6495 #define REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET 0x0000a9b3
6496
6497 #define REG_A6XX_SP_CS_OBJ_START 0x0000a9b4
6498 #define A6XX_SP_CS_OBJ_START__MASK 0xffffffff
6499 #define A6XX_SP_CS_OBJ_START__SHIFT 0
A6XX_SP_CS_OBJ_START(uint32_t val)6500 static inline uint32_t A6XX_SP_CS_OBJ_START(uint32_t val)
6501 {
6502 return ((val) << A6XX_SP_CS_OBJ_START__SHIFT) & A6XX_SP_CS_OBJ_START__MASK;
6503 }
6504
6505 #define REG_A6XX_SP_CS_PVT_MEM_PARAM 0x0000a9b6
6506 #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
6507 #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)6508 static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
6509 {
6510 return ((val >> 9) << A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
6511 }
6512 #define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
6513 #define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)6514 static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
6515 {
6516 return ((val) << A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
6517 }
6518
6519 #define REG_A6XX_SP_CS_PVT_MEM_ADDR 0x0000a9b7
6520 #define A6XX_SP_CS_PVT_MEM_ADDR__MASK 0xffffffff
6521 #define A6XX_SP_CS_PVT_MEM_ADDR__SHIFT 0
A6XX_SP_CS_PVT_MEM_ADDR(uint32_t val)6522 static inline uint32_t A6XX_SP_CS_PVT_MEM_ADDR(uint32_t val)
6523 {
6524 return ((val) << A6XX_SP_CS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_CS_PVT_MEM_ADDR__MASK;
6525 }
6526
6527 #define REG_A6XX_SP_CS_PVT_MEM_SIZE 0x0000a9b9
6528 #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
6529 #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)6530 static inline uint32_t A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
6531 {
6532 return ((val >> 12) << A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
6533 }
6534 #define A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
6535
6536 #define REG_A6XX_SP_CS_TEX_COUNT 0x0000a9ba
6537
6538 #define REG_A6XX_SP_CS_CONFIG 0x0000a9bb
6539 #define A6XX_SP_CS_CONFIG_BINDLESS_TEX 0x00000001
6540 #define A6XX_SP_CS_CONFIG_BINDLESS_SAMP 0x00000002
6541 #define A6XX_SP_CS_CONFIG_BINDLESS_IBO 0x00000004
6542 #define A6XX_SP_CS_CONFIG_BINDLESS_UBO 0x00000008
6543 #define A6XX_SP_CS_CONFIG_ENABLED 0x00000100
6544 #define A6XX_SP_CS_CONFIG_NTEX__MASK 0x0001fe00
6545 #define A6XX_SP_CS_CONFIG_NTEX__SHIFT 9
A6XX_SP_CS_CONFIG_NTEX(uint32_t val)6546 static inline uint32_t A6XX_SP_CS_CONFIG_NTEX(uint32_t val)
6547 {
6548 return ((val) << A6XX_SP_CS_CONFIG_NTEX__SHIFT) & A6XX_SP_CS_CONFIG_NTEX__MASK;
6549 }
6550 #define A6XX_SP_CS_CONFIG_NSAMP__MASK 0x003e0000
6551 #define A6XX_SP_CS_CONFIG_NSAMP__SHIFT 17
A6XX_SP_CS_CONFIG_NSAMP(uint32_t val)6552 static inline uint32_t A6XX_SP_CS_CONFIG_NSAMP(uint32_t val)
6553 {
6554 return ((val) << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK;
6555 }
6556 #define A6XX_SP_CS_CONFIG_NIBO__MASK 0x1fc00000
6557 #define A6XX_SP_CS_CONFIG_NIBO__SHIFT 22
A6XX_SP_CS_CONFIG_NIBO(uint32_t val)6558 static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val)
6559 {
6560 return ((val) << A6XX_SP_CS_CONFIG_NIBO__SHIFT) & A6XX_SP_CS_CONFIG_NIBO__MASK;
6561 }
6562
6563 #define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc
6564
6565 #define REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET 0x0000a9bd
6566 #define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff
6567 #define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)6568 static inline uint32_t A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
6569 {
6570 return ((val >> 11) << A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
6571 }
6572
6573 #define REG_A6XX_SP_CS_CNTL_0 0x0000a9c2
6574 #define A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff
6575 #define A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT 0
A6XX_SP_CS_CNTL_0_WGIDCONSTID(uint32_t val)6576 static inline uint32_t A6XX_SP_CS_CNTL_0_WGIDCONSTID(uint32_t val)
6577 {
6578 return ((val) << A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK;
6579 }
6580 #define A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK 0x0000ff00
6581 #define A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT 8
A6XX_SP_CS_CNTL_0_WGSIZECONSTID(uint32_t val)6582 static inline uint32_t A6XX_SP_CS_CNTL_0_WGSIZECONSTID(uint32_t val)
6583 {
6584 return ((val) << A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK;
6585 }
6586 #define A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK 0x00ff0000
6587 #define A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT 16
A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val)6588 static inline uint32_t A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val)
6589 {
6590 return ((val) << A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK;
6591 }
6592 #define A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000
6593 #define A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT 24
A6XX_SP_CS_CNTL_0_LOCALIDREGID(uint32_t val)6594 static inline uint32_t A6XX_SP_CS_CNTL_0_LOCALIDREGID(uint32_t val)
6595 {
6596 return ((val) << A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK;
6597 }
6598
6599 #define REG_A6XX_SP_CS_CNTL_1 0x0000a9c3
6600 #define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff
6601 #define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0
A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val)6602 static inline uint32_t A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val)
6603 {
6604 return ((val) << A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK;
6605 }
6606 #define A6XX_SP_CS_CNTL_1_SINGLE_SP_CORE 0x00000100
6607 #define A6XX_SP_CS_CNTL_1_THREADSIZE__MASK 0x00000200
6608 #define A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT 9
A6XX_SP_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val)6609 static inline uint32_t A6XX_SP_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val)
6610 {
6611 return ((val) << A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_SP_CS_CNTL_1_THREADSIZE__MASK;
6612 }
6613 #define A6XX_SP_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400
6614
6615 #define REG_A6XX_SP_FS_TEX_SAMP 0x0000a9e0
6616 #define A6XX_SP_FS_TEX_SAMP__MASK 0xffffffff
6617 #define A6XX_SP_FS_TEX_SAMP__SHIFT 0
A6XX_SP_FS_TEX_SAMP(uint32_t val)6618 static inline uint32_t A6XX_SP_FS_TEX_SAMP(uint32_t val)
6619 {
6620 return ((val) << A6XX_SP_FS_TEX_SAMP__SHIFT) & A6XX_SP_FS_TEX_SAMP__MASK;
6621 }
6622
6623 #define REG_A6XX_SP_CS_TEX_SAMP 0x0000a9e2
6624 #define A6XX_SP_CS_TEX_SAMP__MASK 0xffffffff
6625 #define A6XX_SP_CS_TEX_SAMP__SHIFT 0
A6XX_SP_CS_TEX_SAMP(uint32_t val)6626 static inline uint32_t A6XX_SP_CS_TEX_SAMP(uint32_t val)
6627 {
6628 return ((val) << A6XX_SP_CS_TEX_SAMP__SHIFT) & A6XX_SP_CS_TEX_SAMP__MASK;
6629 }
6630
6631 #define REG_A6XX_SP_FS_TEX_CONST 0x0000a9e4
6632 #define A6XX_SP_FS_TEX_CONST__MASK 0xffffffff
6633 #define A6XX_SP_FS_TEX_CONST__SHIFT 0
A6XX_SP_FS_TEX_CONST(uint32_t val)6634 static inline uint32_t A6XX_SP_FS_TEX_CONST(uint32_t val)
6635 {
6636 return ((val) << A6XX_SP_FS_TEX_CONST__SHIFT) & A6XX_SP_FS_TEX_CONST__MASK;
6637 }
6638
6639 #define REG_A6XX_SP_CS_TEX_CONST 0x0000a9e6
6640 #define A6XX_SP_CS_TEX_CONST__MASK 0xffffffff
6641 #define A6XX_SP_CS_TEX_CONST__SHIFT 0
A6XX_SP_CS_TEX_CONST(uint32_t val)6642 static inline uint32_t A6XX_SP_CS_TEX_CONST(uint32_t val)
6643 {
6644 return ((val) << A6XX_SP_CS_TEX_CONST__SHIFT) & A6XX_SP_CS_TEX_CONST__MASK;
6645 }
6646
REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0)6647 static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
6648
REG_A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0)6649 static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
6650 #define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003
6651 #define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0
A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val)6652 static inline uint32_t A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val)
6653 {
6654 return ((val) << A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK;
6655 }
6656 #define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffc
6657 #define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2
A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val)6658 static inline uint32_t A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val)
6659 {
6660 return ((val >> 2) << A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK;
6661 }
6662
6663 #define REG_A6XX_SP_CS_IBO 0x0000a9f2
6664 #define A6XX_SP_CS_IBO__MASK 0xffffffff
6665 #define A6XX_SP_CS_IBO__SHIFT 0
A6XX_SP_CS_IBO(uint32_t val)6666 static inline uint32_t A6XX_SP_CS_IBO(uint32_t val)
6667 {
6668 return ((val) << A6XX_SP_CS_IBO__SHIFT) & A6XX_SP_CS_IBO__MASK;
6669 }
6670
6671 #define REG_A6XX_SP_CS_IBO_COUNT 0x0000aa00
6672
6673 #define REG_A6XX_SP_MODE_CONTROL 0x0000ab00
6674 #define A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE 0x00000001
6675 #define A6XX_SP_MODE_CONTROL_ISAMMODE__MASK 0x00000006
6676 #define A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT 1
A6XX_SP_MODE_CONTROL_ISAMMODE(enum a6xx_isam_mode val)6677 static inline uint32_t A6XX_SP_MODE_CONTROL_ISAMMODE(enum a6xx_isam_mode val)
6678 {
6679 return ((val) << A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT) & A6XX_SP_MODE_CONTROL_ISAMMODE__MASK;
6680 }
6681 #define A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE 0x00000008
6682
6683 #define REG_A6XX_SP_FS_CONFIG 0x0000ab04
6684 #define A6XX_SP_FS_CONFIG_BINDLESS_TEX 0x00000001
6685 #define A6XX_SP_FS_CONFIG_BINDLESS_SAMP 0x00000002
6686 #define A6XX_SP_FS_CONFIG_BINDLESS_IBO 0x00000004
6687 #define A6XX_SP_FS_CONFIG_BINDLESS_UBO 0x00000008
6688 #define A6XX_SP_FS_CONFIG_ENABLED 0x00000100
6689 #define A6XX_SP_FS_CONFIG_NTEX__MASK 0x0001fe00
6690 #define A6XX_SP_FS_CONFIG_NTEX__SHIFT 9
A6XX_SP_FS_CONFIG_NTEX(uint32_t val)6691 static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val)
6692 {
6693 return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK;
6694 }
6695 #define A6XX_SP_FS_CONFIG_NSAMP__MASK 0x003e0000
6696 #define A6XX_SP_FS_CONFIG_NSAMP__SHIFT 17
A6XX_SP_FS_CONFIG_NSAMP(uint32_t val)6697 static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val)
6698 {
6699 return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK;
6700 }
6701 #define A6XX_SP_FS_CONFIG_NIBO__MASK 0x1fc00000
6702 #define A6XX_SP_FS_CONFIG_NIBO__SHIFT 22
A6XX_SP_FS_CONFIG_NIBO(uint32_t val)6703 static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val)
6704 {
6705 return ((val) << A6XX_SP_FS_CONFIG_NIBO__SHIFT) & A6XX_SP_FS_CONFIG_NIBO__MASK;
6706 }
6707
6708 #define REG_A6XX_SP_FS_INSTRLEN 0x0000ab05
6709
REG_A6XX_SP_BINDLESS_BASE(uint32_t i0)6710 static inline uint32_t REG_A6XX_SP_BINDLESS_BASE(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }
6711
REG_A6XX_SP_BINDLESS_BASE_DESCRIPTOR(uint32_t i0)6712 static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }
6713 #define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003
6714 #define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0
A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val)6715 static inline uint32_t A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val)
6716 {
6717 return ((val) << A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK;
6718 }
6719 #define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffc
6720 #define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2
A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val)6721 static inline uint32_t A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val)
6722 {
6723 return ((val >> 2) << A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK;
6724 }
6725
6726 #define REG_A6XX_SP_IBO 0x0000ab1a
6727 #define A6XX_SP_IBO__MASK 0xffffffff
6728 #define A6XX_SP_IBO__SHIFT 0
A6XX_SP_IBO(uint32_t val)6729 static inline uint32_t A6XX_SP_IBO(uint32_t val)
6730 {
6731 return ((val) << A6XX_SP_IBO__SHIFT) & A6XX_SP_IBO__MASK;
6732 }
6733
6734 #define REG_A6XX_SP_IBO_COUNT 0x0000ab20
6735
6736 #define REG_A6XX_SP_2D_DST_FORMAT 0x0000acc0
6737 #define A6XX_SP_2D_DST_FORMAT_NORM 0x00000001
6738 #define A6XX_SP_2D_DST_FORMAT_SINT 0x00000002
6739 #define A6XX_SP_2D_DST_FORMAT_UINT 0x00000004
6740 #define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK 0x000007f8
6741 #define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT 3
A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val)6742 static inline uint32_t A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val)
6743 {
6744 return ((val) << A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT) & A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK;
6745 }
6746 #define A6XX_SP_2D_DST_FORMAT_SRGB 0x00000800
6747 #define A6XX_SP_2D_DST_FORMAT_MASK__MASK 0x0000f000
6748 #define A6XX_SP_2D_DST_FORMAT_MASK__SHIFT 12
A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val)6749 static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val)
6750 {
6751 return ((val) << A6XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A6XX_SP_2D_DST_FORMAT_MASK__MASK;
6752 }
6753
6754 #define REG_A6XX_SP_DBG_ECO_CNTL 0x0000ae00
6755
6756 #define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01
6757
6758 #define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02
6759
6760 #define REG_A6XX_SP_CHICKEN_BITS 0x0000ae03
6761
6762 #define REG_A6XX_SP_FLOAT_CNTL 0x0000ae04
6763 #define A6XX_SP_FLOAT_CNTL_F16_NO_INF 0x00000008
6764
6765 #define REG_A6XX_SP_PERFCTR_ENABLE 0x0000ae0f
6766 #define A6XX_SP_PERFCTR_ENABLE_VS 0x00000001
6767 #define A6XX_SP_PERFCTR_ENABLE_HS 0x00000002
6768 #define A6XX_SP_PERFCTR_ENABLE_DS 0x00000004
6769 #define A6XX_SP_PERFCTR_ENABLE_GS 0x00000008
6770 #define A6XX_SP_PERFCTR_ENABLE_FS 0x00000010
6771 #define A6XX_SP_PERFCTR_ENABLE_CS 0x00000020
6772
REG_A6XX_SP_PERFCTR_SP_SEL(uint32_t i0)6773 static inline uint32_t REG_A6XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae10 + 0x1*i0; }
6774
REG_A7XX_SP_PERFCTR_HLSQ_SEL(uint32_t i0)6775 static inline uint32_t REG_A7XX_SP_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000ae60 + 0x1*i0; }
6776
6777 #define REG_A7XX_SP_READ_SEL 0x0000ae6d
6778
REG_A7XX_SP_PERFCTR_SP_SEL(uint32_t i0)6779 static inline uint32_t REG_A7XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae80 + 0x1*i0; }
6780
6781 #define REG_A6XX_SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE 0x0000be22
6782
6783 #define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR 0x0000b180
6784 #define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff
6785 #define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0
A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(uint32_t val)6786 static inline uint32_t A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(uint32_t val)
6787 {
6788 return ((val) << A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK;
6789 }
6790
6791 #define REG_A6XX_SP_UNKNOWN_B182 0x0000b182
6792
6793 #define REG_A6XX_SP_UNKNOWN_B183 0x0000b183
6794
6795 #define REG_A6XX_SP_UNKNOWN_B190 0x0000b190
6796
6797 #define REG_A6XX_SP_UNKNOWN_B191 0x0000b191
6798
6799 #define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300
6800 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
6801 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)6802 static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
6803 {
6804 return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK;
6805 }
6806 #define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK 0x0000000c
6807 #define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT 2
A6XX_SP_TP_RAS_MSAA_CNTL_UNK2(uint32_t val)6808 static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_UNK2(uint32_t val)
6809 {
6810 return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK;
6811 }
6812
6813 #define REG_A6XX_SP_TP_DEST_MSAA_CNTL 0x0000b301
6814 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
6815 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)6816 static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
6817 {
6818 return ((val) << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK;
6819 }
6820 #define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
6821
6822 #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR 0x0000b302
6823 #define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff
6824 #define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0
A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(uint32_t val)6825 static inline uint32_t A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(uint32_t val)
6826 {
6827 return ((val) << A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK;
6828 }
6829
6830 #define REG_A6XX_SP_TP_SAMPLE_CONFIG 0x0000b304
6831 #define A6XX_SP_TP_SAMPLE_CONFIG_UNK0 0x00000001
6832 #define A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002
6833
6834 #define REG_A6XX_SP_TP_SAMPLE_LOCATION_0 0x0000b305
6835 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f
6836 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)6837 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
6838 {
6839 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
6840 }
6841 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0
6842 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)6843 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
6844 {
6845 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
6846 }
6847 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00
6848 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)6849 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
6850 {
6851 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
6852 }
6853 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000
6854 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)6855 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
6856 {
6857 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
6858 }
6859 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000
6860 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)6861 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
6862 {
6863 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
6864 }
6865 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000
6866 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)6867 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
6868 {
6869 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
6870 }
6871 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000
6872 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)6873 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
6874 {
6875 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
6876 }
6877 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000
6878 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)6879 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
6880 {
6881 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
6882 }
6883
6884 #define REG_A6XX_SP_TP_SAMPLE_LOCATION_1 0x0000b306
6885 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f
6886 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)6887 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
6888 {
6889 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
6890 }
6891 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0
6892 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)6893 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
6894 {
6895 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
6896 }
6897 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00
6898 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)6899 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
6900 {
6901 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
6902 }
6903 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000
6904 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)6905 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
6906 {
6907 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
6908 }
6909 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000
6910 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)6911 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
6912 {
6913 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
6914 }
6915 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000
6916 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)6917 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
6918 {
6919 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
6920 }
6921 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000
6922 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)6923 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
6924 {
6925 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
6926 }
6927 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000
6928 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)6929 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
6930 {
6931 return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
6932 }
6933
6934 #define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307
6935 #define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00003fff
6936 #define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0
A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val)6937 static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val)
6938 {
6939 return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK;
6940 }
6941 #define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x3fff0000
6942 #define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16
A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val)6943 static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val)
6944 {
6945 return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK;
6946 }
6947
6948 #define REG_A6XX_SP_TP_MODE_CNTL 0x0000b309
6949 #define A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK 0x00000003
6950 #define A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT 0
A6XX_SP_TP_MODE_CNTL_ISAMMODE(enum a6xx_isam_mode val)6951 static inline uint32_t A6XX_SP_TP_MODE_CNTL_ISAMMODE(enum a6xx_isam_mode val)
6952 {
6953 return ((val) << A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT) & A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK;
6954 }
6955 #define A6XX_SP_TP_MODE_CNTL_UNK3__MASK 0x000000fc
6956 #define A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT 2
A6XX_SP_TP_MODE_CNTL_UNK3(uint32_t val)6957 static inline uint32_t A6XX_SP_TP_MODE_CNTL_UNK3(uint32_t val)
6958 {
6959 return ((val) << A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT) & A6XX_SP_TP_MODE_CNTL_UNK3__MASK;
6960 }
6961
6962 #define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0
6963 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
6964 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val)6965 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val)
6966 {
6967 return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK;
6968 }
6969 #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300
6970 #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT 8
A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val)6971 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val)
6972 {
6973 return ((val) << A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK;
6974 }
6975 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
6976 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)6977 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
6978 {
6979 return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK;
6980 }
6981 #define A6XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000
6982 #define A6XX_SP_PS_2D_SRC_INFO_SRGB 0x00002000
6983 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK 0x0000c000
6984 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT 14
A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val)6985 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val)
6986 {
6987 return ((val) << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK;
6988 }
6989 #define A6XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000
6990 #define A6XX_SP_PS_2D_SRC_INFO_UNK17 0x00020000
6991 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE 0x00040000
6992 #define A6XX_SP_PS_2D_SRC_INFO_UNK19 0x00080000
6993 #define A6XX_SP_PS_2D_SRC_INFO_UNK20 0x00100000
6994 #define A6XX_SP_PS_2D_SRC_INFO_UNK21 0x00200000
6995 #define A6XX_SP_PS_2D_SRC_INFO_UNK22 0x00400000
6996 #define A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK 0x07800000
6997 #define A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT 23
A6XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val)6998 static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val)
6999 {
7000 return ((val) << A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK;
7001 }
7002 #define A6XX_SP_PS_2D_SRC_INFO_UNK28 0x10000000
7003
7004 #define REG_A6XX_SP_PS_2D_SRC_SIZE 0x0000b4c1
7005 #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff
7006 #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT 0
A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val)7007 static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val)
7008 {
7009 return ((val) << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK;
7010 }
7011 #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK 0x3fff8000
7012 #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT 15
A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val)7013 static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val)
7014 {
7015 return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK;
7016 }
7017
7018 #define REG_A6XX_SP_PS_2D_SRC 0x0000b4c2
7019 #define A6XX_SP_PS_2D_SRC__MASK 0xffffffff
7020 #define A6XX_SP_PS_2D_SRC__SHIFT 0
A6XX_SP_PS_2D_SRC(uint32_t val)7021 static inline uint32_t A6XX_SP_PS_2D_SRC(uint32_t val)
7022 {
7023 return ((val) << A6XX_SP_PS_2D_SRC__SHIFT) & A6XX_SP_PS_2D_SRC__MASK;
7024 }
7025
7026 #define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4
7027 #define A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK 0x000001ff
7028 #define A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT 0
A6XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val)7029 static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val)
7030 {
7031 return ((val) << A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK;
7032 }
7033 #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x00fffe00
7034 #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9
A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val)7035 static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val)
7036 {
7037 return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK;
7038 }
7039
7040 #define REG_A6XX_SP_PS_2D_SRC_PLANE1 0x0000b4c5
7041 #define A6XX_SP_PS_2D_SRC_PLANE1__MASK 0xffffffff
7042 #define A6XX_SP_PS_2D_SRC_PLANE1__SHIFT 0
A6XX_SP_PS_2D_SRC_PLANE1(uint32_t val)7043 static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE1(uint32_t val)
7044 {
7045 return ((val) << A6XX_SP_PS_2D_SRC_PLANE1__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE1__MASK;
7046 }
7047
7048 #define REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH 0x0000b4c7
7049 #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK 0x00000fff
7050 #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT 0
A6XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val)7051 static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val)
7052 {
7053 return ((val >> 6) << A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK;
7054 }
7055
7056 #define REG_A6XX_SP_PS_2D_SRC_PLANE2 0x0000b4c8
7057 #define A6XX_SP_PS_2D_SRC_PLANE2__MASK 0xffffffff
7058 #define A6XX_SP_PS_2D_SRC_PLANE2__SHIFT 0
A6XX_SP_PS_2D_SRC_PLANE2(uint32_t val)7059 static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE2(uint32_t val)
7060 {
7061 return ((val) << A6XX_SP_PS_2D_SRC_PLANE2__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE2__MASK;
7062 }
7063
7064 #define REG_A6XX_SP_PS_2D_SRC_FLAGS 0x0000b4ca
7065 #define A6XX_SP_PS_2D_SRC_FLAGS__MASK 0xffffffff
7066 #define A6XX_SP_PS_2D_SRC_FLAGS__SHIFT 0
A6XX_SP_PS_2D_SRC_FLAGS(uint32_t val)7067 static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS(uint32_t val)
7068 {
7069 return ((val) << A6XX_SP_PS_2D_SRC_FLAGS__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS__MASK;
7070 }
7071
7072 #define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b4cc
7073 #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK 0x000000ff
7074 #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT 0
A6XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val)7075 static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val)
7076 {
7077 return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK;
7078 }
7079
7080 #define REG_A6XX_SP_PS_UNKNOWN_B4CD 0x0000b4cd
7081
7082 #define REG_A6XX_SP_PS_UNKNOWN_B4CE 0x0000b4ce
7083
7084 #define REG_A6XX_SP_PS_UNKNOWN_B4CF 0x0000b4cf
7085
7086 #define REG_A6XX_SP_PS_UNKNOWN_B4D0 0x0000b4d0
7087
7088 #define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1
7089 #define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00003fff
7090 #define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0
A6XX_SP_WINDOW_OFFSET_X(uint32_t val)7091 static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val)
7092 {
7093 return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK;
7094 }
7095 #define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x3fff0000
7096 #define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16
A6XX_SP_WINDOW_OFFSET_Y(uint32_t val)7097 static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val)
7098 {
7099 return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK;
7100 }
7101
7102 #define REG_A6XX_TPL1_DBG_ECO_CNTL 0x0000b600
7103
7104 #define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601
7105
7106 #define REG_A6XX_TPL1_UNKNOWN_B602 0x0000b602
7107
7108 #define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604
7109 #define A6XX_TPL1_NC_MODE_CNTL_MODE 0x00000001
7110 #define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006
7111 #define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT 1
A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT(uint32_t val)7112 static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT(uint32_t val)
7113 {
7114 return ((val) << A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK;
7115 }
7116 #define A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008
7117 #define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000010
7118 #define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT 4
A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT(uint32_t val)7119 static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT(uint32_t val)
7120 {
7121 return ((val) << A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK;
7122 }
7123 #define A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK 0x000000c0
7124 #define A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT 6
A6XX_TPL1_NC_MODE_CNTL_UNK6(uint32_t val)7125 static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UNK6(uint32_t val)
7126 {
7127 return ((val) << A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK;
7128 }
7129
7130 #define REG_A6XX_TPL1_UNKNOWN_B605 0x0000b605
7131
7132 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608
7133
7134 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609
7135
7136 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a
7137
7138 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b
7139
7140 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c
7141
REG_A6XX_TPL1_PERFCTR_TP_SEL(uint32_t i0)7142 static inline uint32_t REG_A6XX_TPL1_PERFCTR_TP_SEL(uint32_t i0) { return 0x0000b610 + 0x1*i0; }
7143
7144 #define REG_A6XX_HLSQ_VS_CNTL 0x0000b800
7145 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff
7146 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0
A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val)7147 static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val)
7148 {
7149 return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK;
7150 }
7151 #define A6XX_HLSQ_VS_CNTL_ENABLED 0x00000100
7152
7153 #define REG_A6XX_HLSQ_HS_CNTL 0x0000b801
7154 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff
7155 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0
A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val)7156 static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val)
7157 {
7158 return ((val >> 2) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK;
7159 }
7160 #define A6XX_HLSQ_HS_CNTL_ENABLED 0x00000100
7161
7162 #define REG_A6XX_HLSQ_DS_CNTL 0x0000b802
7163 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff
7164 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0
A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val)7165 static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val)
7166 {
7167 return ((val >> 2) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK;
7168 }
7169 #define A6XX_HLSQ_DS_CNTL_ENABLED 0x00000100
7170
7171 #define REG_A6XX_HLSQ_GS_CNTL 0x0000b803
7172 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff
7173 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0
A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val)7174 static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val)
7175 {
7176 return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK;
7177 }
7178 #define A6XX_HLSQ_GS_CNTL_ENABLED 0x00000100
7179
7180 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD 0x0000b820
7181
7182 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR 0x0000b821
7183 #define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK 0xffffffff
7184 #define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT 0
A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR(uint32_t val)7185 static inline uint32_t A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR(uint32_t val)
7186 {
7187 return ((val) << A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK;
7188 }
7189
7190 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA 0x0000b823
7191
7192 #define REG_A6XX_HLSQ_FS_CNTL_0 0x0000b980
7193 #define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK 0x00000001
7194 #define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT 0
A6XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val)7195 static inline uint32_t A6XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val)
7196 {
7197 return ((val) << A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK;
7198 }
7199 #define A6XX_HLSQ_FS_CNTL_0_VARYINGS 0x00000002
7200 #define A6XX_HLSQ_FS_CNTL_0_UNK2__MASK 0x00000ffc
7201 #define A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT 2
A6XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val)7202 static inline uint32_t A6XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val)
7203 {
7204 return ((val) << A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A6XX_HLSQ_FS_CNTL_0_UNK2__MASK;
7205 }
7206
7207 #define REG_A6XX_HLSQ_UNKNOWN_B981 0x0000b981
7208
7209 #define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982
7210
7211 #define REG_A7XX_HLSQ_CONTROL_1_REG 0x0000a9c7
7212
7213 #define REG_A6XX_HLSQ_CONTROL_2_REG 0x0000b983
7214 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff
7215 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0
A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)7216 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
7217 {
7218 return ((val) << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
7219 }
7220 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00
7221 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8
A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)7222 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)
7223 {
7224 return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK;
7225 }
7226 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000
7227 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16
A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)7228 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)
7229 {
7230 return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
7231 }
7232 #define A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK 0xff000000
7233 #define A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT 24
A6XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val)7234 static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val)
7235 {
7236 return ((val) << A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK;
7237 }
7238
7239 #define REG_A7XX_HLSQ_CONTROL_2_REG 0x0000a9c8
7240 #define A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff
7241 #define A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0
A7XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)7242 static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
7243 {
7244 return ((val) << A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
7245 }
7246 #define A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00
7247 #define A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8
A7XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)7248 static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)
7249 {
7250 return ((val) << A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK;
7251 }
7252 #define A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000
7253 #define A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16
A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)7254 static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)
7255 {
7256 return ((val) << A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
7257 }
7258 #define A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK 0xff000000
7259 #define A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT 24
A7XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val)7260 static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val)
7261 {
7262 return ((val) << A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK;
7263 }
7264
7265 #define REG_A6XX_HLSQ_CONTROL_3_REG 0x0000b984
7266 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff
7267 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0
A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)7268 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
7269 {
7270 return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK;
7271 }
7272 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00
7273 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8
A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)7274 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
7275 {
7276 return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK;
7277 }
7278 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000
7279 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16
A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)7280 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
7281 {
7282 return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK;
7283 }
7284 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000
7285 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24
A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)7286 static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
7287 {
7288 return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK;
7289 }
7290
7291 #define REG_A7XX_HLSQ_CONTROL_3_REG 0x0000a9c9
7292 #define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff
7293 #define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0
A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)7294 static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
7295 {
7296 return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK;
7297 }
7298 #define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00
7299 #define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8
A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)7300 static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
7301 {
7302 return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK;
7303 }
7304 #define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000
7305 #define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16
A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)7306 static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
7307 {
7308 return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK;
7309 }
7310 #define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000
7311 #define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24
A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)7312 static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
7313 {
7314 return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK;
7315 }
7316
7317 #define REG_A6XX_HLSQ_CONTROL_4_REG 0x0000b985
7318 #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff
7319 #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0
A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)7320 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
7321 {
7322 return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK;
7323 }
7324 #define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00
7325 #define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8
A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)7326 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
7327 {
7328 return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK;
7329 }
7330 #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000
7331 #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16
A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)7332 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
7333 {
7334 return ((val) << A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK;
7335 }
7336 #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000
7337 #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24
A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)7338 static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
7339 {
7340 return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK;
7341 }
7342
7343 #define REG_A7XX_HLSQ_CONTROL_4_REG 0x0000a9ca
7344 #define A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff
7345 #define A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0
A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)7346 static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
7347 {
7348 return ((val) << A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK;
7349 }
7350 #define A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00
7351 #define A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8
A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)7352 static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
7353 {
7354 return ((val) << A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK;
7355 }
7356 #define A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000
7357 #define A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16
A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)7358 static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
7359 {
7360 return ((val) << A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK;
7361 }
7362 #define A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000
7363 #define A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24
A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)7364 static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
7365 {
7366 return ((val) << A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK;
7367 }
7368
7369 #define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986
7370 #define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK 0x000000ff
7371 #define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT 0
A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val)7372 static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val)
7373 {
7374 return ((val) << A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK;
7375 }
7376 #define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK 0x0000ff00
7377 #define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT 8
A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val)7378 static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val)
7379 {
7380 return ((val) << A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK;
7381 }
7382
7383 #define REG_A7XX_HLSQ_CONTROL_5_REG 0x0000a9cb
7384 #define A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK 0x000000ff
7385 #define A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT 0
A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val)7386 static inline uint32_t A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val)
7387 {
7388 return ((val) << A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK;
7389 }
7390 #define A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK 0x0000ff00
7391 #define A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT 8
A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val)7392 static inline uint32_t A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val)
7393 {
7394 return ((val) << A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK;
7395 }
7396
7397 #define REG_A6XX_HLSQ_CS_CNTL 0x0000b987
7398 #define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff
7399 #define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0
A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val)7400 static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val)
7401 {
7402 return ((val >> 2) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK;
7403 }
7404 #define A6XX_HLSQ_CS_CNTL_ENABLED 0x00000100
7405
7406 #define REG_A6XX_HLSQ_CS_NDRANGE_0 0x0000b990
7407 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003
7408 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0
A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)7409 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)
7410 {
7411 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK;
7412 }
7413 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc
7414 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2
A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)7415 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)
7416 {
7417 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK;
7418 }
7419 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000
7420 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12
A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)7421 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)
7422 {
7423 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK;
7424 }
7425 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000
7426 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22
A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)7427 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)
7428 {
7429 return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK;
7430 }
7431
7432 #define REG_A6XX_HLSQ_CS_NDRANGE_1 0x0000b991
7433 #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff
7434 #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0
A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val)7435 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val)
7436 {
7437 return ((val) << A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK;
7438 }
7439
7440 #define REG_A6XX_HLSQ_CS_NDRANGE_2 0x0000b992
7441 #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff
7442 #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0
A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val)7443 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val)
7444 {
7445 return ((val) << A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK;
7446 }
7447
7448 #define REG_A6XX_HLSQ_CS_NDRANGE_3 0x0000b993
7449 #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff
7450 #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0
A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val)7451 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val)
7452 {
7453 return ((val) << A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK;
7454 }
7455
7456 #define REG_A6XX_HLSQ_CS_NDRANGE_4 0x0000b994
7457 #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff
7458 #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0
A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val)7459 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val)
7460 {
7461 return ((val) << A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK;
7462 }
7463
7464 #define REG_A6XX_HLSQ_CS_NDRANGE_5 0x0000b995
7465 #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff
7466 #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0
A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val)7467 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val)
7468 {
7469 return ((val) << A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK;
7470 }
7471
7472 #define REG_A6XX_HLSQ_CS_NDRANGE_6 0x0000b996
7473 #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff
7474 #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0
A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val)7475 static inline uint32_t A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val)
7476 {
7477 return ((val) << A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK;
7478 }
7479
7480 #define REG_A6XX_HLSQ_CS_CNTL_0 0x0000b997
7481 #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff
7482 #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0
A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)7483 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)
7484 {
7485 return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK;
7486 }
7487 #define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK 0x0000ff00
7488 #define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT 8
A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(uint32_t val)7489 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(uint32_t val)
7490 {
7491 return ((val) << A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK;
7492 }
7493 #define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK 0x00ff0000
7494 #define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT 16
A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val)7495 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val)
7496 {
7497 return ((val) << A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK;
7498 }
7499 #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000
7500 #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24
A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)7501 static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
7502 {
7503 return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
7504 }
7505
7506 #define REG_A6XX_HLSQ_CS_CNTL_1 0x0000b998
7507 #define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff
7508 #define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0
A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val)7509 static inline uint32_t A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val)
7510 {
7511 return ((val) << A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK;
7512 }
7513 #define A6XX_HLSQ_CS_CNTL_1_SINGLE_SP_CORE 0x00000100
7514 #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK 0x00000200
7515 #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT 9
A6XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val)7516 static inline uint32_t A6XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val)
7517 {
7518 return ((val) << A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK;
7519 }
7520 #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400
7521
7522 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X 0x0000b999
7523
7524 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000b99a
7525
7526 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000b99b
7527
7528 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD 0x0000b9a0
7529
7530 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR 0x0000b9a1
7531 #define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK 0xffffffff
7532 #define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT 0
A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR(uint32_t val)7533 static inline uint32_t A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR(uint32_t val)
7534 {
7535 return ((val) << A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK;
7536 }
7537
7538 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA 0x0000b9a3
7539
REG_A6XX_HLSQ_CS_BINDLESS_BASE(uint32_t i0)7540 static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }
7541
REG_A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0)7542 static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }
7543 #define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003
7544 #define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0
A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val)7545 static inline uint32_t A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val)
7546 {
7547 return ((val) << A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK;
7548 }
7549 #define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffc
7550 #define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2
A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val)7551 static inline uint32_t A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val)
7552 {
7553 return ((val >> 2) << A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK;
7554 }
7555
7556 #define REG_A6XX_HLSQ_CS_UNKNOWN_B9D0 0x0000b9d0
7557 #define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK 0x0000001f
7558 #define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT 0
A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE(uint32_t val)7559 static inline uint32_t A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE(uint32_t val)
7560 {
7561 return ((val) << A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT) & A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK;
7562 }
7563 #define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK5 0x00000020
7564 #define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK6 0x00000040
7565
7566 #define REG_A6XX_HLSQ_DRAW_CMD 0x0000bb00
7567 #define A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK 0x000000ff
7568 #define A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT 0
A6XX_HLSQ_DRAW_CMD_STATE_ID(uint32_t val)7569 static inline uint32_t A6XX_HLSQ_DRAW_CMD_STATE_ID(uint32_t val)
7570 {
7571 return ((val) << A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK;
7572 }
7573
7574 #define REG_A6XX_HLSQ_DISPATCH_CMD 0x0000bb01
7575 #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK 0x000000ff
7576 #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT 0
A6XX_HLSQ_DISPATCH_CMD_STATE_ID(uint32_t val)7577 static inline uint32_t A6XX_HLSQ_DISPATCH_CMD_STATE_ID(uint32_t val)
7578 {
7579 return ((val) << A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK;
7580 }
7581
7582 #define REG_A6XX_HLSQ_EVENT_CMD 0x0000bb02
7583 #define A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK 0x00ff0000
7584 #define A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT 16
A6XX_HLSQ_EVENT_CMD_STATE_ID(uint32_t val)7585 static inline uint32_t A6XX_HLSQ_EVENT_CMD_STATE_ID(uint32_t val)
7586 {
7587 return ((val) << A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK;
7588 }
7589 #define A6XX_HLSQ_EVENT_CMD_EVENT__MASK 0x0000007f
7590 #define A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT 0
A6XX_HLSQ_EVENT_CMD_EVENT(enum vgt_event_type val)7591 static inline uint32_t A6XX_HLSQ_EVENT_CMD_EVENT(enum vgt_event_type val)
7592 {
7593 return ((val) << A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_EVENT_CMD_EVENT__MASK;
7594 }
7595
7596 #define REG_A6XX_HLSQ_INVALIDATE_CMD 0x0000bb08
7597 #define A6XX_HLSQ_INVALIDATE_CMD_VS_STATE 0x00000001
7598 #define A6XX_HLSQ_INVALIDATE_CMD_HS_STATE 0x00000002
7599 #define A6XX_HLSQ_INVALIDATE_CMD_DS_STATE 0x00000004
7600 #define A6XX_HLSQ_INVALIDATE_CMD_GS_STATE 0x00000008
7601 #define A6XX_HLSQ_INVALIDATE_CMD_FS_STATE 0x00000010
7602 #define A6XX_HLSQ_INVALIDATE_CMD_CS_STATE 0x00000020
7603 #define A6XX_HLSQ_INVALIDATE_CMD_CS_IBO 0x00000040
7604 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO 0x00000080
7605 #define A6XX_HLSQ_INVALIDATE_CMD_CS_SHARED_CONST 0x00080000
7606 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_SHARED_CONST 0x00000100
7607 #define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK 0x00003e00
7608 #define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT 9
A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val)7609 static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val)
7610 {
7611 return ((val) << A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK;
7612 }
7613 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK 0x0007c000
7614 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT 14
A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val)7615 static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val)
7616 {
7617 return ((val) << A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK;
7618 }
7619
7620 #define REG_A6XX_HLSQ_FS_CNTL 0x0000bb10
7621 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff
7622 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0
A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val)7623 static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val)
7624 {
7625 return ((val >> 2) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK;
7626 }
7627 #define A6XX_HLSQ_FS_CNTL_ENABLED 0x00000100
7628
7629 #define REG_A6XX_HLSQ_SHARED_CONSTS 0x0000bb11
7630 #define A6XX_HLSQ_SHARED_CONSTS_ENABLE 0x00000001
7631
REG_A6XX_HLSQ_BINDLESS_BASE(uint32_t i0)7632 static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE(uint32_t i0) { return 0x0000bb20 + 0x2*i0; }
7633
REG_A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR(uint32_t i0)7634 static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000bb20 + 0x2*i0; }
7635 #define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003
7636 #define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0
A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val)7637 static inline uint32_t A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val)
7638 {
7639 return ((val) << A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK;
7640 }
7641 #define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffc
7642 #define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2
A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val)7643 static inline uint32_t A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val)
7644 {
7645 return ((val >> 2) << A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK;
7646 }
7647
7648 #define REG_A6XX_HLSQ_2D_EVENT_CMD 0x0000bd80
7649 #define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00
7650 #define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT 8
A6XX_HLSQ_2D_EVENT_CMD_STATE_ID(uint32_t val)7651 static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_STATE_ID(uint32_t val)
7652 {
7653 return ((val) << A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK;
7654 }
7655 #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK 0x0000007f
7656 #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT 0
A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val)7657 static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val)
7658 {
7659 return ((val) << A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK;
7660 }
7661
7662 #define REG_A6XX_HLSQ_UNKNOWN_BE00 0x0000be00
7663
7664 #define REG_A6XX_HLSQ_UNKNOWN_BE01 0x0000be01
7665
7666 #define REG_A6XX_HLSQ_DBG_ECO_CNTL 0x0000be04
7667
7668 #define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05
7669
7670 #define REG_A6XX_HLSQ_UNKNOWN_BE08 0x0000be08
7671
REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(uint32_t i0)7672 static inline uint32_t REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000be10 + 0x1*i0; }
7673
7674 #define REG_A6XX_HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE 0x0000be22
7675
7676 #define REG_A7XX_SP_AHB_READ_APERTURE 0x0000c000
7677
7678 #define REG_A6XX_CP_EVENT_START 0x0000d600
7679 #define A6XX_CP_EVENT_START_STATE_ID__MASK 0x000000ff
7680 #define A6XX_CP_EVENT_START_STATE_ID__SHIFT 0
A6XX_CP_EVENT_START_STATE_ID(uint32_t val)7681 static inline uint32_t A6XX_CP_EVENT_START_STATE_ID(uint32_t val)
7682 {
7683 return ((val) << A6XX_CP_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_EVENT_START_STATE_ID__MASK;
7684 }
7685
7686 #define REG_A6XX_CP_EVENT_END 0x0000d601
7687 #define A6XX_CP_EVENT_END_STATE_ID__MASK 0x000000ff
7688 #define A6XX_CP_EVENT_END_STATE_ID__SHIFT 0
A6XX_CP_EVENT_END_STATE_ID(uint32_t val)7689 static inline uint32_t A6XX_CP_EVENT_END_STATE_ID(uint32_t val)
7690 {
7691 return ((val) << A6XX_CP_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_EVENT_END_STATE_ID__MASK;
7692 }
7693
7694 #define REG_A6XX_CP_2D_EVENT_START 0x0000d700
7695 #define A6XX_CP_2D_EVENT_START_STATE_ID__MASK 0x000000ff
7696 #define A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT 0
A6XX_CP_2D_EVENT_START_STATE_ID(uint32_t val)7697 static inline uint32_t A6XX_CP_2D_EVENT_START_STATE_ID(uint32_t val)
7698 {
7699 return ((val) << A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_START_STATE_ID__MASK;
7700 }
7701
7702 #define REG_A6XX_CP_2D_EVENT_END 0x0000d701
7703 #define A6XX_CP_2D_EVENT_END_STATE_ID__MASK 0x000000ff
7704 #define A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT 0
A6XX_CP_2D_EVENT_END_STATE_ID(uint32_t val)7705 static inline uint32_t A6XX_CP_2D_EVENT_END_STATE_ID(uint32_t val)
7706 {
7707 return ((val) << A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_END_STATE_ID__MASK;
7708 }
7709
7710 #define REG_A6XX_TEX_SAMP_0 0x00000000
7711 #define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
7712 #define A6XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
7713 #define A6XX_TEX_SAMP_0_XY_MAG__SHIFT 1
A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val)7714 static inline uint32_t A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val)
7715 {
7716 return ((val) << A6XX_TEX_SAMP_0_XY_MAG__SHIFT) & A6XX_TEX_SAMP_0_XY_MAG__MASK;
7717 }
7718 #define A6XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
7719 #define A6XX_TEX_SAMP_0_XY_MIN__SHIFT 3
A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val)7720 static inline uint32_t A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val)
7721 {
7722 return ((val) << A6XX_TEX_SAMP_0_XY_MIN__SHIFT) & A6XX_TEX_SAMP_0_XY_MIN__MASK;
7723 }
7724 #define A6XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
7725 #define A6XX_TEX_SAMP_0_WRAP_S__SHIFT 5
A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val)7726 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val)
7727 {
7728 return ((val) << A6XX_TEX_SAMP_0_WRAP_S__SHIFT) & A6XX_TEX_SAMP_0_WRAP_S__MASK;
7729 }
7730 #define A6XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
7731 #define A6XX_TEX_SAMP_0_WRAP_T__SHIFT 8
A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val)7732 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val)
7733 {
7734 return ((val) << A6XX_TEX_SAMP_0_WRAP_T__SHIFT) & A6XX_TEX_SAMP_0_WRAP_T__MASK;
7735 }
7736 #define A6XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
7737 #define A6XX_TEX_SAMP_0_WRAP_R__SHIFT 11
A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val)7738 static inline uint32_t A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val)
7739 {
7740 return ((val) << A6XX_TEX_SAMP_0_WRAP_R__SHIFT) & A6XX_TEX_SAMP_0_WRAP_R__MASK;
7741 }
7742 #define A6XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
7743 #define A6XX_TEX_SAMP_0_ANISO__SHIFT 14
A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val)7744 static inline uint32_t A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val)
7745 {
7746 return ((val) << A6XX_TEX_SAMP_0_ANISO__SHIFT) & A6XX_TEX_SAMP_0_ANISO__MASK;
7747 }
7748 #define A6XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
7749 #define A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
A6XX_TEX_SAMP_0_LOD_BIAS(float val)7750 static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val)
7751 {
7752 return ((((int32_t)(val * 256.0))) << A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A6XX_TEX_SAMP_0_LOD_BIAS__MASK;
7753 }
7754
7755 #define REG_A6XX_TEX_SAMP_1 0x00000001
7756 #define A6XX_TEX_SAMP_1_CLAMPENABLE 0x00000001
7757 #define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
7758 #define A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)7759 static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
7760 {
7761 return ((val) << A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
7762 }
7763 #define A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
7764 #define A6XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
7765 #define A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
7766 #define A6XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
7767 #define A6XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
A6XX_TEX_SAMP_1_MAX_LOD(float val)7768 static inline uint32_t A6XX_TEX_SAMP_1_MAX_LOD(float val)
7769 {
7770 return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK;
7771 }
7772 #define A6XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
7773 #define A6XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
A6XX_TEX_SAMP_1_MIN_LOD(float val)7774 static inline uint32_t A6XX_TEX_SAMP_1_MIN_LOD(float val)
7775 {
7776 return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK;
7777 }
7778
7779 #define REG_A6XX_TEX_SAMP_2 0x00000002
7780 #define A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK 0x00000003
7781 #define A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT 0
A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode val)7782 static inline uint32_t A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode val)
7783 {
7784 return ((val) << A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT) & A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK;
7785 }
7786 #define A6XX_TEX_SAMP_2_CHROMA_LINEAR 0x00000020
7787 #define A6XX_TEX_SAMP_2_BCOLOR__MASK 0xffffff80
7788 #define A6XX_TEX_SAMP_2_BCOLOR__SHIFT 7
A6XX_TEX_SAMP_2_BCOLOR(uint32_t val)7789 static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR(uint32_t val)
7790 {
7791 return ((val) << A6XX_TEX_SAMP_2_BCOLOR__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR__MASK;
7792 }
7793
7794 #define REG_A6XX_TEX_SAMP_3 0x00000003
7795
7796 #define REG_A6XX_TEX_CONST_0 0x00000000
7797 #define A6XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003
7798 #define A6XX_TEX_CONST_0_TILE_MODE__SHIFT 0
A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val)7799 static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val)
7800 {
7801 return ((val) << A6XX_TEX_CONST_0_TILE_MODE__SHIFT) & A6XX_TEX_CONST_0_TILE_MODE__MASK;
7802 }
7803 #define A6XX_TEX_CONST_0_SRGB 0x00000004
7804 #define A6XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
7805 #define A6XX_TEX_CONST_0_SWIZ_X__SHIFT 4
A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val)7806 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val)
7807 {
7808 return ((val) << A6XX_TEX_CONST_0_SWIZ_X__SHIFT) & A6XX_TEX_CONST_0_SWIZ_X__MASK;
7809 }
7810 #define A6XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
7811 #define A6XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val)7812 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val)
7813 {
7814 return ((val) << A6XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Y__MASK;
7815 }
7816 #define A6XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
7817 #define A6XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val)7818 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val)
7819 {
7820 return ((val) << A6XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Z__MASK;
7821 }
7822 #define A6XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
7823 #define A6XX_TEX_CONST_0_SWIZ_W__SHIFT 13
A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val)7824 static inline uint32_t A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val)
7825 {
7826 return ((val) << A6XX_TEX_CONST_0_SWIZ_W__SHIFT) & A6XX_TEX_CONST_0_SWIZ_W__MASK;
7827 }
7828 #define A6XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
7829 #define A6XX_TEX_CONST_0_MIPLVLS__SHIFT 16
A6XX_TEX_CONST_0_MIPLVLS(uint32_t val)7830 static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val)
7831 {
7832 return ((val) << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK;
7833 }
7834 #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X 0x00010000
7835 #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y 0x00040000
7836 #define A6XX_TEX_CONST_0_SAMPLES__MASK 0x00300000
7837 #define A6XX_TEX_CONST_0_SAMPLES__SHIFT 20
A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val)7838 static inline uint32_t A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val)
7839 {
7840 return ((val) << A6XX_TEX_CONST_0_SAMPLES__SHIFT) & A6XX_TEX_CONST_0_SAMPLES__MASK;
7841 }
7842 #define A6XX_TEX_CONST_0_FMT__MASK 0x3fc00000
7843 #define A6XX_TEX_CONST_0_FMT__SHIFT 22
A6XX_TEX_CONST_0_FMT(enum a6xx_format val)7844 static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_format val)
7845 {
7846 return ((val) << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK;
7847 }
7848 #define A6XX_TEX_CONST_0_SWAP__MASK 0xc0000000
7849 #define A6XX_TEX_CONST_0_SWAP__SHIFT 30
A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val)7850 static inline uint32_t A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val)
7851 {
7852 return ((val) << A6XX_TEX_CONST_0_SWAP__SHIFT) & A6XX_TEX_CONST_0_SWAP__MASK;
7853 }
7854
7855 #define REG_A6XX_TEX_CONST_1 0x00000001
7856 #define A6XX_TEX_CONST_1_WIDTH__MASK 0x00007fff
7857 #define A6XX_TEX_CONST_1_WIDTH__SHIFT 0
A6XX_TEX_CONST_1_WIDTH(uint32_t val)7858 static inline uint32_t A6XX_TEX_CONST_1_WIDTH(uint32_t val)
7859 {
7860 return ((val) << A6XX_TEX_CONST_1_WIDTH__SHIFT) & A6XX_TEX_CONST_1_WIDTH__MASK;
7861 }
7862 #define A6XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000
7863 #define A6XX_TEX_CONST_1_HEIGHT__SHIFT 15
A6XX_TEX_CONST_1_HEIGHT(uint32_t val)7864 static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val)
7865 {
7866 return ((val) << A6XX_TEX_CONST_1_HEIGHT__SHIFT) & A6XX_TEX_CONST_1_HEIGHT__MASK;
7867 }
7868
7869 #define REG_A6XX_TEX_CONST_2 0x00000002
7870 #define A6XX_TEX_CONST_2_STRUCTSIZETEXELS__MASK 0x0000fff0
7871 #define A6XX_TEX_CONST_2_STRUCTSIZETEXELS__SHIFT 4
A6XX_TEX_CONST_2_STRUCTSIZETEXELS(uint32_t val)7872 static inline uint32_t A6XX_TEX_CONST_2_STRUCTSIZETEXELS(uint32_t val)
7873 {
7874 return ((val) << A6XX_TEX_CONST_2_STRUCTSIZETEXELS__SHIFT) & A6XX_TEX_CONST_2_STRUCTSIZETEXELS__MASK;
7875 }
7876 #define A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK 0x003f0000
7877 #define A6XX_TEX_CONST_2_STARTOFFSETTEXELS__SHIFT 16
A6XX_TEX_CONST_2_STARTOFFSETTEXELS(uint32_t val)7878 static inline uint32_t A6XX_TEX_CONST_2_STARTOFFSETTEXELS(uint32_t val)
7879 {
7880 return ((val) << A6XX_TEX_CONST_2_STARTOFFSETTEXELS__SHIFT) & A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK;
7881 }
7882 #define A6XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f
7883 #define A6XX_TEX_CONST_2_PITCHALIGN__SHIFT 0
A6XX_TEX_CONST_2_PITCHALIGN(uint32_t val)7884 static inline uint32_t A6XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
7885 {
7886 return ((val) << A6XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A6XX_TEX_CONST_2_PITCHALIGN__MASK;
7887 }
7888 #define A6XX_TEX_CONST_2_PITCH__MASK 0x1fffff80
7889 #define A6XX_TEX_CONST_2_PITCH__SHIFT 7
A6XX_TEX_CONST_2_PITCH(uint32_t val)7890 static inline uint32_t A6XX_TEX_CONST_2_PITCH(uint32_t val)
7891 {
7892 return ((val) << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK;
7893 }
7894 #define A6XX_TEX_CONST_2_TYPE__MASK 0xe0000000
7895 #define A6XX_TEX_CONST_2_TYPE__SHIFT 29
A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val)7896 static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val)
7897 {
7898 return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK;
7899 }
7900
7901 #define REG_A6XX_TEX_CONST_3 0x00000003
7902 #define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff
7903 #define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0
A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)7904 static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
7905 {
7906 return ((val >> 12) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK;
7907 }
7908 #define A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000
7909 #define A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23
A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val)7910 static inline uint32_t A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val)
7911 {
7912 return ((val >> 12) << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK;
7913 }
7914 #define A6XX_TEX_CONST_3_TILE_ALL 0x08000000
7915 #define A6XX_TEX_CONST_3_FLAG 0x10000000
7916
7917 #define REG_A6XX_TEX_CONST_4 0x00000004
7918 #define A6XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0
7919 #define A6XX_TEX_CONST_4_BASE_LO__SHIFT 5
A6XX_TEX_CONST_4_BASE_LO(uint32_t val)7920 static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val)
7921 {
7922 return ((val >> 5) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK;
7923 }
7924
7925 #define REG_A6XX_TEX_CONST_5 0x00000005
7926 #define A6XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff
7927 #define A6XX_TEX_CONST_5_BASE_HI__SHIFT 0
A6XX_TEX_CONST_5_BASE_HI(uint32_t val)7928 static inline uint32_t A6XX_TEX_CONST_5_BASE_HI(uint32_t val)
7929 {
7930 return ((val) << A6XX_TEX_CONST_5_BASE_HI__SHIFT) & A6XX_TEX_CONST_5_BASE_HI__MASK;
7931 }
7932 #define A6XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000
7933 #define A6XX_TEX_CONST_5_DEPTH__SHIFT 17
A6XX_TEX_CONST_5_DEPTH(uint32_t val)7934 static inline uint32_t A6XX_TEX_CONST_5_DEPTH(uint32_t val)
7935 {
7936 return ((val) << A6XX_TEX_CONST_5_DEPTH__SHIFT) & A6XX_TEX_CONST_5_DEPTH__MASK;
7937 }
7938
7939 #define REG_A6XX_TEX_CONST_6 0x00000006
7940 #define A6XX_TEX_CONST_6_MIN_LOD_CLAMP__MASK 0x00000fff
7941 #define A6XX_TEX_CONST_6_MIN_LOD_CLAMP__SHIFT 0
A6XX_TEX_CONST_6_MIN_LOD_CLAMP(float val)7942 static inline uint32_t A6XX_TEX_CONST_6_MIN_LOD_CLAMP(float val)
7943 {
7944 return ((((uint32_t)(val * 256.0))) << A6XX_TEX_CONST_6_MIN_LOD_CLAMP__SHIFT) & A6XX_TEX_CONST_6_MIN_LOD_CLAMP__MASK;
7945 }
7946 #define A6XX_TEX_CONST_6_PLANE_PITCH__MASK 0xffffff00
7947 #define A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT 8
A6XX_TEX_CONST_6_PLANE_PITCH(uint32_t val)7948 static inline uint32_t A6XX_TEX_CONST_6_PLANE_PITCH(uint32_t val)
7949 {
7950 return ((val) << A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT) & A6XX_TEX_CONST_6_PLANE_PITCH__MASK;
7951 }
7952
7953 #define REG_A6XX_TEX_CONST_7 0x00000007
7954 #define A6XX_TEX_CONST_7_FLAG_LO__MASK 0xffffffe0
7955 #define A6XX_TEX_CONST_7_FLAG_LO__SHIFT 5
A6XX_TEX_CONST_7_FLAG_LO(uint32_t val)7956 static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val)
7957 {
7958 return ((val >> 5) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK;
7959 }
7960
7961 #define REG_A6XX_TEX_CONST_8 0x00000008
7962 #define A6XX_TEX_CONST_8_FLAG_HI__MASK 0x0001ffff
7963 #define A6XX_TEX_CONST_8_FLAG_HI__SHIFT 0
A6XX_TEX_CONST_8_FLAG_HI(uint32_t val)7964 static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val)
7965 {
7966 return ((val) << A6XX_TEX_CONST_8_FLAG_HI__SHIFT) & A6XX_TEX_CONST_8_FLAG_HI__MASK;
7967 }
7968
7969 #define REG_A6XX_TEX_CONST_9 0x00000009
7970 #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff
7971 #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0
A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)7972 static inline uint32_t A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
7973 {
7974 return ((val >> 4) << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK;
7975 }
7976
7977 #define REG_A6XX_TEX_CONST_10 0x0000000a
7978 #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK 0x0000007f
7979 #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT 0
A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val)7980 static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val)
7981 {
7982 return ((val >> 6) << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK;
7983 }
7984 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK 0x00000f00
7985 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT 8
A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(uint32_t val)7986 static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(uint32_t val)
7987 {
7988 return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK;
7989 }
7990 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK 0x0000f000
7991 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT 12
A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(uint32_t val)7992 static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(uint32_t val)
7993 {
7994 return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK;
7995 }
7996
7997 #define REG_A6XX_TEX_CONST_11 0x0000000b
7998
7999 #define REG_A6XX_TEX_CONST_12 0x0000000c
8000
8001 #define REG_A6XX_TEX_CONST_13 0x0000000d
8002
8003 #define REG_A6XX_TEX_CONST_14 0x0000000e
8004
8005 #define REG_A6XX_TEX_CONST_15 0x0000000f
8006
8007 #define REG_A6XX_UBO_0 0x00000000
8008 #define A6XX_UBO_0_BASE_LO__MASK 0xffffffff
8009 #define A6XX_UBO_0_BASE_LO__SHIFT 0
A6XX_UBO_0_BASE_LO(uint32_t val)8010 static inline uint32_t A6XX_UBO_0_BASE_LO(uint32_t val)
8011 {
8012 return ((val) << A6XX_UBO_0_BASE_LO__SHIFT) & A6XX_UBO_0_BASE_LO__MASK;
8013 }
8014
8015 #define REG_A6XX_UBO_1 0x00000001
8016 #define A6XX_UBO_1_BASE_HI__MASK 0x0001ffff
8017 #define A6XX_UBO_1_BASE_HI__SHIFT 0
A6XX_UBO_1_BASE_HI(uint32_t val)8018 static inline uint32_t A6XX_UBO_1_BASE_HI(uint32_t val)
8019 {
8020 return ((val) << A6XX_UBO_1_BASE_HI__SHIFT) & A6XX_UBO_1_BASE_HI__MASK;
8021 }
8022 #define A6XX_UBO_1_SIZE__MASK 0xfffe0000
8023 #define A6XX_UBO_1_SIZE__SHIFT 17
A6XX_UBO_1_SIZE(uint32_t val)8024 static inline uint32_t A6XX_UBO_1_SIZE(uint32_t val)
8025 {
8026 return ((val) << A6XX_UBO_1_SIZE__SHIFT) & A6XX_UBO_1_SIZE__MASK;
8027 }
8028
8029 #define REG_A6XX_PDC_GPU_ENABLE_PDC 0x00001140
8030
8031 #define REG_A6XX_PDC_GPU_SEQ_START_ADDR 0x00001148
8032
8033 #define REG_A6XX_PDC_GPU_TCS0_CONTROL 0x00001540
8034
8035 #define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK 0x00001541
8036
8037 #define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK 0x00001542
8038
8039 #define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID 0x00001543
8040
8041 #define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR 0x00001544
8042
8043 #define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA 0x00001545
8044
8045 #define REG_A6XX_PDC_GPU_TCS1_CONTROL 0x00001572
8046
8047 #define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK 0x00001573
8048
8049 #define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK 0x00001574
8050
8051 #define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID 0x00001575
8052
8053 #define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR 0x00001576
8054
8055 #define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA 0x00001577
8056
8057 #define REG_A6XX_PDC_GPU_TCS2_CONTROL 0x000015a4
8058
8059 #define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK 0x000015a5
8060
8061 #define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK 0x000015a6
8062
8063 #define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID 0x000015a7
8064
8065 #define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR 0x000015a8
8066
8067 #define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA 0x000015a9
8068
8069 #define REG_A6XX_PDC_GPU_TCS3_CONTROL 0x000015d6
8070
8071 #define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK 0x000015d7
8072
8073 #define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK 0x000015d8
8074
8075 #define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID 0x000015d9
8076
8077 #define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR 0x000015da
8078
8079 #define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA 0x000015db
8080
8081 #define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x00000000
8082
8083 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A 0x00000000
8084 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK 0x000000ff
8085 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT 0
A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val)8086 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val)
8087 {
8088 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK;
8089 }
8090 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK 0x0000ff00
8091 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT 8
A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val)8092 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val)
8093 {
8094 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK;
8095 }
8096
8097 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B 0x00000001
8098
8099 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C 0x00000002
8100
8101 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D 0x00000003
8102
8103 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT 0x00000004
8104 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f
8105 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0
A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)8106 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
8107 {
8108 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK;
8109 }
8110 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000
8111 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12
A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)8112 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
8113 {
8114 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK;
8115 }
8116 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000
8117 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28
A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)8118 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
8119 {
8120 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK;
8121 }
8122
8123 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM 0x00000005
8124 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000
8125 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24
A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)8126 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
8127 {
8128 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK;
8129 }
8130
8131 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 0x00000008
8132
8133 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 0x00000009
8134
8135 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 0x0000000a
8136
8137 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 0x0000000b
8138
8139 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 0x0000000c
8140
8141 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 0x0000000d
8142
8143 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 0x0000000e
8144
8145 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 0x0000000f
8146
8147 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000010
8148 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f
8149 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)8150 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
8151 {
8152 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK;
8153 }
8154 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0
8155 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)8156 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
8157 {
8158 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK;
8159 }
8160 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00
8161 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)8162 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
8163 {
8164 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK;
8165 }
8166 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000
8167 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)8168 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
8169 {
8170 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK;
8171 }
8172 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000
8173 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)8174 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
8175 {
8176 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK;
8177 }
8178 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000
8179 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)8180 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
8181 {
8182 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK;
8183 }
8184 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000
8185 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)8186 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
8187 {
8188 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK;
8189 }
8190 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000
8191 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)8192 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
8193 {
8194 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK;
8195 }
8196
8197 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000011
8198 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f
8199 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)8200 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
8201 {
8202 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK;
8203 }
8204 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0
8205 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)8206 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
8207 {
8208 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK;
8209 }
8210 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00
8211 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)8212 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
8213 {
8214 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK;
8215 }
8216 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000
8217 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)8218 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
8219 {
8220 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK;
8221 }
8222 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000
8223 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)8224 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
8225 {
8226 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK;
8227 }
8228 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000
8229 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)8230 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
8231 {
8232 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK;
8233 }
8234 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000
8235 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)8236 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
8237 {
8238 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK;
8239 }
8240 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000
8241 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)8242 static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
8243 {
8244 return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
8245 }
8246
8247 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000002f
8248
8249 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000030
8250
8251 #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 0x00000001
8252
8253 #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 0x00000002
8254
8255
8256 #endif /* A6XX_XML */
8257