12d756322SRob Clark #ifndef A6XX_XML 22d756322SRob Clark #define A6XX_XML 32d756322SRob Clark 42d756322SRob Clark /* Autogenerated file, DO NOT EDIT manually! 52d756322SRob Clark 62d756322SRob Clark This file was generated by the rules-ng-ng headergen tool in this git repository: 72d756322SRob Clark http://github.com/freedreno/envytools/ 82d756322SRob Clark git clone https://github.com/freedreno/envytools.git 92d756322SRob Clark 102d756322SRob Clark The rules-ng-ng source files this header was generated from are: 11*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2023-03-10 18:32:52) 12*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46) 13*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 91929 bytes, from 2023-02-28 23:52:27) 14*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from 2023-03-10 18:32:53) 15*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 74995 bytes, from 2023-03-20 18:06:23) 16*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2022-08-02 16:38:43) 17*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113474 bytes, from 2022-08-02 16:38:43) 18*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149590 bytes, from 2023-02-14 19:37:12) 19*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 198949 bytes, from 2023-03-20 18:06:23) 20*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11404 bytes, from 2023-03-10 18:32:53) 21*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2022-08-02 16:38:43) 22*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 9055 bytes, from 2023-03-10 18:32:52) 23*f73343faSRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2976 bytes, from 2023-03-10 18:32:52) 242d756322SRob Clark 25*f73343faSRob Clark Copyright (C) 2013-2023 by the following authors: 262d756322SRob Clark - Rob Clark <robdclark@gmail.com> (robclark) 272d756322SRob Clark - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 282d756322SRob Clark 292d756322SRob Clark Permission is hereby granted, free of charge, to any person obtaining 302d756322SRob Clark a copy of this software and associated documentation files (the 312d756322SRob Clark "Software"), to deal in the Software without restriction, including 322d756322SRob Clark without limitation the rights to use, copy, modify, merge, publish, 332d756322SRob Clark distribute, sublicense, and/or sell copies of the Software, and to 342d756322SRob Clark permit persons to whom the Software is furnished to do so, subject to 352d756322SRob Clark the following conditions: 362d756322SRob Clark 372d756322SRob Clark The above copyright notice and this permission notice (including the 382d756322SRob Clark next paragraph) shall be included in all copies or substantial 392d756322SRob Clark portions of the Software. 402d756322SRob Clark 412d756322SRob Clark THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 422d756322SRob Clark EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 432d756322SRob Clark MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 442d756322SRob Clark IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 452d756322SRob Clark LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 462d756322SRob Clark OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 472d756322SRob Clark WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 482d756322SRob Clark */ 492d756322SRob Clark 502d756322SRob Clark 512d756322SRob Clark enum a6xx_tile_mode { 522d756322SRob Clark TILE6_LINEAR = 0, 532d756322SRob Clark TILE6_2 = 2, 542d756322SRob Clark TILE6_3 = 3, 552d756322SRob Clark }; 562d756322SRob Clark 57c28c82e9SRob Clark enum a6xx_format { 58c28c82e9SRob Clark FMT6_A8_UNORM = 2, 59c28c82e9SRob Clark FMT6_8_UNORM = 3, 60c28c82e9SRob Clark FMT6_8_SNORM = 4, 61c28c82e9SRob Clark FMT6_8_UINT = 5, 62c28c82e9SRob Clark FMT6_8_SINT = 6, 63c28c82e9SRob Clark FMT6_4_4_4_4_UNORM = 8, 64c28c82e9SRob Clark FMT6_5_5_5_1_UNORM = 10, 65c28c82e9SRob Clark FMT6_1_5_5_5_UNORM = 12, 66c28c82e9SRob Clark FMT6_5_6_5_UNORM = 14, 67c28c82e9SRob Clark FMT6_8_8_UNORM = 15, 68c28c82e9SRob Clark FMT6_8_8_SNORM = 16, 69c28c82e9SRob Clark FMT6_8_8_UINT = 17, 70c28c82e9SRob Clark FMT6_8_8_SINT = 18, 71c28c82e9SRob Clark FMT6_L8_A8_UNORM = 19, 72c28c82e9SRob Clark FMT6_16_UNORM = 21, 73c28c82e9SRob Clark FMT6_16_SNORM = 22, 74c28c82e9SRob Clark FMT6_16_FLOAT = 23, 75c28c82e9SRob Clark FMT6_16_UINT = 24, 76c28c82e9SRob Clark FMT6_16_SINT = 25, 77c28c82e9SRob Clark FMT6_8_8_8_UNORM = 33, 78c28c82e9SRob Clark FMT6_8_8_8_SNORM = 34, 79c28c82e9SRob Clark FMT6_8_8_8_UINT = 35, 80c28c82e9SRob Clark FMT6_8_8_8_SINT = 36, 81c28c82e9SRob Clark FMT6_8_8_8_8_UNORM = 48, 82c28c82e9SRob Clark FMT6_8_8_8_X8_UNORM = 49, 83c28c82e9SRob Clark FMT6_8_8_8_8_SNORM = 50, 84c28c82e9SRob Clark FMT6_8_8_8_8_UINT = 51, 85c28c82e9SRob Clark FMT6_8_8_8_8_SINT = 52, 86c28c82e9SRob Clark FMT6_9_9_9_E5_FLOAT = 53, 87c28c82e9SRob Clark FMT6_10_10_10_2_UNORM = 54, 88c28c82e9SRob Clark FMT6_10_10_10_2_UNORM_DEST = 55, 89c28c82e9SRob Clark FMT6_10_10_10_2_SNORM = 57, 90c28c82e9SRob Clark FMT6_10_10_10_2_UINT = 58, 91c28c82e9SRob Clark FMT6_10_10_10_2_SINT = 59, 92c28c82e9SRob Clark FMT6_11_11_10_FLOAT = 66, 93c28c82e9SRob Clark FMT6_16_16_UNORM = 67, 94c28c82e9SRob Clark FMT6_16_16_SNORM = 68, 95c28c82e9SRob Clark FMT6_16_16_FLOAT = 69, 96c28c82e9SRob Clark FMT6_16_16_UINT = 70, 97c28c82e9SRob Clark FMT6_16_16_SINT = 71, 98c28c82e9SRob Clark FMT6_32_UNORM = 72, 99c28c82e9SRob Clark FMT6_32_SNORM = 73, 100c28c82e9SRob Clark FMT6_32_FLOAT = 74, 101c28c82e9SRob Clark FMT6_32_UINT = 75, 102c28c82e9SRob Clark FMT6_32_SINT = 76, 103c28c82e9SRob Clark FMT6_32_FIXED = 77, 104c28c82e9SRob Clark FMT6_16_16_16_UNORM = 88, 105c28c82e9SRob Clark FMT6_16_16_16_SNORM = 89, 106c28c82e9SRob Clark FMT6_16_16_16_FLOAT = 90, 107c28c82e9SRob Clark FMT6_16_16_16_UINT = 91, 108c28c82e9SRob Clark FMT6_16_16_16_SINT = 92, 109c28c82e9SRob Clark FMT6_16_16_16_16_UNORM = 96, 110c28c82e9SRob Clark FMT6_16_16_16_16_SNORM = 97, 111c28c82e9SRob Clark FMT6_16_16_16_16_FLOAT = 98, 112c28c82e9SRob Clark FMT6_16_16_16_16_UINT = 99, 113c28c82e9SRob Clark FMT6_16_16_16_16_SINT = 100, 114c28c82e9SRob Clark FMT6_32_32_UNORM = 101, 115c28c82e9SRob Clark FMT6_32_32_SNORM = 102, 116c28c82e9SRob Clark FMT6_32_32_FLOAT = 103, 117c28c82e9SRob Clark FMT6_32_32_UINT = 104, 118c28c82e9SRob Clark FMT6_32_32_SINT = 105, 119c28c82e9SRob Clark FMT6_32_32_FIXED = 106, 120c28c82e9SRob Clark FMT6_32_32_32_UNORM = 112, 121c28c82e9SRob Clark FMT6_32_32_32_SNORM = 113, 122c28c82e9SRob Clark FMT6_32_32_32_UINT = 114, 123c28c82e9SRob Clark FMT6_32_32_32_SINT = 115, 124c28c82e9SRob Clark FMT6_32_32_32_FLOAT = 116, 125c28c82e9SRob Clark FMT6_32_32_32_FIXED = 117, 126c28c82e9SRob Clark FMT6_32_32_32_32_UNORM = 128, 127c28c82e9SRob Clark FMT6_32_32_32_32_SNORM = 129, 128c28c82e9SRob Clark FMT6_32_32_32_32_FLOAT = 130, 129c28c82e9SRob Clark FMT6_32_32_32_32_UINT = 131, 130c28c82e9SRob Clark FMT6_32_32_32_32_SINT = 132, 131c28c82e9SRob Clark FMT6_32_32_32_32_FIXED = 133, 132c28c82e9SRob Clark FMT6_G8R8B8R8_422_UNORM = 140, 133c28c82e9SRob Clark FMT6_R8G8R8B8_422_UNORM = 141, 134c28c82e9SRob Clark FMT6_R8_G8B8_2PLANE_420_UNORM = 142, 13557cfe41cSRob Clark FMT6_NV21 = 143, 136c28c82e9SRob Clark FMT6_R8_G8_B8_3PLANE_420_UNORM = 144, 137c28c82e9SRob Clark FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 = 145, 13857cfe41cSRob Clark FMT6_NV12_Y = 148, 13957cfe41cSRob Clark FMT6_NV12_UV = 149, 14057cfe41cSRob Clark FMT6_NV12_VU = 150, 14157cfe41cSRob Clark FMT6_NV12_4R = 151, 14257cfe41cSRob Clark FMT6_NV12_4R_Y = 152, 14357cfe41cSRob Clark FMT6_NV12_4R_UV = 153, 14457cfe41cSRob Clark FMT6_P010 = 154, 14557cfe41cSRob Clark FMT6_P010_Y = 155, 14657cfe41cSRob Clark FMT6_P010_UV = 156, 14757cfe41cSRob Clark FMT6_TP10 = 157, 14857cfe41cSRob Clark FMT6_TP10_Y = 158, 14957cfe41cSRob Clark FMT6_TP10_UV = 159, 150c28c82e9SRob Clark FMT6_Z24_UNORM_S8_UINT = 160, 151c28c82e9SRob Clark FMT6_ETC2_RG11_UNORM = 171, 152c28c82e9SRob Clark FMT6_ETC2_RG11_SNORM = 172, 153c28c82e9SRob Clark FMT6_ETC2_R11_UNORM = 173, 154c28c82e9SRob Clark FMT6_ETC2_R11_SNORM = 174, 155c28c82e9SRob Clark FMT6_ETC1 = 175, 156c28c82e9SRob Clark FMT6_ETC2_RGB8 = 176, 157c28c82e9SRob Clark FMT6_ETC2_RGBA8 = 177, 158c28c82e9SRob Clark FMT6_ETC2_RGB8A1 = 178, 159c28c82e9SRob Clark FMT6_DXT1 = 179, 160c28c82e9SRob Clark FMT6_DXT3 = 180, 161c28c82e9SRob Clark FMT6_DXT5 = 181, 162c28c82e9SRob Clark FMT6_RGTC1_UNORM = 183, 163c28c82e9SRob Clark FMT6_RGTC1_SNORM = 184, 164c28c82e9SRob Clark FMT6_RGTC2_UNORM = 187, 165c28c82e9SRob Clark FMT6_RGTC2_SNORM = 188, 166c28c82e9SRob Clark FMT6_BPTC_UFLOAT = 190, 167c28c82e9SRob Clark FMT6_BPTC_FLOAT = 191, 168c28c82e9SRob Clark FMT6_BPTC = 192, 169c28c82e9SRob Clark FMT6_ASTC_4x4 = 193, 170c28c82e9SRob Clark FMT6_ASTC_5x4 = 194, 171c28c82e9SRob Clark FMT6_ASTC_5x5 = 195, 172c28c82e9SRob Clark FMT6_ASTC_6x5 = 196, 173c28c82e9SRob Clark FMT6_ASTC_6x6 = 197, 174c28c82e9SRob Clark FMT6_ASTC_8x5 = 198, 175c28c82e9SRob Clark FMT6_ASTC_8x6 = 199, 176c28c82e9SRob Clark FMT6_ASTC_8x8 = 200, 177c28c82e9SRob Clark FMT6_ASTC_10x5 = 201, 178c28c82e9SRob Clark FMT6_ASTC_10x6 = 202, 179c28c82e9SRob Clark FMT6_ASTC_10x8 = 203, 180c28c82e9SRob Clark FMT6_ASTC_10x10 = 204, 181c28c82e9SRob Clark FMT6_ASTC_12x10 = 205, 182c28c82e9SRob Clark FMT6_ASTC_12x12 = 206, 183cc4c26d4SRob Clark FMT6_Z24_UINT_S8_UINT = 234, 184c28c82e9SRob Clark FMT6_NONE = 255, 1852d756322SRob Clark }; 1862d756322SRob Clark 187c28c82e9SRob Clark enum a6xx_polygon_mode { 188c28c82e9SRob Clark POLYMODE6_POINTS = 1, 189c28c82e9SRob Clark POLYMODE6_LINES = 2, 190c28c82e9SRob Clark POLYMODE6_TRIANGLES = 3, 1912d756322SRob Clark }; 1922d756322SRob Clark 1932d756322SRob Clark enum a6xx_depth_format { 1942d756322SRob Clark DEPTH6_NONE = 0, 1952d756322SRob Clark DEPTH6_16 = 1, 1962d756322SRob Clark DEPTH6_24_8 = 2, 1972d756322SRob Clark DEPTH6_32 = 4, 1982d756322SRob Clark }; 1992d756322SRob Clark 200a69c5ed2SRob Clark enum a6xx_shader_id { 201a69c5ed2SRob Clark A6XX_TP0_TMO_DATA = 9, 202a69c5ed2SRob Clark A6XX_TP0_SMO_DATA = 10, 203a69c5ed2SRob Clark A6XX_TP0_MIPMAP_BASE_DATA = 11, 204a69c5ed2SRob Clark A6XX_TP1_TMO_DATA = 25, 205a69c5ed2SRob Clark A6XX_TP1_SMO_DATA = 26, 206a69c5ed2SRob Clark A6XX_TP1_MIPMAP_BASE_DATA = 27, 207a69c5ed2SRob Clark A6XX_SP_INST_DATA = 41, 208a69c5ed2SRob Clark A6XX_SP_LB_0_DATA = 42, 209a69c5ed2SRob Clark A6XX_SP_LB_1_DATA = 43, 210a69c5ed2SRob Clark A6XX_SP_LB_2_DATA = 44, 211a69c5ed2SRob Clark A6XX_SP_LB_3_DATA = 45, 212a69c5ed2SRob Clark A6XX_SP_LB_4_DATA = 46, 213a69c5ed2SRob Clark A6XX_SP_LB_5_DATA = 47, 214a69c5ed2SRob Clark A6XX_SP_CB_BINDLESS_DATA = 48, 215a69c5ed2SRob Clark A6XX_SP_CB_LEGACY_DATA = 49, 216a69c5ed2SRob Clark A6XX_SP_UAV_DATA = 50, 217a69c5ed2SRob Clark A6XX_SP_INST_TAG = 51, 218a69c5ed2SRob Clark A6XX_SP_CB_BINDLESS_TAG = 52, 219a69c5ed2SRob Clark A6XX_SP_TMO_UMO_TAG = 53, 220a69c5ed2SRob Clark A6XX_SP_SMO_TAG = 54, 221a69c5ed2SRob Clark A6XX_SP_STATE_DATA = 55, 222a69c5ed2SRob Clark A6XX_HLSQ_CHUNK_CVS_RAM = 73, 223a69c5ed2SRob Clark A6XX_HLSQ_CHUNK_CPS_RAM = 74, 224a69c5ed2SRob Clark A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75, 225a69c5ed2SRob Clark A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76, 226a69c5ed2SRob Clark A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77, 227a69c5ed2SRob Clark A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78, 228a69c5ed2SRob Clark A6XX_HLSQ_CVS_MISC_RAM = 80, 229a69c5ed2SRob Clark A6XX_HLSQ_CPS_MISC_RAM = 81, 230a69c5ed2SRob Clark A6XX_HLSQ_INST_RAM = 82, 231a69c5ed2SRob Clark A6XX_HLSQ_GFX_CVS_CONST_RAM = 83, 232a69c5ed2SRob Clark A6XX_HLSQ_GFX_CPS_CONST_RAM = 84, 233a69c5ed2SRob Clark A6XX_HLSQ_CVS_MISC_RAM_TAG = 85, 234a69c5ed2SRob Clark A6XX_HLSQ_CPS_MISC_RAM_TAG = 86, 235a69c5ed2SRob Clark A6XX_HLSQ_INST_RAM_TAG = 87, 236a69c5ed2SRob Clark A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88, 237a69c5ed2SRob Clark A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89, 238a69c5ed2SRob Clark A6XX_HLSQ_PWR_REST_RAM = 90, 239a69c5ed2SRob Clark A6XX_HLSQ_PWR_REST_TAG = 91, 240a69c5ed2SRob Clark A6XX_HLSQ_DATAPATH_META = 96, 241a69c5ed2SRob Clark A6XX_HLSQ_FRONTEND_META = 97, 242a69c5ed2SRob Clark A6XX_HLSQ_INDIRECT_META = 98, 243a69c5ed2SRob Clark A6XX_HLSQ_BACKEND_META = 99, 2441e05bba5SAkhil P Oommen A6XX_SP_LB_6_DATA = 112, 2451e05bba5SAkhil P Oommen A6XX_SP_LB_7_DATA = 113, 2461e05bba5SAkhil P Oommen A6XX_HLSQ_INST_RAM_1 = 115, 247a69c5ed2SRob Clark }; 248a69c5ed2SRob Clark 249a69c5ed2SRob Clark enum a6xx_debugbus_id { 250a69c5ed2SRob Clark A6XX_DBGBUS_CP = 1, 251a69c5ed2SRob Clark A6XX_DBGBUS_RBBM = 2, 252a69c5ed2SRob Clark A6XX_DBGBUS_VBIF = 3, 253a69c5ed2SRob Clark A6XX_DBGBUS_HLSQ = 4, 254a69c5ed2SRob Clark A6XX_DBGBUS_UCHE = 5, 255a69c5ed2SRob Clark A6XX_DBGBUS_DPM = 6, 256a69c5ed2SRob Clark A6XX_DBGBUS_TESS = 7, 257a69c5ed2SRob Clark A6XX_DBGBUS_PC = 8, 258a69c5ed2SRob Clark A6XX_DBGBUS_VFDP = 9, 259a69c5ed2SRob Clark A6XX_DBGBUS_VPC = 10, 260a69c5ed2SRob Clark A6XX_DBGBUS_TSE = 11, 261a69c5ed2SRob Clark A6XX_DBGBUS_RAS = 12, 262a69c5ed2SRob Clark A6XX_DBGBUS_VSC = 13, 263a69c5ed2SRob Clark A6XX_DBGBUS_COM = 14, 264a69c5ed2SRob Clark A6XX_DBGBUS_LRZ = 16, 265a69c5ed2SRob Clark A6XX_DBGBUS_A2D = 17, 266a69c5ed2SRob Clark A6XX_DBGBUS_CCUFCHE = 18, 267a69c5ed2SRob Clark A6XX_DBGBUS_GMU_CX = 19, 268a69c5ed2SRob Clark A6XX_DBGBUS_RBP = 20, 269a69c5ed2SRob Clark A6XX_DBGBUS_DCS = 21, 270a69c5ed2SRob Clark A6XX_DBGBUS_DBGC = 22, 271a69c5ed2SRob Clark A6XX_DBGBUS_CX = 23, 272a69c5ed2SRob Clark A6XX_DBGBUS_GMU_GX = 24, 273a69c5ed2SRob Clark A6XX_DBGBUS_TPFCHE = 25, 274a69c5ed2SRob Clark A6XX_DBGBUS_GBIF_GX = 26, 275a69c5ed2SRob Clark A6XX_DBGBUS_GPC = 29, 276a69c5ed2SRob Clark A6XX_DBGBUS_LARC = 30, 277a69c5ed2SRob Clark A6XX_DBGBUS_HLSQ_SPTP = 31, 278a69c5ed2SRob Clark A6XX_DBGBUS_RB_0 = 32, 279a69c5ed2SRob Clark A6XX_DBGBUS_RB_1 = 33, 2801e05bba5SAkhil P Oommen A6XX_DBGBUS_RB_2 = 34, 281a69c5ed2SRob Clark A6XX_DBGBUS_UCHE_WRAPPER = 36, 282a69c5ed2SRob Clark A6XX_DBGBUS_CCU_0 = 40, 283a69c5ed2SRob Clark A6XX_DBGBUS_CCU_1 = 41, 2841e05bba5SAkhil P Oommen A6XX_DBGBUS_CCU_2 = 42, 285a69c5ed2SRob Clark A6XX_DBGBUS_VFD_0 = 56, 286a69c5ed2SRob Clark A6XX_DBGBUS_VFD_1 = 57, 287a69c5ed2SRob Clark A6XX_DBGBUS_VFD_2 = 58, 288a69c5ed2SRob Clark A6XX_DBGBUS_VFD_3 = 59, 2891e05bba5SAkhil P Oommen A6XX_DBGBUS_VFD_4 = 60, 2901e05bba5SAkhil P Oommen A6XX_DBGBUS_VFD_5 = 61, 291a69c5ed2SRob Clark A6XX_DBGBUS_SP_0 = 64, 292a69c5ed2SRob Clark A6XX_DBGBUS_SP_1 = 65, 2931e05bba5SAkhil P Oommen A6XX_DBGBUS_SP_2 = 66, 294a69c5ed2SRob Clark A6XX_DBGBUS_TPL1_0 = 72, 295a69c5ed2SRob Clark A6XX_DBGBUS_TPL1_1 = 73, 296a69c5ed2SRob Clark A6XX_DBGBUS_TPL1_2 = 74, 297a69c5ed2SRob Clark A6XX_DBGBUS_TPL1_3 = 75, 2981e05bba5SAkhil P Oommen A6XX_DBGBUS_TPL1_4 = 76, 2991e05bba5SAkhil P Oommen A6XX_DBGBUS_TPL1_5 = 77, 3001e05bba5SAkhil P Oommen A6XX_DBGBUS_SPTP_0 = 88, 3011e05bba5SAkhil P Oommen A6XX_DBGBUS_SPTP_1 = 89, 3021e05bba5SAkhil P Oommen A6XX_DBGBUS_SPTP_2 = 90, 3031e05bba5SAkhil P Oommen A6XX_DBGBUS_SPTP_3 = 91, 3041e05bba5SAkhil P Oommen A6XX_DBGBUS_SPTP_4 = 92, 3051e05bba5SAkhil P Oommen A6XX_DBGBUS_SPTP_5 = 93, 306a69c5ed2SRob Clark }; 307a69c5ed2SRob Clark 3082d756322SRob Clark enum a6xx_cp_perfcounter_select { 3092d756322SRob Clark PERF_CP_ALWAYS_COUNT = 0, 310a69c5ed2SRob Clark PERF_CP_BUSY_GFX_CORE_IDLE = 1, 311a69c5ed2SRob Clark PERF_CP_BUSY_CYCLES = 2, 312a69c5ed2SRob Clark PERF_CP_NUM_PREEMPTIONS = 3, 313a69c5ed2SRob Clark PERF_CP_PREEMPTION_REACTION_DELAY = 4, 314a69c5ed2SRob Clark PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 5, 315a69c5ed2SRob Clark PERF_CP_PREEMPTION_SWITCH_IN_TIME = 6, 316a69c5ed2SRob Clark PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 7, 317a69c5ed2SRob Clark PERF_CP_PREDICATED_DRAWS_KILLED = 8, 318a69c5ed2SRob Clark PERF_CP_MODE_SWITCH = 9, 319a69c5ed2SRob Clark PERF_CP_ZPASS_DONE = 10, 320a69c5ed2SRob Clark PERF_CP_CONTEXT_DONE = 11, 321a69c5ed2SRob Clark PERF_CP_CACHE_FLUSH = 12, 322a69c5ed2SRob Clark PERF_CP_LONG_PREEMPTIONS = 13, 323a69c5ed2SRob Clark PERF_CP_SQE_I_CACHE_STARVE = 14, 324a69c5ed2SRob Clark PERF_CP_SQE_IDLE = 15, 325a69c5ed2SRob Clark PERF_CP_SQE_PM4_STARVE_RB_IB = 16, 326a69c5ed2SRob Clark PERF_CP_SQE_PM4_STARVE_SDS = 17, 327a69c5ed2SRob Clark PERF_CP_SQE_MRB_STARVE = 18, 328a69c5ed2SRob Clark PERF_CP_SQE_RRB_STARVE = 19, 329a69c5ed2SRob Clark PERF_CP_SQE_VSD_STARVE = 20, 330a69c5ed2SRob Clark PERF_CP_VSD_DECODE_STARVE = 21, 331a69c5ed2SRob Clark PERF_CP_SQE_PIPE_OUT_STALL = 22, 332a69c5ed2SRob Clark PERF_CP_SQE_SYNC_STALL = 23, 333a69c5ed2SRob Clark PERF_CP_SQE_PM4_WFI_STALL = 24, 334a69c5ed2SRob Clark PERF_CP_SQE_SYS_WFI_STALL = 25, 335a69c5ed2SRob Clark PERF_CP_SQE_T4_EXEC = 26, 336a69c5ed2SRob Clark PERF_CP_SQE_LOAD_STATE_EXEC = 27, 337a69c5ed2SRob Clark PERF_CP_SQE_SAVE_SDS_STATE = 28, 338a69c5ed2SRob Clark PERF_CP_SQE_DRAW_EXEC = 29, 339a69c5ed2SRob Clark PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 30, 340a69c5ed2SRob Clark PERF_CP_SQE_EXEC_PROFILED = 31, 341a69c5ed2SRob Clark PERF_CP_MEMORY_POOL_EMPTY = 32, 342a69c5ed2SRob Clark PERF_CP_MEMORY_POOL_SYNC_STALL = 33, 343a69c5ed2SRob Clark PERF_CP_MEMORY_POOL_ABOVE_THRESH = 34, 344a69c5ed2SRob Clark PERF_CP_AHB_WR_STALL_PRE_DRAWS = 35, 345a69c5ed2SRob Clark PERF_CP_AHB_STALL_SQE_GMU = 36, 346a69c5ed2SRob Clark PERF_CP_AHB_STALL_SQE_WR_OTHER = 37, 347a69c5ed2SRob Clark PERF_CP_AHB_STALL_SQE_RD_OTHER = 38, 348a69c5ed2SRob Clark PERF_CP_CLUSTER0_EMPTY = 39, 349a69c5ed2SRob Clark PERF_CP_CLUSTER1_EMPTY = 40, 350a69c5ed2SRob Clark PERF_CP_CLUSTER2_EMPTY = 41, 351a69c5ed2SRob Clark PERF_CP_CLUSTER3_EMPTY = 42, 352a69c5ed2SRob Clark PERF_CP_CLUSTER4_EMPTY = 43, 353a69c5ed2SRob Clark PERF_CP_CLUSTER5_EMPTY = 44, 354a69c5ed2SRob Clark PERF_CP_PM4_DATA = 45, 355a69c5ed2SRob Clark PERF_CP_PM4_HEADERS = 46, 356a69c5ed2SRob Clark PERF_CP_VBIF_READ_BEATS = 47, 357a69c5ed2SRob Clark PERF_CP_VBIF_WRITE_BEATS = 48, 358a69c5ed2SRob Clark PERF_CP_SQE_INSTR_COUNTER = 49, 359a69c5ed2SRob Clark }; 360a69c5ed2SRob Clark 361a69c5ed2SRob Clark enum a6xx_rbbm_perfcounter_select { 362a69c5ed2SRob Clark PERF_RBBM_ALWAYS_COUNT = 0, 363a69c5ed2SRob Clark PERF_RBBM_ALWAYS_ON = 1, 364a69c5ed2SRob Clark PERF_RBBM_TSE_BUSY = 2, 365a69c5ed2SRob Clark PERF_RBBM_RAS_BUSY = 3, 366a69c5ed2SRob Clark PERF_RBBM_PC_DCALL_BUSY = 4, 367a69c5ed2SRob Clark PERF_RBBM_PC_VSD_BUSY = 5, 368a69c5ed2SRob Clark PERF_RBBM_STATUS_MASKED = 6, 369a69c5ed2SRob Clark PERF_RBBM_COM_BUSY = 7, 370a69c5ed2SRob Clark PERF_RBBM_DCOM_BUSY = 8, 371a69c5ed2SRob Clark PERF_RBBM_VBIF_BUSY = 9, 372a69c5ed2SRob Clark PERF_RBBM_VSC_BUSY = 10, 373a69c5ed2SRob Clark PERF_RBBM_TESS_BUSY = 11, 374a69c5ed2SRob Clark PERF_RBBM_UCHE_BUSY = 12, 375a69c5ed2SRob Clark PERF_RBBM_HLSQ_BUSY = 13, 376a69c5ed2SRob Clark }; 377a69c5ed2SRob Clark 378a69c5ed2SRob Clark enum a6xx_pc_perfcounter_select { 379a69c5ed2SRob Clark PERF_PC_BUSY_CYCLES = 0, 380a69c5ed2SRob Clark PERF_PC_WORKING_CYCLES = 1, 381a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_VFD = 2, 382a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_TSE = 3, 383a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_VPC = 4, 384a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_UCHE = 5, 385a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_TESS = 6, 386a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_TSE_ONLY = 7, 387a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_VPC_ONLY = 8, 388a69c5ed2SRob Clark PERF_PC_PASS1_TF_STALL_CYCLES = 9, 389a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_FOR_INDEX = 10, 390a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11, 391a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12, 392a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_FOR_POSITION = 13, 393a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_DI = 14, 394a69c5ed2SRob Clark PERF_PC_VIS_STREAMS_LOADED = 15, 395a69c5ed2SRob Clark PERF_PC_INSTANCES = 16, 396a69c5ed2SRob Clark PERF_PC_VPC_PRIMITIVES = 17, 397a69c5ed2SRob Clark PERF_PC_DEAD_PRIM = 18, 398a69c5ed2SRob Clark PERF_PC_LIVE_PRIM = 19, 399a69c5ed2SRob Clark PERF_PC_VERTEX_HITS = 20, 400a69c5ed2SRob Clark PERF_PC_IA_VERTICES = 21, 401a69c5ed2SRob Clark PERF_PC_IA_PRIMITIVES = 22, 402a69c5ed2SRob Clark PERF_PC_GS_PRIMITIVES = 23, 403a69c5ed2SRob Clark PERF_PC_HS_INVOCATIONS = 24, 404a69c5ed2SRob Clark PERF_PC_DS_INVOCATIONS = 25, 405a69c5ed2SRob Clark PERF_PC_VS_INVOCATIONS = 26, 406a69c5ed2SRob Clark PERF_PC_GS_INVOCATIONS = 27, 407a69c5ed2SRob Clark PERF_PC_DS_PRIMITIVES = 28, 408a69c5ed2SRob Clark PERF_PC_VPC_POS_DATA_TRANSACTION = 29, 409a69c5ed2SRob Clark PERF_PC_3D_DRAWCALLS = 30, 410a69c5ed2SRob Clark PERF_PC_2D_DRAWCALLS = 31, 411a69c5ed2SRob Clark PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32, 412a69c5ed2SRob Clark PERF_TESS_BUSY_CYCLES = 33, 413a69c5ed2SRob Clark PERF_TESS_WORKING_CYCLES = 34, 414a69c5ed2SRob Clark PERF_TESS_STALL_CYCLES_PC = 35, 415a69c5ed2SRob Clark PERF_TESS_STARVE_CYCLES_PC = 36, 416a69c5ed2SRob Clark PERF_PC_TSE_TRANSACTION = 37, 417a69c5ed2SRob Clark PERF_PC_TSE_VERTEX = 38, 418a69c5ed2SRob Clark PERF_PC_TESS_PC_UV_TRANS = 39, 419a69c5ed2SRob Clark PERF_PC_TESS_PC_UV_PATCHES = 40, 420a69c5ed2SRob Clark PERF_PC_TESS_FACTOR_TRANS = 41, 421a69c5ed2SRob Clark }; 422a69c5ed2SRob Clark 423a69c5ed2SRob Clark enum a6xx_vfd_perfcounter_select { 424a69c5ed2SRob Clark PERF_VFD_BUSY_CYCLES = 0, 425a69c5ed2SRob Clark PERF_VFD_STALL_CYCLES_UCHE = 1, 426a69c5ed2SRob Clark PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2, 427a69c5ed2SRob Clark PERF_VFD_STALL_CYCLES_SP_INFO = 3, 428a69c5ed2SRob Clark PERF_VFD_STALL_CYCLES_SP_ATTR = 4, 429a69c5ed2SRob Clark PERF_VFD_STARVE_CYCLES_UCHE = 5, 430a69c5ed2SRob Clark PERF_VFD_RBUFFER_FULL = 6, 431a69c5ed2SRob Clark PERF_VFD_ATTR_INFO_FIFO_FULL = 7, 432a69c5ed2SRob Clark PERF_VFD_DECODED_ATTRIBUTE_BYTES = 8, 433a69c5ed2SRob Clark PERF_VFD_NUM_ATTRIBUTES = 9, 434a69c5ed2SRob Clark PERF_VFD_UPPER_SHADER_FIBERS = 10, 435a69c5ed2SRob Clark PERF_VFD_LOWER_SHADER_FIBERS = 11, 436a69c5ed2SRob Clark PERF_VFD_MODE_0_FIBERS = 12, 437a69c5ed2SRob Clark PERF_VFD_MODE_1_FIBERS = 13, 438a69c5ed2SRob Clark PERF_VFD_MODE_2_FIBERS = 14, 439a69c5ed2SRob Clark PERF_VFD_MODE_3_FIBERS = 15, 440a69c5ed2SRob Clark PERF_VFD_MODE_4_FIBERS = 16, 441a69c5ed2SRob Clark PERF_VFD_TOTAL_VERTICES = 17, 442a69c5ed2SRob Clark PERF_VFDP_STALL_CYCLES_VFD = 18, 443a69c5ed2SRob Clark PERF_VFDP_STALL_CYCLES_VFD_INDEX = 19, 444a69c5ed2SRob Clark PERF_VFDP_STALL_CYCLES_VFD_PROG = 20, 445a69c5ed2SRob Clark PERF_VFDP_STARVE_CYCLES_PC = 21, 446a69c5ed2SRob Clark PERF_VFDP_VS_STAGE_WAVES = 22, 447a69c5ed2SRob Clark }; 448a69c5ed2SRob Clark 449ccdf7e28SRob Clark enum a6xx_hlsq_perfcounter_select { 450a69c5ed2SRob Clark PERF_HLSQ_BUSY_CYCLES = 0, 451a69c5ed2SRob Clark PERF_HLSQ_STALL_CYCLES_UCHE = 1, 452a69c5ed2SRob Clark PERF_HLSQ_STALL_CYCLES_SP_STATE = 2, 453a69c5ed2SRob Clark PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3, 454a69c5ed2SRob Clark PERF_HLSQ_UCHE_LATENCY_CYCLES = 4, 455a69c5ed2SRob Clark PERF_HLSQ_UCHE_LATENCY_COUNT = 5, 456a69c5ed2SRob Clark PERF_HLSQ_FS_STAGE_1X_WAVES = 6, 457a69c5ed2SRob Clark PERF_HLSQ_FS_STAGE_2X_WAVES = 7, 458a69c5ed2SRob Clark PERF_HLSQ_QUADS = 8, 459a69c5ed2SRob Clark PERF_HLSQ_CS_INVOCATIONS = 9, 460a69c5ed2SRob Clark PERF_HLSQ_COMPUTE_DRAWCALLS = 10, 461a69c5ed2SRob Clark PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11, 462a69c5ed2SRob Clark PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12, 463a69c5ed2SRob Clark PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13, 464a69c5ed2SRob Clark PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14, 465a69c5ed2SRob Clark PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15, 466a69c5ed2SRob Clark PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16, 467a69c5ed2SRob Clark PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17, 468a69c5ed2SRob Clark PERF_HLSQ_STALL_CYCLES_VPC = 18, 469a69c5ed2SRob Clark PERF_HLSQ_PIXELS = 19, 470a69c5ed2SRob Clark PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = 20, 471a69c5ed2SRob Clark }; 472a69c5ed2SRob Clark 473a69c5ed2SRob Clark enum a6xx_vpc_perfcounter_select { 474a69c5ed2SRob Clark PERF_VPC_BUSY_CYCLES = 0, 475a69c5ed2SRob Clark PERF_VPC_WORKING_CYCLES = 1, 476a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_UCHE = 2, 477a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_VFD_WACK = 3, 478a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4, 479a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_PC = 5, 480a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_SP_LM = 6, 481a69c5ed2SRob Clark PERF_VPC_STARVE_CYCLES_SP = 7, 482a69c5ed2SRob Clark PERF_VPC_STARVE_CYCLES_LRZ = 8, 483a69c5ed2SRob Clark PERF_VPC_PC_PRIMITIVES = 9, 484a69c5ed2SRob Clark PERF_VPC_SP_COMPONENTS = 10, 485a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_VPCRAM_POS = 11, 486a69c5ed2SRob Clark PERF_VPC_LRZ_ASSIGN_PRIMITIVES = 12, 487a69c5ed2SRob Clark PERF_VPC_RB_VISIBLE_PRIMITIVES = 13, 488a69c5ed2SRob Clark PERF_VPC_LM_TRANSACTION = 14, 489a69c5ed2SRob Clark PERF_VPC_STREAMOUT_TRANSACTION = 15, 490a69c5ed2SRob Clark PERF_VPC_VS_BUSY_CYCLES = 16, 491a69c5ed2SRob Clark PERF_VPC_PS_BUSY_CYCLES = 17, 492a69c5ed2SRob Clark PERF_VPC_VS_WORKING_CYCLES = 18, 493a69c5ed2SRob Clark PERF_VPC_PS_WORKING_CYCLES = 19, 494a69c5ed2SRob Clark PERF_VPC_STARVE_CYCLES_RB = 20, 495a69c5ed2SRob Clark PERF_VPC_NUM_VPCRAM_READ_POS = 21, 496a69c5ed2SRob Clark PERF_VPC_WIT_FULL_CYCLES = 22, 497a69c5ed2SRob Clark PERF_VPC_VPCRAM_FULL_CYCLES = 23, 498a69c5ed2SRob Clark PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = 24, 499a69c5ed2SRob Clark PERF_VPC_NUM_VPCRAM_WRITE = 25, 500a69c5ed2SRob Clark PERF_VPC_NUM_VPCRAM_READ_SO = 26, 501a69c5ed2SRob Clark PERF_VPC_NUM_ATTR_REQ_LM = 27, 502a69c5ed2SRob Clark }; 503a69c5ed2SRob Clark 504a69c5ed2SRob Clark enum a6xx_tse_perfcounter_select { 505a69c5ed2SRob Clark PERF_TSE_BUSY_CYCLES = 0, 506a69c5ed2SRob Clark PERF_TSE_CLIPPING_CYCLES = 1, 507a69c5ed2SRob Clark PERF_TSE_STALL_CYCLES_RAS = 2, 508a69c5ed2SRob Clark PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3, 509a69c5ed2SRob Clark PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4, 510a69c5ed2SRob Clark PERF_TSE_STARVE_CYCLES_PC = 5, 511a69c5ed2SRob Clark PERF_TSE_INPUT_PRIM = 6, 512a69c5ed2SRob Clark PERF_TSE_INPUT_NULL_PRIM = 7, 513a69c5ed2SRob Clark PERF_TSE_TRIVAL_REJ_PRIM = 8, 514a69c5ed2SRob Clark PERF_TSE_CLIPPED_PRIM = 9, 515a69c5ed2SRob Clark PERF_TSE_ZERO_AREA_PRIM = 10, 516a69c5ed2SRob Clark PERF_TSE_FACENESS_CULLED_PRIM = 11, 517a69c5ed2SRob Clark PERF_TSE_ZERO_PIXEL_PRIM = 12, 518a69c5ed2SRob Clark PERF_TSE_OUTPUT_NULL_PRIM = 13, 519a69c5ed2SRob Clark PERF_TSE_OUTPUT_VISIBLE_PRIM = 14, 520a69c5ed2SRob Clark PERF_TSE_CINVOCATION = 15, 521a69c5ed2SRob Clark PERF_TSE_CPRIMITIVES = 16, 522a69c5ed2SRob Clark PERF_TSE_2D_INPUT_PRIM = 17, 523a69c5ed2SRob Clark PERF_TSE_2D_ALIVE_CYCLES = 18, 524a69c5ed2SRob Clark PERF_TSE_CLIP_PLANES = 19, 525a69c5ed2SRob Clark }; 526a69c5ed2SRob Clark 527a69c5ed2SRob Clark enum a6xx_ras_perfcounter_select { 528a69c5ed2SRob Clark PERF_RAS_BUSY_CYCLES = 0, 529a69c5ed2SRob Clark PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1, 530a69c5ed2SRob Clark PERF_RAS_STALL_CYCLES_LRZ = 2, 531a69c5ed2SRob Clark PERF_RAS_STARVE_CYCLES_TSE = 3, 532a69c5ed2SRob Clark PERF_RAS_SUPER_TILES = 4, 533a69c5ed2SRob Clark PERF_RAS_8X4_TILES = 5, 534a69c5ed2SRob Clark PERF_RAS_MASKGEN_ACTIVE = 6, 535a69c5ed2SRob Clark PERF_RAS_FULLY_COVERED_SUPER_TILES = 7, 536a69c5ed2SRob Clark PERF_RAS_FULLY_COVERED_8X4_TILES = 8, 537a69c5ed2SRob Clark PERF_RAS_PRIM_KILLED_INVISILBE = 9, 538a69c5ed2SRob Clark PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 10, 539a69c5ed2SRob Clark PERF_RAS_LRZ_INTF_WORKING_CYCLES = 11, 540a69c5ed2SRob Clark PERF_RAS_BLOCKS = 12, 541a69c5ed2SRob Clark }; 542a69c5ed2SRob Clark 543a69c5ed2SRob Clark enum a6xx_uche_perfcounter_select { 544a69c5ed2SRob Clark PERF_UCHE_BUSY_CYCLES = 0, 545a69c5ed2SRob Clark PERF_UCHE_STALL_CYCLES_ARBITER = 1, 546a69c5ed2SRob Clark PERF_UCHE_VBIF_LATENCY_CYCLES = 2, 547a69c5ed2SRob Clark PERF_UCHE_VBIF_LATENCY_SAMPLES = 3, 548a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_TP = 4, 549a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_VFD = 5, 550a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6, 551a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_LRZ = 7, 552a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_SP = 8, 553a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_TP = 9, 554a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_VFD = 10, 555a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_HLSQ = 11, 556a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_LRZ = 12, 557a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_SP = 13, 558a69c5ed2SRob Clark PERF_UCHE_WRITE_REQUESTS_LRZ = 14, 559a69c5ed2SRob Clark PERF_UCHE_WRITE_REQUESTS_SP = 15, 560a69c5ed2SRob Clark PERF_UCHE_WRITE_REQUESTS_VPC = 16, 561a69c5ed2SRob Clark PERF_UCHE_WRITE_REQUESTS_VSC = 17, 562a69c5ed2SRob Clark PERF_UCHE_EVICTS = 18, 563a69c5ed2SRob Clark PERF_UCHE_BANK_REQ0 = 19, 564a69c5ed2SRob Clark PERF_UCHE_BANK_REQ1 = 20, 565a69c5ed2SRob Clark PERF_UCHE_BANK_REQ2 = 21, 566a69c5ed2SRob Clark PERF_UCHE_BANK_REQ3 = 22, 567a69c5ed2SRob Clark PERF_UCHE_BANK_REQ4 = 23, 568a69c5ed2SRob Clark PERF_UCHE_BANK_REQ5 = 24, 569a69c5ed2SRob Clark PERF_UCHE_BANK_REQ6 = 25, 570a69c5ed2SRob Clark PERF_UCHE_BANK_REQ7 = 26, 571a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_CH0 = 27, 572a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_CH1 = 28, 573a69c5ed2SRob Clark PERF_UCHE_GMEM_READ_BEATS = 29, 574a69c5ed2SRob Clark PERF_UCHE_TPH_REF_FULL = 30, 575a69c5ed2SRob Clark PERF_UCHE_TPH_VICTIM_FULL = 31, 576a69c5ed2SRob Clark PERF_UCHE_TPH_EXT_FULL = 32, 577a69c5ed2SRob Clark PERF_UCHE_VBIF_STALL_WRITE_DATA = 33, 578a69c5ed2SRob Clark PERF_UCHE_DCMP_LATENCY_SAMPLES = 34, 579a69c5ed2SRob Clark PERF_UCHE_DCMP_LATENCY_CYCLES = 35, 580a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_PC = 36, 581a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_PC = 37, 582a69c5ed2SRob Clark PERF_UCHE_RAM_READ_REQ = 38, 583a69c5ed2SRob Clark PERF_UCHE_RAM_WRITE_REQ = 39, 584a69c5ed2SRob Clark }; 585a69c5ed2SRob Clark 586a69c5ed2SRob Clark enum a6xx_tp_perfcounter_select { 587a69c5ed2SRob Clark PERF_TP_BUSY_CYCLES = 0, 588a69c5ed2SRob Clark PERF_TP_STALL_CYCLES_UCHE = 1, 589a69c5ed2SRob Clark PERF_TP_LATENCY_CYCLES = 2, 590a69c5ed2SRob Clark PERF_TP_LATENCY_TRANS = 3, 591a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4, 592a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5, 593a69c5ed2SRob Clark PERF_TP_L1_CACHELINE_REQUESTS = 6, 594a69c5ed2SRob Clark PERF_TP_L1_CACHELINE_MISSES = 7, 595a69c5ed2SRob Clark PERF_TP_SP_TP_TRANS = 8, 596a69c5ed2SRob Clark PERF_TP_TP_SP_TRANS = 9, 597a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS = 10, 598a69c5ed2SRob Clark PERF_TP_FILTER_WORKLOAD_16BIT = 11, 599a69c5ed2SRob Clark PERF_TP_FILTER_WORKLOAD_32BIT = 12, 600a69c5ed2SRob Clark PERF_TP_QUADS_RECEIVED = 13, 601a69c5ed2SRob Clark PERF_TP_QUADS_OFFSET = 14, 602a69c5ed2SRob Clark PERF_TP_QUADS_SHADOW = 15, 603a69c5ed2SRob Clark PERF_TP_QUADS_ARRAY = 16, 604a69c5ed2SRob Clark PERF_TP_QUADS_GRADIENT = 17, 605a69c5ed2SRob Clark PERF_TP_QUADS_1D = 18, 606a69c5ed2SRob Clark PERF_TP_QUADS_2D = 19, 607a69c5ed2SRob Clark PERF_TP_QUADS_BUFFER = 20, 608a69c5ed2SRob Clark PERF_TP_QUADS_3D = 21, 609a69c5ed2SRob Clark PERF_TP_QUADS_CUBE = 22, 610a69c5ed2SRob Clark PERF_TP_DIVERGENT_QUADS_RECEIVED = 23, 611a69c5ed2SRob Clark PERF_TP_PRT_NON_RESIDENT_EVENTS = 24, 612a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_POINT = 25, 613a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_BILINEAR = 26, 614a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_MIP = 27, 615a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_ANISO = 28, 616a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 29, 617a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_REQUESTS = 30, 618a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_MISSES = 31, 619a69c5ed2SRob Clark PERF_TP_L1_5_L2_REQUESTS = 32, 620a69c5ed2SRob Clark PERF_TP_2D_OUTPUT_PIXELS = 33, 621a69c5ed2SRob Clark PERF_TP_2D_OUTPUT_PIXELS_POINT = 34, 622a69c5ed2SRob Clark PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 35, 623a69c5ed2SRob Clark PERF_TP_2D_FILTER_WORKLOAD_16BIT = 36, 624a69c5ed2SRob Clark PERF_TP_2D_FILTER_WORKLOAD_32BIT = 37, 625a69c5ed2SRob Clark PERF_TP_TPA2TPC_TRANS = 38, 626a69c5ed2SRob Clark PERF_TP_L1_MISSES_ASTC_1TILE = 39, 627a69c5ed2SRob Clark PERF_TP_L1_MISSES_ASTC_2TILE = 40, 628a69c5ed2SRob Clark PERF_TP_L1_MISSES_ASTC_4TILE = 41, 629a69c5ed2SRob Clark PERF_TP_L1_5_L2_COMPRESS_REQS = 42, 630a69c5ed2SRob Clark PERF_TP_L1_5_L2_COMPRESS_MISS = 43, 631a69c5ed2SRob Clark PERF_TP_L1_BANK_CONFLICT = 44, 632a69c5ed2SRob Clark PERF_TP_L1_5_MISS_LATENCY_CYCLES = 45, 633a69c5ed2SRob Clark PERF_TP_L1_5_MISS_LATENCY_TRANS = 46, 634a69c5ed2SRob Clark PERF_TP_QUADS_CONSTANT_MULTIPLIED = 47, 635a69c5ed2SRob Clark PERF_TP_FRONTEND_WORKING_CYCLES = 48, 636a69c5ed2SRob Clark PERF_TP_L1_TAG_WORKING_CYCLES = 49, 637a69c5ed2SRob Clark PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 50, 638a69c5ed2SRob Clark PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 51, 639a69c5ed2SRob Clark PERF_TP_BACKEND_WORKING_CYCLES = 52, 640a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_WORKING_CYCLES = 53, 641a69c5ed2SRob Clark PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54, 642a69c5ed2SRob Clark PERF_TP_STARVE_CYCLES_SP = 55, 643a69c5ed2SRob Clark PERF_TP_STARVE_CYCLES_UCHE = 56, 644a69c5ed2SRob Clark }; 645a69c5ed2SRob Clark 646a69c5ed2SRob Clark enum a6xx_sp_perfcounter_select { 647a69c5ed2SRob Clark PERF_SP_BUSY_CYCLES = 0, 648a69c5ed2SRob Clark PERF_SP_ALU_WORKING_CYCLES = 1, 649a69c5ed2SRob Clark PERF_SP_EFU_WORKING_CYCLES = 2, 650a69c5ed2SRob Clark PERF_SP_STALL_CYCLES_VPC = 3, 651a69c5ed2SRob Clark PERF_SP_STALL_CYCLES_TP = 4, 652a69c5ed2SRob Clark PERF_SP_STALL_CYCLES_UCHE = 5, 653a69c5ed2SRob Clark PERF_SP_STALL_CYCLES_RB = 6, 654a69c5ed2SRob Clark PERF_SP_NON_EXECUTION_CYCLES = 7, 655a69c5ed2SRob Clark PERF_SP_WAVE_CONTEXTS = 8, 656a69c5ed2SRob Clark PERF_SP_WAVE_CONTEXT_CYCLES = 9, 657a69c5ed2SRob Clark PERF_SP_FS_STAGE_WAVE_CYCLES = 10, 658a69c5ed2SRob Clark PERF_SP_FS_STAGE_WAVE_SAMPLES = 11, 659a69c5ed2SRob Clark PERF_SP_VS_STAGE_WAVE_CYCLES = 12, 660a69c5ed2SRob Clark PERF_SP_VS_STAGE_WAVE_SAMPLES = 13, 661a69c5ed2SRob Clark PERF_SP_FS_STAGE_DURATION_CYCLES = 14, 662a69c5ed2SRob Clark PERF_SP_VS_STAGE_DURATION_CYCLES = 15, 663a69c5ed2SRob Clark PERF_SP_WAVE_CTRL_CYCLES = 16, 664a69c5ed2SRob Clark PERF_SP_WAVE_LOAD_CYCLES = 17, 665a69c5ed2SRob Clark PERF_SP_WAVE_EMIT_CYCLES = 18, 666a69c5ed2SRob Clark PERF_SP_WAVE_NOP_CYCLES = 19, 667a69c5ed2SRob Clark PERF_SP_WAVE_WAIT_CYCLES = 20, 668a69c5ed2SRob Clark PERF_SP_WAVE_FETCH_CYCLES = 21, 669a69c5ed2SRob Clark PERF_SP_WAVE_IDLE_CYCLES = 22, 670a69c5ed2SRob Clark PERF_SP_WAVE_END_CYCLES = 23, 671a69c5ed2SRob Clark PERF_SP_WAVE_LONG_SYNC_CYCLES = 24, 672a69c5ed2SRob Clark PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25, 673a69c5ed2SRob Clark PERF_SP_WAVE_JOIN_CYCLES = 26, 674a69c5ed2SRob Clark PERF_SP_LM_LOAD_INSTRUCTIONS = 27, 675a69c5ed2SRob Clark PERF_SP_LM_STORE_INSTRUCTIONS = 28, 676a69c5ed2SRob Clark PERF_SP_LM_ATOMICS = 29, 677a69c5ed2SRob Clark PERF_SP_GM_LOAD_INSTRUCTIONS = 30, 678a69c5ed2SRob Clark PERF_SP_GM_STORE_INSTRUCTIONS = 31, 679a69c5ed2SRob Clark PERF_SP_GM_ATOMICS = 32, 680a69c5ed2SRob Clark PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33, 681a69c5ed2SRob Clark PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34, 682a69c5ed2SRob Clark PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35, 683a69c5ed2SRob Clark PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36, 684a69c5ed2SRob Clark PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37, 685a69c5ed2SRob Clark PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38, 686a69c5ed2SRob Clark PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39, 687a69c5ed2SRob Clark PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40, 688a69c5ed2SRob Clark PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41, 689a69c5ed2SRob Clark PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42, 690a69c5ed2SRob Clark PERF_SP_VS_INSTRUCTIONS = 43, 691a69c5ed2SRob Clark PERF_SP_FS_INSTRUCTIONS = 44, 692a69c5ed2SRob Clark PERF_SP_ADDR_LOCK_COUNT = 45, 693a69c5ed2SRob Clark PERF_SP_UCHE_READ_TRANS = 46, 694a69c5ed2SRob Clark PERF_SP_UCHE_WRITE_TRANS = 47, 695a69c5ed2SRob Clark PERF_SP_EXPORT_VPC_TRANS = 48, 696a69c5ed2SRob Clark PERF_SP_EXPORT_RB_TRANS = 49, 697a69c5ed2SRob Clark PERF_SP_PIXELS_KILLED = 50, 698a69c5ed2SRob Clark PERF_SP_ICL1_REQUESTS = 51, 699a69c5ed2SRob Clark PERF_SP_ICL1_MISSES = 52, 700a69c5ed2SRob Clark PERF_SP_HS_INSTRUCTIONS = 53, 701a69c5ed2SRob Clark PERF_SP_DS_INSTRUCTIONS = 54, 702a69c5ed2SRob Clark PERF_SP_GS_INSTRUCTIONS = 55, 703a69c5ed2SRob Clark PERF_SP_CS_INSTRUCTIONS = 56, 704a69c5ed2SRob Clark PERF_SP_GPR_READ = 57, 705a69c5ed2SRob Clark PERF_SP_GPR_WRITE = 58, 706a69c5ed2SRob Clark PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59, 707a69c5ed2SRob Clark PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60, 708a69c5ed2SRob Clark PERF_SP_LM_BANK_CONFLICTS = 61, 709a69c5ed2SRob Clark PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62, 710a69c5ed2SRob Clark PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63, 711a69c5ed2SRob Clark PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64, 712a69c5ed2SRob Clark PERF_SP_LM_WORKING_CYCLES = 65, 713a69c5ed2SRob Clark PERF_SP_DISPATCHER_WORKING_CYCLES = 66, 714a69c5ed2SRob Clark PERF_SP_SEQUENCER_WORKING_CYCLES = 67, 715a69c5ed2SRob Clark PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68, 716a69c5ed2SRob Clark PERF_SP_STARVE_CYCLES_HLSQ = 69, 717a69c5ed2SRob Clark PERF_SP_NON_EXECUTION_LS_CYCLES = 70, 718a69c5ed2SRob Clark PERF_SP_WORKING_EU = 71, 719a69c5ed2SRob Clark PERF_SP_ANY_EU_WORKING = 72, 720a69c5ed2SRob Clark PERF_SP_WORKING_EU_FS_STAGE = 73, 721a69c5ed2SRob Clark PERF_SP_ANY_EU_WORKING_FS_STAGE = 74, 722a69c5ed2SRob Clark PERF_SP_WORKING_EU_VS_STAGE = 75, 723a69c5ed2SRob Clark PERF_SP_ANY_EU_WORKING_VS_STAGE = 76, 724a69c5ed2SRob Clark PERF_SP_WORKING_EU_CS_STAGE = 77, 725a69c5ed2SRob Clark PERF_SP_ANY_EU_WORKING_CS_STAGE = 78, 726a69c5ed2SRob Clark PERF_SP_GPR_READ_PREFETCH = 79, 727a69c5ed2SRob Clark PERF_SP_GPR_READ_CONFLICT = 80, 728a69c5ed2SRob Clark PERF_SP_GPR_WRITE_CONFLICT = 81, 729a69c5ed2SRob Clark PERF_SP_GM_LOAD_LATENCY_CYCLES = 82, 730a69c5ed2SRob Clark PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83, 731a69c5ed2SRob Clark PERF_SP_EXECUTABLE_WAVES = 84, 732a69c5ed2SRob Clark }; 733a69c5ed2SRob Clark 734a69c5ed2SRob Clark enum a6xx_rb_perfcounter_select { 735a69c5ed2SRob Clark PERF_RB_BUSY_CYCLES = 0, 736a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_HLSQ = 1, 737a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_FIFO0_FULL = 2, 738a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_FIFO1_FULL = 3, 739a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_FIFO2_FULL = 4, 740a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_SP = 5, 741a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_LRZ_TILE = 6, 742a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_CCU = 7, 743a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_Z_PLANE = 8, 744a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_BARY_PLANE = 9, 745a69c5ed2SRob Clark PERF_RB_Z_WORKLOAD = 10, 746a69c5ed2SRob Clark PERF_RB_HLSQ_ACTIVE = 11, 747a69c5ed2SRob Clark PERF_RB_Z_READ = 12, 748a69c5ed2SRob Clark PERF_RB_Z_WRITE = 13, 749a69c5ed2SRob Clark PERF_RB_C_READ = 14, 750a69c5ed2SRob Clark PERF_RB_C_WRITE = 15, 751a69c5ed2SRob Clark PERF_RB_TOTAL_PASS = 16, 752a69c5ed2SRob Clark PERF_RB_Z_PASS = 17, 753a69c5ed2SRob Clark PERF_RB_Z_FAIL = 18, 754a69c5ed2SRob Clark PERF_RB_S_FAIL = 19, 755a69c5ed2SRob Clark PERF_RB_BLENDED_FXP_COMPONENTS = 20, 756a69c5ed2SRob Clark PERF_RB_BLENDED_FP16_COMPONENTS = 21, 757a69c5ed2SRob Clark PERF_RB_PS_INVOCATIONS = 22, 758a69c5ed2SRob Clark PERF_RB_2D_ALIVE_CYCLES = 23, 759a69c5ed2SRob Clark PERF_RB_2D_STALL_CYCLES_A2D = 24, 760a69c5ed2SRob Clark PERF_RB_2D_STARVE_CYCLES_SRC = 25, 761a69c5ed2SRob Clark PERF_RB_2D_STARVE_CYCLES_SP = 26, 762a69c5ed2SRob Clark PERF_RB_2D_STARVE_CYCLES_DST = 27, 763a69c5ed2SRob Clark PERF_RB_2D_VALID_PIXELS = 28, 764a69c5ed2SRob Clark PERF_RB_3D_PIXELS = 29, 765a69c5ed2SRob Clark PERF_RB_BLENDER_WORKING_CYCLES = 30, 766a69c5ed2SRob Clark PERF_RB_ZPROC_WORKING_CYCLES = 31, 767a69c5ed2SRob Clark PERF_RB_CPROC_WORKING_CYCLES = 32, 768a69c5ed2SRob Clark PERF_RB_SAMPLER_WORKING_CYCLES = 33, 769a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 34, 770a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 35, 771a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 36, 772a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 37, 773a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_VPC = 38, 774a69c5ed2SRob Clark PERF_RB_2D_INPUT_TRANS = 39, 775a69c5ed2SRob Clark PERF_RB_2D_OUTPUT_RB_DST_TRANS = 40, 776a69c5ed2SRob Clark PERF_RB_2D_OUTPUT_RB_SRC_TRANS = 41, 777a69c5ed2SRob Clark PERF_RB_BLENDED_FP32_COMPONENTS = 42, 778a69c5ed2SRob Clark PERF_RB_COLOR_PIX_TILES = 43, 779a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU = 44, 780a69c5ed2SRob Clark PERF_RB_EARLY_Z_ARB3_GRANT = 45, 781a69c5ed2SRob Clark PERF_RB_LATE_Z_ARB3_GRANT = 46, 782a69c5ed2SRob Clark PERF_RB_EARLY_Z_SKIP_GRANT = 47, 783a69c5ed2SRob Clark }; 784a69c5ed2SRob Clark 785a69c5ed2SRob Clark enum a6xx_vsc_perfcounter_select { 786a69c5ed2SRob Clark PERF_VSC_BUSY_CYCLES = 0, 787a69c5ed2SRob Clark PERF_VSC_WORKING_CYCLES = 1, 788a69c5ed2SRob Clark PERF_VSC_STALL_CYCLES_UCHE = 2, 789a69c5ed2SRob Clark PERF_VSC_EOT_NUM = 3, 790a69c5ed2SRob Clark PERF_VSC_INPUT_TILES = 4, 791a69c5ed2SRob Clark }; 792a69c5ed2SRob Clark 793a69c5ed2SRob Clark enum a6xx_ccu_perfcounter_select { 794a69c5ed2SRob Clark PERF_CCU_BUSY_CYCLES = 0, 795a69c5ed2SRob Clark PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1, 796a69c5ed2SRob Clark PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2, 797a69c5ed2SRob Clark PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3, 798a69c5ed2SRob Clark PERF_CCU_DEPTH_BLOCKS = 4, 799a69c5ed2SRob Clark PERF_CCU_COLOR_BLOCKS = 5, 800a69c5ed2SRob Clark PERF_CCU_DEPTH_BLOCK_HIT = 6, 801a69c5ed2SRob Clark PERF_CCU_COLOR_BLOCK_HIT = 7, 802a69c5ed2SRob Clark PERF_CCU_PARTIAL_BLOCK_READ = 8, 803a69c5ed2SRob Clark PERF_CCU_GMEM_READ = 9, 804a69c5ed2SRob Clark PERF_CCU_GMEM_WRITE = 10, 805a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11, 806a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12, 807a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13, 808a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14, 809a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15, 810a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG5_COUNT = 16, 811a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG6_COUNT = 17, 812a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG8_COUNT = 18, 813a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG0_COUNT = 19, 814a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG1_COUNT = 20, 815a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG2_COUNT = 21, 816a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG3_COUNT = 22, 817a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG4_COUNT = 23, 818a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG5_COUNT = 24, 819a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG6_COUNT = 25, 820a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG8_COUNT = 26, 821a69c5ed2SRob Clark PERF_CCU_2D_RD_REQ = 27, 822a69c5ed2SRob Clark PERF_CCU_2D_WR_REQ = 28, 823a69c5ed2SRob Clark }; 824a69c5ed2SRob Clark 825a69c5ed2SRob Clark enum a6xx_lrz_perfcounter_select { 826a69c5ed2SRob Clark PERF_LRZ_BUSY_CYCLES = 0, 827a69c5ed2SRob Clark PERF_LRZ_STARVE_CYCLES_RAS = 1, 828a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_RB = 2, 829a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_VSC = 3, 830a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_VPC = 4, 831a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5, 832a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_UCHE = 6, 833a69c5ed2SRob Clark PERF_LRZ_LRZ_READ = 7, 834a69c5ed2SRob Clark PERF_LRZ_LRZ_WRITE = 8, 835a69c5ed2SRob Clark PERF_LRZ_READ_LATENCY = 9, 836a69c5ed2SRob Clark PERF_LRZ_MERGE_CACHE_UPDATING = 10, 837a69c5ed2SRob Clark PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11, 838a69c5ed2SRob Clark PERF_LRZ_PRIM_KILLED_BY_LRZ = 12, 839a69c5ed2SRob Clark PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13, 840a69c5ed2SRob Clark PERF_LRZ_FULL_8X8_TILES = 14, 841a69c5ed2SRob Clark PERF_LRZ_PARTIAL_8X8_TILES = 15, 842a69c5ed2SRob Clark PERF_LRZ_TILE_KILLED = 16, 843a69c5ed2SRob Clark PERF_LRZ_TOTAL_PIXEL = 17, 844a69c5ed2SRob Clark PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18, 845a69c5ed2SRob Clark PERF_LRZ_FULLY_COVERED_TILES = 19, 846a69c5ed2SRob Clark PERF_LRZ_PARTIAL_COVERED_TILES = 20, 847a69c5ed2SRob Clark PERF_LRZ_FEEDBACK_ACCEPT = 21, 848a69c5ed2SRob Clark PERF_LRZ_FEEDBACK_DISCARD = 22, 849a69c5ed2SRob Clark PERF_LRZ_FEEDBACK_STALL = 23, 850a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 24, 851a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_RB_BPLANE = 25, 852a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_VC = 26, 853a69c5ed2SRob Clark PERF_LRZ_RAS_MASK_TRANS = 27, 854a69c5ed2SRob Clark }; 855a69c5ed2SRob Clark 856a69c5ed2SRob Clark enum a6xx_cmp_perfcounter_select { 857a69c5ed2SRob Clark PERF_CMPDECMP_STALL_CYCLES_ARB = 0, 858a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1, 859a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2, 860a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3, 861a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4, 862a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_REQUEST = 5, 863a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6, 864a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_DATA = 7, 865a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_WRITE_DATA = 8, 866a69c5ed2SRob Clark PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9, 867a69c5ed2SRob Clark PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10, 868a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11, 869a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12, 870a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13, 871a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14, 872a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 15, 873a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 16, 874a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 17, 875a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 18, 876a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 19, 877a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 20, 878a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 21, 879a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 22, 880a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 23, 881a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 24, 882a69c5ed2SRob Clark PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 25, 883a69c5ed2SRob Clark PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 26, 884a69c5ed2SRob Clark PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 27, 885a69c5ed2SRob Clark PERF_CMPDECMP_2D_RD_DATA = 28, 886a69c5ed2SRob Clark PERF_CMPDECMP_2D_WR_DATA = 29, 887a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 30, 888a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 31, 889a69c5ed2SRob Clark PERF_CMPDECMP_2D_OUTPUT_TRANS = 32, 890a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 33, 891a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 34, 892a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 35, 893a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 36, 894a69c5ed2SRob Clark PERF_CMPDECMP_2D_BUSY_CYCLES = 37, 895a69c5ed2SRob Clark PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = 38, 896a69c5ed2SRob Clark PERF_CMPDECMP_2D_PIXELS = 39, 8972d756322SRob Clark }; 8982d756322SRob Clark 899c28c82e9SRob Clark enum a6xx_2d_ifmt { 900c28c82e9SRob Clark R2D_UNORM8 = 16, 901c28c82e9SRob Clark R2D_INT32 = 7, 902c28c82e9SRob Clark R2D_INT16 = 6, 903c28c82e9SRob Clark R2D_INT8 = 5, 904c28c82e9SRob Clark R2D_FLOAT32 = 4, 905c28c82e9SRob Clark R2D_FLOAT16 = 3, 906c28c82e9SRob Clark R2D_UNORM8_SRGB = 1, 907c28c82e9SRob Clark R2D_RAW = 0, 908c28c82e9SRob Clark }; 909c28c82e9SRob Clark 910c28c82e9SRob Clark enum a6xx_ztest_mode { 911c28c82e9SRob Clark A6XX_EARLY_Z = 0, 912c28c82e9SRob Clark A6XX_LATE_Z = 1, 913c28c82e9SRob Clark A6XX_EARLY_LRZ_LATE_Z = 2, 914*f73343faSRob Clark A6XX_INVALID_ZTEST = 3, 915c28c82e9SRob Clark }; 916c28c82e9SRob Clark 91757cfe41cSRob Clark enum a6xx_sequenced_thread_dist { 91857cfe41cSRob Clark DIST_SCREEN_COORD = 0, 91957cfe41cSRob Clark DIST_ALL_TO_RB0 = 1, 92057cfe41cSRob Clark }; 92157cfe41cSRob Clark 92257cfe41cSRob Clark enum a6xx_single_prim_mode { 92357cfe41cSRob Clark NO_FLUSH = 0, 92457cfe41cSRob Clark FLUSH_PER_OVERLAP_AND_OVERWRITE = 1, 92557cfe41cSRob Clark FLUSH_PER_OVERLAP = 3, 92657cfe41cSRob Clark }; 92757cfe41cSRob Clark 92857cfe41cSRob Clark enum a6xx_raster_mode { 92957cfe41cSRob Clark TYPE_TILED = 0, 93057cfe41cSRob Clark TYPE_WRITER = 1, 93157cfe41cSRob Clark }; 93257cfe41cSRob Clark 93357cfe41cSRob Clark enum a6xx_raster_direction { 93457cfe41cSRob Clark LR_TB = 0, 93557cfe41cSRob Clark RL_TB = 1, 93657cfe41cSRob Clark LR_BT = 2, 93757cfe41cSRob Clark RB_BT = 3, 93857cfe41cSRob Clark }; 93957cfe41cSRob Clark 94057cfe41cSRob Clark enum a6xx_render_mode { 94157cfe41cSRob Clark RENDERING_PASS = 0, 94257cfe41cSRob Clark BINNING_PASS = 1, 94357cfe41cSRob Clark }; 94457cfe41cSRob Clark 94557cfe41cSRob Clark enum a6xx_buffers_location { 94657cfe41cSRob Clark BUFFERS_IN_GMEM = 0, 94757cfe41cSRob Clark BUFFERS_IN_SYSMEM = 3, 94857cfe41cSRob Clark }; 94957cfe41cSRob Clark 950*f73343faSRob Clark enum a6xx_lrz_dir_status { 951*f73343faSRob Clark LRZ_DIR_LE = 1, 952*f73343faSRob Clark LRZ_DIR_GE = 2, 953*f73343faSRob Clark LRZ_DIR_INVALID = 3, 954*f73343faSRob Clark }; 955*f73343faSRob Clark 95657cfe41cSRob Clark enum a6xx_fragcoord_sample_mode { 95757cfe41cSRob Clark FRAGCOORD_CENTER = 0, 95857cfe41cSRob Clark FRAGCOORD_SAMPLE = 3, 95957cfe41cSRob Clark }; 96057cfe41cSRob Clark 961c28c82e9SRob Clark enum a6xx_rotation { 962c28c82e9SRob Clark ROTATE_0 = 0, 963c28c82e9SRob Clark ROTATE_90 = 1, 964c28c82e9SRob Clark ROTATE_180 = 2, 965c28c82e9SRob Clark ROTATE_270 = 3, 966c28c82e9SRob Clark ROTATE_HFLIP = 4, 967c28c82e9SRob Clark ROTATE_VFLIP = 5, 968c28c82e9SRob Clark }; 969c28c82e9SRob Clark 970c28c82e9SRob Clark enum a6xx_tess_spacing { 971c28c82e9SRob Clark TESS_EQUAL = 0, 972c28c82e9SRob Clark TESS_FRACTIONAL_ODD = 2, 973c28c82e9SRob Clark TESS_FRACTIONAL_EVEN = 3, 974c28c82e9SRob Clark }; 975c28c82e9SRob Clark 976c28c82e9SRob Clark enum a6xx_tess_output { 977c28c82e9SRob Clark TESS_POINTS = 0, 978c28c82e9SRob Clark TESS_LINES = 1, 979c28c82e9SRob Clark TESS_CW_TRIS = 2, 980c28c82e9SRob Clark TESS_CCW_TRIS = 3, 981c28c82e9SRob Clark }; 982c28c82e9SRob Clark 983cc4c26d4SRob Clark enum a6xx_threadsize { 984cc4c26d4SRob Clark THREAD64 = 0, 985cc4c26d4SRob Clark THREAD128 = 1, 986cc4c26d4SRob Clark }; 987cc4c26d4SRob Clark 988*f73343faSRob Clark enum a6xx_bindless_descriptor_size { 989*f73343faSRob Clark BINDLESS_DESCRIPTOR_16B = 1, 990*f73343faSRob Clark BINDLESS_DESCRIPTOR_64B = 3, 991*f73343faSRob Clark }; 992*f73343faSRob Clark 99357cfe41cSRob Clark enum a6xx_isam_mode { 99457cfe41cSRob Clark ISAMMODE_GL = 2, 99557cfe41cSRob Clark }; 99657cfe41cSRob Clark 9972d756322SRob Clark enum a6xx_tex_filter { 9982d756322SRob Clark A6XX_TEX_NEAREST = 0, 9992d756322SRob Clark A6XX_TEX_LINEAR = 1, 10002d756322SRob Clark A6XX_TEX_ANISO = 2, 1001c28c82e9SRob Clark A6XX_TEX_CUBIC = 3, 10022d756322SRob Clark }; 10032d756322SRob Clark 10042d756322SRob Clark enum a6xx_tex_clamp { 10052d756322SRob Clark A6XX_TEX_REPEAT = 0, 10062d756322SRob Clark A6XX_TEX_CLAMP_TO_EDGE = 1, 10072d756322SRob Clark A6XX_TEX_MIRROR_REPEAT = 2, 10082d756322SRob Clark A6XX_TEX_CLAMP_TO_BORDER = 3, 10092d756322SRob Clark A6XX_TEX_MIRROR_CLAMP = 4, 10102d756322SRob Clark }; 10112d756322SRob Clark 10122d756322SRob Clark enum a6xx_tex_aniso { 10132d756322SRob Clark A6XX_TEX_ANISO_1 = 0, 10142d756322SRob Clark A6XX_TEX_ANISO_2 = 1, 10152d756322SRob Clark A6XX_TEX_ANISO_4 = 2, 10162d756322SRob Clark A6XX_TEX_ANISO_8 = 3, 10172d756322SRob Clark A6XX_TEX_ANISO_16 = 4, 10182d756322SRob Clark }; 10192d756322SRob Clark 1020c28c82e9SRob Clark enum a6xx_reduction_mode { 1021c28c82e9SRob Clark A6XX_REDUCTION_MODE_AVERAGE = 0, 1022c28c82e9SRob Clark A6XX_REDUCTION_MODE_MIN = 1, 1023c28c82e9SRob Clark A6XX_REDUCTION_MODE_MAX = 2, 1024c28c82e9SRob Clark }; 1025c28c82e9SRob Clark 10262d756322SRob Clark enum a6xx_tex_swiz { 10272d756322SRob Clark A6XX_TEX_X = 0, 10282d756322SRob Clark A6XX_TEX_Y = 1, 10292d756322SRob Clark A6XX_TEX_Z = 2, 10302d756322SRob Clark A6XX_TEX_W = 3, 10312d756322SRob Clark A6XX_TEX_ZERO = 4, 10322d756322SRob Clark A6XX_TEX_ONE = 5, 10332d756322SRob Clark }; 10342d756322SRob Clark 10352d756322SRob Clark enum a6xx_tex_type { 10362d756322SRob Clark A6XX_TEX_1D = 0, 10372d756322SRob Clark A6XX_TEX_2D = 1, 10382d756322SRob Clark A6XX_TEX_CUBE = 2, 10392d756322SRob Clark A6XX_TEX_3D = 3, 104057cfe41cSRob Clark A6XX_TEX_BUFFER = 4, 10412d756322SRob Clark }; 10422d756322SRob Clark 10432d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001 10442d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR 0x00000002 1045*f73343faSRob Clark #define A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_0 0x00000010 1046*f73343faSRob Clark #define A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_1 0x00000020 10472d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW 0x00000040 10482d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080 10492d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_SW 0x00000100 10502d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200 10512d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400 10522d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800 10532d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000 10542d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_IB2 0x00002000 10552d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_IB1 0x00004000 10562d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_RB 0x00008000 1057*f73343faSRob Clark #define A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPT 0x00008000 1058*f73343faSRob Clark #define A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPTLPAC 0x00010000 10592d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000 10602d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000 10612d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000 1062*f73343faSRob Clark #define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS_LPAC 0x00200000 10632d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000 10642d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT 0x00800000 10652d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000 10662d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000 10672d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000 10682d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000 1069*f73343faSRob Clark #define A6XX_RBBM_INT_0_MASK_TSBWRITEERROR 0x10000000 10702d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000 10712d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000 10722d756322SRob Clark #define A6XX_CP_INT_CP_OPCODE_ERROR 0x00000001 10732d756322SRob Clark #define A6XX_CP_INT_CP_UCODE_ERROR 0x00000002 10742d756322SRob Clark #define A6XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004 10752d756322SRob Clark #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010 10762d756322SRob Clark #define A6XX_CP_INT_CP_AHB_ERROR 0x00000020 10772d756322SRob Clark #define A6XX_CP_INT_CP_VSD_PARITY_ERROR 0x00000040 10782d756322SRob Clark #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR 0x00000080 1079*f73343faSRob Clark #define A6XX_CP_INT_CP_OPCODE_ERROR_LPAC 0x00000100 1080*f73343faSRob Clark #define A6XX_CP_INT_CP_UCODE_ERROR_LPAC 0x00000200 1081*f73343faSRob Clark #define A6XX_CP_INT_CP_HW_FAULT_ERROR_LPAC 0x00000400 1082*f73343faSRob Clark #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_LPAC 0x00000800 1083*f73343faSRob Clark #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_LPAC 0x00001000 1084*f73343faSRob Clark #define A6XX_CP_INT_CP_OPCODE_ERROR_BV 0x00002000 1085*f73343faSRob Clark #define A6XX_CP_INT_CP_UCODE_ERROR_BV 0x00004000 1086*f73343faSRob Clark #define A6XX_CP_INT_CP_HW_FAULT_ERROR_BV 0x00008000 1087*f73343faSRob Clark #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_BV 0x00010000 1088*f73343faSRob Clark #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_BV 0x00020000 10892d756322SRob Clark #define REG_A6XX_CP_RB_BASE 0x00000800 10902d756322SRob Clark 10912d756322SRob Clark #define REG_A6XX_CP_RB_CNTL 0x00000802 10922d756322SRob Clark 1093*f73343faSRob Clark #define REG_A6XX_CP_RB_RPTR_ADDR 0x00000804 10942d756322SRob Clark 10952d756322SRob Clark #define REG_A6XX_CP_RB_RPTR 0x00000806 10962d756322SRob Clark 10972d756322SRob Clark #define REG_A6XX_CP_RB_WPTR 0x00000807 10982d756322SRob Clark 10992d756322SRob Clark #define REG_A6XX_CP_SQE_CNTL 0x00000808 11002d756322SRob Clark 1101c28c82e9SRob Clark #define REG_A6XX_CP_CP2GMU_STATUS 0x00000812 1102c28c82e9SRob Clark #define A6XX_CP_CP2GMU_STATUS_IFPC 0x00000001 1103c28c82e9SRob Clark 11042d756322SRob Clark #define REG_A6XX_CP_HW_FAULT 0x00000821 11052d756322SRob Clark 11062d756322SRob Clark #define REG_A6XX_CP_INTERRUPT_STATUS 0x00000823 11072d756322SRob Clark 11082d756322SRob Clark #define REG_A6XX_CP_PROTECT_STATUS 0x00000824 11092d756322SRob Clark 1110*f73343faSRob Clark #define REG_A6XX_CP_STATUS_1 0x00000825 1111*f73343faSRob Clark 1112cc4c26d4SRob Clark #define REG_A6XX_CP_SQE_INSTR_BASE 0x00000830 11132d756322SRob Clark 11142d756322SRob Clark #define REG_A6XX_CP_MISC_CNTL 0x00000840 11152d756322SRob Clark 111624e6938eSJonathan Marek #define REG_A6XX_CP_APRIV_CNTL 0x00000844 111724e6938eSJonathan Marek 1118*f73343faSRob Clark #define REG_A6XX_CP_PREEMPT_THRESHOLD 0x000008c0 1119*f73343faSRob Clark 11202d756322SRob Clark #define REG_A6XX_CP_ROQ_THRESHOLDS_1 0x000008c1 1121*f73343faSRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK 0x000000ff 1122*f73343faSRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT 0 1123*f73343faSRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_MRB_START(uint32_t val) 1124c28c82e9SRob Clark { 1125*f73343faSRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK; 1126c28c82e9SRob Clark } 1127*f73343faSRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK 0x0000ff00 1128*f73343faSRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT 8 1129*f73343faSRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_VSD_START(uint32_t val) 1130c28c82e9SRob Clark { 1131*f73343faSRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK; 1132c28c82e9SRob Clark } 1133c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK 0x00ff0000 1134c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT 16 1135c28c82e9SRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val) 1136c28c82e9SRob Clark { 1137c28c82e9SRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK; 1138c28c82e9SRob Clark } 1139c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK 0xff000000 1140c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT 24 1141c28c82e9SRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val) 1142c28c82e9SRob Clark { 1143c28c82e9SRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK; 1144c28c82e9SRob Clark } 11452d756322SRob Clark 11462d756322SRob Clark #define REG_A6XX_CP_ROQ_THRESHOLDS_2 0x000008c2 1147c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK 0x000001ff 1148c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT 0 1149c28c82e9SRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val) 1150c28c82e9SRob Clark { 1151c28c82e9SRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK; 1152c28c82e9SRob Clark } 1153c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK 0xffff0000 1154c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT 16 1155c28c82e9SRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val) 1156c28c82e9SRob Clark { 1157c28c82e9SRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK; 1158c28c82e9SRob Clark } 11592d756322SRob Clark 11602d756322SRob Clark #define REG_A6XX_CP_MEM_POOL_SIZE 0x000008c3 11612d756322SRob Clark 11622d756322SRob Clark #define REG_A6XX_CP_CHICKEN_DBG 0x00000841 11632d756322SRob Clark 11642d756322SRob Clark #define REG_A6XX_CP_ADDR_MODE_CNTL 0x00000842 11652d756322SRob Clark 11662d756322SRob Clark #define REG_A6XX_CP_DBG_ECO_CNTL 0x00000843 11672d756322SRob Clark 11682d756322SRob Clark #define REG_A6XX_CP_PROTECT_CNTL 0x0000084f 11692d756322SRob Clark 11702d756322SRob Clark static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; } 11712d756322SRob Clark 11722d756322SRob Clark static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; } 11732d756322SRob Clark 11742d756322SRob Clark static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; } 11752d756322SRob Clark 11762d756322SRob Clark static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; } 11772d756322SRob Clark #define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0003ffff 11782d756322SRob Clark #define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0 11792d756322SRob Clark static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) 11802d756322SRob Clark { 11812d756322SRob Clark return ((val) << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK; 11822d756322SRob Clark } 11832d756322SRob Clark #define A6XX_CP_PROTECT_REG_MASK_LEN__MASK 0x7ffc0000 11842d756322SRob Clark #define A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT 18 11852d756322SRob Clark static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) 11862d756322SRob Clark { 11872d756322SRob Clark return ((val) << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK; 11882d756322SRob Clark } 11892d756322SRob Clark #define A6XX_CP_PROTECT_REG_READ 0x80000000 11902d756322SRob Clark 11912d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_CNTL 0x000008a0 11922d756322SRob Clark 1193*f73343faSRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO 0x000008a1 11942d756322SRob Clark 1195*f73343faSRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR 0x000008a3 11962d756322SRob Clark 1197*f73343faSRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR 0x000008a5 11982d756322SRob Clark 1199*f73343faSRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR 0x000008a7 12002d756322SRob Clark 1201*f73343faSRob Clark #define REG_A7XX_CP_CONTEXT_SWITCH_LEVEL_STATUS 0x000008ab 12022d756322SRob Clark 1203cc4c26d4SRob Clark static inline uint32_t REG_A6XX_CP_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008d0 + 0x1*i0; } 12042d756322SRob Clark 1205*f73343faSRob Clark static inline uint32_t REG_A7XX_CP_BV_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008e0 + 0x1*i0; } 12062d756322SRob Clark 1207*f73343faSRob Clark #define REG_A6XX_CP_CRASH_SCRIPT_BASE 0x00000900 12082d756322SRob Clark 12092d756322SRob Clark #define REG_A6XX_CP_CRASH_DUMP_CNTL 0x00000902 12102d756322SRob Clark 12112d756322SRob Clark #define REG_A6XX_CP_CRASH_DUMP_STATUS 0x00000903 12122d756322SRob Clark 12132d756322SRob Clark #define REG_A6XX_CP_SQE_STAT_ADDR 0x00000908 12142d756322SRob Clark 12152d756322SRob Clark #define REG_A6XX_CP_SQE_STAT_DATA 0x00000909 12162d756322SRob Clark 12172d756322SRob Clark #define REG_A6XX_CP_DRAW_STATE_ADDR 0x0000090a 12182d756322SRob Clark 12192d756322SRob Clark #define REG_A6XX_CP_DRAW_STATE_DATA 0x0000090b 12202d756322SRob Clark 12212d756322SRob Clark #define REG_A6XX_CP_ROQ_DBG_ADDR 0x0000090c 12222d756322SRob Clark 12232d756322SRob Clark #define REG_A6XX_CP_ROQ_DBG_DATA 0x0000090d 12242d756322SRob Clark 12252d756322SRob Clark #define REG_A6XX_CP_MEM_POOL_DBG_ADDR 0x0000090e 12262d756322SRob Clark 12272d756322SRob Clark #define REG_A6XX_CP_MEM_POOL_DBG_DATA 0x0000090f 12282d756322SRob Clark 12292d756322SRob Clark #define REG_A6XX_CP_SQE_UCODE_DBG_ADDR 0x00000910 12302d756322SRob Clark 12312d756322SRob Clark #define REG_A6XX_CP_SQE_UCODE_DBG_DATA 0x00000911 12322d756322SRob Clark 12332d756322SRob Clark #define REG_A6XX_CP_IB1_BASE 0x00000928 12342d756322SRob Clark 12352d756322SRob Clark #define REG_A6XX_CP_IB1_REM_SIZE 0x0000092a 12362d756322SRob Clark 12372d756322SRob Clark #define REG_A6XX_CP_IB2_BASE 0x0000092b 12382d756322SRob Clark 12392d756322SRob Clark #define REG_A6XX_CP_IB2_REM_SIZE 0x0000092d 12402d756322SRob Clark 1241c28c82e9SRob Clark #define REG_A6XX_CP_SDS_BASE 0x0000092e 1242c28c82e9SRob Clark 1243cc4c26d4SRob Clark #define REG_A6XX_CP_SDS_REM_SIZE 0x00000930 1244c28c82e9SRob Clark 1245cc4c26d4SRob Clark #define REG_A6XX_CP_MRB_BASE 0x00000931 1246c28c82e9SRob Clark 1247cc4c26d4SRob Clark #define REG_A6XX_CP_MRB_REM_SIZE 0x00000933 1248c28c82e9SRob Clark 1249cc4c26d4SRob Clark #define REG_A6XX_CP_VSD_BASE 0x00000934 1250cc4c26d4SRob Clark 1251*f73343faSRob Clark #define REG_A6XX_CP_ROQ_RB_STAT 0x00000939 1252*f73343faSRob Clark #define A6XX_CP_ROQ_RB_STAT_RPTR__MASK 0x000003ff 1253*f73343faSRob Clark #define A6XX_CP_ROQ_RB_STAT_RPTR__SHIFT 0 1254*f73343faSRob Clark static inline uint32_t A6XX_CP_ROQ_RB_STAT_RPTR(uint32_t val) 1255*f73343faSRob Clark { 1256*f73343faSRob Clark return ((val) << A6XX_CP_ROQ_RB_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_RB_STAT_RPTR__MASK; 1257*f73343faSRob Clark } 1258*f73343faSRob Clark #define A6XX_CP_ROQ_RB_STAT_WPTR__MASK 0x03ff0000 1259*f73343faSRob Clark #define A6XX_CP_ROQ_RB_STAT_WPTR__SHIFT 16 1260*f73343faSRob Clark static inline uint32_t A6XX_CP_ROQ_RB_STAT_WPTR(uint32_t val) 1261*f73343faSRob Clark { 1262*f73343faSRob Clark return ((val) << A6XX_CP_ROQ_RB_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_RB_STAT_WPTR__MASK; 1263*f73343faSRob Clark } 1264*f73343faSRob Clark 1265*f73343faSRob Clark #define REG_A6XX_CP_ROQ_IB1_STAT 0x0000093a 1266*f73343faSRob Clark #define A6XX_CP_ROQ_IB1_STAT_RPTR__MASK 0x000003ff 1267*f73343faSRob Clark #define A6XX_CP_ROQ_IB1_STAT_RPTR__SHIFT 0 1268*f73343faSRob Clark static inline uint32_t A6XX_CP_ROQ_IB1_STAT_RPTR(uint32_t val) 1269*f73343faSRob Clark { 1270*f73343faSRob Clark return ((val) << A6XX_CP_ROQ_IB1_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_IB1_STAT_RPTR__MASK; 1271*f73343faSRob Clark } 1272*f73343faSRob Clark #define A6XX_CP_ROQ_IB1_STAT_WPTR__MASK 0x03ff0000 1273*f73343faSRob Clark #define A6XX_CP_ROQ_IB1_STAT_WPTR__SHIFT 16 1274*f73343faSRob Clark static inline uint32_t A6XX_CP_ROQ_IB1_STAT_WPTR(uint32_t val) 1275*f73343faSRob Clark { 1276*f73343faSRob Clark return ((val) << A6XX_CP_ROQ_IB1_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_IB1_STAT_WPTR__MASK; 1277*f73343faSRob Clark } 1278*f73343faSRob Clark 1279*f73343faSRob Clark #define REG_A6XX_CP_ROQ_IB2_STAT 0x0000093b 1280*f73343faSRob Clark #define A6XX_CP_ROQ_IB2_STAT_RPTR__MASK 0x000003ff 1281*f73343faSRob Clark #define A6XX_CP_ROQ_IB2_STAT_RPTR__SHIFT 0 1282*f73343faSRob Clark static inline uint32_t A6XX_CP_ROQ_IB2_STAT_RPTR(uint32_t val) 1283*f73343faSRob Clark { 1284*f73343faSRob Clark return ((val) << A6XX_CP_ROQ_IB2_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_IB2_STAT_RPTR__MASK; 1285*f73343faSRob Clark } 1286*f73343faSRob Clark #define A6XX_CP_ROQ_IB2_STAT_WPTR__MASK 0x03ff0000 1287*f73343faSRob Clark #define A6XX_CP_ROQ_IB2_STAT_WPTR__SHIFT 16 1288*f73343faSRob Clark static inline uint32_t A6XX_CP_ROQ_IB2_STAT_WPTR(uint32_t val) 1289*f73343faSRob Clark { 1290*f73343faSRob Clark return ((val) << A6XX_CP_ROQ_IB2_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_IB2_STAT_WPTR__MASK; 1291*f73343faSRob Clark } 1292*f73343faSRob Clark 1293*f73343faSRob Clark #define REG_A6XX_CP_ROQ_SDS_STAT 0x0000093c 1294*f73343faSRob Clark #define A6XX_CP_ROQ_SDS_STAT_RPTR__MASK 0x000003ff 1295*f73343faSRob Clark #define A6XX_CP_ROQ_SDS_STAT_RPTR__SHIFT 0 1296*f73343faSRob Clark static inline uint32_t A6XX_CP_ROQ_SDS_STAT_RPTR(uint32_t val) 1297*f73343faSRob Clark { 1298*f73343faSRob Clark return ((val) << A6XX_CP_ROQ_SDS_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_SDS_STAT_RPTR__MASK; 1299*f73343faSRob Clark } 1300*f73343faSRob Clark #define A6XX_CP_ROQ_SDS_STAT_WPTR__MASK 0x03ff0000 1301*f73343faSRob Clark #define A6XX_CP_ROQ_SDS_STAT_WPTR__SHIFT 16 1302*f73343faSRob Clark static inline uint32_t A6XX_CP_ROQ_SDS_STAT_WPTR(uint32_t val) 1303*f73343faSRob Clark { 1304*f73343faSRob Clark return ((val) << A6XX_CP_ROQ_SDS_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_SDS_STAT_WPTR__MASK; 1305*f73343faSRob Clark } 1306*f73343faSRob Clark 1307*f73343faSRob Clark #define REG_A6XX_CP_ROQ_MRB_STAT 0x0000093d 1308*f73343faSRob Clark #define A6XX_CP_ROQ_MRB_STAT_RPTR__MASK 0x000003ff 1309*f73343faSRob Clark #define A6XX_CP_ROQ_MRB_STAT_RPTR__SHIFT 0 1310*f73343faSRob Clark static inline uint32_t A6XX_CP_ROQ_MRB_STAT_RPTR(uint32_t val) 1311*f73343faSRob Clark { 1312*f73343faSRob Clark return ((val) << A6XX_CP_ROQ_MRB_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_MRB_STAT_RPTR__MASK; 1313*f73343faSRob Clark } 1314*f73343faSRob Clark #define A6XX_CP_ROQ_MRB_STAT_WPTR__MASK 0x03ff0000 1315*f73343faSRob Clark #define A6XX_CP_ROQ_MRB_STAT_WPTR__SHIFT 16 1316*f73343faSRob Clark static inline uint32_t A6XX_CP_ROQ_MRB_STAT_WPTR(uint32_t val) 1317*f73343faSRob Clark { 1318*f73343faSRob Clark return ((val) << A6XX_CP_ROQ_MRB_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_MRB_STAT_WPTR__MASK; 1319*f73343faSRob Clark } 1320*f73343faSRob Clark 1321*f73343faSRob Clark #define REG_A6XX_CP_ROQ_VSD_STAT 0x0000093e 1322*f73343faSRob Clark #define A6XX_CP_ROQ_VSD_STAT_RPTR__MASK 0x000003ff 1323*f73343faSRob Clark #define A6XX_CP_ROQ_VSD_STAT_RPTR__SHIFT 0 1324*f73343faSRob Clark static inline uint32_t A6XX_CP_ROQ_VSD_STAT_RPTR(uint32_t val) 1325*f73343faSRob Clark { 1326*f73343faSRob Clark return ((val) << A6XX_CP_ROQ_VSD_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_VSD_STAT_RPTR__MASK; 1327*f73343faSRob Clark } 1328*f73343faSRob Clark #define A6XX_CP_ROQ_VSD_STAT_WPTR__MASK 0x03ff0000 1329*f73343faSRob Clark #define A6XX_CP_ROQ_VSD_STAT_WPTR__SHIFT 16 1330*f73343faSRob Clark static inline uint32_t A6XX_CP_ROQ_VSD_STAT_WPTR(uint32_t val) 1331*f73343faSRob Clark { 1332*f73343faSRob Clark return ((val) << A6XX_CP_ROQ_VSD_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_VSD_STAT_WPTR__MASK; 1333*f73343faSRob Clark } 1334*f73343faSRob Clark 1335*f73343faSRob Clark #define REG_A6XX_CP_IB1_DWORDS 0x00000943 1336*f73343faSRob Clark 1337*f73343faSRob Clark #define REG_A6XX_CP_IB2_DWORDS 0x00000944 1338*f73343faSRob Clark 1339*f73343faSRob Clark #define REG_A6XX_CP_SDS_DWORDS 0x00000945 1340cc4c26d4SRob Clark 1341cc4c26d4SRob Clark #define REG_A6XX_CP_MRB_DWORDS 0x00000946 1342cc4c26d4SRob Clark 1343cc4c26d4SRob Clark #define REG_A6XX_CP_VSD_DWORDS 0x00000947 1344c28c82e9SRob Clark 1345*f73343faSRob Clark #define REG_A6XX_CP_ROQ_AVAIL_RB 0x00000948 1346*f73343faSRob Clark #define A6XX_CP_ROQ_AVAIL_RB_REM__MASK 0xffff0000 1347*f73343faSRob Clark #define A6XX_CP_ROQ_AVAIL_RB_REM__SHIFT 16 1348*f73343faSRob Clark static inline uint32_t A6XX_CP_ROQ_AVAIL_RB_REM(uint32_t val) 1349c28c82e9SRob Clark { 1350*f73343faSRob Clark return ((val) << A6XX_CP_ROQ_AVAIL_RB_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_RB_REM__MASK; 1351c28c82e9SRob Clark } 1352c28c82e9SRob Clark 1353*f73343faSRob Clark #define REG_A6XX_CP_ROQ_AVAIL_IB1 0x00000949 1354*f73343faSRob Clark #define A6XX_CP_ROQ_AVAIL_IB1_REM__MASK 0xffff0000 1355*f73343faSRob Clark #define A6XX_CP_ROQ_AVAIL_IB1_REM__SHIFT 16 1356*f73343faSRob Clark static inline uint32_t A6XX_CP_ROQ_AVAIL_IB1_REM(uint32_t val) 1357c28c82e9SRob Clark { 1358*f73343faSRob Clark return ((val) << A6XX_CP_ROQ_AVAIL_IB1_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_IB1_REM__MASK; 1359c28c82e9SRob Clark } 1360c28c82e9SRob Clark 1361*f73343faSRob Clark #define REG_A6XX_CP_ROQ_AVAIL_IB2 0x0000094a 1362*f73343faSRob Clark #define A6XX_CP_ROQ_AVAIL_IB2_REM__MASK 0xffff0000 1363*f73343faSRob Clark #define A6XX_CP_ROQ_AVAIL_IB2_REM__SHIFT 16 1364*f73343faSRob Clark static inline uint32_t A6XX_CP_ROQ_AVAIL_IB2_REM(uint32_t val) 1365cc4c26d4SRob Clark { 1366*f73343faSRob Clark return ((val) << A6XX_CP_ROQ_AVAIL_IB2_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_IB2_REM__MASK; 1367cc4c26d4SRob Clark } 1368cc4c26d4SRob Clark 1369*f73343faSRob Clark #define REG_A6XX_CP_ROQ_AVAIL_SDS 0x0000094b 1370*f73343faSRob Clark #define A6XX_CP_ROQ_AVAIL_SDS_REM__MASK 0xffff0000 1371*f73343faSRob Clark #define A6XX_CP_ROQ_AVAIL_SDS_REM__SHIFT 16 1372*f73343faSRob Clark static inline uint32_t A6XX_CP_ROQ_AVAIL_SDS_REM(uint32_t val) 1373*f73343faSRob Clark { 1374*f73343faSRob Clark return ((val) << A6XX_CP_ROQ_AVAIL_SDS_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_SDS_REM__MASK; 1375*f73343faSRob Clark } 13762d756322SRob Clark 1377*f73343faSRob Clark #define REG_A6XX_CP_ROQ_AVAIL_MRB 0x0000094c 1378*f73343faSRob Clark #define A6XX_CP_ROQ_AVAIL_MRB_REM__MASK 0xffff0000 1379*f73343faSRob Clark #define A6XX_CP_ROQ_AVAIL_MRB_REM__SHIFT 16 1380*f73343faSRob Clark static inline uint32_t A6XX_CP_ROQ_AVAIL_MRB_REM(uint32_t val) 1381*f73343faSRob Clark { 1382*f73343faSRob Clark return ((val) << A6XX_CP_ROQ_AVAIL_MRB_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_MRB_REM__MASK; 1383*f73343faSRob Clark } 1384*f73343faSRob Clark 1385*f73343faSRob Clark #define REG_A6XX_CP_ROQ_AVAIL_VSD 0x0000094d 1386*f73343faSRob Clark #define A6XX_CP_ROQ_AVAIL_VSD_REM__MASK 0xffff0000 1387*f73343faSRob Clark #define A6XX_CP_ROQ_AVAIL_VSD_REM__SHIFT 16 1388*f73343faSRob Clark static inline uint32_t A6XX_CP_ROQ_AVAIL_VSD_REM(uint32_t val) 1389*f73343faSRob Clark { 1390*f73343faSRob Clark return ((val) << A6XX_CP_ROQ_AVAIL_VSD_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_VSD_REM__MASK; 1391*f73343faSRob Clark } 1392*f73343faSRob Clark 1393*f73343faSRob Clark #define REG_A6XX_CP_ALWAYS_ON_COUNTER 0x00000980 13942d756322SRob Clark 13952d756322SRob Clark #define REG_A6XX_CP_AHB_CNTL 0x0000098d 13962d756322SRob Clark 13972d756322SRob Clark #define REG_A6XX_CP_APERTURE_CNTL_HOST 0x00000a00 13982d756322SRob Clark 13992d756322SRob Clark #define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03 14002d756322SRob Clark 1401*f73343faSRob Clark #define REG_A7XX_CP_BV_PROTECT_STATUS 0x00000a61 1402*f73343faSRob Clark 1403*f73343faSRob Clark #define REG_A7XX_CP_BV_HW_FAULT 0x00000a64 1404*f73343faSRob Clark 1405*f73343faSRob Clark #define REG_A7XX_CP_BV_DRAW_STATE_ADDR 0x00000a81 1406*f73343faSRob Clark 1407*f73343faSRob Clark #define REG_A7XX_CP_BV_DRAW_STATE_DATA 0x00000a82 1408*f73343faSRob Clark 1409*f73343faSRob Clark #define REG_A7XX_CP_BV_ROQ_DBG_ADDR 0x00000a83 1410*f73343faSRob Clark 1411*f73343faSRob Clark #define REG_A7XX_CP_BV_ROQ_DBG_DATA 0x00000a84 1412*f73343faSRob Clark 1413*f73343faSRob Clark #define REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR 0x00000a85 1414*f73343faSRob Clark 1415*f73343faSRob Clark #define REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA 0x00000a86 1416*f73343faSRob Clark 1417*f73343faSRob Clark #define REG_A7XX_CP_BV_SQE_STAT_ADDR 0x00000a87 1418*f73343faSRob Clark 1419*f73343faSRob Clark #define REG_A7XX_CP_BV_SQE_STAT_DATA 0x00000a88 1420*f73343faSRob Clark 1421*f73343faSRob Clark #define REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR 0x00000a96 1422*f73343faSRob Clark 1423*f73343faSRob Clark #define REG_A7XX_CP_BV_MEM_POOL_DBG_DATA 0x00000a97 1424*f73343faSRob Clark 1425*f73343faSRob Clark #define REG_A7XX_CP_BV_RB_RPTR_ADDR 0x00000a98 1426*f73343faSRob Clark 1427*f73343faSRob Clark #define REG_A7XX_CP_RESOURCE_TBL_DBG_ADDR 0x00000a9a 1428*f73343faSRob Clark 1429*f73343faSRob Clark #define REG_A7XX_CP_RESOURCE_TBL_DBG_DATA 0x00000a9b 1430*f73343faSRob Clark 1431*f73343faSRob Clark #define REG_A7XX_CP_BV_APRIV_CNTL 0x00000ad0 1432*f73343faSRob Clark 1433*f73343faSRob Clark #define REG_A7XX_CP_BV_CHICKEN_DBG 0x00000ada 1434*f73343faSRob Clark 1435*f73343faSRob Clark #define REG_A7XX_CP_LPAC_DRAW_STATE_ADDR 0x00000b0a 1436*f73343faSRob Clark 1437*f73343faSRob Clark #define REG_A7XX_CP_LPAC_DRAW_STATE_DATA 0x00000b0b 1438*f73343faSRob Clark 1439*f73343faSRob Clark #define REG_A7XX_CP_LPAC_ROQ_DBG_ADDR 0x00000b0c 1440*f73343faSRob Clark 1441*f73343faSRob Clark #define REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR 0x00000b27 1442*f73343faSRob Clark 1443*f73343faSRob Clark #define REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA 0x00000b28 1444*f73343faSRob Clark 1445*f73343faSRob Clark #define REG_A7XX_CP_SQE_AC_STAT_ADDR 0x00000b29 1446*f73343faSRob Clark 1447*f73343faSRob Clark #define REG_A7XX_CP_SQE_AC_STAT_DATA 0x00000b2a 1448*f73343faSRob Clark 1449*f73343faSRob Clark #define REG_A7XX_CP_LPAC_APRIV_CNTL 0x00000b31 1450*f73343faSRob Clark 1451cc4c26d4SRob Clark #define REG_A6XX_CP_LPAC_PROG_FIFO_SIZE 0x00000b34 1452cc4c26d4SRob Clark 1453*f73343faSRob Clark #define REG_A7XX_CP_LPAC_ROQ_DBG_DATA 0x00000b35 1454*f73343faSRob Clark 1455*f73343faSRob Clark #define REG_A7XX_CP_LPAC_FIFO_DBG_DATA 0x00000b36 1456*f73343faSRob Clark 1457*f73343faSRob Clark #define REG_A7XX_CP_LPAC_FIFO_DBG_ADDR 0x00000b40 1458*f73343faSRob Clark 1459cc4c26d4SRob Clark #define REG_A6XX_CP_LPAC_SQE_INSTR_BASE 0x00000b82 1460cc4c26d4SRob Clark 14612d756322SRob Clark #define REG_A6XX_VSC_ADDR_MODE_CNTL 0x00000c01 14622d756322SRob Clark 1463*f73343faSRob Clark #define REG_A6XX_RBBM_GPR0_CNTL 0x00000018 1464*f73343faSRob Clark 14652d756322SRob Clark #define REG_A6XX_RBBM_INT_0_STATUS 0x00000201 14662d756322SRob Clark 14672d756322SRob Clark #define REG_A6XX_RBBM_STATUS 0x00000210 14682d756322SRob Clark #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x00800000 14692d756322SRob Clark #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x00400000 14702d756322SRob Clark #define A6XX_RBBM_STATUS_HLSQ_BUSY 0x00200000 14712d756322SRob Clark #define A6XX_RBBM_STATUS_VSC_BUSY 0x00100000 14722d756322SRob Clark #define A6XX_RBBM_STATUS_TPL1_BUSY 0x00080000 14732d756322SRob Clark #define A6XX_RBBM_STATUS_SP_BUSY 0x00040000 14742d756322SRob Clark #define A6XX_RBBM_STATUS_UCHE_BUSY 0x00020000 14752d756322SRob Clark #define A6XX_RBBM_STATUS_VPC_BUSY 0x00010000 14762d756322SRob Clark #define A6XX_RBBM_STATUS_VFD_BUSY 0x00008000 14772d756322SRob Clark #define A6XX_RBBM_STATUS_TESS_BUSY 0x00004000 14782d756322SRob Clark #define A6XX_RBBM_STATUS_PC_VSD_BUSY 0x00002000 14792d756322SRob Clark #define A6XX_RBBM_STATUS_PC_DCALL_BUSY 0x00001000 14802d756322SRob Clark #define A6XX_RBBM_STATUS_COM_DCOM_BUSY 0x00000800 14812d756322SRob Clark #define A6XX_RBBM_STATUS_LRZ_BUSY 0x00000400 14822d756322SRob Clark #define A6XX_RBBM_STATUS_A2D_BUSY 0x00000200 14832d756322SRob Clark #define A6XX_RBBM_STATUS_CCU_BUSY 0x00000100 14842d756322SRob Clark #define A6XX_RBBM_STATUS_RB_BUSY 0x00000080 14852d756322SRob Clark #define A6XX_RBBM_STATUS_RAS_BUSY 0x00000040 14862d756322SRob Clark #define A6XX_RBBM_STATUS_TSE_BUSY 0x00000020 14872d756322SRob Clark #define A6XX_RBBM_STATUS_VBIF_BUSY 0x00000010 14882d756322SRob Clark #define A6XX_RBBM_STATUS_GFX_DBGC_BUSY 0x00000008 14892d756322SRob Clark #define A6XX_RBBM_STATUS_CP_BUSY 0x00000004 14902d756322SRob Clark #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER 0x00000002 14912d756322SRob Clark #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER 0x00000001 14922d756322SRob Clark 1493*f73343faSRob Clark #define REG_A6XX_RBBM_STATUS1 0x00000211 1494*f73343faSRob Clark 1495*f73343faSRob Clark #define REG_A6XX_RBBM_STATUS2 0x00000212 1496*f73343faSRob Clark 14972d756322SRob Clark #define REG_A6XX_RBBM_STATUS3 0x00000213 1498c28c82e9SRob Clark #define A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT 0x01000000 14992d756322SRob Clark 15002d756322SRob Clark #define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215 15012d756322SRob Clark 1502*f73343faSRob Clark #define REG_A7XX_RBBM_CLOCK_MODE_CP 0x00000260 1503*f73343faSRob Clark 1504*f73343faSRob Clark #define REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ 0x00000284 1505*f73343faSRob Clark 1506*f73343faSRob Clark #define REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS 0x00000285 1507*f73343faSRob Clark 1508*f73343faSRob Clark #define REG_A7XX_RBBM_CLOCK_MODE2_GRAS 0x00000286 1509*f73343faSRob Clark 1510*f73343faSRob Clark #define REG_A7XX_RBBM_CLOCK_MODE_BV_VFD 0x00000287 1511*f73343faSRob Clark 1512*f73343faSRob Clark #define REG_A7XX_RBBM_CLOCK_MODE_BV_GPC 0x00000288 1513*f73343faSRob Clark 1514cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000400 + 0x2*i0; } 15152d756322SRob Clark 1516cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000041c + 0x2*i0; } 15172d756322SRob Clark 1518cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000424 + 0x2*i0; } 15192d756322SRob Clark 1520cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000434 + 0x2*i0; } 15212d756322SRob Clark 1522cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000444 + 0x2*i0; } 15232d756322SRob Clark 1524cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000450 + 0x2*i0; } 15252d756322SRob Clark 1526cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000045c + 0x2*i0; } 15272d756322SRob Clark 1528cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000466 + 0x2*i0; } 15292d756322SRob Clark 1530cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000046e + 0x2*i0; } 15312d756322SRob Clark 1532cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000476 + 0x2*i0; } 15332d756322SRob Clark 1534cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000048e + 0x2*i0; } 15352d756322SRob Clark 1536cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000004a6 + 0x2*i0; } 15372d756322SRob Clark 1538cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000004d6 + 0x2*i0; } 15392d756322SRob Clark 1540cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000004e6 + 0x2*i0; } 15412d756322SRob Clark 1542cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000004ea + 0x2*i0; } 15432d756322SRob Clark 1544cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000004f2 + 0x2*i0; } 15452d756322SRob Clark 1546*f73343faSRob Clark static inline uint32_t REG_A7XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000300 + 0x2*i0; } 1547*f73343faSRob Clark 1548*f73343faSRob Clark static inline uint32_t REG_A7XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000031c + 0x2*i0; } 1549*f73343faSRob Clark 1550*f73343faSRob Clark static inline uint32_t REG_A7XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000324 + 0x2*i0; } 1551*f73343faSRob Clark 1552*f73343faSRob Clark static inline uint32_t REG_A7XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000334 + 0x2*i0; } 1553*f73343faSRob Clark 1554*f73343faSRob Clark static inline uint32_t REG_A7XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000344 + 0x2*i0; } 1555*f73343faSRob Clark 1556*f73343faSRob Clark static inline uint32_t REG_A7XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000350 + 0x2*i0; } 1557*f73343faSRob Clark 1558*f73343faSRob Clark static inline uint32_t REG_A7XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000035c + 0x2*i0; } 1559*f73343faSRob Clark 1560*f73343faSRob Clark static inline uint32_t REG_A7XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000366 + 0x2*i0; } 1561*f73343faSRob Clark 1562*f73343faSRob Clark static inline uint32_t REG_A7XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000036e + 0x2*i0; } 1563*f73343faSRob Clark 1564*f73343faSRob Clark static inline uint32_t REG_A7XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000376 + 0x2*i0; } 1565*f73343faSRob Clark 1566*f73343faSRob Clark static inline uint32_t REG_A7XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000038e + 0x2*i0; } 1567*f73343faSRob Clark 1568*f73343faSRob Clark static inline uint32_t REG_A7XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000003a6 + 0x2*i0; } 1569*f73343faSRob Clark 1570*f73343faSRob Clark static inline uint32_t REG_A7XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000003d6 + 0x2*i0; } 1571*f73343faSRob Clark 1572*f73343faSRob Clark static inline uint32_t REG_A7XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000003e6 + 0x2*i0; } 1573*f73343faSRob Clark 1574*f73343faSRob Clark static inline uint32_t REG_A7XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000003ea + 0x2*i0; } 1575*f73343faSRob Clark 1576*f73343faSRob Clark static inline uint32_t REG_A7XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000003f2 + 0x2*i0; } 1577*f73343faSRob Clark 1578*f73343faSRob Clark static inline uint32_t REG_A7XX_RBBM_PERFCTR_UFC(uint32_t i0) { return 0x000003fa + 0x2*i0; } 1579*f73343faSRob Clark 1580*f73343faSRob Clark static inline uint32_t REG_A7XX_RBBM_PERFCTR2_HLSQ(uint32_t i0) { return 0x00000410 + 0x2*i0; } 1581*f73343faSRob Clark 1582*f73343faSRob Clark static inline uint32_t REG_A7XX_RBBM_PERFCTR2_CP(uint32_t i0) { return 0x0000041c + 0x2*i0; } 1583*f73343faSRob Clark 1584*f73343faSRob Clark static inline uint32_t REG_A7XX_RBBM_PERFCTR2_SP(uint32_t i0) { return 0x0000042a + 0x2*i0; } 1585*f73343faSRob Clark 1586*f73343faSRob Clark static inline uint32_t REG_A7XX_RBBM_PERFCTR2_TP(uint32_t i0) { return 0x00000442 + 0x2*i0; } 1587*f73343faSRob Clark 1588*f73343faSRob Clark static inline uint32_t REG_A7XX_RBBM_PERFCTR2_UFC(uint32_t i0) { return 0x0000044e + 0x2*i0; } 1589*f73343faSRob Clark 1590*f73343faSRob Clark static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_PC(uint32_t i0) { return 0x00000460 + 0x2*i0; } 1591*f73343faSRob Clark 1592*f73343faSRob Clark static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_VFD(uint32_t i0) { return 0x00000470 + 0x2*i0; } 1593*f73343faSRob Clark 1594*f73343faSRob Clark static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_VPC(uint32_t i0) { return 0x00000480 + 0x2*i0; } 1595*f73343faSRob Clark 1596*f73343faSRob Clark static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_TSE(uint32_t i0) { return 0x0000048c + 0x2*i0; } 1597*f73343faSRob Clark 1598*f73343faSRob Clark static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_RAS(uint32_t i0) { return 0x00000494 + 0x2*i0; } 1599*f73343faSRob Clark 1600*f73343faSRob Clark static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_LRZ(uint32_t i0) { return 0x0000049c + 0x2*i0; } 1601*f73343faSRob Clark 16022d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500 16032d756322SRob Clark 16042d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 0x00000501 16052d756322SRob Clark 16062d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 0x00000502 16072d756322SRob Clark 16082d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 0x00000503 16092d756322SRob Clark 16102d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 0x00000504 16112d756322SRob Clark 16122d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000505 16132d756322SRob Clark 16142d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506 16152d756322SRob Clark 1616cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00000507 + 0x1*i0; } 16172d756322SRob Clark 16182d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b 16192d756322SRob Clark 162057cfe41cSRob Clark #define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD 0x0000050e 162157cfe41cSRob Clark 162257cfe41cSRob Clark #define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS 0x0000050f 162357cfe41cSRob Clark 16242d756322SRob Clark #define REG_A6XX_RBBM_ISDB_CNT 0x00000533 16252d756322SRob Clark 1626*f73343faSRob Clark #define REG_A7XX_RBBM_NC_MODE_CNTL 0x00000534 1627*f73343faSRob Clark 1628*f73343faSRob Clark #define REG_A7XX_RBBM_SNAPSHOT_STATUS 0x00000535 1629*f73343faSRob Clark 1630c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_0_LO 0x00000540 1631c28c82e9SRob Clark 1632c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_0_HI 0x00000541 1633c28c82e9SRob Clark 1634c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_1_LO 0x00000542 1635c28c82e9SRob Clark 1636c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_1_HI 0x00000543 1637c28c82e9SRob Clark 1638c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_2_LO 0x00000544 1639c28c82e9SRob Clark 1640c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_2_HI 0x00000545 1641c28c82e9SRob Clark 1642c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_3_LO 0x00000546 1643c28c82e9SRob Clark 1644c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_3_HI 0x00000547 1645c28c82e9SRob Clark 1646c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_4_LO 0x00000548 1647c28c82e9SRob Clark 1648c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_4_HI 0x00000549 1649c28c82e9SRob Clark 1650c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_5_LO 0x0000054a 1651c28c82e9SRob Clark 1652c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_5_HI 0x0000054b 1653c28c82e9SRob Clark 1654c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_6_LO 0x0000054c 1655c28c82e9SRob Clark 1656c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_6_HI 0x0000054d 1657c28c82e9SRob Clark 1658c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_7_LO 0x0000054e 1659c28c82e9SRob Clark 1660c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_7_HI 0x0000054f 1661c28c82e9SRob Clark 1662c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_8_LO 0x00000550 1663c28c82e9SRob Clark 1664c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_8_HI 0x00000551 1665c28c82e9SRob Clark 1666c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_9_LO 0x00000552 1667c28c82e9SRob Clark 1668c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_9_HI 0x00000553 1669c28c82e9SRob Clark 1670c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_10_LO 0x00000554 1671c28c82e9SRob Clark 1672c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_10_HI 0x00000555 1673c28c82e9SRob Clark 16742d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TRUST_CNTL 0x0000f400 16752d756322SRob Clark 1676*f73343faSRob Clark #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE 0x0000f800 16772d756322SRob Clark 16782d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802 16792d756322SRob Clark 16802d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_CNTL 0x0000f803 16812d756322SRob Clark 16822d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810 16832d756322SRob Clark 1684*f73343faSRob Clark #define REG_A7XX_RBBM_SECVID_TSB_STATUS 0x0000fc00 1685*f73343faSRob Clark 16862d756322SRob Clark #define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL 0x00000010 16872d756322SRob Clark 168824e6938eSJonathan Marek #define REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL 0x00000011 168924e6938eSJonathan Marek 16903a9dd708SAkhil P Oommen #define REG_A6XX_RBBM_GBIF_HALT 0x00000016 16913a9dd708SAkhil P Oommen 16923a9dd708SAkhil P Oommen #define REG_A6XX_RBBM_GBIF_HALT_ACK 0x00000017 16933a9dd708SAkhil P Oommen 1694c28c82e9SRob Clark #define REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD 0x0000001c 1695c28c82e9SRob Clark #define A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE 0x00000001 1696c28c82e9SRob Clark 1697*f73343faSRob Clark #define REG_A7XX_RBBM_GBIF_HALT 0x00000016 1698*f73343faSRob Clark 1699*f73343faSRob Clark #define REG_A7XX_RBBM_GBIF_HALT_ACK 0x00000017 1700*f73343faSRob Clark 17012d756322SRob Clark #define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000001f 17022d756322SRob Clark 17032d756322SRob Clark #define REG_A6XX_RBBM_INT_CLEAR_CMD 0x00000037 17042d756322SRob Clark 17052d756322SRob Clark #define REG_A6XX_RBBM_INT_0_MASK 0x00000038 17062d756322SRob Clark 1707*f73343faSRob Clark #define REG_A7XX_RBBM_INT_2_MASK 0x0000003a 1708*f73343faSRob Clark 17092d756322SRob Clark #define REG_A6XX_RBBM_SP_HYST_CNT 0x00000042 17102d756322SRob Clark 17112d756322SRob Clark #define REG_A6XX_RBBM_SW_RESET_CMD 0x00000043 17122d756322SRob Clark 17132d756322SRob Clark #define REG_A6XX_RBBM_RAC_THRESHOLD_CNT 0x00000044 17142d756322SRob Clark 17152d756322SRob Clark #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 17162d756322SRob Clark 17172d756322SRob Clark #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046 17182d756322SRob Clark 17192d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae 17202d756322SRob Clark 17212d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0 17222d756322SRob Clark 17232d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_SP1 0x000000b1 17242d756322SRob Clark 17252d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_SP2 0x000000b2 17262d756322SRob Clark 17272d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_SP3 0x000000b3 17282d756322SRob Clark 17292d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_SP0 0x000000b4 17302d756322SRob Clark 17312d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_SP1 0x000000b5 17322d756322SRob Clark 17332d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_SP2 0x000000b6 17342d756322SRob Clark 17352d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_SP3 0x000000b7 17362d756322SRob Clark 17372d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_SP0 0x000000b8 17382d756322SRob Clark 17392d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_SP1 0x000000b9 17402d756322SRob Clark 17412d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_SP2 0x000000ba 17422d756322SRob Clark 17432d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_SP3 0x000000bb 17442d756322SRob Clark 17452d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_SP0 0x000000bc 17462d756322SRob Clark 17472d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_SP1 0x000000bd 17482d756322SRob Clark 17492d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_SP2 0x000000be 17502d756322SRob Clark 17512d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_SP3 0x000000bf 17522d756322SRob Clark 17532d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TP0 0x000000c0 17542d756322SRob Clark 17552d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TP1 0x000000c1 17562d756322SRob Clark 17572d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TP2 0x000000c2 17582d756322SRob Clark 17592d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TP3 0x000000c3 17602d756322SRob Clark 17612d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_TP0 0x000000c4 17622d756322SRob Clark 17632d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_TP1 0x000000c5 17642d756322SRob Clark 17652d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_TP2 0x000000c6 17662d756322SRob Clark 17672d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_TP3 0x000000c7 17682d756322SRob Clark 17692d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_TP0 0x000000c8 17702d756322SRob Clark 17712d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_TP1 0x000000c9 17722d756322SRob Clark 17732d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_TP2 0x000000ca 17742d756322SRob Clark 17752d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_TP3 0x000000cb 17762d756322SRob Clark 17772d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_TP0 0x000000cc 17782d756322SRob Clark 17792d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_TP1 0x000000cd 17802d756322SRob Clark 17812d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_TP2 0x000000ce 17822d756322SRob Clark 17832d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_TP3 0x000000cf 17842d756322SRob Clark 17852d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TP0 0x000000d0 17862d756322SRob Clark 17872d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TP1 0x000000d1 17882d756322SRob Clark 17892d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TP2 0x000000d2 17902d756322SRob Clark 17912d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TP3 0x000000d3 17922d756322SRob Clark 17932d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY2_TP0 0x000000d4 17942d756322SRob Clark 17952d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY2_TP1 0x000000d5 17962d756322SRob Clark 17972d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY2_TP2 0x000000d6 17982d756322SRob Clark 17992d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY2_TP3 0x000000d7 18002d756322SRob Clark 18012d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY3_TP0 0x000000d8 18022d756322SRob Clark 18032d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY3_TP1 0x000000d9 18042d756322SRob Clark 18052d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY3_TP2 0x000000da 18062d756322SRob Clark 18072d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY3_TP3 0x000000db 18082d756322SRob Clark 18092d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY4_TP0 0x000000dc 18102d756322SRob Clark 18112d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY4_TP1 0x000000dd 18122d756322SRob Clark 18132d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY4_TP2 0x000000de 18142d756322SRob Clark 18152d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY4_TP3 0x000000df 18162d756322SRob Clark 18172d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TP0 0x000000e0 18182d756322SRob Clark 18192d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TP1 0x000000e1 18202d756322SRob Clark 18212d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TP2 0x000000e2 18222d756322SRob Clark 18232d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TP3 0x000000e3 18242d756322SRob Clark 18252d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST2_TP0 0x000000e4 18262d756322SRob Clark 18272d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST2_TP1 0x000000e5 18282d756322SRob Clark 18292d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST2_TP2 0x000000e6 18302d756322SRob Clark 18312d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST2_TP3 0x000000e7 18322d756322SRob Clark 18332d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST3_TP0 0x000000e8 18342d756322SRob Clark 18352d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST3_TP1 0x000000e9 18362d756322SRob Clark 18372d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST3_TP2 0x000000ea 18382d756322SRob Clark 18392d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST3_TP3 0x000000eb 18402d756322SRob Clark 18412d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST4_TP0 0x000000ec 18422d756322SRob Clark 18432d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST4_TP1 0x000000ed 18442d756322SRob Clark 18452d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST4_TP2 0x000000ee 18462d756322SRob Clark 18472d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST4_TP3 0x000000ef 18482d756322SRob Clark 18492d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RB0 0x000000f0 18502d756322SRob Clark 18512d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RB1 0x000000f1 18522d756322SRob Clark 18532d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RB2 0x000000f2 18542d756322SRob Clark 18552d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RB3 0x000000f3 18562d756322SRob Clark 18572d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RB0 0x000000f4 18582d756322SRob Clark 18592d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RB1 0x000000f5 18602d756322SRob Clark 18612d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RB2 0x000000f6 18622d756322SRob Clark 18632d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RB3 0x000000f7 18642d756322SRob Clark 18652d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_CCU0 0x000000f8 18662d756322SRob Clark 18672d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_CCU1 0x000000f9 18682d756322SRob Clark 18692d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_CCU2 0x000000fa 18702d756322SRob Clark 18712d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_CCU3 0x000000fb 18722d756322SRob Clark 18732d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000100 18742d756322SRob Clark 18752d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000101 18762d756322SRob Clark 18772d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000102 18782d756322SRob Clark 18792d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000103 18802d756322SRob Clark 18812d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RAC 0x00000104 18822d756322SRob Clark 18832d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RAC 0x00000105 18842d756322SRob Clark 18852d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_RAC 0x00000106 18862d756322SRob Clark 18872d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RAC 0x00000107 18882d756322SRob Clark 18892d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000108 18902d756322SRob Clark 18912d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000109 18922d756322SRob Clark 18932d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000010a 18942d756322SRob Clark 18952d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_UCHE 0x0000010b 18962d756322SRob Clark 18972d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE 0x0000010c 18982d756322SRob Clark 18992d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE 0x0000010d 19002d756322SRob Clark 19012d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE 0x0000010e 19022d756322SRob Clark 19032d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_UCHE 0x0000010f 19042d756322SRob Clark 19052d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_UCHE 0x00000110 19062d756322SRob Clark 19072d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_MODE_VFD 0x00000111 19082d756322SRob Clark 19092d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_VFD 0x00000112 19102d756322SRob Clark 19112d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_VFD 0x00000113 19122d756322SRob Clark 19132d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_MODE_GPC 0x00000114 19142d756322SRob Clark 19152d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_GPC 0x00000115 19162d756322SRob Clark 19172d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_GPC 0x00000116 19182d756322SRob Clark 19192d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2 0x00000117 19202d756322SRob Clark 19212d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX 0x00000118 19222d756322SRob Clark 19232d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX 0x00000119 19242d756322SRob Clark 19252d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX 0x0000011a 19262d756322SRob Clark 19272d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_MODE_HLSQ 0x0000011b 19282d756322SRob Clark 19292d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ 0x0000011c 19302d756322SRob Clark 1931c28c82e9SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_HLSQ 0x0000011d 1932c28c82e9SRob Clark 1933c28c82e9SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE 0x00000120 1934c28c82e9SRob Clark 1935c28c82e9SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE 0x00000121 1936c28c82e9SRob Clark 1937c28c82e9SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122 1938c28c82e9SRob Clark 1939*f73343faSRob Clark #define REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL 0x000005ff 1940*f73343faSRob Clark 19412d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A 0x00000600 19422d756322SRob Clark 19432d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B 0x00000601 19442d756322SRob Clark 19452d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C 0x00000602 19462d756322SRob Clark 19472d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D 0x00000603 19482d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK 0x000000ff 19492d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT 0 19502d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val) 19512d756322SRob Clark { 19522d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK; 19532d756322SRob Clark } 19542d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK 0x0000ff00 19552d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT 8 19562d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val) 19572d756322SRob Clark { 19582d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK; 19592d756322SRob Clark } 19602d756322SRob Clark 19612d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT 0x00000604 19622d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f 19632d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0 19642d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) 19652d756322SRob Clark { 19662d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; 19672d756322SRob Clark } 19682d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000 19692d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12 19702d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) 19712d756322SRob Clark { 19722d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; 19732d756322SRob Clark } 19742d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000 19752d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28 19762d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) 19772d756322SRob Clark { 19782d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; 19792d756322SRob Clark } 19802d756322SRob Clark 19812d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM 0x00000605 19822d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000 19832d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24 19842d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) 19852d756322SRob Clark { 19862d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; 19872d756322SRob Clark } 19882d756322SRob Clark 19892d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 0x00000608 19902d756322SRob Clark 19912d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 0x00000609 19922d756322SRob Clark 19932d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 0x0000060a 19942d756322SRob Clark 19952d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 0x0000060b 19962d756322SRob Clark 19972d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 0x0000060c 19982d756322SRob Clark 19992d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 0x0000060d 20002d756322SRob Clark 20012d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 0x0000060e 20022d756322SRob Clark 20032d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 0x0000060f 20042d756322SRob Clark 20052d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000610 20062d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f 20072d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0 20082d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) 20092d756322SRob Clark { 20102d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; 20112d756322SRob Clark } 20122d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0 20132d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4 20142d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) 20152d756322SRob Clark { 20162d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; 20172d756322SRob Clark } 20182d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00 20192d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8 20202d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) 20212d756322SRob Clark { 20222d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; 20232d756322SRob Clark } 20242d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000 20252d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12 20262d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) 20272d756322SRob Clark { 20282d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; 20292d756322SRob Clark } 20302d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000 20312d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16 20322d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) 20332d756322SRob Clark { 20342d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; 20352d756322SRob Clark } 20362d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000 20372d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20 20382d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) 20392d756322SRob Clark { 20402d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; 20412d756322SRob Clark } 20422d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000 20432d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24 20442d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) 20452d756322SRob Clark { 20462d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; 20472d756322SRob Clark } 20482d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000 20492d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28 20502d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) 20512d756322SRob Clark { 20522d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; 20532d756322SRob Clark } 20542d756322SRob Clark 20552d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000611 20562d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f 20572d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0 20582d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) 20592d756322SRob Clark { 20602d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; 20612d756322SRob Clark } 20622d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0 20632d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4 20642d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) 20652d756322SRob Clark { 20662d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; 20672d756322SRob Clark } 20682d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00 20692d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8 20702d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) 20712d756322SRob Clark { 20722d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; 20732d756322SRob Clark } 20742d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000 20752d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12 20762d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) 20772d756322SRob Clark { 20782d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; 20792d756322SRob Clark } 20802d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000 20812d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16 20822d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) 20832d756322SRob Clark { 20842d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; 20852d756322SRob Clark } 20862d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000 20872d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20 20882d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) 20892d756322SRob Clark { 20902d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; 20912d756322SRob Clark } 20922d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000 20932d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24 20942d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) 20952d756322SRob Clark { 20962d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; 20972d756322SRob Clark } 20982d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000 20992d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28 21002d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) 21012d756322SRob Clark { 21022d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; 21032d756322SRob Clark } 21042d756322SRob Clark 21052d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000062f 21062d756322SRob Clark 21072d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630 21082d756322SRob Clark 2109cc4c26d4SRob Clark static inline uint32_t REG_A6XX_VSC_PERFCTR_VSC_SEL(uint32_t i0) { return 0x00000cd8 + 0x1*i0; } 21102d756322SRob Clark 21112d756322SRob Clark #define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800 21122d756322SRob Clark 21132d756322SRob Clark #define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000 21142d756322SRob Clark 21152d756322SRob Clark #define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00 21162d756322SRob Clark 21172d756322SRob Clark #define REG_A6XX_UCHE_MODE_CNTL 0x00000e01 21182d756322SRob Clark 2119*f73343faSRob Clark #define REG_A6XX_UCHE_WRITE_RANGE_MAX 0x00000e05 21202d756322SRob Clark 2121*f73343faSRob Clark #define REG_A6XX_UCHE_WRITE_THRU_BASE 0x00000e07 21222d756322SRob Clark 2123*f73343faSRob Clark #define REG_A6XX_UCHE_TRAP_BASE 0x00000e09 21242d756322SRob Clark 2125*f73343faSRob Clark #define REG_A6XX_UCHE_GMEM_RANGE_MIN 0x00000e0b 21262d756322SRob Clark 2127*f73343faSRob Clark #define REG_A6XX_UCHE_GMEM_RANGE_MAX 0x00000e0d 21282d756322SRob Clark 21292d756322SRob Clark #define REG_A6XX_UCHE_CACHE_WAYS 0x00000e17 21302d756322SRob Clark 21312d756322SRob Clark #define REG_A6XX_UCHE_FILTER_CNTL 0x00000e18 21322d756322SRob Clark 21332d756322SRob Clark #define REG_A6XX_UCHE_CLIENT_PF 0x00000e19 21342d756322SRob Clark #define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK 0x000000ff 21352d756322SRob Clark #define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT 0 21362d756322SRob Clark static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val) 21372d756322SRob Clark { 21382d756322SRob Clark return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK; 21392d756322SRob Clark } 21402d756322SRob Clark 2141cc4c26d4SRob Clark static inline uint32_t REG_A6XX_UCHE_PERFCTR_UCHE_SEL(uint32_t i0) { return 0x00000e1c + 0x1*i0; } 21422d756322SRob Clark 2143*f73343faSRob Clark #define REG_A6XX_UCHE_GBIF_GX_CONFIG 0x00000e3a 2144*f73343faSRob Clark 2145cc4c26d4SRob Clark #define REG_A6XX_UCHE_CMDQ_CONFIG 0x00000e3c 21462d756322SRob Clark 21472d756322SRob Clark #define REG_A6XX_VBIF_VERSION 0x00003000 21482d756322SRob Clark 2149a69c5ed2SRob Clark #define REG_A6XX_VBIF_CLKON 0x00003001 2150a69c5ed2SRob Clark #define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000002 2151a69c5ed2SRob Clark 21522d756322SRob Clark #define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 21532d756322SRob Clark 21542d756322SRob Clark #define REG_A6XX_VBIF_XIN_HALT_CTRL0 0x00003080 21552d756322SRob Clark 21562d756322SRob Clark #define REG_A6XX_VBIF_XIN_HALT_CTRL1 0x00003081 21572d756322SRob Clark 2158a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084 2159a69c5ed2SRob Clark 2160a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS1_CTRL0 0x00003085 2161a69c5ed2SRob Clark 2162a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS1_CTRL1 0x00003086 2163a69c5ed2SRob Clark #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK 0x0000000f 2164a69c5ed2SRob Clark #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT 0 2165a69c5ed2SRob Clark static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val) 2166a69c5ed2SRob Clark { 2167a69c5ed2SRob Clark return ((val) << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK; 2168a69c5ed2SRob Clark } 2169a69c5ed2SRob Clark 2170a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS2_CTRL0 0x00003087 2171a69c5ed2SRob Clark 2172a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS2_CTRL1 0x00003088 2173a69c5ed2SRob Clark #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK 0x000001ff 2174a69c5ed2SRob Clark #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT 0 2175a69c5ed2SRob Clark static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val) 2176a69c5ed2SRob Clark { 2177a69c5ed2SRob Clark return ((val) << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK; 2178a69c5ed2SRob Clark } 2179a69c5ed2SRob Clark 2180a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS_OUT 0x0000308c 2181a69c5ed2SRob Clark 21822d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_SEL0 0x000030d0 21832d756322SRob Clark 21842d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_SEL1 0x000030d1 21852d756322SRob Clark 21862d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_SEL2 0x000030d2 21872d756322SRob Clark 21882d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_SEL3 0x000030d3 21892d756322SRob Clark 21902d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_LOW0 0x000030d8 21912d756322SRob Clark 21922d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_LOW1 0x000030d9 21932d756322SRob Clark 21942d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_LOW2 0x000030da 21952d756322SRob Clark 21962d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_LOW3 0x000030db 21972d756322SRob Clark 21982d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_HIGH0 0x000030e0 21992d756322SRob Clark 22002d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_HIGH1 0x000030e1 22012d756322SRob Clark 22022d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_HIGH2 0x000030e2 22032d756322SRob Clark 22042d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_HIGH3 0x000030e3 22052d756322SRob Clark 22062d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_EN0 0x00003100 22072d756322SRob Clark 22082d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_EN1 0x00003101 22092d756322SRob Clark 22102d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_EN2 0x00003102 22112d756322SRob Clark 22122d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110 22132d756322SRob Clark 22142d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111 22152d756322SRob Clark 22162d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112 22172d756322SRob Clark 22182d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118 22192d756322SRob Clark 22202d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119 22212d756322SRob Clark 22222d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a 22232d756322SRob Clark 2224cc4c26d4SRob Clark #define REG_A6XX_GBIF_SCACHE_CNTL0 0x00003c01 2225cc4c26d4SRob Clark 2226e812744cSSharat Masetty #define REG_A6XX_GBIF_SCACHE_CNTL1 0x00003c02 2227e812744cSSharat Masetty 2228e812744cSSharat Masetty #define REG_A6XX_GBIF_QSB_SIDE0 0x00003c03 2229e812744cSSharat Masetty 2230e812744cSSharat Masetty #define REG_A6XX_GBIF_QSB_SIDE1 0x00003c04 2231e812744cSSharat Masetty 2232e812744cSSharat Masetty #define REG_A6XX_GBIF_QSB_SIDE2 0x00003c05 2233e812744cSSharat Masetty 2234e812744cSSharat Masetty #define REG_A6XX_GBIF_QSB_SIDE3 0x00003c06 2235e812744cSSharat Masetty 2236e812744cSSharat Masetty #define REG_A6XX_GBIF_HALT 0x00003c45 2237e812744cSSharat Masetty 2238e812744cSSharat Masetty #define REG_A6XX_GBIF_HALT_ACK 0x00003c46 2239e812744cSSharat Masetty 2240e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_PWR_CNT_EN 0x00003cc0 2241e812744cSSharat Masetty 2242*f73343faSRob Clark #define REG_A6XX_GBIF_PERF_PWR_CNT_CLR 0x00003cc1 2243*f73343faSRob Clark 2244e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_SEL 0x00003cc2 2245e812744cSSharat Masetty 2246e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_PWR_CNT_SEL 0x00003cc3 2247e812744cSSharat Masetty 2248e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_LOW0 0x00003cc4 2249e812744cSSharat Masetty 2250e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_LOW1 0x00003cc5 2251e812744cSSharat Masetty 2252e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_LOW2 0x00003cc6 2253e812744cSSharat Masetty 2254e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_LOW3 0x00003cc7 2255e812744cSSharat Masetty 2256e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_HIGH0 0x00003cc8 2257e812744cSSharat Masetty 2258e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_HIGH1 0x00003cc9 2259e812744cSSharat Masetty 2260e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_HIGH2 0x00003cca 2261e812744cSSharat Masetty 2262e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_HIGH3 0x00003ccb 2263e812744cSSharat Masetty 2264e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_LOW0 0x00003ccc 2265e812744cSSharat Masetty 2266e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_LOW1 0x00003ccd 2267e812744cSSharat Masetty 2268e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_LOW2 0x00003cce 2269e812744cSSharat Masetty 2270e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_HIGH0 0x00003ccf 2271e812744cSSharat Masetty 2272e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_HIGH1 0x00003cd0 2273e812744cSSharat Masetty 2274e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_HIGH2 0x00003cd1 2275e812744cSSharat Masetty 227657cfe41cSRob Clark #define REG_A6XX_VSC_DBG_ECO_CNTL 0x00000c00 227757cfe41cSRob Clark 22782d756322SRob Clark #define REG_A6XX_VSC_BIN_SIZE 0x00000c02 22792d756322SRob Clark #define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff 22802d756322SRob Clark #define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 22812d756322SRob Clark static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 22822d756322SRob Clark { 22832d756322SRob Clark return ((val >> 5) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK; 22842d756322SRob Clark } 22852d756322SRob Clark #define A6XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001ff00 22862d756322SRob Clark #define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT 8 22872d756322SRob Clark static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 22882d756322SRob Clark { 22892d756322SRob Clark return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK; 22902d756322SRob Clark } 22912d756322SRob Clark 2292c28c82e9SRob Clark #define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS 0x00000c03 22932d756322SRob Clark 22942d756322SRob Clark #define REG_A6XX_VSC_BIN_COUNT 0x00000c06 22952d756322SRob Clark #define A6XX_VSC_BIN_COUNT_NX__MASK 0x000007fe 22962d756322SRob Clark #define A6XX_VSC_BIN_COUNT_NX__SHIFT 1 22972d756322SRob Clark static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val) 22982d756322SRob Clark { 22992d756322SRob Clark return ((val) << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK; 23002d756322SRob Clark } 23012d756322SRob Clark #define A6XX_VSC_BIN_COUNT_NY__MASK 0x001ff800 23022d756322SRob Clark #define A6XX_VSC_BIN_COUNT_NY__SHIFT 11 23032d756322SRob Clark static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val) 23042d756322SRob Clark { 23052d756322SRob Clark return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK; 23062d756322SRob Clark } 23072d756322SRob Clark 23082d756322SRob Clark static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 23092d756322SRob Clark 23102d756322SRob Clark static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 23112d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff 23122d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0 23132d756322SRob Clark static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) 23142d756322SRob Clark { 23152d756322SRob Clark return ((val) << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK; 23162d756322SRob Clark } 23172d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00 23182d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10 23192d756322SRob Clark static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) 23202d756322SRob Clark { 23212d756322SRob Clark return ((val) << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK; 23222d756322SRob Clark } 23232d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_W__MASK 0x03f00000 23242d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20 23252d756322SRob Clark static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) 23262d756322SRob Clark { 23272d756322SRob Clark return ((val) << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK; 23282d756322SRob Clark } 23292d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_H__MASK 0xfc000000 23302d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT 26 23312d756322SRob Clark static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) 23322d756322SRob Clark { 23332d756322SRob Clark return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK; 23342d756322SRob Clark } 23352d756322SRob Clark 2336c28c82e9SRob Clark #define REG_A6XX_VSC_PRIM_STRM_ADDRESS 0x00000c30 2337a69c5ed2SRob Clark 2338c28c82e9SRob Clark #define REG_A6XX_VSC_PRIM_STRM_PITCH 0x00000c32 23392d756322SRob Clark 2340c28c82e9SRob Clark #define REG_A6XX_VSC_PRIM_STRM_LIMIT 0x00000c33 23412d756322SRob Clark 2342c28c82e9SRob Clark #define REG_A6XX_VSC_DRAW_STRM_ADDRESS 0x00000c34 2343a69c5ed2SRob Clark 2344c28c82e9SRob Clark #define REG_A6XX_VSC_DRAW_STRM_PITCH 0x00000c36 23452d756322SRob Clark 2346c28c82e9SRob Clark #define REG_A6XX_VSC_DRAW_STRM_LIMIT 0x00000c37 2347c28c82e9SRob Clark 2348c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_STATE(uint32_t i0) { return 0x00000c38 + 0x1*i0; } 2349c28c82e9SRob Clark 2350c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_STATE_REG(uint32_t i0) { return 0x00000c38 + 0x1*i0; } 2351c28c82e9SRob Clark 2352c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE(uint32_t i0) { return 0x00000c58 + 0x1*i0; } 2353c28c82e9SRob Clark 2354c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0) { return 0x00000c58 + 0x1*i0; } 2355c28c82e9SRob Clark 2356c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; } 2357c28c82e9SRob Clark 2358c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; } 23592d756322SRob Clark 23602d756322SRob Clark #define REG_A6XX_UCHE_UNKNOWN_0E12 0x00000e12 23612d756322SRob Clark 2362c28c82e9SRob Clark #define REG_A6XX_GRAS_CL_CNTL 0x00008000 2363c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_CLIP_DISABLE 0x00000001 2364c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE 0x00000002 2365c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE 0x00000004 2366*f73343faSRob Clark #define A6XX_GRAS_CL_CNTL_Z_CLAMP_ENABLE 0x00000020 2367c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040 2368c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE 0x00000080 2369c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE 0x00000100 2370c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE 0x00000200 2371a69c5ed2SRob Clark 2372c28c82e9SRob Clark #define REG_A6XX_GRAS_VS_CL_CNTL 0x00008001 2373c28c82e9SRob Clark #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK 0x000000ff 2374c28c82e9SRob Clark #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT 0 2375c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val) 2376c28c82e9SRob Clark { 2377c28c82e9SRob Clark return ((val) << A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK; 2378c28c82e9SRob Clark } 2379c28c82e9SRob Clark #define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK 0x0000ff00 2380c28c82e9SRob Clark #define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT 8 2381c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val) 2382c28c82e9SRob Clark { 2383c28c82e9SRob Clark return ((val) << A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK; 2384c28c82e9SRob Clark } 23852d756322SRob Clark 2386c28c82e9SRob Clark #define REG_A6XX_GRAS_DS_CL_CNTL 0x00008002 2387c28c82e9SRob Clark #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK 0x000000ff 2388c28c82e9SRob Clark #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT 0 2389c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(uint32_t val) 2390c28c82e9SRob Clark { 2391c28c82e9SRob Clark return ((val) << A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK; 2392c28c82e9SRob Clark } 2393c28c82e9SRob Clark #define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK 0x0000ff00 2394c28c82e9SRob Clark #define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT 8 2395c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CULL_MASK(uint32_t val) 2396c28c82e9SRob Clark { 2397c28c82e9SRob Clark return ((val) << A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK; 2398c28c82e9SRob Clark } 2399c28c82e9SRob Clark 2400c28c82e9SRob Clark #define REG_A6XX_GRAS_GS_CL_CNTL 0x00008003 2401c28c82e9SRob Clark #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK 0x000000ff 2402c28c82e9SRob Clark #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT 0 2403c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(uint32_t val) 2404c28c82e9SRob Clark { 2405c28c82e9SRob Clark return ((val) << A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK; 2406c28c82e9SRob Clark } 2407c28c82e9SRob Clark #define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK 0x0000ff00 2408c28c82e9SRob Clark #define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT 8 2409c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CULL_MASK(uint32_t val) 2410c28c82e9SRob Clark { 2411c28c82e9SRob Clark return ((val) << A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK; 2412c28c82e9SRob Clark } 2413c28c82e9SRob Clark 2414c28c82e9SRob Clark #define REG_A6XX_GRAS_MAX_LAYER_INDEX 0x00008004 24152d756322SRob Clark 24162d756322SRob Clark #define REG_A6XX_GRAS_CNTL 0x00008005 2417c28c82e9SRob Clark #define A6XX_GRAS_CNTL_IJ_PERSP_PIXEL 0x00000001 2418c28c82e9SRob Clark #define A6XX_GRAS_CNTL_IJ_PERSP_CENTROID 0x00000002 2419c28c82e9SRob Clark #define A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE 0x00000004 242057cfe41cSRob Clark #define A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL 0x00000008 242157cfe41cSRob Clark #define A6XX_GRAS_CNTL_IJ_LINEAR_CENTROID 0x00000010 242257cfe41cSRob Clark #define A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE 0x00000020 2423c28c82e9SRob Clark #define A6XX_GRAS_CNTL_COORD_MASK__MASK 0x000003c0 2424c28c82e9SRob Clark #define A6XX_GRAS_CNTL_COORD_MASK__SHIFT 6 2425c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CNTL_COORD_MASK(uint32_t val) 2426c28c82e9SRob Clark { 2427c28c82e9SRob Clark return ((val) << A6XX_GRAS_CNTL_COORD_MASK__SHIFT) & A6XX_GRAS_CNTL_COORD_MASK__MASK; 2428c28c82e9SRob Clark } 24292d756322SRob Clark 24302d756322SRob Clark #define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x00008006 2431c28c82e9SRob Clark #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000001ff 24322d756322SRob Clark #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0 24332d756322SRob Clark static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val) 24342d756322SRob Clark { 24352d756322SRob Clark return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK; 24362d756322SRob Clark } 2437c28c82e9SRob Clark #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x0007fc00 24382d756322SRob Clark #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10 24392d756322SRob Clark static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) 24402d756322SRob Clark { 24412d756322SRob Clark return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK; 24422d756322SRob Clark } 24432d756322SRob Clark 2444c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT(uint32_t i0) { return 0x00008010 + 0x6*i0; } 2445c28c82e9SRob Clark 2446c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0) { return 0x00008010 + 0x6*i0; } 2447c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff 2448c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0 2449c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET(float val) 24502d756322SRob Clark { 2451c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET__MASK; 24522d756322SRob Clark } 24532d756322SRob Clark 2454c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XSCALE(uint32_t i0) { return 0x00008011 + 0x6*i0; } 2455c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff 2456c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_XSCALE__SHIFT 0 2457c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE(float val) 24582d756322SRob Clark { 2459c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE__MASK; 24602d756322SRob Clark } 24612d756322SRob Clark 2462c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YOFFSET(uint32_t i0) { return 0x00008012 + 0x6*i0; } 2463c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff 2464c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0 2465c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET(float val) 24662d756322SRob Clark { 2467c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET__MASK; 24682d756322SRob Clark } 24692d756322SRob Clark 2470c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YSCALE(uint32_t i0) { return 0x00008013 + 0x6*i0; } 2471c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff 2472c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_YSCALE__SHIFT 0 2473c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE(float val) 24742d756322SRob Clark { 2475c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE__MASK; 24762d756322SRob Clark } 24772d756322SRob Clark 2478c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZOFFSET(uint32_t i0) { return 0x00008014 + 0x6*i0; } 2479c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff 2480c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0 2481c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET(float val) 24822d756322SRob Clark { 2483c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET__MASK; 24842d756322SRob Clark } 24852d756322SRob Clark 2486c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZSCALE(uint32_t i0) { return 0x00008015 + 0x6*i0; } 2487c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff 2488c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0 2489c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE(float val) 24902d756322SRob Clark { 2491c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE__MASK; 2492c28c82e9SRob Clark } 2493c28c82e9SRob Clark 2494c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP(uint32_t i0) { return 0x00008070 + 0x2*i0; } 2495c28c82e9SRob Clark 2496c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0) { return 0x00008070 + 0x2*i0; } 2497c28c82e9SRob Clark #define A6XX_GRAS_CL_Z_CLAMP_MIN__MASK 0xffffffff 2498c28c82e9SRob Clark #define A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT 0 2499c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MIN(float val) 2500c28c82e9SRob Clark { 2501c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MIN__MASK; 2502c28c82e9SRob Clark } 2503c28c82e9SRob Clark 2504c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MAX(uint32_t i0) { return 0x00008071 + 0x2*i0; } 2505c28c82e9SRob Clark #define A6XX_GRAS_CL_Z_CLAMP_MAX__MASK 0xffffffff 2506c28c82e9SRob Clark #define A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT 0 2507c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MAX(float val) 2508c28c82e9SRob Clark { 2509c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MAX__MASK; 25102d756322SRob Clark } 25112d756322SRob Clark 25122d756322SRob Clark #define REG_A6XX_GRAS_SU_CNTL 0x00008090 25132d756322SRob Clark #define A6XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001 25142d756322SRob Clark #define A6XX_GRAS_SU_CNTL_CULL_BACK 0x00000002 25152d756322SRob Clark #define A6XX_GRAS_SU_CNTL_FRONT_CW 0x00000004 25162d756322SRob Clark #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8 25172d756322SRob Clark #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3 25182d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) 25192d756322SRob Clark { 25202d756322SRob Clark return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK; 25212d756322SRob Clark } 25222d756322SRob Clark #define A6XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800 2523c28c82e9SRob Clark #define A6XX_GRAS_SU_CNTL_UNK12__MASK 0x00001000 2524c28c82e9SRob Clark #define A6XX_GRAS_SU_CNTL_UNK12__SHIFT 12 2525c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SU_CNTL_UNK12(uint32_t val) 2526c28c82e9SRob Clark { 2527c28c82e9SRob Clark return ((val) << A6XX_GRAS_SU_CNTL_UNK12__SHIFT) & A6XX_GRAS_SU_CNTL_UNK12__MASK; 2528c28c82e9SRob Clark } 252957cfe41cSRob Clark #define A6XX_GRAS_SU_CNTL_LINE_MODE__MASK 0x00002000 253057cfe41cSRob Clark #define A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT 13 253157cfe41cSRob Clark static inline uint32_t A6XX_GRAS_SU_CNTL_LINE_MODE(enum a5xx_line_mode val) 253257cfe41cSRob Clark { 253357cfe41cSRob Clark return ((val) << A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT) & A6XX_GRAS_SU_CNTL_LINE_MODE__MASK; 253457cfe41cSRob Clark } 2535cc4c26d4SRob Clark #define A6XX_GRAS_SU_CNTL_UNK15__MASK 0x00018000 2536c28c82e9SRob Clark #define A6XX_GRAS_SU_CNTL_UNK15__SHIFT 15 2537c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SU_CNTL_UNK15(uint32_t val) 2538c28c82e9SRob Clark { 2539c28c82e9SRob Clark return ((val) << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK; 2540c28c82e9SRob Clark } 2541cc4c26d4SRob Clark #define A6XX_GRAS_SU_CNTL_UNK17 0x00020000 2542cc4c26d4SRob Clark #define A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE 0x00040000 2543cc4c26d4SRob Clark #define A6XX_GRAS_SU_CNTL_UNK19__MASK 0x00780000 2544cc4c26d4SRob Clark #define A6XX_GRAS_SU_CNTL_UNK19__SHIFT 19 2545cc4c26d4SRob Clark static inline uint32_t A6XX_GRAS_SU_CNTL_UNK19(uint32_t val) 2546cc4c26d4SRob Clark { 2547cc4c26d4SRob Clark return ((val) << A6XX_GRAS_SU_CNTL_UNK19__SHIFT) & A6XX_GRAS_SU_CNTL_UNK19__MASK; 2548cc4c26d4SRob Clark } 25492d756322SRob Clark 25502d756322SRob Clark #define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091 25512d756322SRob Clark #define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 25522d756322SRob Clark #define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 25532d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val) 25542d756322SRob Clark { 25552d756322SRob Clark return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 25562d756322SRob Clark } 25572d756322SRob Clark #define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 25582d756322SRob Clark #define A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 25592d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MAX(float val) 25602d756322SRob Clark { 25612d756322SRob Clark return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 25622d756322SRob Clark } 25632d756322SRob Clark 25642d756322SRob Clark #define REG_A6XX_GRAS_SU_POINT_SIZE 0x00008092 2565c28c82e9SRob Clark #define A6XX_GRAS_SU_POINT_SIZE__MASK 0x0000ffff 25662d756322SRob Clark #define A6XX_GRAS_SU_POINT_SIZE__SHIFT 0 25672d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val) 25682d756322SRob Clark { 25692d756322SRob Clark return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK; 25702d756322SRob Clark } 25712d756322SRob Clark 2572a69c5ed2SRob Clark #define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL 0x00008094 2573c28c82e9SRob Clark #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003 2574c28c82e9SRob Clark #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0 2575c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val) 2576c28c82e9SRob Clark { 2577c28c82e9SRob Clark return ((val) << A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK; 2578c28c82e9SRob Clark } 2579a69c5ed2SRob Clark 25802d756322SRob Clark #define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE 0x00008095 25812d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff 25822d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 25832d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val) 25842d756322SRob Clark { 25852d756322SRob Clark return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; 25862d756322SRob Clark } 25872d756322SRob Clark 25882d756322SRob Clark #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00008096 25892d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 25902d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 25912d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 25922d756322SRob Clark { 25932d756322SRob Clark return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 25942d756322SRob Clark } 25952d756322SRob Clark 25962d756322SRob Clark #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x00008097 25972d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff 25982d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0 25992d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val) 26002d756322SRob Clark { 26012d756322SRob Clark return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK; 26022d756322SRob Clark } 26032d756322SRob Clark 26042d756322SRob Clark #define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO 0x00008098 26052d756322SRob Clark #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 26062d756322SRob Clark #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 26072d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) 26082d756322SRob Clark { 26092d756322SRob Clark return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; 26102d756322SRob Clark } 2611c28c82e9SRob Clark #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000008 2612c28c82e9SRob Clark #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT 3 2613c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3(uint32_t val) 2614c28c82e9SRob Clark { 2615c28c82e9SRob Clark return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK; 2616c28c82e9SRob Clark } 26172d756322SRob Clark 261857cfe41cSRob Clark #define REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x00008099 261957cfe41cSRob Clark #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN 0x00000001 262057cfe41cSRob Clark #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK 0x00000006 262157cfe41cSRob Clark #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT 1 262257cfe41cSRob Clark static inline uint32_t A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT(uint32_t val) 262357cfe41cSRob Clark { 262457cfe41cSRob Clark return ((val) << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK; 262557cfe41cSRob Clark } 262657cfe41cSRob Clark #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_INNERCONSERVATIVERASEN 0x00000008 262757cfe41cSRob Clark #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK 0x00000030 262857cfe41cSRob Clark #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT 4 262957cfe41cSRob Clark static inline uint32_t A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4(uint32_t val) 263057cfe41cSRob Clark { 263157cfe41cSRob Clark return ((val) << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK; 263257cfe41cSRob Clark } 26332d756322SRob Clark 263457cfe41cSRob Clark #define REG_A6XX_GRAS_SU_PATH_RENDERING_CNTL 0x0000809a 263557cfe41cSRob Clark #define A6XX_GRAS_SU_PATH_RENDERING_CNTL_UNK0 0x00000001 263657cfe41cSRob Clark #define A6XX_GRAS_SU_PATH_RENDERING_CNTL_LINELENGTHEN 0x00000002 2637c28c82e9SRob Clark 2638c28c82e9SRob Clark #define REG_A6XX_GRAS_VS_LAYER_CNTL 0x0000809b 2639c28c82e9SRob Clark #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER 0x00000001 2640c28c82e9SRob Clark #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW 0x00000002 2641c28c82e9SRob Clark 2642c28c82e9SRob Clark #define REG_A6XX_GRAS_GS_LAYER_CNTL 0x0000809c 2643c28c82e9SRob Clark #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER 0x00000001 2644c28c82e9SRob Clark #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW 0x00000002 2645c28c82e9SRob Clark 2646c28c82e9SRob Clark #define REG_A6XX_GRAS_DS_LAYER_CNTL 0x0000809d 2647c28c82e9SRob Clark #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER 0x00000001 2648c28c82e9SRob Clark #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW 0x00000002 26492d756322SRob Clark 265057cfe41cSRob Clark #define REG_A6XX_GRAS_SC_CNTL 0x000080a0 265157cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK 0x00000007 265257cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT 0 265357cfe41cSRob Clark static inline uint32_t A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(uint32_t val) 265457cfe41cSRob Clark { 265557cfe41cSRob Clark return ((val) << A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK; 265657cfe41cSRob Clark } 265757cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK 0x00000018 265857cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT 3 265957cfe41cSRob Clark static inline uint32_t A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE(enum a6xx_single_prim_mode val) 266057cfe41cSRob Clark { 266157cfe41cSRob Clark return ((val) << A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK; 266257cfe41cSRob Clark } 266357cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK 0x00000020 266457cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT 5 266557cfe41cSRob Clark static inline uint32_t A6XX_GRAS_SC_CNTL_RASTER_MODE(enum a6xx_raster_mode val) 266657cfe41cSRob Clark { 266757cfe41cSRob Clark return ((val) << A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK; 266857cfe41cSRob Clark } 266957cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK 0x000000c0 267057cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT 6 267157cfe41cSRob Clark static inline uint32_t A6XX_GRAS_SC_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val) 267257cfe41cSRob Clark { 267357cfe41cSRob Clark return ((val) << A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK; 267457cfe41cSRob Clark } 267557cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK 0x00000100 267657cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT 8 267757cfe41cSRob Clark static inline uint32_t A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION(enum a6xx_sequenced_thread_dist val) 267857cfe41cSRob Clark { 267957cfe41cSRob Clark return ((val) << A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT) & A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK; 268057cfe41cSRob Clark } 2681*f73343faSRob Clark #define A6XX_GRAS_SC_CNTL_UNK9 0x00000200 2682*f73343faSRob Clark #define A6XX_GRAS_SC_CNTL_ROTATION__MASK 0x00000c00 2683*f73343faSRob Clark #define A6XX_GRAS_SC_CNTL_ROTATION__SHIFT 10 2684*f73343faSRob Clark static inline uint32_t A6XX_GRAS_SC_CNTL_ROTATION(uint32_t val) 268557cfe41cSRob Clark { 2686*f73343faSRob Clark return ((val) << A6XX_GRAS_SC_CNTL_ROTATION__SHIFT) & A6XX_GRAS_SC_CNTL_ROTATION__MASK; 268757cfe41cSRob Clark } 268857cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_EARLYVIZOUTEN 0x00001000 2689a69c5ed2SRob Clark 2690c28c82e9SRob Clark #define REG_A6XX_GRAS_BIN_CONTROL 0x000080a1 2691c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_BINW__MASK 0x0000003f 2692c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT 0 2693c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val) 2694c28c82e9SRob Clark { 2695c28c82e9SRob Clark return ((val >> 5) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK; 2696c28c82e9SRob Clark } 2697c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_BINH__MASK 0x00007f00 2698c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT 8 2699c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val) 2700c28c82e9SRob Clark { 2701c28c82e9SRob Clark return ((val >> 4) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK; 2702c28c82e9SRob Clark } 270357cfe41cSRob Clark #define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000 270457cfe41cSRob Clark #define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT 18 270557cfe41cSRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val) 2706c28c82e9SRob Clark { 270757cfe41cSRob Clark return ((val) << A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK; 2708c28c82e9SRob Clark } 270957cfe41cSRob Clark #define A6XX_GRAS_BIN_CONTROL_FORCE_LRZ_WRITE_DIS 0x00200000 271057cfe41cSRob Clark #define A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK 0x00c00000 271157cfe41cSRob Clark #define A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT 22 271257cfe41cSRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val) 2713c28c82e9SRob Clark { 271457cfe41cSRob Clark return ((val) << A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK; 2715c28c82e9SRob Clark } 271657cfe41cSRob Clark #define A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK 0x07000000 271757cfe41cSRob Clark #define A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT 24 271857cfe41cSRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val) 2719c28c82e9SRob Clark { 272057cfe41cSRob Clark return ((val) << A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK; 272157cfe41cSRob Clark } 272257cfe41cSRob Clark #define A6XX_GRAS_BIN_CONTROL_UNK27__MASK 0x08000000 272357cfe41cSRob Clark #define A6XX_GRAS_BIN_CONTROL_UNK27__SHIFT 27 272457cfe41cSRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK27(uint32_t val) 272557cfe41cSRob Clark { 272657cfe41cSRob Clark return ((val) << A6XX_GRAS_BIN_CONTROL_UNK27__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK27__MASK; 2727c28c82e9SRob Clark } 2728c28c82e9SRob Clark 27292d756322SRob Clark #define REG_A6XX_GRAS_RAS_MSAA_CNTL 0x000080a2 27302d756322SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 27312d756322SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 27322d756322SRob Clark static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 27332d756322SRob Clark { 27342d756322SRob Clark return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK; 27352d756322SRob Clark } 2736c28c82e9SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK 0x00000004 2737c28c82e9SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT 2 2738c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK2(uint32_t val) 2739c28c82e9SRob Clark { 2740c28c82e9SRob Clark return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK; 2741c28c82e9SRob Clark } 2742c28c82e9SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK 0x00000008 2743c28c82e9SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT 3 2744c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK3(uint32_t val) 2745c28c82e9SRob Clark { 2746c28c82e9SRob Clark return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK; 2747c28c82e9SRob Clark } 27482d756322SRob Clark 27492d756322SRob Clark #define REG_A6XX_GRAS_DEST_MSAA_CNTL 0x000080a3 27502d756322SRob Clark #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 27512d756322SRob Clark #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 27522d756322SRob Clark static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 27532d756322SRob Clark { 27542d756322SRob Clark return ((val) << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK; 27552d756322SRob Clark } 27562d756322SRob Clark #define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 27572d756322SRob Clark 2758c28c82e9SRob Clark #define REG_A6XX_GRAS_SAMPLE_CONFIG 0x000080a4 2759c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_CONFIG_UNK0 0x00000001 2760c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002 27612d756322SRob Clark 2762c28c82e9SRob Clark #define REG_A6XX_GRAS_SAMPLE_LOCATION_0 0x000080a5 2763c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f 2764c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 2765c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) 2766c28c82e9SRob Clark { 2767c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; 2768c28c82e9SRob Clark } 2769c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 2770c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 2771c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) 2772c28c82e9SRob Clark { 2773c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; 2774c28c82e9SRob Clark } 2775c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 2776c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 2777c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) 2778c28c82e9SRob Clark { 2779c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; 2780c28c82e9SRob Clark } 2781c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 2782c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 2783c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) 2784c28c82e9SRob Clark { 2785c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; 2786c28c82e9SRob Clark } 2787c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 2788c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 2789c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) 2790c28c82e9SRob Clark { 2791c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; 2792c28c82e9SRob Clark } 2793c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 2794c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 2795c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) 2796c28c82e9SRob Clark { 2797c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; 2798c28c82e9SRob Clark } 2799c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 2800c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 2801c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) 2802c28c82e9SRob Clark { 2803c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; 2804c28c82e9SRob Clark } 2805c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 2806c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 2807c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) 2808c28c82e9SRob Clark { 2809c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; 2810c28c82e9SRob Clark } 28112d756322SRob Clark 2812c28c82e9SRob Clark #define REG_A6XX_GRAS_SAMPLE_LOCATION_1 0x000080a6 2813c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f 2814c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 2815c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) 2816c28c82e9SRob Clark { 2817c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; 2818c28c82e9SRob Clark } 2819c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 2820c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 2821c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) 2822c28c82e9SRob Clark { 2823c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; 2824c28c82e9SRob Clark } 2825c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 2826c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 2827c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) 2828c28c82e9SRob Clark { 2829c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; 2830c28c82e9SRob Clark } 2831c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 2832c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 2833c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) 2834c28c82e9SRob Clark { 2835c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; 2836c28c82e9SRob Clark } 2837c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 2838c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 2839c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) 2840c28c82e9SRob Clark { 2841c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; 2842c28c82e9SRob Clark } 2843c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 2844c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 2845c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) 2846c28c82e9SRob Clark { 2847c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; 2848c28c82e9SRob Clark } 2849c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 2850c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 2851c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) 2852c28c82e9SRob Clark { 2853c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; 2854c28c82e9SRob Clark } 2855c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 2856c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 2857c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) 2858c28c82e9SRob Clark { 2859c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; 2860c28c82e9SRob Clark } 28612d756322SRob Clark 28622d756322SRob Clark #define REG_A6XX_GRAS_UNKNOWN_80AF 0x000080af 28632d756322SRob Clark 2864c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR(uint32_t i0) { return 0x000080b0 + 0x2*i0; } 2865c28c82e9SRob Clark 2866c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0) { return 0x000080b0 + 0x2*i0; } 2867c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x0000ffff 2868c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 2869c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 28702d756322SRob Clark { 2871c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; 28722d756322SRob Clark } 2873c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0xffff0000 2874c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 2875c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 28762d756322SRob Clark { 2877c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; 28782d756322SRob Clark } 28792d756322SRob Clark 2880c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR(uint32_t i0) { return 0x000080b1 + 0x2*i0; } 2881c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x0000ffff 2882c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 2883c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 28842d756322SRob Clark { 2885c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; 28862d756322SRob Clark } 2887c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0xffff0000 2888c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 2889c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 28902d756322SRob Clark { 2891c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; 28922d756322SRob Clark } 28932d756322SRob Clark 2894c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(uint32_t i0) { return 0x000080d0 + 0x2*i0; } 2895c28c82e9SRob Clark 2896c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0) { return 0x000080d0 + 0x2*i0; } 2897c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK 0x0000ffff 2898c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT 0 2899c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(uint32_t val) 29002d756322SRob Clark { 2901c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK; 29022d756322SRob Clark } 2903c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK 0xffff0000 2904c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT 16 2905c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(uint32_t val) 29062d756322SRob Clark { 2907c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK; 29082d756322SRob Clark } 29092d756322SRob Clark 2910c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(uint32_t i0) { return 0x000080d1 + 0x2*i0; } 2911c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK 0x0000ffff 2912c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT 0 2913c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X(uint32_t val) 29142d756322SRob Clark { 2915c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK; 29162d756322SRob Clark } 2917c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK 0xffff0000 2918c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT 16 2919c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y(uint32_t val) 29202d756322SRob Clark { 2921c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK; 29222d756322SRob Clark } 29232d756322SRob Clark 29242d756322SRob Clark #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL 0x000080f0 2925c28c82e9SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00003fff 29262d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 29272d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 29282d756322SRob Clark { 29292d756322SRob Clark return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 29302d756322SRob Clark } 2931c28c82e9SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x3fff0000 29322d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 29332d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 29342d756322SRob Clark { 29352d756322SRob Clark return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 29362d756322SRob Clark } 29372d756322SRob Clark 29382d756322SRob Clark #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR 0x000080f1 2939c28c82e9SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00003fff 29402d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 29412d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 29422d756322SRob Clark { 29432d756322SRob Clark return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 29442d756322SRob Clark } 2945c28c82e9SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x3fff0000 29462d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 29472d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 29482d756322SRob Clark { 29492d756322SRob Clark return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 29502d756322SRob Clark } 29512d756322SRob Clark 29522d756322SRob Clark #define REG_A6XX_GRAS_LRZ_CNTL 0x00008100 29532d756322SRob Clark #define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001 29542d756322SRob Clark #define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002 29552d756322SRob Clark #define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004 2956c28c82e9SRob Clark #define A6XX_GRAS_LRZ_CNTL_FC_ENABLE 0x00000008 2957c28c82e9SRob Clark #define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE 0x00000010 2958cc4c26d4SRob Clark #define A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE 0x00000020 2959*f73343faSRob Clark #define A6XX_GRAS_LRZ_CNTL_DIR__MASK 0x000000c0 2960*f73343faSRob Clark #define A6XX_GRAS_LRZ_CNTL_DIR__SHIFT 6 2961*f73343faSRob Clark static inline uint32_t A6XX_GRAS_LRZ_CNTL_DIR(enum a6xx_lrz_dir_status val) 2962c28c82e9SRob Clark { 2963*f73343faSRob Clark return ((val) << A6XX_GRAS_LRZ_CNTL_DIR__SHIFT) & A6XX_GRAS_LRZ_CNTL_DIR__MASK; 2964c28c82e9SRob Clark } 2965*f73343faSRob Clark #define A6XX_GRAS_LRZ_CNTL_DIR_WRITE 0x00000100 2966*f73343faSRob Clark #define A6XX_GRAS_LRZ_CNTL_DISABLE_ON_WRONG_DIR 0x00000200 29672d756322SRob Clark 296857cfe41cSRob Clark #define REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL 0x00008101 296957cfe41cSRob Clark #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_SAMPLEID 0x00000001 297057cfe41cSRob Clark #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK 0x00000006 297157cfe41cSRob Clark #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT 1 297257cfe41cSRob Clark static inline uint32_t A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val) 29732d756322SRob Clark { 297457cfe41cSRob Clark return ((val) << A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK; 297557cfe41cSRob Clark } 297657cfe41cSRob Clark 297757cfe41cSRob Clark #define REG_A6XX_GRAS_LRZ_MRT_BUF_INFO_0 0x00008102 297857cfe41cSRob Clark #define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK 0x000000ff 297957cfe41cSRob Clark #define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT 0 298057cfe41cSRob Clark static inline uint32_t A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT(enum a6xx_format val) 298157cfe41cSRob Clark { 298257cfe41cSRob Clark return ((val) << A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT) & A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK; 29832d756322SRob Clark } 29842d756322SRob Clark 2985c28c82e9SRob Clark #define REG_A6XX_GRAS_LRZ_BUFFER_BASE 0x00008103 2986c28c82e9SRob Clark #define A6XX_GRAS_LRZ_BUFFER_BASE__MASK 0xffffffff 2987c28c82e9SRob Clark #define A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT 0 2988c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_LRZ_BUFFER_BASE(uint32_t val) 2989c28c82e9SRob Clark { 2990c28c82e9SRob Clark return ((val) << A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_BUFFER_BASE__MASK; 2991c28c82e9SRob Clark } 2992c28c82e9SRob Clark 29932d756322SRob Clark #define REG_A6XX_GRAS_LRZ_BUFFER_PITCH 0x00008105 2994c28c82e9SRob Clark #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK 0x000000ff 29952d756322SRob Clark #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT 0 29962d756322SRob Clark static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val) 29972d756322SRob Clark { 29982d756322SRob Clark return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK; 29992d756322SRob Clark } 3000c28c82e9SRob Clark #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffffc00 3001c28c82e9SRob Clark #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT 10 30022d756322SRob Clark static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 30032d756322SRob Clark { 3004c28c82e9SRob Clark return ((val >> 4) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK; 30052d756322SRob Clark } 30062d756322SRob Clark 3007c28c82e9SRob Clark #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE 0x00008106 3008c28c82e9SRob Clark #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK 0xffffffff 3009c28c82e9SRob Clark #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT 0 3010c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(uint32_t val) 3011c28c82e9SRob Clark { 3012c28c82e9SRob Clark return ((val) << A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK; 3013c28c82e9SRob Clark } 3014c28c82e9SRob Clark 3015c28c82e9SRob Clark #define REG_A6XX_GRAS_SAMPLE_CNTL 0x00008109 3016c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001 3017c28c82e9SRob Clark 3018*f73343faSRob Clark #define REG_A6XX_GRAS_LRZ_DEPTH_VIEW 0x0000810a 3019*f73343faSRob Clark #define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__MASK 0x000007ff 3020*f73343faSRob Clark #define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__SHIFT 0 3021*f73343faSRob Clark static inline uint32_t A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER(uint32_t val) 3022c28c82e9SRob Clark { 3023*f73343faSRob Clark return ((val) << A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__MASK; 3024c28c82e9SRob Clark } 3025*f73343faSRob Clark #define A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__MASK 0x07ff0000 3026*f73343faSRob Clark #define A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__SHIFT 16 3027*f73343faSRob Clark static inline uint32_t A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT(uint32_t val) 3028c28c82e9SRob Clark { 3029*f73343faSRob Clark return ((val) << A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__MASK; 3030c28c82e9SRob Clark } 3031*f73343faSRob Clark #define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__MASK 0xf0000000 3032*f73343faSRob Clark #define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__SHIFT 28 3033*f73343faSRob Clark static inline uint32_t A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL(uint32_t val) 3034c28c82e9SRob Clark { 3035*f73343faSRob Clark return ((val) << A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__MASK; 3036c28c82e9SRob Clark } 3037a69c5ed2SRob Clark 3038a69c5ed2SRob Clark #define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110 3039a69c5ed2SRob Clark 30402d756322SRob Clark #define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400 3041c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK 0x00000007 3042c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT 0 3043c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val) 3044c28c82e9SRob Clark { 3045c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK; 3046c28c82e9SRob Clark } 304757cfe41cSRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_OVERWRITEEN 0x00000008 304857cfe41cSRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK 0x00000070 304957cfe41cSRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT 4 305057cfe41cSRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK4(uint32_t val) 3051c28c82e9SRob Clark { 305257cfe41cSRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK; 3053c28c82e9SRob Clark } 3054c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR 0x00000080 3055ccdf7e28SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00 3056ccdf7e28SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8 3057c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val) 3058ccdf7e28SRob Clark { 3059ccdf7e28SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK; 3060ccdf7e28SRob Clark } 3061ccdf7e28SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR 0x00010000 3062c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK 0x00060000 3063c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT 17 3064c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK17(uint32_t val) 3065c28c82e9SRob Clark { 3066c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK; 3067c28c82e9SRob Clark } 3068c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_D24S8 0x00080000 3069c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK 0x00f00000 3070c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT 20 3071c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_MASK(uint32_t val) 3072c28c82e9SRob Clark { 3073c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK; 3074c28c82e9SRob Clark } 3075c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK 0x1f000000 3076c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT 24 3077c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val) 3078c28c82e9SRob Clark { 3079c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK; 3080c28c82e9SRob Clark } 308157cfe41cSRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK 0x20000000 308257cfe41cSRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT 29 308357cfe41cSRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val) 3084c28c82e9SRob Clark { 308557cfe41cSRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK; 3086c28c82e9SRob Clark } 30872d756322SRob Clark 30882d756322SRob Clark #define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401 30892d756322SRob Clark 30902d756322SRob Clark #define REG_A6XX_GRAS_2D_SRC_BR_X 0x00008402 30912d756322SRob Clark 30922d756322SRob Clark #define REG_A6XX_GRAS_2D_SRC_TL_Y 0x00008403 30932d756322SRob Clark 30942d756322SRob Clark #define REG_A6XX_GRAS_2D_SRC_BR_Y 0x00008404 30952d756322SRob Clark 30962d756322SRob Clark #define REG_A6XX_GRAS_2D_DST_TL 0x00008405 3097c28c82e9SRob Clark #define A6XX_GRAS_2D_DST_TL_X__MASK 0x00003fff 30982d756322SRob Clark #define A6XX_GRAS_2D_DST_TL_X__SHIFT 0 30992d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val) 31002d756322SRob Clark { 31012d756322SRob Clark return ((val) << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK; 31022d756322SRob Clark } 3103c28c82e9SRob Clark #define A6XX_GRAS_2D_DST_TL_Y__MASK 0x3fff0000 31042d756322SRob Clark #define A6XX_GRAS_2D_DST_TL_Y__SHIFT 16 31052d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val) 31062d756322SRob Clark { 31072d756322SRob Clark return ((val) << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK; 31082d756322SRob Clark } 31092d756322SRob Clark 31102d756322SRob Clark #define REG_A6XX_GRAS_2D_DST_BR 0x00008406 3111c28c82e9SRob Clark #define A6XX_GRAS_2D_DST_BR_X__MASK 0x00003fff 31122d756322SRob Clark #define A6XX_GRAS_2D_DST_BR_X__SHIFT 0 31132d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val) 31142d756322SRob Clark { 31152d756322SRob Clark return ((val) << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK; 31162d756322SRob Clark } 3117c28c82e9SRob Clark #define A6XX_GRAS_2D_DST_BR_Y__MASK 0x3fff0000 31182d756322SRob Clark #define A6XX_GRAS_2D_DST_BR_Y__SHIFT 16 31192d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val) 31202d756322SRob Clark { 31212d756322SRob Clark return ((val) << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK; 31222d756322SRob Clark } 31232d756322SRob Clark 3124c28c82e9SRob Clark #define REG_A6XX_GRAS_2D_UNKNOWN_8407 0x00008407 3125c28c82e9SRob Clark 3126c28c82e9SRob Clark #define REG_A6XX_GRAS_2D_UNKNOWN_8408 0x00008408 3127c28c82e9SRob Clark 3128c28c82e9SRob Clark #define REG_A6XX_GRAS_2D_UNKNOWN_8409 0x00008409 3129c28c82e9SRob Clark 3130c28c82e9SRob Clark #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_1 0x0000840a 3131c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK 0x00003fff 3132c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT 0 3133c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_X(uint32_t val) 31342d756322SRob Clark { 3135c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK; 31362d756322SRob Clark } 3137c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK 0x3fff0000 3138c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT 16 3139c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(uint32_t val) 31402d756322SRob Clark { 3141c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK; 31422d756322SRob Clark } 31432d756322SRob Clark 3144c28c82e9SRob Clark #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_2 0x0000840b 3145c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK 0x00003fff 3146c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT 0 3147c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_X(uint32_t val) 31482d756322SRob Clark { 3149c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK; 31502d756322SRob Clark } 3151c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK 0x3fff0000 3152c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT 16 3153c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val) 31542d756322SRob Clark { 3155c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK; 31562d756322SRob Clark } 31572d756322SRob Clark 315857cfe41cSRob Clark #define REG_A6XX_GRAS_DBG_ECO_CNTL 0x00008600 315957cfe41cSRob Clark #define A6XX_GRAS_DBG_ECO_CNTL_UNK7 0x00000080 316057cfe41cSRob Clark #define A6XX_GRAS_DBG_ECO_CNTL_LRZCACHELOCKDIS 0x00000800 31612d756322SRob Clark 3162c28c82e9SRob Clark #define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601 3163c28c82e9SRob Clark 3164*f73343faSRob Clark #define REG_A7XX_GRAS_NC_MODE_CNTL 0x00008602 3165*f73343faSRob Clark 3166cc4c26d4SRob Clark static inline uint32_t REG_A6XX_GRAS_PERFCTR_TSE_SEL(uint32_t i0) { return 0x00008610 + 0x1*i0; } 3167c28c82e9SRob Clark 3168cc4c26d4SRob Clark static inline uint32_t REG_A6XX_GRAS_PERFCTR_RAS_SEL(uint32_t i0) { return 0x00008614 + 0x1*i0; } 3169c28c82e9SRob Clark 3170cc4c26d4SRob Clark static inline uint32_t REG_A6XX_GRAS_PERFCTR_LRZ_SEL(uint32_t i0) { return 0x00008618 + 0x1*i0; } 3171c28c82e9SRob Clark 3172a69c5ed2SRob Clark #define REG_A6XX_RB_BIN_CONTROL 0x00008800 3173c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f 3174a69c5ed2SRob Clark #define A6XX_RB_BIN_CONTROL_BINW__SHIFT 0 3175a69c5ed2SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val) 3176a69c5ed2SRob Clark { 3177a69c5ed2SRob Clark return ((val >> 5) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK; 3178a69c5ed2SRob Clark } 3179c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL_BINH__MASK 0x00007f00 3180a69c5ed2SRob Clark #define A6XX_RB_BIN_CONTROL_BINH__SHIFT 8 3181a69c5ed2SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val) 3182a69c5ed2SRob Clark { 3183a69c5ed2SRob Clark return ((val >> 4) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK; 3184a69c5ed2SRob Clark } 318557cfe41cSRob Clark #define A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000 318657cfe41cSRob Clark #define A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT 18 318757cfe41cSRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val) 3188c28c82e9SRob Clark { 318957cfe41cSRob Clark return ((val) << A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK; 3190c28c82e9SRob Clark } 319157cfe41cSRob Clark #define A6XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS 0x00200000 319257cfe41cSRob Clark #define A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK 0x00c00000 319357cfe41cSRob Clark #define A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT 22 319457cfe41cSRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val) 3195c28c82e9SRob Clark { 319657cfe41cSRob Clark return ((val) << A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK; 3197c28c82e9SRob Clark } 319857cfe41cSRob Clark #define A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK 0x07000000 319957cfe41cSRob Clark #define A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT 24 320057cfe41cSRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val) 3201c28c82e9SRob Clark { 320257cfe41cSRob Clark return ((val) << A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK; 3203c28c82e9SRob Clark } 3204a69c5ed2SRob Clark 3205a69c5ed2SRob Clark #define REG_A6XX_RB_RENDER_CNTL 0x00008801 320657cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK 0x00000038 320757cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT 3 320857cfe41cSRob Clark static inline uint32_t A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE(uint32_t val) 3209c28c82e9SRob Clark { 321057cfe41cSRob Clark return ((val) << A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK; 3211c28c82e9SRob Clark } 321257cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_EARLYVIZOUTEN 0x00000040 3213a69c5ed2SRob Clark #define A6XX_RB_RENDER_CNTL_BINNING 0x00000080 321457cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_UNK8__MASK 0x00000700 3215c28c82e9SRob Clark #define A6XX_RB_RENDER_CNTL_UNK8__SHIFT 8 3216c28c82e9SRob Clark static inline uint32_t A6XX_RB_RENDER_CNTL_UNK8(uint32_t val) 3217c28c82e9SRob Clark { 3218c28c82e9SRob Clark return ((val) << A6XX_RB_RENDER_CNTL_UNK8__SHIFT) & A6XX_RB_RENDER_CNTL_UNK8__MASK; 3219c28c82e9SRob Clark } 322057cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK 0x00000100 322157cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT 8 322257cfe41cSRob Clark static inline uint32_t A6XX_RB_RENDER_CNTL_RASTER_MODE(enum a6xx_raster_mode val) 322357cfe41cSRob Clark { 322457cfe41cSRob Clark return ((val) << A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK; 322557cfe41cSRob Clark } 322657cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK 0x00000600 322757cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT 9 322857cfe41cSRob Clark static inline uint32_t A6XX_RB_RENDER_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val) 322957cfe41cSRob Clark { 323057cfe41cSRob Clark return ((val) << A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK; 323157cfe41cSRob Clark } 323257cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_CONSERVATIVERASEN 0x00000800 323357cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN 0x00001000 3234a69c5ed2SRob Clark #define A6XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000 3235a69c5ed2SRob Clark #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000 3236a69c5ed2SRob Clark #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16 3237a69c5ed2SRob Clark static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val) 3238a69c5ed2SRob Clark { 3239a69c5ed2SRob Clark return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK; 3240a69c5ed2SRob Clark } 3241a69c5ed2SRob Clark 32422d756322SRob Clark #define REG_A6XX_RB_RAS_MSAA_CNTL 0x00008802 32432d756322SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 32442d756322SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 32452d756322SRob Clark static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 32462d756322SRob Clark { 32472d756322SRob Clark return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK; 32482d756322SRob Clark } 3249c28c82e9SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK 0x00000004 3250c28c82e9SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT 2 3251c28c82e9SRob Clark static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK2(uint32_t val) 3252c28c82e9SRob Clark { 3253c28c82e9SRob Clark return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK; 3254c28c82e9SRob Clark } 3255c28c82e9SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK 0x00000008 3256c28c82e9SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT 3 3257c28c82e9SRob Clark static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK3(uint32_t val) 3258c28c82e9SRob Clark { 3259c28c82e9SRob Clark return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK; 3260c28c82e9SRob Clark } 32612d756322SRob Clark 32622d756322SRob Clark #define REG_A6XX_RB_DEST_MSAA_CNTL 0x00008803 32632d756322SRob Clark #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 32642d756322SRob Clark #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 32652d756322SRob Clark static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 32662d756322SRob Clark { 32672d756322SRob Clark return ((val) << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK; 32682d756322SRob Clark } 32692d756322SRob Clark #define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 32702d756322SRob Clark 3271c28c82e9SRob Clark #define REG_A6XX_RB_SAMPLE_CONFIG 0x00008804 3272c28c82e9SRob Clark #define A6XX_RB_SAMPLE_CONFIG_UNK0 0x00000001 3273c28c82e9SRob Clark #define A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002 32742d756322SRob Clark 3275c28c82e9SRob Clark #define REG_A6XX_RB_SAMPLE_LOCATION_0 0x00008805 3276c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f 3277c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 3278c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) 3279c28c82e9SRob Clark { 3280c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; 3281c28c82e9SRob Clark } 3282c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 3283c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 3284c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) 3285c28c82e9SRob Clark { 3286c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; 3287c28c82e9SRob Clark } 3288c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 3289c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 3290c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) 3291c28c82e9SRob Clark { 3292c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; 3293c28c82e9SRob Clark } 3294c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 3295c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 3296c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) 3297c28c82e9SRob Clark { 3298c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; 3299c28c82e9SRob Clark } 3300c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 3301c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 3302c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) 3303c28c82e9SRob Clark { 3304c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; 3305c28c82e9SRob Clark } 3306c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 3307c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 3308c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) 3309c28c82e9SRob Clark { 3310c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; 3311c28c82e9SRob Clark } 3312c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 3313c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 3314c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) 3315c28c82e9SRob Clark { 3316c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; 3317c28c82e9SRob Clark } 3318c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 3319c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 3320c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) 3321c28c82e9SRob Clark { 3322c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; 3323c28c82e9SRob Clark } 33242d756322SRob Clark 3325c28c82e9SRob Clark #define REG_A6XX_RB_SAMPLE_LOCATION_1 0x00008806 3326c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f 3327c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 3328c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) 3329c28c82e9SRob Clark { 3330c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; 3331c28c82e9SRob Clark } 3332c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 3333c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 3334c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) 3335c28c82e9SRob Clark { 3336c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; 3337c28c82e9SRob Clark } 3338c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 3339c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 3340c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) 3341c28c82e9SRob Clark { 3342c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; 3343c28c82e9SRob Clark } 3344c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 3345c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 3346c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) 3347c28c82e9SRob Clark { 3348c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; 3349c28c82e9SRob Clark } 3350c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 3351c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 3352c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) 3353c28c82e9SRob Clark { 3354c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; 3355c28c82e9SRob Clark } 3356c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 3357c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 3358c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) 3359c28c82e9SRob Clark { 3360c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; 3361c28c82e9SRob Clark } 3362c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 3363c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 3364c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) 3365c28c82e9SRob Clark { 3366c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; 3367c28c82e9SRob Clark } 3368c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 3369c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 3370c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) 3371c28c82e9SRob Clark { 3372c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; 3373c28c82e9SRob Clark } 33742d756322SRob Clark 33752d756322SRob Clark #define REG_A6XX_RB_RENDER_CONTROL0 0x00008809 3376c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL 0x00000001 3377c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID 0x00000002 3378c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE 0x00000004 337957cfe41cSRob Clark #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL 0x00000008 338057cfe41cSRob Clark #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID 0x00000010 338157cfe41cSRob Clark #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE 0x00000020 3382c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK 0x000003c0 3383c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT 6 3384c28c82e9SRob Clark static inline uint32_t A6XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val) 3385c28c82e9SRob Clark { 3386c28c82e9SRob Clark return ((val) << A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK; 3387c28c82e9SRob Clark } 33882d756322SRob Clark #define A6XX_RB_RENDER_CONTROL0_UNK10 0x00000400 33892d756322SRob Clark 33902d756322SRob Clark #define REG_A6XX_RB_RENDER_CONTROL1 0x0000880a 33912d756322SRob Clark #define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001 3392*f73343faSRob Clark #define A6XX_RB_RENDER_CONTROL1_POSTDEPTHCOVERAGE 0x00000002 3393c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL1_FACENESS 0x00000004 33942d756322SRob Clark #define A6XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000008 339557cfe41cSRob Clark #define A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK 0x00000030 339657cfe41cSRob Clark #define A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT 4 339757cfe41cSRob Clark static inline uint32_t A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val) 339857cfe41cSRob Clark { 339957cfe41cSRob Clark return ((val) << A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK; 340057cfe41cSRob Clark } 3401*f73343faSRob Clark #define A6XX_RB_RENDER_CONTROL1_CENTERRHW 0x00000040 340257cfe41cSRob Clark #define A6XX_RB_RENDER_CONTROL1_LINELENGTHEN 0x00000080 340357cfe41cSRob Clark #define A6XX_RB_RENDER_CONTROL1_FOVEATION 0x00000100 34042d756322SRob Clark 34052d756322SRob Clark #define REG_A6XX_RB_FS_OUTPUT_CNTL0 0x0000880b 3406c28c82e9SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001 34072d756322SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z 0x00000002 3408c28c82e9SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK 0x00000004 3409c28c82e9SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF 0x00000008 34102d756322SRob Clark 34112d756322SRob Clark #define REG_A6XX_RB_FS_OUTPUT_CNTL1 0x0000880c 34122d756322SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f 34132d756322SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT 0 34142d756322SRob Clark static inline uint32_t A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val) 34152d756322SRob Clark { 34162d756322SRob Clark return ((val) << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK; 34172d756322SRob Clark } 34182d756322SRob Clark 34192d756322SRob Clark #define REG_A6XX_RB_RENDER_COMPONENTS 0x0000880d 34202d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f 34212d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0 34222d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) 34232d756322SRob Clark { 34242d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK; 34252d756322SRob Clark } 34262d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0 34272d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4 34282d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) 34292d756322SRob Clark { 34302d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK; 34312d756322SRob Clark } 34322d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00 34332d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8 34342d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) 34352d756322SRob Clark { 34362d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK; 34372d756322SRob Clark } 34382d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000 34392d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12 34402d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) 34412d756322SRob Clark { 34422d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK; 34432d756322SRob Clark } 34442d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000 34452d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16 34462d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) 34472d756322SRob Clark { 34482d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK; 34492d756322SRob Clark } 34502d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000 34512d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20 34522d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) 34532d756322SRob Clark { 34542d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK; 34552d756322SRob Clark } 34562d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000 34572d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24 34582d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) 34592d756322SRob Clark { 34602d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK; 34612d756322SRob Clark } 34622d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000 34632d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28 34642d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) 34652d756322SRob Clark { 34662d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK; 34672d756322SRob Clark } 34682d756322SRob Clark 34692d756322SRob Clark #define REG_A6XX_RB_DITHER_CNTL 0x0000880e 34702d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK 0x00000003 34712d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT 0 34722d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val) 34732d756322SRob Clark { 34742d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK; 34752d756322SRob Clark } 34762d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK 0x0000000c 34772d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT 2 34782d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val) 34792d756322SRob Clark { 34802d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK; 34812d756322SRob Clark } 34822d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK 0x00000030 34832d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT 4 34842d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val) 34852d756322SRob Clark { 34862d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK; 34872d756322SRob Clark } 34882d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK 0x000000c0 34892d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT 6 34902d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val) 34912d756322SRob Clark { 34922d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK; 34932d756322SRob Clark } 34942d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK 0x00000300 34952d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT 8 34962d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val) 34972d756322SRob Clark { 34982d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK; 34992d756322SRob Clark } 35002d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK 0x00000c00 35012d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT 10 35022d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val) 35032d756322SRob Clark { 35042d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK; 35052d756322SRob Clark } 35062d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK 0x00001000 35072d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT 12 35082d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val) 35092d756322SRob Clark { 35102d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK; 35112d756322SRob Clark } 35122d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK 0x0000c000 35132d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT 14 35142d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val) 35152d756322SRob Clark { 35162d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK; 35172d756322SRob Clark } 35182d756322SRob Clark 35192d756322SRob Clark #define REG_A6XX_RB_SRGB_CNTL 0x0000880f 35202d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT0 0x00000001 35212d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT1 0x00000002 35222d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT2 0x00000004 35232d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT3 0x00000008 35242d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT4 0x00000010 35252d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT5 0x00000020 35262d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT6 0x00000040 35272d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT7 0x00000080 35282d756322SRob Clark 3529c28c82e9SRob Clark #define REG_A6XX_RB_SAMPLE_CNTL 0x00008810 3530c28c82e9SRob Clark #define A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001 3531a69c5ed2SRob Clark 3532a69c5ed2SRob Clark #define REG_A6XX_RB_UNKNOWN_8811 0x00008811 3533a69c5ed2SRob Clark 35342d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8818 0x00008818 35352d756322SRob Clark 35362d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8819 0x00008819 35372d756322SRob Clark 35382d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881A 0x0000881a 35392d756322SRob Clark 35402d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881B 0x0000881b 35412d756322SRob Clark 35422d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881C 0x0000881c 35432d756322SRob Clark 35442d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881D 0x0000881d 35452d756322SRob Clark 35462d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881E 0x0000881e 35472d756322SRob Clark 35482d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; } 35492d756322SRob Clark 35502d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; } 35512d756322SRob Clark #define A6XX_RB_MRT_CONTROL_BLEND 0x00000001 35522d756322SRob Clark #define A6XX_RB_MRT_CONTROL_BLEND2 0x00000002 35532d756322SRob Clark #define A6XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004 35542d756322SRob Clark #define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078 35552d756322SRob Clark #define A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3 35562d756322SRob Clark static inline uint32_t A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) 35572d756322SRob Clark { 35582d756322SRob Clark return ((val) << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK; 35592d756322SRob Clark } 35602d756322SRob Clark #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780 35612d756322SRob Clark #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7 35622d756322SRob Clark static inline uint32_t A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 35632d756322SRob Clark { 35642d756322SRob Clark return ((val) << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 35652d756322SRob Clark } 35662d756322SRob Clark 35672d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; } 35682d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 35692d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 35702d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 35712d756322SRob Clark { 35722d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 35732d756322SRob Clark } 35742d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 35752d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 35762d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 35772d756322SRob Clark { 35782d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 35792d756322SRob Clark } 35802d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 35812d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 35822d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 35832d756322SRob Clark { 35842d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 35852d756322SRob Clark } 35862d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 35872d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 35882d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 35892d756322SRob Clark { 35902d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 35912d756322SRob Clark } 35922d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 35932d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 35942d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 35952d756322SRob Clark { 35962d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 35972d756322SRob Clark } 35982d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 35992d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 36002d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 36012d756322SRob Clark { 36022d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 36032d756322SRob Clark } 36042d756322SRob Clark 36052d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; } 36062d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff 36072d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 3608c28c82e9SRob Clark static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val) 36092d756322SRob Clark { 36102d756322SRob Clark return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 36112d756322SRob Clark } 36122d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300 36132d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8 36142d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val) 36152d756322SRob Clark { 36162d756322SRob Clark return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 36172d756322SRob Clark } 3618c28c82e9SRob Clark #define A6XX_RB_MRT_BUF_INFO_UNK10__MASK 0x00000400 3619c28c82e9SRob Clark #define A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT 10 3620c28c82e9SRob Clark static inline uint32_t A6XX_RB_MRT_BUF_INFO_UNK10(uint32_t val) 3621c28c82e9SRob Clark { 3622c28c82e9SRob Clark return ((val) << A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT) & A6XX_RB_MRT_BUF_INFO_UNK10__MASK; 3623c28c82e9SRob Clark } 36242d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000 36252d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13 36262d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 36272d756322SRob Clark { 36282d756322SRob Clark return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 36292d756322SRob Clark } 36302d756322SRob Clark 36312d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; } 3632c28c82e9SRob Clark #define A6XX_RB_MRT_PITCH__MASK 0x0000ffff 36332d756322SRob Clark #define A6XX_RB_MRT_PITCH__SHIFT 0 36342d756322SRob Clark static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val) 36352d756322SRob Clark { 36362d756322SRob Clark return ((val >> 6) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK; 36372d756322SRob Clark } 36382d756322SRob Clark 36392d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; } 3640c28c82e9SRob Clark #define A6XX_RB_MRT_ARRAY_PITCH__MASK 0x1fffffff 36412d756322SRob Clark #define A6XX_RB_MRT_ARRAY_PITCH__SHIFT 0 36422d756322SRob Clark static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val) 36432d756322SRob Clark { 36442d756322SRob Clark return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK; 36452d756322SRob Clark } 36462d756322SRob Clark 3647c28c82e9SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; } 3648c28c82e9SRob Clark #define A6XX_RB_MRT_BASE__MASK 0xffffffff 3649c28c82e9SRob Clark #define A6XX_RB_MRT_BASE__SHIFT 0 3650c28c82e9SRob Clark static inline uint32_t A6XX_RB_MRT_BASE(uint32_t val) 3651c28c82e9SRob Clark { 3652c28c82e9SRob Clark return ((val) << A6XX_RB_MRT_BASE__SHIFT) & A6XX_RB_MRT_BASE__MASK; 3653c28c82e9SRob Clark } 3654c28c82e9SRob Clark 36552d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; } 3656c28c82e9SRob Clark #define A6XX_RB_MRT_BASE_GMEM__MASK 0xfffff000 3657c28c82e9SRob Clark #define A6XX_RB_MRT_BASE_GMEM__SHIFT 12 3658c28c82e9SRob Clark static inline uint32_t A6XX_RB_MRT_BASE_GMEM(uint32_t val) 3659c28c82e9SRob Clark { 3660c28c82e9SRob Clark return ((val >> 12) << A6XX_RB_MRT_BASE_GMEM__SHIFT) & A6XX_RB_MRT_BASE_GMEM__MASK; 3661c28c82e9SRob Clark } 36622d756322SRob Clark 36632d756322SRob Clark #define REG_A6XX_RB_BLEND_RED_F32 0x00008860 36642d756322SRob Clark #define A6XX_RB_BLEND_RED_F32__MASK 0xffffffff 36652d756322SRob Clark #define A6XX_RB_BLEND_RED_F32__SHIFT 0 36662d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_RED_F32(float val) 36672d756322SRob Clark { 36682d756322SRob Clark return ((fui(val)) << A6XX_RB_BLEND_RED_F32__SHIFT) & A6XX_RB_BLEND_RED_F32__MASK; 36692d756322SRob Clark } 36702d756322SRob Clark 36712d756322SRob Clark #define REG_A6XX_RB_BLEND_GREEN_F32 0x00008861 36722d756322SRob Clark #define A6XX_RB_BLEND_GREEN_F32__MASK 0xffffffff 36732d756322SRob Clark #define A6XX_RB_BLEND_GREEN_F32__SHIFT 0 36742d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_GREEN_F32(float val) 36752d756322SRob Clark { 36762d756322SRob Clark return ((fui(val)) << A6XX_RB_BLEND_GREEN_F32__SHIFT) & A6XX_RB_BLEND_GREEN_F32__MASK; 36772d756322SRob Clark } 36782d756322SRob Clark 36792d756322SRob Clark #define REG_A6XX_RB_BLEND_BLUE_F32 0x00008862 36802d756322SRob Clark #define A6XX_RB_BLEND_BLUE_F32__MASK 0xffffffff 36812d756322SRob Clark #define A6XX_RB_BLEND_BLUE_F32__SHIFT 0 36822d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_BLUE_F32(float val) 36832d756322SRob Clark { 36842d756322SRob Clark return ((fui(val)) << A6XX_RB_BLEND_BLUE_F32__SHIFT) & A6XX_RB_BLEND_BLUE_F32__MASK; 36852d756322SRob Clark } 36862d756322SRob Clark 36872d756322SRob Clark #define REG_A6XX_RB_BLEND_ALPHA_F32 0x00008863 36882d756322SRob Clark #define A6XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff 36892d756322SRob Clark #define A6XX_RB_BLEND_ALPHA_F32__SHIFT 0 36902d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_ALPHA_F32(float val) 36912d756322SRob Clark { 36922d756322SRob Clark return ((fui(val)) << A6XX_RB_BLEND_ALPHA_F32__SHIFT) & A6XX_RB_BLEND_ALPHA_F32__MASK; 36932d756322SRob Clark } 36942d756322SRob Clark 36952d756322SRob Clark #define REG_A6XX_RB_ALPHA_CONTROL 0x00008864 36962d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff 36972d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 36982d756322SRob Clark static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) 36992d756322SRob Clark { 37002d756322SRob Clark return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; 37012d756322SRob Clark } 37022d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 37032d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 37042d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 37052d756322SRob Clark static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 37062d756322SRob Clark { 37072d756322SRob Clark return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; 37082d756322SRob Clark } 37092d756322SRob Clark 37102d756322SRob Clark #define REG_A6XX_RB_BLEND_CNTL 0x00008865 37112d756322SRob Clark #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff 37122d756322SRob Clark #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 37132d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val) 37142d756322SRob Clark { 37152d756322SRob Clark return ((val) << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK; 37162d756322SRob Clark } 37172d756322SRob Clark #define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100 3718c28c82e9SRob Clark #define A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200 3719ccdf7e28SRob Clark #define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 3720c28c82e9SRob Clark #define A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE 0x00000800 37212d756322SRob Clark #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000 37222d756322SRob Clark #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16 37232d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val) 37242d756322SRob Clark { 37252d756322SRob Clark return ((val) << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK; 37262d756322SRob Clark } 37272d756322SRob Clark 3728a69c5ed2SRob Clark #define REG_A6XX_RB_DEPTH_PLANE_CNTL 0x00008870 3729c28c82e9SRob Clark #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003 3730c28c82e9SRob Clark #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0 3731c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val) 3732c28c82e9SRob Clark { 3733c28c82e9SRob Clark return ((val) << A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK; 3734c28c82e9SRob Clark } 3735a69c5ed2SRob Clark 37362d756322SRob Clark #define REG_A6XX_RB_DEPTH_CNTL 0x00008871 373757cfe41cSRob Clark #define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000001 37382d756322SRob Clark #define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002 37392d756322SRob Clark #define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c 37402d756322SRob Clark #define A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2 37412d756322SRob Clark static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) 37422d756322SRob Clark { 37432d756322SRob Clark return ((val) << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK; 37442d756322SRob Clark } 3745c28c82e9SRob Clark #define A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE 0x00000020 374657cfe41cSRob Clark #define A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE 0x00000040 3747c28c82e9SRob Clark #define A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE 0x00000080 37482d756322SRob Clark 37492d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_INFO 0x00008872 37502d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 37512d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 37522d756322SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) 37532d756322SRob Clark { 37542d756322SRob Clark return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; 37552d756322SRob Clark } 3756c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000018 3757c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT 3 3758c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val) 3759c28c82e9SRob Clark { 3760c28c82e9SRob Clark return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK; 3761c28c82e9SRob Clark } 37622d756322SRob Clark 37632d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_PITCH 0x00008873 3764c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_PITCH__MASK 0x00003fff 37652d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0 37662d756322SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) 37672d756322SRob Clark { 37682d756322SRob Clark return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK; 37692d756322SRob Clark } 37702d756322SRob Clark 37712d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x00008874 3772c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0x0fffffff 37732d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0 37742d756322SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) 37752d756322SRob Clark { 37762d756322SRob Clark return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; 37772d756322SRob Clark } 37782d756322SRob Clark 3779c28c82e9SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_BASE 0x00008875 3780c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_BASE__MASK 0xffffffff 3781c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_BASE__SHIFT 0 3782c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE(uint32_t val) 3783c28c82e9SRob Clark { 3784c28c82e9SRob Clark return ((val) << A6XX_RB_DEPTH_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE__MASK; 3785c28c82e9SRob Clark } 3786c28c82e9SRob Clark 37872d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM 0x00008877 3788c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK 0xfffff000 3789c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT 12 3790c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE_GMEM(uint32_t val) 3791c28c82e9SRob Clark { 3792c28c82e9SRob Clark return ((val >> 12) << A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK; 3793c28c82e9SRob Clark } 37942d756322SRob Clark 3795c28c82e9SRob Clark #define REG_A6XX_RB_Z_BOUNDS_MIN 0x00008878 3796c28c82e9SRob Clark #define A6XX_RB_Z_BOUNDS_MIN__MASK 0xffffffff 3797c28c82e9SRob Clark #define A6XX_RB_Z_BOUNDS_MIN__SHIFT 0 3798c28c82e9SRob Clark static inline uint32_t A6XX_RB_Z_BOUNDS_MIN(float val) 3799c28c82e9SRob Clark { 3800c28c82e9SRob Clark return ((fui(val)) << A6XX_RB_Z_BOUNDS_MIN__SHIFT) & A6XX_RB_Z_BOUNDS_MIN__MASK; 3801c28c82e9SRob Clark } 38022d756322SRob Clark 3803c28c82e9SRob Clark #define REG_A6XX_RB_Z_BOUNDS_MAX 0x00008879 3804c28c82e9SRob Clark #define A6XX_RB_Z_BOUNDS_MAX__MASK 0xffffffff 3805c28c82e9SRob Clark #define A6XX_RB_Z_BOUNDS_MAX__SHIFT 0 3806c28c82e9SRob Clark static inline uint32_t A6XX_RB_Z_BOUNDS_MAX(float val) 3807c28c82e9SRob Clark { 3808c28c82e9SRob Clark return ((fui(val)) << A6XX_RB_Z_BOUNDS_MAX__SHIFT) & A6XX_RB_Z_BOUNDS_MAX__MASK; 3809c28c82e9SRob Clark } 38102d756322SRob Clark 38112d756322SRob Clark #define REG_A6XX_RB_STENCIL_CONTROL 0x00008880 38122d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 38132d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 38142d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 38152d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 38162d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 38172d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 38182d756322SRob Clark { 38192d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC__MASK; 38202d756322SRob Clark } 38212d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 38222d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 38232d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 38242d756322SRob Clark { 38252d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL__MASK; 38262d756322SRob Clark } 38272d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 38282d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 38292d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 38302d756322SRob Clark { 38312d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK; 38322d756322SRob Clark } 38332d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 38342d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 38352d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 38362d756322SRob Clark { 38372d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 38382d756322SRob Clark } 38392d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 38402d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 38412d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 38422d756322SRob Clark { 38432d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 38442d756322SRob Clark } 38452d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 38462d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 38472d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 38482d756322SRob Clark { 38492d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 38502d756322SRob Clark } 38512d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 38522d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 38532d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 38542d756322SRob Clark { 38552d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 38562d756322SRob Clark } 38572d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 38582d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 38592d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 38602d756322SRob Clark { 38612d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 38622d756322SRob Clark } 38632d756322SRob Clark 38642d756322SRob Clark #define REG_A6XX_RB_STENCIL_INFO 0x00008881 38652d756322SRob Clark #define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 3866c28c82e9SRob Clark #define A6XX_RB_STENCIL_INFO_UNK1 0x00000002 38672d756322SRob Clark 38682d756322SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_PITCH 0x00008882 3869c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_PITCH__MASK 0x00000fff 38702d756322SRob Clark #define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT 0 38712d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val) 38722d756322SRob Clark { 38732d756322SRob Clark return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK; 38742d756322SRob Clark } 38752d756322SRob Clark 38762d756322SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH 0x00008883 3877c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK 0x00ffffff 38782d756322SRob Clark #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT 0 38792d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val) 38802d756322SRob Clark { 38812d756322SRob Clark return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK; 38822d756322SRob Clark } 38832d756322SRob Clark 3884c28c82e9SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_BASE 0x00008884 3885c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_BASE__MASK 0xffffffff 3886c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_BASE__SHIFT 0 3887c28c82e9SRob Clark static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE(uint32_t val) 3888c28c82e9SRob Clark { 3889c28c82e9SRob Clark return ((val) << A6XX_RB_STENCIL_BUFFER_BASE__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE__MASK; 3890c28c82e9SRob Clark } 3891c28c82e9SRob Clark 38922d756322SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM 0x00008886 3893c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK 0xfffff000 3894c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT 12 3895c28c82e9SRob Clark static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE_GMEM(uint32_t val) 3896c28c82e9SRob Clark { 3897c28c82e9SRob Clark return ((val >> 12) << A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK; 3898c28c82e9SRob Clark } 38992d756322SRob Clark 39002d756322SRob Clark #define REG_A6XX_RB_STENCILREF 0x00008887 39012d756322SRob Clark #define A6XX_RB_STENCILREF_REF__MASK 0x000000ff 39022d756322SRob Clark #define A6XX_RB_STENCILREF_REF__SHIFT 0 39032d756322SRob Clark static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val) 39042d756322SRob Clark { 39052d756322SRob Clark return ((val) << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK; 39062d756322SRob Clark } 3907a69c5ed2SRob Clark #define A6XX_RB_STENCILREF_BFREF__MASK 0x0000ff00 3908a69c5ed2SRob Clark #define A6XX_RB_STENCILREF_BFREF__SHIFT 8 3909a69c5ed2SRob Clark static inline uint32_t A6XX_RB_STENCILREF_BFREF(uint32_t val) 3910a69c5ed2SRob Clark { 3911a69c5ed2SRob Clark return ((val) << A6XX_RB_STENCILREF_BFREF__SHIFT) & A6XX_RB_STENCILREF_BFREF__MASK; 3912a69c5ed2SRob Clark } 39132d756322SRob Clark 39142d756322SRob Clark #define REG_A6XX_RB_STENCILMASK 0x00008888 39152d756322SRob Clark #define A6XX_RB_STENCILMASK_MASK__MASK 0x000000ff 39162d756322SRob Clark #define A6XX_RB_STENCILMASK_MASK__SHIFT 0 39172d756322SRob Clark static inline uint32_t A6XX_RB_STENCILMASK_MASK(uint32_t val) 39182d756322SRob Clark { 39192d756322SRob Clark return ((val) << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK; 39202d756322SRob Clark } 3921a69c5ed2SRob Clark #define A6XX_RB_STENCILMASK_BFMASK__MASK 0x0000ff00 3922a69c5ed2SRob Clark #define A6XX_RB_STENCILMASK_BFMASK__SHIFT 8 3923a69c5ed2SRob Clark static inline uint32_t A6XX_RB_STENCILMASK_BFMASK(uint32_t val) 3924a69c5ed2SRob Clark { 3925a69c5ed2SRob Clark return ((val) << A6XX_RB_STENCILMASK_BFMASK__SHIFT) & A6XX_RB_STENCILMASK_BFMASK__MASK; 3926a69c5ed2SRob Clark } 39272d756322SRob Clark 39282d756322SRob Clark #define REG_A6XX_RB_STENCILWRMASK 0x00008889 39292d756322SRob Clark #define A6XX_RB_STENCILWRMASK_WRMASK__MASK 0x000000ff 39302d756322SRob Clark #define A6XX_RB_STENCILWRMASK_WRMASK__SHIFT 0 39312d756322SRob Clark static inline uint32_t A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val) 39322d756322SRob Clark { 39332d756322SRob Clark return ((val) << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK; 39342d756322SRob Clark } 3935a69c5ed2SRob Clark #define A6XX_RB_STENCILWRMASK_BFWRMASK__MASK 0x0000ff00 3936a69c5ed2SRob Clark #define A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT 8 3937a69c5ed2SRob Clark static inline uint32_t A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val) 3938a69c5ed2SRob Clark { 3939a69c5ed2SRob Clark return ((val) << A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_BFWRMASK__MASK; 3940a69c5ed2SRob Clark } 39412d756322SRob Clark 39422d756322SRob Clark #define REG_A6XX_RB_WINDOW_OFFSET 0x00008890 3943c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET_X__MASK 0x00003fff 39442d756322SRob Clark #define A6XX_RB_WINDOW_OFFSET_X__SHIFT 0 39452d756322SRob Clark static inline uint32_t A6XX_RB_WINDOW_OFFSET_X(uint32_t val) 39462d756322SRob Clark { 39472d756322SRob Clark return ((val) << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK; 39482d756322SRob Clark } 3949c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET_Y__MASK 0x3fff0000 39502d756322SRob Clark #define A6XX_RB_WINDOW_OFFSET_Y__SHIFT 16 39512d756322SRob Clark static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val) 39522d756322SRob Clark { 39532d756322SRob Clark return ((val) << A6XX_RB_WINDOW_OFFSET_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET_Y__MASK; 39542d756322SRob Clark } 39552d756322SRob Clark 39562d756322SRob Clark #define REG_A6XX_RB_SAMPLE_COUNT_CONTROL 0x00008891 3957*f73343faSRob Clark #define A6XX_RB_SAMPLE_COUNT_CONTROL_DISABLE 0x00000001 39582d756322SRob Clark #define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 39592d756322SRob Clark 3960ccdf7e28SRob Clark #define REG_A6XX_RB_LRZ_CNTL 0x00008898 3961ccdf7e28SRob Clark #define A6XX_RB_LRZ_CNTL_ENABLE 0x00000001 3962ccdf7e28SRob Clark 3963c28c82e9SRob Clark #define REG_A6XX_RB_Z_CLAMP_MIN 0x000088c0 3964c28c82e9SRob Clark #define A6XX_RB_Z_CLAMP_MIN__MASK 0xffffffff 3965c28c82e9SRob Clark #define A6XX_RB_Z_CLAMP_MIN__SHIFT 0 3966c28c82e9SRob Clark static inline uint32_t A6XX_RB_Z_CLAMP_MIN(float val) 3967c28c82e9SRob Clark { 3968c28c82e9SRob Clark return ((fui(val)) << A6XX_RB_Z_CLAMP_MIN__SHIFT) & A6XX_RB_Z_CLAMP_MIN__MASK; 3969c28c82e9SRob Clark } 3970c28c82e9SRob Clark 3971c28c82e9SRob Clark #define REG_A6XX_RB_Z_CLAMP_MAX 0x000088c1 3972c28c82e9SRob Clark #define A6XX_RB_Z_CLAMP_MAX__MASK 0xffffffff 3973c28c82e9SRob Clark #define A6XX_RB_Z_CLAMP_MAX__SHIFT 0 3974c28c82e9SRob Clark static inline uint32_t A6XX_RB_Z_CLAMP_MAX(float val) 3975c28c82e9SRob Clark { 3976c28c82e9SRob Clark return ((fui(val)) << A6XX_RB_Z_CLAMP_MAX__SHIFT) & A6XX_RB_Z_CLAMP_MAX__MASK; 3977c28c82e9SRob Clark } 3978c28c82e9SRob Clark 39792d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_88D0 0x000088d0 3980c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_88D0_UNK0__MASK 0x00001fff 3981c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT 0 3982c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK0(uint32_t val) 3983c28c82e9SRob Clark { 3984c28c82e9SRob Clark return ((val) << A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK0__MASK; 3985c28c82e9SRob Clark } 3986c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_88D0_UNK16__MASK 0x07ff0000 3987c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT 16 3988c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK16(uint32_t val) 3989c28c82e9SRob Clark { 3990c28c82e9SRob Clark return ((val) << A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK16__MASK; 3991c28c82e9SRob Clark } 39922d756322SRob Clark 39932d756322SRob Clark #define REG_A6XX_RB_BLIT_SCISSOR_TL 0x000088d1 3994c28c82e9SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_X__MASK 0x00003fff 39952d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT 0 39962d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val) 39972d756322SRob Clark { 39982d756322SRob Clark return ((val) << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK; 39992d756322SRob Clark } 4000c28c82e9SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK 0x3fff0000 40012d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT 16 40022d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val) 40032d756322SRob Clark { 40042d756322SRob Clark return ((val) << A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_Y__MASK; 40052d756322SRob Clark } 40062d756322SRob Clark 40072d756322SRob Clark #define REG_A6XX_RB_BLIT_SCISSOR_BR 0x000088d2 4008c28c82e9SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_X__MASK 0x00003fff 40092d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT 0 40102d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val) 40112d756322SRob Clark { 40122d756322SRob Clark return ((val) << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK; 40132d756322SRob Clark } 4014c28c82e9SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK 0x3fff0000 40152d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT 16 40162d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val) 40172d756322SRob Clark { 40182d756322SRob Clark return ((val) << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK; 40192d756322SRob Clark } 40202d756322SRob Clark 4021c28c82e9SRob Clark #define REG_A6XX_RB_BIN_CONTROL2 0x000088d3 4022c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL2_BINW__MASK 0x0000003f 4023c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL2_BINW__SHIFT 0 4024c28c82e9SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val) 4025c28c82e9SRob Clark { 4026c28c82e9SRob Clark return ((val >> 5) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK; 4027c28c82e9SRob Clark } 4028c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL2_BINH__MASK 0x00007f00 4029c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL2_BINH__SHIFT 8 4030c28c82e9SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val) 4031c28c82e9SRob Clark { 4032c28c82e9SRob Clark return ((val >> 4) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK; 4033c28c82e9SRob Clark } 4034c28c82e9SRob Clark 4035c28c82e9SRob Clark #define REG_A6XX_RB_WINDOW_OFFSET2 0x000088d4 4036c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET2_X__MASK 0x00003fff 4037c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET2_X__SHIFT 0 4038c28c82e9SRob Clark static inline uint32_t A6XX_RB_WINDOW_OFFSET2_X(uint32_t val) 4039c28c82e9SRob Clark { 4040c28c82e9SRob Clark return ((val) << A6XX_RB_WINDOW_OFFSET2_X__SHIFT) & A6XX_RB_WINDOW_OFFSET2_X__MASK; 4041c28c82e9SRob Clark } 4042c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET2_Y__MASK 0x3fff0000 4043c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET2_Y__SHIFT 16 4044c28c82e9SRob Clark static inline uint32_t A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val) 4045c28c82e9SRob Clark { 4046c28c82e9SRob Clark return ((val) << A6XX_RB_WINDOW_OFFSET2_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET2_Y__MASK; 4047c28c82e9SRob Clark } 4048c28c82e9SRob Clark 4049*f73343faSRob Clark #define REG_A6XX_RB_BLIT_GMEM_MSAA_CNTL 0x000088d5 4050*f73343faSRob Clark #define A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__MASK 0x00000018 4051*f73343faSRob Clark #define A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__SHIFT 3 4052*f73343faSRob Clark static inline uint32_t A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 4053ccdf7e28SRob Clark { 4054*f73343faSRob Clark return ((val) << A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__MASK; 4055ccdf7e28SRob Clark } 4056ccdf7e28SRob Clark 40572d756322SRob Clark #define REG_A6XX_RB_BLIT_BASE_GMEM 0x000088d6 4058c28c82e9SRob Clark #define A6XX_RB_BLIT_BASE_GMEM__MASK 0xfffff000 4059c28c82e9SRob Clark #define A6XX_RB_BLIT_BASE_GMEM__SHIFT 12 4060c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_BASE_GMEM(uint32_t val) 4061c28c82e9SRob Clark { 4062c28c82e9SRob Clark return ((val >> 12) << A6XX_RB_BLIT_BASE_GMEM__SHIFT) & A6XX_RB_BLIT_BASE_GMEM__MASK; 4063c28c82e9SRob Clark } 40642d756322SRob Clark 40652d756322SRob Clark #define REG_A6XX_RB_BLIT_DST_INFO 0x000088d7 40662d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK 0x00000003 40672d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT 0 40682d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) 40692d756322SRob Clark { 40702d756322SRob Clark return ((val) << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK; 40712d756322SRob Clark } 40722d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_FLAGS 0x00000004 4073ccdf7e28SRob Clark #define A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK 0x00000018 4074ccdf7e28SRob Clark #define A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT 3 4075ccdf7e28SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) 4076ccdf7e28SRob Clark { 4077ccdf7e28SRob Clark return ((val) << A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK; 4078ccdf7e28SRob Clark } 40792d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK 0x00000060 40802d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT 5 40812d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) 40822d756322SRob Clark { 40832d756322SRob Clark return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK; 40842d756322SRob Clark } 4085c28c82e9SRob Clark #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK 0x00007f80 4086c28c82e9SRob Clark #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT 7 4087c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_format val) 4088c28c82e9SRob Clark { 4089c28c82e9SRob Clark return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK; 4090c28c82e9SRob Clark } 4091c28c82e9SRob Clark #define A6XX_RB_BLIT_DST_INFO_UNK15 0x00008000 4092c28c82e9SRob Clark 4093c28c82e9SRob Clark #define REG_A6XX_RB_BLIT_DST 0x000088d8 4094c28c82e9SRob Clark #define A6XX_RB_BLIT_DST__MASK 0xffffffff 4095c28c82e9SRob Clark #define A6XX_RB_BLIT_DST__SHIFT 0 4096c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_DST(uint32_t val) 4097c28c82e9SRob Clark { 4098c28c82e9SRob Clark return ((val) << A6XX_RB_BLIT_DST__SHIFT) & A6XX_RB_BLIT_DST__MASK; 4099c28c82e9SRob Clark } 41002d756322SRob Clark 41012d756322SRob Clark #define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da 4102c28c82e9SRob Clark #define A6XX_RB_BLIT_DST_PITCH__MASK 0x0000ffff 41032d756322SRob Clark #define A6XX_RB_BLIT_DST_PITCH__SHIFT 0 41042d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val) 41052d756322SRob Clark { 41062d756322SRob Clark return ((val >> 6) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK; 41072d756322SRob Clark } 41082d756322SRob Clark 41092d756322SRob Clark #define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH 0x000088db 4110c28c82e9SRob Clark #define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0x1fffffff 41112d756322SRob Clark #define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0 41122d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) 41132d756322SRob Clark { 41142d756322SRob Clark return ((val >> 6) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK; 41152d756322SRob Clark } 41162d756322SRob Clark 4117c28c82e9SRob Clark #define REG_A6XX_RB_BLIT_FLAG_DST 0x000088dc 4118c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST__MASK 0xffffffff 4119c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST__SHIFT 0 4120c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_FLAG_DST(uint32_t val) 4121c28c82e9SRob Clark { 4122c28c82e9SRob Clark return ((val) << A6XX_RB_BLIT_FLAG_DST__SHIFT) & A6XX_RB_BLIT_FLAG_DST__MASK; 4123c28c82e9SRob Clark } 4124c28c82e9SRob Clark 4125c28c82e9SRob Clark #define REG_A6XX_RB_BLIT_FLAG_DST_PITCH 0x000088de 4126c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK 0x000007ff 4127c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT 0 4128c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val) 4129c28c82e9SRob Clark { 4130c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK; 4131c28c82e9SRob Clark } 4132c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK 0x0ffff800 4133c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT 11 4134c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val) 4135c28c82e9SRob Clark { 4136c28c82e9SRob Clark return ((val >> 7) << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK; 4137c28c82e9SRob Clark } 4138c28c82e9SRob Clark 41392d756322SRob Clark #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 0x000088df 41402d756322SRob Clark 41412d756322SRob Clark #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1 0x000088e0 41422d756322SRob Clark 41432d756322SRob Clark #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2 0x000088e1 41442d756322SRob Clark 41452d756322SRob Clark #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3 0x000088e2 41462d756322SRob Clark 41472d756322SRob Clark #define REG_A6XX_RB_BLIT_INFO 0x000088e3 41482d756322SRob Clark #define A6XX_RB_BLIT_INFO_UNK0 0x00000001 4149a69c5ed2SRob Clark #define A6XX_RB_BLIT_INFO_GMEM 0x00000002 4150cc4c26d4SRob Clark #define A6XX_RB_BLIT_INFO_SAMPLE_0 0x00000004 4151a69c5ed2SRob Clark #define A6XX_RB_BLIT_INFO_DEPTH 0x00000008 4152a69c5ed2SRob Clark #define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK 0x000000f0 4153a69c5ed2SRob Clark #define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT 4 4154a69c5ed2SRob Clark static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val) 41552d756322SRob Clark { 4156a69c5ed2SRob Clark return ((val) << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK; 41572d756322SRob Clark } 4158*f73343faSRob Clark #define A6XX_RB_BLIT_INFO_LAST__MASK 0x00000300 4159*f73343faSRob Clark #define A6XX_RB_BLIT_INFO_LAST__SHIFT 8 4160*f73343faSRob Clark static inline uint32_t A6XX_RB_BLIT_INFO_LAST(uint32_t val) 4161c28c82e9SRob Clark { 4162*f73343faSRob Clark return ((val) << A6XX_RB_BLIT_INFO_LAST__SHIFT) & A6XX_RB_BLIT_INFO_LAST__MASK; 4163c28c82e9SRob Clark } 4164*f73343faSRob Clark #define A6XX_RB_BLIT_INFO_BUFFER_ID__MASK 0x0000f000 4165*f73343faSRob Clark #define A6XX_RB_BLIT_INFO_BUFFER_ID__SHIFT 12 4166*f73343faSRob Clark static inline uint32_t A6XX_RB_BLIT_INFO_BUFFER_ID(uint32_t val) 4167c28c82e9SRob Clark { 4168*f73343faSRob Clark return ((val) << A6XX_RB_BLIT_INFO_BUFFER_ID__SHIFT) & A6XX_RB_BLIT_INFO_BUFFER_ID__MASK; 4169c28c82e9SRob Clark } 41702d756322SRob Clark 41712d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_88F0 0x000088f0 41722d756322SRob Clark 4173c28c82e9SRob Clark #define REG_A6XX_RB_UNK_FLAG_BUFFER_BASE 0x000088f1 4174c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK 0xffffffff 4175c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT 0 4176c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_BASE(uint32_t val) 4177c28c82e9SRob Clark { 4178c28c82e9SRob Clark return ((val) << A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK; 4179c28c82e9SRob Clark } 4180c28c82e9SRob Clark 4181c28c82e9SRob Clark #define REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH 0x000088f3 4182c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff 4183c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 4184c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(uint32_t val) 4185c28c82e9SRob Clark { 4186c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK; 4187c28c82e9SRob Clark } 4188c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x00fff800 4189c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 4190c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 4191c28c82e9SRob Clark { 4192c28c82e9SRob Clark return ((val >> 7) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; 4193c28c82e9SRob Clark } 4194c28c82e9SRob Clark 4195c28c82e9SRob Clark #define REG_A6XX_RB_UNKNOWN_88F4 0x000088f4 4196c28c82e9SRob Clark 4197c28c82e9SRob Clark #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE 0x00008900 4198c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK 0xffffffff 4199c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT 0 4200c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_BASE(uint32_t val) 4201c28c82e9SRob Clark { 4202c28c82e9SRob Clark return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK; 4203c28c82e9SRob Clark } 4204c28c82e9SRob Clark 42052d756322SRob Clark #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x00008902 4206c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK 0x0000007f 4207c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 4208c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val) 4209c28c82e9SRob Clark { 4210c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK; 4211c28c82e9SRob Clark } 4212c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK 0x00000700 4213c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT 8 4214c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8(uint32_t val) 4215c28c82e9SRob Clark { 4216c28c82e9SRob Clark return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK; 4217c28c82e9SRob Clark } 4218c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x0ffff800 4219c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 4220c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 4221c28c82e9SRob Clark { 4222c28c82e9SRob Clark return ((val >> 7) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; 4223c28c82e9SRob Clark } 42242d756322SRob Clark 42252d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; } 42262d756322SRob Clark 4227c28c82e9SRob Clark static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; } 4228c28c82e9SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK 0xffffffff 4229c28c82e9SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT 0 4230c28c82e9SRob Clark static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t val) 4231c28c82e9SRob Clark { 4232c28c82e9SRob Clark return ((val) << A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK; 4233c28c82e9SRob Clark } 4234c28c82e9SRob Clark 42352d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; } 42362d756322SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff 42372d756322SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 42382d756322SRob Clark static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val) 42392d756322SRob Clark { 4240c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK; 42412d756322SRob Clark } 4242c28c82e9SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffff800 42432d756322SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 42442d756322SRob Clark static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 42452d756322SRob Clark { 4246c28c82e9SRob Clark return ((val >> 7) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; 42472d756322SRob Clark } 42482d756322SRob Clark 4249c28c82e9SRob Clark #define REG_A6XX_RB_SAMPLE_COUNT_ADDR 0x00008927 4250c28c82e9SRob Clark #define A6XX_RB_SAMPLE_COUNT_ADDR__MASK 0xffffffff 4251c28c82e9SRob Clark #define A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT 0 4252c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_COUNT_ADDR(uint32_t val) 4253c28c82e9SRob Clark { 4254c28c82e9SRob Clark return ((val) << A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT) & A6XX_RB_SAMPLE_COUNT_ADDR__MASK; 4255c28c82e9SRob Clark } 4256c28c82e9SRob Clark 425757cfe41cSRob Clark #define REG_A6XX_RB_UNKNOWN_8A00 0x00008a00 425857cfe41cSRob Clark 425957cfe41cSRob Clark #define REG_A6XX_RB_UNKNOWN_8A10 0x00008a10 426057cfe41cSRob Clark 426157cfe41cSRob Clark #define REG_A6XX_RB_UNKNOWN_8A20 0x00008a20 426257cfe41cSRob Clark 426357cfe41cSRob Clark #define REG_A6XX_RB_UNKNOWN_8A30 0x00008a30 426457cfe41cSRob Clark 42652d756322SRob Clark #define REG_A6XX_RB_2D_BLIT_CNTL 0x00008c00 4266c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK 0x00000007 4267c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT 0 4268c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val) 4269c28c82e9SRob Clark { 4270c28c82e9SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK; 4271c28c82e9SRob Clark } 427257cfe41cSRob Clark #define A6XX_RB_2D_BLIT_CNTL_OVERWRITEEN 0x00000008 427357cfe41cSRob Clark #define A6XX_RB_2D_BLIT_CNTL_UNK4__MASK 0x00000070 427457cfe41cSRob Clark #define A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT 4 427557cfe41cSRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK4(uint32_t val) 4276c28c82e9SRob Clark { 427757cfe41cSRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK4__MASK; 4278c28c82e9SRob Clark } 4279c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR 0x00000080 42802d756322SRob Clark #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00 42812d756322SRob Clark #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8 4282c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val) 42832d756322SRob Clark { 42842d756322SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK; 42852d756322SRob Clark } 4286ccdf7e28SRob Clark #define A6XX_RB_2D_BLIT_CNTL_SCISSOR 0x00010000 4287c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_UNK17__MASK 0x00060000 4288c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT 17 4289c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK17(uint32_t val) 4290c28c82e9SRob Clark { 4291c28c82e9SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK17__MASK; 4292c28c82e9SRob Clark } 4293c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_D24S8 0x00080000 4294c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_MASK__MASK 0x00f00000 4295c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT 20 4296c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_MASK(uint32_t val) 4297c28c82e9SRob Clark { 4298c28c82e9SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_RB_2D_BLIT_CNTL_MASK__MASK; 4299c28c82e9SRob Clark } 4300c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_IFMT__MASK 0x1f000000 4301c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT 24 4302c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val) 4303c28c82e9SRob Clark { 4304c28c82e9SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_IFMT__MASK; 4305c28c82e9SRob Clark } 430657cfe41cSRob Clark #define A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK 0x20000000 430757cfe41cSRob Clark #define A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT 29 430857cfe41cSRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val) 4309c28c82e9SRob Clark { 431057cfe41cSRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK; 4311c28c82e9SRob Clark } 4312ccdf7e28SRob Clark 4313c28c82e9SRob Clark #define REG_A6XX_RB_2D_UNKNOWN_8C01 0x00008c01 43142d756322SRob Clark 43152d756322SRob Clark #define REG_A6XX_RB_2D_DST_INFO 0x00008c17 43162d756322SRob Clark #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff 43172d756322SRob Clark #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0 4318c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_format val) 43192d756322SRob Clark { 43202d756322SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK; 43212d756322SRob Clark } 43222d756322SRob Clark #define A6XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300 43232d756322SRob Clark #define A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8 43242d756322SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) 43252d756322SRob Clark { 43262d756322SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_2D_DST_INFO_TILE_MODE__MASK; 43272d756322SRob Clark } 43282d756322SRob Clark #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00 43292d756322SRob Clark #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10 43302d756322SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) 43312d756322SRob Clark { 43322d756322SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK; 43332d756322SRob Clark } 43342d756322SRob Clark #define A6XX_RB_2D_DST_INFO_FLAGS 0x00001000 4335c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_SRGB 0x00002000 4336c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_SAMPLES__MASK 0x0000c000 4337c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT 14 4338c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) 4339c28c82e9SRob Clark { 4340c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_2D_DST_INFO_SAMPLES__MASK; 4341c28c82e9SRob Clark } 4342c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_FILTER 0x00010000 4343cc4c26d4SRob Clark #define A6XX_RB_2D_DST_INFO_UNK17 0x00020000 4344c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE 0x00040000 4345cc4c26d4SRob Clark #define A6XX_RB_2D_DST_INFO_UNK19 0x00080000 4346c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_UNK20 0x00100000 4347cc4c26d4SRob Clark #define A6XX_RB_2D_DST_INFO_UNK21 0x00200000 4348c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_UNK22 0x00400000 4349cc4c26d4SRob Clark #define A6XX_RB_2D_DST_INFO_UNK23__MASK 0x07800000 4350cc4c26d4SRob Clark #define A6XX_RB_2D_DST_INFO_UNK23__SHIFT 23 4351cc4c26d4SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_UNK23(uint32_t val) 4352cc4c26d4SRob Clark { 4353cc4c26d4SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_UNK23__SHIFT) & A6XX_RB_2D_DST_INFO_UNK23__MASK; 4354cc4c26d4SRob Clark } 4355cc4c26d4SRob Clark #define A6XX_RB_2D_DST_INFO_UNK28 0x10000000 43562d756322SRob Clark 4357c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST 0x00008c18 4358c28c82e9SRob Clark #define A6XX_RB_2D_DST__MASK 0xffffffff 4359c28c82e9SRob Clark #define A6XX_RB_2D_DST__SHIFT 0 4360c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST(uint32_t val) 43612d756322SRob Clark { 4362c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST__SHIFT) & A6XX_RB_2D_DST__MASK; 4363c28c82e9SRob Clark } 4364c28c82e9SRob Clark 4365c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_PITCH 0x00008c1a 4366c28c82e9SRob Clark #define A6XX_RB_2D_DST_PITCH__MASK 0x0000ffff 4367c28c82e9SRob Clark #define A6XX_RB_2D_DST_PITCH__SHIFT 0 4368c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_PITCH(uint32_t val) 4369c28c82e9SRob Clark { 4370c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_2D_DST_PITCH__SHIFT) & A6XX_RB_2D_DST_PITCH__MASK; 4371c28c82e9SRob Clark } 4372c28c82e9SRob Clark 4373c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_PLANE1 0x00008c1b 4374c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE1__MASK 0xffffffff 4375c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE1__SHIFT 0 4376c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_PLANE1(uint32_t val) 4377c28c82e9SRob Clark { 4378c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST_PLANE1__SHIFT) & A6XX_RB_2D_DST_PLANE1__MASK; 4379c28c82e9SRob Clark } 4380c28c82e9SRob Clark 4381c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_PLANE_PITCH 0x00008c1d 4382c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE_PITCH__MASK 0x0000ffff 4383c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE_PITCH__SHIFT 0 4384c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_PLANE_PITCH(uint32_t val) 4385c28c82e9SRob Clark { 4386c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_2D_DST_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_PLANE_PITCH__MASK; 4387c28c82e9SRob Clark } 4388c28c82e9SRob Clark 4389c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_PLANE2 0x00008c1e 4390c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE2__MASK 0xffffffff 4391c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE2__SHIFT 0 4392c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_PLANE2(uint32_t val) 4393c28c82e9SRob Clark { 4394c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST_PLANE2__SHIFT) & A6XX_RB_2D_DST_PLANE2__MASK; 43952d756322SRob Clark } 43962d756322SRob Clark 4397c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_FLAGS 0x00008c20 4398c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS__MASK 0xffffffff 4399c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS__SHIFT 0 4400c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_FLAGS(uint32_t val) 4401c28c82e9SRob Clark { 4402c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST_FLAGS__SHIFT) & A6XX_RB_2D_DST_FLAGS__MASK; 4403c28c82e9SRob Clark } 4404c28c82e9SRob Clark 4405c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_FLAGS_PITCH 0x00008c22 4406c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PITCH__MASK 0x000000ff 4407c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT 0 4408c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_FLAGS_PITCH(uint32_t val) 4409c28c82e9SRob Clark { 4410c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH__MASK; 4411c28c82e9SRob Clark } 4412c28c82e9SRob Clark 4413c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_FLAGS_PLANE 0x00008c23 4414c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PLANE__MASK 0xffffffff 4415c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT 0 4416c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE(uint32_t val) 4417c28c82e9SRob Clark { 4418c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE__MASK; 4419c28c82e9SRob Clark } 4420c28c82e9SRob Clark 4421c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH 0x00008c25 4422c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK 0x000000ff 4423c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT 0 4424c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(uint32_t val) 4425c28c82e9SRob Clark { 4426c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK; 4427c28c82e9SRob Clark } 4428c28c82e9SRob Clark 44292d756322SRob Clark #define REG_A6XX_RB_2D_SRC_SOLID_C0 0x00008c2c 44302d756322SRob Clark 44312d756322SRob Clark #define REG_A6XX_RB_2D_SRC_SOLID_C1 0x00008c2d 44322d756322SRob Clark 44332d756322SRob Clark #define REG_A6XX_RB_2D_SRC_SOLID_C2 0x00008c2e 44342d756322SRob Clark 44352d756322SRob Clark #define REG_A6XX_RB_2D_SRC_SOLID_C3 0x00008c2f 44362d756322SRob Clark 44372d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8E01 0x00008e01 44382d756322SRob Clark 4439*f73343faSRob Clark #define REG_A6XX_RB_DBG_ECO_CNTL 0x00008e04 4440a69c5ed2SRob Clark 4441c28c82e9SRob Clark #define REG_A6XX_RB_ADDR_MODE_CNTL 0x00008e05 4442c28c82e9SRob Clark 44432d756322SRob Clark #define REG_A6XX_RB_CCU_CNTL 0x00008e07 4444*f73343faSRob Clark #define A6XX_RB_CCU_CNTL_CONCURRENT_RESOLVE 0x00000004 4445*f73343faSRob Clark #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__MASK 0x00000080 4446*f73343faSRob Clark #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__SHIFT 7 4447*f73343faSRob Clark static inline uint32_t A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI(uint32_t val) 4448c28c82e9SRob Clark { 4449*f73343faSRob Clark return ((val) << A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__MASK; 4450*f73343faSRob Clark } 4451*f73343faSRob Clark #define A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__MASK 0x00000200 4452*f73343faSRob Clark #define A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__SHIFT 9 4453*f73343faSRob Clark static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI(uint32_t val) 4454*f73343faSRob Clark { 4455*f73343faSRob Clark return ((val) << A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__MASK; 445657cfe41cSRob Clark } 445757cfe41cSRob Clark #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK 0x001ff000 445857cfe41cSRob Clark #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT 12 445957cfe41cSRob Clark static inline uint32_t A6XX_RB_CCU_CNTL_DEPTH_OFFSET(uint32_t val) 446057cfe41cSRob Clark { 446157cfe41cSRob Clark return ((val >> 12) << A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK; 4462c28c82e9SRob Clark } 4463c28c82e9SRob Clark #define A6XX_RB_CCU_CNTL_GMEM 0x00400000 4464*f73343faSRob Clark #define A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK 0xff800000 4465*f73343faSRob Clark #define A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT 23 4466*f73343faSRob Clark static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_OFFSET(uint32_t val) 4467*f73343faSRob Clark { 4468*f73343faSRob Clark return ((val >> 12) << A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK; 4469*f73343faSRob Clark } 44702d756322SRob Clark 4471c28c82e9SRob Clark #define REG_A6XX_RB_NC_MODE_CNTL 0x00008e08 4472c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_MODE 0x00000001 4473c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006 4474c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT 1 4475c28c82e9SRob Clark static inline uint32_t A6XX_RB_NC_MODE_CNTL_LOWER_BIT(uint32_t val) 4476c28c82e9SRob Clark { 4477c28c82e9SRob Clark return ((val) << A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK; 4478c28c82e9SRob Clark } 4479c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008 4480c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_AMSBC 0x00000010 4481c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000400 4482c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT 10 4483c28c82e9SRob Clark static inline uint32_t A6XX_RB_NC_MODE_CNTL_UPPER_BIT(uint32_t val) 4484c28c82e9SRob Clark { 4485c28c82e9SRob Clark return ((val) << A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK; 4486c28c82e9SRob Clark } 4487c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR 0x00000800 4488c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_UNK12__MASK 0x00003000 4489c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT 12 4490c28c82e9SRob Clark static inline uint32_t A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val) 4491c28c82e9SRob Clark { 4492c28c82e9SRob Clark return ((val) << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK; 4493c28c82e9SRob Clark } 44942d756322SRob Clark 4495cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RB_PERFCTR_RB_SEL(uint32_t i0) { return 0x00008e10 + 0x1*i0; } 4496c28c82e9SRob Clark 4497cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RB_PERFCTR_CCU_SEL(uint32_t i0) { return 0x00008e18 + 0x1*i0; } 4498c28c82e9SRob Clark 4499c28c82e9SRob Clark #define REG_A6XX_RB_UNKNOWN_8E28 0x00008e28 4500c28c82e9SRob Clark 4501cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RB_PERFCTR_CMP_SEL(uint32_t i0) { return 0x00008e2c + 0x1*i0; } 4502c28c82e9SRob Clark 4503*f73343faSRob Clark static inline uint32_t REG_A7XX_RB_PERFCTR_UFC_SEL(uint32_t i0) { return 0x00008e30 + 0x1*i0; } 4504*f73343faSRob Clark 4505c28c82e9SRob Clark #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST 0x00008e3b 4506c28c82e9SRob Clark 4507c28c82e9SRob Clark #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD 0x00008e3d 4508c28c82e9SRob Clark 4509c28c82e9SRob Clark #define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x00008e50 4510c28c82e9SRob Clark 4511c28c82e9SRob Clark #define REG_A6XX_RB_UNKNOWN_8E51 0x00008e51 4512c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_8E51__MASK 0xffffffff 4513c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_8E51__SHIFT 0 4514c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNKNOWN_8E51(uint32_t val) 4515c28c82e9SRob Clark { 4516c28c82e9SRob Clark return ((val) << A6XX_RB_UNKNOWN_8E51__SHIFT) & A6XX_RB_UNKNOWN_8E51__MASK; 4517c28c82e9SRob Clark } 4518c28c82e9SRob Clark 451957cfe41cSRob Clark #define REG_A6XX_VPC_GS_PARAM 0x00009100 452057cfe41cSRob Clark #define A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK 0x000000ff 452157cfe41cSRob Clark #define A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT 0 452257cfe41cSRob Clark static inline uint32_t A6XX_VPC_GS_PARAM_LINELENGTHLOC(uint32_t val) 452357cfe41cSRob Clark { 452457cfe41cSRob Clark return ((val) << A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT) & A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK; 452557cfe41cSRob Clark } 4526c28c82e9SRob Clark 4527c28c82e9SRob Clark #define REG_A6XX_VPC_VS_CLIP_CNTL 0x00009101 4528c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff 4529c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT 0 4530c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(uint32_t val) 4531c28c82e9SRob Clark { 4532c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK; 4533c28c82e9SRob Clark } 4534c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00 4535c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8 4536c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) 4537c28c82e9SRob Clark { 4538c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK; 4539c28c82e9SRob Clark } 4540c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000 4541c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16 4542c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) 4543c28c82e9SRob Clark { 4544c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; 4545c28c82e9SRob Clark } 4546c28c82e9SRob Clark 4547c28c82e9SRob Clark #define REG_A6XX_VPC_GS_CLIP_CNTL 0x00009102 4548c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff 4549c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT 0 4550c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK(uint32_t val) 4551c28c82e9SRob Clark { 4552c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK; 4553c28c82e9SRob Clark } 4554c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00 4555c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8 4556c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) 4557c28c82e9SRob Clark { 4558c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK; 4559c28c82e9SRob Clark } 4560c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000 4561c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16 4562c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) 4563c28c82e9SRob Clark { 4564c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; 4565c28c82e9SRob Clark } 4566c28c82e9SRob Clark 4567c28c82e9SRob Clark #define REG_A6XX_VPC_DS_CLIP_CNTL 0x00009103 4568c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff 4569c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT 0 4570c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK(uint32_t val) 4571c28c82e9SRob Clark { 4572c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK; 4573c28c82e9SRob Clark } 4574c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00 4575c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8 4576c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) 4577c28c82e9SRob Clark { 4578c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK; 4579c28c82e9SRob Clark } 4580c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000 4581c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16 4582c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) 4583c28c82e9SRob Clark { 4584c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; 4585c28c82e9SRob Clark } 4586c28c82e9SRob Clark 4587c28c82e9SRob Clark #define REG_A6XX_VPC_VS_LAYER_CNTL 0x00009104 4588c28c82e9SRob Clark #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff 4589c28c82e9SRob Clark #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT 0 4590c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(uint32_t val) 4591c28c82e9SRob Clark { 4592c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK; 4593c28c82e9SRob Clark } 4594c28c82e9SRob Clark #define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00 4595c28c82e9SRob Clark #define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT 8 4596c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(uint32_t val) 4597c28c82e9SRob Clark { 4598c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK; 4599c28c82e9SRob Clark } 4600c28c82e9SRob Clark 4601c28c82e9SRob Clark #define REG_A6XX_VPC_GS_LAYER_CNTL 0x00009105 4602c28c82e9SRob Clark #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff 4603c28c82e9SRob Clark #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT 0 4604c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(uint32_t val) 4605c28c82e9SRob Clark { 4606c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK; 4607c28c82e9SRob Clark } 4608c28c82e9SRob Clark #define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00 4609c28c82e9SRob Clark #define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT 8 4610c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(uint32_t val) 4611c28c82e9SRob Clark { 4612c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK; 4613c28c82e9SRob Clark } 4614c28c82e9SRob Clark 4615c28c82e9SRob Clark #define REG_A6XX_VPC_DS_LAYER_CNTL 0x00009106 4616c28c82e9SRob Clark #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff 4617c28c82e9SRob Clark #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT 0 4618c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_LAYERLOC(uint32_t val) 4619c28c82e9SRob Clark { 4620c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK; 4621c28c82e9SRob Clark } 4622c28c82e9SRob Clark #define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00 4623c28c82e9SRob Clark #define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT 8 4624c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val) 4625c28c82e9SRob Clark { 4626c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK; 4627c28c82e9SRob Clark } 46282d756322SRob Clark 4629a69c5ed2SRob Clark #define REG_A6XX_VPC_UNKNOWN_9107 0x00009107 4630cc4c26d4SRob Clark #define A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD 0x00000001 4631cc4c26d4SRob Clark #define A6XX_VPC_UNKNOWN_9107_UNK2 0x00000004 4632a69c5ed2SRob Clark 4633c28c82e9SRob Clark #define REG_A6XX_VPC_POLYGON_MODE 0x00009108 4634c28c82e9SRob Clark #define A6XX_VPC_POLYGON_MODE_MODE__MASK 0x00000003 4635c28c82e9SRob Clark #define A6XX_VPC_POLYGON_MODE_MODE__SHIFT 0 4636c28c82e9SRob Clark static inline uint32_t A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) 4637c28c82e9SRob Clark { 4638c28c82e9SRob Clark return ((val) << A6XX_VPC_POLYGON_MODE_MODE__SHIFT) & A6XX_VPC_POLYGON_MODE_MODE__MASK; 4639c28c82e9SRob Clark } 46402d756322SRob Clark 46412d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; } 46422d756322SRob Clark 46432d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; } 46442d756322SRob Clark 46452d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; } 46462d756322SRob Clark 46472d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; } 46482d756322SRob Clark 46492d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9210 0x00009210 46502d756322SRob Clark 46512d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9211 0x00009211 46522d756322SRob Clark 46532d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; } 46542d756322SRob Clark 46552d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; } 46562d756322SRob Clark 46572d756322SRob Clark #define REG_A6XX_VPC_SO_CNTL 0x00009216 4658cc4c26d4SRob Clark #define A6XX_VPC_SO_CNTL_ADDR__MASK 0x000000ff 4659cc4c26d4SRob Clark #define A6XX_VPC_SO_CNTL_ADDR__SHIFT 0 4660cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_SO_CNTL_ADDR(uint32_t val) 4661c28c82e9SRob Clark { 4662cc4c26d4SRob Clark return ((val) << A6XX_VPC_SO_CNTL_ADDR__SHIFT) & A6XX_VPC_SO_CNTL_ADDR__MASK; 4663c28c82e9SRob Clark } 4664cc4c26d4SRob Clark #define A6XX_VPC_SO_CNTL_RESET 0x00010000 46652d756322SRob Clark 46662d756322SRob Clark #define REG_A6XX_VPC_SO_PROG 0x00009217 46672d756322SRob Clark #define A6XX_VPC_SO_PROG_A_BUF__MASK 0x00000003 46682d756322SRob Clark #define A6XX_VPC_SO_PROG_A_BUF__SHIFT 0 46692d756322SRob Clark static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val) 46702d756322SRob Clark { 46712d756322SRob Clark return ((val) << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK; 46722d756322SRob Clark } 46732d756322SRob Clark #define A6XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc 46742d756322SRob Clark #define A6XX_VPC_SO_PROG_A_OFF__SHIFT 2 46752d756322SRob Clark static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val) 46762d756322SRob Clark { 46772d756322SRob Clark return ((val >> 2) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK; 46782d756322SRob Clark } 46792d756322SRob Clark #define A6XX_VPC_SO_PROG_A_EN 0x00000800 46802d756322SRob Clark #define A6XX_VPC_SO_PROG_B_BUF__MASK 0x00003000 46812d756322SRob Clark #define A6XX_VPC_SO_PROG_B_BUF__SHIFT 12 46822d756322SRob Clark static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val) 46832d756322SRob Clark { 46842d756322SRob Clark return ((val) << A6XX_VPC_SO_PROG_B_BUF__SHIFT) & A6XX_VPC_SO_PROG_B_BUF__MASK; 46852d756322SRob Clark } 46862d756322SRob Clark #define A6XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000 46872d756322SRob Clark #define A6XX_VPC_SO_PROG_B_OFF__SHIFT 14 46882d756322SRob Clark static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val) 46892d756322SRob Clark { 46902d756322SRob Clark return ((val >> 2) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK; 46912d756322SRob Clark } 46922d756322SRob Clark #define A6XX_VPC_SO_PROG_B_EN 0x00800000 46932d756322SRob Clark 4694c28c82e9SRob Clark #define REG_A6XX_VPC_SO_STREAM_COUNTS 0x00009218 4695c28c82e9SRob Clark #define A6XX_VPC_SO_STREAM_COUNTS__MASK 0xffffffff 4696c28c82e9SRob Clark #define A6XX_VPC_SO_STREAM_COUNTS__SHIFT 0 4697c28c82e9SRob Clark static inline uint32_t A6XX_VPC_SO_STREAM_COUNTS(uint32_t val) 4698c28c82e9SRob Clark { 4699c28c82e9SRob Clark return ((val) << A6XX_VPC_SO_STREAM_COUNTS__SHIFT) & A6XX_VPC_SO_STREAM_COUNTS__MASK; 4700c28c82e9SRob Clark } 4701c28c82e9SRob Clark 47022d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; } 47032d756322SRob Clark 4704c28c82e9SRob Clark static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0) { return 0x0000921a + 0x7*i0; } 4705c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_BASE__MASK 0xffffffff 4706c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_BASE__SHIFT 0 4707c28c82e9SRob Clark static inline uint32_t A6XX_VPC_SO_BUFFER_BASE(uint32_t val) 4708c28c82e9SRob Clark { 4709c28c82e9SRob Clark return ((val) << A6XX_VPC_SO_BUFFER_BASE__SHIFT) & A6XX_VPC_SO_BUFFER_BASE__MASK; 4710c28c82e9SRob Clark } 4711c28c82e9SRob Clark 47122d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; } 4713c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_SIZE__MASK 0xfffffffc 4714c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_SIZE__SHIFT 2 4715c28c82e9SRob Clark static inline uint32_t A6XX_VPC_SO_BUFFER_SIZE(uint32_t val) 4716c28c82e9SRob Clark { 4717c28c82e9SRob Clark return ((val >> 2) << A6XX_VPC_SO_BUFFER_SIZE__SHIFT) & A6XX_VPC_SO_BUFFER_SIZE__MASK; 4718c28c82e9SRob Clark } 47192d756322SRob Clark 4720*f73343faSRob Clark static inline uint32_t REG_A6XX_VPC_SO_BUFFER_STRIDE(uint32_t i0) { return 0x0000921d + 0x7*i0; } 4721*f73343faSRob Clark #define A6XX_VPC_SO_BUFFER_STRIDE__MASK 0x000003ff 4722*f73343faSRob Clark #define A6XX_VPC_SO_BUFFER_STRIDE__SHIFT 0 4723*f73343faSRob Clark static inline uint32_t A6XX_VPC_SO_BUFFER_STRIDE(uint32_t val) 4724*f73343faSRob Clark { 4725*f73343faSRob Clark return ((val >> 2) << A6XX_VPC_SO_BUFFER_STRIDE__SHIFT) & A6XX_VPC_SO_BUFFER_STRIDE__MASK; 4726*f73343faSRob Clark } 47272d756322SRob Clark 47282d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; } 4729c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_OFFSET__MASK 0xfffffffc 4730c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_OFFSET__SHIFT 2 4731c28c82e9SRob Clark static inline uint32_t A6XX_VPC_SO_BUFFER_OFFSET(uint32_t val) 4732c28c82e9SRob Clark { 4733c28c82e9SRob Clark return ((val >> 2) << A6XX_VPC_SO_BUFFER_OFFSET__SHIFT) & A6XX_VPC_SO_BUFFER_OFFSET__MASK; 4734c28c82e9SRob Clark } 4735c28c82e9SRob Clark 4736c28c82e9SRob Clark static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0) { return 0x0000921f + 0x7*i0; } 4737c28c82e9SRob Clark #define A6XX_VPC_SO_FLUSH_BASE__MASK 0xffffffff 4738c28c82e9SRob Clark #define A6XX_VPC_SO_FLUSH_BASE__SHIFT 0 4739c28c82e9SRob Clark static inline uint32_t A6XX_VPC_SO_FLUSH_BASE(uint32_t val) 4740c28c82e9SRob Clark { 4741c28c82e9SRob Clark return ((val) << A6XX_VPC_SO_FLUSH_BASE__SHIFT) & A6XX_VPC_SO_FLUSH_BASE__MASK; 4742c28c82e9SRob Clark } 47432d756322SRob Clark 4744c28c82e9SRob Clark #define REG_A6XX_VPC_POINT_COORD_INVERT 0x00009236 4745c28c82e9SRob Clark #define A6XX_VPC_POINT_COORD_INVERT_INVERT 0x00000001 47462d756322SRob Clark 47472d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9300 0x00009300 47482d756322SRob Clark 4749c28c82e9SRob Clark #define REG_A6XX_VPC_VS_PACK 0x00009301 4750c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK 0x000000ff 4751c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT 0 4752c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_PACK_STRIDE_IN_VPC(uint32_t val) 47532d756322SRob Clark { 4754c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK; 47552d756322SRob Clark } 4756c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_POSITIONLOC__MASK 0x0000ff00 4757c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT 8 4758c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_PACK_POSITIONLOC(uint32_t val) 47592d756322SRob Clark { 4760c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_VS_PACK_POSITIONLOC__MASK; 47612d756322SRob Clark } 4762c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_PSIZELOC__MASK 0x00ff0000 4763c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_PSIZELOC__SHIFT 16 4764c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_PACK_PSIZELOC(uint32_t val) 47652d756322SRob Clark { 4766c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_VS_PACK_PSIZELOC__MASK; 4767c28c82e9SRob Clark } 4768cc4c26d4SRob Clark #define A6XX_VPC_VS_PACK_EXTRAPOS__MASK 0x0f000000 4769cc4c26d4SRob Clark #define A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT 24 4770cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_VS_PACK_EXTRAPOS(uint32_t val) 4771c28c82e9SRob Clark { 4772cc4c26d4SRob Clark return ((val) << A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_VS_PACK_EXTRAPOS__MASK; 4773c28c82e9SRob Clark } 4774c28c82e9SRob Clark 4775c28c82e9SRob Clark #define REG_A6XX_VPC_GS_PACK 0x00009302 4776c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK 0x000000ff 4777c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT 0 4778c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_PACK_STRIDE_IN_VPC(uint32_t val) 4779c28c82e9SRob Clark { 4780c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK; 4781c28c82e9SRob Clark } 4782c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_POSITIONLOC__MASK 0x0000ff00 4783c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT 8 4784c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_PACK_POSITIONLOC(uint32_t val) 4785c28c82e9SRob Clark { 4786c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_GS_PACK_POSITIONLOC__MASK; 4787c28c82e9SRob Clark } 4788c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_PSIZELOC__MASK 0x00ff0000 4789c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_PSIZELOC__SHIFT 16 4790c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_PACK_PSIZELOC(uint32_t val) 4791c28c82e9SRob Clark { 4792c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_GS_PACK_PSIZELOC__MASK; 4793c28c82e9SRob Clark } 4794cc4c26d4SRob Clark #define A6XX_VPC_GS_PACK_EXTRAPOS__MASK 0x0f000000 4795cc4c26d4SRob Clark #define A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT 24 4796cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_GS_PACK_EXTRAPOS(uint32_t val) 4797c28c82e9SRob Clark { 4798cc4c26d4SRob Clark return ((val) << A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_GS_PACK_EXTRAPOS__MASK; 4799c28c82e9SRob Clark } 4800c28c82e9SRob Clark 4801c28c82e9SRob Clark #define REG_A6XX_VPC_DS_PACK 0x00009303 4802c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK 0x000000ff 4803c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT 0 4804c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_PACK_STRIDE_IN_VPC(uint32_t val) 4805c28c82e9SRob Clark { 4806c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK; 4807c28c82e9SRob Clark } 4808c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_POSITIONLOC__MASK 0x0000ff00 4809c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT 8 4810c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_PACK_POSITIONLOC(uint32_t val) 4811c28c82e9SRob Clark { 4812c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_DS_PACK_POSITIONLOC__MASK; 4813c28c82e9SRob Clark } 4814c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_PSIZELOC__MASK 0x00ff0000 4815c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_PSIZELOC__SHIFT 16 4816c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_PACK_PSIZELOC(uint32_t val) 4817c28c82e9SRob Clark { 4818c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_DS_PACK_PSIZELOC__MASK; 4819c28c82e9SRob Clark } 4820cc4c26d4SRob Clark #define A6XX_VPC_DS_PACK_EXTRAPOS__MASK 0x0f000000 4821cc4c26d4SRob Clark #define A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT 24 4822cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_DS_PACK_EXTRAPOS(uint32_t val) 4823c28c82e9SRob Clark { 4824cc4c26d4SRob Clark return ((val) << A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_DS_PACK_EXTRAPOS__MASK; 48252d756322SRob Clark } 48262d756322SRob Clark 48272d756322SRob Clark #define REG_A6XX_VPC_CNTL_0 0x00009304 48282d756322SRob Clark #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK 0x000000ff 48292d756322SRob Clark #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT 0 48302d756322SRob Clark static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val) 48312d756322SRob Clark { 48322d756322SRob Clark return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK; 48332d756322SRob Clark } 4834c28c82e9SRob Clark #define A6XX_VPC_CNTL_0_PRIMIDLOC__MASK 0x0000ff00 4835c28c82e9SRob Clark #define A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT 8 4836c28c82e9SRob Clark static inline uint32_t A6XX_VPC_CNTL_0_PRIMIDLOC(uint32_t val) 4837c28c82e9SRob Clark { 4838c28c82e9SRob Clark return ((val) << A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT) & A6XX_VPC_CNTL_0_PRIMIDLOC__MASK; 4839c28c82e9SRob Clark } 48402d756322SRob Clark #define A6XX_VPC_CNTL_0_VARYING 0x00010000 4841cc4c26d4SRob Clark #define A6XX_VPC_CNTL_0_VIEWIDLOC__MASK 0xff000000 4842cc4c26d4SRob Clark #define A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT 24 4843cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_CNTL_0_VIEWIDLOC(uint32_t val) 4844c28c82e9SRob Clark { 4845cc4c26d4SRob Clark return ((val) << A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT) & A6XX_VPC_CNTL_0_VIEWIDLOC__MASK; 4846c28c82e9SRob Clark } 48472d756322SRob Clark 4848cc4c26d4SRob Clark #define REG_A6XX_VPC_SO_STREAM_CNTL 0x00009305 4849cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK 0x00000007 4850cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT 0 4851cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(uint32_t val) 4852c28c82e9SRob Clark { 4853cc4c26d4SRob Clark return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK; 4854cc4c26d4SRob Clark } 4855cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK 0x00000038 4856cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT 3 4857cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(uint32_t val) 4858cc4c26d4SRob Clark { 4859cc4c26d4SRob Clark return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK; 4860cc4c26d4SRob Clark } 4861cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK 0x000001c0 4862cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT 6 4863cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(uint32_t val) 4864cc4c26d4SRob Clark { 4865cc4c26d4SRob Clark return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK; 4866cc4c26d4SRob Clark } 4867cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK 0x00000e00 4868cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT 9 4869cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(uint32_t val) 4870cc4c26d4SRob Clark { 4871cc4c26d4SRob Clark return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK; 4872cc4c26d4SRob Clark } 4873cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK 0x00078000 4874cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT 15 4875cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val) 4876cc4c26d4SRob Clark { 4877cc4c26d4SRob Clark return ((val) << A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK; 4878c28c82e9SRob Clark } 48792d756322SRob Clark 4880c28c82e9SRob Clark #define REG_A6XX_VPC_SO_DISABLE 0x00009306 4881c28c82e9SRob Clark #define A6XX_VPC_SO_DISABLE_DISABLE 0x00000001 4882a69c5ed2SRob Clark 4883*f73343faSRob Clark #define REG_A6XX_VPC_DBG_ECO_CNTL 0x00009600 48842d756322SRob Clark 4885c28c82e9SRob Clark #define REG_A6XX_VPC_ADDR_MODE_CNTL 0x00009601 4886c28c82e9SRob Clark 48872d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9602 0x00009602 48882d756322SRob Clark 4889c28c82e9SRob Clark #define REG_A6XX_VPC_UNKNOWN_9603 0x00009603 4890c28c82e9SRob Clark 4891cc4c26d4SRob Clark static inline uint32_t REG_A6XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) { return 0x00009604 + 0x1*i0; } 4892c28c82e9SRob Clark 4893*f73343faSRob Clark static inline uint32_t REG_A7XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) { return 0x0000960b + 0x1*i0; } 4894*f73343faSRob Clark 4895c28c82e9SRob Clark #define REG_A6XX_PC_TESS_NUM_VERTEX 0x00009800 4896c28c82e9SRob Clark 4897cc4c26d4SRob Clark #define REG_A6XX_PC_HS_INPUT_SIZE 0x00009801 4898cc4c26d4SRob Clark #define A6XX_PC_HS_INPUT_SIZE_SIZE__MASK 0x000007ff 4899cc4c26d4SRob Clark #define A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT 0 4900cc4c26d4SRob Clark static inline uint32_t A6XX_PC_HS_INPUT_SIZE_SIZE(uint32_t val) 4901c28c82e9SRob Clark { 4902cc4c26d4SRob Clark return ((val) << A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT) & A6XX_PC_HS_INPUT_SIZE_SIZE__MASK; 4903c28c82e9SRob Clark } 4904cc4c26d4SRob Clark #define A6XX_PC_HS_INPUT_SIZE_UNK13__MASK 0x00002000 4905cc4c26d4SRob Clark #define A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT 13 4906cc4c26d4SRob Clark static inline uint32_t A6XX_PC_HS_INPUT_SIZE_UNK13(uint32_t val) 4907c28c82e9SRob Clark { 4908cc4c26d4SRob Clark return ((val) << A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT) & A6XX_PC_HS_INPUT_SIZE_UNK13__MASK; 4909c28c82e9SRob Clark } 4910c28c82e9SRob Clark 4911c28c82e9SRob Clark #define REG_A6XX_PC_TESS_CNTL 0x00009802 4912c28c82e9SRob Clark #define A6XX_PC_TESS_CNTL_SPACING__MASK 0x00000003 4913c28c82e9SRob Clark #define A6XX_PC_TESS_CNTL_SPACING__SHIFT 0 4914c28c82e9SRob Clark static inline uint32_t A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val) 4915c28c82e9SRob Clark { 4916c28c82e9SRob Clark return ((val) << A6XX_PC_TESS_CNTL_SPACING__SHIFT) & A6XX_PC_TESS_CNTL_SPACING__MASK; 4917c28c82e9SRob Clark } 4918c28c82e9SRob Clark #define A6XX_PC_TESS_CNTL_OUTPUT__MASK 0x0000000c 4919c28c82e9SRob Clark #define A6XX_PC_TESS_CNTL_OUTPUT__SHIFT 2 4920c28c82e9SRob Clark static inline uint32_t A6XX_PC_TESS_CNTL_OUTPUT(enum a6xx_tess_output val) 4921c28c82e9SRob Clark { 4922c28c82e9SRob Clark return ((val) << A6XX_PC_TESS_CNTL_OUTPUT__SHIFT) & A6XX_PC_TESS_CNTL_OUTPUT__MASK; 4923c28c82e9SRob Clark } 49242d756322SRob Clark 49252d756322SRob Clark #define REG_A6XX_PC_RESTART_INDEX 0x00009803 49262d756322SRob Clark 49272d756322SRob Clark #define REG_A6XX_PC_MODE_CNTL 0x00009804 49282d756322SRob Clark 492957cfe41cSRob Clark #define REG_A6XX_PC_POWER_CNTL 0x00009805 49302d756322SRob Clark 4931c28c82e9SRob Clark #define REG_A6XX_PC_PRIMID_PASSTHRU 0x00009806 4932c28c82e9SRob Clark 493357cfe41cSRob Clark #define REG_A6XX_PC_SO_STREAM_CNTL 0x00009808 4934*f73343faSRob Clark #define A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__MASK 0x00078000 4935*f73343faSRob Clark #define A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT 15 4936*f73343faSRob Clark static inline uint32_t A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val) 4937*f73343faSRob Clark { 4938*f73343faSRob Clark return ((val) << A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__MASK; 4939*f73343faSRob Clark } 494057cfe41cSRob Clark 494157cfe41cSRob Clark #define REG_A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL 0x0000980a 494257cfe41cSRob Clark #define A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN 0x00000001 494357cfe41cSRob Clark 4944c28c82e9SRob Clark #define REG_A6XX_PC_DRAW_CMD 0x00009840 4945c28c82e9SRob Clark #define A6XX_PC_DRAW_CMD_STATE_ID__MASK 0x000000ff 4946c28c82e9SRob Clark #define A6XX_PC_DRAW_CMD_STATE_ID__SHIFT 0 4947c28c82e9SRob Clark static inline uint32_t A6XX_PC_DRAW_CMD_STATE_ID(uint32_t val) 4948c28c82e9SRob Clark { 4949c28c82e9SRob Clark return ((val) << A6XX_PC_DRAW_CMD_STATE_ID__SHIFT) & A6XX_PC_DRAW_CMD_STATE_ID__MASK; 4950c28c82e9SRob Clark } 4951c28c82e9SRob Clark 4952c28c82e9SRob Clark #define REG_A6XX_PC_DISPATCH_CMD 0x00009841 4953c28c82e9SRob Clark #define A6XX_PC_DISPATCH_CMD_STATE_ID__MASK 0x000000ff 4954c28c82e9SRob Clark #define A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT 0 4955c28c82e9SRob Clark static inline uint32_t A6XX_PC_DISPATCH_CMD_STATE_ID(uint32_t val) 4956c28c82e9SRob Clark { 4957c28c82e9SRob Clark return ((val) << A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_PC_DISPATCH_CMD_STATE_ID__MASK; 4958c28c82e9SRob Clark } 4959c28c82e9SRob Clark 4960c28c82e9SRob Clark #define REG_A6XX_PC_EVENT_CMD 0x00009842 4961c28c82e9SRob Clark #define A6XX_PC_EVENT_CMD_STATE_ID__MASK 0x00ff0000 4962c28c82e9SRob Clark #define A6XX_PC_EVENT_CMD_STATE_ID__SHIFT 16 4963c28c82e9SRob Clark static inline uint32_t A6XX_PC_EVENT_CMD_STATE_ID(uint32_t val) 4964c28c82e9SRob Clark { 4965c28c82e9SRob Clark return ((val) << A6XX_PC_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_EVENT_CMD_STATE_ID__MASK; 4966c28c82e9SRob Clark } 4967c28c82e9SRob Clark #define A6XX_PC_EVENT_CMD_EVENT__MASK 0x0000007f 4968c28c82e9SRob Clark #define A6XX_PC_EVENT_CMD_EVENT__SHIFT 0 4969c28c82e9SRob Clark static inline uint32_t A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val) 4970c28c82e9SRob Clark { 4971c28c82e9SRob Clark return ((val) << A6XX_PC_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_EVENT_CMD_EVENT__MASK; 4972c28c82e9SRob Clark } 4973c28c82e9SRob Clark 4974cc4c26d4SRob Clark #define REG_A6XX_PC_MARKER 0x00009880 4975cc4c26d4SRob Clark 4976c28c82e9SRob Clark #define REG_A6XX_PC_POLYGON_MODE 0x00009981 4977c28c82e9SRob Clark #define A6XX_PC_POLYGON_MODE_MODE__MASK 0x00000003 4978c28c82e9SRob Clark #define A6XX_PC_POLYGON_MODE_MODE__SHIFT 0 4979c28c82e9SRob Clark static inline uint32_t A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) 4980c28c82e9SRob Clark { 4981c28c82e9SRob Clark return ((val) << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK; 4982c28c82e9SRob Clark } 4983a69c5ed2SRob Clark 4984cc4c26d4SRob Clark #define REG_A6XX_PC_RASTER_CNTL 0x00009980 4985cc4c26d4SRob Clark #define A6XX_PC_RASTER_CNTL_STREAM__MASK 0x00000003 4986cc4c26d4SRob Clark #define A6XX_PC_RASTER_CNTL_STREAM__SHIFT 0 4987cc4c26d4SRob Clark static inline uint32_t A6XX_PC_RASTER_CNTL_STREAM(uint32_t val) 4988cc4c26d4SRob Clark { 4989cc4c26d4SRob Clark return ((val) << A6XX_PC_RASTER_CNTL_STREAM__SHIFT) & A6XX_PC_RASTER_CNTL_STREAM__MASK; 4990cc4c26d4SRob Clark } 4991cc4c26d4SRob Clark #define A6XX_PC_RASTER_CNTL_DISCARD 0x00000004 4992a69c5ed2SRob Clark 49932d756322SRob Clark #define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00 49942d756322SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001 49952d756322SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002 4996c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_0_TESS_UPPER_LEFT_DOMAIN_ORIGIN 0x00000004 4997c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_0_UNK3 0x00000008 49982d756322SRob Clark 4999c28c82e9SRob Clark #define REG_A6XX_PC_VS_OUT_CNTL 0x00009b01 5000c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff 5001c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 5002c28c82e9SRob Clark static inline uint32_t A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) 50032d756322SRob Clark { 5004c28c82e9SRob Clark return ((val) << A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK; 50052d756322SRob Clark } 5006c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_PSIZE 0x00000100 5007c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_LAYER 0x00000200 5008c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_VIEW 0x00000400 5009c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID 0x00000800 5010c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 5011c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT 16 5012c28c82e9SRob Clark static inline uint32_t A6XX_PC_VS_OUT_CNTL_CLIP_MASK(uint32_t val) 5013c28c82e9SRob Clark { 5014c28c82e9SRob Clark return ((val) << A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK; 5015c28c82e9SRob Clark } 50162d756322SRob Clark 5017c28c82e9SRob Clark #define REG_A6XX_PC_GS_OUT_CNTL 0x00009b02 5018c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff 5019c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 5020c28c82e9SRob Clark static inline uint32_t A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) 5021c28c82e9SRob Clark { 5022c28c82e9SRob Clark return ((val) << A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK; 5023c28c82e9SRob Clark } 5024c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_PSIZE 0x00000100 5025c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_LAYER 0x00000200 5026c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_VIEW 0x00000400 5027c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID 0x00000800 5028c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 5029c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT 16 5030c28c82e9SRob Clark static inline uint32_t A6XX_PC_GS_OUT_CNTL_CLIP_MASK(uint32_t val) 5031c28c82e9SRob Clark { 5032c28c82e9SRob Clark return ((val) << A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK; 5033c28c82e9SRob Clark } 5034c28c82e9SRob Clark 503557cfe41cSRob Clark #define REG_A6XX_PC_HS_OUT_CNTL 0x00009b03 503657cfe41cSRob Clark #define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff 503757cfe41cSRob Clark #define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 503857cfe41cSRob Clark static inline uint32_t A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) 503957cfe41cSRob Clark { 504057cfe41cSRob Clark return ((val) << A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK; 504157cfe41cSRob Clark } 504257cfe41cSRob Clark #define A6XX_PC_HS_OUT_CNTL_PSIZE 0x00000100 504357cfe41cSRob Clark #define A6XX_PC_HS_OUT_CNTL_LAYER 0x00000200 504457cfe41cSRob Clark #define A6XX_PC_HS_OUT_CNTL_VIEW 0x00000400 504557cfe41cSRob Clark #define A6XX_PC_HS_OUT_CNTL_PRIMITIVE_ID 0x00000800 504657cfe41cSRob Clark #define A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 504757cfe41cSRob Clark #define A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT 16 504857cfe41cSRob Clark static inline uint32_t A6XX_PC_HS_OUT_CNTL_CLIP_MASK(uint32_t val) 504957cfe41cSRob Clark { 505057cfe41cSRob Clark return ((val) << A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK; 505157cfe41cSRob Clark } 5052c28c82e9SRob Clark 5053c28c82e9SRob Clark #define REG_A6XX_PC_DS_OUT_CNTL 0x00009b04 5054c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff 5055c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 5056c28c82e9SRob Clark static inline uint32_t A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) 5057c28c82e9SRob Clark { 5058c28c82e9SRob Clark return ((val) << A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK; 5059c28c82e9SRob Clark } 5060c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_PSIZE 0x00000100 5061c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_LAYER 0x00000200 5062c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_VIEW 0x00000400 5063c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID 0x00000800 5064c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 5065c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT 16 5066c28c82e9SRob Clark static inline uint32_t A6XX_PC_DS_OUT_CNTL_CLIP_MASK(uint32_t val) 5067c28c82e9SRob Clark { 5068c28c82e9SRob Clark return ((val) << A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK; 5069c28c82e9SRob Clark } 5070c28c82e9SRob Clark 5071c28c82e9SRob Clark #define REG_A6XX_PC_PRIMITIVE_CNTL_5 0x00009b05 5072c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK 0x000000ff 5073c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT 0 5074c28c82e9SRob Clark static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val) 5075c28c82e9SRob Clark { 5076c28c82e9SRob Clark return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK; 5077c28c82e9SRob Clark } 5078c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK 0x00007c00 5079c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT 10 5080c28c82e9SRob Clark static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val) 5081c28c82e9SRob Clark { 5082c28c82e9SRob Clark return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK; 5083c28c82e9SRob Clark } 508457cfe41cSRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_LINELENGTHEN 0x00008000 5085c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK 0x00030000 5086c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT 16 5087c28c82e9SRob Clark static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val) 5088c28c82e9SRob Clark { 5089c28c82e9SRob Clark return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK; 5090c28c82e9SRob Clark } 5091c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK 0x00040000 5092c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT 18 5093c28c82e9SRob Clark static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_UNK18(uint32_t val) 5094c28c82e9SRob Clark { 5095c28c82e9SRob Clark return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK; 5096c28c82e9SRob Clark } 5097c28c82e9SRob Clark 5098c28c82e9SRob Clark #define REG_A6XX_PC_PRIMITIVE_CNTL_6 0x00009b06 5099c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK 0x000007ff 5100c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT 0 5101c28c82e9SRob Clark static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(uint32_t val) 5102c28c82e9SRob Clark { 5103c28c82e9SRob Clark return ((val) << A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK; 5104c28c82e9SRob Clark } 51052d756322SRob Clark 5106cc4c26d4SRob Clark #define REG_A6XX_PC_MULTIVIEW_CNTL 0x00009b07 5107cc4c26d4SRob Clark #define A6XX_PC_MULTIVIEW_CNTL_ENABLE 0x00000001 5108cc4c26d4SRob Clark #define A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002 5109cc4c26d4SRob Clark #define A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c 5110cc4c26d4SRob Clark #define A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT 2 5111cc4c26d4SRob Clark static inline uint32_t A6XX_PC_MULTIVIEW_CNTL_VIEWS(uint32_t val) 5112cc4c26d4SRob Clark { 5113cc4c26d4SRob Clark return ((val) << A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK; 5114cc4c26d4SRob Clark } 51152d756322SRob Clark 5116cc4c26d4SRob Clark #define REG_A6XX_PC_MULTIVIEW_MASK 0x00009b08 5117c28c82e9SRob Clark 5118c28c82e9SRob Clark #define REG_A6XX_PC_2D_EVENT_CMD 0x00009c00 5119c28c82e9SRob Clark #define A6XX_PC_2D_EVENT_CMD_EVENT__MASK 0x0000007f 5120c28c82e9SRob Clark #define A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT 0 5121c28c82e9SRob Clark static inline uint32_t A6XX_PC_2D_EVENT_CMD_EVENT(enum vgt_event_type val) 5122c28c82e9SRob Clark { 5123c28c82e9SRob Clark return ((val) << A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_2D_EVENT_CMD_EVENT__MASK; 5124c28c82e9SRob Clark } 5125c28c82e9SRob Clark #define A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00 5126c28c82e9SRob Clark #define A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT 8 5127c28c82e9SRob Clark static inline uint32_t A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val) 5128c28c82e9SRob Clark { 5129c28c82e9SRob Clark return ((val) << A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK; 5130c28c82e9SRob Clark } 5131c28c82e9SRob Clark 5132c28c82e9SRob Clark #define REG_A6XX_PC_DBG_ECO_CNTL 0x00009e00 5133c28c82e9SRob Clark 5134c28c82e9SRob Clark #define REG_A6XX_PC_ADDR_MODE_CNTL 0x00009e01 5135c28c82e9SRob Clark 5136cc4c26d4SRob Clark #define REG_A6XX_PC_DRAW_INDX_BASE 0x00009e04 51372d756322SRob Clark 5138cc4c26d4SRob Clark #define REG_A6XX_PC_DRAW_FIRST_INDX 0x00009e06 5139cc4c26d4SRob Clark 5140cc4c26d4SRob Clark #define REG_A6XX_PC_DRAW_MAX_INDICES 0x00009e07 51412d756322SRob Clark 5142c28c82e9SRob Clark #define REG_A6XX_PC_TESSFACTOR_ADDR 0x00009e08 5143c28c82e9SRob Clark #define A6XX_PC_TESSFACTOR_ADDR__MASK 0xffffffff 5144c28c82e9SRob Clark #define A6XX_PC_TESSFACTOR_ADDR__SHIFT 0 5145c28c82e9SRob Clark static inline uint32_t A6XX_PC_TESSFACTOR_ADDR(uint32_t val) 5146c28c82e9SRob Clark { 5147c28c82e9SRob Clark return ((val) << A6XX_PC_TESSFACTOR_ADDR__SHIFT) & A6XX_PC_TESSFACTOR_ADDR__MASK; 5148c28c82e9SRob Clark } 5149c28c82e9SRob Clark 5150cc4c26d4SRob Clark #define REG_A6XX_PC_DRAW_INITIATOR 0x00009e0b 5151cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f 5152cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 5153cc4c26d4SRob Clark static inline uint32_t A6XX_PC_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) 5154cc4c26d4SRob Clark { 5155cc4c26d4SRob Clark return ((val) << A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK; 5156cc4c26d4SRob Clark } 5157cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 5158cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 5159cc4c26d4SRob Clark static inline uint32_t A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) 5160cc4c26d4SRob Clark { 5161cc4c26d4SRob Clark return ((val) << A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK; 5162cc4c26d4SRob Clark } 5163cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK 0x00000300 5164cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT 8 5165cc4c26d4SRob Clark static inline uint32_t A6XX_PC_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) 5166cc4c26d4SRob Clark { 5167cc4c26d4SRob Clark return ((val) << A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT) & A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK; 5168cc4c26d4SRob Clark } 5169cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000c00 5170cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT 10 5171cc4c26d4SRob Clark static inline uint32_t A6XX_PC_DRAW_INITIATOR_INDEX_SIZE(enum a4xx_index_size val) 5172cc4c26d4SRob Clark { 5173cc4c26d4SRob Clark return ((val) << A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK; 5174cc4c26d4SRob Clark } 5175cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK 0x00003000 5176cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT 12 5177cc4c26d4SRob Clark static inline uint32_t A6XX_PC_DRAW_INITIATOR_PATCH_TYPE(enum a6xx_patch_type val) 5178cc4c26d4SRob Clark { 5179cc4c26d4SRob Clark return ((val) << A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK; 5180cc4c26d4SRob Clark } 5181cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_GS_ENABLE 0x00010000 5182cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_TESS_ENABLE 0x00020000 5183cc4c26d4SRob Clark 5184cc4c26d4SRob Clark #define REG_A6XX_PC_DRAW_NUM_INSTANCES 0x00009e0c 5185cc4c26d4SRob Clark 5186cc4c26d4SRob Clark #define REG_A6XX_PC_DRAW_NUM_INDICES 0x00009e0d 5187cc4c26d4SRob Clark 5188c28c82e9SRob Clark #define REG_A6XX_PC_VSTREAM_CONTROL 0x00009e11 5189c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_UNK0__MASK 0x0000ffff 5190c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT 0 5191c28c82e9SRob Clark static inline uint32_t A6XX_PC_VSTREAM_CONTROL_UNK0(uint32_t val) 5192c28c82e9SRob Clark { 5193c28c82e9SRob Clark return ((val) << A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT) & A6XX_PC_VSTREAM_CONTROL_UNK0__MASK; 5194c28c82e9SRob Clark } 5195c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK 0x003f0000 5196c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT 16 5197c28c82e9SRob Clark static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_SIZE(uint32_t val) 5198c28c82e9SRob Clark { 5199c28c82e9SRob Clark return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK; 5200c28c82e9SRob Clark } 5201c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK 0x07c00000 5202c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT 22 5203c28c82e9SRob Clark static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_N(uint32_t val) 5204c28c82e9SRob Clark { 5205c28c82e9SRob Clark return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK; 5206c28c82e9SRob Clark } 5207c28c82e9SRob Clark 5208c28c82e9SRob Clark #define REG_A6XX_PC_BIN_PRIM_STRM 0x00009e12 5209c28c82e9SRob Clark #define A6XX_PC_BIN_PRIM_STRM__MASK 0xffffffff 5210c28c82e9SRob Clark #define A6XX_PC_BIN_PRIM_STRM__SHIFT 0 5211c28c82e9SRob Clark static inline uint32_t A6XX_PC_BIN_PRIM_STRM(uint32_t val) 5212c28c82e9SRob Clark { 5213c28c82e9SRob Clark return ((val) << A6XX_PC_BIN_PRIM_STRM__SHIFT) & A6XX_PC_BIN_PRIM_STRM__MASK; 5214c28c82e9SRob Clark } 5215c28c82e9SRob Clark 5216c28c82e9SRob Clark #define REG_A6XX_PC_BIN_DRAW_STRM 0x00009e14 5217c28c82e9SRob Clark #define A6XX_PC_BIN_DRAW_STRM__MASK 0xffffffff 5218c28c82e9SRob Clark #define A6XX_PC_BIN_DRAW_STRM__SHIFT 0 5219c28c82e9SRob Clark static inline uint32_t A6XX_PC_BIN_DRAW_STRM(uint32_t val) 5220c28c82e9SRob Clark { 5221c28c82e9SRob Clark return ((val) << A6XX_PC_BIN_DRAW_STRM__SHIFT) & A6XX_PC_BIN_DRAW_STRM__MASK; 5222c28c82e9SRob Clark } 5223c28c82e9SRob Clark 5224cc4c26d4SRob Clark #define REG_A6XX_PC_VISIBILITY_OVERRIDE 0x00009e1c 5225cc4c26d4SRob Clark #define A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE 0x00000001 5226c28c82e9SRob Clark 5227cc4c26d4SRob Clark static inline uint32_t REG_A6XX_PC_PERFCTR_PC_SEL(uint32_t i0) { return 0x00009e34 + 0x1*i0; } 5228c28c82e9SRob Clark 5229*f73343faSRob Clark static inline uint32_t REG_A7XX_PC_PERFCTR_PC_SEL(uint32_t i0) { return 0x00009e42 + 0x1*i0; } 5230*f73343faSRob Clark 52312d756322SRob Clark #define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72 52322d756322SRob Clark 52332d756322SRob Clark #define REG_A6XX_VFD_CONTROL_0 0x0000a000 5234c28c82e9SRob Clark #define A6XX_VFD_CONTROL_0_FETCH_CNT__MASK 0x0000003f 5235c28c82e9SRob Clark #define A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT 0 5236c28c82e9SRob Clark static inline uint32_t A6XX_VFD_CONTROL_0_FETCH_CNT(uint32_t val) 52372d756322SRob Clark { 5238c28c82e9SRob Clark return ((val) << A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT) & A6XX_VFD_CONTROL_0_FETCH_CNT__MASK; 5239c28c82e9SRob Clark } 5240c28c82e9SRob Clark #define A6XX_VFD_CONTROL_0_DECODE_CNT__MASK 0x00003f00 5241c28c82e9SRob Clark #define A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT 8 5242c28c82e9SRob Clark static inline uint32_t A6XX_VFD_CONTROL_0_DECODE_CNT(uint32_t val) 5243c28c82e9SRob Clark { 5244c28c82e9SRob Clark return ((val) << A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT) & A6XX_VFD_CONTROL_0_DECODE_CNT__MASK; 52452d756322SRob Clark } 52462d756322SRob Clark 52472d756322SRob Clark #define REG_A6XX_VFD_CONTROL_1 0x0000a001 52482d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff 52492d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0 52502d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 52512d756322SRob Clark { 52522d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VTX__MASK; 52532d756322SRob Clark } 52542d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00 52552d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4INST__SHIFT 8 52562d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 52572d756322SRob Clark { 52582d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK; 52592d756322SRob Clark } 52602d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000 52612d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16 52622d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val) 52632d756322SRob Clark { 52642d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK; 52652d756322SRob Clark } 5266cc4c26d4SRob Clark #define A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK 0xff000000 5267cc4c26d4SRob Clark #define A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT 24 5268cc4c26d4SRob Clark static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VIEWID(uint32_t val) 5269cc4c26d4SRob Clark { 5270cc4c26d4SRob Clark return ((val) << A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK; 5271cc4c26d4SRob Clark } 52722d756322SRob Clark 52732d756322SRob Clark #define REG_A6XX_VFD_CONTROL_2 0x0000a002 527457cfe41cSRob Clark #define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK 0x000000ff 527557cfe41cSRob Clark #define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT 0 527657cfe41cSRob Clark static inline uint32_t A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID(uint32_t val) 52772d756322SRob Clark { 527857cfe41cSRob Clark return ((val) << A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK; 5279c28c82e9SRob Clark } 5280c28c82e9SRob Clark #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK 0x0000ff00 5281c28c82e9SRob Clark #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT 8 5282c28c82e9SRob Clark static inline uint32_t A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val) 5283c28c82e9SRob Clark { 5284c28c82e9SRob Clark return ((val) << A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK; 52852d756322SRob Clark } 52862d756322SRob Clark 52872d756322SRob Clark #define REG_A6XX_VFD_CONTROL_3 0x0000a003 528857cfe41cSRob Clark #define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK 0x000000ff 528957cfe41cSRob Clark #define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT 0 529057cfe41cSRob Clark static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPRIMID(uint32_t val) 5291cc4c26d4SRob Clark { 529257cfe41cSRob Clark return ((val) << A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK; 5293cc4c26d4SRob Clark } 529457cfe41cSRob Clark #define A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK 0x0000ff00 529557cfe41cSRob Clark #define A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT 8 529657cfe41cSRob Clark static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID(uint32_t val) 52972d756322SRob Clark { 529857cfe41cSRob Clark return ((val) << A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK; 52992d756322SRob Clark } 53002d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000 53012d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16 53022d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) 53032d756322SRob Clark { 53042d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSX__MASK; 53052d756322SRob Clark } 53062d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000 53072d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24 53082d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) 53092d756322SRob Clark { 53102d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK; 53112d756322SRob Clark } 53122d756322SRob Clark 53132d756322SRob Clark #define REG_A6XX_VFD_CONTROL_4 0x0000a004 5314cc4c26d4SRob Clark #define A6XX_VFD_CONTROL_4_UNK0__MASK 0x000000ff 5315cc4c26d4SRob Clark #define A6XX_VFD_CONTROL_4_UNK0__SHIFT 0 5316cc4c26d4SRob Clark static inline uint32_t A6XX_VFD_CONTROL_4_UNK0(uint32_t val) 5317cc4c26d4SRob Clark { 5318cc4c26d4SRob Clark return ((val) << A6XX_VFD_CONTROL_4_UNK0__SHIFT) & A6XX_VFD_CONTROL_4_UNK0__MASK; 5319cc4c26d4SRob Clark } 53202d756322SRob Clark 53212d756322SRob Clark #define REG_A6XX_VFD_CONTROL_5 0x0000a005 5322c28c82e9SRob Clark #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK 0x000000ff 5323c28c82e9SRob Clark #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT 0 5324c28c82e9SRob Clark static inline uint32_t A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val) 5325c28c82e9SRob Clark { 5326c28c82e9SRob Clark return ((val) << A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT) & A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK; 5327c28c82e9SRob Clark } 5328cc4c26d4SRob Clark #define A6XX_VFD_CONTROL_5_UNK8__MASK 0x0000ff00 5329cc4c26d4SRob Clark #define A6XX_VFD_CONTROL_5_UNK8__SHIFT 8 5330cc4c26d4SRob Clark static inline uint32_t A6XX_VFD_CONTROL_5_UNK8(uint32_t val) 5331cc4c26d4SRob Clark { 5332cc4c26d4SRob Clark return ((val) << A6XX_VFD_CONTROL_5_UNK8__SHIFT) & A6XX_VFD_CONTROL_5_UNK8__MASK; 5333cc4c26d4SRob Clark } 53342d756322SRob Clark 53352d756322SRob Clark #define REG_A6XX_VFD_CONTROL_6 0x0000a006 5336c28c82e9SRob Clark #define A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU 0x00000001 53372d756322SRob Clark 53382d756322SRob Clark #define REG_A6XX_VFD_MODE_CNTL 0x0000a007 533957cfe41cSRob Clark #define A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK 0x00000007 534057cfe41cSRob Clark #define A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT 0 534157cfe41cSRob Clark static inline uint32_t A6XX_VFD_MODE_CNTL_RENDER_MODE(enum a6xx_render_mode val) 534257cfe41cSRob Clark { 534357cfe41cSRob Clark return ((val) << A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT) & A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK; 534457cfe41cSRob Clark } 53452d756322SRob Clark 5346cc4c26d4SRob Clark #define REG_A6XX_VFD_MULTIVIEW_CNTL 0x0000a008 5347cc4c26d4SRob Clark #define A6XX_VFD_MULTIVIEW_CNTL_ENABLE 0x00000001 5348cc4c26d4SRob Clark #define A6XX_VFD_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002 5349cc4c26d4SRob Clark #define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c 5350cc4c26d4SRob Clark #define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT 2 5351cc4c26d4SRob Clark static inline uint32_t A6XX_VFD_MULTIVIEW_CNTL_VIEWS(uint32_t val) 5352cc4c26d4SRob Clark { 5353cc4c26d4SRob Clark return ((val) << A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK; 5354cc4c26d4SRob Clark } 53552d756322SRob Clark 5356c28c82e9SRob Clark #define REG_A6XX_VFD_ADD_OFFSET 0x0000a009 5357c28c82e9SRob Clark #define A6XX_VFD_ADD_OFFSET_VERTEX 0x00000001 5358c28c82e9SRob Clark #define A6XX_VFD_ADD_OFFSET_INSTANCE 0x00000002 5359a69c5ed2SRob Clark 53602d756322SRob Clark #define REG_A6XX_VFD_INDEX_OFFSET 0x0000a00e 53612d756322SRob Clark 53622d756322SRob Clark #define REG_A6XX_VFD_INSTANCE_START_OFFSET 0x0000a00f 53632d756322SRob Clark 53642d756322SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; } 53652d756322SRob Clark 5366c28c82e9SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; } 5367cc4c26d4SRob Clark #define A6XX_VFD_FETCH_BASE__MASK 0xffffffff 5368cc4c26d4SRob Clark #define A6XX_VFD_FETCH_BASE__SHIFT 0 5369cc4c26d4SRob Clark static inline uint32_t A6XX_VFD_FETCH_BASE(uint32_t val) 5370cc4c26d4SRob Clark { 5371cc4c26d4SRob Clark return ((val) << A6XX_VFD_FETCH_BASE__SHIFT) & A6XX_VFD_FETCH_BASE__MASK; 5372cc4c26d4SRob Clark } 53732d756322SRob Clark 53742d756322SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; } 53752d756322SRob Clark 53762d756322SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; } 53772d756322SRob Clark 53782d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; } 53792d756322SRob Clark 53802d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; } 53812d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f 53822d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_IDX__SHIFT 0 53832d756322SRob Clark static inline uint32_t A6XX_VFD_DECODE_INSTR_IDX(uint32_t val) 53842d756322SRob Clark { 53852d756322SRob Clark return ((val) << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK; 53862d756322SRob Clark } 5387c28c82e9SRob Clark #define A6XX_VFD_DECODE_INSTR_OFFSET__MASK 0x0001ffe0 5388c28c82e9SRob Clark #define A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT 5 5389c28c82e9SRob Clark static inline uint32_t A6XX_VFD_DECODE_INSTR_OFFSET(uint32_t val) 5390c28c82e9SRob Clark { 5391c28c82e9SRob Clark return ((val) << A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT) & A6XX_VFD_DECODE_INSTR_OFFSET__MASK; 5392c28c82e9SRob Clark } 53932d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_INSTANCED 0x00020000 53942d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000 53952d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20 5396c28c82e9SRob Clark static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_format val) 53972d756322SRob Clark { 53982d756322SRob Clark return ((val) << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK; 53992d756322SRob Clark } 54002d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000 54012d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_SWAP__SHIFT 28 54022d756322SRob Clark static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 54032d756322SRob Clark { 54042d756322SRob Clark return ((val) << A6XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A6XX_VFD_DECODE_INSTR_SWAP__MASK; 54052d756322SRob Clark } 54062d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_UNK30 0x40000000 54072d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_FLOAT 0x80000000 54082d756322SRob Clark 54092d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; } 54102d756322SRob Clark 54112d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } 54122d756322SRob Clark 54132d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } 54142d756322SRob Clark #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f 54152d756322SRob Clark #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0 54162d756322SRob Clark static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val) 54172d756322SRob Clark { 54182d756322SRob Clark return ((val) << A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK; 54192d756322SRob Clark } 54202d756322SRob Clark #define A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0 54212d756322SRob Clark #define A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4 54222d756322SRob Clark static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) 54232d756322SRob Clark { 54242d756322SRob Clark return ((val) << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK; 54252d756322SRob Clark } 54262d756322SRob Clark 542757cfe41cSRob Clark #define REG_A6XX_VFD_POWER_CNTL 0x0000a0f8 54282d756322SRob Clark 5429cc4c26d4SRob Clark #define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601 5430cc4c26d4SRob Clark 5431cc4c26d4SRob Clark static inline uint32_t REG_A6XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) { return 0x0000a610 + 0x1*i0; } 5432cc4c26d4SRob Clark 5433*f73343faSRob Clark static inline uint32_t REG_A7XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) { return 0x0000a610 + 0x1*i0; } 5434*f73343faSRob Clark 5435c28c82e9SRob Clark #define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800 5436cc4c26d4SRob Clark #define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x00100000 5437*f73343faSRob Clark #define A6XX_SP_VS_CTRL_REG0_EARLYPREAMBLE 0x00200000 5438cc4c26d4SRob Clark #define A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 5439cc4c26d4SRob Clark #define A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 5440cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 5441cc4c26d4SRob Clark { 5442cc4c26d4SRob Clark return ((val) << A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK; 5443cc4c26d4SRob Clark } 5444c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 5445c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 5446c28c82e9SRob Clark static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 54472d756322SRob Clark { 5448c28c82e9SRob Clark return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 5449c28c82e9SRob Clark } 5450c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 5451c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 5452c28c82e9SRob Clark static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 5453c28c82e9SRob Clark { 5454c28c82e9SRob Clark return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 5455c28c82e9SRob Clark } 5456cc4c26d4SRob Clark #define A6XX_SP_VS_CTRL_REG0_UNK13 0x00002000 5457c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 5458c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14 5459c28c82e9SRob Clark static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val) 5460c28c82e9SRob Clark { 5461c28c82e9SRob Clark return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK; 5462c28c82e9SRob Clark } 5463c28c82e9SRob Clark 5464c28c82e9SRob Clark #define REG_A6XX_SP_VS_BRANCH_COND 0x0000a801 5465c28c82e9SRob Clark 5466c28c82e9SRob Clark #define REG_A6XX_SP_VS_PRIMITIVE_CNTL 0x0000a802 5467c28c82e9SRob Clark #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f 5468c28c82e9SRob Clark #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT 0 5469c28c82e9SRob Clark static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_OUT(uint32_t val) 5470c28c82e9SRob Clark { 5471c28c82e9SRob Clark return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK; 54722d756322SRob Clark } 5473cc4c26d4SRob Clark #define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0 5474cc4c26d4SRob Clark #define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6 5475cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) 5476cc4c26d4SRob Clark { 5477cc4c26d4SRob Clark return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; 5478cc4c26d4SRob Clark } 54792d756322SRob Clark 54802d756322SRob Clark static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; } 54812d756322SRob Clark 54822d756322SRob Clark static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; } 54832d756322SRob Clark #define A6XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff 54842d756322SRob Clark #define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 54852d756322SRob Clark static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 54862d756322SRob Clark { 54872d756322SRob Clark return ((val) << A6XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_A_REGID__MASK; 54882d756322SRob Clark } 54892d756322SRob Clark #define A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00 54902d756322SRob Clark #define A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8 54912d756322SRob Clark static inline uint32_t A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 54922d756322SRob Clark { 54932d756322SRob Clark return ((val) << A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 54942d756322SRob Clark } 54952d756322SRob Clark #define A6XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000 54962d756322SRob Clark #define A6XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 54972d756322SRob Clark static inline uint32_t A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 54982d756322SRob Clark { 54992d756322SRob Clark return ((val) << A6XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_B_REGID__MASK; 55002d756322SRob Clark } 55012d756322SRob Clark #define A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000 55022d756322SRob Clark #define A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24 55032d756322SRob Clark static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 55042d756322SRob Clark { 55052d756322SRob Clark return ((val) << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 55062d756322SRob Clark } 55072d756322SRob Clark 55082d756322SRob Clark static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; } 55092d756322SRob Clark 55102d756322SRob Clark static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; } 55112d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 55122d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 55132d756322SRob Clark static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 55142d756322SRob Clark { 55152d756322SRob Clark return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 55162d756322SRob Clark } 55172d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 55182d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 55192d756322SRob Clark static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 55202d756322SRob Clark { 55212d756322SRob Clark return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 55222d756322SRob Clark } 55232d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 55242d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 55252d756322SRob Clark static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 55262d756322SRob Clark { 55272d756322SRob Clark return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 55282d756322SRob Clark } 55292d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 55302d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 55312d756322SRob Clark static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 55322d756322SRob Clark { 55332d756322SRob Clark return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 55342d756322SRob Clark } 55352d756322SRob Clark 5536cc4c26d4SRob Clark #define REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET 0x0000a81b 5537a69c5ed2SRob Clark 5538cc4c26d4SRob Clark #define REG_A6XX_SP_VS_OBJ_START 0x0000a81c 5539cc4c26d4SRob Clark #define A6XX_SP_VS_OBJ_START__MASK 0xffffffff 5540cc4c26d4SRob Clark #define A6XX_SP_VS_OBJ_START__SHIFT 0 5541cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_OBJ_START(uint32_t val) 5542cc4c26d4SRob Clark { 5543cc4c26d4SRob Clark return ((val) << A6XX_SP_VS_OBJ_START__SHIFT) & A6XX_SP_VS_OBJ_START__MASK; 5544cc4c26d4SRob Clark } 55452d756322SRob Clark 5546cc4c26d4SRob Clark #define REG_A6XX_SP_VS_PVT_MEM_PARAM 0x0000a81e 5547cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 5548cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 5549cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 5550cc4c26d4SRob Clark { 5551cc4c26d4SRob Clark return ((val >> 9) << A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 5552cc4c26d4SRob Clark } 5553cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 5554cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 5555cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 5556cc4c26d4SRob Clark { 5557cc4c26d4SRob Clark return ((val) << A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 5558cc4c26d4SRob Clark } 5559cc4c26d4SRob Clark 5560cc4c26d4SRob Clark #define REG_A6XX_SP_VS_PVT_MEM_ADDR 0x0000a81f 5561cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_ADDR__MASK 0xffffffff 5562cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_ADDR__SHIFT 0 5563cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_PVT_MEM_ADDR(uint32_t val) 5564cc4c26d4SRob Clark { 5565cc4c26d4SRob Clark return ((val) << A6XX_SP_VS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_VS_PVT_MEM_ADDR__MASK; 5566cc4c26d4SRob Clark } 5567cc4c26d4SRob Clark 5568cc4c26d4SRob Clark #define REG_A6XX_SP_VS_PVT_MEM_SIZE 0x0000a821 5569cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 5570cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 5571cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 5572cc4c26d4SRob Clark { 5573cc4c26d4SRob Clark return ((val >> 12) << A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 5574cc4c26d4SRob Clark } 5575cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 55762d756322SRob Clark 55772d756322SRob Clark #define REG_A6XX_SP_VS_TEX_COUNT 0x0000a822 55782d756322SRob Clark 55792d756322SRob Clark #define REG_A6XX_SP_VS_CONFIG 0x0000a823 5580c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_BINDLESS_TEX 0x00000001 5581c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_BINDLESS_SAMP 0x00000002 5582c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_BINDLESS_IBO 0x00000004 5583c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_BINDLESS_UBO 0x00000008 55842d756322SRob Clark #define A6XX_SP_VS_CONFIG_ENABLED 0x00000100 55852d756322SRob Clark #define A6XX_SP_VS_CONFIG_NTEX__MASK 0x0001fe00 55862d756322SRob Clark #define A6XX_SP_VS_CONFIG_NTEX__SHIFT 9 55872d756322SRob Clark static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val) 55882d756322SRob Clark { 55892d756322SRob Clark return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK; 55902d756322SRob Clark } 5591c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_NSAMP__MASK 0x003e0000 55922d756322SRob Clark #define A6XX_SP_VS_CONFIG_NSAMP__SHIFT 17 55932d756322SRob Clark static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val) 55942d756322SRob Clark { 55952d756322SRob Clark return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK; 55962d756322SRob Clark } 5597cc4c26d4SRob Clark #define A6XX_SP_VS_CONFIG_NIBO__MASK 0x1fc00000 5598c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_NIBO__SHIFT 22 5599c28c82e9SRob Clark static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val) 5600c28c82e9SRob Clark { 5601c28c82e9SRob Clark return ((val) << A6XX_SP_VS_CONFIG_NIBO__SHIFT) & A6XX_SP_VS_CONFIG_NIBO__MASK; 5602c28c82e9SRob Clark } 56032d756322SRob Clark 56042d756322SRob Clark #define REG_A6XX_SP_VS_INSTRLEN 0x0000a824 56052d756322SRob Clark 5606cc4c26d4SRob Clark #define REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET 0x0000a825 560757cfe41cSRob Clark #define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 560857cfe41cSRob Clark #define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 560957cfe41cSRob Clark static inline uint32_t A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 5610cc4c26d4SRob Clark { 561157cfe41cSRob Clark return ((val >> 11) << A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 5612cc4c26d4SRob Clark } 5613cc4c26d4SRob Clark 56142d756322SRob Clark #define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830 5615*f73343faSRob Clark #define A6XX_SP_HS_CTRL_REG0_EARLYPREAMBLE 0x00100000 5616cc4c26d4SRob Clark #define A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK 0x00000001 5617cc4c26d4SRob Clark #define A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT 0 5618cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 5619cc4c26d4SRob Clark { 5620cc4c26d4SRob Clark return ((val) << A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK; 5621cc4c26d4SRob Clark } 56222d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 56232d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 56242d756322SRob Clark static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 56252d756322SRob Clark { 56262d756322SRob Clark return ((val) << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 56272d756322SRob Clark } 56282d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 56292d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 56302d756322SRob Clark static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 56312d756322SRob Clark { 56322d756322SRob Clark return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 56332d756322SRob Clark } 5634cc4c26d4SRob Clark #define A6XX_SP_HS_CTRL_REG0_UNK13 0x00002000 56352d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 56362d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 14 56372d756322SRob Clark static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val) 56382d756322SRob Clark { 56392d756322SRob Clark return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK; 56402d756322SRob Clark } 5641cc4c26d4SRob Clark 5642cc4c26d4SRob Clark #define REG_A6XX_SP_HS_WAVE_INPUT_SIZE 0x0000a831 5643cc4c26d4SRob Clark 5644cc4c26d4SRob Clark #define REG_A6XX_SP_HS_BRANCH_COND 0x0000a832 5645cc4c26d4SRob Clark 5646cc4c26d4SRob Clark #define REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET 0x0000a833 5647cc4c26d4SRob Clark 5648cc4c26d4SRob Clark #define REG_A6XX_SP_HS_OBJ_START 0x0000a834 5649cc4c26d4SRob Clark #define A6XX_SP_HS_OBJ_START__MASK 0xffffffff 5650cc4c26d4SRob Clark #define A6XX_SP_HS_OBJ_START__SHIFT 0 5651cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_OBJ_START(uint32_t val) 56522d756322SRob Clark { 5653cc4c26d4SRob Clark return ((val) << A6XX_SP_HS_OBJ_START__SHIFT) & A6XX_SP_HS_OBJ_START__MASK; 56542d756322SRob Clark } 56552d756322SRob Clark 5656cc4c26d4SRob Clark #define REG_A6XX_SP_HS_PVT_MEM_PARAM 0x0000a836 5657cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 5658cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 5659cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 5660cc4c26d4SRob Clark { 5661cc4c26d4SRob Clark return ((val >> 9) << A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 5662cc4c26d4SRob Clark } 5663cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 5664cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 5665cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 5666cc4c26d4SRob Clark { 5667cc4c26d4SRob Clark return ((val) << A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 5668cc4c26d4SRob Clark } 56692d756322SRob Clark 5670cc4c26d4SRob Clark #define REG_A6XX_SP_HS_PVT_MEM_ADDR 0x0000a837 5671cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_ADDR__MASK 0xffffffff 5672cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_ADDR__SHIFT 0 5673cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_PVT_MEM_ADDR(uint32_t val) 5674cc4c26d4SRob Clark { 5675cc4c26d4SRob Clark return ((val) << A6XX_SP_HS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_HS_PVT_MEM_ADDR__MASK; 5676cc4c26d4SRob Clark } 5677c28c82e9SRob Clark 5678cc4c26d4SRob Clark #define REG_A6XX_SP_HS_PVT_MEM_SIZE 0x0000a839 5679cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 5680cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 5681cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 5682cc4c26d4SRob Clark { 5683cc4c26d4SRob Clark return ((val >> 12) << A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 5684cc4c26d4SRob Clark } 5685cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 56862d756322SRob Clark 56872d756322SRob Clark #define REG_A6XX_SP_HS_TEX_COUNT 0x0000a83a 56882d756322SRob Clark 56892d756322SRob Clark #define REG_A6XX_SP_HS_CONFIG 0x0000a83b 5690c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_BINDLESS_TEX 0x00000001 5691c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_BINDLESS_SAMP 0x00000002 5692c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_BINDLESS_IBO 0x00000004 5693c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_BINDLESS_UBO 0x00000008 56942d756322SRob Clark #define A6XX_SP_HS_CONFIG_ENABLED 0x00000100 56952d756322SRob Clark #define A6XX_SP_HS_CONFIG_NTEX__MASK 0x0001fe00 56962d756322SRob Clark #define A6XX_SP_HS_CONFIG_NTEX__SHIFT 9 56972d756322SRob Clark static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val) 56982d756322SRob Clark { 56992d756322SRob Clark return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK; 57002d756322SRob Clark } 5701c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_NSAMP__MASK 0x003e0000 57022d756322SRob Clark #define A6XX_SP_HS_CONFIG_NSAMP__SHIFT 17 57032d756322SRob Clark static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val) 57042d756322SRob Clark { 57052d756322SRob Clark return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK; 57062d756322SRob Clark } 5707cc4c26d4SRob Clark #define A6XX_SP_HS_CONFIG_NIBO__MASK 0x1fc00000 5708c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_NIBO__SHIFT 22 5709c28c82e9SRob Clark static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val) 5710c28c82e9SRob Clark { 5711c28c82e9SRob Clark return ((val) << A6XX_SP_HS_CONFIG_NIBO__SHIFT) & A6XX_SP_HS_CONFIG_NIBO__MASK; 5712c28c82e9SRob Clark } 57132d756322SRob Clark 57142d756322SRob Clark #define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c 57152d756322SRob Clark 5716cc4c26d4SRob Clark #define REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET 0x0000a83d 571757cfe41cSRob Clark #define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 571857cfe41cSRob Clark #define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 571957cfe41cSRob Clark static inline uint32_t A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 5720cc4c26d4SRob Clark { 572157cfe41cSRob Clark return ((val >> 11) << A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 5722cc4c26d4SRob Clark } 5723cc4c26d4SRob Clark 57242d756322SRob Clark #define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840 5725*f73343faSRob Clark #define A6XX_SP_DS_CTRL_REG0_EARLYPREAMBLE 0x00100000 5726cc4c26d4SRob Clark #define A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK 0x00000001 5727cc4c26d4SRob Clark #define A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT 0 5728cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 5729cc4c26d4SRob Clark { 5730cc4c26d4SRob Clark return ((val) << A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK; 5731cc4c26d4SRob Clark } 57322d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 57332d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 57342d756322SRob Clark static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 57352d756322SRob Clark { 57362d756322SRob Clark return ((val) << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 57372d756322SRob Clark } 57382d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 57392d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 57402d756322SRob Clark static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 57412d756322SRob Clark { 57422d756322SRob Clark return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 57432d756322SRob Clark } 5744cc4c26d4SRob Clark #define A6XX_SP_DS_CTRL_REG0_UNK13 0x00002000 57452d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 57462d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 14 57472d756322SRob Clark static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val) 57482d756322SRob Clark { 57492d756322SRob Clark return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK; 57502d756322SRob Clark } 5751cc4c26d4SRob Clark 5752cc4c26d4SRob Clark #define REG_A6XX_SP_DS_BRANCH_COND 0x0000a841 57532d756322SRob Clark 5754c28c82e9SRob Clark #define REG_A6XX_SP_DS_PRIMITIVE_CNTL 0x0000a842 5755c28c82e9SRob Clark #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f 5756c28c82e9SRob Clark #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT 0 5757c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_OUT(uint32_t val) 5758c28c82e9SRob Clark { 5759c28c82e9SRob Clark return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK; 5760c28c82e9SRob Clark } 5761cc4c26d4SRob Clark #define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0 5762cc4c26d4SRob Clark #define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6 5763cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) 5764cc4c26d4SRob Clark { 5765cc4c26d4SRob Clark return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; 5766cc4c26d4SRob Clark } 5767c28c82e9SRob Clark 5768c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; } 5769c28c82e9SRob Clark 5770c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000a843 + 0x1*i0; } 5771c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_A_REGID__MASK 0x000000ff 5772c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_A_REGID__SHIFT 0 5773c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_OUT_REG_A_REGID(uint32_t val) 5774c28c82e9SRob Clark { 5775c28c82e9SRob Clark return ((val) << A6XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_A_REGID__MASK; 5776c28c82e9SRob Clark } 5777c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00000f00 5778c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 8 5779c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val) 5780c28c82e9SRob Clark { 5781c28c82e9SRob Clark return ((val) << A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK; 5782c28c82e9SRob Clark } 5783c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_B_REGID__MASK 0x00ff0000 5784c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_B_REGID__SHIFT 16 5785c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_OUT_REG_B_REGID(uint32_t val) 5786c28c82e9SRob Clark { 5787c28c82e9SRob Clark return ((val) << A6XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_B_REGID__MASK; 5788c28c82e9SRob Clark } 5789c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x0f000000 5790c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 24 5791c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val) 5792c28c82e9SRob Clark { 5793c28c82e9SRob Clark return ((val) << A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK; 5794c28c82e9SRob Clark } 5795c28c82e9SRob Clark 5796c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000a853 + 0x1*i0; } 5797c28c82e9SRob Clark 5798c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000a853 + 0x1*i0; } 5799c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 5800c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0 5801c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val) 5802c28c82e9SRob Clark { 5803c28c82e9SRob Clark return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK; 5804c28c82e9SRob Clark } 5805c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 5806c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8 5807c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val) 5808c28c82e9SRob Clark { 5809c28c82e9SRob Clark return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK; 5810c28c82e9SRob Clark } 5811c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 5812c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16 5813c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val) 5814c28c82e9SRob Clark { 5815c28c82e9SRob Clark return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK; 5816c28c82e9SRob Clark } 5817c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 5818c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24 5819c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) 5820c28c82e9SRob Clark { 5821c28c82e9SRob Clark return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK; 5822c28c82e9SRob Clark } 5823c28c82e9SRob Clark 5824cc4c26d4SRob Clark #define REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET 0x0000a85b 5825c28c82e9SRob Clark 5826cc4c26d4SRob Clark #define REG_A6XX_SP_DS_OBJ_START 0x0000a85c 5827cc4c26d4SRob Clark #define A6XX_SP_DS_OBJ_START__MASK 0xffffffff 5828cc4c26d4SRob Clark #define A6XX_SP_DS_OBJ_START__SHIFT 0 5829cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_OBJ_START(uint32_t val) 5830cc4c26d4SRob Clark { 5831cc4c26d4SRob Clark return ((val) << A6XX_SP_DS_OBJ_START__SHIFT) & A6XX_SP_DS_OBJ_START__MASK; 5832cc4c26d4SRob Clark } 58332d756322SRob Clark 5834cc4c26d4SRob Clark #define REG_A6XX_SP_DS_PVT_MEM_PARAM 0x0000a85e 5835cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 5836cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 5837cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 5838cc4c26d4SRob Clark { 5839cc4c26d4SRob Clark return ((val >> 9) << A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 5840cc4c26d4SRob Clark } 5841cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 5842cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 5843cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 5844cc4c26d4SRob Clark { 5845cc4c26d4SRob Clark return ((val) << A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 5846cc4c26d4SRob Clark } 5847cc4c26d4SRob Clark 5848cc4c26d4SRob Clark #define REG_A6XX_SP_DS_PVT_MEM_ADDR 0x0000a85f 5849cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_ADDR__MASK 0xffffffff 5850cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_ADDR__SHIFT 0 5851cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_PVT_MEM_ADDR(uint32_t val) 5852cc4c26d4SRob Clark { 5853cc4c26d4SRob Clark return ((val) << A6XX_SP_DS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_DS_PVT_MEM_ADDR__MASK; 5854cc4c26d4SRob Clark } 5855cc4c26d4SRob Clark 5856cc4c26d4SRob Clark #define REG_A6XX_SP_DS_PVT_MEM_SIZE 0x0000a861 5857cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 5858cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 5859cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 5860cc4c26d4SRob Clark { 5861cc4c26d4SRob Clark return ((val >> 12) << A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 5862cc4c26d4SRob Clark } 5863cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 58642d756322SRob Clark 58652d756322SRob Clark #define REG_A6XX_SP_DS_TEX_COUNT 0x0000a862 58662d756322SRob Clark 58672d756322SRob Clark #define REG_A6XX_SP_DS_CONFIG 0x0000a863 5868c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_BINDLESS_TEX 0x00000001 5869c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_BINDLESS_SAMP 0x00000002 5870c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_BINDLESS_IBO 0x00000004 5871c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_BINDLESS_UBO 0x00000008 58722d756322SRob Clark #define A6XX_SP_DS_CONFIG_ENABLED 0x00000100 58732d756322SRob Clark #define A6XX_SP_DS_CONFIG_NTEX__MASK 0x0001fe00 58742d756322SRob Clark #define A6XX_SP_DS_CONFIG_NTEX__SHIFT 9 58752d756322SRob Clark static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val) 58762d756322SRob Clark { 58772d756322SRob Clark return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK; 58782d756322SRob Clark } 5879c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_NSAMP__MASK 0x003e0000 58802d756322SRob Clark #define A6XX_SP_DS_CONFIG_NSAMP__SHIFT 17 58812d756322SRob Clark static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val) 58822d756322SRob Clark { 58832d756322SRob Clark return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK; 58842d756322SRob Clark } 5885cc4c26d4SRob Clark #define A6XX_SP_DS_CONFIG_NIBO__MASK 0x1fc00000 5886c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_NIBO__SHIFT 22 5887c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val) 5888c28c82e9SRob Clark { 5889c28c82e9SRob Clark return ((val) << A6XX_SP_DS_CONFIG_NIBO__SHIFT) & A6XX_SP_DS_CONFIG_NIBO__MASK; 5890c28c82e9SRob Clark } 58912d756322SRob Clark 58922d756322SRob Clark #define REG_A6XX_SP_DS_INSTRLEN 0x0000a864 58932d756322SRob Clark 5894cc4c26d4SRob Clark #define REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET 0x0000a865 589557cfe41cSRob Clark #define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 589657cfe41cSRob Clark #define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 589757cfe41cSRob Clark static inline uint32_t A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 5898cc4c26d4SRob Clark { 589957cfe41cSRob Clark return ((val >> 11) << A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 5900cc4c26d4SRob Clark } 5901cc4c26d4SRob Clark 59022d756322SRob Clark #define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870 5903*f73343faSRob Clark #define A6XX_SP_GS_CTRL_REG0_EARLYPREAMBLE 0x00100000 5904cc4c26d4SRob Clark #define A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK 0x00000001 5905cc4c26d4SRob Clark #define A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT 0 5906cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 5907cc4c26d4SRob Clark { 5908cc4c26d4SRob Clark return ((val) << A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK; 5909cc4c26d4SRob Clark } 59102d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 59112d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 59122d756322SRob Clark static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 59132d756322SRob Clark { 59142d756322SRob Clark return ((val) << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 59152d756322SRob Clark } 59162d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 59172d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 59182d756322SRob Clark static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 59192d756322SRob Clark { 59202d756322SRob Clark return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 59212d756322SRob Clark } 5922cc4c26d4SRob Clark #define A6XX_SP_GS_CTRL_REG0_UNK13 0x00002000 59232d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 59242d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 14 59252d756322SRob Clark static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val) 59262d756322SRob Clark { 59272d756322SRob Clark return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK; 59282d756322SRob Clark } 59292d756322SRob Clark 5930c28c82e9SRob Clark #define REG_A6XX_SP_GS_PRIM_SIZE 0x0000a871 5931c28c82e9SRob Clark 5932c28c82e9SRob Clark #define REG_A6XX_SP_GS_BRANCH_COND 0x0000a872 5933c28c82e9SRob Clark 5934c28c82e9SRob Clark #define REG_A6XX_SP_GS_PRIMITIVE_CNTL 0x0000a873 5935c28c82e9SRob Clark #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f 5936c28c82e9SRob Clark #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT 0 5937c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_OUT(uint32_t val) 5938c28c82e9SRob Clark { 5939c28c82e9SRob Clark return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK; 5940c28c82e9SRob Clark } 5941c28c82e9SRob Clark #define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0 5942c28c82e9SRob Clark #define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6 5943c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) 5944c28c82e9SRob Clark { 5945c28c82e9SRob Clark return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; 5946c28c82e9SRob Clark } 5947c28c82e9SRob Clark 5948c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_GS_OUT(uint32_t i0) { return 0x0000a874 + 0x1*i0; } 5949c28c82e9SRob Clark 5950c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_GS_OUT_REG(uint32_t i0) { return 0x0000a874 + 0x1*i0; } 5951c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_A_REGID__MASK 0x000000ff 5952c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_A_REGID__SHIFT 0 5953c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_OUT_REG_A_REGID(uint32_t val) 5954c28c82e9SRob Clark { 5955c28c82e9SRob Clark return ((val) << A6XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_A_REGID__MASK; 5956c28c82e9SRob Clark } 5957c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00000f00 5958c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 8 5959c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val) 5960c28c82e9SRob Clark { 5961c28c82e9SRob Clark return ((val) << A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK; 5962c28c82e9SRob Clark } 5963c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_B_REGID__MASK 0x00ff0000 5964c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_B_REGID__SHIFT 16 5965c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_OUT_REG_B_REGID(uint32_t val) 5966c28c82e9SRob Clark { 5967c28c82e9SRob Clark return ((val) << A6XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_B_REGID__MASK; 5968c28c82e9SRob Clark } 5969c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x0f000000 5970c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 24 5971c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val) 5972c28c82e9SRob Clark { 5973c28c82e9SRob Clark return ((val) << A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK; 5974c28c82e9SRob Clark } 5975c28c82e9SRob Clark 5976c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_GS_VPC_DST(uint32_t i0) { return 0x0000a884 + 0x1*i0; } 5977c28c82e9SRob Clark 5978c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x0000a884 + 0x1*i0; } 5979c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 5980c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0 5981c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val) 5982c28c82e9SRob Clark { 5983c28c82e9SRob Clark return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK; 5984c28c82e9SRob Clark } 5985c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 5986c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8 5987c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val) 5988c28c82e9SRob Clark { 5989c28c82e9SRob Clark return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK; 5990c28c82e9SRob Clark } 5991c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 5992c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16 5993c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val) 5994c28c82e9SRob Clark { 5995c28c82e9SRob Clark return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK; 5996c28c82e9SRob Clark } 5997c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 5998c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24 5999c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) 6000c28c82e9SRob Clark { 6001c28c82e9SRob Clark return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK; 6002c28c82e9SRob Clark } 60032d756322SRob Clark 6004cc4c26d4SRob Clark #define REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET 0x0000a88c 60052d756322SRob Clark 6006cc4c26d4SRob Clark #define REG_A6XX_SP_GS_OBJ_START 0x0000a88d 6007cc4c26d4SRob Clark #define A6XX_SP_GS_OBJ_START__MASK 0xffffffff 6008cc4c26d4SRob Clark #define A6XX_SP_GS_OBJ_START__SHIFT 0 6009cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_OBJ_START(uint32_t val) 6010cc4c26d4SRob Clark { 6011cc4c26d4SRob Clark return ((val) << A6XX_SP_GS_OBJ_START__SHIFT) & A6XX_SP_GS_OBJ_START__MASK; 6012cc4c26d4SRob Clark } 6013cc4c26d4SRob Clark 6014cc4c26d4SRob Clark #define REG_A6XX_SP_GS_PVT_MEM_PARAM 0x0000a88f 6015cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 6016cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 6017cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 6018cc4c26d4SRob Clark { 6019cc4c26d4SRob Clark return ((val >> 9) << A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 6020cc4c26d4SRob Clark } 6021cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 6022cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 6023cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 6024cc4c26d4SRob Clark { 6025cc4c26d4SRob Clark return ((val) << A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 6026cc4c26d4SRob Clark } 6027cc4c26d4SRob Clark 6028cc4c26d4SRob Clark #define REG_A6XX_SP_GS_PVT_MEM_ADDR 0x0000a890 6029cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_ADDR__MASK 0xffffffff 6030cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_ADDR__SHIFT 0 6031cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_PVT_MEM_ADDR(uint32_t val) 6032cc4c26d4SRob Clark { 6033cc4c26d4SRob Clark return ((val) << A6XX_SP_GS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_GS_PVT_MEM_ADDR__MASK; 6034cc4c26d4SRob Clark } 6035cc4c26d4SRob Clark 6036cc4c26d4SRob Clark #define REG_A6XX_SP_GS_PVT_MEM_SIZE 0x0000a892 6037cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 6038cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 6039cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 6040cc4c26d4SRob Clark { 6041cc4c26d4SRob Clark return ((val >> 12) << A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 6042cc4c26d4SRob Clark } 6043cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 60442d756322SRob Clark 60452d756322SRob Clark #define REG_A6XX_SP_GS_TEX_COUNT 0x0000a893 60462d756322SRob Clark 60472d756322SRob Clark #define REG_A6XX_SP_GS_CONFIG 0x0000a894 6048c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_BINDLESS_TEX 0x00000001 6049c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_BINDLESS_SAMP 0x00000002 6050c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_BINDLESS_IBO 0x00000004 6051c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_BINDLESS_UBO 0x00000008 60522d756322SRob Clark #define A6XX_SP_GS_CONFIG_ENABLED 0x00000100 60532d756322SRob Clark #define A6XX_SP_GS_CONFIG_NTEX__MASK 0x0001fe00 60542d756322SRob Clark #define A6XX_SP_GS_CONFIG_NTEX__SHIFT 9 60552d756322SRob Clark static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val) 60562d756322SRob Clark { 60572d756322SRob Clark return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK; 60582d756322SRob Clark } 6059c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_NSAMP__MASK 0x003e0000 60602d756322SRob Clark #define A6XX_SP_GS_CONFIG_NSAMP__SHIFT 17 60612d756322SRob Clark static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val) 60622d756322SRob Clark { 60632d756322SRob Clark return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK; 60642d756322SRob Clark } 6065cc4c26d4SRob Clark #define A6XX_SP_GS_CONFIG_NIBO__MASK 0x1fc00000 6066c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_NIBO__SHIFT 22 6067c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val) 6068c28c82e9SRob Clark { 6069c28c82e9SRob Clark return ((val) << A6XX_SP_GS_CONFIG_NIBO__SHIFT) & A6XX_SP_GS_CONFIG_NIBO__MASK; 6070c28c82e9SRob Clark } 60712d756322SRob Clark 60722d756322SRob Clark #define REG_A6XX_SP_GS_INSTRLEN 0x0000a895 60732d756322SRob Clark 6074cc4c26d4SRob Clark #define REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET 0x0000a896 607557cfe41cSRob Clark #define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 607657cfe41cSRob Clark #define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 607757cfe41cSRob Clark static inline uint32_t A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 6078cc4c26d4SRob Clark { 607957cfe41cSRob Clark return ((val >> 11) << A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 6080cc4c26d4SRob Clark } 60812d756322SRob Clark 6082cc4c26d4SRob Clark #define REG_A6XX_SP_VS_TEX_SAMP 0x0000a8a0 6083cc4c26d4SRob Clark #define A6XX_SP_VS_TEX_SAMP__MASK 0xffffffff 6084cc4c26d4SRob Clark #define A6XX_SP_VS_TEX_SAMP__SHIFT 0 6085cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_TEX_SAMP(uint32_t val) 6086cc4c26d4SRob Clark { 6087cc4c26d4SRob Clark return ((val) << A6XX_SP_VS_TEX_SAMP__SHIFT) & A6XX_SP_VS_TEX_SAMP__MASK; 6088cc4c26d4SRob Clark } 60892d756322SRob Clark 6090cc4c26d4SRob Clark #define REG_A6XX_SP_HS_TEX_SAMP 0x0000a8a2 6091cc4c26d4SRob Clark #define A6XX_SP_HS_TEX_SAMP__MASK 0xffffffff 6092cc4c26d4SRob Clark #define A6XX_SP_HS_TEX_SAMP__SHIFT 0 6093cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_TEX_SAMP(uint32_t val) 6094cc4c26d4SRob Clark { 6095cc4c26d4SRob Clark return ((val) << A6XX_SP_HS_TEX_SAMP__SHIFT) & A6XX_SP_HS_TEX_SAMP__MASK; 6096cc4c26d4SRob Clark } 60972d756322SRob Clark 6098cc4c26d4SRob Clark #define REG_A6XX_SP_DS_TEX_SAMP 0x0000a8a4 6099cc4c26d4SRob Clark #define A6XX_SP_DS_TEX_SAMP__MASK 0xffffffff 6100cc4c26d4SRob Clark #define A6XX_SP_DS_TEX_SAMP__SHIFT 0 6101cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_TEX_SAMP(uint32_t val) 6102cc4c26d4SRob Clark { 6103cc4c26d4SRob Clark return ((val) << A6XX_SP_DS_TEX_SAMP__SHIFT) & A6XX_SP_DS_TEX_SAMP__MASK; 6104cc4c26d4SRob Clark } 61052d756322SRob Clark 6106cc4c26d4SRob Clark #define REG_A6XX_SP_GS_TEX_SAMP 0x0000a8a6 6107cc4c26d4SRob Clark #define A6XX_SP_GS_TEX_SAMP__MASK 0xffffffff 6108cc4c26d4SRob Clark #define A6XX_SP_GS_TEX_SAMP__SHIFT 0 6109cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_TEX_SAMP(uint32_t val) 6110cc4c26d4SRob Clark { 6111cc4c26d4SRob Clark return ((val) << A6XX_SP_GS_TEX_SAMP__SHIFT) & A6XX_SP_GS_TEX_SAMP__MASK; 6112cc4c26d4SRob Clark } 61132d756322SRob Clark 6114cc4c26d4SRob Clark #define REG_A6XX_SP_VS_TEX_CONST 0x0000a8a8 6115cc4c26d4SRob Clark #define A6XX_SP_VS_TEX_CONST__MASK 0xffffffff 6116cc4c26d4SRob Clark #define A6XX_SP_VS_TEX_CONST__SHIFT 0 6117cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_TEX_CONST(uint32_t val) 6118cc4c26d4SRob Clark { 6119cc4c26d4SRob Clark return ((val) << A6XX_SP_VS_TEX_CONST__SHIFT) & A6XX_SP_VS_TEX_CONST__MASK; 6120cc4c26d4SRob Clark } 61212d756322SRob Clark 6122cc4c26d4SRob Clark #define REG_A6XX_SP_HS_TEX_CONST 0x0000a8aa 6123cc4c26d4SRob Clark #define A6XX_SP_HS_TEX_CONST__MASK 0xffffffff 6124cc4c26d4SRob Clark #define A6XX_SP_HS_TEX_CONST__SHIFT 0 6125cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_TEX_CONST(uint32_t val) 6126cc4c26d4SRob Clark { 6127cc4c26d4SRob Clark return ((val) << A6XX_SP_HS_TEX_CONST__SHIFT) & A6XX_SP_HS_TEX_CONST__MASK; 6128cc4c26d4SRob Clark } 61292d756322SRob Clark 6130cc4c26d4SRob Clark #define REG_A6XX_SP_DS_TEX_CONST 0x0000a8ac 6131cc4c26d4SRob Clark #define A6XX_SP_DS_TEX_CONST__MASK 0xffffffff 6132cc4c26d4SRob Clark #define A6XX_SP_DS_TEX_CONST__SHIFT 0 6133cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_TEX_CONST(uint32_t val) 6134cc4c26d4SRob Clark { 6135cc4c26d4SRob Clark return ((val) << A6XX_SP_DS_TEX_CONST__SHIFT) & A6XX_SP_DS_TEX_CONST__MASK; 6136cc4c26d4SRob Clark } 61372d756322SRob Clark 6138cc4c26d4SRob Clark #define REG_A6XX_SP_GS_TEX_CONST 0x0000a8ae 6139cc4c26d4SRob Clark #define A6XX_SP_GS_TEX_CONST__MASK 0xffffffff 6140cc4c26d4SRob Clark #define A6XX_SP_GS_TEX_CONST__SHIFT 0 6141cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_TEX_CONST(uint32_t val) 6142cc4c26d4SRob Clark { 6143cc4c26d4SRob Clark return ((val) << A6XX_SP_GS_TEX_CONST__SHIFT) & A6XX_SP_GS_TEX_CONST__MASK; 6144cc4c26d4SRob Clark } 61452d756322SRob Clark 61462d756322SRob Clark #define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980 6147cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 6148cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 6149cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) 6150cc4c26d4SRob Clark { 6151cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 6152cc4c26d4SRob Clark } 6153cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_UNK21 0x00200000 6154cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000 6155cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_DIFF_FINE 0x00800000 6156cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_UNK24 0x01000000 6157cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_UNK25 0x02000000 6158cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000 6159*f73343faSRob Clark #define A6XX_SP_FS_CTRL_REG0_UNK27 0x08000000 6160*f73343faSRob Clark #define A6XX_SP_FS_CTRL_REG0_EARLYPREAMBLE 0x10000000 6161cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000 6162cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 6163cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 6164cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 6165cc4c26d4SRob Clark { 6166cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK; 6167cc4c26d4SRob Clark } 61682d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 61692d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 61702d756322SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 61712d756322SRob Clark { 61722d756322SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 61732d756322SRob Clark } 61742d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 61752d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 61762d756322SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 61772d756322SRob Clark { 61782d756322SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 61792d756322SRob Clark } 6180cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_UNK13 0x00002000 61812d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 61822d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 14 61832d756322SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) 61842d756322SRob Clark { 61852d756322SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK; 61862d756322SRob Clark } 61872d756322SRob Clark 6188c28c82e9SRob Clark #define REG_A6XX_SP_FS_BRANCH_COND 0x0000a981 6189c28c82e9SRob Clark 6190cc4c26d4SRob Clark #define REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET 0x0000a982 6191a69c5ed2SRob Clark 6192cc4c26d4SRob Clark #define REG_A6XX_SP_FS_OBJ_START 0x0000a983 6193cc4c26d4SRob Clark #define A6XX_SP_FS_OBJ_START__MASK 0xffffffff 6194cc4c26d4SRob Clark #define A6XX_SP_FS_OBJ_START__SHIFT 0 6195cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_OBJ_START(uint32_t val) 6196cc4c26d4SRob Clark { 6197cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_OBJ_START__SHIFT) & A6XX_SP_FS_OBJ_START__MASK; 6198cc4c26d4SRob Clark } 61992d756322SRob Clark 6200cc4c26d4SRob Clark #define REG_A6XX_SP_FS_PVT_MEM_PARAM 0x0000a985 6201cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 6202cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 6203cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 6204cc4c26d4SRob Clark { 6205cc4c26d4SRob Clark return ((val >> 9) << A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 6206cc4c26d4SRob Clark } 6207cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 6208cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 6209cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 6210cc4c26d4SRob Clark { 6211cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 6212cc4c26d4SRob Clark } 6213cc4c26d4SRob Clark 6214cc4c26d4SRob Clark #define REG_A6XX_SP_FS_PVT_MEM_ADDR 0x0000a986 6215cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_ADDR__MASK 0xffffffff 6216cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_ADDR__SHIFT 0 6217cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_PVT_MEM_ADDR(uint32_t val) 6218cc4c26d4SRob Clark { 6219cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_FS_PVT_MEM_ADDR__MASK; 6220cc4c26d4SRob Clark } 6221cc4c26d4SRob Clark 6222cc4c26d4SRob Clark #define REG_A6XX_SP_FS_PVT_MEM_SIZE 0x0000a988 6223cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 6224cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 6225cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 6226cc4c26d4SRob Clark { 6227cc4c26d4SRob Clark return ((val >> 12) << A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 6228cc4c26d4SRob Clark } 6229cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 62302d756322SRob Clark 62312d756322SRob Clark #define REG_A6XX_SP_BLEND_CNTL 0x0000a989 6232cc4c26d4SRob Clark #define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff 6233cc4c26d4SRob Clark #define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 6234cc4c26d4SRob Clark static inline uint32_t A6XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val) 6235cc4c26d4SRob Clark { 6236cc4c26d4SRob Clark return ((val) << A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK; 6237cc4c26d4SRob Clark } 62382d756322SRob Clark #define A6XX_SP_BLEND_CNTL_UNK8 0x00000100 6239c28c82e9SRob Clark #define A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200 6240ccdf7e28SRob Clark #define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 62412d756322SRob Clark 62422d756322SRob Clark #define REG_A6XX_SP_SRGB_CNTL 0x0000a98a 62432d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT0 0x00000001 62442d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT1 0x00000002 62452d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT2 0x00000004 62462d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT3 0x00000008 62472d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT4 0x00000010 62482d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT5 0x00000020 62492d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT6 0x00000040 62502d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT7 0x00000080 62512d756322SRob Clark 62522d756322SRob Clark #define REG_A6XX_SP_FS_RENDER_COMPONENTS 0x0000a98b 62532d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK 0x0000000f 62542d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT 0 62552d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val) 62562d756322SRob Clark { 62572d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK; 62582d756322SRob Clark } 62592d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK 0x000000f0 62602d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT 4 62612d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val) 62622d756322SRob Clark { 62632d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK; 62642d756322SRob Clark } 62652d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK 0x00000f00 62662d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT 8 62672d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val) 62682d756322SRob Clark { 62692d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK; 62702d756322SRob Clark } 62712d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK 0x0000f000 62722d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT 12 62732d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val) 62742d756322SRob Clark { 62752d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK; 62762d756322SRob Clark } 62772d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK 0x000f0000 62782d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT 16 62792d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val) 62802d756322SRob Clark { 62812d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK; 62822d756322SRob Clark } 62832d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK 0x00f00000 62842d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT 20 62852d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val) 62862d756322SRob Clark { 62872d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK; 62882d756322SRob Clark } 62892d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK 0x0f000000 62902d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT 24 62912d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val) 62922d756322SRob Clark { 62932d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK; 62942d756322SRob Clark } 62952d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK 0xf0000000 62962d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT 28 62972d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val) 62982d756322SRob Clark { 62992d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK; 63002d756322SRob Clark } 63012d756322SRob Clark 63022d756322SRob Clark #define REG_A6XX_SP_FS_OUTPUT_CNTL0 0x0000a98c 6303c28c82e9SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001 63042d756322SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK 0x0000ff00 63052d756322SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT 8 63062d756322SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val) 63072d756322SRob Clark { 63082d756322SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK; 63092d756322SRob Clark } 6310c28c82e9SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK 0x00ff0000 6311c28c82e9SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT 16 6312c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(uint32_t val) 6313c28c82e9SRob Clark { 6314c28c82e9SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK; 6315c28c82e9SRob Clark } 6316c28c82e9SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK 0xff000000 6317c28c82e9SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT 24 6318c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(uint32_t val) 6319c28c82e9SRob Clark { 6320c28c82e9SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK; 6321c28c82e9SRob Clark } 63222d756322SRob Clark 63232d756322SRob Clark #define REG_A6XX_SP_FS_OUTPUT_CNTL1 0x0000a98d 63242d756322SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f 63252d756322SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT 0 63262d756322SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val) 63272d756322SRob Clark { 63282d756322SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK; 63292d756322SRob Clark } 63302d756322SRob Clark 6331cc4c26d4SRob Clark static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; } 6332cc4c26d4SRob Clark 6333cc4c26d4SRob Clark static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; } 6334cc4c26d4SRob Clark #define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff 6335cc4c26d4SRob Clark #define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0 6336cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) 6337cc4c26d4SRob Clark { 6338cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK; 6339cc4c26d4SRob Clark } 6340cc4c26d4SRob Clark #define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100 6341cc4c26d4SRob Clark 63422d756322SRob Clark static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; } 63432d756322SRob Clark 63442d756322SRob Clark static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; } 63452d756322SRob Clark #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff 63462d756322SRob Clark #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0 6347c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val) 63482d756322SRob Clark { 63492d756322SRob Clark return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK; 63502d756322SRob Clark } 63512d756322SRob Clark #define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100 63522d756322SRob Clark #define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200 6353cc4c26d4SRob Clark #define A6XX_SP_FS_MRT_REG_UNK10 0x00000400 6354a69c5ed2SRob Clark 6355c28c82e9SRob Clark #define REG_A6XX_SP_FS_PREFETCH_CNTL 0x0000a99e 6356c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK 0x00000007 6357c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT 0 6358c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_COUNT(uint32_t val) 6359c28c82e9SRob Clark { 6360c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK; 6361c28c82e9SRob Clark } 6362*f73343faSRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_IJ_WRITE_DISABLE 0x00000008 6363*f73343faSRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_UNK4 0x00000010 6364*f73343faSRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_WRITE_COLOR_TO_OUTPUT 0x00000020 6365*f73343faSRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_UNK6__MASK 0x00007fc0 6366*f73343faSRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_UNK6__SHIFT 6 6367*f73343faSRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK6(uint32_t val) 6368c28c82e9SRob Clark { 6369*f73343faSRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK6__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK6__MASK; 6370cc4c26d4SRob Clark } 6371c28c82e9SRob Clark 6372c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_FS_PREFETCH(uint32_t i0) { return 0x0000a99f + 0x1*i0; } 6373c28c82e9SRob Clark 6374c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; } 6375c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_SRC__MASK 0x0000007f 6376c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT 0 6377c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val) 6378c28c82e9SRob Clark { 6379c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SRC__MASK; 6380c28c82e9SRob Clark } 6381c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK 0x00000780 6382c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT 7 6383c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val) 6384c28c82e9SRob Clark { 6385c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK; 6386c28c82e9SRob Clark } 6387c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK 0x0000f800 6388c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT 11 6389c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val) 6390c28c82e9SRob Clark { 6391c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK; 6392c28c82e9SRob Clark } 6393c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_DST__MASK 0x003f0000 6394c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT 16 6395c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_DST(uint32_t val) 6396c28c82e9SRob Clark { 6397c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_DST__MASK; 6398c28c82e9SRob Clark } 6399c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK 0x03c00000 6400c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT 22 6401c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val) 6402c28c82e9SRob Clark { 6403c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK; 6404c28c82e9SRob Clark } 6405c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_HALF 0x04000000 6406*f73343faSRob Clark #define A6XX_SP_FS_PREFETCH_CMD_UNK27 0x08000000 6407*f73343faSRob Clark #define A6XX_SP_FS_PREFETCH_CMD_BINDLESS 0x10000000 6408*f73343faSRob Clark #define A6XX_SP_FS_PREFETCH_CMD_CMD__MASK 0xe0000000 6409*f73343faSRob Clark #define A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT 29 6410*f73343faSRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_CMD(enum a6xx_tex_prefetch_cmd val) 6411c28c82e9SRob Clark { 6412c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_CMD__MASK; 6413c28c82e9SRob Clark } 6414c28c82e9SRob Clark 6415c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; } 6416c28c82e9SRob Clark 6417c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; } 6418cc4c26d4SRob Clark #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK 0x0000ffff 6419c28c82e9SRob Clark #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT 0 6420c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val) 6421c28c82e9SRob Clark { 6422c28c82e9SRob Clark return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK; 6423c28c82e9SRob Clark } 6424cc4c26d4SRob Clark #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK 0xffff0000 6425c28c82e9SRob Clark #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT 16 6426c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val) 6427c28c82e9SRob Clark { 6428c28c82e9SRob Clark return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK; 6429c28c82e9SRob Clark } 64302d756322SRob Clark 64312d756322SRob Clark #define REG_A6XX_SP_FS_TEX_COUNT 0x0000a9a7 64322d756322SRob Clark 64332d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8 64342d756322SRob Clark 6435cc4c26d4SRob Clark #define REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET 0x0000a9a9 643657cfe41cSRob Clark #define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 643757cfe41cSRob Clark #define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 643857cfe41cSRob Clark static inline uint32_t A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 6439c28c82e9SRob Clark { 644057cfe41cSRob Clark return ((val >> 11) << A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 6441c28c82e9SRob Clark } 6442c28c82e9SRob Clark 64432d756322SRob Clark #define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0 6444cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000 6445cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20 6446cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) 6447cc4c26d4SRob Clark { 6448cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK; 6449cc4c26d4SRob Clark } 6450cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_UNK21 0x00200000 6451cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_UNK22 0x00400000 6452*f73343faSRob Clark #define A6XX_SP_CS_CTRL_REG0_EARLYPREAMBLE 0x00800000 6453cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000 6454cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK 0x00000001 6455cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT 0 6456cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 6457cc4c26d4SRob Clark { 6458cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK; 6459cc4c26d4SRob Clark } 64602d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 64612d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 64622d756322SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 64632d756322SRob Clark { 64642d756322SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 64652d756322SRob Clark } 64662d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 64672d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 64682d756322SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 64692d756322SRob Clark { 64702d756322SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 64712d756322SRob Clark } 6472cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_UNK13 0x00002000 64732d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 64742d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 14 64752d756322SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val) 64762d756322SRob Clark { 64772d756322SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK; 64782d756322SRob Clark } 6479cc4c26d4SRob Clark 6480cc4c26d4SRob Clark #define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1 6481cc4c26d4SRob Clark #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK 0x0000001f 6482cc4c26d4SRob Clark #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT 0 6483cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(uint32_t val) 64842d756322SRob Clark { 6485cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK; 64862d756322SRob Clark } 6487cc4c26d4SRob Clark #define A6XX_SP_CS_UNKNOWN_A9B1_UNK5 0x00000020 6488cc4c26d4SRob Clark #define A6XX_SP_CS_UNKNOWN_A9B1_UNK6 0x00000040 64892d756322SRob Clark 6490cc4c26d4SRob Clark #define REG_A6XX_SP_CS_BRANCH_COND 0x0000a9b2 64912d756322SRob Clark 6492cc4c26d4SRob Clark #define REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET 0x0000a9b3 6493cc4c26d4SRob Clark 6494cc4c26d4SRob Clark #define REG_A6XX_SP_CS_OBJ_START 0x0000a9b4 6495cc4c26d4SRob Clark #define A6XX_SP_CS_OBJ_START__MASK 0xffffffff 6496cc4c26d4SRob Clark #define A6XX_SP_CS_OBJ_START__SHIFT 0 6497cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_OBJ_START(uint32_t val) 6498cc4c26d4SRob Clark { 6499cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_OBJ_START__SHIFT) & A6XX_SP_CS_OBJ_START__MASK; 6500cc4c26d4SRob Clark } 6501cc4c26d4SRob Clark 6502cc4c26d4SRob Clark #define REG_A6XX_SP_CS_PVT_MEM_PARAM 0x0000a9b6 6503cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 6504cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 6505cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 6506cc4c26d4SRob Clark { 6507cc4c26d4SRob Clark return ((val >> 9) << A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 6508cc4c26d4SRob Clark } 6509cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 6510cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 6511cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 6512cc4c26d4SRob Clark { 6513cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 6514cc4c26d4SRob Clark } 6515cc4c26d4SRob Clark 6516cc4c26d4SRob Clark #define REG_A6XX_SP_CS_PVT_MEM_ADDR 0x0000a9b7 6517cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_ADDR__MASK 0xffffffff 6518cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_ADDR__SHIFT 0 6519cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_PVT_MEM_ADDR(uint32_t val) 6520cc4c26d4SRob Clark { 6521cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_CS_PVT_MEM_ADDR__MASK; 6522cc4c26d4SRob Clark } 6523cc4c26d4SRob Clark 6524cc4c26d4SRob Clark #define REG_A6XX_SP_CS_PVT_MEM_SIZE 0x0000a9b9 6525cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 6526cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 6527cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 6528cc4c26d4SRob Clark { 6529cc4c26d4SRob Clark return ((val >> 12) << A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 6530cc4c26d4SRob Clark } 6531cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 6532cc4c26d4SRob Clark 6533cc4c26d4SRob Clark #define REG_A6XX_SP_CS_TEX_COUNT 0x0000a9ba 65342d756322SRob Clark 6535c28c82e9SRob Clark #define REG_A6XX_SP_CS_CONFIG 0x0000a9bb 6536c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_BINDLESS_TEX 0x00000001 6537c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_BINDLESS_SAMP 0x00000002 6538c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_BINDLESS_IBO 0x00000004 6539c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_BINDLESS_UBO 0x00000008 6540c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_ENABLED 0x00000100 6541c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_NTEX__MASK 0x0001fe00 6542c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_NTEX__SHIFT 9 6543c28c82e9SRob Clark static inline uint32_t A6XX_SP_CS_CONFIG_NTEX(uint32_t val) 6544c28c82e9SRob Clark { 6545c28c82e9SRob Clark return ((val) << A6XX_SP_CS_CONFIG_NTEX__SHIFT) & A6XX_SP_CS_CONFIG_NTEX__MASK; 6546c28c82e9SRob Clark } 6547c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_NSAMP__MASK 0x003e0000 6548c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_NSAMP__SHIFT 17 6549c28c82e9SRob Clark static inline uint32_t A6XX_SP_CS_CONFIG_NSAMP(uint32_t val) 6550c28c82e9SRob Clark { 6551c28c82e9SRob Clark return ((val) << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK; 6552c28c82e9SRob Clark } 6553cc4c26d4SRob Clark #define A6XX_SP_CS_CONFIG_NIBO__MASK 0x1fc00000 6554c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_NIBO__SHIFT 22 6555c28c82e9SRob Clark static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val) 6556c28c82e9SRob Clark { 6557c28c82e9SRob Clark return ((val) << A6XX_SP_CS_CONFIG_NIBO__SHIFT) & A6XX_SP_CS_CONFIG_NIBO__MASK; 6558c28c82e9SRob Clark } 6559c28c82e9SRob Clark 65602d756322SRob Clark #define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc 65612d756322SRob Clark 6562cc4c26d4SRob Clark #define REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET 0x0000a9bd 656357cfe41cSRob Clark #define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 656457cfe41cSRob Clark #define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 656557cfe41cSRob Clark static inline uint32_t A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 6566cc4c26d4SRob Clark { 656757cfe41cSRob Clark return ((val >> 11) << A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 6568cc4c26d4SRob Clark } 6569c28c82e9SRob Clark 657057cfe41cSRob Clark #define REG_A6XX_SP_CS_CNTL_0 0x0000a9c2 657157cfe41cSRob Clark #define A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff 657257cfe41cSRob Clark #define A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT 0 657357cfe41cSRob Clark static inline uint32_t A6XX_SP_CS_CNTL_0_WGIDCONSTID(uint32_t val) 657457cfe41cSRob Clark { 657557cfe41cSRob Clark return ((val) << A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK; 657657cfe41cSRob Clark } 657757cfe41cSRob Clark #define A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK 0x0000ff00 657857cfe41cSRob Clark #define A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT 8 657957cfe41cSRob Clark static inline uint32_t A6XX_SP_CS_CNTL_0_WGSIZECONSTID(uint32_t val) 658057cfe41cSRob Clark { 658157cfe41cSRob Clark return ((val) << A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK; 658257cfe41cSRob Clark } 658357cfe41cSRob Clark #define A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK 0x00ff0000 658457cfe41cSRob Clark #define A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT 16 658557cfe41cSRob Clark static inline uint32_t A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val) 658657cfe41cSRob Clark { 658757cfe41cSRob Clark return ((val) << A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK; 658857cfe41cSRob Clark } 658957cfe41cSRob Clark #define A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000 659057cfe41cSRob Clark #define A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT 24 659157cfe41cSRob Clark static inline uint32_t A6XX_SP_CS_CNTL_0_LOCALIDREGID(uint32_t val) 659257cfe41cSRob Clark { 659357cfe41cSRob Clark return ((val) << A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK; 659457cfe41cSRob Clark } 659557cfe41cSRob Clark 659657cfe41cSRob Clark #define REG_A6XX_SP_CS_CNTL_1 0x0000a9c3 659757cfe41cSRob Clark #define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff 659857cfe41cSRob Clark #define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0 659957cfe41cSRob Clark static inline uint32_t A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) 660057cfe41cSRob Clark { 660157cfe41cSRob Clark return ((val) << A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK; 660257cfe41cSRob Clark } 660357cfe41cSRob Clark #define A6XX_SP_CS_CNTL_1_SINGLE_SP_CORE 0x00000100 660457cfe41cSRob Clark #define A6XX_SP_CS_CNTL_1_THREADSIZE__MASK 0x00000200 660557cfe41cSRob Clark #define A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT 9 660657cfe41cSRob Clark static inline uint32_t A6XX_SP_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) 660757cfe41cSRob Clark { 660857cfe41cSRob Clark return ((val) << A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_SP_CS_CNTL_1_THREADSIZE__MASK; 660957cfe41cSRob Clark } 661057cfe41cSRob Clark #define A6XX_SP_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400 661157cfe41cSRob Clark 6612cc4c26d4SRob Clark #define REG_A6XX_SP_FS_TEX_SAMP 0x0000a9e0 6613cc4c26d4SRob Clark #define A6XX_SP_FS_TEX_SAMP__MASK 0xffffffff 6614cc4c26d4SRob Clark #define A6XX_SP_FS_TEX_SAMP__SHIFT 0 6615cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_TEX_SAMP(uint32_t val) 6616cc4c26d4SRob Clark { 6617cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_TEX_SAMP__SHIFT) & A6XX_SP_FS_TEX_SAMP__MASK; 6618cc4c26d4SRob Clark } 6619cc4c26d4SRob Clark 6620cc4c26d4SRob Clark #define REG_A6XX_SP_CS_TEX_SAMP 0x0000a9e2 6621cc4c26d4SRob Clark #define A6XX_SP_CS_TEX_SAMP__MASK 0xffffffff 6622cc4c26d4SRob Clark #define A6XX_SP_CS_TEX_SAMP__SHIFT 0 6623cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_TEX_SAMP(uint32_t val) 6624cc4c26d4SRob Clark { 6625cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_TEX_SAMP__SHIFT) & A6XX_SP_CS_TEX_SAMP__MASK; 6626cc4c26d4SRob Clark } 6627cc4c26d4SRob Clark 6628cc4c26d4SRob Clark #define REG_A6XX_SP_FS_TEX_CONST 0x0000a9e4 6629cc4c26d4SRob Clark #define A6XX_SP_FS_TEX_CONST__MASK 0xffffffff 6630cc4c26d4SRob Clark #define A6XX_SP_FS_TEX_CONST__SHIFT 0 6631cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_TEX_CONST(uint32_t val) 6632cc4c26d4SRob Clark { 6633cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_TEX_CONST__SHIFT) & A6XX_SP_FS_TEX_CONST__MASK; 6634cc4c26d4SRob Clark } 6635cc4c26d4SRob Clark 6636cc4c26d4SRob Clark #define REG_A6XX_SP_CS_TEX_CONST 0x0000a9e6 6637cc4c26d4SRob Clark #define A6XX_SP_CS_TEX_CONST__MASK 0xffffffff 6638cc4c26d4SRob Clark #define A6XX_SP_CS_TEX_CONST__SHIFT 0 6639cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_TEX_CONST(uint32_t val) 6640cc4c26d4SRob Clark { 6641cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_TEX_CONST__SHIFT) & A6XX_SP_CS_TEX_CONST__MASK; 6642cc4c26d4SRob Clark } 6643cc4c26d4SRob Clark 6644cc4c26d4SRob Clark static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; } 6645cc4c26d4SRob Clark 6646*f73343faSRob Clark static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; } 6647*f73343faSRob Clark #define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 6648*f73343faSRob Clark #define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0 6649*f73343faSRob Clark static inline uint32_t A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) 6650*f73343faSRob Clark { 6651*f73343faSRob Clark return ((val) << A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; 6652*f73343faSRob Clark } 6653*f73343faSRob Clark #define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffc 6654*f73343faSRob Clark #define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 6655*f73343faSRob Clark static inline uint32_t A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val) 6656*f73343faSRob Clark { 6657*f73343faSRob Clark return ((val >> 2) << A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; 6658*f73343faSRob Clark } 6659cc4c26d4SRob Clark 6660cc4c26d4SRob Clark #define REG_A6XX_SP_CS_IBO 0x0000a9f2 6661cc4c26d4SRob Clark #define A6XX_SP_CS_IBO__MASK 0xffffffff 6662cc4c26d4SRob Clark #define A6XX_SP_CS_IBO__SHIFT 0 6663cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_IBO(uint32_t val) 6664cc4c26d4SRob Clark { 6665cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_IBO__SHIFT) & A6XX_SP_CS_IBO__MASK; 6666cc4c26d4SRob Clark } 6667c28c82e9SRob Clark 6668c28c82e9SRob Clark #define REG_A6XX_SP_CS_IBO_COUNT 0x0000aa00 6669c28c82e9SRob Clark 6670cc4c26d4SRob Clark #define REG_A6XX_SP_MODE_CONTROL 0x0000ab00 6671cc4c26d4SRob Clark #define A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE 0x00000001 667257cfe41cSRob Clark #define A6XX_SP_MODE_CONTROL_ISAMMODE__MASK 0x00000006 667357cfe41cSRob Clark #define A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT 1 667457cfe41cSRob Clark static inline uint32_t A6XX_SP_MODE_CONTROL_ISAMMODE(enum a6xx_isam_mode val) 667557cfe41cSRob Clark { 667657cfe41cSRob Clark return ((val) << A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT) & A6XX_SP_MODE_CONTROL_ISAMMODE__MASK; 667757cfe41cSRob Clark } 6678cc4c26d4SRob Clark #define A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE 0x00000008 66792d756322SRob Clark 66802d756322SRob Clark #define REG_A6XX_SP_FS_CONFIG 0x0000ab04 6681c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_BINDLESS_TEX 0x00000001 6682c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_BINDLESS_SAMP 0x00000002 6683c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_BINDLESS_IBO 0x00000004 6684c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_BINDLESS_UBO 0x00000008 66852d756322SRob Clark #define A6XX_SP_FS_CONFIG_ENABLED 0x00000100 66862d756322SRob Clark #define A6XX_SP_FS_CONFIG_NTEX__MASK 0x0001fe00 66872d756322SRob Clark #define A6XX_SP_FS_CONFIG_NTEX__SHIFT 9 66882d756322SRob Clark static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val) 66892d756322SRob Clark { 66902d756322SRob Clark return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK; 66912d756322SRob Clark } 6692c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_NSAMP__MASK 0x003e0000 66932d756322SRob Clark #define A6XX_SP_FS_CONFIG_NSAMP__SHIFT 17 66942d756322SRob Clark static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val) 66952d756322SRob Clark { 66962d756322SRob Clark return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK; 66972d756322SRob Clark } 6698cc4c26d4SRob Clark #define A6XX_SP_FS_CONFIG_NIBO__MASK 0x1fc00000 6699c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_NIBO__SHIFT 22 6700c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val) 6701c28c82e9SRob Clark { 6702c28c82e9SRob Clark return ((val) << A6XX_SP_FS_CONFIG_NIBO__SHIFT) & A6XX_SP_FS_CONFIG_NIBO__MASK; 6703c28c82e9SRob Clark } 67042d756322SRob Clark 67052d756322SRob Clark #define REG_A6XX_SP_FS_INSTRLEN 0x0000ab05 67062d756322SRob Clark 6707c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_BINDLESS_BASE(uint32_t i0) { return 0x0000ab10 + 0x2*i0; } 6708a69c5ed2SRob Clark 6709*f73343faSRob Clark static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; } 6710*f73343faSRob Clark #define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 6711*f73343faSRob Clark #define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0 6712*f73343faSRob Clark static inline uint32_t A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) 6713*f73343faSRob Clark { 6714*f73343faSRob Clark return ((val) << A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; 6715*f73343faSRob Clark } 6716*f73343faSRob Clark #define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffc 6717*f73343faSRob Clark #define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 6718*f73343faSRob Clark static inline uint32_t A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val) 6719*f73343faSRob Clark { 6720*f73343faSRob Clark return ((val >> 2) << A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; 6721*f73343faSRob Clark } 6722c28c82e9SRob Clark 6723cc4c26d4SRob Clark #define REG_A6XX_SP_IBO 0x0000ab1a 6724cc4c26d4SRob Clark #define A6XX_SP_IBO__MASK 0xffffffff 6725cc4c26d4SRob Clark #define A6XX_SP_IBO__SHIFT 0 6726cc4c26d4SRob Clark static inline uint32_t A6XX_SP_IBO(uint32_t val) 6727cc4c26d4SRob Clark { 6728cc4c26d4SRob Clark return ((val) << A6XX_SP_IBO__SHIFT) & A6XX_SP_IBO__MASK; 6729cc4c26d4SRob Clark } 6730c28c82e9SRob Clark 6731c28c82e9SRob Clark #define REG_A6XX_SP_IBO_COUNT 0x0000ab20 6732c28c82e9SRob Clark 6733c28c82e9SRob Clark #define REG_A6XX_SP_2D_DST_FORMAT 0x0000acc0 6734c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_NORM 0x00000001 6735c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_SINT 0x00000002 6736c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_UINT 0x00000004 6737c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK 0x000007f8 6738c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT 3 6739c28c82e9SRob Clark static inline uint32_t A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val) 6740c28c82e9SRob Clark { 6741c28c82e9SRob Clark return ((val) << A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT) & A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK; 6742c28c82e9SRob Clark } 6743c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_SRGB 0x00000800 6744c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_MASK__MASK 0x0000f000 6745c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_MASK__SHIFT 12 6746c28c82e9SRob Clark static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val) 6747c28c82e9SRob Clark { 6748c28c82e9SRob Clark return ((val) << A6XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A6XX_SP_2D_DST_FORMAT_MASK__MASK; 6749c28c82e9SRob Clark } 6750ccdf7e28SRob Clark 6751*f73343faSRob Clark #define REG_A6XX_SP_DBG_ECO_CNTL 0x0000ae00 67522d756322SRob Clark 6753cc4c26d4SRob Clark #define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01 6754cc4c26d4SRob Clark 6755cc4c26d4SRob Clark #define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02 6756cc4c26d4SRob Clark 675757cfe41cSRob Clark #define REG_A6XX_SP_CHICKEN_BITS 0x0000ae03 6758a69c5ed2SRob Clark 6759cc4c26d4SRob Clark #define REG_A6XX_SP_FLOAT_CNTL 0x0000ae04 6760cc4c26d4SRob Clark #define A6XX_SP_FLOAT_CNTL_F16_NO_INF 0x00000008 67612d756322SRob Clark 6762cc4c26d4SRob Clark #define REG_A6XX_SP_PERFCTR_ENABLE 0x0000ae0f 6763cc4c26d4SRob Clark #define A6XX_SP_PERFCTR_ENABLE_VS 0x00000001 6764cc4c26d4SRob Clark #define A6XX_SP_PERFCTR_ENABLE_HS 0x00000002 6765cc4c26d4SRob Clark #define A6XX_SP_PERFCTR_ENABLE_DS 0x00000004 6766cc4c26d4SRob Clark #define A6XX_SP_PERFCTR_ENABLE_GS 0x00000008 6767cc4c26d4SRob Clark #define A6XX_SP_PERFCTR_ENABLE_FS 0x00000010 6768cc4c26d4SRob Clark #define A6XX_SP_PERFCTR_ENABLE_CS 0x00000020 6769cc4c26d4SRob Clark 6770cc4c26d4SRob Clark static inline uint32_t REG_A6XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae10 + 0x1*i0; } 67712d756322SRob Clark 6772*f73343faSRob Clark static inline uint32_t REG_A7XX_SP_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000ae60 + 0x1*i0; } 6773*f73343faSRob Clark 6774*f73343faSRob Clark #define REG_A7XX_SP_READ_SEL 0x0000ae6d 6775*f73343faSRob Clark 6776*f73343faSRob Clark static inline uint32_t REG_A7XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae80 + 0x1*i0; } 6777*f73343faSRob Clark 677857cfe41cSRob Clark #define REG_A6XX_SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE 0x0000be22 677957cfe41cSRob Clark 6780c28c82e9SRob Clark #define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR 0x0000b180 6781cc4c26d4SRob Clark #define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff 6782cc4c26d4SRob Clark #define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0 6783cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(uint32_t val) 6784cc4c26d4SRob Clark { 6785cc4c26d4SRob Clark return ((val) << A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK; 6786cc4c26d4SRob Clark } 6787c28c82e9SRob Clark 67882d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_B182 0x0000b182 67892d756322SRob Clark 6790a69c5ed2SRob Clark #define REG_A6XX_SP_UNKNOWN_B183 0x0000b183 6791a69c5ed2SRob Clark 6792cc4c26d4SRob Clark #define REG_A6XX_SP_UNKNOWN_B190 0x0000b190 6793cc4c26d4SRob Clark 6794cc4c26d4SRob Clark #define REG_A6XX_SP_UNKNOWN_B191 0x0000b191 6795cc4c26d4SRob Clark 67962d756322SRob Clark #define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300 67972d756322SRob Clark #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 67982d756322SRob Clark #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 67992d756322SRob Clark static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 68002d756322SRob Clark { 68012d756322SRob Clark return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK; 68022d756322SRob Clark } 6803cc4c26d4SRob Clark #define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK 0x0000000c 6804cc4c26d4SRob Clark #define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT 2 6805cc4c26d4SRob Clark static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_UNK2(uint32_t val) 6806cc4c26d4SRob Clark { 6807cc4c26d4SRob Clark return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK; 6808cc4c26d4SRob Clark } 68092d756322SRob Clark 68102d756322SRob Clark #define REG_A6XX_SP_TP_DEST_MSAA_CNTL 0x0000b301 68112d756322SRob Clark #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 68122d756322SRob Clark #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 68132d756322SRob Clark static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 68142d756322SRob Clark { 68152d756322SRob Clark return ((val) << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK; 68162d756322SRob Clark } 68172d756322SRob Clark #define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 68182d756322SRob Clark 6819c28c82e9SRob Clark #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR 0x0000b302 6820cc4c26d4SRob Clark #define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff 6821cc4c26d4SRob Clark #define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0 6822cc4c26d4SRob Clark static inline uint32_t A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(uint32_t val) 6823cc4c26d4SRob Clark { 6824cc4c26d4SRob Clark return ((val) << A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK; 6825cc4c26d4SRob Clark } 68262d756322SRob Clark 6827c28c82e9SRob Clark #define REG_A6XX_SP_TP_SAMPLE_CONFIG 0x0000b304 6828c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_CONFIG_UNK0 0x00000001 6829c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002 6830c28c82e9SRob Clark 6831c28c82e9SRob Clark #define REG_A6XX_SP_TP_SAMPLE_LOCATION_0 0x0000b305 6832c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f 6833c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 6834c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) 6835c28c82e9SRob Clark { 6836c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; 6837c28c82e9SRob Clark } 6838c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 6839c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 6840c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) 6841c28c82e9SRob Clark { 6842c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; 6843c28c82e9SRob Clark } 6844c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 6845c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 6846c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) 6847c28c82e9SRob Clark { 6848c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; 6849c28c82e9SRob Clark } 6850c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 6851c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 6852c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) 6853c28c82e9SRob Clark { 6854c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; 6855c28c82e9SRob Clark } 6856c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 6857c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 6858c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) 6859c28c82e9SRob Clark { 6860c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; 6861c28c82e9SRob Clark } 6862c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 6863c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 6864c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) 6865c28c82e9SRob Clark { 6866c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; 6867c28c82e9SRob Clark } 6868c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 6869c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 6870c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) 6871c28c82e9SRob Clark { 6872c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; 6873c28c82e9SRob Clark } 6874c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 6875c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 6876c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) 6877c28c82e9SRob Clark { 6878c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; 6879c28c82e9SRob Clark } 6880c28c82e9SRob Clark 6881c28c82e9SRob Clark #define REG_A6XX_SP_TP_SAMPLE_LOCATION_1 0x0000b306 6882c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f 6883c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 6884c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) 6885c28c82e9SRob Clark { 6886c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; 6887c28c82e9SRob Clark } 6888c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 6889c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 6890c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) 6891c28c82e9SRob Clark { 6892c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; 6893c28c82e9SRob Clark } 6894c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 6895c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 6896c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) 6897c28c82e9SRob Clark { 6898c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; 6899c28c82e9SRob Clark } 6900c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 6901c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 6902c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) 6903c28c82e9SRob Clark { 6904c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; 6905c28c82e9SRob Clark } 6906c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 6907c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 6908c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) 6909c28c82e9SRob Clark { 6910c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; 6911c28c82e9SRob Clark } 6912c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 6913c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 6914c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) 6915c28c82e9SRob Clark { 6916c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; 6917c28c82e9SRob Clark } 6918c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 6919c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 6920c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) 6921c28c82e9SRob Clark { 6922c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; 6923c28c82e9SRob Clark } 6924c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 6925c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 6926c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) 6927c28c82e9SRob Clark { 6928c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; 6929c28c82e9SRob Clark } 69302d756322SRob Clark 6931cc4c26d4SRob Clark #define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307 6932cc4c26d4SRob Clark #define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00003fff 6933cc4c26d4SRob Clark #define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0 6934cc4c26d4SRob Clark static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val) 6935cc4c26d4SRob Clark { 6936cc4c26d4SRob Clark return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK; 6937cc4c26d4SRob Clark } 6938cc4c26d4SRob Clark #define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x3fff0000 6939cc4c26d4SRob Clark #define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16 6940cc4c26d4SRob Clark static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val) 6941cc4c26d4SRob Clark { 6942cc4c26d4SRob Clark return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK; 6943cc4c26d4SRob Clark } 6944cc4c26d4SRob Clark 694557cfe41cSRob Clark #define REG_A6XX_SP_TP_MODE_CNTL 0x0000b309 694657cfe41cSRob Clark #define A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK 0x00000003 694757cfe41cSRob Clark #define A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT 0 694857cfe41cSRob Clark static inline uint32_t A6XX_SP_TP_MODE_CNTL_ISAMMODE(enum a6xx_isam_mode val) 694957cfe41cSRob Clark { 695057cfe41cSRob Clark return ((val) << A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT) & A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK; 695157cfe41cSRob Clark } 695257cfe41cSRob Clark #define A6XX_SP_TP_MODE_CNTL_UNK3__MASK 0x000000fc 695357cfe41cSRob Clark #define A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT 2 695457cfe41cSRob Clark static inline uint32_t A6XX_SP_TP_MODE_CNTL_UNK3(uint32_t val) 695557cfe41cSRob Clark { 695657cfe41cSRob Clark return ((val) << A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT) & A6XX_SP_TP_MODE_CNTL_UNK3__MASK; 695757cfe41cSRob Clark } 6958a69c5ed2SRob Clark 69592d756322SRob Clark #define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0 69602d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff 69612d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 6962c28c82e9SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val) 69632d756322SRob Clark { 69642d756322SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK; 69652d756322SRob Clark } 69662d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300 69672d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT 8 69682d756322SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val) 69692d756322SRob Clark { 69702d756322SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK; 69712d756322SRob Clark } 69722d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00 69732d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10 69742d756322SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) 69752d756322SRob Clark { 69762d756322SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK; 69772d756322SRob Clark } 69782d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000 6979c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_SRGB 0x00002000 6980c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK 0x0000c000 6981c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT 14 6982c28c82e9SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val) 6983c28c82e9SRob Clark { 6984c28c82e9SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK; 6985c28c82e9SRob Clark } 6986ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000 6987cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK17 0x00020000 6988c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE 0x00040000 6989cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK19 0x00080000 6990c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK20 0x00100000 6991cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK21 0x00200000 6992c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK22 0x00400000 6993cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK 0x07800000 6994cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT 23 6995cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val) 6996cc4c26d4SRob Clark { 6997cc4c26d4SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK; 6998cc4c26d4SRob Clark } 6999cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK28 0x10000000 7000ccdf7e28SRob Clark 7001ccdf7e28SRob Clark #define REG_A6XX_SP_PS_2D_SRC_SIZE 0x0000b4c1 7002ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff 7003ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT 0 7004ccdf7e28SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val) 7005ccdf7e28SRob Clark { 7006ccdf7e28SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK; 7007ccdf7e28SRob Clark } 7008ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK 0x3fff8000 7009ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT 15 7010ccdf7e28SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val) 7011ccdf7e28SRob Clark { 7012ccdf7e28SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK; 7013ccdf7e28SRob Clark } 70142d756322SRob Clark 7015c28c82e9SRob Clark #define REG_A6XX_SP_PS_2D_SRC 0x0000b4c2 7016cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC__MASK 0xffffffff 7017cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC__SHIFT 0 7018cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC(uint32_t val) 7019cc4c26d4SRob Clark { 7020cc4c26d4SRob Clark return ((val) << A6XX_SP_PS_2D_SRC__SHIFT) & A6XX_SP_PS_2D_SRC__MASK; 7021cc4c26d4SRob Clark } 7022c28c82e9SRob Clark 7023ccdf7e28SRob Clark #define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4 7024cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK 0x000001ff 7025cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT 0 7026cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val) 7027cc4c26d4SRob Clark { 7028cc4c26d4SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK; 7029cc4c26d4SRob Clark } 7030cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x00fffe00 7031ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9 7032ccdf7e28SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val) 7033ccdf7e28SRob Clark { 7034ccdf7e28SRob Clark return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK; 7035ccdf7e28SRob Clark } 7036ccdf7e28SRob Clark 7037cc4c26d4SRob Clark #define REG_A6XX_SP_PS_2D_SRC_PLANE1 0x0000b4c5 7038cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PLANE1__MASK 0xffffffff 7039cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PLANE1__SHIFT 0 7040cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE1(uint32_t val) 7041cc4c26d4SRob Clark { 7042cc4c26d4SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_PLANE1__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE1__MASK; 7043cc4c26d4SRob Clark } 70442d756322SRob Clark 7045cc4c26d4SRob Clark #define REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH 0x0000b4c7 7046cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK 0x00000fff 7047cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT 0 7048cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val) 7049cc4c26d4SRob Clark { 7050cc4c26d4SRob Clark return ((val >> 6) << A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK; 7051cc4c26d4SRob Clark } 7052cc4c26d4SRob Clark 7053cc4c26d4SRob Clark #define REG_A6XX_SP_PS_2D_SRC_PLANE2 0x0000b4c8 7054cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PLANE2__MASK 0xffffffff 7055cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PLANE2__SHIFT 0 7056cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE2(uint32_t val) 7057cc4c26d4SRob Clark { 7058cc4c26d4SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_PLANE2__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE2__MASK; 7059cc4c26d4SRob Clark } 70602d756322SRob Clark 7061c28c82e9SRob Clark #define REG_A6XX_SP_PS_2D_SRC_FLAGS 0x0000b4ca 7062cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_FLAGS__MASK 0xffffffff 7063cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_FLAGS__SHIFT 0 7064cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS(uint32_t val) 7065cc4c26d4SRob Clark { 7066cc4c26d4SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_FLAGS__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS__MASK; 7067cc4c26d4SRob Clark } 7068c28c82e9SRob Clark 7069c28c82e9SRob Clark #define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b4cc 7070cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK 0x000000ff 7071cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT 0 7072cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val) 7073c28c82e9SRob Clark { 7074cc4c26d4SRob Clark return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK; 7075c28c82e9SRob Clark } 7076c28c82e9SRob Clark 7077cc4c26d4SRob Clark #define REG_A6XX_SP_PS_UNKNOWN_B4CD 0x0000b4cd 70782d756322SRob Clark 7079cc4c26d4SRob Clark #define REG_A6XX_SP_PS_UNKNOWN_B4CE 0x0000b4ce 7080cc4c26d4SRob Clark 7081cc4c26d4SRob Clark #define REG_A6XX_SP_PS_UNKNOWN_B4CF 0x0000b4cf 7082cc4c26d4SRob Clark 7083cc4c26d4SRob Clark #define REG_A6XX_SP_PS_UNKNOWN_B4D0 0x0000b4d0 7084cc4c26d4SRob Clark 7085cc4c26d4SRob Clark #define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1 7086cc4c26d4SRob Clark #define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00003fff 7087cc4c26d4SRob Clark #define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0 7088cc4c26d4SRob Clark static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val) 7089cc4c26d4SRob Clark { 7090cc4c26d4SRob Clark return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK; 7091cc4c26d4SRob Clark } 7092cc4c26d4SRob Clark #define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x3fff0000 7093cc4c26d4SRob Clark #define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16 7094cc4c26d4SRob Clark static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val) 7095cc4c26d4SRob Clark { 7096cc4c26d4SRob Clark return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK; 7097cc4c26d4SRob Clark } 7098cc4c26d4SRob Clark 709957cfe41cSRob Clark #define REG_A6XX_TPL1_DBG_ECO_CNTL 0x0000b600 7100cc4c26d4SRob Clark 7101cc4c26d4SRob Clark #define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601 7102cc4c26d4SRob Clark 7103cc4c26d4SRob Clark #define REG_A6XX_TPL1_UNKNOWN_B602 0x0000b602 7104cc4c26d4SRob Clark 7105cc4c26d4SRob Clark #define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604 7106cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_MODE 0x00000001 7107cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006 7108cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT 1 7109cc4c26d4SRob Clark static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT(uint32_t val) 7110cc4c26d4SRob Clark { 7111cc4c26d4SRob Clark return ((val) << A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK; 7112cc4c26d4SRob Clark } 7113cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008 7114cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000010 7115cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT 4 7116cc4c26d4SRob Clark static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT(uint32_t val) 7117cc4c26d4SRob Clark { 7118cc4c26d4SRob Clark return ((val) << A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK; 7119cc4c26d4SRob Clark } 7120cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK 0x000000c0 7121cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT 6 7122cc4c26d4SRob Clark static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UNK6(uint32_t val) 7123cc4c26d4SRob Clark { 7124cc4c26d4SRob Clark return ((val) << A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK; 7125cc4c26d4SRob Clark } 7126cc4c26d4SRob Clark 7127cc4c26d4SRob Clark #define REG_A6XX_TPL1_UNKNOWN_B605 0x0000b605 7128cc4c26d4SRob Clark 7129cc4c26d4SRob Clark #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608 7130cc4c26d4SRob Clark 7131cc4c26d4SRob Clark #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609 7132cc4c26d4SRob Clark 7133cc4c26d4SRob Clark #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a 7134cc4c26d4SRob Clark 7135cc4c26d4SRob Clark #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b 7136cc4c26d4SRob Clark 7137cc4c26d4SRob Clark #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c 7138cc4c26d4SRob Clark 7139cc4c26d4SRob Clark static inline uint32_t REG_A6XX_TPL1_PERFCTR_TP_SEL(uint32_t i0) { return 0x0000b610 + 0x1*i0; } 71402d756322SRob Clark 71412d756322SRob Clark #define REG_A6XX_HLSQ_VS_CNTL 0x0000b800 71422d756322SRob Clark #define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff 71432d756322SRob Clark #define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0 71442d756322SRob Clark static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val) 71452d756322SRob Clark { 71462d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK; 71472d756322SRob Clark } 7148c28c82e9SRob Clark #define A6XX_HLSQ_VS_CNTL_ENABLED 0x00000100 71492d756322SRob Clark 71502d756322SRob Clark #define REG_A6XX_HLSQ_HS_CNTL 0x0000b801 71512d756322SRob Clark #define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff 71522d756322SRob Clark #define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0 71532d756322SRob Clark static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val) 71542d756322SRob Clark { 71552d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK; 71562d756322SRob Clark } 7157c28c82e9SRob Clark #define A6XX_HLSQ_HS_CNTL_ENABLED 0x00000100 71582d756322SRob Clark 71592d756322SRob Clark #define REG_A6XX_HLSQ_DS_CNTL 0x0000b802 71602d756322SRob Clark #define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff 71612d756322SRob Clark #define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0 71622d756322SRob Clark static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val) 71632d756322SRob Clark { 71642d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK; 71652d756322SRob Clark } 7166c28c82e9SRob Clark #define A6XX_HLSQ_DS_CNTL_ENABLED 0x00000100 71672d756322SRob Clark 71682d756322SRob Clark #define REG_A6XX_HLSQ_GS_CNTL 0x0000b803 71692d756322SRob Clark #define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff 71702d756322SRob Clark #define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0 71712d756322SRob Clark static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val) 71722d756322SRob Clark { 71732d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK; 71742d756322SRob Clark } 7175c28c82e9SRob Clark #define A6XX_HLSQ_GS_CNTL_ENABLED 0x00000100 7176c28c82e9SRob Clark 7177c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD 0x0000b820 7178c28c82e9SRob Clark 7179c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR 0x0000b821 7180cc4c26d4SRob Clark #define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK 0xffffffff 7181cc4c26d4SRob Clark #define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT 0 7182cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR(uint32_t val) 7183cc4c26d4SRob Clark { 7184cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK; 7185cc4c26d4SRob Clark } 7186c28c82e9SRob Clark 7187c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA 0x0000b823 71882d756322SRob Clark 7189cc4c26d4SRob Clark #define REG_A6XX_HLSQ_FS_CNTL_0 0x0000b980 7190cc4c26d4SRob Clark #define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK 0x00000001 7191cc4c26d4SRob Clark #define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT 0 7192cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val) 7193cc4c26d4SRob Clark { 7194cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK; 7195cc4c26d4SRob Clark } 7196cc4c26d4SRob Clark #define A6XX_HLSQ_FS_CNTL_0_VARYINGS 0x00000002 7197cc4c26d4SRob Clark #define A6XX_HLSQ_FS_CNTL_0_UNK2__MASK 0x00000ffc 7198cc4c26d4SRob Clark #define A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT 2 7199cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val) 7200cc4c26d4SRob Clark { 7201cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A6XX_HLSQ_FS_CNTL_0_UNK2__MASK; 7202cc4c26d4SRob Clark } 7203cc4c26d4SRob Clark 7204cc4c26d4SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_B981 0x0000b981 7205a69c5ed2SRob Clark 72062d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982 72072d756322SRob Clark 7208*f73343faSRob Clark #define REG_A7XX_HLSQ_CONTROL_1_REG 0x0000a9c7 7209*f73343faSRob Clark 72102d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_2_REG 0x0000b983 72112d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff 72122d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0 72132d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) 72142d756322SRob Clark { 72152d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; 72162d756322SRob Clark } 72172d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00 72182d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8 72192d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) 72202d756322SRob Clark { 72212d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK; 72222d756322SRob Clark } 72232d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000 72242d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16 72252d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) 72262d756322SRob Clark { 72272d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK; 72282d756322SRob Clark } 7229*f73343faSRob Clark #define A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK 0xff000000 7230*f73343faSRob Clark #define A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT 24 7231*f73343faSRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val) 7232c28c82e9SRob Clark { 7233*f73343faSRob Clark return ((val) << A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK; 7234*f73343faSRob Clark } 7235*f73343faSRob Clark 7236*f73343faSRob Clark #define REG_A7XX_HLSQ_CONTROL_2_REG 0x0000a9c8 7237*f73343faSRob Clark #define A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff 7238*f73343faSRob Clark #define A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0 7239*f73343faSRob Clark static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) 7240*f73343faSRob Clark { 7241*f73343faSRob Clark return ((val) << A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; 7242*f73343faSRob Clark } 7243*f73343faSRob Clark #define A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00 7244*f73343faSRob Clark #define A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8 7245*f73343faSRob Clark static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) 7246*f73343faSRob Clark { 7247*f73343faSRob Clark return ((val) << A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK; 7248*f73343faSRob Clark } 7249*f73343faSRob Clark #define A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000 7250*f73343faSRob Clark #define A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16 7251*f73343faSRob Clark static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) 7252*f73343faSRob Clark { 7253*f73343faSRob Clark return ((val) << A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK; 7254*f73343faSRob Clark } 7255*f73343faSRob Clark #define A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK 0xff000000 7256*f73343faSRob Clark #define A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT 24 7257*f73343faSRob Clark static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val) 7258*f73343faSRob Clark { 7259*f73343faSRob Clark return ((val) << A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK; 7260c28c82e9SRob Clark } 72612d756322SRob Clark 72622d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_3_REG 0x0000b984 7263c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff 7264c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0 7265c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val) 72662d756322SRob Clark { 7267c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK; 7268c28c82e9SRob Clark } 7269c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00 7270c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8 7271c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val) 7272c28c82e9SRob Clark { 7273c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK; 7274c28c82e9SRob Clark } 7275c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000 7276c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16 7277c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val) 7278c28c82e9SRob Clark { 7279c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK; 7280c28c82e9SRob Clark } 7281c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000 7282c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24 7283c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) 7284c28c82e9SRob Clark { 7285c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK; 72862d756322SRob Clark } 72872d756322SRob Clark 7288*f73343faSRob Clark #define REG_A7XX_HLSQ_CONTROL_3_REG 0x0000a9c9 7289*f73343faSRob Clark #define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff 7290*f73343faSRob Clark #define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0 7291*f73343faSRob Clark static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val) 7292*f73343faSRob Clark { 7293*f73343faSRob Clark return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK; 7294*f73343faSRob Clark } 7295*f73343faSRob Clark #define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00 7296*f73343faSRob Clark #define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8 7297*f73343faSRob Clark static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val) 7298*f73343faSRob Clark { 7299*f73343faSRob Clark return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK; 7300*f73343faSRob Clark } 7301*f73343faSRob Clark #define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000 7302*f73343faSRob Clark #define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16 7303*f73343faSRob Clark static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val) 7304*f73343faSRob Clark { 7305*f73343faSRob Clark return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK; 7306*f73343faSRob Clark } 7307*f73343faSRob Clark #define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000 7308*f73343faSRob Clark #define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24 7309*f73343faSRob Clark static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) 7310*f73343faSRob Clark { 7311*f73343faSRob Clark return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK; 7312*f73343faSRob Clark } 7313*f73343faSRob Clark 73142d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_4_REG 0x0000b985 7315c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff 7316c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0 7317c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val) 7318c28c82e9SRob Clark { 7319c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK; 7320c28c82e9SRob Clark } 7321c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00 7322c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8 7323c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val) 7324c28c82e9SRob Clark { 7325c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK; 7326c28c82e9SRob Clark } 73272d756322SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000 73282d756322SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16 73292d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) 73302d756322SRob Clark { 73312d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK; 73322d756322SRob Clark } 73332d756322SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000 73342d756322SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24 73352d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) 73362d756322SRob Clark { 73372d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; 73382d756322SRob Clark } 73392d756322SRob Clark 7340*f73343faSRob Clark #define REG_A7XX_HLSQ_CONTROL_4_REG 0x0000a9ca 7341*f73343faSRob Clark #define A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff 7342*f73343faSRob Clark #define A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0 7343*f73343faSRob Clark static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val) 7344*f73343faSRob Clark { 7345*f73343faSRob Clark return ((val) << A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK; 7346*f73343faSRob Clark } 7347*f73343faSRob Clark #define A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00 7348*f73343faSRob Clark #define A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8 7349*f73343faSRob Clark static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val) 7350*f73343faSRob Clark { 7351*f73343faSRob Clark return ((val) << A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK; 7352*f73343faSRob Clark } 7353*f73343faSRob Clark #define A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000 7354*f73343faSRob Clark #define A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16 7355*f73343faSRob Clark static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) 7356*f73343faSRob Clark { 7357*f73343faSRob Clark return ((val) << A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK; 7358*f73343faSRob Clark } 7359*f73343faSRob Clark #define A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000 7360*f73343faSRob Clark #define A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24 7361*f73343faSRob Clark static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) 7362*f73343faSRob Clark { 7363*f73343faSRob Clark return ((val) << A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; 7364*f73343faSRob Clark } 7365*f73343faSRob Clark 73662d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986 736757cfe41cSRob Clark #define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK 0x000000ff 736857cfe41cSRob Clark #define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT 0 736957cfe41cSRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val) 7370cc4c26d4SRob Clark { 737157cfe41cSRob Clark return ((val) << A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK; 7372cc4c26d4SRob Clark } 737357cfe41cSRob Clark #define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK 0x0000ff00 737457cfe41cSRob Clark #define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT 8 737557cfe41cSRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val) 7376cc4c26d4SRob Clark { 737757cfe41cSRob Clark return ((val) << A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK; 7378cc4c26d4SRob Clark } 73792d756322SRob Clark 7380*f73343faSRob Clark #define REG_A7XX_HLSQ_CONTROL_5_REG 0x0000a9cb 7381*f73343faSRob Clark #define A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK 0x000000ff 7382*f73343faSRob Clark #define A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT 0 7383*f73343faSRob Clark static inline uint32_t A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val) 7384*f73343faSRob Clark { 7385*f73343faSRob Clark return ((val) << A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK; 7386*f73343faSRob Clark } 7387*f73343faSRob Clark #define A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK 0x0000ff00 7388*f73343faSRob Clark #define A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT 8 7389*f73343faSRob Clark static inline uint32_t A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val) 7390*f73343faSRob Clark { 7391*f73343faSRob Clark return ((val) << A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK; 7392*f73343faSRob Clark } 7393*f73343faSRob Clark 7394c28c82e9SRob Clark #define REG_A6XX_HLSQ_CS_CNTL 0x0000b987 7395c28c82e9SRob Clark #define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff 7396c28c82e9SRob Clark #define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0 7397c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val) 7398c28c82e9SRob Clark { 7399c28c82e9SRob Clark return ((val >> 2) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK; 7400c28c82e9SRob Clark } 7401c28c82e9SRob Clark #define A6XX_HLSQ_CS_CNTL_ENABLED 0x00000100 7402c28c82e9SRob Clark 74032d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_0 0x0000b990 74042d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003 74052d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0 74062d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) 74072d756322SRob Clark { 74082d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK; 74092d756322SRob Clark } 74102d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc 74112d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2 74122d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) 74132d756322SRob Clark { 74142d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK; 74152d756322SRob Clark } 74162d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000 74172d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12 74182d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) 74192d756322SRob Clark { 74202d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK; 74212d756322SRob Clark } 74222d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000 74232d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22 74242d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) 74252d756322SRob Clark { 74262d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK; 74272d756322SRob Clark } 74282d756322SRob Clark 74292d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_1 0x0000b991 74302d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff 74312d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0 74322d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val) 74332d756322SRob Clark { 74342d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK; 74352d756322SRob Clark } 74362d756322SRob Clark 74372d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_2 0x0000b992 74382d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff 74392d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0 74402d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val) 74412d756322SRob Clark { 74422d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK; 74432d756322SRob Clark } 74442d756322SRob Clark 74452d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_3 0x0000b993 74462d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff 74472d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0 74482d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val) 74492d756322SRob Clark { 74502d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK; 74512d756322SRob Clark } 74522d756322SRob Clark 74532d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_4 0x0000b994 74542d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff 74552d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0 74562d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val) 74572d756322SRob Clark { 74582d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK; 74592d756322SRob Clark } 74602d756322SRob Clark 74612d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_5 0x0000b995 74622d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff 74632d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0 74642d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val) 74652d756322SRob Clark { 74662d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK; 74672d756322SRob Clark } 74682d756322SRob Clark 74692d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_6 0x0000b996 74702d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff 74712d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0 74722d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val) 74732d756322SRob Clark { 74742d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK; 74752d756322SRob Clark } 74762d756322SRob Clark 74772d756322SRob Clark #define REG_A6XX_HLSQ_CS_CNTL_0 0x0000b997 74782d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff 74792d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0 74802d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val) 74812d756322SRob Clark { 74822d756322SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK; 74832d756322SRob Clark } 7484cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK 0x0000ff00 7485cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT 8 7486cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(uint32_t val) 74872d756322SRob Clark { 7488cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK; 74892d756322SRob Clark } 7490cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK 0x00ff0000 7491cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT 16 7492cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val) 74932d756322SRob Clark { 7494cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK; 74952d756322SRob Clark } 74962d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000 74972d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24 74982d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) 74992d756322SRob Clark { 75002d756322SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK; 75012d756322SRob Clark } 75022d756322SRob Clark 7503cc4c26d4SRob Clark #define REG_A6XX_HLSQ_CS_CNTL_1 0x0000b998 7504cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff 7505cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0 7506cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) 7507cc4c26d4SRob Clark { 7508cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK; 7509cc4c26d4SRob Clark } 7510cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_1_SINGLE_SP_CORE 0x00000100 7511cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK 0x00000200 7512cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT 9 7513cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) 7514cc4c26d4SRob Clark { 7515cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK; 7516cc4c26d4SRob Clark } 7517cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400 7518c28c82e9SRob Clark 75192d756322SRob Clark #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X 0x0000b999 75202d756322SRob Clark 75212d756322SRob Clark #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000b99a 75222d756322SRob Clark 75232d756322SRob Clark #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000b99b 75242d756322SRob Clark 7525c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD 0x0000b9a0 7526c28c82e9SRob Clark 7527c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR 0x0000b9a1 7528cc4c26d4SRob Clark #define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK 0xffffffff 7529cc4c26d4SRob Clark #define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT 0 7530cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR(uint32_t val) 7531cc4c26d4SRob Clark { 7532cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK; 7533cc4c26d4SRob Clark } 7534c28c82e9SRob Clark 7535c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA 0x0000b9a3 7536c28c82e9SRob Clark 7537c28c82e9SRob Clark static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; } 7538c28c82e9SRob Clark 7539*f73343faSRob Clark static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; } 7540*f73343faSRob Clark #define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 7541*f73343faSRob Clark #define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0 7542*f73343faSRob Clark static inline uint32_t A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) 7543*f73343faSRob Clark { 7544*f73343faSRob Clark return ((val) << A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; 7545*f73343faSRob Clark } 7546*f73343faSRob Clark #define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffc 7547*f73343faSRob Clark #define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 7548*f73343faSRob Clark static inline uint32_t A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val) 7549*f73343faSRob Clark { 7550*f73343faSRob Clark return ((val >> 2) << A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; 7551*f73343faSRob Clark } 7552c28c82e9SRob Clark 755357cfe41cSRob Clark #define REG_A6XX_HLSQ_CS_UNKNOWN_B9D0 0x0000b9d0 755457cfe41cSRob Clark #define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK 0x0000001f 755557cfe41cSRob Clark #define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT 0 755657cfe41cSRob Clark static inline uint32_t A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE(uint32_t val) 755757cfe41cSRob Clark { 755857cfe41cSRob Clark return ((val) << A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT) & A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK; 755957cfe41cSRob Clark } 756057cfe41cSRob Clark #define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK5 0x00000020 756157cfe41cSRob Clark #define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK6 0x00000040 756257cfe41cSRob Clark 7563c28c82e9SRob Clark #define REG_A6XX_HLSQ_DRAW_CMD 0x0000bb00 7564c28c82e9SRob Clark #define A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK 0x000000ff 7565c28c82e9SRob Clark #define A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT 0 7566c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_DRAW_CMD_STATE_ID(uint32_t val) 7567c28c82e9SRob Clark { 7568c28c82e9SRob Clark return ((val) << A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK; 7569c28c82e9SRob Clark } 7570c28c82e9SRob Clark 7571c28c82e9SRob Clark #define REG_A6XX_HLSQ_DISPATCH_CMD 0x0000bb01 7572c28c82e9SRob Clark #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK 0x000000ff 7573c28c82e9SRob Clark #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT 0 7574c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_DISPATCH_CMD_STATE_ID(uint32_t val) 7575c28c82e9SRob Clark { 7576c28c82e9SRob Clark return ((val) << A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK; 7577c28c82e9SRob Clark } 7578c28c82e9SRob Clark 7579c28c82e9SRob Clark #define REG_A6XX_HLSQ_EVENT_CMD 0x0000bb02 7580c28c82e9SRob Clark #define A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK 0x00ff0000 7581c28c82e9SRob Clark #define A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT 16 7582c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_EVENT_CMD_STATE_ID(uint32_t val) 7583c28c82e9SRob Clark { 7584c28c82e9SRob Clark return ((val) << A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK; 7585c28c82e9SRob Clark } 7586c28c82e9SRob Clark #define A6XX_HLSQ_EVENT_CMD_EVENT__MASK 0x0000007f 7587c28c82e9SRob Clark #define A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT 0 7588c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_EVENT_CMD_EVENT(enum vgt_event_type val) 7589c28c82e9SRob Clark { 7590c28c82e9SRob Clark return ((val) << A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_EVENT_CMD_EVENT__MASK; 7591c28c82e9SRob Clark } 7592c28c82e9SRob Clark 7593c28c82e9SRob Clark #define REG_A6XX_HLSQ_INVALIDATE_CMD 0x0000bb08 7594c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_VS_STATE 0x00000001 7595c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_HS_STATE 0x00000002 7596c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_DS_STATE 0x00000004 7597c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_GS_STATE 0x00000008 7598c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_FS_STATE 0x00000010 7599c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_CS_STATE 0x00000020 7600c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_CS_IBO 0x00000040 7601c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO 0x00000080 7602c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_CS_SHARED_CONST 0x00080000 7603c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_GFX_SHARED_CONST 0x00000100 7604c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK 0x00003e00 7605c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT 9 7606c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val) 7607c28c82e9SRob Clark { 7608c28c82e9SRob Clark return ((val) << A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK; 7609c28c82e9SRob Clark } 7610c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK 0x0007c000 7611c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT 14 7612c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val) 7613c28c82e9SRob Clark { 7614c28c82e9SRob Clark return ((val) << A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK; 7615c28c82e9SRob Clark } 76162d756322SRob Clark 76172d756322SRob Clark #define REG_A6XX_HLSQ_FS_CNTL 0x0000bb10 76182d756322SRob Clark #define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff 76192d756322SRob Clark #define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0 76202d756322SRob Clark static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val) 76212d756322SRob Clark { 76222d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK; 76232d756322SRob Clark } 7624c28c82e9SRob Clark #define A6XX_HLSQ_FS_CNTL_ENABLED 0x00000100 76252d756322SRob Clark 7626c28c82e9SRob Clark #define REG_A6XX_HLSQ_SHARED_CONSTS 0x0000bb11 7627c28c82e9SRob Clark #define A6XX_HLSQ_SHARED_CONSTS_ENABLE 0x00000001 7628c28c82e9SRob Clark 7629c28c82e9SRob Clark static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE(uint32_t i0) { return 0x0000bb20 + 0x2*i0; } 7630c28c82e9SRob Clark 7631*f73343faSRob Clark static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000bb20 + 0x2*i0; } 7632*f73343faSRob Clark #define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 7633*f73343faSRob Clark #define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0 7634*f73343faSRob Clark static inline uint32_t A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) 7635*f73343faSRob Clark { 7636*f73343faSRob Clark return ((val) << A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; 7637*f73343faSRob Clark } 7638*f73343faSRob Clark #define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffc 7639*f73343faSRob Clark #define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 7640*f73343faSRob Clark static inline uint32_t A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val) 7641*f73343faSRob Clark { 7642*f73343faSRob Clark return ((val >> 2) << A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; 7643*f73343faSRob Clark } 7644c28c82e9SRob Clark 7645c28c82e9SRob Clark #define REG_A6XX_HLSQ_2D_EVENT_CMD 0x0000bd80 7646c28c82e9SRob Clark #define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00 7647c28c82e9SRob Clark #define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT 8 7648c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_STATE_ID(uint32_t val) 7649c28c82e9SRob Clark { 7650c28c82e9SRob Clark return ((val) << A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK; 7651c28c82e9SRob Clark } 7652c28c82e9SRob Clark #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK 0x0000007f 7653c28c82e9SRob Clark #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT 0 7654c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val) 7655c28c82e9SRob Clark { 7656c28c82e9SRob Clark return ((val) << A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK; 7657c28c82e9SRob Clark } 76582d756322SRob Clark 76592d756322SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_BE00 0x0000be00 76602d756322SRob Clark 76612d756322SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_BE01 0x0000be01 76622d756322SRob Clark 7663*f73343faSRob Clark #define REG_A6XX_HLSQ_DBG_ECO_CNTL 0x0000be04 76642d756322SRob Clark 7665cc4c26d4SRob Clark #define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05 7666cc4c26d4SRob Clark 7667cc4c26d4SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_BE08 0x0000be08 7668cc4c26d4SRob Clark 7669cc4c26d4SRob Clark static inline uint32_t REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000be10 + 0x1*i0; } 7670cc4c26d4SRob Clark 767157cfe41cSRob Clark #define REG_A6XX_HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE 0x0000be22 767257cfe41cSRob Clark 7673*f73343faSRob Clark #define REG_A7XX_SP_AHB_READ_APERTURE 0x0000c000 7674*f73343faSRob Clark 7675c28c82e9SRob Clark #define REG_A6XX_CP_EVENT_START 0x0000d600 7676c28c82e9SRob Clark #define A6XX_CP_EVENT_START_STATE_ID__MASK 0x000000ff 7677c28c82e9SRob Clark #define A6XX_CP_EVENT_START_STATE_ID__SHIFT 0 7678c28c82e9SRob Clark static inline uint32_t A6XX_CP_EVENT_START_STATE_ID(uint32_t val) 7679c28c82e9SRob Clark { 7680c28c82e9SRob Clark return ((val) << A6XX_CP_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_EVENT_START_STATE_ID__MASK; 7681c28c82e9SRob Clark } 7682c28c82e9SRob Clark 7683c28c82e9SRob Clark #define REG_A6XX_CP_EVENT_END 0x0000d601 7684c28c82e9SRob Clark #define A6XX_CP_EVENT_END_STATE_ID__MASK 0x000000ff 7685c28c82e9SRob Clark #define A6XX_CP_EVENT_END_STATE_ID__SHIFT 0 7686c28c82e9SRob Clark static inline uint32_t A6XX_CP_EVENT_END_STATE_ID(uint32_t val) 7687c28c82e9SRob Clark { 7688c28c82e9SRob Clark return ((val) << A6XX_CP_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_EVENT_END_STATE_ID__MASK; 7689c28c82e9SRob Clark } 7690c28c82e9SRob Clark 7691c28c82e9SRob Clark #define REG_A6XX_CP_2D_EVENT_START 0x0000d700 7692c28c82e9SRob Clark #define A6XX_CP_2D_EVENT_START_STATE_ID__MASK 0x000000ff 7693c28c82e9SRob Clark #define A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT 0 7694c28c82e9SRob Clark static inline uint32_t A6XX_CP_2D_EVENT_START_STATE_ID(uint32_t val) 7695c28c82e9SRob Clark { 7696c28c82e9SRob Clark return ((val) << A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_START_STATE_ID__MASK; 7697c28c82e9SRob Clark } 7698c28c82e9SRob Clark 7699c28c82e9SRob Clark #define REG_A6XX_CP_2D_EVENT_END 0x0000d701 7700c28c82e9SRob Clark #define A6XX_CP_2D_EVENT_END_STATE_ID__MASK 0x000000ff 7701c28c82e9SRob Clark #define A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT 0 7702c28c82e9SRob Clark static inline uint32_t A6XX_CP_2D_EVENT_END_STATE_ID(uint32_t val) 7703c28c82e9SRob Clark { 7704c28c82e9SRob Clark return ((val) << A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_END_STATE_ID__MASK; 7705c28c82e9SRob Clark } 7706c28c82e9SRob Clark 77072d756322SRob Clark #define REG_A6XX_TEX_SAMP_0 0x00000000 77082d756322SRob Clark #define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 77092d756322SRob Clark #define A6XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 77102d756322SRob Clark #define A6XX_TEX_SAMP_0_XY_MAG__SHIFT 1 77112d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val) 77122d756322SRob Clark { 77132d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_XY_MAG__SHIFT) & A6XX_TEX_SAMP_0_XY_MAG__MASK; 77142d756322SRob Clark } 77152d756322SRob Clark #define A6XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 77162d756322SRob Clark #define A6XX_TEX_SAMP_0_XY_MIN__SHIFT 3 77172d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val) 77182d756322SRob Clark { 77192d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_XY_MIN__SHIFT) & A6XX_TEX_SAMP_0_XY_MIN__MASK; 77202d756322SRob Clark } 77212d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 77222d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_S__SHIFT 5 77232d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val) 77242d756322SRob Clark { 77252d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_WRAP_S__SHIFT) & A6XX_TEX_SAMP_0_WRAP_S__MASK; 77262d756322SRob Clark } 77272d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 77282d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_T__SHIFT 8 77292d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val) 77302d756322SRob Clark { 77312d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_WRAP_T__SHIFT) & A6XX_TEX_SAMP_0_WRAP_T__MASK; 77322d756322SRob Clark } 77332d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 77342d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_R__SHIFT 11 77352d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val) 77362d756322SRob Clark { 77372d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_WRAP_R__SHIFT) & A6XX_TEX_SAMP_0_WRAP_R__MASK; 77382d756322SRob Clark } 77392d756322SRob Clark #define A6XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 77402d756322SRob Clark #define A6XX_TEX_SAMP_0_ANISO__SHIFT 14 77412d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val) 77422d756322SRob Clark { 77432d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_ANISO__SHIFT) & A6XX_TEX_SAMP_0_ANISO__MASK; 77442d756322SRob Clark } 77452d756322SRob Clark #define A6XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000 77462d756322SRob Clark #define A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19 77472d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val) 77482d756322SRob Clark { 77492d756322SRob Clark return ((((int32_t)(val * 256.0))) << A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A6XX_TEX_SAMP_0_LOD_BIAS__MASK; 77502d756322SRob Clark } 77512d756322SRob Clark 77522d756322SRob Clark #define REG_A6XX_TEX_SAMP_1 0x00000001 775357cfe41cSRob Clark #define A6XX_TEX_SAMP_1_CLAMPENABLE 0x00000001 77542d756322SRob Clark #define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e 77552d756322SRob Clark #define A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 77562d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) 77572d756322SRob Clark { 77582d756322SRob Clark return ((val) << A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK; 77592d756322SRob Clark } 77602d756322SRob Clark #define A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010 77612d756322SRob Clark #define A6XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 77622d756322SRob Clark #define A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 77632d756322SRob Clark #define A6XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 77642d756322SRob Clark #define A6XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 77652d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_1_MAX_LOD(float val) 77662d756322SRob Clark { 77672d756322SRob Clark return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK; 77682d756322SRob Clark } 77692d756322SRob Clark #define A6XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 77702d756322SRob Clark #define A6XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 77712d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_1_MIN_LOD(float val) 77722d756322SRob Clark { 77732d756322SRob Clark return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK; 77742d756322SRob Clark } 77752d756322SRob Clark 77762d756322SRob Clark #define REG_A6XX_TEX_SAMP_2 0x00000002 7777c28c82e9SRob Clark #define A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK 0x00000003 7778c28c82e9SRob Clark #define A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT 0 7779c28c82e9SRob Clark static inline uint32_t A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode val) 7780c28c82e9SRob Clark { 7781c28c82e9SRob Clark return ((val) << A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT) & A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK; 7782c28c82e9SRob Clark } 7783c28c82e9SRob Clark #define A6XX_TEX_SAMP_2_CHROMA_LINEAR 0x00000020 7784cc4c26d4SRob Clark #define A6XX_TEX_SAMP_2_BCOLOR__MASK 0xffffff80 7785cc4c26d4SRob Clark #define A6XX_TEX_SAMP_2_BCOLOR__SHIFT 7 7786cc4c26d4SRob Clark static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR(uint32_t val) 77872d756322SRob Clark { 7788cc4c26d4SRob Clark return ((val) << A6XX_TEX_SAMP_2_BCOLOR__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR__MASK; 77892d756322SRob Clark } 77902d756322SRob Clark 77912d756322SRob Clark #define REG_A6XX_TEX_SAMP_3 0x00000003 77922d756322SRob Clark 77932d756322SRob Clark #define REG_A6XX_TEX_CONST_0 0x00000000 77942d756322SRob Clark #define A6XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003 77952d756322SRob Clark #define A6XX_TEX_CONST_0_TILE_MODE__SHIFT 0 77962d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val) 77972d756322SRob Clark { 77982d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_TILE_MODE__SHIFT) & A6XX_TEX_CONST_0_TILE_MODE__MASK; 77992d756322SRob Clark } 78002d756322SRob Clark #define A6XX_TEX_CONST_0_SRGB 0x00000004 78012d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 78022d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_X__SHIFT 4 78032d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val) 78042d756322SRob Clark { 78052d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWIZ_X__SHIFT) & A6XX_TEX_CONST_0_SWIZ_X__MASK; 78062d756322SRob Clark } 78072d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 78082d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 78092d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val) 78102d756322SRob Clark { 78112d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Y__MASK; 78122d756322SRob Clark } 78132d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 78142d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 78152d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val) 78162d756322SRob Clark { 78172d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Z__MASK; 78182d756322SRob Clark } 78192d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 78202d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_W__SHIFT 13 78212d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val) 78222d756322SRob Clark { 78232d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWIZ_W__SHIFT) & A6XX_TEX_CONST_0_SWIZ_W__MASK; 78242d756322SRob Clark } 78252d756322SRob Clark #define A6XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 78262d756322SRob Clark #define A6XX_TEX_CONST_0_MIPLVLS__SHIFT 16 78272d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val) 78282d756322SRob Clark { 78292d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK; 78302d756322SRob Clark } 7831c28c82e9SRob Clark #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X 0x00010000 7832c28c82e9SRob Clark #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y 0x00040000 7833ccdf7e28SRob Clark #define A6XX_TEX_CONST_0_SAMPLES__MASK 0x00300000 7834ccdf7e28SRob Clark #define A6XX_TEX_CONST_0_SAMPLES__SHIFT 20 7835ccdf7e28SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val) 7836ccdf7e28SRob Clark { 7837ccdf7e28SRob Clark return ((val) << A6XX_TEX_CONST_0_SAMPLES__SHIFT) & A6XX_TEX_CONST_0_SAMPLES__MASK; 7838ccdf7e28SRob Clark } 78392d756322SRob Clark #define A6XX_TEX_CONST_0_FMT__MASK 0x3fc00000 78402d756322SRob Clark #define A6XX_TEX_CONST_0_FMT__SHIFT 22 7841c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_format val) 78422d756322SRob Clark { 78432d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK; 78442d756322SRob Clark } 78452d756322SRob Clark #define A6XX_TEX_CONST_0_SWAP__MASK 0xc0000000 78462d756322SRob Clark #define A6XX_TEX_CONST_0_SWAP__SHIFT 30 78472d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val) 78482d756322SRob Clark { 78492d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWAP__SHIFT) & A6XX_TEX_CONST_0_SWAP__MASK; 78502d756322SRob Clark } 78512d756322SRob Clark 78522d756322SRob Clark #define REG_A6XX_TEX_CONST_1 0x00000001 78532d756322SRob Clark #define A6XX_TEX_CONST_1_WIDTH__MASK 0x00007fff 78542d756322SRob Clark #define A6XX_TEX_CONST_1_WIDTH__SHIFT 0 78552d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_1_WIDTH(uint32_t val) 78562d756322SRob Clark { 78572d756322SRob Clark return ((val) << A6XX_TEX_CONST_1_WIDTH__SHIFT) & A6XX_TEX_CONST_1_WIDTH__MASK; 78582d756322SRob Clark } 78592d756322SRob Clark #define A6XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000 78602d756322SRob Clark #define A6XX_TEX_CONST_1_HEIGHT__SHIFT 15 78612d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val) 78622d756322SRob Clark { 78632d756322SRob Clark return ((val) << A6XX_TEX_CONST_1_HEIGHT__SHIFT) & A6XX_TEX_CONST_1_HEIGHT__MASK; 78642d756322SRob Clark } 78652d756322SRob Clark 78662d756322SRob Clark #define REG_A6XX_TEX_CONST_2 0x00000002 7867*f73343faSRob Clark #define A6XX_TEX_CONST_2_STRUCTSIZETEXELS__MASK 0x0000fff0 7868*f73343faSRob Clark #define A6XX_TEX_CONST_2_STRUCTSIZETEXELS__SHIFT 4 7869*f73343faSRob Clark static inline uint32_t A6XX_TEX_CONST_2_STRUCTSIZETEXELS(uint32_t val) 7870*f73343faSRob Clark { 7871*f73343faSRob Clark return ((val) << A6XX_TEX_CONST_2_STRUCTSIZETEXELS__SHIFT) & A6XX_TEX_CONST_2_STRUCTSIZETEXELS__MASK; 7872*f73343faSRob Clark } 7873*f73343faSRob Clark #define A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK 0x003f0000 7874*f73343faSRob Clark #define A6XX_TEX_CONST_2_STARTOFFSETTEXELS__SHIFT 16 7875*f73343faSRob Clark static inline uint32_t A6XX_TEX_CONST_2_STARTOFFSETTEXELS(uint32_t val) 7876*f73343faSRob Clark { 7877*f73343faSRob Clark return ((val) << A6XX_TEX_CONST_2_STARTOFFSETTEXELS__SHIFT) & A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK; 7878*f73343faSRob Clark } 7879c28c82e9SRob Clark #define A6XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f 7880c28c82e9SRob Clark #define A6XX_TEX_CONST_2_PITCHALIGN__SHIFT 0 7881c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_2_PITCHALIGN(uint32_t val) 78822d756322SRob Clark { 7883c28c82e9SRob Clark return ((val) << A6XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A6XX_TEX_CONST_2_PITCHALIGN__MASK; 78842d756322SRob Clark } 78852d756322SRob Clark #define A6XX_TEX_CONST_2_PITCH__MASK 0x1fffff80 78862d756322SRob Clark #define A6XX_TEX_CONST_2_PITCH__SHIFT 7 78872d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_2_PITCH(uint32_t val) 78882d756322SRob Clark { 78892d756322SRob Clark return ((val) << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK; 78902d756322SRob Clark } 789157cfe41cSRob Clark #define A6XX_TEX_CONST_2_TYPE__MASK 0xe0000000 78922d756322SRob Clark #define A6XX_TEX_CONST_2_TYPE__SHIFT 29 78932d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val) 78942d756322SRob Clark { 78952d756322SRob Clark return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK; 78962d756322SRob Clark } 78972d756322SRob Clark 78982d756322SRob Clark #define REG_A6XX_TEX_CONST_3 0x00000003 78992d756322SRob Clark #define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff 79002d756322SRob Clark #define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0 79012d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) 79022d756322SRob Clark { 79032d756322SRob Clark return ((val >> 12) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK; 79042d756322SRob Clark } 7905c28c82e9SRob Clark #define A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000 7906c28c82e9SRob Clark #define A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23 7907c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val) 7908c28c82e9SRob Clark { 7909c28c82e9SRob Clark return ((val >> 12) << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK; 7910c28c82e9SRob Clark } 7911c28c82e9SRob Clark #define A6XX_TEX_CONST_3_TILE_ALL 0x08000000 79122d756322SRob Clark #define A6XX_TEX_CONST_3_FLAG 0x10000000 79132d756322SRob Clark 79142d756322SRob Clark #define REG_A6XX_TEX_CONST_4 0x00000004 79152d756322SRob Clark #define A6XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0 79162d756322SRob Clark #define A6XX_TEX_CONST_4_BASE_LO__SHIFT 5 79172d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val) 79182d756322SRob Clark { 79192d756322SRob Clark return ((val >> 5) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK; 79202d756322SRob Clark } 79212d756322SRob Clark 79222d756322SRob Clark #define REG_A6XX_TEX_CONST_5 0x00000005 79232d756322SRob Clark #define A6XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff 79242d756322SRob Clark #define A6XX_TEX_CONST_5_BASE_HI__SHIFT 0 79252d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_5_BASE_HI(uint32_t val) 79262d756322SRob Clark { 79272d756322SRob Clark return ((val) << A6XX_TEX_CONST_5_BASE_HI__SHIFT) & A6XX_TEX_CONST_5_BASE_HI__MASK; 79282d756322SRob Clark } 79292d756322SRob Clark #define A6XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000 79302d756322SRob Clark #define A6XX_TEX_CONST_5_DEPTH__SHIFT 17 79312d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_5_DEPTH(uint32_t val) 79322d756322SRob Clark { 79332d756322SRob Clark return ((val) << A6XX_TEX_CONST_5_DEPTH__SHIFT) & A6XX_TEX_CONST_5_DEPTH__MASK; 79342d756322SRob Clark } 79352d756322SRob Clark 79362d756322SRob Clark #define REG_A6XX_TEX_CONST_6 0x00000006 7937*f73343faSRob Clark #define A6XX_TEX_CONST_6_MIN_LOD_CLAMP__MASK 0x00000fff 7938*f73343faSRob Clark #define A6XX_TEX_CONST_6_MIN_LOD_CLAMP__SHIFT 0 7939*f73343faSRob Clark static inline uint32_t A6XX_TEX_CONST_6_MIN_LOD_CLAMP(float val) 7940*f73343faSRob Clark { 7941*f73343faSRob Clark return ((((uint32_t)(val * 256.0))) << A6XX_TEX_CONST_6_MIN_LOD_CLAMP__SHIFT) & A6XX_TEX_CONST_6_MIN_LOD_CLAMP__MASK; 7942*f73343faSRob Clark } 7943c28c82e9SRob Clark #define A6XX_TEX_CONST_6_PLANE_PITCH__MASK 0xffffff00 7944c28c82e9SRob Clark #define A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT 8 7945c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_6_PLANE_PITCH(uint32_t val) 7946c28c82e9SRob Clark { 7947c28c82e9SRob Clark return ((val) << A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT) & A6XX_TEX_CONST_6_PLANE_PITCH__MASK; 7948c28c82e9SRob Clark } 79492d756322SRob Clark 79502d756322SRob Clark #define REG_A6XX_TEX_CONST_7 0x00000007 79512d756322SRob Clark #define A6XX_TEX_CONST_7_FLAG_LO__MASK 0xffffffe0 79522d756322SRob Clark #define A6XX_TEX_CONST_7_FLAG_LO__SHIFT 5 79532d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val) 79542d756322SRob Clark { 79552d756322SRob Clark return ((val >> 5) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK; 79562d756322SRob Clark } 79572d756322SRob Clark 79582d756322SRob Clark #define REG_A6XX_TEX_CONST_8 0x00000008 7959a69c5ed2SRob Clark #define A6XX_TEX_CONST_8_FLAG_HI__MASK 0x0001ffff 7960a69c5ed2SRob Clark #define A6XX_TEX_CONST_8_FLAG_HI__SHIFT 0 7961a69c5ed2SRob Clark static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val) 79622d756322SRob Clark { 7963a69c5ed2SRob Clark return ((val) << A6XX_TEX_CONST_8_FLAG_HI__SHIFT) & A6XX_TEX_CONST_8_FLAG_HI__MASK; 79642d756322SRob Clark } 79652d756322SRob Clark 79662d756322SRob Clark #define REG_A6XX_TEX_CONST_9 0x00000009 7967c28c82e9SRob Clark #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff 7968c28c82e9SRob Clark #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0 7969c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) 7970c28c82e9SRob Clark { 7971c28c82e9SRob Clark return ((val >> 4) << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK; 7972c28c82e9SRob Clark } 79732d756322SRob Clark 79742d756322SRob Clark #define REG_A6XX_TEX_CONST_10 0x0000000a 7975c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK 0x0000007f 7976c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT 0 7977c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val) 7978c28c82e9SRob Clark { 7979c28c82e9SRob Clark return ((val >> 6) << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK; 7980c28c82e9SRob Clark } 7981c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK 0x00000f00 7982c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT 8 7983c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(uint32_t val) 7984c28c82e9SRob Clark { 7985c28c82e9SRob Clark return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK; 7986c28c82e9SRob Clark } 7987c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK 0x0000f000 7988c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT 12 7989c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(uint32_t val) 7990c28c82e9SRob Clark { 7991c28c82e9SRob Clark return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK; 7992c28c82e9SRob Clark } 79932d756322SRob Clark 79942d756322SRob Clark #define REG_A6XX_TEX_CONST_11 0x0000000b 79952d756322SRob Clark 79962d756322SRob Clark #define REG_A6XX_TEX_CONST_12 0x0000000c 79972d756322SRob Clark 79982d756322SRob Clark #define REG_A6XX_TEX_CONST_13 0x0000000d 79992d756322SRob Clark 80002d756322SRob Clark #define REG_A6XX_TEX_CONST_14 0x0000000e 80012d756322SRob Clark 80022d756322SRob Clark #define REG_A6XX_TEX_CONST_15 0x0000000f 80032d756322SRob Clark 8004c28c82e9SRob Clark #define REG_A6XX_UBO_0 0x00000000 8005c28c82e9SRob Clark #define A6XX_UBO_0_BASE_LO__MASK 0xffffffff 8006c28c82e9SRob Clark #define A6XX_UBO_0_BASE_LO__SHIFT 0 8007c28c82e9SRob Clark static inline uint32_t A6XX_UBO_0_BASE_LO(uint32_t val) 8008c28c82e9SRob Clark { 8009c28c82e9SRob Clark return ((val) << A6XX_UBO_0_BASE_LO__SHIFT) & A6XX_UBO_0_BASE_LO__MASK; 8010c28c82e9SRob Clark } 8011c28c82e9SRob Clark 8012c28c82e9SRob Clark #define REG_A6XX_UBO_1 0x00000001 8013c28c82e9SRob Clark #define A6XX_UBO_1_BASE_HI__MASK 0x0001ffff 8014c28c82e9SRob Clark #define A6XX_UBO_1_BASE_HI__SHIFT 0 8015c28c82e9SRob Clark static inline uint32_t A6XX_UBO_1_BASE_HI(uint32_t val) 8016c28c82e9SRob Clark { 8017c28c82e9SRob Clark return ((val) << A6XX_UBO_1_BASE_HI__SHIFT) & A6XX_UBO_1_BASE_HI__MASK; 8018c28c82e9SRob Clark } 8019c28c82e9SRob Clark #define A6XX_UBO_1_SIZE__MASK 0xfffe0000 8020c28c82e9SRob Clark #define A6XX_UBO_1_SIZE__SHIFT 17 8021c28c82e9SRob Clark static inline uint32_t A6XX_UBO_1_SIZE(uint32_t val) 8022c28c82e9SRob Clark { 8023c28c82e9SRob Clark return ((val) << A6XX_UBO_1_SIZE__SHIFT) & A6XX_UBO_1_SIZE__MASK; 8024c28c82e9SRob Clark } 8025c28c82e9SRob Clark 8026a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_ENABLE_PDC 0x00001140 8027a69c5ed2SRob Clark 8028a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_SEQ_START_ADDR 0x00001148 8029a69c5ed2SRob Clark 8030a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CONTROL 0x00001540 8031a69c5ed2SRob Clark 8032a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK 0x00001541 8033a69c5ed2SRob Clark 8034a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK 0x00001542 8035a69c5ed2SRob Clark 8036a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID 0x00001543 8037a69c5ed2SRob Clark 8038a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR 0x00001544 8039a69c5ed2SRob Clark 8040a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA 0x00001545 8041a69c5ed2SRob Clark 8042a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CONTROL 0x00001572 8043a69c5ed2SRob Clark 8044a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK 0x00001573 8045a69c5ed2SRob Clark 8046a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK 0x00001574 8047a69c5ed2SRob Clark 8048a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID 0x00001575 8049a69c5ed2SRob Clark 8050a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR 0x00001576 8051a69c5ed2SRob Clark 8052a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA 0x00001577 8053a69c5ed2SRob Clark 8054a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CONTROL 0x000015a4 8055a69c5ed2SRob Clark 8056a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK 0x000015a5 8057a69c5ed2SRob Clark 8058a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK 0x000015a6 8059a69c5ed2SRob Clark 8060a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID 0x000015a7 8061a69c5ed2SRob Clark 8062a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR 0x000015a8 8063a69c5ed2SRob Clark 8064a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA 0x000015a9 8065a69c5ed2SRob Clark 8066a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CONTROL 0x000015d6 8067a69c5ed2SRob Clark 8068a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK 0x000015d7 8069a69c5ed2SRob Clark 8070a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK 0x000015d8 8071a69c5ed2SRob Clark 8072a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID 0x000015d9 8073a69c5ed2SRob Clark 8074a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR 0x000015da 8075a69c5ed2SRob Clark 8076a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA 0x000015db 8077a69c5ed2SRob Clark 8078a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x00000000 8079a69c5ed2SRob Clark 8080a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A 0x00000000 8081a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK 0x000000ff 8082a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT 0 8083a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val) 8084a69c5ed2SRob Clark { 8085a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK; 8086a69c5ed2SRob Clark } 8087a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK 0x0000ff00 8088a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT 8 8089a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val) 8090a69c5ed2SRob Clark { 8091a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK; 8092a69c5ed2SRob Clark } 8093a69c5ed2SRob Clark 8094a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B 0x00000001 8095a69c5ed2SRob Clark 8096a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C 0x00000002 8097a69c5ed2SRob Clark 8098a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D 0x00000003 8099a69c5ed2SRob Clark 8100a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT 0x00000004 8101a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f 8102a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0 8103a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) 8104a69c5ed2SRob Clark { 8105a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; 8106a69c5ed2SRob Clark } 8107a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000 8108a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12 8109a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) 8110a69c5ed2SRob Clark { 8111a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; 8112a69c5ed2SRob Clark } 8113a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000 8114a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28 8115a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) 8116a69c5ed2SRob Clark { 8117a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; 8118a69c5ed2SRob Clark } 8119a69c5ed2SRob Clark 8120a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM 0x00000005 8121a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000 8122a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24 8123a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) 8124a69c5ed2SRob Clark { 8125a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; 8126a69c5ed2SRob Clark } 8127a69c5ed2SRob Clark 8128a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 0x00000008 8129a69c5ed2SRob Clark 8130a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 0x00000009 8131a69c5ed2SRob Clark 8132a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 0x0000000a 8133a69c5ed2SRob Clark 8134a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 0x0000000b 8135a69c5ed2SRob Clark 8136a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 0x0000000c 8137a69c5ed2SRob Clark 8138a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 0x0000000d 8139a69c5ed2SRob Clark 8140a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 0x0000000e 8141a69c5ed2SRob Clark 8142a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 0x0000000f 8143a69c5ed2SRob Clark 8144a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000010 8145a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f 8146a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0 8147a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) 8148a69c5ed2SRob Clark { 8149a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; 8150a69c5ed2SRob Clark } 8151a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0 8152a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4 8153a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) 8154a69c5ed2SRob Clark { 8155a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; 8156a69c5ed2SRob Clark } 8157a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00 8158a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8 8159a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) 8160a69c5ed2SRob Clark { 8161a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; 8162a69c5ed2SRob Clark } 8163a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000 8164a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12 8165a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) 8166a69c5ed2SRob Clark { 8167a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; 8168a69c5ed2SRob Clark } 8169a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000 8170a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16 8171a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) 8172a69c5ed2SRob Clark { 8173a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; 8174a69c5ed2SRob Clark } 8175a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000 8176a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20 8177a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) 8178a69c5ed2SRob Clark { 8179a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; 8180a69c5ed2SRob Clark } 8181a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000 8182a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24 8183a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) 8184a69c5ed2SRob Clark { 8185a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; 8186a69c5ed2SRob Clark } 8187a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000 8188a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28 8189a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) 8190a69c5ed2SRob Clark { 8191a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; 8192a69c5ed2SRob Clark } 8193a69c5ed2SRob Clark 8194a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000011 8195a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f 8196a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0 8197a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) 8198a69c5ed2SRob Clark { 8199a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; 8200a69c5ed2SRob Clark } 8201a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0 8202a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4 8203a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) 8204a69c5ed2SRob Clark { 8205a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; 8206a69c5ed2SRob Clark } 8207a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00 8208a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8 8209a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) 8210a69c5ed2SRob Clark { 8211a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; 8212a69c5ed2SRob Clark } 8213a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000 8214a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12 8215a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) 8216a69c5ed2SRob Clark { 8217a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; 8218a69c5ed2SRob Clark } 8219a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000 8220a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16 8221a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) 8222a69c5ed2SRob Clark { 8223a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; 8224a69c5ed2SRob Clark } 8225a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000 8226a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20 8227a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) 8228a69c5ed2SRob Clark { 8229a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; 8230a69c5ed2SRob Clark } 8231a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000 8232a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24 8233a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) 8234a69c5ed2SRob Clark { 8235a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; 8236a69c5ed2SRob Clark } 8237a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000 8238a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28 8239a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) 8240a69c5ed2SRob Clark { 8241a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; 8242a69c5ed2SRob Clark } 8243a69c5ed2SRob Clark 8244a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000002f 8245a69c5ed2SRob Clark 8246a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000030 8247a69c5ed2SRob Clark 8248ccdf7e28SRob Clark #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 0x00000001 8249ccdf7e28SRob Clark 8250ccdf7e28SRob Clark #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 0x00000002 8251ccdf7e28SRob Clark 82522d756322SRob Clark 82532d756322SRob Clark #endif /* A6XX_XML */ 8254