12d756322SRob Clark #ifndef A6XX_XML 22d756322SRob Clark #define A6XX_XML 32d756322SRob Clark 42d756322SRob Clark /* Autogenerated file, DO NOT EDIT manually! 52d756322SRob Clark 62d756322SRob Clark This file was generated by the rules-ng-ng headergen tool in this git repository: 72d756322SRob Clark http://github.com/freedreno/envytools/ 82d756322SRob Clark git clone https://github.com/freedreno/envytools.git 92d756322SRob Clark 102d756322SRob Clark The rules-ng-ng source files this header was generated from are: 112d756322SRob Clark - /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13) 122d756322SRob Clark - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13) 13ccdf7e28SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03) 14ccdf7e28SRob Clark - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14201 bytes, from 2018-12-02 17:29:54) 15ccdf7e28SRob Clark - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-02 17:29:54) 162d756322SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13) 172d756322SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13) 18ccdf7e28SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54) 19e812744cSSharat Masetty - /home/smasetty/playarea/envytools/rnndb/adreno/a6xx.xml ( 161969 bytes, from 2019-11-29 07:18:16) 20a69c5ed2SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07) 212d756322SRob Clark - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13) 222d756322SRob Clark 23e812744cSSharat Masetty Copyright (C) 2013-2019 by the following authors: 242d756322SRob Clark - Rob Clark <robdclark@gmail.com> (robclark) 252d756322SRob Clark - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 262d756322SRob Clark 272d756322SRob Clark Permission is hereby granted, free of charge, to any person obtaining 282d756322SRob Clark a copy of this software and associated documentation files (the 292d756322SRob Clark "Software"), to deal in the Software without restriction, including 302d756322SRob Clark without limitation the rights to use, copy, modify, merge, publish, 312d756322SRob Clark distribute, sublicense, and/or sell copies of the Software, and to 322d756322SRob Clark permit persons to whom the Software is furnished to do so, subject to 332d756322SRob Clark the following conditions: 342d756322SRob Clark 352d756322SRob Clark The above copyright notice and this permission notice (including the 362d756322SRob Clark next paragraph) shall be included in all copies or substantial 372d756322SRob Clark portions of the Software. 382d756322SRob Clark 392d756322SRob Clark THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 402d756322SRob Clark EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 412d756322SRob Clark MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 422d756322SRob Clark IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 432d756322SRob Clark LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 442d756322SRob Clark OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 452d756322SRob Clark WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 462d756322SRob Clark */ 472d756322SRob Clark 482d756322SRob Clark 492d756322SRob Clark enum a6xx_color_fmt { 502d756322SRob Clark RB6_A8_UNORM = 2, 512d756322SRob Clark RB6_R8_UNORM = 3, 522d756322SRob Clark RB6_R8_SNORM = 4, 532d756322SRob Clark RB6_R8_UINT = 5, 542d756322SRob Clark RB6_R8_SINT = 6, 552d756322SRob Clark RB6_R4G4B4A4_UNORM = 8, 562d756322SRob Clark RB6_R5G5B5A1_UNORM = 10, 572d756322SRob Clark RB6_R5G6B5_UNORM = 14, 582d756322SRob Clark RB6_R8G8_UNORM = 15, 592d756322SRob Clark RB6_R8G8_SNORM = 16, 602d756322SRob Clark RB6_R8G8_UINT = 17, 612d756322SRob Clark RB6_R8G8_SINT = 18, 622d756322SRob Clark RB6_R16_UNORM = 21, 632d756322SRob Clark RB6_R16_SNORM = 22, 642d756322SRob Clark RB6_R16_FLOAT = 23, 652d756322SRob Clark RB6_R16_UINT = 24, 662d756322SRob Clark RB6_R16_SINT = 25, 672d756322SRob Clark RB6_R8G8B8A8_UNORM = 48, 682d756322SRob Clark RB6_R8G8B8_UNORM = 49, 692d756322SRob Clark RB6_R8G8B8A8_SNORM = 50, 702d756322SRob Clark RB6_R8G8B8A8_UINT = 51, 712d756322SRob Clark RB6_R8G8B8A8_SINT = 52, 722d756322SRob Clark RB6_R10G10B10A2_UNORM = 55, 732d756322SRob Clark RB6_R10G10B10A2_UINT = 58, 742d756322SRob Clark RB6_R11G11B10_FLOAT = 66, 752d756322SRob Clark RB6_R16G16_UNORM = 67, 762d756322SRob Clark RB6_R16G16_SNORM = 68, 772d756322SRob Clark RB6_R16G16_FLOAT = 69, 782d756322SRob Clark RB6_R16G16_UINT = 70, 792d756322SRob Clark RB6_R16G16_SINT = 71, 802d756322SRob Clark RB6_R32_FLOAT = 74, 812d756322SRob Clark RB6_R32_UINT = 75, 822d756322SRob Clark RB6_R32_SINT = 76, 832d756322SRob Clark RB6_R16G16B16A16_UNORM = 96, 842d756322SRob Clark RB6_R16G16B16A16_SNORM = 97, 852d756322SRob Clark RB6_R16G16B16A16_FLOAT = 98, 862d756322SRob Clark RB6_R16G16B16A16_UINT = 99, 872d756322SRob Clark RB6_R16G16B16A16_SINT = 100, 882d756322SRob Clark RB6_R32G32_FLOAT = 103, 892d756322SRob Clark RB6_R32G32_UINT = 104, 902d756322SRob Clark RB6_R32G32_SINT = 105, 912d756322SRob Clark RB6_R32G32B32A32_FLOAT = 130, 922d756322SRob Clark RB6_R32G32B32A32_UINT = 131, 932d756322SRob Clark RB6_R32G32B32A32_SINT = 132, 942d756322SRob Clark RB6_X8Z24_UNORM = 160, 952d756322SRob Clark }; 962d756322SRob Clark 972d756322SRob Clark enum a6xx_tile_mode { 982d756322SRob Clark TILE6_LINEAR = 0, 992d756322SRob Clark TILE6_2 = 2, 1002d756322SRob Clark TILE6_3 = 3, 1012d756322SRob Clark }; 1022d756322SRob Clark 1032d756322SRob Clark enum a6xx_vtx_fmt { 1042d756322SRob Clark VFMT6_8_UNORM = 3, 1052d756322SRob Clark VFMT6_8_SNORM = 4, 1062d756322SRob Clark VFMT6_8_UINT = 5, 1072d756322SRob Clark VFMT6_8_SINT = 6, 1082d756322SRob Clark VFMT6_8_8_UNORM = 15, 1092d756322SRob Clark VFMT6_8_8_SNORM = 16, 1102d756322SRob Clark VFMT6_8_8_UINT = 17, 1112d756322SRob Clark VFMT6_8_8_SINT = 18, 1122d756322SRob Clark VFMT6_16_UNORM = 21, 1132d756322SRob Clark VFMT6_16_SNORM = 22, 1142d756322SRob Clark VFMT6_16_FLOAT = 23, 1152d756322SRob Clark VFMT6_16_UINT = 24, 1162d756322SRob Clark VFMT6_16_SINT = 25, 1172d756322SRob Clark VFMT6_8_8_8_UNORM = 33, 1182d756322SRob Clark VFMT6_8_8_8_SNORM = 34, 1192d756322SRob Clark VFMT6_8_8_8_UINT = 35, 1202d756322SRob Clark VFMT6_8_8_8_SINT = 36, 1212d756322SRob Clark VFMT6_8_8_8_8_UNORM = 48, 1222d756322SRob Clark VFMT6_8_8_8_8_SNORM = 50, 1232d756322SRob Clark VFMT6_8_8_8_8_UINT = 51, 1242d756322SRob Clark VFMT6_8_8_8_8_SINT = 52, 1252d756322SRob Clark VFMT6_10_10_10_2_UNORM = 54, 1262d756322SRob Clark VFMT6_10_10_10_2_SNORM = 57, 1272d756322SRob Clark VFMT6_10_10_10_2_UINT = 58, 1282d756322SRob Clark VFMT6_10_10_10_2_SINT = 59, 1292d756322SRob Clark VFMT6_11_11_10_FLOAT = 66, 1302d756322SRob Clark VFMT6_16_16_UNORM = 67, 1312d756322SRob Clark VFMT6_16_16_SNORM = 68, 1322d756322SRob Clark VFMT6_16_16_FLOAT = 69, 1332d756322SRob Clark VFMT6_16_16_UINT = 70, 1342d756322SRob Clark VFMT6_16_16_SINT = 71, 1352d756322SRob Clark VFMT6_32_UNORM = 72, 1362d756322SRob Clark VFMT6_32_SNORM = 73, 1372d756322SRob Clark VFMT6_32_FLOAT = 74, 1382d756322SRob Clark VFMT6_32_UINT = 75, 1392d756322SRob Clark VFMT6_32_SINT = 76, 1402d756322SRob Clark VFMT6_32_FIXED = 77, 1412d756322SRob Clark VFMT6_16_16_16_UNORM = 88, 1422d756322SRob Clark VFMT6_16_16_16_SNORM = 89, 1432d756322SRob Clark VFMT6_16_16_16_FLOAT = 90, 1442d756322SRob Clark VFMT6_16_16_16_UINT = 91, 1452d756322SRob Clark VFMT6_16_16_16_SINT = 92, 1462d756322SRob Clark VFMT6_16_16_16_16_UNORM = 96, 1472d756322SRob Clark VFMT6_16_16_16_16_SNORM = 97, 1482d756322SRob Clark VFMT6_16_16_16_16_FLOAT = 98, 1492d756322SRob Clark VFMT6_16_16_16_16_UINT = 99, 1502d756322SRob Clark VFMT6_16_16_16_16_SINT = 100, 1512d756322SRob Clark VFMT6_32_32_UNORM = 101, 1522d756322SRob Clark VFMT6_32_32_SNORM = 102, 1532d756322SRob Clark VFMT6_32_32_FLOAT = 103, 1542d756322SRob Clark VFMT6_32_32_UINT = 104, 1552d756322SRob Clark VFMT6_32_32_SINT = 105, 1562d756322SRob Clark VFMT6_32_32_FIXED = 106, 1572d756322SRob Clark VFMT6_32_32_32_UNORM = 112, 1582d756322SRob Clark VFMT6_32_32_32_SNORM = 113, 1592d756322SRob Clark VFMT6_32_32_32_UINT = 114, 1602d756322SRob Clark VFMT6_32_32_32_SINT = 115, 1612d756322SRob Clark VFMT6_32_32_32_FLOAT = 116, 1622d756322SRob Clark VFMT6_32_32_32_FIXED = 117, 1632d756322SRob Clark VFMT6_32_32_32_32_UNORM = 128, 1642d756322SRob Clark VFMT6_32_32_32_32_SNORM = 129, 1652d756322SRob Clark VFMT6_32_32_32_32_FLOAT = 130, 1662d756322SRob Clark VFMT6_32_32_32_32_UINT = 131, 1672d756322SRob Clark VFMT6_32_32_32_32_SINT = 132, 1682d756322SRob Clark VFMT6_32_32_32_32_FIXED = 133, 1692d756322SRob Clark }; 1702d756322SRob Clark 1712d756322SRob Clark enum a6xx_tex_fmt { 1722d756322SRob Clark TFMT6_A8_UNORM = 2, 1732d756322SRob Clark TFMT6_8_UNORM = 3, 1742d756322SRob Clark TFMT6_8_SNORM = 4, 1752d756322SRob Clark TFMT6_8_UINT = 5, 1762d756322SRob Clark TFMT6_8_SINT = 6, 1772d756322SRob Clark TFMT6_4_4_4_4_UNORM = 8, 1782d756322SRob Clark TFMT6_5_5_5_1_UNORM = 10, 1792d756322SRob Clark TFMT6_5_6_5_UNORM = 14, 1802d756322SRob Clark TFMT6_8_8_UNORM = 15, 1812d756322SRob Clark TFMT6_8_8_SNORM = 16, 1822d756322SRob Clark TFMT6_8_8_UINT = 17, 1832d756322SRob Clark TFMT6_8_8_SINT = 18, 1842d756322SRob Clark TFMT6_L8_A8_UNORM = 19, 1852d756322SRob Clark TFMT6_16_UNORM = 21, 1862d756322SRob Clark TFMT6_16_SNORM = 22, 1872d756322SRob Clark TFMT6_16_FLOAT = 23, 1882d756322SRob Clark TFMT6_16_UINT = 24, 1892d756322SRob Clark TFMT6_16_SINT = 25, 1902d756322SRob Clark TFMT6_8_8_8_8_UNORM = 48, 1912d756322SRob Clark TFMT6_8_8_8_UNORM = 49, 1922d756322SRob Clark TFMT6_8_8_8_8_SNORM = 50, 1932d756322SRob Clark TFMT6_8_8_8_8_UINT = 51, 1942d756322SRob Clark TFMT6_8_8_8_8_SINT = 52, 1952d756322SRob Clark TFMT6_9_9_9_E5_FLOAT = 53, 1962d756322SRob Clark TFMT6_10_10_10_2_UNORM = 54, 1972d756322SRob Clark TFMT6_10_10_10_2_UINT = 58, 1982d756322SRob Clark TFMT6_11_11_10_FLOAT = 66, 1992d756322SRob Clark TFMT6_16_16_UNORM = 67, 2002d756322SRob Clark TFMT6_16_16_SNORM = 68, 2012d756322SRob Clark TFMT6_16_16_FLOAT = 69, 2022d756322SRob Clark TFMT6_16_16_UINT = 70, 2032d756322SRob Clark TFMT6_16_16_SINT = 71, 2042d756322SRob Clark TFMT6_32_FLOAT = 74, 2052d756322SRob Clark TFMT6_32_UINT = 75, 2062d756322SRob Clark TFMT6_32_SINT = 76, 2072d756322SRob Clark TFMT6_16_16_16_16_UNORM = 96, 2082d756322SRob Clark TFMT6_16_16_16_16_SNORM = 97, 2092d756322SRob Clark TFMT6_16_16_16_16_FLOAT = 98, 2102d756322SRob Clark TFMT6_16_16_16_16_UINT = 99, 2112d756322SRob Clark TFMT6_16_16_16_16_SINT = 100, 2122d756322SRob Clark TFMT6_32_32_FLOAT = 103, 2132d756322SRob Clark TFMT6_32_32_UINT = 104, 2142d756322SRob Clark TFMT6_32_32_SINT = 105, 2152d756322SRob Clark TFMT6_32_32_32_UINT = 114, 2162d756322SRob Clark TFMT6_32_32_32_SINT = 115, 2172d756322SRob Clark TFMT6_32_32_32_FLOAT = 116, 2182d756322SRob Clark TFMT6_32_32_32_32_FLOAT = 130, 2192d756322SRob Clark TFMT6_32_32_32_32_UINT = 131, 2202d756322SRob Clark TFMT6_32_32_32_32_SINT = 132, 2212d756322SRob Clark TFMT6_X8Z24_UNORM = 160, 2222d756322SRob Clark TFMT6_ETC2_RG11_UNORM = 171, 2232d756322SRob Clark TFMT6_ETC2_RG11_SNORM = 172, 2242d756322SRob Clark TFMT6_ETC2_R11_UNORM = 173, 2252d756322SRob Clark TFMT6_ETC2_R11_SNORM = 174, 2262d756322SRob Clark TFMT6_ETC1 = 175, 2272d756322SRob Clark TFMT6_ETC2_RGB8 = 176, 2282d756322SRob Clark TFMT6_ETC2_RGBA8 = 177, 2292d756322SRob Clark TFMT6_ETC2_RGB8A1 = 178, 2302d756322SRob Clark TFMT6_DXT1 = 179, 2312d756322SRob Clark TFMT6_DXT3 = 180, 2322d756322SRob Clark TFMT6_DXT5 = 181, 2332d756322SRob Clark TFMT6_RGTC1_UNORM = 183, 2342d756322SRob Clark TFMT6_RGTC1_SNORM = 184, 2352d756322SRob Clark TFMT6_RGTC2_UNORM = 187, 2362d756322SRob Clark TFMT6_RGTC2_SNORM = 188, 2372d756322SRob Clark TFMT6_BPTC_UFLOAT = 190, 2382d756322SRob Clark TFMT6_BPTC_FLOAT = 191, 2392d756322SRob Clark TFMT6_BPTC = 192, 2402d756322SRob Clark TFMT6_ASTC_4x4 = 193, 2412d756322SRob Clark TFMT6_ASTC_5x4 = 194, 2422d756322SRob Clark TFMT6_ASTC_5x5 = 195, 2432d756322SRob Clark TFMT6_ASTC_6x5 = 196, 2442d756322SRob Clark TFMT6_ASTC_6x6 = 197, 2452d756322SRob Clark TFMT6_ASTC_8x5 = 198, 2462d756322SRob Clark TFMT6_ASTC_8x6 = 199, 2472d756322SRob Clark TFMT6_ASTC_8x8 = 200, 2482d756322SRob Clark TFMT6_ASTC_10x5 = 201, 2492d756322SRob Clark TFMT6_ASTC_10x6 = 202, 2502d756322SRob Clark TFMT6_ASTC_10x8 = 203, 2512d756322SRob Clark TFMT6_ASTC_10x10 = 204, 2522d756322SRob Clark TFMT6_ASTC_12x10 = 205, 2532d756322SRob Clark TFMT6_ASTC_12x12 = 206, 2542d756322SRob Clark }; 2552d756322SRob Clark 2562d756322SRob Clark enum a6xx_tex_fetchsize { 2572d756322SRob Clark TFETCH6_1_BYTE = 0, 2582d756322SRob Clark TFETCH6_2_BYTE = 1, 2592d756322SRob Clark TFETCH6_4_BYTE = 2, 2602d756322SRob Clark TFETCH6_8_BYTE = 3, 2612d756322SRob Clark TFETCH6_16_BYTE = 4, 2622d756322SRob Clark }; 2632d756322SRob Clark 2642d756322SRob Clark enum a6xx_depth_format { 2652d756322SRob Clark DEPTH6_NONE = 0, 2662d756322SRob Clark DEPTH6_16 = 1, 2672d756322SRob Clark DEPTH6_24_8 = 2, 2682d756322SRob Clark DEPTH6_32 = 4, 2692d756322SRob Clark }; 2702d756322SRob Clark 271a69c5ed2SRob Clark enum a6xx_shader_id { 272a69c5ed2SRob Clark A6XX_TP0_TMO_DATA = 9, 273a69c5ed2SRob Clark A6XX_TP0_SMO_DATA = 10, 274a69c5ed2SRob Clark A6XX_TP0_MIPMAP_BASE_DATA = 11, 275a69c5ed2SRob Clark A6XX_TP1_TMO_DATA = 25, 276a69c5ed2SRob Clark A6XX_TP1_SMO_DATA = 26, 277a69c5ed2SRob Clark A6XX_TP1_MIPMAP_BASE_DATA = 27, 278a69c5ed2SRob Clark A6XX_SP_INST_DATA = 41, 279a69c5ed2SRob Clark A6XX_SP_LB_0_DATA = 42, 280a69c5ed2SRob Clark A6XX_SP_LB_1_DATA = 43, 281a69c5ed2SRob Clark A6XX_SP_LB_2_DATA = 44, 282a69c5ed2SRob Clark A6XX_SP_LB_3_DATA = 45, 283a69c5ed2SRob Clark A6XX_SP_LB_4_DATA = 46, 284a69c5ed2SRob Clark A6XX_SP_LB_5_DATA = 47, 285a69c5ed2SRob Clark A6XX_SP_CB_BINDLESS_DATA = 48, 286a69c5ed2SRob Clark A6XX_SP_CB_LEGACY_DATA = 49, 287a69c5ed2SRob Clark A6XX_SP_UAV_DATA = 50, 288a69c5ed2SRob Clark A6XX_SP_INST_TAG = 51, 289a69c5ed2SRob Clark A6XX_SP_CB_BINDLESS_TAG = 52, 290a69c5ed2SRob Clark A6XX_SP_TMO_UMO_TAG = 53, 291a69c5ed2SRob Clark A6XX_SP_SMO_TAG = 54, 292a69c5ed2SRob Clark A6XX_SP_STATE_DATA = 55, 293a69c5ed2SRob Clark A6XX_HLSQ_CHUNK_CVS_RAM = 73, 294a69c5ed2SRob Clark A6XX_HLSQ_CHUNK_CPS_RAM = 74, 295a69c5ed2SRob Clark A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75, 296a69c5ed2SRob Clark A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76, 297a69c5ed2SRob Clark A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77, 298a69c5ed2SRob Clark A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78, 299a69c5ed2SRob Clark A6XX_HLSQ_CVS_MISC_RAM = 80, 300a69c5ed2SRob Clark A6XX_HLSQ_CPS_MISC_RAM = 81, 301a69c5ed2SRob Clark A6XX_HLSQ_INST_RAM = 82, 302a69c5ed2SRob Clark A6XX_HLSQ_GFX_CVS_CONST_RAM = 83, 303a69c5ed2SRob Clark A6XX_HLSQ_GFX_CPS_CONST_RAM = 84, 304a69c5ed2SRob Clark A6XX_HLSQ_CVS_MISC_RAM_TAG = 85, 305a69c5ed2SRob Clark A6XX_HLSQ_CPS_MISC_RAM_TAG = 86, 306a69c5ed2SRob Clark A6XX_HLSQ_INST_RAM_TAG = 87, 307a69c5ed2SRob Clark A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88, 308a69c5ed2SRob Clark A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89, 309a69c5ed2SRob Clark A6XX_HLSQ_PWR_REST_RAM = 90, 310a69c5ed2SRob Clark A6XX_HLSQ_PWR_REST_TAG = 91, 311a69c5ed2SRob Clark A6XX_HLSQ_DATAPATH_META = 96, 312a69c5ed2SRob Clark A6XX_HLSQ_FRONTEND_META = 97, 313a69c5ed2SRob Clark A6XX_HLSQ_INDIRECT_META = 98, 314a69c5ed2SRob Clark A6XX_HLSQ_BACKEND_META = 99, 315a69c5ed2SRob Clark }; 316a69c5ed2SRob Clark 317a69c5ed2SRob Clark enum a6xx_debugbus_id { 318a69c5ed2SRob Clark A6XX_DBGBUS_CP = 1, 319a69c5ed2SRob Clark A6XX_DBGBUS_RBBM = 2, 320a69c5ed2SRob Clark A6XX_DBGBUS_VBIF = 3, 321a69c5ed2SRob Clark A6XX_DBGBUS_HLSQ = 4, 322a69c5ed2SRob Clark A6XX_DBGBUS_UCHE = 5, 323a69c5ed2SRob Clark A6XX_DBGBUS_DPM = 6, 324a69c5ed2SRob Clark A6XX_DBGBUS_TESS = 7, 325a69c5ed2SRob Clark A6XX_DBGBUS_PC = 8, 326a69c5ed2SRob Clark A6XX_DBGBUS_VFDP = 9, 327a69c5ed2SRob Clark A6XX_DBGBUS_VPC = 10, 328a69c5ed2SRob Clark A6XX_DBGBUS_TSE = 11, 329a69c5ed2SRob Clark A6XX_DBGBUS_RAS = 12, 330a69c5ed2SRob Clark A6XX_DBGBUS_VSC = 13, 331a69c5ed2SRob Clark A6XX_DBGBUS_COM = 14, 332a69c5ed2SRob Clark A6XX_DBGBUS_LRZ = 16, 333a69c5ed2SRob Clark A6XX_DBGBUS_A2D = 17, 334a69c5ed2SRob Clark A6XX_DBGBUS_CCUFCHE = 18, 335a69c5ed2SRob Clark A6XX_DBGBUS_GMU_CX = 19, 336a69c5ed2SRob Clark A6XX_DBGBUS_RBP = 20, 337a69c5ed2SRob Clark A6XX_DBGBUS_DCS = 21, 338a69c5ed2SRob Clark A6XX_DBGBUS_DBGC = 22, 339a69c5ed2SRob Clark A6XX_DBGBUS_CX = 23, 340a69c5ed2SRob Clark A6XX_DBGBUS_GMU_GX = 24, 341a69c5ed2SRob Clark A6XX_DBGBUS_TPFCHE = 25, 342a69c5ed2SRob Clark A6XX_DBGBUS_GBIF_GX = 26, 343a69c5ed2SRob Clark A6XX_DBGBUS_GPC = 29, 344a69c5ed2SRob Clark A6XX_DBGBUS_LARC = 30, 345a69c5ed2SRob Clark A6XX_DBGBUS_HLSQ_SPTP = 31, 346a69c5ed2SRob Clark A6XX_DBGBUS_RB_0 = 32, 347a69c5ed2SRob Clark A6XX_DBGBUS_RB_1 = 33, 348a69c5ed2SRob Clark A6XX_DBGBUS_UCHE_WRAPPER = 36, 349a69c5ed2SRob Clark A6XX_DBGBUS_CCU_0 = 40, 350a69c5ed2SRob Clark A6XX_DBGBUS_CCU_1 = 41, 351a69c5ed2SRob Clark A6XX_DBGBUS_VFD_0 = 56, 352a69c5ed2SRob Clark A6XX_DBGBUS_VFD_1 = 57, 353a69c5ed2SRob Clark A6XX_DBGBUS_VFD_2 = 58, 354a69c5ed2SRob Clark A6XX_DBGBUS_VFD_3 = 59, 355a69c5ed2SRob Clark A6XX_DBGBUS_SP_0 = 64, 356a69c5ed2SRob Clark A6XX_DBGBUS_SP_1 = 65, 357a69c5ed2SRob Clark A6XX_DBGBUS_TPL1_0 = 72, 358a69c5ed2SRob Clark A6XX_DBGBUS_TPL1_1 = 73, 359a69c5ed2SRob Clark A6XX_DBGBUS_TPL1_2 = 74, 360a69c5ed2SRob Clark A6XX_DBGBUS_TPL1_3 = 75, 361a69c5ed2SRob Clark }; 362a69c5ed2SRob Clark 3632d756322SRob Clark enum a6xx_cp_perfcounter_select { 3642d756322SRob Clark PERF_CP_ALWAYS_COUNT = 0, 365a69c5ed2SRob Clark PERF_CP_BUSY_GFX_CORE_IDLE = 1, 366a69c5ed2SRob Clark PERF_CP_BUSY_CYCLES = 2, 367a69c5ed2SRob Clark PERF_CP_NUM_PREEMPTIONS = 3, 368a69c5ed2SRob Clark PERF_CP_PREEMPTION_REACTION_DELAY = 4, 369a69c5ed2SRob Clark PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 5, 370a69c5ed2SRob Clark PERF_CP_PREEMPTION_SWITCH_IN_TIME = 6, 371a69c5ed2SRob Clark PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 7, 372a69c5ed2SRob Clark PERF_CP_PREDICATED_DRAWS_KILLED = 8, 373a69c5ed2SRob Clark PERF_CP_MODE_SWITCH = 9, 374a69c5ed2SRob Clark PERF_CP_ZPASS_DONE = 10, 375a69c5ed2SRob Clark PERF_CP_CONTEXT_DONE = 11, 376a69c5ed2SRob Clark PERF_CP_CACHE_FLUSH = 12, 377a69c5ed2SRob Clark PERF_CP_LONG_PREEMPTIONS = 13, 378a69c5ed2SRob Clark PERF_CP_SQE_I_CACHE_STARVE = 14, 379a69c5ed2SRob Clark PERF_CP_SQE_IDLE = 15, 380a69c5ed2SRob Clark PERF_CP_SQE_PM4_STARVE_RB_IB = 16, 381a69c5ed2SRob Clark PERF_CP_SQE_PM4_STARVE_SDS = 17, 382a69c5ed2SRob Clark PERF_CP_SQE_MRB_STARVE = 18, 383a69c5ed2SRob Clark PERF_CP_SQE_RRB_STARVE = 19, 384a69c5ed2SRob Clark PERF_CP_SQE_VSD_STARVE = 20, 385a69c5ed2SRob Clark PERF_CP_VSD_DECODE_STARVE = 21, 386a69c5ed2SRob Clark PERF_CP_SQE_PIPE_OUT_STALL = 22, 387a69c5ed2SRob Clark PERF_CP_SQE_SYNC_STALL = 23, 388a69c5ed2SRob Clark PERF_CP_SQE_PM4_WFI_STALL = 24, 389a69c5ed2SRob Clark PERF_CP_SQE_SYS_WFI_STALL = 25, 390a69c5ed2SRob Clark PERF_CP_SQE_T4_EXEC = 26, 391a69c5ed2SRob Clark PERF_CP_SQE_LOAD_STATE_EXEC = 27, 392a69c5ed2SRob Clark PERF_CP_SQE_SAVE_SDS_STATE = 28, 393a69c5ed2SRob Clark PERF_CP_SQE_DRAW_EXEC = 29, 394a69c5ed2SRob Clark PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 30, 395a69c5ed2SRob Clark PERF_CP_SQE_EXEC_PROFILED = 31, 396a69c5ed2SRob Clark PERF_CP_MEMORY_POOL_EMPTY = 32, 397a69c5ed2SRob Clark PERF_CP_MEMORY_POOL_SYNC_STALL = 33, 398a69c5ed2SRob Clark PERF_CP_MEMORY_POOL_ABOVE_THRESH = 34, 399a69c5ed2SRob Clark PERF_CP_AHB_WR_STALL_PRE_DRAWS = 35, 400a69c5ed2SRob Clark PERF_CP_AHB_STALL_SQE_GMU = 36, 401a69c5ed2SRob Clark PERF_CP_AHB_STALL_SQE_WR_OTHER = 37, 402a69c5ed2SRob Clark PERF_CP_AHB_STALL_SQE_RD_OTHER = 38, 403a69c5ed2SRob Clark PERF_CP_CLUSTER0_EMPTY = 39, 404a69c5ed2SRob Clark PERF_CP_CLUSTER1_EMPTY = 40, 405a69c5ed2SRob Clark PERF_CP_CLUSTER2_EMPTY = 41, 406a69c5ed2SRob Clark PERF_CP_CLUSTER3_EMPTY = 42, 407a69c5ed2SRob Clark PERF_CP_CLUSTER4_EMPTY = 43, 408a69c5ed2SRob Clark PERF_CP_CLUSTER5_EMPTY = 44, 409a69c5ed2SRob Clark PERF_CP_PM4_DATA = 45, 410a69c5ed2SRob Clark PERF_CP_PM4_HEADERS = 46, 411a69c5ed2SRob Clark PERF_CP_VBIF_READ_BEATS = 47, 412a69c5ed2SRob Clark PERF_CP_VBIF_WRITE_BEATS = 48, 413a69c5ed2SRob Clark PERF_CP_SQE_INSTR_COUNTER = 49, 414a69c5ed2SRob Clark }; 415a69c5ed2SRob Clark 416a69c5ed2SRob Clark enum a6xx_rbbm_perfcounter_select { 417a69c5ed2SRob Clark PERF_RBBM_ALWAYS_COUNT = 0, 418a69c5ed2SRob Clark PERF_RBBM_ALWAYS_ON = 1, 419a69c5ed2SRob Clark PERF_RBBM_TSE_BUSY = 2, 420a69c5ed2SRob Clark PERF_RBBM_RAS_BUSY = 3, 421a69c5ed2SRob Clark PERF_RBBM_PC_DCALL_BUSY = 4, 422a69c5ed2SRob Clark PERF_RBBM_PC_VSD_BUSY = 5, 423a69c5ed2SRob Clark PERF_RBBM_STATUS_MASKED = 6, 424a69c5ed2SRob Clark PERF_RBBM_COM_BUSY = 7, 425a69c5ed2SRob Clark PERF_RBBM_DCOM_BUSY = 8, 426a69c5ed2SRob Clark PERF_RBBM_VBIF_BUSY = 9, 427a69c5ed2SRob Clark PERF_RBBM_VSC_BUSY = 10, 428a69c5ed2SRob Clark PERF_RBBM_TESS_BUSY = 11, 429a69c5ed2SRob Clark PERF_RBBM_UCHE_BUSY = 12, 430a69c5ed2SRob Clark PERF_RBBM_HLSQ_BUSY = 13, 431a69c5ed2SRob Clark }; 432a69c5ed2SRob Clark 433a69c5ed2SRob Clark enum a6xx_pc_perfcounter_select { 434a69c5ed2SRob Clark PERF_PC_BUSY_CYCLES = 0, 435a69c5ed2SRob Clark PERF_PC_WORKING_CYCLES = 1, 436a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_VFD = 2, 437a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_TSE = 3, 438a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_VPC = 4, 439a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_UCHE = 5, 440a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_TESS = 6, 441a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_TSE_ONLY = 7, 442a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_VPC_ONLY = 8, 443a69c5ed2SRob Clark PERF_PC_PASS1_TF_STALL_CYCLES = 9, 444a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_FOR_INDEX = 10, 445a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11, 446a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12, 447a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_FOR_POSITION = 13, 448a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_DI = 14, 449a69c5ed2SRob Clark PERF_PC_VIS_STREAMS_LOADED = 15, 450a69c5ed2SRob Clark PERF_PC_INSTANCES = 16, 451a69c5ed2SRob Clark PERF_PC_VPC_PRIMITIVES = 17, 452a69c5ed2SRob Clark PERF_PC_DEAD_PRIM = 18, 453a69c5ed2SRob Clark PERF_PC_LIVE_PRIM = 19, 454a69c5ed2SRob Clark PERF_PC_VERTEX_HITS = 20, 455a69c5ed2SRob Clark PERF_PC_IA_VERTICES = 21, 456a69c5ed2SRob Clark PERF_PC_IA_PRIMITIVES = 22, 457a69c5ed2SRob Clark PERF_PC_GS_PRIMITIVES = 23, 458a69c5ed2SRob Clark PERF_PC_HS_INVOCATIONS = 24, 459a69c5ed2SRob Clark PERF_PC_DS_INVOCATIONS = 25, 460a69c5ed2SRob Clark PERF_PC_VS_INVOCATIONS = 26, 461a69c5ed2SRob Clark PERF_PC_GS_INVOCATIONS = 27, 462a69c5ed2SRob Clark PERF_PC_DS_PRIMITIVES = 28, 463a69c5ed2SRob Clark PERF_PC_VPC_POS_DATA_TRANSACTION = 29, 464a69c5ed2SRob Clark PERF_PC_3D_DRAWCALLS = 30, 465a69c5ed2SRob Clark PERF_PC_2D_DRAWCALLS = 31, 466a69c5ed2SRob Clark PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32, 467a69c5ed2SRob Clark PERF_TESS_BUSY_CYCLES = 33, 468a69c5ed2SRob Clark PERF_TESS_WORKING_CYCLES = 34, 469a69c5ed2SRob Clark PERF_TESS_STALL_CYCLES_PC = 35, 470a69c5ed2SRob Clark PERF_TESS_STARVE_CYCLES_PC = 36, 471a69c5ed2SRob Clark PERF_PC_TSE_TRANSACTION = 37, 472a69c5ed2SRob Clark PERF_PC_TSE_VERTEX = 38, 473a69c5ed2SRob Clark PERF_PC_TESS_PC_UV_TRANS = 39, 474a69c5ed2SRob Clark PERF_PC_TESS_PC_UV_PATCHES = 40, 475a69c5ed2SRob Clark PERF_PC_TESS_FACTOR_TRANS = 41, 476a69c5ed2SRob Clark }; 477a69c5ed2SRob Clark 478a69c5ed2SRob Clark enum a6xx_vfd_perfcounter_select { 479a69c5ed2SRob Clark PERF_VFD_BUSY_CYCLES = 0, 480a69c5ed2SRob Clark PERF_VFD_STALL_CYCLES_UCHE = 1, 481a69c5ed2SRob Clark PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2, 482a69c5ed2SRob Clark PERF_VFD_STALL_CYCLES_SP_INFO = 3, 483a69c5ed2SRob Clark PERF_VFD_STALL_CYCLES_SP_ATTR = 4, 484a69c5ed2SRob Clark PERF_VFD_STARVE_CYCLES_UCHE = 5, 485a69c5ed2SRob Clark PERF_VFD_RBUFFER_FULL = 6, 486a69c5ed2SRob Clark PERF_VFD_ATTR_INFO_FIFO_FULL = 7, 487a69c5ed2SRob Clark PERF_VFD_DECODED_ATTRIBUTE_BYTES = 8, 488a69c5ed2SRob Clark PERF_VFD_NUM_ATTRIBUTES = 9, 489a69c5ed2SRob Clark PERF_VFD_UPPER_SHADER_FIBERS = 10, 490a69c5ed2SRob Clark PERF_VFD_LOWER_SHADER_FIBERS = 11, 491a69c5ed2SRob Clark PERF_VFD_MODE_0_FIBERS = 12, 492a69c5ed2SRob Clark PERF_VFD_MODE_1_FIBERS = 13, 493a69c5ed2SRob Clark PERF_VFD_MODE_2_FIBERS = 14, 494a69c5ed2SRob Clark PERF_VFD_MODE_3_FIBERS = 15, 495a69c5ed2SRob Clark PERF_VFD_MODE_4_FIBERS = 16, 496a69c5ed2SRob Clark PERF_VFD_TOTAL_VERTICES = 17, 497a69c5ed2SRob Clark PERF_VFDP_STALL_CYCLES_VFD = 18, 498a69c5ed2SRob Clark PERF_VFDP_STALL_CYCLES_VFD_INDEX = 19, 499a69c5ed2SRob Clark PERF_VFDP_STALL_CYCLES_VFD_PROG = 20, 500a69c5ed2SRob Clark PERF_VFDP_STARVE_CYCLES_PC = 21, 501a69c5ed2SRob Clark PERF_VFDP_VS_STAGE_WAVES = 22, 502a69c5ed2SRob Clark }; 503a69c5ed2SRob Clark 504ccdf7e28SRob Clark enum a6xx_hlsq_perfcounter_select { 505a69c5ed2SRob Clark PERF_HLSQ_BUSY_CYCLES = 0, 506a69c5ed2SRob Clark PERF_HLSQ_STALL_CYCLES_UCHE = 1, 507a69c5ed2SRob Clark PERF_HLSQ_STALL_CYCLES_SP_STATE = 2, 508a69c5ed2SRob Clark PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3, 509a69c5ed2SRob Clark PERF_HLSQ_UCHE_LATENCY_CYCLES = 4, 510a69c5ed2SRob Clark PERF_HLSQ_UCHE_LATENCY_COUNT = 5, 511a69c5ed2SRob Clark PERF_HLSQ_FS_STAGE_1X_WAVES = 6, 512a69c5ed2SRob Clark PERF_HLSQ_FS_STAGE_2X_WAVES = 7, 513a69c5ed2SRob Clark PERF_HLSQ_QUADS = 8, 514a69c5ed2SRob Clark PERF_HLSQ_CS_INVOCATIONS = 9, 515a69c5ed2SRob Clark PERF_HLSQ_COMPUTE_DRAWCALLS = 10, 516a69c5ed2SRob Clark PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11, 517a69c5ed2SRob Clark PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12, 518a69c5ed2SRob Clark PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13, 519a69c5ed2SRob Clark PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14, 520a69c5ed2SRob Clark PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15, 521a69c5ed2SRob Clark PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16, 522a69c5ed2SRob Clark PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17, 523a69c5ed2SRob Clark PERF_HLSQ_STALL_CYCLES_VPC = 18, 524a69c5ed2SRob Clark PERF_HLSQ_PIXELS = 19, 525a69c5ed2SRob Clark PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = 20, 526a69c5ed2SRob Clark }; 527a69c5ed2SRob Clark 528a69c5ed2SRob Clark enum a6xx_vpc_perfcounter_select { 529a69c5ed2SRob Clark PERF_VPC_BUSY_CYCLES = 0, 530a69c5ed2SRob Clark PERF_VPC_WORKING_CYCLES = 1, 531a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_UCHE = 2, 532a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_VFD_WACK = 3, 533a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4, 534a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_PC = 5, 535a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_SP_LM = 6, 536a69c5ed2SRob Clark PERF_VPC_STARVE_CYCLES_SP = 7, 537a69c5ed2SRob Clark PERF_VPC_STARVE_CYCLES_LRZ = 8, 538a69c5ed2SRob Clark PERF_VPC_PC_PRIMITIVES = 9, 539a69c5ed2SRob Clark PERF_VPC_SP_COMPONENTS = 10, 540a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_VPCRAM_POS = 11, 541a69c5ed2SRob Clark PERF_VPC_LRZ_ASSIGN_PRIMITIVES = 12, 542a69c5ed2SRob Clark PERF_VPC_RB_VISIBLE_PRIMITIVES = 13, 543a69c5ed2SRob Clark PERF_VPC_LM_TRANSACTION = 14, 544a69c5ed2SRob Clark PERF_VPC_STREAMOUT_TRANSACTION = 15, 545a69c5ed2SRob Clark PERF_VPC_VS_BUSY_CYCLES = 16, 546a69c5ed2SRob Clark PERF_VPC_PS_BUSY_CYCLES = 17, 547a69c5ed2SRob Clark PERF_VPC_VS_WORKING_CYCLES = 18, 548a69c5ed2SRob Clark PERF_VPC_PS_WORKING_CYCLES = 19, 549a69c5ed2SRob Clark PERF_VPC_STARVE_CYCLES_RB = 20, 550a69c5ed2SRob Clark PERF_VPC_NUM_VPCRAM_READ_POS = 21, 551a69c5ed2SRob Clark PERF_VPC_WIT_FULL_CYCLES = 22, 552a69c5ed2SRob Clark PERF_VPC_VPCRAM_FULL_CYCLES = 23, 553a69c5ed2SRob Clark PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = 24, 554a69c5ed2SRob Clark PERF_VPC_NUM_VPCRAM_WRITE = 25, 555a69c5ed2SRob Clark PERF_VPC_NUM_VPCRAM_READ_SO = 26, 556a69c5ed2SRob Clark PERF_VPC_NUM_ATTR_REQ_LM = 27, 557a69c5ed2SRob Clark }; 558a69c5ed2SRob Clark 559a69c5ed2SRob Clark enum a6xx_tse_perfcounter_select { 560a69c5ed2SRob Clark PERF_TSE_BUSY_CYCLES = 0, 561a69c5ed2SRob Clark PERF_TSE_CLIPPING_CYCLES = 1, 562a69c5ed2SRob Clark PERF_TSE_STALL_CYCLES_RAS = 2, 563a69c5ed2SRob Clark PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3, 564a69c5ed2SRob Clark PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4, 565a69c5ed2SRob Clark PERF_TSE_STARVE_CYCLES_PC = 5, 566a69c5ed2SRob Clark PERF_TSE_INPUT_PRIM = 6, 567a69c5ed2SRob Clark PERF_TSE_INPUT_NULL_PRIM = 7, 568a69c5ed2SRob Clark PERF_TSE_TRIVAL_REJ_PRIM = 8, 569a69c5ed2SRob Clark PERF_TSE_CLIPPED_PRIM = 9, 570a69c5ed2SRob Clark PERF_TSE_ZERO_AREA_PRIM = 10, 571a69c5ed2SRob Clark PERF_TSE_FACENESS_CULLED_PRIM = 11, 572a69c5ed2SRob Clark PERF_TSE_ZERO_PIXEL_PRIM = 12, 573a69c5ed2SRob Clark PERF_TSE_OUTPUT_NULL_PRIM = 13, 574a69c5ed2SRob Clark PERF_TSE_OUTPUT_VISIBLE_PRIM = 14, 575a69c5ed2SRob Clark PERF_TSE_CINVOCATION = 15, 576a69c5ed2SRob Clark PERF_TSE_CPRIMITIVES = 16, 577a69c5ed2SRob Clark PERF_TSE_2D_INPUT_PRIM = 17, 578a69c5ed2SRob Clark PERF_TSE_2D_ALIVE_CYCLES = 18, 579a69c5ed2SRob Clark PERF_TSE_CLIP_PLANES = 19, 580a69c5ed2SRob Clark }; 581a69c5ed2SRob Clark 582a69c5ed2SRob Clark enum a6xx_ras_perfcounter_select { 583a69c5ed2SRob Clark PERF_RAS_BUSY_CYCLES = 0, 584a69c5ed2SRob Clark PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1, 585a69c5ed2SRob Clark PERF_RAS_STALL_CYCLES_LRZ = 2, 586a69c5ed2SRob Clark PERF_RAS_STARVE_CYCLES_TSE = 3, 587a69c5ed2SRob Clark PERF_RAS_SUPER_TILES = 4, 588a69c5ed2SRob Clark PERF_RAS_8X4_TILES = 5, 589a69c5ed2SRob Clark PERF_RAS_MASKGEN_ACTIVE = 6, 590a69c5ed2SRob Clark PERF_RAS_FULLY_COVERED_SUPER_TILES = 7, 591a69c5ed2SRob Clark PERF_RAS_FULLY_COVERED_8X4_TILES = 8, 592a69c5ed2SRob Clark PERF_RAS_PRIM_KILLED_INVISILBE = 9, 593a69c5ed2SRob Clark PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 10, 594a69c5ed2SRob Clark PERF_RAS_LRZ_INTF_WORKING_CYCLES = 11, 595a69c5ed2SRob Clark PERF_RAS_BLOCKS = 12, 596a69c5ed2SRob Clark }; 597a69c5ed2SRob Clark 598a69c5ed2SRob Clark enum a6xx_uche_perfcounter_select { 599a69c5ed2SRob Clark PERF_UCHE_BUSY_CYCLES = 0, 600a69c5ed2SRob Clark PERF_UCHE_STALL_CYCLES_ARBITER = 1, 601a69c5ed2SRob Clark PERF_UCHE_VBIF_LATENCY_CYCLES = 2, 602a69c5ed2SRob Clark PERF_UCHE_VBIF_LATENCY_SAMPLES = 3, 603a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_TP = 4, 604a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_VFD = 5, 605a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6, 606a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_LRZ = 7, 607a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_SP = 8, 608a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_TP = 9, 609a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_VFD = 10, 610a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_HLSQ = 11, 611a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_LRZ = 12, 612a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_SP = 13, 613a69c5ed2SRob Clark PERF_UCHE_WRITE_REQUESTS_LRZ = 14, 614a69c5ed2SRob Clark PERF_UCHE_WRITE_REQUESTS_SP = 15, 615a69c5ed2SRob Clark PERF_UCHE_WRITE_REQUESTS_VPC = 16, 616a69c5ed2SRob Clark PERF_UCHE_WRITE_REQUESTS_VSC = 17, 617a69c5ed2SRob Clark PERF_UCHE_EVICTS = 18, 618a69c5ed2SRob Clark PERF_UCHE_BANK_REQ0 = 19, 619a69c5ed2SRob Clark PERF_UCHE_BANK_REQ1 = 20, 620a69c5ed2SRob Clark PERF_UCHE_BANK_REQ2 = 21, 621a69c5ed2SRob Clark PERF_UCHE_BANK_REQ3 = 22, 622a69c5ed2SRob Clark PERF_UCHE_BANK_REQ4 = 23, 623a69c5ed2SRob Clark PERF_UCHE_BANK_REQ5 = 24, 624a69c5ed2SRob Clark PERF_UCHE_BANK_REQ6 = 25, 625a69c5ed2SRob Clark PERF_UCHE_BANK_REQ7 = 26, 626a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_CH0 = 27, 627a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_CH1 = 28, 628a69c5ed2SRob Clark PERF_UCHE_GMEM_READ_BEATS = 29, 629a69c5ed2SRob Clark PERF_UCHE_TPH_REF_FULL = 30, 630a69c5ed2SRob Clark PERF_UCHE_TPH_VICTIM_FULL = 31, 631a69c5ed2SRob Clark PERF_UCHE_TPH_EXT_FULL = 32, 632a69c5ed2SRob Clark PERF_UCHE_VBIF_STALL_WRITE_DATA = 33, 633a69c5ed2SRob Clark PERF_UCHE_DCMP_LATENCY_SAMPLES = 34, 634a69c5ed2SRob Clark PERF_UCHE_DCMP_LATENCY_CYCLES = 35, 635a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_PC = 36, 636a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_PC = 37, 637a69c5ed2SRob Clark PERF_UCHE_RAM_READ_REQ = 38, 638a69c5ed2SRob Clark PERF_UCHE_RAM_WRITE_REQ = 39, 639a69c5ed2SRob Clark }; 640a69c5ed2SRob Clark 641a69c5ed2SRob Clark enum a6xx_tp_perfcounter_select { 642a69c5ed2SRob Clark PERF_TP_BUSY_CYCLES = 0, 643a69c5ed2SRob Clark PERF_TP_STALL_CYCLES_UCHE = 1, 644a69c5ed2SRob Clark PERF_TP_LATENCY_CYCLES = 2, 645a69c5ed2SRob Clark PERF_TP_LATENCY_TRANS = 3, 646a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4, 647a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5, 648a69c5ed2SRob Clark PERF_TP_L1_CACHELINE_REQUESTS = 6, 649a69c5ed2SRob Clark PERF_TP_L1_CACHELINE_MISSES = 7, 650a69c5ed2SRob Clark PERF_TP_SP_TP_TRANS = 8, 651a69c5ed2SRob Clark PERF_TP_TP_SP_TRANS = 9, 652a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS = 10, 653a69c5ed2SRob Clark PERF_TP_FILTER_WORKLOAD_16BIT = 11, 654a69c5ed2SRob Clark PERF_TP_FILTER_WORKLOAD_32BIT = 12, 655a69c5ed2SRob Clark PERF_TP_QUADS_RECEIVED = 13, 656a69c5ed2SRob Clark PERF_TP_QUADS_OFFSET = 14, 657a69c5ed2SRob Clark PERF_TP_QUADS_SHADOW = 15, 658a69c5ed2SRob Clark PERF_TP_QUADS_ARRAY = 16, 659a69c5ed2SRob Clark PERF_TP_QUADS_GRADIENT = 17, 660a69c5ed2SRob Clark PERF_TP_QUADS_1D = 18, 661a69c5ed2SRob Clark PERF_TP_QUADS_2D = 19, 662a69c5ed2SRob Clark PERF_TP_QUADS_BUFFER = 20, 663a69c5ed2SRob Clark PERF_TP_QUADS_3D = 21, 664a69c5ed2SRob Clark PERF_TP_QUADS_CUBE = 22, 665a69c5ed2SRob Clark PERF_TP_DIVERGENT_QUADS_RECEIVED = 23, 666a69c5ed2SRob Clark PERF_TP_PRT_NON_RESIDENT_EVENTS = 24, 667a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_POINT = 25, 668a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_BILINEAR = 26, 669a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_MIP = 27, 670a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_ANISO = 28, 671a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 29, 672a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_REQUESTS = 30, 673a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_MISSES = 31, 674a69c5ed2SRob Clark PERF_TP_L1_5_L2_REQUESTS = 32, 675a69c5ed2SRob Clark PERF_TP_2D_OUTPUT_PIXELS = 33, 676a69c5ed2SRob Clark PERF_TP_2D_OUTPUT_PIXELS_POINT = 34, 677a69c5ed2SRob Clark PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 35, 678a69c5ed2SRob Clark PERF_TP_2D_FILTER_WORKLOAD_16BIT = 36, 679a69c5ed2SRob Clark PERF_TP_2D_FILTER_WORKLOAD_32BIT = 37, 680a69c5ed2SRob Clark PERF_TP_TPA2TPC_TRANS = 38, 681a69c5ed2SRob Clark PERF_TP_L1_MISSES_ASTC_1TILE = 39, 682a69c5ed2SRob Clark PERF_TP_L1_MISSES_ASTC_2TILE = 40, 683a69c5ed2SRob Clark PERF_TP_L1_MISSES_ASTC_4TILE = 41, 684a69c5ed2SRob Clark PERF_TP_L1_5_L2_COMPRESS_REQS = 42, 685a69c5ed2SRob Clark PERF_TP_L1_5_L2_COMPRESS_MISS = 43, 686a69c5ed2SRob Clark PERF_TP_L1_BANK_CONFLICT = 44, 687a69c5ed2SRob Clark PERF_TP_L1_5_MISS_LATENCY_CYCLES = 45, 688a69c5ed2SRob Clark PERF_TP_L1_5_MISS_LATENCY_TRANS = 46, 689a69c5ed2SRob Clark PERF_TP_QUADS_CONSTANT_MULTIPLIED = 47, 690a69c5ed2SRob Clark PERF_TP_FRONTEND_WORKING_CYCLES = 48, 691a69c5ed2SRob Clark PERF_TP_L1_TAG_WORKING_CYCLES = 49, 692a69c5ed2SRob Clark PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 50, 693a69c5ed2SRob Clark PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 51, 694a69c5ed2SRob Clark PERF_TP_BACKEND_WORKING_CYCLES = 52, 695a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_WORKING_CYCLES = 53, 696a69c5ed2SRob Clark PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54, 697a69c5ed2SRob Clark PERF_TP_STARVE_CYCLES_SP = 55, 698a69c5ed2SRob Clark PERF_TP_STARVE_CYCLES_UCHE = 56, 699a69c5ed2SRob Clark }; 700a69c5ed2SRob Clark 701a69c5ed2SRob Clark enum a6xx_sp_perfcounter_select { 702a69c5ed2SRob Clark PERF_SP_BUSY_CYCLES = 0, 703a69c5ed2SRob Clark PERF_SP_ALU_WORKING_CYCLES = 1, 704a69c5ed2SRob Clark PERF_SP_EFU_WORKING_CYCLES = 2, 705a69c5ed2SRob Clark PERF_SP_STALL_CYCLES_VPC = 3, 706a69c5ed2SRob Clark PERF_SP_STALL_CYCLES_TP = 4, 707a69c5ed2SRob Clark PERF_SP_STALL_CYCLES_UCHE = 5, 708a69c5ed2SRob Clark PERF_SP_STALL_CYCLES_RB = 6, 709a69c5ed2SRob Clark PERF_SP_NON_EXECUTION_CYCLES = 7, 710a69c5ed2SRob Clark PERF_SP_WAVE_CONTEXTS = 8, 711a69c5ed2SRob Clark PERF_SP_WAVE_CONTEXT_CYCLES = 9, 712a69c5ed2SRob Clark PERF_SP_FS_STAGE_WAVE_CYCLES = 10, 713a69c5ed2SRob Clark PERF_SP_FS_STAGE_WAVE_SAMPLES = 11, 714a69c5ed2SRob Clark PERF_SP_VS_STAGE_WAVE_CYCLES = 12, 715a69c5ed2SRob Clark PERF_SP_VS_STAGE_WAVE_SAMPLES = 13, 716a69c5ed2SRob Clark PERF_SP_FS_STAGE_DURATION_CYCLES = 14, 717a69c5ed2SRob Clark PERF_SP_VS_STAGE_DURATION_CYCLES = 15, 718a69c5ed2SRob Clark PERF_SP_WAVE_CTRL_CYCLES = 16, 719a69c5ed2SRob Clark PERF_SP_WAVE_LOAD_CYCLES = 17, 720a69c5ed2SRob Clark PERF_SP_WAVE_EMIT_CYCLES = 18, 721a69c5ed2SRob Clark PERF_SP_WAVE_NOP_CYCLES = 19, 722a69c5ed2SRob Clark PERF_SP_WAVE_WAIT_CYCLES = 20, 723a69c5ed2SRob Clark PERF_SP_WAVE_FETCH_CYCLES = 21, 724a69c5ed2SRob Clark PERF_SP_WAVE_IDLE_CYCLES = 22, 725a69c5ed2SRob Clark PERF_SP_WAVE_END_CYCLES = 23, 726a69c5ed2SRob Clark PERF_SP_WAVE_LONG_SYNC_CYCLES = 24, 727a69c5ed2SRob Clark PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25, 728a69c5ed2SRob Clark PERF_SP_WAVE_JOIN_CYCLES = 26, 729a69c5ed2SRob Clark PERF_SP_LM_LOAD_INSTRUCTIONS = 27, 730a69c5ed2SRob Clark PERF_SP_LM_STORE_INSTRUCTIONS = 28, 731a69c5ed2SRob Clark PERF_SP_LM_ATOMICS = 29, 732a69c5ed2SRob Clark PERF_SP_GM_LOAD_INSTRUCTIONS = 30, 733a69c5ed2SRob Clark PERF_SP_GM_STORE_INSTRUCTIONS = 31, 734a69c5ed2SRob Clark PERF_SP_GM_ATOMICS = 32, 735a69c5ed2SRob Clark PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33, 736a69c5ed2SRob Clark PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34, 737a69c5ed2SRob Clark PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35, 738a69c5ed2SRob Clark PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36, 739a69c5ed2SRob Clark PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37, 740a69c5ed2SRob Clark PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38, 741a69c5ed2SRob Clark PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39, 742a69c5ed2SRob Clark PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40, 743a69c5ed2SRob Clark PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41, 744a69c5ed2SRob Clark PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42, 745a69c5ed2SRob Clark PERF_SP_VS_INSTRUCTIONS = 43, 746a69c5ed2SRob Clark PERF_SP_FS_INSTRUCTIONS = 44, 747a69c5ed2SRob Clark PERF_SP_ADDR_LOCK_COUNT = 45, 748a69c5ed2SRob Clark PERF_SP_UCHE_READ_TRANS = 46, 749a69c5ed2SRob Clark PERF_SP_UCHE_WRITE_TRANS = 47, 750a69c5ed2SRob Clark PERF_SP_EXPORT_VPC_TRANS = 48, 751a69c5ed2SRob Clark PERF_SP_EXPORT_RB_TRANS = 49, 752a69c5ed2SRob Clark PERF_SP_PIXELS_KILLED = 50, 753a69c5ed2SRob Clark PERF_SP_ICL1_REQUESTS = 51, 754a69c5ed2SRob Clark PERF_SP_ICL1_MISSES = 52, 755a69c5ed2SRob Clark PERF_SP_HS_INSTRUCTIONS = 53, 756a69c5ed2SRob Clark PERF_SP_DS_INSTRUCTIONS = 54, 757a69c5ed2SRob Clark PERF_SP_GS_INSTRUCTIONS = 55, 758a69c5ed2SRob Clark PERF_SP_CS_INSTRUCTIONS = 56, 759a69c5ed2SRob Clark PERF_SP_GPR_READ = 57, 760a69c5ed2SRob Clark PERF_SP_GPR_WRITE = 58, 761a69c5ed2SRob Clark PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59, 762a69c5ed2SRob Clark PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60, 763a69c5ed2SRob Clark PERF_SP_LM_BANK_CONFLICTS = 61, 764a69c5ed2SRob Clark PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62, 765a69c5ed2SRob Clark PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63, 766a69c5ed2SRob Clark PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64, 767a69c5ed2SRob Clark PERF_SP_LM_WORKING_CYCLES = 65, 768a69c5ed2SRob Clark PERF_SP_DISPATCHER_WORKING_CYCLES = 66, 769a69c5ed2SRob Clark PERF_SP_SEQUENCER_WORKING_CYCLES = 67, 770a69c5ed2SRob Clark PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68, 771a69c5ed2SRob Clark PERF_SP_STARVE_CYCLES_HLSQ = 69, 772a69c5ed2SRob Clark PERF_SP_NON_EXECUTION_LS_CYCLES = 70, 773a69c5ed2SRob Clark PERF_SP_WORKING_EU = 71, 774a69c5ed2SRob Clark PERF_SP_ANY_EU_WORKING = 72, 775a69c5ed2SRob Clark PERF_SP_WORKING_EU_FS_STAGE = 73, 776a69c5ed2SRob Clark PERF_SP_ANY_EU_WORKING_FS_STAGE = 74, 777a69c5ed2SRob Clark PERF_SP_WORKING_EU_VS_STAGE = 75, 778a69c5ed2SRob Clark PERF_SP_ANY_EU_WORKING_VS_STAGE = 76, 779a69c5ed2SRob Clark PERF_SP_WORKING_EU_CS_STAGE = 77, 780a69c5ed2SRob Clark PERF_SP_ANY_EU_WORKING_CS_STAGE = 78, 781a69c5ed2SRob Clark PERF_SP_GPR_READ_PREFETCH = 79, 782a69c5ed2SRob Clark PERF_SP_GPR_READ_CONFLICT = 80, 783a69c5ed2SRob Clark PERF_SP_GPR_WRITE_CONFLICT = 81, 784a69c5ed2SRob Clark PERF_SP_GM_LOAD_LATENCY_CYCLES = 82, 785a69c5ed2SRob Clark PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83, 786a69c5ed2SRob Clark PERF_SP_EXECUTABLE_WAVES = 84, 787a69c5ed2SRob Clark }; 788a69c5ed2SRob Clark 789a69c5ed2SRob Clark enum a6xx_rb_perfcounter_select { 790a69c5ed2SRob Clark PERF_RB_BUSY_CYCLES = 0, 791a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_HLSQ = 1, 792a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_FIFO0_FULL = 2, 793a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_FIFO1_FULL = 3, 794a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_FIFO2_FULL = 4, 795a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_SP = 5, 796a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_LRZ_TILE = 6, 797a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_CCU = 7, 798a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_Z_PLANE = 8, 799a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_BARY_PLANE = 9, 800a69c5ed2SRob Clark PERF_RB_Z_WORKLOAD = 10, 801a69c5ed2SRob Clark PERF_RB_HLSQ_ACTIVE = 11, 802a69c5ed2SRob Clark PERF_RB_Z_READ = 12, 803a69c5ed2SRob Clark PERF_RB_Z_WRITE = 13, 804a69c5ed2SRob Clark PERF_RB_C_READ = 14, 805a69c5ed2SRob Clark PERF_RB_C_WRITE = 15, 806a69c5ed2SRob Clark PERF_RB_TOTAL_PASS = 16, 807a69c5ed2SRob Clark PERF_RB_Z_PASS = 17, 808a69c5ed2SRob Clark PERF_RB_Z_FAIL = 18, 809a69c5ed2SRob Clark PERF_RB_S_FAIL = 19, 810a69c5ed2SRob Clark PERF_RB_BLENDED_FXP_COMPONENTS = 20, 811a69c5ed2SRob Clark PERF_RB_BLENDED_FP16_COMPONENTS = 21, 812a69c5ed2SRob Clark PERF_RB_PS_INVOCATIONS = 22, 813a69c5ed2SRob Clark PERF_RB_2D_ALIVE_CYCLES = 23, 814a69c5ed2SRob Clark PERF_RB_2D_STALL_CYCLES_A2D = 24, 815a69c5ed2SRob Clark PERF_RB_2D_STARVE_CYCLES_SRC = 25, 816a69c5ed2SRob Clark PERF_RB_2D_STARVE_CYCLES_SP = 26, 817a69c5ed2SRob Clark PERF_RB_2D_STARVE_CYCLES_DST = 27, 818a69c5ed2SRob Clark PERF_RB_2D_VALID_PIXELS = 28, 819a69c5ed2SRob Clark PERF_RB_3D_PIXELS = 29, 820a69c5ed2SRob Clark PERF_RB_BLENDER_WORKING_CYCLES = 30, 821a69c5ed2SRob Clark PERF_RB_ZPROC_WORKING_CYCLES = 31, 822a69c5ed2SRob Clark PERF_RB_CPROC_WORKING_CYCLES = 32, 823a69c5ed2SRob Clark PERF_RB_SAMPLER_WORKING_CYCLES = 33, 824a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 34, 825a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 35, 826a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 36, 827a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 37, 828a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_VPC = 38, 829a69c5ed2SRob Clark PERF_RB_2D_INPUT_TRANS = 39, 830a69c5ed2SRob Clark PERF_RB_2D_OUTPUT_RB_DST_TRANS = 40, 831a69c5ed2SRob Clark PERF_RB_2D_OUTPUT_RB_SRC_TRANS = 41, 832a69c5ed2SRob Clark PERF_RB_BLENDED_FP32_COMPONENTS = 42, 833a69c5ed2SRob Clark PERF_RB_COLOR_PIX_TILES = 43, 834a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU = 44, 835a69c5ed2SRob Clark PERF_RB_EARLY_Z_ARB3_GRANT = 45, 836a69c5ed2SRob Clark PERF_RB_LATE_Z_ARB3_GRANT = 46, 837a69c5ed2SRob Clark PERF_RB_EARLY_Z_SKIP_GRANT = 47, 838a69c5ed2SRob Clark }; 839a69c5ed2SRob Clark 840a69c5ed2SRob Clark enum a6xx_vsc_perfcounter_select { 841a69c5ed2SRob Clark PERF_VSC_BUSY_CYCLES = 0, 842a69c5ed2SRob Clark PERF_VSC_WORKING_CYCLES = 1, 843a69c5ed2SRob Clark PERF_VSC_STALL_CYCLES_UCHE = 2, 844a69c5ed2SRob Clark PERF_VSC_EOT_NUM = 3, 845a69c5ed2SRob Clark PERF_VSC_INPUT_TILES = 4, 846a69c5ed2SRob Clark }; 847a69c5ed2SRob Clark 848a69c5ed2SRob Clark enum a6xx_ccu_perfcounter_select { 849a69c5ed2SRob Clark PERF_CCU_BUSY_CYCLES = 0, 850a69c5ed2SRob Clark PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1, 851a69c5ed2SRob Clark PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2, 852a69c5ed2SRob Clark PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3, 853a69c5ed2SRob Clark PERF_CCU_DEPTH_BLOCKS = 4, 854a69c5ed2SRob Clark PERF_CCU_COLOR_BLOCKS = 5, 855a69c5ed2SRob Clark PERF_CCU_DEPTH_BLOCK_HIT = 6, 856a69c5ed2SRob Clark PERF_CCU_COLOR_BLOCK_HIT = 7, 857a69c5ed2SRob Clark PERF_CCU_PARTIAL_BLOCK_READ = 8, 858a69c5ed2SRob Clark PERF_CCU_GMEM_READ = 9, 859a69c5ed2SRob Clark PERF_CCU_GMEM_WRITE = 10, 860a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11, 861a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12, 862a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13, 863a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14, 864a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15, 865a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG5_COUNT = 16, 866a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG6_COUNT = 17, 867a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG8_COUNT = 18, 868a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG0_COUNT = 19, 869a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG1_COUNT = 20, 870a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG2_COUNT = 21, 871a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG3_COUNT = 22, 872a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG4_COUNT = 23, 873a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG5_COUNT = 24, 874a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG6_COUNT = 25, 875a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG8_COUNT = 26, 876a69c5ed2SRob Clark PERF_CCU_2D_RD_REQ = 27, 877a69c5ed2SRob Clark PERF_CCU_2D_WR_REQ = 28, 878a69c5ed2SRob Clark }; 879a69c5ed2SRob Clark 880a69c5ed2SRob Clark enum a6xx_lrz_perfcounter_select { 881a69c5ed2SRob Clark PERF_LRZ_BUSY_CYCLES = 0, 882a69c5ed2SRob Clark PERF_LRZ_STARVE_CYCLES_RAS = 1, 883a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_RB = 2, 884a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_VSC = 3, 885a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_VPC = 4, 886a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5, 887a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_UCHE = 6, 888a69c5ed2SRob Clark PERF_LRZ_LRZ_READ = 7, 889a69c5ed2SRob Clark PERF_LRZ_LRZ_WRITE = 8, 890a69c5ed2SRob Clark PERF_LRZ_READ_LATENCY = 9, 891a69c5ed2SRob Clark PERF_LRZ_MERGE_CACHE_UPDATING = 10, 892a69c5ed2SRob Clark PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11, 893a69c5ed2SRob Clark PERF_LRZ_PRIM_KILLED_BY_LRZ = 12, 894a69c5ed2SRob Clark PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13, 895a69c5ed2SRob Clark PERF_LRZ_FULL_8X8_TILES = 14, 896a69c5ed2SRob Clark PERF_LRZ_PARTIAL_8X8_TILES = 15, 897a69c5ed2SRob Clark PERF_LRZ_TILE_KILLED = 16, 898a69c5ed2SRob Clark PERF_LRZ_TOTAL_PIXEL = 17, 899a69c5ed2SRob Clark PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18, 900a69c5ed2SRob Clark PERF_LRZ_FULLY_COVERED_TILES = 19, 901a69c5ed2SRob Clark PERF_LRZ_PARTIAL_COVERED_TILES = 20, 902a69c5ed2SRob Clark PERF_LRZ_FEEDBACK_ACCEPT = 21, 903a69c5ed2SRob Clark PERF_LRZ_FEEDBACK_DISCARD = 22, 904a69c5ed2SRob Clark PERF_LRZ_FEEDBACK_STALL = 23, 905a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 24, 906a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_RB_BPLANE = 25, 907a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_VC = 26, 908a69c5ed2SRob Clark PERF_LRZ_RAS_MASK_TRANS = 27, 909a69c5ed2SRob Clark }; 910a69c5ed2SRob Clark 911a69c5ed2SRob Clark enum a6xx_cmp_perfcounter_select { 912a69c5ed2SRob Clark PERF_CMPDECMP_STALL_CYCLES_ARB = 0, 913a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1, 914a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2, 915a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3, 916a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4, 917a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_REQUEST = 5, 918a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6, 919a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_DATA = 7, 920a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_WRITE_DATA = 8, 921a69c5ed2SRob Clark PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9, 922a69c5ed2SRob Clark PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10, 923a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11, 924a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12, 925a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13, 926a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14, 927a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 15, 928a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 16, 929a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 17, 930a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 18, 931a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 19, 932a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 20, 933a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 21, 934a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 22, 935a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 23, 936a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 24, 937a69c5ed2SRob Clark PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 25, 938a69c5ed2SRob Clark PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 26, 939a69c5ed2SRob Clark PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 27, 940a69c5ed2SRob Clark PERF_CMPDECMP_2D_RD_DATA = 28, 941a69c5ed2SRob Clark PERF_CMPDECMP_2D_WR_DATA = 29, 942a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 30, 943a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 31, 944a69c5ed2SRob Clark PERF_CMPDECMP_2D_OUTPUT_TRANS = 32, 945a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 33, 946a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 34, 947a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 35, 948a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 36, 949a69c5ed2SRob Clark PERF_CMPDECMP_2D_BUSY_CYCLES = 37, 950a69c5ed2SRob Clark PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = 38, 951a69c5ed2SRob Clark PERF_CMPDECMP_2D_PIXELS = 39, 9522d756322SRob Clark }; 9532d756322SRob Clark 9542d756322SRob Clark enum a6xx_tex_filter { 9552d756322SRob Clark A6XX_TEX_NEAREST = 0, 9562d756322SRob Clark A6XX_TEX_LINEAR = 1, 9572d756322SRob Clark A6XX_TEX_ANISO = 2, 9582d756322SRob Clark }; 9592d756322SRob Clark 9602d756322SRob Clark enum a6xx_tex_clamp { 9612d756322SRob Clark A6XX_TEX_REPEAT = 0, 9622d756322SRob Clark A6XX_TEX_CLAMP_TO_EDGE = 1, 9632d756322SRob Clark A6XX_TEX_MIRROR_REPEAT = 2, 9642d756322SRob Clark A6XX_TEX_CLAMP_TO_BORDER = 3, 9652d756322SRob Clark A6XX_TEX_MIRROR_CLAMP = 4, 9662d756322SRob Clark }; 9672d756322SRob Clark 9682d756322SRob Clark enum a6xx_tex_aniso { 9692d756322SRob Clark A6XX_TEX_ANISO_1 = 0, 9702d756322SRob Clark A6XX_TEX_ANISO_2 = 1, 9712d756322SRob Clark A6XX_TEX_ANISO_4 = 2, 9722d756322SRob Clark A6XX_TEX_ANISO_8 = 3, 9732d756322SRob Clark A6XX_TEX_ANISO_16 = 4, 9742d756322SRob Clark }; 9752d756322SRob Clark 9762d756322SRob Clark enum a6xx_tex_swiz { 9772d756322SRob Clark A6XX_TEX_X = 0, 9782d756322SRob Clark A6XX_TEX_Y = 1, 9792d756322SRob Clark A6XX_TEX_Z = 2, 9802d756322SRob Clark A6XX_TEX_W = 3, 9812d756322SRob Clark A6XX_TEX_ZERO = 4, 9822d756322SRob Clark A6XX_TEX_ONE = 5, 9832d756322SRob Clark }; 9842d756322SRob Clark 9852d756322SRob Clark enum a6xx_tex_type { 9862d756322SRob Clark A6XX_TEX_1D = 0, 9872d756322SRob Clark A6XX_TEX_2D = 1, 9882d756322SRob Clark A6XX_TEX_CUBE = 2, 9892d756322SRob Clark A6XX_TEX_3D = 3, 9902d756322SRob Clark }; 9912d756322SRob Clark 9922d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001 9932d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR 0x00000002 9942d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW 0x00000040 9952d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080 9962d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_SW 0x00000100 9972d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200 9982d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400 9992d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800 10002d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000 10012d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_IB2 0x00002000 10022d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_IB1 0x00004000 10032d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_RB 0x00008000 10042d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000 10052d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000 10062d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000 10072d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000 10082d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT 0x00800000 10092d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000 10102d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000 10112d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000 10122d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000 10132d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000 10142d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000 10152d756322SRob Clark #define A6XX_CP_INT_CP_OPCODE_ERROR 0x00000001 10162d756322SRob Clark #define A6XX_CP_INT_CP_UCODE_ERROR 0x00000002 10172d756322SRob Clark #define A6XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004 10182d756322SRob Clark #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010 10192d756322SRob Clark #define A6XX_CP_INT_CP_AHB_ERROR 0x00000020 10202d756322SRob Clark #define A6XX_CP_INT_CP_VSD_PARITY_ERROR 0x00000040 10212d756322SRob Clark #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR 0x00000080 10222d756322SRob Clark #define REG_A6XX_CP_RB_BASE 0x00000800 10232d756322SRob Clark 10242d756322SRob Clark #define REG_A6XX_CP_RB_BASE_HI 0x00000801 10252d756322SRob Clark 10262d756322SRob Clark #define REG_A6XX_CP_RB_CNTL 0x00000802 10272d756322SRob Clark 10282d756322SRob Clark #define REG_A6XX_CP_RB_RPTR_ADDR_LO 0x00000804 10292d756322SRob Clark 10302d756322SRob Clark #define REG_A6XX_CP_RB_RPTR_ADDR_HI 0x00000805 10312d756322SRob Clark 10322d756322SRob Clark #define REG_A6XX_CP_RB_RPTR 0x00000806 10332d756322SRob Clark 10342d756322SRob Clark #define REG_A6XX_CP_RB_WPTR 0x00000807 10352d756322SRob Clark 10362d756322SRob Clark #define REG_A6XX_CP_SQE_CNTL 0x00000808 10372d756322SRob Clark 10382d756322SRob Clark #define REG_A6XX_CP_HW_FAULT 0x00000821 10392d756322SRob Clark 10402d756322SRob Clark #define REG_A6XX_CP_INTERRUPT_STATUS 0x00000823 10412d756322SRob Clark 10422d756322SRob Clark #define REG_A6XX_CP_PROTECT_STATUS 0x00000824 10432d756322SRob Clark 10442d756322SRob Clark #define REG_A6XX_CP_SQE_INSTR_BASE_LO 0x00000830 10452d756322SRob Clark 10462d756322SRob Clark #define REG_A6XX_CP_SQE_INSTR_BASE_HI 0x00000831 10472d756322SRob Clark 10482d756322SRob Clark #define REG_A6XX_CP_MISC_CNTL 0x00000840 10492d756322SRob Clark 10502d756322SRob Clark #define REG_A6XX_CP_ROQ_THRESHOLDS_1 0x000008c1 10512d756322SRob Clark 10522d756322SRob Clark #define REG_A6XX_CP_ROQ_THRESHOLDS_2 0x000008c2 10532d756322SRob Clark 10542d756322SRob Clark #define REG_A6XX_CP_MEM_POOL_SIZE 0x000008c3 10552d756322SRob Clark 10562d756322SRob Clark #define REG_A6XX_CP_CHICKEN_DBG 0x00000841 10572d756322SRob Clark 10582d756322SRob Clark #define REG_A6XX_CP_ADDR_MODE_CNTL 0x00000842 10592d756322SRob Clark 10602d756322SRob Clark #define REG_A6XX_CP_DBG_ECO_CNTL 0x00000843 10612d756322SRob Clark 10622d756322SRob Clark #define REG_A6XX_CP_PROTECT_CNTL 0x0000084f 10632d756322SRob Clark 10642d756322SRob Clark static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; } 10652d756322SRob Clark 10662d756322SRob Clark static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; } 10672d756322SRob Clark 10682d756322SRob Clark static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; } 10692d756322SRob Clark 10702d756322SRob Clark static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; } 10712d756322SRob Clark #define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0003ffff 10722d756322SRob Clark #define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0 10732d756322SRob Clark static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) 10742d756322SRob Clark { 10752d756322SRob Clark return ((val) << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK; 10762d756322SRob Clark } 10772d756322SRob Clark #define A6XX_CP_PROTECT_REG_MASK_LEN__MASK 0x7ffc0000 10782d756322SRob Clark #define A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT 18 10792d756322SRob Clark static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) 10802d756322SRob Clark { 10812d756322SRob Clark return ((val) << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK; 10822d756322SRob Clark } 10832d756322SRob Clark #define A6XX_CP_PROTECT_REG_READ 0x80000000 10842d756322SRob Clark 10852d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_CNTL 0x000008a0 10862d756322SRob Clark 10872d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x000008a1 10882d756322SRob Clark 10892d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x000008a2 10902d756322SRob Clark 10912d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO 0x000008a3 10922d756322SRob Clark 10932d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI 0x000008a4 10942d756322SRob Clark 10952d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO 0x000008a5 10962d756322SRob Clark 10972d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI 0x000008a6 10982d756322SRob Clark 10992d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO 0x000008a7 11002d756322SRob Clark 11012d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI 0x000008a8 11022d756322SRob Clark 11032d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_0 0x000008d0 11042d756322SRob Clark 11052d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_1 0x000008d1 11062d756322SRob Clark 11072d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_2 0x000008d2 11082d756322SRob Clark 11092d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_3 0x000008d3 11102d756322SRob Clark 11112d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_4 0x000008d4 11122d756322SRob Clark 11132d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_5 0x000008d5 11142d756322SRob Clark 11152d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_6 0x000008d6 11162d756322SRob Clark 11172d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_7 0x000008d7 11182d756322SRob Clark 11192d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_8 0x000008d8 11202d756322SRob Clark 11212d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_9 0x000008d9 11222d756322SRob Clark 11232d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_10 0x000008da 11242d756322SRob Clark 11252d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_11 0x000008db 11262d756322SRob Clark 11272d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_12 0x000008dc 11282d756322SRob Clark 11292d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_13 0x000008dd 11302d756322SRob Clark 11312d756322SRob Clark #define REG_A6XX_CP_CRASH_SCRIPT_BASE_LO 0x00000900 11322d756322SRob Clark 11332d756322SRob Clark #define REG_A6XX_CP_CRASH_SCRIPT_BASE_HI 0x00000901 11342d756322SRob Clark 11352d756322SRob Clark #define REG_A6XX_CP_CRASH_DUMP_CNTL 0x00000902 11362d756322SRob Clark 11372d756322SRob Clark #define REG_A6XX_CP_CRASH_DUMP_STATUS 0x00000903 11382d756322SRob Clark 11392d756322SRob Clark #define REG_A6XX_CP_SQE_STAT_ADDR 0x00000908 11402d756322SRob Clark 11412d756322SRob Clark #define REG_A6XX_CP_SQE_STAT_DATA 0x00000909 11422d756322SRob Clark 11432d756322SRob Clark #define REG_A6XX_CP_DRAW_STATE_ADDR 0x0000090a 11442d756322SRob Clark 11452d756322SRob Clark #define REG_A6XX_CP_DRAW_STATE_DATA 0x0000090b 11462d756322SRob Clark 11472d756322SRob Clark #define REG_A6XX_CP_ROQ_DBG_ADDR 0x0000090c 11482d756322SRob Clark 11492d756322SRob Clark #define REG_A6XX_CP_ROQ_DBG_DATA 0x0000090d 11502d756322SRob Clark 11512d756322SRob Clark #define REG_A6XX_CP_MEM_POOL_DBG_ADDR 0x0000090e 11522d756322SRob Clark 11532d756322SRob Clark #define REG_A6XX_CP_MEM_POOL_DBG_DATA 0x0000090f 11542d756322SRob Clark 11552d756322SRob Clark #define REG_A6XX_CP_SQE_UCODE_DBG_ADDR 0x00000910 11562d756322SRob Clark 11572d756322SRob Clark #define REG_A6XX_CP_SQE_UCODE_DBG_DATA 0x00000911 11582d756322SRob Clark 11592d756322SRob Clark #define REG_A6XX_CP_IB1_BASE 0x00000928 11602d756322SRob Clark 11612d756322SRob Clark #define REG_A6XX_CP_IB1_BASE_HI 0x00000929 11622d756322SRob Clark 11632d756322SRob Clark #define REG_A6XX_CP_IB1_REM_SIZE 0x0000092a 11642d756322SRob Clark 11652d756322SRob Clark #define REG_A6XX_CP_IB2_BASE 0x0000092b 11662d756322SRob Clark 11672d756322SRob Clark #define REG_A6XX_CP_IB2_BASE_HI 0x0000092c 11682d756322SRob Clark 11692d756322SRob Clark #define REG_A6XX_CP_IB2_REM_SIZE 0x0000092d 11702d756322SRob Clark 11712d756322SRob Clark #define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO 0x00000980 11722d756322SRob Clark 11732d756322SRob Clark #define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI 0x00000981 11742d756322SRob Clark 11752d756322SRob Clark #define REG_A6XX_CP_AHB_CNTL 0x0000098d 11762d756322SRob Clark 11772d756322SRob Clark #define REG_A6XX_CP_APERTURE_CNTL_HOST 0x00000a00 11782d756322SRob Clark 11792d756322SRob Clark #define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03 11802d756322SRob Clark 11812d756322SRob Clark #define REG_A6XX_VSC_ADDR_MODE_CNTL 0x00000c01 11822d756322SRob Clark 11832d756322SRob Clark #define REG_A6XX_RBBM_INT_0_STATUS 0x00000201 11842d756322SRob Clark 11852d756322SRob Clark #define REG_A6XX_RBBM_STATUS 0x00000210 11862d756322SRob Clark #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x00800000 11872d756322SRob Clark #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x00400000 11882d756322SRob Clark #define A6XX_RBBM_STATUS_HLSQ_BUSY 0x00200000 11892d756322SRob Clark #define A6XX_RBBM_STATUS_VSC_BUSY 0x00100000 11902d756322SRob Clark #define A6XX_RBBM_STATUS_TPL1_BUSY 0x00080000 11912d756322SRob Clark #define A6XX_RBBM_STATUS_SP_BUSY 0x00040000 11922d756322SRob Clark #define A6XX_RBBM_STATUS_UCHE_BUSY 0x00020000 11932d756322SRob Clark #define A6XX_RBBM_STATUS_VPC_BUSY 0x00010000 11942d756322SRob Clark #define A6XX_RBBM_STATUS_VFD_BUSY 0x00008000 11952d756322SRob Clark #define A6XX_RBBM_STATUS_TESS_BUSY 0x00004000 11962d756322SRob Clark #define A6XX_RBBM_STATUS_PC_VSD_BUSY 0x00002000 11972d756322SRob Clark #define A6XX_RBBM_STATUS_PC_DCALL_BUSY 0x00001000 11982d756322SRob Clark #define A6XX_RBBM_STATUS_COM_DCOM_BUSY 0x00000800 11992d756322SRob Clark #define A6XX_RBBM_STATUS_LRZ_BUSY 0x00000400 12002d756322SRob Clark #define A6XX_RBBM_STATUS_A2D_BUSY 0x00000200 12012d756322SRob Clark #define A6XX_RBBM_STATUS_CCU_BUSY 0x00000100 12022d756322SRob Clark #define A6XX_RBBM_STATUS_RB_BUSY 0x00000080 12032d756322SRob Clark #define A6XX_RBBM_STATUS_RAS_BUSY 0x00000040 12042d756322SRob Clark #define A6XX_RBBM_STATUS_TSE_BUSY 0x00000020 12052d756322SRob Clark #define A6XX_RBBM_STATUS_VBIF_BUSY 0x00000010 12062d756322SRob Clark #define A6XX_RBBM_STATUS_GFX_DBGC_BUSY 0x00000008 12072d756322SRob Clark #define A6XX_RBBM_STATUS_CP_BUSY 0x00000004 12082d756322SRob Clark #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER 0x00000002 12092d756322SRob Clark #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER 0x00000001 12102d756322SRob Clark 12112d756322SRob Clark #define REG_A6XX_RBBM_STATUS3 0x00000213 12122d756322SRob Clark 12132d756322SRob Clark #define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215 12142d756322SRob Clark 12152d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_0_LO 0x00000400 12162d756322SRob Clark 12172d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_0_HI 0x00000401 12182d756322SRob Clark 12192d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_1_LO 0x00000402 12202d756322SRob Clark 12212d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_1_HI 0x00000403 12222d756322SRob Clark 12232d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_2_LO 0x00000404 12242d756322SRob Clark 12252d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_2_HI 0x00000405 12262d756322SRob Clark 12272d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_3_LO 0x00000406 12282d756322SRob Clark 12292d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_3_HI 0x00000407 12302d756322SRob Clark 12312d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_4_LO 0x00000408 12322d756322SRob Clark 12332d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_4_HI 0x00000409 12342d756322SRob Clark 12352d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_5_LO 0x0000040a 12362d756322SRob Clark 12372d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_5_HI 0x0000040b 12382d756322SRob Clark 12392d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_6_LO 0x0000040c 12402d756322SRob Clark 12412d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_6_HI 0x0000040d 12422d756322SRob Clark 12432d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_7_LO 0x0000040e 12442d756322SRob Clark 12452d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_7_HI 0x0000040f 12462d756322SRob Clark 12472d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_8_LO 0x00000410 12482d756322SRob Clark 12492d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_8_HI 0x00000411 12502d756322SRob Clark 12512d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_9_LO 0x00000412 12522d756322SRob Clark 12532d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_9_HI 0x00000413 12542d756322SRob Clark 12552d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_10_LO 0x00000414 12562d756322SRob Clark 12572d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_10_HI 0x00000415 12582d756322SRob Clark 12592d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_11_LO 0x00000416 12602d756322SRob Clark 12612d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_11_HI 0x00000417 12622d756322SRob Clark 12632d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_12_LO 0x00000418 12642d756322SRob Clark 12652d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_12_HI 0x00000419 12662d756322SRob Clark 12672d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_13_LO 0x0000041a 12682d756322SRob Clark 12692d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_13_HI 0x0000041b 12702d756322SRob Clark 12712d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_0_LO 0x0000041c 12722d756322SRob Clark 12732d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_0_HI 0x0000041d 12742d756322SRob Clark 12752d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_1_LO 0x0000041e 12762d756322SRob Clark 12772d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_1_HI 0x0000041f 12782d756322SRob Clark 12792d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_2_LO 0x00000420 12802d756322SRob Clark 12812d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_2_HI 0x00000421 12822d756322SRob Clark 12832d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_3_LO 0x00000422 12842d756322SRob Clark 12852d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_3_HI 0x00000423 12862d756322SRob Clark 12872d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_0_LO 0x00000424 12882d756322SRob Clark 12892d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_0_HI 0x00000425 12902d756322SRob Clark 12912d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_1_LO 0x00000426 12922d756322SRob Clark 12932d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_1_HI 0x00000427 12942d756322SRob Clark 12952d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_2_LO 0x00000428 12962d756322SRob Clark 12972d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_2_HI 0x00000429 12982d756322SRob Clark 12992d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_3_LO 0x0000042a 13002d756322SRob Clark 13012d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_3_HI 0x0000042b 13022d756322SRob Clark 13032d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_4_LO 0x0000042c 13042d756322SRob Clark 13052d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_4_HI 0x0000042d 13062d756322SRob Clark 13072d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_5_LO 0x0000042e 13082d756322SRob Clark 13092d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_5_HI 0x0000042f 13102d756322SRob Clark 13112d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_6_LO 0x00000430 13122d756322SRob Clark 13132d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_6_HI 0x00000431 13142d756322SRob Clark 13152d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_7_LO 0x00000432 13162d756322SRob Clark 13172d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_7_HI 0x00000433 13182d756322SRob Clark 13192d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_0_LO 0x00000434 13202d756322SRob Clark 13212d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_0_HI 0x00000435 13222d756322SRob Clark 13232d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_1_LO 0x00000436 13242d756322SRob Clark 13252d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_1_HI 0x00000437 13262d756322SRob Clark 13272d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_2_LO 0x00000438 13282d756322SRob Clark 13292d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_2_HI 0x00000439 13302d756322SRob Clark 13312d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_3_LO 0x0000043a 13322d756322SRob Clark 13332d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_3_HI 0x0000043b 13342d756322SRob Clark 13352d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_4_LO 0x0000043c 13362d756322SRob Clark 13372d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_4_HI 0x0000043d 13382d756322SRob Clark 13392d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_5_LO 0x0000043e 13402d756322SRob Clark 13412d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_5_HI 0x0000043f 13422d756322SRob Clark 13432d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_6_LO 0x00000440 13442d756322SRob Clark 13452d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_6_HI 0x00000441 13462d756322SRob Clark 13472d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_7_LO 0x00000442 13482d756322SRob Clark 13492d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_7_HI 0x00000443 13502d756322SRob Clark 13512d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_0_LO 0x00000444 13522d756322SRob Clark 13532d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_0_HI 0x00000445 13542d756322SRob Clark 13552d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_1_LO 0x00000446 13562d756322SRob Clark 13572d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_1_HI 0x00000447 13582d756322SRob Clark 13592d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_2_LO 0x00000448 13602d756322SRob Clark 13612d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_2_HI 0x00000449 13622d756322SRob Clark 13632d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_3_LO 0x0000044a 13642d756322SRob Clark 13652d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_3_HI 0x0000044b 13662d756322SRob Clark 13672d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_4_LO 0x0000044c 13682d756322SRob Clark 13692d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_4_HI 0x0000044d 13702d756322SRob Clark 13712d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_5_LO 0x0000044e 13722d756322SRob Clark 13732d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_5_HI 0x0000044f 13742d756322SRob Clark 13752d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_0_LO 0x00000450 13762d756322SRob Clark 13772d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_0_HI 0x00000451 13782d756322SRob Clark 13792d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_1_LO 0x00000452 13802d756322SRob Clark 13812d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_1_HI 0x00000453 13822d756322SRob Clark 13832d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_2_LO 0x00000454 13842d756322SRob Clark 13852d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_2_HI 0x00000455 13862d756322SRob Clark 13872d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_3_LO 0x00000456 13882d756322SRob Clark 13892d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_3_HI 0x00000457 13902d756322SRob Clark 13912d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_4_LO 0x00000458 13922d756322SRob Clark 13932d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_4_HI 0x00000459 13942d756322SRob Clark 13952d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_5_LO 0x0000045a 13962d756322SRob Clark 13972d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_5_HI 0x0000045b 13982d756322SRob Clark 13992d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_0_LO 0x0000045c 14002d756322SRob Clark 14012d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_0_HI 0x0000045d 14022d756322SRob Clark 14032d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_1_LO 0x0000045e 14042d756322SRob Clark 14052d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_1_HI 0x0000045f 14062d756322SRob Clark 14072d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_2_LO 0x00000460 14082d756322SRob Clark 14092d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_2_HI 0x00000461 14102d756322SRob Clark 14112d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_3_LO 0x00000462 14122d756322SRob Clark 14132d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_3_HI 0x00000463 14142d756322SRob Clark 14152d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_4_LO 0x00000464 14162d756322SRob Clark 14172d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_4_HI 0x00000465 14182d756322SRob Clark 14192d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_0_LO 0x00000466 14202d756322SRob Clark 14212d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_0_HI 0x00000467 14222d756322SRob Clark 14232d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_1_LO 0x00000468 14242d756322SRob Clark 14252d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_1_HI 0x00000469 14262d756322SRob Clark 14272d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_2_LO 0x0000046a 14282d756322SRob Clark 14292d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_4_HI 0x00000465 14302d756322SRob Clark 14312d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_0_LO 0x00000466 14322d756322SRob Clark 14332d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_0_HI 0x00000467 14342d756322SRob Clark 14352d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_1_LO 0x00000468 14362d756322SRob Clark 14372d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_1_HI 0x00000469 14382d756322SRob Clark 14392d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_2_LO 0x0000046a 14402d756322SRob Clark 14412d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_2_HI 0x0000046b 14422d756322SRob Clark 14432d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_3_LO 0x0000046c 14442d756322SRob Clark 14452d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_3_HI 0x0000046d 14462d756322SRob Clark 14472d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RAS_0_LO 0x0000046e 14482d756322SRob Clark 14492d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RAS_0_HI 0x0000046f 14502d756322SRob Clark 14512d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RAS_1_LO 0x00000470 14522d756322SRob Clark 14532d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RAS_1_HI 0x00000471 14542d756322SRob Clark 14552d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RAS_2_LO 0x00000472 14562d756322SRob Clark 14572d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RAS_2_HI 0x00000473 14582d756322SRob Clark 14592d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RAS_3_LO 0x00000474 14602d756322SRob Clark 14612d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RAS_3_HI 0x00000475 14622d756322SRob Clark 14632d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_0_LO 0x00000476 14642d756322SRob Clark 14652d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_0_HI 0x00000477 14662d756322SRob Clark 14672d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_1_LO 0x00000478 14682d756322SRob Clark 14692d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_1_HI 0x00000479 14702d756322SRob Clark 14712d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_2_LO 0x0000047a 14722d756322SRob Clark 14732d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_2_HI 0x0000047b 14742d756322SRob Clark 14752d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_3_LO 0x0000047c 14762d756322SRob Clark 14772d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_3_HI 0x0000047d 14782d756322SRob Clark 14792d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_4_LO 0x0000047e 14802d756322SRob Clark 14812d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_4_HI 0x0000047f 14822d756322SRob Clark 14832d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_5_LO 0x00000480 14842d756322SRob Clark 14852d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_5_HI 0x00000481 14862d756322SRob Clark 14872d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_6_LO 0x00000482 14882d756322SRob Clark 14892d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_6_HI 0x00000483 14902d756322SRob Clark 14912d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_7_LO 0x00000484 14922d756322SRob Clark 14932d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_7_HI 0x00000485 14942d756322SRob Clark 14952d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_8_LO 0x00000486 14962d756322SRob Clark 14972d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_8_HI 0x00000487 14982d756322SRob Clark 14992d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_9_LO 0x00000488 15002d756322SRob Clark 15012d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_9_HI 0x00000489 15022d756322SRob Clark 15032d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_10_LO 0x0000048a 15042d756322SRob Clark 15052d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_10_HI 0x0000048b 15062d756322SRob Clark 15072d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_11_LO 0x0000048c 15082d756322SRob Clark 15092d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_11_HI 0x0000048d 15102d756322SRob Clark 15112d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_0_LO 0x0000048e 15122d756322SRob Clark 15132d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_0_HI 0x0000048f 15142d756322SRob Clark 15152d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_1_LO 0x00000490 15162d756322SRob Clark 15172d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_1_HI 0x00000491 15182d756322SRob Clark 15192d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_2_LO 0x00000492 15202d756322SRob Clark 15212d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_2_HI 0x00000493 15222d756322SRob Clark 15232d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_3_LO 0x00000494 15242d756322SRob Clark 15252d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_3_HI 0x00000495 15262d756322SRob Clark 15272d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_4_LO 0x00000496 15282d756322SRob Clark 15292d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_4_HI 0x00000497 15302d756322SRob Clark 15312d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_5_LO 0x00000498 15322d756322SRob Clark 15332d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_5_HI 0x00000499 15342d756322SRob Clark 15352d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_6_LO 0x0000049a 15362d756322SRob Clark 15372d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_6_HI 0x0000049b 15382d756322SRob Clark 15392d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_7_LO 0x0000049c 15402d756322SRob Clark 15412d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_7_HI 0x0000049d 15422d756322SRob Clark 15432d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_8_LO 0x0000049e 15442d756322SRob Clark 15452d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_8_HI 0x0000049f 15462d756322SRob Clark 15472d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_9_LO 0x000004a0 15482d756322SRob Clark 15492d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_9_HI 0x000004a1 15502d756322SRob Clark 15512d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_10_LO 0x000004a2 15522d756322SRob Clark 15532d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_10_HI 0x000004a3 15542d756322SRob Clark 15552d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_11_LO 0x000004a4 15562d756322SRob Clark 15572d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_11_HI 0x000004a5 15582d756322SRob Clark 15592d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_0_LO 0x000004a6 15602d756322SRob Clark 15612d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_0_HI 0x000004a7 15622d756322SRob Clark 15632d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_1_LO 0x000004a8 15642d756322SRob Clark 15652d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_1_HI 0x000004a9 15662d756322SRob Clark 15672d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_2_LO 0x000004aa 15682d756322SRob Clark 15692d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_2_HI 0x000004ab 15702d756322SRob Clark 15712d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_3_LO 0x000004ac 15722d756322SRob Clark 15732d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_3_HI 0x000004ad 15742d756322SRob Clark 15752d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_4_LO 0x000004ae 15762d756322SRob Clark 15772d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_4_HI 0x000004af 15782d756322SRob Clark 15792d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_5_LO 0x000004b0 15802d756322SRob Clark 15812d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_5_HI 0x000004b1 15822d756322SRob Clark 15832d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_6_LO 0x000004b2 15842d756322SRob Clark 15852d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_6_HI 0x000004b3 15862d756322SRob Clark 15872d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_7_LO 0x000004b4 15882d756322SRob Clark 15892d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_7_HI 0x000004b5 15902d756322SRob Clark 15912d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_8_LO 0x000004b6 15922d756322SRob Clark 15932d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_8_HI 0x000004b7 15942d756322SRob Clark 15952d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_9_LO 0x000004b8 15962d756322SRob Clark 15972d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_9_HI 0x000004b9 15982d756322SRob Clark 15992d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_10_LO 0x000004ba 16002d756322SRob Clark 16012d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_10_HI 0x000004bb 16022d756322SRob Clark 16032d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_11_LO 0x000004bc 16042d756322SRob Clark 16052d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_11_HI 0x000004bd 16062d756322SRob Clark 16072d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_12_LO 0x000004be 16082d756322SRob Clark 16092d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_12_HI 0x000004bf 16102d756322SRob Clark 16112d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_13_LO 0x000004c0 16122d756322SRob Clark 16132d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_13_HI 0x000004c1 16142d756322SRob Clark 16152d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_14_LO 0x000004c2 16162d756322SRob Clark 16172d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_14_HI 0x000004c3 16182d756322SRob Clark 16192d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_15_LO 0x000004c4 16202d756322SRob Clark 16212d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_15_HI 0x000004c5 16222d756322SRob Clark 16232d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_16_LO 0x000004c6 16242d756322SRob Clark 16252d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_16_HI 0x000004c7 16262d756322SRob Clark 16272d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_17_LO 0x000004c8 16282d756322SRob Clark 16292d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_17_HI 0x000004c9 16302d756322SRob Clark 16312d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_18_LO 0x000004ca 16322d756322SRob Clark 16332d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_18_HI 0x000004cb 16342d756322SRob Clark 16352d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_19_LO 0x000004cc 16362d756322SRob Clark 16372d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_19_HI 0x000004cd 16382d756322SRob Clark 16392d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_20_LO 0x000004ce 16402d756322SRob Clark 16412d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_20_HI 0x000004cf 16422d756322SRob Clark 16432d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_21_LO 0x000004d0 16442d756322SRob Clark 16452d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_21_HI 0x000004d1 16462d756322SRob Clark 16472d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_22_LO 0x000004d2 16482d756322SRob Clark 16492d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_22_HI 0x000004d3 16502d756322SRob Clark 16512d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_23_LO 0x000004d4 16522d756322SRob Clark 16532d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_23_HI 0x000004d5 16542d756322SRob Clark 16552d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_0_LO 0x000004d6 16562d756322SRob Clark 16572d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_0_HI 0x000004d7 16582d756322SRob Clark 16592d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_1_LO 0x000004d8 16602d756322SRob Clark 16612d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_1_HI 0x000004d9 16622d756322SRob Clark 16632d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_2_LO 0x000004da 16642d756322SRob Clark 16652d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_2_HI 0x000004db 16662d756322SRob Clark 16672d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_3_LO 0x000004dc 16682d756322SRob Clark 16692d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_3_HI 0x000004dd 16702d756322SRob Clark 16712d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_4_LO 0x000004de 16722d756322SRob Clark 16732d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_4_HI 0x000004df 16742d756322SRob Clark 16752d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_5_LO 0x000004e0 16762d756322SRob Clark 16772d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_5_HI 0x000004e1 16782d756322SRob Clark 16792d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_6_LO 0x000004e2 16802d756322SRob Clark 16812d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_6_HI 0x000004e3 16822d756322SRob Clark 16832d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_7_LO 0x000004e4 16842d756322SRob Clark 16852d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_7_HI 0x000004e5 16862d756322SRob Clark 16872d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VSC_0_LO 0x000004e6 16882d756322SRob Clark 16892d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VSC_0_HI 0x000004e7 16902d756322SRob Clark 16912d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VSC_1_LO 0x000004e8 16922d756322SRob Clark 16932d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VSC_1_HI 0x000004e9 16942d756322SRob Clark 16952d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LRZ_0_LO 0x000004ea 16962d756322SRob Clark 16972d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LRZ_0_HI 0x000004eb 16982d756322SRob Clark 16992d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LRZ_1_LO 0x000004ec 17002d756322SRob Clark 17012d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LRZ_1_HI 0x000004ed 17022d756322SRob Clark 17032d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LRZ_2_LO 0x000004ee 17042d756322SRob Clark 17052d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LRZ_2_HI 0x000004ef 17062d756322SRob Clark 17072d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LRZ_3_LO 0x000004f0 17082d756322SRob Clark 17092d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LRZ_3_HI 0x000004f1 17102d756322SRob Clark 17112d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CMP_0_LO 0x000004f2 17122d756322SRob Clark 17132d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CMP_0_HI 0x000004f3 17142d756322SRob Clark 17152d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CMP_1_LO 0x000004f4 17162d756322SRob Clark 17172d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CMP_1_HI 0x000004f5 17182d756322SRob Clark 17192d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CMP_2_LO 0x000004f6 17202d756322SRob Clark 17212d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CMP_2_HI 0x000004f7 17222d756322SRob Clark 17232d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CMP_3_LO 0x000004f8 17242d756322SRob Clark 17252d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CMP_3_HI 0x000004f9 17262d756322SRob Clark 17272d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500 17282d756322SRob Clark 17292d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 0x00000501 17302d756322SRob Clark 17312d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 0x00000502 17322d756322SRob Clark 17332d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 0x00000503 17342d756322SRob Clark 17352d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 0x00000504 17362d756322SRob Clark 17372d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000505 17382d756322SRob Clark 17392d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506 17402d756322SRob Clark 17412d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000507 17422d756322SRob Clark 17432d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000508 17442d756322SRob Clark 17452d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000509 17462d756322SRob Clark 17472d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000050a 17482d756322SRob Clark 17492d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b 17502d756322SRob Clark 17512d756322SRob Clark #define REG_A6XX_RBBM_ISDB_CNT 0x00000533 17522d756322SRob Clark 17532d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TRUST_CNTL 0x0000f400 17542d756322SRob Clark 17552d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800 17562d756322SRob Clark 17572d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801 17582d756322SRob Clark 17592d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802 17602d756322SRob Clark 17612d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_CNTL 0x0000f803 17622d756322SRob Clark 17632d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810 17642d756322SRob Clark 17652d756322SRob Clark #define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL 0x00000010 17662d756322SRob Clark 17672d756322SRob Clark #define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000001f 17682d756322SRob Clark 17692d756322SRob Clark #define REG_A6XX_RBBM_INT_CLEAR_CMD 0x00000037 17702d756322SRob Clark 17712d756322SRob Clark #define REG_A6XX_RBBM_INT_0_MASK 0x00000038 17722d756322SRob Clark 17732d756322SRob Clark #define REG_A6XX_RBBM_SP_HYST_CNT 0x00000042 17742d756322SRob Clark 17752d756322SRob Clark #define REG_A6XX_RBBM_SW_RESET_CMD 0x00000043 17762d756322SRob Clark 17772d756322SRob Clark #define REG_A6XX_RBBM_RAC_THRESHOLD_CNT 0x00000044 17782d756322SRob Clark 17792d756322SRob Clark #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 17802d756322SRob Clark 17812d756322SRob Clark #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046 17822d756322SRob Clark 17832d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae 17842d756322SRob Clark 17852d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0 17862d756322SRob Clark 17872d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_SP1 0x000000b1 17882d756322SRob Clark 17892d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_SP2 0x000000b2 17902d756322SRob Clark 17912d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_SP3 0x000000b3 17922d756322SRob Clark 17932d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_SP0 0x000000b4 17942d756322SRob Clark 17952d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_SP1 0x000000b5 17962d756322SRob Clark 17972d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_SP2 0x000000b6 17982d756322SRob Clark 17992d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_SP3 0x000000b7 18002d756322SRob Clark 18012d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_SP0 0x000000b8 18022d756322SRob Clark 18032d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_SP1 0x000000b9 18042d756322SRob Clark 18052d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_SP2 0x000000ba 18062d756322SRob Clark 18072d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_SP3 0x000000bb 18082d756322SRob Clark 18092d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_SP0 0x000000bc 18102d756322SRob Clark 18112d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_SP1 0x000000bd 18122d756322SRob Clark 18132d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_SP2 0x000000be 18142d756322SRob Clark 18152d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_SP3 0x000000bf 18162d756322SRob Clark 18172d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TP0 0x000000c0 18182d756322SRob Clark 18192d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TP1 0x000000c1 18202d756322SRob Clark 18212d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TP2 0x000000c2 18222d756322SRob Clark 18232d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TP3 0x000000c3 18242d756322SRob Clark 18252d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_TP0 0x000000c4 18262d756322SRob Clark 18272d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_TP1 0x000000c5 18282d756322SRob Clark 18292d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_TP2 0x000000c6 18302d756322SRob Clark 18312d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_TP3 0x000000c7 18322d756322SRob Clark 18332d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_TP0 0x000000c8 18342d756322SRob Clark 18352d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_TP1 0x000000c9 18362d756322SRob Clark 18372d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_TP2 0x000000ca 18382d756322SRob Clark 18392d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_TP3 0x000000cb 18402d756322SRob Clark 18412d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_TP0 0x000000cc 18422d756322SRob Clark 18432d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_TP1 0x000000cd 18442d756322SRob Clark 18452d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_TP2 0x000000ce 18462d756322SRob Clark 18472d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_TP3 0x000000cf 18482d756322SRob Clark 18492d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TP0 0x000000d0 18502d756322SRob Clark 18512d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TP1 0x000000d1 18522d756322SRob Clark 18532d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TP2 0x000000d2 18542d756322SRob Clark 18552d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TP3 0x000000d3 18562d756322SRob Clark 18572d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY2_TP0 0x000000d4 18582d756322SRob Clark 18592d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY2_TP1 0x000000d5 18602d756322SRob Clark 18612d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY2_TP2 0x000000d6 18622d756322SRob Clark 18632d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY2_TP3 0x000000d7 18642d756322SRob Clark 18652d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY3_TP0 0x000000d8 18662d756322SRob Clark 18672d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY3_TP1 0x000000d9 18682d756322SRob Clark 18692d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY3_TP2 0x000000da 18702d756322SRob Clark 18712d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY3_TP3 0x000000db 18722d756322SRob Clark 18732d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY4_TP0 0x000000dc 18742d756322SRob Clark 18752d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY4_TP1 0x000000dd 18762d756322SRob Clark 18772d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY4_TP2 0x000000de 18782d756322SRob Clark 18792d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY4_TP3 0x000000df 18802d756322SRob Clark 18812d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TP0 0x000000e0 18822d756322SRob Clark 18832d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TP1 0x000000e1 18842d756322SRob Clark 18852d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TP2 0x000000e2 18862d756322SRob Clark 18872d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TP3 0x000000e3 18882d756322SRob Clark 18892d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST2_TP0 0x000000e4 18902d756322SRob Clark 18912d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST2_TP1 0x000000e5 18922d756322SRob Clark 18932d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST2_TP2 0x000000e6 18942d756322SRob Clark 18952d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST2_TP3 0x000000e7 18962d756322SRob Clark 18972d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST3_TP0 0x000000e8 18982d756322SRob Clark 18992d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST3_TP1 0x000000e9 19002d756322SRob Clark 19012d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST3_TP2 0x000000ea 19022d756322SRob Clark 19032d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST3_TP3 0x000000eb 19042d756322SRob Clark 19052d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST4_TP0 0x000000ec 19062d756322SRob Clark 19072d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST4_TP1 0x000000ed 19082d756322SRob Clark 19092d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST4_TP2 0x000000ee 19102d756322SRob Clark 19112d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST4_TP3 0x000000ef 19122d756322SRob Clark 19132d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RB0 0x000000f0 19142d756322SRob Clark 19152d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RB1 0x000000f1 19162d756322SRob Clark 19172d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RB2 0x000000f2 19182d756322SRob Clark 19192d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RB3 0x000000f3 19202d756322SRob Clark 19212d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RB0 0x000000f4 19222d756322SRob Clark 19232d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RB1 0x000000f5 19242d756322SRob Clark 19252d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RB2 0x000000f6 19262d756322SRob Clark 19272d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RB3 0x000000f7 19282d756322SRob Clark 19292d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_CCU0 0x000000f8 19302d756322SRob Clark 19312d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_CCU1 0x000000f9 19322d756322SRob Clark 19332d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_CCU2 0x000000fa 19342d756322SRob Clark 19352d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_CCU3 0x000000fb 19362d756322SRob Clark 19372d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000100 19382d756322SRob Clark 19392d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000101 19402d756322SRob Clark 19412d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000102 19422d756322SRob Clark 19432d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000103 19442d756322SRob Clark 19452d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RAC 0x00000104 19462d756322SRob Clark 19472d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RAC 0x00000105 19482d756322SRob Clark 19492d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_RAC 0x00000106 19502d756322SRob Clark 19512d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RAC 0x00000107 19522d756322SRob Clark 19532d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000108 19542d756322SRob Clark 19552d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000109 19562d756322SRob Clark 19572d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000010a 19582d756322SRob Clark 19592d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_UCHE 0x0000010b 19602d756322SRob Clark 19612d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE 0x0000010c 19622d756322SRob Clark 19632d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE 0x0000010d 19642d756322SRob Clark 19652d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE 0x0000010e 19662d756322SRob Clark 19672d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_UCHE 0x0000010f 19682d756322SRob Clark 19692d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_UCHE 0x00000110 19702d756322SRob Clark 19712d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_MODE_VFD 0x00000111 19722d756322SRob Clark 19732d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_VFD 0x00000112 19742d756322SRob Clark 19752d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_VFD 0x00000113 19762d756322SRob Clark 19772d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_MODE_GPC 0x00000114 19782d756322SRob Clark 19792d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_GPC 0x00000115 19802d756322SRob Clark 19812d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_GPC 0x00000116 19822d756322SRob Clark 19832d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2 0x00000117 19842d756322SRob Clark 19852d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX 0x00000118 19862d756322SRob Clark 19872d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX 0x00000119 19882d756322SRob Clark 19892d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX 0x0000011a 19902d756322SRob Clark 19912d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_MODE_HLSQ 0x0000011b 19922d756322SRob Clark 19932d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ 0x0000011c 19942d756322SRob Clark 19952d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A 0x00000600 19962d756322SRob Clark 19972d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B 0x00000601 19982d756322SRob Clark 19992d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C 0x00000602 20002d756322SRob Clark 20012d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D 0x00000603 20022d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK 0x000000ff 20032d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT 0 20042d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val) 20052d756322SRob Clark { 20062d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK; 20072d756322SRob Clark } 20082d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK 0x0000ff00 20092d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT 8 20102d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val) 20112d756322SRob Clark { 20122d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK; 20132d756322SRob Clark } 20142d756322SRob Clark 20152d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT 0x00000604 20162d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f 20172d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0 20182d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) 20192d756322SRob Clark { 20202d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; 20212d756322SRob Clark } 20222d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000 20232d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12 20242d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) 20252d756322SRob Clark { 20262d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; 20272d756322SRob Clark } 20282d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000 20292d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28 20302d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) 20312d756322SRob Clark { 20322d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; 20332d756322SRob Clark } 20342d756322SRob Clark 20352d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM 0x00000605 20362d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000 20372d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24 20382d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) 20392d756322SRob Clark { 20402d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; 20412d756322SRob Clark } 20422d756322SRob Clark 20432d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 0x00000608 20442d756322SRob Clark 20452d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 0x00000609 20462d756322SRob Clark 20472d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 0x0000060a 20482d756322SRob Clark 20492d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 0x0000060b 20502d756322SRob Clark 20512d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 0x0000060c 20522d756322SRob Clark 20532d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 0x0000060d 20542d756322SRob Clark 20552d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 0x0000060e 20562d756322SRob Clark 20572d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 0x0000060f 20582d756322SRob Clark 20592d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000610 20602d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f 20612d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0 20622d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) 20632d756322SRob Clark { 20642d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; 20652d756322SRob Clark } 20662d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0 20672d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4 20682d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) 20692d756322SRob Clark { 20702d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; 20712d756322SRob Clark } 20722d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00 20732d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8 20742d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) 20752d756322SRob Clark { 20762d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; 20772d756322SRob Clark } 20782d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000 20792d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12 20802d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) 20812d756322SRob Clark { 20822d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; 20832d756322SRob Clark } 20842d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000 20852d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16 20862d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) 20872d756322SRob Clark { 20882d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; 20892d756322SRob Clark } 20902d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000 20912d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20 20922d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) 20932d756322SRob Clark { 20942d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; 20952d756322SRob Clark } 20962d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000 20972d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24 20982d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) 20992d756322SRob Clark { 21002d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; 21012d756322SRob Clark } 21022d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000 21032d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28 21042d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) 21052d756322SRob Clark { 21062d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; 21072d756322SRob Clark } 21082d756322SRob Clark 21092d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000611 21102d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f 21112d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0 21122d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) 21132d756322SRob Clark { 21142d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; 21152d756322SRob Clark } 21162d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0 21172d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4 21182d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) 21192d756322SRob Clark { 21202d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; 21212d756322SRob Clark } 21222d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00 21232d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8 21242d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) 21252d756322SRob Clark { 21262d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; 21272d756322SRob Clark } 21282d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000 21292d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12 21302d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) 21312d756322SRob Clark { 21322d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; 21332d756322SRob Clark } 21342d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000 21352d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16 21362d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) 21372d756322SRob Clark { 21382d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; 21392d756322SRob Clark } 21402d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000 21412d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20 21422d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) 21432d756322SRob Clark { 21442d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; 21452d756322SRob Clark } 21462d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000 21472d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24 21482d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) 21492d756322SRob Clark { 21502d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; 21512d756322SRob Clark } 21522d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000 21532d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28 21542d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) 21552d756322SRob Clark { 21562d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; 21572d756322SRob Clark } 21582d756322SRob Clark 21592d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000062f 21602d756322SRob Clark 21612d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630 21622d756322SRob Clark 21632d756322SRob Clark #define REG_A6XX_VSC_PERFCTR_VSC_SEL_0 0x00000cd8 21642d756322SRob Clark 21652d756322SRob Clark #define REG_A6XX_VSC_PERFCTR_VSC_SEL_1 0x00000cd9 21662d756322SRob Clark 21672d756322SRob Clark #define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601 21682d756322SRob Clark 21692d756322SRob Clark #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_0 0x00008610 21702d756322SRob Clark 21712d756322SRob Clark #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_1 0x00008611 21722d756322SRob Clark 21732d756322SRob Clark #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_2 0x00008612 21742d756322SRob Clark 21752d756322SRob Clark #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_3 0x00008613 21762d756322SRob Clark 21772d756322SRob Clark #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_0 0x00008614 21782d756322SRob Clark 21792d756322SRob Clark #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_1 0x00008615 21802d756322SRob Clark 21812d756322SRob Clark #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_2 0x00008616 21822d756322SRob Clark 21832d756322SRob Clark #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_3 0x00008617 21842d756322SRob Clark 21852d756322SRob Clark #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_0 0x00008618 21862d756322SRob Clark 21872d756322SRob Clark #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_1 0x00008619 21882d756322SRob Clark 21892d756322SRob Clark #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_2 0x0000861a 21902d756322SRob Clark 21912d756322SRob Clark #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_3 0x0000861b 21922d756322SRob Clark 21932d756322SRob Clark #define REG_A6XX_RB_ADDR_MODE_CNTL 0x00008e05 21942d756322SRob Clark 21952d756322SRob Clark #define REG_A6XX_RB_NC_MODE_CNTL 0x00008e08 21962d756322SRob Clark 21972d756322SRob Clark #define REG_A6XX_RB_PERFCTR_RB_SEL_0 0x00008e10 21982d756322SRob Clark 21992d756322SRob Clark #define REG_A6XX_RB_PERFCTR_RB_SEL_1 0x00008e11 22002d756322SRob Clark 22012d756322SRob Clark #define REG_A6XX_RB_PERFCTR_RB_SEL_2 0x00008e12 22022d756322SRob Clark 22032d756322SRob Clark #define REG_A6XX_RB_PERFCTR_RB_SEL_3 0x00008e13 22042d756322SRob Clark 22052d756322SRob Clark #define REG_A6XX_RB_PERFCTR_RB_SEL_4 0x00008e14 22062d756322SRob Clark 22072d756322SRob Clark #define REG_A6XX_RB_PERFCTR_RB_SEL_5 0x00008e15 22082d756322SRob Clark 22092d756322SRob Clark #define REG_A6XX_RB_PERFCTR_RB_SEL_6 0x00008e16 22102d756322SRob Clark 22112d756322SRob Clark #define REG_A6XX_RB_PERFCTR_RB_SEL_7 0x00008e17 22122d756322SRob Clark 22132d756322SRob Clark #define REG_A6XX_RB_PERFCTR_CCU_SEL_0 0x00008e18 22142d756322SRob Clark 22152d756322SRob Clark #define REG_A6XX_RB_PERFCTR_CCU_SEL_1 0x00008e19 22162d756322SRob Clark 22172d756322SRob Clark #define REG_A6XX_RB_PERFCTR_CCU_SEL_2 0x00008e1a 22182d756322SRob Clark 22192d756322SRob Clark #define REG_A6XX_RB_PERFCTR_CCU_SEL_3 0x00008e1b 22202d756322SRob Clark 22212d756322SRob Clark #define REG_A6XX_RB_PERFCTR_CCU_SEL_4 0x00008e1c 22222d756322SRob Clark 22232d756322SRob Clark #define REG_A6XX_RB_PERFCTR_CMP_SEL_0 0x00008e2c 22242d756322SRob Clark 22252d756322SRob Clark #define REG_A6XX_RB_PERFCTR_CMP_SEL_1 0x00008e2d 22262d756322SRob Clark 22272d756322SRob Clark #define REG_A6XX_RB_PERFCTR_CMP_SEL_2 0x00008e2e 22282d756322SRob Clark 22292d756322SRob Clark #define REG_A6XX_RB_PERFCTR_CMP_SEL_3 0x00008e2f 22302d756322SRob Clark 22312d756322SRob Clark #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD 0x00008e3d 22322d756322SRob Clark 22332d756322SRob Clark #define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x00008e50 22342d756322SRob Clark 22352d756322SRob Clark #define REG_A6XX_PC_DBG_ECO_CNTL 0x00009e00 22362d756322SRob Clark 22372d756322SRob Clark #define REG_A6XX_PC_ADDR_MODE_CNTL 0x00009e01 22382d756322SRob Clark 22392d756322SRob Clark #define REG_A6XX_PC_PERFCTR_PC_SEL_0 0x00009e34 22402d756322SRob Clark 22412d756322SRob Clark #define REG_A6XX_PC_PERFCTR_PC_SEL_1 0x00009e35 22422d756322SRob Clark 22432d756322SRob Clark #define REG_A6XX_PC_PERFCTR_PC_SEL_2 0x00009e36 22442d756322SRob Clark 22452d756322SRob Clark #define REG_A6XX_PC_PERFCTR_PC_SEL_3 0x00009e37 22462d756322SRob Clark 22472d756322SRob Clark #define REG_A6XX_PC_PERFCTR_PC_SEL_4 0x00009e38 22482d756322SRob Clark 22492d756322SRob Clark #define REG_A6XX_PC_PERFCTR_PC_SEL_5 0x00009e39 22502d756322SRob Clark 22512d756322SRob Clark #define REG_A6XX_PC_PERFCTR_PC_SEL_6 0x00009e3a 22522d756322SRob Clark 22532d756322SRob Clark #define REG_A6XX_PC_PERFCTR_PC_SEL_7 0x00009e3b 22542d756322SRob Clark 22552d756322SRob Clark #define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05 22562d756322SRob Clark 22572d756322SRob Clark #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x0000be10 22582d756322SRob Clark 22592d756322SRob Clark #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x0000be11 22602d756322SRob Clark 22612d756322SRob Clark #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x0000be12 22622d756322SRob Clark 22632d756322SRob Clark #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x0000be13 22642d756322SRob Clark 22652d756322SRob Clark #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x0000be14 22662d756322SRob Clark 22672d756322SRob Clark #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x0000be15 22682d756322SRob Clark 22692d756322SRob Clark #define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800 22702d756322SRob Clark 22712d756322SRob Clark #define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000 22722d756322SRob Clark 22732d756322SRob Clark #define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601 22742d756322SRob Clark 22752d756322SRob Clark #define REG_A6XX_VFD_PERFCTR_VFD_SEL_0 0x0000a610 22762d756322SRob Clark 22772d756322SRob Clark #define REG_A6XX_VFD_PERFCTR_VFD_SEL_1 0x0000a611 22782d756322SRob Clark 22792d756322SRob Clark #define REG_A6XX_VFD_PERFCTR_VFD_SEL_2 0x0000a612 22802d756322SRob Clark 22812d756322SRob Clark #define REG_A6XX_VFD_PERFCTR_VFD_SEL_3 0x0000a613 22822d756322SRob Clark 22832d756322SRob Clark #define REG_A6XX_VFD_PERFCTR_VFD_SEL_4 0x0000a614 22842d756322SRob Clark 22852d756322SRob Clark #define REG_A6XX_VFD_PERFCTR_VFD_SEL_5 0x0000a615 22862d756322SRob Clark 22872d756322SRob Clark #define REG_A6XX_VFD_PERFCTR_VFD_SEL_6 0x0000a616 22882d756322SRob Clark 22892d756322SRob Clark #define REG_A6XX_VFD_PERFCTR_VFD_SEL_7 0x0000a617 22902d756322SRob Clark 22912d756322SRob Clark #define REG_A6XX_VPC_ADDR_MODE_CNTL 0x00009601 22922d756322SRob Clark 22932d756322SRob Clark #define REG_A6XX_VPC_PERFCTR_VPC_SEL_0 0x00009604 22942d756322SRob Clark 22952d756322SRob Clark #define REG_A6XX_VPC_PERFCTR_VPC_SEL_1 0x00009605 22962d756322SRob Clark 22972d756322SRob Clark #define REG_A6XX_VPC_PERFCTR_VPC_SEL_2 0x00009606 22982d756322SRob Clark 22992d756322SRob Clark #define REG_A6XX_VPC_PERFCTR_VPC_SEL_3 0x00009607 23002d756322SRob Clark 23012d756322SRob Clark #define REG_A6XX_VPC_PERFCTR_VPC_SEL_4 0x00009608 23022d756322SRob Clark 23032d756322SRob Clark #define REG_A6XX_VPC_PERFCTR_VPC_SEL_5 0x00009609 23042d756322SRob Clark 23052d756322SRob Clark #define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00 23062d756322SRob Clark 23072d756322SRob Clark #define REG_A6XX_UCHE_MODE_CNTL 0x00000e01 23082d756322SRob Clark 23092d756322SRob Clark #define REG_A6XX_UCHE_WRITE_RANGE_MAX_LO 0x00000e05 23102d756322SRob Clark 23112d756322SRob Clark #define REG_A6XX_UCHE_WRITE_RANGE_MAX_HI 0x00000e06 23122d756322SRob Clark 23132d756322SRob Clark #define REG_A6XX_UCHE_WRITE_THRU_BASE_LO 0x00000e07 23142d756322SRob Clark 23152d756322SRob Clark #define REG_A6XX_UCHE_WRITE_THRU_BASE_HI 0x00000e08 23162d756322SRob Clark 23172d756322SRob Clark #define REG_A6XX_UCHE_TRAP_BASE_LO 0x00000e09 23182d756322SRob Clark 23192d756322SRob Clark #define REG_A6XX_UCHE_TRAP_BASE_HI 0x00000e0a 23202d756322SRob Clark 23212d756322SRob Clark #define REG_A6XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e0b 23222d756322SRob Clark 23232d756322SRob Clark #define REG_A6XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e0c 23242d756322SRob Clark 23252d756322SRob Clark #define REG_A6XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e0d 23262d756322SRob Clark 23272d756322SRob Clark #define REG_A6XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e0e 23282d756322SRob Clark 23292d756322SRob Clark #define REG_A6XX_UCHE_CACHE_WAYS 0x00000e17 23302d756322SRob Clark 23312d756322SRob Clark #define REG_A6XX_UCHE_FILTER_CNTL 0x00000e18 23322d756322SRob Clark 23332d756322SRob Clark #define REG_A6XX_UCHE_CLIENT_PF 0x00000e19 23342d756322SRob Clark #define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK 0x000000ff 23352d756322SRob Clark #define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT 0 23362d756322SRob Clark static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val) 23372d756322SRob Clark { 23382d756322SRob Clark return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK; 23392d756322SRob Clark } 23402d756322SRob Clark 23412d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e1c 23422d756322SRob Clark 23432d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e1d 23442d756322SRob Clark 23452d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e1e 23462d756322SRob Clark 23472d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e1f 23482d756322SRob Clark 23492d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e20 23502d756322SRob Clark 23512d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e21 23522d756322SRob Clark 23532d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e22 23542d756322SRob Clark 23552d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e23 23562d756322SRob Clark 23572d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_8 0x00000e24 23582d756322SRob Clark 23592d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_9 0x00000e25 23602d756322SRob Clark 23612d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_10 0x00000e26 23622d756322SRob Clark 23632d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_11 0x00000e27 23642d756322SRob Clark 23652d756322SRob Clark #define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01 23662d756322SRob Clark 23672d756322SRob Clark #define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02 23682d756322SRob Clark 23692d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_0 0x0000ae10 23702d756322SRob Clark 23712d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_1 0x0000ae11 23722d756322SRob Clark 23732d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_2 0x0000ae12 23742d756322SRob Clark 23752d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_3 0x0000ae13 23762d756322SRob Clark 23772d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_4 0x0000ae14 23782d756322SRob Clark 23792d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_5 0x0000ae15 23802d756322SRob Clark 23812d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_6 0x0000ae16 23822d756322SRob Clark 23832d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_7 0x0000ae17 23842d756322SRob Clark 23852d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_8 0x0000ae18 23862d756322SRob Clark 23872d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_9 0x0000ae19 23882d756322SRob Clark 23892d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_10 0x0000ae1a 23902d756322SRob Clark 23912d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_11 0x0000ae1b 23922d756322SRob Clark 23932d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_12 0x0000ae1c 23942d756322SRob Clark 23952d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_13 0x0000ae1d 23962d756322SRob Clark 23972d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_14 0x0000ae1e 23982d756322SRob Clark 23992d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_15 0x0000ae1f 24002d756322SRob Clark 24012d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_16 0x0000ae20 24022d756322SRob Clark 24032d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_17 0x0000ae21 24042d756322SRob Clark 24052d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_18 0x0000ae22 24062d756322SRob Clark 24072d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_19 0x0000ae23 24082d756322SRob Clark 24092d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_20 0x0000ae24 24102d756322SRob Clark 24112d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_21 0x0000ae25 24122d756322SRob Clark 24132d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_22 0x0000ae26 24142d756322SRob Clark 24152d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_23 0x0000ae27 24162d756322SRob Clark 24172d756322SRob Clark #define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601 24182d756322SRob Clark 24192d756322SRob Clark #define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604 24202d756322SRob Clark 24212d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_0 0x0000b610 24222d756322SRob Clark 24232d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_1 0x0000b611 24242d756322SRob Clark 24252d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_2 0x0000b612 24262d756322SRob Clark 24272d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_3 0x0000b613 24282d756322SRob Clark 24292d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_4 0x0000b614 24302d756322SRob Clark 24312d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_5 0x0000b615 24322d756322SRob Clark 24332d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_6 0x0000b616 24342d756322SRob Clark 24352d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_7 0x0000b617 24362d756322SRob Clark 24372d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_8 0x0000b618 24382d756322SRob Clark 24392d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_9 0x0000b619 24402d756322SRob Clark 24412d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_10 0x0000b61a 24422d756322SRob Clark 24432d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_11 0x0000b61b 24442d756322SRob Clark 24452d756322SRob Clark #define REG_A6XX_VBIF_VERSION 0x00003000 24462d756322SRob Clark 2447a69c5ed2SRob Clark #define REG_A6XX_VBIF_CLKON 0x00003001 2448a69c5ed2SRob Clark #define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000002 2449a69c5ed2SRob Clark 24502d756322SRob Clark #define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 24512d756322SRob Clark 24522d756322SRob Clark #define REG_A6XX_VBIF_XIN_HALT_CTRL0 0x00003080 24532d756322SRob Clark 24542d756322SRob Clark #define REG_A6XX_VBIF_XIN_HALT_CTRL1 0x00003081 24552d756322SRob Clark 2456a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084 2457a69c5ed2SRob Clark 2458a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS1_CTRL0 0x00003085 2459a69c5ed2SRob Clark 2460a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS1_CTRL1 0x00003086 2461a69c5ed2SRob Clark #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK 0x0000000f 2462a69c5ed2SRob Clark #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT 0 2463a69c5ed2SRob Clark static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val) 2464a69c5ed2SRob Clark { 2465a69c5ed2SRob Clark return ((val) << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK; 2466a69c5ed2SRob Clark } 2467a69c5ed2SRob Clark 2468a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS2_CTRL0 0x00003087 2469a69c5ed2SRob Clark 2470a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS2_CTRL1 0x00003088 2471a69c5ed2SRob Clark #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK 0x000001ff 2472a69c5ed2SRob Clark #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT 0 2473a69c5ed2SRob Clark static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val) 2474a69c5ed2SRob Clark { 2475a69c5ed2SRob Clark return ((val) << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK; 2476a69c5ed2SRob Clark } 2477a69c5ed2SRob Clark 2478a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS_OUT 0x0000308c 2479a69c5ed2SRob Clark 24802d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_SEL0 0x000030d0 24812d756322SRob Clark 24822d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_SEL1 0x000030d1 24832d756322SRob Clark 24842d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_SEL2 0x000030d2 24852d756322SRob Clark 24862d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_SEL3 0x000030d3 24872d756322SRob Clark 24882d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_LOW0 0x000030d8 24892d756322SRob Clark 24902d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_LOW1 0x000030d9 24912d756322SRob Clark 24922d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_LOW2 0x000030da 24932d756322SRob Clark 24942d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_LOW3 0x000030db 24952d756322SRob Clark 24962d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_HIGH0 0x000030e0 24972d756322SRob Clark 24982d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_HIGH1 0x000030e1 24992d756322SRob Clark 25002d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_HIGH2 0x000030e2 25012d756322SRob Clark 25022d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_HIGH3 0x000030e3 25032d756322SRob Clark 25042d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_EN0 0x00003100 25052d756322SRob Clark 25062d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_EN1 0x00003101 25072d756322SRob Clark 25082d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_EN2 0x00003102 25092d756322SRob Clark 25102d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110 25112d756322SRob Clark 25122d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111 25132d756322SRob Clark 25142d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112 25152d756322SRob Clark 25162d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118 25172d756322SRob Clark 25182d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119 25192d756322SRob Clark 25202d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a 25212d756322SRob Clark 2522e812744cSSharat Masetty #define REG_A6XX_GBIF_SCACHE_CNTL1 0x00003c02 2523e812744cSSharat Masetty 2524e812744cSSharat Masetty #define REG_A6XX_GBIF_QSB_SIDE0 0x00003c03 2525e812744cSSharat Masetty 2526e812744cSSharat Masetty #define REG_A6XX_GBIF_QSB_SIDE1 0x00003c04 2527e812744cSSharat Masetty 2528e812744cSSharat Masetty #define REG_A6XX_GBIF_QSB_SIDE2 0x00003c05 2529e812744cSSharat Masetty 2530e812744cSSharat Masetty #define REG_A6XX_GBIF_QSB_SIDE3 0x00003c06 2531e812744cSSharat Masetty 2532e812744cSSharat Masetty #define REG_A6XX_GBIF_HALT 0x00003c45 2533e812744cSSharat Masetty 2534e812744cSSharat Masetty #define REG_A6XX_GBIF_HALT_ACK 0x00003c46 2535e812744cSSharat Masetty 2536e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_PWR_CNT_EN 0x00003cc0 2537e812744cSSharat Masetty 2538e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_SEL 0x00003cc2 2539e812744cSSharat Masetty 2540e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_PWR_CNT_SEL 0x00003cc3 2541e812744cSSharat Masetty 2542e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_LOW0 0x00003cc4 2543e812744cSSharat Masetty 2544e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_LOW1 0x00003cc5 2545e812744cSSharat Masetty 2546e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_LOW2 0x00003cc6 2547e812744cSSharat Masetty 2548e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_LOW3 0x00003cc7 2549e812744cSSharat Masetty 2550e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_HIGH0 0x00003cc8 2551e812744cSSharat Masetty 2552e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_HIGH1 0x00003cc9 2553e812744cSSharat Masetty 2554e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_HIGH2 0x00003cca 2555e812744cSSharat Masetty 2556e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_HIGH3 0x00003ccb 2557e812744cSSharat Masetty 2558e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_LOW0 0x00003ccc 2559e812744cSSharat Masetty 2560e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_LOW1 0x00003ccd 2561e812744cSSharat Masetty 2562e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_LOW2 0x00003cce 2563e812744cSSharat Masetty 2564e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_HIGH0 0x00003ccf 2565e812744cSSharat Masetty 2566e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_HIGH1 0x00003cd0 2567e812744cSSharat Masetty 2568e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_HIGH2 0x00003cd1 2569e812744cSSharat Masetty 2570a69c5ed2SRob Clark #define REG_A6XX_RB_WINDOW_OFFSET2 0x000088d4 2571a69c5ed2SRob Clark #define A6XX_RB_WINDOW_OFFSET2_WINDOW_OFFSET_DISABLE 0x80000000 2572a69c5ed2SRob Clark #define A6XX_RB_WINDOW_OFFSET2_X__MASK 0x00007fff 2573a69c5ed2SRob Clark #define A6XX_RB_WINDOW_OFFSET2_X__SHIFT 0 2574a69c5ed2SRob Clark static inline uint32_t A6XX_RB_WINDOW_OFFSET2_X(uint32_t val) 25752d756322SRob Clark { 2576a69c5ed2SRob Clark return ((val) << A6XX_RB_WINDOW_OFFSET2_X__SHIFT) & A6XX_RB_WINDOW_OFFSET2_X__MASK; 25772d756322SRob Clark } 2578a69c5ed2SRob Clark #define A6XX_RB_WINDOW_OFFSET2_Y__MASK 0x7fff0000 2579a69c5ed2SRob Clark #define A6XX_RB_WINDOW_OFFSET2_Y__SHIFT 16 2580a69c5ed2SRob Clark static inline uint32_t A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val) 25812d756322SRob Clark { 2582a69c5ed2SRob Clark return ((val) << A6XX_RB_WINDOW_OFFSET2_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET2_Y__MASK; 25832d756322SRob Clark } 25842d756322SRob Clark 2585a69c5ed2SRob Clark #define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1 2586a69c5ed2SRob Clark #define A6XX_SP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 2587a69c5ed2SRob Clark #define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00007fff 2588a69c5ed2SRob Clark #define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0 2589a69c5ed2SRob Clark static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val) 25902d756322SRob Clark { 2591a69c5ed2SRob Clark return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK; 25922d756322SRob Clark } 2593a69c5ed2SRob Clark #define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x7fff0000 2594a69c5ed2SRob Clark #define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16 2595a69c5ed2SRob Clark static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val) 25962d756322SRob Clark { 2597a69c5ed2SRob Clark return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK; 25982d756322SRob Clark } 25992d756322SRob Clark 2600a69c5ed2SRob Clark #define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307 2601a69c5ed2SRob Clark #define A6XX_SP_TP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 2602a69c5ed2SRob Clark #define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00007fff 2603a69c5ed2SRob Clark #define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0 2604a69c5ed2SRob Clark static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val) 26052d756322SRob Clark { 2606a69c5ed2SRob Clark return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK; 2607a69c5ed2SRob Clark } 2608a69c5ed2SRob Clark #define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x7fff0000 2609a69c5ed2SRob Clark #define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16 2610a69c5ed2SRob Clark static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val) 2611a69c5ed2SRob Clark { 2612a69c5ed2SRob Clark return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK; 26132d756322SRob Clark } 26142d756322SRob Clark 2615a69c5ed2SRob Clark #define REG_A6XX_GRAS_BIN_CONTROL 0x000080a1 2616a69c5ed2SRob Clark #define A6XX_GRAS_BIN_CONTROL_BINW__MASK 0x000000ff 2617a69c5ed2SRob Clark #define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT 0 2618a69c5ed2SRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val) 26192d756322SRob Clark { 2620a69c5ed2SRob Clark return ((val >> 5) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK; 26212d756322SRob Clark } 2622a69c5ed2SRob Clark #define A6XX_GRAS_BIN_CONTROL_BINH__MASK 0x0001ff00 2623a69c5ed2SRob Clark #define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT 8 2624a69c5ed2SRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val) 26252d756322SRob Clark { 2626a69c5ed2SRob Clark return ((val >> 4) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK; 26272d756322SRob Clark } 2628a69c5ed2SRob Clark #define A6XX_GRAS_BIN_CONTROL_BINNING_PASS 0x00040000 2629a69c5ed2SRob Clark #define A6XX_GRAS_BIN_CONTROL_USE_VIZ 0x00200000 2630a69c5ed2SRob Clark 2631a69c5ed2SRob Clark #define REG_A6XX_RB_BIN_CONTROL2 0x000088d3 2632a69c5ed2SRob Clark #define A6XX_RB_BIN_CONTROL2_BINW__MASK 0x000000ff 2633a69c5ed2SRob Clark #define A6XX_RB_BIN_CONTROL2_BINW__SHIFT 0 2634a69c5ed2SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val) 26352d756322SRob Clark { 2636a69c5ed2SRob Clark return ((val >> 5) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK; 26372d756322SRob Clark } 2638a69c5ed2SRob Clark #define A6XX_RB_BIN_CONTROL2_BINH__MASK 0x0001ff00 2639a69c5ed2SRob Clark #define A6XX_RB_BIN_CONTROL2_BINH__SHIFT 8 2640a69c5ed2SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val) 26412d756322SRob Clark { 2642a69c5ed2SRob Clark return ((val >> 4) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK; 26432d756322SRob Clark } 26442d756322SRob Clark 26452d756322SRob Clark #define REG_A6XX_VSC_BIN_SIZE 0x00000c02 26462d756322SRob Clark #define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff 26472d756322SRob Clark #define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 26482d756322SRob Clark static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 26492d756322SRob Clark { 26502d756322SRob Clark return ((val >> 5) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK; 26512d756322SRob Clark } 26522d756322SRob Clark #define A6XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001ff00 26532d756322SRob Clark #define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT 8 26542d756322SRob Clark static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 26552d756322SRob Clark { 26562d756322SRob Clark return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK; 26572d756322SRob Clark } 26582d756322SRob Clark 26592d756322SRob Clark #define REG_A6XX_VSC_SIZE_ADDRESS_LO 0x00000c03 26602d756322SRob Clark 26612d756322SRob Clark #define REG_A6XX_VSC_SIZE_ADDRESS_HI 0x00000c04 26622d756322SRob Clark 26632d756322SRob Clark #define REG_A6XX_VSC_BIN_COUNT 0x00000c06 26642d756322SRob Clark #define A6XX_VSC_BIN_COUNT_NX__MASK 0x000007fe 26652d756322SRob Clark #define A6XX_VSC_BIN_COUNT_NX__SHIFT 1 26662d756322SRob Clark static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val) 26672d756322SRob Clark { 26682d756322SRob Clark return ((val) << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK; 26692d756322SRob Clark } 26702d756322SRob Clark #define A6XX_VSC_BIN_COUNT_NY__MASK 0x001ff800 26712d756322SRob Clark #define A6XX_VSC_BIN_COUNT_NY__SHIFT 11 26722d756322SRob Clark static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val) 26732d756322SRob Clark { 26742d756322SRob Clark return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK; 26752d756322SRob Clark } 26762d756322SRob Clark 26772d756322SRob Clark static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 26782d756322SRob Clark 26792d756322SRob Clark static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 26802d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff 26812d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0 26822d756322SRob Clark static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) 26832d756322SRob Clark { 26842d756322SRob Clark return ((val) << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK; 26852d756322SRob Clark } 26862d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00 26872d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10 26882d756322SRob Clark static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) 26892d756322SRob Clark { 26902d756322SRob Clark return ((val) << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK; 26912d756322SRob Clark } 26922d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_W__MASK 0x03f00000 26932d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20 26942d756322SRob Clark static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) 26952d756322SRob Clark { 26962d756322SRob Clark return ((val) << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK; 26972d756322SRob Clark } 26982d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_H__MASK 0xfc000000 26992d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT 26 27002d756322SRob Clark static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) 27012d756322SRob Clark { 27022d756322SRob Clark return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK; 27032d756322SRob Clark } 27042d756322SRob Clark 2705a69c5ed2SRob Clark #define REG_A6XX_VSC_PIPE_DATA2_ADDRESS_LO 0x00000c30 27062d756322SRob Clark 2707a69c5ed2SRob Clark #define REG_A6XX_VSC_PIPE_DATA2_ADDRESS_HI 0x00000c31 27082d756322SRob Clark 2709a69c5ed2SRob Clark #define REG_A6XX_VSC_PIPE_DATA2_PITCH 0x00000c32 2710a69c5ed2SRob Clark 2711a69c5ed2SRob Clark #define REG_A6XX_VSC_PIPE_DATA2_ARRAY_PITCH 0x00000c33 2712a69c5ed2SRob Clark #define A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__MASK 0xffffffff 2713a69c5ed2SRob Clark #define A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__SHIFT 0 2714a69c5ed2SRob Clark static inline uint32_t A6XX_VSC_PIPE_DATA2_ARRAY_PITCH(uint32_t val) 2715a69c5ed2SRob Clark { 2716a69c5ed2SRob Clark return ((val >> 4) << A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__SHIFT) & A6XX_VSC_PIPE_DATA2_ARRAY_PITCH__MASK; 2717a69c5ed2SRob Clark } 27182d756322SRob Clark 27192d756322SRob Clark #define REG_A6XX_VSC_PIPE_DATA_ADDRESS_LO 0x00000c34 27202d756322SRob Clark 27212d756322SRob Clark #define REG_A6XX_VSC_PIPE_DATA_ADDRESS_HI 0x00000c35 27222d756322SRob Clark 27232d756322SRob Clark #define REG_A6XX_VSC_PIPE_DATA_PITCH 0x00000c36 27242d756322SRob Clark 2725a69c5ed2SRob Clark #define REG_A6XX_VSC_PIPE_DATA_ARRAY_PITCH 0x00000c37 2726a69c5ed2SRob Clark #define A6XX_VSC_PIPE_DATA_ARRAY_PITCH__MASK 0xffffffff 2727a69c5ed2SRob Clark #define A6XX_VSC_PIPE_DATA_ARRAY_PITCH__SHIFT 0 2728a69c5ed2SRob Clark static inline uint32_t A6XX_VSC_PIPE_DATA_ARRAY_PITCH(uint32_t val) 2729a69c5ed2SRob Clark { 2730a69c5ed2SRob Clark return ((val >> 4) << A6XX_VSC_PIPE_DATA_ARRAY_PITCH__SHIFT) & A6XX_VSC_PIPE_DATA_ARRAY_PITCH__MASK; 2731a69c5ed2SRob Clark } 2732a69c5ed2SRob Clark 27332d756322SRob Clark static inline uint32_t REG_A6XX_VSC_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; } 27342d756322SRob Clark 27352d756322SRob Clark static inline uint32_t REG_A6XX_VSC_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; } 27362d756322SRob Clark 27372d756322SRob Clark #define REG_A6XX_UCHE_UNKNOWN_0E12 0x00000e12 27382d756322SRob Clark 2739a69c5ed2SRob Clark #define REG_A6XX_GRAS_UNKNOWN_8000 0x00008000 2740a69c5ed2SRob Clark 27412d756322SRob Clark #define REG_A6XX_GRAS_UNKNOWN_8001 0x00008001 27422d756322SRob Clark 27432d756322SRob Clark #define REG_A6XX_GRAS_UNKNOWN_8004 0x00008004 27442d756322SRob Clark 27452d756322SRob Clark #define REG_A6XX_GRAS_CNTL 0x00008005 27462d756322SRob Clark #define A6XX_GRAS_CNTL_VARYING 0x00000001 2747a69c5ed2SRob Clark #define A6XX_GRAS_CNTL_UNK3 0x00000008 27482d756322SRob Clark #define A6XX_GRAS_CNTL_XCOORD 0x00000040 27492d756322SRob Clark #define A6XX_GRAS_CNTL_YCOORD 0x00000080 27502d756322SRob Clark #define A6XX_GRAS_CNTL_ZCOORD 0x00000100 27512d756322SRob Clark #define A6XX_GRAS_CNTL_WCOORD 0x00000200 27522d756322SRob Clark 27532d756322SRob Clark #define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x00008006 27542d756322SRob Clark #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff 27552d756322SRob Clark #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0 27562d756322SRob Clark static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val) 27572d756322SRob Clark { 27582d756322SRob Clark return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK; 27592d756322SRob Clark } 27602d756322SRob Clark #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x000ffc00 27612d756322SRob Clark #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10 27622d756322SRob Clark static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) 27632d756322SRob Clark { 27642d756322SRob Clark return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK; 27652d756322SRob Clark } 27662d756322SRob Clark 27672d756322SRob Clark #define REG_A6XX_GRAS_CL_VPORT_XOFFSET_0 0x00008010 27682d756322SRob Clark #define A6XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff 27692d756322SRob Clark #define A6XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0 27702d756322SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET_0(float val) 27712d756322SRob Clark { 27722d756322SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET_0__MASK; 27732d756322SRob Clark } 27742d756322SRob Clark 27752d756322SRob Clark #define REG_A6XX_GRAS_CL_VPORT_XSCALE_0 0x00008011 27762d756322SRob Clark #define A6XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff 27772d756322SRob Clark #define A6XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0 27782d756322SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE_0(float val) 27792d756322SRob Clark { 27802d756322SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE_0__MASK; 27812d756322SRob Clark } 27822d756322SRob Clark 27832d756322SRob Clark #define REG_A6XX_GRAS_CL_VPORT_YOFFSET_0 0x00008012 27842d756322SRob Clark #define A6XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff 27852d756322SRob Clark #define A6XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0 27862d756322SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET_0(float val) 27872d756322SRob Clark { 27882d756322SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET_0__MASK; 27892d756322SRob Clark } 27902d756322SRob Clark 27912d756322SRob Clark #define REG_A6XX_GRAS_CL_VPORT_YSCALE_0 0x00008013 27922d756322SRob Clark #define A6XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff 27932d756322SRob Clark #define A6XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0 27942d756322SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE_0(float val) 27952d756322SRob Clark { 27962d756322SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE_0__MASK; 27972d756322SRob Clark } 27982d756322SRob Clark 27992d756322SRob Clark #define REG_A6XX_GRAS_CL_VPORT_ZOFFSET_0 0x00008014 28002d756322SRob Clark #define A6XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff 28012d756322SRob Clark #define A6XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0 28022d756322SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET_0(float val) 28032d756322SRob Clark { 28042d756322SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET_0__MASK; 28052d756322SRob Clark } 28062d756322SRob Clark 28072d756322SRob Clark #define REG_A6XX_GRAS_CL_VPORT_ZSCALE_0 0x00008015 28082d756322SRob Clark #define A6XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff 28092d756322SRob Clark #define A6XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0 28102d756322SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE_0(float val) 28112d756322SRob Clark { 28122d756322SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE_0__MASK; 28132d756322SRob Clark } 28142d756322SRob Clark 28152d756322SRob Clark #define REG_A6XX_GRAS_SU_CNTL 0x00008090 28162d756322SRob Clark #define A6XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001 28172d756322SRob Clark #define A6XX_GRAS_SU_CNTL_CULL_BACK 0x00000002 28182d756322SRob Clark #define A6XX_GRAS_SU_CNTL_FRONT_CW 0x00000004 28192d756322SRob Clark #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8 28202d756322SRob Clark #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3 28212d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) 28222d756322SRob Clark { 28232d756322SRob Clark return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK; 28242d756322SRob Clark } 28252d756322SRob Clark #define A6XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800 28262d756322SRob Clark #define A6XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000 28272d756322SRob Clark 28282d756322SRob Clark #define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091 28292d756322SRob Clark #define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 28302d756322SRob Clark #define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 28312d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val) 28322d756322SRob Clark { 28332d756322SRob Clark return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 28342d756322SRob Clark } 28352d756322SRob Clark #define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 28362d756322SRob Clark #define A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 28372d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MAX(float val) 28382d756322SRob Clark { 28392d756322SRob Clark return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 28402d756322SRob Clark } 28412d756322SRob Clark 28422d756322SRob Clark #define REG_A6XX_GRAS_SU_POINT_SIZE 0x00008092 28432d756322SRob Clark #define A6XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff 28442d756322SRob Clark #define A6XX_GRAS_SU_POINT_SIZE__SHIFT 0 28452d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val) 28462d756322SRob Clark { 28472d756322SRob Clark return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK; 28482d756322SRob Clark } 28492d756322SRob Clark 2850a69c5ed2SRob Clark #define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL 0x00008094 2851a69c5ed2SRob Clark #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001 2852a69c5ed2SRob Clark 28532d756322SRob Clark #define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE 0x00008095 28542d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff 28552d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 28562d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val) 28572d756322SRob Clark { 28582d756322SRob Clark return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; 28592d756322SRob Clark } 28602d756322SRob Clark 28612d756322SRob Clark #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00008096 28622d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 28632d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 28642d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 28652d756322SRob Clark { 28662d756322SRob Clark return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 28672d756322SRob Clark } 28682d756322SRob Clark 28692d756322SRob Clark #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x00008097 28702d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff 28712d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0 28722d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val) 28732d756322SRob Clark { 28742d756322SRob Clark return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK; 28752d756322SRob Clark } 28762d756322SRob Clark 28772d756322SRob Clark #define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO 0x00008098 28782d756322SRob Clark #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 28792d756322SRob Clark #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 28802d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) 28812d756322SRob Clark { 28822d756322SRob Clark return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; 28832d756322SRob Clark } 28842d756322SRob Clark 28852d756322SRob Clark #define REG_A6XX_GRAS_UNKNOWN_8099 0x00008099 28862d756322SRob Clark 28872d756322SRob Clark #define REG_A6XX_GRAS_UNKNOWN_809B 0x0000809b 28882d756322SRob Clark 2889a69c5ed2SRob Clark #define REG_A6XX_GRAS_UNKNOWN_80A0 0x000080a0 2890a69c5ed2SRob Clark 28912d756322SRob Clark #define REG_A6XX_GRAS_RAS_MSAA_CNTL 0x000080a2 28922d756322SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 28932d756322SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 28942d756322SRob Clark static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 28952d756322SRob Clark { 28962d756322SRob Clark return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK; 28972d756322SRob Clark } 28982d756322SRob Clark 28992d756322SRob Clark #define REG_A6XX_GRAS_DEST_MSAA_CNTL 0x000080a3 29002d756322SRob Clark #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 29012d756322SRob Clark #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 29022d756322SRob Clark static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 29032d756322SRob Clark { 29042d756322SRob Clark return ((val) << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK; 29052d756322SRob Clark } 29062d756322SRob Clark #define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 29072d756322SRob Clark 29082d756322SRob Clark #define REG_A6XX_GRAS_UNKNOWN_80A4 0x000080a4 29092d756322SRob Clark 29102d756322SRob Clark #define REG_A6XX_GRAS_UNKNOWN_80A5 0x000080a5 29112d756322SRob Clark 29122d756322SRob Clark #define REG_A6XX_GRAS_UNKNOWN_80A6 0x000080a6 29132d756322SRob Clark 29142d756322SRob Clark #define REG_A6XX_GRAS_UNKNOWN_80AF 0x000080af 29152d756322SRob Clark 29162d756322SRob Clark #define REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0 0x000080b0 29172d756322SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000 29182d756322SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK 0x00007fff 29192d756322SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT 0 29202d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val) 29212d756322SRob Clark { 29222d756322SRob Clark return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK; 29232d756322SRob Clark } 29242d756322SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK 0x7fff0000 29252d756322SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT 16 29262d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val) 29272d756322SRob Clark { 29282d756322SRob Clark return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK; 29292d756322SRob Clark } 29302d756322SRob Clark 29312d756322SRob Clark #define REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0 0x000080b1 29322d756322SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000 29332d756322SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK 0x00007fff 29342d756322SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT 0 29352d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val) 29362d756322SRob Clark { 29372d756322SRob Clark return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK; 29382d756322SRob Clark } 29392d756322SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK 0x7fff0000 29402d756322SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT 16 29412d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val) 29422d756322SRob Clark { 29432d756322SRob Clark return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK; 29442d756322SRob Clark } 29452d756322SRob Clark 29462d756322SRob Clark #define REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0 0x000080d0 29472d756322SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000 29482d756322SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK 0x00007fff 29492d756322SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT 0 29502d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val) 29512d756322SRob Clark { 29522d756322SRob Clark return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK; 29532d756322SRob Clark } 29542d756322SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK 0x7fff0000 29552d756322SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT 16 29562d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val) 29572d756322SRob Clark { 29582d756322SRob Clark return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK; 29592d756322SRob Clark } 29602d756322SRob Clark 29612d756322SRob Clark #define REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0 0x000080d1 29622d756322SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000 29632d756322SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK 0x00007fff 29642d756322SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT 0 29652d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val) 29662d756322SRob Clark { 29672d756322SRob Clark return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK; 29682d756322SRob Clark } 29692d756322SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK 0x7fff0000 29702d756322SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT 16 29712d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val) 29722d756322SRob Clark { 29732d756322SRob Clark return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK; 29742d756322SRob Clark } 29752d756322SRob Clark 29762d756322SRob Clark #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL 0x000080f0 29772d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 29782d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 29792d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 29802d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 29812d756322SRob Clark { 29822d756322SRob Clark return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 29832d756322SRob Clark } 29842d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 29852d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 29862d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 29872d756322SRob Clark { 29882d756322SRob Clark return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 29892d756322SRob Clark } 29902d756322SRob Clark 29912d756322SRob Clark #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR 0x000080f1 29922d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 29932d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 29942d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 29952d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 29962d756322SRob Clark { 29972d756322SRob Clark return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 29982d756322SRob Clark } 29992d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 30002d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 30012d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 30022d756322SRob Clark { 30032d756322SRob Clark return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 30042d756322SRob Clark } 30052d756322SRob Clark 30062d756322SRob Clark #define REG_A6XX_GRAS_LRZ_CNTL 0x00008100 30072d756322SRob Clark #define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001 30082d756322SRob Clark #define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002 30092d756322SRob Clark #define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004 3010ccdf7e28SRob Clark #define A6XX_GRAS_LRZ_CNTL_UNK3 0x00000008 3011ccdf7e28SRob Clark #define A6XX_GRAS_LRZ_CNTL_UNK4 0x00000010 30122d756322SRob Clark 3013a69c5ed2SRob Clark #define REG_A6XX_GRAS_UNKNOWN_8101 0x00008101 3014a69c5ed2SRob Clark 30152d756322SRob Clark #define REG_A6XX_GRAS_2D_BLIT_INFO 0x00008102 30162d756322SRob Clark #define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK 0x000000ff 30172d756322SRob Clark #define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT 0 30182d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) 30192d756322SRob Clark { 30202d756322SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK; 30212d756322SRob Clark } 30222d756322SRob Clark 30232d756322SRob Clark #define REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO 0x00008103 30242d756322SRob Clark 30252d756322SRob Clark #define REG_A6XX_GRAS_LRZ_BUFFER_BASE_HI 0x00008104 30262d756322SRob Clark 30272d756322SRob Clark #define REG_A6XX_GRAS_LRZ_BUFFER_PITCH 0x00008105 30282d756322SRob Clark #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK 0x000007ff 30292d756322SRob Clark #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT 0 30302d756322SRob Clark static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val) 30312d756322SRob Clark { 30322d756322SRob Clark return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK; 30332d756322SRob Clark } 30342d756322SRob Clark #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK 0x003ff800 30352d756322SRob Clark #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 30362d756322SRob Clark static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 30372d756322SRob Clark { 30382d756322SRob Clark return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK; 30392d756322SRob Clark } 30402d756322SRob Clark 30412d756322SRob Clark #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x00008106 30422d756322SRob Clark 30432d756322SRob Clark #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x00008107 30442d756322SRob Clark 3045a69c5ed2SRob Clark #define REG_A6XX_GRAS_UNKNOWN_8109 0x00008109 3046a69c5ed2SRob Clark 3047a69c5ed2SRob Clark #define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110 3048a69c5ed2SRob Clark 30492d756322SRob Clark #define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400 3050ccdf7e28SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00 3051ccdf7e28SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8 3052ccdf7e28SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_color_fmt val) 3053ccdf7e28SRob Clark { 3054ccdf7e28SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK; 3055ccdf7e28SRob Clark } 3056ccdf7e28SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR 0x00010000 30572d756322SRob Clark 30582d756322SRob Clark #define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401 30592d756322SRob Clark #define A6XX_GRAS_2D_SRC_TL_X_X__MASK 0x00ffff00 30602d756322SRob Clark #define A6XX_GRAS_2D_SRC_TL_X_X__SHIFT 8 30612d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_SRC_TL_X_X(uint32_t val) 30622d756322SRob Clark { 30632d756322SRob Clark return ((val) << A6XX_GRAS_2D_SRC_TL_X_X__SHIFT) & A6XX_GRAS_2D_SRC_TL_X_X__MASK; 30642d756322SRob Clark } 30652d756322SRob Clark 30662d756322SRob Clark #define REG_A6XX_GRAS_2D_SRC_BR_X 0x00008402 30672d756322SRob Clark #define A6XX_GRAS_2D_SRC_BR_X_X__MASK 0x00ffff00 30682d756322SRob Clark #define A6XX_GRAS_2D_SRC_BR_X_X__SHIFT 8 30692d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_SRC_BR_X_X(uint32_t val) 30702d756322SRob Clark { 30712d756322SRob Clark return ((val) << A6XX_GRAS_2D_SRC_BR_X_X__SHIFT) & A6XX_GRAS_2D_SRC_BR_X_X__MASK; 30722d756322SRob Clark } 30732d756322SRob Clark 30742d756322SRob Clark #define REG_A6XX_GRAS_2D_SRC_TL_Y 0x00008403 30752d756322SRob Clark #define A6XX_GRAS_2D_SRC_TL_Y_Y__MASK 0x00ffff00 30762d756322SRob Clark #define A6XX_GRAS_2D_SRC_TL_Y_Y__SHIFT 8 30772d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_SRC_TL_Y_Y(uint32_t val) 30782d756322SRob Clark { 30792d756322SRob Clark return ((val) << A6XX_GRAS_2D_SRC_TL_Y_Y__SHIFT) & A6XX_GRAS_2D_SRC_TL_Y_Y__MASK; 30802d756322SRob Clark } 30812d756322SRob Clark 30822d756322SRob Clark #define REG_A6XX_GRAS_2D_SRC_BR_Y 0x00008404 30832d756322SRob Clark #define A6XX_GRAS_2D_SRC_BR_Y_Y__MASK 0x00ffff00 30842d756322SRob Clark #define A6XX_GRAS_2D_SRC_BR_Y_Y__SHIFT 8 30852d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_SRC_BR_Y_Y(uint32_t val) 30862d756322SRob Clark { 30872d756322SRob Clark return ((val) << A6XX_GRAS_2D_SRC_BR_Y_Y__SHIFT) & A6XX_GRAS_2D_SRC_BR_Y_Y__MASK; 30882d756322SRob Clark } 30892d756322SRob Clark 30902d756322SRob Clark #define REG_A6XX_GRAS_2D_DST_TL 0x00008405 30912d756322SRob Clark #define A6XX_GRAS_2D_DST_TL_WINDOW_OFFSET_DISABLE 0x80000000 30922d756322SRob Clark #define A6XX_GRAS_2D_DST_TL_X__MASK 0x00007fff 30932d756322SRob Clark #define A6XX_GRAS_2D_DST_TL_X__SHIFT 0 30942d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val) 30952d756322SRob Clark { 30962d756322SRob Clark return ((val) << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK; 30972d756322SRob Clark } 30982d756322SRob Clark #define A6XX_GRAS_2D_DST_TL_Y__MASK 0x7fff0000 30992d756322SRob Clark #define A6XX_GRAS_2D_DST_TL_Y__SHIFT 16 31002d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val) 31012d756322SRob Clark { 31022d756322SRob Clark return ((val) << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK; 31032d756322SRob Clark } 31042d756322SRob Clark 31052d756322SRob Clark #define REG_A6XX_GRAS_2D_DST_BR 0x00008406 31062d756322SRob Clark #define A6XX_GRAS_2D_DST_BR_WINDOW_OFFSET_DISABLE 0x80000000 31072d756322SRob Clark #define A6XX_GRAS_2D_DST_BR_X__MASK 0x00007fff 31082d756322SRob Clark #define A6XX_GRAS_2D_DST_BR_X__SHIFT 0 31092d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val) 31102d756322SRob Clark { 31112d756322SRob Clark return ((val) << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK; 31122d756322SRob Clark } 31132d756322SRob Clark #define A6XX_GRAS_2D_DST_BR_Y__MASK 0x7fff0000 31142d756322SRob Clark #define A6XX_GRAS_2D_DST_BR_Y__SHIFT 16 31152d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val) 31162d756322SRob Clark { 31172d756322SRob Clark return ((val) << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK; 31182d756322SRob Clark } 31192d756322SRob Clark 31202d756322SRob Clark #define REG_A6XX_GRAS_RESOLVE_CNTL_1 0x0000840a 31212d756322SRob Clark #define A6XX_GRAS_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE 0x80000000 31222d756322SRob Clark #define A6XX_GRAS_RESOLVE_CNTL_1_X__MASK 0x00007fff 31232d756322SRob Clark #define A6XX_GRAS_RESOLVE_CNTL_1_X__SHIFT 0 31242d756322SRob Clark static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_1_X(uint32_t val) 31252d756322SRob Clark { 31262d756322SRob Clark return ((val) << A6XX_GRAS_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_1_X__MASK; 31272d756322SRob Clark } 31282d756322SRob Clark #define A6XX_GRAS_RESOLVE_CNTL_1_Y__MASK 0x7fff0000 31292d756322SRob Clark #define A6XX_GRAS_RESOLVE_CNTL_1_Y__SHIFT 16 31302d756322SRob Clark static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_1_Y(uint32_t val) 31312d756322SRob Clark { 31322d756322SRob Clark return ((val) << A6XX_GRAS_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_1_Y__MASK; 31332d756322SRob Clark } 31342d756322SRob Clark 31352d756322SRob Clark #define REG_A6XX_GRAS_RESOLVE_CNTL_2 0x0000840b 31362d756322SRob Clark #define A6XX_GRAS_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE 0x80000000 31372d756322SRob Clark #define A6XX_GRAS_RESOLVE_CNTL_2_X__MASK 0x00007fff 31382d756322SRob Clark #define A6XX_GRAS_RESOLVE_CNTL_2_X__SHIFT 0 31392d756322SRob Clark static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_2_X(uint32_t val) 31402d756322SRob Clark { 31412d756322SRob Clark return ((val) << A6XX_GRAS_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_2_X__MASK; 31422d756322SRob Clark } 31432d756322SRob Clark #define A6XX_GRAS_RESOLVE_CNTL_2_Y__MASK 0x7fff0000 31442d756322SRob Clark #define A6XX_GRAS_RESOLVE_CNTL_2_Y__SHIFT 16 31452d756322SRob Clark static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_2_Y(uint32_t val) 31462d756322SRob Clark { 31472d756322SRob Clark return ((val) << A6XX_GRAS_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_2_Y__MASK; 31482d756322SRob Clark } 31492d756322SRob Clark 31502d756322SRob Clark #define REG_A6XX_GRAS_UNKNOWN_8600 0x00008600 31512d756322SRob Clark 3152a69c5ed2SRob Clark #define REG_A6XX_RB_BIN_CONTROL 0x00008800 3153a69c5ed2SRob Clark #define A6XX_RB_BIN_CONTROL_BINW__MASK 0x000000ff 3154a69c5ed2SRob Clark #define A6XX_RB_BIN_CONTROL_BINW__SHIFT 0 3155a69c5ed2SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val) 3156a69c5ed2SRob Clark { 3157a69c5ed2SRob Clark return ((val >> 5) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK; 3158a69c5ed2SRob Clark } 3159a69c5ed2SRob Clark #define A6XX_RB_BIN_CONTROL_BINH__MASK 0x0001ff00 3160a69c5ed2SRob Clark #define A6XX_RB_BIN_CONTROL_BINH__SHIFT 8 3161a69c5ed2SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val) 3162a69c5ed2SRob Clark { 3163a69c5ed2SRob Clark return ((val >> 4) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK; 3164a69c5ed2SRob Clark } 3165a69c5ed2SRob Clark #define A6XX_RB_BIN_CONTROL_BINNING_PASS 0x00040000 3166a69c5ed2SRob Clark #define A6XX_RB_BIN_CONTROL_USE_VIZ 0x00200000 3167a69c5ed2SRob Clark 3168a69c5ed2SRob Clark #define REG_A6XX_RB_RENDER_CNTL 0x00008801 3169a69c5ed2SRob Clark #define A6XX_RB_RENDER_CNTL_UNK4 0x00000010 3170a69c5ed2SRob Clark #define A6XX_RB_RENDER_CNTL_BINNING 0x00000080 3171a69c5ed2SRob Clark #define A6XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000 3172a69c5ed2SRob Clark #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000 3173a69c5ed2SRob Clark #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16 3174a69c5ed2SRob Clark static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val) 3175a69c5ed2SRob Clark { 3176a69c5ed2SRob Clark return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK; 3177a69c5ed2SRob Clark } 3178a69c5ed2SRob Clark 31792d756322SRob Clark #define REG_A6XX_RB_RAS_MSAA_CNTL 0x00008802 31802d756322SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 31812d756322SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 31822d756322SRob Clark static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 31832d756322SRob Clark { 31842d756322SRob Clark return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK; 31852d756322SRob Clark } 31862d756322SRob Clark 31872d756322SRob Clark #define REG_A6XX_RB_DEST_MSAA_CNTL 0x00008803 31882d756322SRob Clark #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 31892d756322SRob Clark #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 31902d756322SRob Clark static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 31912d756322SRob Clark { 31922d756322SRob Clark return ((val) << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK; 31932d756322SRob Clark } 31942d756322SRob Clark #define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 31952d756322SRob Clark 31962d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8804 0x00008804 31972d756322SRob Clark 31982d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8805 0x00008805 31992d756322SRob Clark 32002d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8806 0x00008806 32012d756322SRob Clark 32022d756322SRob Clark #define REG_A6XX_RB_RENDER_CONTROL0 0x00008809 32032d756322SRob Clark #define A6XX_RB_RENDER_CONTROL0_VARYING 0x00000001 3204a69c5ed2SRob Clark #define A6XX_RB_RENDER_CONTROL0_UNK3 0x00000008 32052d756322SRob Clark #define A6XX_RB_RENDER_CONTROL0_XCOORD 0x00000040 32062d756322SRob Clark #define A6XX_RB_RENDER_CONTROL0_YCOORD 0x00000080 32072d756322SRob Clark #define A6XX_RB_RENDER_CONTROL0_ZCOORD 0x00000100 32082d756322SRob Clark #define A6XX_RB_RENDER_CONTROL0_WCOORD 0x00000200 32092d756322SRob Clark #define A6XX_RB_RENDER_CONTROL0_UNK10 0x00000400 32102d756322SRob Clark 32112d756322SRob Clark #define REG_A6XX_RB_RENDER_CONTROL1 0x0000880a 32122d756322SRob Clark #define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001 32132d756322SRob Clark #define A6XX_RB_RENDER_CONTROL1_FACENESS 0x00000002 32142d756322SRob Clark #define A6XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000008 32152d756322SRob Clark 32162d756322SRob Clark #define REG_A6XX_RB_FS_OUTPUT_CNTL0 0x0000880b 32172d756322SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z 0x00000002 32182d756322SRob Clark 32192d756322SRob Clark #define REG_A6XX_RB_FS_OUTPUT_CNTL1 0x0000880c 32202d756322SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f 32212d756322SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT 0 32222d756322SRob Clark static inline uint32_t A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val) 32232d756322SRob Clark { 32242d756322SRob Clark return ((val) << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK; 32252d756322SRob Clark } 32262d756322SRob Clark 32272d756322SRob Clark #define REG_A6XX_RB_RENDER_COMPONENTS 0x0000880d 32282d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f 32292d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0 32302d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) 32312d756322SRob Clark { 32322d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK; 32332d756322SRob Clark } 32342d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0 32352d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4 32362d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) 32372d756322SRob Clark { 32382d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK; 32392d756322SRob Clark } 32402d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00 32412d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8 32422d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) 32432d756322SRob Clark { 32442d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK; 32452d756322SRob Clark } 32462d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000 32472d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12 32482d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) 32492d756322SRob Clark { 32502d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK; 32512d756322SRob Clark } 32522d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000 32532d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16 32542d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) 32552d756322SRob Clark { 32562d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK; 32572d756322SRob Clark } 32582d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000 32592d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20 32602d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) 32612d756322SRob Clark { 32622d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK; 32632d756322SRob Clark } 32642d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000 32652d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24 32662d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) 32672d756322SRob Clark { 32682d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK; 32692d756322SRob Clark } 32702d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000 32712d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28 32722d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) 32732d756322SRob Clark { 32742d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK; 32752d756322SRob Clark } 32762d756322SRob Clark 32772d756322SRob Clark #define REG_A6XX_RB_DITHER_CNTL 0x0000880e 32782d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK 0x00000003 32792d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT 0 32802d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val) 32812d756322SRob Clark { 32822d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK; 32832d756322SRob Clark } 32842d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK 0x0000000c 32852d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT 2 32862d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val) 32872d756322SRob Clark { 32882d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK; 32892d756322SRob Clark } 32902d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK 0x00000030 32912d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT 4 32922d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val) 32932d756322SRob Clark { 32942d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK; 32952d756322SRob Clark } 32962d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK 0x000000c0 32972d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT 6 32982d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val) 32992d756322SRob Clark { 33002d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK; 33012d756322SRob Clark } 33022d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK 0x00000300 33032d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT 8 33042d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val) 33052d756322SRob Clark { 33062d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK; 33072d756322SRob Clark } 33082d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK 0x00000c00 33092d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT 10 33102d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val) 33112d756322SRob Clark { 33122d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK; 33132d756322SRob Clark } 33142d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK 0x00001000 33152d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT 12 33162d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val) 33172d756322SRob Clark { 33182d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK; 33192d756322SRob Clark } 33202d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK 0x0000c000 33212d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT 14 33222d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val) 33232d756322SRob Clark { 33242d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK; 33252d756322SRob Clark } 33262d756322SRob Clark 33272d756322SRob Clark #define REG_A6XX_RB_SRGB_CNTL 0x0000880f 33282d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT0 0x00000001 33292d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT1 0x00000002 33302d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT2 0x00000004 33312d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT3 0x00000008 33322d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT4 0x00000010 33332d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT5 0x00000020 33342d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT6 0x00000040 33352d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT7 0x00000080 33362d756322SRob Clark 3337a69c5ed2SRob Clark #define REG_A6XX_RB_UNKNOWN_8810 0x00008810 3338a69c5ed2SRob Clark 3339a69c5ed2SRob Clark #define REG_A6XX_RB_UNKNOWN_8811 0x00008811 3340a69c5ed2SRob Clark 33412d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8818 0x00008818 33422d756322SRob Clark 33432d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8819 0x00008819 33442d756322SRob Clark 33452d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881A 0x0000881a 33462d756322SRob Clark 33472d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881B 0x0000881b 33482d756322SRob Clark 33492d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881C 0x0000881c 33502d756322SRob Clark 33512d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881D 0x0000881d 33522d756322SRob Clark 33532d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881E 0x0000881e 33542d756322SRob Clark 33552d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; } 33562d756322SRob Clark 33572d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; } 33582d756322SRob Clark #define A6XX_RB_MRT_CONTROL_BLEND 0x00000001 33592d756322SRob Clark #define A6XX_RB_MRT_CONTROL_BLEND2 0x00000002 33602d756322SRob Clark #define A6XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004 33612d756322SRob Clark #define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078 33622d756322SRob Clark #define A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3 33632d756322SRob Clark static inline uint32_t A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) 33642d756322SRob Clark { 33652d756322SRob Clark return ((val) << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK; 33662d756322SRob Clark } 33672d756322SRob Clark #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780 33682d756322SRob Clark #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7 33692d756322SRob Clark static inline uint32_t A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 33702d756322SRob Clark { 33712d756322SRob Clark return ((val) << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 33722d756322SRob Clark } 33732d756322SRob Clark 33742d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; } 33752d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 33762d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 33772d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 33782d756322SRob Clark { 33792d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 33802d756322SRob Clark } 33812d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 33822d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 33832d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 33842d756322SRob Clark { 33852d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 33862d756322SRob Clark } 33872d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 33882d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 33892d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 33902d756322SRob Clark { 33912d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 33922d756322SRob Clark } 33932d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 33942d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 33952d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 33962d756322SRob Clark { 33972d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 33982d756322SRob Clark } 33992d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 34002d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 34012d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 34022d756322SRob Clark { 34032d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 34042d756322SRob Clark } 34052d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 34062d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 34072d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 34082d756322SRob Clark { 34092d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 34102d756322SRob Clark } 34112d756322SRob Clark 34122d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; } 34132d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff 34142d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 34152d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) 34162d756322SRob Clark { 34172d756322SRob Clark return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 34182d756322SRob Clark } 34192d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300 34202d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8 34212d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val) 34222d756322SRob Clark { 34232d756322SRob Clark return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 34242d756322SRob Clark } 34252d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000 34262d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13 34272d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 34282d756322SRob Clark { 34292d756322SRob Clark return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 34302d756322SRob Clark } 34312d756322SRob Clark 34322d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; } 34332d756322SRob Clark #define A6XX_RB_MRT_PITCH__MASK 0xffffffff 34342d756322SRob Clark #define A6XX_RB_MRT_PITCH__SHIFT 0 34352d756322SRob Clark static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val) 34362d756322SRob Clark { 34372d756322SRob Clark return ((val >> 6) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK; 34382d756322SRob Clark } 34392d756322SRob Clark 34402d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; } 34412d756322SRob Clark #define A6XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff 34422d756322SRob Clark #define A6XX_RB_MRT_ARRAY_PITCH__SHIFT 0 34432d756322SRob Clark static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val) 34442d756322SRob Clark { 34452d756322SRob Clark return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK; 34462d756322SRob Clark } 34472d756322SRob Clark 34482d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x00008825 + 0x8*i0; } 34492d756322SRob Clark 34502d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x00008826 + 0x8*i0; } 34512d756322SRob Clark 34522d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; } 34532d756322SRob Clark 34542d756322SRob Clark #define REG_A6XX_RB_BLEND_RED_F32 0x00008860 34552d756322SRob Clark #define A6XX_RB_BLEND_RED_F32__MASK 0xffffffff 34562d756322SRob Clark #define A6XX_RB_BLEND_RED_F32__SHIFT 0 34572d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_RED_F32(float val) 34582d756322SRob Clark { 34592d756322SRob Clark return ((fui(val)) << A6XX_RB_BLEND_RED_F32__SHIFT) & A6XX_RB_BLEND_RED_F32__MASK; 34602d756322SRob Clark } 34612d756322SRob Clark 34622d756322SRob Clark #define REG_A6XX_RB_BLEND_GREEN_F32 0x00008861 34632d756322SRob Clark #define A6XX_RB_BLEND_GREEN_F32__MASK 0xffffffff 34642d756322SRob Clark #define A6XX_RB_BLEND_GREEN_F32__SHIFT 0 34652d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_GREEN_F32(float val) 34662d756322SRob Clark { 34672d756322SRob Clark return ((fui(val)) << A6XX_RB_BLEND_GREEN_F32__SHIFT) & A6XX_RB_BLEND_GREEN_F32__MASK; 34682d756322SRob Clark } 34692d756322SRob Clark 34702d756322SRob Clark #define REG_A6XX_RB_BLEND_BLUE_F32 0x00008862 34712d756322SRob Clark #define A6XX_RB_BLEND_BLUE_F32__MASK 0xffffffff 34722d756322SRob Clark #define A6XX_RB_BLEND_BLUE_F32__SHIFT 0 34732d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_BLUE_F32(float val) 34742d756322SRob Clark { 34752d756322SRob Clark return ((fui(val)) << A6XX_RB_BLEND_BLUE_F32__SHIFT) & A6XX_RB_BLEND_BLUE_F32__MASK; 34762d756322SRob Clark } 34772d756322SRob Clark 34782d756322SRob Clark #define REG_A6XX_RB_BLEND_ALPHA_F32 0x00008863 34792d756322SRob Clark #define A6XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff 34802d756322SRob Clark #define A6XX_RB_BLEND_ALPHA_F32__SHIFT 0 34812d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_ALPHA_F32(float val) 34822d756322SRob Clark { 34832d756322SRob Clark return ((fui(val)) << A6XX_RB_BLEND_ALPHA_F32__SHIFT) & A6XX_RB_BLEND_ALPHA_F32__MASK; 34842d756322SRob Clark } 34852d756322SRob Clark 34862d756322SRob Clark #define REG_A6XX_RB_ALPHA_CONTROL 0x00008864 34872d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff 34882d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 34892d756322SRob Clark static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) 34902d756322SRob Clark { 34912d756322SRob Clark return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; 34922d756322SRob Clark } 34932d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 34942d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 34952d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 34962d756322SRob Clark static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 34972d756322SRob Clark { 34982d756322SRob Clark return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; 34992d756322SRob Clark } 35002d756322SRob Clark 35012d756322SRob Clark #define REG_A6XX_RB_BLEND_CNTL 0x00008865 35022d756322SRob Clark #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff 35032d756322SRob Clark #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 35042d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val) 35052d756322SRob Clark { 35062d756322SRob Clark return ((val) << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK; 35072d756322SRob Clark } 35082d756322SRob Clark #define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100 3509ccdf7e28SRob Clark #define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 35102d756322SRob Clark #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000 35112d756322SRob Clark #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16 35122d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val) 35132d756322SRob Clark { 35142d756322SRob Clark return ((val) << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK; 35152d756322SRob Clark } 35162d756322SRob Clark 3517a69c5ed2SRob Clark #define REG_A6XX_RB_DEPTH_PLANE_CNTL 0x00008870 3518a69c5ed2SRob Clark #define A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001 3519a69c5ed2SRob Clark 35202d756322SRob Clark #define REG_A6XX_RB_DEPTH_CNTL 0x00008871 35212d756322SRob Clark #define A6XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001 35222d756322SRob Clark #define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002 35232d756322SRob Clark #define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c 35242d756322SRob Clark #define A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2 35252d756322SRob Clark static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) 35262d756322SRob Clark { 35272d756322SRob Clark return ((val) << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK; 35282d756322SRob Clark } 35292d756322SRob Clark #define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040 35302d756322SRob Clark 35312d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_INFO 0x00008872 35322d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 35332d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 35342d756322SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) 35352d756322SRob Clark { 35362d756322SRob Clark return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; 35372d756322SRob Clark } 35382d756322SRob Clark 35392d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_PITCH 0x00008873 35402d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_PITCH__MASK 0xffffffff 35412d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0 35422d756322SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) 35432d756322SRob Clark { 35442d756322SRob Clark return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK; 35452d756322SRob Clark } 35462d756322SRob Clark 35472d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x00008874 35482d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0xffffffff 35492d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0 35502d756322SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) 35512d756322SRob Clark { 35522d756322SRob Clark return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; 35532d756322SRob Clark } 35542d756322SRob Clark 35552d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_BASE_LO 0x00008875 35562d756322SRob Clark 35572d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_BASE_HI 0x00008876 35582d756322SRob Clark 35592d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM 0x00008877 35602d756322SRob Clark 35612d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8878 0x00008878 35622d756322SRob Clark 35632d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8879 0x00008879 35642d756322SRob Clark 35652d756322SRob Clark #define REG_A6XX_RB_STENCIL_CONTROL 0x00008880 35662d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 35672d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 35682d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 35692d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 35702d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 35712d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 35722d756322SRob Clark { 35732d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC__MASK; 35742d756322SRob Clark } 35752d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 35762d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 35772d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 35782d756322SRob Clark { 35792d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL__MASK; 35802d756322SRob Clark } 35812d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 35822d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 35832d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 35842d756322SRob Clark { 35852d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK; 35862d756322SRob Clark } 35872d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 35882d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 35892d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 35902d756322SRob Clark { 35912d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 35922d756322SRob Clark } 35932d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 35942d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 35952d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 35962d756322SRob Clark { 35972d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 35982d756322SRob Clark } 35992d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 36002d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 36012d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 36022d756322SRob Clark { 36032d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 36042d756322SRob Clark } 36052d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 36062d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 36072d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 36082d756322SRob Clark { 36092d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 36102d756322SRob Clark } 36112d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 36122d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 36132d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 36142d756322SRob Clark { 36152d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 36162d756322SRob Clark } 36172d756322SRob Clark 36182d756322SRob Clark #define REG_A6XX_RB_STENCIL_INFO 0x00008881 36192d756322SRob Clark #define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 36202d756322SRob Clark 36212d756322SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_PITCH 0x00008882 36222d756322SRob Clark #define A6XX_RB_STENCIL_BUFFER_PITCH__MASK 0xffffffff 36232d756322SRob Clark #define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT 0 36242d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val) 36252d756322SRob Clark { 36262d756322SRob Clark return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK; 36272d756322SRob Clark } 36282d756322SRob Clark 36292d756322SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH 0x00008883 36302d756322SRob Clark #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK 0xffffffff 36312d756322SRob Clark #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT 0 36322d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val) 36332d756322SRob Clark { 36342d756322SRob Clark return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK; 36352d756322SRob Clark } 36362d756322SRob Clark 36372d756322SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_BASE_LO 0x00008884 36382d756322SRob Clark 36392d756322SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_BASE_HI 0x00008885 36402d756322SRob Clark 36412d756322SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM 0x00008886 36422d756322SRob Clark 36432d756322SRob Clark #define REG_A6XX_RB_STENCILREF 0x00008887 36442d756322SRob Clark #define A6XX_RB_STENCILREF_REF__MASK 0x000000ff 36452d756322SRob Clark #define A6XX_RB_STENCILREF_REF__SHIFT 0 36462d756322SRob Clark static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val) 36472d756322SRob Clark { 36482d756322SRob Clark return ((val) << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK; 36492d756322SRob Clark } 3650a69c5ed2SRob Clark #define A6XX_RB_STENCILREF_BFREF__MASK 0x0000ff00 3651a69c5ed2SRob Clark #define A6XX_RB_STENCILREF_BFREF__SHIFT 8 3652a69c5ed2SRob Clark static inline uint32_t A6XX_RB_STENCILREF_BFREF(uint32_t val) 3653a69c5ed2SRob Clark { 3654a69c5ed2SRob Clark return ((val) << A6XX_RB_STENCILREF_BFREF__SHIFT) & A6XX_RB_STENCILREF_BFREF__MASK; 3655a69c5ed2SRob Clark } 36562d756322SRob Clark 36572d756322SRob Clark #define REG_A6XX_RB_STENCILMASK 0x00008888 36582d756322SRob Clark #define A6XX_RB_STENCILMASK_MASK__MASK 0x000000ff 36592d756322SRob Clark #define A6XX_RB_STENCILMASK_MASK__SHIFT 0 36602d756322SRob Clark static inline uint32_t A6XX_RB_STENCILMASK_MASK(uint32_t val) 36612d756322SRob Clark { 36622d756322SRob Clark return ((val) << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK; 36632d756322SRob Clark } 3664a69c5ed2SRob Clark #define A6XX_RB_STENCILMASK_BFMASK__MASK 0x0000ff00 3665a69c5ed2SRob Clark #define A6XX_RB_STENCILMASK_BFMASK__SHIFT 8 3666a69c5ed2SRob Clark static inline uint32_t A6XX_RB_STENCILMASK_BFMASK(uint32_t val) 3667a69c5ed2SRob Clark { 3668a69c5ed2SRob Clark return ((val) << A6XX_RB_STENCILMASK_BFMASK__SHIFT) & A6XX_RB_STENCILMASK_BFMASK__MASK; 3669a69c5ed2SRob Clark } 36702d756322SRob Clark 36712d756322SRob Clark #define REG_A6XX_RB_STENCILWRMASK 0x00008889 36722d756322SRob Clark #define A6XX_RB_STENCILWRMASK_WRMASK__MASK 0x000000ff 36732d756322SRob Clark #define A6XX_RB_STENCILWRMASK_WRMASK__SHIFT 0 36742d756322SRob Clark static inline uint32_t A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val) 36752d756322SRob Clark { 36762d756322SRob Clark return ((val) << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK; 36772d756322SRob Clark } 3678a69c5ed2SRob Clark #define A6XX_RB_STENCILWRMASK_BFWRMASK__MASK 0x0000ff00 3679a69c5ed2SRob Clark #define A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT 8 3680a69c5ed2SRob Clark static inline uint32_t A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val) 3681a69c5ed2SRob Clark { 3682a69c5ed2SRob Clark return ((val) << A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_BFWRMASK__MASK; 3683a69c5ed2SRob Clark } 36842d756322SRob Clark 36852d756322SRob Clark #define REG_A6XX_RB_WINDOW_OFFSET 0x00008890 36862d756322SRob Clark #define A6XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 36872d756322SRob Clark #define A6XX_RB_WINDOW_OFFSET_X__MASK 0x00007fff 36882d756322SRob Clark #define A6XX_RB_WINDOW_OFFSET_X__SHIFT 0 36892d756322SRob Clark static inline uint32_t A6XX_RB_WINDOW_OFFSET_X(uint32_t val) 36902d756322SRob Clark { 36912d756322SRob Clark return ((val) << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK; 36922d756322SRob Clark } 36932d756322SRob Clark #define A6XX_RB_WINDOW_OFFSET_Y__MASK 0x7fff0000 36942d756322SRob Clark #define A6XX_RB_WINDOW_OFFSET_Y__SHIFT 16 36952d756322SRob Clark static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val) 36962d756322SRob Clark { 36972d756322SRob Clark return ((val) << A6XX_RB_WINDOW_OFFSET_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET_Y__MASK; 36982d756322SRob Clark } 36992d756322SRob Clark 37002d756322SRob Clark #define REG_A6XX_RB_SAMPLE_COUNT_CONTROL 0x00008891 37012d756322SRob Clark #define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 37022d756322SRob Clark 3703ccdf7e28SRob Clark #define REG_A6XX_RB_LRZ_CNTL 0x00008898 3704ccdf7e28SRob Clark #define A6XX_RB_LRZ_CNTL_ENABLE 0x00000001 3705ccdf7e28SRob Clark 37062d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_88D0 0x000088d0 37072d756322SRob Clark 37082d756322SRob Clark #define REG_A6XX_RB_BLIT_SCISSOR_TL 0x000088d1 37092d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 37102d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_X__MASK 0x00007fff 37112d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT 0 37122d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val) 37132d756322SRob Clark { 37142d756322SRob Clark return ((val) << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK; 37152d756322SRob Clark } 37162d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK 0x7fff0000 37172d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT 16 37182d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val) 37192d756322SRob Clark { 37202d756322SRob Clark return ((val) << A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_Y__MASK; 37212d756322SRob Clark } 37222d756322SRob Clark 37232d756322SRob Clark #define REG_A6XX_RB_BLIT_SCISSOR_BR 0x000088d2 37242d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 37252d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_X__MASK 0x00007fff 37262d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT 0 37272d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val) 37282d756322SRob Clark { 37292d756322SRob Clark return ((val) << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK; 37302d756322SRob Clark } 37312d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK 0x7fff0000 37322d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT 16 37332d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val) 37342d756322SRob Clark { 37352d756322SRob Clark return ((val) << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK; 37362d756322SRob Clark } 37372d756322SRob Clark 3738ccdf7e28SRob Clark #define REG_A6XX_RB_MSAA_CNTL 0x000088d5 3739ccdf7e28SRob Clark #define A6XX_RB_MSAA_CNTL_SAMPLES__MASK 0x00000018 3740ccdf7e28SRob Clark #define A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT 3 3741ccdf7e28SRob Clark static inline uint32_t A6XX_RB_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 3742ccdf7e28SRob Clark { 3743ccdf7e28SRob Clark return ((val) << A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_MSAA_CNTL_SAMPLES__MASK; 3744ccdf7e28SRob Clark } 3745ccdf7e28SRob Clark 37462d756322SRob Clark #define REG_A6XX_RB_BLIT_BASE_GMEM 0x000088d6 37472d756322SRob Clark 37482d756322SRob Clark #define REG_A6XX_RB_BLIT_DST_INFO 0x000088d7 37492d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK 0x00000003 37502d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT 0 37512d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) 37522d756322SRob Clark { 37532d756322SRob Clark return ((val) << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK; 37542d756322SRob Clark } 37552d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_FLAGS 0x00000004 3756ccdf7e28SRob Clark #define A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK 0x00000018 3757ccdf7e28SRob Clark #define A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT 3 3758ccdf7e28SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) 3759ccdf7e28SRob Clark { 3760ccdf7e28SRob Clark return ((val) << A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK; 3761ccdf7e28SRob Clark } 37622d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK 0x00007f80 37632d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT 7 37642d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) 37652d756322SRob Clark { 37662d756322SRob Clark return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK; 37672d756322SRob Clark } 37682d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK 0x00000060 37692d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT 5 37702d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) 37712d756322SRob Clark { 37722d756322SRob Clark return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK; 37732d756322SRob Clark } 37742d756322SRob Clark 37752d756322SRob Clark #define REG_A6XX_RB_BLIT_DST_LO 0x000088d8 37762d756322SRob Clark 37772d756322SRob Clark #define REG_A6XX_RB_BLIT_DST_HI 0x000088d9 37782d756322SRob Clark 37792d756322SRob Clark #define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da 37802d756322SRob Clark #define A6XX_RB_BLIT_DST_PITCH__MASK 0xffffffff 37812d756322SRob Clark #define A6XX_RB_BLIT_DST_PITCH__SHIFT 0 37822d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val) 37832d756322SRob Clark { 37842d756322SRob Clark return ((val >> 6) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK; 37852d756322SRob Clark } 37862d756322SRob Clark 37872d756322SRob Clark #define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH 0x000088db 37882d756322SRob Clark #define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0xffffffff 37892d756322SRob Clark #define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0 37902d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) 37912d756322SRob Clark { 37922d756322SRob Clark return ((val >> 6) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK; 37932d756322SRob Clark } 37942d756322SRob Clark 37952d756322SRob Clark #define REG_A6XX_RB_BLIT_FLAG_DST_LO 0x000088dc 37962d756322SRob Clark 37972d756322SRob Clark #define REG_A6XX_RB_BLIT_FLAG_DST_HI 0x000088dd 37982d756322SRob Clark 37992d756322SRob Clark #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 0x000088df 38002d756322SRob Clark 38012d756322SRob Clark #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1 0x000088e0 38022d756322SRob Clark 38032d756322SRob Clark #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2 0x000088e1 38042d756322SRob Clark 38052d756322SRob Clark #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3 0x000088e2 38062d756322SRob Clark 38072d756322SRob Clark #define REG_A6XX_RB_BLIT_INFO 0x000088e3 38082d756322SRob Clark #define A6XX_RB_BLIT_INFO_UNK0 0x00000001 3809a69c5ed2SRob Clark #define A6XX_RB_BLIT_INFO_GMEM 0x00000002 38102d756322SRob Clark #define A6XX_RB_BLIT_INFO_INTEGER 0x00000004 3811a69c5ed2SRob Clark #define A6XX_RB_BLIT_INFO_DEPTH 0x00000008 3812a69c5ed2SRob Clark #define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK 0x000000f0 3813a69c5ed2SRob Clark #define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT 4 3814a69c5ed2SRob Clark static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val) 38152d756322SRob Clark { 3816a69c5ed2SRob Clark return ((val) << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK; 38172d756322SRob Clark } 38182d756322SRob Clark 38192d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_88F0 0x000088f0 38202d756322SRob Clark 38212d756322SRob Clark #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x00008900 38222d756322SRob Clark 38232d756322SRob Clark #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x00008901 38242d756322SRob Clark 38252d756322SRob Clark #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x00008902 38262d756322SRob Clark 38272d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; } 38282d756322SRob Clark 38292d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x00008903 + 0x3*i0; } 38302d756322SRob Clark 38312d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x00008904 + 0x3*i0; } 38322d756322SRob Clark 38332d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; } 38342d756322SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff 38352d756322SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 38362d756322SRob Clark static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val) 38372d756322SRob Clark { 38382d756322SRob Clark return ((val >> 5) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK; 38392d756322SRob Clark } 38402d756322SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x003ff800 38412d756322SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 38422d756322SRob Clark static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 38432d756322SRob Clark { 38442d756322SRob Clark return ((val >> 5) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; 38452d756322SRob Clark } 38462d756322SRob Clark 38472d756322SRob Clark #define REG_A6XX_RB_SAMPLE_COUNT_ADDR_LO 0x00008927 38482d756322SRob Clark 38492d756322SRob Clark #define REG_A6XX_RB_SAMPLE_COUNT_ADDR_HI 0x00008928 38502d756322SRob Clark 38512d756322SRob Clark #define REG_A6XX_RB_2D_BLIT_CNTL 0x00008c00 38522d756322SRob Clark #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00 38532d756322SRob Clark #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8 38542d756322SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_color_fmt val) 38552d756322SRob Clark { 38562d756322SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK; 38572d756322SRob Clark } 3858ccdf7e28SRob Clark #define A6XX_RB_2D_BLIT_CNTL_SCISSOR 0x00010000 3859ccdf7e28SRob Clark 3860ccdf7e28SRob Clark #define REG_A6XX_RB_UNKNOWN_8C01 0x00008c01 38612d756322SRob Clark 38622d756322SRob Clark #define REG_A6XX_RB_2D_DST_INFO 0x00008c17 38632d756322SRob Clark #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff 38642d756322SRob Clark #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0 38652d756322SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) 38662d756322SRob Clark { 38672d756322SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK; 38682d756322SRob Clark } 38692d756322SRob Clark #define A6XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300 38702d756322SRob Clark #define A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8 38712d756322SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) 38722d756322SRob Clark { 38732d756322SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_2D_DST_INFO_TILE_MODE__MASK; 38742d756322SRob Clark } 38752d756322SRob Clark #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00 38762d756322SRob Clark #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10 38772d756322SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) 38782d756322SRob Clark { 38792d756322SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK; 38802d756322SRob Clark } 38812d756322SRob Clark #define A6XX_RB_2D_DST_INFO_FLAGS 0x00001000 38822d756322SRob Clark 38832d756322SRob Clark #define REG_A6XX_RB_2D_DST_LO 0x00008c18 38842d756322SRob Clark 38852d756322SRob Clark #define REG_A6XX_RB_2D_DST_HI 0x00008c19 38862d756322SRob Clark 38872d756322SRob Clark #define REG_A6XX_RB_2D_DST_SIZE 0x00008c1a 38882d756322SRob Clark #define A6XX_RB_2D_DST_SIZE_PITCH__MASK 0x0000ffff 38892d756322SRob Clark #define A6XX_RB_2D_DST_SIZE_PITCH__SHIFT 0 38902d756322SRob Clark static inline uint32_t A6XX_RB_2D_DST_SIZE_PITCH(uint32_t val) 38912d756322SRob Clark { 38922d756322SRob Clark return ((val >> 6) << A6XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A6XX_RB_2D_DST_SIZE_PITCH__MASK; 38932d756322SRob Clark } 38942d756322SRob Clark 38952d756322SRob Clark #define REG_A6XX_RB_2D_DST_FLAGS_LO 0x00008c20 38962d756322SRob Clark 38972d756322SRob Clark #define REG_A6XX_RB_2D_DST_FLAGS_HI 0x00008c21 38982d756322SRob Clark 38992d756322SRob Clark #define REG_A6XX_RB_2D_SRC_SOLID_C0 0x00008c2c 39002d756322SRob Clark 39012d756322SRob Clark #define REG_A6XX_RB_2D_SRC_SOLID_C1 0x00008c2d 39022d756322SRob Clark 39032d756322SRob Clark #define REG_A6XX_RB_2D_SRC_SOLID_C2 0x00008c2e 39042d756322SRob Clark 39052d756322SRob Clark #define REG_A6XX_RB_2D_SRC_SOLID_C3 0x00008c2f 39062d756322SRob Clark 39072d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8E01 0x00008e01 39082d756322SRob Clark 3909a69c5ed2SRob Clark #define REG_A6XX_RB_UNKNOWN_8E04 0x00008e04 3910a69c5ed2SRob Clark 39112d756322SRob Clark #define REG_A6XX_RB_CCU_CNTL 0x00008e07 39122d756322SRob Clark 39132d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9101 0x00009101 39142d756322SRob Clark 39152d756322SRob Clark #define REG_A6XX_VPC_GS_SIV_CNTL 0x00009104 39162d756322SRob Clark 3917a69c5ed2SRob Clark #define REG_A6XX_VPC_UNKNOWN_9107 0x00009107 3918a69c5ed2SRob Clark 39192d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9108 0x00009108 39202d756322SRob Clark 39212d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; } 39222d756322SRob Clark 39232d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; } 39242d756322SRob Clark 39252d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; } 39262d756322SRob Clark 39272d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; } 39282d756322SRob Clark 39292d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9210 0x00009210 39302d756322SRob Clark 39312d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9211 0x00009211 39322d756322SRob Clark 39332d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; } 39342d756322SRob Clark 39352d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; } 39362d756322SRob Clark 39372d756322SRob Clark #define REG_A6XX_VPC_SO_CNTL 0x00009216 39382d756322SRob Clark #define A6XX_VPC_SO_CNTL_ENABLE 0x00010000 39392d756322SRob Clark 39402d756322SRob Clark #define REG_A6XX_VPC_SO_PROG 0x00009217 39412d756322SRob Clark #define A6XX_VPC_SO_PROG_A_BUF__MASK 0x00000003 39422d756322SRob Clark #define A6XX_VPC_SO_PROG_A_BUF__SHIFT 0 39432d756322SRob Clark static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val) 39442d756322SRob Clark { 39452d756322SRob Clark return ((val) << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK; 39462d756322SRob Clark } 39472d756322SRob Clark #define A6XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc 39482d756322SRob Clark #define A6XX_VPC_SO_PROG_A_OFF__SHIFT 2 39492d756322SRob Clark static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val) 39502d756322SRob Clark { 39512d756322SRob Clark return ((val >> 2) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK; 39522d756322SRob Clark } 39532d756322SRob Clark #define A6XX_VPC_SO_PROG_A_EN 0x00000800 39542d756322SRob Clark #define A6XX_VPC_SO_PROG_B_BUF__MASK 0x00003000 39552d756322SRob Clark #define A6XX_VPC_SO_PROG_B_BUF__SHIFT 12 39562d756322SRob Clark static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val) 39572d756322SRob Clark { 39582d756322SRob Clark return ((val) << A6XX_VPC_SO_PROG_B_BUF__SHIFT) & A6XX_VPC_SO_PROG_B_BUF__MASK; 39592d756322SRob Clark } 39602d756322SRob Clark #define A6XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000 39612d756322SRob Clark #define A6XX_VPC_SO_PROG_B_OFF__SHIFT 14 39622d756322SRob Clark static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val) 39632d756322SRob Clark { 39642d756322SRob Clark return ((val >> 2) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK; 39652d756322SRob Clark } 39662d756322SRob Clark #define A6XX_VPC_SO_PROG_B_EN 0x00800000 39672d756322SRob Clark 39682d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; } 39692d756322SRob Clark 39702d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000921a + 0x7*i0; } 39712d756322SRob Clark 39722d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000921b + 0x7*i0; } 39732d756322SRob Clark 39742d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; } 39752d756322SRob Clark 39762d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000921d + 0x7*i0; } 39772d756322SRob Clark 39782d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; } 39792d756322SRob Clark 39802d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000921f + 0x7*i0; } 39812d756322SRob Clark 39822d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x00009220 + 0x7*i0; } 39832d756322SRob Clark 39842d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9236 0x00009236 39852d756322SRob Clark 39862d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9300 0x00009300 39872d756322SRob Clark 39882d756322SRob Clark #define REG_A6XX_VPC_PACK 0x00009301 39892d756322SRob Clark #define A6XX_VPC_PACK_STRIDE_IN_VPC__MASK 0x000000ff 39902d756322SRob Clark #define A6XX_VPC_PACK_STRIDE_IN_VPC__SHIFT 0 39912d756322SRob Clark static inline uint32_t A6XX_VPC_PACK_STRIDE_IN_VPC(uint32_t val) 39922d756322SRob Clark { 39932d756322SRob Clark return ((val) << A6XX_VPC_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_PACK_STRIDE_IN_VPC__MASK; 39942d756322SRob Clark } 39952d756322SRob Clark #define A6XX_VPC_PACK_NUMNONPOSVAR__MASK 0x0000ff00 39962d756322SRob Clark #define A6XX_VPC_PACK_NUMNONPOSVAR__SHIFT 8 39972d756322SRob Clark static inline uint32_t A6XX_VPC_PACK_NUMNONPOSVAR(uint32_t val) 39982d756322SRob Clark { 39992d756322SRob Clark return ((val) << A6XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A6XX_VPC_PACK_NUMNONPOSVAR__MASK; 40002d756322SRob Clark } 40012d756322SRob Clark #define A6XX_VPC_PACK_PSIZELOC__MASK 0x00ff0000 40022d756322SRob Clark #define A6XX_VPC_PACK_PSIZELOC__SHIFT 16 40032d756322SRob Clark static inline uint32_t A6XX_VPC_PACK_PSIZELOC(uint32_t val) 40042d756322SRob Clark { 40052d756322SRob Clark return ((val) << A6XX_VPC_PACK_PSIZELOC__SHIFT) & A6XX_VPC_PACK_PSIZELOC__MASK; 40062d756322SRob Clark } 40072d756322SRob Clark 40082d756322SRob Clark #define REG_A6XX_VPC_CNTL_0 0x00009304 40092d756322SRob Clark #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK 0x000000ff 40102d756322SRob Clark #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT 0 40112d756322SRob Clark static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val) 40122d756322SRob Clark { 40132d756322SRob Clark return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK; 40142d756322SRob Clark } 40152d756322SRob Clark #define A6XX_VPC_CNTL_0_VARYING 0x00010000 40162d756322SRob Clark 40172d756322SRob Clark #define REG_A6XX_VPC_SO_BUF_CNTL 0x00009305 40182d756322SRob Clark #define A6XX_VPC_SO_BUF_CNTL_BUF0 0x00000001 40192d756322SRob Clark #define A6XX_VPC_SO_BUF_CNTL_BUF1 0x00000008 40202d756322SRob Clark #define A6XX_VPC_SO_BUF_CNTL_BUF2 0x00000040 40212d756322SRob Clark #define A6XX_VPC_SO_BUF_CNTL_BUF3 0x00000200 40222d756322SRob Clark #define A6XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000 40232d756322SRob Clark 4024a69c5ed2SRob Clark #define REG_A6XX_VPC_SO_OVERRIDE 0x00009306 4025a69c5ed2SRob Clark #define A6XX_VPC_SO_OVERRIDE_SO_DISABLE 0x00000001 4026a69c5ed2SRob Clark 40272d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9600 0x00009600 40282d756322SRob Clark 40292d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9602 0x00009602 40302d756322SRob Clark 40312d756322SRob Clark #define REG_A6XX_PC_UNKNOWN_9801 0x00009801 40322d756322SRob Clark 40332d756322SRob Clark #define REG_A6XX_PC_RESTART_INDEX 0x00009803 40342d756322SRob Clark 40352d756322SRob Clark #define REG_A6XX_PC_MODE_CNTL 0x00009804 40362d756322SRob Clark 40372d756322SRob Clark #define REG_A6XX_PC_UNKNOWN_9805 0x00009805 40382d756322SRob Clark 4039a69c5ed2SRob Clark #define REG_A6XX_PC_UNKNOWN_9806 0x00009806 4040a69c5ed2SRob Clark 4041a69c5ed2SRob Clark #define REG_A6XX_PC_UNKNOWN_9980 0x00009980 4042a69c5ed2SRob Clark 40432d756322SRob Clark #define REG_A6XX_PC_UNKNOWN_9981 0x00009981 40442d756322SRob Clark 4045a69c5ed2SRob Clark #define REG_A6XX_PC_UNKNOWN_9990 0x00009990 4046a69c5ed2SRob Clark 40472d756322SRob Clark #define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00 40482d756322SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001 40492d756322SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002 40502d756322SRob Clark 40512d756322SRob Clark #define REG_A6XX_PC_PRIMITIVE_CNTL_1 0x00009b01 40522d756322SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__MASK 0x0000007f 40532d756322SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__SHIFT 0 40542d756322SRob Clark static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(uint32_t val) 40552d756322SRob Clark { 40562d756322SRob Clark return ((val) << A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__MASK; 40572d756322SRob Clark } 4058a69c5ed2SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_1_PSIZE 0x00000100 40592d756322SRob Clark 40602d756322SRob Clark #define REG_A6XX_PC_UNKNOWN_9B06 0x00009b06 40612d756322SRob Clark 40622d756322SRob Clark #define REG_A6XX_PC_UNKNOWN_9B07 0x00009b07 40632d756322SRob Clark 40642d756322SRob Clark #define REG_A6XX_PC_TESSFACTOR_ADDR_LO 0x00009e08 40652d756322SRob Clark 40662d756322SRob Clark #define REG_A6XX_PC_TESSFACTOR_ADDR_HI 0x00009e09 40672d756322SRob Clark 40682d756322SRob Clark #define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72 40692d756322SRob Clark 40702d756322SRob Clark #define REG_A6XX_VFD_CONTROL_0 0x0000a000 40712d756322SRob Clark #define A6XX_VFD_CONTROL_0_VTXCNT__MASK 0x0000003f 40722d756322SRob Clark #define A6XX_VFD_CONTROL_0_VTXCNT__SHIFT 0 40732d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_0_VTXCNT(uint32_t val) 40742d756322SRob Clark { 40752d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A6XX_VFD_CONTROL_0_VTXCNT__MASK; 40762d756322SRob Clark } 40772d756322SRob Clark 40782d756322SRob Clark #define REG_A6XX_VFD_CONTROL_1 0x0000a001 40792d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff 40802d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0 40812d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 40822d756322SRob Clark { 40832d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VTX__MASK; 40842d756322SRob Clark } 40852d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00 40862d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4INST__SHIFT 8 40872d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 40882d756322SRob Clark { 40892d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK; 40902d756322SRob Clark } 40912d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000 40922d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16 40932d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val) 40942d756322SRob Clark { 40952d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK; 40962d756322SRob Clark } 40972d756322SRob Clark 40982d756322SRob Clark #define REG_A6XX_VFD_CONTROL_2 0x0000a002 40992d756322SRob Clark #define A6XX_VFD_CONTROL_2_REGID_PATCHID__MASK 0x000000ff 41002d756322SRob Clark #define A6XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT 0 41012d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_2_REGID_PATCHID(uint32_t val) 41022d756322SRob Clark { 41032d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_PATCHID__MASK; 41042d756322SRob Clark } 41052d756322SRob Clark 41062d756322SRob Clark #define REG_A6XX_VFD_CONTROL_3 0x0000a003 41072d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_PATCHID__MASK 0x0000ff00 41082d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT 8 41092d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_3_REGID_PATCHID(uint32_t val) 41102d756322SRob Clark { 41112d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_PATCHID__MASK; 41122d756322SRob Clark } 41132d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000 41142d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16 41152d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) 41162d756322SRob Clark { 41172d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSX__MASK; 41182d756322SRob Clark } 41192d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000 41202d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24 41212d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) 41222d756322SRob Clark { 41232d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK; 41242d756322SRob Clark } 41252d756322SRob Clark 41262d756322SRob Clark #define REG_A6XX_VFD_CONTROL_4 0x0000a004 41272d756322SRob Clark 41282d756322SRob Clark #define REG_A6XX_VFD_CONTROL_5 0x0000a005 41292d756322SRob Clark 41302d756322SRob Clark #define REG_A6XX_VFD_CONTROL_6 0x0000a006 41312d756322SRob Clark 41322d756322SRob Clark #define REG_A6XX_VFD_MODE_CNTL 0x0000a007 41332d756322SRob Clark #define A6XX_VFD_MODE_CNTL_BINNING_PASS 0x00000001 41342d756322SRob Clark 41352d756322SRob Clark #define REG_A6XX_VFD_UNKNOWN_A008 0x0000a008 41362d756322SRob Clark 4137a69c5ed2SRob Clark #define REG_A6XX_VFD_UNKNOWN_A009 0x0000a009 4138a69c5ed2SRob Clark 41392d756322SRob Clark #define REG_A6XX_VFD_INDEX_OFFSET 0x0000a00e 41402d756322SRob Clark 41412d756322SRob Clark #define REG_A6XX_VFD_INSTANCE_START_OFFSET 0x0000a00f 41422d756322SRob Clark 41432d756322SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; } 41442d756322SRob Clark 41452d756322SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000a010 + 0x4*i0; } 41462d756322SRob Clark 41472d756322SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000a011 + 0x4*i0; } 41482d756322SRob Clark 41492d756322SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; } 41502d756322SRob Clark 41512d756322SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; } 41522d756322SRob Clark 41532d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; } 41542d756322SRob Clark 41552d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; } 41562d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f 41572d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_IDX__SHIFT 0 41582d756322SRob Clark static inline uint32_t A6XX_VFD_DECODE_INSTR_IDX(uint32_t val) 41592d756322SRob Clark { 41602d756322SRob Clark return ((val) << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK; 41612d756322SRob Clark } 41622d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_INSTANCED 0x00020000 41632d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000 41642d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20 41652d756322SRob Clark static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_vtx_fmt val) 41662d756322SRob Clark { 41672d756322SRob Clark return ((val) << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK; 41682d756322SRob Clark } 41692d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000 41702d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_SWAP__SHIFT 28 41712d756322SRob Clark static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 41722d756322SRob Clark { 41732d756322SRob Clark return ((val) << A6XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A6XX_VFD_DECODE_INSTR_SWAP__MASK; 41742d756322SRob Clark } 41752d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_UNK30 0x40000000 41762d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_FLOAT 0x80000000 41772d756322SRob Clark 41782d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; } 41792d756322SRob Clark 41802d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } 41812d756322SRob Clark 41822d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } 41832d756322SRob Clark #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f 41842d756322SRob Clark #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0 41852d756322SRob Clark static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val) 41862d756322SRob Clark { 41872d756322SRob Clark return ((val) << A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK; 41882d756322SRob Clark } 41892d756322SRob Clark #define A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0 41902d756322SRob Clark #define A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4 41912d756322SRob Clark static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) 41922d756322SRob Clark { 41932d756322SRob Clark return ((val) << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK; 41942d756322SRob Clark } 41952d756322SRob Clark 41962d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_A0F8 0x0000a0f8 41972d756322SRob Clark 41982d756322SRob Clark #define REG_A6XX_SP_PRIMITIVE_CNTL 0x0000a802 41992d756322SRob Clark #define A6XX_SP_PRIMITIVE_CNTL_VSOUT__MASK 0x0000001f 42002d756322SRob Clark #define A6XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT 0 42012d756322SRob Clark static inline uint32_t A6XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val) 42022d756322SRob Clark { 42032d756322SRob Clark return ((val) << A6XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT) & A6XX_SP_PRIMITIVE_CNTL_VSOUT__MASK; 42042d756322SRob Clark } 42052d756322SRob Clark 42062d756322SRob Clark static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; } 42072d756322SRob Clark 42082d756322SRob Clark static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; } 42092d756322SRob Clark #define A6XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff 42102d756322SRob Clark #define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 42112d756322SRob Clark static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 42122d756322SRob Clark { 42132d756322SRob Clark return ((val) << A6XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_A_REGID__MASK; 42142d756322SRob Clark } 42152d756322SRob Clark #define A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00 42162d756322SRob Clark #define A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8 42172d756322SRob Clark static inline uint32_t A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 42182d756322SRob Clark { 42192d756322SRob Clark return ((val) << A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 42202d756322SRob Clark } 42212d756322SRob Clark #define A6XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000 42222d756322SRob Clark #define A6XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 42232d756322SRob Clark static inline uint32_t A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 42242d756322SRob Clark { 42252d756322SRob Clark return ((val) << A6XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_B_REGID__MASK; 42262d756322SRob Clark } 42272d756322SRob Clark #define A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000 42282d756322SRob Clark #define A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24 42292d756322SRob Clark static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 42302d756322SRob Clark { 42312d756322SRob Clark return ((val) << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 42322d756322SRob Clark } 42332d756322SRob Clark 42342d756322SRob Clark static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; } 42352d756322SRob Clark 42362d756322SRob Clark static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; } 42372d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 42382d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 42392d756322SRob Clark static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 42402d756322SRob Clark { 42412d756322SRob Clark return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 42422d756322SRob Clark } 42432d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 42442d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 42452d756322SRob Clark static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 42462d756322SRob Clark { 42472d756322SRob Clark return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 42482d756322SRob Clark } 42492d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 42502d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 42512d756322SRob Clark static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 42522d756322SRob Clark { 42532d756322SRob Clark return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 42542d756322SRob Clark } 42552d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 42562d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 42572d756322SRob Clark static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 42582d756322SRob Clark { 42592d756322SRob Clark return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 42602d756322SRob Clark } 42612d756322SRob Clark 42622d756322SRob Clark #define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800 42632d756322SRob Clark #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 42642d756322SRob Clark #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 42652d756322SRob Clark static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 42662d756322SRob Clark { 42672d756322SRob Clark return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 42682d756322SRob Clark } 42692d756322SRob Clark #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 42702d756322SRob Clark #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 42712d756322SRob Clark static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 42722d756322SRob Clark { 42732d756322SRob Clark return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 42742d756322SRob Clark } 42752d756322SRob Clark #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 42762d756322SRob Clark #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14 42772d756322SRob Clark static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val) 42782d756322SRob Clark { 42792d756322SRob Clark return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK; 42802d756322SRob Clark } 42812d756322SRob Clark #define A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000 42822d756322SRob Clark #define A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20 42832d756322SRob Clark static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 42842d756322SRob Clark { 42852d756322SRob Clark return ((val) << A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; 42862d756322SRob Clark } 42872d756322SRob Clark #define A6XX_SP_VS_CTRL_REG0_VARYING 0x00400000 42882d756322SRob Clark #define A6XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x04000000 42892d756322SRob Clark #define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x80000000 42902d756322SRob Clark 4291a69c5ed2SRob Clark #define REG_A6XX_SP_UNKNOWN_A81B 0x0000a81b 4292a69c5ed2SRob Clark 42932d756322SRob Clark #define REG_A6XX_SP_VS_OBJ_START_LO 0x0000a81c 42942d756322SRob Clark 42952d756322SRob Clark #define REG_A6XX_SP_VS_OBJ_START_HI 0x0000a81d 42962d756322SRob Clark 42972d756322SRob Clark #define REG_A6XX_SP_VS_TEX_COUNT 0x0000a822 42982d756322SRob Clark 42992d756322SRob Clark #define REG_A6XX_SP_VS_CONFIG 0x0000a823 43002d756322SRob Clark #define A6XX_SP_VS_CONFIG_ENABLED 0x00000100 43012d756322SRob Clark #define A6XX_SP_VS_CONFIG_NTEX__MASK 0x0001fe00 43022d756322SRob Clark #define A6XX_SP_VS_CONFIG_NTEX__SHIFT 9 43032d756322SRob Clark static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val) 43042d756322SRob Clark { 43052d756322SRob Clark return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK; 43062d756322SRob Clark } 43072d756322SRob Clark #define A6XX_SP_VS_CONFIG_NSAMP__MASK 0x01fe0000 43082d756322SRob Clark #define A6XX_SP_VS_CONFIG_NSAMP__SHIFT 17 43092d756322SRob Clark static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val) 43102d756322SRob Clark { 43112d756322SRob Clark return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK; 43122d756322SRob Clark } 43132d756322SRob Clark 43142d756322SRob Clark #define REG_A6XX_SP_VS_INSTRLEN 0x0000a824 43152d756322SRob Clark 43162d756322SRob Clark #define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830 43172d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 43182d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 43192d756322SRob Clark static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 43202d756322SRob Clark { 43212d756322SRob Clark return ((val) << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 43222d756322SRob Clark } 43232d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 43242d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 43252d756322SRob Clark static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 43262d756322SRob Clark { 43272d756322SRob Clark return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 43282d756322SRob Clark } 43292d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 43302d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 14 43312d756322SRob Clark static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val) 43322d756322SRob Clark { 43332d756322SRob Clark return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK; 43342d756322SRob Clark } 43352d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK 0x00100000 43362d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT 20 43372d756322SRob Clark static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 43382d756322SRob Clark { 43392d756322SRob Clark return ((val) << A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK; 43402d756322SRob Clark } 43412d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_VARYING 0x00400000 43422d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_PIXLODENABLE 0x04000000 43432d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_MERGEDREGS 0x80000000 43442d756322SRob Clark 43452d756322SRob Clark #define REG_A6XX_SP_HS_UNKNOWN_A831 0x0000a831 43462d756322SRob Clark 43472d756322SRob Clark #define REG_A6XX_SP_HS_OBJ_START_LO 0x0000a834 43482d756322SRob Clark 43492d756322SRob Clark #define REG_A6XX_SP_HS_OBJ_START_HI 0x0000a835 43502d756322SRob Clark 43512d756322SRob Clark #define REG_A6XX_SP_HS_TEX_COUNT 0x0000a83a 43522d756322SRob Clark 43532d756322SRob Clark #define REG_A6XX_SP_HS_CONFIG 0x0000a83b 43542d756322SRob Clark #define A6XX_SP_HS_CONFIG_ENABLED 0x00000100 43552d756322SRob Clark #define A6XX_SP_HS_CONFIG_NTEX__MASK 0x0001fe00 43562d756322SRob Clark #define A6XX_SP_HS_CONFIG_NTEX__SHIFT 9 43572d756322SRob Clark static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val) 43582d756322SRob Clark { 43592d756322SRob Clark return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK; 43602d756322SRob Clark } 43612d756322SRob Clark #define A6XX_SP_HS_CONFIG_NSAMP__MASK 0x01fe0000 43622d756322SRob Clark #define A6XX_SP_HS_CONFIG_NSAMP__SHIFT 17 43632d756322SRob Clark static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val) 43642d756322SRob Clark { 43652d756322SRob Clark return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK; 43662d756322SRob Clark } 43672d756322SRob Clark 43682d756322SRob Clark #define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c 43692d756322SRob Clark 43702d756322SRob Clark #define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840 43712d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 43722d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 43732d756322SRob Clark static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 43742d756322SRob Clark { 43752d756322SRob Clark return ((val) << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 43762d756322SRob Clark } 43772d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 43782d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 43792d756322SRob Clark static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 43802d756322SRob Clark { 43812d756322SRob Clark return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 43822d756322SRob Clark } 43832d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 43842d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 14 43852d756322SRob Clark static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val) 43862d756322SRob Clark { 43872d756322SRob Clark return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK; 43882d756322SRob Clark } 43892d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK 0x00100000 43902d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT 20 43912d756322SRob Clark static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 43922d756322SRob Clark { 43932d756322SRob Clark return ((val) << A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK; 43942d756322SRob Clark } 43952d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_VARYING 0x00400000 43962d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_PIXLODENABLE 0x04000000 43972d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_MERGEDREGS 0x80000000 43982d756322SRob Clark 43992d756322SRob Clark #define REG_A6XX_SP_DS_OBJ_START_LO 0x0000a85c 44002d756322SRob Clark 44012d756322SRob Clark #define REG_A6XX_SP_DS_OBJ_START_HI 0x0000a85d 44022d756322SRob Clark 44032d756322SRob Clark #define REG_A6XX_SP_DS_TEX_COUNT 0x0000a862 44042d756322SRob Clark 44052d756322SRob Clark #define REG_A6XX_SP_DS_CONFIG 0x0000a863 44062d756322SRob Clark #define A6XX_SP_DS_CONFIG_ENABLED 0x00000100 44072d756322SRob Clark #define A6XX_SP_DS_CONFIG_NTEX__MASK 0x0001fe00 44082d756322SRob Clark #define A6XX_SP_DS_CONFIG_NTEX__SHIFT 9 44092d756322SRob Clark static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val) 44102d756322SRob Clark { 44112d756322SRob Clark return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK; 44122d756322SRob Clark } 44132d756322SRob Clark #define A6XX_SP_DS_CONFIG_NSAMP__MASK 0x01fe0000 44142d756322SRob Clark #define A6XX_SP_DS_CONFIG_NSAMP__SHIFT 17 44152d756322SRob Clark static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val) 44162d756322SRob Clark { 44172d756322SRob Clark return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK; 44182d756322SRob Clark } 44192d756322SRob Clark 44202d756322SRob Clark #define REG_A6XX_SP_DS_INSTRLEN 0x0000a864 44212d756322SRob Clark 44222d756322SRob Clark #define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870 44232d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 44242d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 44252d756322SRob Clark static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 44262d756322SRob Clark { 44272d756322SRob Clark return ((val) << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 44282d756322SRob Clark } 44292d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 44302d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 44312d756322SRob Clark static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 44322d756322SRob Clark { 44332d756322SRob Clark return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 44342d756322SRob Clark } 44352d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 44362d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 14 44372d756322SRob Clark static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val) 44382d756322SRob Clark { 44392d756322SRob Clark return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK; 44402d756322SRob Clark } 44412d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK 0x00100000 44422d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT 20 44432d756322SRob Clark static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 44442d756322SRob Clark { 44452d756322SRob Clark return ((val) << A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK; 44462d756322SRob Clark } 44472d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_VARYING 0x00400000 44482d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_PIXLODENABLE 0x04000000 44492d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_MERGEDREGS 0x80000000 44502d756322SRob Clark 44512d756322SRob Clark #define REG_A6XX_SP_GS_UNKNOWN_A871 0x0000a871 44522d756322SRob Clark 44532d756322SRob Clark #define REG_A6XX_SP_GS_OBJ_START_LO 0x0000a88d 44542d756322SRob Clark 44552d756322SRob Clark #define REG_A6XX_SP_GS_OBJ_START_HI 0x0000a88e 44562d756322SRob Clark 44572d756322SRob Clark #define REG_A6XX_SP_GS_TEX_COUNT 0x0000a893 44582d756322SRob Clark 44592d756322SRob Clark #define REG_A6XX_SP_GS_CONFIG 0x0000a894 44602d756322SRob Clark #define A6XX_SP_GS_CONFIG_ENABLED 0x00000100 44612d756322SRob Clark #define A6XX_SP_GS_CONFIG_NTEX__MASK 0x0001fe00 44622d756322SRob Clark #define A6XX_SP_GS_CONFIG_NTEX__SHIFT 9 44632d756322SRob Clark static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val) 44642d756322SRob Clark { 44652d756322SRob Clark return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK; 44662d756322SRob Clark } 44672d756322SRob Clark #define A6XX_SP_GS_CONFIG_NSAMP__MASK 0x01fe0000 44682d756322SRob Clark #define A6XX_SP_GS_CONFIG_NSAMP__SHIFT 17 44692d756322SRob Clark static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val) 44702d756322SRob Clark { 44712d756322SRob Clark return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK; 44722d756322SRob Clark } 44732d756322SRob Clark 44742d756322SRob Clark #define REG_A6XX_SP_GS_INSTRLEN 0x0000a895 44752d756322SRob Clark 44762d756322SRob Clark #define REG_A6XX_SP_VS_TEX_SAMP_LO 0x0000a8a0 44772d756322SRob Clark 44782d756322SRob Clark #define REG_A6XX_SP_VS_TEX_SAMP_HI 0x0000a8a1 44792d756322SRob Clark 44802d756322SRob Clark #define REG_A6XX_SP_HS_TEX_SAMP_LO 0x0000a8a2 44812d756322SRob Clark 44822d756322SRob Clark #define REG_A6XX_SP_HS_TEX_SAMP_HI 0x0000a8a3 44832d756322SRob Clark 44842d756322SRob Clark #define REG_A6XX_SP_DS_TEX_SAMP_LO 0x0000a8a4 44852d756322SRob Clark 44862d756322SRob Clark #define REG_A6XX_SP_DS_TEX_SAMP_HI 0x0000a8a5 44872d756322SRob Clark 44882d756322SRob Clark #define REG_A6XX_SP_GS_TEX_SAMP_LO 0x0000a8a6 44892d756322SRob Clark 44902d756322SRob Clark #define REG_A6XX_SP_GS_TEX_SAMP_HI 0x0000a8a7 44912d756322SRob Clark 44922d756322SRob Clark #define REG_A6XX_SP_VS_TEX_CONST_LO 0x0000a8a8 44932d756322SRob Clark 44942d756322SRob Clark #define REG_A6XX_SP_VS_TEX_CONST_HI 0x0000a8a9 44952d756322SRob Clark 44962d756322SRob Clark #define REG_A6XX_SP_HS_TEX_CONST_LO 0x0000a8aa 44972d756322SRob Clark 44982d756322SRob Clark #define REG_A6XX_SP_HS_TEX_CONST_HI 0x0000a8ab 44992d756322SRob Clark 45002d756322SRob Clark #define REG_A6XX_SP_DS_TEX_CONST_LO 0x0000a8ac 45012d756322SRob Clark 45022d756322SRob Clark #define REG_A6XX_SP_DS_TEX_CONST_HI 0x0000a8ad 45032d756322SRob Clark 45042d756322SRob Clark #define REG_A6XX_SP_GS_TEX_CONST_LO 0x0000a8ae 45052d756322SRob Clark 45062d756322SRob Clark #define REG_A6XX_SP_GS_TEX_CONST_HI 0x0000a8af 45072d756322SRob Clark 45082d756322SRob Clark #define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980 45092d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 45102d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 45112d756322SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 45122d756322SRob Clark { 45132d756322SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 45142d756322SRob Clark } 45152d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 45162d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 45172d756322SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 45182d756322SRob Clark { 45192d756322SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 45202d756322SRob Clark } 45212d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 45222d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 14 45232d756322SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) 45242d756322SRob Clark { 45252d756322SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK; 45262d756322SRob Clark } 45272d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 45282d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 45292d756322SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 45302d756322SRob Clark { 45312d756322SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 45322d756322SRob Clark } 45332d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000 45342d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000 45352d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000 45362d756322SRob Clark 4537a69c5ed2SRob Clark #define REG_A6XX_SP_UNKNOWN_A982 0x0000a982 4538a69c5ed2SRob Clark 45392d756322SRob Clark #define REG_A6XX_SP_FS_OBJ_START_LO 0x0000a983 45402d756322SRob Clark 45412d756322SRob Clark #define REG_A6XX_SP_FS_OBJ_START_HI 0x0000a984 45422d756322SRob Clark 45432d756322SRob Clark #define REG_A6XX_SP_BLEND_CNTL 0x0000a989 45442d756322SRob Clark #define A6XX_SP_BLEND_CNTL_ENABLED 0x00000001 45452d756322SRob Clark #define A6XX_SP_BLEND_CNTL_UNK8 0x00000100 4546ccdf7e28SRob Clark #define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 45472d756322SRob Clark 45482d756322SRob Clark #define REG_A6XX_SP_SRGB_CNTL 0x0000a98a 45492d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT0 0x00000001 45502d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT1 0x00000002 45512d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT2 0x00000004 45522d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT3 0x00000008 45532d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT4 0x00000010 45542d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT5 0x00000020 45552d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT6 0x00000040 45562d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT7 0x00000080 45572d756322SRob Clark 45582d756322SRob Clark #define REG_A6XX_SP_FS_RENDER_COMPONENTS 0x0000a98b 45592d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK 0x0000000f 45602d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT 0 45612d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val) 45622d756322SRob Clark { 45632d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK; 45642d756322SRob Clark } 45652d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK 0x000000f0 45662d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT 4 45672d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val) 45682d756322SRob Clark { 45692d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK; 45702d756322SRob Clark } 45712d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK 0x00000f00 45722d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT 8 45732d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val) 45742d756322SRob Clark { 45752d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK; 45762d756322SRob Clark } 45772d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK 0x0000f000 45782d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT 12 45792d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val) 45802d756322SRob Clark { 45812d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK; 45822d756322SRob Clark } 45832d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK 0x000f0000 45842d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT 16 45852d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val) 45862d756322SRob Clark { 45872d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK; 45882d756322SRob Clark } 45892d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK 0x00f00000 45902d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT 20 45912d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val) 45922d756322SRob Clark { 45932d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK; 45942d756322SRob Clark } 45952d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK 0x0f000000 45962d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT 24 45972d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val) 45982d756322SRob Clark { 45992d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK; 46002d756322SRob Clark } 46012d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK 0xf0000000 46022d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT 28 46032d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val) 46042d756322SRob Clark { 46052d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK; 46062d756322SRob Clark } 46072d756322SRob Clark 46082d756322SRob Clark #define REG_A6XX_SP_FS_OUTPUT_CNTL0 0x0000a98c 46092d756322SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK 0x0000ff00 46102d756322SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT 8 46112d756322SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val) 46122d756322SRob Clark { 46132d756322SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK; 46142d756322SRob Clark } 46152d756322SRob Clark 46162d756322SRob Clark #define REG_A6XX_SP_FS_OUTPUT_CNTL1 0x0000a98d 46172d756322SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f 46182d756322SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT 0 46192d756322SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val) 46202d756322SRob Clark { 46212d756322SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK; 46222d756322SRob Clark } 46232d756322SRob Clark 46242d756322SRob Clark static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; } 46252d756322SRob Clark 46262d756322SRob Clark static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; } 46272d756322SRob Clark #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff 46282d756322SRob Clark #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0 46292d756322SRob Clark static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_color_fmt val) 46302d756322SRob Clark { 46312d756322SRob Clark return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK; 46322d756322SRob Clark } 46332d756322SRob Clark #define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100 46342d756322SRob Clark #define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200 4635a69c5ed2SRob Clark 4636a69c5ed2SRob Clark #define REG_A6XX_SP_UNKNOWN_A99E 0x0000a99e 46372d756322SRob Clark 46382d756322SRob Clark #define REG_A6XX_SP_FS_TEX_COUNT 0x0000a9a7 46392d756322SRob Clark 46402d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8 46412d756322SRob Clark 46422d756322SRob Clark #define REG_A6XX_SP_FS_TEX_SAMP_LO 0x0000a9e0 46432d756322SRob Clark 46442d756322SRob Clark #define REG_A6XX_SP_FS_TEX_SAMP_HI 0x0000a9e1 46452d756322SRob Clark 46462d756322SRob Clark #define REG_A6XX_SP_CS_TEX_SAMP_LO 0x0000a9e2 46472d756322SRob Clark 46482d756322SRob Clark #define REG_A6XX_SP_CS_TEX_SAMP_HI 0x0000a9e3 46492d756322SRob Clark 46502d756322SRob Clark #define REG_A6XX_SP_FS_TEX_CONST_LO 0x0000a9e4 46512d756322SRob Clark 46522d756322SRob Clark #define REG_A6XX_SP_FS_TEX_CONST_HI 0x0000a9e5 46532d756322SRob Clark 46542d756322SRob Clark #define REG_A6XX_SP_CS_TEX_CONST_LO 0x0000a9e6 46552d756322SRob Clark 46562d756322SRob Clark #define REG_A6XX_SP_CS_TEX_CONST_HI 0x0000a9e7 46572d756322SRob Clark 46582d756322SRob Clark static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; } 46592d756322SRob Clark 46602d756322SRob Clark static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; } 46612d756322SRob Clark #define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff 46622d756322SRob Clark #define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0 46632d756322SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) 46642d756322SRob Clark { 46652d756322SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK; 46662d756322SRob Clark } 46672d756322SRob Clark #define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100 46682d756322SRob Clark 46692d756322SRob Clark #define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0 46702d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 46712d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 46722d756322SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 46732d756322SRob Clark { 46742d756322SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 46752d756322SRob Clark } 46762d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 46772d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 46782d756322SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 46792d756322SRob Clark { 46802d756322SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 46812d756322SRob Clark } 46822d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 46832d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 14 46842d756322SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val) 46852d756322SRob Clark { 46862d756322SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK; 46872d756322SRob Clark } 46882d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000 46892d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20 46902d756322SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 46912d756322SRob Clark { 46922d756322SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK; 46932d756322SRob Clark } 46942d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_VARYING 0x00400000 46952d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x04000000 46962d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000 46972d756322SRob Clark 46982d756322SRob Clark #define REG_A6XX_SP_CS_OBJ_START_LO 0x0000a9b4 46992d756322SRob Clark 47002d756322SRob Clark #define REG_A6XX_SP_CS_OBJ_START_HI 0x0000a9b5 47012d756322SRob Clark 47022d756322SRob Clark #define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc 47032d756322SRob Clark 47042d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_AB00 0x0000ab00 47052d756322SRob Clark 47062d756322SRob Clark #define REG_A6XX_SP_FS_CONFIG 0x0000ab04 47072d756322SRob Clark #define A6XX_SP_FS_CONFIG_ENABLED 0x00000100 47082d756322SRob Clark #define A6XX_SP_FS_CONFIG_NTEX__MASK 0x0001fe00 47092d756322SRob Clark #define A6XX_SP_FS_CONFIG_NTEX__SHIFT 9 47102d756322SRob Clark static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val) 47112d756322SRob Clark { 47122d756322SRob Clark return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK; 47132d756322SRob Clark } 47142d756322SRob Clark #define A6XX_SP_FS_CONFIG_NSAMP__MASK 0x01fe0000 47152d756322SRob Clark #define A6XX_SP_FS_CONFIG_NSAMP__SHIFT 17 47162d756322SRob Clark static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val) 47172d756322SRob Clark { 47182d756322SRob Clark return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK; 47192d756322SRob Clark } 47202d756322SRob Clark 47212d756322SRob Clark #define REG_A6XX_SP_FS_INSTRLEN 0x0000ab05 47222d756322SRob Clark 4723a69c5ed2SRob Clark #define REG_A6XX_SP_UNKNOWN_AB20 0x0000ab20 4724a69c5ed2SRob Clark 4725ccdf7e28SRob Clark #define REG_A6XX_SP_UNKNOWN_ACC0 0x0000acc0 4726ccdf7e28SRob Clark 47272d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_AE00 0x0000ae00 47282d756322SRob Clark 4729a69c5ed2SRob Clark #define REG_A6XX_SP_UNKNOWN_AE03 0x0000ae03 4730a69c5ed2SRob Clark 47312d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_AE04 0x0000ae04 47322d756322SRob Clark 47332d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_AE0F 0x0000ae0f 47342d756322SRob Clark 47352d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_B182 0x0000b182 47362d756322SRob Clark 4737a69c5ed2SRob Clark #define REG_A6XX_SP_UNKNOWN_B183 0x0000b183 4738a69c5ed2SRob Clark 47392d756322SRob Clark #define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300 47402d756322SRob Clark #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 47412d756322SRob Clark #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 47422d756322SRob Clark static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 47432d756322SRob Clark { 47442d756322SRob Clark return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK; 47452d756322SRob Clark } 47462d756322SRob Clark 47472d756322SRob Clark #define REG_A6XX_SP_TP_DEST_MSAA_CNTL 0x0000b301 47482d756322SRob Clark #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 47492d756322SRob Clark #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 47502d756322SRob Clark static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 47512d756322SRob Clark { 47522d756322SRob Clark return ((val) << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK; 47532d756322SRob Clark } 47542d756322SRob Clark #define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 47552d756322SRob Clark 47562d756322SRob Clark #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO 0x0000b302 47572d756322SRob Clark 47582d756322SRob Clark #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_HI 0x0000b303 47592d756322SRob Clark 47602d756322SRob Clark #define REG_A6XX_SP_TP_UNKNOWN_B304 0x0000b304 47612d756322SRob Clark 4762a69c5ed2SRob Clark #define REG_A6XX_SP_TP_UNKNOWN_B309 0x0000b309 4763a69c5ed2SRob Clark 47642d756322SRob Clark #define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0 47652d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff 47662d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 47672d756322SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) 47682d756322SRob Clark { 47692d756322SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK; 47702d756322SRob Clark } 47712d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300 47722d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT 8 47732d756322SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val) 47742d756322SRob Clark { 47752d756322SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK; 47762d756322SRob Clark } 47772d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00 47782d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10 47792d756322SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) 47802d756322SRob Clark { 47812d756322SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK; 47822d756322SRob Clark } 47832d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000 4784ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000 4785ccdf7e28SRob Clark 4786ccdf7e28SRob Clark #define REG_A6XX_SP_PS_2D_SRC_SIZE 0x0000b4c1 4787ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff 4788ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT 0 4789ccdf7e28SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val) 4790ccdf7e28SRob Clark { 4791ccdf7e28SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK; 4792ccdf7e28SRob Clark } 4793ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK 0x3fff8000 4794ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT 15 4795ccdf7e28SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val) 4796ccdf7e28SRob Clark { 4797ccdf7e28SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK; 4798ccdf7e28SRob Clark } 47992d756322SRob Clark 48002d756322SRob Clark #define REG_A6XX_SP_PS_2D_SRC_LO 0x0000b4c2 48012d756322SRob Clark 48022d756322SRob Clark #define REG_A6XX_SP_PS_2D_SRC_HI 0x0000b4c3 48032d756322SRob Clark 4804ccdf7e28SRob Clark #define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4 4805ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x01fffe00 4806ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9 4807ccdf7e28SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val) 4808ccdf7e28SRob Clark { 4809ccdf7e28SRob Clark return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK; 4810ccdf7e28SRob Clark } 4811ccdf7e28SRob Clark 48122d756322SRob Clark #define REG_A6XX_SP_PS_2D_SRC_FLAGS_LO 0x0000b4ca 48132d756322SRob Clark 48142d756322SRob Clark #define REG_A6XX_SP_PS_2D_SRC_FLAGS_HI 0x0000b4cb 48152d756322SRob Clark 48162d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_B600 0x0000b600 48172d756322SRob Clark 48182d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_B605 0x0000b605 48192d756322SRob Clark 48202d756322SRob Clark #define REG_A6XX_HLSQ_VS_CNTL 0x0000b800 48212d756322SRob Clark #define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff 48222d756322SRob Clark #define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0 48232d756322SRob Clark static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val) 48242d756322SRob Clark { 48252d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK; 48262d756322SRob Clark } 48272d756322SRob Clark 48282d756322SRob Clark #define REG_A6XX_HLSQ_HS_CNTL 0x0000b801 48292d756322SRob Clark #define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff 48302d756322SRob Clark #define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0 48312d756322SRob Clark static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val) 48322d756322SRob Clark { 48332d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK; 48342d756322SRob Clark } 48352d756322SRob Clark 48362d756322SRob Clark #define REG_A6XX_HLSQ_DS_CNTL 0x0000b802 48372d756322SRob Clark #define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff 48382d756322SRob Clark #define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0 48392d756322SRob Clark static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val) 48402d756322SRob Clark { 48412d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK; 48422d756322SRob Clark } 48432d756322SRob Clark 48442d756322SRob Clark #define REG_A6XX_HLSQ_GS_CNTL 0x0000b803 48452d756322SRob Clark #define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff 48462d756322SRob Clark #define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0 48472d756322SRob Clark static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val) 48482d756322SRob Clark { 48492d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK; 48502d756322SRob Clark } 48512d756322SRob Clark 4852a69c5ed2SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_B980 0x0000b980 4853a69c5ed2SRob Clark 48542d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982 48552d756322SRob Clark 48562d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_2_REG 0x0000b983 48572d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff 48582d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0 48592d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) 48602d756322SRob Clark { 48612d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; 48622d756322SRob Clark } 48632d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00 48642d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8 48652d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) 48662d756322SRob Clark { 48672d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK; 48682d756322SRob Clark } 48692d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000 48702d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16 48712d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) 48722d756322SRob Clark { 48732d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK; 48742d756322SRob Clark } 48752d756322SRob Clark 48762d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_3_REG 0x0000b984 48772d756322SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK 0x000000ff 48782d756322SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT 0 48792d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val) 48802d756322SRob Clark { 48812d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK; 48822d756322SRob Clark } 48832d756322SRob Clark 48842d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_4_REG 0x0000b985 48852d756322SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000 48862d756322SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16 48872d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) 48882d756322SRob Clark { 48892d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK; 48902d756322SRob Clark } 48912d756322SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000 48922d756322SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24 48932d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) 48942d756322SRob Clark { 48952d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; 48962d756322SRob Clark } 48972d756322SRob Clark 48982d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986 48992d756322SRob Clark 49002d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_0 0x0000b990 49012d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003 49022d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0 49032d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) 49042d756322SRob Clark { 49052d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK; 49062d756322SRob Clark } 49072d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc 49082d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2 49092d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) 49102d756322SRob Clark { 49112d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK; 49122d756322SRob Clark } 49132d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000 49142d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12 49152d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) 49162d756322SRob Clark { 49172d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK; 49182d756322SRob Clark } 49192d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000 49202d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22 49212d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) 49222d756322SRob Clark { 49232d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK; 49242d756322SRob Clark } 49252d756322SRob Clark 49262d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_1 0x0000b991 49272d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff 49282d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0 49292d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val) 49302d756322SRob Clark { 49312d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK; 49322d756322SRob Clark } 49332d756322SRob Clark 49342d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_2 0x0000b992 49352d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff 49362d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0 49372d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val) 49382d756322SRob Clark { 49392d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK; 49402d756322SRob Clark } 49412d756322SRob Clark 49422d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_3 0x0000b993 49432d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff 49442d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0 49452d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val) 49462d756322SRob Clark { 49472d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK; 49482d756322SRob Clark } 49492d756322SRob Clark 49502d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_4 0x0000b994 49512d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff 49522d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0 49532d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val) 49542d756322SRob Clark { 49552d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK; 49562d756322SRob Clark } 49572d756322SRob Clark 49582d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_5 0x0000b995 49592d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff 49602d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0 49612d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val) 49622d756322SRob Clark { 49632d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK; 49642d756322SRob Clark } 49652d756322SRob Clark 49662d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_6 0x0000b996 49672d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff 49682d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0 49692d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val) 49702d756322SRob Clark { 49712d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK; 49722d756322SRob Clark } 49732d756322SRob Clark 49742d756322SRob Clark #define REG_A6XX_HLSQ_CS_CNTL_0 0x0000b997 49752d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff 49762d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0 49772d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val) 49782d756322SRob Clark { 49792d756322SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK; 49802d756322SRob Clark } 49812d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_UNK0__MASK 0x0000ff00 49822d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT 8 49832d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val) 49842d756322SRob Clark { 49852d756322SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK0__MASK; 49862d756322SRob Clark } 49872d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_UNK1__MASK 0x00ff0000 49882d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT 16 49892d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val) 49902d756322SRob Clark { 49912d756322SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK1__MASK; 49922d756322SRob Clark } 49932d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000 49942d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24 49952d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) 49962d756322SRob Clark { 49972d756322SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK; 49982d756322SRob Clark } 49992d756322SRob Clark 50002d756322SRob Clark #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X 0x0000b999 50012d756322SRob Clark 50022d756322SRob Clark #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000b99a 50032d756322SRob Clark 50042d756322SRob Clark #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000b99b 50052d756322SRob Clark 50062d756322SRob Clark #define REG_A6XX_HLSQ_UPDATE_CNTL 0x0000bb08 50072d756322SRob Clark 50082d756322SRob Clark #define REG_A6XX_HLSQ_FS_CNTL 0x0000bb10 50092d756322SRob Clark #define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff 50102d756322SRob Clark #define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0 50112d756322SRob Clark static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val) 50122d756322SRob Clark { 50132d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK; 50142d756322SRob Clark } 50152d756322SRob Clark 50162d756322SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_BB11 0x0000bb11 50172d756322SRob Clark 50182d756322SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_BE00 0x0000be00 50192d756322SRob Clark 50202d756322SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_BE01 0x0000be01 50212d756322SRob Clark 50222d756322SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_BE04 0x0000be04 50232d756322SRob Clark 50242d756322SRob Clark #define REG_A6XX_TEX_SAMP_0 0x00000000 50252d756322SRob Clark #define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 50262d756322SRob Clark #define A6XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 50272d756322SRob Clark #define A6XX_TEX_SAMP_0_XY_MAG__SHIFT 1 50282d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val) 50292d756322SRob Clark { 50302d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_XY_MAG__SHIFT) & A6XX_TEX_SAMP_0_XY_MAG__MASK; 50312d756322SRob Clark } 50322d756322SRob Clark #define A6XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 50332d756322SRob Clark #define A6XX_TEX_SAMP_0_XY_MIN__SHIFT 3 50342d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val) 50352d756322SRob Clark { 50362d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_XY_MIN__SHIFT) & A6XX_TEX_SAMP_0_XY_MIN__MASK; 50372d756322SRob Clark } 50382d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 50392d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_S__SHIFT 5 50402d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val) 50412d756322SRob Clark { 50422d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_WRAP_S__SHIFT) & A6XX_TEX_SAMP_0_WRAP_S__MASK; 50432d756322SRob Clark } 50442d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 50452d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_T__SHIFT 8 50462d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val) 50472d756322SRob Clark { 50482d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_WRAP_T__SHIFT) & A6XX_TEX_SAMP_0_WRAP_T__MASK; 50492d756322SRob Clark } 50502d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 50512d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_R__SHIFT 11 50522d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val) 50532d756322SRob Clark { 50542d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_WRAP_R__SHIFT) & A6XX_TEX_SAMP_0_WRAP_R__MASK; 50552d756322SRob Clark } 50562d756322SRob Clark #define A6XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 50572d756322SRob Clark #define A6XX_TEX_SAMP_0_ANISO__SHIFT 14 50582d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val) 50592d756322SRob Clark { 50602d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_ANISO__SHIFT) & A6XX_TEX_SAMP_0_ANISO__MASK; 50612d756322SRob Clark } 50622d756322SRob Clark #define A6XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000 50632d756322SRob Clark #define A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19 50642d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val) 50652d756322SRob Clark { 50662d756322SRob Clark return ((((int32_t)(val * 256.0))) << A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A6XX_TEX_SAMP_0_LOD_BIAS__MASK; 50672d756322SRob Clark } 50682d756322SRob Clark 50692d756322SRob Clark #define REG_A6XX_TEX_SAMP_1 0x00000001 50702d756322SRob Clark #define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e 50712d756322SRob Clark #define A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 50722d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) 50732d756322SRob Clark { 50742d756322SRob Clark return ((val) << A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK; 50752d756322SRob Clark } 50762d756322SRob Clark #define A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010 50772d756322SRob Clark #define A6XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 50782d756322SRob Clark #define A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 50792d756322SRob Clark #define A6XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 50802d756322SRob Clark #define A6XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 50812d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_1_MAX_LOD(float val) 50822d756322SRob Clark { 50832d756322SRob Clark return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK; 50842d756322SRob Clark } 50852d756322SRob Clark #define A6XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 50862d756322SRob Clark #define A6XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 50872d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_1_MIN_LOD(float val) 50882d756322SRob Clark { 50892d756322SRob Clark return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK; 50902d756322SRob Clark } 50912d756322SRob Clark 50922d756322SRob Clark #define REG_A6XX_TEX_SAMP_2 0x00000002 50932d756322SRob Clark #define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xfffffff0 50942d756322SRob Clark #define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 4 50952d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val) 50962d756322SRob Clark { 50972d756322SRob Clark return ((val) << A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK; 50982d756322SRob Clark } 50992d756322SRob Clark 51002d756322SRob Clark #define REG_A6XX_TEX_SAMP_3 0x00000003 51012d756322SRob Clark 51022d756322SRob Clark #define REG_A6XX_TEX_CONST_0 0x00000000 51032d756322SRob Clark #define A6XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003 51042d756322SRob Clark #define A6XX_TEX_CONST_0_TILE_MODE__SHIFT 0 51052d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val) 51062d756322SRob Clark { 51072d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_TILE_MODE__SHIFT) & A6XX_TEX_CONST_0_TILE_MODE__MASK; 51082d756322SRob Clark } 51092d756322SRob Clark #define A6XX_TEX_CONST_0_SRGB 0x00000004 51102d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 51112d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_X__SHIFT 4 51122d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val) 51132d756322SRob Clark { 51142d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWIZ_X__SHIFT) & A6XX_TEX_CONST_0_SWIZ_X__MASK; 51152d756322SRob Clark } 51162d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 51172d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 51182d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val) 51192d756322SRob Clark { 51202d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Y__MASK; 51212d756322SRob Clark } 51222d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 51232d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 51242d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val) 51252d756322SRob Clark { 51262d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Z__MASK; 51272d756322SRob Clark } 51282d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 51292d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_W__SHIFT 13 51302d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val) 51312d756322SRob Clark { 51322d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWIZ_W__SHIFT) & A6XX_TEX_CONST_0_SWIZ_W__MASK; 51332d756322SRob Clark } 51342d756322SRob Clark #define A6XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 51352d756322SRob Clark #define A6XX_TEX_CONST_0_MIPLVLS__SHIFT 16 51362d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val) 51372d756322SRob Clark { 51382d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK; 51392d756322SRob Clark } 5140ccdf7e28SRob Clark #define A6XX_TEX_CONST_0_SAMPLES__MASK 0x00300000 5141ccdf7e28SRob Clark #define A6XX_TEX_CONST_0_SAMPLES__SHIFT 20 5142ccdf7e28SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val) 5143ccdf7e28SRob Clark { 5144ccdf7e28SRob Clark return ((val) << A6XX_TEX_CONST_0_SAMPLES__SHIFT) & A6XX_TEX_CONST_0_SAMPLES__MASK; 5145ccdf7e28SRob Clark } 51462d756322SRob Clark #define A6XX_TEX_CONST_0_FMT__MASK 0x3fc00000 51472d756322SRob Clark #define A6XX_TEX_CONST_0_FMT__SHIFT 22 51482d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_tex_fmt val) 51492d756322SRob Clark { 51502d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK; 51512d756322SRob Clark } 51522d756322SRob Clark #define A6XX_TEX_CONST_0_SWAP__MASK 0xc0000000 51532d756322SRob Clark #define A6XX_TEX_CONST_0_SWAP__SHIFT 30 51542d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val) 51552d756322SRob Clark { 51562d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWAP__SHIFT) & A6XX_TEX_CONST_0_SWAP__MASK; 51572d756322SRob Clark } 51582d756322SRob Clark 51592d756322SRob Clark #define REG_A6XX_TEX_CONST_1 0x00000001 51602d756322SRob Clark #define A6XX_TEX_CONST_1_WIDTH__MASK 0x00007fff 51612d756322SRob Clark #define A6XX_TEX_CONST_1_WIDTH__SHIFT 0 51622d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_1_WIDTH(uint32_t val) 51632d756322SRob Clark { 51642d756322SRob Clark return ((val) << A6XX_TEX_CONST_1_WIDTH__SHIFT) & A6XX_TEX_CONST_1_WIDTH__MASK; 51652d756322SRob Clark } 51662d756322SRob Clark #define A6XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000 51672d756322SRob Clark #define A6XX_TEX_CONST_1_HEIGHT__SHIFT 15 51682d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val) 51692d756322SRob Clark { 51702d756322SRob Clark return ((val) << A6XX_TEX_CONST_1_HEIGHT__SHIFT) & A6XX_TEX_CONST_1_HEIGHT__MASK; 51712d756322SRob Clark } 51722d756322SRob Clark 51732d756322SRob Clark #define REG_A6XX_TEX_CONST_2 0x00000002 51742d756322SRob Clark #define A6XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f 51752d756322SRob Clark #define A6XX_TEX_CONST_2_FETCHSIZE__SHIFT 0 51762d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_2_FETCHSIZE(enum a6xx_tex_fetchsize val) 51772d756322SRob Clark { 51782d756322SRob Clark return ((val) << A6XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A6XX_TEX_CONST_2_FETCHSIZE__MASK; 51792d756322SRob Clark } 51802d756322SRob Clark #define A6XX_TEX_CONST_2_PITCH__MASK 0x1fffff80 51812d756322SRob Clark #define A6XX_TEX_CONST_2_PITCH__SHIFT 7 51822d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_2_PITCH(uint32_t val) 51832d756322SRob Clark { 51842d756322SRob Clark return ((val) << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK; 51852d756322SRob Clark } 51862d756322SRob Clark #define A6XX_TEX_CONST_2_TYPE__MASK 0x60000000 51872d756322SRob Clark #define A6XX_TEX_CONST_2_TYPE__SHIFT 29 51882d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val) 51892d756322SRob Clark { 51902d756322SRob Clark return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK; 51912d756322SRob Clark } 51922d756322SRob Clark 51932d756322SRob Clark #define REG_A6XX_TEX_CONST_3 0x00000003 51942d756322SRob Clark #define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff 51952d756322SRob Clark #define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0 51962d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) 51972d756322SRob Clark { 51982d756322SRob Clark return ((val >> 12) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK; 51992d756322SRob Clark } 52002d756322SRob Clark #define A6XX_TEX_CONST_3_FLAG 0x10000000 52012d756322SRob Clark 52022d756322SRob Clark #define REG_A6XX_TEX_CONST_4 0x00000004 52032d756322SRob Clark #define A6XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0 52042d756322SRob Clark #define A6XX_TEX_CONST_4_BASE_LO__SHIFT 5 52052d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val) 52062d756322SRob Clark { 52072d756322SRob Clark return ((val >> 5) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK; 52082d756322SRob Clark } 52092d756322SRob Clark 52102d756322SRob Clark #define REG_A6XX_TEX_CONST_5 0x00000005 52112d756322SRob Clark #define A6XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff 52122d756322SRob Clark #define A6XX_TEX_CONST_5_BASE_HI__SHIFT 0 52132d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_5_BASE_HI(uint32_t val) 52142d756322SRob Clark { 52152d756322SRob Clark return ((val) << A6XX_TEX_CONST_5_BASE_HI__SHIFT) & A6XX_TEX_CONST_5_BASE_HI__MASK; 52162d756322SRob Clark } 52172d756322SRob Clark #define A6XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000 52182d756322SRob Clark #define A6XX_TEX_CONST_5_DEPTH__SHIFT 17 52192d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_5_DEPTH(uint32_t val) 52202d756322SRob Clark { 52212d756322SRob Clark return ((val) << A6XX_TEX_CONST_5_DEPTH__SHIFT) & A6XX_TEX_CONST_5_DEPTH__MASK; 52222d756322SRob Clark } 52232d756322SRob Clark 52242d756322SRob Clark #define REG_A6XX_TEX_CONST_6 0x00000006 52252d756322SRob Clark 52262d756322SRob Clark #define REG_A6XX_TEX_CONST_7 0x00000007 52272d756322SRob Clark #define A6XX_TEX_CONST_7_FLAG_LO__MASK 0xffffffe0 52282d756322SRob Clark #define A6XX_TEX_CONST_7_FLAG_LO__SHIFT 5 52292d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val) 52302d756322SRob Clark { 52312d756322SRob Clark return ((val >> 5) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK; 52322d756322SRob Clark } 52332d756322SRob Clark 52342d756322SRob Clark #define REG_A6XX_TEX_CONST_8 0x00000008 5235a69c5ed2SRob Clark #define A6XX_TEX_CONST_8_FLAG_HI__MASK 0x0001ffff 5236a69c5ed2SRob Clark #define A6XX_TEX_CONST_8_FLAG_HI__SHIFT 0 5237a69c5ed2SRob Clark static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val) 52382d756322SRob Clark { 5239a69c5ed2SRob Clark return ((val) << A6XX_TEX_CONST_8_FLAG_HI__SHIFT) & A6XX_TEX_CONST_8_FLAG_HI__MASK; 52402d756322SRob Clark } 52412d756322SRob Clark 52422d756322SRob Clark #define REG_A6XX_TEX_CONST_9 0x00000009 52432d756322SRob Clark 52442d756322SRob Clark #define REG_A6XX_TEX_CONST_10 0x0000000a 52452d756322SRob Clark 52462d756322SRob Clark #define REG_A6XX_TEX_CONST_11 0x0000000b 52472d756322SRob Clark 52482d756322SRob Clark #define REG_A6XX_TEX_CONST_12 0x0000000c 52492d756322SRob Clark 52502d756322SRob Clark #define REG_A6XX_TEX_CONST_13 0x0000000d 52512d756322SRob Clark 52522d756322SRob Clark #define REG_A6XX_TEX_CONST_14 0x0000000e 52532d756322SRob Clark 52542d756322SRob Clark #define REG_A6XX_TEX_CONST_15 0x0000000f 52552d756322SRob Clark 5256a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_ENABLE_PDC 0x00001140 5257a69c5ed2SRob Clark 5258a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_SEQ_START_ADDR 0x00001148 5259a69c5ed2SRob Clark 5260a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CONTROL 0x00001540 5261a69c5ed2SRob Clark 5262a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK 0x00001541 5263a69c5ed2SRob Clark 5264a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK 0x00001542 5265a69c5ed2SRob Clark 5266a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID 0x00001543 5267a69c5ed2SRob Clark 5268a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR 0x00001544 5269a69c5ed2SRob Clark 5270a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA 0x00001545 5271a69c5ed2SRob Clark 5272a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CONTROL 0x00001572 5273a69c5ed2SRob Clark 5274a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK 0x00001573 5275a69c5ed2SRob Clark 5276a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK 0x00001574 5277a69c5ed2SRob Clark 5278a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID 0x00001575 5279a69c5ed2SRob Clark 5280a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR 0x00001576 5281a69c5ed2SRob Clark 5282a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA 0x00001577 5283a69c5ed2SRob Clark 5284a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CONTROL 0x000015a4 5285a69c5ed2SRob Clark 5286a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK 0x000015a5 5287a69c5ed2SRob Clark 5288a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK 0x000015a6 5289a69c5ed2SRob Clark 5290a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID 0x000015a7 5291a69c5ed2SRob Clark 5292a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR 0x000015a8 5293a69c5ed2SRob Clark 5294a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA 0x000015a9 5295a69c5ed2SRob Clark 5296a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CONTROL 0x000015d6 5297a69c5ed2SRob Clark 5298a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK 0x000015d7 5299a69c5ed2SRob Clark 5300a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK 0x000015d8 5301a69c5ed2SRob Clark 5302a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID 0x000015d9 5303a69c5ed2SRob Clark 5304a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR 0x000015da 5305a69c5ed2SRob Clark 5306a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA 0x000015db 5307a69c5ed2SRob Clark 5308a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x00000000 5309a69c5ed2SRob Clark 5310a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A 0x00000000 5311a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK 0x000000ff 5312a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT 0 5313a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val) 5314a69c5ed2SRob Clark { 5315a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK; 5316a69c5ed2SRob Clark } 5317a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK 0x0000ff00 5318a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT 8 5319a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val) 5320a69c5ed2SRob Clark { 5321a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK; 5322a69c5ed2SRob Clark } 5323a69c5ed2SRob Clark 5324a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B 0x00000001 5325a69c5ed2SRob Clark 5326a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C 0x00000002 5327a69c5ed2SRob Clark 5328a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D 0x00000003 5329a69c5ed2SRob Clark 5330a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT 0x00000004 5331a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f 5332a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0 5333a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) 5334a69c5ed2SRob Clark { 5335a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; 5336a69c5ed2SRob Clark } 5337a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000 5338a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12 5339a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) 5340a69c5ed2SRob Clark { 5341a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; 5342a69c5ed2SRob Clark } 5343a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000 5344a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28 5345a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) 5346a69c5ed2SRob Clark { 5347a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; 5348a69c5ed2SRob Clark } 5349a69c5ed2SRob Clark 5350a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM 0x00000005 5351a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000 5352a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24 5353a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) 5354a69c5ed2SRob Clark { 5355a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; 5356a69c5ed2SRob Clark } 5357a69c5ed2SRob Clark 5358a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 0x00000008 5359a69c5ed2SRob Clark 5360a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 0x00000009 5361a69c5ed2SRob Clark 5362a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 0x0000000a 5363a69c5ed2SRob Clark 5364a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 0x0000000b 5365a69c5ed2SRob Clark 5366a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 0x0000000c 5367a69c5ed2SRob Clark 5368a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 0x0000000d 5369a69c5ed2SRob Clark 5370a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 0x0000000e 5371a69c5ed2SRob Clark 5372a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 0x0000000f 5373a69c5ed2SRob Clark 5374a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000010 5375a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f 5376a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0 5377a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) 5378a69c5ed2SRob Clark { 5379a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; 5380a69c5ed2SRob Clark } 5381a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0 5382a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4 5383a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) 5384a69c5ed2SRob Clark { 5385a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; 5386a69c5ed2SRob Clark } 5387a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00 5388a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8 5389a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) 5390a69c5ed2SRob Clark { 5391a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; 5392a69c5ed2SRob Clark } 5393a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000 5394a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12 5395a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) 5396a69c5ed2SRob Clark { 5397a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; 5398a69c5ed2SRob Clark } 5399a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000 5400a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16 5401a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) 5402a69c5ed2SRob Clark { 5403a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; 5404a69c5ed2SRob Clark } 5405a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000 5406a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20 5407a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) 5408a69c5ed2SRob Clark { 5409a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; 5410a69c5ed2SRob Clark } 5411a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000 5412a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24 5413a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) 5414a69c5ed2SRob Clark { 5415a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; 5416a69c5ed2SRob Clark } 5417a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000 5418a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28 5419a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) 5420a69c5ed2SRob Clark { 5421a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; 5422a69c5ed2SRob Clark } 5423a69c5ed2SRob Clark 5424a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000011 5425a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f 5426a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0 5427a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) 5428a69c5ed2SRob Clark { 5429a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; 5430a69c5ed2SRob Clark } 5431a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0 5432a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4 5433a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) 5434a69c5ed2SRob Clark { 5435a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; 5436a69c5ed2SRob Clark } 5437a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00 5438a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8 5439a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) 5440a69c5ed2SRob Clark { 5441a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; 5442a69c5ed2SRob Clark } 5443a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000 5444a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12 5445a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) 5446a69c5ed2SRob Clark { 5447a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; 5448a69c5ed2SRob Clark } 5449a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000 5450a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16 5451a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) 5452a69c5ed2SRob Clark { 5453a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; 5454a69c5ed2SRob Clark } 5455a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000 5456a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20 5457a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) 5458a69c5ed2SRob Clark { 5459a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; 5460a69c5ed2SRob Clark } 5461a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000 5462a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24 5463a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) 5464a69c5ed2SRob Clark { 5465a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; 5466a69c5ed2SRob Clark } 5467a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000 5468a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28 5469a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) 5470a69c5ed2SRob Clark { 5471a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; 5472a69c5ed2SRob Clark } 5473a69c5ed2SRob Clark 5474a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000002f 5475a69c5ed2SRob Clark 5476a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000030 5477a69c5ed2SRob Clark 5478ccdf7e28SRob Clark #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 0x00000001 5479ccdf7e28SRob Clark 5480ccdf7e28SRob Clark #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 0x00000002 5481ccdf7e28SRob Clark 54822d756322SRob Clark 54832d756322SRob Clark #endif /* A6XX_XML */ 5484