12d756322SRob Clark #ifndef A6XX_XML 22d756322SRob Clark #define A6XX_XML 32d756322SRob Clark 42d756322SRob Clark /* Autogenerated file, DO NOT EDIT manually! 52d756322SRob Clark 62d756322SRob Clark This file was generated by the rules-ng-ng headergen tool in this git repository: 72d756322SRob Clark http://github.com/freedreno/envytools/ 82d756322SRob Clark git clone https://github.com/freedreno/envytools.git 92d756322SRob Clark 102d756322SRob Clark The rules-ng-ng source files this header was generated from are: 11*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44) 12*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) 13*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44) 14*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44) 15*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57) 16*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44) 17*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44) 18*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02) 19*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19) 20*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08) 21*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44) 22*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36) 23*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13) 242d756322SRob Clark 25*cc4c26d4SRob Clark Copyright (C) 2013-2021 by the following authors: 262d756322SRob Clark - Rob Clark <robdclark@gmail.com> (robclark) 272d756322SRob Clark - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 282d756322SRob Clark 292d756322SRob Clark Permission is hereby granted, free of charge, to any person obtaining 302d756322SRob Clark a copy of this software and associated documentation files (the 312d756322SRob Clark "Software"), to deal in the Software without restriction, including 322d756322SRob Clark without limitation the rights to use, copy, modify, merge, publish, 332d756322SRob Clark distribute, sublicense, and/or sell copies of the Software, and to 342d756322SRob Clark permit persons to whom the Software is furnished to do so, subject to 352d756322SRob Clark the following conditions: 362d756322SRob Clark 372d756322SRob Clark The above copyright notice and this permission notice (including the 382d756322SRob Clark next paragraph) shall be included in all copies or substantial 392d756322SRob Clark portions of the Software. 402d756322SRob Clark 412d756322SRob Clark THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 422d756322SRob Clark EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 432d756322SRob Clark MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 442d756322SRob Clark IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 452d756322SRob Clark LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 462d756322SRob Clark OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 472d756322SRob Clark WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 482d756322SRob Clark */ 492d756322SRob Clark 502d756322SRob Clark 512d756322SRob Clark enum a6xx_tile_mode { 522d756322SRob Clark TILE6_LINEAR = 0, 532d756322SRob Clark TILE6_2 = 2, 542d756322SRob Clark TILE6_3 = 3, 552d756322SRob Clark }; 562d756322SRob Clark 57c28c82e9SRob Clark enum a6xx_format { 58c28c82e9SRob Clark FMT6_A8_UNORM = 2, 59c28c82e9SRob Clark FMT6_8_UNORM = 3, 60c28c82e9SRob Clark FMT6_8_SNORM = 4, 61c28c82e9SRob Clark FMT6_8_UINT = 5, 62c28c82e9SRob Clark FMT6_8_SINT = 6, 63c28c82e9SRob Clark FMT6_4_4_4_4_UNORM = 8, 64c28c82e9SRob Clark FMT6_5_5_5_1_UNORM = 10, 65c28c82e9SRob Clark FMT6_1_5_5_5_UNORM = 12, 66c28c82e9SRob Clark FMT6_5_6_5_UNORM = 14, 67c28c82e9SRob Clark FMT6_8_8_UNORM = 15, 68c28c82e9SRob Clark FMT6_8_8_SNORM = 16, 69c28c82e9SRob Clark FMT6_8_8_UINT = 17, 70c28c82e9SRob Clark FMT6_8_8_SINT = 18, 71c28c82e9SRob Clark FMT6_L8_A8_UNORM = 19, 72c28c82e9SRob Clark FMT6_16_UNORM = 21, 73c28c82e9SRob Clark FMT6_16_SNORM = 22, 74c28c82e9SRob Clark FMT6_16_FLOAT = 23, 75c28c82e9SRob Clark FMT6_16_UINT = 24, 76c28c82e9SRob Clark FMT6_16_SINT = 25, 77c28c82e9SRob Clark FMT6_8_8_8_UNORM = 33, 78c28c82e9SRob Clark FMT6_8_8_8_SNORM = 34, 79c28c82e9SRob Clark FMT6_8_8_8_UINT = 35, 80c28c82e9SRob Clark FMT6_8_8_8_SINT = 36, 81c28c82e9SRob Clark FMT6_8_8_8_8_UNORM = 48, 82c28c82e9SRob Clark FMT6_8_8_8_X8_UNORM = 49, 83c28c82e9SRob Clark FMT6_8_8_8_8_SNORM = 50, 84c28c82e9SRob Clark FMT6_8_8_8_8_UINT = 51, 85c28c82e9SRob Clark FMT6_8_8_8_8_SINT = 52, 86c28c82e9SRob Clark FMT6_9_9_9_E5_FLOAT = 53, 87c28c82e9SRob Clark FMT6_10_10_10_2_UNORM = 54, 88c28c82e9SRob Clark FMT6_10_10_10_2_UNORM_DEST = 55, 89c28c82e9SRob Clark FMT6_10_10_10_2_SNORM = 57, 90c28c82e9SRob Clark FMT6_10_10_10_2_UINT = 58, 91c28c82e9SRob Clark FMT6_10_10_10_2_SINT = 59, 92c28c82e9SRob Clark FMT6_11_11_10_FLOAT = 66, 93c28c82e9SRob Clark FMT6_16_16_UNORM = 67, 94c28c82e9SRob Clark FMT6_16_16_SNORM = 68, 95c28c82e9SRob Clark FMT6_16_16_FLOAT = 69, 96c28c82e9SRob Clark FMT6_16_16_UINT = 70, 97c28c82e9SRob Clark FMT6_16_16_SINT = 71, 98c28c82e9SRob Clark FMT6_32_UNORM = 72, 99c28c82e9SRob Clark FMT6_32_SNORM = 73, 100c28c82e9SRob Clark FMT6_32_FLOAT = 74, 101c28c82e9SRob Clark FMT6_32_UINT = 75, 102c28c82e9SRob Clark FMT6_32_SINT = 76, 103c28c82e9SRob Clark FMT6_32_FIXED = 77, 104c28c82e9SRob Clark FMT6_16_16_16_UNORM = 88, 105c28c82e9SRob Clark FMT6_16_16_16_SNORM = 89, 106c28c82e9SRob Clark FMT6_16_16_16_FLOAT = 90, 107c28c82e9SRob Clark FMT6_16_16_16_UINT = 91, 108c28c82e9SRob Clark FMT6_16_16_16_SINT = 92, 109c28c82e9SRob Clark FMT6_16_16_16_16_UNORM = 96, 110c28c82e9SRob Clark FMT6_16_16_16_16_SNORM = 97, 111c28c82e9SRob Clark FMT6_16_16_16_16_FLOAT = 98, 112c28c82e9SRob Clark FMT6_16_16_16_16_UINT = 99, 113c28c82e9SRob Clark FMT6_16_16_16_16_SINT = 100, 114c28c82e9SRob Clark FMT6_32_32_UNORM = 101, 115c28c82e9SRob Clark FMT6_32_32_SNORM = 102, 116c28c82e9SRob Clark FMT6_32_32_FLOAT = 103, 117c28c82e9SRob Clark FMT6_32_32_UINT = 104, 118c28c82e9SRob Clark FMT6_32_32_SINT = 105, 119c28c82e9SRob Clark FMT6_32_32_FIXED = 106, 120c28c82e9SRob Clark FMT6_32_32_32_UNORM = 112, 121c28c82e9SRob Clark FMT6_32_32_32_SNORM = 113, 122c28c82e9SRob Clark FMT6_32_32_32_UINT = 114, 123c28c82e9SRob Clark FMT6_32_32_32_SINT = 115, 124c28c82e9SRob Clark FMT6_32_32_32_FLOAT = 116, 125c28c82e9SRob Clark FMT6_32_32_32_FIXED = 117, 126c28c82e9SRob Clark FMT6_32_32_32_32_UNORM = 128, 127c28c82e9SRob Clark FMT6_32_32_32_32_SNORM = 129, 128c28c82e9SRob Clark FMT6_32_32_32_32_FLOAT = 130, 129c28c82e9SRob Clark FMT6_32_32_32_32_UINT = 131, 130c28c82e9SRob Clark FMT6_32_32_32_32_SINT = 132, 131c28c82e9SRob Clark FMT6_32_32_32_32_FIXED = 133, 132c28c82e9SRob Clark FMT6_G8R8B8R8_422_UNORM = 140, 133c28c82e9SRob Clark FMT6_R8G8R8B8_422_UNORM = 141, 134c28c82e9SRob Clark FMT6_R8_G8B8_2PLANE_420_UNORM = 142, 135c28c82e9SRob Clark FMT6_R8_G8_B8_3PLANE_420_UNORM = 144, 136c28c82e9SRob Clark FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 = 145, 137c28c82e9SRob Clark FMT6_8_PLANE_UNORM = 148, 138c28c82e9SRob Clark FMT6_Z24_UNORM_S8_UINT = 160, 139c28c82e9SRob Clark FMT6_ETC2_RG11_UNORM = 171, 140c28c82e9SRob Clark FMT6_ETC2_RG11_SNORM = 172, 141c28c82e9SRob Clark FMT6_ETC2_R11_UNORM = 173, 142c28c82e9SRob Clark FMT6_ETC2_R11_SNORM = 174, 143c28c82e9SRob Clark FMT6_ETC1 = 175, 144c28c82e9SRob Clark FMT6_ETC2_RGB8 = 176, 145c28c82e9SRob Clark FMT6_ETC2_RGBA8 = 177, 146c28c82e9SRob Clark FMT6_ETC2_RGB8A1 = 178, 147c28c82e9SRob Clark FMT6_DXT1 = 179, 148c28c82e9SRob Clark FMT6_DXT3 = 180, 149c28c82e9SRob Clark FMT6_DXT5 = 181, 150c28c82e9SRob Clark FMT6_RGTC1_UNORM = 183, 151c28c82e9SRob Clark FMT6_RGTC1_SNORM = 184, 152c28c82e9SRob Clark FMT6_RGTC2_UNORM = 187, 153c28c82e9SRob Clark FMT6_RGTC2_SNORM = 188, 154c28c82e9SRob Clark FMT6_BPTC_UFLOAT = 190, 155c28c82e9SRob Clark FMT6_BPTC_FLOAT = 191, 156c28c82e9SRob Clark FMT6_BPTC = 192, 157c28c82e9SRob Clark FMT6_ASTC_4x4 = 193, 158c28c82e9SRob Clark FMT6_ASTC_5x4 = 194, 159c28c82e9SRob Clark FMT6_ASTC_5x5 = 195, 160c28c82e9SRob Clark FMT6_ASTC_6x5 = 196, 161c28c82e9SRob Clark FMT6_ASTC_6x6 = 197, 162c28c82e9SRob Clark FMT6_ASTC_8x5 = 198, 163c28c82e9SRob Clark FMT6_ASTC_8x6 = 199, 164c28c82e9SRob Clark FMT6_ASTC_8x8 = 200, 165c28c82e9SRob Clark FMT6_ASTC_10x5 = 201, 166c28c82e9SRob Clark FMT6_ASTC_10x6 = 202, 167c28c82e9SRob Clark FMT6_ASTC_10x8 = 203, 168c28c82e9SRob Clark FMT6_ASTC_10x10 = 204, 169c28c82e9SRob Clark FMT6_ASTC_12x10 = 205, 170c28c82e9SRob Clark FMT6_ASTC_12x12 = 206, 171*cc4c26d4SRob Clark FMT6_Z24_UINT_S8_UINT = 234, 172c28c82e9SRob Clark FMT6_NONE = 255, 1732d756322SRob Clark }; 1742d756322SRob Clark 175c28c82e9SRob Clark enum a6xx_polygon_mode { 176c28c82e9SRob Clark POLYMODE6_POINTS = 1, 177c28c82e9SRob Clark POLYMODE6_LINES = 2, 178c28c82e9SRob Clark POLYMODE6_TRIANGLES = 3, 1792d756322SRob Clark }; 1802d756322SRob Clark 1812d756322SRob Clark enum a6xx_depth_format { 1822d756322SRob Clark DEPTH6_NONE = 0, 1832d756322SRob Clark DEPTH6_16 = 1, 1842d756322SRob Clark DEPTH6_24_8 = 2, 1852d756322SRob Clark DEPTH6_32 = 4, 1862d756322SRob Clark }; 1872d756322SRob Clark 188a69c5ed2SRob Clark enum a6xx_shader_id { 189a69c5ed2SRob Clark A6XX_TP0_TMO_DATA = 9, 190a69c5ed2SRob Clark A6XX_TP0_SMO_DATA = 10, 191a69c5ed2SRob Clark A6XX_TP0_MIPMAP_BASE_DATA = 11, 192a69c5ed2SRob Clark A6XX_TP1_TMO_DATA = 25, 193a69c5ed2SRob Clark A6XX_TP1_SMO_DATA = 26, 194a69c5ed2SRob Clark A6XX_TP1_MIPMAP_BASE_DATA = 27, 195a69c5ed2SRob Clark A6XX_SP_INST_DATA = 41, 196a69c5ed2SRob Clark A6XX_SP_LB_0_DATA = 42, 197a69c5ed2SRob Clark A6XX_SP_LB_1_DATA = 43, 198a69c5ed2SRob Clark A6XX_SP_LB_2_DATA = 44, 199a69c5ed2SRob Clark A6XX_SP_LB_3_DATA = 45, 200a69c5ed2SRob Clark A6XX_SP_LB_4_DATA = 46, 201a69c5ed2SRob Clark A6XX_SP_LB_5_DATA = 47, 202a69c5ed2SRob Clark A6XX_SP_CB_BINDLESS_DATA = 48, 203a69c5ed2SRob Clark A6XX_SP_CB_LEGACY_DATA = 49, 204a69c5ed2SRob Clark A6XX_SP_UAV_DATA = 50, 205a69c5ed2SRob Clark A6XX_SP_INST_TAG = 51, 206a69c5ed2SRob Clark A6XX_SP_CB_BINDLESS_TAG = 52, 207a69c5ed2SRob Clark A6XX_SP_TMO_UMO_TAG = 53, 208a69c5ed2SRob Clark A6XX_SP_SMO_TAG = 54, 209a69c5ed2SRob Clark A6XX_SP_STATE_DATA = 55, 210a69c5ed2SRob Clark A6XX_HLSQ_CHUNK_CVS_RAM = 73, 211a69c5ed2SRob Clark A6XX_HLSQ_CHUNK_CPS_RAM = 74, 212a69c5ed2SRob Clark A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75, 213a69c5ed2SRob Clark A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76, 214a69c5ed2SRob Clark A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77, 215a69c5ed2SRob Clark A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78, 216a69c5ed2SRob Clark A6XX_HLSQ_CVS_MISC_RAM = 80, 217a69c5ed2SRob Clark A6XX_HLSQ_CPS_MISC_RAM = 81, 218a69c5ed2SRob Clark A6XX_HLSQ_INST_RAM = 82, 219a69c5ed2SRob Clark A6XX_HLSQ_GFX_CVS_CONST_RAM = 83, 220a69c5ed2SRob Clark A6XX_HLSQ_GFX_CPS_CONST_RAM = 84, 221a69c5ed2SRob Clark A6XX_HLSQ_CVS_MISC_RAM_TAG = 85, 222a69c5ed2SRob Clark A6XX_HLSQ_CPS_MISC_RAM_TAG = 86, 223a69c5ed2SRob Clark A6XX_HLSQ_INST_RAM_TAG = 87, 224a69c5ed2SRob Clark A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88, 225a69c5ed2SRob Clark A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89, 226a69c5ed2SRob Clark A6XX_HLSQ_PWR_REST_RAM = 90, 227a69c5ed2SRob Clark A6XX_HLSQ_PWR_REST_TAG = 91, 228a69c5ed2SRob Clark A6XX_HLSQ_DATAPATH_META = 96, 229a69c5ed2SRob Clark A6XX_HLSQ_FRONTEND_META = 97, 230a69c5ed2SRob Clark A6XX_HLSQ_INDIRECT_META = 98, 231a69c5ed2SRob Clark A6XX_HLSQ_BACKEND_META = 99, 232a69c5ed2SRob Clark }; 233a69c5ed2SRob Clark 234a69c5ed2SRob Clark enum a6xx_debugbus_id { 235a69c5ed2SRob Clark A6XX_DBGBUS_CP = 1, 236a69c5ed2SRob Clark A6XX_DBGBUS_RBBM = 2, 237a69c5ed2SRob Clark A6XX_DBGBUS_VBIF = 3, 238a69c5ed2SRob Clark A6XX_DBGBUS_HLSQ = 4, 239a69c5ed2SRob Clark A6XX_DBGBUS_UCHE = 5, 240a69c5ed2SRob Clark A6XX_DBGBUS_DPM = 6, 241a69c5ed2SRob Clark A6XX_DBGBUS_TESS = 7, 242a69c5ed2SRob Clark A6XX_DBGBUS_PC = 8, 243a69c5ed2SRob Clark A6XX_DBGBUS_VFDP = 9, 244a69c5ed2SRob Clark A6XX_DBGBUS_VPC = 10, 245a69c5ed2SRob Clark A6XX_DBGBUS_TSE = 11, 246a69c5ed2SRob Clark A6XX_DBGBUS_RAS = 12, 247a69c5ed2SRob Clark A6XX_DBGBUS_VSC = 13, 248a69c5ed2SRob Clark A6XX_DBGBUS_COM = 14, 249a69c5ed2SRob Clark A6XX_DBGBUS_LRZ = 16, 250a69c5ed2SRob Clark A6XX_DBGBUS_A2D = 17, 251a69c5ed2SRob Clark A6XX_DBGBUS_CCUFCHE = 18, 252a69c5ed2SRob Clark A6XX_DBGBUS_GMU_CX = 19, 253a69c5ed2SRob Clark A6XX_DBGBUS_RBP = 20, 254a69c5ed2SRob Clark A6XX_DBGBUS_DCS = 21, 255a69c5ed2SRob Clark A6XX_DBGBUS_DBGC = 22, 256a69c5ed2SRob Clark A6XX_DBGBUS_CX = 23, 257a69c5ed2SRob Clark A6XX_DBGBUS_GMU_GX = 24, 258a69c5ed2SRob Clark A6XX_DBGBUS_TPFCHE = 25, 259a69c5ed2SRob Clark A6XX_DBGBUS_GBIF_GX = 26, 260a69c5ed2SRob Clark A6XX_DBGBUS_GPC = 29, 261a69c5ed2SRob Clark A6XX_DBGBUS_LARC = 30, 262a69c5ed2SRob Clark A6XX_DBGBUS_HLSQ_SPTP = 31, 263a69c5ed2SRob Clark A6XX_DBGBUS_RB_0 = 32, 264a69c5ed2SRob Clark A6XX_DBGBUS_RB_1 = 33, 265a69c5ed2SRob Clark A6XX_DBGBUS_UCHE_WRAPPER = 36, 266a69c5ed2SRob Clark A6XX_DBGBUS_CCU_0 = 40, 267a69c5ed2SRob Clark A6XX_DBGBUS_CCU_1 = 41, 268a69c5ed2SRob Clark A6XX_DBGBUS_VFD_0 = 56, 269a69c5ed2SRob Clark A6XX_DBGBUS_VFD_1 = 57, 270a69c5ed2SRob Clark A6XX_DBGBUS_VFD_2 = 58, 271a69c5ed2SRob Clark A6XX_DBGBUS_VFD_3 = 59, 272a69c5ed2SRob Clark A6XX_DBGBUS_SP_0 = 64, 273a69c5ed2SRob Clark A6XX_DBGBUS_SP_1 = 65, 274a69c5ed2SRob Clark A6XX_DBGBUS_TPL1_0 = 72, 275a69c5ed2SRob Clark A6XX_DBGBUS_TPL1_1 = 73, 276a69c5ed2SRob Clark A6XX_DBGBUS_TPL1_2 = 74, 277a69c5ed2SRob Clark A6XX_DBGBUS_TPL1_3 = 75, 278a69c5ed2SRob Clark }; 279a69c5ed2SRob Clark 2802d756322SRob Clark enum a6xx_cp_perfcounter_select { 2812d756322SRob Clark PERF_CP_ALWAYS_COUNT = 0, 282a69c5ed2SRob Clark PERF_CP_BUSY_GFX_CORE_IDLE = 1, 283a69c5ed2SRob Clark PERF_CP_BUSY_CYCLES = 2, 284a69c5ed2SRob Clark PERF_CP_NUM_PREEMPTIONS = 3, 285a69c5ed2SRob Clark PERF_CP_PREEMPTION_REACTION_DELAY = 4, 286a69c5ed2SRob Clark PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 5, 287a69c5ed2SRob Clark PERF_CP_PREEMPTION_SWITCH_IN_TIME = 6, 288a69c5ed2SRob Clark PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 7, 289a69c5ed2SRob Clark PERF_CP_PREDICATED_DRAWS_KILLED = 8, 290a69c5ed2SRob Clark PERF_CP_MODE_SWITCH = 9, 291a69c5ed2SRob Clark PERF_CP_ZPASS_DONE = 10, 292a69c5ed2SRob Clark PERF_CP_CONTEXT_DONE = 11, 293a69c5ed2SRob Clark PERF_CP_CACHE_FLUSH = 12, 294a69c5ed2SRob Clark PERF_CP_LONG_PREEMPTIONS = 13, 295a69c5ed2SRob Clark PERF_CP_SQE_I_CACHE_STARVE = 14, 296a69c5ed2SRob Clark PERF_CP_SQE_IDLE = 15, 297a69c5ed2SRob Clark PERF_CP_SQE_PM4_STARVE_RB_IB = 16, 298a69c5ed2SRob Clark PERF_CP_SQE_PM4_STARVE_SDS = 17, 299a69c5ed2SRob Clark PERF_CP_SQE_MRB_STARVE = 18, 300a69c5ed2SRob Clark PERF_CP_SQE_RRB_STARVE = 19, 301a69c5ed2SRob Clark PERF_CP_SQE_VSD_STARVE = 20, 302a69c5ed2SRob Clark PERF_CP_VSD_DECODE_STARVE = 21, 303a69c5ed2SRob Clark PERF_CP_SQE_PIPE_OUT_STALL = 22, 304a69c5ed2SRob Clark PERF_CP_SQE_SYNC_STALL = 23, 305a69c5ed2SRob Clark PERF_CP_SQE_PM4_WFI_STALL = 24, 306a69c5ed2SRob Clark PERF_CP_SQE_SYS_WFI_STALL = 25, 307a69c5ed2SRob Clark PERF_CP_SQE_T4_EXEC = 26, 308a69c5ed2SRob Clark PERF_CP_SQE_LOAD_STATE_EXEC = 27, 309a69c5ed2SRob Clark PERF_CP_SQE_SAVE_SDS_STATE = 28, 310a69c5ed2SRob Clark PERF_CP_SQE_DRAW_EXEC = 29, 311a69c5ed2SRob Clark PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 30, 312a69c5ed2SRob Clark PERF_CP_SQE_EXEC_PROFILED = 31, 313a69c5ed2SRob Clark PERF_CP_MEMORY_POOL_EMPTY = 32, 314a69c5ed2SRob Clark PERF_CP_MEMORY_POOL_SYNC_STALL = 33, 315a69c5ed2SRob Clark PERF_CP_MEMORY_POOL_ABOVE_THRESH = 34, 316a69c5ed2SRob Clark PERF_CP_AHB_WR_STALL_PRE_DRAWS = 35, 317a69c5ed2SRob Clark PERF_CP_AHB_STALL_SQE_GMU = 36, 318a69c5ed2SRob Clark PERF_CP_AHB_STALL_SQE_WR_OTHER = 37, 319a69c5ed2SRob Clark PERF_CP_AHB_STALL_SQE_RD_OTHER = 38, 320a69c5ed2SRob Clark PERF_CP_CLUSTER0_EMPTY = 39, 321a69c5ed2SRob Clark PERF_CP_CLUSTER1_EMPTY = 40, 322a69c5ed2SRob Clark PERF_CP_CLUSTER2_EMPTY = 41, 323a69c5ed2SRob Clark PERF_CP_CLUSTER3_EMPTY = 42, 324a69c5ed2SRob Clark PERF_CP_CLUSTER4_EMPTY = 43, 325a69c5ed2SRob Clark PERF_CP_CLUSTER5_EMPTY = 44, 326a69c5ed2SRob Clark PERF_CP_PM4_DATA = 45, 327a69c5ed2SRob Clark PERF_CP_PM4_HEADERS = 46, 328a69c5ed2SRob Clark PERF_CP_VBIF_READ_BEATS = 47, 329a69c5ed2SRob Clark PERF_CP_VBIF_WRITE_BEATS = 48, 330a69c5ed2SRob Clark PERF_CP_SQE_INSTR_COUNTER = 49, 331a69c5ed2SRob Clark }; 332a69c5ed2SRob Clark 333a69c5ed2SRob Clark enum a6xx_rbbm_perfcounter_select { 334a69c5ed2SRob Clark PERF_RBBM_ALWAYS_COUNT = 0, 335a69c5ed2SRob Clark PERF_RBBM_ALWAYS_ON = 1, 336a69c5ed2SRob Clark PERF_RBBM_TSE_BUSY = 2, 337a69c5ed2SRob Clark PERF_RBBM_RAS_BUSY = 3, 338a69c5ed2SRob Clark PERF_RBBM_PC_DCALL_BUSY = 4, 339a69c5ed2SRob Clark PERF_RBBM_PC_VSD_BUSY = 5, 340a69c5ed2SRob Clark PERF_RBBM_STATUS_MASKED = 6, 341a69c5ed2SRob Clark PERF_RBBM_COM_BUSY = 7, 342a69c5ed2SRob Clark PERF_RBBM_DCOM_BUSY = 8, 343a69c5ed2SRob Clark PERF_RBBM_VBIF_BUSY = 9, 344a69c5ed2SRob Clark PERF_RBBM_VSC_BUSY = 10, 345a69c5ed2SRob Clark PERF_RBBM_TESS_BUSY = 11, 346a69c5ed2SRob Clark PERF_RBBM_UCHE_BUSY = 12, 347a69c5ed2SRob Clark PERF_RBBM_HLSQ_BUSY = 13, 348a69c5ed2SRob Clark }; 349a69c5ed2SRob Clark 350a69c5ed2SRob Clark enum a6xx_pc_perfcounter_select { 351a69c5ed2SRob Clark PERF_PC_BUSY_CYCLES = 0, 352a69c5ed2SRob Clark PERF_PC_WORKING_CYCLES = 1, 353a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_VFD = 2, 354a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_TSE = 3, 355a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_VPC = 4, 356a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_UCHE = 5, 357a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_TESS = 6, 358a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_TSE_ONLY = 7, 359a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_VPC_ONLY = 8, 360a69c5ed2SRob Clark PERF_PC_PASS1_TF_STALL_CYCLES = 9, 361a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_FOR_INDEX = 10, 362a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11, 363a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12, 364a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_FOR_POSITION = 13, 365a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_DI = 14, 366a69c5ed2SRob Clark PERF_PC_VIS_STREAMS_LOADED = 15, 367a69c5ed2SRob Clark PERF_PC_INSTANCES = 16, 368a69c5ed2SRob Clark PERF_PC_VPC_PRIMITIVES = 17, 369a69c5ed2SRob Clark PERF_PC_DEAD_PRIM = 18, 370a69c5ed2SRob Clark PERF_PC_LIVE_PRIM = 19, 371a69c5ed2SRob Clark PERF_PC_VERTEX_HITS = 20, 372a69c5ed2SRob Clark PERF_PC_IA_VERTICES = 21, 373a69c5ed2SRob Clark PERF_PC_IA_PRIMITIVES = 22, 374a69c5ed2SRob Clark PERF_PC_GS_PRIMITIVES = 23, 375a69c5ed2SRob Clark PERF_PC_HS_INVOCATIONS = 24, 376a69c5ed2SRob Clark PERF_PC_DS_INVOCATIONS = 25, 377a69c5ed2SRob Clark PERF_PC_VS_INVOCATIONS = 26, 378a69c5ed2SRob Clark PERF_PC_GS_INVOCATIONS = 27, 379a69c5ed2SRob Clark PERF_PC_DS_PRIMITIVES = 28, 380a69c5ed2SRob Clark PERF_PC_VPC_POS_DATA_TRANSACTION = 29, 381a69c5ed2SRob Clark PERF_PC_3D_DRAWCALLS = 30, 382a69c5ed2SRob Clark PERF_PC_2D_DRAWCALLS = 31, 383a69c5ed2SRob Clark PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32, 384a69c5ed2SRob Clark PERF_TESS_BUSY_CYCLES = 33, 385a69c5ed2SRob Clark PERF_TESS_WORKING_CYCLES = 34, 386a69c5ed2SRob Clark PERF_TESS_STALL_CYCLES_PC = 35, 387a69c5ed2SRob Clark PERF_TESS_STARVE_CYCLES_PC = 36, 388a69c5ed2SRob Clark PERF_PC_TSE_TRANSACTION = 37, 389a69c5ed2SRob Clark PERF_PC_TSE_VERTEX = 38, 390a69c5ed2SRob Clark PERF_PC_TESS_PC_UV_TRANS = 39, 391a69c5ed2SRob Clark PERF_PC_TESS_PC_UV_PATCHES = 40, 392a69c5ed2SRob Clark PERF_PC_TESS_FACTOR_TRANS = 41, 393a69c5ed2SRob Clark }; 394a69c5ed2SRob Clark 395a69c5ed2SRob Clark enum a6xx_vfd_perfcounter_select { 396a69c5ed2SRob Clark PERF_VFD_BUSY_CYCLES = 0, 397a69c5ed2SRob Clark PERF_VFD_STALL_CYCLES_UCHE = 1, 398a69c5ed2SRob Clark PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2, 399a69c5ed2SRob Clark PERF_VFD_STALL_CYCLES_SP_INFO = 3, 400a69c5ed2SRob Clark PERF_VFD_STALL_CYCLES_SP_ATTR = 4, 401a69c5ed2SRob Clark PERF_VFD_STARVE_CYCLES_UCHE = 5, 402a69c5ed2SRob Clark PERF_VFD_RBUFFER_FULL = 6, 403a69c5ed2SRob Clark PERF_VFD_ATTR_INFO_FIFO_FULL = 7, 404a69c5ed2SRob Clark PERF_VFD_DECODED_ATTRIBUTE_BYTES = 8, 405a69c5ed2SRob Clark PERF_VFD_NUM_ATTRIBUTES = 9, 406a69c5ed2SRob Clark PERF_VFD_UPPER_SHADER_FIBERS = 10, 407a69c5ed2SRob Clark PERF_VFD_LOWER_SHADER_FIBERS = 11, 408a69c5ed2SRob Clark PERF_VFD_MODE_0_FIBERS = 12, 409a69c5ed2SRob Clark PERF_VFD_MODE_1_FIBERS = 13, 410a69c5ed2SRob Clark PERF_VFD_MODE_2_FIBERS = 14, 411a69c5ed2SRob Clark PERF_VFD_MODE_3_FIBERS = 15, 412a69c5ed2SRob Clark PERF_VFD_MODE_4_FIBERS = 16, 413a69c5ed2SRob Clark PERF_VFD_TOTAL_VERTICES = 17, 414a69c5ed2SRob Clark PERF_VFDP_STALL_CYCLES_VFD = 18, 415a69c5ed2SRob Clark PERF_VFDP_STALL_CYCLES_VFD_INDEX = 19, 416a69c5ed2SRob Clark PERF_VFDP_STALL_CYCLES_VFD_PROG = 20, 417a69c5ed2SRob Clark PERF_VFDP_STARVE_CYCLES_PC = 21, 418a69c5ed2SRob Clark PERF_VFDP_VS_STAGE_WAVES = 22, 419a69c5ed2SRob Clark }; 420a69c5ed2SRob Clark 421ccdf7e28SRob Clark enum a6xx_hlsq_perfcounter_select { 422a69c5ed2SRob Clark PERF_HLSQ_BUSY_CYCLES = 0, 423a69c5ed2SRob Clark PERF_HLSQ_STALL_CYCLES_UCHE = 1, 424a69c5ed2SRob Clark PERF_HLSQ_STALL_CYCLES_SP_STATE = 2, 425a69c5ed2SRob Clark PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3, 426a69c5ed2SRob Clark PERF_HLSQ_UCHE_LATENCY_CYCLES = 4, 427a69c5ed2SRob Clark PERF_HLSQ_UCHE_LATENCY_COUNT = 5, 428a69c5ed2SRob Clark PERF_HLSQ_FS_STAGE_1X_WAVES = 6, 429a69c5ed2SRob Clark PERF_HLSQ_FS_STAGE_2X_WAVES = 7, 430a69c5ed2SRob Clark PERF_HLSQ_QUADS = 8, 431a69c5ed2SRob Clark PERF_HLSQ_CS_INVOCATIONS = 9, 432a69c5ed2SRob Clark PERF_HLSQ_COMPUTE_DRAWCALLS = 10, 433a69c5ed2SRob Clark PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11, 434a69c5ed2SRob Clark PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12, 435a69c5ed2SRob Clark PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13, 436a69c5ed2SRob Clark PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14, 437a69c5ed2SRob Clark PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15, 438a69c5ed2SRob Clark PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16, 439a69c5ed2SRob Clark PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17, 440a69c5ed2SRob Clark PERF_HLSQ_STALL_CYCLES_VPC = 18, 441a69c5ed2SRob Clark PERF_HLSQ_PIXELS = 19, 442a69c5ed2SRob Clark PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = 20, 443a69c5ed2SRob Clark }; 444a69c5ed2SRob Clark 445a69c5ed2SRob Clark enum a6xx_vpc_perfcounter_select { 446a69c5ed2SRob Clark PERF_VPC_BUSY_CYCLES = 0, 447a69c5ed2SRob Clark PERF_VPC_WORKING_CYCLES = 1, 448a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_UCHE = 2, 449a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_VFD_WACK = 3, 450a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4, 451a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_PC = 5, 452a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_SP_LM = 6, 453a69c5ed2SRob Clark PERF_VPC_STARVE_CYCLES_SP = 7, 454a69c5ed2SRob Clark PERF_VPC_STARVE_CYCLES_LRZ = 8, 455a69c5ed2SRob Clark PERF_VPC_PC_PRIMITIVES = 9, 456a69c5ed2SRob Clark PERF_VPC_SP_COMPONENTS = 10, 457a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_VPCRAM_POS = 11, 458a69c5ed2SRob Clark PERF_VPC_LRZ_ASSIGN_PRIMITIVES = 12, 459a69c5ed2SRob Clark PERF_VPC_RB_VISIBLE_PRIMITIVES = 13, 460a69c5ed2SRob Clark PERF_VPC_LM_TRANSACTION = 14, 461a69c5ed2SRob Clark PERF_VPC_STREAMOUT_TRANSACTION = 15, 462a69c5ed2SRob Clark PERF_VPC_VS_BUSY_CYCLES = 16, 463a69c5ed2SRob Clark PERF_VPC_PS_BUSY_CYCLES = 17, 464a69c5ed2SRob Clark PERF_VPC_VS_WORKING_CYCLES = 18, 465a69c5ed2SRob Clark PERF_VPC_PS_WORKING_CYCLES = 19, 466a69c5ed2SRob Clark PERF_VPC_STARVE_CYCLES_RB = 20, 467a69c5ed2SRob Clark PERF_VPC_NUM_VPCRAM_READ_POS = 21, 468a69c5ed2SRob Clark PERF_VPC_WIT_FULL_CYCLES = 22, 469a69c5ed2SRob Clark PERF_VPC_VPCRAM_FULL_CYCLES = 23, 470a69c5ed2SRob Clark PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = 24, 471a69c5ed2SRob Clark PERF_VPC_NUM_VPCRAM_WRITE = 25, 472a69c5ed2SRob Clark PERF_VPC_NUM_VPCRAM_READ_SO = 26, 473a69c5ed2SRob Clark PERF_VPC_NUM_ATTR_REQ_LM = 27, 474a69c5ed2SRob Clark }; 475a69c5ed2SRob Clark 476a69c5ed2SRob Clark enum a6xx_tse_perfcounter_select { 477a69c5ed2SRob Clark PERF_TSE_BUSY_CYCLES = 0, 478a69c5ed2SRob Clark PERF_TSE_CLIPPING_CYCLES = 1, 479a69c5ed2SRob Clark PERF_TSE_STALL_CYCLES_RAS = 2, 480a69c5ed2SRob Clark PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3, 481a69c5ed2SRob Clark PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4, 482a69c5ed2SRob Clark PERF_TSE_STARVE_CYCLES_PC = 5, 483a69c5ed2SRob Clark PERF_TSE_INPUT_PRIM = 6, 484a69c5ed2SRob Clark PERF_TSE_INPUT_NULL_PRIM = 7, 485a69c5ed2SRob Clark PERF_TSE_TRIVAL_REJ_PRIM = 8, 486a69c5ed2SRob Clark PERF_TSE_CLIPPED_PRIM = 9, 487a69c5ed2SRob Clark PERF_TSE_ZERO_AREA_PRIM = 10, 488a69c5ed2SRob Clark PERF_TSE_FACENESS_CULLED_PRIM = 11, 489a69c5ed2SRob Clark PERF_TSE_ZERO_PIXEL_PRIM = 12, 490a69c5ed2SRob Clark PERF_TSE_OUTPUT_NULL_PRIM = 13, 491a69c5ed2SRob Clark PERF_TSE_OUTPUT_VISIBLE_PRIM = 14, 492a69c5ed2SRob Clark PERF_TSE_CINVOCATION = 15, 493a69c5ed2SRob Clark PERF_TSE_CPRIMITIVES = 16, 494a69c5ed2SRob Clark PERF_TSE_2D_INPUT_PRIM = 17, 495a69c5ed2SRob Clark PERF_TSE_2D_ALIVE_CYCLES = 18, 496a69c5ed2SRob Clark PERF_TSE_CLIP_PLANES = 19, 497a69c5ed2SRob Clark }; 498a69c5ed2SRob Clark 499a69c5ed2SRob Clark enum a6xx_ras_perfcounter_select { 500a69c5ed2SRob Clark PERF_RAS_BUSY_CYCLES = 0, 501a69c5ed2SRob Clark PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1, 502a69c5ed2SRob Clark PERF_RAS_STALL_CYCLES_LRZ = 2, 503a69c5ed2SRob Clark PERF_RAS_STARVE_CYCLES_TSE = 3, 504a69c5ed2SRob Clark PERF_RAS_SUPER_TILES = 4, 505a69c5ed2SRob Clark PERF_RAS_8X4_TILES = 5, 506a69c5ed2SRob Clark PERF_RAS_MASKGEN_ACTIVE = 6, 507a69c5ed2SRob Clark PERF_RAS_FULLY_COVERED_SUPER_TILES = 7, 508a69c5ed2SRob Clark PERF_RAS_FULLY_COVERED_8X4_TILES = 8, 509a69c5ed2SRob Clark PERF_RAS_PRIM_KILLED_INVISILBE = 9, 510a69c5ed2SRob Clark PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 10, 511a69c5ed2SRob Clark PERF_RAS_LRZ_INTF_WORKING_CYCLES = 11, 512a69c5ed2SRob Clark PERF_RAS_BLOCKS = 12, 513a69c5ed2SRob Clark }; 514a69c5ed2SRob Clark 515a69c5ed2SRob Clark enum a6xx_uche_perfcounter_select { 516a69c5ed2SRob Clark PERF_UCHE_BUSY_CYCLES = 0, 517a69c5ed2SRob Clark PERF_UCHE_STALL_CYCLES_ARBITER = 1, 518a69c5ed2SRob Clark PERF_UCHE_VBIF_LATENCY_CYCLES = 2, 519a69c5ed2SRob Clark PERF_UCHE_VBIF_LATENCY_SAMPLES = 3, 520a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_TP = 4, 521a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_VFD = 5, 522a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6, 523a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_LRZ = 7, 524a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_SP = 8, 525a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_TP = 9, 526a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_VFD = 10, 527a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_HLSQ = 11, 528a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_LRZ = 12, 529a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_SP = 13, 530a69c5ed2SRob Clark PERF_UCHE_WRITE_REQUESTS_LRZ = 14, 531a69c5ed2SRob Clark PERF_UCHE_WRITE_REQUESTS_SP = 15, 532a69c5ed2SRob Clark PERF_UCHE_WRITE_REQUESTS_VPC = 16, 533a69c5ed2SRob Clark PERF_UCHE_WRITE_REQUESTS_VSC = 17, 534a69c5ed2SRob Clark PERF_UCHE_EVICTS = 18, 535a69c5ed2SRob Clark PERF_UCHE_BANK_REQ0 = 19, 536a69c5ed2SRob Clark PERF_UCHE_BANK_REQ1 = 20, 537a69c5ed2SRob Clark PERF_UCHE_BANK_REQ2 = 21, 538a69c5ed2SRob Clark PERF_UCHE_BANK_REQ3 = 22, 539a69c5ed2SRob Clark PERF_UCHE_BANK_REQ4 = 23, 540a69c5ed2SRob Clark PERF_UCHE_BANK_REQ5 = 24, 541a69c5ed2SRob Clark PERF_UCHE_BANK_REQ6 = 25, 542a69c5ed2SRob Clark PERF_UCHE_BANK_REQ7 = 26, 543a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_CH0 = 27, 544a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_CH1 = 28, 545a69c5ed2SRob Clark PERF_UCHE_GMEM_READ_BEATS = 29, 546a69c5ed2SRob Clark PERF_UCHE_TPH_REF_FULL = 30, 547a69c5ed2SRob Clark PERF_UCHE_TPH_VICTIM_FULL = 31, 548a69c5ed2SRob Clark PERF_UCHE_TPH_EXT_FULL = 32, 549a69c5ed2SRob Clark PERF_UCHE_VBIF_STALL_WRITE_DATA = 33, 550a69c5ed2SRob Clark PERF_UCHE_DCMP_LATENCY_SAMPLES = 34, 551a69c5ed2SRob Clark PERF_UCHE_DCMP_LATENCY_CYCLES = 35, 552a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_PC = 36, 553a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_PC = 37, 554a69c5ed2SRob Clark PERF_UCHE_RAM_READ_REQ = 38, 555a69c5ed2SRob Clark PERF_UCHE_RAM_WRITE_REQ = 39, 556a69c5ed2SRob Clark }; 557a69c5ed2SRob Clark 558a69c5ed2SRob Clark enum a6xx_tp_perfcounter_select { 559a69c5ed2SRob Clark PERF_TP_BUSY_CYCLES = 0, 560a69c5ed2SRob Clark PERF_TP_STALL_CYCLES_UCHE = 1, 561a69c5ed2SRob Clark PERF_TP_LATENCY_CYCLES = 2, 562a69c5ed2SRob Clark PERF_TP_LATENCY_TRANS = 3, 563a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4, 564a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5, 565a69c5ed2SRob Clark PERF_TP_L1_CACHELINE_REQUESTS = 6, 566a69c5ed2SRob Clark PERF_TP_L1_CACHELINE_MISSES = 7, 567a69c5ed2SRob Clark PERF_TP_SP_TP_TRANS = 8, 568a69c5ed2SRob Clark PERF_TP_TP_SP_TRANS = 9, 569a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS = 10, 570a69c5ed2SRob Clark PERF_TP_FILTER_WORKLOAD_16BIT = 11, 571a69c5ed2SRob Clark PERF_TP_FILTER_WORKLOAD_32BIT = 12, 572a69c5ed2SRob Clark PERF_TP_QUADS_RECEIVED = 13, 573a69c5ed2SRob Clark PERF_TP_QUADS_OFFSET = 14, 574a69c5ed2SRob Clark PERF_TP_QUADS_SHADOW = 15, 575a69c5ed2SRob Clark PERF_TP_QUADS_ARRAY = 16, 576a69c5ed2SRob Clark PERF_TP_QUADS_GRADIENT = 17, 577a69c5ed2SRob Clark PERF_TP_QUADS_1D = 18, 578a69c5ed2SRob Clark PERF_TP_QUADS_2D = 19, 579a69c5ed2SRob Clark PERF_TP_QUADS_BUFFER = 20, 580a69c5ed2SRob Clark PERF_TP_QUADS_3D = 21, 581a69c5ed2SRob Clark PERF_TP_QUADS_CUBE = 22, 582a69c5ed2SRob Clark PERF_TP_DIVERGENT_QUADS_RECEIVED = 23, 583a69c5ed2SRob Clark PERF_TP_PRT_NON_RESIDENT_EVENTS = 24, 584a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_POINT = 25, 585a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_BILINEAR = 26, 586a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_MIP = 27, 587a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_ANISO = 28, 588a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 29, 589a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_REQUESTS = 30, 590a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_MISSES = 31, 591a69c5ed2SRob Clark PERF_TP_L1_5_L2_REQUESTS = 32, 592a69c5ed2SRob Clark PERF_TP_2D_OUTPUT_PIXELS = 33, 593a69c5ed2SRob Clark PERF_TP_2D_OUTPUT_PIXELS_POINT = 34, 594a69c5ed2SRob Clark PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 35, 595a69c5ed2SRob Clark PERF_TP_2D_FILTER_WORKLOAD_16BIT = 36, 596a69c5ed2SRob Clark PERF_TP_2D_FILTER_WORKLOAD_32BIT = 37, 597a69c5ed2SRob Clark PERF_TP_TPA2TPC_TRANS = 38, 598a69c5ed2SRob Clark PERF_TP_L1_MISSES_ASTC_1TILE = 39, 599a69c5ed2SRob Clark PERF_TP_L1_MISSES_ASTC_2TILE = 40, 600a69c5ed2SRob Clark PERF_TP_L1_MISSES_ASTC_4TILE = 41, 601a69c5ed2SRob Clark PERF_TP_L1_5_L2_COMPRESS_REQS = 42, 602a69c5ed2SRob Clark PERF_TP_L1_5_L2_COMPRESS_MISS = 43, 603a69c5ed2SRob Clark PERF_TP_L1_BANK_CONFLICT = 44, 604a69c5ed2SRob Clark PERF_TP_L1_5_MISS_LATENCY_CYCLES = 45, 605a69c5ed2SRob Clark PERF_TP_L1_5_MISS_LATENCY_TRANS = 46, 606a69c5ed2SRob Clark PERF_TP_QUADS_CONSTANT_MULTIPLIED = 47, 607a69c5ed2SRob Clark PERF_TP_FRONTEND_WORKING_CYCLES = 48, 608a69c5ed2SRob Clark PERF_TP_L1_TAG_WORKING_CYCLES = 49, 609a69c5ed2SRob Clark PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 50, 610a69c5ed2SRob Clark PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 51, 611a69c5ed2SRob Clark PERF_TP_BACKEND_WORKING_CYCLES = 52, 612a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_WORKING_CYCLES = 53, 613a69c5ed2SRob Clark PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54, 614a69c5ed2SRob Clark PERF_TP_STARVE_CYCLES_SP = 55, 615a69c5ed2SRob Clark PERF_TP_STARVE_CYCLES_UCHE = 56, 616a69c5ed2SRob Clark }; 617a69c5ed2SRob Clark 618a69c5ed2SRob Clark enum a6xx_sp_perfcounter_select { 619a69c5ed2SRob Clark PERF_SP_BUSY_CYCLES = 0, 620a69c5ed2SRob Clark PERF_SP_ALU_WORKING_CYCLES = 1, 621a69c5ed2SRob Clark PERF_SP_EFU_WORKING_CYCLES = 2, 622a69c5ed2SRob Clark PERF_SP_STALL_CYCLES_VPC = 3, 623a69c5ed2SRob Clark PERF_SP_STALL_CYCLES_TP = 4, 624a69c5ed2SRob Clark PERF_SP_STALL_CYCLES_UCHE = 5, 625a69c5ed2SRob Clark PERF_SP_STALL_CYCLES_RB = 6, 626a69c5ed2SRob Clark PERF_SP_NON_EXECUTION_CYCLES = 7, 627a69c5ed2SRob Clark PERF_SP_WAVE_CONTEXTS = 8, 628a69c5ed2SRob Clark PERF_SP_WAVE_CONTEXT_CYCLES = 9, 629a69c5ed2SRob Clark PERF_SP_FS_STAGE_WAVE_CYCLES = 10, 630a69c5ed2SRob Clark PERF_SP_FS_STAGE_WAVE_SAMPLES = 11, 631a69c5ed2SRob Clark PERF_SP_VS_STAGE_WAVE_CYCLES = 12, 632a69c5ed2SRob Clark PERF_SP_VS_STAGE_WAVE_SAMPLES = 13, 633a69c5ed2SRob Clark PERF_SP_FS_STAGE_DURATION_CYCLES = 14, 634a69c5ed2SRob Clark PERF_SP_VS_STAGE_DURATION_CYCLES = 15, 635a69c5ed2SRob Clark PERF_SP_WAVE_CTRL_CYCLES = 16, 636a69c5ed2SRob Clark PERF_SP_WAVE_LOAD_CYCLES = 17, 637a69c5ed2SRob Clark PERF_SP_WAVE_EMIT_CYCLES = 18, 638a69c5ed2SRob Clark PERF_SP_WAVE_NOP_CYCLES = 19, 639a69c5ed2SRob Clark PERF_SP_WAVE_WAIT_CYCLES = 20, 640a69c5ed2SRob Clark PERF_SP_WAVE_FETCH_CYCLES = 21, 641a69c5ed2SRob Clark PERF_SP_WAVE_IDLE_CYCLES = 22, 642a69c5ed2SRob Clark PERF_SP_WAVE_END_CYCLES = 23, 643a69c5ed2SRob Clark PERF_SP_WAVE_LONG_SYNC_CYCLES = 24, 644a69c5ed2SRob Clark PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25, 645a69c5ed2SRob Clark PERF_SP_WAVE_JOIN_CYCLES = 26, 646a69c5ed2SRob Clark PERF_SP_LM_LOAD_INSTRUCTIONS = 27, 647a69c5ed2SRob Clark PERF_SP_LM_STORE_INSTRUCTIONS = 28, 648a69c5ed2SRob Clark PERF_SP_LM_ATOMICS = 29, 649a69c5ed2SRob Clark PERF_SP_GM_LOAD_INSTRUCTIONS = 30, 650a69c5ed2SRob Clark PERF_SP_GM_STORE_INSTRUCTIONS = 31, 651a69c5ed2SRob Clark PERF_SP_GM_ATOMICS = 32, 652a69c5ed2SRob Clark PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33, 653a69c5ed2SRob Clark PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34, 654a69c5ed2SRob Clark PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35, 655a69c5ed2SRob Clark PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36, 656a69c5ed2SRob Clark PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37, 657a69c5ed2SRob Clark PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38, 658a69c5ed2SRob Clark PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39, 659a69c5ed2SRob Clark PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40, 660a69c5ed2SRob Clark PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41, 661a69c5ed2SRob Clark PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42, 662a69c5ed2SRob Clark PERF_SP_VS_INSTRUCTIONS = 43, 663a69c5ed2SRob Clark PERF_SP_FS_INSTRUCTIONS = 44, 664a69c5ed2SRob Clark PERF_SP_ADDR_LOCK_COUNT = 45, 665a69c5ed2SRob Clark PERF_SP_UCHE_READ_TRANS = 46, 666a69c5ed2SRob Clark PERF_SP_UCHE_WRITE_TRANS = 47, 667a69c5ed2SRob Clark PERF_SP_EXPORT_VPC_TRANS = 48, 668a69c5ed2SRob Clark PERF_SP_EXPORT_RB_TRANS = 49, 669a69c5ed2SRob Clark PERF_SP_PIXELS_KILLED = 50, 670a69c5ed2SRob Clark PERF_SP_ICL1_REQUESTS = 51, 671a69c5ed2SRob Clark PERF_SP_ICL1_MISSES = 52, 672a69c5ed2SRob Clark PERF_SP_HS_INSTRUCTIONS = 53, 673a69c5ed2SRob Clark PERF_SP_DS_INSTRUCTIONS = 54, 674a69c5ed2SRob Clark PERF_SP_GS_INSTRUCTIONS = 55, 675a69c5ed2SRob Clark PERF_SP_CS_INSTRUCTIONS = 56, 676a69c5ed2SRob Clark PERF_SP_GPR_READ = 57, 677a69c5ed2SRob Clark PERF_SP_GPR_WRITE = 58, 678a69c5ed2SRob Clark PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59, 679a69c5ed2SRob Clark PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60, 680a69c5ed2SRob Clark PERF_SP_LM_BANK_CONFLICTS = 61, 681a69c5ed2SRob Clark PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62, 682a69c5ed2SRob Clark PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63, 683a69c5ed2SRob Clark PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64, 684a69c5ed2SRob Clark PERF_SP_LM_WORKING_CYCLES = 65, 685a69c5ed2SRob Clark PERF_SP_DISPATCHER_WORKING_CYCLES = 66, 686a69c5ed2SRob Clark PERF_SP_SEQUENCER_WORKING_CYCLES = 67, 687a69c5ed2SRob Clark PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68, 688a69c5ed2SRob Clark PERF_SP_STARVE_CYCLES_HLSQ = 69, 689a69c5ed2SRob Clark PERF_SP_NON_EXECUTION_LS_CYCLES = 70, 690a69c5ed2SRob Clark PERF_SP_WORKING_EU = 71, 691a69c5ed2SRob Clark PERF_SP_ANY_EU_WORKING = 72, 692a69c5ed2SRob Clark PERF_SP_WORKING_EU_FS_STAGE = 73, 693a69c5ed2SRob Clark PERF_SP_ANY_EU_WORKING_FS_STAGE = 74, 694a69c5ed2SRob Clark PERF_SP_WORKING_EU_VS_STAGE = 75, 695a69c5ed2SRob Clark PERF_SP_ANY_EU_WORKING_VS_STAGE = 76, 696a69c5ed2SRob Clark PERF_SP_WORKING_EU_CS_STAGE = 77, 697a69c5ed2SRob Clark PERF_SP_ANY_EU_WORKING_CS_STAGE = 78, 698a69c5ed2SRob Clark PERF_SP_GPR_READ_PREFETCH = 79, 699a69c5ed2SRob Clark PERF_SP_GPR_READ_CONFLICT = 80, 700a69c5ed2SRob Clark PERF_SP_GPR_WRITE_CONFLICT = 81, 701a69c5ed2SRob Clark PERF_SP_GM_LOAD_LATENCY_CYCLES = 82, 702a69c5ed2SRob Clark PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83, 703a69c5ed2SRob Clark PERF_SP_EXECUTABLE_WAVES = 84, 704a69c5ed2SRob Clark }; 705a69c5ed2SRob Clark 706a69c5ed2SRob Clark enum a6xx_rb_perfcounter_select { 707a69c5ed2SRob Clark PERF_RB_BUSY_CYCLES = 0, 708a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_HLSQ = 1, 709a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_FIFO0_FULL = 2, 710a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_FIFO1_FULL = 3, 711a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_FIFO2_FULL = 4, 712a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_SP = 5, 713a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_LRZ_TILE = 6, 714a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_CCU = 7, 715a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_Z_PLANE = 8, 716a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_BARY_PLANE = 9, 717a69c5ed2SRob Clark PERF_RB_Z_WORKLOAD = 10, 718a69c5ed2SRob Clark PERF_RB_HLSQ_ACTIVE = 11, 719a69c5ed2SRob Clark PERF_RB_Z_READ = 12, 720a69c5ed2SRob Clark PERF_RB_Z_WRITE = 13, 721a69c5ed2SRob Clark PERF_RB_C_READ = 14, 722a69c5ed2SRob Clark PERF_RB_C_WRITE = 15, 723a69c5ed2SRob Clark PERF_RB_TOTAL_PASS = 16, 724a69c5ed2SRob Clark PERF_RB_Z_PASS = 17, 725a69c5ed2SRob Clark PERF_RB_Z_FAIL = 18, 726a69c5ed2SRob Clark PERF_RB_S_FAIL = 19, 727a69c5ed2SRob Clark PERF_RB_BLENDED_FXP_COMPONENTS = 20, 728a69c5ed2SRob Clark PERF_RB_BLENDED_FP16_COMPONENTS = 21, 729a69c5ed2SRob Clark PERF_RB_PS_INVOCATIONS = 22, 730a69c5ed2SRob Clark PERF_RB_2D_ALIVE_CYCLES = 23, 731a69c5ed2SRob Clark PERF_RB_2D_STALL_CYCLES_A2D = 24, 732a69c5ed2SRob Clark PERF_RB_2D_STARVE_CYCLES_SRC = 25, 733a69c5ed2SRob Clark PERF_RB_2D_STARVE_CYCLES_SP = 26, 734a69c5ed2SRob Clark PERF_RB_2D_STARVE_CYCLES_DST = 27, 735a69c5ed2SRob Clark PERF_RB_2D_VALID_PIXELS = 28, 736a69c5ed2SRob Clark PERF_RB_3D_PIXELS = 29, 737a69c5ed2SRob Clark PERF_RB_BLENDER_WORKING_CYCLES = 30, 738a69c5ed2SRob Clark PERF_RB_ZPROC_WORKING_CYCLES = 31, 739a69c5ed2SRob Clark PERF_RB_CPROC_WORKING_CYCLES = 32, 740a69c5ed2SRob Clark PERF_RB_SAMPLER_WORKING_CYCLES = 33, 741a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 34, 742a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 35, 743a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 36, 744a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 37, 745a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_VPC = 38, 746a69c5ed2SRob Clark PERF_RB_2D_INPUT_TRANS = 39, 747a69c5ed2SRob Clark PERF_RB_2D_OUTPUT_RB_DST_TRANS = 40, 748a69c5ed2SRob Clark PERF_RB_2D_OUTPUT_RB_SRC_TRANS = 41, 749a69c5ed2SRob Clark PERF_RB_BLENDED_FP32_COMPONENTS = 42, 750a69c5ed2SRob Clark PERF_RB_COLOR_PIX_TILES = 43, 751a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU = 44, 752a69c5ed2SRob Clark PERF_RB_EARLY_Z_ARB3_GRANT = 45, 753a69c5ed2SRob Clark PERF_RB_LATE_Z_ARB3_GRANT = 46, 754a69c5ed2SRob Clark PERF_RB_EARLY_Z_SKIP_GRANT = 47, 755a69c5ed2SRob Clark }; 756a69c5ed2SRob Clark 757a69c5ed2SRob Clark enum a6xx_vsc_perfcounter_select { 758a69c5ed2SRob Clark PERF_VSC_BUSY_CYCLES = 0, 759a69c5ed2SRob Clark PERF_VSC_WORKING_CYCLES = 1, 760a69c5ed2SRob Clark PERF_VSC_STALL_CYCLES_UCHE = 2, 761a69c5ed2SRob Clark PERF_VSC_EOT_NUM = 3, 762a69c5ed2SRob Clark PERF_VSC_INPUT_TILES = 4, 763a69c5ed2SRob Clark }; 764a69c5ed2SRob Clark 765a69c5ed2SRob Clark enum a6xx_ccu_perfcounter_select { 766a69c5ed2SRob Clark PERF_CCU_BUSY_CYCLES = 0, 767a69c5ed2SRob Clark PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1, 768a69c5ed2SRob Clark PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2, 769a69c5ed2SRob Clark PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3, 770a69c5ed2SRob Clark PERF_CCU_DEPTH_BLOCKS = 4, 771a69c5ed2SRob Clark PERF_CCU_COLOR_BLOCKS = 5, 772a69c5ed2SRob Clark PERF_CCU_DEPTH_BLOCK_HIT = 6, 773a69c5ed2SRob Clark PERF_CCU_COLOR_BLOCK_HIT = 7, 774a69c5ed2SRob Clark PERF_CCU_PARTIAL_BLOCK_READ = 8, 775a69c5ed2SRob Clark PERF_CCU_GMEM_READ = 9, 776a69c5ed2SRob Clark PERF_CCU_GMEM_WRITE = 10, 777a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11, 778a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12, 779a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13, 780a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14, 781a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15, 782a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG5_COUNT = 16, 783a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG6_COUNT = 17, 784a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG8_COUNT = 18, 785a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG0_COUNT = 19, 786a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG1_COUNT = 20, 787a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG2_COUNT = 21, 788a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG3_COUNT = 22, 789a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG4_COUNT = 23, 790a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG5_COUNT = 24, 791a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG6_COUNT = 25, 792a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG8_COUNT = 26, 793a69c5ed2SRob Clark PERF_CCU_2D_RD_REQ = 27, 794a69c5ed2SRob Clark PERF_CCU_2D_WR_REQ = 28, 795a69c5ed2SRob Clark }; 796a69c5ed2SRob Clark 797a69c5ed2SRob Clark enum a6xx_lrz_perfcounter_select { 798a69c5ed2SRob Clark PERF_LRZ_BUSY_CYCLES = 0, 799a69c5ed2SRob Clark PERF_LRZ_STARVE_CYCLES_RAS = 1, 800a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_RB = 2, 801a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_VSC = 3, 802a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_VPC = 4, 803a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5, 804a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_UCHE = 6, 805a69c5ed2SRob Clark PERF_LRZ_LRZ_READ = 7, 806a69c5ed2SRob Clark PERF_LRZ_LRZ_WRITE = 8, 807a69c5ed2SRob Clark PERF_LRZ_READ_LATENCY = 9, 808a69c5ed2SRob Clark PERF_LRZ_MERGE_CACHE_UPDATING = 10, 809a69c5ed2SRob Clark PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11, 810a69c5ed2SRob Clark PERF_LRZ_PRIM_KILLED_BY_LRZ = 12, 811a69c5ed2SRob Clark PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13, 812a69c5ed2SRob Clark PERF_LRZ_FULL_8X8_TILES = 14, 813a69c5ed2SRob Clark PERF_LRZ_PARTIAL_8X8_TILES = 15, 814a69c5ed2SRob Clark PERF_LRZ_TILE_KILLED = 16, 815a69c5ed2SRob Clark PERF_LRZ_TOTAL_PIXEL = 17, 816a69c5ed2SRob Clark PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18, 817a69c5ed2SRob Clark PERF_LRZ_FULLY_COVERED_TILES = 19, 818a69c5ed2SRob Clark PERF_LRZ_PARTIAL_COVERED_TILES = 20, 819a69c5ed2SRob Clark PERF_LRZ_FEEDBACK_ACCEPT = 21, 820a69c5ed2SRob Clark PERF_LRZ_FEEDBACK_DISCARD = 22, 821a69c5ed2SRob Clark PERF_LRZ_FEEDBACK_STALL = 23, 822a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 24, 823a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_RB_BPLANE = 25, 824a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_VC = 26, 825a69c5ed2SRob Clark PERF_LRZ_RAS_MASK_TRANS = 27, 826a69c5ed2SRob Clark }; 827a69c5ed2SRob Clark 828a69c5ed2SRob Clark enum a6xx_cmp_perfcounter_select { 829a69c5ed2SRob Clark PERF_CMPDECMP_STALL_CYCLES_ARB = 0, 830a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1, 831a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2, 832a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3, 833a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4, 834a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_REQUEST = 5, 835a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6, 836a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_DATA = 7, 837a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_WRITE_DATA = 8, 838a69c5ed2SRob Clark PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9, 839a69c5ed2SRob Clark PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10, 840a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11, 841a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12, 842a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13, 843a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14, 844a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 15, 845a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 16, 846a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 17, 847a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 18, 848a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 19, 849a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 20, 850a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 21, 851a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 22, 852a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 23, 853a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 24, 854a69c5ed2SRob Clark PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 25, 855a69c5ed2SRob Clark PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 26, 856a69c5ed2SRob Clark PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 27, 857a69c5ed2SRob Clark PERF_CMPDECMP_2D_RD_DATA = 28, 858a69c5ed2SRob Clark PERF_CMPDECMP_2D_WR_DATA = 29, 859a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 30, 860a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 31, 861a69c5ed2SRob Clark PERF_CMPDECMP_2D_OUTPUT_TRANS = 32, 862a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 33, 863a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 34, 864a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 35, 865a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 36, 866a69c5ed2SRob Clark PERF_CMPDECMP_2D_BUSY_CYCLES = 37, 867a69c5ed2SRob Clark PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = 38, 868a69c5ed2SRob Clark PERF_CMPDECMP_2D_PIXELS = 39, 8692d756322SRob Clark }; 8702d756322SRob Clark 871c28c82e9SRob Clark enum a6xx_2d_ifmt { 872c28c82e9SRob Clark R2D_UNORM8 = 16, 873c28c82e9SRob Clark R2D_INT32 = 7, 874c28c82e9SRob Clark R2D_INT16 = 6, 875c28c82e9SRob Clark R2D_INT8 = 5, 876c28c82e9SRob Clark R2D_FLOAT32 = 4, 877c28c82e9SRob Clark R2D_FLOAT16 = 3, 878c28c82e9SRob Clark R2D_UNORM8_SRGB = 1, 879c28c82e9SRob Clark R2D_RAW = 0, 880c28c82e9SRob Clark }; 881c28c82e9SRob Clark 882c28c82e9SRob Clark enum a6xx_ztest_mode { 883c28c82e9SRob Clark A6XX_EARLY_Z = 0, 884c28c82e9SRob Clark A6XX_LATE_Z = 1, 885c28c82e9SRob Clark A6XX_EARLY_LRZ_LATE_Z = 2, 886c28c82e9SRob Clark }; 887c28c82e9SRob Clark 888c28c82e9SRob Clark enum a6xx_rotation { 889c28c82e9SRob Clark ROTATE_0 = 0, 890c28c82e9SRob Clark ROTATE_90 = 1, 891c28c82e9SRob Clark ROTATE_180 = 2, 892c28c82e9SRob Clark ROTATE_270 = 3, 893c28c82e9SRob Clark ROTATE_HFLIP = 4, 894c28c82e9SRob Clark ROTATE_VFLIP = 5, 895c28c82e9SRob Clark }; 896c28c82e9SRob Clark 897c28c82e9SRob Clark enum a6xx_tess_spacing { 898c28c82e9SRob Clark TESS_EQUAL = 0, 899c28c82e9SRob Clark TESS_FRACTIONAL_ODD = 2, 900c28c82e9SRob Clark TESS_FRACTIONAL_EVEN = 3, 901c28c82e9SRob Clark }; 902c28c82e9SRob Clark 903c28c82e9SRob Clark enum a6xx_tess_output { 904c28c82e9SRob Clark TESS_POINTS = 0, 905c28c82e9SRob Clark TESS_LINES = 1, 906c28c82e9SRob Clark TESS_CW_TRIS = 2, 907c28c82e9SRob Clark TESS_CCW_TRIS = 3, 908c28c82e9SRob Clark }; 909c28c82e9SRob Clark 910*cc4c26d4SRob Clark enum a6xx_threadsize { 911*cc4c26d4SRob Clark THREAD64 = 0, 912*cc4c26d4SRob Clark THREAD128 = 1, 913*cc4c26d4SRob Clark }; 914*cc4c26d4SRob Clark 9152d756322SRob Clark enum a6xx_tex_filter { 9162d756322SRob Clark A6XX_TEX_NEAREST = 0, 9172d756322SRob Clark A6XX_TEX_LINEAR = 1, 9182d756322SRob Clark A6XX_TEX_ANISO = 2, 919c28c82e9SRob Clark A6XX_TEX_CUBIC = 3, 9202d756322SRob Clark }; 9212d756322SRob Clark 9222d756322SRob Clark enum a6xx_tex_clamp { 9232d756322SRob Clark A6XX_TEX_REPEAT = 0, 9242d756322SRob Clark A6XX_TEX_CLAMP_TO_EDGE = 1, 9252d756322SRob Clark A6XX_TEX_MIRROR_REPEAT = 2, 9262d756322SRob Clark A6XX_TEX_CLAMP_TO_BORDER = 3, 9272d756322SRob Clark A6XX_TEX_MIRROR_CLAMP = 4, 9282d756322SRob Clark }; 9292d756322SRob Clark 9302d756322SRob Clark enum a6xx_tex_aniso { 9312d756322SRob Clark A6XX_TEX_ANISO_1 = 0, 9322d756322SRob Clark A6XX_TEX_ANISO_2 = 1, 9332d756322SRob Clark A6XX_TEX_ANISO_4 = 2, 9342d756322SRob Clark A6XX_TEX_ANISO_8 = 3, 9352d756322SRob Clark A6XX_TEX_ANISO_16 = 4, 9362d756322SRob Clark }; 9372d756322SRob Clark 938c28c82e9SRob Clark enum a6xx_reduction_mode { 939c28c82e9SRob Clark A6XX_REDUCTION_MODE_AVERAGE = 0, 940c28c82e9SRob Clark A6XX_REDUCTION_MODE_MIN = 1, 941c28c82e9SRob Clark A6XX_REDUCTION_MODE_MAX = 2, 942c28c82e9SRob Clark }; 943c28c82e9SRob Clark 9442d756322SRob Clark enum a6xx_tex_swiz { 9452d756322SRob Clark A6XX_TEX_X = 0, 9462d756322SRob Clark A6XX_TEX_Y = 1, 9472d756322SRob Clark A6XX_TEX_Z = 2, 9482d756322SRob Clark A6XX_TEX_W = 3, 9492d756322SRob Clark A6XX_TEX_ZERO = 4, 9502d756322SRob Clark A6XX_TEX_ONE = 5, 9512d756322SRob Clark }; 9522d756322SRob Clark 9532d756322SRob Clark enum a6xx_tex_type { 9542d756322SRob Clark A6XX_TEX_1D = 0, 9552d756322SRob Clark A6XX_TEX_2D = 1, 9562d756322SRob Clark A6XX_TEX_CUBE = 2, 9572d756322SRob Clark A6XX_TEX_3D = 3, 9582d756322SRob Clark }; 9592d756322SRob Clark 9602d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001 9612d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR 0x00000002 9622d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW 0x00000040 9632d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080 9642d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_SW 0x00000100 9652d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200 9662d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400 9672d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800 9682d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000 9692d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_IB2 0x00002000 9702d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_IB1 0x00004000 9712d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_RB 0x00008000 9722d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000 9732d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000 9742d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000 9752d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000 9762d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT 0x00800000 9772d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000 9782d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000 9792d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000 9802d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000 9812d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000 9822d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000 9832d756322SRob Clark #define A6XX_CP_INT_CP_OPCODE_ERROR 0x00000001 9842d756322SRob Clark #define A6XX_CP_INT_CP_UCODE_ERROR 0x00000002 9852d756322SRob Clark #define A6XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004 9862d756322SRob Clark #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010 9872d756322SRob Clark #define A6XX_CP_INT_CP_AHB_ERROR 0x00000020 9882d756322SRob Clark #define A6XX_CP_INT_CP_VSD_PARITY_ERROR 0x00000040 9892d756322SRob Clark #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR 0x00000080 9902d756322SRob Clark #define REG_A6XX_CP_RB_BASE 0x00000800 9912d756322SRob Clark 9922d756322SRob Clark #define REG_A6XX_CP_RB_BASE_HI 0x00000801 9932d756322SRob Clark 9942d756322SRob Clark #define REG_A6XX_CP_RB_CNTL 0x00000802 9952d756322SRob Clark 9962d756322SRob Clark #define REG_A6XX_CP_RB_RPTR_ADDR_LO 0x00000804 9972d756322SRob Clark 9982d756322SRob Clark #define REG_A6XX_CP_RB_RPTR_ADDR_HI 0x00000805 9992d756322SRob Clark 10002d756322SRob Clark #define REG_A6XX_CP_RB_RPTR 0x00000806 10012d756322SRob Clark 10022d756322SRob Clark #define REG_A6XX_CP_RB_WPTR 0x00000807 10032d756322SRob Clark 10042d756322SRob Clark #define REG_A6XX_CP_SQE_CNTL 0x00000808 10052d756322SRob Clark 1006c28c82e9SRob Clark #define REG_A6XX_CP_CP2GMU_STATUS 0x00000812 1007c28c82e9SRob Clark #define A6XX_CP_CP2GMU_STATUS_IFPC 0x00000001 1008c28c82e9SRob Clark 10092d756322SRob Clark #define REG_A6XX_CP_HW_FAULT 0x00000821 10102d756322SRob Clark 10112d756322SRob Clark #define REG_A6XX_CP_INTERRUPT_STATUS 0x00000823 10122d756322SRob Clark 10132d756322SRob Clark #define REG_A6XX_CP_PROTECT_STATUS 0x00000824 10142d756322SRob Clark 1015*cc4c26d4SRob Clark #define REG_A6XX_CP_SQE_INSTR_BASE 0x00000830 10162d756322SRob Clark 10172d756322SRob Clark #define REG_A6XX_CP_MISC_CNTL 0x00000840 10182d756322SRob Clark 101924e6938eSJonathan Marek #define REG_A6XX_CP_APRIV_CNTL 0x00000844 102024e6938eSJonathan Marek 10212d756322SRob Clark #define REG_A6XX_CP_ROQ_THRESHOLDS_1 0x000008c1 1022c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK 0x000000ff 1023c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT 0 1024c28c82e9SRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_LO(uint32_t val) 1025c28c82e9SRob Clark { 1026c28c82e9SRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK; 1027c28c82e9SRob Clark } 1028c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MASK 0x0000ff00 1029c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__SHIFT 8 1030c28c82e9SRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_HI(uint32_t val) 1031c28c82e9SRob Clark { 1032c28c82e9SRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MASK; 1033c28c82e9SRob Clark } 1034c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK 0x00ff0000 1035c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT 16 1036c28c82e9SRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val) 1037c28c82e9SRob Clark { 1038c28c82e9SRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK; 1039c28c82e9SRob Clark } 1040c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK 0xff000000 1041c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT 24 1042c28c82e9SRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val) 1043c28c82e9SRob Clark { 1044c28c82e9SRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK; 1045c28c82e9SRob Clark } 10462d756322SRob Clark 10472d756322SRob Clark #define REG_A6XX_CP_ROQ_THRESHOLDS_2 0x000008c2 1048c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK 0x000001ff 1049c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT 0 1050c28c82e9SRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val) 1051c28c82e9SRob Clark { 1052c28c82e9SRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK; 1053c28c82e9SRob Clark } 1054c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK 0xffff0000 1055c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT 16 1056c28c82e9SRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val) 1057c28c82e9SRob Clark { 1058c28c82e9SRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK; 1059c28c82e9SRob Clark } 10602d756322SRob Clark 10612d756322SRob Clark #define REG_A6XX_CP_MEM_POOL_SIZE 0x000008c3 10622d756322SRob Clark 10632d756322SRob Clark #define REG_A6XX_CP_CHICKEN_DBG 0x00000841 10642d756322SRob Clark 10652d756322SRob Clark #define REG_A6XX_CP_ADDR_MODE_CNTL 0x00000842 10662d756322SRob Clark 10672d756322SRob Clark #define REG_A6XX_CP_DBG_ECO_CNTL 0x00000843 10682d756322SRob Clark 10692d756322SRob Clark #define REG_A6XX_CP_PROTECT_CNTL 0x0000084f 10702d756322SRob Clark 10712d756322SRob Clark static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; } 10722d756322SRob Clark 10732d756322SRob Clark static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; } 10742d756322SRob Clark 10752d756322SRob Clark static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; } 10762d756322SRob Clark 10772d756322SRob Clark static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; } 10782d756322SRob Clark #define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0003ffff 10792d756322SRob Clark #define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0 10802d756322SRob Clark static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) 10812d756322SRob Clark { 10822d756322SRob Clark return ((val) << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK; 10832d756322SRob Clark } 10842d756322SRob Clark #define A6XX_CP_PROTECT_REG_MASK_LEN__MASK 0x7ffc0000 10852d756322SRob Clark #define A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT 18 10862d756322SRob Clark static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) 10872d756322SRob Clark { 10882d756322SRob Clark return ((val) << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK; 10892d756322SRob Clark } 10902d756322SRob Clark #define A6XX_CP_PROTECT_REG_READ 0x80000000 10912d756322SRob Clark 10922d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_CNTL 0x000008a0 10932d756322SRob Clark 10942d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x000008a1 10952d756322SRob Clark 10962d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x000008a2 10972d756322SRob Clark 10982d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO 0x000008a3 10992d756322SRob Clark 11002d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI 0x000008a4 11012d756322SRob Clark 11022d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO 0x000008a5 11032d756322SRob Clark 11042d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI 0x000008a6 11052d756322SRob Clark 11062d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO 0x000008a7 11072d756322SRob Clark 11082d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI 0x000008a8 11092d756322SRob Clark 1110*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_CP_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008d0 + 0x1*i0; } 11112d756322SRob Clark 11122d756322SRob Clark #define REG_A6XX_CP_CRASH_SCRIPT_BASE_LO 0x00000900 11132d756322SRob Clark 11142d756322SRob Clark #define REG_A6XX_CP_CRASH_SCRIPT_BASE_HI 0x00000901 11152d756322SRob Clark 11162d756322SRob Clark #define REG_A6XX_CP_CRASH_DUMP_CNTL 0x00000902 11172d756322SRob Clark 11182d756322SRob Clark #define REG_A6XX_CP_CRASH_DUMP_STATUS 0x00000903 11192d756322SRob Clark 11202d756322SRob Clark #define REG_A6XX_CP_SQE_STAT_ADDR 0x00000908 11212d756322SRob Clark 11222d756322SRob Clark #define REG_A6XX_CP_SQE_STAT_DATA 0x00000909 11232d756322SRob Clark 11242d756322SRob Clark #define REG_A6XX_CP_DRAW_STATE_ADDR 0x0000090a 11252d756322SRob Clark 11262d756322SRob Clark #define REG_A6XX_CP_DRAW_STATE_DATA 0x0000090b 11272d756322SRob Clark 11282d756322SRob Clark #define REG_A6XX_CP_ROQ_DBG_ADDR 0x0000090c 11292d756322SRob Clark 11302d756322SRob Clark #define REG_A6XX_CP_ROQ_DBG_DATA 0x0000090d 11312d756322SRob Clark 11322d756322SRob Clark #define REG_A6XX_CP_MEM_POOL_DBG_ADDR 0x0000090e 11332d756322SRob Clark 11342d756322SRob Clark #define REG_A6XX_CP_MEM_POOL_DBG_DATA 0x0000090f 11352d756322SRob Clark 11362d756322SRob Clark #define REG_A6XX_CP_SQE_UCODE_DBG_ADDR 0x00000910 11372d756322SRob Clark 11382d756322SRob Clark #define REG_A6XX_CP_SQE_UCODE_DBG_DATA 0x00000911 11392d756322SRob Clark 11402d756322SRob Clark #define REG_A6XX_CP_IB1_BASE 0x00000928 11412d756322SRob Clark 11422d756322SRob Clark #define REG_A6XX_CP_IB1_BASE_HI 0x00000929 11432d756322SRob Clark 11442d756322SRob Clark #define REG_A6XX_CP_IB1_REM_SIZE 0x0000092a 11452d756322SRob Clark 11462d756322SRob Clark #define REG_A6XX_CP_IB2_BASE 0x0000092b 11472d756322SRob Clark 11482d756322SRob Clark #define REG_A6XX_CP_IB2_BASE_HI 0x0000092c 11492d756322SRob Clark 11502d756322SRob Clark #define REG_A6XX_CP_IB2_REM_SIZE 0x0000092d 11512d756322SRob Clark 1152c28c82e9SRob Clark #define REG_A6XX_CP_SDS_BASE 0x0000092e 1153c28c82e9SRob Clark 1154c28c82e9SRob Clark #define REG_A6XX_CP_SDS_BASE_HI 0x0000092f 1155c28c82e9SRob Clark 1156*cc4c26d4SRob Clark #define REG_A6XX_CP_SDS_REM_SIZE 0x00000930 1157c28c82e9SRob Clark 1158*cc4c26d4SRob Clark #define REG_A6XX_CP_MRB_BASE 0x00000931 1159c28c82e9SRob Clark 1160*cc4c26d4SRob Clark #define REG_A6XX_CP_MRB_BASE_HI 0x00000932 1161c28c82e9SRob Clark 1162*cc4c26d4SRob Clark #define REG_A6XX_CP_MRB_REM_SIZE 0x00000933 1163c28c82e9SRob Clark 1164*cc4c26d4SRob Clark #define REG_A6XX_CP_VSD_BASE 0x00000934 1165*cc4c26d4SRob Clark 1166*cc4c26d4SRob Clark #define REG_A6XX_CP_VSD_BASE_HI 0x00000935 1167*cc4c26d4SRob Clark 1168*cc4c26d4SRob Clark #define REG_A6XX_CP_MRB_DWORDS 0x00000946 1169*cc4c26d4SRob Clark 1170*cc4c26d4SRob Clark #define REG_A6XX_CP_VSD_DWORDS 0x00000947 1171c28c82e9SRob Clark 1172c28c82e9SRob Clark #define REG_A6XX_CP_CSQ_IB1_STAT 0x00000949 1173c28c82e9SRob Clark #define A6XX_CP_CSQ_IB1_STAT_REM__MASK 0xffff0000 1174c28c82e9SRob Clark #define A6XX_CP_CSQ_IB1_STAT_REM__SHIFT 16 1175c28c82e9SRob Clark static inline uint32_t A6XX_CP_CSQ_IB1_STAT_REM(uint32_t val) 1176c28c82e9SRob Clark { 1177c28c82e9SRob Clark return ((val) << A6XX_CP_CSQ_IB1_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB1_STAT_REM__MASK; 1178c28c82e9SRob Clark } 1179c28c82e9SRob Clark 1180c28c82e9SRob Clark #define REG_A6XX_CP_CSQ_IB2_STAT 0x0000094a 1181c28c82e9SRob Clark #define A6XX_CP_CSQ_IB2_STAT_REM__MASK 0xffff0000 1182c28c82e9SRob Clark #define A6XX_CP_CSQ_IB2_STAT_REM__SHIFT 16 1183c28c82e9SRob Clark static inline uint32_t A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val) 1184c28c82e9SRob Clark { 1185c28c82e9SRob Clark return ((val) << A6XX_CP_CSQ_IB2_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB2_STAT_REM__MASK; 1186c28c82e9SRob Clark } 1187c28c82e9SRob Clark 1188*cc4c26d4SRob Clark #define REG_A6XX_CP_MRQ_MRB_STAT 0x0000094c 1189*cc4c26d4SRob Clark #define A6XX_CP_MRQ_MRB_STAT_REM__MASK 0xffff0000 1190*cc4c26d4SRob Clark #define A6XX_CP_MRQ_MRB_STAT_REM__SHIFT 16 1191*cc4c26d4SRob Clark static inline uint32_t A6XX_CP_MRQ_MRB_STAT_REM(uint32_t val) 1192*cc4c26d4SRob Clark { 1193*cc4c26d4SRob Clark return ((val) << A6XX_CP_MRQ_MRB_STAT_REM__SHIFT) & A6XX_CP_MRQ_MRB_STAT_REM__MASK; 1194*cc4c26d4SRob Clark } 1195*cc4c26d4SRob Clark 11962d756322SRob Clark #define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO 0x00000980 11972d756322SRob Clark 11982d756322SRob Clark #define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI 0x00000981 11992d756322SRob Clark 12002d756322SRob Clark #define REG_A6XX_CP_AHB_CNTL 0x0000098d 12012d756322SRob Clark 12022d756322SRob Clark #define REG_A6XX_CP_APERTURE_CNTL_HOST 0x00000a00 12032d756322SRob Clark 12042d756322SRob Clark #define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03 12052d756322SRob Clark 1206*cc4c26d4SRob Clark #define REG_A6XX_CP_LPAC_PROG_FIFO_SIZE 0x00000b34 1207*cc4c26d4SRob Clark 1208*cc4c26d4SRob Clark #define REG_A6XX_CP_LPAC_SQE_INSTR_BASE 0x00000b82 1209*cc4c26d4SRob Clark 12102d756322SRob Clark #define REG_A6XX_VSC_ADDR_MODE_CNTL 0x00000c01 12112d756322SRob Clark 12122d756322SRob Clark #define REG_A6XX_RBBM_INT_0_STATUS 0x00000201 12132d756322SRob Clark 12142d756322SRob Clark #define REG_A6XX_RBBM_STATUS 0x00000210 12152d756322SRob Clark #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x00800000 12162d756322SRob Clark #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x00400000 12172d756322SRob Clark #define A6XX_RBBM_STATUS_HLSQ_BUSY 0x00200000 12182d756322SRob Clark #define A6XX_RBBM_STATUS_VSC_BUSY 0x00100000 12192d756322SRob Clark #define A6XX_RBBM_STATUS_TPL1_BUSY 0x00080000 12202d756322SRob Clark #define A6XX_RBBM_STATUS_SP_BUSY 0x00040000 12212d756322SRob Clark #define A6XX_RBBM_STATUS_UCHE_BUSY 0x00020000 12222d756322SRob Clark #define A6XX_RBBM_STATUS_VPC_BUSY 0x00010000 12232d756322SRob Clark #define A6XX_RBBM_STATUS_VFD_BUSY 0x00008000 12242d756322SRob Clark #define A6XX_RBBM_STATUS_TESS_BUSY 0x00004000 12252d756322SRob Clark #define A6XX_RBBM_STATUS_PC_VSD_BUSY 0x00002000 12262d756322SRob Clark #define A6XX_RBBM_STATUS_PC_DCALL_BUSY 0x00001000 12272d756322SRob Clark #define A6XX_RBBM_STATUS_COM_DCOM_BUSY 0x00000800 12282d756322SRob Clark #define A6XX_RBBM_STATUS_LRZ_BUSY 0x00000400 12292d756322SRob Clark #define A6XX_RBBM_STATUS_A2D_BUSY 0x00000200 12302d756322SRob Clark #define A6XX_RBBM_STATUS_CCU_BUSY 0x00000100 12312d756322SRob Clark #define A6XX_RBBM_STATUS_RB_BUSY 0x00000080 12322d756322SRob Clark #define A6XX_RBBM_STATUS_RAS_BUSY 0x00000040 12332d756322SRob Clark #define A6XX_RBBM_STATUS_TSE_BUSY 0x00000020 12342d756322SRob Clark #define A6XX_RBBM_STATUS_VBIF_BUSY 0x00000010 12352d756322SRob Clark #define A6XX_RBBM_STATUS_GFX_DBGC_BUSY 0x00000008 12362d756322SRob Clark #define A6XX_RBBM_STATUS_CP_BUSY 0x00000004 12372d756322SRob Clark #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER 0x00000002 12382d756322SRob Clark #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER 0x00000001 12392d756322SRob Clark 12402d756322SRob Clark #define REG_A6XX_RBBM_STATUS3 0x00000213 1241c28c82e9SRob Clark #define A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT 0x01000000 12422d756322SRob Clark 12432d756322SRob Clark #define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215 12442d756322SRob Clark 1245*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000400 + 0x2*i0; } 12462d756322SRob Clark 1247*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000041c + 0x2*i0; } 12482d756322SRob Clark 1249*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000424 + 0x2*i0; } 12502d756322SRob Clark 1251*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000434 + 0x2*i0; } 12522d756322SRob Clark 1253*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000444 + 0x2*i0; } 12542d756322SRob Clark 1255*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000450 + 0x2*i0; } 12562d756322SRob Clark 1257*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000045c + 0x2*i0; } 12582d756322SRob Clark 1259*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000466 + 0x2*i0; } 12602d756322SRob Clark 1261*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000046e + 0x2*i0; } 12622d756322SRob Clark 1263*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000476 + 0x2*i0; } 12642d756322SRob Clark 1265*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000048e + 0x2*i0; } 12662d756322SRob Clark 1267*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000004a6 + 0x2*i0; } 12682d756322SRob Clark 1269*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000004d6 + 0x2*i0; } 12702d756322SRob Clark 1271*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000004e6 + 0x2*i0; } 12722d756322SRob Clark 1273*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000004ea + 0x2*i0; } 12742d756322SRob Clark 1275*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000004f2 + 0x2*i0; } 12762d756322SRob Clark 12772d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500 12782d756322SRob Clark 12792d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 0x00000501 12802d756322SRob Clark 12812d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 0x00000502 12822d756322SRob Clark 12832d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 0x00000503 12842d756322SRob Clark 12852d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 0x00000504 12862d756322SRob Clark 12872d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000505 12882d756322SRob Clark 12892d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506 12902d756322SRob Clark 1291*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00000507 + 0x1*i0; } 12922d756322SRob Clark 12932d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b 12942d756322SRob Clark 12952d756322SRob Clark #define REG_A6XX_RBBM_ISDB_CNT 0x00000533 12962d756322SRob Clark 1297c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_0_LO 0x00000540 1298c28c82e9SRob Clark 1299c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_0_HI 0x00000541 1300c28c82e9SRob Clark 1301c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_1_LO 0x00000542 1302c28c82e9SRob Clark 1303c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_1_HI 0x00000543 1304c28c82e9SRob Clark 1305c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_2_LO 0x00000544 1306c28c82e9SRob Clark 1307c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_2_HI 0x00000545 1308c28c82e9SRob Clark 1309c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_3_LO 0x00000546 1310c28c82e9SRob Clark 1311c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_3_HI 0x00000547 1312c28c82e9SRob Clark 1313c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_4_LO 0x00000548 1314c28c82e9SRob Clark 1315c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_4_HI 0x00000549 1316c28c82e9SRob Clark 1317c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_5_LO 0x0000054a 1318c28c82e9SRob Clark 1319c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_5_HI 0x0000054b 1320c28c82e9SRob Clark 1321c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_6_LO 0x0000054c 1322c28c82e9SRob Clark 1323c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_6_HI 0x0000054d 1324c28c82e9SRob Clark 1325c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_7_LO 0x0000054e 1326c28c82e9SRob Clark 1327c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_7_HI 0x0000054f 1328c28c82e9SRob Clark 1329c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_8_LO 0x00000550 1330c28c82e9SRob Clark 1331c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_8_HI 0x00000551 1332c28c82e9SRob Clark 1333c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_9_LO 0x00000552 1334c28c82e9SRob Clark 1335c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_9_HI 0x00000553 1336c28c82e9SRob Clark 1337c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_10_LO 0x00000554 1338c28c82e9SRob Clark 1339c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_10_HI 0x00000555 1340c28c82e9SRob Clark 13412d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TRUST_CNTL 0x0000f400 13422d756322SRob Clark 13432d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800 13442d756322SRob Clark 13452d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801 13462d756322SRob Clark 13472d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802 13482d756322SRob Clark 13492d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_CNTL 0x0000f803 13502d756322SRob Clark 13512d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810 13522d756322SRob Clark 13532d756322SRob Clark #define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL 0x00000010 13542d756322SRob Clark 135524e6938eSJonathan Marek #define REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL 0x00000011 135624e6938eSJonathan Marek 1357c28c82e9SRob Clark #define REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD 0x0000001c 1358c28c82e9SRob Clark #define A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE 0x00000001 1359c28c82e9SRob Clark 13602d756322SRob Clark #define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000001f 13612d756322SRob Clark 13622d756322SRob Clark #define REG_A6XX_RBBM_INT_CLEAR_CMD 0x00000037 13632d756322SRob Clark 13642d756322SRob Clark #define REG_A6XX_RBBM_INT_0_MASK 0x00000038 13652d756322SRob Clark 13662d756322SRob Clark #define REG_A6XX_RBBM_SP_HYST_CNT 0x00000042 13672d756322SRob Clark 13682d756322SRob Clark #define REG_A6XX_RBBM_SW_RESET_CMD 0x00000043 13692d756322SRob Clark 13702d756322SRob Clark #define REG_A6XX_RBBM_RAC_THRESHOLD_CNT 0x00000044 13712d756322SRob Clark 13722d756322SRob Clark #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 13732d756322SRob Clark 13742d756322SRob Clark #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046 13752d756322SRob Clark 13762d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae 13772d756322SRob Clark 13782d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0 13792d756322SRob Clark 13802d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_SP1 0x000000b1 13812d756322SRob Clark 13822d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_SP2 0x000000b2 13832d756322SRob Clark 13842d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_SP3 0x000000b3 13852d756322SRob Clark 13862d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_SP0 0x000000b4 13872d756322SRob Clark 13882d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_SP1 0x000000b5 13892d756322SRob Clark 13902d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_SP2 0x000000b6 13912d756322SRob Clark 13922d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_SP3 0x000000b7 13932d756322SRob Clark 13942d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_SP0 0x000000b8 13952d756322SRob Clark 13962d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_SP1 0x000000b9 13972d756322SRob Clark 13982d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_SP2 0x000000ba 13992d756322SRob Clark 14002d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_SP3 0x000000bb 14012d756322SRob Clark 14022d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_SP0 0x000000bc 14032d756322SRob Clark 14042d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_SP1 0x000000bd 14052d756322SRob Clark 14062d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_SP2 0x000000be 14072d756322SRob Clark 14082d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_SP3 0x000000bf 14092d756322SRob Clark 14102d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TP0 0x000000c0 14112d756322SRob Clark 14122d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TP1 0x000000c1 14132d756322SRob Clark 14142d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TP2 0x000000c2 14152d756322SRob Clark 14162d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TP3 0x000000c3 14172d756322SRob Clark 14182d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_TP0 0x000000c4 14192d756322SRob Clark 14202d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_TP1 0x000000c5 14212d756322SRob Clark 14222d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_TP2 0x000000c6 14232d756322SRob Clark 14242d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_TP3 0x000000c7 14252d756322SRob Clark 14262d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_TP0 0x000000c8 14272d756322SRob Clark 14282d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_TP1 0x000000c9 14292d756322SRob Clark 14302d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_TP2 0x000000ca 14312d756322SRob Clark 14322d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_TP3 0x000000cb 14332d756322SRob Clark 14342d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_TP0 0x000000cc 14352d756322SRob Clark 14362d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_TP1 0x000000cd 14372d756322SRob Clark 14382d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_TP2 0x000000ce 14392d756322SRob Clark 14402d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_TP3 0x000000cf 14412d756322SRob Clark 14422d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TP0 0x000000d0 14432d756322SRob Clark 14442d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TP1 0x000000d1 14452d756322SRob Clark 14462d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TP2 0x000000d2 14472d756322SRob Clark 14482d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TP3 0x000000d3 14492d756322SRob Clark 14502d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY2_TP0 0x000000d4 14512d756322SRob Clark 14522d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY2_TP1 0x000000d5 14532d756322SRob Clark 14542d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY2_TP2 0x000000d6 14552d756322SRob Clark 14562d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY2_TP3 0x000000d7 14572d756322SRob Clark 14582d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY3_TP0 0x000000d8 14592d756322SRob Clark 14602d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY3_TP1 0x000000d9 14612d756322SRob Clark 14622d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY3_TP2 0x000000da 14632d756322SRob Clark 14642d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY3_TP3 0x000000db 14652d756322SRob Clark 14662d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY4_TP0 0x000000dc 14672d756322SRob Clark 14682d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY4_TP1 0x000000dd 14692d756322SRob Clark 14702d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY4_TP2 0x000000de 14712d756322SRob Clark 14722d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY4_TP3 0x000000df 14732d756322SRob Clark 14742d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TP0 0x000000e0 14752d756322SRob Clark 14762d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TP1 0x000000e1 14772d756322SRob Clark 14782d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TP2 0x000000e2 14792d756322SRob Clark 14802d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TP3 0x000000e3 14812d756322SRob Clark 14822d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST2_TP0 0x000000e4 14832d756322SRob Clark 14842d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST2_TP1 0x000000e5 14852d756322SRob Clark 14862d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST2_TP2 0x000000e6 14872d756322SRob Clark 14882d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST2_TP3 0x000000e7 14892d756322SRob Clark 14902d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST3_TP0 0x000000e8 14912d756322SRob Clark 14922d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST3_TP1 0x000000e9 14932d756322SRob Clark 14942d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST3_TP2 0x000000ea 14952d756322SRob Clark 14962d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST3_TP3 0x000000eb 14972d756322SRob Clark 14982d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST4_TP0 0x000000ec 14992d756322SRob Clark 15002d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST4_TP1 0x000000ed 15012d756322SRob Clark 15022d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST4_TP2 0x000000ee 15032d756322SRob Clark 15042d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST4_TP3 0x000000ef 15052d756322SRob Clark 15062d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RB0 0x000000f0 15072d756322SRob Clark 15082d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RB1 0x000000f1 15092d756322SRob Clark 15102d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RB2 0x000000f2 15112d756322SRob Clark 15122d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RB3 0x000000f3 15132d756322SRob Clark 15142d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RB0 0x000000f4 15152d756322SRob Clark 15162d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RB1 0x000000f5 15172d756322SRob Clark 15182d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RB2 0x000000f6 15192d756322SRob Clark 15202d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RB3 0x000000f7 15212d756322SRob Clark 15222d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_CCU0 0x000000f8 15232d756322SRob Clark 15242d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_CCU1 0x000000f9 15252d756322SRob Clark 15262d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_CCU2 0x000000fa 15272d756322SRob Clark 15282d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_CCU3 0x000000fb 15292d756322SRob Clark 15302d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000100 15312d756322SRob Clark 15322d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000101 15332d756322SRob Clark 15342d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000102 15352d756322SRob Clark 15362d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000103 15372d756322SRob Clark 15382d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RAC 0x00000104 15392d756322SRob Clark 15402d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RAC 0x00000105 15412d756322SRob Clark 15422d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_RAC 0x00000106 15432d756322SRob Clark 15442d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RAC 0x00000107 15452d756322SRob Clark 15462d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000108 15472d756322SRob Clark 15482d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000109 15492d756322SRob Clark 15502d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000010a 15512d756322SRob Clark 15522d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_UCHE 0x0000010b 15532d756322SRob Clark 15542d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE 0x0000010c 15552d756322SRob Clark 15562d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE 0x0000010d 15572d756322SRob Clark 15582d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE 0x0000010e 15592d756322SRob Clark 15602d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_UCHE 0x0000010f 15612d756322SRob Clark 15622d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_UCHE 0x00000110 15632d756322SRob Clark 15642d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_MODE_VFD 0x00000111 15652d756322SRob Clark 15662d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_VFD 0x00000112 15672d756322SRob Clark 15682d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_VFD 0x00000113 15692d756322SRob Clark 15702d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_MODE_GPC 0x00000114 15712d756322SRob Clark 15722d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_GPC 0x00000115 15732d756322SRob Clark 15742d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_GPC 0x00000116 15752d756322SRob Clark 15762d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2 0x00000117 15772d756322SRob Clark 15782d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX 0x00000118 15792d756322SRob Clark 15802d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX 0x00000119 15812d756322SRob Clark 15822d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX 0x0000011a 15832d756322SRob Clark 15842d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_MODE_HLSQ 0x0000011b 15852d756322SRob Clark 15862d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ 0x0000011c 15872d756322SRob Clark 1588c28c82e9SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_HLSQ 0x0000011d 1589c28c82e9SRob Clark 1590c28c82e9SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE 0x00000120 1591c28c82e9SRob Clark 1592c28c82e9SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE 0x00000121 1593c28c82e9SRob Clark 1594c28c82e9SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122 1595c28c82e9SRob Clark 15962d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A 0x00000600 15972d756322SRob Clark 15982d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B 0x00000601 15992d756322SRob Clark 16002d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C 0x00000602 16012d756322SRob Clark 16022d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D 0x00000603 16032d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK 0x000000ff 16042d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT 0 16052d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val) 16062d756322SRob Clark { 16072d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK; 16082d756322SRob Clark } 16092d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK 0x0000ff00 16102d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT 8 16112d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val) 16122d756322SRob Clark { 16132d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK; 16142d756322SRob Clark } 16152d756322SRob Clark 16162d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT 0x00000604 16172d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f 16182d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0 16192d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) 16202d756322SRob Clark { 16212d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; 16222d756322SRob Clark } 16232d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000 16242d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12 16252d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) 16262d756322SRob Clark { 16272d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; 16282d756322SRob Clark } 16292d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000 16302d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28 16312d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) 16322d756322SRob Clark { 16332d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; 16342d756322SRob Clark } 16352d756322SRob Clark 16362d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM 0x00000605 16372d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000 16382d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24 16392d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) 16402d756322SRob Clark { 16412d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; 16422d756322SRob Clark } 16432d756322SRob Clark 16442d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 0x00000608 16452d756322SRob Clark 16462d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 0x00000609 16472d756322SRob Clark 16482d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 0x0000060a 16492d756322SRob Clark 16502d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 0x0000060b 16512d756322SRob Clark 16522d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 0x0000060c 16532d756322SRob Clark 16542d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 0x0000060d 16552d756322SRob Clark 16562d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 0x0000060e 16572d756322SRob Clark 16582d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 0x0000060f 16592d756322SRob Clark 16602d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000610 16612d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f 16622d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0 16632d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) 16642d756322SRob Clark { 16652d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; 16662d756322SRob Clark } 16672d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0 16682d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4 16692d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) 16702d756322SRob Clark { 16712d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; 16722d756322SRob Clark } 16732d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00 16742d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8 16752d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) 16762d756322SRob Clark { 16772d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; 16782d756322SRob Clark } 16792d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000 16802d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12 16812d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) 16822d756322SRob Clark { 16832d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; 16842d756322SRob Clark } 16852d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000 16862d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16 16872d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) 16882d756322SRob Clark { 16892d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; 16902d756322SRob Clark } 16912d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000 16922d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20 16932d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) 16942d756322SRob Clark { 16952d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; 16962d756322SRob Clark } 16972d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000 16982d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24 16992d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) 17002d756322SRob Clark { 17012d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; 17022d756322SRob Clark } 17032d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000 17042d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28 17052d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) 17062d756322SRob Clark { 17072d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; 17082d756322SRob Clark } 17092d756322SRob Clark 17102d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000611 17112d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f 17122d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0 17132d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) 17142d756322SRob Clark { 17152d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; 17162d756322SRob Clark } 17172d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0 17182d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4 17192d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) 17202d756322SRob Clark { 17212d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; 17222d756322SRob Clark } 17232d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00 17242d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8 17252d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) 17262d756322SRob Clark { 17272d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; 17282d756322SRob Clark } 17292d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000 17302d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12 17312d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) 17322d756322SRob Clark { 17332d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; 17342d756322SRob Clark } 17352d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000 17362d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16 17372d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) 17382d756322SRob Clark { 17392d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; 17402d756322SRob Clark } 17412d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000 17422d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20 17432d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) 17442d756322SRob Clark { 17452d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; 17462d756322SRob Clark } 17472d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000 17482d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24 17492d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) 17502d756322SRob Clark { 17512d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; 17522d756322SRob Clark } 17532d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000 17542d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28 17552d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) 17562d756322SRob Clark { 17572d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; 17582d756322SRob Clark } 17592d756322SRob Clark 17602d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000062f 17612d756322SRob Clark 17622d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630 17632d756322SRob Clark 1764*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_VSC_PERFCTR_VSC_SEL(uint32_t i0) { return 0x00000cd8 + 0x1*i0; } 17652d756322SRob Clark 17662d756322SRob Clark #define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800 17672d756322SRob Clark 17682d756322SRob Clark #define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000 17692d756322SRob Clark 17702d756322SRob Clark #define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00 17712d756322SRob Clark 17722d756322SRob Clark #define REG_A6XX_UCHE_MODE_CNTL 0x00000e01 17732d756322SRob Clark 17742d756322SRob Clark #define REG_A6XX_UCHE_WRITE_RANGE_MAX_LO 0x00000e05 17752d756322SRob Clark 17762d756322SRob Clark #define REG_A6XX_UCHE_WRITE_RANGE_MAX_HI 0x00000e06 17772d756322SRob Clark 17782d756322SRob Clark #define REG_A6XX_UCHE_WRITE_THRU_BASE_LO 0x00000e07 17792d756322SRob Clark 17802d756322SRob Clark #define REG_A6XX_UCHE_WRITE_THRU_BASE_HI 0x00000e08 17812d756322SRob Clark 17822d756322SRob Clark #define REG_A6XX_UCHE_TRAP_BASE_LO 0x00000e09 17832d756322SRob Clark 17842d756322SRob Clark #define REG_A6XX_UCHE_TRAP_BASE_HI 0x00000e0a 17852d756322SRob Clark 17862d756322SRob Clark #define REG_A6XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e0b 17872d756322SRob Clark 17882d756322SRob Clark #define REG_A6XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e0c 17892d756322SRob Clark 17902d756322SRob Clark #define REG_A6XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e0d 17912d756322SRob Clark 17922d756322SRob Clark #define REG_A6XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e0e 17932d756322SRob Clark 17942d756322SRob Clark #define REG_A6XX_UCHE_CACHE_WAYS 0x00000e17 17952d756322SRob Clark 17962d756322SRob Clark #define REG_A6XX_UCHE_FILTER_CNTL 0x00000e18 17972d756322SRob Clark 17982d756322SRob Clark #define REG_A6XX_UCHE_CLIENT_PF 0x00000e19 17992d756322SRob Clark #define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK 0x000000ff 18002d756322SRob Clark #define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT 0 18012d756322SRob Clark static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val) 18022d756322SRob Clark { 18032d756322SRob Clark return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK; 18042d756322SRob Clark } 18052d756322SRob Clark 1806*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_UCHE_PERFCTR_UCHE_SEL(uint32_t i0) { return 0x00000e1c + 0x1*i0; } 18072d756322SRob Clark 1808*cc4c26d4SRob Clark #define REG_A6XX_UCHE_CMDQ_CONFIG 0x00000e3c 18092d756322SRob Clark 18102d756322SRob Clark #define REG_A6XX_VBIF_VERSION 0x00003000 18112d756322SRob Clark 1812a69c5ed2SRob Clark #define REG_A6XX_VBIF_CLKON 0x00003001 1813a69c5ed2SRob Clark #define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000002 1814a69c5ed2SRob Clark 18152d756322SRob Clark #define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 18162d756322SRob Clark 18172d756322SRob Clark #define REG_A6XX_VBIF_XIN_HALT_CTRL0 0x00003080 18182d756322SRob Clark 18192d756322SRob Clark #define REG_A6XX_VBIF_XIN_HALT_CTRL1 0x00003081 18202d756322SRob Clark 1821a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084 1822a69c5ed2SRob Clark 1823a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS1_CTRL0 0x00003085 1824a69c5ed2SRob Clark 1825a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS1_CTRL1 0x00003086 1826a69c5ed2SRob Clark #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK 0x0000000f 1827a69c5ed2SRob Clark #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT 0 1828a69c5ed2SRob Clark static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val) 1829a69c5ed2SRob Clark { 1830a69c5ed2SRob Clark return ((val) << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK; 1831a69c5ed2SRob Clark } 1832a69c5ed2SRob Clark 1833a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS2_CTRL0 0x00003087 1834a69c5ed2SRob Clark 1835a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS2_CTRL1 0x00003088 1836a69c5ed2SRob Clark #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK 0x000001ff 1837a69c5ed2SRob Clark #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT 0 1838a69c5ed2SRob Clark static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val) 1839a69c5ed2SRob Clark { 1840a69c5ed2SRob Clark return ((val) << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK; 1841a69c5ed2SRob Clark } 1842a69c5ed2SRob Clark 1843a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS_OUT 0x0000308c 1844a69c5ed2SRob Clark 18452d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_SEL0 0x000030d0 18462d756322SRob Clark 18472d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_SEL1 0x000030d1 18482d756322SRob Clark 18492d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_SEL2 0x000030d2 18502d756322SRob Clark 18512d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_SEL3 0x000030d3 18522d756322SRob Clark 18532d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_LOW0 0x000030d8 18542d756322SRob Clark 18552d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_LOW1 0x000030d9 18562d756322SRob Clark 18572d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_LOW2 0x000030da 18582d756322SRob Clark 18592d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_LOW3 0x000030db 18602d756322SRob Clark 18612d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_HIGH0 0x000030e0 18622d756322SRob Clark 18632d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_HIGH1 0x000030e1 18642d756322SRob Clark 18652d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_HIGH2 0x000030e2 18662d756322SRob Clark 18672d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_HIGH3 0x000030e3 18682d756322SRob Clark 18692d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_EN0 0x00003100 18702d756322SRob Clark 18712d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_EN1 0x00003101 18722d756322SRob Clark 18732d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_EN2 0x00003102 18742d756322SRob Clark 18752d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110 18762d756322SRob Clark 18772d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111 18782d756322SRob Clark 18792d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112 18802d756322SRob Clark 18812d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118 18822d756322SRob Clark 18832d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119 18842d756322SRob Clark 18852d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a 18862d756322SRob Clark 1887*cc4c26d4SRob Clark #define REG_A6XX_GBIF_SCACHE_CNTL0 0x00003c01 1888*cc4c26d4SRob Clark 1889e812744cSSharat Masetty #define REG_A6XX_GBIF_SCACHE_CNTL1 0x00003c02 1890e812744cSSharat Masetty 1891e812744cSSharat Masetty #define REG_A6XX_GBIF_QSB_SIDE0 0x00003c03 1892e812744cSSharat Masetty 1893e812744cSSharat Masetty #define REG_A6XX_GBIF_QSB_SIDE1 0x00003c04 1894e812744cSSharat Masetty 1895e812744cSSharat Masetty #define REG_A6XX_GBIF_QSB_SIDE2 0x00003c05 1896e812744cSSharat Masetty 1897e812744cSSharat Masetty #define REG_A6XX_GBIF_QSB_SIDE3 0x00003c06 1898e812744cSSharat Masetty 1899e812744cSSharat Masetty #define REG_A6XX_GBIF_HALT 0x00003c45 1900e812744cSSharat Masetty 1901e812744cSSharat Masetty #define REG_A6XX_GBIF_HALT_ACK 0x00003c46 1902e812744cSSharat Masetty 1903e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_PWR_CNT_EN 0x00003cc0 1904e812744cSSharat Masetty 1905e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_SEL 0x00003cc2 1906e812744cSSharat Masetty 1907e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_PWR_CNT_SEL 0x00003cc3 1908e812744cSSharat Masetty 1909e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_LOW0 0x00003cc4 1910e812744cSSharat Masetty 1911e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_LOW1 0x00003cc5 1912e812744cSSharat Masetty 1913e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_LOW2 0x00003cc6 1914e812744cSSharat Masetty 1915e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_LOW3 0x00003cc7 1916e812744cSSharat Masetty 1917e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_HIGH0 0x00003cc8 1918e812744cSSharat Masetty 1919e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_HIGH1 0x00003cc9 1920e812744cSSharat Masetty 1921e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_HIGH2 0x00003cca 1922e812744cSSharat Masetty 1923e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_HIGH3 0x00003ccb 1924e812744cSSharat Masetty 1925e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_LOW0 0x00003ccc 1926e812744cSSharat Masetty 1927e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_LOW1 0x00003ccd 1928e812744cSSharat Masetty 1929e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_LOW2 0x00003cce 1930e812744cSSharat Masetty 1931e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_HIGH0 0x00003ccf 1932e812744cSSharat Masetty 1933e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_HIGH1 0x00003cd0 1934e812744cSSharat Masetty 1935e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_HIGH2 0x00003cd1 1936e812744cSSharat Masetty 19372d756322SRob Clark #define REG_A6XX_VSC_BIN_SIZE 0x00000c02 19382d756322SRob Clark #define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff 19392d756322SRob Clark #define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 19402d756322SRob Clark static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 19412d756322SRob Clark { 19422d756322SRob Clark return ((val >> 5) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK; 19432d756322SRob Clark } 19442d756322SRob Clark #define A6XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001ff00 19452d756322SRob Clark #define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT 8 19462d756322SRob Clark static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 19472d756322SRob Clark { 19482d756322SRob Clark return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK; 19492d756322SRob Clark } 19502d756322SRob Clark 1951c28c82e9SRob Clark #define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS 0x00000c03 19522d756322SRob Clark 19532d756322SRob Clark #define REG_A6XX_VSC_BIN_COUNT 0x00000c06 19542d756322SRob Clark #define A6XX_VSC_BIN_COUNT_NX__MASK 0x000007fe 19552d756322SRob Clark #define A6XX_VSC_BIN_COUNT_NX__SHIFT 1 19562d756322SRob Clark static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val) 19572d756322SRob Clark { 19582d756322SRob Clark return ((val) << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK; 19592d756322SRob Clark } 19602d756322SRob Clark #define A6XX_VSC_BIN_COUNT_NY__MASK 0x001ff800 19612d756322SRob Clark #define A6XX_VSC_BIN_COUNT_NY__SHIFT 11 19622d756322SRob Clark static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val) 19632d756322SRob Clark { 19642d756322SRob Clark return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK; 19652d756322SRob Clark } 19662d756322SRob Clark 19672d756322SRob Clark static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 19682d756322SRob Clark 19692d756322SRob Clark static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 19702d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff 19712d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0 19722d756322SRob Clark static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) 19732d756322SRob Clark { 19742d756322SRob Clark return ((val) << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK; 19752d756322SRob Clark } 19762d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00 19772d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10 19782d756322SRob Clark static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) 19792d756322SRob Clark { 19802d756322SRob Clark return ((val) << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK; 19812d756322SRob Clark } 19822d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_W__MASK 0x03f00000 19832d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20 19842d756322SRob Clark static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) 19852d756322SRob Clark { 19862d756322SRob Clark return ((val) << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK; 19872d756322SRob Clark } 19882d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_H__MASK 0xfc000000 19892d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT 26 19902d756322SRob Clark static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) 19912d756322SRob Clark { 19922d756322SRob Clark return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK; 19932d756322SRob Clark } 19942d756322SRob Clark 1995c28c82e9SRob Clark #define REG_A6XX_VSC_PRIM_STRM_ADDRESS 0x00000c30 1996a69c5ed2SRob Clark 1997c28c82e9SRob Clark #define REG_A6XX_VSC_PRIM_STRM_PITCH 0x00000c32 19982d756322SRob Clark 1999c28c82e9SRob Clark #define REG_A6XX_VSC_PRIM_STRM_LIMIT 0x00000c33 20002d756322SRob Clark 2001c28c82e9SRob Clark #define REG_A6XX_VSC_DRAW_STRM_ADDRESS 0x00000c34 2002a69c5ed2SRob Clark 2003c28c82e9SRob Clark #define REG_A6XX_VSC_DRAW_STRM_PITCH 0x00000c36 20042d756322SRob Clark 2005c28c82e9SRob Clark #define REG_A6XX_VSC_DRAW_STRM_LIMIT 0x00000c37 2006c28c82e9SRob Clark 2007c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_STATE(uint32_t i0) { return 0x00000c38 + 0x1*i0; } 2008c28c82e9SRob Clark 2009c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_STATE_REG(uint32_t i0) { return 0x00000c38 + 0x1*i0; } 2010c28c82e9SRob Clark 2011c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE(uint32_t i0) { return 0x00000c58 + 0x1*i0; } 2012c28c82e9SRob Clark 2013c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0) { return 0x00000c58 + 0x1*i0; } 2014c28c82e9SRob Clark 2015c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; } 2016c28c82e9SRob Clark 2017c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; } 20182d756322SRob Clark 20192d756322SRob Clark #define REG_A6XX_UCHE_UNKNOWN_0E12 0x00000e12 20202d756322SRob Clark 2021c28c82e9SRob Clark #define REG_A6XX_GRAS_CL_CNTL 0x00008000 2022c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_CLIP_DISABLE 0x00000001 2023c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE 0x00000002 2024c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE 0x00000004 2025c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_UNK5 0x00000020 2026c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040 2027c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE 0x00000080 2028c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE 0x00000100 2029c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE 0x00000200 2030a69c5ed2SRob Clark 2031c28c82e9SRob Clark #define REG_A6XX_GRAS_VS_CL_CNTL 0x00008001 2032c28c82e9SRob Clark #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK 0x000000ff 2033c28c82e9SRob Clark #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT 0 2034c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val) 2035c28c82e9SRob Clark { 2036c28c82e9SRob Clark return ((val) << A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK; 2037c28c82e9SRob Clark } 2038c28c82e9SRob Clark #define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK 0x0000ff00 2039c28c82e9SRob Clark #define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT 8 2040c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val) 2041c28c82e9SRob Clark { 2042c28c82e9SRob Clark return ((val) << A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK; 2043c28c82e9SRob Clark } 20442d756322SRob Clark 2045c28c82e9SRob Clark #define REG_A6XX_GRAS_DS_CL_CNTL 0x00008002 2046c28c82e9SRob Clark #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK 0x000000ff 2047c28c82e9SRob Clark #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT 0 2048c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(uint32_t val) 2049c28c82e9SRob Clark { 2050c28c82e9SRob Clark return ((val) << A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK; 2051c28c82e9SRob Clark } 2052c28c82e9SRob Clark #define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK 0x0000ff00 2053c28c82e9SRob Clark #define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT 8 2054c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CULL_MASK(uint32_t val) 2055c28c82e9SRob Clark { 2056c28c82e9SRob Clark return ((val) << A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK; 2057c28c82e9SRob Clark } 2058c28c82e9SRob Clark 2059c28c82e9SRob Clark #define REG_A6XX_GRAS_GS_CL_CNTL 0x00008003 2060c28c82e9SRob Clark #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK 0x000000ff 2061c28c82e9SRob Clark #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT 0 2062c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(uint32_t val) 2063c28c82e9SRob Clark { 2064c28c82e9SRob Clark return ((val) << A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK; 2065c28c82e9SRob Clark } 2066c28c82e9SRob Clark #define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK 0x0000ff00 2067c28c82e9SRob Clark #define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT 8 2068c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CULL_MASK(uint32_t val) 2069c28c82e9SRob Clark { 2070c28c82e9SRob Clark return ((val) << A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK; 2071c28c82e9SRob Clark } 2072c28c82e9SRob Clark 2073c28c82e9SRob Clark #define REG_A6XX_GRAS_MAX_LAYER_INDEX 0x00008004 20742d756322SRob Clark 20752d756322SRob Clark #define REG_A6XX_GRAS_CNTL 0x00008005 2076c28c82e9SRob Clark #define A6XX_GRAS_CNTL_IJ_PERSP_PIXEL 0x00000001 2077c28c82e9SRob Clark #define A6XX_GRAS_CNTL_IJ_PERSP_CENTROID 0x00000002 2078c28c82e9SRob Clark #define A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE 0x00000004 2079c28c82e9SRob Clark #define A6XX_GRAS_CNTL_SIZE 0x00000008 2080c28c82e9SRob Clark #define A6XX_GRAS_CNTL_UNK4 0x00000010 2081c28c82e9SRob Clark #define A6XX_GRAS_CNTL_SIZE_PERSAMP 0x00000020 2082c28c82e9SRob Clark #define A6XX_GRAS_CNTL_COORD_MASK__MASK 0x000003c0 2083c28c82e9SRob Clark #define A6XX_GRAS_CNTL_COORD_MASK__SHIFT 6 2084c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CNTL_COORD_MASK(uint32_t val) 2085c28c82e9SRob Clark { 2086c28c82e9SRob Clark return ((val) << A6XX_GRAS_CNTL_COORD_MASK__SHIFT) & A6XX_GRAS_CNTL_COORD_MASK__MASK; 2087c28c82e9SRob Clark } 20882d756322SRob Clark 20892d756322SRob Clark #define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x00008006 2090c28c82e9SRob Clark #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000001ff 20912d756322SRob Clark #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0 20922d756322SRob Clark static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val) 20932d756322SRob Clark { 20942d756322SRob Clark return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK; 20952d756322SRob Clark } 2096c28c82e9SRob Clark #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x0007fc00 20972d756322SRob Clark #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10 20982d756322SRob Clark static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) 20992d756322SRob Clark { 21002d756322SRob Clark return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK; 21012d756322SRob Clark } 21022d756322SRob Clark 2103c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT(uint32_t i0) { return 0x00008010 + 0x6*i0; } 2104c28c82e9SRob Clark 2105c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0) { return 0x00008010 + 0x6*i0; } 2106c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff 2107c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0 2108c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET(float val) 21092d756322SRob Clark { 2110c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET__MASK; 21112d756322SRob Clark } 21122d756322SRob Clark 2113c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XSCALE(uint32_t i0) { return 0x00008011 + 0x6*i0; } 2114c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff 2115c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_XSCALE__SHIFT 0 2116c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE(float val) 21172d756322SRob Clark { 2118c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE__MASK; 21192d756322SRob Clark } 21202d756322SRob Clark 2121c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YOFFSET(uint32_t i0) { return 0x00008012 + 0x6*i0; } 2122c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff 2123c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0 2124c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET(float val) 21252d756322SRob Clark { 2126c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET__MASK; 21272d756322SRob Clark } 21282d756322SRob Clark 2129c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YSCALE(uint32_t i0) { return 0x00008013 + 0x6*i0; } 2130c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff 2131c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_YSCALE__SHIFT 0 2132c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE(float val) 21332d756322SRob Clark { 2134c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE__MASK; 21352d756322SRob Clark } 21362d756322SRob Clark 2137c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZOFFSET(uint32_t i0) { return 0x00008014 + 0x6*i0; } 2138c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff 2139c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0 2140c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET(float val) 21412d756322SRob Clark { 2142c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET__MASK; 21432d756322SRob Clark } 21442d756322SRob Clark 2145c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZSCALE(uint32_t i0) { return 0x00008015 + 0x6*i0; } 2146c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff 2147c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0 2148c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE(float val) 21492d756322SRob Clark { 2150c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE__MASK; 2151c28c82e9SRob Clark } 2152c28c82e9SRob Clark 2153c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP(uint32_t i0) { return 0x00008070 + 0x2*i0; } 2154c28c82e9SRob Clark 2155c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0) { return 0x00008070 + 0x2*i0; } 2156c28c82e9SRob Clark #define A6XX_GRAS_CL_Z_CLAMP_MIN__MASK 0xffffffff 2157c28c82e9SRob Clark #define A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT 0 2158c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MIN(float val) 2159c28c82e9SRob Clark { 2160c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MIN__MASK; 2161c28c82e9SRob Clark } 2162c28c82e9SRob Clark 2163c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MAX(uint32_t i0) { return 0x00008071 + 0x2*i0; } 2164c28c82e9SRob Clark #define A6XX_GRAS_CL_Z_CLAMP_MAX__MASK 0xffffffff 2165c28c82e9SRob Clark #define A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT 0 2166c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MAX(float val) 2167c28c82e9SRob Clark { 2168c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MAX__MASK; 21692d756322SRob Clark } 21702d756322SRob Clark 21712d756322SRob Clark #define REG_A6XX_GRAS_SU_CNTL 0x00008090 21722d756322SRob Clark #define A6XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001 21732d756322SRob Clark #define A6XX_GRAS_SU_CNTL_CULL_BACK 0x00000002 21742d756322SRob Clark #define A6XX_GRAS_SU_CNTL_FRONT_CW 0x00000004 21752d756322SRob Clark #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8 21762d756322SRob Clark #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3 21772d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) 21782d756322SRob Clark { 21792d756322SRob Clark return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK; 21802d756322SRob Clark } 21812d756322SRob Clark #define A6XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800 2182c28c82e9SRob Clark #define A6XX_GRAS_SU_CNTL_UNK12__MASK 0x00001000 2183c28c82e9SRob Clark #define A6XX_GRAS_SU_CNTL_UNK12__SHIFT 12 2184c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SU_CNTL_UNK12(uint32_t val) 2185c28c82e9SRob Clark { 2186c28c82e9SRob Clark return ((val) << A6XX_GRAS_SU_CNTL_UNK12__SHIFT) & A6XX_GRAS_SU_CNTL_UNK12__MASK; 2187c28c82e9SRob Clark } 21882d756322SRob Clark #define A6XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000 2189*cc4c26d4SRob Clark #define A6XX_GRAS_SU_CNTL_UNK15__MASK 0x00018000 2190c28c82e9SRob Clark #define A6XX_GRAS_SU_CNTL_UNK15__SHIFT 15 2191c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SU_CNTL_UNK15(uint32_t val) 2192c28c82e9SRob Clark { 2193c28c82e9SRob Clark return ((val) << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK; 2194c28c82e9SRob Clark } 2195*cc4c26d4SRob Clark #define A6XX_GRAS_SU_CNTL_UNK17 0x00020000 2196*cc4c26d4SRob Clark #define A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE 0x00040000 2197*cc4c26d4SRob Clark #define A6XX_GRAS_SU_CNTL_UNK19__MASK 0x00780000 2198*cc4c26d4SRob Clark #define A6XX_GRAS_SU_CNTL_UNK19__SHIFT 19 2199*cc4c26d4SRob Clark static inline uint32_t A6XX_GRAS_SU_CNTL_UNK19(uint32_t val) 2200*cc4c26d4SRob Clark { 2201*cc4c26d4SRob Clark return ((val) << A6XX_GRAS_SU_CNTL_UNK19__SHIFT) & A6XX_GRAS_SU_CNTL_UNK19__MASK; 2202*cc4c26d4SRob Clark } 22032d756322SRob Clark 22042d756322SRob Clark #define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091 22052d756322SRob Clark #define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 22062d756322SRob Clark #define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 22072d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val) 22082d756322SRob Clark { 22092d756322SRob Clark return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 22102d756322SRob Clark } 22112d756322SRob Clark #define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 22122d756322SRob Clark #define A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 22132d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MAX(float val) 22142d756322SRob Clark { 22152d756322SRob Clark return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 22162d756322SRob Clark } 22172d756322SRob Clark 22182d756322SRob Clark #define REG_A6XX_GRAS_SU_POINT_SIZE 0x00008092 2219c28c82e9SRob Clark #define A6XX_GRAS_SU_POINT_SIZE__MASK 0x0000ffff 22202d756322SRob Clark #define A6XX_GRAS_SU_POINT_SIZE__SHIFT 0 22212d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val) 22222d756322SRob Clark { 22232d756322SRob Clark return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK; 22242d756322SRob Clark } 22252d756322SRob Clark 2226a69c5ed2SRob Clark #define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL 0x00008094 2227c28c82e9SRob Clark #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003 2228c28c82e9SRob Clark #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0 2229c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val) 2230c28c82e9SRob Clark { 2231c28c82e9SRob Clark return ((val) << A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK; 2232c28c82e9SRob Clark } 2233a69c5ed2SRob Clark 22342d756322SRob Clark #define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE 0x00008095 22352d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff 22362d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 22372d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val) 22382d756322SRob Clark { 22392d756322SRob Clark return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; 22402d756322SRob Clark } 22412d756322SRob Clark 22422d756322SRob Clark #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00008096 22432d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 22442d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 22452d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 22462d756322SRob Clark { 22472d756322SRob Clark return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 22482d756322SRob Clark } 22492d756322SRob Clark 22502d756322SRob Clark #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x00008097 22512d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff 22522d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0 22532d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val) 22542d756322SRob Clark { 22552d756322SRob Clark return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK; 22562d756322SRob Clark } 22572d756322SRob Clark 22582d756322SRob Clark #define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO 0x00008098 22592d756322SRob Clark #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 22602d756322SRob Clark #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 22612d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) 22622d756322SRob Clark { 22632d756322SRob Clark return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; 22642d756322SRob Clark } 2265c28c82e9SRob Clark #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000008 2266c28c82e9SRob Clark #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT 3 2267c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3(uint32_t val) 2268c28c82e9SRob Clark { 2269c28c82e9SRob Clark return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK; 2270c28c82e9SRob Clark } 22712d756322SRob Clark 22722d756322SRob Clark #define REG_A6XX_GRAS_UNKNOWN_8099 0x00008099 22732d756322SRob Clark 2274c28c82e9SRob Clark #define REG_A6XX_GRAS_UNKNOWN_809A 0x0000809a 2275c28c82e9SRob Clark 2276c28c82e9SRob Clark #define REG_A6XX_GRAS_VS_LAYER_CNTL 0x0000809b 2277c28c82e9SRob Clark #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER 0x00000001 2278c28c82e9SRob Clark #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW 0x00000002 2279c28c82e9SRob Clark 2280c28c82e9SRob Clark #define REG_A6XX_GRAS_GS_LAYER_CNTL 0x0000809c 2281c28c82e9SRob Clark #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER 0x00000001 2282c28c82e9SRob Clark #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW 0x00000002 2283c28c82e9SRob Clark 2284c28c82e9SRob Clark #define REG_A6XX_GRAS_DS_LAYER_CNTL 0x0000809d 2285c28c82e9SRob Clark #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER 0x00000001 2286c28c82e9SRob Clark #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW 0x00000002 22872d756322SRob Clark 2288a69c5ed2SRob Clark #define REG_A6XX_GRAS_UNKNOWN_80A0 0x000080a0 2289a69c5ed2SRob Clark 2290c28c82e9SRob Clark #define REG_A6XX_GRAS_BIN_CONTROL 0x000080a1 2291c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_BINW__MASK 0x0000003f 2292c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT 0 2293c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val) 2294c28c82e9SRob Clark { 2295c28c82e9SRob Clark return ((val >> 5) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK; 2296c28c82e9SRob Clark } 2297c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_BINH__MASK 0x00007f00 2298c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT 8 2299c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val) 2300c28c82e9SRob Clark { 2301c28c82e9SRob Clark return ((val >> 4) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK; 2302c28c82e9SRob Clark } 2303c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_BINNING_PASS 0x00040000 2304c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_UNK19__MASK 0x00080000 2305c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_UNK19__SHIFT 19 2306c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK19(uint32_t val) 2307c28c82e9SRob Clark { 2308c28c82e9SRob Clark return ((val) << A6XX_GRAS_BIN_CONTROL_UNK19__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK19__MASK; 2309c28c82e9SRob Clark } 2310c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_UNK20__MASK 0x00100000 2311c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_UNK20__SHIFT 20 2312c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK20(uint32_t val) 2313c28c82e9SRob Clark { 2314c28c82e9SRob Clark return ((val) << A6XX_GRAS_BIN_CONTROL_UNK20__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK20__MASK; 2315c28c82e9SRob Clark } 2316c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_USE_VIZ 0x00200000 2317c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_UNK22__MASK 0x0fc00000 2318c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_UNK22__SHIFT 22 2319c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK22(uint32_t val) 2320c28c82e9SRob Clark { 2321c28c82e9SRob Clark return ((val) << A6XX_GRAS_BIN_CONTROL_UNK22__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK22__MASK; 2322c28c82e9SRob Clark } 2323c28c82e9SRob Clark 23242d756322SRob Clark #define REG_A6XX_GRAS_RAS_MSAA_CNTL 0x000080a2 23252d756322SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 23262d756322SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 23272d756322SRob Clark static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 23282d756322SRob Clark { 23292d756322SRob Clark return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK; 23302d756322SRob Clark } 2331c28c82e9SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK 0x00000004 2332c28c82e9SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT 2 2333c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK2(uint32_t val) 2334c28c82e9SRob Clark { 2335c28c82e9SRob Clark return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK; 2336c28c82e9SRob Clark } 2337c28c82e9SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK 0x00000008 2338c28c82e9SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT 3 2339c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK3(uint32_t val) 2340c28c82e9SRob Clark { 2341c28c82e9SRob Clark return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK; 2342c28c82e9SRob Clark } 23432d756322SRob Clark 23442d756322SRob Clark #define REG_A6XX_GRAS_DEST_MSAA_CNTL 0x000080a3 23452d756322SRob Clark #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 23462d756322SRob Clark #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 23472d756322SRob Clark static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 23482d756322SRob Clark { 23492d756322SRob Clark return ((val) << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK; 23502d756322SRob Clark } 23512d756322SRob Clark #define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 23522d756322SRob Clark 2353c28c82e9SRob Clark #define REG_A6XX_GRAS_SAMPLE_CONFIG 0x000080a4 2354c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_CONFIG_UNK0 0x00000001 2355c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002 23562d756322SRob Clark 2357c28c82e9SRob Clark #define REG_A6XX_GRAS_SAMPLE_LOCATION_0 0x000080a5 2358c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f 2359c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 2360c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) 2361c28c82e9SRob Clark { 2362c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; 2363c28c82e9SRob Clark } 2364c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 2365c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 2366c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) 2367c28c82e9SRob Clark { 2368c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; 2369c28c82e9SRob Clark } 2370c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 2371c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 2372c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) 2373c28c82e9SRob Clark { 2374c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; 2375c28c82e9SRob Clark } 2376c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 2377c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 2378c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) 2379c28c82e9SRob Clark { 2380c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; 2381c28c82e9SRob Clark } 2382c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 2383c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 2384c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) 2385c28c82e9SRob Clark { 2386c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; 2387c28c82e9SRob Clark } 2388c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 2389c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 2390c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) 2391c28c82e9SRob Clark { 2392c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; 2393c28c82e9SRob Clark } 2394c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 2395c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 2396c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) 2397c28c82e9SRob Clark { 2398c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; 2399c28c82e9SRob Clark } 2400c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 2401c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 2402c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) 2403c28c82e9SRob Clark { 2404c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; 2405c28c82e9SRob Clark } 24062d756322SRob Clark 2407c28c82e9SRob Clark #define REG_A6XX_GRAS_SAMPLE_LOCATION_1 0x000080a6 2408c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f 2409c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 2410c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) 2411c28c82e9SRob Clark { 2412c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; 2413c28c82e9SRob Clark } 2414c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 2415c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 2416c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) 2417c28c82e9SRob Clark { 2418c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; 2419c28c82e9SRob Clark } 2420c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 2421c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 2422c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) 2423c28c82e9SRob Clark { 2424c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; 2425c28c82e9SRob Clark } 2426c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 2427c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 2428c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) 2429c28c82e9SRob Clark { 2430c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; 2431c28c82e9SRob Clark } 2432c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 2433c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 2434c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) 2435c28c82e9SRob Clark { 2436c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; 2437c28c82e9SRob Clark } 2438c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 2439c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 2440c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) 2441c28c82e9SRob Clark { 2442c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; 2443c28c82e9SRob Clark } 2444c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 2445c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 2446c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) 2447c28c82e9SRob Clark { 2448c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; 2449c28c82e9SRob Clark } 2450c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 2451c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 2452c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) 2453c28c82e9SRob Clark { 2454c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; 2455c28c82e9SRob Clark } 24562d756322SRob Clark 24572d756322SRob Clark #define REG_A6XX_GRAS_UNKNOWN_80AF 0x000080af 24582d756322SRob Clark 2459c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR(uint32_t i0) { return 0x000080b0 + 0x2*i0; } 2460c28c82e9SRob Clark 2461c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0) { return 0x000080b0 + 0x2*i0; } 2462c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x0000ffff 2463c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 2464c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 24652d756322SRob Clark { 2466c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; 24672d756322SRob Clark } 2468c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0xffff0000 2469c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 2470c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 24712d756322SRob Clark { 2472c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; 24732d756322SRob Clark } 24742d756322SRob Clark 2475c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR(uint32_t i0) { return 0x000080b1 + 0x2*i0; } 2476c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x0000ffff 2477c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 2478c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 24792d756322SRob Clark { 2480c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; 24812d756322SRob Clark } 2482c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0xffff0000 2483c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 2484c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 24852d756322SRob Clark { 2486c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; 24872d756322SRob Clark } 24882d756322SRob Clark 2489c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(uint32_t i0) { return 0x000080d0 + 0x2*i0; } 2490c28c82e9SRob Clark 2491c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0) { return 0x000080d0 + 0x2*i0; } 2492c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK 0x0000ffff 2493c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT 0 2494c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(uint32_t val) 24952d756322SRob Clark { 2496c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK; 24972d756322SRob Clark } 2498c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK 0xffff0000 2499c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT 16 2500c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(uint32_t val) 25012d756322SRob Clark { 2502c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK; 25032d756322SRob Clark } 25042d756322SRob Clark 2505c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(uint32_t i0) { return 0x000080d1 + 0x2*i0; } 2506c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK 0x0000ffff 2507c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT 0 2508c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X(uint32_t val) 25092d756322SRob Clark { 2510c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK; 25112d756322SRob Clark } 2512c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK 0xffff0000 2513c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT 16 2514c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y(uint32_t val) 25152d756322SRob Clark { 2516c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK; 25172d756322SRob Clark } 25182d756322SRob Clark 25192d756322SRob Clark #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL 0x000080f0 2520c28c82e9SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00003fff 25212d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 25222d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 25232d756322SRob Clark { 25242d756322SRob Clark return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 25252d756322SRob Clark } 2526c28c82e9SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x3fff0000 25272d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 25282d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 25292d756322SRob Clark { 25302d756322SRob Clark return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 25312d756322SRob Clark } 25322d756322SRob Clark 25332d756322SRob Clark #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR 0x000080f1 2534c28c82e9SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00003fff 25352d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 25362d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 25372d756322SRob Clark { 25382d756322SRob Clark return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 25392d756322SRob Clark } 2540c28c82e9SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x3fff0000 25412d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 25422d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 25432d756322SRob Clark { 25442d756322SRob Clark return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 25452d756322SRob Clark } 25462d756322SRob Clark 25472d756322SRob Clark #define REG_A6XX_GRAS_LRZ_CNTL 0x00008100 25482d756322SRob Clark #define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001 25492d756322SRob Clark #define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002 25502d756322SRob Clark #define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004 2551c28c82e9SRob Clark #define A6XX_GRAS_LRZ_CNTL_FC_ENABLE 0x00000008 2552c28c82e9SRob Clark #define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE 0x00000010 2553*cc4c26d4SRob Clark #define A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE 0x00000020 2554*cc4c26d4SRob Clark #define A6XX_GRAS_LRZ_CNTL_UNK6__MASK 0x000003c0 2555*cc4c26d4SRob Clark #define A6XX_GRAS_LRZ_CNTL_UNK6__SHIFT 6 2556*cc4c26d4SRob Clark static inline uint32_t A6XX_GRAS_LRZ_CNTL_UNK6(uint32_t val) 2557c28c82e9SRob Clark { 2558*cc4c26d4SRob Clark return ((val) << A6XX_GRAS_LRZ_CNTL_UNK6__SHIFT) & A6XX_GRAS_LRZ_CNTL_UNK6__MASK; 2559c28c82e9SRob Clark } 25602d756322SRob Clark 2561a69c5ed2SRob Clark #define REG_A6XX_GRAS_UNKNOWN_8101 0x00008101 2562a69c5ed2SRob Clark 25632d756322SRob Clark #define REG_A6XX_GRAS_2D_BLIT_INFO 0x00008102 25642d756322SRob Clark #define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK 0x000000ff 25652d756322SRob Clark #define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT 0 2566c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(enum a6xx_format val) 25672d756322SRob Clark { 25682d756322SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK; 25692d756322SRob Clark } 25702d756322SRob Clark 2571c28c82e9SRob Clark #define REG_A6XX_GRAS_LRZ_BUFFER_BASE 0x00008103 2572c28c82e9SRob Clark #define A6XX_GRAS_LRZ_BUFFER_BASE__MASK 0xffffffff 2573c28c82e9SRob Clark #define A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT 0 2574c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_LRZ_BUFFER_BASE(uint32_t val) 2575c28c82e9SRob Clark { 2576c28c82e9SRob Clark return ((val) << A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_BUFFER_BASE__MASK; 2577c28c82e9SRob Clark } 2578c28c82e9SRob Clark 25792d756322SRob Clark #define REG_A6XX_GRAS_LRZ_BUFFER_PITCH 0x00008105 2580c28c82e9SRob Clark #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK 0x000000ff 25812d756322SRob Clark #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT 0 25822d756322SRob Clark static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val) 25832d756322SRob Clark { 25842d756322SRob Clark return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK; 25852d756322SRob Clark } 2586c28c82e9SRob Clark #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffffc00 2587c28c82e9SRob Clark #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT 10 25882d756322SRob Clark static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 25892d756322SRob Clark { 2590c28c82e9SRob Clark return ((val >> 4) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK; 25912d756322SRob Clark } 25922d756322SRob Clark 2593c28c82e9SRob Clark #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE 0x00008106 2594c28c82e9SRob Clark #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK 0xffffffff 2595c28c82e9SRob Clark #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT 0 2596c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(uint32_t val) 2597c28c82e9SRob Clark { 2598c28c82e9SRob Clark return ((val) << A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK; 2599c28c82e9SRob Clark } 2600c28c82e9SRob Clark 2601c28c82e9SRob Clark #define REG_A6XX_GRAS_SAMPLE_CNTL 0x00008109 2602c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001 2603c28c82e9SRob Clark 2604c28c82e9SRob Clark #define REG_A6XX_GRAS_UNKNOWN_810A 0x0000810a 2605c28c82e9SRob Clark #define A6XX_GRAS_UNKNOWN_810A_UNK0__MASK 0x000007ff 2606c28c82e9SRob Clark #define A6XX_GRAS_UNKNOWN_810A_UNK0__SHIFT 0 2607c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK0(uint32_t val) 2608c28c82e9SRob Clark { 2609c28c82e9SRob Clark return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK0__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK0__MASK; 2610c28c82e9SRob Clark } 2611c28c82e9SRob Clark #define A6XX_GRAS_UNKNOWN_810A_UNK16__MASK 0x07ff0000 2612c28c82e9SRob Clark #define A6XX_GRAS_UNKNOWN_810A_UNK16__SHIFT 16 2613c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK16(uint32_t val) 2614c28c82e9SRob Clark { 2615c28c82e9SRob Clark return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK16__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK16__MASK; 2616c28c82e9SRob Clark } 2617c28c82e9SRob Clark #define A6XX_GRAS_UNKNOWN_810A_UNK28__MASK 0xf0000000 2618c28c82e9SRob Clark #define A6XX_GRAS_UNKNOWN_810A_UNK28__SHIFT 28 2619c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK28(uint32_t val) 2620c28c82e9SRob Clark { 2621c28c82e9SRob Clark return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK28__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK28__MASK; 2622c28c82e9SRob Clark } 2623a69c5ed2SRob Clark 2624a69c5ed2SRob Clark #define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110 2625a69c5ed2SRob Clark 26262d756322SRob Clark #define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400 2627c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK 0x00000007 2628c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT 0 2629c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val) 2630c28c82e9SRob Clark { 2631c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK; 2632c28c82e9SRob Clark } 2633c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_UNK3__MASK 0x00000078 2634c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_UNK3__SHIFT 3 2635c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK3(uint32_t val) 2636c28c82e9SRob Clark { 2637c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK3__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK3__MASK; 2638c28c82e9SRob Clark } 2639c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR 0x00000080 2640ccdf7e28SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00 2641ccdf7e28SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8 2642c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val) 2643ccdf7e28SRob Clark { 2644ccdf7e28SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK; 2645ccdf7e28SRob Clark } 2646ccdf7e28SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR 0x00010000 2647c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK 0x00060000 2648c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT 17 2649c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK17(uint32_t val) 2650c28c82e9SRob Clark { 2651c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK; 2652c28c82e9SRob Clark } 2653c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_D24S8 0x00080000 2654c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK 0x00f00000 2655c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT 20 2656c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_MASK(uint32_t val) 2657c28c82e9SRob Clark { 2658c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK; 2659c28c82e9SRob Clark } 2660c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK 0x1f000000 2661c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT 24 2662c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val) 2663c28c82e9SRob Clark { 2664c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK; 2665c28c82e9SRob Clark } 2666c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_UNK29__MASK 0x20000000 2667c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_UNK29__SHIFT 29 2668c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK29(uint32_t val) 2669c28c82e9SRob Clark { 2670c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK29__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK29__MASK; 2671c28c82e9SRob Clark } 26722d756322SRob Clark 26732d756322SRob Clark #define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401 26742d756322SRob Clark 26752d756322SRob Clark #define REG_A6XX_GRAS_2D_SRC_BR_X 0x00008402 26762d756322SRob Clark 26772d756322SRob Clark #define REG_A6XX_GRAS_2D_SRC_TL_Y 0x00008403 26782d756322SRob Clark 26792d756322SRob Clark #define REG_A6XX_GRAS_2D_SRC_BR_Y 0x00008404 26802d756322SRob Clark 26812d756322SRob Clark #define REG_A6XX_GRAS_2D_DST_TL 0x00008405 2682c28c82e9SRob Clark #define A6XX_GRAS_2D_DST_TL_X__MASK 0x00003fff 26832d756322SRob Clark #define A6XX_GRAS_2D_DST_TL_X__SHIFT 0 26842d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val) 26852d756322SRob Clark { 26862d756322SRob Clark return ((val) << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK; 26872d756322SRob Clark } 2688c28c82e9SRob Clark #define A6XX_GRAS_2D_DST_TL_Y__MASK 0x3fff0000 26892d756322SRob Clark #define A6XX_GRAS_2D_DST_TL_Y__SHIFT 16 26902d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val) 26912d756322SRob Clark { 26922d756322SRob Clark return ((val) << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK; 26932d756322SRob Clark } 26942d756322SRob Clark 26952d756322SRob Clark #define REG_A6XX_GRAS_2D_DST_BR 0x00008406 2696c28c82e9SRob Clark #define A6XX_GRAS_2D_DST_BR_X__MASK 0x00003fff 26972d756322SRob Clark #define A6XX_GRAS_2D_DST_BR_X__SHIFT 0 26982d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val) 26992d756322SRob Clark { 27002d756322SRob Clark return ((val) << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK; 27012d756322SRob Clark } 2702c28c82e9SRob Clark #define A6XX_GRAS_2D_DST_BR_Y__MASK 0x3fff0000 27032d756322SRob Clark #define A6XX_GRAS_2D_DST_BR_Y__SHIFT 16 27042d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val) 27052d756322SRob Clark { 27062d756322SRob Clark return ((val) << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK; 27072d756322SRob Clark } 27082d756322SRob Clark 2709c28c82e9SRob Clark #define REG_A6XX_GRAS_2D_UNKNOWN_8407 0x00008407 2710c28c82e9SRob Clark 2711c28c82e9SRob Clark #define REG_A6XX_GRAS_2D_UNKNOWN_8408 0x00008408 2712c28c82e9SRob Clark 2713c28c82e9SRob Clark #define REG_A6XX_GRAS_2D_UNKNOWN_8409 0x00008409 2714c28c82e9SRob Clark 2715c28c82e9SRob Clark #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_1 0x0000840a 2716c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK 0x00003fff 2717c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT 0 2718c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_X(uint32_t val) 27192d756322SRob Clark { 2720c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK; 27212d756322SRob Clark } 2722c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK 0x3fff0000 2723c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT 16 2724c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(uint32_t val) 27252d756322SRob Clark { 2726c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK; 27272d756322SRob Clark } 27282d756322SRob Clark 2729c28c82e9SRob Clark #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_2 0x0000840b 2730c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK 0x00003fff 2731c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT 0 2732c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_X(uint32_t val) 27332d756322SRob Clark { 2734c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK; 27352d756322SRob Clark } 2736c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK 0x3fff0000 2737c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT 16 2738c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val) 27392d756322SRob Clark { 2740c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK; 27412d756322SRob Clark } 27422d756322SRob Clark 27432d756322SRob Clark #define REG_A6XX_GRAS_UNKNOWN_8600 0x00008600 27442d756322SRob Clark 2745c28c82e9SRob Clark #define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601 2746c28c82e9SRob Clark 2747*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_GRAS_PERFCTR_TSE_SEL(uint32_t i0) { return 0x00008610 + 0x1*i0; } 2748c28c82e9SRob Clark 2749*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_GRAS_PERFCTR_RAS_SEL(uint32_t i0) { return 0x00008614 + 0x1*i0; } 2750c28c82e9SRob Clark 2751*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_GRAS_PERFCTR_LRZ_SEL(uint32_t i0) { return 0x00008618 + 0x1*i0; } 2752c28c82e9SRob Clark 2753a69c5ed2SRob Clark #define REG_A6XX_RB_BIN_CONTROL 0x00008800 2754c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f 2755a69c5ed2SRob Clark #define A6XX_RB_BIN_CONTROL_BINW__SHIFT 0 2756a69c5ed2SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val) 2757a69c5ed2SRob Clark { 2758a69c5ed2SRob Clark return ((val >> 5) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK; 2759a69c5ed2SRob Clark } 2760c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL_BINH__MASK 0x00007f00 2761a69c5ed2SRob Clark #define A6XX_RB_BIN_CONTROL_BINH__SHIFT 8 2762a69c5ed2SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val) 2763a69c5ed2SRob Clark { 2764a69c5ed2SRob Clark return ((val >> 4) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK; 2765a69c5ed2SRob Clark } 2766a69c5ed2SRob Clark #define A6XX_RB_BIN_CONTROL_BINNING_PASS 0x00040000 2767c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL_UNK19__MASK 0x00080000 2768c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL_UNK19__SHIFT 19 2769c28c82e9SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL_UNK19(uint32_t val) 2770c28c82e9SRob Clark { 2771c28c82e9SRob Clark return ((val) << A6XX_RB_BIN_CONTROL_UNK19__SHIFT) & A6XX_RB_BIN_CONTROL_UNK19__MASK; 2772c28c82e9SRob Clark } 2773c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL_UNK20__MASK 0x00100000 2774c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL_UNK20__SHIFT 20 2775c28c82e9SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL_UNK20(uint32_t val) 2776c28c82e9SRob Clark { 2777c28c82e9SRob Clark return ((val) << A6XX_RB_BIN_CONTROL_UNK20__SHIFT) & A6XX_RB_BIN_CONTROL_UNK20__MASK; 2778c28c82e9SRob Clark } 2779a69c5ed2SRob Clark #define A6XX_RB_BIN_CONTROL_USE_VIZ 0x00200000 2780c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL_UNK22__MASK 0x07c00000 2781c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL_UNK22__SHIFT 22 2782c28c82e9SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL_UNK22(uint32_t val) 2783c28c82e9SRob Clark { 2784c28c82e9SRob Clark return ((val) << A6XX_RB_BIN_CONTROL_UNK22__SHIFT) & A6XX_RB_BIN_CONTROL_UNK22__MASK; 2785c28c82e9SRob Clark } 2786a69c5ed2SRob Clark 2787a69c5ed2SRob Clark #define REG_A6XX_RB_RENDER_CNTL 0x00008801 2788c28c82e9SRob Clark #define A6XX_RB_RENDER_CNTL_UNK3 0x00000008 2789a69c5ed2SRob Clark #define A6XX_RB_RENDER_CNTL_UNK4 0x00000010 2790c28c82e9SRob Clark #define A6XX_RB_RENDER_CNTL_UNK5__MASK 0x00000060 2791c28c82e9SRob Clark #define A6XX_RB_RENDER_CNTL_UNK5__SHIFT 5 2792c28c82e9SRob Clark static inline uint32_t A6XX_RB_RENDER_CNTL_UNK5(uint32_t val) 2793c28c82e9SRob Clark { 2794c28c82e9SRob Clark return ((val) << A6XX_RB_RENDER_CNTL_UNK5__SHIFT) & A6XX_RB_RENDER_CNTL_UNK5__MASK; 2795c28c82e9SRob Clark } 2796a69c5ed2SRob Clark #define A6XX_RB_RENDER_CNTL_BINNING 0x00000080 2797c28c82e9SRob Clark #define A6XX_RB_RENDER_CNTL_UNK8__MASK 0x00001f00 2798c28c82e9SRob Clark #define A6XX_RB_RENDER_CNTL_UNK8__SHIFT 8 2799c28c82e9SRob Clark static inline uint32_t A6XX_RB_RENDER_CNTL_UNK8(uint32_t val) 2800c28c82e9SRob Clark { 2801c28c82e9SRob Clark return ((val) << A6XX_RB_RENDER_CNTL_UNK8__SHIFT) & A6XX_RB_RENDER_CNTL_UNK8__MASK; 2802c28c82e9SRob Clark } 2803a69c5ed2SRob Clark #define A6XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000 2804a69c5ed2SRob Clark #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000 2805a69c5ed2SRob Clark #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16 2806a69c5ed2SRob Clark static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val) 2807a69c5ed2SRob Clark { 2808a69c5ed2SRob Clark return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK; 2809a69c5ed2SRob Clark } 2810a69c5ed2SRob Clark 28112d756322SRob Clark #define REG_A6XX_RB_RAS_MSAA_CNTL 0x00008802 28122d756322SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 28132d756322SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 28142d756322SRob Clark static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 28152d756322SRob Clark { 28162d756322SRob Clark return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK; 28172d756322SRob Clark } 2818c28c82e9SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK 0x00000004 2819c28c82e9SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT 2 2820c28c82e9SRob Clark static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK2(uint32_t val) 2821c28c82e9SRob Clark { 2822c28c82e9SRob Clark return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK; 2823c28c82e9SRob Clark } 2824c28c82e9SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK 0x00000008 2825c28c82e9SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT 3 2826c28c82e9SRob Clark static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK3(uint32_t val) 2827c28c82e9SRob Clark { 2828c28c82e9SRob Clark return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK; 2829c28c82e9SRob Clark } 28302d756322SRob Clark 28312d756322SRob Clark #define REG_A6XX_RB_DEST_MSAA_CNTL 0x00008803 28322d756322SRob Clark #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 28332d756322SRob Clark #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 28342d756322SRob Clark static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 28352d756322SRob Clark { 28362d756322SRob Clark return ((val) << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK; 28372d756322SRob Clark } 28382d756322SRob Clark #define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 28392d756322SRob Clark 2840c28c82e9SRob Clark #define REG_A6XX_RB_SAMPLE_CONFIG 0x00008804 2841c28c82e9SRob Clark #define A6XX_RB_SAMPLE_CONFIG_UNK0 0x00000001 2842c28c82e9SRob Clark #define A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002 28432d756322SRob Clark 2844c28c82e9SRob Clark #define REG_A6XX_RB_SAMPLE_LOCATION_0 0x00008805 2845c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f 2846c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 2847c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) 2848c28c82e9SRob Clark { 2849c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; 2850c28c82e9SRob Clark } 2851c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 2852c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 2853c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) 2854c28c82e9SRob Clark { 2855c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; 2856c28c82e9SRob Clark } 2857c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 2858c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 2859c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) 2860c28c82e9SRob Clark { 2861c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; 2862c28c82e9SRob Clark } 2863c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 2864c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 2865c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) 2866c28c82e9SRob Clark { 2867c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; 2868c28c82e9SRob Clark } 2869c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 2870c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 2871c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) 2872c28c82e9SRob Clark { 2873c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; 2874c28c82e9SRob Clark } 2875c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 2876c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 2877c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) 2878c28c82e9SRob Clark { 2879c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; 2880c28c82e9SRob Clark } 2881c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 2882c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 2883c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) 2884c28c82e9SRob Clark { 2885c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; 2886c28c82e9SRob Clark } 2887c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 2888c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 2889c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) 2890c28c82e9SRob Clark { 2891c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; 2892c28c82e9SRob Clark } 28932d756322SRob Clark 2894c28c82e9SRob Clark #define REG_A6XX_RB_SAMPLE_LOCATION_1 0x00008806 2895c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f 2896c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 2897c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) 2898c28c82e9SRob Clark { 2899c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; 2900c28c82e9SRob Clark } 2901c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 2902c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 2903c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) 2904c28c82e9SRob Clark { 2905c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; 2906c28c82e9SRob Clark } 2907c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 2908c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 2909c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) 2910c28c82e9SRob Clark { 2911c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; 2912c28c82e9SRob Clark } 2913c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 2914c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 2915c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) 2916c28c82e9SRob Clark { 2917c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; 2918c28c82e9SRob Clark } 2919c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 2920c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 2921c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) 2922c28c82e9SRob Clark { 2923c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; 2924c28c82e9SRob Clark } 2925c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 2926c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 2927c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) 2928c28c82e9SRob Clark { 2929c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; 2930c28c82e9SRob Clark } 2931c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 2932c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 2933c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) 2934c28c82e9SRob Clark { 2935c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; 2936c28c82e9SRob Clark } 2937c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 2938c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 2939c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) 2940c28c82e9SRob Clark { 2941c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; 2942c28c82e9SRob Clark } 29432d756322SRob Clark 29442d756322SRob Clark #define REG_A6XX_RB_RENDER_CONTROL0 0x00008809 2945c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL 0x00000001 2946c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID 0x00000002 2947c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE 0x00000004 2948c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_SIZE 0x00000008 2949c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_UNK4 0x00000010 2950c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP 0x00000020 2951c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK 0x000003c0 2952c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT 6 2953c28c82e9SRob Clark static inline uint32_t A6XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val) 2954c28c82e9SRob Clark { 2955c28c82e9SRob Clark return ((val) << A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK; 2956c28c82e9SRob Clark } 29572d756322SRob Clark #define A6XX_RB_RENDER_CONTROL0_UNK10 0x00000400 29582d756322SRob Clark 29592d756322SRob Clark #define REG_A6XX_RB_RENDER_CONTROL1 0x0000880a 29602d756322SRob Clark #define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001 2961c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL1_UNK1 0x00000002 2962c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL1_FACENESS 0x00000004 29632d756322SRob Clark #define A6XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000008 2964c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL1_UNK4 0x00000010 2965c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL1_UNK5 0x00000020 2966c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL1_SIZE 0x00000040 2967c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL1_UNK7 0x00000080 2968c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL1_UNK8 0x00000100 29692d756322SRob Clark 29702d756322SRob Clark #define REG_A6XX_RB_FS_OUTPUT_CNTL0 0x0000880b 2971c28c82e9SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001 29722d756322SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z 0x00000002 2973c28c82e9SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK 0x00000004 2974c28c82e9SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF 0x00000008 29752d756322SRob Clark 29762d756322SRob Clark #define REG_A6XX_RB_FS_OUTPUT_CNTL1 0x0000880c 29772d756322SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f 29782d756322SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT 0 29792d756322SRob Clark static inline uint32_t A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val) 29802d756322SRob Clark { 29812d756322SRob Clark return ((val) << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK; 29822d756322SRob Clark } 29832d756322SRob Clark 29842d756322SRob Clark #define REG_A6XX_RB_RENDER_COMPONENTS 0x0000880d 29852d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f 29862d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0 29872d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) 29882d756322SRob Clark { 29892d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK; 29902d756322SRob Clark } 29912d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0 29922d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4 29932d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) 29942d756322SRob Clark { 29952d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK; 29962d756322SRob Clark } 29972d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00 29982d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8 29992d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) 30002d756322SRob Clark { 30012d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK; 30022d756322SRob Clark } 30032d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000 30042d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12 30052d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) 30062d756322SRob Clark { 30072d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK; 30082d756322SRob Clark } 30092d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000 30102d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16 30112d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) 30122d756322SRob Clark { 30132d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK; 30142d756322SRob Clark } 30152d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000 30162d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20 30172d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) 30182d756322SRob Clark { 30192d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK; 30202d756322SRob Clark } 30212d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000 30222d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24 30232d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) 30242d756322SRob Clark { 30252d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK; 30262d756322SRob Clark } 30272d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000 30282d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28 30292d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) 30302d756322SRob Clark { 30312d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK; 30322d756322SRob Clark } 30332d756322SRob Clark 30342d756322SRob Clark #define REG_A6XX_RB_DITHER_CNTL 0x0000880e 30352d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK 0x00000003 30362d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT 0 30372d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val) 30382d756322SRob Clark { 30392d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK; 30402d756322SRob Clark } 30412d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK 0x0000000c 30422d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT 2 30432d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val) 30442d756322SRob Clark { 30452d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK; 30462d756322SRob Clark } 30472d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK 0x00000030 30482d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT 4 30492d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val) 30502d756322SRob Clark { 30512d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK; 30522d756322SRob Clark } 30532d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK 0x000000c0 30542d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT 6 30552d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val) 30562d756322SRob Clark { 30572d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK; 30582d756322SRob Clark } 30592d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK 0x00000300 30602d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT 8 30612d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val) 30622d756322SRob Clark { 30632d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK; 30642d756322SRob Clark } 30652d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK 0x00000c00 30662d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT 10 30672d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val) 30682d756322SRob Clark { 30692d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK; 30702d756322SRob Clark } 30712d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK 0x00001000 30722d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT 12 30732d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val) 30742d756322SRob Clark { 30752d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK; 30762d756322SRob Clark } 30772d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK 0x0000c000 30782d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT 14 30792d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val) 30802d756322SRob Clark { 30812d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK; 30822d756322SRob Clark } 30832d756322SRob Clark 30842d756322SRob Clark #define REG_A6XX_RB_SRGB_CNTL 0x0000880f 30852d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT0 0x00000001 30862d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT1 0x00000002 30872d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT2 0x00000004 30882d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT3 0x00000008 30892d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT4 0x00000010 30902d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT5 0x00000020 30912d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT6 0x00000040 30922d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT7 0x00000080 30932d756322SRob Clark 3094c28c82e9SRob Clark #define REG_A6XX_RB_SAMPLE_CNTL 0x00008810 3095c28c82e9SRob Clark #define A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001 3096a69c5ed2SRob Clark 3097a69c5ed2SRob Clark #define REG_A6XX_RB_UNKNOWN_8811 0x00008811 3098a69c5ed2SRob Clark 30992d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8818 0x00008818 31002d756322SRob Clark 31012d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8819 0x00008819 31022d756322SRob Clark 31032d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881A 0x0000881a 31042d756322SRob Clark 31052d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881B 0x0000881b 31062d756322SRob Clark 31072d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881C 0x0000881c 31082d756322SRob Clark 31092d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881D 0x0000881d 31102d756322SRob Clark 31112d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881E 0x0000881e 31122d756322SRob Clark 31132d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; } 31142d756322SRob Clark 31152d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; } 31162d756322SRob Clark #define A6XX_RB_MRT_CONTROL_BLEND 0x00000001 31172d756322SRob Clark #define A6XX_RB_MRT_CONTROL_BLEND2 0x00000002 31182d756322SRob Clark #define A6XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004 31192d756322SRob Clark #define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078 31202d756322SRob Clark #define A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3 31212d756322SRob Clark static inline uint32_t A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) 31222d756322SRob Clark { 31232d756322SRob Clark return ((val) << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK; 31242d756322SRob Clark } 31252d756322SRob Clark #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780 31262d756322SRob Clark #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7 31272d756322SRob Clark static inline uint32_t A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 31282d756322SRob Clark { 31292d756322SRob Clark return ((val) << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 31302d756322SRob Clark } 31312d756322SRob Clark 31322d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; } 31332d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 31342d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 31352d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 31362d756322SRob Clark { 31372d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 31382d756322SRob Clark } 31392d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 31402d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 31412d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 31422d756322SRob Clark { 31432d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 31442d756322SRob Clark } 31452d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 31462d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 31472d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 31482d756322SRob Clark { 31492d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 31502d756322SRob Clark } 31512d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 31522d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 31532d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 31542d756322SRob Clark { 31552d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 31562d756322SRob Clark } 31572d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 31582d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 31592d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 31602d756322SRob Clark { 31612d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 31622d756322SRob Clark } 31632d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 31642d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 31652d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 31662d756322SRob Clark { 31672d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 31682d756322SRob Clark } 31692d756322SRob Clark 31702d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; } 31712d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff 31722d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 3173c28c82e9SRob Clark static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val) 31742d756322SRob Clark { 31752d756322SRob Clark return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 31762d756322SRob Clark } 31772d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300 31782d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8 31792d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val) 31802d756322SRob Clark { 31812d756322SRob Clark return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 31822d756322SRob Clark } 3183c28c82e9SRob Clark #define A6XX_RB_MRT_BUF_INFO_UNK10__MASK 0x00000400 3184c28c82e9SRob Clark #define A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT 10 3185c28c82e9SRob Clark static inline uint32_t A6XX_RB_MRT_BUF_INFO_UNK10(uint32_t val) 3186c28c82e9SRob Clark { 3187c28c82e9SRob Clark return ((val) << A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT) & A6XX_RB_MRT_BUF_INFO_UNK10__MASK; 3188c28c82e9SRob Clark } 31892d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000 31902d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13 31912d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 31922d756322SRob Clark { 31932d756322SRob Clark return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 31942d756322SRob Clark } 31952d756322SRob Clark 31962d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; } 3197c28c82e9SRob Clark #define A6XX_RB_MRT_PITCH__MASK 0x0000ffff 31982d756322SRob Clark #define A6XX_RB_MRT_PITCH__SHIFT 0 31992d756322SRob Clark static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val) 32002d756322SRob Clark { 32012d756322SRob Clark return ((val >> 6) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK; 32022d756322SRob Clark } 32032d756322SRob Clark 32042d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; } 3205c28c82e9SRob Clark #define A6XX_RB_MRT_ARRAY_PITCH__MASK 0x1fffffff 32062d756322SRob Clark #define A6XX_RB_MRT_ARRAY_PITCH__SHIFT 0 32072d756322SRob Clark static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val) 32082d756322SRob Clark { 32092d756322SRob Clark return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK; 32102d756322SRob Clark } 32112d756322SRob Clark 3212c28c82e9SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; } 3213c28c82e9SRob Clark #define A6XX_RB_MRT_BASE__MASK 0xffffffff 3214c28c82e9SRob Clark #define A6XX_RB_MRT_BASE__SHIFT 0 3215c28c82e9SRob Clark static inline uint32_t A6XX_RB_MRT_BASE(uint32_t val) 3216c28c82e9SRob Clark { 3217c28c82e9SRob Clark return ((val) << A6XX_RB_MRT_BASE__SHIFT) & A6XX_RB_MRT_BASE__MASK; 3218c28c82e9SRob Clark } 3219c28c82e9SRob Clark 32202d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; } 3221c28c82e9SRob Clark #define A6XX_RB_MRT_BASE_GMEM__MASK 0xfffff000 3222c28c82e9SRob Clark #define A6XX_RB_MRT_BASE_GMEM__SHIFT 12 3223c28c82e9SRob Clark static inline uint32_t A6XX_RB_MRT_BASE_GMEM(uint32_t val) 3224c28c82e9SRob Clark { 3225c28c82e9SRob Clark return ((val >> 12) << A6XX_RB_MRT_BASE_GMEM__SHIFT) & A6XX_RB_MRT_BASE_GMEM__MASK; 3226c28c82e9SRob Clark } 32272d756322SRob Clark 32282d756322SRob Clark #define REG_A6XX_RB_BLEND_RED_F32 0x00008860 32292d756322SRob Clark #define A6XX_RB_BLEND_RED_F32__MASK 0xffffffff 32302d756322SRob Clark #define A6XX_RB_BLEND_RED_F32__SHIFT 0 32312d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_RED_F32(float val) 32322d756322SRob Clark { 32332d756322SRob Clark return ((fui(val)) << A6XX_RB_BLEND_RED_F32__SHIFT) & A6XX_RB_BLEND_RED_F32__MASK; 32342d756322SRob Clark } 32352d756322SRob Clark 32362d756322SRob Clark #define REG_A6XX_RB_BLEND_GREEN_F32 0x00008861 32372d756322SRob Clark #define A6XX_RB_BLEND_GREEN_F32__MASK 0xffffffff 32382d756322SRob Clark #define A6XX_RB_BLEND_GREEN_F32__SHIFT 0 32392d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_GREEN_F32(float val) 32402d756322SRob Clark { 32412d756322SRob Clark return ((fui(val)) << A6XX_RB_BLEND_GREEN_F32__SHIFT) & A6XX_RB_BLEND_GREEN_F32__MASK; 32422d756322SRob Clark } 32432d756322SRob Clark 32442d756322SRob Clark #define REG_A6XX_RB_BLEND_BLUE_F32 0x00008862 32452d756322SRob Clark #define A6XX_RB_BLEND_BLUE_F32__MASK 0xffffffff 32462d756322SRob Clark #define A6XX_RB_BLEND_BLUE_F32__SHIFT 0 32472d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_BLUE_F32(float val) 32482d756322SRob Clark { 32492d756322SRob Clark return ((fui(val)) << A6XX_RB_BLEND_BLUE_F32__SHIFT) & A6XX_RB_BLEND_BLUE_F32__MASK; 32502d756322SRob Clark } 32512d756322SRob Clark 32522d756322SRob Clark #define REG_A6XX_RB_BLEND_ALPHA_F32 0x00008863 32532d756322SRob Clark #define A6XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff 32542d756322SRob Clark #define A6XX_RB_BLEND_ALPHA_F32__SHIFT 0 32552d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_ALPHA_F32(float val) 32562d756322SRob Clark { 32572d756322SRob Clark return ((fui(val)) << A6XX_RB_BLEND_ALPHA_F32__SHIFT) & A6XX_RB_BLEND_ALPHA_F32__MASK; 32582d756322SRob Clark } 32592d756322SRob Clark 32602d756322SRob Clark #define REG_A6XX_RB_ALPHA_CONTROL 0x00008864 32612d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff 32622d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 32632d756322SRob Clark static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) 32642d756322SRob Clark { 32652d756322SRob Clark return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; 32662d756322SRob Clark } 32672d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 32682d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 32692d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 32702d756322SRob Clark static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 32712d756322SRob Clark { 32722d756322SRob Clark return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; 32732d756322SRob Clark } 32742d756322SRob Clark 32752d756322SRob Clark #define REG_A6XX_RB_BLEND_CNTL 0x00008865 32762d756322SRob Clark #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff 32772d756322SRob Clark #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 32782d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val) 32792d756322SRob Clark { 32802d756322SRob Clark return ((val) << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK; 32812d756322SRob Clark } 32822d756322SRob Clark #define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100 3283c28c82e9SRob Clark #define A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200 3284ccdf7e28SRob Clark #define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 3285c28c82e9SRob Clark #define A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE 0x00000800 32862d756322SRob Clark #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000 32872d756322SRob Clark #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16 32882d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val) 32892d756322SRob Clark { 32902d756322SRob Clark return ((val) << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK; 32912d756322SRob Clark } 32922d756322SRob Clark 3293a69c5ed2SRob Clark #define REG_A6XX_RB_DEPTH_PLANE_CNTL 0x00008870 3294c28c82e9SRob Clark #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003 3295c28c82e9SRob Clark #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0 3296c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val) 3297c28c82e9SRob Clark { 3298c28c82e9SRob Clark return ((val) << A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK; 3299c28c82e9SRob Clark } 3300a69c5ed2SRob Clark 33012d756322SRob Clark #define REG_A6XX_RB_DEPTH_CNTL 0x00008871 33022d756322SRob Clark #define A6XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001 33032d756322SRob Clark #define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002 33042d756322SRob Clark #define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c 33052d756322SRob Clark #define A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2 33062d756322SRob Clark static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) 33072d756322SRob Clark { 33082d756322SRob Clark return ((val) << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK; 33092d756322SRob Clark } 3310c28c82e9SRob Clark #define A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE 0x00000020 33112d756322SRob Clark #define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040 3312c28c82e9SRob Clark #define A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE 0x00000080 33132d756322SRob Clark 33142d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_INFO 0x00008872 33152d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 33162d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 33172d756322SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) 33182d756322SRob Clark { 33192d756322SRob Clark return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; 33202d756322SRob Clark } 3321c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000018 3322c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT 3 3323c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val) 3324c28c82e9SRob Clark { 3325c28c82e9SRob Clark return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK; 3326c28c82e9SRob Clark } 33272d756322SRob Clark 33282d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_PITCH 0x00008873 3329c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_PITCH__MASK 0x00003fff 33302d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0 33312d756322SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) 33322d756322SRob Clark { 33332d756322SRob Clark return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK; 33342d756322SRob Clark } 33352d756322SRob Clark 33362d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x00008874 3337c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0x0fffffff 33382d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0 33392d756322SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) 33402d756322SRob Clark { 33412d756322SRob Clark return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; 33422d756322SRob Clark } 33432d756322SRob Clark 3344c28c82e9SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_BASE 0x00008875 3345c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_BASE__MASK 0xffffffff 3346c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_BASE__SHIFT 0 3347c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE(uint32_t val) 3348c28c82e9SRob Clark { 3349c28c82e9SRob Clark return ((val) << A6XX_RB_DEPTH_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE__MASK; 3350c28c82e9SRob Clark } 3351c28c82e9SRob Clark 33522d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM 0x00008877 3353c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK 0xfffff000 3354c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT 12 3355c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE_GMEM(uint32_t val) 3356c28c82e9SRob Clark { 3357c28c82e9SRob Clark return ((val >> 12) << A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK; 3358c28c82e9SRob Clark } 33592d756322SRob Clark 3360c28c82e9SRob Clark #define REG_A6XX_RB_Z_BOUNDS_MIN 0x00008878 3361c28c82e9SRob Clark #define A6XX_RB_Z_BOUNDS_MIN__MASK 0xffffffff 3362c28c82e9SRob Clark #define A6XX_RB_Z_BOUNDS_MIN__SHIFT 0 3363c28c82e9SRob Clark static inline uint32_t A6XX_RB_Z_BOUNDS_MIN(float val) 3364c28c82e9SRob Clark { 3365c28c82e9SRob Clark return ((fui(val)) << A6XX_RB_Z_BOUNDS_MIN__SHIFT) & A6XX_RB_Z_BOUNDS_MIN__MASK; 3366c28c82e9SRob Clark } 33672d756322SRob Clark 3368c28c82e9SRob Clark #define REG_A6XX_RB_Z_BOUNDS_MAX 0x00008879 3369c28c82e9SRob Clark #define A6XX_RB_Z_BOUNDS_MAX__MASK 0xffffffff 3370c28c82e9SRob Clark #define A6XX_RB_Z_BOUNDS_MAX__SHIFT 0 3371c28c82e9SRob Clark static inline uint32_t A6XX_RB_Z_BOUNDS_MAX(float val) 3372c28c82e9SRob Clark { 3373c28c82e9SRob Clark return ((fui(val)) << A6XX_RB_Z_BOUNDS_MAX__SHIFT) & A6XX_RB_Z_BOUNDS_MAX__MASK; 3374c28c82e9SRob Clark } 33752d756322SRob Clark 33762d756322SRob Clark #define REG_A6XX_RB_STENCIL_CONTROL 0x00008880 33772d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 33782d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 33792d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 33802d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 33812d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 33822d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 33832d756322SRob Clark { 33842d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC__MASK; 33852d756322SRob Clark } 33862d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 33872d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 33882d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 33892d756322SRob Clark { 33902d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL__MASK; 33912d756322SRob Clark } 33922d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 33932d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 33942d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 33952d756322SRob Clark { 33962d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK; 33972d756322SRob Clark } 33982d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 33992d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 34002d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 34012d756322SRob Clark { 34022d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 34032d756322SRob Clark } 34042d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 34052d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 34062d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 34072d756322SRob Clark { 34082d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 34092d756322SRob Clark } 34102d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 34112d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 34122d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 34132d756322SRob Clark { 34142d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 34152d756322SRob Clark } 34162d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 34172d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 34182d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 34192d756322SRob Clark { 34202d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 34212d756322SRob Clark } 34222d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 34232d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 34242d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 34252d756322SRob Clark { 34262d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 34272d756322SRob Clark } 34282d756322SRob Clark 34292d756322SRob Clark #define REG_A6XX_RB_STENCIL_INFO 0x00008881 34302d756322SRob Clark #define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 3431c28c82e9SRob Clark #define A6XX_RB_STENCIL_INFO_UNK1 0x00000002 34322d756322SRob Clark 34332d756322SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_PITCH 0x00008882 3434c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_PITCH__MASK 0x00000fff 34352d756322SRob Clark #define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT 0 34362d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val) 34372d756322SRob Clark { 34382d756322SRob Clark return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK; 34392d756322SRob Clark } 34402d756322SRob Clark 34412d756322SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH 0x00008883 3442c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK 0x00ffffff 34432d756322SRob Clark #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT 0 34442d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val) 34452d756322SRob Clark { 34462d756322SRob Clark return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK; 34472d756322SRob Clark } 34482d756322SRob Clark 3449c28c82e9SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_BASE 0x00008884 3450c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_BASE__MASK 0xffffffff 3451c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_BASE__SHIFT 0 3452c28c82e9SRob Clark static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE(uint32_t val) 3453c28c82e9SRob Clark { 3454c28c82e9SRob Clark return ((val) << A6XX_RB_STENCIL_BUFFER_BASE__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE__MASK; 3455c28c82e9SRob Clark } 3456c28c82e9SRob Clark 34572d756322SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM 0x00008886 3458c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK 0xfffff000 3459c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT 12 3460c28c82e9SRob Clark static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE_GMEM(uint32_t val) 3461c28c82e9SRob Clark { 3462c28c82e9SRob Clark return ((val >> 12) << A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK; 3463c28c82e9SRob Clark } 34642d756322SRob Clark 34652d756322SRob Clark #define REG_A6XX_RB_STENCILREF 0x00008887 34662d756322SRob Clark #define A6XX_RB_STENCILREF_REF__MASK 0x000000ff 34672d756322SRob Clark #define A6XX_RB_STENCILREF_REF__SHIFT 0 34682d756322SRob Clark static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val) 34692d756322SRob Clark { 34702d756322SRob Clark return ((val) << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK; 34712d756322SRob Clark } 3472a69c5ed2SRob Clark #define A6XX_RB_STENCILREF_BFREF__MASK 0x0000ff00 3473a69c5ed2SRob Clark #define A6XX_RB_STENCILREF_BFREF__SHIFT 8 3474a69c5ed2SRob Clark static inline uint32_t A6XX_RB_STENCILREF_BFREF(uint32_t val) 3475a69c5ed2SRob Clark { 3476a69c5ed2SRob Clark return ((val) << A6XX_RB_STENCILREF_BFREF__SHIFT) & A6XX_RB_STENCILREF_BFREF__MASK; 3477a69c5ed2SRob Clark } 34782d756322SRob Clark 34792d756322SRob Clark #define REG_A6XX_RB_STENCILMASK 0x00008888 34802d756322SRob Clark #define A6XX_RB_STENCILMASK_MASK__MASK 0x000000ff 34812d756322SRob Clark #define A6XX_RB_STENCILMASK_MASK__SHIFT 0 34822d756322SRob Clark static inline uint32_t A6XX_RB_STENCILMASK_MASK(uint32_t val) 34832d756322SRob Clark { 34842d756322SRob Clark return ((val) << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK; 34852d756322SRob Clark } 3486a69c5ed2SRob Clark #define A6XX_RB_STENCILMASK_BFMASK__MASK 0x0000ff00 3487a69c5ed2SRob Clark #define A6XX_RB_STENCILMASK_BFMASK__SHIFT 8 3488a69c5ed2SRob Clark static inline uint32_t A6XX_RB_STENCILMASK_BFMASK(uint32_t val) 3489a69c5ed2SRob Clark { 3490a69c5ed2SRob Clark return ((val) << A6XX_RB_STENCILMASK_BFMASK__SHIFT) & A6XX_RB_STENCILMASK_BFMASK__MASK; 3491a69c5ed2SRob Clark } 34922d756322SRob Clark 34932d756322SRob Clark #define REG_A6XX_RB_STENCILWRMASK 0x00008889 34942d756322SRob Clark #define A6XX_RB_STENCILWRMASK_WRMASK__MASK 0x000000ff 34952d756322SRob Clark #define A6XX_RB_STENCILWRMASK_WRMASK__SHIFT 0 34962d756322SRob Clark static inline uint32_t A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val) 34972d756322SRob Clark { 34982d756322SRob Clark return ((val) << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK; 34992d756322SRob Clark } 3500a69c5ed2SRob Clark #define A6XX_RB_STENCILWRMASK_BFWRMASK__MASK 0x0000ff00 3501a69c5ed2SRob Clark #define A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT 8 3502a69c5ed2SRob Clark static inline uint32_t A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val) 3503a69c5ed2SRob Clark { 3504a69c5ed2SRob Clark return ((val) << A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_BFWRMASK__MASK; 3505a69c5ed2SRob Clark } 35062d756322SRob Clark 35072d756322SRob Clark #define REG_A6XX_RB_WINDOW_OFFSET 0x00008890 3508c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET_X__MASK 0x00003fff 35092d756322SRob Clark #define A6XX_RB_WINDOW_OFFSET_X__SHIFT 0 35102d756322SRob Clark static inline uint32_t A6XX_RB_WINDOW_OFFSET_X(uint32_t val) 35112d756322SRob Clark { 35122d756322SRob Clark return ((val) << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK; 35132d756322SRob Clark } 3514c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET_Y__MASK 0x3fff0000 35152d756322SRob Clark #define A6XX_RB_WINDOW_OFFSET_Y__SHIFT 16 35162d756322SRob Clark static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val) 35172d756322SRob Clark { 35182d756322SRob Clark return ((val) << A6XX_RB_WINDOW_OFFSET_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET_Y__MASK; 35192d756322SRob Clark } 35202d756322SRob Clark 35212d756322SRob Clark #define REG_A6XX_RB_SAMPLE_COUNT_CONTROL 0x00008891 3522c28c82e9SRob Clark #define A6XX_RB_SAMPLE_COUNT_CONTROL_UNK0 0x00000001 35232d756322SRob Clark #define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 35242d756322SRob Clark 3525ccdf7e28SRob Clark #define REG_A6XX_RB_LRZ_CNTL 0x00008898 3526ccdf7e28SRob Clark #define A6XX_RB_LRZ_CNTL_ENABLE 0x00000001 3527ccdf7e28SRob Clark 3528c28c82e9SRob Clark #define REG_A6XX_RB_Z_CLAMP_MIN 0x000088c0 3529c28c82e9SRob Clark #define A6XX_RB_Z_CLAMP_MIN__MASK 0xffffffff 3530c28c82e9SRob Clark #define A6XX_RB_Z_CLAMP_MIN__SHIFT 0 3531c28c82e9SRob Clark static inline uint32_t A6XX_RB_Z_CLAMP_MIN(float val) 3532c28c82e9SRob Clark { 3533c28c82e9SRob Clark return ((fui(val)) << A6XX_RB_Z_CLAMP_MIN__SHIFT) & A6XX_RB_Z_CLAMP_MIN__MASK; 3534c28c82e9SRob Clark } 3535c28c82e9SRob Clark 3536c28c82e9SRob Clark #define REG_A6XX_RB_Z_CLAMP_MAX 0x000088c1 3537c28c82e9SRob Clark #define A6XX_RB_Z_CLAMP_MAX__MASK 0xffffffff 3538c28c82e9SRob Clark #define A6XX_RB_Z_CLAMP_MAX__SHIFT 0 3539c28c82e9SRob Clark static inline uint32_t A6XX_RB_Z_CLAMP_MAX(float val) 3540c28c82e9SRob Clark { 3541c28c82e9SRob Clark return ((fui(val)) << A6XX_RB_Z_CLAMP_MAX__SHIFT) & A6XX_RB_Z_CLAMP_MAX__MASK; 3542c28c82e9SRob Clark } 3543c28c82e9SRob Clark 35442d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_88D0 0x000088d0 3545c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_88D0_UNK0__MASK 0x00001fff 3546c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT 0 3547c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK0(uint32_t val) 3548c28c82e9SRob Clark { 3549c28c82e9SRob Clark return ((val) << A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK0__MASK; 3550c28c82e9SRob Clark } 3551c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_88D0_UNK16__MASK 0x07ff0000 3552c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT 16 3553c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK16(uint32_t val) 3554c28c82e9SRob Clark { 3555c28c82e9SRob Clark return ((val) << A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK16__MASK; 3556c28c82e9SRob Clark } 35572d756322SRob Clark 35582d756322SRob Clark #define REG_A6XX_RB_BLIT_SCISSOR_TL 0x000088d1 3559c28c82e9SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_X__MASK 0x00003fff 35602d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT 0 35612d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val) 35622d756322SRob Clark { 35632d756322SRob Clark return ((val) << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK; 35642d756322SRob Clark } 3565c28c82e9SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK 0x3fff0000 35662d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT 16 35672d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val) 35682d756322SRob Clark { 35692d756322SRob Clark return ((val) << A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_Y__MASK; 35702d756322SRob Clark } 35712d756322SRob Clark 35722d756322SRob Clark #define REG_A6XX_RB_BLIT_SCISSOR_BR 0x000088d2 3573c28c82e9SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_X__MASK 0x00003fff 35742d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT 0 35752d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val) 35762d756322SRob Clark { 35772d756322SRob Clark return ((val) << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK; 35782d756322SRob Clark } 3579c28c82e9SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK 0x3fff0000 35802d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT 16 35812d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val) 35822d756322SRob Clark { 35832d756322SRob Clark return ((val) << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK; 35842d756322SRob Clark } 35852d756322SRob Clark 3586c28c82e9SRob Clark #define REG_A6XX_RB_BIN_CONTROL2 0x000088d3 3587c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL2_BINW__MASK 0x0000003f 3588c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL2_BINW__SHIFT 0 3589c28c82e9SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val) 3590c28c82e9SRob Clark { 3591c28c82e9SRob Clark return ((val >> 5) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK; 3592c28c82e9SRob Clark } 3593c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL2_BINH__MASK 0x00007f00 3594c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL2_BINH__SHIFT 8 3595c28c82e9SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val) 3596c28c82e9SRob Clark { 3597c28c82e9SRob Clark return ((val >> 4) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK; 3598c28c82e9SRob Clark } 3599c28c82e9SRob Clark 3600c28c82e9SRob Clark #define REG_A6XX_RB_WINDOW_OFFSET2 0x000088d4 3601c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET2_X__MASK 0x00003fff 3602c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET2_X__SHIFT 0 3603c28c82e9SRob Clark static inline uint32_t A6XX_RB_WINDOW_OFFSET2_X(uint32_t val) 3604c28c82e9SRob Clark { 3605c28c82e9SRob Clark return ((val) << A6XX_RB_WINDOW_OFFSET2_X__SHIFT) & A6XX_RB_WINDOW_OFFSET2_X__MASK; 3606c28c82e9SRob Clark } 3607c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET2_Y__MASK 0x3fff0000 3608c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET2_Y__SHIFT 16 3609c28c82e9SRob Clark static inline uint32_t A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val) 3610c28c82e9SRob Clark { 3611c28c82e9SRob Clark return ((val) << A6XX_RB_WINDOW_OFFSET2_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET2_Y__MASK; 3612c28c82e9SRob Clark } 3613c28c82e9SRob Clark 3614ccdf7e28SRob Clark #define REG_A6XX_RB_MSAA_CNTL 0x000088d5 3615ccdf7e28SRob Clark #define A6XX_RB_MSAA_CNTL_SAMPLES__MASK 0x00000018 3616ccdf7e28SRob Clark #define A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT 3 3617ccdf7e28SRob Clark static inline uint32_t A6XX_RB_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 3618ccdf7e28SRob Clark { 3619ccdf7e28SRob Clark return ((val) << A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_MSAA_CNTL_SAMPLES__MASK; 3620ccdf7e28SRob Clark } 3621ccdf7e28SRob Clark 36222d756322SRob Clark #define REG_A6XX_RB_BLIT_BASE_GMEM 0x000088d6 3623c28c82e9SRob Clark #define A6XX_RB_BLIT_BASE_GMEM__MASK 0xfffff000 3624c28c82e9SRob Clark #define A6XX_RB_BLIT_BASE_GMEM__SHIFT 12 3625c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_BASE_GMEM(uint32_t val) 3626c28c82e9SRob Clark { 3627c28c82e9SRob Clark return ((val >> 12) << A6XX_RB_BLIT_BASE_GMEM__SHIFT) & A6XX_RB_BLIT_BASE_GMEM__MASK; 3628c28c82e9SRob Clark } 36292d756322SRob Clark 36302d756322SRob Clark #define REG_A6XX_RB_BLIT_DST_INFO 0x000088d7 36312d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK 0x00000003 36322d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT 0 36332d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) 36342d756322SRob Clark { 36352d756322SRob Clark return ((val) << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK; 36362d756322SRob Clark } 36372d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_FLAGS 0x00000004 3638ccdf7e28SRob Clark #define A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK 0x00000018 3639ccdf7e28SRob Clark #define A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT 3 3640ccdf7e28SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) 3641ccdf7e28SRob Clark { 3642ccdf7e28SRob Clark return ((val) << A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK; 3643ccdf7e28SRob Clark } 36442d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK 0x00000060 36452d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT 5 36462d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) 36472d756322SRob Clark { 36482d756322SRob Clark return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK; 36492d756322SRob Clark } 3650c28c82e9SRob Clark #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK 0x00007f80 3651c28c82e9SRob Clark #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT 7 3652c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_format val) 3653c28c82e9SRob Clark { 3654c28c82e9SRob Clark return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK; 3655c28c82e9SRob Clark } 3656c28c82e9SRob Clark #define A6XX_RB_BLIT_DST_INFO_UNK15 0x00008000 3657c28c82e9SRob Clark 3658c28c82e9SRob Clark #define REG_A6XX_RB_BLIT_DST 0x000088d8 3659c28c82e9SRob Clark #define A6XX_RB_BLIT_DST__MASK 0xffffffff 3660c28c82e9SRob Clark #define A6XX_RB_BLIT_DST__SHIFT 0 3661c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_DST(uint32_t val) 3662c28c82e9SRob Clark { 3663c28c82e9SRob Clark return ((val) << A6XX_RB_BLIT_DST__SHIFT) & A6XX_RB_BLIT_DST__MASK; 3664c28c82e9SRob Clark } 36652d756322SRob Clark 36662d756322SRob Clark #define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da 3667c28c82e9SRob Clark #define A6XX_RB_BLIT_DST_PITCH__MASK 0x0000ffff 36682d756322SRob Clark #define A6XX_RB_BLIT_DST_PITCH__SHIFT 0 36692d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val) 36702d756322SRob Clark { 36712d756322SRob Clark return ((val >> 6) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK; 36722d756322SRob Clark } 36732d756322SRob Clark 36742d756322SRob Clark #define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH 0x000088db 3675c28c82e9SRob Clark #define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0x1fffffff 36762d756322SRob Clark #define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0 36772d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) 36782d756322SRob Clark { 36792d756322SRob Clark return ((val >> 6) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK; 36802d756322SRob Clark } 36812d756322SRob Clark 3682c28c82e9SRob Clark #define REG_A6XX_RB_BLIT_FLAG_DST 0x000088dc 3683c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST__MASK 0xffffffff 3684c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST__SHIFT 0 3685c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_FLAG_DST(uint32_t val) 3686c28c82e9SRob Clark { 3687c28c82e9SRob Clark return ((val) << A6XX_RB_BLIT_FLAG_DST__SHIFT) & A6XX_RB_BLIT_FLAG_DST__MASK; 3688c28c82e9SRob Clark } 3689c28c82e9SRob Clark 3690c28c82e9SRob Clark #define REG_A6XX_RB_BLIT_FLAG_DST_PITCH 0x000088de 3691c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK 0x000007ff 3692c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT 0 3693c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val) 3694c28c82e9SRob Clark { 3695c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK; 3696c28c82e9SRob Clark } 3697c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK 0x0ffff800 3698c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT 11 3699c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val) 3700c28c82e9SRob Clark { 3701c28c82e9SRob Clark return ((val >> 7) << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK; 3702c28c82e9SRob Clark } 3703c28c82e9SRob Clark 37042d756322SRob Clark #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 0x000088df 37052d756322SRob Clark 37062d756322SRob Clark #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1 0x000088e0 37072d756322SRob Clark 37082d756322SRob Clark #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2 0x000088e1 37092d756322SRob Clark 37102d756322SRob Clark #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3 0x000088e2 37112d756322SRob Clark 37122d756322SRob Clark #define REG_A6XX_RB_BLIT_INFO 0x000088e3 37132d756322SRob Clark #define A6XX_RB_BLIT_INFO_UNK0 0x00000001 3714a69c5ed2SRob Clark #define A6XX_RB_BLIT_INFO_GMEM 0x00000002 3715*cc4c26d4SRob Clark #define A6XX_RB_BLIT_INFO_SAMPLE_0 0x00000004 3716a69c5ed2SRob Clark #define A6XX_RB_BLIT_INFO_DEPTH 0x00000008 3717a69c5ed2SRob Clark #define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK 0x000000f0 3718a69c5ed2SRob Clark #define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT 4 3719a69c5ed2SRob Clark static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val) 37202d756322SRob Clark { 3721a69c5ed2SRob Clark return ((val) << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK; 37222d756322SRob Clark } 3723c28c82e9SRob Clark #define A6XX_RB_BLIT_INFO_UNK8__MASK 0x00000300 3724c28c82e9SRob Clark #define A6XX_RB_BLIT_INFO_UNK8__SHIFT 8 3725c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_INFO_UNK8(uint32_t val) 3726c28c82e9SRob Clark { 3727c28c82e9SRob Clark return ((val) << A6XX_RB_BLIT_INFO_UNK8__SHIFT) & A6XX_RB_BLIT_INFO_UNK8__MASK; 3728c28c82e9SRob Clark } 3729c28c82e9SRob Clark #define A6XX_RB_BLIT_INFO_UNK12__MASK 0x0000f000 3730c28c82e9SRob Clark #define A6XX_RB_BLIT_INFO_UNK12__SHIFT 12 3731c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_INFO_UNK12(uint32_t val) 3732c28c82e9SRob Clark { 3733c28c82e9SRob Clark return ((val) << A6XX_RB_BLIT_INFO_UNK12__SHIFT) & A6XX_RB_BLIT_INFO_UNK12__MASK; 3734c28c82e9SRob Clark } 37352d756322SRob Clark 37362d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_88F0 0x000088f0 37372d756322SRob Clark 3738c28c82e9SRob Clark #define REG_A6XX_RB_UNK_FLAG_BUFFER_BASE 0x000088f1 3739c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK 0xffffffff 3740c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT 0 3741c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_BASE(uint32_t val) 3742c28c82e9SRob Clark { 3743c28c82e9SRob Clark return ((val) << A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK; 3744c28c82e9SRob Clark } 3745c28c82e9SRob Clark 3746c28c82e9SRob Clark #define REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH 0x000088f3 3747c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff 3748c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 3749c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(uint32_t val) 3750c28c82e9SRob Clark { 3751c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK; 3752c28c82e9SRob Clark } 3753c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x00fff800 3754c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 3755c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 3756c28c82e9SRob Clark { 3757c28c82e9SRob Clark return ((val >> 7) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; 3758c28c82e9SRob Clark } 3759c28c82e9SRob Clark 3760c28c82e9SRob Clark #define REG_A6XX_RB_UNKNOWN_88F4 0x000088f4 3761c28c82e9SRob Clark 3762c28c82e9SRob Clark #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE 0x00008900 3763c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK 0xffffffff 3764c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT 0 3765c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_BASE(uint32_t val) 3766c28c82e9SRob Clark { 3767c28c82e9SRob Clark return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK; 3768c28c82e9SRob Clark } 3769c28c82e9SRob Clark 37702d756322SRob Clark #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x00008902 3771c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK 0x0000007f 3772c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 3773c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val) 3774c28c82e9SRob Clark { 3775c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK; 3776c28c82e9SRob Clark } 3777c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK 0x00000700 3778c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT 8 3779c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8(uint32_t val) 3780c28c82e9SRob Clark { 3781c28c82e9SRob Clark return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK; 3782c28c82e9SRob Clark } 3783c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x0ffff800 3784c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 3785c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 3786c28c82e9SRob Clark { 3787c28c82e9SRob Clark return ((val >> 7) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; 3788c28c82e9SRob Clark } 37892d756322SRob Clark 37902d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; } 37912d756322SRob Clark 3792c28c82e9SRob Clark static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; } 3793c28c82e9SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK 0xffffffff 3794c28c82e9SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT 0 3795c28c82e9SRob Clark static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t val) 3796c28c82e9SRob Clark { 3797c28c82e9SRob Clark return ((val) << A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK; 3798c28c82e9SRob Clark } 3799c28c82e9SRob Clark 38002d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; } 38012d756322SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff 38022d756322SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 38032d756322SRob Clark static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val) 38042d756322SRob Clark { 3805c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK; 38062d756322SRob Clark } 3807c28c82e9SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffff800 38082d756322SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 38092d756322SRob Clark static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 38102d756322SRob Clark { 3811c28c82e9SRob Clark return ((val >> 7) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; 38122d756322SRob Clark } 38132d756322SRob Clark 3814c28c82e9SRob Clark #define REG_A6XX_RB_SAMPLE_COUNT_ADDR 0x00008927 3815c28c82e9SRob Clark #define A6XX_RB_SAMPLE_COUNT_ADDR__MASK 0xffffffff 3816c28c82e9SRob Clark #define A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT 0 3817c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_COUNT_ADDR(uint32_t val) 3818c28c82e9SRob Clark { 3819c28c82e9SRob Clark return ((val) << A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT) & A6XX_RB_SAMPLE_COUNT_ADDR__MASK; 3820c28c82e9SRob Clark } 3821c28c82e9SRob Clark 38222d756322SRob Clark #define REG_A6XX_RB_2D_BLIT_CNTL 0x00008c00 3823c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK 0x00000007 3824c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT 0 3825c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val) 3826c28c82e9SRob Clark { 3827c28c82e9SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK; 3828c28c82e9SRob Clark } 3829c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_UNK3__MASK 0x00000078 3830c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_UNK3__SHIFT 3 3831c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK3(uint32_t val) 3832c28c82e9SRob Clark { 3833c28c82e9SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK3__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK3__MASK; 3834c28c82e9SRob Clark } 3835c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR 0x00000080 38362d756322SRob Clark #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00 38372d756322SRob Clark #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8 3838c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val) 38392d756322SRob Clark { 38402d756322SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK; 38412d756322SRob Clark } 3842ccdf7e28SRob Clark #define A6XX_RB_2D_BLIT_CNTL_SCISSOR 0x00010000 3843c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_UNK17__MASK 0x00060000 3844c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT 17 3845c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK17(uint32_t val) 3846c28c82e9SRob Clark { 3847c28c82e9SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK17__MASK; 3848c28c82e9SRob Clark } 3849c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_D24S8 0x00080000 3850c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_MASK__MASK 0x00f00000 3851c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT 20 3852c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_MASK(uint32_t val) 3853c28c82e9SRob Clark { 3854c28c82e9SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_RB_2D_BLIT_CNTL_MASK__MASK; 3855c28c82e9SRob Clark } 3856c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_IFMT__MASK 0x1f000000 3857c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT 24 3858c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val) 3859c28c82e9SRob Clark { 3860c28c82e9SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_IFMT__MASK; 3861c28c82e9SRob Clark } 3862c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_UNK29__MASK 0x20000000 3863c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_UNK29__SHIFT 29 3864c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK29(uint32_t val) 3865c28c82e9SRob Clark { 3866c28c82e9SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK29__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK29__MASK; 3867c28c82e9SRob Clark } 3868ccdf7e28SRob Clark 3869c28c82e9SRob Clark #define REG_A6XX_RB_2D_UNKNOWN_8C01 0x00008c01 38702d756322SRob Clark 38712d756322SRob Clark #define REG_A6XX_RB_2D_DST_INFO 0x00008c17 38722d756322SRob Clark #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff 38732d756322SRob Clark #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0 3874c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_format val) 38752d756322SRob Clark { 38762d756322SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK; 38772d756322SRob Clark } 38782d756322SRob Clark #define A6XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300 38792d756322SRob Clark #define A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8 38802d756322SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) 38812d756322SRob Clark { 38822d756322SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_2D_DST_INFO_TILE_MODE__MASK; 38832d756322SRob Clark } 38842d756322SRob Clark #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00 38852d756322SRob Clark #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10 38862d756322SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) 38872d756322SRob Clark { 38882d756322SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK; 38892d756322SRob Clark } 38902d756322SRob Clark #define A6XX_RB_2D_DST_INFO_FLAGS 0x00001000 3891c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_SRGB 0x00002000 3892c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_SAMPLES__MASK 0x0000c000 3893c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT 14 3894c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) 3895c28c82e9SRob Clark { 3896c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_2D_DST_INFO_SAMPLES__MASK; 3897c28c82e9SRob Clark } 3898c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_FILTER 0x00010000 3899*cc4c26d4SRob Clark #define A6XX_RB_2D_DST_INFO_UNK17 0x00020000 3900c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE 0x00040000 3901*cc4c26d4SRob Clark #define A6XX_RB_2D_DST_INFO_UNK19 0x00080000 3902c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_UNK20 0x00100000 3903*cc4c26d4SRob Clark #define A6XX_RB_2D_DST_INFO_UNK21 0x00200000 3904c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_UNK22 0x00400000 3905*cc4c26d4SRob Clark #define A6XX_RB_2D_DST_INFO_UNK23__MASK 0x07800000 3906*cc4c26d4SRob Clark #define A6XX_RB_2D_DST_INFO_UNK23__SHIFT 23 3907*cc4c26d4SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_UNK23(uint32_t val) 3908*cc4c26d4SRob Clark { 3909*cc4c26d4SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_UNK23__SHIFT) & A6XX_RB_2D_DST_INFO_UNK23__MASK; 3910*cc4c26d4SRob Clark } 3911*cc4c26d4SRob Clark #define A6XX_RB_2D_DST_INFO_UNK28 0x10000000 39122d756322SRob Clark 3913c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST 0x00008c18 3914c28c82e9SRob Clark #define A6XX_RB_2D_DST__MASK 0xffffffff 3915c28c82e9SRob Clark #define A6XX_RB_2D_DST__SHIFT 0 3916c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST(uint32_t val) 39172d756322SRob Clark { 3918c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST__SHIFT) & A6XX_RB_2D_DST__MASK; 3919c28c82e9SRob Clark } 3920c28c82e9SRob Clark 3921c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_PITCH 0x00008c1a 3922c28c82e9SRob Clark #define A6XX_RB_2D_DST_PITCH__MASK 0x0000ffff 3923c28c82e9SRob Clark #define A6XX_RB_2D_DST_PITCH__SHIFT 0 3924c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_PITCH(uint32_t val) 3925c28c82e9SRob Clark { 3926c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_2D_DST_PITCH__SHIFT) & A6XX_RB_2D_DST_PITCH__MASK; 3927c28c82e9SRob Clark } 3928c28c82e9SRob Clark 3929c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_PLANE1 0x00008c1b 3930c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE1__MASK 0xffffffff 3931c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE1__SHIFT 0 3932c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_PLANE1(uint32_t val) 3933c28c82e9SRob Clark { 3934c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST_PLANE1__SHIFT) & A6XX_RB_2D_DST_PLANE1__MASK; 3935c28c82e9SRob Clark } 3936c28c82e9SRob Clark 3937c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_PLANE_PITCH 0x00008c1d 3938c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE_PITCH__MASK 0x0000ffff 3939c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE_PITCH__SHIFT 0 3940c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_PLANE_PITCH(uint32_t val) 3941c28c82e9SRob Clark { 3942c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_2D_DST_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_PLANE_PITCH__MASK; 3943c28c82e9SRob Clark } 3944c28c82e9SRob Clark 3945c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_PLANE2 0x00008c1e 3946c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE2__MASK 0xffffffff 3947c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE2__SHIFT 0 3948c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_PLANE2(uint32_t val) 3949c28c82e9SRob Clark { 3950c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST_PLANE2__SHIFT) & A6XX_RB_2D_DST_PLANE2__MASK; 39512d756322SRob Clark } 39522d756322SRob Clark 3953c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_FLAGS 0x00008c20 3954c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS__MASK 0xffffffff 3955c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS__SHIFT 0 3956c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_FLAGS(uint32_t val) 3957c28c82e9SRob Clark { 3958c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST_FLAGS__SHIFT) & A6XX_RB_2D_DST_FLAGS__MASK; 3959c28c82e9SRob Clark } 3960c28c82e9SRob Clark 3961c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_FLAGS_PITCH 0x00008c22 3962c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PITCH__MASK 0x000000ff 3963c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT 0 3964c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_FLAGS_PITCH(uint32_t val) 3965c28c82e9SRob Clark { 3966c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH__MASK; 3967c28c82e9SRob Clark } 3968c28c82e9SRob Clark 3969c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_FLAGS_PLANE 0x00008c23 3970c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PLANE__MASK 0xffffffff 3971c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT 0 3972c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE(uint32_t val) 3973c28c82e9SRob Clark { 3974c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE__MASK; 3975c28c82e9SRob Clark } 3976c28c82e9SRob Clark 3977c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH 0x00008c25 3978c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK 0x000000ff 3979c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT 0 3980c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(uint32_t val) 3981c28c82e9SRob Clark { 3982c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK; 3983c28c82e9SRob Clark } 3984c28c82e9SRob Clark 39852d756322SRob Clark #define REG_A6XX_RB_2D_SRC_SOLID_C0 0x00008c2c 39862d756322SRob Clark 39872d756322SRob Clark #define REG_A6XX_RB_2D_SRC_SOLID_C1 0x00008c2d 39882d756322SRob Clark 39892d756322SRob Clark #define REG_A6XX_RB_2D_SRC_SOLID_C2 0x00008c2e 39902d756322SRob Clark 39912d756322SRob Clark #define REG_A6XX_RB_2D_SRC_SOLID_C3 0x00008c2f 39922d756322SRob Clark 39932d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8E01 0x00008e01 39942d756322SRob Clark 3995a69c5ed2SRob Clark #define REG_A6XX_RB_UNKNOWN_8E04 0x00008e04 3996a69c5ed2SRob Clark 3997c28c82e9SRob Clark #define REG_A6XX_RB_ADDR_MODE_CNTL 0x00008e05 3998c28c82e9SRob Clark 39992d756322SRob Clark #define REG_A6XX_RB_CCU_CNTL 0x00008e07 4000c28c82e9SRob Clark #define A6XX_RB_CCU_CNTL_OFFSET__MASK 0xff800000 4001c28c82e9SRob Clark #define A6XX_RB_CCU_CNTL_OFFSET__SHIFT 23 4002c28c82e9SRob Clark static inline uint32_t A6XX_RB_CCU_CNTL_OFFSET(uint32_t val) 4003c28c82e9SRob Clark { 4004c28c82e9SRob Clark return ((val >> 12) << A6XX_RB_CCU_CNTL_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_OFFSET__MASK; 4005c28c82e9SRob Clark } 4006c28c82e9SRob Clark #define A6XX_RB_CCU_CNTL_GMEM 0x00400000 4007c28c82e9SRob Clark #define A6XX_RB_CCU_CNTL_UNK2 0x00000004 40082d756322SRob Clark 4009c28c82e9SRob Clark #define REG_A6XX_RB_NC_MODE_CNTL 0x00008e08 4010c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_MODE 0x00000001 4011c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006 4012c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT 1 4013c28c82e9SRob Clark static inline uint32_t A6XX_RB_NC_MODE_CNTL_LOWER_BIT(uint32_t val) 4014c28c82e9SRob Clark { 4015c28c82e9SRob Clark return ((val) << A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK; 4016c28c82e9SRob Clark } 4017c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008 4018c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_AMSBC 0x00000010 4019c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000400 4020c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT 10 4021c28c82e9SRob Clark static inline uint32_t A6XX_RB_NC_MODE_CNTL_UPPER_BIT(uint32_t val) 4022c28c82e9SRob Clark { 4023c28c82e9SRob Clark return ((val) << A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK; 4024c28c82e9SRob Clark } 4025c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR 0x00000800 4026c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_UNK12__MASK 0x00003000 4027c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT 12 4028c28c82e9SRob Clark static inline uint32_t A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val) 4029c28c82e9SRob Clark { 4030c28c82e9SRob Clark return ((val) << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK; 4031c28c82e9SRob Clark } 40322d756322SRob Clark 4033*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RB_PERFCTR_RB_SEL(uint32_t i0) { return 0x00008e10 + 0x1*i0; } 4034c28c82e9SRob Clark 4035*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RB_PERFCTR_CCU_SEL(uint32_t i0) { return 0x00008e18 + 0x1*i0; } 4036c28c82e9SRob Clark 4037c28c82e9SRob Clark #define REG_A6XX_RB_UNKNOWN_8E28 0x00008e28 4038c28c82e9SRob Clark 4039*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RB_PERFCTR_CMP_SEL(uint32_t i0) { return 0x00008e2c + 0x1*i0; } 4040c28c82e9SRob Clark 4041c28c82e9SRob Clark #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST 0x00008e3b 4042c28c82e9SRob Clark 4043c28c82e9SRob Clark #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD 0x00008e3d 4044c28c82e9SRob Clark 4045c28c82e9SRob Clark #define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x00008e50 4046c28c82e9SRob Clark 4047c28c82e9SRob Clark #define REG_A6XX_RB_UNKNOWN_8E51 0x00008e51 4048c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_8E51__MASK 0xffffffff 4049c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_8E51__SHIFT 0 4050c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNKNOWN_8E51(uint32_t val) 4051c28c82e9SRob Clark { 4052c28c82e9SRob Clark return ((val) << A6XX_RB_UNKNOWN_8E51__SHIFT) & A6XX_RB_UNKNOWN_8E51__MASK; 4053c28c82e9SRob Clark } 4054c28c82e9SRob Clark 4055c28c82e9SRob Clark #define REG_A6XX_VPC_UNKNOWN_9100 0x00009100 4056c28c82e9SRob Clark 4057c28c82e9SRob Clark #define REG_A6XX_VPC_VS_CLIP_CNTL 0x00009101 4058c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff 4059c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT 0 4060c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(uint32_t val) 4061c28c82e9SRob Clark { 4062c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK; 4063c28c82e9SRob Clark } 4064c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00 4065c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8 4066c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) 4067c28c82e9SRob Clark { 4068c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK; 4069c28c82e9SRob Clark } 4070c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000 4071c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16 4072c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) 4073c28c82e9SRob Clark { 4074c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; 4075c28c82e9SRob Clark } 4076c28c82e9SRob Clark 4077c28c82e9SRob Clark #define REG_A6XX_VPC_GS_CLIP_CNTL 0x00009102 4078c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff 4079c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT 0 4080c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK(uint32_t val) 4081c28c82e9SRob Clark { 4082c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK; 4083c28c82e9SRob Clark } 4084c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00 4085c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8 4086c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) 4087c28c82e9SRob Clark { 4088c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK; 4089c28c82e9SRob Clark } 4090c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000 4091c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16 4092c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) 4093c28c82e9SRob Clark { 4094c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; 4095c28c82e9SRob Clark } 4096c28c82e9SRob Clark 4097c28c82e9SRob Clark #define REG_A6XX_VPC_DS_CLIP_CNTL 0x00009103 4098c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff 4099c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT 0 4100c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK(uint32_t val) 4101c28c82e9SRob Clark { 4102c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK; 4103c28c82e9SRob Clark } 4104c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00 4105c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8 4106c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) 4107c28c82e9SRob Clark { 4108c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK; 4109c28c82e9SRob Clark } 4110c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000 4111c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16 4112c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) 4113c28c82e9SRob Clark { 4114c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; 4115c28c82e9SRob Clark } 4116c28c82e9SRob Clark 4117c28c82e9SRob Clark #define REG_A6XX_VPC_VS_LAYER_CNTL 0x00009104 4118c28c82e9SRob Clark #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff 4119c28c82e9SRob Clark #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT 0 4120c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(uint32_t val) 4121c28c82e9SRob Clark { 4122c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK; 4123c28c82e9SRob Clark } 4124c28c82e9SRob Clark #define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00 4125c28c82e9SRob Clark #define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT 8 4126c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(uint32_t val) 4127c28c82e9SRob Clark { 4128c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK; 4129c28c82e9SRob Clark } 4130c28c82e9SRob Clark 4131c28c82e9SRob Clark #define REG_A6XX_VPC_GS_LAYER_CNTL 0x00009105 4132c28c82e9SRob Clark #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff 4133c28c82e9SRob Clark #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT 0 4134c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(uint32_t val) 4135c28c82e9SRob Clark { 4136c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK; 4137c28c82e9SRob Clark } 4138c28c82e9SRob Clark #define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00 4139c28c82e9SRob Clark #define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT 8 4140c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(uint32_t val) 4141c28c82e9SRob Clark { 4142c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK; 4143c28c82e9SRob Clark } 4144c28c82e9SRob Clark 4145c28c82e9SRob Clark #define REG_A6XX_VPC_DS_LAYER_CNTL 0x00009106 4146c28c82e9SRob Clark #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff 4147c28c82e9SRob Clark #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT 0 4148c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_LAYERLOC(uint32_t val) 4149c28c82e9SRob Clark { 4150c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK; 4151c28c82e9SRob Clark } 4152c28c82e9SRob Clark #define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00 4153c28c82e9SRob Clark #define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT 8 4154c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val) 4155c28c82e9SRob Clark { 4156c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK; 4157c28c82e9SRob Clark } 41582d756322SRob Clark 4159a69c5ed2SRob Clark #define REG_A6XX_VPC_UNKNOWN_9107 0x00009107 4160*cc4c26d4SRob Clark #define A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD 0x00000001 4161*cc4c26d4SRob Clark #define A6XX_VPC_UNKNOWN_9107_UNK2 0x00000004 4162a69c5ed2SRob Clark 4163c28c82e9SRob Clark #define REG_A6XX_VPC_POLYGON_MODE 0x00009108 4164c28c82e9SRob Clark #define A6XX_VPC_POLYGON_MODE_MODE__MASK 0x00000003 4165c28c82e9SRob Clark #define A6XX_VPC_POLYGON_MODE_MODE__SHIFT 0 4166c28c82e9SRob Clark static inline uint32_t A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) 4167c28c82e9SRob Clark { 4168c28c82e9SRob Clark return ((val) << A6XX_VPC_POLYGON_MODE_MODE__SHIFT) & A6XX_VPC_POLYGON_MODE_MODE__MASK; 4169c28c82e9SRob Clark } 41702d756322SRob Clark 41712d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; } 41722d756322SRob Clark 41732d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; } 41742d756322SRob Clark 41752d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; } 41762d756322SRob Clark 41772d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; } 41782d756322SRob Clark 41792d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9210 0x00009210 41802d756322SRob Clark 41812d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9211 0x00009211 41822d756322SRob Clark 41832d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; } 41842d756322SRob Clark 41852d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; } 41862d756322SRob Clark 41872d756322SRob Clark #define REG_A6XX_VPC_SO_CNTL 0x00009216 4188*cc4c26d4SRob Clark #define A6XX_VPC_SO_CNTL_ADDR__MASK 0x000000ff 4189*cc4c26d4SRob Clark #define A6XX_VPC_SO_CNTL_ADDR__SHIFT 0 4190*cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_SO_CNTL_ADDR(uint32_t val) 4191c28c82e9SRob Clark { 4192*cc4c26d4SRob Clark return ((val) << A6XX_VPC_SO_CNTL_ADDR__SHIFT) & A6XX_VPC_SO_CNTL_ADDR__MASK; 4193c28c82e9SRob Clark } 4194*cc4c26d4SRob Clark #define A6XX_VPC_SO_CNTL_RESET 0x00010000 41952d756322SRob Clark 41962d756322SRob Clark #define REG_A6XX_VPC_SO_PROG 0x00009217 41972d756322SRob Clark #define A6XX_VPC_SO_PROG_A_BUF__MASK 0x00000003 41982d756322SRob Clark #define A6XX_VPC_SO_PROG_A_BUF__SHIFT 0 41992d756322SRob Clark static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val) 42002d756322SRob Clark { 42012d756322SRob Clark return ((val) << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK; 42022d756322SRob Clark } 42032d756322SRob Clark #define A6XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc 42042d756322SRob Clark #define A6XX_VPC_SO_PROG_A_OFF__SHIFT 2 42052d756322SRob Clark static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val) 42062d756322SRob Clark { 42072d756322SRob Clark return ((val >> 2) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK; 42082d756322SRob Clark } 42092d756322SRob Clark #define A6XX_VPC_SO_PROG_A_EN 0x00000800 42102d756322SRob Clark #define A6XX_VPC_SO_PROG_B_BUF__MASK 0x00003000 42112d756322SRob Clark #define A6XX_VPC_SO_PROG_B_BUF__SHIFT 12 42122d756322SRob Clark static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val) 42132d756322SRob Clark { 42142d756322SRob Clark return ((val) << A6XX_VPC_SO_PROG_B_BUF__SHIFT) & A6XX_VPC_SO_PROG_B_BUF__MASK; 42152d756322SRob Clark } 42162d756322SRob Clark #define A6XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000 42172d756322SRob Clark #define A6XX_VPC_SO_PROG_B_OFF__SHIFT 14 42182d756322SRob Clark static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val) 42192d756322SRob Clark { 42202d756322SRob Clark return ((val >> 2) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK; 42212d756322SRob Clark } 42222d756322SRob Clark #define A6XX_VPC_SO_PROG_B_EN 0x00800000 42232d756322SRob Clark 4224c28c82e9SRob Clark #define REG_A6XX_VPC_SO_STREAM_COUNTS 0x00009218 4225c28c82e9SRob Clark #define A6XX_VPC_SO_STREAM_COUNTS__MASK 0xffffffff 4226c28c82e9SRob Clark #define A6XX_VPC_SO_STREAM_COUNTS__SHIFT 0 4227c28c82e9SRob Clark static inline uint32_t A6XX_VPC_SO_STREAM_COUNTS(uint32_t val) 4228c28c82e9SRob Clark { 4229c28c82e9SRob Clark return ((val) << A6XX_VPC_SO_STREAM_COUNTS__SHIFT) & A6XX_VPC_SO_STREAM_COUNTS__MASK; 4230c28c82e9SRob Clark } 4231c28c82e9SRob Clark 42322d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; } 42332d756322SRob Clark 4234c28c82e9SRob Clark static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0) { return 0x0000921a + 0x7*i0; } 4235c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_BASE__MASK 0xffffffff 4236c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_BASE__SHIFT 0 4237c28c82e9SRob Clark static inline uint32_t A6XX_VPC_SO_BUFFER_BASE(uint32_t val) 4238c28c82e9SRob Clark { 4239c28c82e9SRob Clark return ((val) << A6XX_VPC_SO_BUFFER_BASE__SHIFT) & A6XX_VPC_SO_BUFFER_BASE__MASK; 4240c28c82e9SRob Clark } 4241c28c82e9SRob Clark 42422d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; } 4243c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_SIZE__MASK 0xfffffffc 4244c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_SIZE__SHIFT 2 4245c28c82e9SRob Clark static inline uint32_t A6XX_VPC_SO_BUFFER_SIZE(uint32_t val) 4246c28c82e9SRob Clark { 4247c28c82e9SRob Clark return ((val >> 2) << A6XX_VPC_SO_BUFFER_SIZE__SHIFT) & A6XX_VPC_SO_BUFFER_SIZE__MASK; 4248c28c82e9SRob Clark } 42492d756322SRob Clark 42502d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000921d + 0x7*i0; } 42512d756322SRob Clark 42522d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; } 4253c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_OFFSET__MASK 0xfffffffc 4254c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_OFFSET__SHIFT 2 4255c28c82e9SRob Clark static inline uint32_t A6XX_VPC_SO_BUFFER_OFFSET(uint32_t val) 4256c28c82e9SRob Clark { 4257c28c82e9SRob Clark return ((val >> 2) << A6XX_VPC_SO_BUFFER_OFFSET__SHIFT) & A6XX_VPC_SO_BUFFER_OFFSET__MASK; 4258c28c82e9SRob Clark } 4259c28c82e9SRob Clark 4260c28c82e9SRob Clark static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0) { return 0x0000921f + 0x7*i0; } 4261c28c82e9SRob Clark #define A6XX_VPC_SO_FLUSH_BASE__MASK 0xffffffff 4262c28c82e9SRob Clark #define A6XX_VPC_SO_FLUSH_BASE__SHIFT 0 4263c28c82e9SRob Clark static inline uint32_t A6XX_VPC_SO_FLUSH_BASE(uint32_t val) 4264c28c82e9SRob Clark { 4265c28c82e9SRob Clark return ((val) << A6XX_VPC_SO_FLUSH_BASE__SHIFT) & A6XX_VPC_SO_FLUSH_BASE__MASK; 4266c28c82e9SRob Clark } 42672d756322SRob Clark 4268c28c82e9SRob Clark #define REG_A6XX_VPC_POINT_COORD_INVERT 0x00009236 4269c28c82e9SRob Clark #define A6XX_VPC_POINT_COORD_INVERT_INVERT 0x00000001 42702d756322SRob Clark 42712d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9300 0x00009300 42722d756322SRob Clark 4273c28c82e9SRob Clark #define REG_A6XX_VPC_VS_PACK 0x00009301 4274c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK 0x000000ff 4275c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT 0 4276c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_PACK_STRIDE_IN_VPC(uint32_t val) 42772d756322SRob Clark { 4278c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK; 42792d756322SRob Clark } 4280c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_POSITIONLOC__MASK 0x0000ff00 4281c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT 8 4282c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_PACK_POSITIONLOC(uint32_t val) 42832d756322SRob Clark { 4284c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_VS_PACK_POSITIONLOC__MASK; 42852d756322SRob Clark } 4286c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_PSIZELOC__MASK 0x00ff0000 4287c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_PSIZELOC__SHIFT 16 4288c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_PACK_PSIZELOC(uint32_t val) 42892d756322SRob Clark { 4290c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_VS_PACK_PSIZELOC__MASK; 4291c28c82e9SRob Clark } 4292*cc4c26d4SRob Clark #define A6XX_VPC_VS_PACK_EXTRAPOS__MASK 0x0f000000 4293*cc4c26d4SRob Clark #define A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT 24 4294*cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_VS_PACK_EXTRAPOS(uint32_t val) 4295c28c82e9SRob Clark { 4296*cc4c26d4SRob Clark return ((val) << A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_VS_PACK_EXTRAPOS__MASK; 4297c28c82e9SRob Clark } 4298c28c82e9SRob Clark 4299c28c82e9SRob Clark #define REG_A6XX_VPC_GS_PACK 0x00009302 4300c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK 0x000000ff 4301c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT 0 4302c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_PACK_STRIDE_IN_VPC(uint32_t val) 4303c28c82e9SRob Clark { 4304c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK; 4305c28c82e9SRob Clark } 4306c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_POSITIONLOC__MASK 0x0000ff00 4307c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT 8 4308c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_PACK_POSITIONLOC(uint32_t val) 4309c28c82e9SRob Clark { 4310c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_GS_PACK_POSITIONLOC__MASK; 4311c28c82e9SRob Clark } 4312c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_PSIZELOC__MASK 0x00ff0000 4313c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_PSIZELOC__SHIFT 16 4314c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_PACK_PSIZELOC(uint32_t val) 4315c28c82e9SRob Clark { 4316c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_GS_PACK_PSIZELOC__MASK; 4317c28c82e9SRob Clark } 4318*cc4c26d4SRob Clark #define A6XX_VPC_GS_PACK_EXTRAPOS__MASK 0x0f000000 4319*cc4c26d4SRob Clark #define A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT 24 4320*cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_GS_PACK_EXTRAPOS(uint32_t val) 4321c28c82e9SRob Clark { 4322*cc4c26d4SRob Clark return ((val) << A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_GS_PACK_EXTRAPOS__MASK; 4323c28c82e9SRob Clark } 4324c28c82e9SRob Clark 4325c28c82e9SRob Clark #define REG_A6XX_VPC_DS_PACK 0x00009303 4326c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK 0x000000ff 4327c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT 0 4328c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_PACK_STRIDE_IN_VPC(uint32_t val) 4329c28c82e9SRob Clark { 4330c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK; 4331c28c82e9SRob Clark } 4332c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_POSITIONLOC__MASK 0x0000ff00 4333c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT 8 4334c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_PACK_POSITIONLOC(uint32_t val) 4335c28c82e9SRob Clark { 4336c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_DS_PACK_POSITIONLOC__MASK; 4337c28c82e9SRob Clark } 4338c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_PSIZELOC__MASK 0x00ff0000 4339c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_PSIZELOC__SHIFT 16 4340c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_PACK_PSIZELOC(uint32_t val) 4341c28c82e9SRob Clark { 4342c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_DS_PACK_PSIZELOC__MASK; 4343c28c82e9SRob Clark } 4344*cc4c26d4SRob Clark #define A6XX_VPC_DS_PACK_EXTRAPOS__MASK 0x0f000000 4345*cc4c26d4SRob Clark #define A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT 24 4346*cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_DS_PACK_EXTRAPOS(uint32_t val) 4347c28c82e9SRob Clark { 4348*cc4c26d4SRob Clark return ((val) << A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_DS_PACK_EXTRAPOS__MASK; 43492d756322SRob Clark } 43502d756322SRob Clark 43512d756322SRob Clark #define REG_A6XX_VPC_CNTL_0 0x00009304 43522d756322SRob Clark #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK 0x000000ff 43532d756322SRob Clark #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT 0 43542d756322SRob Clark static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val) 43552d756322SRob Clark { 43562d756322SRob Clark return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK; 43572d756322SRob Clark } 4358c28c82e9SRob Clark #define A6XX_VPC_CNTL_0_PRIMIDLOC__MASK 0x0000ff00 4359c28c82e9SRob Clark #define A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT 8 4360c28c82e9SRob Clark static inline uint32_t A6XX_VPC_CNTL_0_PRIMIDLOC(uint32_t val) 4361c28c82e9SRob Clark { 4362c28c82e9SRob Clark return ((val) << A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT) & A6XX_VPC_CNTL_0_PRIMIDLOC__MASK; 4363c28c82e9SRob Clark } 43642d756322SRob Clark #define A6XX_VPC_CNTL_0_VARYING 0x00010000 4365*cc4c26d4SRob Clark #define A6XX_VPC_CNTL_0_VIEWIDLOC__MASK 0xff000000 4366*cc4c26d4SRob Clark #define A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT 24 4367*cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_CNTL_0_VIEWIDLOC(uint32_t val) 4368c28c82e9SRob Clark { 4369*cc4c26d4SRob Clark return ((val) << A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT) & A6XX_VPC_CNTL_0_VIEWIDLOC__MASK; 4370c28c82e9SRob Clark } 43712d756322SRob Clark 4372*cc4c26d4SRob Clark #define REG_A6XX_VPC_SO_STREAM_CNTL 0x00009305 4373*cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK 0x00000007 4374*cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT 0 4375*cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(uint32_t val) 4376c28c82e9SRob Clark { 4377*cc4c26d4SRob Clark return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK; 4378*cc4c26d4SRob Clark } 4379*cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK 0x00000038 4380*cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT 3 4381*cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(uint32_t val) 4382*cc4c26d4SRob Clark { 4383*cc4c26d4SRob Clark return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK; 4384*cc4c26d4SRob Clark } 4385*cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK 0x000001c0 4386*cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT 6 4387*cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(uint32_t val) 4388*cc4c26d4SRob Clark { 4389*cc4c26d4SRob Clark return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK; 4390*cc4c26d4SRob Clark } 4391*cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK 0x00000e00 4392*cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT 9 4393*cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(uint32_t val) 4394*cc4c26d4SRob Clark { 4395*cc4c26d4SRob Clark return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK; 4396*cc4c26d4SRob Clark } 4397*cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK 0x00078000 4398*cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT 15 4399*cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val) 4400*cc4c26d4SRob Clark { 4401*cc4c26d4SRob Clark return ((val) << A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK; 4402c28c82e9SRob Clark } 44032d756322SRob Clark 4404c28c82e9SRob Clark #define REG_A6XX_VPC_SO_DISABLE 0x00009306 4405c28c82e9SRob Clark #define A6XX_VPC_SO_DISABLE_DISABLE 0x00000001 4406a69c5ed2SRob Clark 44072d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9600 0x00009600 44082d756322SRob Clark 4409c28c82e9SRob Clark #define REG_A6XX_VPC_ADDR_MODE_CNTL 0x00009601 4410c28c82e9SRob Clark 44112d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9602 0x00009602 44122d756322SRob Clark 4413c28c82e9SRob Clark #define REG_A6XX_VPC_UNKNOWN_9603 0x00009603 4414c28c82e9SRob Clark 4415*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) { return 0x00009604 + 0x1*i0; } 4416c28c82e9SRob Clark 4417c28c82e9SRob Clark #define REG_A6XX_PC_TESS_NUM_VERTEX 0x00009800 4418c28c82e9SRob Clark 4419*cc4c26d4SRob Clark #define REG_A6XX_PC_HS_INPUT_SIZE 0x00009801 4420*cc4c26d4SRob Clark #define A6XX_PC_HS_INPUT_SIZE_SIZE__MASK 0x000007ff 4421*cc4c26d4SRob Clark #define A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT 0 4422*cc4c26d4SRob Clark static inline uint32_t A6XX_PC_HS_INPUT_SIZE_SIZE(uint32_t val) 4423c28c82e9SRob Clark { 4424*cc4c26d4SRob Clark return ((val) << A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT) & A6XX_PC_HS_INPUT_SIZE_SIZE__MASK; 4425c28c82e9SRob Clark } 4426*cc4c26d4SRob Clark #define A6XX_PC_HS_INPUT_SIZE_UNK13__MASK 0x00002000 4427*cc4c26d4SRob Clark #define A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT 13 4428*cc4c26d4SRob Clark static inline uint32_t A6XX_PC_HS_INPUT_SIZE_UNK13(uint32_t val) 4429c28c82e9SRob Clark { 4430*cc4c26d4SRob Clark return ((val) << A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT) & A6XX_PC_HS_INPUT_SIZE_UNK13__MASK; 4431c28c82e9SRob Clark } 4432c28c82e9SRob Clark 4433c28c82e9SRob Clark #define REG_A6XX_PC_TESS_CNTL 0x00009802 4434c28c82e9SRob Clark #define A6XX_PC_TESS_CNTL_SPACING__MASK 0x00000003 4435c28c82e9SRob Clark #define A6XX_PC_TESS_CNTL_SPACING__SHIFT 0 4436c28c82e9SRob Clark static inline uint32_t A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val) 4437c28c82e9SRob Clark { 4438c28c82e9SRob Clark return ((val) << A6XX_PC_TESS_CNTL_SPACING__SHIFT) & A6XX_PC_TESS_CNTL_SPACING__MASK; 4439c28c82e9SRob Clark } 4440c28c82e9SRob Clark #define A6XX_PC_TESS_CNTL_OUTPUT__MASK 0x0000000c 4441c28c82e9SRob Clark #define A6XX_PC_TESS_CNTL_OUTPUT__SHIFT 2 4442c28c82e9SRob Clark static inline uint32_t A6XX_PC_TESS_CNTL_OUTPUT(enum a6xx_tess_output val) 4443c28c82e9SRob Clark { 4444c28c82e9SRob Clark return ((val) << A6XX_PC_TESS_CNTL_OUTPUT__SHIFT) & A6XX_PC_TESS_CNTL_OUTPUT__MASK; 4445c28c82e9SRob Clark } 44462d756322SRob Clark 44472d756322SRob Clark #define REG_A6XX_PC_RESTART_INDEX 0x00009803 44482d756322SRob Clark 44492d756322SRob Clark #define REG_A6XX_PC_MODE_CNTL 0x00009804 44502d756322SRob Clark 44512d756322SRob Clark #define REG_A6XX_PC_UNKNOWN_9805 0x00009805 44522d756322SRob Clark 4453c28c82e9SRob Clark #define REG_A6XX_PC_PRIMID_PASSTHRU 0x00009806 4454c28c82e9SRob Clark 4455c28c82e9SRob Clark #define REG_A6XX_PC_DRAW_CMD 0x00009840 4456c28c82e9SRob Clark #define A6XX_PC_DRAW_CMD_STATE_ID__MASK 0x000000ff 4457c28c82e9SRob Clark #define A6XX_PC_DRAW_CMD_STATE_ID__SHIFT 0 4458c28c82e9SRob Clark static inline uint32_t A6XX_PC_DRAW_CMD_STATE_ID(uint32_t val) 4459c28c82e9SRob Clark { 4460c28c82e9SRob Clark return ((val) << A6XX_PC_DRAW_CMD_STATE_ID__SHIFT) & A6XX_PC_DRAW_CMD_STATE_ID__MASK; 4461c28c82e9SRob Clark } 4462c28c82e9SRob Clark 4463c28c82e9SRob Clark #define REG_A6XX_PC_DISPATCH_CMD 0x00009841 4464c28c82e9SRob Clark #define A6XX_PC_DISPATCH_CMD_STATE_ID__MASK 0x000000ff 4465c28c82e9SRob Clark #define A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT 0 4466c28c82e9SRob Clark static inline uint32_t A6XX_PC_DISPATCH_CMD_STATE_ID(uint32_t val) 4467c28c82e9SRob Clark { 4468c28c82e9SRob Clark return ((val) << A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_PC_DISPATCH_CMD_STATE_ID__MASK; 4469c28c82e9SRob Clark } 4470c28c82e9SRob Clark 4471c28c82e9SRob Clark #define REG_A6XX_PC_EVENT_CMD 0x00009842 4472c28c82e9SRob Clark #define A6XX_PC_EVENT_CMD_STATE_ID__MASK 0x00ff0000 4473c28c82e9SRob Clark #define A6XX_PC_EVENT_CMD_STATE_ID__SHIFT 16 4474c28c82e9SRob Clark static inline uint32_t A6XX_PC_EVENT_CMD_STATE_ID(uint32_t val) 4475c28c82e9SRob Clark { 4476c28c82e9SRob Clark return ((val) << A6XX_PC_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_EVENT_CMD_STATE_ID__MASK; 4477c28c82e9SRob Clark } 4478c28c82e9SRob Clark #define A6XX_PC_EVENT_CMD_EVENT__MASK 0x0000007f 4479c28c82e9SRob Clark #define A6XX_PC_EVENT_CMD_EVENT__SHIFT 0 4480c28c82e9SRob Clark static inline uint32_t A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val) 4481c28c82e9SRob Clark { 4482c28c82e9SRob Clark return ((val) << A6XX_PC_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_EVENT_CMD_EVENT__MASK; 4483c28c82e9SRob Clark } 4484c28c82e9SRob Clark 4485*cc4c26d4SRob Clark #define REG_A6XX_PC_MARKER 0x00009880 4486*cc4c26d4SRob Clark 4487c28c82e9SRob Clark #define REG_A6XX_PC_POLYGON_MODE 0x00009981 4488c28c82e9SRob Clark #define A6XX_PC_POLYGON_MODE_MODE__MASK 0x00000003 4489c28c82e9SRob Clark #define A6XX_PC_POLYGON_MODE_MODE__SHIFT 0 4490c28c82e9SRob Clark static inline uint32_t A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) 4491c28c82e9SRob Clark { 4492c28c82e9SRob Clark return ((val) << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK; 4493c28c82e9SRob Clark } 4494a69c5ed2SRob Clark 4495*cc4c26d4SRob Clark #define REG_A6XX_PC_RASTER_CNTL 0x00009980 4496*cc4c26d4SRob Clark #define A6XX_PC_RASTER_CNTL_STREAM__MASK 0x00000003 4497*cc4c26d4SRob Clark #define A6XX_PC_RASTER_CNTL_STREAM__SHIFT 0 4498*cc4c26d4SRob Clark static inline uint32_t A6XX_PC_RASTER_CNTL_STREAM(uint32_t val) 4499*cc4c26d4SRob Clark { 4500*cc4c26d4SRob Clark return ((val) << A6XX_PC_RASTER_CNTL_STREAM__SHIFT) & A6XX_PC_RASTER_CNTL_STREAM__MASK; 4501*cc4c26d4SRob Clark } 4502*cc4c26d4SRob Clark #define A6XX_PC_RASTER_CNTL_DISCARD 0x00000004 4503a69c5ed2SRob Clark 45042d756322SRob Clark #define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00 45052d756322SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001 45062d756322SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002 4507c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_0_TESS_UPPER_LEFT_DOMAIN_ORIGIN 0x00000004 4508c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_0_UNK3 0x00000008 45092d756322SRob Clark 4510c28c82e9SRob Clark #define REG_A6XX_PC_VS_OUT_CNTL 0x00009b01 4511c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff 4512c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 4513c28c82e9SRob Clark static inline uint32_t A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) 45142d756322SRob Clark { 4515c28c82e9SRob Clark return ((val) << A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK; 45162d756322SRob Clark } 4517c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_PSIZE 0x00000100 4518c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_LAYER 0x00000200 4519c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_VIEW 0x00000400 4520c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID 0x00000800 4521c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 4522c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT 16 4523c28c82e9SRob Clark static inline uint32_t A6XX_PC_VS_OUT_CNTL_CLIP_MASK(uint32_t val) 4524c28c82e9SRob Clark { 4525c28c82e9SRob Clark return ((val) << A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK; 4526c28c82e9SRob Clark } 45272d756322SRob Clark 4528c28c82e9SRob Clark #define REG_A6XX_PC_GS_OUT_CNTL 0x00009b02 4529c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff 4530c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 4531c28c82e9SRob Clark static inline uint32_t A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) 4532c28c82e9SRob Clark { 4533c28c82e9SRob Clark return ((val) << A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK; 4534c28c82e9SRob Clark } 4535c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_PSIZE 0x00000100 4536c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_LAYER 0x00000200 4537c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_VIEW 0x00000400 4538c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID 0x00000800 4539c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 4540c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT 16 4541c28c82e9SRob Clark static inline uint32_t A6XX_PC_GS_OUT_CNTL_CLIP_MASK(uint32_t val) 4542c28c82e9SRob Clark { 4543c28c82e9SRob Clark return ((val) << A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK; 4544c28c82e9SRob Clark } 4545c28c82e9SRob Clark 4546c28c82e9SRob Clark #define REG_A6XX_PC_PRIMITIVE_CNTL_3 0x00009b03 4547c28c82e9SRob Clark 4548c28c82e9SRob Clark #define REG_A6XX_PC_DS_OUT_CNTL 0x00009b04 4549c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff 4550c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 4551c28c82e9SRob Clark static inline uint32_t A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) 4552c28c82e9SRob Clark { 4553c28c82e9SRob Clark return ((val) << A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK; 4554c28c82e9SRob Clark } 4555c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_PSIZE 0x00000100 4556c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_LAYER 0x00000200 4557c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_VIEW 0x00000400 4558c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID 0x00000800 4559c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 4560c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT 16 4561c28c82e9SRob Clark static inline uint32_t A6XX_PC_DS_OUT_CNTL_CLIP_MASK(uint32_t val) 4562c28c82e9SRob Clark { 4563c28c82e9SRob Clark return ((val) << A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK; 4564c28c82e9SRob Clark } 4565c28c82e9SRob Clark 4566c28c82e9SRob Clark #define REG_A6XX_PC_PRIMITIVE_CNTL_5 0x00009b05 4567c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK 0x000000ff 4568c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT 0 4569c28c82e9SRob Clark static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val) 4570c28c82e9SRob Clark { 4571c28c82e9SRob Clark return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK; 4572c28c82e9SRob Clark } 4573c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK 0x00007c00 4574c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT 10 4575c28c82e9SRob Clark static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val) 4576c28c82e9SRob Clark { 4577c28c82e9SRob Clark return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK; 4578c28c82e9SRob Clark } 4579c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK 0x00030000 4580c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT 16 4581c28c82e9SRob Clark static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val) 4582c28c82e9SRob Clark { 4583c28c82e9SRob Clark return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK; 4584c28c82e9SRob Clark } 4585c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK 0x00040000 4586c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT 18 4587c28c82e9SRob Clark static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_UNK18(uint32_t val) 4588c28c82e9SRob Clark { 4589c28c82e9SRob Clark return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK; 4590c28c82e9SRob Clark } 4591c28c82e9SRob Clark 4592c28c82e9SRob Clark #define REG_A6XX_PC_PRIMITIVE_CNTL_6 0x00009b06 4593c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK 0x000007ff 4594c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT 0 4595c28c82e9SRob Clark static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(uint32_t val) 4596c28c82e9SRob Clark { 4597c28c82e9SRob Clark return ((val) << A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK; 4598c28c82e9SRob Clark } 45992d756322SRob Clark 4600*cc4c26d4SRob Clark #define REG_A6XX_PC_MULTIVIEW_CNTL 0x00009b07 4601*cc4c26d4SRob Clark #define A6XX_PC_MULTIVIEW_CNTL_ENABLE 0x00000001 4602*cc4c26d4SRob Clark #define A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002 4603*cc4c26d4SRob Clark #define A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c 4604*cc4c26d4SRob Clark #define A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT 2 4605*cc4c26d4SRob Clark static inline uint32_t A6XX_PC_MULTIVIEW_CNTL_VIEWS(uint32_t val) 4606*cc4c26d4SRob Clark { 4607*cc4c26d4SRob Clark return ((val) << A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK; 4608*cc4c26d4SRob Clark } 46092d756322SRob Clark 4610*cc4c26d4SRob Clark #define REG_A6XX_PC_MULTIVIEW_MASK 0x00009b08 4611c28c82e9SRob Clark 4612c28c82e9SRob Clark #define REG_A6XX_PC_2D_EVENT_CMD 0x00009c00 4613c28c82e9SRob Clark #define A6XX_PC_2D_EVENT_CMD_EVENT__MASK 0x0000007f 4614c28c82e9SRob Clark #define A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT 0 4615c28c82e9SRob Clark static inline uint32_t A6XX_PC_2D_EVENT_CMD_EVENT(enum vgt_event_type val) 4616c28c82e9SRob Clark { 4617c28c82e9SRob Clark return ((val) << A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_2D_EVENT_CMD_EVENT__MASK; 4618c28c82e9SRob Clark } 4619c28c82e9SRob Clark #define A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00 4620c28c82e9SRob Clark #define A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT 8 4621c28c82e9SRob Clark static inline uint32_t A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val) 4622c28c82e9SRob Clark { 4623c28c82e9SRob Clark return ((val) << A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK; 4624c28c82e9SRob Clark } 4625c28c82e9SRob Clark 4626c28c82e9SRob Clark #define REG_A6XX_PC_DBG_ECO_CNTL 0x00009e00 4627c28c82e9SRob Clark 4628c28c82e9SRob Clark #define REG_A6XX_PC_ADDR_MODE_CNTL 0x00009e01 4629c28c82e9SRob Clark 4630*cc4c26d4SRob Clark #define REG_A6XX_PC_DRAW_INDX_BASE 0x00009e04 46312d756322SRob Clark 4632*cc4c26d4SRob Clark #define REG_A6XX_PC_DRAW_FIRST_INDX 0x00009e06 4633*cc4c26d4SRob Clark 4634*cc4c26d4SRob Clark #define REG_A6XX_PC_DRAW_MAX_INDICES 0x00009e07 46352d756322SRob Clark 4636c28c82e9SRob Clark #define REG_A6XX_PC_TESSFACTOR_ADDR 0x00009e08 4637c28c82e9SRob Clark #define A6XX_PC_TESSFACTOR_ADDR__MASK 0xffffffff 4638c28c82e9SRob Clark #define A6XX_PC_TESSFACTOR_ADDR__SHIFT 0 4639c28c82e9SRob Clark static inline uint32_t A6XX_PC_TESSFACTOR_ADDR(uint32_t val) 4640c28c82e9SRob Clark { 4641c28c82e9SRob Clark return ((val) << A6XX_PC_TESSFACTOR_ADDR__SHIFT) & A6XX_PC_TESSFACTOR_ADDR__MASK; 4642c28c82e9SRob Clark } 4643c28c82e9SRob Clark 4644*cc4c26d4SRob Clark #define REG_A6XX_PC_DRAW_INITIATOR 0x00009e0b 4645*cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f 4646*cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 4647*cc4c26d4SRob Clark static inline uint32_t A6XX_PC_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) 4648*cc4c26d4SRob Clark { 4649*cc4c26d4SRob Clark return ((val) << A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK; 4650*cc4c26d4SRob Clark } 4651*cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 4652*cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 4653*cc4c26d4SRob Clark static inline uint32_t A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) 4654*cc4c26d4SRob Clark { 4655*cc4c26d4SRob Clark return ((val) << A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK; 4656*cc4c26d4SRob Clark } 4657*cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK 0x00000300 4658*cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT 8 4659*cc4c26d4SRob Clark static inline uint32_t A6XX_PC_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) 4660*cc4c26d4SRob Clark { 4661*cc4c26d4SRob Clark return ((val) << A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT) & A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK; 4662*cc4c26d4SRob Clark } 4663*cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000c00 4664*cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT 10 4665*cc4c26d4SRob Clark static inline uint32_t A6XX_PC_DRAW_INITIATOR_INDEX_SIZE(enum a4xx_index_size val) 4666*cc4c26d4SRob Clark { 4667*cc4c26d4SRob Clark return ((val) << A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK; 4668*cc4c26d4SRob Clark } 4669*cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK 0x00003000 4670*cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT 12 4671*cc4c26d4SRob Clark static inline uint32_t A6XX_PC_DRAW_INITIATOR_PATCH_TYPE(enum a6xx_patch_type val) 4672*cc4c26d4SRob Clark { 4673*cc4c26d4SRob Clark return ((val) << A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK; 4674*cc4c26d4SRob Clark } 4675*cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_GS_ENABLE 0x00010000 4676*cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_TESS_ENABLE 0x00020000 4677*cc4c26d4SRob Clark 4678*cc4c26d4SRob Clark #define REG_A6XX_PC_DRAW_NUM_INSTANCES 0x00009e0c 4679*cc4c26d4SRob Clark 4680*cc4c26d4SRob Clark #define REG_A6XX_PC_DRAW_NUM_INDICES 0x00009e0d 4681*cc4c26d4SRob Clark 4682c28c82e9SRob Clark #define REG_A6XX_PC_VSTREAM_CONTROL 0x00009e11 4683c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_UNK0__MASK 0x0000ffff 4684c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT 0 4685c28c82e9SRob Clark static inline uint32_t A6XX_PC_VSTREAM_CONTROL_UNK0(uint32_t val) 4686c28c82e9SRob Clark { 4687c28c82e9SRob Clark return ((val) << A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT) & A6XX_PC_VSTREAM_CONTROL_UNK0__MASK; 4688c28c82e9SRob Clark } 4689c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK 0x003f0000 4690c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT 16 4691c28c82e9SRob Clark static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_SIZE(uint32_t val) 4692c28c82e9SRob Clark { 4693c28c82e9SRob Clark return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK; 4694c28c82e9SRob Clark } 4695c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK 0x07c00000 4696c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT 22 4697c28c82e9SRob Clark static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_N(uint32_t val) 4698c28c82e9SRob Clark { 4699c28c82e9SRob Clark return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK; 4700c28c82e9SRob Clark } 4701c28c82e9SRob Clark 4702c28c82e9SRob Clark #define REG_A6XX_PC_BIN_PRIM_STRM 0x00009e12 4703c28c82e9SRob Clark #define A6XX_PC_BIN_PRIM_STRM__MASK 0xffffffff 4704c28c82e9SRob Clark #define A6XX_PC_BIN_PRIM_STRM__SHIFT 0 4705c28c82e9SRob Clark static inline uint32_t A6XX_PC_BIN_PRIM_STRM(uint32_t val) 4706c28c82e9SRob Clark { 4707c28c82e9SRob Clark return ((val) << A6XX_PC_BIN_PRIM_STRM__SHIFT) & A6XX_PC_BIN_PRIM_STRM__MASK; 4708c28c82e9SRob Clark } 4709c28c82e9SRob Clark 4710c28c82e9SRob Clark #define REG_A6XX_PC_BIN_DRAW_STRM 0x00009e14 4711c28c82e9SRob Clark #define A6XX_PC_BIN_DRAW_STRM__MASK 0xffffffff 4712c28c82e9SRob Clark #define A6XX_PC_BIN_DRAW_STRM__SHIFT 0 4713c28c82e9SRob Clark static inline uint32_t A6XX_PC_BIN_DRAW_STRM(uint32_t val) 4714c28c82e9SRob Clark { 4715c28c82e9SRob Clark return ((val) << A6XX_PC_BIN_DRAW_STRM__SHIFT) & A6XX_PC_BIN_DRAW_STRM__MASK; 4716c28c82e9SRob Clark } 4717c28c82e9SRob Clark 4718*cc4c26d4SRob Clark #define REG_A6XX_PC_VISIBILITY_OVERRIDE 0x00009e1c 4719*cc4c26d4SRob Clark #define A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE 0x00000001 4720c28c82e9SRob Clark 4721*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_PC_PERFCTR_PC_SEL(uint32_t i0) { return 0x00009e34 + 0x1*i0; } 4722c28c82e9SRob Clark 47232d756322SRob Clark #define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72 47242d756322SRob Clark 47252d756322SRob Clark #define REG_A6XX_VFD_CONTROL_0 0x0000a000 4726c28c82e9SRob Clark #define A6XX_VFD_CONTROL_0_FETCH_CNT__MASK 0x0000003f 4727c28c82e9SRob Clark #define A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT 0 4728c28c82e9SRob Clark static inline uint32_t A6XX_VFD_CONTROL_0_FETCH_CNT(uint32_t val) 47292d756322SRob Clark { 4730c28c82e9SRob Clark return ((val) << A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT) & A6XX_VFD_CONTROL_0_FETCH_CNT__MASK; 4731c28c82e9SRob Clark } 4732c28c82e9SRob Clark #define A6XX_VFD_CONTROL_0_DECODE_CNT__MASK 0x00003f00 4733c28c82e9SRob Clark #define A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT 8 4734c28c82e9SRob Clark static inline uint32_t A6XX_VFD_CONTROL_0_DECODE_CNT(uint32_t val) 4735c28c82e9SRob Clark { 4736c28c82e9SRob Clark return ((val) << A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT) & A6XX_VFD_CONTROL_0_DECODE_CNT__MASK; 47372d756322SRob Clark } 47382d756322SRob Clark 47392d756322SRob Clark #define REG_A6XX_VFD_CONTROL_1 0x0000a001 47402d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff 47412d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0 47422d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 47432d756322SRob Clark { 47442d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VTX__MASK; 47452d756322SRob Clark } 47462d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00 47472d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4INST__SHIFT 8 47482d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 47492d756322SRob Clark { 47502d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK; 47512d756322SRob Clark } 47522d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000 47532d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16 47542d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val) 47552d756322SRob Clark { 47562d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK; 47572d756322SRob Clark } 4758*cc4c26d4SRob Clark #define A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK 0xff000000 4759*cc4c26d4SRob Clark #define A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT 24 4760*cc4c26d4SRob Clark static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VIEWID(uint32_t val) 4761*cc4c26d4SRob Clark { 4762*cc4c26d4SRob Clark return ((val) << A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK; 4763*cc4c26d4SRob Clark } 47642d756322SRob Clark 47652d756322SRob Clark #define REG_A6XX_VFD_CONTROL_2 0x0000a002 4766c28c82e9SRob Clark #define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK 0x000000ff 4767c28c82e9SRob Clark #define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__SHIFT 0 4768c28c82e9SRob Clark static inline uint32_t A6XX_VFD_CONTROL_2_REGID_HSPATCHID(uint32_t val) 47692d756322SRob Clark { 4770c28c82e9SRob Clark return ((val) << A6XX_VFD_CONTROL_2_REGID_HSPATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK; 4771c28c82e9SRob Clark } 4772c28c82e9SRob Clark #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK 0x0000ff00 4773c28c82e9SRob Clark #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT 8 4774c28c82e9SRob Clark static inline uint32_t A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val) 4775c28c82e9SRob Clark { 4776c28c82e9SRob Clark return ((val) << A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK; 47772d756322SRob Clark } 47782d756322SRob Clark 47792d756322SRob Clark #define REG_A6XX_VFD_CONTROL_3 0x0000a003 4780*cc4c26d4SRob Clark #define A6XX_VFD_CONTROL_3_UNK0__MASK 0x000000ff 4781*cc4c26d4SRob Clark #define A6XX_VFD_CONTROL_3_UNK0__SHIFT 0 4782*cc4c26d4SRob Clark static inline uint32_t A6XX_VFD_CONTROL_3_UNK0(uint32_t val) 4783*cc4c26d4SRob Clark { 4784*cc4c26d4SRob Clark return ((val) << A6XX_VFD_CONTROL_3_UNK0__SHIFT) & A6XX_VFD_CONTROL_3_UNK0__MASK; 4785*cc4c26d4SRob Clark } 4786c28c82e9SRob Clark #define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK 0x0000ff00 4787c28c82e9SRob Clark #define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT 8 4788c28c82e9SRob Clark static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPATCHID(uint32_t val) 47892d756322SRob Clark { 4790c28c82e9SRob Clark return ((val) << A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK; 47912d756322SRob Clark } 47922d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000 47932d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16 47942d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) 47952d756322SRob Clark { 47962d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSX__MASK; 47972d756322SRob Clark } 47982d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000 47992d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24 48002d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) 48012d756322SRob Clark { 48022d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK; 48032d756322SRob Clark } 48042d756322SRob Clark 48052d756322SRob Clark #define REG_A6XX_VFD_CONTROL_4 0x0000a004 4806*cc4c26d4SRob Clark #define A6XX_VFD_CONTROL_4_UNK0__MASK 0x000000ff 4807*cc4c26d4SRob Clark #define A6XX_VFD_CONTROL_4_UNK0__SHIFT 0 4808*cc4c26d4SRob Clark static inline uint32_t A6XX_VFD_CONTROL_4_UNK0(uint32_t val) 4809*cc4c26d4SRob Clark { 4810*cc4c26d4SRob Clark return ((val) << A6XX_VFD_CONTROL_4_UNK0__SHIFT) & A6XX_VFD_CONTROL_4_UNK0__MASK; 4811*cc4c26d4SRob Clark } 48122d756322SRob Clark 48132d756322SRob Clark #define REG_A6XX_VFD_CONTROL_5 0x0000a005 4814c28c82e9SRob Clark #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK 0x000000ff 4815c28c82e9SRob Clark #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT 0 4816c28c82e9SRob Clark static inline uint32_t A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val) 4817c28c82e9SRob Clark { 4818c28c82e9SRob Clark return ((val) << A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT) & A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK; 4819c28c82e9SRob Clark } 4820*cc4c26d4SRob Clark #define A6XX_VFD_CONTROL_5_UNK8__MASK 0x0000ff00 4821*cc4c26d4SRob Clark #define A6XX_VFD_CONTROL_5_UNK8__SHIFT 8 4822*cc4c26d4SRob Clark static inline uint32_t A6XX_VFD_CONTROL_5_UNK8(uint32_t val) 4823*cc4c26d4SRob Clark { 4824*cc4c26d4SRob Clark return ((val) << A6XX_VFD_CONTROL_5_UNK8__SHIFT) & A6XX_VFD_CONTROL_5_UNK8__MASK; 4825*cc4c26d4SRob Clark } 48262d756322SRob Clark 48272d756322SRob Clark #define REG_A6XX_VFD_CONTROL_6 0x0000a006 4828c28c82e9SRob Clark #define A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU 0x00000001 48292d756322SRob Clark 48302d756322SRob Clark #define REG_A6XX_VFD_MODE_CNTL 0x0000a007 48312d756322SRob Clark #define A6XX_VFD_MODE_CNTL_BINNING_PASS 0x00000001 4832*cc4c26d4SRob Clark #define A6XX_VFD_MODE_CNTL_UNK1 0x00000002 4833*cc4c26d4SRob Clark #define A6XX_VFD_MODE_CNTL_UNK2 0x00000004 48342d756322SRob Clark 4835*cc4c26d4SRob Clark #define REG_A6XX_VFD_MULTIVIEW_CNTL 0x0000a008 4836*cc4c26d4SRob Clark #define A6XX_VFD_MULTIVIEW_CNTL_ENABLE 0x00000001 4837*cc4c26d4SRob Clark #define A6XX_VFD_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002 4838*cc4c26d4SRob Clark #define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c 4839*cc4c26d4SRob Clark #define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT 2 4840*cc4c26d4SRob Clark static inline uint32_t A6XX_VFD_MULTIVIEW_CNTL_VIEWS(uint32_t val) 4841*cc4c26d4SRob Clark { 4842*cc4c26d4SRob Clark return ((val) << A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK; 4843*cc4c26d4SRob Clark } 48442d756322SRob Clark 4845c28c82e9SRob Clark #define REG_A6XX_VFD_ADD_OFFSET 0x0000a009 4846c28c82e9SRob Clark #define A6XX_VFD_ADD_OFFSET_VERTEX 0x00000001 4847c28c82e9SRob Clark #define A6XX_VFD_ADD_OFFSET_INSTANCE 0x00000002 4848a69c5ed2SRob Clark 48492d756322SRob Clark #define REG_A6XX_VFD_INDEX_OFFSET 0x0000a00e 48502d756322SRob Clark 48512d756322SRob Clark #define REG_A6XX_VFD_INSTANCE_START_OFFSET 0x0000a00f 48522d756322SRob Clark 48532d756322SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; } 48542d756322SRob Clark 4855c28c82e9SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; } 4856*cc4c26d4SRob Clark #define A6XX_VFD_FETCH_BASE__MASK 0xffffffff 4857*cc4c26d4SRob Clark #define A6XX_VFD_FETCH_BASE__SHIFT 0 4858*cc4c26d4SRob Clark static inline uint32_t A6XX_VFD_FETCH_BASE(uint32_t val) 4859*cc4c26d4SRob Clark { 4860*cc4c26d4SRob Clark return ((val) << A6XX_VFD_FETCH_BASE__SHIFT) & A6XX_VFD_FETCH_BASE__MASK; 4861*cc4c26d4SRob Clark } 48622d756322SRob Clark 48632d756322SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; } 48642d756322SRob Clark 48652d756322SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; } 48662d756322SRob Clark 48672d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; } 48682d756322SRob Clark 48692d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; } 48702d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f 48712d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_IDX__SHIFT 0 48722d756322SRob Clark static inline uint32_t A6XX_VFD_DECODE_INSTR_IDX(uint32_t val) 48732d756322SRob Clark { 48742d756322SRob Clark return ((val) << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK; 48752d756322SRob Clark } 4876c28c82e9SRob Clark #define A6XX_VFD_DECODE_INSTR_OFFSET__MASK 0x0001ffe0 4877c28c82e9SRob Clark #define A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT 5 4878c28c82e9SRob Clark static inline uint32_t A6XX_VFD_DECODE_INSTR_OFFSET(uint32_t val) 4879c28c82e9SRob Clark { 4880c28c82e9SRob Clark return ((val) << A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT) & A6XX_VFD_DECODE_INSTR_OFFSET__MASK; 4881c28c82e9SRob Clark } 48822d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_INSTANCED 0x00020000 48832d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000 48842d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20 4885c28c82e9SRob Clark static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_format val) 48862d756322SRob Clark { 48872d756322SRob Clark return ((val) << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK; 48882d756322SRob Clark } 48892d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000 48902d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_SWAP__SHIFT 28 48912d756322SRob Clark static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 48922d756322SRob Clark { 48932d756322SRob Clark return ((val) << A6XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A6XX_VFD_DECODE_INSTR_SWAP__MASK; 48942d756322SRob Clark } 48952d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_UNK30 0x40000000 48962d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_FLOAT 0x80000000 48972d756322SRob Clark 48982d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; } 48992d756322SRob Clark 49002d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } 49012d756322SRob Clark 49022d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } 49032d756322SRob Clark #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f 49042d756322SRob Clark #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0 49052d756322SRob Clark static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val) 49062d756322SRob Clark { 49072d756322SRob Clark return ((val) << A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK; 49082d756322SRob Clark } 49092d756322SRob Clark #define A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0 49102d756322SRob Clark #define A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4 49112d756322SRob Clark static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) 49122d756322SRob Clark { 49132d756322SRob Clark return ((val) << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK; 49142d756322SRob Clark } 49152d756322SRob Clark 49162d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_A0F8 0x0000a0f8 49172d756322SRob Clark 4918*cc4c26d4SRob Clark #define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601 4919*cc4c26d4SRob Clark 4920*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) { return 0x0000a610 + 0x1*i0; } 4921*cc4c26d4SRob Clark 4922c28c82e9SRob Clark #define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800 4923*cc4c26d4SRob Clark #define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x00100000 4924*cc4c26d4SRob Clark #define A6XX_SP_VS_CTRL_REG0_UNK21 0x00200000 4925*cc4c26d4SRob Clark #define A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 4926*cc4c26d4SRob Clark #define A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 4927*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 4928*cc4c26d4SRob Clark { 4929*cc4c26d4SRob Clark return ((val) << A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK; 4930*cc4c26d4SRob Clark } 4931c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 4932c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 4933c28c82e9SRob Clark static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 49342d756322SRob Clark { 4935c28c82e9SRob Clark return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 4936c28c82e9SRob Clark } 4937c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 4938c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 4939c28c82e9SRob Clark static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 4940c28c82e9SRob Clark { 4941c28c82e9SRob Clark return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 4942c28c82e9SRob Clark } 4943*cc4c26d4SRob Clark #define A6XX_SP_VS_CTRL_REG0_UNK13 0x00002000 4944c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 4945c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14 4946c28c82e9SRob Clark static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val) 4947c28c82e9SRob Clark { 4948c28c82e9SRob Clark return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK; 4949c28c82e9SRob Clark } 4950c28c82e9SRob Clark 4951c28c82e9SRob Clark #define REG_A6XX_SP_VS_BRANCH_COND 0x0000a801 4952c28c82e9SRob Clark 4953c28c82e9SRob Clark #define REG_A6XX_SP_VS_PRIMITIVE_CNTL 0x0000a802 4954c28c82e9SRob Clark #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f 4955c28c82e9SRob Clark #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT 0 4956c28c82e9SRob Clark static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_OUT(uint32_t val) 4957c28c82e9SRob Clark { 4958c28c82e9SRob Clark return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK; 49592d756322SRob Clark } 4960*cc4c26d4SRob Clark #define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0 4961*cc4c26d4SRob Clark #define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6 4962*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) 4963*cc4c26d4SRob Clark { 4964*cc4c26d4SRob Clark return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; 4965*cc4c26d4SRob Clark } 49662d756322SRob Clark 49672d756322SRob Clark static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; } 49682d756322SRob Clark 49692d756322SRob Clark static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; } 49702d756322SRob Clark #define A6XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff 49712d756322SRob Clark #define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 49722d756322SRob Clark static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 49732d756322SRob Clark { 49742d756322SRob Clark return ((val) << A6XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_A_REGID__MASK; 49752d756322SRob Clark } 49762d756322SRob Clark #define A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00 49772d756322SRob Clark #define A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8 49782d756322SRob Clark static inline uint32_t A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 49792d756322SRob Clark { 49802d756322SRob Clark return ((val) << A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 49812d756322SRob Clark } 49822d756322SRob Clark #define A6XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000 49832d756322SRob Clark #define A6XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 49842d756322SRob Clark static inline uint32_t A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 49852d756322SRob Clark { 49862d756322SRob Clark return ((val) << A6XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_B_REGID__MASK; 49872d756322SRob Clark } 49882d756322SRob Clark #define A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000 49892d756322SRob Clark #define A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24 49902d756322SRob Clark static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 49912d756322SRob Clark { 49922d756322SRob Clark return ((val) << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 49932d756322SRob Clark } 49942d756322SRob Clark 49952d756322SRob Clark static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; } 49962d756322SRob Clark 49972d756322SRob Clark static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; } 49982d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 49992d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 50002d756322SRob Clark static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 50012d756322SRob Clark { 50022d756322SRob Clark return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 50032d756322SRob Clark } 50042d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 50052d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 50062d756322SRob Clark static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 50072d756322SRob Clark { 50082d756322SRob Clark return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 50092d756322SRob Clark } 50102d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 50112d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 50122d756322SRob Clark static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 50132d756322SRob Clark { 50142d756322SRob Clark return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 50152d756322SRob Clark } 50162d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 50172d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 50182d756322SRob Clark static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 50192d756322SRob Clark { 50202d756322SRob Clark return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 50212d756322SRob Clark } 50222d756322SRob Clark 5023*cc4c26d4SRob Clark #define REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET 0x0000a81b 5024a69c5ed2SRob Clark 5025*cc4c26d4SRob Clark #define REG_A6XX_SP_VS_OBJ_START 0x0000a81c 5026*cc4c26d4SRob Clark #define A6XX_SP_VS_OBJ_START__MASK 0xffffffff 5027*cc4c26d4SRob Clark #define A6XX_SP_VS_OBJ_START__SHIFT 0 5028*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_OBJ_START(uint32_t val) 5029*cc4c26d4SRob Clark { 5030*cc4c26d4SRob Clark return ((val) << A6XX_SP_VS_OBJ_START__SHIFT) & A6XX_SP_VS_OBJ_START__MASK; 5031*cc4c26d4SRob Clark } 50322d756322SRob Clark 5033*cc4c26d4SRob Clark #define REG_A6XX_SP_VS_PVT_MEM_PARAM 0x0000a81e 5034*cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 5035*cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 5036*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 5037*cc4c26d4SRob Clark { 5038*cc4c26d4SRob Clark return ((val >> 9) << A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 5039*cc4c26d4SRob Clark } 5040*cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 5041*cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 5042*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 5043*cc4c26d4SRob Clark { 5044*cc4c26d4SRob Clark return ((val) << A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 5045*cc4c26d4SRob Clark } 5046*cc4c26d4SRob Clark 5047*cc4c26d4SRob Clark #define REG_A6XX_SP_VS_PVT_MEM_ADDR 0x0000a81f 5048*cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_ADDR__MASK 0xffffffff 5049*cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_ADDR__SHIFT 0 5050*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_PVT_MEM_ADDR(uint32_t val) 5051*cc4c26d4SRob Clark { 5052*cc4c26d4SRob Clark return ((val) << A6XX_SP_VS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_VS_PVT_MEM_ADDR__MASK; 5053*cc4c26d4SRob Clark } 5054*cc4c26d4SRob Clark 5055*cc4c26d4SRob Clark #define REG_A6XX_SP_VS_PVT_MEM_SIZE 0x0000a821 5056*cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 5057*cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 5058*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 5059*cc4c26d4SRob Clark { 5060*cc4c26d4SRob Clark return ((val >> 12) << A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 5061*cc4c26d4SRob Clark } 5062*cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 50632d756322SRob Clark 50642d756322SRob Clark #define REG_A6XX_SP_VS_TEX_COUNT 0x0000a822 50652d756322SRob Clark 50662d756322SRob Clark #define REG_A6XX_SP_VS_CONFIG 0x0000a823 5067c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_BINDLESS_TEX 0x00000001 5068c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_BINDLESS_SAMP 0x00000002 5069c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_BINDLESS_IBO 0x00000004 5070c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_BINDLESS_UBO 0x00000008 50712d756322SRob Clark #define A6XX_SP_VS_CONFIG_ENABLED 0x00000100 50722d756322SRob Clark #define A6XX_SP_VS_CONFIG_NTEX__MASK 0x0001fe00 50732d756322SRob Clark #define A6XX_SP_VS_CONFIG_NTEX__SHIFT 9 50742d756322SRob Clark static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val) 50752d756322SRob Clark { 50762d756322SRob Clark return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK; 50772d756322SRob Clark } 5078c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_NSAMP__MASK 0x003e0000 50792d756322SRob Clark #define A6XX_SP_VS_CONFIG_NSAMP__SHIFT 17 50802d756322SRob Clark static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val) 50812d756322SRob Clark { 50822d756322SRob Clark return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK; 50832d756322SRob Clark } 5084*cc4c26d4SRob Clark #define A6XX_SP_VS_CONFIG_NIBO__MASK 0x1fc00000 5085c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_NIBO__SHIFT 22 5086c28c82e9SRob Clark static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val) 5087c28c82e9SRob Clark { 5088c28c82e9SRob Clark return ((val) << A6XX_SP_VS_CONFIG_NIBO__SHIFT) & A6XX_SP_VS_CONFIG_NIBO__MASK; 5089c28c82e9SRob Clark } 50902d756322SRob Clark 50912d756322SRob Clark #define REG_A6XX_SP_VS_INSTRLEN 0x0000a824 50922d756322SRob Clark 5093*cc4c26d4SRob Clark #define REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET 0x0000a825 5094*cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff 5095*cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0 5096*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET(uint32_t val) 5097*cc4c26d4SRob Clark { 5098*cc4c26d4SRob Clark return ((val >> 11) << A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__MASK; 5099*cc4c26d4SRob Clark } 5100*cc4c26d4SRob Clark 51012d756322SRob Clark #define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830 5102*cc4c26d4SRob Clark #define A6XX_SP_HS_CTRL_REG0_UNK20 0x00100000 5103*cc4c26d4SRob Clark #define A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK 0x00000001 5104*cc4c26d4SRob Clark #define A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT 0 5105*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 5106*cc4c26d4SRob Clark { 5107*cc4c26d4SRob Clark return ((val) << A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK; 5108*cc4c26d4SRob Clark } 51092d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 51102d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 51112d756322SRob Clark static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 51122d756322SRob Clark { 51132d756322SRob Clark return ((val) << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 51142d756322SRob Clark } 51152d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 51162d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 51172d756322SRob Clark static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 51182d756322SRob Clark { 51192d756322SRob Clark return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 51202d756322SRob Clark } 5121*cc4c26d4SRob Clark #define A6XX_SP_HS_CTRL_REG0_UNK13 0x00002000 51222d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 51232d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 14 51242d756322SRob Clark static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val) 51252d756322SRob Clark { 51262d756322SRob Clark return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK; 51272d756322SRob Clark } 5128*cc4c26d4SRob Clark 5129*cc4c26d4SRob Clark #define REG_A6XX_SP_HS_WAVE_INPUT_SIZE 0x0000a831 5130*cc4c26d4SRob Clark 5131*cc4c26d4SRob Clark #define REG_A6XX_SP_HS_BRANCH_COND 0x0000a832 5132*cc4c26d4SRob Clark 5133*cc4c26d4SRob Clark #define REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET 0x0000a833 5134*cc4c26d4SRob Clark 5135*cc4c26d4SRob Clark #define REG_A6XX_SP_HS_OBJ_START 0x0000a834 5136*cc4c26d4SRob Clark #define A6XX_SP_HS_OBJ_START__MASK 0xffffffff 5137*cc4c26d4SRob Clark #define A6XX_SP_HS_OBJ_START__SHIFT 0 5138*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_OBJ_START(uint32_t val) 51392d756322SRob Clark { 5140*cc4c26d4SRob Clark return ((val) << A6XX_SP_HS_OBJ_START__SHIFT) & A6XX_SP_HS_OBJ_START__MASK; 51412d756322SRob Clark } 51422d756322SRob Clark 5143*cc4c26d4SRob Clark #define REG_A6XX_SP_HS_PVT_MEM_PARAM 0x0000a836 5144*cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 5145*cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 5146*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 5147*cc4c26d4SRob Clark { 5148*cc4c26d4SRob Clark return ((val >> 9) << A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 5149*cc4c26d4SRob Clark } 5150*cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 5151*cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 5152*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 5153*cc4c26d4SRob Clark { 5154*cc4c26d4SRob Clark return ((val) << A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 5155*cc4c26d4SRob Clark } 51562d756322SRob Clark 5157*cc4c26d4SRob Clark #define REG_A6XX_SP_HS_PVT_MEM_ADDR 0x0000a837 5158*cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_ADDR__MASK 0xffffffff 5159*cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_ADDR__SHIFT 0 5160*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_PVT_MEM_ADDR(uint32_t val) 5161*cc4c26d4SRob Clark { 5162*cc4c26d4SRob Clark return ((val) << A6XX_SP_HS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_HS_PVT_MEM_ADDR__MASK; 5163*cc4c26d4SRob Clark } 5164c28c82e9SRob Clark 5165*cc4c26d4SRob Clark #define REG_A6XX_SP_HS_PVT_MEM_SIZE 0x0000a839 5166*cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 5167*cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 5168*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 5169*cc4c26d4SRob Clark { 5170*cc4c26d4SRob Clark return ((val >> 12) << A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 5171*cc4c26d4SRob Clark } 5172*cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 51732d756322SRob Clark 51742d756322SRob Clark #define REG_A6XX_SP_HS_TEX_COUNT 0x0000a83a 51752d756322SRob Clark 51762d756322SRob Clark #define REG_A6XX_SP_HS_CONFIG 0x0000a83b 5177c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_BINDLESS_TEX 0x00000001 5178c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_BINDLESS_SAMP 0x00000002 5179c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_BINDLESS_IBO 0x00000004 5180c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_BINDLESS_UBO 0x00000008 51812d756322SRob Clark #define A6XX_SP_HS_CONFIG_ENABLED 0x00000100 51822d756322SRob Clark #define A6XX_SP_HS_CONFIG_NTEX__MASK 0x0001fe00 51832d756322SRob Clark #define A6XX_SP_HS_CONFIG_NTEX__SHIFT 9 51842d756322SRob Clark static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val) 51852d756322SRob Clark { 51862d756322SRob Clark return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK; 51872d756322SRob Clark } 5188c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_NSAMP__MASK 0x003e0000 51892d756322SRob Clark #define A6XX_SP_HS_CONFIG_NSAMP__SHIFT 17 51902d756322SRob Clark static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val) 51912d756322SRob Clark { 51922d756322SRob Clark return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK; 51932d756322SRob Clark } 5194*cc4c26d4SRob Clark #define A6XX_SP_HS_CONFIG_NIBO__MASK 0x1fc00000 5195c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_NIBO__SHIFT 22 5196c28c82e9SRob Clark static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val) 5197c28c82e9SRob Clark { 5198c28c82e9SRob Clark return ((val) << A6XX_SP_HS_CONFIG_NIBO__SHIFT) & A6XX_SP_HS_CONFIG_NIBO__MASK; 5199c28c82e9SRob Clark } 52002d756322SRob Clark 52012d756322SRob Clark #define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c 52022d756322SRob Clark 5203*cc4c26d4SRob Clark #define REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET 0x0000a83d 5204*cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff 5205*cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0 5206*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET(uint32_t val) 5207*cc4c26d4SRob Clark { 5208*cc4c26d4SRob Clark return ((val >> 11) << A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__MASK; 5209*cc4c26d4SRob Clark } 5210*cc4c26d4SRob Clark 52112d756322SRob Clark #define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840 5212*cc4c26d4SRob Clark #define A6XX_SP_DS_CTRL_REG0_MERGEDREGS 0x00100000 5213*cc4c26d4SRob Clark #define A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK 0x00000001 5214*cc4c26d4SRob Clark #define A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT 0 5215*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 5216*cc4c26d4SRob Clark { 5217*cc4c26d4SRob Clark return ((val) << A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK; 5218*cc4c26d4SRob Clark } 52192d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 52202d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 52212d756322SRob Clark static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 52222d756322SRob Clark { 52232d756322SRob Clark return ((val) << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 52242d756322SRob Clark } 52252d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 52262d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 52272d756322SRob Clark static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 52282d756322SRob Clark { 52292d756322SRob Clark return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 52302d756322SRob Clark } 5231*cc4c26d4SRob Clark #define A6XX_SP_DS_CTRL_REG0_UNK13 0x00002000 52322d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 52332d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 14 52342d756322SRob Clark static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val) 52352d756322SRob Clark { 52362d756322SRob Clark return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK; 52372d756322SRob Clark } 5238*cc4c26d4SRob Clark 5239*cc4c26d4SRob Clark #define REG_A6XX_SP_DS_BRANCH_COND 0x0000a841 52402d756322SRob Clark 5241c28c82e9SRob Clark #define REG_A6XX_SP_DS_PRIMITIVE_CNTL 0x0000a842 5242c28c82e9SRob Clark #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f 5243c28c82e9SRob Clark #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT 0 5244c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_OUT(uint32_t val) 5245c28c82e9SRob Clark { 5246c28c82e9SRob Clark return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK; 5247c28c82e9SRob Clark } 5248*cc4c26d4SRob Clark #define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0 5249*cc4c26d4SRob Clark #define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6 5250*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) 5251*cc4c26d4SRob Clark { 5252*cc4c26d4SRob Clark return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; 5253*cc4c26d4SRob Clark } 5254c28c82e9SRob Clark 5255c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; } 5256c28c82e9SRob Clark 5257c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000a843 + 0x1*i0; } 5258c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_A_REGID__MASK 0x000000ff 5259c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_A_REGID__SHIFT 0 5260c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_OUT_REG_A_REGID(uint32_t val) 5261c28c82e9SRob Clark { 5262c28c82e9SRob Clark return ((val) << A6XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_A_REGID__MASK; 5263c28c82e9SRob Clark } 5264c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00000f00 5265c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 8 5266c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val) 5267c28c82e9SRob Clark { 5268c28c82e9SRob Clark return ((val) << A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK; 5269c28c82e9SRob Clark } 5270c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_B_REGID__MASK 0x00ff0000 5271c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_B_REGID__SHIFT 16 5272c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_OUT_REG_B_REGID(uint32_t val) 5273c28c82e9SRob Clark { 5274c28c82e9SRob Clark return ((val) << A6XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_B_REGID__MASK; 5275c28c82e9SRob Clark } 5276c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x0f000000 5277c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 24 5278c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val) 5279c28c82e9SRob Clark { 5280c28c82e9SRob Clark return ((val) << A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK; 5281c28c82e9SRob Clark } 5282c28c82e9SRob Clark 5283c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000a853 + 0x1*i0; } 5284c28c82e9SRob Clark 5285c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000a853 + 0x1*i0; } 5286c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 5287c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0 5288c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val) 5289c28c82e9SRob Clark { 5290c28c82e9SRob Clark return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK; 5291c28c82e9SRob Clark } 5292c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 5293c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8 5294c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val) 5295c28c82e9SRob Clark { 5296c28c82e9SRob Clark return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK; 5297c28c82e9SRob Clark } 5298c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 5299c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16 5300c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val) 5301c28c82e9SRob Clark { 5302c28c82e9SRob Clark return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK; 5303c28c82e9SRob Clark } 5304c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 5305c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24 5306c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) 5307c28c82e9SRob Clark { 5308c28c82e9SRob Clark return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK; 5309c28c82e9SRob Clark } 5310c28c82e9SRob Clark 5311*cc4c26d4SRob Clark #define REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET 0x0000a85b 5312c28c82e9SRob Clark 5313*cc4c26d4SRob Clark #define REG_A6XX_SP_DS_OBJ_START 0x0000a85c 5314*cc4c26d4SRob Clark #define A6XX_SP_DS_OBJ_START__MASK 0xffffffff 5315*cc4c26d4SRob Clark #define A6XX_SP_DS_OBJ_START__SHIFT 0 5316*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_OBJ_START(uint32_t val) 5317*cc4c26d4SRob Clark { 5318*cc4c26d4SRob Clark return ((val) << A6XX_SP_DS_OBJ_START__SHIFT) & A6XX_SP_DS_OBJ_START__MASK; 5319*cc4c26d4SRob Clark } 53202d756322SRob Clark 5321*cc4c26d4SRob Clark #define REG_A6XX_SP_DS_PVT_MEM_PARAM 0x0000a85e 5322*cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 5323*cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 5324*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 5325*cc4c26d4SRob Clark { 5326*cc4c26d4SRob Clark return ((val >> 9) << A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 5327*cc4c26d4SRob Clark } 5328*cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 5329*cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 5330*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 5331*cc4c26d4SRob Clark { 5332*cc4c26d4SRob Clark return ((val) << A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 5333*cc4c26d4SRob Clark } 5334*cc4c26d4SRob Clark 5335*cc4c26d4SRob Clark #define REG_A6XX_SP_DS_PVT_MEM_ADDR 0x0000a85f 5336*cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_ADDR__MASK 0xffffffff 5337*cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_ADDR__SHIFT 0 5338*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_PVT_MEM_ADDR(uint32_t val) 5339*cc4c26d4SRob Clark { 5340*cc4c26d4SRob Clark return ((val) << A6XX_SP_DS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_DS_PVT_MEM_ADDR__MASK; 5341*cc4c26d4SRob Clark } 5342*cc4c26d4SRob Clark 5343*cc4c26d4SRob Clark #define REG_A6XX_SP_DS_PVT_MEM_SIZE 0x0000a861 5344*cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 5345*cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 5346*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 5347*cc4c26d4SRob Clark { 5348*cc4c26d4SRob Clark return ((val >> 12) << A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 5349*cc4c26d4SRob Clark } 5350*cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 53512d756322SRob Clark 53522d756322SRob Clark #define REG_A6XX_SP_DS_TEX_COUNT 0x0000a862 53532d756322SRob Clark 53542d756322SRob Clark #define REG_A6XX_SP_DS_CONFIG 0x0000a863 5355c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_BINDLESS_TEX 0x00000001 5356c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_BINDLESS_SAMP 0x00000002 5357c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_BINDLESS_IBO 0x00000004 5358c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_BINDLESS_UBO 0x00000008 53592d756322SRob Clark #define A6XX_SP_DS_CONFIG_ENABLED 0x00000100 53602d756322SRob Clark #define A6XX_SP_DS_CONFIG_NTEX__MASK 0x0001fe00 53612d756322SRob Clark #define A6XX_SP_DS_CONFIG_NTEX__SHIFT 9 53622d756322SRob Clark static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val) 53632d756322SRob Clark { 53642d756322SRob Clark return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK; 53652d756322SRob Clark } 5366c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_NSAMP__MASK 0x003e0000 53672d756322SRob Clark #define A6XX_SP_DS_CONFIG_NSAMP__SHIFT 17 53682d756322SRob Clark static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val) 53692d756322SRob Clark { 53702d756322SRob Clark return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK; 53712d756322SRob Clark } 5372*cc4c26d4SRob Clark #define A6XX_SP_DS_CONFIG_NIBO__MASK 0x1fc00000 5373c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_NIBO__SHIFT 22 5374c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val) 5375c28c82e9SRob Clark { 5376c28c82e9SRob Clark return ((val) << A6XX_SP_DS_CONFIG_NIBO__SHIFT) & A6XX_SP_DS_CONFIG_NIBO__MASK; 5377c28c82e9SRob Clark } 53782d756322SRob Clark 53792d756322SRob Clark #define REG_A6XX_SP_DS_INSTRLEN 0x0000a864 53802d756322SRob Clark 5381*cc4c26d4SRob Clark #define REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET 0x0000a865 5382*cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff 5383*cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0 5384*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET(uint32_t val) 5385*cc4c26d4SRob Clark { 5386*cc4c26d4SRob Clark return ((val >> 11) << A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__MASK; 5387*cc4c26d4SRob Clark } 5388*cc4c26d4SRob Clark 53892d756322SRob Clark #define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870 5390*cc4c26d4SRob Clark #define A6XX_SP_GS_CTRL_REG0_UNK20 0x00100000 5391*cc4c26d4SRob Clark #define A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK 0x00000001 5392*cc4c26d4SRob Clark #define A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT 0 5393*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 5394*cc4c26d4SRob Clark { 5395*cc4c26d4SRob Clark return ((val) << A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK; 5396*cc4c26d4SRob Clark } 53972d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 53982d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 53992d756322SRob Clark static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 54002d756322SRob Clark { 54012d756322SRob Clark return ((val) << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 54022d756322SRob Clark } 54032d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 54042d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 54052d756322SRob Clark static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 54062d756322SRob Clark { 54072d756322SRob Clark return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 54082d756322SRob Clark } 5409*cc4c26d4SRob Clark #define A6XX_SP_GS_CTRL_REG0_UNK13 0x00002000 54102d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 54112d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 14 54122d756322SRob Clark static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val) 54132d756322SRob Clark { 54142d756322SRob Clark return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK; 54152d756322SRob Clark } 54162d756322SRob Clark 5417c28c82e9SRob Clark #define REG_A6XX_SP_GS_PRIM_SIZE 0x0000a871 5418c28c82e9SRob Clark 5419c28c82e9SRob Clark #define REG_A6XX_SP_GS_BRANCH_COND 0x0000a872 5420c28c82e9SRob Clark 5421c28c82e9SRob Clark #define REG_A6XX_SP_GS_PRIMITIVE_CNTL 0x0000a873 5422c28c82e9SRob Clark #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f 5423c28c82e9SRob Clark #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT 0 5424c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_OUT(uint32_t val) 5425c28c82e9SRob Clark { 5426c28c82e9SRob Clark return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK; 5427c28c82e9SRob Clark } 5428c28c82e9SRob Clark #define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0 5429c28c82e9SRob Clark #define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6 5430c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) 5431c28c82e9SRob Clark { 5432c28c82e9SRob Clark return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; 5433c28c82e9SRob Clark } 5434c28c82e9SRob Clark 5435c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_GS_OUT(uint32_t i0) { return 0x0000a874 + 0x1*i0; } 5436c28c82e9SRob Clark 5437c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_GS_OUT_REG(uint32_t i0) { return 0x0000a874 + 0x1*i0; } 5438c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_A_REGID__MASK 0x000000ff 5439c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_A_REGID__SHIFT 0 5440c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_OUT_REG_A_REGID(uint32_t val) 5441c28c82e9SRob Clark { 5442c28c82e9SRob Clark return ((val) << A6XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_A_REGID__MASK; 5443c28c82e9SRob Clark } 5444c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00000f00 5445c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 8 5446c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val) 5447c28c82e9SRob Clark { 5448c28c82e9SRob Clark return ((val) << A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK; 5449c28c82e9SRob Clark } 5450c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_B_REGID__MASK 0x00ff0000 5451c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_B_REGID__SHIFT 16 5452c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_OUT_REG_B_REGID(uint32_t val) 5453c28c82e9SRob Clark { 5454c28c82e9SRob Clark return ((val) << A6XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_B_REGID__MASK; 5455c28c82e9SRob Clark } 5456c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x0f000000 5457c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 24 5458c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val) 5459c28c82e9SRob Clark { 5460c28c82e9SRob Clark return ((val) << A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK; 5461c28c82e9SRob Clark } 5462c28c82e9SRob Clark 5463c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_GS_VPC_DST(uint32_t i0) { return 0x0000a884 + 0x1*i0; } 5464c28c82e9SRob Clark 5465c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x0000a884 + 0x1*i0; } 5466c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 5467c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0 5468c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val) 5469c28c82e9SRob Clark { 5470c28c82e9SRob Clark return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK; 5471c28c82e9SRob Clark } 5472c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 5473c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8 5474c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val) 5475c28c82e9SRob Clark { 5476c28c82e9SRob Clark return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK; 5477c28c82e9SRob Clark } 5478c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 5479c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16 5480c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val) 5481c28c82e9SRob Clark { 5482c28c82e9SRob Clark return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK; 5483c28c82e9SRob Clark } 5484c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 5485c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24 5486c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) 5487c28c82e9SRob Clark { 5488c28c82e9SRob Clark return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK; 5489c28c82e9SRob Clark } 54902d756322SRob Clark 5491*cc4c26d4SRob Clark #define REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET 0x0000a88c 54922d756322SRob Clark 5493*cc4c26d4SRob Clark #define REG_A6XX_SP_GS_OBJ_START 0x0000a88d 5494*cc4c26d4SRob Clark #define A6XX_SP_GS_OBJ_START__MASK 0xffffffff 5495*cc4c26d4SRob Clark #define A6XX_SP_GS_OBJ_START__SHIFT 0 5496*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_OBJ_START(uint32_t val) 5497*cc4c26d4SRob Clark { 5498*cc4c26d4SRob Clark return ((val) << A6XX_SP_GS_OBJ_START__SHIFT) & A6XX_SP_GS_OBJ_START__MASK; 5499*cc4c26d4SRob Clark } 5500*cc4c26d4SRob Clark 5501*cc4c26d4SRob Clark #define REG_A6XX_SP_GS_PVT_MEM_PARAM 0x0000a88f 5502*cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 5503*cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 5504*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 5505*cc4c26d4SRob Clark { 5506*cc4c26d4SRob Clark return ((val >> 9) << A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 5507*cc4c26d4SRob Clark } 5508*cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 5509*cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 5510*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 5511*cc4c26d4SRob Clark { 5512*cc4c26d4SRob Clark return ((val) << A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 5513*cc4c26d4SRob Clark } 5514*cc4c26d4SRob Clark 5515*cc4c26d4SRob Clark #define REG_A6XX_SP_GS_PVT_MEM_ADDR 0x0000a890 5516*cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_ADDR__MASK 0xffffffff 5517*cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_ADDR__SHIFT 0 5518*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_PVT_MEM_ADDR(uint32_t val) 5519*cc4c26d4SRob Clark { 5520*cc4c26d4SRob Clark return ((val) << A6XX_SP_GS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_GS_PVT_MEM_ADDR__MASK; 5521*cc4c26d4SRob Clark } 5522*cc4c26d4SRob Clark 5523*cc4c26d4SRob Clark #define REG_A6XX_SP_GS_PVT_MEM_SIZE 0x0000a892 5524*cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 5525*cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 5526*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 5527*cc4c26d4SRob Clark { 5528*cc4c26d4SRob Clark return ((val >> 12) << A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 5529*cc4c26d4SRob Clark } 5530*cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 55312d756322SRob Clark 55322d756322SRob Clark #define REG_A6XX_SP_GS_TEX_COUNT 0x0000a893 55332d756322SRob Clark 55342d756322SRob Clark #define REG_A6XX_SP_GS_CONFIG 0x0000a894 5535c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_BINDLESS_TEX 0x00000001 5536c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_BINDLESS_SAMP 0x00000002 5537c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_BINDLESS_IBO 0x00000004 5538c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_BINDLESS_UBO 0x00000008 55392d756322SRob Clark #define A6XX_SP_GS_CONFIG_ENABLED 0x00000100 55402d756322SRob Clark #define A6XX_SP_GS_CONFIG_NTEX__MASK 0x0001fe00 55412d756322SRob Clark #define A6XX_SP_GS_CONFIG_NTEX__SHIFT 9 55422d756322SRob Clark static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val) 55432d756322SRob Clark { 55442d756322SRob Clark return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK; 55452d756322SRob Clark } 5546c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_NSAMP__MASK 0x003e0000 55472d756322SRob Clark #define A6XX_SP_GS_CONFIG_NSAMP__SHIFT 17 55482d756322SRob Clark static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val) 55492d756322SRob Clark { 55502d756322SRob Clark return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK; 55512d756322SRob Clark } 5552*cc4c26d4SRob Clark #define A6XX_SP_GS_CONFIG_NIBO__MASK 0x1fc00000 5553c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_NIBO__SHIFT 22 5554c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val) 5555c28c82e9SRob Clark { 5556c28c82e9SRob Clark return ((val) << A6XX_SP_GS_CONFIG_NIBO__SHIFT) & A6XX_SP_GS_CONFIG_NIBO__MASK; 5557c28c82e9SRob Clark } 55582d756322SRob Clark 55592d756322SRob Clark #define REG_A6XX_SP_GS_INSTRLEN 0x0000a895 55602d756322SRob Clark 5561*cc4c26d4SRob Clark #define REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET 0x0000a896 5562*cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff 5563*cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0 5564*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET(uint32_t val) 5565*cc4c26d4SRob Clark { 5566*cc4c26d4SRob Clark return ((val >> 11) << A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__MASK; 5567*cc4c26d4SRob Clark } 55682d756322SRob Clark 5569*cc4c26d4SRob Clark #define REG_A6XX_SP_VS_TEX_SAMP 0x0000a8a0 5570*cc4c26d4SRob Clark #define A6XX_SP_VS_TEX_SAMP__MASK 0xffffffff 5571*cc4c26d4SRob Clark #define A6XX_SP_VS_TEX_SAMP__SHIFT 0 5572*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_TEX_SAMP(uint32_t val) 5573*cc4c26d4SRob Clark { 5574*cc4c26d4SRob Clark return ((val) << A6XX_SP_VS_TEX_SAMP__SHIFT) & A6XX_SP_VS_TEX_SAMP__MASK; 5575*cc4c26d4SRob Clark } 55762d756322SRob Clark 5577*cc4c26d4SRob Clark #define REG_A6XX_SP_HS_TEX_SAMP 0x0000a8a2 5578*cc4c26d4SRob Clark #define A6XX_SP_HS_TEX_SAMP__MASK 0xffffffff 5579*cc4c26d4SRob Clark #define A6XX_SP_HS_TEX_SAMP__SHIFT 0 5580*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_TEX_SAMP(uint32_t val) 5581*cc4c26d4SRob Clark { 5582*cc4c26d4SRob Clark return ((val) << A6XX_SP_HS_TEX_SAMP__SHIFT) & A6XX_SP_HS_TEX_SAMP__MASK; 5583*cc4c26d4SRob Clark } 55842d756322SRob Clark 5585*cc4c26d4SRob Clark #define REG_A6XX_SP_DS_TEX_SAMP 0x0000a8a4 5586*cc4c26d4SRob Clark #define A6XX_SP_DS_TEX_SAMP__MASK 0xffffffff 5587*cc4c26d4SRob Clark #define A6XX_SP_DS_TEX_SAMP__SHIFT 0 5588*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_TEX_SAMP(uint32_t val) 5589*cc4c26d4SRob Clark { 5590*cc4c26d4SRob Clark return ((val) << A6XX_SP_DS_TEX_SAMP__SHIFT) & A6XX_SP_DS_TEX_SAMP__MASK; 5591*cc4c26d4SRob Clark } 55922d756322SRob Clark 5593*cc4c26d4SRob Clark #define REG_A6XX_SP_GS_TEX_SAMP 0x0000a8a6 5594*cc4c26d4SRob Clark #define A6XX_SP_GS_TEX_SAMP__MASK 0xffffffff 5595*cc4c26d4SRob Clark #define A6XX_SP_GS_TEX_SAMP__SHIFT 0 5596*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_TEX_SAMP(uint32_t val) 5597*cc4c26d4SRob Clark { 5598*cc4c26d4SRob Clark return ((val) << A6XX_SP_GS_TEX_SAMP__SHIFT) & A6XX_SP_GS_TEX_SAMP__MASK; 5599*cc4c26d4SRob Clark } 56002d756322SRob Clark 5601*cc4c26d4SRob Clark #define REG_A6XX_SP_VS_TEX_CONST 0x0000a8a8 5602*cc4c26d4SRob Clark #define A6XX_SP_VS_TEX_CONST__MASK 0xffffffff 5603*cc4c26d4SRob Clark #define A6XX_SP_VS_TEX_CONST__SHIFT 0 5604*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_TEX_CONST(uint32_t val) 5605*cc4c26d4SRob Clark { 5606*cc4c26d4SRob Clark return ((val) << A6XX_SP_VS_TEX_CONST__SHIFT) & A6XX_SP_VS_TEX_CONST__MASK; 5607*cc4c26d4SRob Clark } 56082d756322SRob Clark 5609*cc4c26d4SRob Clark #define REG_A6XX_SP_HS_TEX_CONST 0x0000a8aa 5610*cc4c26d4SRob Clark #define A6XX_SP_HS_TEX_CONST__MASK 0xffffffff 5611*cc4c26d4SRob Clark #define A6XX_SP_HS_TEX_CONST__SHIFT 0 5612*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_TEX_CONST(uint32_t val) 5613*cc4c26d4SRob Clark { 5614*cc4c26d4SRob Clark return ((val) << A6XX_SP_HS_TEX_CONST__SHIFT) & A6XX_SP_HS_TEX_CONST__MASK; 5615*cc4c26d4SRob Clark } 56162d756322SRob Clark 5617*cc4c26d4SRob Clark #define REG_A6XX_SP_DS_TEX_CONST 0x0000a8ac 5618*cc4c26d4SRob Clark #define A6XX_SP_DS_TEX_CONST__MASK 0xffffffff 5619*cc4c26d4SRob Clark #define A6XX_SP_DS_TEX_CONST__SHIFT 0 5620*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_TEX_CONST(uint32_t val) 5621*cc4c26d4SRob Clark { 5622*cc4c26d4SRob Clark return ((val) << A6XX_SP_DS_TEX_CONST__SHIFT) & A6XX_SP_DS_TEX_CONST__MASK; 5623*cc4c26d4SRob Clark } 56242d756322SRob Clark 5625*cc4c26d4SRob Clark #define REG_A6XX_SP_GS_TEX_CONST 0x0000a8ae 5626*cc4c26d4SRob Clark #define A6XX_SP_GS_TEX_CONST__MASK 0xffffffff 5627*cc4c26d4SRob Clark #define A6XX_SP_GS_TEX_CONST__SHIFT 0 5628*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_TEX_CONST(uint32_t val) 5629*cc4c26d4SRob Clark { 5630*cc4c26d4SRob Clark return ((val) << A6XX_SP_GS_TEX_CONST__SHIFT) & A6XX_SP_GS_TEX_CONST__MASK; 5631*cc4c26d4SRob Clark } 56322d756322SRob Clark 56332d756322SRob Clark #define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980 5634*cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 5635*cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 5636*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) 5637*cc4c26d4SRob Clark { 5638*cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 5639*cc4c26d4SRob Clark } 5640*cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_UNK21 0x00200000 5641*cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000 5642*cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_DIFF_FINE 0x00800000 5643*cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_UNK24 0x01000000 5644*cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_UNK25 0x02000000 5645*cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000 5646*cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_UNK27__MASK 0x18000000 5647*cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_UNK27__SHIFT 27 5648*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_UNK27(uint32_t val) 5649*cc4c26d4SRob Clark { 5650*cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_UNK27__SHIFT) & A6XX_SP_FS_CTRL_REG0_UNK27__MASK; 5651*cc4c26d4SRob Clark } 5652*cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000 5653*cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 5654*cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 5655*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 5656*cc4c26d4SRob Clark { 5657*cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK; 5658*cc4c26d4SRob Clark } 56592d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 56602d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 56612d756322SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 56622d756322SRob Clark { 56632d756322SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 56642d756322SRob Clark } 56652d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 56662d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 56672d756322SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 56682d756322SRob Clark { 56692d756322SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 56702d756322SRob Clark } 5671*cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_UNK13 0x00002000 56722d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 56732d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 14 56742d756322SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) 56752d756322SRob Clark { 56762d756322SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK; 56772d756322SRob Clark } 56782d756322SRob Clark 5679c28c82e9SRob Clark #define REG_A6XX_SP_FS_BRANCH_COND 0x0000a981 5680c28c82e9SRob Clark 5681*cc4c26d4SRob Clark #define REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET 0x0000a982 5682a69c5ed2SRob Clark 5683*cc4c26d4SRob Clark #define REG_A6XX_SP_FS_OBJ_START 0x0000a983 5684*cc4c26d4SRob Clark #define A6XX_SP_FS_OBJ_START__MASK 0xffffffff 5685*cc4c26d4SRob Clark #define A6XX_SP_FS_OBJ_START__SHIFT 0 5686*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_OBJ_START(uint32_t val) 5687*cc4c26d4SRob Clark { 5688*cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_OBJ_START__SHIFT) & A6XX_SP_FS_OBJ_START__MASK; 5689*cc4c26d4SRob Clark } 56902d756322SRob Clark 5691*cc4c26d4SRob Clark #define REG_A6XX_SP_FS_PVT_MEM_PARAM 0x0000a985 5692*cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 5693*cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 5694*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 5695*cc4c26d4SRob Clark { 5696*cc4c26d4SRob Clark return ((val >> 9) << A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 5697*cc4c26d4SRob Clark } 5698*cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 5699*cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 5700*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 5701*cc4c26d4SRob Clark { 5702*cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 5703*cc4c26d4SRob Clark } 5704*cc4c26d4SRob Clark 5705*cc4c26d4SRob Clark #define REG_A6XX_SP_FS_PVT_MEM_ADDR 0x0000a986 5706*cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_ADDR__MASK 0xffffffff 5707*cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_ADDR__SHIFT 0 5708*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_PVT_MEM_ADDR(uint32_t val) 5709*cc4c26d4SRob Clark { 5710*cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_FS_PVT_MEM_ADDR__MASK; 5711*cc4c26d4SRob Clark } 5712*cc4c26d4SRob Clark 5713*cc4c26d4SRob Clark #define REG_A6XX_SP_FS_PVT_MEM_SIZE 0x0000a988 5714*cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 5715*cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 5716*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 5717*cc4c26d4SRob Clark { 5718*cc4c26d4SRob Clark return ((val >> 12) << A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 5719*cc4c26d4SRob Clark } 5720*cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 57212d756322SRob Clark 57222d756322SRob Clark #define REG_A6XX_SP_BLEND_CNTL 0x0000a989 5723*cc4c26d4SRob Clark #define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff 5724*cc4c26d4SRob Clark #define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 5725*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val) 5726*cc4c26d4SRob Clark { 5727*cc4c26d4SRob Clark return ((val) << A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK; 5728*cc4c26d4SRob Clark } 57292d756322SRob Clark #define A6XX_SP_BLEND_CNTL_UNK8 0x00000100 5730c28c82e9SRob Clark #define A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200 5731ccdf7e28SRob Clark #define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 57322d756322SRob Clark 57332d756322SRob Clark #define REG_A6XX_SP_SRGB_CNTL 0x0000a98a 57342d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT0 0x00000001 57352d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT1 0x00000002 57362d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT2 0x00000004 57372d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT3 0x00000008 57382d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT4 0x00000010 57392d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT5 0x00000020 57402d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT6 0x00000040 57412d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT7 0x00000080 57422d756322SRob Clark 57432d756322SRob Clark #define REG_A6XX_SP_FS_RENDER_COMPONENTS 0x0000a98b 57442d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK 0x0000000f 57452d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT 0 57462d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val) 57472d756322SRob Clark { 57482d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK; 57492d756322SRob Clark } 57502d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK 0x000000f0 57512d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT 4 57522d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val) 57532d756322SRob Clark { 57542d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK; 57552d756322SRob Clark } 57562d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK 0x00000f00 57572d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT 8 57582d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val) 57592d756322SRob Clark { 57602d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK; 57612d756322SRob Clark } 57622d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK 0x0000f000 57632d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT 12 57642d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val) 57652d756322SRob Clark { 57662d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK; 57672d756322SRob Clark } 57682d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK 0x000f0000 57692d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT 16 57702d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val) 57712d756322SRob Clark { 57722d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK; 57732d756322SRob Clark } 57742d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK 0x00f00000 57752d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT 20 57762d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val) 57772d756322SRob Clark { 57782d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK; 57792d756322SRob Clark } 57802d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK 0x0f000000 57812d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT 24 57822d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val) 57832d756322SRob Clark { 57842d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK; 57852d756322SRob Clark } 57862d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK 0xf0000000 57872d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT 28 57882d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val) 57892d756322SRob Clark { 57902d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK; 57912d756322SRob Clark } 57922d756322SRob Clark 57932d756322SRob Clark #define REG_A6XX_SP_FS_OUTPUT_CNTL0 0x0000a98c 5794c28c82e9SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001 57952d756322SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK 0x0000ff00 57962d756322SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT 8 57972d756322SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val) 57982d756322SRob Clark { 57992d756322SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK; 58002d756322SRob Clark } 5801c28c82e9SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK 0x00ff0000 5802c28c82e9SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT 16 5803c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(uint32_t val) 5804c28c82e9SRob Clark { 5805c28c82e9SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK; 5806c28c82e9SRob Clark } 5807c28c82e9SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK 0xff000000 5808c28c82e9SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT 24 5809c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(uint32_t val) 5810c28c82e9SRob Clark { 5811c28c82e9SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK; 5812c28c82e9SRob Clark } 58132d756322SRob Clark 58142d756322SRob Clark #define REG_A6XX_SP_FS_OUTPUT_CNTL1 0x0000a98d 58152d756322SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f 58162d756322SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT 0 58172d756322SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val) 58182d756322SRob Clark { 58192d756322SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK; 58202d756322SRob Clark } 58212d756322SRob Clark 5822*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; } 5823*cc4c26d4SRob Clark 5824*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; } 5825*cc4c26d4SRob Clark #define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff 5826*cc4c26d4SRob Clark #define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0 5827*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) 5828*cc4c26d4SRob Clark { 5829*cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK; 5830*cc4c26d4SRob Clark } 5831*cc4c26d4SRob Clark #define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100 5832*cc4c26d4SRob Clark 58332d756322SRob Clark static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; } 58342d756322SRob Clark 58352d756322SRob Clark static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; } 58362d756322SRob Clark #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff 58372d756322SRob Clark #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0 5838c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val) 58392d756322SRob Clark { 58402d756322SRob Clark return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK; 58412d756322SRob Clark } 58422d756322SRob Clark #define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100 58432d756322SRob Clark #define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200 5844*cc4c26d4SRob Clark #define A6XX_SP_FS_MRT_REG_UNK10 0x00000400 5845a69c5ed2SRob Clark 5846c28c82e9SRob Clark #define REG_A6XX_SP_FS_PREFETCH_CNTL 0x0000a99e 5847c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK 0x00000007 5848c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT 0 5849c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_COUNT(uint32_t val) 5850c28c82e9SRob Clark { 5851c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK; 5852c28c82e9SRob Clark } 5853c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_UNK3 0x00000008 5854c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK 0x00000ff0 5855c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT 4 5856c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK4(uint32_t val) 5857c28c82e9SRob Clark { 5858c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK; 5859c28c82e9SRob Clark } 5860*cc4c26d4SRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_UNK12__MASK 0x00007000 5861*cc4c26d4SRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_UNK12__SHIFT 12 5862*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK12(uint32_t val) 5863*cc4c26d4SRob Clark { 5864*cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK12__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK12__MASK; 5865*cc4c26d4SRob Clark } 5866c28c82e9SRob Clark 5867c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_FS_PREFETCH(uint32_t i0) { return 0x0000a99f + 0x1*i0; } 5868c28c82e9SRob Clark 5869c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; } 5870c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_SRC__MASK 0x0000007f 5871c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT 0 5872c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val) 5873c28c82e9SRob Clark { 5874c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SRC__MASK; 5875c28c82e9SRob Clark } 5876c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK 0x00000780 5877c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT 7 5878c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val) 5879c28c82e9SRob Clark { 5880c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK; 5881c28c82e9SRob Clark } 5882c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK 0x0000f800 5883c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT 11 5884c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val) 5885c28c82e9SRob Clark { 5886c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK; 5887c28c82e9SRob Clark } 5888c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_DST__MASK 0x003f0000 5889c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT 16 5890c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_DST(uint32_t val) 5891c28c82e9SRob Clark { 5892c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_DST__MASK; 5893c28c82e9SRob Clark } 5894c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK 0x03c00000 5895c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT 22 5896c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val) 5897c28c82e9SRob Clark { 5898c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK; 5899c28c82e9SRob Clark } 5900c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_HALF 0x04000000 5901c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_CMD__MASK 0xf8000000 5902c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT 27 5903c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_CMD(uint32_t val) 5904c28c82e9SRob Clark { 5905c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_CMD__MASK; 5906c28c82e9SRob Clark } 5907c28c82e9SRob Clark 5908c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; } 5909c28c82e9SRob Clark 5910c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; } 5911*cc4c26d4SRob Clark #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK 0x0000ffff 5912c28c82e9SRob Clark #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT 0 5913c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val) 5914c28c82e9SRob Clark { 5915c28c82e9SRob Clark return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK; 5916c28c82e9SRob Clark } 5917*cc4c26d4SRob Clark #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK 0xffff0000 5918c28c82e9SRob Clark #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT 16 5919c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val) 5920c28c82e9SRob Clark { 5921c28c82e9SRob Clark return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK; 5922c28c82e9SRob Clark } 59232d756322SRob Clark 59242d756322SRob Clark #define REG_A6XX_SP_FS_TEX_COUNT 0x0000a9a7 59252d756322SRob Clark 59262d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8 59272d756322SRob Clark 5928*cc4c26d4SRob Clark #define REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET 0x0000a9a9 5929*cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff 5930*cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0 5931*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET(uint32_t val) 5932c28c82e9SRob Clark { 5933*cc4c26d4SRob Clark return ((val >> 11) << A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__MASK; 5934c28c82e9SRob Clark } 5935c28c82e9SRob Clark 59362d756322SRob Clark #define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0 5937*cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000 5938*cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20 5939*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) 5940*cc4c26d4SRob Clark { 5941*cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK; 5942*cc4c26d4SRob Clark } 5943*cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_UNK21 0x00200000 5944*cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_UNK22 0x00400000 5945*cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_SEPARATEPROLOG 0x00800000 5946*cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000 5947*cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK 0x00000001 5948*cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT 0 5949*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 5950*cc4c26d4SRob Clark { 5951*cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK; 5952*cc4c26d4SRob Clark } 59532d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 59542d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 59552d756322SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 59562d756322SRob Clark { 59572d756322SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 59582d756322SRob Clark } 59592d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 59602d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 59612d756322SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 59622d756322SRob Clark { 59632d756322SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 59642d756322SRob Clark } 5965*cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_UNK13 0x00002000 59662d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 59672d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 14 59682d756322SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val) 59692d756322SRob Clark { 59702d756322SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK; 59712d756322SRob Clark } 5972*cc4c26d4SRob Clark 5973*cc4c26d4SRob Clark #define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1 5974*cc4c26d4SRob Clark #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK 0x0000001f 5975*cc4c26d4SRob Clark #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT 0 5976*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(uint32_t val) 59772d756322SRob Clark { 5978*cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK; 59792d756322SRob Clark } 5980*cc4c26d4SRob Clark #define A6XX_SP_CS_UNKNOWN_A9B1_UNK5 0x00000020 5981*cc4c26d4SRob Clark #define A6XX_SP_CS_UNKNOWN_A9B1_UNK6 0x00000040 59822d756322SRob Clark 5983*cc4c26d4SRob Clark #define REG_A6XX_SP_CS_BRANCH_COND 0x0000a9b2 59842d756322SRob Clark 5985*cc4c26d4SRob Clark #define REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET 0x0000a9b3 5986*cc4c26d4SRob Clark 5987*cc4c26d4SRob Clark #define REG_A6XX_SP_CS_OBJ_START 0x0000a9b4 5988*cc4c26d4SRob Clark #define A6XX_SP_CS_OBJ_START__MASK 0xffffffff 5989*cc4c26d4SRob Clark #define A6XX_SP_CS_OBJ_START__SHIFT 0 5990*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_OBJ_START(uint32_t val) 5991*cc4c26d4SRob Clark { 5992*cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_OBJ_START__SHIFT) & A6XX_SP_CS_OBJ_START__MASK; 5993*cc4c26d4SRob Clark } 5994*cc4c26d4SRob Clark 5995*cc4c26d4SRob Clark #define REG_A6XX_SP_CS_PVT_MEM_PARAM 0x0000a9b6 5996*cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 5997*cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 5998*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 5999*cc4c26d4SRob Clark { 6000*cc4c26d4SRob Clark return ((val >> 9) << A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 6001*cc4c26d4SRob Clark } 6002*cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 6003*cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 6004*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 6005*cc4c26d4SRob Clark { 6006*cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 6007*cc4c26d4SRob Clark } 6008*cc4c26d4SRob Clark 6009*cc4c26d4SRob Clark #define REG_A6XX_SP_CS_PVT_MEM_ADDR 0x0000a9b7 6010*cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_ADDR__MASK 0xffffffff 6011*cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_ADDR__SHIFT 0 6012*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_PVT_MEM_ADDR(uint32_t val) 6013*cc4c26d4SRob Clark { 6014*cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_CS_PVT_MEM_ADDR__MASK; 6015*cc4c26d4SRob Clark } 6016*cc4c26d4SRob Clark 6017*cc4c26d4SRob Clark #define REG_A6XX_SP_CS_PVT_MEM_SIZE 0x0000a9b9 6018*cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 6019*cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 6020*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 6021*cc4c26d4SRob Clark { 6022*cc4c26d4SRob Clark return ((val >> 12) << A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 6023*cc4c26d4SRob Clark } 6024*cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 6025*cc4c26d4SRob Clark 6026*cc4c26d4SRob Clark #define REG_A6XX_SP_CS_TEX_COUNT 0x0000a9ba 60272d756322SRob Clark 6028c28c82e9SRob Clark #define REG_A6XX_SP_CS_CONFIG 0x0000a9bb 6029c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_BINDLESS_TEX 0x00000001 6030c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_BINDLESS_SAMP 0x00000002 6031c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_BINDLESS_IBO 0x00000004 6032c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_BINDLESS_UBO 0x00000008 6033c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_ENABLED 0x00000100 6034c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_NTEX__MASK 0x0001fe00 6035c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_NTEX__SHIFT 9 6036c28c82e9SRob Clark static inline uint32_t A6XX_SP_CS_CONFIG_NTEX(uint32_t val) 6037c28c82e9SRob Clark { 6038c28c82e9SRob Clark return ((val) << A6XX_SP_CS_CONFIG_NTEX__SHIFT) & A6XX_SP_CS_CONFIG_NTEX__MASK; 6039c28c82e9SRob Clark } 6040c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_NSAMP__MASK 0x003e0000 6041c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_NSAMP__SHIFT 17 6042c28c82e9SRob Clark static inline uint32_t A6XX_SP_CS_CONFIG_NSAMP(uint32_t val) 6043c28c82e9SRob Clark { 6044c28c82e9SRob Clark return ((val) << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK; 6045c28c82e9SRob Clark } 6046*cc4c26d4SRob Clark #define A6XX_SP_CS_CONFIG_NIBO__MASK 0x1fc00000 6047c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_NIBO__SHIFT 22 6048c28c82e9SRob Clark static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val) 6049c28c82e9SRob Clark { 6050c28c82e9SRob Clark return ((val) << A6XX_SP_CS_CONFIG_NIBO__SHIFT) & A6XX_SP_CS_CONFIG_NIBO__MASK; 6051c28c82e9SRob Clark } 6052c28c82e9SRob Clark 60532d756322SRob Clark #define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc 60542d756322SRob Clark 6055*cc4c26d4SRob Clark #define REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET 0x0000a9bd 6056*cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff 6057*cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0 6058*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET(uint32_t val) 6059*cc4c26d4SRob Clark { 6060*cc4c26d4SRob Clark return ((val >> 11) << A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__MASK; 6061*cc4c26d4SRob Clark } 6062c28c82e9SRob Clark 6063*cc4c26d4SRob Clark #define REG_A6XX_SP_FS_TEX_SAMP 0x0000a9e0 6064*cc4c26d4SRob Clark #define A6XX_SP_FS_TEX_SAMP__MASK 0xffffffff 6065*cc4c26d4SRob Clark #define A6XX_SP_FS_TEX_SAMP__SHIFT 0 6066*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_TEX_SAMP(uint32_t val) 6067*cc4c26d4SRob Clark { 6068*cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_TEX_SAMP__SHIFT) & A6XX_SP_FS_TEX_SAMP__MASK; 6069*cc4c26d4SRob Clark } 6070*cc4c26d4SRob Clark 6071*cc4c26d4SRob Clark #define REG_A6XX_SP_CS_TEX_SAMP 0x0000a9e2 6072*cc4c26d4SRob Clark #define A6XX_SP_CS_TEX_SAMP__MASK 0xffffffff 6073*cc4c26d4SRob Clark #define A6XX_SP_CS_TEX_SAMP__SHIFT 0 6074*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_TEX_SAMP(uint32_t val) 6075*cc4c26d4SRob Clark { 6076*cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_TEX_SAMP__SHIFT) & A6XX_SP_CS_TEX_SAMP__MASK; 6077*cc4c26d4SRob Clark } 6078*cc4c26d4SRob Clark 6079*cc4c26d4SRob Clark #define REG_A6XX_SP_FS_TEX_CONST 0x0000a9e4 6080*cc4c26d4SRob Clark #define A6XX_SP_FS_TEX_CONST__MASK 0xffffffff 6081*cc4c26d4SRob Clark #define A6XX_SP_FS_TEX_CONST__SHIFT 0 6082*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_TEX_CONST(uint32_t val) 6083*cc4c26d4SRob Clark { 6084*cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_TEX_CONST__SHIFT) & A6XX_SP_FS_TEX_CONST__MASK; 6085*cc4c26d4SRob Clark } 6086*cc4c26d4SRob Clark 6087*cc4c26d4SRob Clark #define REG_A6XX_SP_CS_TEX_CONST 0x0000a9e6 6088*cc4c26d4SRob Clark #define A6XX_SP_CS_TEX_CONST__MASK 0xffffffff 6089*cc4c26d4SRob Clark #define A6XX_SP_CS_TEX_CONST__SHIFT 0 6090*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_TEX_CONST(uint32_t val) 6091*cc4c26d4SRob Clark { 6092*cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_TEX_CONST__SHIFT) & A6XX_SP_CS_TEX_CONST__MASK; 6093*cc4c26d4SRob Clark } 6094*cc4c26d4SRob Clark 6095*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; } 6096*cc4c26d4SRob Clark 6097*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; } 6098*cc4c26d4SRob Clark 6099*cc4c26d4SRob Clark #define REG_A6XX_SP_CS_IBO 0x0000a9f2 6100*cc4c26d4SRob Clark #define A6XX_SP_CS_IBO__MASK 0xffffffff 6101*cc4c26d4SRob Clark #define A6XX_SP_CS_IBO__SHIFT 0 6102*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_IBO(uint32_t val) 6103*cc4c26d4SRob Clark { 6104*cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_IBO__SHIFT) & A6XX_SP_CS_IBO__MASK; 6105*cc4c26d4SRob Clark } 6106c28c82e9SRob Clark 6107c28c82e9SRob Clark #define REG_A6XX_SP_CS_IBO_COUNT 0x0000aa00 6108c28c82e9SRob Clark 6109*cc4c26d4SRob Clark #define REG_A6XX_SP_MODE_CONTROL 0x0000ab00 6110*cc4c26d4SRob Clark #define A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE 0x00000001 6111*cc4c26d4SRob Clark #define A6XX_SP_MODE_CONTROL_UNK1 0x00000002 6112*cc4c26d4SRob Clark #define A6XX_SP_MODE_CONTROL_UNK2 0x00000004 6113*cc4c26d4SRob Clark #define A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE 0x00000008 61142d756322SRob Clark 61152d756322SRob Clark #define REG_A6XX_SP_FS_CONFIG 0x0000ab04 6116c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_BINDLESS_TEX 0x00000001 6117c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_BINDLESS_SAMP 0x00000002 6118c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_BINDLESS_IBO 0x00000004 6119c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_BINDLESS_UBO 0x00000008 61202d756322SRob Clark #define A6XX_SP_FS_CONFIG_ENABLED 0x00000100 61212d756322SRob Clark #define A6XX_SP_FS_CONFIG_NTEX__MASK 0x0001fe00 61222d756322SRob Clark #define A6XX_SP_FS_CONFIG_NTEX__SHIFT 9 61232d756322SRob Clark static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val) 61242d756322SRob Clark { 61252d756322SRob Clark return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK; 61262d756322SRob Clark } 6127c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_NSAMP__MASK 0x003e0000 61282d756322SRob Clark #define A6XX_SP_FS_CONFIG_NSAMP__SHIFT 17 61292d756322SRob Clark static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val) 61302d756322SRob Clark { 61312d756322SRob Clark return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK; 61322d756322SRob Clark } 6133*cc4c26d4SRob Clark #define A6XX_SP_FS_CONFIG_NIBO__MASK 0x1fc00000 6134c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_NIBO__SHIFT 22 6135c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val) 6136c28c82e9SRob Clark { 6137c28c82e9SRob Clark return ((val) << A6XX_SP_FS_CONFIG_NIBO__SHIFT) & A6XX_SP_FS_CONFIG_NIBO__MASK; 6138c28c82e9SRob Clark } 61392d756322SRob Clark 61402d756322SRob Clark #define REG_A6XX_SP_FS_INSTRLEN 0x0000ab05 61412d756322SRob Clark 6142c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_BINDLESS_BASE(uint32_t i0) { return 0x0000ab10 + 0x2*i0; } 6143a69c5ed2SRob Clark 6144c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; } 6145c28c82e9SRob Clark 6146*cc4c26d4SRob Clark #define REG_A6XX_SP_IBO 0x0000ab1a 6147*cc4c26d4SRob Clark #define A6XX_SP_IBO__MASK 0xffffffff 6148*cc4c26d4SRob Clark #define A6XX_SP_IBO__SHIFT 0 6149*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_IBO(uint32_t val) 6150*cc4c26d4SRob Clark { 6151*cc4c26d4SRob Clark return ((val) << A6XX_SP_IBO__SHIFT) & A6XX_SP_IBO__MASK; 6152*cc4c26d4SRob Clark } 6153c28c82e9SRob Clark 6154c28c82e9SRob Clark #define REG_A6XX_SP_IBO_COUNT 0x0000ab20 6155c28c82e9SRob Clark 6156c28c82e9SRob Clark #define REG_A6XX_SP_2D_DST_FORMAT 0x0000acc0 6157c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_NORM 0x00000001 6158c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_SINT 0x00000002 6159c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_UINT 0x00000004 6160c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK 0x000007f8 6161c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT 3 6162c28c82e9SRob Clark static inline uint32_t A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val) 6163c28c82e9SRob Clark { 6164c28c82e9SRob Clark return ((val) << A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT) & A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK; 6165c28c82e9SRob Clark } 6166c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_SRGB 0x00000800 6167c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_MASK__MASK 0x0000f000 6168c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_MASK__SHIFT 12 6169c28c82e9SRob Clark static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val) 6170c28c82e9SRob Clark { 6171c28c82e9SRob Clark return ((val) << A6XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A6XX_SP_2D_DST_FORMAT_MASK__MASK; 6172c28c82e9SRob Clark } 6173ccdf7e28SRob Clark 61742d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_AE00 0x0000ae00 61752d756322SRob Clark 6176*cc4c26d4SRob Clark #define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01 6177*cc4c26d4SRob Clark 6178*cc4c26d4SRob Clark #define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02 6179*cc4c26d4SRob Clark 6180a69c5ed2SRob Clark #define REG_A6XX_SP_UNKNOWN_AE03 0x0000ae03 6181a69c5ed2SRob Clark 6182*cc4c26d4SRob Clark #define REG_A6XX_SP_FLOAT_CNTL 0x0000ae04 6183*cc4c26d4SRob Clark #define A6XX_SP_FLOAT_CNTL_F16_NO_INF 0x00000008 61842d756322SRob Clark 6185*cc4c26d4SRob Clark #define REG_A6XX_SP_PERFCTR_ENABLE 0x0000ae0f 6186*cc4c26d4SRob Clark #define A6XX_SP_PERFCTR_ENABLE_VS 0x00000001 6187*cc4c26d4SRob Clark #define A6XX_SP_PERFCTR_ENABLE_HS 0x00000002 6188*cc4c26d4SRob Clark #define A6XX_SP_PERFCTR_ENABLE_DS 0x00000004 6189*cc4c26d4SRob Clark #define A6XX_SP_PERFCTR_ENABLE_GS 0x00000008 6190*cc4c26d4SRob Clark #define A6XX_SP_PERFCTR_ENABLE_FS 0x00000010 6191*cc4c26d4SRob Clark #define A6XX_SP_PERFCTR_ENABLE_CS 0x00000020 6192*cc4c26d4SRob Clark 6193*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae10 + 0x1*i0; } 61942d756322SRob Clark 6195c28c82e9SRob Clark #define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR 0x0000b180 6196*cc4c26d4SRob Clark #define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff 6197*cc4c26d4SRob Clark #define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0 6198*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(uint32_t val) 6199*cc4c26d4SRob Clark { 6200*cc4c26d4SRob Clark return ((val) << A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK; 6201*cc4c26d4SRob Clark } 6202c28c82e9SRob Clark 62032d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_B182 0x0000b182 62042d756322SRob Clark 6205a69c5ed2SRob Clark #define REG_A6XX_SP_UNKNOWN_B183 0x0000b183 6206a69c5ed2SRob Clark 6207*cc4c26d4SRob Clark #define REG_A6XX_SP_UNKNOWN_B190 0x0000b190 6208*cc4c26d4SRob Clark 6209*cc4c26d4SRob Clark #define REG_A6XX_SP_UNKNOWN_B191 0x0000b191 6210*cc4c26d4SRob Clark 62112d756322SRob Clark #define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300 62122d756322SRob Clark #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 62132d756322SRob Clark #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 62142d756322SRob Clark static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 62152d756322SRob Clark { 62162d756322SRob Clark return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK; 62172d756322SRob Clark } 6218*cc4c26d4SRob Clark #define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK 0x0000000c 6219*cc4c26d4SRob Clark #define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT 2 6220*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_UNK2(uint32_t val) 6221*cc4c26d4SRob Clark { 6222*cc4c26d4SRob Clark return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK; 6223*cc4c26d4SRob Clark } 62242d756322SRob Clark 62252d756322SRob Clark #define REG_A6XX_SP_TP_DEST_MSAA_CNTL 0x0000b301 62262d756322SRob Clark #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 62272d756322SRob Clark #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 62282d756322SRob Clark static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 62292d756322SRob Clark { 62302d756322SRob Clark return ((val) << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK; 62312d756322SRob Clark } 62322d756322SRob Clark #define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 62332d756322SRob Clark 6234c28c82e9SRob Clark #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR 0x0000b302 6235*cc4c26d4SRob Clark #define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff 6236*cc4c26d4SRob Clark #define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0 6237*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(uint32_t val) 6238*cc4c26d4SRob Clark { 6239*cc4c26d4SRob Clark return ((val) << A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK; 6240*cc4c26d4SRob Clark } 62412d756322SRob Clark 6242c28c82e9SRob Clark #define REG_A6XX_SP_TP_SAMPLE_CONFIG 0x0000b304 6243c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_CONFIG_UNK0 0x00000001 6244c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002 6245c28c82e9SRob Clark 6246c28c82e9SRob Clark #define REG_A6XX_SP_TP_SAMPLE_LOCATION_0 0x0000b305 6247c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f 6248c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 6249c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) 6250c28c82e9SRob Clark { 6251c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; 6252c28c82e9SRob Clark } 6253c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 6254c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 6255c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) 6256c28c82e9SRob Clark { 6257c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; 6258c28c82e9SRob Clark } 6259c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 6260c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 6261c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) 6262c28c82e9SRob Clark { 6263c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; 6264c28c82e9SRob Clark } 6265c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 6266c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 6267c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) 6268c28c82e9SRob Clark { 6269c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; 6270c28c82e9SRob Clark } 6271c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 6272c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 6273c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) 6274c28c82e9SRob Clark { 6275c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; 6276c28c82e9SRob Clark } 6277c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 6278c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 6279c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) 6280c28c82e9SRob Clark { 6281c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; 6282c28c82e9SRob Clark } 6283c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 6284c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 6285c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) 6286c28c82e9SRob Clark { 6287c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; 6288c28c82e9SRob Clark } 6289c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 6290c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 6291c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) 6292c28c82e9SRob Clark { 6293c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; 6294c28c82e9SRob Clark } 6295c28c82e9SRob Clark 6296c28c82e9SRob Clark #define REG_A6XX_SP_TP_SAMPLE_LOCATION_1 0x0000b306 6297c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f 6298c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 6299c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) 6300c28c82e9SRob Clark { 6301c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; 6302c28c82e9SRob Clark } 6303c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 6304c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 6305c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) 6306c28c82e9SRob Clark { 6307c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; 6308c28c82e9SRob Clark } 6309c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 6310c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 6311c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) 6312c28c82e9SRob Clark { 6313c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; 6314c28c82e9SRob Clark } 6315c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 6316c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 6317c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) 6318c28c82e9SRob Clark { 6319c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; 6320c28c82e9SRob Clark } 6321c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 6322c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 6323c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) 6324c28c82e9SRob Clark { 6325c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; 6326c28c82e9SRob Clark } 6327c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 6328c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 6329c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) 6330c28c82e9SRob Clark { 6331c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; 6332c28c82e9SRob Clark } 6333c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 6334c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 6335c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) 6336c28c82e9SRob Clark { 6337c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; 6338c28c82e9SRob Clark } 6339c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 6340c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 6341c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) 6342c28c82e9SRob Clark { 6343c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; 6344c28c82e9SRob Clark } 63452d756322SRob Clark 6346*cc4c26d4SRob Clark #define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307 6347*cc4c26d4SRob Clark #define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00003fff 6348*cc4c26d4SRob Clark #define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0 6349*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val) 6350*cc4c26d4SRob Clark { 6351*cc4c26d4SRob Clark return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK; 6352*cc4c26d4SRob Clark } 6353*cc4c26d4SRob Clark #define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x3fff0000 6354*cc4c26d4SRob Clark #define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16 6355*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val) 6356*cc4c26d4SRob Clark { 6357*cc4c26d4SRob Clark return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK; 6358*cc4c26d4SRob Clark } 6359*cc4c26d4SRob Clark 6360a69c5ed2SRob Clark #define REG_A6XX_SP_TP_UNKNOWN_B309 0x0000b309 6361a69c5ed2SRob Clark 63622d756322SRob Clark #define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0 63632d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff 63642d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 6365c28c82e9SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val) 63662d756322SRob Clark { 63672d756322SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK; 63682d756322SRob Clark } 63692d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300 63702d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT 8 63712d756322SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val) 63722d756322SRob Clark { 63732d756322SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK; 63742d756322SRob Clark } 63752d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00 63762d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10 63772d756322SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) 63782d756322SRob Clark { 63792d756322SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK; 63802d756322SRob Clark } 63812d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000 6382c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_SRGB 0x00002000 6383c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK 0x0000c000 6384c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT 14 6385c28c82e9SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val) 6386c28c82e9SRob Clark { 6387c28c82e9SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK; 6388c28c82e9SRob Clark } 6389ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000 6390*cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK17 0x00020000 6391c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE 0x00040000 6392*cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK19 0x00080000 6393c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK20 0x00100000 6394*cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK21 0x00200000 6395c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK22 0x00400000 6396*cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK 0x07800000 6397*cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT 23 6398*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val) 6399*cc4c26d4SRob Clark { 6400*cc4c26d4SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK; 6401*cc4c26d4SRob Clark } 6402*cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK28 0x10000000 6403ccdf7e28SRob Clark 6404ccdf7e28SRob Clark #define REG_A6XX_SP_PS_2D_SRC_SIZE 0x0000b4c1 6405ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff 6406ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT 0 6407ccdf7e28SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val) 6408ccdf7e28SRob Clark { 6409ccdf7e28SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK; 6410ccdf7e28SRob Clark } 6411ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK 0x3fff8000 6412ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT 15 6413ccdf7e28SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val) 6414ccdf7e28SRob Clark { 6415ccdf7e28SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK; 6416ccdf7e28SRob Clark } 64172d756322SRob Clark 6418c28c82e9SRob Clark #define REG_A6XX_SP_PS_2D_SRC 0x0000b4c2 6419*cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC__MASK 0xffffffff 6420*cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC__SHIFT 0 6421*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC(uint32_t val) 6422*cc4c26d4SRob Clark { 6423*cc4c26d4SRob Clark return ((val) << A6XX_SP_PS_2D_SRC__SHIFT) & A6XX_SP_PS_2D_SRC__MASK; 6424*cc4c26d4SRob Clark } 6425c28c82e9SRob Clark 6426ccdf7e28SRob Clark #define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4 6427*cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK 0x000001ff 6428*cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT 0 6429*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val) 6430*cc4c26d4SRob Clark { 6431*cc4c26d4SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK; 6432*cc4c26d4SRob Clark } 6433*cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x00fffe00 6434ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9 6435ccdf7e28SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val) 6436ccdf7e28SRob Clark { 6437ccdf7e28SRob Clark return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK; 6438ccdf7e28SRob Clark } 6439ccdf7e28SRob Clark 6440*cc4c26d4SRob Clark #define REG_A6XX_SP_PS_2D_SRC_PLANE1 0x0000b4c5 6441*cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PLANE1__MASK 0xffffffff 6442*cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PLANE1__SHIFT 0 6443*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE1(uint32_t val) 6444*cc4c26d4SRob Clark { 6445*cc4c26d4SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_PLANE1__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE1__MASK; 6446*cc4c26d4SRob Clark } 64472d756322SRob Clark 6448*cc4c26d4SRob Clark #define REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH 0x0000b4c7 6449*cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK 0x00000fff 6450*cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT 0 6451*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val) 6452*cc4c26d4SRob Clark { 6453*cc4c26d4SRob Clark return ((val >> 6) << A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK; 6454*cc4c26d4SRob Clark } 6455*cc4c26d4SRob Clark 6456*cc4c26d4SRob Clark #define REG_A6XX_SP_PS_2D_SRC_PLANE2 0x0000b4c8 6457*cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PLANE2__MASK 0xffffffff 6458*cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PLANE2__SHIFT 0 6459*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE2(uint32_t val) 6460*cc4c26d4SRob Clark { 6461*cc4c26d4SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_PLANE2__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE2__MASK; 6462*cc4c26d4SRob Clark } 64632d756322SRob Clark 6464c28c82e9SRob Clark #define REG_A6XX_SP_PS_2D_SRC_FLAGS 0x0000b4ca 6465*cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_FLAGS__MASK 0xffffffff 6466*cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_FLAGS__SHIFT 0 6467*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS(uint32_t val) 6468*cc4c26d4SRob Clark { 6469*cc4c26d4SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_FLAGS__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS__MASK; 6470*cc4c26d4SRob Clark } 6471c28c82e9SRob Clark 6472c28c82e9SRob Clark #define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b4cc 6473*cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK 0x000000ff 6474*cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT 0 6475*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val) 6476c28c82e9SRob Clark { 6477*cc4c26d4SRob Clark return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK; 6478c28c82e9SRob Clark } 6479c28c82e9SRob Clark 6480*cc4c26d4SRob Clark #define REG_A6XX_SP_PS_UNKNOWN_B4CD 0x0000b4cd 64812d756322SRob Clark 6482*cc4c26d4SRob Clark #define REG_A6XX_SP_PS_UNKNOWN_B4CE 0x0000b4ce 6483*cc4c26d4SRob Clark 6484*cc4c26d4SRob Clark #define REG_A6XX_SP_PS_UNKNOWN_B4CF 0x0000b4cf 6485*cc4c26d4SRob Clark 6486*cc4c26d4SRob Clark #define REG_A6XX_SP_PS_UNKNOWN_B4D0 0x0000b4d0 6487*cc4c26d4SRob Clark 6488*cc4c26d4SRob Clark #define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1 6489*cc4c26d4SRob Clark #define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00003fff 6490*cc4c26d4SRob Clark #define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0 6491*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val) 6492*cc4c26d4SRob Clark { 6493*cc4c26d4SRob Clark return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK; 6494*cc4c26d4SRob Clark } 6495*cc4c26d4SRob Clark #define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x3fff0000 6496*cc4c26d4SRob Clark #define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16 6497*cc4c26d4SRob Clark static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val) 6498*cc4c26d4SRob Clark { 6499*cc4c26d4SRob Clark return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK; 6500*cc4c26d4SRob Clark } 6501*cc4c26d4SRob Clark 6502*cc4c26d4SRob Clark #define REG_A6XX_TPL1_UNKNOWN_B600 0x0000b600 6503*cc4c26d4SRob Clark 6504*cc4c26d4SRob Clark #define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601 6505*cc4c26d4SRob Clark 6506*cc4c26d4SRob Clark #define REG_A6XX_TPL1_UNKNOWN_B602 0x0000b602 6507*cc4c26d4SRob Clark 6508*cc4c26d4SRob Clark #define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604 6509*cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_MODE 0x00000001 6510*cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006 6511*cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT 1 6512*cc4c26d4SRob Clark static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT(uint32_t val) 6513*cc4c26d4SRob Clark { 6514*cc4c26d4SRob Clark return ((val) << A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK; 6515*cc4c26d4SRob Clark } 6516*cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008 6517*cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000010 6518*cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT 4 6519*cc4c26d4SRob Clark static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT(uint32_t val) 6520*cc4c26d4SRob Clark { 6521*cc4c26d4SRob Clark return ((val) << A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK; 6522*cc4c26d4SRob Clark } 6523*cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK 0x000000c0 6524*cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT 6 6525*cc4c26d4SRob Clark static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UNK6(uint32_t val) 6526*cc4c26d4SRob Clark { 6527*cc4c26d4SRob Clark return ((val) << A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK; 6528*cc4c26d4SRob Clark } 6529*cc4c26d4SRob Clark 6530*cc4c26d4SRob Clark #define REG_A6XX_TPL1_UNKNOWN_B605 0x0000b605 6531*cc4c26d4SRob Clark 6532*cc4c26d4SRob Clark #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608 6533*cc4c26d4SRob Clark 6534*cc4c26d4SRob Clark #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609 6535*cc4c26d4SRob Clark 6536*cc4c26d4SRob Clark #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a 6537*cc4c26d4SRob Clark 6538*cc4c26d4SRob Clark #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b 6539*cc4c26d4SRob Clark 6540*cc4c26d4SRob Clark #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c 6541*cc4c26d4SRob Clark 6542*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_TPL1_PERFCTR_TP_SEL(uint32_t i0) { return 0x0000b610 + 0x1*i0; } 65432d756322SRob Clark 65442d756322SRob Clark #define REG_A6XX_HLSQ_VS_CNTL 0x0000b800 65452d756322SRob Clark #define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff 65462d756322SRob Clark #define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0 65472d756322SRob Clark static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val) 65482d756322SRob Clark { 65492d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK; 65502d756322SRob Clark } 6551c28c82e9SRob Clark #define A6XX_HLSQ_VS_CNTL_ENABLED 0x00000100 65522d756322SRob Clark 65532d756322SRob Clark #define REG_A6XX_HLSQ_HS_CNTL 0x0000b801 65542d756322SRob Clark #define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff 65552d756322SRob Clark #define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0 65562d756322SRob Clark static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val) 65572d756322SRob Clark { 65582d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK; 65592d756322SRob Clark } 6560c28c82e9SRob Clark #define A6XX_HLSQ_HS_CNTL_ENABLED 0x00000100 65612d756322SRob Clark 65622d756322SRob Clark #define REG_A6XX_HLSQ_DS_CNTL 0x0000b802 65632d756322SRob Clark #define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff 65642d756322SRob Clark #define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0 65652d756322SRob Clark static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val) 65662d756322SRob Clark { 65672d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK; 65682d756322SRob Clark } 6569c28c82e9SRob Clark #define A6XX_HLSQ_DS_CNTL_ENABLED 0x00000100 65702d756322SRob Clark 65712d756322SRob Clark #define REG_A6XX_HLSQ_GS_CNTL 0x0000b803 65722d756322SRob Clark #define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff 65732d756322SRob Clark #define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0 65742d756322SRob Clark static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val) 65752d756322SRob Clark { 65762d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK; 65772d756322SRob Clark } 6578c28c82e9SRob Clark #define A6XX_HLSQ_GS_CNTL_ENABLED 0x00000100 6579c28c82e9SRob Clark 6580c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD 0x0000b820 6581c28c82e9SRob Clark 6582c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR 0x0000b821 6583*cc4c26d4SRob Clark #define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK 0xffffffff 6584*cc4c26d4SRob Clark #define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT 0 6585*cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR(uint32_t val) 6586*cc4c26d4SRob Clark { 6587*cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK; 6588*cc4c26d4SRob Clark } 6589c28c82e9SRob Clark 6590c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA 0x0000b823 65912d756322SRob Clark 6592*cc4c26d4SRob Clark #define REG_A6XX_HLSQ_FS_CNTL_0 0x0000b980 6593*cc4c26d4SRob Clark #define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK 0x00000001 6594*cc4c26d4SRob Clark #define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT 0 6595*cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val) 6596*cc4c26d4SRob Clark { 6597*cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK; 6598*cc4c26d4SRob Clark } 6599*cc4c26d4SRob Clark #define A6XX_HLSQ_FS_CNTL_0_VARYINGS 0x00000002 6600*cc4c26d4SRob Clark #define A6XX_HLSQ_FS_CNTL_0_UNK2__MASK 0x00000ffc 6601*cc4c26d4SRob Clark #define A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT 2 6602*cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val) 6603*cc4c26d4SRob Clark { 6604*cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A6XX_HLSQ_FS_CNTL_0_UNK2__MASK; 6605*cc4c26d4SRob Clark } 6606*cc4c26d4SRob Clark 6607*cc4c26d4SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_B981 0x0000b981 6608a69c5ed2SRob Clark 66092d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982 66102d756322SRob Clark 66112d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_2_REG 0x0000b983 66122d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff 66132d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0 66142d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) 66152d756322SRob Clark { 66162d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; 66172d756322SRob Clark } 66182d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00 66192d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8 66202d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) 66212d756322SRob Clark { 66222d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK; 66232d756322SRob Clark } 66242d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000 66252d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16 66262d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) 66272d756322SRob Clark { 66282d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK; 66292d756322SRob Clark } 6630c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK 0xff000000 6631c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT 24 6632c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SIZE(uint32_t val) 6633c28c82e9SRob Clark { 6634c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK; 6635c28c82e9SRob Clark } 66362d756322SRob Clark 66372d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_3_REG 0x0000b984 6638c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff 6639c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0 6640c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val) 66412d756322SRob Clark { 6642c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK; 6643c28c82e9SRob Clark } 6644c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00 6645c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8 6646c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val) 6647c28c82e9SRob Clark { 6648c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK; 6649c28c82e9SRob Clark } 6650c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000 6651c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16 6652c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val) 6653c28c82e9SRob Clark { 6654c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK; 6655c28c82e9SRob Clark } 6656c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000 6657c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24 6658c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) 6659c28c82e9SRob Clark { 6660c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK; 66612d756322SRob Clark } 66622d756322SRob Clark 66632d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_4_REG 0x0000b985 6664c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff 6665c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0 6666c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val) 6667c28c82e9SRob Clark { 6668c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK; 6669c28c82e9SRob Clark } 6670c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00 6671c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8 6672c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val) 6673c28c82e9SRob Clark { 6674c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK; 6675c28c82e9SRob Clark } 66762d756322SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000 66772d756322SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16 66782d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) 66792d756322SRob Clark { 66802d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK; 66812d756322SRob Clark } 66822d756322SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000 66832d756322SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24 66842d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) 66852d756322SRob Clark { 66862d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; 66872d756322SRob Clark } 66882d756322SRob Clark 66892d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986 6690*cc4c26d4SRob Clark #define A6XX_HLSQ_CONTROL_5_REG_UNK0__MASK 0x000000ff 6691*cc4c26d4SRob Clark #define A6XX_HLSQ_CONTROL_5_REG_UNK0__SHIFT 0 6692*cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_UNK0(uint32_t val) 6693*cc4c26d4SRob Clark { 6694*cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_CONTROL_5_REG_UNK0__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_UNK0__MASK; 6695*cc4c26d4SRob Clark } 6696*cc4c26d4SRob Clark #define A6XX_HLSQ_CONTROL_5_REG_UNK8__MASK 0x0000ff00 6697*cc4c26d4SRob Clark #define A6XX_HLSQ_CONTROL_5_REG_UNK8__SHIFT 8 6698*cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_UNK8(uint32_t val) 6699*cc4c26d4SRob Clark { 6700*cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_CONTROL_5_REG_UNK8__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_UNK8__MASK; 6701*cc4c26d4SRob Clark } 67022d756322SRob Clark 6703c28c82e9SRob Clark #define REG_A6XX_HLSQ_CS_CNTL 0x0000b987 6704c28c82e9SRob Clark #define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff 6705c28c82e9SRob Clark #define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0 6706c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val) 6707c28c82e9SRob Clark { 6708c28c82e9SRob Clark return ((val >> 2) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK; 6709c28c82e9SRob Clark } 6710c28c82e9SRob Clark #define A6XX_HLSQ_CS_CNTL_ENABLED 0x00000100 6711c28c82e9SRob Clark 67122d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_0 0x0000b990 67132d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003 67142d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0 67152d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) 67162d756322SRob Clark { 67172d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK; 67182d756322SRob Clark } 67192d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc 67202d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2 67212d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) 67222d756322SRob Clark { 67232d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK; 67242d756322SRob Clark } 67252d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000 67262d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12 67272d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) 67282d756322SRob Clark { 67292d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK; 67302d756322SRob Clark } 67312d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000 67322d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22 67332d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) 67342d756322SRob Clark { 67352d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK; 67362d756322SRob Clark } 67372d756322SRob Clark 67382d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_1 0x0000b991 67392d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff 67402d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0 67412d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val) 67422d756322SRob Clark { 67432d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK; 67442d756322SRob Clark } 67452d756322SRob Clark 67462d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_2 0x0000b992 67472d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff 67482d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0 67492d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val) 67502d756322SRob Clark { 67512d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK; 67522d756322SRob Clark } 67532d756322SRob Clark 67542d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_3 0x0000b993 67552d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff 67562d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0 67572d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val) 67582d756322SRob Clark { 67592d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK; 67602d756322SRob Clark } 67612d756322SRob Clark 67622d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_4 0x0000b994 67632d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff 67642d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0 67652d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val) 67662d756322SRob Clark { 67672d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK; 67682d756322SRob Clark } 67692d756322SRob Clark 67702d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_5 0x0000b995 67712d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff 67722d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0 67732d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val) 67742d756322SRob Clark { 67752d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK; 67762d756322SRob Clark } 67772d756322SRob Clark 67782d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_6 0x0000b996 67792d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff 67802d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0 67812d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val) 67822d756322SRob Clark { 67832d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK; 67842d756322SRob Clark } 67852d756322SRob Clark 67862d756322SRob Clark #define REG_A6XX_HLSQ_CS_CNTL_0 0x0000b997 67872d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff 67882d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0 67892d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val) 67902d756322SRob Clark { 67912d756322SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK; 67922d756322SRob Clark } 6793*cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK 0x0000ff00 6794*cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT 8 6795*cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(uint32_t val) 67962d756322SRob Clark { 6797*cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK; 67982d756322SRob Clark } 6799*cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK 0x00ff0000 6800*cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT 16 6801*cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val) 68022d756322SRob Clark { 6803*cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK; 68042d756322SRob Clark } 68052d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000 68062d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24 68072d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) 68082d756322SRob Clark { 68092d756322SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK; 68102d756322SRob Clark } 68112d756322SRob Clark 6812*cc4c26d4SRob Clark #define REG_A6XX_HLSQ_CS_CNTL_1 0x0000b998 6813*cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff 6814*cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0 6815*cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) 6816*cc4c26d4SRob Clark { 6817*cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK; 6818*cc4c26d4SRob Clark } 6819*cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_1_SINGLE_SP_CORE 0x00000100 6820*cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK 0x00000200 6821*cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT 9 6822*cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) 6823*cc4c26d4SRob Clark { 6824*cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK; 6825*cc4c26d4SRob Clark } 6826*cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400 6827c28c82e9SRob Clark 68282d756322SRob Clark #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X 0x0000b999 68292d756322SRob Clark 68302d756322SRob Clark #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000b99a 68312d756322SRob Clark 68322d756322SRob Clark #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000b99b 68332d756322SRob Clark 6834c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD 0x0000b9a0 6835c28c82e9SRob Clark 6836c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR 0x0000b9a1 6837*cc4c26d4SRob Clark #define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK 0xffffffff 6838*cc4c26d4SRob Clark #define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT 0 6839*cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR(uint32_t val) 6840*cc4c26d4SRob Clark { 6841*cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK; 6842*cc4c26d4SRob Clark } 6843c28c82e9SRob Clark 6844c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA 0x0000b9a3 6845c28c82e9SRob Clark 6846c28c82e9SRob Clark static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; } 6847c28c82e9SRob Clark 6848c28c82e9SRob Clark static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; } 6849c28c82e9SRob Clark 6850c28c82e9SRob Clark #define REG_A6XX_HLSQ_DRAW_CMD 0x0000bb00 6851c28c82e9SRob Clark #define A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK 0x000000ff 6852c28c82e9SRob Clark #define A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT 0 6853c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_DRAW_CMD_STATE_ID(uint32_t val) 6854c28c82e9SRob Clark { 6855c28c82e9SRob Clark return ((val) << A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK; 6856c28c82e9SRob Clark } 6857c28c82e9SRob Clark 6858c28c82e9SRob Clark #define REG_A6XX_HLSQ_DISPATCH_CMD 0x0000bb01 6859c28c82e9SRob Clark #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK 0x000000ff 6860c28c82e9SRob Clark #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT 0 6861c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_DISPATCH_CMD_STATE_ID(uint32_t val) 6862c28c82e9SRob Clark { 6863c28c82e9SRob Clark return ((val) << A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK; 6864c28c82e9SRob Clark } 6865c28c82e9SRob Clark 6866c28c82e9SRob Clark #define REG_A6XX_HLSQ_EVENT_CMD 0x0000bb02 6867c28c82e9SRob Clark #define A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK 0x00ff0000 6868c28c82e9SRob Clark #define A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT 16 6869c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_EVENT_CMD_STATE_ID(uint32_t val) 6870c28c82e9SRob Clark { 6871c28c82e9SRob Clark return ((val) << A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK; 6872c28c82e9SRob Clark } 6873c28c82e9SRob Clark #define A6XX_HLSQ_EVENT_CMD_EVENT__MASK 0x0000007f 6874c28c82e9SRob Clark #define A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT 0 6875c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_EVENT_CMD_EVENT(enum vgt_event_type val) 6876c28c82e9SRob Clark { 6877c28c82e9SRob Clark return ((val) << A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_EVENT_CMD_EVENT__MASK; 6878c28c82e9SRob Clark } 6879c28c82e9SRob Clark 6880c28c82e9SRob Clark #define REG_A6XX_HLSQ_INVALIDATE_CMD 0x0000bb08 6881c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_VS_STATE 0x00000001 6882c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_HS_STATE 0x00000002 6883c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_DS_STATE 0x00000004 6884c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_GS_STATE 0x00000008 6885c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_FS_STATE 0x00000010 6886c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_CS_STATE 0x00000020 6887c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_CS_IBO 0x00000040 6888c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO 0x00000080 6889c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_CS_SHARED_CONST 0x00080000 6890c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_GFX_SHARED_CONST 0x00000100 6891c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK 0x00003e00 6892c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT 9 6893c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val) 6894c28c82e9SRob Clark { 6895c28c82e9SRob Clark return ((val) << A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK; 6896c28c82e9SRob Clark } 6897c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK 0x0007c000 6898c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT 14 6899c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val) 6900c28c82e9SRob Clark { 6901c28c82e9SRob Clark return ((val) << A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK; 6902c28c82e9SRob Clark } 69032d756322SRob Clark 69042d756322SRob Clark #define REG_A6XX_HLSQ_FS_CNTL 0x0000bb10 69052d756322SRob Clark #define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff 69062d756322SRob Clark #define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0 69072d756322SRob Clark static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val) 69082d756322SRob Clark { 69092d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK; 69102d756322SRob Clark } 6911c28c82e9SRob Clark #define A6XX_HLSQ_FS_CNTL_ENABLED 0x00000100 69122d756322SRob Clark 6913c28c82e9SRob Clark #define REG_A6XX_HLSQ_SHARED_CONSTS 0x0000bb11 6914c28c82e9SRob Clark #define A6XX_HLSQ_SHARED_CONSTS_ENABLE 0x00000001 6915c28c82e9SRob Clark 6916c28c82e9SRob Clark static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE(uint32_t i0) { return 0x0000bb20 + 0x2*i0; } 6917c28c82e9SRob Clark 6918c28c82e9SRob Clark static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000bb20 + 0x2*i0; } 6919c28c82e9SRob Clark 6920c28c82e9SRob Clark #define REG_A6XX_HLSQ_2D_EVENT_CMD 0x0000bd80 6921c28c82e9SRob Clark #define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00 6922c28c82e9SRob Clark #define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT 8 6923c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_STATE_ID(uint32_t val) 6924c28c82e9SRob Clark { 6925c28c82e9SRob Clark return ((val) << A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK; 6926c28c82e9SRob Clark } 6927c28c82e9SRob Clark #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK 0x0000007f 6928c28c82e9SRob Clark #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT 0 6929c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val) 6930c28c82e9SRob Clark { 6931c28c82e9SRob Clark return ((val) << A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK; 6932c28c82e9SRob Clark } 69332d756322SRob Clark 69342d756322SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_BE00 0x0000be00 69352d756322SRob Clark 69362d756322SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_BE01 0x0000be01 69372d756322SRob Clark 69382d756322SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_BE04 0x0000be04 69392d756322SRob Clark 6940*cc4c26d4SRob Clark #define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05 6941*cc4c26d4SRob Clark 6942*cc4c26d4SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_BE08 0x0000be08 6943*cc4c26d4SRob Clark 6944*cc4c26d4SRob Clark static inline uint32_t REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000be10 + 0x1*i0; } 6945*cc4c26d4SRob Clark 6946c28c82e9SRob Clark #define REG_A6XX_CP_EVENT_START 0x0000d600 6947c28c82e9SRob Clark #define A6XX_CP_EVENT_START_STATE_ID__MASK 0x000000ff 6948c28c82e9SRob Clark #define A6XX_CP_EVENT_START_STATE_ID__SHIFT 0 6949c28c82e9SRob Clark static inline uint32_t A6XX_CP_EVENT_START_STATE_ID(uint32_t val) 6950c28c82e9SRob Clark { 6951c28c82e9SRob Clark return ((val) << A6XX_CP_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_EVENT_START_STATE_ID__MASK; 6952c28c82e9SRob Clark } 6953c28c82e9SRob Clark 6954c28c82e9SRob Clark #define REG_A6XX_CP_EVENT_END 0x0000d601 6955c28c82e9SRob Clark #define A6XX_CP_EVENT_END_STATE_ID__MASK 0x000000ff 6956c28c82e9SRob Clark #define A6XX_CP_EVENT_END_STATE_ID__SHIFT 0 6957c28c82e9SRob Clark static inline uint32_t A6XX_CP_EVENT_END_STATE_ID(uint32_t val) 6958c28c82e9SRob Clark { 6959c28c82e9SRob Clark return ((val) << A6XX_CP_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_EVENT_END_STATE_ID__MASK; 6960c28c82e9SRob Clark } 6961c28c82e9SRob Clark 6962c28c82e9SRob Clark #define REG_A6XX_CP_2D_EVENT_START 0x0000d700 6963c28c82e9SRob Clark #define A6XX_CP_2D_EVENT_START_STATE_ID__MASK 0x000000ff 6964c28c82e9SRob Clark #define A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT 0 6965c28c82e9SRob Clark static inline uint32_t A6XX_CP_2D_EVENT_START_STATE_ID(uint32_t val) 6966c28c82e9SRob Clark { 6967c28c82e9SRob Clark return ((val) << A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_START_STATE_ID__MASK; 6968c28c82e9SRob Clark } 6969c28c82e9SRob Clark 6970c28c82e9SRob Clark #define REG_A6XX_CP_2D_EVENT_END 0x0000d701 6971c28c82e9SRob Clark #define A6XX_CP_2D_EVENT_END_STATE_ID__MASK 0x000000ff 6972c28c82e9SRob Clark #define A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT 0 6973c28c82e9SRob Clark static inline uint32_t A6XX_CP_2D_EVENT_END_STATE_ID(uint32_t val) 6974c28c82e9SRob Clark { 6975c28c82e9SRob Clark return ((val) << A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_END_STATE_ID__MASK; 6976c28c82e9SRob Clark } 6977c28c82e9SRob Clark 69782d756322SRob Clark #define REG_A6XX_TEX_SAMP_0 0x00000000 69792d756322SRob Clark #define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 69802d756322SRob Clark #define A6XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 69812d756322SRob Clark #define A6XX_TEX_SAMP_0_XY_MAG__SHIFT 1 69822d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val) 69832d756322SRob Clark { 69842d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_XY_MAG__SHIFT) & A6XX_TEX_SAMP_0_XY_MAG__MASK; 69852d756322SRob Clark } 69862d756322SRob Clark #define A6XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 69872d756322SRob Clark #define A6XX_TEX_SAMP_0_XY_MIN__SHIFT 3 69882d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val) 69892d756322SRob Clark { 69902d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_XY_MIN__SHIFT) & A6XX_TEX_SAMP_0_XY_MIN__MASK; 69912d756322SRob Clark } 69922d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 69932d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_S__SHIFT 5 69942d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val) 69952d756322SRob Clark { 69962d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_WRAP_S__SHIFT) & A6XX_TEX_SAMP_0_WRAP_S__MASK; 69972d756322SRob Clark } 69982d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 69992d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_T__SHIFT 8 70002d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val) 70012d756322SRob Clark { 70022d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_WRAP_T__SHIFT) & A6XX_TEX_SAMP_0_WRAP_T__MASK; 70032d756322SRob Clark } 70042d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 70052d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_R__SHIFT 11 70062d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val) 70072d756322SRob Clark { 70082d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_WRAP_R__SHIFT) & A6XX_TEX_SAMP_0_WRAP_R__MASK; 70092d756322SRob Clark } 70102d756322SRob Clark #define A6XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 70112d756322SRob Clark #define A6XX_TEX_SAMP_0_ANISO__SHIFT 14 70122d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val) 70132d756322SRob Clark { 70142d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_ANISO__SHIFT) & A6XX_TEX_SAMP_0_ANISO__MASK; 70152d756322SRob Clark } 70162d756322SRob Clark #define A6XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000 70172d756322SRob Clark #define A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19 70182d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val) 70192d756322SRob Clark { 70202d756322SRob Clark return ((((int32_t)(val * 256.0))) << A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A6XX_TEX_SAMP_0_LOD_BIAS__MASK; 70212d756322SRob Clark } 70222d756322SRob Clark 70232d756322SRob Clark #define REG_A6XX_TEX_SAMP_1 0x00000001 7024c28c82e9SRob Clark #define A6XX_TEX_SAMP_1_UNK0 0x00000001 70252d756322SRob Clark #define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e 70262d756322SRob Clark #define A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 70272d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) 70282d756322SRob Clark { 70292d756322SRob Clark return ((val) << A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK; 70302d756322SRob Clark } 70312d756322SRob Clark #define A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010 70322d756322SRob Clark #define A6XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 70332d756322SRob Clark #define A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 70342d756322SRob Clark #define A6XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 70352d756322SRob Clark #define A6XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 70362d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_1_MAX_LOD(float val) 70372d756322SRob Clark { 70382d756322SRob Clark return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK; 70392d756322SRob Clark } 70402d756322SRob Clark #define A6XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 70412d756322SRob Clark #define A6XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 70422d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_1_MIN_LOD(float val) 70432d756322SRob Clark { 70442d756322SRob Clark return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK; 70452d756322SRob Clark } 70462d756322SRob Clark 70472d756322SRob Clark #define REG_A6XX_TEX_SAMP_2 0x00000002 7048c28c82e9SRob Clark #define A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK 0x00000003 7049c28c82e9SRob Clark #define A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT 0 7050c28c82e9SRob Clark static inline uint32_t A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode val) 7051c28c82e9SRob Clark { 7052c28c82e9SRob Clark return ((val) << A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT) & A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK; 7053c28c82e9SRob Clark } 7054c28c82e9SRob Clark #define A6XX_TEX_SAMP_2_CHROMA_LINEAR 0x00000020 7055*cc4c26d4SRob Clark #define A6XX_TEX_SAMP_2_BCOLOR__MASK 0xffffff80 7056*cc4c26d4SRob Clark #define A6XX_TEX_SAMP_2_BCOLOR__SHIFT 7 7057*cc4c26d4SRob Clark static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR(uint32_t val) 70582d756322SRob Clark { 7059*cc4c26d4SRob Clark return ((val) << A6XX_TEX_SAMP_2_BCOLOR__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR__MASK; 70602d756322SRob Clark } 70612d756322SRob Clark 70622d756322SRob Clark #define REG_A6XX_TEX_SAMP_3 0x00000003 70632d756322SRob Clark 70642d756322SRob Clark #define REG_A6XX_TEX_CONST_0 0x00000000 70652d756322SRob Clark #define A6XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003 70662d756322SRob Clark #define A6XX_TEX_CONST_0_TILE_MODE__SHIFT 0 70672d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val) 70682d756322SRob Clark { 70692d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_TILE_MODE__SHIFT) & A6XX_TEX_CONST_0_TILE_MODE__MASK; 70702d756322SRob Clark } 70712d756322SRob Clark #define A6XX_TEX_CONST_0_SRGB 0x00000004 70722d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 70732d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_X__SHIFT 4 70742d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val) 70752d756322SRob Clark { 70762d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWIZ_X__SHIFT) & A6XX_TEX_CONST_0_SWIZ_X__MASK; 70772d756322SRob Clark } 70782d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 70792d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 70802d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val) 70812d756322SRob Clark { 70822d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Y__MASK; 70832d756322SRob Clark } 70842d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 70852d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 70862d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val) 70872d756322SRob Clark { 70882d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Z__MASK; 70892d756322SRob Clark } 70902d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 70912d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_W__SHIFT 13 70922d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val) 70932d756322SRob Clark { 70942d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWIZ_W__SHIFT) & A6XX_TEX_CONST_0_SWIZ_W__MASK; 70952d756322SRob Clark } 70962d756322SRob Clark #define A6XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 70972d756322SRob Clark #define A6XX_TEX_CONST_0_MIPLVLS__SHIFT 16 70982d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val) 70992d756322SRob Clark { 71002d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK; 71012d756322SRob Clark } 7102c28c82e9SRob Clark #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X 0x00010000 7103c28c82e9SRob Clark #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y 0x00040000 7104ccdf7e28SRob Clark #define A6XX_TEX_CONST_0_SAMPLES__MASK 0x00300000 7105ccdf7e28SRob Clark #define A6XX_TEX_CONST_0_SAMPLES__SHIFT 20 7106ccdf7e28SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val) 7107ccdf7e28SRob Clark { 7108ccdf7e28SRob Clark return ((val) << A6XX_TEX_CONST_0_SAMPLES__SHIFT) & A6XX_TEX_CONST_0_SAMPLES__MASK; 7109ccdf7e28SRob Clark } 71102d756322SRob Clark #define A6XX_TEX_CONST_0_FMT__MASK 0x3fc00000 71112d756322SRob Clark #define A6XX_TEX_CONST_0_FMT__SHIFT 22 7112c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_format val) 71132d756322SRob Clark { 71142d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK; 71152d756322SRob Clark } 71162d756322SRob Clark #define A6XX_TEX_CONST_0_SWAP__MASK 0xc0000000 71172d756322SRob Clark #define A6XX_TEX_CONST_0_SWAP__SHIFT 30 71182d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val) 71192d756322SRob Clark { 71202d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWAP__SHIFT) & A6XX_TEX_CONST_0_SWAP__MASK; 71212d756322SRob Clark } 71222d756322SRob Clark 71232d756322SRob Clark #define REG_A6XX_TEX_CONST_1 0x00000001 71242d756322SRob Clark #define A6XX_TEX_CONST_1_WIDTH__MASK 0x00007fff 71252d756322SRob Clark #define A6XX_TEX_CONST_1_WIDTH__SHIFT 0 71262d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_1_WIDTH(uint32_t val) 71272d756322SRob Clark { 71282d756322SRob Clark return ((val) << A6XX_TEX_CONST_1_WIDTH__SHIFT) & A6XX_TEX_CONST_1_WIDTH__MASK; 71292d756322SRob Clark } 71302d756322SRob Clark #define A6XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000 71312d756322SRob Clark #define A6XX_TEX_CONST_1_HEIGHT__SHIFT 15 71322d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val) 71332d756322SRob Clark { 71342d756322SRob Clark return ((val) << A6XX_TEX_CONST_1_HEIGHT__SHIFT) & A6XX_TEX_CONST_1_HEIGHT__MASK; 71352d756322SRob Clark } 71362d756322SRob Clark 71372d756322SRob Clark #define REG_A6XX_TEX_CONST_2 0x00000002 7138c28c82e9SRob Clark #define A6XX_TEX_CONST_2_UNK4 0x00000010 7139c28c82e9SRob Clark #define A6XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f 7140c28c82e9SRob Clark #define A6XX_TEX_CONST_2_PITCHALIGN__SHIFT 0 7141c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_2_PITCHALIGN(uint32_t val) 71422d756322SRob Clark { 7143c28c82e9SRob Clark return ((val) << A6XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A6XX_TEX_CONST_2_PITCHALIGN__MASK; 71442d756322SRob Clark } 71452d756322SRob Clark #define A6XX_TEX_CONST_2_PITCH__MASK 0x1fffff80 71462d756322SRob Clark #define A6XX_TEX_CONST_2_PITCH__SHIFT 7 71472d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_2_PITCH(uint32_t val) 71482d756322SRob Clark { 71492d756322SRob Clark return ((val) << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK; 71502d756322SRob Clark } 71512d756322SRob Clark #define A6XX_TEX_CONST_2_TYPE__MASK 0x60000000 71522d756322SRob Clark #define A6XX_TEX_CONST_2_TYPE__SHIFT 29 71532d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val) 71542d756322SRob Clark { 71552d756322SRob Clark return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK; 71562d756322SRob Clark } 7157c28c82e9SRob Clark #define A6XX_TEX_CONST_2_UNK31 0x80000000 71582d756322SRob Clark 71592d756322SRob Clark #define REG_A6XX_TEX_CONST_3 0x00000003 71602d756322SRob Clark #define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff 71612d756322SRob Clark #define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0 71622d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) 71632d756322SRob Clark { 71642d756322SRob Clark return ((val >> 12) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK; 71652d756322SRob Clark } 7166c28c82e9SRob Clark #define A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000 7167c28c82e9SRob Clark #define A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23 7168c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val) 7169c28c82e9SRob Clark { 7170c28c82e9SRob Clark return ((val >> 12) << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK; 7171c28c82e9SRob Clark } 7172c28c82e9SRob Clark #define A6XX_TEX_CONST_3_TILE_ALL 0x08000000 71732d756322SRob Clark #define A6XX_TEX_CONST_3_FLAG 0x10000000 71742d756322SRob Clark 71752d756322SRob Clark #define REG_A6XX_TEX_CONST_4 0x00000004 71762d756322SRob Clark #define A6XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0 71772d756322SRob Clark #define A6XX_TEX_CONST_4_BASE_LO__SHIFT 5 71782d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val) 71792d756322SRob Clark { 71802d756322SRob Clark return ((val >> 5) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK; 71812d756322SRob Clark } 71822d756322SRob Clark 71832d756322SRob Clark #define REG_A6XX_TEX_CONST_5 0x00000005 71842d756322SRob Clark #define A6XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff 71852d756322SRob Clark #define A6XX_TEX_CONST_5_BASE_HI__SHIFT 0 71862d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_5_BASE_HI(uint32_t val) 71872d756322SRob Clark { 71882d756322SRob Clark return ((val) << A6XX_TEX_CONST_5_BASE_HI__SHIFT) & A6XX_TEX_CONST_5_BASE_HI__MASK; 71892d756322SRob Clark } 71902d756322SRob Clark #define A6XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000 71912d756322SRob Clark #define A6XX_TEX_CONST_5_DEPTH__SHIFT 17 71922d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_5_DEPTH(uint32_t val) 71932d756322SRob Clark { 71942d756322SRob Clark return ((val) << A6XX_TEX_CONST_5_DEPTH__SHIFT) & A6XX_TEX_CONST_5_DEPTH__MASK; 71952d756322SRob Clark } 71962d756322SRob Clark 71972d756322SRob Clark #define REG_A6XX_TEX_CONST_6 0x00000006 7198c28c82e9SRob Clark #define A6XX_TEX_CONST_6_PLANE_PITCH__MASK 0xffffff00 7199c28c82e9SRob Clark #define A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT 8 7200c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_6_PLANE_PITCH(uint32_t val) 7201c28c82e9SRob Clark { 7202c28c82e9SRob Clark return ((val) << A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT) & A6XX_TEX_CONST_6_PLANE_PITCH__MASK; 7203c28c82e9SRob Clark } 72042d756322SRob Clark 72052d756322SRob Clark #define REG_A6XX_TEX_CONST_7 0x00000007 72062d756322SRob Clark #define A6XX_TEX_CONST_7_FLAG_LO__MASK 0xffffffe0 72072d756322SRob Clark #define A6XX_TEX_CONST_7_FLAG_LO__SHIFT 5 72082d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val) 72092d756322SRob Clark { 72102d756322SRob Clark return ((val >> 5) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK; 72112d756322SRob Clark } 72122d756322SRob Clark 72132d756322SRob Clark #define REG_A6XX_TEX_CONST_8 0x00000008 7214a69c5ed2SRob Clark #define A6XX_TEX_CONST_8_FLAG_HI__MASK 0x0001ffff 7215a69c5ed2SRob Clark #define A6XX_TEX_CONST_8_FLAG_HI__SHIFT 0 7216a69c5ed2SRob Clark static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val) 72172d756322SRob Clark { 7218a69c5ed2SRob Clark return ((val) << A6XX_TEX_CONST_8_FLAG_HI__SHIFT) & A6XX_TEX_CONST_8_FLAG_HI__MASK; 72192d756322SRob Clark } 72202d756322SRob Clark 72212d756322SRob Clark #define REG_A6XX_TEX_CONST_9 0x00000009 7222c28c82e9SRob Clark #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff 7223c28c82e9SRob Clark #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0 7224c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) 7225c28c82e9SRob Clark { 7226c28c82e9SRob Clark return ((val >> 4) << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK; 7227c28c82e9SRob Clark } 72282d756322SRob Clark 72292d756322SRob Clark #define REG_A6XX_TEX_CONST_10 0x0000000a 7230c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK 0x0000007f 7231c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT 0 7232c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val) 7233c28c82e9SRob Clark { 7234c28c82e9SRob Clark return ((val >> 6) << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK; 7235c28c82e9SRob Clark } 7236c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK 0x00000f00 7237c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT 8 7238c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(uint32_t val) 7239c28c82e9SRob Clark { 7240c28c82e9SRob Clark return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK; 7241c28c82e9SRob Clark } 7242c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK 0x0000f000 7243c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT 12 7244c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(uint32_t val) 7245c28c82e9SRob Clark { 7246c28c82e9SRob Clark return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK; 7247c28c82e9SRob Clark } 72482d756322SRob Clark 72492d756322SRob Clark #define REG_A6XX_TEX_CONST_11 0x0000000b 72502d756322SRob Clark 72512d756322SRob Clark #define REG_A6XX_TEX_CONST_12 0x0000000c 72522d756322SRob Clark 72532d756322SRob Clark #define REG_A6XX_TEX_CONST_13 0x0000000d 72542d756322SRob Clark 72552d756322SRob Clark #define REG_A6XX_TEX_CONST_14 0x0000000e 72562d756322SRob Clark 72572d756322SRob Clark #define REG_A6XX_TEX_CONST_15 0x0000000f 72582d756322SRob Clark 7259c28c82e9SRob Clark #define REG_A6XX_IBO_0 0x00000000 7260c28c82e9SRob Clark #define A6XX_IBO_0_TILE_MODE__MASK 0x00000003 7261c28c82e9SRob Clark #define A6XX_IBO_0_TILE_MODE__SHIFT 0 7262c28c82e9SRob Clark static inline uint32_t A6XX_IBO_0_TILE_MODE(enum a6xx_tile_mode val) 7263c28c82e9SRob Clark { 7264c28c82e9SRob Clark return ((val) << A6XX_IBO_0_TILE_MODE__SHIFT) & A6XX_IBO_0_TILE_MODE__MASK; 7265c28c82e9SRob Clark } 7266c28c82e9SRob Clark #define A6XX_IBO_0_FMT__MASK 0x3fc00000 7267c28c82e9SRob Clark #define A6XX_IBO_0_FMT__SHIFT 22 7268c28c82e9SRob Clark static inline uint32_t A6XX_IBO_0_FMT(enum a6xx_format val) 7269c28c82e9SRob Clark { 7270c28c82e9SRob Clark return ((val) << A6XX_IBO_0_FMT__SHIFT) & A6XX_IBO_0_FMT__MASK; 7271c28c82e9SRob Clark } 7272c28c82e9SRob Clark 7273c28c82e9SRob Clark #define REG_A6XX_IBO_1 0x00000001 7274c28c82e9SRob Clark #define A6XX_IBO_1_WIDTH__MASK 0x00007fff 7275c28c82e9SRob Clark #define A6XX_IBO_1_WIDTH__SHIFT 0 7276c28c82e9SRob Clark static inline uint32_t A6XX_IBO_1_WIDTH(uint32_t val) 7277c28c82e9SRob Clark { 7278c28c82e9SRob Clark return ((val) << A6XX_IBO_1_WIDTH__SHIFT) & A6XX_IBO_1_WIDTH__MASK; 7279c28c82e9SRob Clark } 7280c28c82e9SRob Clark #define A6XX_IBO_1_HEIGHT__MASK 0x3fff8000 7281c28c82e9SRob Clark #define A6XX_IBO_1_HEIGHT__SHIFT 15 7282c28c82e9SRob Clark static inline uint32_t A6XX_IBO_1_HEIGHT(uint32_t val) 7283c28c82e9SRob Clark { 7284c28c82e9SRob Clark return ((val) << A6XX_IBO_1_HEIGHT__SHIFT) & A6XX_IBO_1_HEIGHT__MASK; 7285c28c82e9SRob Clark } 7286c28c82e9SRob Clark 7287c28c82e9SRob Clark #define REG_A6XX_IBO_2 0x00000002 7288c28c82e9SRob Clark #define A6XX_IBO_2_UNK4 0x00000010 7289c28c82e9SRob Clark #define A6XX_IBO_2_PITCH__MASK 0x1fffff80 7290c28c82e9SRob Clark #define A6XX_IBO_2_PITCH__SHIFT 7 7291c28c82e9SRob Clark static inline uint32_t A6XX_IBO_2_PITCH(uint32_t val) 7292c28c82e9SRob Clark { 7293c28c82e9SRob Clark return ((val) << A6XX_IBO_2_PITCH__SHIFT) & A6XX_IBO_2_PITCH__MASK; 7294c28c82e9SRob Clark } 7295c28c82e9SRob Clark #define A6XX_IBO_2_TYPE__MASK 0x60000000 7296c28c82e9SRob Clark #define A6XX_IBO_2_TYPE__SHIFT 29 7297c28c82e9SRob Clark static inline uint32_t A6XX_IBO_2_TYPE(enum a6xx_tex_type val) 7298c28c82e9SRob Clark { 7299c28c82e9SRob Clark return ((val) << A6XX_IBO_2_TYPE__SHIFT) & A6XX_IBO_2_TYPE__MASK; 7300c28c82e9SRob Clark } 7301c28c82e9SRob Clark #define A6XX_IBO_2_UNK31 0x80000000 7302c28c82e9SRob Clark 7303c28c82e9SRob Clark #define REG_A6XX_IBO_3 0x00000003 7304c28c82e9SRob Clark #define A6XX_IBO_3_ARRAY_PITCH__MASK 0x00003fff 7305c28c82e9SRob Clark #define A6XX_IBO_3_ARRAY_PITCH__SHIFT 0 7306c28c82e9SRob Clark static inline uint32_t A6XX_IBO_3_ARRAY_PITCH(uint32_t val) 7307c28c82e9SRob Clark { 7308c28c82e9SRob Clark return ((val >> 12) << A6XX_IBO_3_ARRAY_PITCH__SHIFT) & A6XX_IBO_3_ARRAY_PITCH__MASK; 7309c28c82e9SRob Clark } 7310c28c82e9SRob Clark #define A6XX_IBO_3_UNK27 0x08000000 7311c28c82e9SRob Clark #define A6XX_IBO_3_FLAG 0x10000000 7312c28c82e9SRob Clark 7313c28c82e9SRob Clark #define REG_A6XX_IBO_4 0x00000004 7314c28c82e9SRob Clark #define A6XX_IBO_4_BASE_LO__MASK 0xffffffff 7315c28c82e9SRob Clark #define A6XX_IBO_4_BASE_LO__SHIFT 0 7316c28c82e9SRob Clark static inline uint32_t A6XX_IBO_4_BASE_LO(uint32_t val) 7317c28c82e9SRob Clark { 7318c28c82e9SRob Clark return ((val) << A6XX_IBO_4_BASE_LO__SHIFT) & A6XX_IBO_4_BASE_LO__MASK; 7319c28c82e9SRob Clark } 7320c28c82e9SRob Clark 7321c28c82e9SRob Clark #define REG_A6XX_IBO_5 0x00000005 7322c28c82e9SRob Clark #define A6XX_IBO_5_BASE_HI__MASK 0x0001ffff 7323c28c82e9SRob Clark #define A6XX_IBO_5_BASE_HI__SHIFT 0 7324c28c82e9SRob Clark static inline uint32_t A6XX_IBO_5_BASE_HI(uint32_t val) 7325c28c82e9SRob Clark { 7326c28c82e9SRob Clark return ((val) << A6XX_IBO_5_BASE_HI__SHIFT) & A6XX_IBO_5_BASE_HI__MASK; 7327c28c82e9SRob Clark } 7328c28c82e9SRob Clark #define A6XX_IBO_5_DEPTH__MASK 0x3ffe0000 7329c28c82e9SRob Clark #define A6XX_IBO_5_DEPTH__SHIFT 17 7330c28c82e9SRob Clark static inline uint32_t A6XX_IBO_5_DEPTH(uint32_t val) 7331c28c82e9SRob Clark { 7332c28c82e9SRob Clark return ((val) << A6XX_IBO_5_DEPTH__SHIFT) & A6XX_IBO_5_DEPTH__MASK; 7333c28c82e9SRob Clark } 7334c28c82e9SRob Clark 7335c28c82e9SRob Clark #define REG_A6XX_IBO_6 0x00000006 7336c28c82e9SRob Clark 7337c28c82e9SRob Clark #define REG_A6XX_IBO_7 0x00000007 7338c28c82e9SRob Clark 7339c28c82e9SRob Clark #define REG_A6XX_IBO_8 0x00000008 7340c28c82e9SRob Clark 7341c28c82e9SRob Clark #define REG_A6XX_IBO_9 0x00000009 7342c28c82e9SRob Clark #define A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff 7343c28c82e9SRob Clark #define A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0 7344c28c82e9SRob Clark static inline uint32_t A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) 7345c28c82e9SRob Clark { 7346c28c82e9SRob Clark return ((val >> 4) << A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__MASK; 7347c28c82e9SRob Clark } 7348c28c82e9SRob Clark 7349c28c82e9SRob Clark #define REG_A6XX_IBO_10 0x0000000a 7350c28c82e9SRob Clark #define A6XX_IBO_10_FLAG_BUFFER_PITCH__MASK 0x0000007f 7351c28c82e9SRob Clark #define A6XX_IBO_10_FLAG_BUFFER_PITCH__SHIFT 0 7352c28c82e9SRob Clark static inline uint32_t A6XX_IBO_10_FLAG_BUFFER_PITCH(uint32_t val) 7353c28c82e9SRob Clark { 7354c28c82e9SRob Clark return ((val >> 6) << A6XX_IBO_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_IBO_10_FLAG_BUFFER_PITCH__MASK; 7355c28c82e9SRob Clark } 7356c28c82e9SRob Clark 7357c28c82e9SRob Clark #define REG_A6XX_UBO_0 0x00000000 7358c28c82e9SRob Clark #define A6XX_UBO_0_BASE_LO__MASK 0xffffffff 7359c28c82e9SRob Clark #define A6XX_UBO_0_BASE_LO__SHIFT 0 7360c28c82e9SRob Clark static inline uint32_t A6XX_UBO_0_BASE_LO(uint32_t val) 7361c28c82e9SRob Clark { 7362c28c82e9SRob Clark return ((val) << A6XX_UBO_0_BASE_LO__SHIFT) & A6XX_UBO_0_BASE_LO__MASK; 7363c28c82e9SRob Clark } 7364c28c82e9SRob Clark 7365c28c82e9SRob Clark #define REG_A6XX_UBO_1 0x00000001 7366c28c82e9SRob Clark #define A6XX_UBO_1_BASE_HI__MASK 0x0001ffff 7367c28c82e9SRob Clark #define A6XX_UBO_1_BASE_HI__SHIFT 0 7368c28c82e9SRob Clark static inline uint32_t A6XX_UBO_1_BASE_HI(uint32_t val) 7369c28c82e9SRob Clark { 7370c28c82e9SRob Clark return ((val) << A6XX_UBO_1_BASE_HI__SHIFT) & A6XX_UBO_1_BASE_HI__MASK; 7371c28c82e9SRob Clark } 7372c28c82e9SRob Clark #define A6XX_UBO_1_SIZE__MASK 0xfffe0000 7373c28c82e9SRob Clark #define A6XX_UBO_1_SIZE__SHIFT 17 7374c28c82e9SRob Clark static inline uint32_t A6XX_UBO_1_SIZE(uint32_t val) 7375c28c82e9SRob Clark { 7376c28c82e9SRob Clark return ((val) << A6XX_UBO_1_SIZE__SHIFT) & A6XX_UBO_1_SIZE__MASK; 7377c28c82e9SRob Clark } 7378c28c82e9SRob Clark 7379a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_ENABLE_PDC 0x00001140 7380a69c5ed2SRob Clark 7381a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_SEQ_START_ADDR 0x00001148 7382a69c5ed2SRob Clark 7383a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CONTROL 0x00001540 7384a69c5ed2SRob Clark 7385a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK 0x00001541 7386a69c5ed2SRob Clark 7387a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK 0x00001542 7388a69c5ed2SRob Clark 7389a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID 0x00001543 7390a69c5ed2SRob Clark 7391a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR 0x00001544 7392a69c5ed2SRob Clark 7393a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA 0x00001545 7394a69c5ed2SRob Clark 7395a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CONTROL 0x00001572 7396a69c5ed2SRob Clark 7397a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK 0x00001573 7398a69c5ed2SRob Clark 7399a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK 0x00001574 7400a69c5ed2SRob Clark 7401a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID 0x00001575 7402a69c5ed2SRob Clark 7403a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR 0x00001576 7404a69c5ed2SRob Clark 7405a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA 0x00001577 7406a69c5ed2SRob Clark 7407a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CONTROL 0x000015a4 7408a69c5ed2SRob Clark 7409a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK 0x000015a5 7410a69c5ed2SRob Clark 7411a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK 0x000015a6 7412a69c5ed2SRob Clark 7413a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID 0x000015a7 7414a69c5ed2SRob Clark 7415a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR 0x000015a8 7416a69c5ed2SRob Clark 7417a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA 0x000015a9 7418a69c5ed2SRob Clark 7419a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CONTROL 0x000015d6 7420a69c5ed2SRob Clark 7421a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK 0x000015d7 7422a69c5ed2SRob Clark 7423a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK 0x000015d8 7424a69c5ed2SRob Clark 7425a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID 0x000015d9 7426a69c5ed2SRob Clark 7427a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR 0x000015da 7428a69c5ed2SRob Clark 7429a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA 0x000015db 7430a69c5ed2SRob Clark 7431a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x00000000 7432a69c5ed2SRob Clark 7433a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A 0x00000000 7434a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK 0x000000ff 7435a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT 0 7436a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val) 7437a69c5ed2SRob Clark { 7438a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK; 7439a69c5ed2SRob Clark } 7440a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK 0x0000ff00 7441a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT 8 7442a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val) 7443a69c5ed2SRob Clark { 7444a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK; 7445a69c5ed2SRob Clark } 7446a69c5ed2SRob Clark 7447a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B 0x00000001 7448a69c5ed2SRob Clark 7449a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C 0x00000002 7450a69c5ed2SRob Clark 7451a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D 0x00000003 7452a69c5ed2SRob Clark 7453a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT 0x00000004 7454a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f 7455a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0 7456a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) 7457a69c5ed2SRob Clark { 7458a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; 7459a69c5ed2SRob Clark } 7460a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000 7461a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12 7462a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) 7463a69c5ed2SRob Clark { 7464a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; 7465a69c5ed2SRob Clark } 7466a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000 7467a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28 7468a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) 7469a69c5ed2SRob Clark { 7470a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; 7471a69c5ed2SRob Clark } 7472a69c5ed2SRob Clark 7473a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM 0x00000005 7474a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000 7475a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24 7476a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) 7477a69c5ed2SRob Clark { 7478a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; 7479a69c5ed2SRob Clark } 7480a69c5ed2SRob Clark 7481a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 0x00000008 7482a69c5ed2SRob Clark 7483a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 0x00000009 7484a69c5ed2SRob Clark 7485a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 0x0000000a 7486a69c5ed2SRob Clark 7487a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 0x0000000b 7488a69c5ed2SRob Clark 7489a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 0x0000000c 7490a69c5ed2SRob Clark 7491a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 0x0000000d 7492a69c5ed2SRob Clark 7493a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 0x0000000e 7494a69c5ed2SRob Clark 7495a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 0x0000000f 7496a69c5ed2SRob Clark 7497a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000010 7498a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f 7499a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0 7500a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) 7501a69c5ed2SRob Clark { 7502a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; 7503a69c5ed2SRob Clark } 7504a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0 7505a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4 7506a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) 7507a69c5ed2SRob Clark { 7508a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; 7509a69c5ed2SRob Clark } 7510a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00 7511a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8 7512a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) 7513a69c5ed2SRob Clark { 7514a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; 7515a69c5ed2SRob Clark } 7516a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000 7517a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12 7518a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) 7519a69c5ed2SRob Clark { 7520a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; 7521a69c5ed2SRob Clark } 7522a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000 7523a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16 7524a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) 7525a69c5ed2SRob Clark { 7526a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; 7527a69c5ed2SRob Clark } 7528a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000 7529a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20 7530a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) 7531a69c5ed2SRob Clark { 7532a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; 7533a69c5ed2SRob Clark } 7534a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000 7535a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24 7536a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) 7537a69c5ed2SRob Clark { 7538a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; 7539a69c5ed2SRob Clark } 7540a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000 7541a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28 7542a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) 7543a69c5ed2SRob Clark { 7544a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; 7545a69c5ed2SRob Clark } 7546a69c5ed2SRob Clark 7547a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000011 7548a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f 7549a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0 7550a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) 7551a69c5ed2SRob Clark { 7552a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; 7553a69c5ed2SRob Clark } 7554a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0 7555a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4 7556a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) 7557a69c5ed2SRob Clark { 7558a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; 7559a69c5ed2SRob Clark } 7560a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00 7561a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8 7562a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) 7563a69c5ed2SRob Clark { 7564a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; 7565a69c5ed2SRob Clark } 7566a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000 7567a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12 7568a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) 7569a69c5ed2SRob Clark { 7570a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; 7571a69c5ed2SRob Clark } 7572a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000 7573a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16 7574a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) 7575a69c5ed2SRob Clark { 7576a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; 7577a69c5ed2SRob Clark } 7578a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000 7579a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20 7580a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) 7581a69c5ed2SRob Clark { 7582a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; 7583a69c5ed2SRob Clark } 7584a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000 7585a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24 7586a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) 7587a69c5ed2SRob Clark { 7588a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; 7589a69c5ed2SRob Clark } 7590a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000 7591a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28 7592a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) 7593a69c5ed2SRob Clark { 7594a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; 7595a69c5ed2SRob Clark } 7596a69c5ed2SRob Clark 7597a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000002f 7598a69c5ed2SRob Clark 7599a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000030 7600a69c5ed2SRob Clark 7601ccdf7e28SRob Clark #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 0x00000001 7602ccdf7e28SRob Clark 7603ccdf7e28SRob Clark #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 0x00000002 7604ccdf7e28SRob Clark 76052d756322SRob Clark 76062d756322SRob Clark #endif /* A6XX_XML */ 7607