12d756322SRob Clark #ifndef A6XX_XML 22d756322SRob Clark #define A6XX_XML 32d756322SRob Clark 42d756322SRob Clark /* Autogenerated file, DO NOT EDIT manually! 52d756322SRob Clark 62d756322SRob Clark This file was generated by the rules-ng-ng headergen tool in this git repository: 72d756322SRob Clark http://github.com/freedreno/envytools/ 82d756322SRob Clark git clone https://github.com/freedreno/envytools.git 92d756322SRob Clark 102d756322SRob Clark The rules-ng-ng source files this header was generated from are: 11c28c82e9SRob Clark - /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14) 12c28c82e9SRob Clark - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14) 13c28c82e9SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14) 14c28c82e9SRob Clark - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14) 15c28c82e9SRob Clark - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14) 16c28c82e9SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14) 17c28c82e9SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14) 18c28c82e9SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14) 19c28c82e9SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14) 20c28c82e9SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14) 21c28c82e9SRob Clark - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14) 22c28c82e9SRob Clark - /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14) 23c28c82e9SRob Clark - /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14) 242d756322SRob Clark 25c28c82e9SRob Clark Copyright (C) 2013-2020 by the following authors: 262d756322SRob Clark - Rob Clark <robdclark@gmail.com> (robclark) 272d756322SRob Clark - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 282d756322SRob Clark 292d756322SRob Clark Permission is hereby granted, free of charge, to any person obtaining 302d756322SRob Clark a copy of this software and associated documentation files (the 312d756322SRob Clark "Software"), to deal in the Software without restriction, including 322d756322SRob Clark without limitation the rights to use, copy, modify, merge, publish, 332d756322SRob Clark distribute, sublicense, and/or sell copies of the Software, and to 342d756322SRob Clark permit persons to whom the Software is furnished to do so, subject to 352d756322SRob Clark the following conditions: 362d756322SRob Clark 372d756322SRob Clark The above copyright notice and this permission notice (including the 382d756322SRob Clark next paragraph) shall be included in all copies or substantial 392d756322SRob Clark portions of the Software. 402d756322SRob Clark 412d756322SRob Clark THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 422d756322SRob Clark EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 432d756322SRob Clark MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 442d756322SRob Clark IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 452d756322SRob Clark LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 462d756322SRob Clark OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 472d756322SRob Clark WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 482d756322SRob Clark */ 492d756322SRob Clark 502d756322SRob Clark 512d756322SRob Clark enum a6xx_tile_mode { 522d756322SRob Clark TILE6_LINEAR = 0, 532d756322SRob Clark TILE6_2 = 2, 542d756322SRob Clark TILE6_3 = 3, 552d756322SRob Clark }; 562d756322SRob Clark 57c28c82e9SRob Clark enum a6xx_format { 58c28c82e9SRob Clark FMT6_A8_UNORM = 2, 59c28c82e9SRob Clark FMT6_8_UNORM = 3, 60c28c82e9SRob Clark FMT6_8_SNORM = 4, 61c28c82e9SRob Clark FMT6_8_UINT = 5, 62c28c82e9SRob Clark FMT6_8_SINT = 6, 63c28c82e9SRob Clark FMT6_4_4_4_4_UNORM = 8, 64c28c82e9SRob Clark FMT6_5_5_5_1_UNORM = 10, 65c28c82e9SRob Clark FMT6_1_5_5_5_UNORM = 12, 66c28c82e9SRob Clark FMT6_5_6_5_UNORM = 14, 67c28c82e9SRob Clark FMT6_8_8_UNORM = 15, 68c28c82e9SRob Clark FMT6_8_8_SNORM = 16, 69c28c82e9SRob Clark FMT6_8_8_UINT = 17, 70c28c82e9SRob Clark FMT6_8_8_SINT = 18, 71c28c82e9SRob Clark FMT6_L8_A8_UNORM = 19, 72c28c82e9SRob Clark FMT6_16_UNORM = 21, 73c28c82e9SRob Clark FMT6_16_SNORM = 22, 74c28c82e9SRob Clark FMT6_16_FLOAT = 23, 75c28c82e9SRob Clark FMT6_16_UINT = 24, 76c28c82e9SRob Clark FMT6_16_SINT = 25, 77c28c82e9SRob Clark FMT6_8_8_8_UNORM = 33, 78c28c82e9SRob Clark FMT6_8_8_8_SNORM = 34, 79c28c82e9SRob Clark FMT6_8_8_8_UINT = 35, 80c28c82e9SRob Clark FMT6_8_8_8_SINT = 36, 81c28c82e9SRob Clark FMT6_8_8_8_8_UNORM = 48, 82c28c82e9SRob Clark FMT6_8_8_8_X8_UNORM = 49, 83c28c82e9SRob Clark FMT6_8_8_8_8_SNORM = 50, 84c28c82e9SRob Clark FMT6_8_8_8_8_UINT = 51, 85c28c82e9SRob Clark FMT6_8_8_8_8_SINT = 52, 86c28c82e9SRob Clark FMT6_9_9_9_E5_FLOAT = 53, 87c28c82e9SRob Clark FMT6_10_10_10_2_UNORM = 54, 88c28c82e9SRob Clark FMT6_10_10_10_2_UNORM_DEST = 55, 89c28c82e9SRob Clark FMT6_10_10_10_2_SNORM = 57, 90c28c82e9SRob Clark FMT6_10_10_10_2_UINT = 58, 91c28c82e9SRob Clark FMT6_10_10_10_2_SINT = 59, 92c28c82e9SRob Clark FMT6_11_11_10_FLOAT = 66, 93c28c82e9SRob Clark FMT6_16_16_UNORM = 67, 94c28c82e9SRob Clark FMT6_16_16_SNORM = 68, 95c28c82e9SRob Clark FMT6_16_16_FLOAT = 69, 96c28c82e9SRob Clark FMT6_16_16_UINT = 70, 97c28c82e9SRob Clark FMT6_16_16_SINT = 71, 98c28c82e9SRob Clark FMT6_32_UNORM = 72, 99c28c82e9SRob Clark FMT6_32_SNORM = 73, 100c28c82e9SRob Clark FMT6_32_FLOAT = 74, 101c28c82e9SRob Clark FMT6_32_UINT = 75, 102c28c82e9SRob Clark FMT6_32_SINT = 76, 103c28c82e9SRob Clark FMT6_32_FIXED = 77, 104c28c82e9SRob Clark FMT6_16_16_16_UNORM = 88, 105c28c82e9SRob Clark FMT6_16_16_16_SNORM = 89, 106c28c82e9SRob Clark FMT6_16_16_16_FLOAT = 90, 107c28c82e9SRob Clark FMT6_16_16_16_UINT = 91, 108c28c82e9SRob Clark FMT6_16_16_16_SINT = 92, 109c28c82e9SRob Clark FMT6_16_16_16_16_UNORM = 96, 110c28c82e9SRob Clark FMT6_16_16_16_16_SNORM = 97, 111c28c82e9SRob Clark FMT6_16_16_16_16_FLOAT = 98, 112c28c82e9SRob Clark FMT6_16_16_16_16_UINT = 99, 113c28c82e9SRob Clark FMT6_16_16_16_16_SINT = 100, 114c28c82e9SRob Clark FMT6_32_32_UNORM = 101, 115c28c82e9SRob Clark FMT6_32_32_SNORM = 102, 116c28c82e9SRob Clark FMT6_32_32_FLOAT = 103, 117c28c82e9SRob Clark FMT6_32_32_UINT = 104, 118c28c82e9SRob Clark FMT6_32_32_SINT = 105, 119c28c82e9SRob Clark FMT6_32_32_FIXED = 106, 120c28c82e9SRob Clark FMT6_32_32_32_UNORM = 112, 121c28c82e9SRob Clark FMT6_32_32_32_SNORM = 113, 122c28c82e9SRob Clark FMT6_32_32_32_UINT = 114, 123c28c82e9SRob Clark FMT6_32_32_32_SINT = 115, 124c28c82e9SRob Clark FMT6_32_32_32_FLOAT = 116, 125c28c82e9SRob Clark FMT6_32_32_32_FIXED = 117, 126c28c82e9SRob Clark FMT6_32_32_32_32_UNORM = 128, 127c28c82e9SRob Clark FMT6_32_32_32_32_SNORM = 129, 128c28c82e9SRob Clark FMT6_32_32_32_32_FLOAT = 130, 129c28c82e9SRob Clark FMT6_32_32_32_32_UINT = 131, 130c28c82e9SRob Clark FMT6_32_32_32_32_SINT = 132, 131c28c82e9SRob Clark FMT6_32_32_32_32_FIXED = 133, 132c28c82e9SRob Clark FMT6_G8R8B8R8_422_UNORM = 140, 133c28c82e9SRob Clark FMT6_R8G8R8B8_422_UNORM = 141, 134c28c82e9SRob Clark FMT6_R8_G8B8_2PLANE_420_UNORM = 142, 135c28c82e9SRob Clark FMT6_R8_G8_B8_3PLANE_420_UNORM = 144, 136c28c82e9SRob Clark FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 = 145, 137c28c82e9SRob Clark FMT6_8_PLANE_UNORM = 148, 138c28c82e9SRob Clark FMT6_Z24_UNORM_S8_UINT = 160, 139c28c82e9SRob Clark FMT6_ETC2_RG11_UNORM = 171, 140c28c82e9SRob Clark FMT6_ETC2_RG11_SNORM = 172, 141c28c82e9SRob Clark FMT6_ETC2_R11_UNORM = 173, 142c28c82e9SRob Clark FMT6_ETC2_R11_SNORM = 174, 143c28c82e9SRob Clark FMT6_ETC1 = 175, 144c28c82e9SRob Clark FMT6_ETC2_RGB8 = 176, 145c28c82e9SRob Clark FMT6_ETC2_RGBA8 = 177, 146c28c82e9SRob Clark FMT6_ETC2_RGB8A1 = 178, 147c28c82e9SRob Clark FMT6_DXT1 = 179, 148c28c82e9SRob Clark FMT6_DXT3 = 180, 149c28c82e9SRob Clark FMT6_DXT5 = 181, 150c28c82e9SRob Clark FMT6_RGTC1_UNORM = 183, 151c28c82e9SRob Clark FMT6_RGTC1_SNORM = 184, 152c28c82e9SRob Clark FMT6_RGTC2_UNORM = 187, 153c28c82e9SRob Clark FMT6_RGTC2_SNORM = 188, 154c28c82e9SRob Clark FMT6_BPTC_UFLOAT = 190, 155c28c82e9SRob Clark FMT6_BPTC_FLOAT = 191, 156c28c82e9SRob Clark FMT6_BPTC = 192, 157c28c82e9SRob Clark FMT6_ASTC_4x4 = 193, 158c28c82e9SRob Clark FMT6_ASTC_5x4 = 194, 159c28c82e9SRob Clark FMT6_ASTC_5x5 = 195, 160c28c82e9SRob Clark FMT6_ASTC_6x5 = 196, 161c28c82e9SRob Clark FMT6_ASTC_6x6 = 197, 162c28c82e9SRob Clark FMT6_ASTC_8x5 = 198, 163c28c82e9SRob Clark FMT6_ASTC_8x6 = 199, 164c28c82e9SRob Clark FMT6_ASTC_8x8 = 200, 165c28c82e9SRob Clark FMT6_ASTC_10x5 = 201, 166c28c82e9SRob Clark FMT6_ASTC_10x6 = 202, 167c28c82e9SRob Clark FMT6_ASTC_10x8 = 203, 168c28c82e9SRob Clark FMT6_ASTC_10x10 = 204, 169c28c82e9SRob Clark FMT6_ASTC_12x10 = 205, 170c28c82e9SRob Clark FMT6_ASTC_12x12 = 206, 171c28c82e9SRob Clark FMT6_S8Z24_UINT = 234, 172c28c82e9SRob Clark FMT6_NONE = 255, 1732d756322SRob Clark }; 1742d756322SRob Clark 175c28c82e9SRob Clark enum a6xx_polygon_mode { 176c28c82e9SRob Clark POLYMODE6_POINTS = 1, 177c28c82e9SRob Clark POLYMODE6_LINES = 2, 178c28c82e9SRob Clark POLYMODE6_TRIANGLES = 3, 1792d756322SRob Clark }; 1802d756322SRob Clark 1812d756322SRob Clark enum a6xx_depth_format { 1822d756322SRob Clark DEPTH6_NONE = 0, 1832d756322SRob Clark DEPTH6_16 = 1, 1842d756322SRob Clark DEPTH6_24_8 = 2, 1852d756322SRob Clark DEPTH6_32 = 4, 1862d756322SRob Clark }; 1872d756322SRob Clark 188a69c5ed2SRob Clark enum a6xx_shader_id { 189a69c5ed2SRob Clark A6XX_TP0_TMO_DATA = 9, 190a69c5ed2SRob Clark A6XX_TP0_SMO_DATA = 10, 191a69c5ed2SRob Clark A6XX_TP0_MIPMAP_BASE_DATA = 11, 192a69c5ed2SRob Clark A6XX_TP1_TMO_DATA = 25, 193a69c5ed2SRob Clark A6XX_TP1_SMO_DATA = 26, 194a69c5ed2SRob Clark A6XX_TP1_MIPMAP_BASE_DATA = 27, 195a69c5ed2SRob Clark A6XX_SP_INST_DATA = 41, 196a69c5ed2SRob Clark A6XX_SP_LB_0_DATA = 42, 197a69c5ed2SRob Clark A6XX_SP_LB_1_DATA = 43, 198a69c5ed2SRob Clark A6XX_SP_LB_2_DATA = 44, 199a69c5ed2SRob Clark A6XX_SP_LB_3_DATA = 45, 200a69c5ed2SRob Clark A6XX_SP_LB_4_DATA = 46, 201a69c5ed2SRob Clark A6XX_SP_LB_5_DATA = 47, 202a69c5ed2SRob Clark A6XX_SP_CB_BINDLESS_DATA = 48, 203a69c5ed2SRob Clark A6XX_SP_CB_LEGACY_DATA = 49, 204a69c5ed2SRob Clark A6XX_SP_UAV_DATA = 50, 205a69c5ed2SRob Clark A6XX_SP_INST_TAG = 51, 206a69c5ed2SRob Clark A6XX_SP_CB_BINDLESS_TAG = 52, 207a69c5ed2SRob Clark A6XX_SP_TMO_UMO_TAG = 53, 208a69c5ed2SRob Clark A6XX_SP_SMO_TAG = 54, 209a69c5ed2SRob Clark A6XX_SP_STATE_DATA = 55, 210a69c5ed2SRob Clark A6XX_HLSQ_CHUNK_CVS_RAM = 73, 211a69c5ed2SRob Clark A6XX_HLSQ_CHUNK_CPS_RAM = 74, 212a69c5ed2SRob Clark A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75, 213a69c5ed2SRob Clark A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76, 214a69c5ed2SRob Clark A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77, 215a69c5ed2SRob Clark A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78, 216a69c5ed2SRob Clark A6XX_HLSQ_CVS_MISC_RAM = 80, 217a69c5ed2SRob Clark A6XX_HLSQ_CPS_MISC_RAM = 81, 218a69c5ed2SRob Clark A6XX_HLSQ_INST_RAM = 82, 219a69c5ed2SRob Clark A6XX_HLSQ_GFX_CVS_CONST_RAM = 83, 220a69c5ed2SRob Clark A6XX_HLSQ_GFX_CPS_CONST_RAM = 84, 221a69c5ed2SRob Clark A6XX_HLSQ_CVS_MISC_RAM_TAG = 85, 222a69c5ed2SRob Clark A6XX_HLSQ_CPS_MISC_RAM_TAG = 86, 223a69c5ed2SRob Clark A6XX_HLSQ_INST_RAM_TAG = 87, 224a69c5ed2SRob Clark A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88, 225a69c5ed2SRob Clark A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89, 226a69c5ed2SRob Clark A6XX_HLSQ_PWR_REST_RAM = 90, 227a69c5ed2SRob Clark A6XX_HLSQ_PWR_REST_TAG = 91, 228a69c5ed2SRob Clark A6XX_HLSQ_DATAPATH_META = 96, 229a69c5ed2SRob Clark A6XX_HLSQ_FRONTEND_META = 97, 230a69c5ed2SRob Clark A6XX_HLSQ_INDIRECT_META = 98, 231a69c5ed2SRob Clark A6XX_HLSQ_BACKEND_META = 99, 232a69c5ed2SRob Clark }; 233a69c5ed2SRob Clark 234a69c5ed2SRob Clark enum a6xx_debugbus_id { 235a69c5ed2SRob Clark A6XX_DBGBUS_CP = 1, 236a69c5ed2SRob Clark A6XX_DBGBUS_RBBM = 2, 237a69c5ed2SRob Clark A6XX_DBGBUS_VBIF = 3, 238a69c5ed2SRob Clark A6XX_DBGBUS_HLSQ = 4, 239a69c5ed2SRob Clark A6XX_DBGBUS_UCHE = 5, 240a69c5ed2SRob Clark A6XX_DBGBUS_DPM = 6, 241a69c5ed2SRob Clark A6XX_DBGBUS_TESS = 7, 242a69c5ed2SRob Clark A6XX_DBGBUS_PC = 8, 243a69c5ed2SRob Clark A6XX_DBGBUS_VFDP = 9, 244a69c5ed2SRob Clark A6XX_DBGBUS_VPC = 10, 245a69c5ed2SRob Clark A6XX_DBGBUS_TSE = 11, 246a69c5ed2SRob Clark A6XX_DBGBUS_RAS = 12, 247a69c5ed2SRob Clark A6XX_DBGBUS_VSC = 13, 248a69c5ed2SRob Clark A6XX_DBGBUS_COM = 14, 249a69c5ed2SRob Clark A6XX_DBGBUS_LRZ = 16, 250a69c5ed2SRob Clark A6XX_DBGBUS_A2D = 17, 251a69c5ed2SRob Clark A6XX_DBGBUS_CCUFCHE = 18, 252a69c5ed2SRob Clark A6XX_DBGBUS_GMU_CX = 19, 253a69c5ed2SRob Clark A6XX_DBGBUS_RBP = 20, 254a69c5ed2SRob Clark A6XX_DBGBUS_DCS = 21, 255a69c5ed2SRob Clark A6XX_DBGBUS_DBGC = 22, 256a69c5ed2SRob Clark A6XX_DBGBUS_CX = 23, 257a69c5ed2SRob Clark A6XX_DBGBUS_GMU_GX = 24, 258a69c5ed2SRob Clark A6XX_DBGBUS_TPFCHE = 25, 259a69c5ed2SRob Clark A6XX_DBGBUS_GBIF_GX = 26, 260a69c5ed2SRob Clark A6XX_DBGBUS_GPC = 29, 261a69c5ed2SRob Clark A6XX_DBGBUS_LARC = 30, 262a69c5ed2SRob Clark A6XX_DBGBUS_HLSQ_SPTP = 31, 263a69c5ed2SRob Clark A6XX_DBGBUS_RB_0 = 32, 264a69c5ed2SRob Clark A6XX_DBGBUS_RB_1 = 33, 265a69c5ed2SRob Clark A6XX_DBGBUS_UCHE_WRAPPER = 36, 266a69c5ed2SRob Clark A6XX_DBGBUS_CCU_0 = 40, 267a69c5ed2SRob Clark A6XX_DBGBUS_CCU_1 = 41, 268a69c5ed2SRob Clark A6XX_DBGBUS_VFD_0 = 56, 269a69c5ed2SRob Clark A6XX_DBGBUS_VFD_1 = 57, 270a69c5ed2SRob Clark A6XX_DBGBUS_VFD_2 = 58, 271a69c5ed2SRob Clark A6XX_DBGBUS_VFD_3 = 59, 272a69c5ed2SRob Clark A6XX_DBGBUS_SP_0 = 64, 273a69c5ed2SRob Clark A6XX_DBGBUS_SP_1 = 65, 274a69c5ed2SRob Clark A6XX_DBGBUS_TPL1_0 = 72, 275a69c5ed2SRob Clark A6XX_DBGBUS_TPL1_1 = 73, 276a69c5ed2SRob Clark A6XX_DBGBUS_TPL1_2 = 74, 277a69c5ed2SRob Clark A6XX_DBGBUS_TPL1_3 = 75, 278a69c5ed2SRob Clark }; 279a69c5ed2SRob Clark 2802d756322SRob Clark enum a6xx_cp_perfcounter_select { 2812d756322SRob Clark PERF_CP_ALWAYS_COUNT = 0, 282a69c5ed2SRob Clark PERF_CP_BUSY_GFX_CORE_IDLE = 1, 283a69c5ed2SRob Clark PERF_CP_BUSY_CYCLES = 2, 284a69c5ed2SRob Clark PERF_CP_NUM_PREEMPTIONS = 3, 285a69c5ed2SRob Clark PERF_CP_PREEMPTION_REACTION_DELAY = 4, 286a69c5ed2SRob Clark PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 5, 287a69c5ed2SRob Clark PERF_CP_PREEMPTION_SWITCH_IN_TIME = 6, 288a69c5ed2SRob Clark PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 7, 289a69c5ed2SRob Clark PERF_CP_PREDICATED_DRAWS_KILLED = 8, 290a69c5ed2SRob Clark PERF_CP_MODE_SWITCH = 9, 291a69c5ed2SRob Clark PERF_CP_ZPASS_DONE = 10, 292a69c5ed2SRob Clark PERF_CP_CONTEXT_DONE = 11, 293a69c5ed2SRob Clark PERF_CP_CACHE_FLUSH = 12, 294a69c5ed2SRob Clark PERF_CP_LONG_PREEMPTIONS = 13, 295a69c5ed2SRob Clark PERF_CP_SQE_I_CACHE_STARVE = 14, 296a69c5ed2SRob Clark PERF_CP_SQE_IDLE = 15, 297a69c5ed2SRob Clark PERF_CP_SQE_PM4_STARVE_RB_IB = 16, 298a69c5ed2SRob Clark PERF_CP_SQE_PM4_STARVE_SDS = 17, 299a69c5ed2SRob Clark PERF_CP_SQE_MRB_STARVE = 18, 300a69c5ed2SRob Clark PERF_CP_SQE_RRB_STARVE = 19, 301a69c5ed2SRob Clark PERF_CP_SQE_VSD_STARVE = 20, 302a69c5ed2SRob Clark PERF_CP_VSD_DECODE_STARVE = 21, 303a69c5ed2SRob Clark PERF_CP_SQE_PIPE_OUT_STALL = 22, 304a69c5ed2SRob Clark PERF_CP_SQE_SYNC_STALL = 23, 305a69c5ed2SRob Clark PERF_CP_SQE_PM4_WFI_STALL = 24, 306a69c5ed2SRob Clark PERF_CP_SQE_SYS_WFI_STALL = 25, 307a69c5ed2SRob Clark PERF_CP_SQE_T4_EXEC = 26, 308a69c5ed2SRob Clark PERF_CP_SQE_LOAD_STATE_EXEC = 27, 309a69c5ed2SRob Clark PERF_CP_SQE_SAVE_SDS_STATE = 28, 310a69c5ed2SRob Clark PERF_CP_SQE_DRAW_EXEC = 29, 311a69c5ed2SRob Clark PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 30, 312a69c5ed2SRob Clark PERF_CP_SQE_EXEC_PROFILED = 31, 313a69c5ed2SRob Clark PERF_CP_MEMORY_POOL_EMPTY = 32, 314a69c5ed2SRob Clark PERF_CP_MEMORY_POOL_SYNC_STALL = 33, 315a69c5ed2SRob Clark PERF_CP_MEMORY_POOL_ABOVE_THRESH = 34, 316a69c5ed2SRob Clark PERF_CP_AHB_WR_STALL_PRE_DRAWS = 35, 317a69c5ed2SRob Clark PERF_CP_AHB_STALL_SQE_GMU = 36, 318a69c5ed2SRob Clark PERF_CP_AHB_STALL_SQE_WR_OTHER = 37, 319a69c5ed2SRob Clark PERF_CP_AHB_STALL_SQE_RD_OTHER = 38, 320a69c5ed2SRob Clark PERF_CP_CLUSTER0_EMPTY = 39, 321a69c5ed2SRob Clark PERF_CP_CLUSTER1_EMPTY = 40, 322a69c5ed2SRob Clark PERF_CP_CLUSTER2_EMPTY = 41, 323a69c5ed2SRob Clark PERF_CP_CLUSTER3_EMPTY = 42, 324a69c5ed2SRob Clark PERF_CP_CLUSTER4_EMPTY = 43, 325a69c5ed2SRob Clark PERF_CP_CLUSTER5_EMPTY = 44, 326a69c5ed2SRob Clark PERF_CP_PM4_DATA = 45, 327a69c5ed2SRob Clark PERF_CP_PM4_HEADERS = 46, 328a69c5ed2SRob Clark PERF_CP_VBIF_READ_BEATS = 47, 329a69c5ed2SRob Clark PERF_CP_VBIF_WRITE_BEATS = 48, 330a69c5ed2SRob Clark PERF_CP_SQE_INSTR_COUNTER = 49, 331a69c5ed2SRob Clark }; 332a69c5ed2SRob Clark 333a69c5ed2SRob Clark enum a6xx_rbbm_perfcounter_select { 334a69c5ed2SRob Clark PERF_RBBM_ALWAYS_COUNT = 0, 335a69c5ed2SRob Clark PERF_RBBM_ALWAYS_ON = 1, 336a69c5ed2SRob Clark PERF_RBBM_TSE_BUSY = 2, 337a69c5ed2SRob Clark PERF_RBBM_RAS_BUSY = 3, 338a69c5ed2SRob Clark PERF_RBBM_PC_DCALL_BUSY = 4, 339a69c5ed2SRob Clark PERF_RBBM_PC_VSD_BUSY = 5, 340a69c5ed2SRob Clark PERF_RBBM_STATUS_MASKED = 6, 341a69c5ed2SRob Clark PERF_RBBM_COM_BUSY = 7, 342a69c5ed2SRob Clark PERF_RBBM_DCOM_BUSY = 8, 343a69c5ed2SRob Clark PERF_RBBM_VBIF_BUSY = 9, 344a69c5ed2SRob Clark PERF_RBBM_VSC_BUSY = 10, 345a69c5ed2SRob Clark PERF_RBBM_TESS_BUSY = 11, 346a69c5ed2SRob Clark PERF_RBBM_UCHE_BUSY = 12, 347a69c5ed2SRob Clark PERF_RBBM_HLSQ_BUSY = 13, 348a69c5ed2SRob Clark }; 349a69c5ed2SRob Clark 350a69c5ed2SRob Clark enum a6xx_pc_perfcounter_select { 351a69c5ed2SRob Clark PERF_PC_BUSY_CYCLES = 0, 352a69c5ed2SRob Clark PERF_PC_WORKING_CYCLES = 1, 353a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_VFD = 2, 354a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_TSE = 3, 355a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_VPC = 4, 356a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_UCHE = 5, 357a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_TESS = 6, 358a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_TSE_ONLY = 7, 359a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_VPC_ONLY = 8, 360a69c5ed2SRob Clark PERF_PC_PASS1_TF_STALL_CYCLES = 9, 361a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_FOR_INDEX = 10, 362a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11, 363a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12, 364a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_FOR_POSITION = 13, 365a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_DI = 14, 366a69c5ed2SRob Clark PERF_PC_VIS_STREAMS_LOADED = 15, 367a69c5ed2SRob Clark PERF_PC_INSTANCES = 16, 368a69c5ed2SRob Clark PERF_PC_VPC_PRIMITIVES = 17, 369a69c5ed2SRob Clark PERF_PC_DEAD_PRIM = 18, 370a69c5ed2SRob Clark PERF_PC_LIVE_PRIM = 19, 371a69c5ed2SRob Clark PERF_PC_VERTEX_HITS = 20, 372a69c5ed2SRob Clark PERF_PC_IA_VERTICES = 21, 373a69c5ed2SRob Clark PERF_PC_IA_PRIMITIVES = 22, 374a69c5ed2SRob Clark PERF_PC_GS_PRIMITIVES = 23, 375a69c5ed2SRob Clark PERF_PC_HS_INVOCATIONS = 24, 376a69c5ed2SRob Clark PERF_PC_DS_INVOCATIONS = 25, 377a69c5ed2SRob Clark PERF_PC_VS_INVOCATIONS = 26, 378a69c5ed2SRob Clark PERF_PC_GS_INVOCATIONS = 27, 379a69c5ed2SRob Clark PERF_PC_DS_PRIMITIVES = 28, 380a69c5ed2SRob Clark PERF_PC_VPC_POS_DATA_TRANSACTION = 29, 381a69c5ed2SRob Clark PERF_PC_3D_DRAWCALLS = 30, 382a69c5ed2SRob Clark PERF_PC_2D_DRAWCALLS = 31, 383a69c5ed2SRob Clark PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32, 384a69c5ed2SRob Clark PERF_TESS_BUSY_CYCLES = 33, 385a69c5ed2SRob Clark PERF_TESS_WORKING_CYCLES = 34, 386a69c5ed2SRob Clark PERF_TESS_STALL_CYCLES_PC = 35, 387a69c5ed2SRob Clark PERF_TESS_STARVE_CYCLES_PC = 36, 388a69c5ed2SRob Clark PERF_PC_TSE_TRANSACTION = 37, 389a69c5ed2SRob Clark PERF_PC_TSE_VERTEX = 38, 390a69c5ed2SRob Clark PERF_PC_TESS_PC_UV_TRANS = 39, 391a69c5ed2SRob Clark PERF_PC_TESS_PC_UV_PATCHES = 40, 392a69c5ed2SRob Clark PERF_PC_TESS_FACTOR_TRANS = 41, 393a69c5ed2SRob Clark }; 394a69c5ed2SRob Clark 395a69c5ed2SRob Clark enum a6xx_vfd_perfcounter_select { 396a69c5ed2SRob Clark PERF_VFD_BUSY_CYCLES = 0, 397a69c5ed2SRob Clark PERF_VFD_STALL_CYCLES_UCHE = 1, 398a69c5ed2SRob Clark PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2, 399a69c5ed2SRob Clark PERF_VFD_STALL_CYCLES_SP_INFO = 3, 400a69c5ed2SRob Clark PERF_VFD_STALL_CYCLES_SP_ATTR = 4, 401a69c5ed2SRob Clark PERF_VFD_STARVE_CYCLES_UCHE = 5, 402a69c5ed2SRob Clark PERF_VFD_RBUFFER_FULL = 6, 403a69c5ed2SRob Clark PERF_VFD_ATTR_INFO_FIFO_FULL = 7, 404a69c5ed2SRob Clark PERF_VFD_DECODED_ATTRIBUTE_BYTES = 8, 405a69c5ed2SRob Clark PERF_VFD_NUM_ATTRIBUTES = 9, 406a69c5ed2SRob Clark PERF_VFD_UPPER_SHADER_FIBERS = 10, 407a69c5ed2SRob Clark PERF_VFD_LOWER_SHADER_FIBERS = 11, 408a69c5ed2SRob Clark PERF_VFD_MODE_0_FIBERS = 12, 409a69c5ed2SRob Clark PERF_VFD_MODE_1_FIBERS = 13, 410a69c5ed2SRob Clark PERF_VFD_MODE_2_FIBERS = 14, 411a69c5ed2SRob Clark PERF_VFD_MODE_3_FIBERS = 15, 412a69c5ed2SRob Clark PERF_VFD_MODE_4_FIBERS = 16, 413a69c5ed2SRob Clark PERF_VFD_TOTAL_VERTICES = 17, 414a69c5ed2SRob Clark PERF_VFDP_STALL_CYCLES_VFD = 18, 415a69c5ed2SRob Clark PERF_VFDP_STALL_CYCLES_VFD_INDEX = 19, 416a69c5ed2SRob Clark PERF_VFDP_STALL_CYCLES_VFD_PROG = 20, 417a69c5ed2SRob Clark PERF_VFDP_STARVE_CYCLES_PC = 21, 418a69c5ed2SRob Clark PERF_VFDP_VS_STAGE_WAVES = 22, 419a69c5ed2SRob Clark }; 420a69c5ed2SRob Clark 421ccdf7e28SRob Clark enum a6xx_hlsq_perfcounter_select { 422a69c5ed2SRob Clark PERF_HLSQ_BUSY_CYCLES = 0, 423a69c5ed2SRob Clark PERF_HLSQ_STALL_CYCLES_UCHE = 1, 424a69c5ed2SRob Clark PERF_HLSQ_STALL_CYCLES_SP_STATE = 2, 425a69c5ed2SRob Clark PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3, 426a69c5ed2SRob Clark PERF_HLSQ_UCHE_LATENCY_CYCLES = 4, 427a69c5ed2SRob Clark PERF_HLSQ_UCHE_LATENCY_COUNT = 5, 428a69c5ed2SRob Clark PERF_HLSQ_FS_STAGE_1X_WAVES = 6, 429a69c5ed2SRob Clark PERF_HLSQ_FS_STAGE_2X_WAVES = 7, 430a69c5ed2SRob Clark PERF_HLSQ_QUADS = 8, 431a69c5ed2SRob Clark PERF_HLSQ_CS_INVOCATIONS = 9, 432a69c5ed2SRob Clark PERF_HLSQ_COMPUTE_DRAWCALLS = 10, 433a69c5ed2SRob Clark PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11, 434a69c5ed2SRob Clark PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12, 435a69c5ed2SRob Clark PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13, 436a69c5ed2SRob Clark PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14, 437a69c5ed2SRob Clark PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15, 438a69c5ed2SRob Clark PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16, 439a69c5ed2SRob Clark PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17, 440a69c5ed2SRob Clark PERF_HLSQ_STALL_CYCLES_VPC = 18, 441a69c5ed2SRob Clark PERF_HLSQ_PIXELS = 19, 442a69c5ed2SRob Clark PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = 20, 443a69c5ed2SRob Clark }; 444a69c5ed2SRob Clark 445a69c5ed2SRob Clark enum a6xx_vpc_perfcounter_select { 446a69c5ed2SRob Clark PERF_VPC_BUSY_CYCLES = 0, 447a69c5ed2SRob Clark PERF_VPC_WORKING_CYCLES = 1, 448a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_UCHE = 2, 449a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_VFD_WACK = 3, 450a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4, 451a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_PC = 5, 452a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_SP_LM = 6, 453a69c5ed2SRob Clark PERF_VPC_STARVE_CYCLES_SP = 7, 454a69c5ed2SRob Clark PERF_VPC_STARVE_CYCLES_LRZ = 8, 455a69c5ed2SRob Clark PERF_VPC_PC_PRIMITIVES = 9, 456a69c5ed2SRob Clark PERF_VPC_SP_COMPONENTS = 10, 457a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_VPCRAM_POS = 11, 458a69c5ed2SRob Clark PERF_VPC_LRZ_ASSIGN_PRIMITIVES = 12, 459a69c5ed2SRob Clark PERF_VPC_RB_VISIBLE_PRIMITIVES = 13, 460a69c5ed2SRob Clark PERF_VPC_LM_TRANSACTION = 14, 461a69c5ed2SRob Clark PERF_VPC_STREAMOUT_TRANSACTION = 15, 462a69c5ed2SRob Clark PERF_VPC_VS_BUSY_CYCLES = 16, 463a69c5ed2SRob Clark PERF_VPC_PS_BUSY_CYCLES = 17, 464a69c5ed2SRob Clark PERF_VPC_VS_WORKING_CYCLES = 18, 465a69c5ed2SRob Clark PERF_VPC_PS_WORKING_CYCLES = 19, 466a69c5ed2SRob Clark PERF_VPC_STARVE_CYCLES_RB = 20, 467a69c5ed2SRob Clark PERF_VPC_NUM_VPCRAM_READ_POS = 21, 468a69c5ed2SRob Clark PERF_VPC_WIT_FULL_CYCLES = 22, 469a69c5ed2SRob Clark PERF_VPC_VPCRAM_FULL_CYCLES = 23, 470a69c5ed2SRob Clark PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = 24, 471a69c5ed2SRob Clark PERF_VPC_NUM_VPCRAM_WRITE = 25, 472a69c5ed2SRob Clark PERF_VPC_NUM_VPCRAM_READ_SO = 26, 473a69c5ed2SRob Clark PERF_VPC_NUM_ATTR_REQ_LM = 27, 474a69c5ed2SRob Clark }; 475a69c5ed2SRob Clark 476a69c5ed2SRob Clark enum a6xx_tse_perfcounter_select { 477a69c5ed2SRob Clark PERF_TSE_BUSY_CYCLES = 0, 478a69c5ed2SRob Clark PERF_TSE_CLIPPING_CYCLES = 1, 479a69c5ed2SRob Clark PERF_TSE_STALL_CYCLES_RAS = 2, 480a69c5ed2SRob Clark PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3, 481a69c5ed2SRob Clark PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4, 482a69c5ed2SRob Clark PERF_TSE_STARVE_CYCLES_PC = 5, 483a69c5ed2SRob Clark PERF_TSE_INPUT_PRIM = 6, 484a69c5ed2SRob Clark PERF_TSE_INPUT_NULL_PRIM = 7, 485a69c5ed2SRob Clark PERF_TSE_TRIVAL_REJ_PRIM = 8, 486a69c5ed2SRob Clark PERF_TSE_CLIPPED_PRIM = 9, 487a69c5ed2SRob Clark PERF_TSE_ZERO_AREA_PRIM = 10, 488a69c5ed2SRob Clark PERF_TSE_FACENESS_CULLED_PRIM = 11, 489a69c5ed2SRob Clark PERF_TSE_ZERO_PIXEL_PRIM = 12, 490a69c5ed2SRob Clark PERF_TSE_OUTPUT_NULL_PRIM = 13, 491a69c5ed2SRob Clark PERF_TSE_OUTPUT_VISIBLE_PRIM = 14, 492a69c5ed2SRob Clark PERF_TSE_CINVOCATION = 15, 493a69c5ed2SRob Clark PERF_TSE_CPRIMITIVES = 16, 494a69c5ed2SRob Clark PERF_TSE_2D_INPUT_PRIM = 17, 495a69c5ed2SRob Clark PERF_TSE_2D_ALIVE_CYCLES = 18, 496a69c5ed2SRob Clark PERF_TSE_CLIP_PLANES = 19, 497a69c5ed2SRob Clark }; 498a69c5ed2SRob Clark 499a69c5ed2SRob Clark enum a6xx_ras_perfcounter_select { 500a69c5ed2SRob Clark PERF_RAS_BUSY_CYCLES = 0, 501a69c5ed2SRob Clark PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1, 502a69c5ed2SRob Clark PERF_RAS_STALL_CYCLES_LRZ = 2, 503a69c5ed2SRob Clark PERF_RAS_STARVE_CYCLES_TSE = 3, 504a69c5ed2SRob Clark PERF_RAS_SUPER_TILES = 4, 505a69c5ed2SRob Clark PERF_RAS_8X4_TILES = 5, 506a69c5ed2SRob Clark PERF_RAS_MASKGEN_ACTIVE = 6, 507a69c5ed2SRob Clark PERF_RAS_FULLY_COVERED_SUPER_TILES = 7, 508a69c5ed2SRob Clark PERF_RAS_FULLY_COVERED_8X4_TILES = 8, 509a69c5ed2SRob Clark PERF_RAS_PRIM_KILLED_INVISILBE = 9, 510a69c5ed2SRob Clark PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 10, 511a69c5ed2SRob Clark PERF_RAS_LRZ_INTF_WORKING_CYCLES = 11, 512a69c5ed2SRob Clark PERF_RAS_BLOCKS = 12, 513a69c5ed2SRob Clark }; 514a69c5ed2SRob Clark 515a69c5ed2SRob Clark enum a6xx_uche_perfcounter_select { 516a69c5ed2SRob Clark PERF_UCHE_BUSY_CYCLES = 0, 517a69c5ed2SRob Clark PERF_UCHE_STALL_CYCLES_ARBITER = 1, 518a69c5ed2SRob Clark PERF_UCHE_VBIF_LATENCY_CYCLES = 2, 519a69c5ed2SRob Clark PERF_UCHE_VBIF_LATENCY_SAMPLES = 3, 520a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_TP = 4, 521a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_VFD = 5, 522a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6, 523a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_LRZ = 7, 524a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_SP = 8, 525a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_TP = 9, 526a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_VFD = 10, 527a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_HLSQ = 11, 528a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_LRZ = 12, 529a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_SP = 13, 530a69c5ed2SRob Clark PERF_UCHE_WRITE_REQUESTS_LRZ = 14, 531a69c5ed2SRob Clark PERF_UCHE_WRITE_REQUESTS_SP = 15, 532a69c5ed2SRob Clark PERF_UCHE_WRITE_REQUESTS_VPC = 16, 533a69c5ed2SRob Clark PERF_UCHE_WRITE_REQUESTS_VSC = 17, 534a69c5ed2SRob Clark PERF_UCHE_EVICTS = 18, 535a69c5ed2SRob Clark PERF_UCHE_BANK_REQ0 = 19, 536a69c5ed2SRob Clark PERF_UCHE_BANK_REQ1 = 20, 537a69c5ed2SRob Clark PERF_UCHE_BANK_REQ2 = 21, 538a69c5ed2SRob Clark PERF_UCHE_BANK_REQ3 = 22, 539a69c5ed2SRob Clark PERF_UCHE_BANK_REQ4 = 23, 540a69c5ed2SRob Clark PERF_UCHE_BANK_REQ5 = 24, 541a69c5ed2SRob Clark PERF_UCHE_BANK_REQ6 = 25, 542a69c5ed2SRob Clark PERF_UCHE_BANK_REQ7 = 26, 543a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_CH0 = 27, 544a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_CH1 = 28, 545a69c5ed2SRob Clark PERF_UCHE_GMEM_READ_BEATS = 29, 546a69c5ed2SRob Clark PERF_UCHE_TPH_REF_FULL = 30, 547a69c5ed2SRob Clark PERF_UCHE_TPH_VICTIM_FULL = 31, 548a69c5ed2SRob Clark PERF_UCHE_TPH_EXT_FULL = 32, 549a69c5ed2SRob Clark PERF_UCHE_VBIF_STALL_WRITE_DATA = 33, 550a69c5ed2SRob Clark PERF_UCHE_DCMP_LATENCY_SAMPLES = 34, 551a69c5ed2SRob Clark PERF_UCHE_DCMP_LATENCY_CYCLES = 35, 552a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_PC = 36, 553a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_PC = 37, 554a69c5ed2SRob Clark PERF_UCHE_RAM_READ_REQ = 38, 555a69c5ed2SRob Clark PERF_UCHE_RAM_WRITE_REQ = 39, 556a69c5ed2SRob Clark }; 557a69c5ed2SRob Clark 558a69c5ed2SRob Clark enum a6xx_tp_perfcounter_select { 559a69c5ed2SRob Clark PERF_TP_BUSY_CYCLES = 0, 560a69c5ed2SRob Clark PERF_TP_STALL_CYCLES_UCHE = 1, 561a69c5ed2SRob Clark PERF_TP_LATENCY_CYCLES = 2, 562a69c5ed2SRob Clark PERF_TP_LATENCY_TRANS = 3, 563a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4, 564a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5, 565a69c5ed2SRob Clark PERF_TP_L1_CACHELINE_REQUESTS = 6, 566a69c5ed2SRob Clark PERF_TP_L1_CACHELINE_MISSES = 7, 567a69c5ed2SRob Clark PERF_TP_SP_TP_TRANS = 8, 568a69c5ed2SRob Clark PERF_TP_TP_SP_TRANS = 9, 569a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS = 10, 570a69c5ed2SRob Clark PERF_TP_FILTER_WORKLOAD_16BIT = 11, 571a69c5ed2SRob Clark PERF_TP_FILTER_WORKLOAD_32BIT = 12, 572a69c5ed2SRob Clark PERF_TP_QUADS_RECEIVED = 13, 573a69c5ed2SRob Clark PERF_TP_QUADS_OFFSET = 14, 574a69c5ed2SRob Clark PERF_TP_QUADS_SHADOW = 15, 575a69c5ed2SRob Clark PERF_TP_QUADS_ARRAY = 16, 576a69c5ed2SRob Clark PERF_TP_QUADS_GRADIENT = 17, 577a69c5ed2SRob Clark PERF_TP_QUADS_1D = 18, 578a69c5ed2SRob Clark PERF_TP_QUADS_2D = 19, 579a69c5ed2SRob Clark PERF_TP_QUADS_BUFFER = 20, 580a69c5ed2SRob Clark PERF_TP_QUADS_3D = 21, 581a69c5ed2SRob Clark PERF_TP_QUADS_CUBE = 22, 582a69c5ed2SRob Clark PERF_TP_DIVERGENT_QUADS_RECEIVED = 23, 583a69c5ed2SRob Clark PERF_TP_PRT_NON_RESIDENT_EVENTS = 24, 584a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_POINT = 25, 585a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_BILINEAR = 26, 586a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_MIP = 27, 587a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_ANISO = 28, 588a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 29, 589a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_REQUESTS = 30, 590a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_MISSES = 31, 591a69c5ed2SRob Clark PERF_TP_L1_5_L2_REQUESTS = 32, 592a69c5ed2SRob Clark PERF_TP_2D_OUTPUT_PIXELS = 33, 593a69c5ed2SRob Clark PERF_TP_2D_OUTPUT_PIXELS_POINT = 34, 594a69c5ed2SRob Clark PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 35, 595a69c5ed2SRob Clark PERF_TP_2D_FILTER_WORKLOAD_16BIT = 36, 596a69c5ed2SRob Clark PERF_TP_2D_FILTER_WORKLOAD_32BIT = 37, 597a69c5ed2SRob Clark PERF_TP_TPA2TPC_TRANS = 38, 598a69c5ed2SRob Clark PERF_TP_L1_MISSES_ASTC_1TILE = 39, 599a69c5ed2SRob Clark PERF_TP_L1_MISSES_ASTC_2TILE = 40, 600a69c5ed2SRob Clark PERF_TP_L1_MISSES_ASTC_4TILE = 41, 601a69c5ed2SRob Clark PERF_TP_L1_5_L2_COMPRESS_REQS = 42, 602a69c5ed2SRob Clark PERF_TP_L1_5_L2_COMPRESS_MISS = 43, 603a69c5ed2SRob Clark PERF_TP_L1_BANK_CONFLICT = 44, 604a69c5ed2SRob Clark PERF_TP_L1_5_MISS_LATENCY_CYCLES = 45, 605a69c5ed2SRob Clark PERF_TP_L1_5_MISS_LATENCY_TRANS = 46, 606a69c5ed2SRob Clark PERF_TP_QUADS_CONSTANT_MULTIPLIED = 47, 607a69c5ed2SRob Clark PERF_TP_FRONTEND_WORKING_CYCLES = 48, 608a69c5ed2SRob Clark PERF_TP_L1_TAG_WORKING_CYCLES = 49, 609a69c5ed2SRob Clark PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 50, 610a69c5ed2SRob Clark PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 51, 611a69c5ed2SRob Clark PERF_TP_BACKEND_WORKING_CYCLES = 52, 612a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_WORKING_CYCLES = 53, 613a69c5ed2SRob Clark PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54, 614a69c5ed2SRob Clark PERF_TP_STARVE_CYCLES_SP = 55, 615a69c5ed2SRob Clark PERF_TP_STARVE_CYCLES_UCHE = 56, 616a69c5ed2SRob Clark }; 617a69c5ed2SRob Clark 618a69c5ed2SRob Clark enum a6xx_sp_perfcounter_select { 619a69c5ed2SRob Clark PERF_SP_BUSY_CYCLES = 0, 620a69c5ed2SRob Clark PERF_SP_ALU_WORKING_CYCLES = 1, 621a69c5ed2SRob Clark PERF_SP_EFU_WORKING_CYCLES = 2, 622a69c5ed2SRob Clark PERF_SP_STALL_CYCLES_VPC = 3, 623a69c5ed2SRob Clark PERF_SP_STALL_CYCLES_TP = 4, 624a69c5ed2SRob Clark PERF_SP_STALL_CYCLES_UCHE = 5, 625a69c5ed2SRob Clark PERF_SP_STALL_CYCLES_RB = 6, 626a69c5ed2SRob Clark PERF_SP_NON_EXECUTION_CYCLES = 7, 627a69c5ed2SRob Clark PERF_SP_WAVE_CONTEXTS = 8, 628a69c5ed2SRob Clark PERF_SP_WAVE_CONTEXT_CYCLES = 9, 629a69c5ed2SRob Clark PERF_SP_FS_STAGE_WAVE_CYCLES = 10, 630a69c5ed2SRob Clark PERF_SP_FS_STAGE_WAVE_SAMPLES = 11, 631a69c5ed2SRob Clark PERF_SP_VS_STAGE_WAVE_CYCLES = 12, 632a69c5ed2SRob Clark PERF_SP_VS_STAGE_WAVE_SAMPLES = 13, 633a69c5ed2SRob Clark PERF_SP_FS_STAGE_DURATION_CYCLES = 14, 634a69c5ed2SRob Clark PERF_SP_VS_STAGE_DURATION_CYCLES = 15, 635a69c5ed2SRob Clark PERF_SP_WAVE_CTRL_CYCLES = 16, 636a69c5ed2SRob Clark PERF_SP_WAVE_LOAD_CYCLES = 17, 637a69c5ed2SRob Clark PERF_SP_WAVE_EMIT_CYCLES = 18, 638a69c5ed2SRob Clark PERF_SP_WAVE_NOP_CYCLES = 19, 639a69c5ed2SRob Clark PERF_SP_WAVE_WAIT_CYCLES = 20, 640a69c5ed2SRob Clark PERF_SP_WAVE_FETCH_CYCLES = 21, 641a69c5ed2SRob Clark PERF_SP_WAVE_IDLE_CYCLES = 22, 642a69c5ed2SRob Clark PERF_SP_WAVE_END_CYCLES = 23, 643a69c5ed2SRob Clark PERF_SP_WAVE_LONG_SYNC_CYCLES = 24, 644a69c5ed2SRob Clark PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25, 645a69c5ed2SRob Clark PERF_SP_WAVE_JOIN_CYCLES = 26, 646a69c5ed2SRob Clark PERF_SP_LM_LOAD_INSTRUCTIONS = 27, 647a69c5ed2SRob Clark PERF_SP_LM_STORE_INSTRUCTIONS = 28, 648a69c5ed2SRob Clark PERF_SP_LM_ATOMICS = 29, 649a69c5ed2SRob Clark PERF_SP_GM_LOAD_INSTRUCTIONS = 30, 650a69c5ed2SRob Clark PERF_SP_GM_STORE_INSTRUCTIONS = 31, 651a69c5ed2SRob Clark PERF_SP_GM_ATOMICS = 32, 652a69c5ed2SRob Clark PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33, 653a69c5ed2SRob Clark PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34, 654a69c5ed2SRob Clark PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35, 655a69c5ed2SRob Clark PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36, 656a69c5ed2SRob Clark PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37, 657a69c5ed2SRob Clark PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38, 658a69c5ed2SRob Clark PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39, 659a69c5ed2SRob Clark PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40, 660a69c5ed2SRob Clark PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41, 661a69c5ed2SRob Clark PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42, 662a69c5ed2SRob Clark PERF_SP_VS_INSTRUCTIONS = 43, 663a69c5ed2SRob Clark PERF_SP_FS_INSTRUCTIONS = 44, 664a69c5ed2SRob Clark PERF_SP_ADDR_LOCK_COUNT = 45, 665a69c5ed2SRob Clark PERF_SP_UCHE_READ_TRANS = 46, 666a69c5ed2SRob Clark PERF_SP_UCHE_WRITE_TRANS = 47, 667a69c5ed2SRob Clark PERF_SP_EXPORT_VPC_TRANS = 48, 668a69c5ed2SRob Clark PERF_SP_EXPORT_RB_TRANS = 49, 669a69c5ed2SRob Clark PERF_SP_PIXELS_KILLED = 50, 670a69c5ed2SRob Clark PERF_SP_ICL1_REQUESTS = 51, 671a69c5ed2SRob Clark PERF_SP_ICL1_MISSES = 52, 672a69c5ed2SRob Clark PERF_SP_HS_INSTRUCTIONS = 53, 673a69c5ed2SRob Clark PERF_SP_DS_INSTRUCTIONS = 54, 674a69c5ed2SRob Clark PERF_SP_GS_INSTRUCTIONS = 55, 675a69c5ed2SRob Clark PERF_SP_CS_INSTRUCTIONS = 56, 676a69c5ed2SRob Clark PERF_SP_GPR_READ = 57, 677a69c5ed2SRob Clark PERF_SP_GPR_WRITE = 58, 678a69c5ed2SRob Clark PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59, 679a69c5ed2SRob Clark PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60, 680a69c5ed2SRob Clark PERF_SP_LM_BANK_CONFLICTS = 61, 681a69c5ed2SRob Clark PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62, 682a69c5ed2SRob Clark PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63, 683a69c5ed2SRob Clark PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64, 684a69c5ed2SRob Clark PERF_SP_LM_WORKING_CYCLES = 65, 685a69c5ed2SRob Clark PERF_SP_DISPATCHER_WORKING_CYCLES = 66, 686a69c5ed2SRob Clark PERF_SP_SEQUENCER_WORKING_CYCLES = 67, 687a69c5ed2SRob Clark PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68, 688a69c5ed2SRob Clark PERF_SP_STARVE_CYCLES_HLSQ = 69, 689a69c5ed2SRob Clark PERF_SP_NON_EXECUTION_LS_CYCLES = 70, 690a69c5ed2SRob Clark PERF_SP_WORKING_EU = 71, 691a69c5ed2SRob Clark PERF_SP_ANY_EU_WORKING = 72, 692a69c5ed2SRob Clark PERF_SP_WORKING_EU_FS_STAGE = 73, 693a69c5ed2SRob Clark PERF_SP_ANY_EU_WORKING_FS_STAGE = 74, 694a69c5ed2SRob Clark PERF_SP_WORKING_EU_VS_STAGE = 75, 695a69c5ed2SRob Clark PERF_SP_ANY_EU_WORKING_VS_STAGE = 76, 696a69c5ed2SRob Clark PERF_SP_WORKING_EU_CS_STAGE = 77, 697a69c5ed2SRob Clark PERF_SP_ANY_EU_WORKING_CS_STAGE = 78, 698a69c5ed2SRob Clark PERF_SP_GPR_READ_PREFETCH = 79, 699a69c5ed2SRob Clark PERF_SP_GPR_READ_CONFLICT = 80, 700a69c5ed2SRob Clark PERF_SP_GPR_WRITE_CONFLICT = 81, 701a69c5ed2SRob Clark PERF_SP_GM_LOAD_LATENCY_CYCLES = 82, 702a69c5ed2SRob Clark PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83, 703a69c5ed2SRob Clark PERF_SP_EXECUTABLE_WAVES = 84, 704a69c5ed2SRob Clark }; 705a69c5ed2SRob Clark 706a69c5ed2SRob Clark enum a6xx_rb_perfcounter_select { 707a69c5ed2SRob Clark PERF_RB_BUSY_CYCLES = 0, 708a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_HLSQ = 1, 709a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_FIFO0_FULL = 2, 710a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_FIFO1_FULL = 3, 711a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_FIFO2_FULL = 4, 712a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_SP = 5, 713a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_LRZ_TILE = 6, 714a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_CCU = 7, 715a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_Z_PLANE = 8, 716a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_BARY_PLANE = 9, 717a69c5ed2SRob Clark PERF_RB_Z_WORKLOAD = 10, 718a69c5ed2SRob Clark PERF_RB_HLSQ_ACTIVE = 11, 719a69c5ed2SRob Clark PERF_RB_Z_READ = 12, 720a69c5ed2SRob Clark PERF_RB_Z_WRITE = 13, 721a69c5ed2SRob Clark PERF_RB_C_READ = 14, 722a69c5ed2SRob Clark PERF_RB_C_WRITE = 15, 723a69c5ed2SRob Clark PERF_RB_TOTAL_PASS = 16, 724a69c5ed2SRob Clark PERF_RB_Z_PASS = 17, 725a69c5ed2SRob Clark PERF_RB_Z_FAIL = 18, 726a69c5ed2SRob Clark PERF_RB_S_FAIL = 19, 727a69c5ed2SRob Clark PERF_RB_BLENDED_FXP_COMPONENTS = 20, 728a69c5ed2SRob Clark PERF_RB_BLENDED_FP16_COMPONENTS = 21, 729a69c5ed2SRob Clark PERF_RB_PS_INVOCATIONS = 22, 730a69c5ed2SRob Clark PERF_RB_2D_ALIVE_CYCLES = 23, 731a69c5ed2SRob Clark PERF_RB_2D_STALL_CYCLES_A2D = 24, 732a69c5ed2SRob Clark PERF_RB_2D_STARVE_CYCLES_SRC = 25, 733a69c5ed2SRob Clark PERF_RB_2D_STARVE_CYCLES_SP = 26, 734a69c5ed2SRob Clark PERF_RB_2D_STARVE_CYCLES_DST = 27, 735a69c5ed2SRob Clark PERF_RB_2D_VALID_PIXELS = 28, 736a69c5ed2SRob Clark PERF_RB_3D_PIXELS = 29, 737a69c5ed2SRob Clark PERF_RB_BLENDER_WORKING_CYCLES = 30, 738a69c5ed2SRob Clark PERF_RB_ZPROC_WORKING_CYCLES = 31, 739a69c5ed2SRob Clark PERF_RB_CPROC_WORKING_CYCLES = 32, 740a69c5ed2SRob Clark PERF_RB_SAMPLER_WORKING_CYCLES = 33, 741a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 34, 742a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 35, 743a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 36, 744a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 37, 745a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_VPC = 38, 746a69c5ed2SRob Clark PERF_RB_2D_INPUT_TRANS = 39, 747a69c5ed2SRob Clark PERF_RB_2D_OUTPUT_RB_DST_TRANS = 40, 748a69c5ed2SRob Clark PERF_RB_2D_OUTPUT_RB_SRC_TRANS = 41, 749a69c5ed2SRob Clark PERF_RB_BLENDED_FP32_COMPONENTS = 42, 750a69c5ed2SRob Clark PERF_RB_COLOR_PIX_TILES = 43, 751a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU = 44, 752a69c5ed2SRob Clark PERF_RB_EARLY_Z_ARB3_GRANT = 45, 753a69c5ed2SRob Clark PERF_RB_LATE_Z_ARB3_GRANT = 46, 754a69c5ed2SRob Clark PERF_RB_EARLY_Z_SKIP_GRANT = 47, 755a69c5ed2SRob Clark }; 756a69c5ed2SRob Clark 757a69c5ed2SRob Clark enum a6xx_vsc_perfcounter_select { 758a69c5ed2SRob Clark PERF_VSC_BUSY_CYCLES = 0, 759a69c5ed2SRob Clark PERF_VSC_WORKING_CYCLES = 1, 760a69c5ed2SRob Clark PERF_VSC_STALL_CYCLES_UCHE = 2, 761a69c5ed2SRob Clark PERF_VSC_EOT_NUM = 3, 762a69c5ed2SRob Clark PERF_VSC_INPUT_TILES = 4, 763a69c5ed2SRob Clark }; 764a69c5ed2SRob Clark 765a69c5ed2SRob Clark enum a6xx_ccu_perfcounter_select { 766a69c5ed2SRob Clark PERF_CCU_BUSY_CYCLES = 0, 767a69c5ed2SRob Clark PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1, 768a69c5ed2SRob Clark PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2, 769a69c5ed2SRob Clark PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3, 770a69c5ed2SRob Clark PERF_CCU_DEPTH_BLOCKS = 4, 771a69c5ed2SRob Clark PERF_CCU_COLOR_BLOCKS = 5, 772a69c5ed2SRob Clark PERF_CCU_DEPTH_BLOCK_HIT = 6, 773a69c5ed2SRob Clark PERF_CCU_COLOR_BLOCK_HIT = 7, 774a69c5ed2SRob Clark PERF_CCU_PARTIAL_BLOCK_READ = 8, 775a69c5ed2SRob Clark PERF_CCU_GMEM_READ = 9, 776a69c5ed2SRob Clark PERF_CCU_GMEM_WRITE = 10, 777a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11, 778a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12, 779a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13, 780a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14, 781a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15, 782a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG5_COUNT = 16, 783a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG6_COUNT = 17, 784a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG8_COUNT = 18, 785a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG0_COUNT = 19, 786a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG1_COUNT = 20, 787a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG2_COUNT = 21, 788a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG3_COUNT = 22, 789a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG4_COUNT = 23, 790a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG5_COUNT = 24, 791a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG6_COUNT = 25, 792a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG8_COUNT = 26, 793a69c5ed2SRob Clark PERF_CCU_2D_RD_REQ = 27, 794a69c5ed2SRob Clark PERF_CCU_2D_WR_REQ = 28, 795a69c5ed2SRob Clark }; 796a69c5ed2SRob Clark 797a69c5ed2SRob Clark enum a6xx_lrz_perfcounter_select { 798a69c5ed2SRob Clark PERF_LRZ_BUSY_CYCLES = 0, 799a69c5ed2SRob Clark PERF_LRZ_STARVE_CYCLES_RAS = 1, 800a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_RB = 2, 801a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_VSC = 3, 802a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_VPC = 4, 803a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5, 804a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_UCHE = 6, 805a69c5ed2SRob Clark PERF_LRZ_LRZ_READ = 7, 806a69c5ed2SRob Clark PERF_LRZ_LRZ_WRITE = 8, 807a69c5ed2SRob Clark PERF_LRZ_READ_LATENCY = 9, 808a69c5ed2SRob Clark PERF_LRZ_MERGE_CACHE_UPDATING = 10, 809a69c5ed2SRob Clark PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11, 810a69c5ed2SRob Clark PERF_LRZ_PRIM_KILLED_BY_LRZ = 12, 811a69c5ed2SRob Clark PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13, 812a69c5ed2SRob Clark PERF_LRZ_FULL_8X8_TILES = 14, 813a69c5ed2SRob Clark PERF_LRZ_PARTIAL_8X8_TILES = 15, 814a69c5ed2SRob Clark PERF_LRZ_TILE_KILLED = 16, 815a69c5ed2SRob Clark PERF_LRZ_TOTAL_PIXEL = 17, 816a69c5ed2SRob Clark PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18, 817a69c5ed2SRob Clark PERF_LRZ_FULLY_COVERED_TILES = 19, 818a69c5ed2SRob Clark PERF_LRZ_PARTIAL_COVERED_TILES = 20, 819a69c5ed2SRob Clark PERF_LRZ_FEEDBACK_ACCEPT = 21, 820a69c5ed2SRob Clark PERF_LRZ_FEEDBACK_DISCARD = 22, 821a69c5ed2SRob Clark PERF_LRZ_FEEDBACK_STALL = 23, 822a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 24, 823a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_RB_BPLANE = 25, 824a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_VC = 26, 825a69c5ed2SRob Clark PERF_LRZ_RAS_MASK_TRANS = 27, 826a69c5ed2SRob Clark }; 827a69c5ed2SRob Clark 828a69c5ed2SRob Clark enum a6xx_cmp_perfcounter_select { 829a69c5ed2SRob Clark PERF_CMPDECMP_STALL_CYCLES_ARB = 0, 830a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1, 831a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2, 832a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3, 833a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4, 834a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_REQUEST = 5, 835a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6, 836a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_DATA = 7, 837a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_WRITE_DATA = 8, 838a69c5ed2SRob Clark PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9, 839a69c5ed2SRob Clark PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10, 840a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11, 841a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12, 842a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13, 843a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14, 844a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 15, 845a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 16, 846a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 17, 847a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 18, 848a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 19, 849a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 20, 850a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 21, 851a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 22, 852a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 23, 853a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 24, 854a69c5ed2SRob Clark PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 25, 855a69c5ed2SRob Clark PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 26, 856a69c5ed2SRob Clark PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 27, 857a69c5ed2SRob Clark PERF_CMPDECMP_2D_RD_DATA = 28, 858a69c5ed2SRob Clark PERF_CMPDECMP_2D_WR_DATA = 29, 859a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 30, 860a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 31, 861a69c5ed2SRob Clark PERF_CMPDECMP_2D_OUTPUT_TRANS = 32, 862a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 33, 863a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 34, 864a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 35, 865a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 36, 866a69c5ed2SRob Clark PERF_CMPDECMP_2D_BUSY_CYCLES = 37, 867a69c5ed2SRob Clark PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = 38, 868a69c5ed2SRob Clark PERF_CMPDECMP_2D_PIXELS = 39, 8692d756322SRob Clark }; 8702d756322SRob Clark 871c28c82e9SRob Clark enum a6xx_2d_ifmt { 872c28c82e9SRob Clark R2D_UNORM8 = 16, 873c28c82e9SRob Clark R2D_INT32 = 7, 874c28c82e9SRob Clark R2D_INT16 = 6, 875c28c82e9SRob Clark R2D_INT8 = 5, 876c28c82e9SRob Clark R2D_FLOAT32 = 4, 877c28c82e9SRob Clark R2D_FLOAT16 = 3, 878c28c82e9SRob Clark R2D_UNORM8_SRGB = 1, 879c28c82e9SRob Clark R2D_RAW = 0, 880c28c82e9SRob Clark }; 881c28c82e9SRob Clark 882c28c82e9SRob Clark enum a6xx_ztest_mode { 883c28c82e9SRob Clark A6XX_EARLY_Z = 0, 884c28c82e9SRob Clark A6XX_LATE_Z = 1, 885c28c82e9SRob Clark A6XX_EARLY_LRZ_LATE_Z = 2, 886c28c82e9SRob Clark }; 887c28c82e9SRob Clark 888c28c82e9SRob Clark enum a6xx_rotation { 889c28c82e9SRob Clark ROTATE_0 = 0, 890c28c82e9SRob Clark ROTATE_90 = 1, 891c28c82e9SRob Clark ROTATE_180 = 2, 892c28c82e9SRob Clark ROTATE_270 = 3, 893c28c82e9SRob Clark ROTATE_HFLIP = 4, 894c28c82e9SRob Clark ROTATE_VFLIP = 5, 895c28c82e9SRob Clark }; 896c28c82e9SRob Clark 897c28c82e9SRob Clark enum a6xx_tess_spacing { 898c28c82e9SRob Clark TESS_EQUAL = 0, 899c28c82e9SRob Clark TESS_FRACTIONAL_ODD = 2, 900c28c82e9SRob Clark TESS_FRACTIONAL_EVEN = 3, 901c28c82e9SRob Clark }; 902c28c82e9SRob Clark 903c28c82e9SRob Clark enum a6xx_tess_output { 904c28c82e9SRob Clark TESS_POINTS = 0, 905c28c82e9SRob Clark TESS_LINES = 1, 906c28c82e9SRob Clark TESS_CW_TRIS = 2, 907c28c82e9SRob Clark TESS_CCW_TRIS = 3, 908c28c82e9SRob Clark }; 909c28c82e9SRob Clark 9102d756322SRob Clark enum a6xx_tex_filter { 9112d756322SRob Clark A6XX_TEX_NEAREST = 0, 9122d756322SRob Clark A6XX_TEX_LINEAR = 1, 9132d756322SRob Clark A6XX_TEX_ANISO = 2, 914c28c82e9SRob Clark A6XX_TEX_CUBIC = 3, 9152d756322SRob Clark }; 9162d756322SRob Clark 9172d756322SRob Clark enum a6xx_tex_clamp { 9182d756322SRob Clark A6XX_TEX_REPEAT = 0, 9192d756322SRob Clark A6XX_TEX_CLAMP_TO_EDGE = 1, 9202d756322SRob Clark A6XX_TEX_MIRROR_REPEAT = 2, 9212d756322SRob Clark A6XX_TEX_CLAMP_TO_BORDER = 3, 9222d756322SRob Clark A6XX_TEX_MIRROR_CLAMP = 4, 9232d756322SRob Clark }; 9242d756322SRob Clark 9252d756322SRob Clark enum a6xx_tex_aniso { 9262d756322SRob Clark A6XX_TEX_ANISO_1 = 0, 9272d756322SRob Clark A6XX_TEX_ANISO_2 = 1, 9282d756322SRob Clark A6XX_TEX_ANISO_4 = 2, 9292d756322SRob Clark A6XX_TEX_ANISO_8 = 3, 9302d756322SRob Clark A6XX_TEX_ANISO_16 = 4, 9312d756322SRob Clark }; 9322d756322SRob Clark 933c28c82e9SRob Clark enum a6xx_reduction_mode { 934c28c82e9SRob Clark A6XX_REDUCTION_MODE_AVERAGE = 0, 935c28c82e9SRob Clark A6XX_REDUCTION_MODE_MIN = 1, 936c28c82e9SRob Clark A6XX_REDUCTION_MODE_MAX = 2, 937c28c82e9SRob Clark }; 938c28c82e9SRob Clark 9392d756322SRob Clark enum a6xx_tex_swiz { 9402d756322SRob Clark A6XX_TEX_X = 0, 9412d756322SRob Clark A6XX_TEX_Y = 1, 9422d756322SRob Clark A6XX_TEX_Z = 2, 9432d756322SRob Clark A6XX_TEX_W = 3, 9442d756322SRob Clark A6XX_TEX_ZERO = 4, 9452d756322SRob Clark A6XX_TEX_ONE = 5, 9462d756322SRob Clark }; 9472d756322SRob Clark 9482d756322SRob Clark enum a6xx_tex_type { 9492d756322SRob Clark A6XX_TEX_1D = 0, 9502d756322SRob Clark A6XX_TEX_2D = 1, 9512d756322SRob Clark A6XX_TEX_CUBE = 2, 9522d756322SRob Clark A6XX_TEX_3D = 3, 9532d756322SRob Clark }; 9542d756322SRob Clark 9552d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001 9562d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR 0x00000002 9572d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW 0x00000040 9582d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080 9592d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_SW 0x00000100 9602d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200 9612d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400 9622d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800 9632d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000 9642d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_IB2 0x00002000 9652d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_IB1 0x00004000 9662d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_RB 0x00008000 9672d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000 9682d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000 9692d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000 9702d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000 9712d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT 0x00800000 9722d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000 9732d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000 9742d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000 9752d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000 9762d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000 9772d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000 9782d756322SRob Clark #define A6XX_CP_INT_CP_OPCODE_ERROR 0x00000001 9792d756322SRob Clark #define A6XX_CP_INT_CP_UCODE_ERROR 0x00000002 9802d756322SRob Clark #define A6XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004 9812d756322SRob Clark #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010 9822d756322SRob Clark #define A6XX_CP_INT_CP_AHB_ERROR 0x00000020 9832d756322SRob Clark #define A6XX_CP_INT_CP_VSD_PARITY_ERROR 0x00000040 9842d756322SRob Clark #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR 0x00000080 9852d756322SRob Clark #define REG_A6XX_CP_RB_BASE 0x00000800 9862d756322SRob Clark 9872d756322SRob Clark #define REG_A6XX_CP_RB_BASE_HI 0x00000801 9882d756322SRob Clark 9892d756322SRob Clark #define REG_A6XX_CP_RB_CNTL 0x00000802 9902d756322SRob Clark 9912d756322SRob Clark #define REG_A6XX_CP_RB_RPTR_ADDR_LO 0x00000804 9922d756322SRob Clark 9932d756322SRob Clark #define REG_A6XX_CP_RB_RPTR_ADDR_HI 0x00000805 9942d756322SRob Clark 9952d756322SRob Clark #define REG_A6XX_CP_RB_RPTR 0x00000806 9962d756322SRob Clark 9972d756322SRob Clark #define REG_A6XX_CP_RB_WPTR 0x00000807 9982d756322SRob Clark 9992d756322SRob Clark #define REG_A6XX_CP_SQE_CNTL 0x00000808 10002d756322SRob Clark 1001c28c82e9SRob Clark #define REG_A6XX_CP_CP2GMU_STATUS 0x00000812 1002c28c82e9SRob Clark #define A6XX_CP_CP2GMU_STATUS_IFPC 0x00000001 1003c28c82e9SRob Clark 10042d756322SRob Clark #define REG_A6XX_CP_HW_FAULT 0x00000821 10052d756322SRob Clark 10062d756322SRob Clark #define REG_A6XX_CP_INTERRUPT_STATUS 0x00000823 10072d756322SRob Clark 10082d756322SRob Clark #define REG_A6XX_CP_PROTECT_STATUS 0x00000824 10092d756322SRob Clark 10102d756322SRob Clark #define REG_A6XX_CP_SQE_INSTR_BASE_LO 0x00000830 10112d756322SRob Clark 10122d756322SRob Clark #define REG_A6XX_CP_SQE_INSTR_BASE_HI 0x00000831 10132d756322SRob Clark 10142d756322SRob Clark #define REG_A6XX_CP_MISC_CNTL 0x00000840 10152d756322SRob Clark 101624e6938eSJonathan Marek #define REG_A6XX_CP_APRIV_CNTL 0x00000844 101724e6938eSJonathan Marek 10182d756322SRob Clark #define REG_A6XX_CP_ROQ_THRESHOLDS_1 0x000008c1 1019c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK 0x000000ff 1020c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT 0 1021c28c82e9SRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_LO(uint32_t val) 1022c28c82e9SRob Clark { 1023c28c82e9SRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK; 1024c28c82e9SRob Clark } 1025c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MASK 0x0000ff00 1026c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__SHIFT 8 1027c28c82e9SRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_HI(uint32_t val) 1028c28c82e9SRob Clark { 1029c28c82e9SRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MASK; 1030c28c82e9SRob Clark } 1031c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK 0x00ff0000 1032c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT 16 1033c28c82e9SRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val) 1034c28c82e9SRob Clark { 1035c28c82e9SRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK; 1036c28c82e9SRob Clark } 1037c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK 0xff000000 1038c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT 24 1039c28c82e9SRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val) 1040c28c82e9SRob Clark { 1041c28c82e9SRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK; 1042c28c82e9SRob Clark } 10432d756322SRob Clark 10442d756322SRob Clark #define REG_A6XX_CP_ROQ_THRESHOLDS_2 0x000008c2 1045c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK 0x000001ff 1046c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT 0 1047c28c82e9SRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val) 1048c28c82e9SRob Clark { 1049c28c82e9SRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK; 1050c28c82e9SRob Clark } 1051c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK 0xffff0000 1052c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT 16 1053c28c82e9SRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val) 1054c28c82e9SRob Clark { 1055c28c82e9SRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK; 1056c28c82e9SRob Clark } 10572d756322SRob Clark 10582d756322SRob Clark #define REG_A6XX_CP_MEM_POOL_SIZE 0x000008c3 10592d756322SRob Clark 10602d756322SRob Clark #define REG_A6XX_CP_CHICKEN_DBG 0x00000841 10612d756322SRob Clark 10622d756322SRob Clark #define REG_A6XX_CP_ADDR_MODE_CNTL 0x00000842 10632d756322SRob Clark 10642d756322SRob Clark #define REG_A6XX_CP_DBG_ECO_CNTL 0x00000843 10652d756322SRob Clark 10662d756322SRob Clark #define REG_A6XX_CP_PROTECT_CNTL 0x0000084f 10672d756322SRob Clark 10682d756322SRob Clark static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; } 10692d756322SRob Clark 10702d756322SRob Clark static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; } 10712d756322SRob Clark 10722d756322SRob Clark static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; } 10732d756322SRob Clark 10742d756322SRob Clark static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; } 10752d756322SRob Clark #define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0003ffff 10762d756322SRob Clark #define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0 10772d756322SRob Clark static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) 10782d756322SRob Clark { 10792d756322SRob Clark return ((val) << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK; 10802d756322SRob Clark } 10812d756322SRob Clark #define A6XX_CP_PROTECT_REG_MASK_LEN__MASK 0x7ffc0000 10822d756322SRob Clark #define A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT 18 10832d756322SRob Clark static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) 10842d756322SRob Clark { 10852d756322SRob Clark return ((val) << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK; 10862d756322SRob Clark } 10872d756322SRob Clark #define A6XX_CP_PROTECT_REG_READ 0x80000000 10882d756322SRob Clark 10892d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_CNTL 0x000008a0 10902d756322SRob Clark 10912d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x000008a1 10922d756322SRob Clark 10932d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x000008a2 10942d756322SRob Clark 10952d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO 0x000008a3 10962d756322SRob Clark 10972d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI 0x000008a4 10982d756322SRob Clark 10992d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO 0x000008a5 11002d756322SRob Clark 11012d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI 0x000008a6 11022d756322SRob Clark 11032d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO 0x000008a7 11042d756322SRob Clark 11052d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI 0x000008a8 11062d756322SRob Clark 11072d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_0 0x000008d0 11082d756322SRob Clark 11092d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_1 0x000008d1 11102d756322SRob Clark 11112d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_2 0x000008d2 11122d756322SRob Clark 11132d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_3 0x000008d3 11142d756322SRob Clark 11152d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_4 0x000008d4 11162d756322SRob Clark 11172d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_5 0x000008d5 11182d756322SRob Clark 11192d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_6 0x000008d6 11202d756322SRob Clark 11212d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_7 0x000008d7 11222d756322SRob Clark 11232d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_8 0x000008d8 11242d756322SRob Clark 11252d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_9 0x000008d9 11262d756322SRob Clark 11272d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_10 0x000008da 11282d756322SRob Clark 11292d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_11 0x000008db 11302d756322SRob Clark 11312d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_12 0x000008dc 11322d756322SRob Clark 11332d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_13 0x000008dd 11342d756322SRob Clark 11352d756322SRob Clark #define REG_A6XX_CP_CRASH_SCRIPT_BASE_LO 0x00000900 11362d756322SRob Clark 11372d756322SRob Clark #define REG_A6XX_CP_CRASH_SCRIPT_BASE_HI 0x00000901 11382d756322SRob Clark 11392d756322SRob Clark #define REG_A6XX_CP_CRASH_DUMP_CNTL 0x00000902 11402d756322SRob Clark 11412d756322SRob Clark #define REG_A6XX_CP_CRASH_DUMP_STATUS 0x00000903 11422d756322SRob Clark 11432d756322SRob Clark #define REG_A6XX_CP_SQE_STAT_ADDR 0x00000908 11442d756322SRob Clark 11452d756322SRob Clark #define REG_A6XX_CP_SQE_STAT_DATA 0x00000909 11462d756322SRob Clark 11472d756322SRob Clark #define REG_A6XX_CP_DRAW_STATE_ADDR 0x0000090a 11482d756322SRob Clark 11492d756322SRob Clark #define REG_A6XX_CP_DRAW_STATE_DATA 0x0000090b 11502d756322SRob Clark 11512d756322SRob Clark #define REG_A6XX_CP_ROQ_DBG_ADDR 0x0000090c 11522d756322SRob Clark 11532d756322SRob Clark #define REG_A6XX_CP_ROQ_DBG_DATA 0x0000090d 11542d756322SRob Clark 11552d756322SRob Clark #define REG_A6XX_CP_MEM_POOL_DBG_ADDR 0x0000090e 11562d756322SRob Clark 11572d756322SRob Clark #define REG_A6XX_CP_MEM_POOL_DBG_DATA 0x0000090f 11582d756322SRob Clark 11592d756322SRob Clark #define REG_A6XX_CP_SQE_UCODE_DBG_ADDR 0x00000910 11602d756322SRob Clark 11612d756322SRob Clark #define REG_A6XX_CP_SQE_UCODE_DBG_DATA 0x00000911 11622d756322SRob Clark 11632d756322SRob Clark #define REG_A6XX_CP_IB1_BASE 0x00000928 11642d756322SRob Clark 11652d756322SRob Clark #define REG_A6XX_CP_IB1_BASE_HI 0x00000929 11662d756322SRob Clark 11672d756322SRob Clark #define REG_A6XX_CP_IB1_REM_SIZE 0x0000092a 11682d756322SRob Clark 11692d756322SRob Clark #define REG_A6XX_CP_IB2_BASE 0x0000092b 11702d756322SRob Clark 11712d756322SRob Clark #define REG_A6XX_CP_IB2_BASE_HI 0x0000092c 11722d756322SRob Clark 11732d756322SRob Clark #define REG_A6XX_CP_IB2_REM_SIZE 0x0000092d 11742d756322SRob Clark 1175c28c82e9SRob Clark #define REG_A6XX_CP_SDS_BASE 0x0000092e 1176c28c82e9SRob Clark 1177c28c82e9SRob Clark #define REG_A6XX_CP_SDS_BASE_HI 0x0000092f 1178c28c82e9SRob Clark 1179c28c82e9SRob Clark #define REG_A6XX_CP_SDS_REM_SIZE 0x0000092e 1180c28c82e9SRob Clark 1181c28c82e9SRob Clark #define REG_A6XX_CP_BIN_SIZE_ADDRESS 0x00000931 1182c28c82e9SRob Clark 1183c28c82e9SRob Clark #define REG_A6XX_CP_BIN_SIZE_ADDRESS_HI 0x00000932 1184c28c82e9SRob Clark 1185c28c82e9SRob Clark #define REG_A6XX_CP_BIN_DATA_ADDR 0x00000934 1186c28c82e9SRob Clark 1187c28c82e9SRob Clark #define REG_A6XX_CP_BIN_DATA_ADDR_HI 0x00000935 1188c28c82e9SRob Clark 1189c28c82e9SRob Clark #define REG_A6XX_CP_CSQ_IB1_STAT 0x00000949 1190c28c82e9SRob Clark #define A6XX_CP_CSQ_IB1_STAT_REM__MASK 0xffff0000 1191c28c82e9SRob Clark #define A6XX_CP_CSQ_IB1_STAT_REM__SHIFT 16 1192c28c82e9SRob Clark static inline uint32_t A6XX_CP_CSQ_IB1_STAT_REM(uint32_t val) 1193c28c82e9SRob Clark { 1194c28c82e9SRob Clark return ((val) << A6XX_CP_CSQ_IB1_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB1_STAT_REM__MASK; 1195c28c82e9SRob Clark } 1196c28c82e9SRob Clark 1197c28c82e9SRob Clark #define REG_A6XX_CP_CSQ_IB2_STAT 0x0000094a 1198c28c82e9SRob Clark #define A6XX_CP_CSQ_IB2_STAT_REM__MASK 0xffff0000 1199c28c82e9SRob Clark #define A6XX_CP_CSQ_IB2_STAT_REM__SHIFT 16 1200c28c82e9SRob Clark static inline uint32_t A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val) 1201c28c82e9SRob Clark { 1202c28c82e9SRob Clark return ((val) << A6XX_CP_CSQ_IB2_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB2_STAT_REM__MASK; 1203c28c82e9SRob Clark } 1204c28c82e9SRob Clark 12052d756322SRob Clark #define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO 0x00000980 12062d756322SRob Clark 12072d756322SRob Clark #define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI 0x00000981 12082d756322SRob Clark 12092d756322SRob Clark #define REG_A6XX_CP_AHB_CNTL 0x0000098d 12102d756322SRob Clark 12112d756322SRob Clark #define REG_A6XX_CP_APERTURE_CNTL_HOST 0x00000a00 12122d756322SRob Clark 12132d756322SRob Clark #define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03 12142d756322SRob Clark 12152d756322SRob Clark #define REG_A6XX_VSC_ADDR_MODE_CNTL 0x00000c01 12162d756322SRob Clark 12172d756322SRob Clark #define REG_A6XX_RBBM_INT_0_STATUS 0x00000201 12182d756322SRob Clark 12192d756322SRob Clark #define REG_A6XX_RBBM_STATUS 0x00000210 12202d756322SRob Clark #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x00800000 12212d756322SRob Clark #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x00400000 12222d756322SRob Clark #define A6XX_RBBM_STATUS_HLSQ_BUSY 0x00200000 12232d756322SRob Clark #define A6XX_RBBM_STATUS_VSC_BUSY 0x00100000 12242d756322SRob Clark #define A6XX_RBBM_STATUS_TPL1_BUSY 0x00080000 12252d756322SRob Clark #define A6XX_RBBM_STATUS_SP_BUSY 0x00040000 12262d756322SRob Clark #define A6XX_RBBM_STATUS_UCHE_BUSY 0x00020000 12272d756322SRob Clark #define A6XX_RBBM_STATUS_VPC_BUSY 0x00010000 12282d756322SRob Clark #define A6XX_RBBM_STATUS_VFD_BUSY 0x00008000 12292d756322SRob Clark #define A6XX_RBBM_STATUS_TESS_BUSY 0x00004000 12302d756322SRob Clark #define A6XX_RBBM_STATUS_PC_VSD_BUSY 0x00002000 12312d756322SRob Clark #define A6XX_RBBM_STATUS_PC_DCALL_BUSY 0x00001000 12322d756322SRob Clark #define A6XX_RBBM_STATUS_COM_DCOM_BUSY 0x00000800 12332d756322SRob Clark #define A6XX_RBBM_STATUS_LRZ_BUSY 0x00000400 12342d756322SRob Clark #define A6XX_RBBM_STATUS_A2D_BUSY 0x00000200 12352d756322SRob Clark #define A6XX_RBBM_STATUS_CCU_BUSY 0x00000100 12362d756322SRob Clark #define A6XX_RBBM_STATUS_RB_BUSY 0x00000080 12372d756322SRob Clark #define A6XX_RBBM_STATUS_RAS_BUSY 0x00000040 12382d756322SRob Clark #define A6XX_RBBM_STATUS_TSE_BUSY 0x00000020 12392d756322SRob Clark #define A6XX_RBBM_STATUS_VBIF_BUSY 0x00000010 12402d756322SRob Clark #define A6XX_RBBM_STATUS_GFX_DBGC_BUSY 0x00000008 12412d756322SRob Clark #define A6XX_RBBM_STATUS_CP_BUSY 0x00000004 12422d756322SRob Clark #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER 0x00000002 12432d756322SRob Clark #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER 0x00000001 12442d756322SRob Clark 12452d756322SRob Clark #define REG_A6XX_RBBM_STATUS3 0x00000213 1246c28c82e9SRob Clark #define A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT 0x01000000 12472d756322SRob Clark 12482d756322SRob Clark #define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215 12492d756322SRob Clark 12502d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_0_LO 0x00000400 12512d756322SRob Clark 12522d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_0_HI 0x00000401 12532d756322SRob Clark 12542d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_1_LO 0x00000402 12552d756322SRob Clark 12562d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_1_HI 0x00000403 12572d756322SRob Clark 12582d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_2_LO 0x00000404 12592d756322SRob Clark 12602d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_2_HI 0x00000405 12612d756322SRob Clark 12622d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_3_LO 0x00000406 12632d756322SRob Clark 12642d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_3_HI 0x00000407 12652d756322SRob Clark 12662d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_4_LO 0x00000408 12672d756322SRob Clark 12682d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_4_HI 0x00000409 12692d756322SRob Clark 12702d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_5_LO 0x0000040a 12712d756322SRob Clark 12722d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_5_HI 0x0000040b 12732d756322SRob Clark 12742d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_6_LO 0x0000040c 12752d756322SRob Clark 12762d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_6_HI 0x0000040d 12772d756322SRob Clark 12782d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_7_LO 0x0000040e 12792d756322SRob Clark 12802d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_7_HI 0x0000040f 12812d756322SRob Clark 12822d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_8_LO 0x00000410 12832d756322SRob Clark 12842d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_8_HI 0x00000411 12852d756322SRob Clark 12862d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_9_LO 0x00000412 12872d756322SRob Clark 12882d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_9_HI 0x00000413 12892d756322SRob Clark 12902d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_10_LO 0x00000414 12912d756322SRob Clark 12922d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_10_HI 0x00000415 12932d756322SRob Clark 12942d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_11_LO 0x00000416 12952d756322SRob Clark 12962d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_11_HI 0x00000417 12972d756322SRob Clark 12982d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_12_LO 0x00000418 12992d756322SRob Clark 13002d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_12_HI 0x00000419 13012d756322SRob Clark 13022d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_13_LO 0x0000041a 13032d756322SRob Clark 13042d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_13_HI 0x0000041b 13052d756322SRob Clark 13062d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_0_LO 0x0000041c 13072d756322SRob Clark 13082d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_0_HI 0x0000041d 13092d756322SRob Clark 13102d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_1_LO 0x0000041e 13112d756322SRob Clark 13122d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_1_HI 0x0000041f 13132d756322SRob Clark 13142d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_2_LO 0x00000420 13152d756322SRob Clark 13162d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_2_HI 0x00000421 13172d756322SRob Clark 13182d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_3_LO 0x00000422 13192d756322SRob Clark 13202d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_3_HI 0x00000423 13212d756322SRob Clark 13222d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_0_LO 0x00000424 13232d756322SRob Clark 13242d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_0_HI 0x00000425 13252d756322SRob Clark 13262d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_1_LO 0x00000426 13272d756322SRob Clark 13282d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_1_HI 0x00000427 13292d756322SRob Clark 13302d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_2_LO 0x00000428 13312d756322SRob Clark 13322d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_2_HI 0x00000429 13332d756322SRob Clark 13342d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_3_LO 0x0000042a 13352d756322SRob Clark 13362d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_3_HI 0x0000042b 13372d756322SRob Clark 13382d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_4_LO 0x0000042c 13392d756322SRob Clark 13402d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_4_HI 0x0000042d 13412d756322SRob Clark 13422d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_5_LO 0x0000042e 13432d756322SRob Clark 13442d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_5_HI 0x0000042f 13452d756322SRob Clark 13462d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_6_LO 0x00000430 13472d756322SRob Clark 13482d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_6_HI 0x00000431 13492d756322SRob Clark 13502d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_7_LO 0x00000432 13512d756322SRob Clark 13522d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_7_HI 0x00000433 13532d756322SRob Clark 13542d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_0_LO 0x00000434 13552d756322SRob Clark 13562d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_0_HI 0x00000435 13572d756322SRob Clark 13582d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_1_LO 0x00000436 13592d756322SRob Clark 13602d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_1_HI 0x00000437 13612d756322SRob Clark 13622d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_2_LO 0x00000438 13632d756322SRob Clark 13642d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_2_HI 0x00000439 13652d756322SRob Clark 13662d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_3_LO 0x0000043a 13672d756322SRob Clark 13682d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_3_HI 0x0000043b 13692d756322SRob Clark 13702d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_4_LO 0x0000043c 13712d756322SRob Clark 13722d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_4_HI 0x0000043d 13732d756322SRob Clark 13742d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_5_LO 0x0000043e 13752d756322SRob Clark 13762d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_5_HI 0x0000043f 13772d756322SRob Clark 13782d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_6_LO 0x00000440 13792d756322SRob Clark 13802d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_6_HI 0x00000441 13812d756322SRob Clark 13822d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_7_LO 0x00000442 13832d756322SRob Clark 13842d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_7_HI 0x00000443 13852d756322SRob Clark 13862d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_0_LO 0x00000444 13872d756322SRob Clark 13882d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_0_HI 0x00000445 13892d756322SRob Clark 13902d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_1_LO 0x00000446 13912d756322SRob Clark 13922d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_1_HI 0x00000447 13932d756322SRob Clark 13942d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_2_LO 0x00000448 13952d756322SRob Clark 13962d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_2_HI 0x00000449 13972d756322SRob Clark 13982d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_3_LO 0x0000044a 13992d756322SRob Clark 14002d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_3_HI 0x0000044b 14012d756322SRob Clark 14022d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_4_LO 0x0000044c 14032d756322SRob Clark 14042d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_4_HI 0x0000044d 14052d756322SRob Clark 14062d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_5_LO 0x0000044e 14072d756322SRob Clark 14082d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_5_HI 0x0000044f 14092d756322SRob Clark 14102d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_0_LO 0x00000450 14112d756322SRob Clark 14122d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_0_HI 0x00000451 14132d756322SRob Clark 14142d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_1_LO 0x00000452 14152d756322SRob Clark 14162d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_1_HI 0x00000453 14172d756322SRob Clark 14182d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_2_LO 0x00000454 14192d756322SRob Clark 14202d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_2_HI 0x00000455 14212d756322SRob Clark 14222d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_3_LO 0x00000456 14232d756322SRob Clark 14242d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_3_HI 0x00000457 14252d756322SRob Clark 14262d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_4_LO 0x00000458 14272d756322SRob Clark 14282d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_4_HI 0x00000459 14292d756322SRob Clark 14302d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_5_LO 0x0000045a 14312d756322SRob Clark 14322d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_5_HI 0x0000045b 14332d756322SRob Clark 14342d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_0_LO 0x0000045c 14352d756322SRob Clark 14362d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_0_HI 0x0000045d 14372d756322SRob Clark 14382d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_1_LO 0x0000045e 14392d756322SRob Clark 14402d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_1_HI 0x0000045f 14412d756322SRob Clark 14422d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_2_LO 0x00000460 14432d756322SRob Clark 14442d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_2_HI 0x00000461 14452d756322SRob Clark 14462d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_3_LO 0x00000462 14472d756322SRob Clark 14482d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_3_HI 0x00000463 14492d756322SRob Clark 14502d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_4_LO 0x00000464 14512d756322SRob Clark 14522d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_4_HI 0x00000465 14532d756322SRob Clark 14542d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_0_LO 0x00000466 14552d756322SRob Clark 14562d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_0_HI 0x00000467 14572d756322SRob Clark 14582d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_1_LO 0x00000468 14592d756322SRob Clark 14602d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_1_HI 0x00000469 14612d756322SRob Clark 14622d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_2_LO 0x0000046a 14632d756322SRob Clark 14642d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_2_HI 0x0000046b 14652d756322SRob Clark 14662d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_3_LO 0x0000046c 14672d756322SRob Clark 14682d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_3_HI 0x0000046d 14692d756322SRob Clark 14702d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RAS_0_LO 0x0000046e 14712d756322SRob Clark 14722d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RAS_0_HI 0x0000046f 14732d756322SRob Clark 14742d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RAS_1_LO 0x00000470 14752d756322SRob Clark 14762d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RAS_1_HI 0x00000471 14772d756322SRob Clark 14782d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RAS_2_LO 0x00000472 14792d756322SRob Clark 14802d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RAS_2_HI 0x00000473 14812d756322SRob Clark 14822d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RAS_3_LO 0x00000474 14832d756322SRob Clark 14842d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RAS_3_HI 0x00000475 14852d756322SRob Clark 14862d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_0_LO 0x00000476 14872d756322SRob Clark 14882d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_0_HI 0x00000477 14892d756322SRob Clark 14902d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_1_LO 0x00000478 14912d756322SRob Clark 14922d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_1_HI 0x00000479 14932d756322SRob Clark 14942d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_2_LO 0x0000047a 14952d756322SRob Clark 14962d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_2_HI 0x0000047b 14972d756322SRob Clark 14982d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_3_LO 0x0000047c 14992d756322SRob Clark 15002d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_3_HI 0x0000047d 15012d756322SRob Clark 15022d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_4_LO 0x0000047e 15032d756322SRob Clark 15042d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_4_HI 0x0000047f 15052d756322SRob Clark 15062d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_5_LO 0x00000480 15072d756322SRob Clark 15082d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_5_HI 0x00000481 15092d756322SRob Clark 15102d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_6_LO 0x00000482 15112d756322SRob Clark 15122d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_6_HI 0x00000483 15132d756322SRob Clark 15142d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_7_LO 0x00000484 15152d756322SRob Clark 15162d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_7_HI 0x00000485 15172d756322SRob Clark 15182d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_8_LO 0x00000486 15192d756322SRob Clark 15202d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_8_HI 0x00000487 15212d756322SRob Clark 15222d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_9_LO 0x00000488 15232d756322SRob Clark 15242d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_9_HI 0x00000489 15252d756322SRob Clark 15262d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_10_LO 0x0000048a 15272d756322SRob Clark 15282d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_10_HI 0x0000048b 15292d756322SRob Clark 15302d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_11_LO 0x0000048c 15312d756322SRob Clark 15322d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_11_HI 0x0000048d 15332d756322SRob Clark 15342d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_0_LO 0x0000048e 15352d756322SRob Clark 15362d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_0_HI 0x0000048f 15372d756322SRob Clark 15382d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_1_LO 0x00000490 15392d756322SRob Clark 15402d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_1_HI 0x00000491 15412d756322SRob Clark 15422d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_2_LO 0x00000492 15432d756322SRob Clark 15442d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_2_HI 0x00000493 15452d756322SRob Clark 15462d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_3_LO 0x00000494 15472d756322SRob Clark 15482d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_3_HI 0x00000495 15492d756322SRob Clark 15502d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_4_LO 0x00000496 15512d756322SRob Clark 15522d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_4_HI 0x00000497 15532d756322SRob Clark 15542d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_5_LO 0x00000498 15552d756322SRob Clark 15562d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_5_HI 0x00000499 15572d756322SRob Clark 15582d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_6_LO 0x0000049a 15592d756322SRob Clark 15602d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_6_HI 0x0000049b 15612d756322SRob Clark 15622d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_7_LO 0x0000049c 15632d756322SRob Clark 15642d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_7_HI 0x0000049d 15652d756322SRob Clark 15662d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_8_LO 0x0000049e 15672d756322SRob Clark 15682d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_8_HI 0x0000049f 15692d756322SRob Clark 15702d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_9_LO 0x000004a0 15712d756322SRob Clark 15722d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_9_HI 0x000004a1 15732d756322SRob Clark 15742d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_10_LO 0x000004a2 15752d756322SRob Clark 15762d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_10_HI 0x000004a3 15772d756322SRob Clark 15782d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_11_LO 0x000004a4 15792d756322SRob Clark 15802d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_11_HI 0x000004a5 15812d756322SRob Clark 15822d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_0_LO 0x000004a6 15832d756322SRob Clark 15842d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_0_HI 0x000004a7 15852d756322SRob Clark 15862d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_1_LO 0x000004a8 15872d756322SRob Clark 15882d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_1_HI 0x000004a9 15892d756322SRob Clark 15902d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_2_LO 0x000004aa 15912d756322SRob Clark 15922d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_2_HI 0x000004ab 15932d756322SRob Clark 15942d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_3_LO 0x000004ac 15952d756322SRob Clark 15962d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_3_HI 0x000004ad 15972d756322SRob Clark 15982d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_4_LO 0x000004ae 15992d756322SRob Clark 16002d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_4_HI 0x000004af 16012d756322SRob Clark 16022d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_5_LO 0x000004b0 16032d756322SRob Clark 16042d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_5_HI 0x000004b1 16052d756322SRob Clark 16062d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_6_LO 0x000004b2 16072d756322SRob Clark 16082d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_6_HI 0x000004b3 16092d756322SRob Clark 16102d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_7_LO 0x000004b4 16112d756322SRob Clark 16122d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_7_HI 0x000004b5 16132d756322SRob Clark 16142d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_8_LO 0x000004b6 16152d756322SRob Clark 16162d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_8_HI 0x000004b7 16172d756322SRob Clark 16182d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_9_LO 0x000004b8 16192d756322SRob Clark 16202d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_9_HI 0x000004b9 16212d756322SRob Clark 16222d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_10_LO 0x000004ba 16232d756322SRob Clark 16242d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_10_HI 0x000004bb 16252d756322SRob Clark 16262d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_11_LO 0x000004bc 16272d756322SRob Clark 16282d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_11_HI 0x000004bd 16292d756322SRob Clark 16302d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_12_LO 0x000004be 16312d756322SRob Clark 16322d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_12_HI 0x000004bf 16332d756322SRob Clark 16342d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_13_LO 0x000004c0 16352d756322SRob Clark 16362d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_13_HI 0x000004c1 16372d756322SRob Clark 16382d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_14_LO 0x000004c2 16392d756322SRob Clark 16402d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_14_HI 0x000004c3 16412d756322SRob Clark 16422d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_15_LO 0x000004c4 16432d756322SRob Clark 16442d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_15_HI 0x000004c5 16452d756322SRob Clark 16462d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_16_LO 0x000004c6 16472d756322SRob Clark 16482d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_16_HI 0x000004c7 16492d756322SRob Clark 16502d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_17_LO 0x000004c8 16512d756322SRob Clark 16522d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_17_HI 0x000004c9 16532d756322SRob Clark 16542d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_18_LO 0x000004ca 16552d756322SRob Clark 16562d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_18_HI 0x000004cb 16572d756322SRob Clark 16582d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_19_LO 0x000004cc 16592d756322SRob Clark 16602d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_19_HI 0x000004cd 16612d756322SRob Clark 16622d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_20_LO 0x000004ce 16632d756322SRob Clark 16642d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_20_HI 0x000004cf 16652d756322SRob Clark 16662d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_21_LO 0x000004d0 16672d756322SRob Clark 16682d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_21_HI 0x000004d1 16692d756322SRob Clark 16702d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_22_LO 0x000004d2 16712d756322SRob Clark 16722d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_22_HI 0x000004d3 16732d756322SRob Clark 16742d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_23_LO 0x000004d4 16752d756322SRob Clark 16762d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_23_HI 0x000004d5 16772d756322SRob Clark 16782d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_0_LO 0x000004d6 16792d756322SRob Clark 16802d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_0_HI 0x000004d7 16812d756322SRob Clark 16822d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_1_LO 0x000004d8 16832d756322SRob Clark 16842d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_1_HI 0x000004d9 16852d756322SRob Clark 16862d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_2_LO 0x000004da 16872d756322SRob Clark 16882d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_2_HI 0x000004db 16892d756322SRob Clark 16902d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_3_LO 0x000004dc 16912d756322SRob Clark 16922d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_3_HI 0x000004dd 16932d756322SRob Clark 16942d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_4_LO 0x000004de 16952d756322SRob Clark 16962d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_4_HI 0x000004df 16972d756322SRob Clark 16982d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_5_LO 0x000004e0 16992d756322SRob Clark 17002d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_5_HI 0x000004e1 17012d756322SRob Clark 17022d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_6_LO 0x000004e2 17032d756322SRob Clark 17042d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_6_HI 0x000004e3 17052d756322SRob Clark 17062d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_7_LO 0x000004e4 17072d756322SRob Clark 17082d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_7_HI 0x000004e5 17092d756322SRob Clark 17102d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VSC_0_LO 0x000004e6 17112d756322SRob Clark 17122d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VSC_0_HI 0x000004e7 17132d756322SRob Clark 17142d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VSC_1_LO 0x000004e8 17152d756322SRob Clark 17162d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VSC_1_HI 0x000004e9 17172d756322SRob Clark 17182d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LRZ_0_LO 0x000004ea 17192d756322SRob Clark 17202d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LRZ_0_HI 0x000004eb 17212d756322SRob Clark 17222d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LRZ_1_LO 0x000004ec 17232d756322SRob Clark 17242d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LRZ_1_HI 0x000004ed 17252d756322SRob Clark 17262d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LRZ_2_LO 0x000004ee 17272d756322SRob Clark 17282d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LRZ_2_HI 0x000004ef 17292d756322SRob Clark 17302d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LRZ_3_LO 0x000004f0 17312d756322SRob Clark 17322d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LRZ_3_HI 0x000004f1 17332d756322SRob Clark 17342d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CMP_0_LO 0x000004f2 17352d756322SRob Clark 17362d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CMP_0_HI 0x000004f3 17372d756322SRob Clark 17382d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CMP_1_LO 0x000004f4 17392d756322SRob Clark 17402d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CMP_1_HI 0x000004f5 17412d756322SRob Clark 17422d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CMP_2_LO 0x000004f6 17432d756322SRob Clark 17442d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CMP_2_HI 0x000004f7 17452d756322SRob Clark 17462d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CMP_3_LO 0x000004f8 17472d756322SRob Clark 17482d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CMP_3_HI 0x000004f9 17492d756322SRob Clark 17502d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500 17512d756322SRob Clark 17522d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 0x00000501 17532d756322SRob Clark 17542d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 0x00000502 17552d756322SRob Clark 17562d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 0x00000503 17572d756322SRob Clark 17582d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 0x00000504 17592d756322SRob Clark 17602d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000505 17612d756322SRob Clark 17622d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506 17632d756322SRob Clark 17642d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000507 17652d756322SRob Clark 17662d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000508 17672d756322SRob Clark 17682d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000509 17692d756322SRob Clark 17702d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000050a 17712d756322SRob Clark 17722d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b 17732d756322SRob Clark 17742d756322SRob Clark #define REG_A6XX_RBBM_ISDB_CNT 0x00000533 17752d756322SRob Clark 1776c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_0_LO 0x00000540 1777c28c82e9SRob Clark 1778c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_0_HI 0x00000541 1779c28c82e9SRob Clark 1780c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_1_LO 0x00000542 1781c28c82e9SRob Clark 1782c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_1_HI 0x00000543 1783c28c82e9SRob Clark 1784c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_2_LO 0x00000544 1785c28c82e9SRob Clark 1786c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_2_HI 0x00000545 1787c28c82e9SRob Clark 1788c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_3_LO 0x00000546 1789c28c82e9SRob Clark 1790c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_3_HI 0x00000547 1791c28c82e9SRob Clark 1792c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_4_LO 0x00000548 1793c28c82e9SRob Clark 1794c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_4_HI 0x00000549 1795c28c82e9SRob Clark 1796c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_5_LO 0x0000054a 1797c28c82e9SRob Clark 1798c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_5_HI 0x0000054b 1799c28c82e9SRob Clark 1800c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_6_LO 0x0000054c 1801c28c82e9SRob Clark 1802c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_6_HI 0x0000054d 1803c28c82e9SRob Clark 1804c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_7_LO 0x0000054e 1805c28c82e9SRob Clark 1806c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_7_HI 0x0000054f 1807c28c82e9SRob Clark 1808c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_8_LO 0x00000550 1809c28c82e9SRob Clark 1810c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_8_HI 0x00000551 1811c28c82e9SRob Clark 1812c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_9_LO 0x00000552 1813c28c82e9SRob Clark 1814c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_9_HI 0x00000553 1815c28c82e9SRob Clark 1816c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_10_LO 0x00000554 1817c28c82e9SRob Clark 1818c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_10_HI 0x00000555 1819c28c82e9SRob Clark 18202d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TRUST_CNTL 0x0000f400 18212d756322SRob Clark 18222d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800 18232d756322SRob Clark 18242d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801 18252d756322SRob Clark 18262d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802 18272d756322SRob Clark 18282d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_CNTL 0x0000f803 18292d756322SRob Clark 18302d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810 18312d756322SRob Clark 18322d756322SRob Clark #define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL 0x00000010 18332d756322SRob Clark 183424e6938eSJonathan Marek #define REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL 0x00000011 183524e6938eSJonathan Marek 1836c28c82e9SRob Clark #define REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD 0x0000001c 1837c28c82e9SRob Clark #define A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE 0x00000001 1838c28c82e9SRob Clark 18392d756322SRob Clark #define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000001f 18402d756322SRob Clark 18412d756322SRob Clark #define REG_A6XX_RBBM_INT_CLEAR_CMD 0x00000037 18422d756322SRob Clark 18432d756322SRob Clark #define REG_A6XX_RBBM_INT_0_MASK 0x00000038 18442d756322SRob Clark 18452d756322SRob Clark #define REG_A6XX_RBBM_SP_HYST_CNT 0x00000042 18462d756322SRob Clark 18472d756322SRob Clark #define REG_A6XX_RBBM_SW_RESET_CMD 0x00000043 18482d756322SRob Clark 18492d756322SRob Clark #define REG_A6XX_RBBM_RAC_THRESHOLD_CNT 0x00000044 18502d756322SRob Clark 18512d756322SRob Clark #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 18522d756322SRob Clark 18532d756322SRob Clark #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046 18542d756322SRob Clark 18552d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae 18562d756322SRob Clark 18572d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0 18582d756322SRob Clark 18592d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_SP1 0x000000b1 18602d756322SRob Clark 18612d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_SP2 0x000000b2 18622d756322SRob Clark 18632d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_SP3 0x000000b3 18642d756322SRob Clark 18652d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_SP0 0x000000b4 18662d756322SRob Clark 18672d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_SP1 0x000000b5 18682d756322SRob Clark 18692d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_SP2 0x000000b6 18702d756322SRob Clark 18712d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_SP3 0x000000b7 18722d756322SRob Clark 18732d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_SP0 0x000000b8 18742d756322SRob Clark 18752d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_SP1 0x000000b9 18762d756322SRob Clark 18772d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_SP2 0x000000ba 18782d756322SRob Clark 18792d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_SP3 0x000000bb 18802d756322SRob Clark 18812d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_SP0 0x000000bc 18822d756322SRob Clark 18832d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_SP1 0x000000bd 18842d756322SRob Clark 18852d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_SP2 0x000000be 18862d756322SRob Clark 18872d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_SP3 0x000000bf 18882d756322SRob Clark 18892d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TP0 0x000000c0 18902d756322SRob Clark 18912d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TP1 0x000000c1 18922d756322SRob Clark 18932d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TP2 0x000000c2 18942d756322SRob Clark 18952d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TP3 0x000000c3 18962d756322SRob Clark 18972d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_TP0 0x000000c4 18982d756322SRob Clark 18992d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_TP1 0x000000c5 19002d756322SRob Clark 19012d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_TP2 0x000000c6 19022d756322SRob Clark 19032d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_TP3 0x000000c7 19042d756322SRob Clark 19052d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_TP0 0x000000c8 19062d756322SRob Clark 19072d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_TP1 0x000000c9 19082d756322SRob Clark 19092d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_TP2 0x000000ca 19102d756322SRob Clark 19112d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_TP3 0x000000cb 19122d756322SRob Clark 19132d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_TP0 0x000000cc 19142d756322SRob Clark 19152d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_TP1 0x000000cd 19162d756322SRob Clark 19172d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_TP2 0x000000ce 19182d756322SRob Clark 19192d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_TP3 0x000000cf 19202d756322SRob Clark 19212d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TP0 0x000000d0 19222d756322SRob Clark 19232d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TP1 0x000000d1 19242d756322SRob Clark 19252d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TP2 0x000000d2 19262d756322SRob Clark 19272d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TP3 0x000000d3 19282d756322SRob Clark 19292d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY2_TP0 0x000000d4 19302d756322SRob Clark 19312d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY2_TP1 0x000000d5 19322d756322SRob Clark 19332d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY2_TP2 0x000000d6 19342d756322SRob Clark 19352d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY2_TP3 0x000000d7 19362d756322SRob Clark 19372d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY3_TP0 0x000000d8 19382d756322SRob Clark 19392d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY3_TP1 0x000000d9 19402d756322SRob Clark 19412d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY3_TP2 0x000000da 19422d756322SRob Clark 19432d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY3_TP3 0x000000db 19442d756322SRob Clark 19452d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY4_TP0 0x000000dc 19462d756322SRob Clark 19472d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY4_TP1 0x000000dd 19482d756322SRob Clark 19492d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY4_TP2 0x000000de 19502d756322SRob Clark 19512d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY4_TP3 0x000000df 19522d756322SRob Clark 19532d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TP0 0x000000e0 19542d756322SRob Clark 19552d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TP1 0x000000e1 19562d756322SRob Clark 19572d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TP2 0x000000e2 19582d756322SRob Clark 19592d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TP3 0x000000e3 19602d756322SRob Clark 19612d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST2_TP0 0x000000e4 19622d756322SRob Clark 19632d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST2_TP1 0x000000e5 19642d756322SRob Clark 19652d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST2_TP2 0x000000e6 19662d756322SRob Clark 19672d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST2_TP3 0x000000e7 19682d756322SRob Clark 19692d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST3_TP0 0x000000e8 19702d756322SRob Clark 19712d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST3_TP1 0x000000e9 19722d756322SRob Clark 19732d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST3_TP2 0x000000ea 19742d756322SRob Clark 19752d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST3_TP3 0x000000eb 19762d756322SRob Clark 19772d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST4_TP0 0x000000ec 19782d756322SRob Clark 19792d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST4_TP1 0x000000ed 19802d756322SRob Clark 19812d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST4_TP2 0x000000ee 19822d756322SRob Clark 19832d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST4_TP3 0x000000ef 19842d756322SRob Clark 19852d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RB0 0x000000f0 19862d756322SRob Clark 19872d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RB1 0x000000f1 19882d756322SRob Clark 19892d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RB2 0x000000f2 19902d756322SRob Clark 19912d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RB3 0x000000f3 19922d756322SRob Clark 19932d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RB0 0x000000f4 19942d756322SRob Clark 19952d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RB1 0x000000f5 19962d756322SRob Clark 19972d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RB2 0x000000f6 19982d756322SRob Clark 19992d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RB3 0x000000f7 20002d756322SRob Clark 20012d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_CCU0 0x000000f8 20022d756322SRob Clark 20032d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_CCU1 0x000000f9 20042d756322SRob Clark 20052d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_CCU2 0x000000fa 20062d756322SRob Clark 20072d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_CCU3 0x000000fb 20082d756322SRob Clark 20092d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000100 20102d756322SRob Clark 20112d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000101 20122d756322SRob Clark 20132d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000102 20142d756322SRob Clark 20152d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000103 20162d756322SRob Clark 20172d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RAC 0x00000104 20182d756322SRob Clark 20192d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RAC 0x00000105 20202d756322SRob Clark 20212d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_RAC 0x00000106 20222d756322SRob Clark 20232d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RAC 0x00000107 20242d756322SRob Clark 20252d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000108 20262d756322SRob Clark 20272d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000109 20282d756322SRob Clark 20292d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000010a 20302d756322SRob Clark 20312d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_UCHE 0x0000010b 20322d756322SRob Clark 20332d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE 0x0000010c 20342d756322SRob Clark 20352d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE 0x0000010d 20362d756322SRob Clark 20372d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE 0x0000010e 20382d756322SRob Clark 20392d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_UCHE 0x0000010f 20402d756322SRob Clark 20412d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_UCHE 0x00000110 20422d756322SRob Clark 20432d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_MODE_VFD 0x00000111 20442d756322SRob Clark 20452d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_VFD 0x00000112 20462d756322SRob Clark 20472d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_VFD 0x00000113 20482d756322SRob Clark 20492d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_MODE_GPC 0x00000114 20502d756322SRob Clark 20512d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_GPC 0x00000115 20522d756322SRob Clark 20532d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_GPC 0x00000116 20542d756322SRob Clark 20552d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2 0x00000117 20562d756322SRob Clark 20572d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX 0x00000118 20582d756322SRob Clark 20592d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX 0x00000119 20602d756322SRob Clark 20612d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX 0x0000011a 20622d756322SRob Clark 20632d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_MODE_HLSQ 0x0000011b 20642d756322SRob Clark 20652d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ 0x0000011c 20662d756322SRob Clark 2067c28c82e9SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_HLSQ 0x0000011d 2068c28c82e9SRob Clark 2069c28c82e9SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE 0x00000120 2070c28c82e9SRob Clark 2071c28c82e9SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE 0x00000121 2072c28c82e9SRob Clark 2073c28c82e9SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122 2074c28c82e9SRob Clark 20752d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A 0x00000600 20762d756322SRob Clark 20772d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B 0x00000601 20782d756322SRob Clark 20792d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C 0x00000602 20802d756322SRob Clark 20812d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D 0x00000603 20822d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK 0x000000ff 20832d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT 0 20842d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val) 20852d756322SRob Clark { 20862d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK; 20872d756322SRob Clark } 20882d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK 0x0000ff00 20892d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT 8 20902d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val) 20912d756322SRob Clark { 20922d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK; 20932d756322SRob Clark } 20942d756322SRob Clark 20952d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT 0x00000604 20962d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f 20972d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0 20982d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) 20992d756322SRob Clark { 21002d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; 21012d756322SRob Clark } 21022d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000 21032d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12 21042d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) 21052d756322SRob Clark { 21062d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; 21072d756322SRob Clark } 21082d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000 21092d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28 21102d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) 21112d756322SRob Clark { 21122d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; 21132d756322SRob Clark } 21142d756322SRob Clark 21152d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM 0x00000605 21162d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000 21172d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24 21182d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) 21192d756322SRob Clark { 21202d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; 21212d756322SRob Clark } 21222d756322SRob Clark 21232d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 0x00000608 21242d756322SRob Clark 21252d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 0x00000609 21262d756322SRob Clark 21272d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 0x0000060a 21282d756322SRob Clark 21292d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 0x0000060b 21302d756322SRob Clark 21312d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 0x0000060c 21322d756322SRob Clark 21332d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 0x0000060d 21342d756322SRob Clark 21352d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 0x0000060e 21362d756322SRob Clark 21372d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 0x0000060f 21382d756322SRob Clark 21392d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000610 21402d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f 21412d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0 21422d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) 21432d756322SRob Clark { 21442d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; 21452d756322SRob Clark } 21462d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0 21472d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4 21482d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) 21492d756322SRob Clark { 21502d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; 21512d756322SRob Clark } 21522d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00 21532d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8 21542d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) 21552d756322SRob Clark { 21562d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; 21572d756322SRob Clark } 21582d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000 21592d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12 21602d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) 21612d756322SRob Clark { 21622d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; 21632d756322SRob Clark } 21642d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000 21652d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16 21662d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) 21672d756322SRob Clark { 21682d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; 21692d756322SRob Clark } 21702d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000 21712d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20 21722d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) 21732d756322SRob Clark { 21742d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; 21752d756322SRob Clark } 21762d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000 21772d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24 21782d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) 21792d756322SRob Clark { 21802d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; 21812d756322SRob Clark } 21822d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000 21832d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28 21842d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) 21852d756322SRob Clark { 21862d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; 21872d756322SRob Clark } 21882d756322SRob Clark 21892d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000611 21902d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f 21912d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0 21922d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) 21932d756322SRob Clark { 21942d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; 21952d756322SRob Clark } 21962d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0 21972d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4 21982d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) 21992d756322SRob Clark { 22002d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; 22012d756322SRob Clark } 22022d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00 22032d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8 22042d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) 22052d756322SRob Clark { 22062d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; 22072d756322SRob Clark } 22082d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000 22092d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12 22102d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) 22112d756322SRob Clark { 22122d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; 22132d756322SRob Clark } 22142d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000 22152d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16 22162d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) 22172d756322SRob Clark { 22182d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; 22192d756322SRob Clark } 22202d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000 22212d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20 22222d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) 22232d756322SRob Clark { 22242d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; 22252d756322SRob Clark } 22262d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000 22272d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24 22282d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) 22292d756322SRob Clark { 22302d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; 22312d756322SRob Clark } 22322d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000 22332d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28 22342d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) 22352d756322SRob Clark { 22362d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; 22372d756322SRob Clark } 22382d756322SRob Clark 22392d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000062f 22402d756322SRob Clark 22412d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630 22422d756322SRob Clark 22432d756322SRob Clark #define REG_A6XX_VSC_PERFCTR_VSC_SEL_0 0x00000cd8 22442d756322SRob Clark 22452d756322SRob Clark #define REG_A6XX_VSC_PERFCTR_VSC_SEL_1 0x00000cd9 22462d756322SRob Clark 22472d756322SRob Clark #define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05 22482d756322SRob Clark 22492d756322SRob Clark #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x0000be10 22502d756322SRob Clark 22512d756322SRob Clark #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x0000be11 22522d756322SRob Clark 22532d756322SRob Clark #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x0000be12 22542d756322SRob Clark 22552d756322SRob Clark #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x0000be13 22562d756322SRob Clark 22572d756322SRob Clark #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x0000be14 22582d756322SRob Clark 22592d756322SRob Clark #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x0000be15 22602d756322SRob Clark 22612d756322SRob Clark #define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800 22622d756322SRob Clark 22632d756322SRob Clark #define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000 22642d756322SRob Clark 22652d756322SRob Clark #define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601 22662d756322SRob Clark 22672d756322SRob Clark #define REG_A6XX_VFD_PERFCTR_VFD_SEL_0 0x0000a610 22682d756322SRob Clark 22692d756322SRob Clark #define REG_A6XX_VFD_PERFCTR_VFD_SEL_1 0x0000a611 22702d756322SRob Clark 22712d756322SRob Clark #define REG_A6XX_VFD_PERFCTR_VFD_SEL_2 0x0000a612 22722d756322SRob Clark 22732d756322SRob Clark #define REG_A6XX_VFD_PERFCTR_VFD_SEL_3 0x0000a613 22742d756322SRob Clark 22752d756322SRob Clark #define REG_A6XX_VFD_PERFCTR_VFD_SEL_4 0x0000a614 22762d756322SRob Clark 22772d756322SRob Clark #define REG_A6XX_VFD_PERFCTR_VFD_SEL_5 0x0000a615 22782d756322SRob Clark 22792d756322SRob Clark #define REG_A6XX_VFD_PERFCTR_VFD_SEL_6 0x0000a616 22802d756322SRob Clark 22812d756322SRob Clark #define REG_A6XX_VFD_PERFCTR_VFD_SEL_7 0x0000a617 22822d756322SRob Clark 22832d756322SRob Clark #define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00 22842d756322SRob Clark 22852d756322SRob Clark #define REG_A6XX_UCHE_MODE_CNTL 0x00000e01 22862d756322SRob Clark 22872d756322SRob Clark #define REG_A6XX_UCHE_WRITE_RANGE_MAX_LO 0x00000e05 22882d756322SRob Clark 22892d756322SRob Clark #define REG_A6XX_UCHE_WRITE_RANGE_MAX_HI 0x00000e06 22902d756322SRob Clark 22912d756322SRob Clark #define REG_A6XX_UCHE_WRITE_THRU_BASE_LO 0x00000e07 22922d756322SRob Clark 22932d756322SRob Clark #define REG_A6XX_UCHE_WRITE_THRU_BASE_HI 0x00000e08 22942d756322SRob Clark 22952d756322SRob Clark #define REG_A6XX_UCHE_TRAP_BASE_LO 0x00000e09 22962d756322SRob Clark 22972d756322SRob Clark #define REG_A6XX_UCHE_TRAP_BASE_HI 0x00000e0a 22982d756322SRob Clark 22992d756322SRob Clark #define REG_A6XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e0b 23002d756322SRob Clark 23012d756322SRob Clark #define REG_A6XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e0c 23022d756322SRob Clark 23032d756322SRob Clark #define REG_A6XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e0d 23042d756322SRob Clark 23052d756322SRob Clark #define REG_A6XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e0e 23062d756322SRob Clark 23072d756322SRob Clark #define REG_A6XX_UCHE_CACHE_WAYS 0x00000e17 23082d756322SRob Clark 23092d756322SRob Clark #define REG_A6XX_UCHE_FILTER_CNTL 0x00000e18 23102d756322SRob Clark 23112d756322SRob Clark #define REG_A6XX_UCHE_CLIENT_PF 0x00000e19 23122d756322SRob Clark #define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK 0x000000ff 23132d756322SRob Clark #define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT 0 23142d756322SRob Clark static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val) 23152d756322SRob Clark { 23162d756322SRob Clark return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK; 23172d756322SRob Clark } 23182d756322SRob Clark 23192d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e1c 23202d756322SRob Clark 23212d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e1d 23222d756322SRob Clark 23232d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e1e 23242d756322SRob Clark 23252d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e1f 23262d756322SRob Clark 23272d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e20 23282d756322SRob Clark 23292d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e21 23302d756322SRob Clark 23312d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e22 23322d756322SRob Clark 23332d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e23 23342d756322SRob Clark 23352d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_8 0x00000e24 23362d756322SRob Clark 23372d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_9 0x00000e25 23382d756322SRob Clark 23392d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_10 0x00000e26 23402d756322SRob Clark 23412d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_11 0x00000e27 23422d756322SRob Clark 23432d756322SRob Clark #define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01 23442d756322SRob Clark 23452d756322SRob Clark #define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02 23462d756322SRob Clark 23472d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_0 0x0000ae10 23482d756322SRob Clark 23492d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_1 0x0000ae11 23502d756322SRob Clark 23512d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_2 0x0000ae12 23522d756322SRob Clark 23532d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_3 0x0000ae13 23542d756322SRob Clark 23552d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_4 0x0000ae14 23562d756322SRob Clark 23572d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_5 0x0000ae15 23582d756322SRob Clark 23592d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_6 0x0000ae16 23602d756322SRob Clark 23612d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_7 0x0000ae17 23622d756322SRob Clark 23632d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_8 0x0000ae18 23642d756322SRob Clark 23652d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_9 0x0000ae19 23662d756322SRob Clark 23672d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_10 0x0000ae1a 23682d756322SRob Clark 23692d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_11 0x0000ae1b 23702d756322SRob Clark 23712d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_12 0x0000ae1c 23722d756322SRob Clark 23732d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_13 0x0000ae1d 23742d756322SRob Clark 23752d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_14 0x0000ae1e 23762d756322SRob Clark 23772d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_15 0x0000ae1f 23782d756322SRob Clark 23792d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_16 0x0000ae20 23802d756322SRob Clark 23812d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_17 0x0000ae21 23822d756322SRob Clark 23832d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_18 0x0000ae22 23842d756322SRob Clark 23852d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_19 0x0000ae23 23862d756322SRob Clark 23872d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_20 0x0000ae24 23882d756322SRob Clark 23892d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_21 0x0000ae25 23902d756322SRob Clark 23912d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_22 0x0000ae26 23922d756322SRob Clark 23932d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_23 0x0000ae27 23942d756322SRob Clark 23952d756322SRob Clark #define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601 23962d756322SRob Clark 23972d756322SRob Clark #define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604 23982d756322SRob Clark 239924e6938eSJonathan Marek #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608 240024e6938eSJonathan Marek 240124e6938eSJonathan Marek #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609 240224e6938eSJonathan Marek 240324e6938eSJonathan Marek #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a 240424e6938eSJonathan Marek 240524e6938eSJonathan Marek #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b 240624e6938eSJonathan Marek 240724e6938eSJonathan Marek #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c 240824e6938eSJonathan Marek 24092d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_0 0x0000b610 24102d756322SRob Clark 24112d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_1 0x0000b611 24122d756322SRob Clark 24132d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_2 0x0000b612 24142d756322SRob Clark 24152d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_3 0x0000b613 24162d756322SRob Clark 24172d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_4 0x0000b614 24182d756322SRob Clark 24192d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_5 0x0000b615 24202d756322SRob Clark 24212d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_6 0x0000b616 24222d756322SRob Clark 24232d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_7 0x0000b617 24242d756322SRob Clark 24252d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_8 0x0000b618 24262d756322SRob Clark 24272d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_9 0x0000b619 24282d756322SRob Clark 24292d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_10 0x0000b61a 24302d756322SRob Clark 24312d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_11 0x0000b61b 24322d756322SRob Clark 24332d756322SRob Clark #define REG_A6XX_VBIF_VERSION 0x00003000 24342d756322SRob Clark 2435a69c5ed2SRob Clark #define REG_A6XX_VBIF_CLKON 0x00003001 2436a69c5ed2SRob Clark #define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000002 2437a69c5ed2SRob Clark 24382d756322SRob Clark #define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 24392d756322SRob Clark 24402d756322SRob Clark #define REG_A6XX_VBIF_XIN_HALT_CTRL0 0x00003080 24412d756322SRob Clark 24422d756322SRob Clark #define REG_A6XX_VBIF_XIN_HALT_CTRL1 0x00003081 24432d756322SRob Clark 2444a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084 2445a69c5ed2SRob Clark 2446a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS1_CTRL0 0x00003085 2447a69c5ed2SRob Clark 2448a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS1_CTRL1 0x00003086 2449a69c5ed2SRob Clark #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK 0x0000000f 2450a69c5ed2SRob Clark #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT 0 2451a69c5ed2SRob Clark static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val) 2452a69c5ed2SRob Clark { 2453a69c5ed2SRob Clark return ((val) << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK; 2454a69c5ed2SRob Clark } 2455a69c5ed2SRob Clark 2456a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS2_CTRL0 0x00003087 2457a69c5ed2SRob Clark 2458a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS2_CTRL1 0x00003088 2459a69c5ed2SRob Clark #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK 0x000001ff 2460a69c5ed2SRob Clark #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT 0 2461a69c5ed2SRob Clark static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val) 2462a69c5ed2SRob Clark { 2463a69c5ed2SRob Clark return ((val) << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK; 2464a69c5ed2SRob Clark } 2465a69c5ed2SRob Clark 2466a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS_OUT 0x0000308c 2467a69c5ed2SRob Clark 24682d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_SEL0 0x000030d0 24692d756322SRob Clark 24702d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_SEL1 0x000030d1 24712d756322SRob Clark 24722d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_SEL2 0x000030d2 24732d756322SRob Clark 24742d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_SEL3 0x000030d3 24752d756322SRob Clark 24762d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_LOW0 0x000030d8 24772d756322SRob Clark 24782d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_LOW1 0x000030d9 24792d756322SRob Clark 24802d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_LOW2 0x000030da 24812d756322SRob Clark 24822d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_LOW3 0x000030db 24832d756322SRob Clark 24842d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_HIGH0 0x000030e0 24852d756322SRob Clark 24862d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_HIGH1 0x000030e1 24872d756322SRob Clark 24882d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_HIGH2 0x000030e2 24892d756322SRob Clark 24902d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_HIGH3 0x000030e3 24912d756322SRob Clark 24922d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_EN0 0x00003100 24932d756322SRob Clark 24942d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_EN1 0x00003101 24952d756322SRob Clark 24962d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_EN2 0x00003102 24972d756322SRob Clark 24982d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110 24992d756322SRob Clark 25002d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111 25012d756322SRob Clark 25022d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112 25032d756322SRob Clark 25042d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118 25052d756322SRob Clark 25062d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119 25072d756322SRob Clark 25082d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a 25092d756322SRob Clark 2510e812744cSSharat Masetty #define REG_A6XX_GBIF_SCACHE_CNTL1 0x00003c02 2511e812744cSSharat Masetty 2512e812744cSSharat Masetty #define REG_A6XX_GBIF_QSB_SIDE0 0x00003c03 2513e812744cSSharat Masetty 2514e812744cSSharat Masetty #define REG_A6XX_GBIF_QSB_SIDE1 0x00003c04 2515e812744cSSharat Masetty 2516e812744cSSharat Masetty #define REG_A6XX_GBIF_QSB_SIDE2 0x00003c05 2517e812744cSSharat Masetty 2518e812744cSSharat Masetty #define REG_A6XX_GBIF_QSB_SIDE3 0x00003c06 2519e812744cSSharat Masetty 2520e812744cSSharat Masetty #define REG_A6XX_GBIF_HALT 0x00003c45 2521e812744cSSharat Masetty 2522e812744cSSharat Masetty #define REG_A6XX_GBIF_HALT_ACK 0x00003c46 2523e812744cSSharat Masetty 2524e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_PWR_CNT_EN 0x00003cc0 2525e812744cSSharat Masetty 2526e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_SEL 0x00003cc2 2527e812744cSSharat Masetty 2528e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_PWR_CNT_SEL 0x00003cc3 2529e812744cSSharat Masetty 2530e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_LOW0 0x00003cc4 2531e812744cSSharat Masetty 2532e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_LOW1 0x00003cc5 2533e812744cSSharat Masetty 2534e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_LOW2 0x00003cc6 2535e812744cSSharat Masetty 2536e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_LOW3 0x00003cc7 2537e812744cSSharat Masetty 2538e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_HIGH0 0x00003cc8 2539e812744cSSharat Masetty 2540e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_HIGH1 0x00003cc9 2541e812744cSSharat Masetty 2542e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_HIGH2 0x00003cca 2543e812744cSSharat Masetty 2544e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_HIGH3 0x00003ccb 2545e812744cSSharat Masetty 2546e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_LOW0 0x00003ccc 2547e812744cSSharat Masetty 2548e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_LOW1 0x00003ccd 2549e812744cSSharat Masetty 2550e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_LOW2 0x00003cce 2551e812744cSSharat Masetty 2552e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_HIGH0 0x00003ccf 2553e812744cSSharat Masetty 2554e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_HIGH1 0x00003cd0 2555e812744cSSharat Masetty 2556e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_HIGH2 0x00003cd1 2557e812744cSSharat Masetty 2558a69c5ed2SRob Clark #define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1 2559a69c5ed2SRob Clark #define A6XX_SP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 2560a69c5ed2SRob Clark #define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00007fff 2561a69c5ed2SRob Clark #define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0 2562a69c5ed2SRob Clark static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val) 25632d756322SRob Clark { 2564a69c5ed2SRob Clark return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK; 25652d756322SRob Clark } 2566a69c5ed2SRob Clark #define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x7fff0000 2567a69c5ed2SRob Clark #define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16 2568a69c5ed2SRob Clark static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val) 25692d756322SRob Clark { 2570a69c5ed2SRob Clark return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK; 25712d756322SRob Clark } 25722d756322SRob Clark 2573a69c5ed2SRob Clark #define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307 2574a69c5ed2SRob Clark #define A6XX_SP_TP_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 2575a69c5ed2SRob Clark #define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00007fff 2576a69c5ed2SRob Clark #define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0 2577a69c5ed2SRob Clark static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val) 25782d756322SRob Clark { 2579a69c5ed2SRob Clark return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK; 2580a69c5ed2SRob Clark } 2581a69c5ed2SRob Clark #define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x7fff0000 2582a69c5ed2SRob Clark #define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16 2583a69c5ed2SRob Clark static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val) 2584a69c5ed2SRob Clark { 2585a69c5ed2SRob Clark return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK; 25862d756322SRob Clark } 25872d756322SRob Clark 25882d756322SRob Clark #define REG_A6XX_VSC_BIN_SIZE 0x00000c02 25892d756322SRob Clark #define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff 25902d756322SRob Clark #define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 25912d756322SRob Clark static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 25922d756322SRob Clark { 25932d756322SRob Clark return ((val >> 5) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK; 25942d756322SRob Clark } 25952d756322SRob Clark #define A6XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001ff00 25962d756322SRob Clark #define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT 8 25972d756322SRob Clark static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 25982d756322SRob Clark { 25992d756322SRob Clark return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK; 26002d756322SRob Clark } 26012d756322SRob Clark 2602c28c82e9SRob Clark #define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS_LO 0x00000c03 26032d756322SRob Clark 2604c28c82e9SRob Clark #define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS_HI 0x00000c04 2605c28c82e9SRob Clark 2606c28c82e9SRob Clark #define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS 0x00000c03 26072d756322SRob Clark 26082d756322SRob Clark #define REG_A6XX_VSC_BIN_COUNT 0x00000c06 26092d756322SRob Clark #define A6XX_VSC_BIN_COUNT_NX__MASK 0x000007fe 26102d756322SRob Clark #define A6XX_VSC_BIN_COUNT_NX__SHIFT 1 26112d756322SRob Clark static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val) 26122d756322SRob Clark { 26132d756322SRob Clark return ((val) << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK; 26142d756322SRob Clark } 26152d756322SRob Clark #define A6XX_VSC_BIN_COUNT_NY__MASK 0x001ff800 26162d756322SRob Clark #define A6XX_VSC_BIN_COUNT_NY__SHIFT 11 26172d756322SRob Clark static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val) 26182d756322SRob Clark { 26192d756322SRob Clark return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK; 26202d756322SRob Clark } 26212d756322SRob Clark 26222d756322SRob Clark static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 26232d756322SRob Clark 26242d756322SRob Clark static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 26252d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff 26262d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0 26272d756322SRob Clark static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) 26282d756322SRob Clark { 26292d756322SRob Clark return ((val) << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK; 26302d756322SRob Clark } 26312d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00 26322d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10 26332d756322SRob Clark static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) 26342d756322SRob Clark { 26352d756322SRob Clark return ((val) << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK; 26362d756322SRob Clark } 26372d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_W__MASK 0x03f00000 26382d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20 26392d756322SRob Clark static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) 26402d756322SRob Clark { 26412d756322SRob Clark return ((val) << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK; 26422d756322SRob Clark } 26432d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_H__MASK 0xfc000000 26442d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT 26 26452d756322SRob Clark static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) 26462d756322SRob Clark { 26472d756322SRob Clark return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK; 26482d756322SRob Clark } 26492d756322SRob Clark 2650c28c82e9SRob Clark #define REG_A6XX_VSC_PRIM_STRM_ADDRESS_LO 0x00000c30 26512d756322SRob Clark 2652c28c82e9SRob Clark #define REG_A6XX_VSC_PRIM_STRM_ADDRESS_HI 0x00000c31 26532d756322SRob Clark 2654c28c82e9SRob Clark #define REG_A6XX_VSC_PRIM_STRM_ADDRESS 0x00000c30 2655a69c5ed2SRob Clark 2656c28c82e9SRob Clark #define REG_A6XX_VSC_PRIM_STRM_PITCH 0x00000c32 26572d756322SRob Clark 2658c28c82e9SRob Clark #define REG_A6XX_VSC_PRIM_STRM_LIMIT 0x00000c33 26592d756322SRob Clark 2660c28c82e9SRob Clark #define REG_A6XX_VSC_DRAW_STRM_ADDRESS_LO 0x00000c34 26612d756322SRob Clark 2662c28c82e9SRob Clark #define REG_A6XX_VSC_DRAW_STRM_ADDRESS_HI 0x00000c35 26632d756322SRob Clark 2664c28c82e9SRob Clark #define REG_A6XX_VSC_DRAW_STRM_ADDRESS 0x00000c34 2665a69c5ed2SRob Clark 2666c28c82e9SRob Clark #define REG_A6XX_VSC_DRAW_STRM_PITCH 0x00000c36 26672d756322SRob Clark 2668c28c82e9SRob Clark #define REG_A6XX_VSC_DRAW_STRM_LIMIT 0x00000c37 2669c28c82e9SRob Clark 2670c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_STATE(uint32_t i0) { return 0x00000c38 + 0x1*i0; } 2671c28c82e9SRob Clark 2672c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_STATE_REG(uint32_t i0) { return 0x00000c38 + 0x1*i0; } 2673c28c82e9SRob Clark 2674c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE(uint32_t i0) { return 0x00000c58 + 0x1*i0; } 2675c28c82e9SRob Clark 2676c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0) { return 0x00000c58 + 0x1*i0; } 2677c28c82e9SRob Clark 2678c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; } 2679c28c82e9SRob Clark 2680c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; } 26812d756322SRob Clark 26822d756322SRob Clark #define REG_A6XX_UCHE_UNKNOWN_0E12 0x00000e12 26832d756322SRob Clark 2684c28c82e9SRob Clark #define REG_A6XX_GRAS_CL_CNTL 0x00008000 2685c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_CLIP_DISABLE 0x00000001 2686c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE 0x00000002 2687c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE 0x00000004 2688c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_UNK5 0x00000020 2689c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040 2690c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE 0x00000080 2691c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE 0x00000100 2692c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE 0x00000200 2693a69c5ed2SRob Clark 2694c28c82e9SRob Clark #define REG_A6XX_GRAS_VS_CL_CNTL 0x00008001 2695c28c82e9SRob Clark #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK 0x000000ff 2696c28c82e9SRob Clark #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT 0 2697c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val) 2698c28c82e9SRob Clark { 2699c28c82e9SRob Clark return ((val) << A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK; 2700c28c82e9SRob Clark } 2701c28c82e9SRob Clark #define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK 0x0000ff00 2702c28c82e9SRob Clark #define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT 8 2703c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val) 2704c28c82e9SRob Clark { 2705c28c82e9SRob Clark return ((val) << A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK; 2706c28c82e9SRob Clark } 27072d756322SRob Clark 2708c28c82e9SRob Clark #define REG_A6XX_GRAS_DS_CL_CNTL 0x00008002 2709c28c82e9SRob Clark #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK 0x000000ff 2710c28c82e9SRob Clark #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT 0 2711c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(uint32_t val) 2712c28c82e9SRob Clark { 2713c28c82e9SRob Clark return ((val) << A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK; 2714c28c82e9SRob Clark } 2715c28c82e9SRob Clark #define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK 0x0000ff00 2716c28c82e9SRob Clark #define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT 8 2717c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CULL_MASK(uint32_t val) 2718c28c82e9SRob Clark { 2719c28c82e9SRob Clark return ((val) << A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK; 2720c28c82e9SRob Clark } 2721c28c82e9SRob Clark 2722c28c82e9SRob Clark #define REG_A6XX_GRAS_GS_CL_CNTL 0x00008003 2723c28c82e9SRob Clark #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK 0x000000ff 2724c28c82e9SRob Clark #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT 0 2725c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(uint32_t val) 2726c28c82e9SRob Clark { 2727c28c82e9SRob Clark return ((val) << A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK; 2728c28c82e9SRob Clark } 2729c28c82e9SRob Clark #define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK 0x0000ff00 2730c28c82e9SRob Clark #define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT 8 2731c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CULL_MASK(uint32_t val) 2732c28c82e9SRob Clark { 2733c28c82e9SRob Clark return ((val) << A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK; 2734c28c82e9SRob Clark } 2735c28c82e9SRob Clark 2736c28c82e9SRob Clark #define REG_A6XX_GRAS_MAX_LAYER_INDEX 0x00008004 27372d756322SRob Clark 27382d756322SRob Clark #define REG_A6XX_GRAS_CNTL 0x00008005 2739c28c82e9SRob Clark #define A6XX_GRAS_CNTL_IJ_PERSP_PIXEL 0x00000001 2740c28c82e9SRob Clark #define A6XX_GRAS_CNTL_IJ_PERSP_CENTROID 0x00000002 2741c28c82e9SRob Clark #define A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE 0x00000004 2742c28c82e9SRob Clark #define A6XX_GRAS_CNTL_SIZE 0x00000008 2743c28c82e9SRob Clark #define A6XX_GRAS_CNTL_UNK4 0x00000010 2744c28c82e9SRob Clark #define A6XX_GRAS_CNTL_SIZE_PERSAMP 0x00000020 2745c28c82e9SRob Clark #define A6XX_GRAS_CNTL_COORD_MASK__MASK 0x000003c0 2746c28c82e9SRob Clark #define A6XX_GRAS_CNTL_COORD_MASK__SHIFT 6 2747c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CNTL_COORD_MASK(uint32_t val) 2748c28c82e9SRob Clark { 2749c28c82e9SRob Clark return ((val) << A6XX_GRAS_CNTL_COORD_MASK__SHIFT) & A6XX_GRAS_CNTL_COORD_MASK__MASK; 2750c28c82e9SRob Clark } 27512d756322SRob Clark 27522d756322SRob Clark #define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x00008006 2753c28c82e9SRob Clark #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000001ff 27542d756322SRob Clark #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0 27552d756322SRob Clark static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val) 27562d756322SRob Clark { 27572d756322SRob Clark return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK; 27582d756322SRob Clark } 2759c28c82e9SRob Clark #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x0007fc00 27602d756322SRob Clark #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10 27612d756322SRob Clark static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) 27622d756322SRob Clark { 27632d756322SRob Clark return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK; 27642d756322SRob Clark } 27652d756322SRob Clark 2766c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT(uint32_t i0) { return 0x00008010 + 0x6*i0; } 2767c28c82e9SRob Clark 2768c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0) { return 0x00008010 + 0x6*i0; } 2769c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff 2770c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0 2771c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET(float val) 27722d756322SRob Clark { 2773c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET__MASK; 27742d756322SRob Clark } 27752d756322SRob Clark 2776c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XSCALE(uint32_t i0) { return 0x00008011 + 0x6*i0; } 2777c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff 2778c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_XSCALE__SHIFT 0 2779c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE(float val) 27802d756322SRob Clark { 2781c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE__MASK; 27822d756322SRob Clark } 27832d756322SRob Clark 2784c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YOFFSET(uint32_t i0) { return 0x00008012 + 0x6*i0; } 2785c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff 2786c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0 2787c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET(float val) 27882d756322SRob Clark { 2789c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET__MASK; 27902d756322SRob Clark } 27912d756322SRob Clark 2792c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YSCALE(uint32_t i0) { return 0x00008013 + 0x6*i0; } 2793c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff 2794c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_YSCALE__SHIFT 0 2795c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE(float val) 27962d756322SRob Clark { 2797c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE__MASK; 27982d756322SRob Clark } 27992d756322SRob Clark 2800c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZOFFSET(uint32_t i0) { return 0x00008014 + 0x6*i0; } 2801c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff 2802c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0 2803c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET(float val) 28042d756322SRob Clark { 2805c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET__MASK; 28062d756322SRob Clark } 28072d756322SRob Clark 2808c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZSCALE(uint32_t i0) { return 0x00008015 + 0x6*i0; } 2809c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff 2810c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0 2811c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE(float val) 28122d756322SRob Clark { 2813c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE__MASK; 2814c28c82e9SRob Clark } 2815c28c82e9SRob Clark 2816c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP(uint32_t i0) { return 0x00008070 + 0x2*i0; } 2817c28c82e9SRob Clark 2818c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0) { return 0x00008070 + 0x2*i0; } 2819c28c82e9SRob Clark #define A6XX_GRAS_CL_Z_CLAMP_MIN__MASK 0xffffffff 2820c28c82e9SRob Clark #define A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT 0 2821c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MIN(float val) 2822c28c82e9SRob Clark { 2823c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MIN__MASK; 2824c28c82e9SRob Clark } 2825c28c82e9SRob Clark 2826c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MAX(uint32_t i0) { return 0x00008071 + 0x2*i0; } 2827c28c82e9SRob Clark #define A6XX_GRAS_CL_Z_CLAMP_MAX__MASK 0xffffffff 2828c28c82e9SRob Clark #define A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT 0 2829c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MAX(float val) 2830c28c82e9SRob Clark { 2831c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MAX__MASK; 28322d756322SRob Clark } 28332d756322SRob Clark 28342d756322SRob Clark #define REG_A6XX_GRAS_SU_CNTL 0x00008090 28352d756322SRob Clark #define A6XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001 28362d756322SRob Clark #define A6XX_GRAS_SU_CNTL_CULL_BACK 0x00000002 28372d756322SRob Clark #define A6XX_GRAS_SU_CNTL_FRONT_CW 0x00000004 28382d756322SRob Clark #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8 28392d756322SRob Clark #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3 28402d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) 28412d756322SRob Clark { 28422d756322SRob Clark return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK; 28432d756322SRob Clark } 28442d756322SRob Clark #define A6XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800 2845c28c82e9SRob Clark #define A6XX_GRAS_SU_CNTL_UNK12__MASK 0x00001000 2846c28c82e9SRob Clark #define A6XX_GRAS_SU_CNTL_UNK12__SHIFT 12 2847c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SU_CNTL_UNK12(uint32_t val) 2848c28c82e9SRob Clark { 2849c28c82e9SRob Clark return ((val) << A6XX_GRAS_SU_CNTL_UNK12__SHIFT) & A6XX_GRAS_SU_CNTL_UNK12__MASK; 2850c28c82e9SRob Clark } 28512d756322SRob Clark #define A6XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000 2852c28c82e9SRob Clark #define A6XX_GRAS_SU_CNTL_UNK15__MASK 0x007f8000 2853c28c82e9SRob Clark #define A6XX_GRAS_SU_CNTL_UNK15__SHIFT 15 2854c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SU_CNTL_UNK15(uint32_t val) 2855c28c82e9SRob Clark { 2856c28c82e9SRob Clark return ((val) << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK; 2857c28c82e9SRob Clark } 28582d756322SRob Clark 28592d756322SRob Clark #define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091 28602d756322SRob Clark #define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 28612d756322SRob Clark #define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 28622d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val) 28632d756322SRob Clark { 28642d756322SRob Clark return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 28652d756322SRob Clark } 28662d756322SRob Clark #define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 28672d756322SRob Clark #define A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 28682d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MAX(float val) 28692d756322SRob Clark { 28702d756322SRob Clark return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 28712d756322SRob Clark } 28722d756322SRob Clark 28732d756322SRob Clark #define REG_A6XX_GRAS_SU_POINT_SIZE 0x00008092 2874c28c82e9SRob Clark #define A6XX_GRAS_SU_POINT_SIZE__MASK 0x0000ffff 28752d756322SRob Clark #define A6XX_GRAS_SU_POINT_SIZE__SHIFT 0 28762d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val) 28772d756322SRob Clark { 28782d756322SRob Clark return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK; 28792d756322SRob Clark } 28802d756322SRob Clark 2881a69c5ed2SRob Clark #define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL 0x00008094 2882c28c82e9SRob Clark #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003 2883c28c82e9SRob Clark #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0 2884c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val) 2885c28c82e9SRob Clark { 2886c28c82e9SRob Clark return ((val) << A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK; 2887c28c82e9SRob Clark } 2888a69c5ed2SRob Clark 28892d756322SRob Clark #define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE 0x00008095 28902d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff 28912d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 28922d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val) 28932d756322SRob Clark { 28942d756322SRob Clark return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; 28952d756322SRob Clark } 28962d756322SRob Clark 28972d756322SRob Clark #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00008096 28982d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 28992d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 29002d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 29012d756322SRob Clark { 29022d756322SRob Clark return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 29032d756322SRob Clark } 29042d756322SRob Clark 29052d756322SRob Clark #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x00008097 29062d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff 29072d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0 29082d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val) 29092d756322SRob Clark { 29102d756322SRob Clark return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK; 29112d756322SRob Clark } 29122d756322SRob Clark 29132d756322SRob Clark #define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO 0x00008098 29142d756322SRob Clark #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 29152d756322SRob Clark #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 29162d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) 29172d756322SRob Clark { 29182d756322SRob Clark return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; 29192d756322SRob Clark } 2920c28c82e9SRob Clark #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000008 2921c28c82e9SRob Clark #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT 3 2922c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3(uint32_t val) 2923c28c82e9SRob Clark { 2924c28c82e9SRob Clark return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK; 2925c28c82e9SRob Clark } 29262d756322SRob Clark 29272d756322SRob Clark #define REG_A6XX_GRAS_UNKNOWN_8099 0x00008099 29282d756322SRob Clark 2929c28c82e9SRob Clark #define REG_A6XX_GRAS_UNKNOWN_809A 0x0000809a 2930c28c82e9SRob Clark 2931c28c82e9SRob Clark #define REG_A6XX_GRAS_VS_LAYER_CNTL 0x0000809b 2932c28c82e9SRob Clark #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER 0x00000001 2933c28c82e9SRob Clark #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW 0x00000002 2934c28c82e9SRob Clark 2935c28c82e9SRob Clark #define REG_A6XX_GRAS_GS_LAYER_CNTL 0x0000809c 2936c28c82e9SRob Clark #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER 0x00000001 2937c28c82e9SRob Clark #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW 0x00000002 2938c28c82e9SRob Clark 2939c28c82e9SRob Clark #define REG_A6XX_GRAS_DS_LAYER_CNTL 0x0000809d 2940c28c82e9SRob Clark #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER 0x00000001 2941c28c82e9SRob Clark #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW 0x00000002 29422d756322SRob Clark 2943a69c5ed2SRob Clark #define REG_A6XX_GRAS_UNKNOWN_80A0 0x000080a0 2944a69c5ed2SRob Clark 2945c28c82e9SRob Clark #define REG_A6XX_GRAS_BIN_CONTROL 0x000080a1 2946c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_BINW__MASK 0x0000003f 2947c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT 0 2948c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val) 2949c28c82e9SRob Clark { 2950c28c82e9SRob Clark return ((val >> 5) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK; 2951c28c82e9SRob Clark } 2952c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_BINH__MASK 0x00007f00 2953c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT 8 2954c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val) 2955c28c82e9SRob Clark { 2956c28c82e9SRob Clark return ((val >> 4) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK; 2957c28c82e9SRob Clark } 2958c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_BINNING_PASS 0x00040000 2959c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_UNK19__MASK 0x00080000 2960c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_UNK19__SHIFT 19 2961c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK19(uint32_t val) 2962c28c82e9SRob Clark { 2963c28c82e9SRob Clark return ((val) << A6XX_GRAS_BIN_CONTROL_UNK19__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK19__MASK; 2964c28c82e9SRob Clark } 2965c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_UNK20__MASK 0x00100000 2966c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_UNK20__SHIFT 20 2967c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK20(uint32_t val) 2968c28c82e9SRob Clark { 2969c28c82e9SRob Clark return ((val) << A6XX_GRAS_BIN_CONTROL_UNK20__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK20__MASK; 2970c28c82e9SRob Clark } 2971c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_USE_VIZ 0x00200000 2972c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_UNK22__MASK 0x0fc00000 2973c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_UNK22__SHIFT 22 2974c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK22(uint32_t val) 2975c28c82e9SRob Clark { 2976c28c82e9SRob Clark return ((val) << A6XX_GRAS_BIN_CONTROL_UNK22__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK22__MASK; 2977c28c82e9SRob Clark } 2978c28c82e9SRob Clark 29792d756322SRob Clark #define REG_A6XX_GRAS_RAS_MSAA_CNTL 0x000080a2 29802d756322SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 29812d756322SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 29822d756322SRob Clark static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 29832d756322SRob Clark { 29842d756322SRob Clark return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK; 29852d756322SRob Clark } 2986c28c82e9SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK 0x00000004 2987c28c82e9SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT 2 2988c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK2(uint32_t val) 2989c28c82e9SRob Clark { 2990c28c82e9SRob Clark return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK; 2991c28c82e9SRob Clark } 2992c28c82e9SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK 0x00000008 2993c28c82e9SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT 3 2994c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK3(uint32_t val) 2995c28c82e9SRob Clark { 2996c28c82e9SRob Clark return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK; 2997c28c82e9SRob Clark } 29982d756322SRob Clark 29992d756322SRob Clark #define REG_A6XX_GRAS_DEST_MSAA_CNTL 0x000080a3 30002d756322SRob Clark #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 30012d756322SRob Clark #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 30022d756322SRob Clark static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 30032d756322SRob Clark { 30042d756322SRob Clark return ((val) << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK; 30052d756322SRob Clark } 30062d756322SRob Clark #define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 30072d756322SRob Clark 3008c28c82e9SRob Clark #define REG_A6XX_GRAS_SAMPLE_CONFIG 0x000080a4 3009c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_CONFIG_UNK0 0x00000001 3010c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002 30112d756322SRob Clark 3012c28c82e9SRob Clark #define REG_A6XX_GRAS_SAMPLE_LOCATION_0 0x000080a5 3013c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f 3014c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 3015c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) 3016c28c82e9SRob Clark { 3017c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; 3018c28c82e9SRob Clark } 3019c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 3020c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 3021c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) 3022c28c82e9SRob Clark { 3023c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; 3024c28c82e9SRob Clark } 3025c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 3026c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 3027c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) 3028c28c82e9SRob Clark { 3029c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; 3030c28c82e9SRob Clark } 3031c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 3032c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 3033c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) 3034c28c82e9SRob Clark { 3035c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; 3036c28c82e9SRob Clark } 3037c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 3038c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 3039c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) 3040c28c82e9SRob Clark { 3041c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; 3042c28c82e9SRob Clark } 3043c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 3044c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 3045c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) 3046c28c82e9SRob Clark { 3047c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; 3048c28c82e9SRob Clark } 3049c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 3050c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 3051c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) 3052c28c82e9SRob Clark { 3053c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; 3054c28c82e9SRob Clark } 3055c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 3056c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 3057c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) 3058c28c82e9SRob Clark { 3059c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; 3060c28c82e9SRob Clark } 30612d756322SRob Clark 3062c28c82e9SRob Clark #define REG_A6XX_GRAS_SAMPLE_LOCATION_1 0x000080a6 3063c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f 3064c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 3065c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) 3066c28c82e9SRob Clark { 3067c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; 3068c28c82e9SRob Clark } 3069c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 3070c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 3071c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) 3072c28c82e9SRob Clark { 3073c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; 3074c28c82e9SRob Clark } 3075c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 3076c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 3077c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) 3078c28c82e9SRob Clark { 3079c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; 3080c28c82e9SRob Clark } 3081c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 3082c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 3083c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) 3084c28c82e9SRob Clark { 3085c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; 3086c28c82e9SRob Clark } 3087c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 3088c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 3089c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) 3090c28c82e9SRob Clark { 3091c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; 3092c28c82e9SRob Clark } 3093c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 3094c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 3095c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) 3096c28c82e9SRob Clark { 3097c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; 3098c28c82e9SRob Clark } 3099c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 3100c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 3101c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) 3102c28c82e9SRob Clark { 3103c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; 3104c28c82e9SRob Clark } 3105c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 3106c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 3107c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) 3108c28c82e9SRob Clark { 3109c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; 3110c28c82e9SRob Clark } 31112d756322SRob Clark 31122d756322SRob Clark #define REG_A6XX_GRAS_UNKNOWN_80AF 0x000080af 31132d756322SRob Clark 3114c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR(uint32_t i0) { return 0x000080b0 + 0x2*i0; } 3115c28c82e9SRob Clark 3116c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0) { return 0x000080b0 + 0x2*i0; } 3117c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x0000ffff 3118c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 3119c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 31202d756322SRob Clark { 3121c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; 31222d756322SRob Clark } 3123c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0xffff0000 3124c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 3125c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 31262d756322SRob Clark { 3127c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; 31282d756322SRob Clark } 31292d756322SRob Clark 3130c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR(uint32_t i0) { return 0x000080b1 + 0x2*i0; } 3131c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x0000ffff 3132c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 3133c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 31342d756322SRob Clark { 3135c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; 31362d756322SRob Clark } 3137c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0xffff0000 3138c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 3139c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 31402d756322SRob Clark { 3141c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; 31422d756322SRob Clark } 31432d756322SRob Clark 3144c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(uint32_t i0) { return 0x000080d0 + 0x2*i0; } 3145c28c82e9SRob Clark 3146c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0) { return 0x000080d0 + 0x2*i0; } 3147c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK 0x0000ffff 3148c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT 0 3149c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(uint32_t val) 31502d756322SRob Clark { 3151c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK; 31522d756322SRob Clark } 3153c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK 0xffff0000 3154c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT 16 3155c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(uint32_t val) 31562d756322SRob Clark { 3157c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK; 31582d756322SRob Clark } 31592d756322SRob Clark 3160c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(uint32_t i0) { return 0x000080d1 + 0x2*i0; } 3161c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK 0x0000ffff 3162c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT 0 3163c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X(uint32_t val) 31642d756322SRob Clark { 3165c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK; 31662d756322SRob Clark } 3167c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK 0xffff0000 3168c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT 16 3169c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y(uint32_t val) 31702d756322SRob Clark { 3171c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK; 31722d756322SRob Clark } 31732d756322SRob Clark 31742d756322SRob Clark #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL 0x000080f0 3175c28c82e9SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00003fff 31762d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 31772d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 31782d756322SRob Clark { 31792d756322SRob Clark return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 31802d756322SRob Clark } 3181c28c82e9SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x3fff0000 31822d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 31832d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 31842d756322SRob Clark { 31852d756322SRob Clark return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 31862d756322SRob Clark } 31872d756322SRob Clark 31882d756322SRob Clark #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR 0x000080f1 3189c28c82e9SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00003fff 31902d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 31912d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 31922d756322SRob Clark { 31932d756322SRob Clark return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 31942d756322SRob Clark } 3195c28c82e9SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x3fff0000 31962d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 31972d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 31982d756322SRob Clark { 31992d756322SRob Clark return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 32002d756322SRob Clark } 32012d756322SRob Clark 32022d756322SRob Clark #define REG_A6XX_GRAS_LRZ_CNTL 0x00008100 32032d756322SRob Clark #define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001 32042d756322SRob Clark #define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002 32052d756322SRob Clark #define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004 3206c28c82e9SRob Clark #define A6XX_GRAS_LRZ_CNTL_FC_ENABLE 0x00000008 3207c28c82e9SRob Clark #define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE 0x00000010 3208c28c82e9SRob Clark #define A6XX_GRAS_LRZ_CNTL_UNK5__MASK 0x000003e0 3209c28c82e9SRob Clark #define A6XX_GRAS_LRZ_CNTL_UNK5__SHIFT 5 3210c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_LRZ_CNTL_UNK5(uint32_t val) 3211c28c82e9SRob Clark { 3212c28c82e9SRob Clark return ((val) << A6XX_GRAS_LRZ_CNTL_UNK5__SHIFT) & A6XX_GRAS_LRZ_CNTL_UNK5__MASK; 3213c28c82e9SRob Clark } 32142d756322SRob Clark 3215a69c5ed2SRob Clark #define REG_A6XX_GRAS_UNKNOWN_8101 0x00008101 3216a69c5ed2SRob Clark 32172d756322SRob Clark #define REG_A6XX_GRAS_2D_BLIT_INFO 0x00008102 32182d756322SRob Clark #define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK 0x000000ff 32192d756322SRob Clark #define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT 0 3220c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(enum a6xx_format val) 32212d756322SRob Clark { 32222d756322SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK; 32232d756322SRob Clark } 32242d756322SRob Clark 32252d756322SRob Clark #define REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO 0x00008103 32262d756322SRob Clark 32272d756322SRob Clark #define REG_A6XX_GRAS_LRZ_BUFFER_BASE_HI 0x00008104 32282d756322SRob Clark 3229c28c82e9SRob Clark #define REG_A6XX_GRAS_LRZ_BUFFER_BASE 0x00008103 3230c28c82e9SRob Clark #define A6XX_GRAS_LRZ_BUFFER_BASE__MASK 0xffffffff 3231c28c82e9SRob Clark #define A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT 0 3232c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_LRZ_BUFFER_BASE(uint32_t val) 3233c28c82e9SRob Clark { 3234c28c82e9SRob Clark return ((val) << A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_BUFFER_BASE__MASK; 3235c28c82e9SRob Clark } 3236c28c82e9SRob Clark 32372d756322SRob Clark #define REG_A6XX_GRAS_LRZ_BUFFER_PITCH 0x00008105 3238c28c82e9SRob Clark #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK 0x000000ff 32392d756322SRob Clark #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT 0 32402d756322SRob Clark static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val) 32412d756322SRob Clark { 32422d756322SRob Clark return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK; 32432d756322SRob Clark } 3244c28c82e9SRob Clark #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffffc00 3245c28c82e9SRob Clark #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT 10 32462d756322SRob Clark static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 32472d756322SRob Clark { 3248c28c82e9SRob Clark return ((val >> 4) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK; 32492d756322SRob Clark } 32502d756322SRob Clark 32512d756322SRob Clark #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x00008106 32522d756322SRob Clark 32532d756322SRob Clark #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x00008107 32542d756322SRob Clark 3255c28c82e9SRob Clark #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE 0x00008106 3256c28c82e9SRob Clark #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK 0xffffffff 3257c28c82e9SRob Clark #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT 0 3258c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(uint32_t val) 3259c28c82e9SRob Clark { 3260c28c82e9SRob Clark return ((val) << A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK; 3261c28c82e9SRob Clark } 3262c28c82e9SRob Clark 3263c28c82e9SRob Clark #define REG_A6XX_GRAS_SAMPLE_CNTL 0x00008109 3264c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001 3265c28c82e9SRob Clark 3266c28c82e9SRob Clark #define REG_A6XX_GRAS_UNKNOWN_810A 0x0000810a 3267c28c82e9SRob Clark #define A6XX_GRAS_UNKNOWN_810A_UNK0__MASK 0x000007ff 3268c28c82e9SRob Clark #define A6XX_GRAS_UNKNOWN_810A_UNK0__SHIFT 0 3269c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK0(uint32_t val) 3270c28c82e9SRob Clark { 3271c28c82e9SRob Clark return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK0__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK0__MASK; 3272c28c82e9SRob Clark } 3273c28c82e9SRob Clark #define A6XX_GRAS_UNKNOWN_810A_UNK16__MASK 0x07ff0000 3274c28c82e9SRob Clark #define A6XX_GRAS_UNKNOWN_810A_UNK16__SHIFT 16 3275c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK16(uint32_t val) 3276c28c82e9SRob Clark { 3277c28c82e9SRob Clark return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK16__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK16__MASK; 3278c28c82e9SRob Clark } 3279c28c82e9SRob Clark #define A6XX_GRAS_UNKNOWN_810A_UNK28__MASK 0xf0000000 3280c28c82e9SRob Clark #define A6XX_GRAS_UNKNOWN_810A_UNK28__SHIFT 28 3281c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK28(uint32_t val) 3282c28c82e9SRob Clark { 3283c28c82e9SRob Clark return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK28__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK28__MASK; 3284c28c82e9SRob Clark } 3285a69c5ed2SRob Clark 3286a69c5ed2SRob Clark #define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110 3287a69c5ed2SRob Clark 32882d756322SRob Clark #define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400 3289c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK 0x00000007 3290c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT 0 3291c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val) 3292c28c82e9SRob Clark { 3293c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK; 3294c28c82e9SRob Clark } 3295c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_UNK3__MASK 0x00000078 3296c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_UNK3__SHIFT 3 3297c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK3(uint32_t val) 3298c28c82e9SRob Clark { 3299c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK3__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK3__MASK; 3300c28c82e9SRob Clark } 3301c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR 0x00000080 3302ccdf7e28SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00 3303ccdf7e28SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8 3304c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val) 3305ccdf7e28SRob Clark { 3306ccdf7e28SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK; 3307ccdf7e28SRob Clark } 3308ccdf7e28SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR 0x00010000 3309c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK 0x00060000 3310c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT 17 3311c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK17(uint32_t val) 3312c28c82e9SRob Clark { 3313c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK; 3314c28c82e9SRob Clark } 3315c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_D24S8 0x00080000 3316c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK 0x00f00000 3317c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT 20 3318c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_MASK(uint32_t val) 3319c28c82e9SRob Clark { 3320c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK; 3321c28c82e9SRob Clark } 3322c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK 0x1f000000 3323c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT 24 3324c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val) 3325c28c82e9SRob Clark { 3326c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK; 3327c28c82e9SRob Clark } 3328c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_UNK29__MASK 0x20000000 3329c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_UNK29__SHIFT 29 3330c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK29(uint32_t val) 3331c28c82e9SRob Clark { 3332c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK29__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK29__MASK; 3333c28c82e9SRob Clark } 33342d756322SRob Clark 33352d756322SRob Clark #define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401 33362d756322SRob Clark 33372d756322SRob Clark #define REG_A6XX_GRAS_2D_SRC_BR_X 0x00008402 33382d756322SRob Clark 33392d756322SRob Clark #define REG_A6XX_GRAS_2D_SRC_TL_Y 0x00008403 33402d756322SRob Clark 33412d756322SRob Clark #define REG_A6XX_GRAS_2D_SRC_BR_Y 0x00008404 33422d756322SRob Clark 33432d756322SRob Clark #define REG_A6XX_GRAS_2D_DST_TL 0x00008405 3344c28c82e9SRob Clark #define A6XX_GRAS_2D_DST_TL_X__MASK 0x00003fff 33452d756322SRob Clark #define A6XX_GRAS_2D_DST_TL_X__SHIFT 0 33462d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val) 33472d756322SRob Clark { 33482d756322SRob Clark return ((val) << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK; 33492d756322SRob Clark } 3350c28c82e9SRob Clark #define A6XX_GRAS_2D_DST_TL_Y__MASK 0x3fff0000 33512d756322SRob Clark #define A6XX_GRAS_2D_DST_TL_Y__SHIFT 16 33522d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val) 33532d756322SRob Clark { 33542d756322SRob Clark return ((val) << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK; 33552d756322SRob Clark } 33562d756322SRob Clark 33572d756322SRob Clark #define REG_A6XX_GRAS_2D_DST_BR 0x00008406 3358c28c82e9SRob Clark #define A6XX_GRAS_2D_DST_BR_X__MASK 0x00003fff 33592d756322SRob Clark #define A6XX_GRAS_2D_DST_BR_X__SHIFT 0 33602d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val) 33612d756322SRob Clark { 33622d756322SRob Clark return ((val) << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK; 33632d756322SRob Clark } 3364c28c82e9SRob Clark #define A6XX_GRAS_2D_DST_BR_Y__MASK 0x3fff0000 33652d756322SRob Clark #define A6XX_GRAS_2D_DST_BR_Y__SHIFT 16 33662d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val) 33672d756322SRob Clark { 33682d756322SRob Clark return ((val) << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK; 33692d756322SRob Clark } 33702d756322SRob Clark 3371c28c82e9SRob Clark #define REG_A6XX_GRAS_2D_UNKNOWN_8407 0x00008407 3372c28c82e9SRob Clark 3373c28c82e9SRob Clark #define REG_A6XX_GRAS_2D_UNKNOWN_8408 0x00008408 3374c28c82e9SRob Clark 3375c28c82e9SRob Clark #define REG_A6XX_GRAS_2D_UNKNOWN_8409 0x00008409 3376c28c82e9SRob Clark 3377c28c82e9SRob Clark #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_1 0x0000840a 3378c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK 0x00003fff 3379c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT 0 3380c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_X(uint32_t val) 33812d756322SRob Clark { 3382c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK; 33832d756322SRob Clark } 3384c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK 0x3fff0000 3385c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT 16 3386c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(uint32_t val) 33872d756322SRob Clark { 3388c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK; 33892d756322SRob Clark } 33902d756322SRob Clark 3391c28c82e9SRob Clark #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_2 0x0000840b 3392c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK 0x00003fff 3393c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT 0 3394c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_X(uint32_t val) 33952d756322SRob Clark { 3396c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK; 33972d756322SRob Clark } 3398c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK 0x3fff0000 3399c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT 16 3400c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val) 34012d756322SRob Clark { 3402c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK; 34032d756322SRob Clark } 34042d756322SRob Clark 34052d756322SRob Clark #define REG_A6XX_GRAS_UNKNOWN_8600 0x00008600 34062d756322SRob Clark 3407c28c82e9SRob Clark #define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601 3408c28c82e9SRob Clark 3409c28c82e9SRob Clark #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_0 0x00008610 3410c28c82e9SRob Clark 3411c28c82e9SRob Clark #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_1 0x00008611 3412c28c82e9SRob Clark 3413c28c82e9SRob Clark #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_2 0x00008612 3414c28c82e9SRob Clark 3415c28c82e9SRob Clark #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_3 0x00008613 3416c28c82e9SRob Clark 3417c28c82e9SRob Clark #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_0 0x00008614 3418c28c82e9SRob Clark 3419c28c82e9SRob Clark #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_1 0x00008615 3420c28c82e9SRob Clark 3421c28c82e9SRob Clark #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_2 0x00008616 3422c28c82e9SRob Clark 3423c28c82e9SRob Clark #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_3 0x00008617 3424c28c82e9SRob Clark 3425c28c82e9SRob Clark #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_0 0x00008618 3426c28c82e9SRob Clark 3427c28c82e9SRob Clark #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_1 0x00008619 3428c28c82e9SRob Clark 3429c28c82e9SRob Clark #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_2 0x0000861a 3430c28c82e9SRob Clark 3431c28c82e9SRob Clark #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_3 0x0000861b 3432c28c82e9SRob Clark 3433a69c5ed2SRob Clark #define REG_A6XX_RB_BIN_CONTROL 0x00008800 3434c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f 3435a69c5ed2SRob Clark #define A6XX_RB_BIN_CONTROL_BINW__SHIFT 0 3436a69c5ed2SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val) 3437a69c5ed2SRob Clark { 3438a69c5ed2SRob Clark return ((val >> 5) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK; 3439a69c5ed2SRob Clark } 3440c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL_BINH__MASK 0x00007f00 3441a69c5ed2SRob Clark #define A6XX_RB_BIN_CONTROL_BINH__SHIFT 8 3442a69c5ed2SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val) 3443a69c5ed2SRob Clark { 3444a69c5ed2SRob Clark return ((val >> 4) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK; 3445a69c5ed2SRob Clark } 3446a69c5ed2SRob Clark #define A6XX_RB_BIN_CONTROL_BINNING_PASS 0x00040000 3447c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL_UNK19__MASK 0x00080000 3448c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL_UNK19__SHIFT 19 3449c28c82e9SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL_UNK19(uint32_t val) 3450c28c82e9SRob Clark { 3451c28c82e9SRob Clark return ((val) << A6XX_RB_BIN_CONTROL_UNK19__SHIFT) & A6XX_RB_BIN_CONTROL_UNK19__MASK; 3452c28c82e9SRob Clark } 3453c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL_UNK20__MASK 0x00100000 3454c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL_UNK20__SHIFT 20 3455c28c82e9SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL_UNK20(uint32_t val) 3456c28c82e9SRob Clark { 3457c28c82e9SRob Clark return ((val) << A6XX_RB_BIN_CONTROL_UNK20__SHIFT) & A6XX_RB_BIN_CONTROL_UNK20__MASK; 3458c28c82e9SRob Clark } 3459a69c5ed2SRob Clark #define A6XX_RB_BIN_CONTROL_USE_VIZ 0x00200000 3460c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL_UNK22__MASK 0x07c00000 3461c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL_UNK22__SHIFT 22 3462c28c82e9SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL_UNK22(uint32_t val) 3463c28c82e9SRob Clark { 3464c28c82e9SRob Clark return ((val) << A6XX_RB_BIN_CONTROL_UNK22__SHIFT) & A6XX_RB_BIN_CONTROL_UNK22__MASK; 3465c28c82e9SRob Clark } 3466a69c5ed2SRob Clark 3467a69c5ed2SRob Clark #define REG_A6XX_RB_RENDER_CNTL 0x00008801 3468c28c82e9SRob Clark #define A6XX_RB_RENDER_CNTL_UNK3 0x00000008 3469a69c5ed2SRob Clark #define A6XX_RB_RENDER_CNTL_UNK4 0x00000010 3470c28c82e9SRob Clark #define A6XX_RB_RENDER_CNTL_UNK5__MASK 0x00000060 3471c28c82e9SRob Clark #define A6XX_RB_RENDER_CNTL_UNK5__SHIFT 5 3472c28c82e9SRob Clark static inline uint32_t A6XX_RB_RENDER_CNTL_UNK5(uint32_t val) 3473c28c82e9SRob Clark { 3474c28c82e9SRob Clark return ((val) << A6XX_RB_RENDER_CNTL_UNK5__SHIFT) & A6XX_RB_RENDER_CNTL_UNK5__MASK; 3475c28c82e9SRob Clark } 3476a69c5ed2SRob Clark #define A6XX_RB_RENDER_CNTL_BINNING 0x00000080 3477c28c82e9SRob Clark #define A6XX_RB_RENDER_CNTL_UNK8__MASK 0x00001f00 3478c28c82e9SRob Clark #define A6XX_RB_RENDER_CNTL_UNK8__SHIFT 8 3479c28c82e9SRob Clark static inline uint32_t A6XX_RB_RENDER_CNTL_UNK8(uint32_t val) 3480c28c82e9SRob Clark { 3481c28c82e9SRob Clark return ((val) << A6XX_RB_RENDER_CNTL_UNK8__SHIFT) & A6XX_RB_RENDER_CNTL_UNK8__MASK; 3482c28c82e9SRob Clark } 3483a69c5ed2SRob Clark #define A6XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000 3484a69c5ed2SRob Clark #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000 3485a69c5ed2SRob Clark #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16 3486a69c5ed2SRob Clark static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val) 3487a69c5ed2SRob Clark { 3488a69c5ed2SRob Clark return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK; 3489a69c5ed2SRob Clark } 3490a69c5ed2SRob Clark 34912d756322SRob Clark #define REG_A6XX_RB_RAS_MSAA_CNTL 0x00008802 34922d756322SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 34932d756322SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 34942d756322SRob Clark static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 34952d756322SRob Clark { 34962d756322SRob Clark return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK; 34972d756322SRob Clark } 3498c28c82e9SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK 0x00000004 3499c28c82e9SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT 2 3500c28c82e9SRob Clark static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK2(uint32_t val) 3501c28c82e9SRob Clark { 3502c28c82e9SRob Clark return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK; 3503c28c82e9SRob Clark } 3504c28c82e9SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK 0x00000008 3505c28c82e9SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT 3 3506c28c82e9SRob Clark static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK3(uint32_t val) 3507c28c82e9SRob Clark { 3508c28c82e9SRob Clark return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK; 3509c28c82e9SRob Clark } 35102d756322SRob Clark 35112d756322SRob Clark #define REG_A6XX_RB_DEST_MSAA_CNTL 0x00008803 35122d756322SRob Clark #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 35132d756322SRob Clark #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 35142d756322SRob Clark static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 35152d756322SRob Clark { 35162d756322SRob Clark return ((val) << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK; 35172d756322SRob Clark } 35182d756322SRob Clark #define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 35192d756322SRob Clark 3520c28c82e9SRob Clark #define REG_A6XX_RB_SAMPLE_CONFIG 0x00008804 3521c28c82e9SRob Clark #define A6XX_RB_SAMPLE_CONFIG_UNK0 0x00000001 3522c28c82e9SRob Clark #define A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002 35232d756322SRob Clark 3524c28c82e9SRob Clark #define REG_A6XX_RB_SAMPLE_LOCATION_0 0x00008805 3525c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f 3526c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 3527c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) 3528c28c82e9SRob Clark { 3529c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; 3530c28c82e9SRob Clark } 3531c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 3532c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 3533c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) 3534c28c82e9SRob Clark { 3535c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; 3536c28c82e9SRob Clark } 3537c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 3538c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 3539c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) 3540c28c82e9SRob Clark { 3541c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; 3542c28c82e9SRob Clark } 3543c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 3544c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 3545c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) 3546c28c82e9SRob Clark { 3547c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; 3548c28c82e9SRob Clark } 3549c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 3550c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 3551c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) 3552c28c82e9SRob Clark { 3553c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; 3554c28c82e9SRob Clark } 3555c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 3556c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 3557c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) 3558c28c82e9SRob Clark { 3559c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; 3560c28c82e9SRob Clark } 3561c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 3562c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 3563c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) 3564c28c82e9SRob Clark { 3565c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; 3566c28c82e9SRob Clark } 3567c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 3568c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 3569c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) 3570c28c82e9SRob Clark { 3571c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; 3572c28c82e9SRob Clark } 35732d756322SRob Clark 3574c28c82e9SRob Clark #define REG_A6XX_RB_SAMPLE_LOCATION_1 0x00008806 3575c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f 3576c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 3577c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) 3578c28c82e9SRob Clark { 3579c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; 3580c28c82e9SRob Clark } 3581c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 3582c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 3583c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) 3584c28c82e9SRob Clark { 3585c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; 3586c28c82e9SRob Clark } 3587c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 3588c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 3589c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) 3590c28c82e9SRob Clark { 3591c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; 3592c28c82e9SRob Clark } 3593c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 3594c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 3595c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) 3596c28c82e9SRob Clark { 3597c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; 3598c28c82e9SRob Clark } 3599c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 3600c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 3601c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) 3602c28c82e9SRob Clark { 3603c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; 3604c28c82e9SRob Clark } 3605c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 3606c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 3607c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) 3608c28c82e9SRob Clark { 3609c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; 3610c28c82e9SRob Clark } 3611c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 3612c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 3613c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) 3614c28c82e9SRob Clark { 3615c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; 3616c28c82e9SRob Clark } 3617c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 3618c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 3619c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) 3620c28c82e9SRob Clark { 3621c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; 3622c28c82e9SRob Clark } 36232d756322SRob Clark 36242d756322SRob Clark #define REG_A6XX_RB_RENDER_CONTROL0 0x00008809 3625c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL 0x00000001 3626c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID 0x00000002 3627c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE 0x00000004 3628c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_SIZE 0x00000008 3629c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_UNK4 0x00000010 3630c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP 0x00000020 3631c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK 0x000003c0 3632c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT 6 3633c28c82e9SRob Clark static inline uint32_t A6XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val) 3634c28c82e9SRob Clark { 3635c28c82e9SRob Clark return ((val) << A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK; 3636c28c82e9SRob Clark } 36372d756322SRob Clark #define A6XX_RB_RENDER_CONTROL0_UNK10 0x00000400 36382d756322SRob Clark 36392d756322SRob Clark #define REG_A6XX_RB_RENDER_CONTROL1 0x0000880a 36402d756322SRob Clark #define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001 3641c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL1_UNK1 0x00000002 3642c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL1_FACENESS 0x00000004 36432d756322SRob Clark #define A6XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000008 3644c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL1_UNK4 0x00000010 3645c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL1_UNK5 0x00000020 3646c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL1_SIZE 0x00000040 3647c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL1_UNK7 0x00000080 3648c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL1_UNK8 0x00000100 36492d756322SRob Clark 36502d756322SRob Clark #define REG_A6XX_RB_FS_OUTPUT_CNTL0 0x0000880b 3651c28c82e9SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001 36522d756322SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z 0x00000002 3653c28c82e9SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK 0x00000004 3654c28c82e9SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF 0x00000008 36552d756322SRob Clark 36562d756322SRob Clark #define REG_A6XX_RB_FS_OUTPUT_CNTL1 0x0000880c 36572d756322SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f 36582d756322SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT 0 36592d756322SRob Clark static inline uint32_t A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val) 36602d756322SRob Clark { 36612d756322SRob Clark return ((val) << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK; 36622d756322SRob Clark } 36632d756322SRob Clark 36642d756322SRob Clark #define REG_A6XX_RB_RENDER_COMPONENTS 0x0000880d 36652d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f 36662d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0 36672d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) 36682d756322SRob Clark { 36692d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK; 36702d756322SRob Clark } 36712d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0 36722d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4 36732d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) 36742d756322SRob Clark { 36752d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK; 36762d756322SRob Clark } 36772d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00 36782d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8 36792d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) 36802d756322SRob Clark { 36812d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK; 36822d756322SRob Clark } 36832d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000 36842d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12 36852d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) 36862d756322SRob Clark { 36872d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK; 36882d756322SRob Clark } 36892d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000 36902d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16 36912d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) 36922d756322SRob Clark { 36932d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK; 36942d756322SRob Clark } 36952d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000 36962d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20 36972d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) 36982d756322SRob Clark { 36992d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK; 37002d756322SRob Clark } 37012d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000 37022d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24 37032d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) 37042d756322SRob Clark { 37052d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK; 37062d756322SRob Clark } 37072d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000 37082d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28 37092d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) 37102d756322SRob Clark { 37112d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK; 37122d756322SRob Clark } 37132d756322SRob Clark 37142d756322SRob Clark #define REG_A6XX_RB_DITHER_CNTL 0x0000880e 37152d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK 0x00000003 37162d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT 0 37172d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val) 37182d756322SRob Clark { 37192d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK; 37202d756322SRob Clark } 37212d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK 0x0000000c 37222d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT 2 37232d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val) 37242d756322SRob Clark { 37252d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK; 37262d756322SRob Clark } 37272d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK 0x00000030 37282d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT 4 37292d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val) 37302d756322SRob Clark { 37312d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK; 37322d756322SRob Clark } 37332d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK 0x000000c0 37342d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT 6 37352d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val) 37362d756322SRob Clark { 37372d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK; 37382d756322SRob Clark } 37392d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK 0x00000300 37402d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT 8 37412d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val) 37422d756322SRob Clark { 37432d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK; 37442d756322SRob Clark } 37452d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK 0x00000c00 37462d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT 10 37472d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val) 37482d756322SRob Clark { 37492d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK; 37502d756322SRob Clark } 37512d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK 0x00001000 37522d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT 12 37532d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val) 37542d756322SRob Clark { 37552d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK; 37562d756322SRob Clark } 37572d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK 0x0000c000 37582d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT 14 37592d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val) 37602d756322SRob Clark { 37612d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK; 37622d756322SRob Clark } 37632d756322SRob Clark 37642d756322SRob Clark #define REG_A6XX_RB_SRGB_CNTL 0x0000880f 37652d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT0 0x00000001 37662d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT1 0x00000002 37672d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT2 0x00000004 37682d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT3 0x00000008 37692d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT4 0x00000010 37702d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT5 0x00000020 37712d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT6 0x00000040 37722d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT7 0x00000080 37732d756322SRob Clark 3774c28c82e9SRob Clark #define REG_A6XX_RB_SAMPLE_CNTL 0x00008810 3775c28c82e9SRob Clark #define A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001 3776a69c5ed2SRob Clark 3777a69c5ed2SRob Clark #define REG_A6XX_RB_UNKNOWN_8811 0x00008811 3778a69c5ed2SRob Clark 37792d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8818 0x00008818 37802d756322SRob Clark 37812d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8819 0x00008819 37822d756322SRob Clark 37832d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881A 0x0000881a 37842d756322SRob Clark 37852d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881B 0x0000881b 37862d756322SRob Clark 37872d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881C 0x0000881c 37882d756322SRob Clark 37892d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881D 0x0000881d 37902d756322SRob Clark 37912d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881E 0x0000881e 37922d756322SRob Clark 37932d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; } 37942d756322SRob Clark 37952d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; } 37962d756322SRob Clark #define A6XX_RB_MRT_CONTROL_BLEND 0x00000001 37972d756322SRob Clark #define A6XX_RB_MRT_CONTROL_BLEND2 0x00000002 37982d756322SRob Clark #define A6XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004 37992d756322SRob Clark #define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078 38002d756322SRob Clark #define A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3 38012d756322SRob Clark static inline uint32_t A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) 38022d756322SRob Clark { 38032d756322SRob Clark return ((val) << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK; 38042d756322SRob Clark } 38052d756322SRob Clark #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780 38062d756322SRob Clark #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7 38072d756322SRob Clark static inline uint32_t A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 38082d756322SRob Clark { 38092d756322SRob Clark return ((val) << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 38102d756322SRob Clark } 38112d756322SRob Clark 38122d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; } 38132d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 38142d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 38152d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 38162d756322SRob Clark { 38172d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 38182d756322SRob Clark } 38192d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 38202d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 38212d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 38222d756322SRob Clark { 38232d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 38242d756322SRob Clark } 38252d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 38262d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 38272d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 38282d756322SRob Clark { 38292d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 38302d756322SRob Clark } 38312d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 38322d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 38332d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 38342d756322SRob Clark { 38352d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 38362d756322SRob Clark } 38372d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 38382d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 38392d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 38402d756322SRob Clark { 38412d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 38422d756322SRob Clark } 38432d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 38442d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 38452d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 38462d756322SRob Clark { 38472d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 38482d756322SRob Clark } 38492d756322SRob Clark 38502d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; } 38512d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff 38522d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 3853c28c82e9SRob Clark static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val) 38542d756322SRob Clark { 38552d756322SRob Clark return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 38562d756322SRob Clark } 38572d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300 38582d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8 38592d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val) 38602d756322SRob Clark { 38612d756322SRob Clark return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 38622d756322SRob Clark } 3863c28c82e9SRob Clark #define A6XX_RB_MRT_BUF_INFO_UNK10__MASK 0x00000400 3864c28c82e9SRob Clark #define A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT 10 3865c28c82e9SRob Clark static inline uint32_t A6XX_RB_MRT_BUF_INFO_UNK10(uint32_t val) 3866c28c82e9SRob Clark { 3867c28c82e9SRob Clark return ((val) << A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT) & A6XX_RB_MRT_BUF_INFO_UNK10__MASK; 3868c28c82e9SRob Clark } 38692d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000 38702d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13 38712d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 38722d756322SRob Clark { 38732d756322SRob Clark return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 38742d756322SRob Clark } 38752d756322SRob Clark 38762d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; } 3877c28c82e9SRob Clark #define A6XX_RB_MRT_PITCH__MASK 0x0000ffff 38782d756322SRob Clark #define A6XX_RB_MRT_PITCH__SHIFT 0 38792d756322SRob Clark static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val) 38802d756322SRob Clark { 38812d756322SRob Clark return ((val >> 6) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK; 38822d756322SRob Clark } 38832d756322SRob Clark 38842d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; } 3885c28c82e9SRob Clark #define A6XX_RB_MRT_ARRAY_PITCH__MASK 0x1fffffff 38862d756322SRob Clark #define A6XX_RB_MRT_ARRAY_PITCH__SHIFT 0 38872d756322SRob Clark static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val) 38882d756322SRob Clark { 38892d756322SRob Clark return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK; 38902d756322SRob Clark } 38912d756322SRob Clark 38922d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x00008825 + 0x8*i0; } 38932d756322SRob Clark 38942d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x00008826 + 0x8*i0; } 38952d756322SRob Clark 3896c28c82e9SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; } 3897c28c82e9SRob Clark #define A6XX_RB_MRT_BASE__MASK 0xffffffff 3898c28c82e9SRob Clark #define A6XX_RB_MRT_BASE__SHIFT 0 3899c28c82e9SRob Clark static inline uint32_t A6XX_RB_MRT_BASE(uint32_t val) 3900c28c82e9SRob Clark { 3901c28c82e9SRob Clark return ((val) << A6XX_RB_MRT_BASE__SHIFT) & A6XX_RB_MRT_BASE__MASK; 3902c28c82e9SRob Clark } 3903c28c82e9SRob Clark 39042d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; } 3905c28c82e9SRob Clark #define A6XX_RB_MRT_BASE_GMEM__MASK 0xfffff000 3906c28c82e9SRob Clark #define A6XX_RB_MRT_BASE_GMEM__SHIFT 12 3907c28c82e9SRob Clark static inline uint32_t A6XX_RB_MRT_BASE_GMEM(uint32_t val) 3908c28c82e9SRob Clark { 3909c28c82e9SRob Clark return ((val >> 12) << A6XX_RB_MRT_BASE_GMEM__SHIFT) & A6XX_RB_MRT_BASE_GMEM__MASK; 3910c28c82e9SRob Clark } 39112d756322SRob Clark 39122d756322SRob Clark #define REG_A6XX_RB_BLEND_RED_F32 0x00008860 39132d756322SRob Clark #define A6XX_RB_BLEND_RED_F32__MASK 0xffffffff 39142d756322SRob Clark #define A6XX_RB_BLEND_RED_F32__SHIFT 0 39152d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_RED_F32(float val) 39162d756322SRob Clark { 39172d756322SRob Clark return ((fui(val)) << A6XX_RB_BLEND_RED_F32__SHIFT) & A6XX_RB_BLEND_RED_F32__MASK; 39182d756322SRob Clark } 39192d756322SRob Clark 39202d756322SRob Clark #define REG_A6XX_RB_BLEND_GREEN_F32 0x00008861 39212d756322SRob Clark #define A6XX_RB_BLEND_GREEN_F32__MASK 0xffffffff 39222d756322SRob Clark #define A6XX_RB_BLEND_GREEN_F32__SHIFT 0 39232d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_GREEN_F32(float val) 39242d756322SRob Clark { 39252d756322SRob Clark return ((fui(val)) << A6XX_RB_BLEND_GREEN_F32__SHIFT) & A6XX_RB_BLEND_GREEN_F32__MASK; 39262d756322SRob Clark } 39272d756322SRob Clark 39282d756322SRob Clark #define REG_A6XX_RB_BLEND_BLUE_F32 0x00008862 39292d756322SRob Clark #define A6XX_RB_BLEND_BLUE_F32__MASK 0xffffffff 39302d756322SRob Clark #define A6XX_RB_BLEND_BLUE_F32__SHIFT 0 39312d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_BLUE_F32(float val) 39322d756322SRob Clark { 39332d756322SRob Clark return ((fui(val)) << A6XX_RB_BLEND_BLUE_F32__SHIFT) & A6XX_RB_BLEND_BLUE_F32__MASK; 39342d756322SRob Clark } 39352d756322SRob Clark 39362d756322SRob Clark #define REG_A6XX_RB_BLEND_ALPHA_F32 0x00008863 39372d756322SRob Clark #define A6XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff 39382d756322SRob Clark #define A6XX_RB_BLEND_ALPHA_F32__SHIFT 0 39392d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_ALPHA_F32(float val) 39402d756322SRob Clark { 39412d756322SRob Clark return ((fui(val)) << A6XX_RB_BLEND_ALPHA_F32__SHIFT) & A6XX_RB_BLEND_ALPHA_F32__MASK; 39422d756322SRob Clark } 39432d756322SRob Clark 39442d756322SRob Clark #define REG_A6XX_RB_ALPHA_CONTROL 0x00008864 39452d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff 39462d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 39472d756322SRob Clark static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) 39482d756322SRob Clark { 39492d756322SRob Clark return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; 39502d756322SRob Clark } 39512d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 39522d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 39532d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 39542d756322SRob Clark static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 39552d756322SRob Clark { 39562d756322SRob Clark return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; 39572d756322SRob Clark } 39582d756322SRob Clark 39592d756322SRob Clark #define REG_A6XX_RB_BLEND_CNTL 0x00008865 39602d756322SRob Clark #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff 39612d756322SRob Clark #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 39622d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val) 39632d756322SRob Clark { 39642d756322SRob Clark return ((val) << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK; 39652d756322SRob Clark } 39662d756322SRob Clark #define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100 3967c28c82e9SRob Clark #define A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200 3968ccdf7e28SRob Clark #define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 3969c28c82e9SRob Clark #define A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE 0x00000800 39702d756322SRob Clark #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000 39712d756322SRob Clark #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16 39722d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val) 39732d756322SRob Clark { 39742d756322SRob Clark return ((val) << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK; 39752d756322SRob Clark } 39762d756322SRob Clark 3977a69c5ed2SRob Clark #define REG_A6XX_RB_DEPTH_PLANE_CNTL 0x00008870 3978c28c82e9SRob Clark #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003 3979c28c82e9SRob Clark #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0 3980c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val) 3981c28c82e9SRob Clark { 3982c28c82e9SRob Clark return ((val) << A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK; 3983c28c82e9SRob Clark } 3984a69c5ed2SRob Clark 39852d756322SRob Clark #define REG_A6XX_RB_DEPTH_CNTL 0x00008871 39862d756322SRob Clark #define A6XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001 39872d756322SRob Clark #define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002 39882d756322SRob Clark #define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c 39892d756322SRob Clark #define A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2 39902d756322SRob Clark static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) 39912d756322SRob Clark { 39922d756322SRob Clark return ((val) << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK; 39932d756322SRob Clark } 3994c28c82e9SRob Clark #define A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE 0x00000020 39952d756322SRob Clark #define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040 3996c28c82e9SRob Clark #define A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE 0x00000080 39972d756322SRob Clark 39982d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_INFO 0x00008872 39992d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 40002d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 40012d756322SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) 40022d756322SRob Clark { 40032d756322SRob Clark return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; 40042d756322SRob Clark } 4005c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000018 4006c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT 3 4007c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val) 4008c28c82e9SRob Clark { 4009c28c82e9SRob Clark return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK; 4010c28c82e9SRob Clark } 40112d756322SRob Clark 40122d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_PITCH 0x00008873 4013c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_PITCH__MASK 0x00003fff 40142d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0 40152d756322SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) 40162d756322SRob Clark { 40172d756322SRob Clark return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK; 40182d756322SRob Clark } 40192d756322SRob Clark 40202d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x00008874 4021c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0x0fffffff 40222d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0 40232d756322SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) 40242d756322SRob Clark { 40252d756322SRob Clark return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; 40262d756322SRob Clark } 40272d756322SRob Clark 40282d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_BASE_LO 0x00008875 40292d756322SRob Clark 40302d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_BASE_HI 0x00008876 40312d756322SRob Clark 4032c28c82e9SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_BASE 0x00008875 4033c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_BASE__MASK 0xffffffff 4034c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_BASE__SHIFT 0 4035c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE(uint32_t val) 4036c28c82e9SRob Clark { 4037c28c82e9SRob Clark return ((val) << A6XX_RB_DEPTH_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE__MASK; 4038c28c82e9SRob Clark } 4039c28c82e9SRob Clark 40402d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM 0x00008877 4041c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK 0xfffff000 4042c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT 12 4043c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE_GMEM(uint32_t val) 4044c28c82e9SRob Clark { 4045c28c82e9SRob Clark return ((val >> 12) << A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK; 4046c28c82e9SRob Clark } 40472d756322SRob Clark 4048c28c82e9SRob Clark #define REG_A6XX_RB_Z_BOUNDS_MIN 0x00008878 4049c28c82e9SRob Clark #define A6XX_RB_Z_BOUNDS_MIN__MASK 0xffffffff 4050c28c82e9SRob Clark #define A6XX_RB_Z_BOUNDS_MIN__SHIFT 0 4051c28c82e9SRob Clark static inline uint32_t A6XX_RB_Z_BOUNDS_MIN(float val) 4052c28c82e9SRob Clark { 4053c28c82e9SRob Clark return ((fui(val)) << A6XX_RB_Z_BOUNDS_MIN__SHIFT) & A6XX_RB_Z_BOUNDS_MIN__MASK; 4054c28c82e9SRob Clark } 40552d756322SRob Clark 4056c28c82e9SRob Clark #define REG_A6XX_RB_Z_BOUNDS_MAX 0x00008879 4057c28c82e9SRob Clark #define A6XX_RB_Z_BOUNDS_MAX__MASK 0xffffffff 4058c28c82e9SRob Clark #define A6XX_RB_Z_BOUNDS_MAX__SHIFT 0 4059c28c82e9SRob Clark static inline uint32_t A6XX_RB_Z_BOUNDS_MAX(float val) 4060c28c82e9SRob Clark { 4061c28c82e9SRob Clark return ((fui(val)) << A6XX_RB_Z_BOUNDS_MAX__SHIFT) & A6XX_RB_Z_BOUNDS_MAX__MASK; 4062c28c82e9SRob Clark } 40632d756322SRob Clark 40642d756322SRob Clark #define REG_A6XX_RB_STENCIL_CONTROL 0x00008880 40652d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 40662d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 40672d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 40682d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 40692d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 40702d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 40712d756322SRob Clark { 40722d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC__MASK; 40732d756322SRob Clark } 40742d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 40752d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 40762d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 40772d756322SRob Clark { 40782d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL__MASK; 40792d756322SRob Clark } 40802d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 40812d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 40822d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 40832d756322SRob Clark { 40842d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK; 40852d756322SRob Clark } 40862d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 40872d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 40882d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 40892d756322SRob Clark { 40902d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 40912d756322SRob Clark } 40922d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 40932d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 40942d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 40952d756322SRob Clark { 40962d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 40972d756322SRob Clark } 40982d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 40992d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 41002d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 41012d756322SRob Clark { 41022d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 41032d756322SRob Clark } 41042d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 41052d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 41062d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 41072d756322SRob Clark { 41082d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 41092d756322SRob Clark } 41102d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 41112d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 41122d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 41132d756322SRob Clark { 41142d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 41152d756322SRob Clark } 41162d756322SRob Clark 41172d756322SRob Clark #define REG_A6XX_RB_STENCIL_INFO 0x00008881 41182d756322SRob Clark #define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 4119c28c82e9SRob Clark #define A6XX_RB_STENCIL_INFO_UNK1 0x00000002 41202d756322SRob Clark 41212d756322SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_PITCH 0x00008882 4122c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_PITCH__MASK 0x00000fff 41232d756322SRob Clark #define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT 0 41242d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val) 41252d756322SRob Clark { 41262d756322SRob Clark return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK; 41272d756322SRob Clark } 41282d756322SRob Clark 41292d756322SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH 0x00008883 4130c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK 0x00ffffff 41312d756322SRob Clark #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT 0 41322d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val) 41332d756322SRob Clark { 41342d756322SRob Clark return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK; 41352d756322SRob Clark } 41362d756322SRob Clark 41372d756322SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_BASE_LO 0x00008884 41382d756322SRob Clark 41392d756322SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_BASE_HI 0x00008885 41402d756322SRob Clark 4141c28c82e9SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_BASE 0x00008884 4142c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_BASE__MASK 0xffffffff 4143c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_BASE__SHIFT 0 4144c28c82e9SRob Clark static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE(uint32_t val) 4145c28c82e9SRob Clark { 4146c28c82e9SRob Clark return ((val) << A6XX_RB_STENCIL_BUFFER_BASE__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE__MASK; 4147c28c82e9SRob Clark } 4148c28c82e9SRob Clark 41492d756322SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM 0x00008886 4150c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK 0xfffff000 4151c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT 12 4152c28c82e9SRob Clark static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE_GMEM(uint32_t val) 4153c28c82e9SRob Clark { 4154c28c82e9SRob Clark return ((val >> 12) << A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK; 4155c28c82e9SRob Clark } 41562d756322SRob Clark 41572d756322SRob Clark #define REG_A6XX_RB_STENCILREF 0x00008887 41582d756322SRob Clark #define A6XX_RB_STENCILREF_REF__MASK 0x000000ff 41592d756322SRob Clark #define A6XX_RB_STENCILREF_REF__SHIFT 0 41602d756322SRob Clark static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val) 41612d756322SRob Clark { 41622d756322SRob Clark return ((val) << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK; 41632d756322SRob Clark } 4164a69c5ed2SRob Clark #define A6XX_RB_STENCILREF_BFREF__MASK 0x0000ff00 4165a69c5ed2SRob Clark #define A6XX_RB_STENCILREF_BFREF__SHIFT 8 4166a69c5ed2SRob Clark static inline uint32_t A6XX_RB_STENCILREF_BFREF(uint32_t val) 4167a69c5ed2SRob Clark { 4168a69c5ed2SRob Clark return ((val) << A6XX_RB_STENCILREF_BFREF__SHIFT) & A6XX_RB_STENCILREF_BFREF__MASK; 4169a69c5ed2SRob Clark } 41702d756322SRob Clark 41712d756322SRob Clark #define REG_A6XX_RB_STENCILMASK 0x00008888 41722d756322SRob Clark #define A6XX_RB_STENCILMASK_MASK__MASK 0x000000ff 41732d756322SRob Clark #define A6XX_RB_STENCILMASK_MASK__SHIFT 0 41742d756322SRob Clark static inline uint32_t A6XX_RB_STENCILMASK_MASK(uint32_t val) 41752d756322SRob Clark { 41762d756322SRob Clark return ((val) << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK; 41772d756322SRob Clark } 4178a69c5ed2SRob Clark #define A6XX_RB_STENCILMASK_BFMASK__MASK 0x0000ff00 4179a69c5ed2SRob Clark #define A6XX_RB_STENCILMASK_BFMASK__SHIFT 8 4180a69c5ed2SRob Clark static inline uint32_t A6XX_RB_STENCILMASK_BFMASK(uint32_t val) 4181a69c5ed2SRob Clark { 4182a69c5ed2SRob Clark return ((val) << A6XX_RB_STENCILMASK_BFMASK__SHIFT) & A6XX_RB_STENCILMASK_BFMASK__MASK; 4183a69c5ed2SRob Clark } 41842d756322SRob Clark 41852d756322SRob Clark #define REG_A6XX_RB_STENCILWRMASK 0x00008889 41862d756322SRob Clark #define A6XX_RB_STENCILWRMASK_WRMASK__MASK 0x000000ff 41872d756322SRob Clark #define A6XX_RB_STENCILWRMASK_WRMASK__SHIFT 0 41882d756322SRob Clark static inline uint32_t A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val) 41892d756322SRob Clark { 41902d756322SRob Clark return ((val) << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK; 41912d756322SRob Clark } 4192a69c5ed2SRob Clark #define A6XX_RB_STENCILWRMASK_BFWRMASK__MASK 0x0000ff00 4193a69c5ed2SRob Clark #define A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT 8 4194a69c5ed2SRob Clark static inline uint32_t A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val) 4195a69c5ed2SRob Clark { 4196a69c5ed2SRob Clark return ((val) << A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_BFWRMASK__MASK; 4197a69c5ed2SRob Clark } 41982d756322SRob Clark 41992d756322SRob Clark #define REG_A6XX_RB_WINDOW_OFFSET 0x00008890 4200c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET_X__MASK 0x00003fff 42012d756322SRob Clark #define A6XX_RB_WINDOW_OFFSET_X__SHIFT 0 42022d756322SRob Clark static inline uint32_t A6XX_RB_WINDOW_OFFSET_X(uint32_t val) 42032d756322SRob Clark { 42042d756322SRob Clark return ((val) << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK; 42052d756322SRob Clark } 4206c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET_Y__MASK 0x3fff0000 42072d756322SRob Clark #define A6XX_RB_WINDOW_OFFSET_Y__SHIFT 16 42082d756322SRob Clark static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val) 42092d756322SRob Clark { 42102d756322SRob Clark return ((val) << A6XX_RB_WINDOW_OFFSET_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET_Y__MASK; 42112d756322SRob Clark } 42122d756322SRob Clark 42132d756322SRob Clark #define REG_A6XX_RB_SAMPLE_COUNT_CONTROL 0x00008891 4214c28c82e9SRob Clark #define A6XX_RB_SAMPLE_COUNT_CONTROL_UNK0 0x00000001 42152d756322SRob Clark #define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 42162d756322SRob Clark 4217ccdf7e28SRob Clark #define REG_A6XX_RB_LRZ_CNTL 0x00008898 4218ccdf7e28SRob Clark #define A6XX_RB_LRZ_CNTL_ENABLE 0x00000001 4219ccdf7e28SRob Clark 4220c28c82e9SRob Clark #define REG_A6XX_RB_Z_CLAMP_MIN 0x000088c0 4221c28c82e9SRob Clark #define A6XX_RB_Z_CLAMP_MIN__MASK 0xffffffff 4222c28c82e9SRob Clark #define A6XX_RB_Z_CLAMP_MIN__SHIFT 0 4223c28c82e9SRob Clark static inline uint32_t A6XX_RB_Z_CLAMP_MIN(float val) 4224c28c82e9SRob Clark { 4225c28c82e9SRob Clark return ((fui(val)) << A6XX_RB_Z_CLAMP_MIN__SHIFT) & A6XX_RB_Z_CLAMP_MIN__MASK; 4226c28c82e9SRob Clark } 4227c28c82e9SRob Clark 4228c28c82e9SRob Clark #define REG_A6XX_RB_Z_CLAMP_MAX 0x000088c1 4229c28c82e9SRob Clark #define A6XX_RB_Z_CLAMP_MAX__MASK 0xffffffff 4230c28c82e9SRob Clark #define A6XX_RB_Z_CLAMP_MAX__SHIFT 0 4231c28c82e9SRob Clark static inline uint32_t A6XX_RB_Z_CLAMP_MAX(float val) 4232c28c82e9SRob Clark { 4233c28c82e9SRob Clark return ((fui(val)) << A6XX_RB_Z_CLAMP_MAX__SHIFT) & A6XX_RB_Z_CLAMP_MAX__MASK; 4234c28c82e9SRob Clark } 4235c28c82e9SRob Clark 42362d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_88D0 0x000088d0 4237c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_88D0_UNK0__MASK 0x00001fff 4238c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT 0 4239c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK0(uint32_t val) 4240c28c82e9SRob Clark { 4241c28c82e9SRob Clark return ((val) << A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK0__MASK; 4242c28c82e9SRob Clark } 4243c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_88D0_UNK16__MASK 0x07ff0000 4244c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT 16 4245c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK16(uint32_t val) 4246c28c82e9SRob Clark { 4247c28c82e9SRob Clark return ((val) << A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK16__MASK; 4248c28c82e9SRob Clark } 42492d756322SRob Clark 42502d756322SRob Clark #define REG_A6XX_RB_BLIT_SCISSOR_TL 0x000088d1 4251c28c82e9SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_X__MASK 0x00003fff 42522d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT 0 42532d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val) 42542d756322SRob Clark { 42552d756322SRob Clark return ((val) << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK; 42562d756322SRob Clark } 4257c28c82e9SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK 0x3fff0000 42582d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT 16 42592d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val) 42602d756322SRob Clark { 42612d756322SRob Clark return ((val) << A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_Y__MASK; 42622d756322SRob Clark } 42632d756322SRob Clark 42642d756322SRob Clark #define REG_A6XX_RB_BLIT_SCISSOR_BR 0x000088d2 4265c28c82e9SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_X__MASK 0x00003fff 42662d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT 0 42672d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val) 42682d756322SRob Clark { 42692d756322SRob Clark return ((val) << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK; 42702d756322SRob Clark } 4271c28c82e9SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK 0x3fff0000 42722d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT 16 42732d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val) 42742d756322SRob Clark { 42752d756322SRob Clark return ((val) << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK; 42762d756322SRob Clark } 42772d756322SRob Clark 4278c28c82e9SRob Clark #define REG_A6XX_RB_BIN_CONTROL2 0x000088d3 4279c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL2_BINW__MASK 0x0000003f 4280c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL2_BINW__SHIFT 0 4281c28c82e9SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val) 4282c28c82e9SRob Clark { 4283c28c82e9SRob Clark return ((val >> 5) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK; 4284c28c82e9SRob Clark } 4285c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL2_BINH__MASK 0x00007f00 4286c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL2_BINH__SHIFT 8 4287c28c82e9SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val) 4288c28c82e9SRob Clark { 4289c28c82e9SRob Clark return ((val >> 4) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK; 4290c28c82e9SRob Clark } 4291c28c82e9SRob Clark 4292c28c82e9SRob Clark #define REG_A6XX_RB_WINDOW_OFFSET2 0x000088d4 4293c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET2_X__MASK 0x00003fff 4294c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET2_X__SHIFT 0 4295c28c82e9SRob Clark static inline uint32_t A6XX_RB_WINDOW_OFFSET2_X(uint32_t val) 4296c28c82e9SRob Clark { 4297c28c82e9SRob Clark return ((val) << A6XX_RB_WINDOW_OFFSET2_X__SHIFT) & A6XX_RB_WINDOW_OFFSET2_X__MASK; 4298c28c82e9SRob Clark } 4299c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET2_Y__MASK 0x3fff0000 4300c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET2_Y__SHIFT 16 4301c28c82e9SRob Clark static inline uint32_t A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val) 4302c28c82e9SRob Clark { 4303c28c82e9SRob Clark return ((val) << A6XX_RB_WINDOW_OFFSET2_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET2_Y__MASK; 4304c28c82e9SRob Clark } 4305c28c82e9SRob Clark 4306ccdf7e28SRob Clark #define REG_A6XX_RB_MSAA_CNTL 0x000088d5 4307ccdf7e28SRob Clark #define A6XX_RB_MSAA_CNTL_SAMPLES__MASK 0x00000018 4308ccdf7e28SRob Clark #define A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT 3 4309ccdf7e28SRob Clark static inline uint32_t A6XX_RB_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 4310ccdf7e28SRob Clark { 4311ccdf7e28SRob Clark return ((val) << A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_MSAA_CNTL_SAMPLES__MASK; 4312ccdf7e28SRob Clark } 4313ccdf7e28SRob Clark 43142d756322SRob Clark #define REG_A6XX_RB_BLIT_BASE_GMEM 0x000088d6 4315c28c82e9SRob Clark #define A6XX_RB_BLIT_BASE_GMEM__MASK 0xfffff000 4316c28c82e9SRob Clark #define A6XX_RB_BLIT_BASE_GMEM__SHIFT 12 4317c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_BASE_GMEM(uint32_t val) 4318c28c82e9SRob Clark { 4319c28c82e9SRob Clark return ((val >> 12) << A6XX_RB_BLIT_BASE_GMEM__SHIFT) & A6XX_RB_BLIT_BASE_GMEM__MASK; 4320c28c82e9SRob Clark } 43212d756322SRob Clark 43222d756322SRob Clark #define REG_A6XX_RB_BLIT_DST_INFO 0x000088d7 43232d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK 0x00000003 43242d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT 0 43252d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) 43262d756322SRob Clark { 43272d756322SRob Clark return ((val) << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK; 43282d756322SRob Clark } 43292d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_FLAGS 0x00000004 4330ccdf7e28SRob Clark #define A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK 0x00000018 4331ccdf7e28SRob Clark #define A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT 3 4332ccdf7e28SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) 4333ccdf7e28SRob Clark { 4334ccdf7e28SRob Clark return ((val) << A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK; 4335ccdf7e28SRob Clark } 43362d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK 0x00000060 43372d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT 5 43382d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) 43392d756322SRob Clark { 43402d756322SRob Clark return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK; 43412d756322SRob Clark } 4342c28c82e9SRob Clark #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK 0x00007f80 4343c28c82e9SRob Clark #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT 7 4344c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_format val) 4345c28c82e9SRob Clark { 4346c28c82e9SRob Clark return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK; 4347c28c82e9SRob Clark } 4348c28c82e9SRob Clark #define A6XX_RB_BLIT_DST_INFO_UNK15 0x00008000 4349c28c82e9SRob Clark 4350c28c82e9SRob Clark #define REG_A6XX_RB_BLIT_DST 0x000088d8 4351c28c82e9SRob Clark #define A6XX_RB_BLIT_DST__MASK 0xffffffff 4352c28c82e9SRob Clark #define A6XX_RB_BLIT_DST__SHIFT 0 4353c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_DST(uint32_t val) 4354c28c82e9SRob Clark { 4355c28c82e9SRob Clark return ((val) << A6XX_RB_BLIT_DST__SHIFT) & A6XX_RB_BLIT_DST__MASK; 4356c28c82e9SRob Clark } 43572d756322SRob Clark 43582d756322SRob Clark #define REG_A6XX_RB_BLIT_DST_LO 0x000088d8 43592d756322SRob Clark 43602d756322SRob Clark #define REG_A6XX_RB_BLIT_DST_HI 0x000088d9 43612d756322SRob Clark 43622d756322SRob Clark #define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da 4363c28c82e9SRob Clark #define A6XX_RB_BLIT_DST_PITCH__MASK 0x0000ffff 43642d756322SRob Clark #define A6XX_RB_BLIT_DST_PITCH__SHIFT 0 43652d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val) 43662d756322SRob Clark { 43672d756322SRob Clark return ((val >> 6) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK; 43682d756322SRob Clark } 43692d756322SRob Clark 43702d756322SRob Clark #define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH 0x000088db 4371c28c82e9SRob Clark #define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0x1fffffff 43722d756322SRob Clark #define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0 43732d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) 43742d756322SRob Clark { 43752d756322SRob Clark return ((val >> 6) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK; 43762d756322SRob Clark } 43772d756322SRob Clark 4378c28c82e9SRob Clark #define REG_A6XX_RB_BLIT_FLAG_DST 0x000088dc 4379c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST__MASK 0xffffffff 4380c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST__SHIFT 0 4381c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_FLAG_DST(uint32_t val) 4382c28c82e9SRob Clark { 4383c28c82e9SRob Clark return ((val) << A6XX_RB_BLIT_FLAG_DST__SHIFT) & A6XX_RB_BLIT_FLAG_DST__MASK; 4384c28c82e9SRob Clark } 4385c28c82e9SRob Clark 43862d756322SRob Clark #define REG_A6XX_RB_BLIT_FLAG_DST_LO 0x000088dc 43872d756322SRob Clark 43882d756322SRob Clark #define REG_A6XX_RB_BLIT_FLAG_DST_HI 0x000088dd 43892d756322SRob Clark 4390c28c82e9SRob Clark #define REG_A6XX_RB_BLIT_FLAG_DST_PITCH 0x000088de 4391c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK 0x000007ff 4392c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT 0 4393c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val) 4394c28c82e9SRob Clark { 4395c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK; 4396c28c82e9SRob Clark } 4397c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK 0x0ffff800 4398c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT 11 4399c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val) 4400c28c82e9SRob Clark { 4401c28c82e9SRob Clark return ((val >> 7) << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK; 4402c28c82e9SRob Clark } 4403c28c82e9SRob Clark 44042d756322SRob Clark #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 0x000088df 44052d756322SRob Clark 44062d756322SRob Clark #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1 0x000088e0 44072d756322SRob Clark 44082d756322SRob Clark #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2 0x000088e1 44092d756322SRob Clark 44102d756322SRob Clark #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3 0x000088e2 44112d756322SRob Clark 44122d756322SRob Clark #define REG_A6XX_RB_BLIT_INFO 0x000088e3 44132d756322SRob Clark #define A6XX_RB_BLIT_INFO_UNK0 0x00000001 4414a69c5ed2SRob Clark #define A6XX_RB_BLIT_INFO_GMEM 0x00000002 44152d756322SRob Clark #define A6XX_RB_BLIT_INFO_INTEGER 0x00000004 4416a69c5ed2SRob Clark #define A6XX_RB_BLIT_INFO_DEPTH 0x00000008 4417a69c5ed2SRob Clark #define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK 0x000000f0 4418a69c5ed2SRob Clark #define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT 4 4419a69c5ed2SRob Clark static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val) 44202d756322SRob Clark { 4421a69c5ed2SRob Clark return ((val) << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK; 44222d756322SRob Clark } 4423c28c82e9SRob Clark #define A6XX_RB_BLIT_INFO_UNK8__MASK 0x00000300 4424c28c82e9SRob Clark #define A6XX_RB_BLIT_INFO_UNK8__SHIFT 8 4425c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_INFO_UNK8(uint32_t val) 4426c28c82e9SRob Clark { 4427c28c82e9SRob Clark return ((val) << A6XX_RB_BLIT_INFO_UNK8__SHIFT) & A6XX_RB_BLIT_INFO_UNK8__MASK; 4428c28c82e9SRob Clark } 4429c28c82e9SRob Clark #define A6XX_RB_BLIT_INFO_UNK12__MASK 0x0000f000 4430c28c82e9SRob Clark #define A6XX_RB_BLIT_INFO_UNK12__SHIFT 12 4431c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_INFO_UNK12(uint32_t val) 4432c28c82e9SRob Clark { 4433c28c82e9SRob Clark return ((val) << A6XX_RB_BLIT_INFO_UNK12__SHIFT) & A6XX_RB_BLIT_INFO_UNK12__MASK; 4434c28c82e9SRob Clark } 44352d756322SRob Clark 44362d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_88F0 0x000088f0 44372d756322SRob Clark 4438c28c82e9SRob Clark #define REG_A6XX_RB_UNK_FLAG_BUFFER_BASE 0x000088f1 4439c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK 0xffffffff 4440c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT 0 4441c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_BASE(uint32_t val) 4442c28c82e9SRob Clark { 4443c28c82e9SRob Clark return ((val) << A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK; 4444c28c82e9SRob Clark } 4445c28c82e9SRob Clark 4446c28c82e9SRob Clark #define REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH 0x000088f3 4447c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff 4448c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 4449c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(uint32_t val) 4450c28c82e9SRob Clark { 4451c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK; 4452c28c82e9SRob Clark } 4453c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x00fff800 4454c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 4455c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 4456c28c82e9SRob Clark { 4457c28c82e9SRob Clark return ((val >> 7) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; 4458c28c82e9SRob Clark } 4459c28c82e9SRob Clark 4460c28c82e9SRob Clark #define REG_A6XX_RB_UNKNOWN_88F4 0x000088f4 4461c28c82e9SRob Clark 44622d756322SRob Clark #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x00008900 44632d756322SRob Clark 44642d756322SRob Clark #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x00008901 44652d756322SRob Clark 4466c28c82e9SRob Clark #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE 0x00008900 4467c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK 0xffffffff 4468c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT 0 4469c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_BASE(uint32_t val) 4470c28c82e9SRob Clark { 4471c28c82e9SRob Clark return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK; 4472c28c82e9SRob Clark } 4473c28c82e9SRob Clark 44742d756322SRob Clark #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x00008902 4475c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK 0x0000007f 4476c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 4477c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val) 4478c28c82e9SRob Clark { 4479c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK; 4480c28c82e9SRob Clark } 4481c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK 0x00000700 4482c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT 8 4483c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8(uint32_t val) 4484c28c82e9SRob Clark { 4485c28c82e9SRob Clark return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK; 4486c28c82e9SRob Clark } 4487c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x0ffff800 4488c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 4489c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 4490c28c82e9SRob Clark { 4491c28c82e9SRob Clark return ((val >> 7) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; 4492c28c82e9SRob Clark } 44932d756322SRob Clark 44942d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; } 44952d756322SRob Clark 44962d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x00008903 + 0x3*i0; } 44972d756322SRob Clark 44982d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x00008904 + 0x3*i0; } 44992d756322SRob Clark 4500c28c82e9SRob Clark static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; } 4501c28c82e9SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK 0xffffffff 4502c28c82e9SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT 0 4503c28c82e9SRob Clark static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t val) 4504c28c82e9SRob Clark { 4505c28c82e9SRob Clark return ((val) << A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK; 4506c28c82e9SRob Clark } 4507c28c82e9SRob Clark 45082d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; } 45092d756322SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff 45102d756322SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 45112d756322SRob Clark static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val) 45122d756322SRob Clark { 4513c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK; 45142d756322SRob Clark } 4515c28c82e9SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffff800 45162d756322SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 45172d756322SRob Clark static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 45182d756322SRob Clark { 4519c28c82e9SRob Clark return ((val >> 7) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; 45202d756322SRob Clark } 45212d756322SRob Clark 45222d756322SRob Clark #define REG_A6XX_RB_SAMPLE_COUNT_ADDR_LO 0x00008927 45232d756322SRob Clark 45242d756322SRob Clark #define REG_A6XX_RB_SAMPLE_COUNT_ADDR_HI 0x00008928 45252d756322SRob Clark 4526c28c82e9SRob Clark #define REG_A6XX_RB_SAMPLE_COUNT_ADDR 0x00008927 4527c28c82e9SRob Clark #define A6XX_RB_SAMPLE_COUNT_ADDR__MASK 0xffffffff 4528c28c82e9SRob Clark #define A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT 0 4529c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_COUNT_ADDR(uint32_t val) 4530c28c82e9SRob Clark { 4531c28c82e9SRob Clark return ((val) << A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT) & A6XX_RB_SAMPLE_COUNT_ADDR__MASK; 4532c28c82e9SRob Clark } 4533c28c82e9SRob Clark 45342d756322SRob Clark #define REG_A6XX_RB_2D_BLIT_CNTL 0x00008c00 4535c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK 0x00000007 4536c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT 0 4537c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val) 4538c28c82e9SRob Clark { 4539c28c82e9SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK; 4540c28c82e9SRob Clark } 4541c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_UNK3__MASK 0x00000078 4542c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_UNK3__SHIFT 3 4543c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK3(uint32_t val) 4544c28c82e9SRob Clark { 4545c28c82e9SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK3__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK3__MASK; 4546c28c82e9SRob Clark } 4547c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR 0x00000080 45482d756322SRob Clark #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00 45492d756322SRob Clark #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8 4550c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val) 45512d756322SRob Clark { 45522d756322SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK; 45532d756322SRob Clark } 4554ccdf7e28SRob Clark #define A6XX_RB_2D_BLIT_CNTL_SCISSOR 0x00010000 4555c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_UNK17__MASK 0x00060000 4556c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT 17 4557c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK17(uint32_t val) 4558c28c82e9SRob Clark { 4559c28c82e9SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK17__MASK; 4560c28c82e9SRob Clark } 4561c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_D24S8 0x00080000 4562c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_MASK__MASK 0x00f00000 4563c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT 20 4564c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_MASK(uint32_t val) 4565c28c82e9SRob Clark { 4566c28c82e9SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_RB_2D_BLIT_CNTL_MASK__MASK; 4567c28c82e9SRob Clark } 4568c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_IFMT__MASK 0x1f000000 4569c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT 24 4570c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val) 4571c28c82e9SRob Clark { 4572c28c82e9SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_IFMT__MASK; 4573c28c82e9SRob Clark } 4574c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_UNK29__MASK 0x20000000 4575c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_UNK29__SHIFT 29 4576c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK29(uint32_t val) 4577c28c82e9SRob Clark { 4578c28c82e9SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK29__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK29__MASK; 4579c28c82e9SRob Clark } 4580ccdf7e28SRob Clark 4581c28c82e9SRob Clark #define REG_A6XX_RB_2D_UNKNOWN_8C01 0x00008c01 45822d756322SRob Clark 45832d756322SRob Clark #define REG_A6XX_RB_2D_DST_INFO 0x00008c17 45842d756322SRob Clark #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff 45852d756322SRob Clark #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0 4586c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_format val) 45872d756322SRob Clark { 45882d756322SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK; 45892d756322SRob Clark } 45902d756322SRob Clark #define A6XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300 45912d756322SRob Clark #define A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8 45922d756322SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) 45932d756322SRob Clark { 45942d756322SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_2D_DST_INFO_TILE_MODE__MASK; 45952d756322SRob Clark } 45962d756322SRob Clark #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00 45972d756322SRob Clark #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10 45982d756322SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) 45992d756322SRob Clark { 46002d756322SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK; 46012d756322SRob Clark } 46022d756322SRob Clark #define A6XX_RB_2D_DST_INFO_FLAGS 0x00001000 4603c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_SRGB 0x00002000 4604c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_SAMPLES__MASK 0x0000c000 4605c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT 14 4606c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) 4607c28c82e9SRob Clark { 4608c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_2D_DST_INFO_SAMPLES__MASK; 4609c28c82e9SRob Clark } 4610c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_FILTER 0x00010000 4611c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE 0x00040000 4612c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_UNK20 0x00100000 4613c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_UNK22 0x00400000 46142d756322SRob Clark 46152d756322SRob Clark #define REG_A6XX_RB_2D_DST_LO 0x00008c18 46162d756322SRob Clark 46172d756322SRob Clark #define REG_A6XX_RB_2D_DST_HI 0x00008c19 46182d756322SRob Clark 4619c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST 0x00008c18 4620c28c82e9SRob Clark #define A6XX_RB_2D_DST__MASK 0xffffffff 4621c28c82e9SRob Clark #define A6XX_RB_2D_DST__SHIFT 0 4622c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST(uint32_t val) 46232d756322SRob Clark { 4624c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST__SHIFT) & A6XX_RB_2D_DST__MASK; 4625c28c82e9SRob Clark } 4626c28c82e9SRob Clark 4627c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_PITCH 0x00008c1a 4628c28c82e9SRob Clark #define A6XX_RB_2D_DST_PITCH__MASK 0x0000ffff 4629c28c82e9SRob Clark #define A6XX_RB_2D_DST_PITCH__SHIFT 0 4630c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_PITCH(uint32_t val) 4631c28c82e9SRob Clark { 4632c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_2D_DST_PITCH__SHIFT) & A6XX_RB_2D_DST_PITCH__MASK; 4633c28c82e9SRob Clark } 4634c28c82e9SRob Clark 4635c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_PLANE1 0x00008c1b 4636c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE1__MASK 0xffffffff 4637c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE1__SHIFT 0 4638c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_PLANE1(uint32_t val) 4639c28c82e9SRob Clark { 4640c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST_PLANE1__SHIFT) & A6XX_RB_2D_DST_PLANE1__MASK; 4641c28c82e9SRob Clark } 4642c28c82e9SRob Clark 4643c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_PLANE_PITCH 0x00008c1d 4644c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE_PITCH__MASK 0x0000ffff 4645c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE_PITCH__SHIFT 0 4646c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_PLANE_PITCH(uint32_t val) 4647c28c82e9SRob Clark { 4648c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_2D_DST_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_PLANE_PITCH__MASK; 4649c28c82e9SRob Clark } 4650c28c82e9SRob Clark 4651c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_PLANE2 0x00008c1e 4652c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE2__MASK 0xffffffff 4653c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE2__SHIFT 0 4654c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_PLANE2(uint32_t val) 4655c28c82e9SRob Clark { 4656c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST_PLANE2__SHIFT) & A6XX_RB_2D_DST_PLANE2__MASK; 46572d756322SRob Clark } 46582d756322SRob Clark 46592d756322SRob Clark #define REG_A6XX_RB_2D_DST_FLAGS_LO 0x00008c20 46602d756322SRob Clark 46612d756322SRob Clark #define REG_A6XX_RB_2D_DST_FLAGS_HI 0x00008c21 46622d756322SRob Clark 4663c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_FLAGS 0x00008c20 4664c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS__MASK 0xffffffff 4665c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS__SHIFT 0 4666c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_FLAGS(uint32_t val) 4667c28c82e9SRob Clark { 4668c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST_FLAGS__SHIFT) & A6XX_RB_2D_DST_FLAGS__MASK; 4669c28c82e9SRob Clark } 4670c28c82e9SRob Clark 4671c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_FLAGS_PITCH 0x00008c22 4672c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PITCH__MASK 0x000000ff 4673c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT 0 4674c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_FLAGS_PITCH(uint32_t val) 4675c28c82e9SRob Clark { 4676c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH__MASK; 4677c28c82e9SRob Clark } 4678c28c82e9SRob Clark 4679c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_FLAGS_PLANE 0x00008c23 4680c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PLANE__MASK 0xffffffff 4681c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT 0 4682c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE(uint32_t val) 4683c28c82e9SRob Clark { 4684c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE__MASK; 4685c28c82e9SRob Clark } 4686c28c82e9SRob Clark 4687c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH 0x00008c25 4688c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK 0x000000ff 4689c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT 0 4690c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(uint32_t val) 4691c28c82e9SRob Clark { 4692c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK; 4693c28c82e9SRob Clark } 4694c28c82e9SRob Clark 46952d756322SRob Clark #define REG_A6XX_RB_2D_SRC_SOLID_C0 0x00008c2c 46962d756322SRob Clark 46972d756322SRob Clark #define REG_A6XX_RB_2D_SRC_SOLID_C1 0x00008c2d 46982d756322SRob Clark 46992d756322SRob Clark #define REG_A6XX_RB_2D_SRC_SOLID_C2 0x00008c2e 47002d756322SRob Clark 47012d756322SRob Clark #define REG_A6XX_RB_2D_SRC_SOLID_C3 0x00008c2f 47022d756322SRob Clark 47032d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8E01 0x00008e01 47042d756322SRob Clark 4705a69c5ed2SRob Clark #define REG_A6XX_RB_UNKNOWN_8E04 0x00008e04 4706a69c5ed2SRob Clark 4707c28c82e9SRob Clark #define REG_A6XX_RB_ADDR_MODE_CNTL 0x00008e05 4708c28c82e9SRob Clark 47092d756322SRob Clark #define REG_A6XX_RB_CCU_CNTL 0x00008e07 4710c28c82e9SRob Clark #define A6XX_RB_CCU_CNTL_OFFSET__MASK 0xff800000 4711c28c82e9SRob Clark #define A6XX_RB_CCU_CNTL_OFFSET__SHIFT 23 4712c28c82e9SRob Clark static inline uint32_t A6XX_RB_CCU_CNTL_OFFSET(uint32_t val) 4713c28c82e9SRob Clark { 4714c28c82e9SRob Clark return ((val >> 12) << A6XX_RB_CCU_CNTL_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_OFFSET__MASK; 4715c28c82e9SRob Clark } 4716c28c82e9SRob Clark #define A6XX_RB_CCU_CNTL_GMEM 0x00400000 4717c28c82e9SRob Clark #define A6XX_RB_CCU_CNTL_UNK2 0x00000004 47182d756322SRob Clark 4719c28c82e9SRob Clark #define REG_A6XX_RB_NC_MODE_CNTL 0x00008e08 4720c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_MODE 0x00000001 4721c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006 4722c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT 1 4723c28c82e9SRob Clark static inline uint32_t A6XX_RB_NC_MODE_CNTL_LOWER_BIT(uint32_t val) 4724c28c82e9SRob Clark { 4725c28c82e9SRob Clark return ((val) << A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK; 4726c28c82e9SRob Clark } 4727c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008 4728c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_AMSBC 0x00000010 4729c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000400 4730c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT 10 4731c28c82e9SRob Clark static inline uint32_t A6XX_RB_NC_MODE_CNTL_UPPER_BIT(uint32_t val) 4732c28c82e9SRob Clark { 4733c28c82e9SRob Clark return ((val) << A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK; 4734c28c82e9SRob Clark } 4735c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR 0x00000800 4736c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_UNK12__MASK 0x00003000 4737c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT 12 4738c28c82e9SRob Clark static inline uint32_t A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val) 4739c28c82e9SRob Clark { 4740c28c82e9SRob Clark return ((val) << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK; 4741c28c82e9SRob Clark } 47422d756322SRob Clark 4743c28c82e9SRob Clark #define REG_A6XX_RB_PERFCTR_RB_SEL_0 0x00008e10 4744c28c82e9SRob Clark 4745c28c82e9SRob Clark #define REG_A6XX_RB_PERFCTR_RB_SEL_1 0x00008e11 4746c28c82e9SRob Clark 4747c28c82e9SRob Clark #define REG_A6XX_RB_PERFCTR_RB_SEL_2 0x00008e12 4748c28c82e9SRob Clark 4749c28c82e9SRob Clark #define REG_A6XX_RB_PERFCTR_RB_SEL_3 0x00008e13 4750c28c82e9SRob Clark 4751c28c82e9SRob Clark #define REG_A6XX_RB_PERFCTR_RB_SEL_4 0x00008e14 4752c28c82e9SRob Clark 4753c28c82e9SRob Clark #define REG_A6XX_RB_PERFCTR_RB_SEL_5 0x00008e15 4754c28c82e9SRob Clark 4755c28c82e9SRob Clark #define REG_A6XX_RB_PERFCTR_RB_SEL_6 0x00008e16 4756c28c82e9SRob Clark 4757c28c82e9SRob Clark #define REG_A6XX_RB_PERFCTR_RB_SEL_7 0x00008e17 4758c28c82e9SRob Clark 4759c28c82e9SRob Clark #define REG_A6XX_RB_PERFCTR_CCU_SEL_0 0x00008e18 4760c28c82e9SRob Clark 4761c28c82e9SRob Clark #define REG_A6XX_RB_PERFCTR_CCU_SEL_1 0x00008e19 4762c28c82e9SRob Clark 4763c28c82e9SRob Clark #define REG_A6XX_RB_PERFCTR_CCU_SEL_2 0x00008e1a 4764c28c82e9SRob Clark 4765c28c82e9SRob Clark #define REG_A6XX_RB_PERFCTR_CCU_SEL_3 0x00008e1b 4766c28c82e9SRob Clark 4767c28c82e9SRob Clark #define REG_A6XX_RB_PERFCTR_CCU_SEL_4 0x00008e1c 4768c28c82e9SRob Clark 4769c28c82e9SRob Clark #define REG_A6XX_RB_UNKNOWN_8E28 0x00008e28 4770c28c82e9SRob Clark 4771c28c82e9SRob Clark #define REG_A6XX_RB_PERFCTR_CMP_SEL_0 0x00008e2c 4772c28c82e9SRob Clark 4773c28c82e9SRob Clark #define REG_A6XX_RB_PERFCTR_CMP_SEL_1 0x00008e2d 4774c28c82e9SRob Clark 4775c28c82e9SRob Clark #define REG_A6XX_RB_PERFCTR_CMP_SEL_2 0x00008e2e 4776c28c82e9SRob Clark 4777c28c82e9SRob Clark #define REG_A6XX_RB_PERFCTR_CMP_SEL_3 0x00008e2f 4778c28c82e9SRob Clark 4779c28c82e9SRob Clark #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST 0x00008e3b 4780c28c82e9SRob Clark 4781c28c82e9SRob Clark #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD 0x00008e3d 4782c28c82e9SRob Clark 4783c28c82e9SRob Clark #define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x00008e50 4784c28c82e9SRob Clark 4785c28c82e9SRob Clark #define REG_A6XX_RB_UNKNOWN_8E51 0x00008e51 4786c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_8E51__MASK 0xffffffff 4787c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_8E51__SHIFT 0 4788c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNKNOWN_8E51(uint32_t val) 4789c28c82e9SRob Clark { 4790c28c82e9SRob Clark return ((val) << A6XX_RB_UNKNOWN_8E51__SHIFT) & A6XX_RB_UNKNOWN_8E51__MASK; 4791c28c82e9SRob Clark } 4792c28c82e9SRob Clark 4793c28c82e9SRob Clark #define REG_A6XX_VPC_UNKNOWN_9100 0x00009100 4794c28c82e9SRob Clark 4795c28c82e9SRob Clark #define REG_A6XX_VPC_VS_CLIP_CNTL 0x00009101 4796c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff 4797c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT 0 4798c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(uint32_t val) 4799c28c82e9SRob Clark { 4800c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK; 4801c28c82e9SRob Clark } 4802c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00 4803c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8 4804c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) 4805c28c82e9SRob Clark { 4806c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK; 4807c28c82e9SRob Clark } 4808c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000 4809c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16 4810c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) 4811c28c82e9SRob Clark { 4812c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; 4813c28c82e9SRob Clark } 4814c28c82e9SRob Clark 4815c28c82e9SRob Clark #define REG_A6XX_VPC_GS_CLIP_CNTL 0x00009102 4816c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff 4817c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT 0 4818c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK(uint32_t val) 4819c28c82e9SRob Clark { 4820c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK; 4821c28c82e9SRob Clark } 4822c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00 4823c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8 4824c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) 4825c28c82e9SRob Clark { 4826c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK; 4827c28c82e9SRob Clark } 4828c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000 4829c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16 4830c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) 4831c28c82e9SRob Clark { 4832c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; 4833c28c82e9SRob Clark } 4834c28c82e9SRob Clark 4835c28c82e9SRob Clark #define REG_A6XX_VPC_DS_CLIP_CNTL 0x00009103 4836c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff 4837c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT 0 4838c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK(uint32_t val) 4839c28c82e9SRob Clark { 4840c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK; 4841c28c82e9SRob Clark } 4842c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00 4843c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8 4844c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) 4845c28c82e9SRob Clark { 4846c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK; 4847c28c82e9SRob Clark } 4848c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000 4849c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16 4850c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) 4851c28c82e9SRob Clark { 4852c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; 4853c28c82e9SRob Clark } 4854c28c82e9SRob Clark 4855c28c82e9SRob Clark #define REG_A6XX_VPC_VS_LAYER_CNTL 0x00009104 4856c28c82e9SRob Clark #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff 4857c28c82e9SRob Clark #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT 0 4858c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(uint32_t val) 4859c28c82e9SRob Clark { 4860c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK; 4861c28c82e9SRob Clark } 4862c28c82e9SRob Clark #define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00 4863c28c82e9SRob Clark #define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT 8 4864c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(uint32_t val) 4865c28c82e9SRob Clark { 4866c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK; 4867c28c82e9SRob Clark } 4868c28c82e9SRob Clark 4869c28c82e9SRob Clark #define REG_A6XX_VPC_GS_LAYER_CNTL 0x00009105 4870c28c82e9SRob Clark #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff 4871c28c82e9SRob Clark #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT 0 4872c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(uint32_t val) 4873c28c82e9SRob Clark { 4874c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK; 4875c28c82e9SRob Clark } 4876c28c82e9SRob Clark #define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00 4877c28c82e9SRob Clark #define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT 8 4878c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(uint32_t val) 4879c28c82e9SRob Clark { 4880c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK; 4881c28c82e9SRob Clark } 4882c28c82e9SRob Clark 4883c28c82e9SRob Clark #define REG_A6XX_VPC_DS_LAYER_CNTL 0x00009106 4884c28c82e9SRob Clark #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff 4885c28c82e9SRob Clark #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT 0 4886c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_LAYERLOC(uint32_t val) 4887c28c82e9SRob Clark { 4888c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK; 4889c28c82e9SRob Clark } 4890c28c82e9SRob Clark #define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00 4891c28c82e9SRob Clark #define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT 8 4892c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val) 4893c28c82e9SRob Clark { 4894c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK; 4895c28c82e9SRob Clark } 48962d756322SRob Clark 4897a69c5ed2SRob Clark #define REG_A6XX_VPC_UNKNOWN_9107 0x00009107 4898a69c5ed2SRob Clark 4899c28c82e9SRob Clark #define REG_A6XX_VPC_POLYGON_MODE 0x00009108 4900c28c82e9SRob Clark #define A6XX_VPC_POLYGON_MODE_MODE__MASK 0x00000003 4901c28c82e9SRob Clark #define A6XX_VPC_POLYGON_MODE_MODE__SHIFT 0 4902c28c82e9SRob Clark static inline uint32_t A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) 4903c28c82e9SRob Clark { 4904c28c82e9SRob Clark return ((val) << A6XX_VPC_POLYGON_MODE_MODE__SHIFT) & A6XX_VPC_POLYGON_MODE_MODE__MASK; 4905c28c82e9SRob Clark } 49062d756322SRob Clark 49072d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; } 49082d756322SRob Clark 49092d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; } 49102d756322SRob Clark 49112d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; } 49122d756322SRob Clark 49132d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; } 49142d756322SRob Clark 49152d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9210 0x00009210 49162d756322SRob Clark 49172d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9211 0x00009211 49182d756322SRob Clark 49192d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; } 49202d756322SRob Clark 49212d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; } 49222d756322SRob Clark 49232d756322SRob Clark #define REG_A6XX_VPC_SO_CNTL 0x00009216 4924c28c82e9SRob Clark #define A6XX_VPC_SO_CNTL_UNK0__MASK 0x000000ff 4925c28c82e9SRob Clark #define A6XX_VPC_SO_CNTL_UNK0__SHIFT 0 4926c28c82e9SRob Clark static inline uint32_t A6XX_VPC_SO_CNTL_UNK0(uint32_t val) 4927c28c82e9SRob Clark { 4928c28c82e9SRob Clark return ((val) << A6XX_VPC_SO_CNTL_UNK0__SHIFT) & A6XX_VPC_SO_CNTL_UNK0__MASK; 4929c28c82e9SRob Clark } 49302d756322SRob Clark #define A6XX_VPC_SO_CNTL_ENABLE 0x00010000 49312d756322SRob Clark 49322d756322SRob Clark #define REG_A6XX_VPC_SO_PROG 0x00009217 49332d756322SRob Clark #define A6XX_VPC_SO_PROG_A_BUF__MASK 0x00000003 49342d756322SRob Clark #define A6XX_VPC_SO_PROG_A_BUF__SHIFT 0 49352d756322SRob Clark static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val) 49362d756322SRob Clark { 49372d756322SRob Clark return ((val) << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK; 49382d756322SRob Clark } 49392d756322SRob Clark #define A6XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc 49402d756322SRob Clark #define A6XX_VPC_SO_PROG_A_OFF__SHIFT 2 49412d756322SRob Clark static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val) 49422d756322SRob Clark { 49432d756322SRob Clark return ((val >> 2) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK; 49442d756322SRob Clark } 49452d756322SRob Clark #define A6XX_VPC_SO_PROG_A_EN 0x00000800 49462d756322SRob Clark #define A6XX_VPC_SO_PROG_B_BUF__MASK 0x00003000 49472d756322SRob Clark #define A6XX_VPC_SO_PROG_B_BUF__SHIFT 12 49482d756322SRob Clark static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val) 49492d756322SRob Clark { 49502d756322SRob Clark return ((val) << A6XX_VPC_SO_PROG_B_BUF__SHIFT) & A6XX_VPC_SO_PROG_B_BUF__MASK; 49512d756322SRob Clark } 49522d756322SRob Clark #define A6XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000 49532d756322SRob Clark #define A6XX_VPC_SO_PROG_B_OFF__SHIFT 14 49542d756322SRob Clark static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val) 49552d756322SRob Clark { 49562d756322SRob Clark return ((val >> 2) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK; 49572d756322SRob Clark } 49582d756322SRob Clark #define A6XX_VPC_SO_PROG_B_EN 0x00800000 49592d756322SRob Clark 4960c28c82e9SRob Clark #define REG_A6XX_VPC_SO_STREAM_COUNTS_LO 0x00009218 4961c28c82e9SRob Clark 4962c28c82e9SRob Clark #define REG_A6XX_VPC_SO_STREAM_COUNTS_HI 0x00009219 4963c28c82e9SRob Clark 4964c28c82e9SRob Clark #define REG_A6XX_VPC_SO_STREAM_COUNTS 0x00009218 4965c28c82e9SRob Clark #define A6XX_VPC_SO_STREAM_COUNTS__MASK 0xffffffff 4966c28c82e9SRob Clark #define A6XX_VPC_SO_STREAM_COUNTS__SHIFT 0 4967c28c82e9SRob Clark static inline uint32_t A6XX_VPC_SO_STREAM_COUNTS(uint32_t val) 4968c28c82e9SRob Clark { 4969c28c82e9SRob Clark return ((val) << A6XX_VPC_SO_STREAM_COUNTS__SHIFT) & A6XX_VPC_SO_STREAM_COUNTS__MASK; 4970c28c82e9SRob Clark } 4971c28c82e9SRob Clark 49722d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; } 49732d756322SRob Clark 4974c28c82e9SRob Clark static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0) { return 0x0000921a + 0x7*i0; } 4975c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_BASE__MASK 0xffffffff 4976c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_BASE__SHIFT 0 4977c28c82e9SRob Clark static inline uint32_t A6XX_VPC_SO_BUFFER_BASE(uint32_t val) 4978c28c82e9SRob Clark { 4979c28c82e9SRob Clark return ((val) << A6XX_VPC_SO_BUFFER_BASE__SHIFT) & A6XX_VPC_SO_BUFFER_BASE__MASK; 4980c28c82e9SRob Clark } 4981c28c82e9SRob Clark 49822d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000921a + 0x7*i0; } 49832d756322SRob Clark 49842d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000921b + 0x7*i0; } 49852d756322SRob Clark 49862d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; } 4987c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_SIZE__MASK 0xfffffffc 4988c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_SIZE__SHIFT 2 4989c28c82e9SRob Clark static inline uint32_t A6XX_VPC_SO_BUFFER_SIZE(uint32_t val) 4990c28c82e9SRob Clark { 4991c28c82e9SRob Clark return ((val >> 2) << A6XX_VPC_SO_BUFFER_SIZE__SHIFT) & A6XX_VPC_SO_BUFFER_SIZE__MASK; 4992c28c82e9SRob Clark } 49932d756322SRob Clark 49942d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000921d + 0x7*i0; } 49952d756322SRob Clark 49962d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; } 4997c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_OFFSET__MASK 0xfffffffc 4998c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_OFFSET__SHIFT 2 4999c28c82e9SRob Clark static inline uint32_t A6XX_VPC_SO_BUFFER_OFFSET(uint32_t val) 5000c28c82e9SRob Clark { 5001c28c82e9SRob Clark return ((val >> 2) << A6XX_VPC_SO_BUFFER_OFFSET__SHIFT) & A6XX_VPC_SO_BUFFER_OFFSET__MASK; 5002c28c82e9SRob Clark } 5003c28c82e9SRob Clark 5004c28c82e9SRob Clark static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0) { return 0x0000921f + 0x7*i0; } 5005c28c82e9SRob Clark #define A6XX_VPC_SO_FLUSH_BASE__MASK 0xffffffff 5006c28c82e9SRob Clark #define A6XX_VPC_SO_FLUSH_BASE__SHIFT 0 5007c28c82e9SRob Clark static inline uint32_t A6XX_VPC_SO_FLUSH_BASE(uint32_t val) 5008c28c82e9SRob Clark { 5009c28c82e9SRob Clark return ((val) << A6XX_VPC_SO_FLUSH_BASE__SHIFT) & A6XX_VPC_SO_FLUSH_BASE__MASK; 5010c28c82e9SRob Clark } 50112d756322SRob Clark 50122d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000921f + 0x7*i0; } 50132d756322SRob Clark 50142d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x00009220 + 0x7*i0; } 50152d756322SRob Clark 5016c28c82e9SRob Clark #define REG_A6XX_VPC_POINT_COORD_INVERT 0x00009236 5017c28c82e9SRob Clark #define A6XX_VPC_POINT_COORD_INVERT_INVERT 0x00000001 50182d756322SRob Clark 50192d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9300 0x00009300 50202d756322SRob Clark 5021c28c82e9SRob Clark #define REG_A6XX_VPC_VS_PACK 0x00009301 5022c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK 0x000000ff 5023c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT 0 5024c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_PACK_STRIDE_IN_VPC(uint32_t val) 50252d756322SRob Clark { 5026c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK; 50272d756322SRob Clark } 5028c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_POSITIONLOC__MASK 0x0000ff00 5029c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT 8 5030c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_PACK_POSITIONLOC(uint32_t val) 50312d756322SRob Clark { 5032c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_VS_PACK_POSITIONLOC__MASK; 50332d756322SRob Clark } 5034c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_PSIZELOC__MASK 0x00ff0000 5035c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_PSIZELOC__SHIFT 16 5036c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_PACK_PSIZELOC(uint32_t val) 50372d756322SRob Clark { 5038c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_VS_PACK_PSIZELOC__MASK; 5039c28c82e9SRob Clark } 5040c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_UNK24__MASK 0x0f000000 5041c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_UNK24__SHIFT 24 5042c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_PACK_UNK24(uint32_t val) 5043c28c82e9SRob Clark { 5044c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_PACK_UNK24__SHIFT) & A6XX_VPC_VS_PACK_UNK24__MASK; 5045c28c82e9SRob Clark } 5046c28c82e9SRob Clark 5047c28c82e9SRob Clark #define REG_A6XX_VPC_GS_PACK 0x00009302 5048c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK 0x000000ff 5049c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT 0 5050c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_PACK_STRIDE_IN_VPC(uint32_t val) 5051c28c82e9SRob Clark { 5052c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK; 5053c28c82e9SRob Clark } 5054c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_POSITIONLOC__MASK 0x0000ff00 5055c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT 8 5056c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_PACK_POSITIONLOC(uint32_t val) 5057c28c82e9SRob Clark { 5058c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_GS_PACK_POSITIONLOC__MASK; 5059c28c82e9SRob Clark } 5060c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_PSIZELOC__MASK 0x00ff0000 5061c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_PSIZELOC__SHIFT 16 5062c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_PACK_PSIZELOC(uint32_t val) 5063c28c82e9SRob Clark { 5064c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_GS_PACK_PSIZELOC__MASK; 5065c28c82e9SRob Clark } 5066c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_UNK24__MASK 0x0f000000 5067c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_UNK24__SHIFT 24 5068c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_PACK_UNK24(uint32_t val) 5069c28c82e9SRob Clark { 5070c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_PACK_UNK24__SHIFT) & A6XX_VPC_GS_PACK_UNK24__MASK; 5071c28c82e9SRob Clark } 5072c28c82e9SRob Clark 5073c28c82e9SRob Clark #define REG_A6XX_VPC_DS_PACK 0x00009303 5074c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK 0x000000ff 5075c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT 0 5076c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_PACK_STRIDE_IN_VPC(uint32_t val) 5077c28c82e9SRob Clark { 5078c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK; 5079c28c82e9SRob Clark } 5080c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_POSITIONLOC__MASK 0x0000ff00 5081c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT 8 5082c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_PACK_POSITIONLOC(uint32_t val) 5083c28c82e9SRob Clark { 5084c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_DS_PACK_POSITIONLOC__MASK; 5085c28c82e9SRob Clark } 5086c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_PSIZELOC__MASK 0x00ff0000 5087c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_PSIZELOC__SHIFT 16 5088c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_PACK_PSIZELOC(uint32_t val) 5089c28c82e9SRob Clark { 5090c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_DS_PACK_PSIZELOC__MASK; 5091c28c82e9SRob Clark } 5092c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_UNK24__MASK 0x0f000000 5093c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_UNK24__SHIFT 24 5094c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_PACK_UNK24(uint32_t val) 5095c28c82e9SRob Clark { 5096c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_PACK_UNK24__SHIFT) & A6XX_VPC_DS_PACK_UNK24__MASK; 50972d756322SRob Clark } 50982d756322SRob Clark 50992d756322SRob Clark #define REG_A6XX_VPC_CNTL_0 0x00009304 51002d756322SRob Clark #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK 0x000000ff 51012d756322SRob Clark #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT 0 51022d756322SRob Clark static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val) 51032d756322SRob Clark { 51042d756322SRob Clark return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK; 51052d756322SRob Clark } 5106c28c82e9SRob Clark #define A6XX_VPC_CNTL_0_PRIMIDLOC__MASK 0x0000ff00 5107c28c82e9SRob Clark #define A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT 8 5108c28c82e9SRob Clark static inline uint32_t A6XX_VPC_CNTL_0_PRIMIDLOC(uint32_t val) 5109c28c82e9SRob Clark { 5110c28c82e9SRob Clark return ((val) << A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT) & A6XX_VPC_CNTL_0_PRIMIDLOC__MASK; 5111c28c82e9SRob Clark } 51122d756322SRob Clark #define A6XX_VPC_CNTL_0_VARYING 0x00010000 5113c28c82e9SRob Clark #define A6XX_VPC_CNTL_0_UNKLOC__MASK 0xff000000 5114c28c82e9SRob Clark #define A6XX_VPC_CNTL_0_UNKLOC__SHIFT 24 5115c28c82e9SRob Clark static inline uint32_t A6XX_VPC_CNTL_0_UNKLOC(uint32_t val) 5116c28c82e9SRob Clark { 5117c28c82e9SRob Clark return ((val) << A6XX_VPC_CNTL_0_UNKLOC__SHIFT) & A6XX_VPC_CNTL_0_UNKLOC__MASK; 5118c28c82e9SRob Clark } 51192d756322SRob Clark 51202d756322SRob Clark #define REG_A6XX_VPC_SO_BUF_CNTL 0x00009305 51212d756322SRob Clark #define A6XX_VPC_SO_BUF_CNTL_BUF0 0x00000001 51222d756322SRob Clark #define A6XX_VPC_SO_BUF_CNTL_BUF1 0x00000008 51232d756322SRob Clark #define A6XX_VPC_SO_BUF_CNTL_BUF2 0x00000040 51242d756322SRob Clark #define A6XX_VPC_SO_BUF_CNTL_BUF3 0x00000200 51252d756322SRob Clark #define A6XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000 5126c28c82e9SRob Clark #define A6XX_VPC_SO_BUF_CNTL_UNK16__MASK 0x000f0000 5127c28c82e9SRob Clark #define A6XX_VPC_SO_BUF_CNTL_UNK16__SHIFT 16 5128c28c82e9SRob Clark static inline uint32_t A6XX_VPC_SO_BUF_CNTL_UNK16(uint32_t val) 5129c28c82e9SRob Clark { 5130c28c82e9SRob Clark return ((val) << A6XX_VPC_SO_BUF_CNTL_UNK16__SHIFT) & A6XX_VPC_SO_BUF_CNTL_UNK16__MASK; 5131c28c82e9SRob Clark } 51322d756322SRob Clark 5133c28c82e9SRob Clark #define REG_A6XX_VPC_SO_DISABLE 0x00009306 5134c28c82e9SRob Clark #define A6XX_VPC_SO_DISABLE_DISABLE 0x00000001 5135a69c5ed2SRob Clark 51362d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9600 0x00009600 51372d756322SRob Clark 5138c28c82e9SRob Clark #define REG_A6XX_VPC_ADDR_MODE_CNTL 0x00009601 5139c28c82e9SRob Clark 51402d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9602 0x00009602 51412d756322SRob Clark 5142c28c82e9SRob Clark #define REG_A6XX_VPC_UNKNOWN_9603 0x00009603 5143c28c82e9SRob Clark 5144c28c82e9SRob Clark #define REG_A6XX_VPC_PERFCTR_VPC_SEL_0 0x00009604 5145c28c82e9SRob Clark 5146c28c82e9SRob Clark #define REG_A6XX_VPC_PERFCTR_VPC_SEL_1 0x00009605 5147c28c82e9SRob Clark 5148c28c82e9SRob Clark #define REG_A6XX_VPC_PERFCTR_VPC_SEL_2 0x00009606 5149c28c82e9SRob Clark 5150c28c82e9SRob Clark #define REG_A6XX_VPC_PERFCTR_VPC_SEL_3 0x00009607 5151c28c82e9SRob Clark 5152c28c82e9SRob Clark #define REG_A6XX_VPC_PERFCTR_VPC_SEL_4 0x00009608 5153c28c82e9SRob Clark 5154c28c82e9SRob Clark #define REG_A6XX_VPC_PERFCTR_VPC_SEL_5 0x00009609 5155c28c82e9SRob Clark 5156c28c82e9SRob Clark #define REG_A6XX_PC_TESS_NUM_VERTEX 0x00009800 5157c28c82e9SRob Clark 51582d756322SRob Clark #define REG_A6XX_PC_UNKNOWN_9801 0x00009801 5159c28c82e9SRob Clark #define A6XX_PC_UNKNOWN_9801_UNK0__MASK 0x000007ff 5160c28c82e9SRob Clark #define A6XX_PC_UNKNOWN_9801_UNK0__SHIFT 0 5161c28c82e9SRob Clark static inline uint32_t A6XX_PC_UNKNOWN_9801_UNK0(uint32_t val) 5162c28c82e9SRob Clark { 5163c28c82e9SRob Clark return ((val) << A6XX_PC_UNKNOWN_9801_UNK0__SHIFT) & A6XX_PC_UNKNOWN_9801_UNK0__MASK; 5164c28c82e9SRob Clark } 5165c28c82e9SRob Clark #define A6XX_PC_UNKNOWN_9801_UNK13__MASK 0x00002000 5166c28c82e9SRob Clark #define A6XX_PC_UNKNOWN_9801_UNK13__SHIFT 13 5167c28c82e9SRob Clark static inline uint32_t A6XX_PC_UNKNOWN_9801_UNK13(uint32_t val) 5168c28c82e9SRob Clark { 5169c28c82e9SRob Clark return ((val) << A6XX_PC_UNKNOWN_9801_UNK13__SHIFT) & A6XX_PC_UNKNOWN_9801_UNK13__MASK; 5170c28c82e9SRob Clark } 5171c28c82e9SRob Clark 5172c28c82e9SRob Clark #define REG_A6XX_PC_TESS_CNTL 0x00009802 5173c28c82e9SRob Clark #define A6XX_PC_TESS_CNTL_SPACING__MASK 0x00000003 5174c28c82e9SRob Clark #define A6XX_PC_TESS_CNTL_SPACING__SHIFT 0 5175c28c82e9SRob Clark static inline uint32_t A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val) 5176c28c82e9SRob Clark { 5177c28c82e9SRob Clark return ((val) << A6XX_PC_TESS_CNTL_SPACING__SHIFT) & A6XX_PC_TESS_CNTL_SPACING__MASK; 5178c28c82e9SRob Clark } 5179c28c82e9SRob Clark #define A6XX_PC_TESS_CNTL_OUTPUT__MASK 0x0000000c 5180c28c82e9SRob Clark #define A6XX_PC_TESS_CNTL_OUTPUT__SHIFT 2 5181c28c82e9SRob Clark static inline uint32_t A6XX_PC_TESS_CNTL_OUTPUT(enum a6xx_tess_output val) 5182c28c82e9SRob Clark { 5183c28c82e9SRob Clark return ((val) << A6XX_PC_TESS_CNTL_OUTPUT__SHIFT) & A6XX_PC_TESS_CNTL_OUTPUT__MASK; 5184c28c82e9SRob Clark } 51852d756322SRob Clark 51862d756322SRob Clark #define REG_A6XX_PC_RESTART_INDEX 0x00009803 51872d756322SRob Clark 51882d756322SRob Clark #define REG_A6XX_PC_MODE_CNTL 0x00009804 51892d756322SRob Clark 51902d756322SRob Clark #define REG_A6XX_PC_UNKNOWN_9805 0x00009805 51912d756322SRob Clark 5192c28c82e9SRob Clark #define REG_A6XX_PC_PRIMID_PASSTHRU 0x00009806 5193c28c82e9SRob Clark 5194c28c82e9SRob Clark #define REG_A6XX_PC_DRAW_CMD 0x00009840 5195c28c82e9SRob Clark #define A6XX_PC_DRAW_CMD_STATE_ID__MASK 0x000000ff 5196c28c82e9SRob Clark #define A6XX_PC_DRAW_CMD_STATE_ID__SHIFT 0 5197c28c82e9SRob Clark static inline uint32_t A6XX_PC_DRAW_CMD_STATE_ID(uint32_t val) 5198c28c82e9SRob Clark { 5199c28c82e9SRob Clark return ((val) << A6XX_PC_DRAW_CMD_STATE_ID__SHIFT) & A6XX_PC_DRAW_CMD_STATE_ID__MASK; 5200c28c82e9SRob Clark } 5201c28c82e9SRob Clark 5202c28c82e9SRob Clark #define REG_A6XX_PC_DISPATCH_CMD 0x00009841 5203c28c82e9SRob Clark #define A6XX_PC_DISPATCH_CMD_STATE_ID__MASK 0x000000ff 5204c28c82e9SRob Clark #define A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT 0 5205c28c82e9SRob Clark static inline uint32_t A6XX_PC_DISPATCH_CMD_STATE_ID(uint32_t val) 5206c28c82e9SRob Clark { 5207c28c82e9SRob Clark return ((val) << A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_PC_DISPATCH_CMD_STATE_ID__MASK; 5208c28c82e9SRob Clark } 5209c28c82e9SRob Clark 5210c28c82e9SRob Clark #define REG_A6XX_PC_EVENT_CMD 0x00009842 5211c28c82e9SRob Clark #define A6XX_PC_EVENT_CMD_STATE_ID__MASK 0x00ff0000 5212c28c82e9SRob Clark #define A6XX_PC_EVENT_CMD_STATE_ID__SHIFT 16 5213c28c82e9SRob Clark static inline uint32_t A6XX_PC_EVENT_CMD_STATE_ID(uint32_t val) 5214c28c82e9SRob Clark { 5215c28c82e9SRob Clark return ((val) << A6XX_PC_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_EVENT_CMD_STATE_ID__MASK; 5216c28c82e9SRob Clark } 5217c28c82e9SRob Clark #define A6XX_PC_EVENT_CMD_EVENT__MASK 0x0000007f 5218c28c82e9SRob Clark #define A6XX_PC_EVENT_CMD_EVENT__SHIFT 0 5219c28c82e9SRob Clark static inline uint32_t A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val) 5220c28c82e9SRob Clark { 5221c28c82e9SRob Clark return ((val) << A6XX_PC_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_EVENT_CMD_EVENT__MASK; 5222c28c82e9SRob Clark } 5223c28c82e9SRob Clark 5224c28c82e9SRob Clark #define REG_A6XX_PC_POLYGON_MODE 0x00009981 5225c28c82e9SRob Clark #define A6XX_PC_POLYGON_MODE_MODE__MASK 0x00000003 5226c28c82e9SRob Clark #define A6XX_PC_POLYGON_MODE_MODE__SHIFT 0 5227c28c82e9SRob Clark static inline uint32_t A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) 5228c28c82e9SRob Clark { 5229c28c82e9SRob Clark return ((val) << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK; 5230c28c82e9SRob Clark } 5231a69c5ed2SRob Clark 5232a69c5ed2SRob Clark #define REG_A6XX_PC_UNKNOWN_9980 0x00009980 5233a69c5ed2SRob Clark 52342d756322SRob Clark #define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00 52352d756322SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001 52362d756322SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002 5237c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_0_TESS_UPPER_LEFT_DOMAIN_ORIGIN 0x00000004 5238c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_0_UNK3 0x00000008 52392d756322SRob Clark 5240c28c82e9SRob Clark #define REG_A6XX_PC_VS_OUT_CNTL 0x00009b01 5241c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff 5242c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 5243c28c82e9SRob Clark static inline uint32_t A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) 52442d756322SRob Clark { 5245c28c82e9SRob Clark return ((val) << A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK; 52462d756322SRob Clark } 5247c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_PSIZE 0x00000100 5248c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_LAYER 0x00000200 5249c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_VIEW 0x00000400 5250c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID 0x00000800 5251c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 5252c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT 16 5253c28c82e9SRob Clark static inline uint32_t A6XX_PC_VS_OUT_CNTL_CLIP_MASK(uint32_t val) 5254c28c82e9SRob Clark { 5255c28c82e9SRob Clark return ((val) << A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK; 5256c28c82e9SRob Clark } 52572d756322SRob Clark 5258c28c82e9SRob Clark #define REG_A6XX_PC_GS_OUT_CNTL 0x00009b02 5259c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff 5260c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 5261c28c82e9SRob Clark static inline uint32_t A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) 5262c28c82e9SRob Clark { 5263c28c82e9SRob Clark return ((val) << A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK; 5264c28c82e9SRob Clark } 5265c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_PSIZE 0x00000100 5266c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_LAYER 0x00000200 5267c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_VIEW 0x00000400 5268c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID 0x00000800 5269c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 5270c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT 16 5271c28c82e9SRob Clark static inline uint32_t A6XX_PC_GS_OUT_CNTL_CLIP_MASK(uint32_t val) 5272c28c82e9SRob Clark { 5273c28c82e9SRob Clark return ((val) << A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK; 5274c28c82e9SRob Clark } 5275c28c82e9SRob Clark 5276c28c82e9SRob Clark #define REG_A6XX_PC_PRIMITIVE_CNTL_3 0x00009b03 5277c28c82e9SRob Clark 5278c28c82e9SRob Clark #define REG_A6XX_PC_DS_OUT_CNTL 0x00009b04 5279c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff 5280c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 5281c28c82e9SRob Clark static inline uint32_t A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) 5282c28c82e9SRob Clark { 5283c28c82e9SRob Clark return ((val) << A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK; 5284c28c82e9SRob Clark } 5285c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_PSIZE 0x00000100 5286c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_LAYER 0x00000200 5287c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_VIEW 0x00000400 5288c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID 0x00000800 5289c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 5290c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT 16 5291c28c82e9SRob Clark static inline uint32_t A6XX_PC_DS_OUT_CNTL_CLIP_MASK(uint32_t val) 5292c28c82e9SRob Clark { 5293c28c82e9SRob Clark return ((val) << A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK; 5294c28c82e9SRob Clark } 5295c28c82e9SRob Clark 5296c28c82e9SRob Clark #define REG_A6XX_PC_PRIMITIVE_CNTL_5 0x00009b05 5297c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK 0x000000ff 5298c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT 0 5299c28c82e9SRob Clark static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val) 5300c28c82e9SRob Clark { 5301c28c82e9SRob Clark return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK; 5302c28c82e9SRob Clark } 5303c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK 0x00007c00 5304c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT 10 5305c28c82e9SRob Clark static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val) 5306c28c82e9SRob Clark { 5307c28c82e9SRob Clark return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK; 5308c28c82e9SRob Clark } 5309c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK 0x00030000 5310c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT 16 5311c28c82e9SRob Clark static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val) 5312c28c82e9SRob Clark { 5313c28c82e9SRob Clark return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK; 5314c28c82e9SRob Clark } 5315c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK 0x00040000 5316c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT 18 5317c28c82e9SRob Clark static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_UNK18(uint32_t val) 5318c28c82e9SRob Clark { 5319c28c82e9SRob Clark return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK; 5320c28c82e9SRob Clark } 5321c28c82e9SRob Clark 5322c28c82e9SRob Clark #define REG_A6XX_PC_PRIMITIVE_CNTL_6 0x00009b06 5323c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK 0x000007ff 5324c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT 0 5325c28c82e9SRob Clark static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(uint32_t val) 5326c28c82e9SRob Clark { 5327c28c82e9SRob Clark return ((val) << A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK; 5328c28c82e9SRob Clark } 53292d756322SRob Clark 53302d756322SRob Clark #define REG_A6XX_PC_UNKNOWN_9B07 0x00009b07 53312d756322SRob Clark 5332c28c82e9SRob Clark #define REG_A6XX_PC_UNKNOWN_9B08 0x00009b08 5333c28c82e9SRob Clark 5334c28c82e9SRob Clark #define REG_A6XX_PC_2D_EVENT_CMD 0x00009c00 5335c28c82e9SRob Clark #define A6XX_PC_2D_EVENT_CMD_EVENT__MASK 0x0000007f 5336c28c82e9SRob Clark #define A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT 0 5337c28c82e9SRob Clark static inline uint32_t A6XX_PC_2D_EVENT_CMD_EVENT(enum vgt_event_type val) 5338c28c82e9SRob Clark { 5339c28c82e9SRob Clark return ((val) << A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_2D_EVENT_CMD_EVENT__MASK; 5340c28c82e9SRob Clark } 5341c28c82e9SRob Clark #define A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00 5342c28c82e9SRob Clark #define A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT 8 5343c28c82e9SRob Clark static inline uint32_t A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val) 5344c28c82e9SRob Clark { 5345c28c82e9SRob Clark return ((val) << A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK; 5346c28c82e9SRob Clark } 5347c28c82e9SRob Clark 5348c28c82e9SRob Clark #define REG_A6XX_PC_DBG_ECO_CNTL 0x00009e00 5349c28c82e9SRob Clark 5350c28c82e9SRob Clark #define REG_A6XX_PC_ADDR_MODE_CNTL 0x00009e01 5351c28c82e9SRob Clark 53522d756322SRob Clark #define REG_A6XX_PC_TESSFACTOR_ADDR_LO 0x00009e08 53532d756322SRob Clark 53542d756322SRob Clark #define REG_A6XX_PC_TESSFACTOR_ADDR_HI 0x00009e09 53552d756322SRob Clark 5356c28c82e9SRob Clark #define REG_A6XX_PC_TESSFACTOR_ADDR 0x00009e08 5357c28c82e9SRob Clark #define A6XX_PC_TESSFACTOR_ADDR__MASK 0xffffffff 5358c28c82e9SRob Clark #define A6XX_PC_TESSFACTOR_ADDR__SHIFT 0 5359c28c82e9SRob Clark static inline uint32_t A6XX_PC_TESSFACTOR_ADDR(uint32_t val) 5360c28c82e9SRob Clark { 5361c28c82e9SRob Clark return ((val) << A6XX_PC_TESSFACTOR_ADDR__SHIFT) & A6XX_PC_TESSFACTOR_ADDR__MASK; 5362c28c82e9SRob Clark } 5363c28c82e9SRob Clark 5364c28c82e9SRob Clark #define REG_A6XX_PC_VSTREAM_CONTROL 0x00009e11 5365c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_UNK0__MASK 0x0000ffff 5366c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT 0 5367c28c82e9SRob Clark static inline uint32_t A6XX_PC_VSTREAM_CONTROL_UNK0(uint32_t val) 5368c28c82e9SRob Clark { 5369c28c82e9SRob Clark return ((val) << A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT) & A6XX_PC_VSTREAM_CONTROL_UNK0__MASK; 5370c28c82e9SRob Clark } 5371c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK 0x003f0000 5372c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT 16 5373c28c82e9SRob Clark static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_SIZE(uint32_t val) 5374c28c82e9SRob Clark { 5375c28c82e9SRob Clark return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK; 5376c28c82e9SRob Clark } 5377c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK 0x07c00000 5378c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT 22 5379c28c82e9SRob Clark static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_N(uint32_t val) 5380c28c82e9SRob Clark { 5381c28c82e9SRob Clark return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK; 5382c28c82e9SRob Clark } 5383c28c82e9SRob Clark 5384c28c82e9SRob Clark #define REG_A6XX_PC_BIN_PRIM_STRM 0x00009e12 5385c28c82e9SRob Clark #define A6XX_PC_BIN_PRIM_STRM__MASK 0xffffffff 5386c28c82e9SRob Clark #define A6XX_PC_BIN_PRIM_STRM__SHIFT 0 5387c28c82e9SRob Clark static inline uint32_t A6XX_PC_BIN_PRIM_STRM(uint32_t val) 5388c28c82e9SRob Clark { 5389c28c82e9SRob Clark return ((val) << A6XX_PC_BIN_PRIM_STRM__SHIFT) & A6XX_PC_BIN_PRIM_STRM__MASK; 5390c28c82e9SRob Clark } 5391c28c82e9SRob Clark 5392c28c82e9SRob Clark #define REG_A6XX_PC_BIN_DRAW_STRM 0x00009e14 5393c28c82e9SRob Clark #define A6XX_PC_BIN_DRAW_STRM__MASK 0xffffffff 5394c28c82e9SRob Clark #define A6XX_PC_BIN_DRAW_STRM__SHIFT 0 5395c28c82e9SRob Clark static inline uint32_t A6XX_PC_BIN_DRAW_STRM(uint32_t val) 5396c28c82e9SRob Clark { 5397c28c82e9SRob Clark return ((val) << A6XX_PC_BIN_DRAW_STRM__SHIFT) & A6XX_PC_BIN_DRAW_STRM__MASK; 5398c28c82e9SRob Clark } 5399c28c82e9SRob Clark 5400c28c82e9SRob Clark #define REG_A6XX_PC_PERFCTR_PC_SEL_0 0x00009e34 5401c28c82e9SRob Clark 5402c28c82e9SRob Clark #define REG_A6XX_PC_PERFCTR_PC_SEL_1 0x00009e35 5403c28c82e9SRob Clark 5404c28c82e9SRob Clark #define REG_A6XX_PC_PERFCTR_PC_SEL_2 0x00009e36 5405c28c82e9SRob Clark 5406c28c82e9SRob Clark #define REG_A6XX_PC_PERFCTR_PC_SEL_3 0x00009e37 5407c28c82e9SRob Clark 5408c28c82e9SRob Clark #define REG_A6XX_PC_PERFCTR_PC_SEL_4 0x00009e38 5409c28c82e9SRob Clark 5410c28c82e9SRob Clark #define REG_A6XX_PC_PERFCTR_PC_SEL_5 0x00009e39 5411c28c82e9SRob Clark 5412c28c82e9SRob Clark #define REG_A6XX_PC_PERFCTR_PC_SEL_6 0x00009e3a 5413c28c82e9SRob Clark 5414c28c82e9SRob Clark #define REG_A6XX_PC_PERFCTR_PC_SEL_7 0x00009e3b 5415c28c82e9SRob Clark 54162d756322SRob Clark #define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72 54172d756322SRob Clark 54182d756322SRob Clark #define REG_A6XX_VFD_CONTROL_0 0x0000a000 5419c28c82e9SRob Clark #define A6XX_VFD_CONTROL_0_FETCH_CNT__MASK 0x0000003f 5420c28c82e9SRob Clark #define A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT 0 5421c28c82e9SRob Clark static inline uint32_t A6XX_VFD_CONTROL_0_FETCH_CNT(uint32_t val) 54222d756322SRob Clark { 5423c28c82e9SRob Clark return ((val) << A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT) & A6XX_VFD_CONTROL_0_FETCH_CNT__MASK; 5424c28c82e9SRob Clark } 5425c28c82e9SRob Clark #define A6XX_VFD_CONTROL_0_DECODE_CNT__MASK 0x00003f00 5426c28c82e9SRob Clark #define A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT 8 5427c28c82e9SRob Clark static inline uint32_t A6XX_VFD_CONTROL_0_DECODE_CNT(uint32_t val) 5428c28c82e9SRob Clark { 5429c28c82e9SRob Clark return ((val) << A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT) & A6XX_VFD_CONTROL_0_DECODE_CNT__MASK; 54302d756322SRob Clark } 54312d756322SRob Clark 54322d756322SRob Clark #define REG_A6XX_VFD_CONTROL_1 0x0000a001 54332d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff 54342d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0 54352d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 54362d756322SRob Clark { 54372d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VTX__MASK; 54382d756322SRob Clark } 54392d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00 54402d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4INST__SHIFT 8 54412d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 54422d756322SRob Clark { 54432d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK; 54442d756322SRob Clark } 54452d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000 54462d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16 54472d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val) 54482d756322SRob Clark { 54492d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK; 54502d756322SRob Clark } 54512d756322SRob Clark 54522d756322SRob Clark #define REG_A6XX_VFD_CONTROL_2 0x0000a002 5453c28c82e9SRob Clark #define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK 0x000000ff 5454c28c82e9SRob Clark #define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__SHIFT 0 5455c28c82e9SRob Clark static inline uint32_t A6XX_VFD_CONTROL_2_REGID_HSPATCHID(uint32_t val) 54562d756322SRob Clark { 5457c28c82e9SRob Clark return ((val) << A6XX_VFD_CONTROL_2_REGID_HSPATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK; 5458c28c82e9SRob Clark } 5459c28c82e9SRob Clark #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK 0x0000ff00 5460c28c82e9SRob Clark #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT 8 5461c28c82e9SRob Clark static inline uint32_t A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val) 5462c28c82e9SRob Clark { 5463c28c82e9SRob Clark return ((val) << A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK; 54642d756322SRob Clark } 54652d756322SRob Clark 54662d756322SRob Clark #define REG_A6XX_VFD_CONTROL_3 0x0000a003 5467c28c82e9SRob Clark #define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK 0x0000ff00 5468c28c82e9SRob Clark #define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT 8 5469c28c82e9SRob Clark static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPATCHID(uint32_t val) 54702d756322SRob Clark { 5471c28c82e9SRob Clark return ((val) << A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK; 54722d756322SRob Clark } 54732d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000 54742d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16 54752d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) 54762d756322SRob Clark { 54772d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSX__MASK; 54782d756322SRob Clark } 54792d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000 54802d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24 54812d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) 54822d756322SRob Clark { 54832d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK; 54842d756322SRob Clark } 54852d756322SRob Clark 54862d756322SRob Clark #define REG_A6XX_VFD_CONTROL_4 0x0000a004 54872d756322SRob Clark 54882d756322SRob Clark #define REG_A6XX_VFD_CONTROL_5 0x0000a005 5489c28c82e9SRob Clark #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK 0x000000ff 5490c28c82e9SRob Clark #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT 0 5491c28c82e9SRob Clark static inline uint32_t A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val) 5492c28c82e9SRob Clark { 5493c28c82e9SRob Clark return ((val) << A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT) & A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK; 5494c28c82e9SRob Clark } 54952d756322SRob Clark 54962d756322SRob Clark #define REG_A6XX_VFD_CONTROL_6 0x0000a006 5497c28c82e9SRob Clark #define A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU 0x00000001 54982d756322SRob Clark 54992d756322SRob Clark #define REG_A6XX_VFD_MODE_CNTL 0x0000a007 55002d756322SRob Clark #define A6XX_VFD_MODE_CNTL_BINNING_PASS 0x00000001 55012d756322SRob Clark 55022d756322SRob Clark #define REG_A6XX_VFD_UNKNOWN_A008 0x0000a008 55032d756322SRob Clark 5504c28c82e9SRob Clark #define REG_A6XX_VFD_ADD_OFFSET 0x0000a009 5505c28c82e9SRob Clark #define A6XX_VFD_ADD_OFFSET_VERTEX 0x00000001 5506c28c82e9SRob Clark #define A6XX_VFD_ADD_OFFSET_INSTANCE 0x00000002 5507a69c5ed2SRob Clark 55082d756322SRob Clark #define REG_A6XX_VFD_INDEX_OFFSET 0x0000a00e 55092d756322SRob Clark 55102d756322SRob Clark #define REG_A6XX_VFD_INSTANCE_START_OFFSET 0x0000a00f 55112d756322SRob Clark 55122d756322SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; } 55132d756322SRob Clark 5514c28c82e9SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; } 5515c28c82e9SRob Clark 55162d756322SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000a010 + 0x4*i0; } 55172d756322SRob Clark 55182d756322SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000a011 + 0x4*i0; } 55192d756322SRob Clark 55202d756322SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; } 55212d756322SRob Clark 55222d756322SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; } 55232d756322SRob Clark 55242d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; } 55252d756322SRob Clark 55262d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; } 55272d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f 55282d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_IDX__SHIFT 0 55292d756322SRob Clark static inline uint32_t A6XX_VFD_DECODE_INSTR_IDX(uint32_t val) 55302d756322SRob Clark { 55312d756322SRob Clark return ((val) << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK; 55322d756322SRob Clark } 5533c28c82e9SRob Clark #define A6XX_VFD_DECODE_INSTR_OFFSET__MASK 0x0001ffe0 5534c28c82e9SRob Clark #define A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT 5 5535c28c82e9SRob Clark static inline uint32_t A6XX_VFD_DECODE_INSTR_OFFSET(uint32_t val) 5536c28c82e9SRob Clark { 5537c28c82e9SRob Clark return ((val) << A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT) & A6XX_VFD_DECODE_INSTR_OFFSET__MASK; 5538c28c82e9SRob Clark } 55392d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_INSTANCED 0x00020000 55402d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000 55412d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20 5542c28c82e9SRob Clark static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_format val) 55432d756322SRob Clark { 55442d756322SRob Clark return ((val) << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK; 55452d756322SRob Clark } 55462d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000 55472d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_SWAP__SHIFT 28 55482d756322SRob Clark static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 55492d756322SRob Clark { 55502d756322SRob Clark return ((val) << A6XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A6XX_VFD_DECODE_INSTR_SWAP__MASK; 55512d756322SRob Clark } 55522d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_UNK30 0x40000000 55532d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_FLOAT 0x80000000 55542d756322SRob Clark 55552d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; } 55562d756322SRob Clark 55572d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } 55582d756322SRob Clark 55592d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } 55602d756322SRob Clark #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f 55612d756322SRob Clark #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0 55622d756322SRob Clark static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val) 55632d756322SRob Clark { 55642d756322SRob Clark return ((val) << A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK; 55652d756322SRob Clark } 55662d756322SRob Clark #define A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0 55672d756322SRob Clark #define A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4 55682d756322SRob Clark static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) 55692d756322SRob Clark { 55702d756322SRob Clark return ((val) << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK; 55712d756322SRob Clark } 55722d756322SRob Clark 55732d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_A0F8 0x0000a0f8 55742d756322SRob Clark 5575c28c82e9SRob Clark #define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800 5576c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 5577c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 5578c28c82e9SRob Clark static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 55792d756322SRob Clark { 5580c28c82e9SRob Clark return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 5581c28c82e9SRob Clark } 5582c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 5583c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 5584c28c82e9SRob Clark static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 5585c28c82e9SRob Clark { 5586c28c82e9SRob Clark return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 5587c28c82e9SRob Clark } 5588c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 5589c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14 5590c28c82e9SRob Clark static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val) 5591c28c82e9SRob Clark { 5592c28c82e9SRob Clark return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK; 5593c28c82e9SRob Clark } 5594c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000 5595c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20 5596c28c82e9SRob Clark static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 5597c28c82e9SRob Clark { 5598c28c82e9SRob Clark return ((val) << A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; 5599c28c82e9SRob Clark } 5600c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_VARYING 0x00400000 5601c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_DIFF_FINE 0x00800000 5602c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x04000000 5603c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x80000000 5604c28c82e9SRob Clark 5605c28c82e9SRob Clark #define REG_A6XX_SP_VS_BRANCH_COND 0x0000a801 5606c28c82e9SRob Clark 5607c28c82e9SRob Clark #define REG_A6XX_SP_VS_PRIMITIVE_CNTL 0x0000a802 5608c28c82e9SRob Clark #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f 5609c28c82e9SRob Clark #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT 0 5610c28c82e9SRob Clark static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_OUT(uint32_t val) 5611c28c82e9SRob Clark { 5612c28c82e9SRob Clark return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK; 56132d756322SRob Clark } 56142d756322SRob Clark 56152d756322SRob Clark static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; } 56162d756322SRob Clark 56172d756322SRob Clark static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; } 56182d756322SRob Clark #define A6XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff 56192d756322SRob Clark #define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 56202d756322SRob Clark static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 56212d756322SRob Clark { 56222d756322SRob Clark return ((val) << A6XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_A_REGID__MASK; 56232d756322SRob Clark } 56242d756322SRob Clark #define A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00 56252d756322SRob Clark #define A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8 56262d756322SRob Clark static inline uint32_t A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 56272d756322SRob Clark { 56282d756322SRob Clark return ((val) << A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 56292d756322SRob Clark } 56302d756322SRob Clark #define A6XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000 56312d756322SRob Clark #define A6XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 56322d756322SRob Clark static inline uint32_t A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 56332d756322SRob Clark { 56342d756322SRob Clark return ((val) << A6XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_B_REGID__MASK; 56352d756322SRob Clark } 56362d756322SRob Clark #define A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000 56372d756322SRob Clark #define A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24 56382d756322SRob Clark static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 56392d756322SRob Clark { 56402d756322SRob Clark return ((val) << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 56412d756322SRob Clark } 56422d756322SRob Clark 56432d756322SRob Clark static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; } 56442d756322SRob Clark 56452d756322SRob Clark static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; } 56462d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 56472d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 56482d756322SRob Clark static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 56492d756322SRob Clark { 56502d756322SRob Clark return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 56512d756322SRob Clark } 56522d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 56532d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 56542d756322SRob Clark static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 56552d756322SRob Clark { 56562d756322SRob Clark return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 56572d756322SRob Clark } 56582d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 56592d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 56602d756322SRob Clark static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 56612d756322SRob Clark { 56622d756322SRob Clark return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 56632d756322SRob Clark } 56642d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 56652d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 56662d756322SRob Clark static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 56672d756322SRob Clark { 56682d756322SRob Clark return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 56692d756322SRob Clark } 56702d756322SRob Clark 5671a69c5ed2SRob Clark #define REG_A6XX_SP_UNKNOWN_A81B 0x0000a81b 5672a69c5ed2SRob Clark 56732d756322SRob Clark #define REG_A6XX_SP_VS_OBJ_START_LO 0x0000a81c 56742d756322SRob Clark 56752d756322SRob Clark #define REG_A6XX_SP_VS_OBJ_START_HI 0x0000a81d 56762d756322SRob Clark 56772d756322SRob Clark #define REG_A6XX_SP_VS_TEX_COUNT 0x0000a822 56782d756322SRob Clark 56792d756322SRob Clark #define REG_A6XX_SP_VS_CONFIG 0x0000a823 5680c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_BINDLESS_TEX 0x00000001 5681c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_BINDLESS_SAMP 0x00000002 5682c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_BINDLESS_IBO 0x00000004 5683c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_BINDLESS_UBO 0x00000008 56842d756322SRob Clark #define A6XX_SP_VS_CONFIG_ENABLED 0x00000100 56852d756322SRob Clark #define A6XX_SP_VS_CONFIG_NTEX__MASK 0x0001fe00 56862d756322SRob Clark #define A6XX_SP_VS_CONFIG_NTEX__SHIFT 9 56872d756322SRob Clark static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val) 56882d756322SRob Clark { 56892d756322SRob Clark return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK; 56902d756322SRob Clark } 5691c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_NSAMP__MASK 0x003e0000 56922d756322SRob Clark #define A6XX_SP_VS_CONFIG_NSAMP__SHIFT 17 56932d756322SRob Clark static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val) 56942d756322SRob Clark { 56952d756322SRob Clark return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK; 56962d756322SRob Clark } 5697c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_NIBO__MASK 0x3fc00000 5698c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_NIBO__SHIFT 22 5699c28c82e9SRob Clark static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val) 5700c28c82e9SRob Clark { 5701c28c82e9SRob Clark return ((val) << A6XX_SP_VS_CONFIG_NIBO__SHIFT) & A6XX_SP_VS_CONFIG_NIBO__MASK; 5702c28c82e9SRob Clark } 57032d756322SRob Clark 57042d756322SRob Clark #define REG_A6XX_SP_VS_INSTRLEN 0x0000a824 57052d756322SRob Clark 57062d756322SRob Clark #define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830 57072d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 57082d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 57092d756322SRob Clark static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 57102d756322SRob Clark { 57112d756322SRob Clark return ((val) << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 57122d756322SRob Clark } 57132d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 57142d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 57152d756322SRob Clark static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 57162d756322SRob Clark { 57172d756322SRob Clark return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 57182d756322SRob Clark } 57192d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 57202d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 14 57212d756322SRob Clark static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val) 57222d756322SRob Clark { 57232d756322SRob Clark return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK; 57242d756322SRob Clark } 57252d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK 0x00100000 57262d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT 20 57272d756322SRob Clark static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 57282d756322SRob Clark { 57292d756322SRob Clark return ((val) << A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK; 57302d756322SRob Clark } 57312d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_VARYING 0x00400000 5732c28c82e9SRob Clark #define A6XX_SP_HS_CTRL_REG0_DIFF_FINE 0x00800000 57332d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_PIXLODENABLE 0x04000000 57342d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_MERGEDREGS 0x80000000 57352d756322SRob Clark 57362d756322SRob Clark #define REG_A6XX_SP_HS_UNKNOWN_A831 0x0000a831 57372d756322SRob Clark 5738c28c82e9SRob Clark #define REG_A6XX_SP_HS_UNKNOWN_A833 0x0000a833 5739c28c82e9SRob Clark 57402d756322SRob Clark #define REG_A6XX_SP_HS_OBJ_START_LO 0x0000a834 57412d756322SRob Clark 57422d756322SRob Clark #define REG_A6XX_SP_HS_OBJ_START_HI 0x0000a835 57432d756322SRob Clark 57442d756322SRob Clark #define REG_A6XX_SP_HS_TEX_COUNT 0x0000a83a 57452d756322SRob Clark 57462d756322SRob Clark #define REG_A6XX_SP_HS_CONFIG 0x0000a83b 5747c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_BINDLESS_TEX 0x00000001 5748c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_BINDLESS_SAMP 0x00000002 5749c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_BINDLESS_IBO 0x00000004 5750c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_BINDLESS_UBO 0x00000008 57512d756322SRob Clark #define A6XX_SP_HS_CONFIG_ENABLED 0x00000100 57522d756322SRob Clark #define A6XX_SP_HS_CONFIG_NTEX__MASK 0x0001fe00 57532d756322SRob Clark #define A6XX_SP_HS_CONFIG_NTEX__SHIFT 9 57542d756322SRob Clark static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val) 57552d756322SRob Clark { 57562d756322SRob Clark return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK; 57572d756322SRob Clark } 5758c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_NSAMP__MASK 0x003e0000 57592d756322SRob Clark #define A6XX_SP_HS_CONFIG_NSAMP__SHIFT 17 57602d756322SRob Clark static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val) 57612d756322SRob Clark { 57622d756322SRob Clark return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK; 57632d756322SRob Clark } 5764c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_NIBO__MASK 0x3fc00000 5765c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_NIBO__SHIFT 22 5766c28c82e9SRob Clark static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val) 5767c28c82e9SRob Clark { 5768c28c82e9SRob Clark return ((val) << A6XX_SP_HS_CONFIG_NIBO__SHIFT) & A6XX_SP_HS_CONFIG_NIBO__MASK; 5769c28c82e9SRob Clark } 57702d756322SRob Clark 57712d756322SRob Clark #define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c 57722d756322SRob Clark 57732d756322SRob Clark #define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840 57742d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 57752d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 57762d756322SRob Clark static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 57772d756322SRob Clark { 57782d756322SRob Clark return ((val) << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 57792d756322SRob Clark } 57802d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 57812d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 57822d756322SRob Clark static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 57832d756322SRob Clark { 57842d756322SRob Clark return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 57852d756322SRob Clark } 57862d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 57872d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 14 57882d756322SRob Clark static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val) 57892d756322SRob Clark { 57902d756322SRob Clark return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK; 57912d756322SRob Clark } 57922d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK 0x00100000 57932d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT 20 57942d756322SRob Clark static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 57952d756322SRob Clark { 57962d756322SRob Clark return ((val) << A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK; 57972d756322SRob Clark } 57982d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_VARYING 0x00400000 5799c28c82e9SRob Clark #define A6XX_SP_DS_CTRL_REG0_DIFF_FINE 0x00800000 58002d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_PIXLODENABLE 0x04000000 58012d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_MERGEDREGS 0x80000000 58022d756322SRob Clark 5803c28c82e9SRob Clark #define REG_A6XX_SP_DS_PRIMITIVE_CNTL 0x0000a842 5804c28c82e9SRob Clark #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f 5805c28c82e9SRob Clark #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT 0 5806c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_OUT(uint32_t val) 5807c28c82e9SRob Clark { 5808c28c82e9SRob Clark return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK; 5809c28c82e9SRob Clark } 5810c28c82e9SRob Clark 5811c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; } 5812c28c82e9SRob Clark 5813c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000a843 + 0x1*i0; } 5814c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_A_REGID__MASK 0x000000ff 5815c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_A_REGID__SHIFT 0 5816c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_OUT_REG_A_REGID(uint32_t val) 5817c28c82e9SRob Clark { 5818c28c82e9SRob Clark return ((val) << A6XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_A_REGID__MASK; 5819c28c82e9SRob Clark } 5820c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00000f00 5821c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 8 5822c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val) 5823c28c82e9SRob Clark { 5824c28c82e9SRob Clark return ((val) << A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK; 5825c28c82e9SRob Clark } 5826c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_B_REGID__MASK 0x00ff0000 5827c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_B_REGID__SHIFT 16 5828c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_OUT_REG_B_REGID(uint32_t val) 5829c28c82e9SRob Clark { 5830c28c82e9SRob Clark return ((val) << A6XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_B_REGID__MASK; 5831c28c82e9SRob Clark } 5832c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x0f000000 5833c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 24 5834c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val) 5835c28c82e9SRob Clark { 5836c28c82e9SRob Clark return ((val) << A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK; 5837c28c82e9SRob Clark } 5838c28c82e9SRob Clark 5839c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000a853 + 0x1*i0; } 5840c28c82e9SRob Clark 5841c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000a853 + 0x1*i0; } 5842c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 5843c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0 5844c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val) 5845c28c82e9SRob Clark { 5846c28c82e9SRob Clark return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK; 5847c28c82e9SRob Clark } 5848c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 5849c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8 5850c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val) 5851c28c82e9SRob Clark { 5852c28c82e9SRob Clark return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK; 5853c28c82e9SRob Clark } 5854c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 5855c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16 5856c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val) 5857c28c82e9SRob Clark { 5858c28c82e9SRob Clark return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK; 5859c28c82e9SRob Clark } 5860c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 5861c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24 5862c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) 5863c28c82e9SRob Clark { 5864c28c82e9SRob Clark return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK; 5865c28c82e9SRob Clark } 5866c28c82e9SRob Clark 5867c28c82e9SRob Clark #define REG_A6XX_SP_DS_UNKNOWN_A85B 0x0000a85b 5868c28c82e9SRob Clark 58692d756322SRob Clark #define REG_A6XX_SP_DS_OBJ_START_LO 0x0000a85c 58702d756322SRob Clark 58712d756322SRob Clark #define REG_A6XX_SP_DS_OBJ_START_HI 0x0000a85d 58722d756322SRob Clark 58732d756322SRob Clark #define REG_A6XX_SP_DS_TEX_COUNT 0x0000a862 58742d756322SRob Clark 58752d756322SRob Clark #define REG_A6XX_SP_DS_CONFIG 0x0000a863 5876c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_BINDLESS_TEX 0x00000001 5877c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_BINDLESS_SAMP 0x00000002 5878c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_BINDLESS_IBO 0x00000004 5879c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_BINDLESS_UBO 0x00000008 58802d756322SRob Clark #define A6XX_SP_DS_CONFIG_ENABLED 0x00000100 58812d756322SRob Clark #define A6XX_SP_DS_CONFIG_NTEX__MASK 0x0001fe00 58822d756322SRob Clark #define A6XX_SP_DS_CONFIG_NTEX__SHIFT 9 58832d756322SRob Clark static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val) 58842d756322SRob Clark { 58852d756322SRob Clark return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK; 58862d756322SRob Clark } 5887c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_NSAMP__MASK 0x003e0000 58882d756322SRob Clark #define A6XX_SP_DS_CONFIG_NSAMP__SHIFT 17 58892d756322SRob Clark static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val) 58902d756322SRob Clark { 58912d756322SRob Clark return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK; 58922d756322SRob Clark } 5893c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_NIBO__MASK 0x3fc00000 5894c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_NIBO__SHIFT 22 5895c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val) 5896c28c82e9SRob Clark { 5897c28c82e9SRob Clark return ((val) << A6XX_SP_DS_CONFIG_NIBO__SHIFT) & A6XX_SP_DS_CONFIG_NIBO__MASK; 5898c28c82e9SRob Clark } 58992d756322SRob Clark 59002d756322SRob Clark #define REG_A6XX_SP_DS_INSTRLEN 0x0000a864 59012d756322SRob Clark 59022d756322SRob Clark #define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870 59032d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 59042d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 59052d756322SRob Clark static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 59062d756322SRob Clark { 59072d756322SRob Clark return ((val) << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 59082d756322SRob Clark } 59092d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 59102d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 59112d756322SRob Clark static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 59122d756322SRob Clark { 59132d756322SRob Clark return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 59142d756322SRob Clark } 59152d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 59162d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 14 59172d756322SRob Clark static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val) 59182d756322SRob Clark { 59192d756322SRob Clark return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK; 59202d756322SRob Clark } 59212d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK 0x00100000 59222d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT 20 59232d756322SRob Clark static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 59242d756322SRob Clark { 59252d756322SRob Clark return ((val) << A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK; 59262d756322SRob Clark } 59272d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_VARYING 0x00400000 5928c28c82e9SRob Clark #define A6XX_SP_GS_CTRL_REG0_DIFF_FINE 0x00800000 59292d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_PIXLODENABLE 0x04000000 59302d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_MERGEDREGS 0x80000000 59312d756322SRob Clark 5932c28c82e9SRob Clark #define REG_A6XX_SP_GS_PRIM_SIZE 0x0000a871 5933c28c82e9SRob Clark 5934c28c82e9SRob Clark #define REG_A6XX_SP_GS_BRANCH_COND 0x0000a872 5935c28c82e9SRob Clark 5936c28c82e9SRob Clark #define REG_A6XX_SP_GS_PRIMITIVE_CNTL 0x0000a873 5937c28c82e9SRob Clark #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f 5938c28c82e9SRob Clark #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT 0 5939c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_OUT(uint32_t val) 5940c28c82e9SRob Clark { 5941c28c82e9SRob Clark return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK; 5942c28c82e9SRob Clark } 5943c28c82e9SRob Clark #define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0 5944c28c82e9SRob Clark #define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6 5945c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) 5946c28c82e9SRob Clark { 5947c28c82e9SRob Clark return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; 5948c28c82e9SRob Clark } 5949c28c82e9SRob Clark 5950c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_GS_OUT(uint32_t i0) { return 0x0000a874 + 0x1*i0; } 5951c28c82e9SRob Clark 5952c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_GS_OUT_REG(uint32_t i0) { return 0x0000a874 + 0x1*i0; } 5953c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_A_REGID__MASK 0x000000ff 5954c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_A_REGID__SHIFT 0 5955c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_OUT_REG_A_REGID(uint32_t val) 5956c28c82e9SRob Clark { 5957c28c82e9SRob Clark return ((val) << A6XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_A_REGID__MASK; 5958c28c82e9SRob Clark } 5959c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00000f00 5960c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 8 5961c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val) 5962c28c82e9SRob Clark { 5963c28c82e9SRob Clark return ((val) << A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK; 5964c28c82e9SRob Clark } 5965c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_B_REGID__MASK 0x00ff0000 5966c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_B_REGID__SHIFT 16 5967c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_OUT_REG_B_REGID(uint32_t val) 5968c28c82e9SRob Clark { 5969c28c82e9SRob Clark return ((val) << A6XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_B_REGID__MASK; 5970c28c82e9SRob Clark } 5971c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x0f000000 5972c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 24 5973c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val) 5974c28c82e9SRob Clark { 5975c28c82e9SRob Clark return ((val) << A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK; 5976c28c82e9SRob Clark } 5977c28c82e9SRob Clark 5978c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_GS_VPC_DST(uint32_t i0) { return 0x0000a884 + 0x1*i0; } 5979c28c82e9SRob Clark 5980c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x0000a884 + 0x1*i0; } 5981c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 5982c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0 5983c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val) 5984c28c82e9SRob Clark { 5985c28c82e9SRob Clark return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK; 5986c28c82e9SRob Clark } 5987c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 5988c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8 5989c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val) 5990c28c82e9SRob Clark { 5991c28c82e9SRob Clark return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK; 5992c28c82e9SRob Clark } 5993c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 5994c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16 5995c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val) 5996c28c82e9SRob Clark { 5997c28c82e9SRob Clark return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK; 5998c28c82e9SRob Clark } 5999c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 6000c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24 6001c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) 6002c28c82e9SRob Clark { 6003c28c82e9SRob Clark return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK; 6004c28c82e9SRob Clark } 60052d756322SRob Clark 60062d756322SRob Clark #define REG_A6XX_SP_GS_OBJ_START_LO 0x0000a88d 60072d756322SRob Clark 60082d756322SRob Clark #define REG_A6XX_SP_GS_OBJ_START_HI 0x0000a88e 60092d756322SRob Clark 60102d756322SRob Clark #define REG_A6XX_SP_GS_TEX_COUNT 0x0000a893 60112d756322SRob Clark 60122d756322SRob Clark #define REG_A6XX_SP_GS_CONFIG 0x0000a894 6013c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_BINDLESS_TEX 0x00000001 6014c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_BINDLESS_SAMP 0x00000002 6015c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_BINDLESS_IBO 0x00000004 6016c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_BINDLESS_UBO 0x00000008 60172d756322SRob Clark #define A6XX_SP_GS_CONFIG_ENABLED 0x00000100 60182d756322SRob Clark #define A6XX_SP_GS_CONFIG_NTEX__MASK 0x0001fe00 60192d756322SRob Clark #define A6XX_SP_GS_CONFIG_NTEX__SHIFT 9 60202d756322SRob Clark static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val) 60212d756322SRob Clark { 60222d756322SRob Clark return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK; 60232d756322SRob Clark } 6024c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_NSAMP__MASK 0x003e0000 60252d756322SRob Clark #define A6XX_SP_GS_CONFIG_NSAMP__SHIFT 17 60262d756322SRob Clark static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val) 60272d756322SRob Clark { 60282d756322SRob Clark return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK; 60292d756322SRob Clark } 6030c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_NIBO__MASK 0x3fc00000 6031c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_NIBO__SHIFT 22 6032c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val) 6033c28c82e9SRob Clark { 6034c28c82e9SRob Clark return ((val) << A6XX_SP_GS_CONFIG_NIBO__SHIFT) & A6XX_SP_GS_CONFIG_NIBO__MASK; 6035c28c82e9SRob Clark } 60362d756322SRob Clark 60372d756322SRob Clark #define REG_A6XX_SP_GS_INSTRLEN 0x0000a895 60382d756322SRob Clark 60392d756322SRob Clark #define REG_A6XX_SP_VS_TEX_SAMP_LO 0x0000a8a0 60402d756322SRob Clark 60412d756322SRob Clark #define REG_A6XX_SP_VS_TEX_SAMP_HI 0x0000a8a1 60422d756322SRob Clark 60432d756322SRob Clark #define REG_A6XX_SP_HS_TEX_SAMP_LO 0x0000a8a2 60442d756322SRob Clark 60452d756322SRob Clark #define REG_A6XX_SP_HS_TEX_SAMP_HI 0x0000a8a3 60462d756322SRob Clark 60472d756322SRob Clark #define REG_A6XX_SP_DS_TEX_SAMP_LO 0x0000a8a4 60482d756322SRob Clark 60492d756322SRob Clark #define REG_A6XX_SP_DS_TEX_SAMP_HI 0x0000a8a5 60502d756322SRob Clark 60512d756322SRob Clark #define REG_A6XX_SP_GS_TEX_SAMP_LO 0x0000a8a6 60522d756322SRob Clark 60532d756322SRob Clark #define REG_A6XX_SP_GS_TEX_SAMP_HI 0x0000a8a7 60542d756322SRob Clark 60552d756322SRob Clark #define REG_A6XX_SP_VS_TEX_CONST_LO 0x0000a8a8 60562d756322SRob Clark 60572d756322SRob Clark #define REG_A6XX_SP_VS_TEX_CONST_HI 0x0000a8a9 60582d756322SRob Clark 60592d756322SRob Clark #define REG_A6XX_SP_HS_TEX_CONST_LO 0x0000a8aa 60602d756322SRob Clark 60612d756322SRob Clark #define REG_A6XX_SP_HS_TEX_CONST_HI 0x0000a8ab 60622d756322SRob Clark 60632d756322SRob Clark #define REG_A6XX_SP_DS_TEX_CONST_LO 0x0000a8ac 60642d756322SRob Clark 60652d756322SRob Clark #define REG_A6XX_SP_DS_TEX_CONST_HI 0x0000a8ad 60662d756322SRob Clark 60672d756322SRob Clark #define REG_A6XX_SP_GS_TEX_CONST_LO 0x0000a8ae 60682d756322SRob Clark 60692d756322SRob Clark #define REG_A6XX_SP_GS_TEX_CONST_HI 0x0000a8af 60702d756322SRob Clark 60712d756322SRob Clark #define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980 60722d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 60732d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 60742d756322SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 60752d756322SRob Clark { 60762d756322SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 60772d756322SRob Clark } 60782d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 60792d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 60802d756322SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 60812d756322SRob Clark { 60822d756322SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 60832d756322SRob Clark } 60842d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 60852d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 14 60862d756322SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) 60872d756322SRob Clark { 60882d756322SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK; 60892d756322SRob Clark } 60902d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 60912d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 60922d756322SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 60932d756322SRob Clark { 60942d756322SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 60952d756322SRob Clark } 60962d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000 6097c28c82e9SRob Clark #define A6XX_SP_FS_CTRL_REG0_DIFF_FINE 0x00800000 60982d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000 60992d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000 61002d756322SRob Clark 6101c28c82e9SRob Clark #define REG_A6XX_SP_FS_BRANCH_COND 0x0000a981 6102c28c82e9SRob Clark 6103a69c5ed2SRob Clark #define REG_A6XX_SP_UNKNOWN_A982 0x0000a982 6104a69c5ed2SRob Clark 61052d756322SRob Clark #define REG_A6XX_SP_FS_OBJ_START_LO 0x0000a983 61062d756322SRob Clark 61072d756322SRob Clark #define REG_A6XX_SP_FS_OBJ_START_HI 0x0000a984 61082d756322SRob Clark 61092d756322SRob Clark #define REG_A6XX_SP_BLEND_CNTL 0x0000a989 61102d756322SRob Clark #define A6XX_SP_BLEND_CNTL_ENABLED 0x00000001 61112d756322SRob Clark #define A6XX_SP_BLEND_CNTL_UNK8 0x00000100 6112c28c82e9SRob Clark #define A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200 6113ccdf7e28SRob Clark #define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 61142d756322SRob Clark 61152d756322SRob Clark #define REG_A6XX_SP_SRGB_CNTL 0x0000a98a 61162d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT0 0x00000001 61172d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT1 0x00000002 61182d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT2 0x00000004 61192d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT3 0x00000008 61202d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT4 0x00000010 61212d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT5 0x00000020 61222d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT6 0x00000040 61232d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT7 0x00000080 61242d756322SRob Clark 61252d756322SRob Clark #define REG_A6XX_SP_FS_RENDER_COMPONENTS 0x0000a98b 61262d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK 0x0000000f 61272d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT 0 61282d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val) 61292d756322SRob Clark { 61302d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK; 61312d756322SRob Clark } 61322d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK 0x000000f0 61332d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT 4 61342d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val) 61352d756322SRob Clark { 61362d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK; 61372d756322SRob Clark } 61382d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK 0x00000f00 61392d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT 8 61402d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val) 61412d756322SRob Clark { 61422d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK; 61432d756322SRob Clark } 61442d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK 0x0000f000 61452d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT 12 61462d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val) 61472d756322SRob Clark { 61482d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK; 61492d756322SRob Clark } 61502d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK 0x000f0000 61512d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT 16 61522d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val) 61532d756322SRob Clark { 61542d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK; 61552d756322SRob Clark } 61562d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK 0x00f00000 61572d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT 20 61582d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val) 61592d756322SRob Clark { 61602d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK; 61612d756322SRob Clark } 61622d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK 0x0f000000 61632d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT 24 61642d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val) 61652d756322SRob Clark { 61662d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK; 61672d756322SRob Clark } 61682d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK 0xf0000000 61692d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT 28 61702d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val) 61712d756322SRob Clark { 61722d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK; 61732d756322SRob Clark } 61742d756322SRob Clark 61752d756322SRob Clark #define REG_A6XX_SP_FS_OUTPUT_CNTL0 0x0000a98c 6176c28c82e9SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001 61772d756322SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK 0x0000ff00 61782d756322SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT 8 61792d756322SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val) 61802d756322SRob Clark { 61812d756322SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK; 61822d756322SRob Clark } 6183c28c82e9SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK 0x00ff0000 6184c28c82e9SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT 16 6185c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(uint32_t val) 6186c28c82e9SRob Clark { 6187c28c82e9SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK; 6188c28c82e9SRob Clark } 6189c28c82e9SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK 0xff000000 6190c28c82e9SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT 24 6191c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(uint32_t val) 6192c28c82e9SRob Clark { 6193c28c82e9SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK; 6194c28c82e9SRob Clark } 61952d756322SRob Clark 61962d756322SRob Clark #define REG_A6XX_SP_FS_OUTPUT_CNTL1 0x0000a98d 61972d756322SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f 61982d756322SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT 0 61992d756322SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val) 62002d756322SRob Clark { 62012d756322SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK; 62022d756322SRob Clark } 62032d756322SRob Clark 62042d756322SRob Clark static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; } 62052d756322SRob Clark 62062d756322SRob Clark static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; } 62072d756322SRob Clark #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff 62082d756322SRob Clark #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0 6209c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val) 62102d756322SRob Clark { 62112d756322SRob Clark return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK; 62122d756322SRob Clark } 62132d756322SRob Clark #define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100 62142d756322SRob Clark #define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200 6215a69c5ed2SRob Clark 6216c28c82e9SRob Clark #define REG_A6XX_SP_FS_PREFETCH_CNTL 0x0000a99e 6217c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK 0x00000007 6218c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT 0 6219c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_COUNT(uint32_t val) 6220c28c82e9SRob Clark { 6221c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK; 6222c28c82e9SRob Clark } 6223c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_UNK3 0x00000008 6224c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK 0x00000ff0 6225c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT 4 6226c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK4(uint32_t val) 6227c28c82e9SRob Clark { 6228c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK; 6229c28c82e9SRob Clark } 6230c28c82e9SRob Clark 6231c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_FS_PREFETCH(uint32_t i0) { return 0x0000a99f + 0x1*i0; } 6232c28c82e9SRob Clark 6233c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; } 6234c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_SRC__MASK 0x0000007f 6235c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT 0 6236c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val) 6237c28c82e9SRob Clark { 6238c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SRC__MASK; 6239c28c82e9SRob Clark } 6240c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK 0x00000780 6241c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT 7 6242c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val) 6243c28c82e9SRob Clark { 6244c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK; 6245c28c82e9SRob Clark } 6246c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK 0x0000f800 6247c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT 11 6248c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val) 6249c28c82e9SRob Clark { 6250c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK; 6251c28c82e9SRob Clark } 6252c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_DST__MASK 0x003f0000 6253c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT 16 6254c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_DST(uint32_t val) 6255c28c82e9SRob Clark { 6256c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_DST__MASK; 6257c28c82e9SRob Clark } 6258c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK 0x03c00000 6259c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT 22 6260c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val) 6261c28c82e9SRob Clark { 6262c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK; 6263c28c82e9SRob Clark } 6264c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_HALF 0x04000000 6265c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_CMD__MASK 0xf8000000 6266c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT 27 6267c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_CMD(uint32_t val) 6268c28c82e9SRob Clark { 6269c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_CMD__MASK; 6270c28c82e9SRob Clark } 6271c28c82e9SRob Clark 6272c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; } 6273c28c82e9SRob Clark 6274c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; } 6275c28c82e9SRob Clark #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK 0x000000ff 6276c28c82e9SRob Clark #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT 0 6277c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val) 6278c28c82e9SRob Clark { 6279c28c82e9SRob Clark return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK; 6280c28c82e9SRob Clark } 6281c28c82e9SRob Clark #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK 0x00ff0000 6282c28c82e9SRob Clark #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT 16 6283c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val) 6284c28c82e9SRob Clark { 6285c28c82e9SRob Clark return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK; 6286c28c82e9SRob Clark } 62872d756322SRob Clark 62882d756322SRob Clark #define REG_A6XX_SP_FS_TEX_COUNT 0x0000a9a7 62892d756322SRob Clark 62902d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8 62912d756322SRob Clark 6292c28c82e9SRob Clark #define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1 6293c28c82e9SRob Clark #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__MASK 0x00000001 6294c28c82e9SRob Clark #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__SHIFT 0 6295c28c82e9SRob Clark static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K(uint32_t val) 6296c28c82e9SRob Clark { 6297c28c82e9SRob Clark return ((val) << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE_2K__MASK; 6298c28c82e9SRob Clark } 6299c28c82e9SRob Clark 6300c28c82e9SRob Clark #define REG_A6XX_SP_CS_UNKNOWN_A9B3 0x0000a9b3 6301c28c82e9SRob Clark 6302c28c82e9SRob Clark #define REG_A6XX_SP_CS_TEX_COUNT 0x0000a9ba 6303c28c82e9SRob Clark 63042d756322SRob Clark #define REG_A6XX_SP_FS_TEX_SAMP_LO 0x0000a9e0 63052d756322SRob Clark 63062d756322SRob Clark #define REG_A6XX_SP_FS_TEX_SAMP_HI 0x0000a9e1 63072d756322SRob Clark 63082d756322SRob Clark #define REG_A6XX_SP_CS_TEX_SAMP_LO 0x0000a9e2 63092d756322SRob Clark 63102d756322SRob Clark #define REG_A6XX_SP_CS_TEX_SAMP_HI 0x0000a9e3 63112d756322SRob Clark 63122d756322SRob Clark #define REG_A6XX_SP_FS_TEX_CONST_LO 0x0000a9e4 63132d756322SRob Clark 63142d756322SRob Clark #define REG_A6XX_SP_FS_TEX_CONST_HI 0x0000a9e5 63152d756322SRob Clark 63162d756322SRob Clark #define REG_A6XX_SP_CS_TEX_CONST_LO 0x0000a9e6 63172d756322SRob Clark 63182d756322SRob Clark #define REG_A6XX_SP_CS_TEX_CONST_HI 0x0000a9e7 63192d756322SRob Clark 6320c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; } 6321c28c82e9SRob Clark 6322c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; } 6323c28c82e9SRob Clark 63242d756322SRob Clark static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; } 63252d756322SRob Clark 63262d756322SRob Clark static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; } 63272d756322SRob Clark #define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff 63282d756322SRob Clark #define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0 63292d756322SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) 63302d756322SRob Clark { 63312d756322SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK; 63322d756322SRob Clark } 63332d756322SRob Clark #define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100 63342d756322SRob Clark 63352d756322SRob Clark #define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0 63362d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 63372d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 63382d756322SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 63392d756322SRob Clark { 63402d756322SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 63412d756322SRob Clark } 63422d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 63432d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 63442d756322SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 63452d756322SRob Clark { 63462d756322SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 63472d756322SRob Clark } 63482d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 63492d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 14 63502d756322SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val) 63512d756322SRob Clark { 63522d756322SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK; 63532d756322SRob Clark } 63542d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000 63552d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20 63562d756322SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 63572d756322SRob Clark { 63582d756322SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK; 63592d756322SRob Clark } 63602d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_VARYING 0x00400000 6361c28c82e9SRob Clark #define A6XX_SP_CS_CTRL_REG0_DIFF_FINE 0x00800000 63622d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x04000000 63632d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000 63642d756322SRob Clark 63652d756322SRob Clark #define REG_A6XX_SP_CS_OBJ_START_LO 0x0000a9b4 63662d756322SRob Clark 63672d756322SRob Clark #define REG_A6XX_SP_CS_OBJ_START_HI 0x0000a9b5 63682d756322SRob Clark 6369c28c82e9SRob Clark #define REG_A6XX_SP_CS_CONFIG 0x0000a9bb 6370c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_BINDLESS_TEX 0x00000001 6371c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_BINDLESS_SAMP 0x00000002 6372c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_BINDLESS_IBO 0x00000004 6373c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_BINDLESS_UBO 0x00000008 6374c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_ENABLED 0x00000100 6375c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_NTEX__MASK 0x0001fe00 6376c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_NTEX__SHIFT 9 6377c28c82e9SRob Clark static inline uint32_t A6XX_SP_CS_CONFIG_NTEX(uint32_t val) 6378c28c82e9SRob Clark { 6379c28c82e9SRob Clark return ((val) << A6XX_SP_CS_CONFIG_NTEX__SHIFT) & A6XX_SP_CS_CONFIG_NTEX__MASK; 6380c28c82e9SRob Clark } 6381c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_NSAMP__MASK 0x003e0000 6382c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_NSAMP__SHIFT 17 6383c28c82e9SRob Clark static inline uint32_t A6XX_SP_CS_CONFIG_NSAMP(uint32_t val) 6384c28c82e9SRob Clark { 6385c28c82e9SRob Clark return ((val) << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK; 6386c28c82e9SRob Clark } 6387c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_NIBO__MASK 0x3fc00000 6388c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_NIBO__SHIFT 22 6389c28c82e9SRob Clark static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val) 6390c28c82e9SRob Clark { 6391c28c82e9SRob Clark return ((val) << A6XX_SP_CS_CONFIG_NIBO__SHIFT) & A6XX_SP_CS_CONFIG_NIBO__MASK; 6392c28c82e9SRob Clark } 6393c28c82e9SRob Clark 63942d756322SRob Clark #define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc 63952d756322SRob Clark 6396c28c82e9SRob Clark #define REG_A6XX_SP_CS_IBO_LO 0x0000a9f2 6397c28c82e9SRob Clark 6398c28c82e9SRob Clark #define REG_A6XX_SP_CS_IBO_HI 0x0000a9f3 6399c28c82e9SRob Clark 6400c28c82e9SRob Clark #define REG_A6XX_SP_CS_IBO_COUNT 0x0000aa00 6401c28c82e9SRob Clark 64022d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_AB00 0x0000ab00 64032d756322SRob Clark 64042d756322SRob Clark #define REG_A6XX_SP_FS_CONFIG 0x0000ab04 6405c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_BINDLESS_TEX 0x00000001 6406c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_BINDLESS_SAMP 0x00000002 6407c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_BINDLESS_IBO 0x00000004 6408c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_BINDLESS_UBO 0x00000008 64092d756322SRob Clark #define A6XX_SP_FS_CONFIG_ENABLED 0x00000100 64102d756322SRob Clark #define A6XX_SP_FS_CONFIG_NTEX__MASK 0x0001fe00 64112d756322SRob Clark #define A6XX_SP_FS_CONFIG_NTEX__SHIFT 9 64122d756322SRob Clark static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val) 64132d756322SRob Clark { 64142d756322SRob Clark return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK; 64152d756322SRob Clark } 6416c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_NSAMP__MASK 0x003e0000 64172d756322SRob Clark #define A6XX_SP_FS_CONFIG_NSAMP__SHIFT 17 64182d756322SRob Clark static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val) 64192d756322SRob Clark { 64202d756322SRob Clark return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK; 64212d756322SRob Clark } 6422c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_NIBO__MASK 0x3fc00000 6423c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_NIBO__SHIFT 22 6424c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val) 6425c28c82e9SRob Clark { 6426c28c82e9SRob Clark return ((val) << A6XX_SP_FS_CONFIG_NIBO__SHIFT) & A6XX_SP_FS_CONFIG_NIBO__MASK; 6427c28c82e9SRob Clark } 64282d756322SRob Clark 64292d756322SRob Clark #define REG_A6XX_SP_FS_INSTRLEN 0x0000ab05 64302d756322SRob Clark 6431c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_BINDLESS_BASE(uint32_t i0) { return 0x0000ab10 + 0x2*i0; } 6432a69c5ed2SRob Clark 6433c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; } 6434c28c82e9SRob Clark 6435c28c82e9SRob Clark #define REG_A6XX_SP_IBO_LO 0x0000ab1a 6436c28c82e9SRob Clark 6437c28c82e9SRob Clark #define REG_A6XX_SP_IBO_HI 0x0000ab1b 6438c28c82e9SRob Clark 6439c28c82e9SRob Clark #define REG_A6XX_SP_IBO_COUNT 0x0000ab20 6440c28c82e9SRob Clark 6441c28c82e9SRob Clark #define REG_A6XX_SP_2D_DST_FORMAT 0x0000acc0 6442c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_NORM 0x00000001 6443c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_SINT 0x00000002 6444c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_UINT 0x00000004 6445c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK 0x000007f8 6446c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT 3 6447c28c82e9SRob Clark static inline uint32_t A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val) 6448c28c82e9SRob Clark { 6449c28c82e9SRob Clark return ((val) << A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT) & A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK; 6450c28c82e9SRob Clark } 6451c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_SRGB 0x00000800 6452c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_MASK__MASK 0x0000f000 6453c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_MASK__SHIFT 12 6454c28c82e9SRob Clark static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val) 6455c28c82e9SRob Clark { 6456c28c82e9SRob Clark return ((val) << A6XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A6XX_SP_2D_DST_FORMAT_MASK__MASK; 6457c28c82e9SRob Clark } 6458ccdf7e28SRob Clark 64592d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_AE00 0x0000ae00 64602d756322SRob Clark 6461a69c5ed2SRob Clark #define REG_A6XX_SP_UNKNOWN_AE03 0x0000ae03 6462a69c5ed2SRob Clark 64632d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_AE04 0x0000ae04 64642d756322SRob Clark 64652d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_AE0F 0x0000ae0f 64662d756322SRob Clark 6467c28c82e9SRob Clark #define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR 0x0000b180 6468c28c82e9SRob Clark 64692d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_B182 0x0000b182 64702d756322SRob Clark 6471a69c5ed2SRob Clark #define REG_A6XX_SP_UNKNOWN_B183 0x0000b183 6472a69c5ed2SRob Clark 64732d756322SRob Clark #define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300 64742d756322SRob Clark #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 64752d756322SRob Clark #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 64762d756322SRob Clark static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 64772d756322SRob Clark { 64782d756322SRob Clark return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK; 64792d756322SRob Clark } 64802d756322SRob Clark 64812d756322SRob Clark #define REG_A6XX_SP_TP_DEST_MSAA_CNTL 0x0000b301 64822d756322SRob Clark #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 64832d756322SRob Clark #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 64842d756322SRob Clark static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 64852d756322SRob Clark { 64862d756322SRob Clark return ((val) << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK; 64872d756322SRob Clark } 64882d756322SRob Clark #define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 64892d756322SRob Clark 6490c28c82e9SRob Clark #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR 0x0000b302 6491c28c82e9SRob Clark 64922d756322SRob Clark #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO 0x0000b302 64932d756322SRob Clark 64942d756322SRob Clark #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_HI 0x0000b303 64952d756322SRob Clark 6496c28c82e9SRob Clark #define REG_A6XX_SP_TP_SAMPLE_CONFIG 0x0000b304 6497c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_CONFIG_UNK0 0x00000001 6498c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002 6499c28c82e9SRob Clark 6500c28c82e9SRob Clark #define REG_A6XX_SP_TP_SAMPLE_LOCATION_0 0x0000b305 6501c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f 6502c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 6503c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) 6504c28c82e9SRob Clark { 6505c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; 6506c28c82e9SRob Clark } 6507c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 6508c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 6509c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) 6510c28c82e9SRob Clark { 6511c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; 6512c28c82e9SRob Clark } 6513c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 6514c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 6515c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) 6516c28c82e9SRob Clark { 6517c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; 6518c28c82e9SRob Clark } 6519c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 6520c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 6521c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) 6522c28c82e9SRob Clark { 6523c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; 6524c28c82e9SRob Clark } 6525c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 6526c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 6527c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) 6528c28c82e9SRob Clark { 6529c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; 6530c28c82e9SRob Clark } 6531c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 6532c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 6533c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) 6534c28c82e9SRob Clark { 6535c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; 6536c28c82e9SRob Clark } 6537c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 6538c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 6539c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) 6540c28c82e9SRob Clark { 6541c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; 6542c28c82e9SRob Clark } 6543c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 6544c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 6545c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) 6546c28c82e9SRob Clark { 6547c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; 6548c28c82e9SRob Clark } 6549c28c82e9SRob Clark 6550c28c82e9SRob Clark #define REG_A6XX_SP_TP_SAMPLE_LOCATION_1 0x0000b306 6551c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f 6552c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 6553c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) 6554c28c82e9SRob Clark { 6555c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; 6556c28c82e9SRob Clark } 6557c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 6558c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 6559c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) 6560c28c82e9SRob Clark { 6561c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; 6562c28c82e9SRob Clark } 6563c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 6564c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 6565c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) 6566c28c82e9SRob Clark { 6567c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; 6568c28c82e9SRob Clark } 6569c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 6570c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 6571c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) 6572c28c82e9SRob Clark { 6573c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; 6574c28c82e9SRob Clark } 6575c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 6576c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 6577c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) 6578c28c82e9SRob Clark { 6579c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; 6580c28c82e9SRob Clark } 6581c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 6582c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 6583c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) 6584c28c82e9SRob Clark { 6585c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; 6586c28c82e9SRob Clark } 6587c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 6588c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 6589c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) 6590c28c82e9SRob Clark { 6591c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; 6592c28c82e9SRob Clark } 6593c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 6594c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 6595c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) 6596c28c82e9SRob Clark { 6597c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; 6598c28c82e9SRob Clark } 65992d756322SRob Clark 6600a69c5ed2SRob Clark #define REG_A6XX_SP_TP_UNKNOWN_B309 0x0000b309 6601a69c5ed2SRob Clark 66022d756322SRob Clark #define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0 66032d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff 66042d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 6605c28c82e9SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val) 66062d756322SRob Clark { 66072d756322SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK; 66082d756322SRob Clark } 66092d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300 66102d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT 8 66112d756322SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val) 66122d756322SRob Clark { 66132d756322SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK; 66142d756322SRob Clark } 66152d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00 66162d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10 66172d756322SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) 66182d756322SRob Clark { 66192d756322SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK; 66202d756322SRob Clark } 66212d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000 6622c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_SRGB 0x00002000 6623c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK 0x0000c000 6624c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT 14 6625c28c82e9SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val) 6626c28c82e9SRob Clark { 6627c28c82e9SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK; 6628c28c82e9SRob Clark } 6629ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000 6630c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE 0x00040000 6631c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK20 0x00100000 6632c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK22 0x00400000 6633ccdf7e28SRob Clark 6634ccdf7e28SRob Clark #define REG_A6XX_SP_PS_2D_SRC_SIZE 0x0000b4c1 6635ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff 6636ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT 0 6637ccdf7e28SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val) 6638ccdf7e28SRob Clark { 6639ccdf7e28SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK; 6640ccdf7e28SRob Clark } 6641ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK 0x3fff8000 6642ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT 15 6643ccdf7e28SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val) 6644ccdf7e28SRob Clark { 6645ccdf7e28SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK; 6646ccdf7e28SRob Clark } 66472d756322SRob Clark 66482d756322SRob Clark #define REG_A6XX_SP_PS_2D_SRC_LO 0x0000b4c2 66492d756322SRob Clark 66502d756322SRob Clark #define REG_A6XX_SP_PS_2D_SRC_HI 0x0000b4c3 66512d756322SRob Clark 6652c28c82e9SRob Clark #define REG_A6XX_SP_PS_2D_SRC 0x0000b4c2 6653c28c82e9SRob Clark 6654ccdf7e28SRob Clark #define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4 6655ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x01fffe00 6656ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9 6657ccdf7e28SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val) 6658ccdf7e28SRob Clark { 6659ccdf7e28SRob Clark return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK; 6660ccdf7e28SRob Clark } 6661ccdf7e28SRob Clark 66622d756322SRob Clark #define REG_A6XX_SP_PS_2D_SRC_FLAGS_LO 0x0000b4ca 66632d756322SRob Clark 66642d756322SRob Clark #define REG_A6XX_SP_PS_2D_SRC_FLAGS_HI 0x0000b4cb 66652d756322SRob Clark 6666c28c82e9SRob Clark #define REG_A6XX_SP_PS_2D_SRC_FLAGS 0x0000b4ca 6667c28c82e9SRob Clark 6668c28c82e9SRob Clark #define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b4cc 6669c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__MASK 0x000007ff 6670c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__SHIFT 0 6671c28c82e9SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH(uint32_t val) 6672c28c82e9SRob Clark { 6673c28c82e9SRob Clark return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH_PITCH__MASK; 6674c28c82e9SRob Clark } 6675c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__MASK 0x003ff800 6676c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__SHIFT 11 6677c28c82e9SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH(uint32_t val) 6678c28c82e9SRob Clark { 6679c28c82e9SRob Clark return ((val >> 7) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH_ARRAY_PITCH__MASK; 6680c28c82e9SRob Clark } 6681c28c82e9SRob Clark 66822d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_B600 0x0000b600 66832d756322SRob Clark 66842d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_B605 0x0000b605 66852d756322SRob Clark 66862d756322SRob Clark #define REG_A6XX_HLSQ_VS_CNTL 0x0000b800 66872d756322SRob Clark #define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff 66882d756322SRob Clark #define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0 66892d756322SRob Clark static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val) 66902d756322SRob Clark { 66912d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK; 66922d756322SRob Clark } 6693c28c82e9SRob Clark #define A6XX_HLSQ_VS_CNTL_ENABLED 0x00000100 66942d756322SRob Clark 66952d756322SRob Clark #define REG_A6XX_HLSQ_HS_CNTL 0x0000b801 66962d756322SRob Clark #define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff 66972d756322SRob Clark #define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0 66982d756322SRob Clark static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val) 66992d756322SRob Clark { 67002d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK; 67012d756322SRob Clark } 6702c28c82e9SRob Clark #define A6XX_HLSQ_HS_CNTL_ENABLED 0x00000100 67032d756322SRob Clark 67042d756322SRob Clark #define REG_A6XX_HLSQ_DS_CNTL 0x0000b802 67052d756322SRob Clark #define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff 67062d756322SRob Clark #define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0 67072d756322SRob Clark static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val) 67082d756322SRob Clark { 67092d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK; 67102d756322SRob Clark } 6711c28c82e9SRob Clark #define A6XX_HLSQ_DS_CNTL_ENABLED 0x00000100 67122d756322SRob Clark 67132d756322SRob Clark #define REG_A6XX_HLSQ_GS_CNTL 0x0000b803 67142d756322SRob Clark #define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff 67152d756322SRob Clark #define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0 67162d756322SRob Clark static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val) 67172d756322SRob Clark { 67182d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK; 67192d756322SRob Clark } 6720c28c82e9SRob Clark #define A6XX_HLSQ_GS_CNTL_ENABLED 0x00000100 6721c28c82e9SRob Clark 6722c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD 0x0000b820 6723c28c82e9SRob Clark 6724c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR 0x0000b821 6725c28c82e9SRob Clark 6726c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA 0x0000b823 67272d756322SRob Clark 6728a69c5ed2SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_B980 0x0000b980 6729a69c5ed2SRob Clark 67302d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982 67312d756322SRob Clark 67322d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_2_REG 0x0000b983 67332d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff 67342d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0 67352d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) 67362d756322SRob Clark { 67372d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; 67382d756322SRob Clark } 67392d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00 67402d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8 67412d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) 67422d756322SRob Clark { 67432d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK; 67442d756322SRob Clark } 67452d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000 67462d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16 67472d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) 67482d756322SRob Clark { 67492d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK; 67502d756322SRob Clark } 6751c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK 0xff000000 6752c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT 24 6753c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SIZE(uint32_t val) 6754c28c82e9SRob Clark { 6755c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK; 6756c28c82e9SRob Clark } 67572d756322SRob Clark 67582d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_3_REG 0x0000b984 6759c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff 6760c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0 6761c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val) 67622d756322SRob Clark { 6763c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK; 6764c28c82e9SRob Clark } 6765c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00 6766c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8 6767c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val) 6768c28c82e9SRob Clark { 6769c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK; 6770c28c82e9SRob Clark } 6771c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000 6772c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16 6773c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val) 6774c28c82e9SRob Clark { 6775c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK; 6776c28c82e9SRob Clark } 6777c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000 6778c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24 6779c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) 6780c28c82e9SRob Clark { 6781c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK; 67822d756322SRob Clark } 67832d756322SRob Clark 67842d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_4_REG 0x0000b985 6785c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff 6786c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0 6787c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val) 6788c28c82e9SRob Clark { 6789c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK; 6790c28c82e9SRob Clark } 6791c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00 6792c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8 6793c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val) 6794c28c82e9SRob Clark { 6795c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK; 6796c28c82e9SRob Clark } 67972d756322SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000 67982d756322SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16 67992d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) 68002d756322SRob Clark { 68012d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK; 68022d756322SRob Clark } 68032d756322SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000 68042d756322SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24 68052d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) 68062d756322SRob Clark { 68072d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; 68082d756322SRob Clark } 68092d756322SRob Clark 68102d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986 68112d756322SRob Clark 6812c28c82e9SRob Clark #define REG_A6XX_HLSQ_CS_CNTL 0x0000b987 6813c28c82e9SRob Clark #define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff 6814c28c82e9SRob Clark #define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0 6815c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val) 6816c28c82e9SRob Clark { 6817c28c82e9SRob Clark return ((val >> 2) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK; 6818c28c82e9SRob Clark } 6819c28c82e9SRob Clark #define A6XX_HLSQ_CS_CNTL_ENABLED 0x00000100 6820c28c82e9SRob Clark 68212d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_0 0x0000b990 68222d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003 68232d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0 68242d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) 68252d756322SRob Clark { 68262d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK; 68272d756322SRob Clark } 68282d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc 68292d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2 68302d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) 68312d756322SRob Clark { 68322d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK; 68332d756322SRob Clark } 68342d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000 68352d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12 68362d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) 68372d756322SRob Clark { 68382d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK; 68392d756322SRob Clark } 68402d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000 68412d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22 68422d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) 68432d756322SRob Clark { 68442d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK; 68452d756322SRob Clark } 68462d756322SRob Clark 68472d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_1 0x0000b991 68482d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff 68492d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0 68502d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val) 68512d756322SRob Clark { 68522d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK; 68532d756322SRob Clark } 68542d756322SRob Clark 68552d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_2 0x0000b992 68562d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff 68572d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0 68582d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val) 68592d756322SRob Clark { 68602d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK; 68612d756322SRob Clark } 68622d756322SRob Clark 68632d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_3 0x0000b993 68642d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff 68652d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0 68662d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val) 68672d756322SRob Clark { 68682d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK; 68692d756322SRob Clark } 68702d756322SRob Clark 68712d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_4 0x0000b994 68722d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff 68732d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0 68742d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val) 68752d756322SRob Clark { 68762d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK; 68772d756322SRob Clark } 68782d756322SRob Clark 68792d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_5 0x0000b995 68802d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff 68812d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0 68822d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val) 68832d756322SRob Clark { 68842d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK; 68852d756322SRob Clark } 68862d756322SRob Clark 68872d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_6 0x0000b996 68882d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff 68892d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0 68902d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val) 68912d756322SRob Clark { 68922d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK; 68932d756322SRob Clark } 68942d756322SRob Clark 68952d756322SRob Clark #define REG_A6XX_HLSQ_CS_CNTL_0 0x0000b997 68962d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff 68972d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0 68982d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val) 68992d756322SRob Clark { 69002d756322SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK; 69012d756322SRob Clark } 69022d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_UNK0__MASK 0x0000ff00 69032d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT 8 69042d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val) 69052d756322SRob Clark { 69062d756322SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK0__MASK; 69072d756322SRob Clark } 69082d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_UNK1__MASK 0x00ff0000 69092d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT 16 69102d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val) 69112d756322SRob Clark { 69122d756322SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK1__MASK; 69132d756322SRob Clark } 69142d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000 69152d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24 69162d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) 69172d756322SRob Clark { 69182d756322SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK; 69192d756322SRob Clark } 69202d756322SRob Clark 6921c28c82e9SRob Clark #define REG_A6XX_HLSQ_CS_UNKNOWN_B998 0x0000b998 6922c28c82e9SRob Clark 69232d756322SRob Clark #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X 0x0000b999 69242d756322SRob Clark 69252d756322SRob Clark #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000b99a 69262d756322SRob Clark 69272d756322SRob Clark #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000b99b 69282d756322SRob Clark 6929c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD 0x0000b9a0 6930c28c82e9SRob Clark 6931c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR 0x0000b9a1 6932c28c82e9SRob Clark 6933c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA 0x0000b9a3 6934c28c82e9SRob Clark 6935c28c82e9SRob Clark static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; } 6936c28c82e9SRob Clark 6937c28c82e9SRob Clark static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; } 6938c28c82e9SRob Clark 6939c28c82e9SRob Clark #define REG_A6XX_HLSQ_DRAW_CMD 0x0000bb00 6940c28c82e9SRob Clark #define A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK 0x000000ff 6941c28c82e9SRob Clark #define A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT 0 6942c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_DRAW_CMD_STATE_ID(uint32_t val) 6943c28c82e9SRob Clark { 6944c28c82e9SRob Clark return ((val) << A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK; 6945c28c82e9SRob Clark } 6946c28c82e9SRob Clark 6947c28c82e9SRob Clark #define REG_A6XX_HLSQ_DISPATCH_CMD 0x0000bb01 6948c28c82e9SRob Clark #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK 0x000000ff 6949c28c82e9SRob Clark #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT 0 6950c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_DISPATCH_CMD_STATE_ID(uint32_t val) 6951c28c82e9SRob Clark { 6952c28c82e9SRob Clark return ((val) << A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK; 6953c28c82e9SRob Clark } 6954c28c82e9SRob Clark 6955c28c82e9SRob Clark #define REG_A6XX_HLSQ_EVENT_CMD 0x0000bb02 6956c28c82e9SRob Clark #define A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK 0x00ff0000 6957c28c82e9SRob Clark #define A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT 16 6958c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_EVENT_CMD_STATE_ID(uint32_t val) 6959c28c82e9SRob Clark { 6960c28c82e9SRob Clark return ((val) << A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK; 6961c28c82e9SRob Clark } 6962c28c82e9SRob Clark #define A6XX_HLSQ_EVENT_CMD_EVENT__MASK 0x0000007f 6963c28c82e9SRob Clark #define A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT 0 6964c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_EVENT_CMD_EVENT(enum vgt_event_type val) 6965c28c82e9SRob Clark { 6966c28c82e9SRob Clark return ((val) << A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_EVENT_CMD_EVENT__MASK; 6967c28c82e9SRob Clark } 6968c28c82e9SRob Clark 6969c28c82e9SRob Clark #define REG_A6XX_HLSQ_INVALIDATE_CMD 0x0000bb08 6970c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_VS_STATE 0x00000001 6971c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_HS_STATE 0x00000002 6972c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_DS_STATE 0x00000004 6973c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_GS_STATE 0x00000008 6974c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_FS_STATE 0x00000010 6975c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_CS_STATE 0x00000020 6976c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_CS_IBO 0x00000040 6977c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO 0x00000080 6978c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_CS_SHARED_CONST 0x00080000 6979c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_GFX_SHARED_CONST 0x00000100 6980c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK 0x00003e00 6981c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT 9 6982c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val) 6983c28c82e9SRob Clark { 6984c28c82e9SRob Clark return ((val) << A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK; 6985c28c82e9SRob Clark } 6986c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK 0x0007c000 6987c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT 14 6988c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val) 6989c28c82e9SRob Clark { 6990c28c82e9SRob Clark return ((val) << A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK; 6991c28c82e9SRob Clark } 69922d756322SRob Clark 69932d756322SRob Clark #define REG_A6XX_HLSQ_FS_CNTL 0x0000bb10 69942d756322SRob Clark #define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff 69952d756322SRob Clark #define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0 69962d756322SRob Clark static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val) 69972d756322SRob Clark { 69982d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK; 69992d756322SRob Clark } 7000c28c82e9SRob Clark #define A6XX_HLSQ_FS_CNTL_ENABLED 0x00000100 70012d756322SRob Clark 7002c28c82e9SRob Clark #define REG_A6XX_HLSQ_SHARED_CONSTS 0x0000bb11 7003c28c82e9SRob Clark #define A6XX_HLSQ_SHARED_CONSTS_ENABLE 0x00000001 7004c28c82e9SRob Clark 7005c28c82e9SRob Clark static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE(uint32_t i0) { return 0x0000bb20 + 0x2*i0; } 7006c28c82e9SRob Clark 7007c28c82e9SRob Clark static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000bb20 + 0x2*i0; } 7008c28c82e9SRob Clark 7009c28c82e9SRob Clark #define REG_A6XX_HLSQ_2D_EVENT_CMD 0x0000bd80 7010c28c82e9SRob Clark #define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00 7011c28c82e9SRob Clark #define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT 8 7012c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_STATE_ID(uint32_t val) 7013c28c82e9SRob Clark { 7014c28c82e9SRob Clark return ((val) << A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK; 7015c28c82e9SRob Clark } 7016c28c82e9SRob Clark #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK 0x0000007f 7017c28c82e9SRob Clark #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT 0 7018c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val) 7019c28c82e9SRob Clark { 7020c28c82e9SRob Clark return ((val) << A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK; 7021c28c82e9SRob Clark } 70222d756322SRob Clark 70232d756322SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_BE00 0x0000be00 70242d756322SRob Clark 70252d756322SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_BE01 0x0000be01 70262d756322SRob Clark 70272d756322SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_BE04 0x0000be04 70282d756322SRob Clark 7029c28c82e9SRob Clark #define REG_A6XX_CP_EVENT_START 0x0000d600 7030c28c82e9SRob Clark #define A6XX_CP_EVENT_START_STATE_ID__MASK 0x000000ff 7031c28c82e9SRob Clark #define A6XX_CP_EVENT_START_STATE_ID__SHIFT 0 7032c28c82e9SRob Clark static inline uint32_t A6XX_CP_EVENT_START_STATE_ID(uint32_t val) 7033c28c82e9SRob Clark { 7034c28c82e9SRob Clark return ((val) << A6XX_CP_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_EVENT_START_STATE_ID__MASK; 7035c28c82e9SRob Clark } 7036c28c82e9SRob Clark 7037c28c82e9SRob Clark #define REG_A6XX_CP_EVENT_END 0x0000d601 7038c28c82e9SRob Clark #define A6XX_CP_EVENT_END_STATE_ID__MASK 0x000000ff 7039c28c82e9SRob Clark #define A6XX_CP_EVENT_END_STATE_ID__SHIFT 0 7040c28c82e9SRob Clark static inline uint32_t A6XX_CP_EVENT_END_STATE_ID(uint32_t val) 7041c28c82e9SRob Clark { 7042c28c82e9SRob Clark return ((val) << A6XX_CP_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_EVENT_END_STATE_ID__MASK; 7043c28c82e9SRob Clark } 7044c28c82e9SRob Clark 7045c28c82e9SRob Clark #define REG_A6XX_CP_2D_EVENT_START 0x0000d700 7046c28c82e9SRob Clark #define A6XX_CP_2D_EVENT_START_STATE_ID__MASK 0x000000ff 7047c28c82e9SRob Clark #define A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT 0 7048c28c82e9SRob Clark static inline uint32_t A6XX_CP_2D_EVENT_START_STATE_ID(uint32_t val) 7049c28c82e9SRob Clark { 7050c28c82e9SRob Clark return ((val) << A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_START_STATE_ID__MASK; 7051c28c82e9SRob Clark } 7052c28c82e9SRob Clark 7053c28c82e9SRob Clark #define REG_A6XX_CP_2D_EVENT_END 0x0000d701 7054c28c82e9SRob Clark #define A6XX_CP_2D_EVENT_END_STATE_ID__MASK 0x000000ff 7055c28c82e9SRob Clark #define A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT 0 7056c28c82e9SRob Clark static inline uint32_t A6XX_CP_2D_EVENT_END_STATE_ID(uint32_t val) 7057c28c82e9SRob Clark { 7058c28c82e9SRob Clark return ((val) << A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_END_STATE_ID__MASK; 7059c28c82e9SRob Clark } 7060c28c82e9SRob Clark 70612d756322SRob Clark #define REG_A6XX_TEX_SAMP_0 0x00000000 70622d756322SRob Clark #define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 70632d756322SRob Clark #define A6XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 70642d756322SRob Clark #define A6XX_TEX_SAMP_0_XY_MAG__SHIFT 1 70652d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val) 70662d756322SRob Clark { 70672d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_XY_MAG__SHIFT) & A6XX_TEX_SAMP_0_XY_MAG__MASK; 70682d756322SRob Clark } 70692d756322SRob Clark #define A6XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 70702d756322SRob Clark #define A6XX_TEX_SAMP_0_XY_MIN__SHIFT 3 70712d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val) 70722d756322SRob Clark { 70732d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_XY_MIN__SHIFT) & A6XX_TEX_SAMP_0_XY_MIN__MASK; 70742d756322SRob Clark } 70752d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 70762d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_S__SHIFT 5 70772d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val) 70782d756322SRob Clark { 70792d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_WRAP_S__SHIFT) & A6XX_TEX_SAMP_0_WRAP_S__MASK; 70802d756322SRob Clark } 70812d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 70822d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_T__SHIFT 8 70832d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val) 70842d756322SRob Clark { 70852d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_WRAP_T__SHIFT) & A6XX_TEX_SAMP_0_WRAP_T__MASK; 70862d756322SRob Clark } 70872d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 70882d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_R__SHIFT 11 70892d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val) 70902d756322SRob Clark { 70912d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_WRAP_R__SHIFT) & A6XX_TEX_SAMP_0_WRAP_R__MASK; 70922d756322SRob Clark } 70932d756322SRob Clark #define A6XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 70942d756322SRob Clark #define A6XX_TEX_SAMP_0_ANISO__SHIFT 14 70952d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val) 70962d756322SRob Clark { 70972d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_ANISO__SHIFT) & A6XX_TEX_SAMP_0_ANISO__MASK; 70982d756322SRob Clark } 70992d756322SRob Clark #define A6XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000 71002d756322SRob Clark #define A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19 71012d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val) 71022d756322SRob Clark { 71032d756322SRob Clark return ((((int32_t)(val * 256.0))) << A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A6XX_TEX_SAMP_0_LOD_BIAS__MASK; 71042d756322SRob Clark } 71052d756322SRob Clark 71062d756322SRob Clark #define REG_A6XX_TEX_SAMP_1 0x00000001 7107c28c82e9SRob Clark #define A6XX_TEX_SAMP_1_UNK0 0x00000001 71082d756322SRob Clark #define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e 71092d756322SRob Clark #define A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 71102d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) 71112d756322SRob Clark { 71122d756322SRob Clark return ((val) << A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK; 71132d756322SRob Clark } 71142d756322SRob Clark #define A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010 71152d756322SRob Clark #define A6XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 71162d756322SRob Clark #define A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 71172d756322SRob Clark #define A6XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 71182d756322SRob Clark #define A6XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 71192d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_1_MAX_LOD(float val) 71202d756322SRob Clark { 71212d756322SRob Clark return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK; 71222d756322SRob Clark } 71232d756322SRob Clark #define A6XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 71242d756322SRob Clark #define A6XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 71252d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_1_MIN_LOD(float val) 71262d756322SRob Clark { 71272d756322SRob Clark return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK; 71282d756322SRob Clark } 71292d756322SRob Clark 71302d756322SRob Clark #define REG_A6XX_TEX_SAMP_2 0x00000002 7131c28c82e9SRob Clark #define A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK 0x00000003 7132c28c82e9SRob Clark #define A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT 0 7133c28c82e9SRob Clark static inline uint32_t A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode val) 7134c28c82e9SRob Clark { 7135c28c82e9SRob Clark return ((val) << A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT) & A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK; 7136c28c82e9SRob Clark } 7137c28c82e9SRob Clark #define A6XX_TEX_SAMP_2_CHROMA_LINEAR 0x00000020 7138c28c82e9SRob Clark #define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xffffff80 7139c28c82e9SRob Clark #define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 7 71402d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val) 71412d756322SRob Clark { 7142c28c82e9SRob Clark return ((val >> 7) << A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK; 71432d756322SRob Clark } 71442d756322SRob Clark 71452d756322SRob Clark #define REG_A6XX_TEX_SAMP_3 0x00000003 71462d756322SRob Clark 71472d756322SRob Clark #define REG_A6XX_TEX_CONST_0 0x00000000 71482d756322SRob Clark #define A6XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003 71492d756322SRob Clark #define A6XX_TEX_CONST_0_TILE_MODE__SHIFT 0 71502d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val) 71512d756322SRob Clark { 71522d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_TILE_MODE__SHIFT) & A6XX_TEX_CONST_0_TILE_MODE__MASK; 71532d756322SRob Clark } 71542d756322SRob Clark #define A6XX_TEX_CONST_0_SRGB 0x00000004 71552d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 71562d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_X__SHIFT 4 71572d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val) 71582d756322SRob Clark { 71592d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWIZ_X__SHIFT) & A6XX_TEX_CONST_0_SWIZ_X__MASK; 71602d756322SRob Clark } 71612d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 71622d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 71632d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val) 71642d756322SRob Clark { 71652d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Y__MASK; 71662d756322SRob Clark } 71672d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 71682d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 71692d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val) 71702d756322SRob Clark { 71712d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Z__MASK; 71722d756322SRob Clark } 71732d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 71742d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_W__SHIFT 13 71752d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val) 71762d756322SRob Clark { 71772d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWIZ_W__SHIFT) & A6XX_TEX_CONST_0_SWIZ_W__MASK; 71782d756322SRob Clark } 71792d756322SRob Clark #define A6XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 71802d756322SRob Clark #define A6XX_TEX_CONST_0_MIPLVLS__SHIFT 16 71812d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val) 71822d756322SRob Clark { 71832d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK; 71842d756322SRob Clark } 7185c28c82e9SRob Clark #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X 0x00010000 7186c28c82e9SRob Clark #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y 0x00040000 7187ccdf7e28SRob Clark #define A6XX_TEX_CONST_0_SAMPLES__MASK 0x00300000 7188ccdf7e28SRob Clark #define A6XX_TEX_CONST_0_SAMPLES__SHIFT 20 7189ccdf7e28SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val) 7190ccdf7e28SRob Clark { 7191ccdf7e28SRob Clark return ((val) << A6XX_TEX_CONST_0_SAMPLES__SHIFT) & A6XX_TEX_CONST_0_SAMPLES__MASK; 7192ccdf7e28SRob Clark } 71932d756322SRob Clark #define A6XX_TEX_CONST_0_FMT__MASK 0x3fc00000 71942d756322SRob Clark #define A6XX_TEX_CONST_0_FMT__SHIFT 22 7195c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_format val) 71962d756322SRob Clark { 71972d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK; 71982d756322SRob Clark } 71992d756322SRob Clark #define A6XX_TEX_CONST_0_SWAP__MASK 0xc0000000 72002d756322SRob Clark #define A6XX_TEX_CONST_0_SWAP__SHIFT 30 72012d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val) 72022d756322SRob Clark { 72032d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWAP__SHIFT) & A6XX_TEX_CONST_0_SWAP__MASK; 72042d756322SRob Clark } 72052d756322SRob Clark 72062d756322SRob Clark #define REG_A6XX_TEX_CONST_1 0x00000001 72072d756322SRob Clark #define A6XX_TEX_CONST_1_WIDTH__MASK 0x00007fff 72082d756322SRob Clark #define A6XX_TEX_CONST_1_WIDTH__SHIFT 0 72092d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_1_WIDTH(uint32_t val) 72102d756322SRob Clark { 72112d756322SRob Clark return ((val) << A6XX_TEX_CONST_1_WIDTH__SHIFT) & A6XX_TEX_CONST_1_WIDTH__MASK; 72122d756322SRob Clark } 72132d756322SRob Clark #define A6XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000 72142d756322SRob Clark #define A6XX_TEX_CONST_1_HEIGHT__SHIFT 15 72152d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val) 72162d756322SRob Clark { 72172d756322SRob Clark return ((val) << A6XX_TEX_CONST_1_HEIGHT__SHIFT) & A6XX_TEX_CONST_1_HEIGHT__MASK; 72182d756322SRob Clark } 72192d756322SRob Clark 72202d756322SRob Clark #define REG_A6XX_TEX_CONST_2 0x00000002 7221c28c82e9SRob Clark #define A6XX_TEX_CONST_2_UNK4 0x00000010 7222c28c82e9SRob Clark #define A6XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f 7223c28c82e9SRob Clark #define A6XX_TEX_CONST_2_PITCHALIGN__SHIFT 0 7224c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_2_PITCHALIGN(uint32_t val) 72252d756322SRob Clark { 7226c28c82e9SRob Clark return ((val) << A6XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A6XX_TEX_CONST_2_PITCHALIGN__MASK; 72272d756322SRob Clark } 72282d756322SRob Clark #define A6XX_TEX_CONST_2_PITCH__MASK 0x1fffff80 72292d756322SRob Clark #define A6XX_TEX_CONST_2_PITCH__SHIFT 7 72302d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_2_PITCH(uint32_t val) 72312d756322SRob Clark { 72322d756322SRob Clark return ((val) << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK; 72332d756322SRob Clark } 72342d756322SRob Clark #define A6XX_TEX_CONST_2_TYPE__MASK 0x60000000 72352d756322SRob Clark #define A6XX_TEX_CONST_2_TYPE__SHIFT 29 72362d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val) 72372d756322SRob Clark { 72382d756322SRob Clark return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK; 72392d756322SRob Clark } 7240c28c82e9SRob Clark #define A6XX_TEX_CONST_2_UNK31 0x80000000 72412d756322SRob Clark 72422d756322SRob Clark #define REG_A6XX_TEX_CONST_3 0x00000003 72432d756322SRob Clark #define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff 72442d756322SRob Clark #define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0 72452d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) 72462d756322SRob Clark { 72472d756322SRob Clark return ((val >> 12) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK; 72482d756322SRob Clark } 7249c28c82e9SRob Clark #define A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000 7250c28c82e9SRob Clark #define A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23 7251c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val) 7252c28c82e9SRob Clark { 7253c28c82e9SRob Clark return ((val >> 12) << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK; 7254c28c82e9SRob Clark } 7255c28c82e9SRob Clark #define A6XX_TEX_CONST_3_TILE_ALL 0x08000000 72562d756322SRob Clark #define A6XX_TEX_CONST_3_FLAG 0x10000000 72572d756322SRob Clark 72582d756322SRob Clark #define REG_A6XX_TEX_CONST_4 0x00000004 72592d756322SRob Clark #define A6XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0 72602d756322SRob Clark #define A6XX_TEX_CONST_4_BASE_LO__SHIFT 5 72612d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val) 72622d756322SRob Clark { 72632d756322SRob Clark return ((val >> 5) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK; 72642d756322SRob Clark } 72652d756322SRob Clark 72662d756322SRob Clark #define REG_A6XX_TEX_CONST_5 0x00000005 72672d756322SRob Clark #define A6XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff 72682d756322SRob Clark #define A6XX_TEX_CONST_5_BASE_HI__SHIFT 0 72692d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_5_BASE_HI(uint32_t val) 72702d756322SRob Clark { 72712d756322SRob Clark return ((val) << A6XX_TEX_CONST_5_BASE_HI__SHIFT) & A6XX_TEX_CONST_5_BASE_HI__MASK; 72722d756322SRob Clark } 72732d756322SRob Clark #define A6XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000 72742d756322SRob Clark #define A6XX_TEX_CONST_5_DEPTH__SHIFT 17 72752d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_5_DEPTH(uint32_t val) 72762d756322SRob Clark { 72772d756322SRob Clark return ((val) << A6XX_TEX_CONST_5_DEPTH__SHIFT) & A6XX_TEX_CONST_5_DEPTH__MASK; 72782d756322SRob Clark } 72792d756322SRob Clark 72802d756322SRob Clark #define REG_A6XX_TEX_CONST_6 0x00000006 7281c28c82e9SRob Clark #define A6XX_TEX_CONST_6_PLANE_PITCH__MASK 0xffffff00 7282c28c82e9SRob Clark #define A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT 8 7283c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_6_PLANE_PITCH(uint32_t val) 7284c28c82e9SRob Clark { 7285c28c82e9SRob Clark return ((val) << A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT) & A6XX_TEX_CONST_6_PLANE_PITCH__MASK; 7286c28c82e9SRob Clark } 72872d756322SRob Clark 72882d756322SRob Clark #define REG_A6XX_TEX_CONST_7 0x00000007 72892d756322SRob Clark #define A6XX_TEX_CONST_7_FLAG_LO__MASK 0xffffffe0 72902d756322SRob Clark #define A6XX_TEX_CONST_7_FLAG_LO__SHIFT 5 72912d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val) 72922d756322SRob Clark { 72932d756322SRob Clark return ((val >> 5) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK; 72942d756322SRob Clark } 72952d756322SRob Clark 72962d756322SRob Clark #define REG_A6XX_TEX_CONST_8 0x00000008 7297a69c5ed2SRob Clark #define A6XX_TEX_CONST_8_FLAG_HI__MASK 0x0001ffff 7298a69c5ed2SRob Clark #define A6XX_TEX_CONST_8_FLAG_HI__SHIFT 0 7299a69c5ed2SRob Clark static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val) 73002d756322SRob Clark { 7301a69c5ed2SRob Clark return ((val) << A6XX_TEX_CONST_8_FLAG_HI__SHIFT) & A6XX_TEX_CONST_8_FLAG_HI__MASK; 73022d756322SRob Clark } 73032d756322SRob Clark 73042d756322SRob Clark #define REG_A6XX_TEX_CONST_9 0x00000009 7305c28c82e9SRob Clark #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff 7306c28c82e9SRob Clark #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0 7307c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) 7308c28c82e9SRob Clark { 7309c28c82e9SRob Clark return ((val >> 4) << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK; 7310c28c82e9SRob Clark } 73112d756322SRob Clark 73122d756322SRob Clark #define REG_A6XX_TEX_CONST_10 0x0000000a 7313c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK 0x0000007f 7314c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT 0 7315c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val) 7316c28c82e9SRob Clark { 7317c28c82e9SRob Clark return ((val >> 6) << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK; 7318c28c82e9SRob Clark } 7319c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK 0x00000f00 7320c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT 8 7321c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(uint32_t val) 7322c28c82e9SRob Clark { 7323c28c82e9SRob Clark return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK; 7324c28c82e9SRob Clark } 7325c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK 0x0000f000 7326c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT 12 7327c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(uint32_t val) 7328c28c82e9SRob Clark { 7329c28c82e9SRob Clark return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK; 7330c28c82e9SRob Clark } 73312d756322SRob Clark 73322d756322SRob Clark #define REG_A6XX_TEX_CONST_11 0x0000000b 73332d756322SRob Clark 73342d756322SRob Clark #define REG_A6XX_TEX_CONST_12 0x0000000c 73352d756322SRob Clark 73362d756322SRob Clark #define REG_A6XX_TEX_CONST_13 0x0000000d 73372d756322SRob Clark 73382d756322SRob Clark #define REG_A6XX_TEX_CONST_14 0x0000000e 73392d756322SRob Clark 73402d756322SRob Clark #define REG_A6XX_TEX_CONST_15 0x0000000f 73412d756322SRob Clark 7342c28c82e9SRob Clark #define REG_A6XX_IBO_0 0x00000000 7343c28c82e9SRob Clark #define A6XX_IBO_0_TILE_MODE__MASK 0x00000003 7344c28c82e9SRob Clark #define A6XX_IBO_0_TILE_MODE__SHIFT 0 7345c28c82e9SRob Clark static inline uint32_t A6XX_IBO_0_TILE_MODE(enum a6xx_tile_mode val) 7346c28c82e9SRob Clark { 7347c28c82e9SRob Clark return ((val) << A6XX_IBO_0_TILE_MODE__SHIFT) & A6XX_IBO_0_TILE_MODE__MASK; 7348c28c82e9SRob Clark } 7349c28c82e9SRob Clark #define A6XX_IBO_0_FMT__MASK 0x3fc00000 7350c28c82e9SRob Clark #define A6XX_IBO_0_FMT__SHIFT 22 7351c28c82e9SRob Clark static inline uint32_t A6XX_IBO_0_FMT(enum a6xx_format val) 7352c28c82e9SRob Clark { 7353c28c82e9SRob Clark return ((val) << A6XX_IBO_0_FMT__SHIFT) & A6XX_IBO_0_FMT__MASK; 7354c28c82e9SRob Clark } 7355c28c82e9SRob Clark 7356c28c82e9SRob Clark #define REG_A6XX_IBO_1 0x00000001 7357c28c82e9SRob Clark #define A6XX_IBO_1_WIDTH__MASK 0x00007fff 7358c28c82e9SRob Clark #define A6XX_IBO_1_WIDTH__SHIFT 0 7359c28c82e9SRob Clark static inline uint32_t A6XX_IBO_1_WIDTH(uint32_t val) 7360c28c82e9SRob Clark { 7361c28c82e9SRob Clark return ((val) << A6XX_IBO_1_WIDTH__SHIFT) & A6XX_IBO_1_WIDTH__MASK; 7362c28c82e9SRob Clark } 7363c28c82e9SRob Clark #define A6XX_IBO_1_HEIGHT__MASK 0x3fff8000 7364c28c82e9SRob Clark #define A6XX_IBO_1_HEIGHT__SHIFT 15 7365c28c82e9SRob Clark static inline uint32_t A6XX_IBO_1_HEIGHT(uint32_t val) 7366c28c82e9SRob Clark { 7367c28c82e9SRob Clark return ((val) << A6XX_IBO_1_HEIGHT__SHIFT) & A6XX_IBO_1_HEIGHT__MASK; 7368c28c82e9SRob Clark } 7369c28c82e9SRob Clark 7370c28c82e9SRob Clark #define REG_A6XX_IBO_2 0x00000002 7371c28c82e9SRob Clark #define A6XX_IBO_2_UNK4 0x00000010 7372c28c82e9SRob Clark #define A6XX_IBO_2_PITCH__MASK 0x1fffff80 7373c28c82e9SRob Clark #define A6XX_IBO_2_PITCH__SHIFT 7 7374c28c82e9SRob Clark static inline uint32_t A6XX_IBO_2_PITCH(uint32_t val) 7375c28c82e9SRob Clark { 7376c28c82e9SRob Clark return ((val) << A6XX_IBO_2_PITCH__SHIFT) & A6XX_IBO_2_PITCH__MASK; 7377c28c82e9SRob Clark } 7378c28c82e9SRob Clark #define A6XX_IBO_2_TYPE__MASK 0x60000000 7379c28c82e9SRob Clark #define A6XX_IBO_2_TYPE__SHIFT 29 7380c28c82e9SRob Clark static inline uint32_t A6XX_IBO_2_TYPE(enum a6xx_tex_type val) 7381c28c82e9SRob Clark { 7382c28c82e9SRob Clark return ((val) << A6XX_IBO_2_TYPE__SHIFT) & A6XX_IBO_2_TYPE__MASK; 7383c28c82e9SRob Clark } 7384c28c82e9SRob Clark #define A6XX_IBO_2_UNK31 0x80000000 7385c28c82e9SRob Clark 7386c28c82e9SRob Clark #define REG_A6XX_IBO_3 0x00000003 7387c28c82e9SRob Clark #define A6XX_IBO_3_ARRAY_PITCH__MASK 0x00003fff 7388c28c82e9SRob Clark #define A6XX_IBO_3_ARRAY_PITCH__SHIFT 0 7389c28c82e9SRob Clark static inline uint32_t A6XX_IBO_3_ARRAY_PITCH(uint32_t val) 7390c28c82e9SRob Clark { 7391c28c82e9SRob Clark return ((val >> 12) << A6XX_IBO_3_ARRAY_PITCH__SHIFT) & A6XX_IBO_3_ARRAY_PITCH__MASK; 7392c28c82e9SRob Clark } 7393c28c82e9SRob Clark #define A6XX_IBO_3_UNK27 0x08000000 7394c28c82e9SRob Clark #define A6XX_IBO_3_FLAG 0x10000000 7395c28c82e9SRob Clark 7396c28c82e9SRob Clark #define REG_A6XX_IBO_4 0x00000004 7397c28c82e9SRob Clark #define A6XX_IBO_4_BASE_LO__MASK 0xffffffff 7398c28c82e9SRob Clark #define A6XX_IBO_4_BASE_LO__SHIFT 0 7399c28c82e9SRob Clark static inline uint32_t A6XX_IBO_4_BASE_LO(uint32_t val) 7400c28c82e9SRob Clark { 7401c28c82e9SRob Clark return ((val) << A6XX_IBO_4_BASE_LO__SHIFT) & A6XX_IBO_4_BASE_LO__MASK; 7402c28c82e9SRob Clark } 7403c28c82e9SRob Clark 7404c28c82e9SRob Clark #define REG_A6XX_IBO_5 0x00000005 7405c28c82e9SRob Clark #define A6XX_IBO_5_BASE_HI__MASK 0x0001ffff 7406c28c82e9SRob Clark #define A6XX_IBO_5_BASE_HI__SHIFT 0 7407c28c82e9SRob Clark static inline uint32_t A6XX_IBO_5_BASE_HI(uint32_t val) 7408c28c82e9SRob Clark { 7409c28c82e9SRob Clark return ((val) << A6XX_IBO_5_BASE_HI__SHIFT) & A6XX_IBO_5_BASE_HI__MASK; 7410c28c82e9SRob Clark } 7411c28c82e9SRob Clark #define A6XX_IBO_5_DEPTH__MASK 0x3ffe0000 7412c28c82e9SRob Clark #define A6XX_IBO_5_DEPTH__SHIFT 17 7413c28c82e9SRob Clark static inline uint32_t A6XX_IBO_5_DEPTH(uint32_t val) 7414c28c82e9SRob Clark { 7415c28c82e9SRob Clark return ((val) << A6XX_IBO_5_DEPTH__SHIFT) & A6XX_IBO_5_DEPTH__MASK; 7416c28c82e9SRob Clark } 7417c28c82e9SRob Clark 7418c28c82e9SRob Clark #define REG_A6XX_IBO_6 0x00000006 7419c28c82e9SRob Clark 7420c28c82e9SRob Clark #define REG_A6XX_IBO_7 0x00000007 7421c28c82e9SRob Clark 7422c28c82e9SRob Clark #define REG_A6XX_IBO_8 0x00000008 7423c28c82e9SRob Clark 7424c28c82e9SRob Clark #define REG_A6XX_IBO_9 0x00000009 7425c28c82e9SRob Clark #define A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff 7426c28c82e9SRob Clark #define A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0 7427c28c82e9SRob Clark static inline uint32_t A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) 7428c28c82e9SRob Clark { 7429c28c82e9SRob Clark return ((val >> 4) << A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__MASK; 7430c28c82e9SRob Clark } 7431c28c82e9SRob Clark 7432c28c82e9SRob Clark #define REG_A6XX_IBO_10 0x0000000a 7433c28c82e9SRob Clark #define A6XX_IBO_10_FLAG_BUFFER_PITCH__MASK 0x0000007f 7434c28c82e9SRob Clark #define A6XX_IBO_10_FLAG_BUFFER_PITCH__SHIFT 0 7435c28c82e9SRob Clark static inline uint32_t A6XX_IBO_10_FLAG_BUFFER_PITCH(uint32_t val) 7436c28c82e9SRob Clark { 7437c28c82e9SRob Clark return ((val >> 6) << A6XX_IBO_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_IBO_10_FLAG_BUFFER_PITCH__MASK; 7438c28c82e9SRob Clark } 7439c28c82e9SRob Clark 7440c28c82e9SRob Clark #define REG_A6XX_UBO_0 0x00000000 7441c28c82e9SRob Clark #define A6XX_UBO_0_BASE_LO__MASK 0xffffffff 7442c28c82e9SRob Clark #define A6XX_UBO_0_BASE_LO__SHIFT 0 7443c28c82e9SRob Clark static inline uint32_t A6XX_UBO_0_BASE_LO(uint32_t val) 7444c28c82e9SRob Clark { 7445c28c82e9SRob Clark return ((val) << A6XX_UBO_0_BASE_LO__SHIFT) & A6XX_UBO_0_BASE_LO__MASK; 7446c28c82e9SRob Clark } 7447c28c82e9SRob Clark 7448c28c82e9SRob Clark #define REG_A6XX_UBO_1 0x00000001 7449c28c82e9SRob Clark #define A6XX_UBO_1_BASE_HI__MASK 0x0001ffff 7450c28c82e9SRob Clark #define A6XX_UBO_1_BASE_HI__SHIFT 0 7451c28c82e9SRob Clark static inline uint32_t A6XX_UBO_1_BASE_HI(uint32_t val) 7452c28c82e9SRob Clark { 7453c28c82e9SRob Clark return ((val) << A6XX_UBO_1_BASE_HI__SHIFT) & A6XX_UBO_1_BASE_HI__MASK; 7454c28c82e9SRob Clark } 7455c28c82e9SRob Clark #define A6XX_UBO_1_SIZE__MASK 0xfffe0000 7456c28c82e9SRob Clark #define A6XX_UBO_1_SIZE__SHIFT 17 7457c28c82e9SRob Clark static inline uint32_t A6XX_UBO_1_SIZE(uint32_t val) 7458c28c82e9SRob Clark { 7459c28c82e9SRob Clark return ((val) << A6XX_UBO_1_SIZE__SHIFT) & A6XX_UBO_1_SIZE__MASK; 7460c28c82e9SRob Clark } 7461c28c82e9SRob Clark 7462a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_ENABLE_PDC 0x00001140 7463a69c5ed2SRob Clark 7464a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_SEQ_START_ADDR 0x00001148 7465a69c5ed2SRob Clark 7466a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CONTROL 0x00001540 7467a69c5ed2SRob Clark 7468a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK 0x00001541 7469a69c5ed2SRob Clark 7470a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK 0x00001542 7471a69c5ed2SRob Clark 7472a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID 0x00001543 7473a69c5ed2SRob Clark 7474a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR 0x00001544 7475a69c5ed2SRob Clark 7476a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA 0x00001545 7477a69c5ed2SRob Clark 7478a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CONTROL 0x00001572 7479a69c5ed2SRob Clark 7480a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK 0x00001573 7481a69c5ed2SRob Clark 7482a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK 0x00001574 7483a69c5ed2SRob Clark 7484a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID 0x00001575 7485a69c5ed2SRob Clark 7486a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR 0x00001576 7487a69c5ed2SRob Clark 7488a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA 0x00001577 7489a69c5ed2SRob Clark 7490a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CONTROL 0x000015a4 7491a69c5ed2SRob Clark 7492a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK 0x000015a5 7493a69c5ed2SRob Clark 7494a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK 0x000015a6 7495a69c5ed2SRob Clark 7496a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID 0x000015a7 7497a69c5ed2SRob Clark 7498a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR 0x000015a8 7499a69c5ed2SRob Clark 7500a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA 0x000015a9 7501a69c5ed2SRob Clark 7502a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CONTROL 0x000015d6 7503a69c5ed2SRob Clark 7504a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK 0x000015d7 7505a69c5ed2SRob Clark 7506a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK 0x000015d8 7507a69c5ed2SRob Clark 7508a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID 0x000015d9 7509a69c5ed2SRob Clark 7510a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR 0x000015da 7511a69c5ed2SRob Clark 7512a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA 0x000015db 7513a69c5ed2SRob Clark 7514a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x00000000 7515a69c5ed2SRob Clark 7516a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A 0x00000000 7517a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK 0x000000ff 7518a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT 0 7519a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val) 7520a69c5ed2SRob Clark { 7521a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK; 7522a69c5ed2SRob Clark } 7523a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK 0x0000ff00 7524a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT 8 7525a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val) 7526a69c5ed2SRob Clark { 7527a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK; 7528a69c5ed2SRob Clark } 7529a69c5ed2SRob Clark 7530a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B 0x00000001 7531a69c5ed2SRob Clark 7532a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C 0x00000002 7533a69c5ed2SRob Clark 7534a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D 0x00000003 7535a69c5ed2SRob Clark 7536a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT 0x00000004 7537a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f 7538a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0 7539a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) 7540a69c5ed2SRob Clark { 7541a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; 7542a69c5ed2SRob Clark } 7543a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000 7544a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12 7545a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) 7546a69c5ed2SRob Clark { 7547a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; 7548a69c5ed2SRob Clark } 7549a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000 7550a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28 7551a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) 7552a69c5ed2SRob Clark { 7553a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; 7554a69c5ed2SRob Clark } 7555a69c5ed2SRob Clark 7556a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM 0x00000005 7557a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000 7558a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24 7559a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) 7560a69c5ed2SRob Clark { 7561a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; 7562a69c5ed2SRob Clark } 7563a69c5ed2SRob Clark 7564a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 0x00000008 7565a69c5ed2SRob Clark 7566a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 0x00000009 7567a69c5ed2SRob Clark 7568a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 0x0000000a 7569a69c5ed2SRob Clark 7570a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 0x0000000b 7571a69c5ed2SRob Clark 7572a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 0x0000000c 7573a69c5ed2SRob Clark 7574a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 0x0000000d 7575a69c5ed2SRob Clark 7576a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 0x0000000e 7577a69c5ed2SRob Clark 7578a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 0x0000000f 7579a69c5ed2SRob Clark 7580a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000010 7581a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f 7582a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0 7583a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) 7584a69c5ed2SRob Clark { 7585a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; 7586a69c5ed2SRob Clark } 7587a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0 7588a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4 7589a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) 7590a69c5ed2SRob Clark { 7591a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; 7592a69c5ed2SRob Clark } 7593a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00 7594a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8 7595a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) 7596a69c5ed2SRob Clark { 7597a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; 7598a69c5ed2SRob Clark } 7599a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000 7600a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12 7601a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) 7602a69c5ed2SRob Clark { 7603a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; 7604a69c5ed2SRob Clark } 7605a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000 7606a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16 7607a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) 7608a69c5ed2SRob Clark { 7609a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; 7610a69c5ed2SRob Clark } 7611a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000 7612a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20 7613a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) 7614a69c5ed2SRob Clark { 7615a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; 7616a69c5ed2SRob Clark } 7617a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000 7618a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24 7619a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) 7620a69c5ed2SRob Clark { 7621a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; 7622a69c5ed2SRob Clark } 7623a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000 7624a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28 7625a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) 7626a69c5ed2SRob Clark { 7627a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; 7628a69c5ed2SRob Clark } 7629a69c5ed2SRob Clark 7630a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000011 7631a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f 7632a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0 7633a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) 7634a69c5ed2SRob Clark { 7635a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; 7636a69c5ed2SRob Clark } 7637a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0 7638a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4 7639a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) 7640a69c5ed2SRob Clark { 7641a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; 7642a69c5ed2SRob Clark } 7643a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00 7644a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8 7645a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) 7646a69c5ed2SRob Clark { 7647a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; 7648a69c5ed2SRob Clark } 7649a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000 7650a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12 7651a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) 7652a69c5ed2SRob Clark { 7653a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; 7654a69c5ed2SRob Clark } 7655a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000 7656a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16 7657a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) 7658a69c5ed2SRob Clark { 7659a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; 7660a69c5ed2SRob Clark } 7661a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000 7662a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20 7663a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) 7664a69c5ed2SRob Clark { 7665a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; 7666a69c5ed2SRob Clark } 7667a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000 7668a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24 7669a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) 7670a69c5ed2SRob Clark { 7671a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; 7672a69c5ed2SRob Clark } 7673a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000 7674a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28 7675a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) 7676a69c5ed2SRob Clark { 7677a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; 7678a69c5ed2SRob Clark } 7679a69c5ed2SRob Clark 7680a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000002f 7681a69c5ed2SRob Clark 7682a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000030 7683a69c5ed2SRob Clark 7684ccdf7e28SRob Clark #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 0x00000001 7685ccdf7e28SRob Clark 7686ccdf7e28SRob Clark #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 0x00000002 7687ccdf7e28SRob Clark 76882d756322SRob Clark 76892d756322SRob Clark #endif /* A6XX_XML */ 7690