12d756322SRob Clark #ifndef A6XX_XML 22d756322SRob Clark #define A6XX_XML 32d756322SRob Clark 42d756322SRob Clark /* Autogenerated file, DO NOT EDIT manually! 52d756322SRob Clark 62d756322SRob Clark This file was generated by the rules-ng-ng headergen tool in this git repository: 72d756322SRob Clark http://github.com/freedreno/envytools/ 82d756322SRob Clark git clone https://github.com/freedreno/envytools.git 92d756322SRob Clark 102d756322SRob Clark The rules-ng-ng source files this header was generated from are: 11*57cfe41cSRob Clark - /home/robclark/tmp/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-01-30 18:25:22) 12*57cfe41cSRob Clark - /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2020-12-31 19:26:32) 13*57cfe41cSRob Clark - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-06-21 15:24:24) 14*57cfe41cSRob Clark - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14609 bytes, from 2021-11-24 23:05:10) 15*57cfe41cSRob Clark - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 69086 bytes, from 2022-03-03 16:41:33) 16*57cfe41cSRob Clark - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2021-11-24 23:05:10) 17*57cfe41cSRob Clark - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113358 bytes, from 2022-01-31 23:06:21) 18*57cfe41cSRob Clark - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149512 bytes, from 2022-01-31 23:06:21) 19*57cfe41cSRob Clark - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx.xml ( 184954 bytes, from 2022-03-03 16:41:33) 20*57cfe41cSRob Clark - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-07-22 15:21:56) 21*57cfe41cSRob Clark - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-01-30 18:25:22) 22*57cfe41cSRob Clark - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-07-22 15:21:56) 23*57cfe41cSRob Clark - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-07-22 15:21:56) 242d756322SRob Clark 25*57cfe41cSRob Clark Copyright (C) 2013-2022 by the following authors: 262d756322SRob Clark - Rob Clark <robdclark@gmail.com> (robclark) 272d756322SRob Clark - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 282d756322SRob Clark 292d756322SRob Clark Permission is hereby granted, free of charge, to any person obtaining 302d756322SRob Clark a copy of this software and associated documentation files (the 312d756322SRob Clark "Software"), to deal in the Software without restriction, including 322d756322SRob Clark without limitation the rights to use, copy, modify, merge, publish, 332d756322SRob Clark distribute, sublicense, and/or sell copies of the Software, and to 342d756322SRob Clark permit persons to whom the Software is furnished to do so, subject to 352d756322SRob Clark the following conditions: 362d756322SRob Clark 372d756322SRob Clark The above copyright notice and this permission notice (including the 382d756322SRob Clark next paragraph) shall be included in all copies or substantial 392d756322SRob Clark portions of the Software. 402d756322SRob Clark 412d756322SRob Clark THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 422d756322SRob Clark EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 432d756322SRob Clark MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 442d756322SRob Clark IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 452d756322SRob Clark LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 462d756322SRob Clark OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 472d756322SRob Clark WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 482d756322SRob Clark */ 492d756322SRob Clark 502d756322SRob Clark 512d756322SRob Clark enum a6xx_tile_mode { 522d756322SRob Clark TILE6_LINEAR = 0, 532d756322SRob Clark TILE6_2 = 2, 542d756322SRob Clark TILE6_3 = 3, 552d756322SRob Clark }; 562d756322SRob Clark 57c28c82e9SRob Clark enum a6xx_format { 58c28c82e9SRob Clark FMT6_A8_UNORM = 2, 59c28c82e9SRob Clark FMT6_8_UNORM = 3, 60c28c82e9SRob Clark FMT6_8_SNORM = 4, 61c28c82e9SRob Clark FMT6_8_UINT = 5, 62c28c82e9SRob Clark FMT6_8_SINT = 6, 63c28c82e9SRob Clark FMT6_4_4_4_4_UNORM = 8, 64c28c82e9SRob Clark FMT6_5_5_5_1_UNORM = 10, 65c28c82e9SRob Clark FMT6_1_5_5_5_UNORM = 12, 66c28c82e9SRob Clark FMT6_5_6_5_UNORM = 14, 67c28c82e9SRob Clark FMT6_8_8_UNORM = 15, 68c28c82e9SRob Clark FMT6_8_8_SNORM = 16, 69c28c82e9SRob Clark FMT6_8_8_UINT = 17, 70c28c82e9SRob Clark FMT6_8_8_SINT = 18, 71c28c82e9SRob Clark FMT6_L8_A8_UNORM = 19, 72c28c82e9SRob Clark FMT6_16_UNORM = 21, 73c28c82e9SRob Clark FMT6_16_SNORM = 22, 74c28c82e9SRob Clark FMT6_16_FLOAT = 23, 75c28c82e9SRob Clark FMT6_16_UINT = 24, 76c28c82e9SRob Clark FMT6_16_SINT = 25, 77c28c82e9SRob Clark FMT6_8_8_8_UNORM = 33, 78c28c82e9SRob Clark FMT6_8_8_8_SNORM = 34, 79c28c82e9SRob Clark FMT6_8_8_8_UINT = 35, 80c28c82e9SRob Clark FMT6_8_8_8_SINT = 36, 81c28c82e9SRob Clark FMT6_8_8_8_8_UNORM = 48, 82c28c82e9SRob Clark FMT6_8_8_8_X8_UNORM = 49, 83c28c82e9SRob Clark FMT6_8_8_8_8_SNORM = 50, 84c28c82e9SRob Clark FMT6_8_8_8_8_UINT = 51, 85c28c82e9SRob Clark FMT6_8_8_8_8_SINT = 52, 86c28c82e9SRob Clark FMT6_9_9_9_E5_FLOAT = 53, 87c28c82e9SRob Clark FMT6_10_10_10_2_UNORM = 54, 88c28c82e9SRob Clark FMT6_10_10_10_2_UNORM_DEST = 55, 89c28c82e9SRob Clark FMT6_10_10_10_2_SNORM = 57, 90c28c82e9SRob Clark FMT6_10_10_10_2_UINT = 58, 91c28c82e9SRob Clark FMT6_10_10_10_2_SINT = 59, 92c28c82e9SRob Clark FMT6_11_11_10_FLOAT = 66, 93c28c82e9SRob Clark FMT6_16_16_UNORM = 67, 94c28c82e9SRob Clark FMT6_16_16_SNORM = 68, 95c28c82e9SRob Clark FMT6_16_16_FLOAT = 69, 96c28c82e9SRob Clark FMT6_16_16_UINT = 70, 97c28c82e9SRob Clark FMT6_16_16_SINT = 71, 98c28c82e9SRob Clark FMT6_32_UNORM = 72, 99c28c82e9SRob Clark FMT6_32_SNORM = 73, 100c28c82e9SRob Clark FMT6_32_FLOAT = 74, 101c28c82e9SRob Clark FMT6_32_UINT = 75, 102c28c82e9SRob Clark FMT6_32_SINT = 76, 103c28c82e9SRob Clark FMT6_32_FIXED = 77, 104c28c82e9SRob Clark FMT6_16_16_16_UNORM = 88, 105c28c82e9SRob Clark FMT6_16_16_16_SNORM = 89, 106c28c82e9SRob Clark FMT6_16_16_16_FLOAT = 90, 107c28c82e9SRob Clark FMT6_16_16_16_UINT = 91, 108c28c82e9SRob Clark FMT6_16_16_16_SINT = 92, 109c28c82e9SRob Clark FMT6_16_16_16_16_UNORM = 96, 110c28c82e9SRob Clark FMT6_16_16_16_16_SNORM = 97, 111c28c82e9SRob Clark FMT6_16_16_16_16_FLOAT = 98, 112c28c82e9SRob Clark FMT6_16_16_16_16_UINT = 99, 113c28c82e9SRob Clark FMT6_16_16_16_16_SINT = 100, 114c28c82e9SRob Clark FMT6_32_32_UNORM = 101, 115c28c82e9SRob Clark FMT6_32_32_SNORM = 102, 116c28c82e9SRob Clark FMT6_32_32_FLOAT = 103, 117c28c82e9SRob Clark FMT6_32_32_UINT = 104, 118c28c82e9SRob Clark FMT6_32_32_SINT = 105, 119c28c82e9SRob Clark FMT6_32_32_FIXED = 106, 120c28c82e9SRob Clark FMT6_32_32_32_UNORM = 112, 121c28c82e9SRob Clark FMT6_32_32_32_SNORM = 113, 122c28c82e9SRob Clark FMT6_32_32_32_UINT = 114, 123c28c82e9SRob Clark FMT6_32_32_32_SINT = 115, 124c28c82e9SRob Clark FMT6_32_32_32_FLOAT = 116, 125c28c82e9SRob Clark FMT6_32_32_32_FIXED = 117, 126c28c82e9SRob Clark FMT6_32_32_32_32_UNORM = 128, 127c28c82e9SRob Clark FMT6_32_32_32_32_SNORM = 129, 128c28c82e9SRob Clark FMT6_32_32_32_32_FLOAT = 130, 129c28c82e9SRob Clark FMT6_32_32_32_32_UINT = 131, 130c28c82e9SRob Clark FMT6_32_32_32_32_SINT = 132, 131c28c82e9SRob Clark FMT6_32_32_32_32_FIXED = 133, 132c28c82e9SRob Clark FMT6_G8R8B8R8_422_UNORM = 140, 133c28c82e9SRob Clark FMT6_R8G8R8B8_422_UNORM = 141, 134c28c82e9SRob Clark FMT6_R8_G8B8_2PLANE_420_UNORM = 142, 135*57cfe41cSRob Clark FMT6_NV21 = 143, 136c28c82e9SRob Clark FMT6_R8_G8_B8_3PLANE_420_UNORM = 144, 137c28c82e9SRob Clark FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 = 145, 138*57cfe41cSRob Clark FMT6_NV12_Y = 148, 139*57cfe41cSRob Clark FMT6_NV12_UV = 149, 140*57cfe41cSRob Clark FMT6_NV12_VU = 150, 141*57cfe41cSRob Clark FMT6_NV12_4R = 151, 142*57cfe41cSRob Clark FMT6_NV12_4R_Y = 152, 143*57cfe41cSRob Clark FMT6_NV12_4R_UV = 153, 144*57cfe41cSRob Clark FMT6_P010 = 154, 145*57cfe41cSRob Clark FMT6_P010_Y = 155, 146*57cfe41cSRob Clark FMT6_P010_UV = 156, 147*57cfe41cSRob Clark FMT6_TP10 = 157, 148*57cfe41cSRob Clark FMT6_TP10_Y = 158, 149*57cfe41cSRob Clark FMT6_TP10_UV = 159, 150c28c82e9SRob Clark FMT6_Z24_UNORM_S8_UINT = 160, 151c28c82e9SRob Clark FMT6_ETC2_RG11_UNORM = 171, 152c28c82e9SRob Clark FMT6_ETC2_RG11_SNORM = 172, 153c28c82e9SRob Clark FMT6_ETC2_R11_UNORM = 173, 154c28c82e9SRob Clark FMT6_ETC2_R11_SNORM = 174, 155c28c82e9SRob Clark FMT6_ETC1 = 175, 156c28c82e9SRob Clark FMT6_ETC2_RGB8 = 176, 157c28c82e9SRob Clark FMT6_ETC2_RGBA8 = 177, 158c28c82e9SRob Clark FMT6_ETC2_RGB8A1 = 178, 159c28c82e9SRob Clark FMT6_DXT1 = 179, 160c28c82e9SRob Clark FMT6_DXT3 = 180, 161c28c82e9SRob Clark FMT6_DXT5 = 181, 162c28c82e9SRob Clark FMT6_RGTC1_UNORM = 183, 163c28c82e9SRob Clark FMT6_RGTC1_SNORM = 184, 164c28c82e9SRob Clark FMT6_RGTC2_UNORM = 187, 165c28c82e9SRob Clark FMT6_RGTC2_SNORM = 188, 166c28c82e9SRob Clark FMT6_BPTC_UFLOAT = 190, 167c28c82e9SRob Clark FMT6_BPTC_FLOAT = 191, 168c28c82e9SRob Clark FMT6_BPTC = 192, 169c28c82e9SRob Clark FMT6_ASTC_4x4 = 193, 170c28c82e9SRob Clark FMT6_ASTC_5x4 = 194, 171c28c82e9SRob Clark FMT6_ASTC_5x5 = 195, 172c28c82e9SRob Clark FMT6_ASTC_6x5 = 196, 173c28c82e9SRob Clark FMT6_ASTC_6x6 = 197, 174c28c82e9SRob Clark FMT6_ASTC_8x5 = 198, 175c28c82e9SRob Clark FMT6_ASTC_8x6 = 199, 176c28c82e9SRob Clark FMT6_ASTC_8x8 = 200, 177c28c82e9SRob Clark FMT6_ASTC_10x5 = 201, 178c28c82e9SRob Clark FMT6_ASTC_10x6 = 202, 179c28c82e9SRob Clark FMT6_ASTC_10x8 = 203, 180c28c82e9SRob Clark FMT6_ASTC_10x10 = 204, 181c28c82e9SRob Clark FMT6_ASTC_12x10 = 205, 182c28c82e9SRob Clark FMT6_ASTC_12x12 = 206, 183cc4c26d4SRob Clark FMT6_Z24_UINT_S8_UINT = 234, 184c28c82e9SRob Clark FMT6_NONE = 255, 1852d756322SRob Clark }; 1862d756322SRob Clark 187c28c82e9SRob Clark enum a6xx_polygon_mode { 188c28c82e9SRob Clark POLYMODE6_POINTS = 1, 189c28c82e9SRob Clark POLYMODE6_LINES = 2, 190c28c82e9SRob Clark POLYMODE6_TRIANGLES = 3, 1912d756322SRob Clark }; 1922d756322SRob Clark 1932d756322SRob Clark enum a6xx_depth_format { 1942d756322SRob Clark DEPTH6_NONE = 0, 1952d756322SRob Clark DEPTH6_16 = 1, 1962d756322SRob Clark DEPTH6_24_8 = 2, 1972d756322SRob Clark DEPTH6_32 = 4, 1982d756322SRob Clark }; 1992d756322SRob Clark 200a69c5ed2SRob Clark enum a6xx_shader_id { 201a69c5ed2SRob Clark A6XX_TP0_TMO_DATA = 9, 202a69c5ed2SRob Clark A6XX_TP0_SMO_DATA = 10, 203a69c5ed2SRob Clark A6XX_TP0_MIPMAP_BASE_DATA = 11, 204a69c5ed2SRob Clark A6XX_TP1_TMO_DATA = 25, 205a69c5ed2SRob Clark A6XX_TP1_SMO_DATA = 26, 206a69c5ed2SRob Clark A6XX_TP1_MIPMAP_BASE_DATA = 27, 207a69c5ed2SRob Clark A6XX_SP_INST_DATA = 41, 208a69c5ed2SRob Clark A6XX_SP_LB_0_DATA = 42, 209a69c5ed2SRob Clark A6XX_SP_LB_1_DATA = 43, 210a69c5ed2SRob Clark A6XX_SP_LB_2_DATA = 44, 211a69c5ed2SRob Clark A6XX_SP_LB_3_DATA = 45, 212a69c5ed2SRob Clark A6XX_SP_LB_4_DATA = 46, 213a69c5ed2SRob Clark A6XX_SP_LB_5_DATA = 47, 214a69c5ed2SRob Clark A6XX_SP_CB_BINDLESS_DATA = 48, 215a69c5ed2SRob Clark A6XX_SP_CB_LEGACY_DATA = 49, 216a69c5ed2SRob Clark A6XX_SP_UAV_DATA = 50, 217a69c5ed2SRob Clark A6XX_SP_INST_TAG = 51, 218a69c5ed2SRob Clark A6XX_SP_CB_BINDLESS_TAG = 52, 219a69c5ed2SRob Clark A6XX_SP_TMO_UMO_TAG = 53, 220a69c5ed2SRob Clark A6XX_SP_SMO_TAG = 54, 221a69c5ed2SRob Clark A6XX_SP_STATE_DATA = 55, 222a69c5ed2SRob Clark A6XX_HLSQ_CHUNK_CVS_RAM = 73, 223a69c5ed2SRob Clark A6XX_HLSQ_CHUNK_CPS_RAM = 74, 224a69c5ed2SRob Clark A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75, 225a69c5ed2SRob Clark A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76, 226a69c5ed2SRob Clark A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77, 227a69c5ed2SRob Clark A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78, 228a69c5ed2SRob Clark A6XX_HLSQ_CVS_MISC_RAM = 80, 229a69c5ed2SRob Clark A6XX_HLSQ_CPS_MISC_RAM = 81, 230a69c5ed2SRob Clark A6XX_HLSQ_INST_RAM = 82, 231a69c5ed2SRob Clark A6XX_HLSQ_GFX_CVS_CONST_RAM = 83, 232a69c5ed2SRob Clark A6XX_HLSQ_GFX_CPS_CONST_RAM = 84, 233a69c5ed2SRob Clark A6XX_HLSQ_CVS_MISC_RAM_TAG = 85, 234a69c5ed2SRob Clark A6XX_HLSQ_CPS_MISC_RAM_TAG = 86, 235a69c5ed2SRob Clark A6XX_HLSQ_INST_RAM_TAG = 87, 236a69c5ed2SRob Clark A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88, 237a69c5ed2SRob Clark A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89, 238a69c5ed2SRob Clark A6XX_HLSQ_PWR_REST_RAM = 90, 239a69c5ed2SRob Clark A6XX_HLSQ_PWR_REST_TAG = 91, 240a69c5ed2SRob Clark A6XX_HLSQ_DATAPATH_META = 96, 241a69c5ed2SRob Clark A6XX_HLSQ_FRONTEND_META = 97, 242a69c5ed2SRob Clark A6XX_HLSQ_INDIRECT_META = 98, 243a69c5ed2SRob Clark A6XX_HLSQ_BACKEND_META = 99, 244a69c5ed2SRob Clark }; 245a69c5ed2SRob Clark 246a69c5ed2SRob Clark enum a6xx_debugbus_id { 247a69c5ed2SRob Clark A6XX_DBGBUS_CP = 1, 248a69c5ed2SRob Clark A6XX_DBGBUS_RBBM = 2, 249a69c5ed2SRob Clark A6XX_DBGBUS_VBIF = 3, 250a69c5ed2SRob Clark A6XX_DBGBUS_HLSQ = 4, 251a69c5ed2SRob Clark A6XX_DBGBUS_UCHE = 5, 252a69c5ed2SRob Clark A6XX_DBGBUS_DPM = 6, 253a69c5ed2SRob Clark A6XX_DBGBUS_TESS = 7, 254a69c5ed2SRob Clark A6XX_DBGBUS_PC = 8, 255a69c5ed2SRob Clark A6XX_DBGBUS_VFDP = 9, 256a69c5ed2SRob Clark A6XX_DBGBUS_VPC = 10, 257a69c5ed2SRob Clark A6XX_DBGBUS_TSE = 11, 258a69c5ed2SRob Clark A6XX_DBGBUS_RAS = 12, 259a69c5ed2SRob Clark A6XX_DBGBUS_VSC = 13, 260a69c5ed2SRob Clark A6XX_DBGBUS_COM = 14, 261a69c5ed2SRob Clark A6XX_DBGBUS_LRZ = 16, 262a69c5ed2SRob Clark A6XX_DBGBUS_A2D = 17, 263a69c5ed2SRob Clark A6XX_DBGBUS_CCUFCHE = 18, 264a69c5ed2SRob Clark A6XX_DBGBUS_GMU_CX = 19, 265a69c5ed2SRob Clark A6XX_DBGBUS_RBP = 20, 266a69c5ed2SRob Clark A6XX_DBGBUS_DCS = 21, 267a69c5ed2SRob Clark A6XX_DBGBUS_DBGC = 22, 268a69c5ed2SRob Clark A6XX_DBGBUS_CX = 23, 269a69c5ed2SRob Clark A6XX_DBGBUS_GMU_GX = 24, 270a69c5ed2SRob Clark A6XX_DBGBUS_TPFCHE = 25, 271a69c5ed2SRob Clark A6XX_DBGBUS_GBIF_GX = 26, 272a69c5ed2SRob Clark A6XX_DBGBUS_GPC = 29, 273a69c5ed2SRob Clark A6XX_DBGBUS_LARC = 30, 274a69c5ed2SRob Clark A6XX_DBGBUS_HLSQ_SPTP = 31, 275a69c5ed2SRob Clark A6XX_DBGBUS_RB_0 = 32, 276a69c5ed2SRob Clark A6XX_DBGBUS_RB_1 = 33, 277a69c5ed2SRob Clark A6XX_DBGBUS_UCHE_WRAPPER = 36, 278a69c5ed2SRob Clark A6XX_DBGBUS_CCU_0 = 40, 279a69c5ed2SRob Clark A6XX_DBGBUS_CCU_1 = 41, 280a69c5ed2SRob Clark A6XX_DBGBUS_VFD_0 = 56, 281a69c5ed2SRob Clark A6XX_DBGBUS_VFD_1 = 57, 282a69c5ed2SRob Clark A6XX_DBGBUS_VFD_2 = 58, 283a69c5ed2SRob Clark A6XX_DBGBUS_VFD_3 = 59, 284a69c5ed2SRob Clark A6XX_DBGBUS_SP_0 = 64, 285a69c5ed2SRob Clark A6XX_DBGBUS_SP_1 = 65, 286a69c5ed2SRob Clark A6XX_DBGBUS_TPL1_0 = 72, 287a69c5ed2SRob Clark A6XX_DBGBUS_TPL1_1 = 73, 288a69c5ed2SRob Clark A6XX_DBGBUS_TPL1_2 = 74, 289a69c5ed2SRob Clark A6XX_DBGBUS_TPL1_3 = 75, 290a69c5ed2SRob Clark }; 291a69c5ed2SRob Clark 2922d756322SRob Clark enum a6xx_cp_perfcounter_select { 2932d756322SRob Clark PERF_CP_ALWAYS_COUNT = 0, 294a69c5ed2SRob Clark PERF_CP_BUSY_GFX_CORE_IDLE = 1, 295a69c5ed2SRob Clark PERF_CP_BUSY_CYCLES = 2, 296a69c5ed2SRob Clark PERF_CP_NUM_PREEMPTIONS = 3, 297a69c5ed2SRob Clark PERF_CP_PREEMPTION_REACTION_DELAY = 4, 298a69c5ed2SRob Clark PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 5, 299a69c5ed2SRob Clark PERF_CP_PREEMPTION_SWITCH_IN_TIME = 6, 300a69c5ed2SRob Clark PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 7, 301a69c5ed2SRob Clark PERF_CP_PREDICATED_DRAWS_KILLED = 8, 302a69c5ed2SRob Clark PERF_CP_MODE_SWITCH = 9, 303a69c5ed2SRob Clark PERF_CP_ZPASS_DONE = 10, 304a69c5ed2SRob Clark PERF_CP_CONTEXT_DONE = 11, 305a69c5ed2SRob Clark PERF_CP_CACHE_FLUSH = 12, 306a69c5ed2SRob Clark PERF_CP_LONG_PREEMPTIONS = 13, 307a69c5ed2SRob Clark PERF_CP_SQE_I_CACHE_STARVE = 14, 308a69c5ed2SRob Clark PERF_CP_SQE_IDLE = 15, 309a69c5ed2SRob Clark PERF_CP_SQE_PM4_STARVE_RB_IB = 16, 310a69c5ed2SRob Clark PERF_CP_SQE_PM4_STARVE_SDS = 17, 311a69c5ed2SRob Clark PERF_CP_SQE_MRB_STARVE = 18, 312a69c5ed2SRob Clark PERF_CP_SQE_RRB_STARVE = 19, 313a69c5ed2SRob Clark PERF_CP_SQE_VSD_STARVE = 20, 314a69c5ed2SRob Clark PERF_CP_VSD_DECODE_STARVE = 21, 315a69c5ed2SRob Clark PERF_CP_SQE_PIPE_OUT_STALL = 22, 316a69c5ed2SRob Clark PERF_CP_SQE_SYNC_STALL = 23, 317a69c5ed2SRob Clark PERF_CP_SQE_PM4_WFI_STALL = 24, 318a69c5ed2SRob Clark PERF_CP_SQE_SYS_WFI_STALL = 25, 319a69c5ed2SRob Clark PERF_CP_SQE_T4_EXEC = 26, 320a69c5ed2SRob Clark PERF_CP_SQE_LOAD_STATE_EXEC = 27, 321a69c5ed2SRob Clark PERF_CP_SQE_SAVE_SDS_STATE = 28, 322a69c5ed2SRob Clark PERF_CP_SQE_DRAW_EXEC = 29, 323a69c5ed2SRob Clark PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 30, 324a69c5ed2SRob Clark PERF_CP_SQE_EXEC_PROFILED = 31, 325a69c5ed2SRob Clark PERF_CP_MEMORY_POOL_EMPTY = 32, 326a69c5ed2SRob Clark PERF_CP_MEMORY_POOL_SYNC_STALL = 33, 327a69c5ed2SRob Clark PERF_CP_MEMORY_POOL_ABOVE_THRESH = 34, 328a69c5ed2SRob Clark PERF_CP_AHB_WR_STALL_PRE_DRAWS = 35, 329a69c5ed2SRob Clark PERF_CP_AHB_STALL_SQE_GMU = 36, 330a69c5ed2SRob Clark PERF_CP_AHB_STALL_SQE_WR_OTHER = 37, 331a69c5ed2SRob Clark PERF_CP_AHB_STALL_SQE_RD_OTHER = 38, 332a69c5ed2SRob Clark PERF_CP_CLUSTER0_EMPTY = 39, 333a69c5ed2SRob Clark PERF_CP_CLUSTER1_EMPTY = 40, 334a69c5ed2SRob Clark PERF_CP_CLUSTER2_EMPTY = 41, 335a69c5ed2SRob Clark PERF_CP_CLUSTER3_EMPTY = 42, 336a69c5ed2SRob Clark PERF_CP_CLUSTER4_EMPTY = 43, 337a69c5ed2SRob Clark PERF_CP_CLUSTER5_EMPTY = 44, 338a69c5ed2SRob Clark PERF_CP_PM4_DATA = 45, 339a69c5ed2SRob Clark PERF_CP_PM4_HEADERS = 46, 340a69c5ed2SRob Clark PERF_CP_VBIF_READ_BEATS = 47, 341a69c5ed2SRob Clark PERF_CP_VBIF_WRITE_BEATS = 48, 342a69c5ed2SRob Clark PERF_CP_SQE_INSTR_COUNTER = 49, 343a69c5ed2SRob Clark }; 344a69c5ed2SRob Clark 345a69c5ed2SRob Clark enum a6xx_rbbm_perfcounter_select { 346a69c5ed2SRob Clark PERF_RBBM_ALWAYS_COUNT = 0, 347a69c5ed2SRob Clark PERF_RBBM_ALWAYS_ON = 1, 348a69c5ed2SRob Clark PERF_RBBM_TSE_BUSY = 2, 349a69c5ed2SRob Clark PERF_RBBM_RAS_BUSY = 3, 350a69c5ed2SRob Clark PERF_RBBM_PC_DCALL_BUSY = 4, 351a69c5ed2SRob Clark PERF_RBBM_PC_VSD_BUSY = 5, 352a69c5ed2SRob Clark PERF_RBBM_STATUS_MASKED = 6, 353a69c5ed2SRob Clark PERF_RBBM_COM_BUSY = 7, 354a69c5ed2SRob Clark PERF_RBBM_DCOM_BUSY = 8, 355a69c5ed2SRob Clark PERF_RBBM_VBIF_BUSY = 9, 356a69c5ed2SRob Clark PERF_RBBM_VSC_BUSY = 10, 357a69c5ed2SRob Clark PERF_RBBM_TESS_BUSY = 11, 358a69c5ed2SRob Clark PERF_RBBM_UCHE_BUSY = 12, 359a69c5ed2SRob Clark PERF_RBBM_HLSQ_BUSY = 13, 360a69c5ed2SRob Clark }; 361a69c5ed2SRob Clark 362a69c5ed2SRob Clark enum a6xx_pc_perfcounter_select { 363a69c5ed2SRob Clark PERF_PC_BUSY_CYCLES = 0, 364a69c5ed2SRob Clark PERF_PC_WORKING_CYCLES = 1, 365a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_VFD = 2, 366a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_TSE = 3, 367a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_VPC = 4, 368a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_UCHE = 5, 369a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_TESS = 6, 370a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_TSE_ONLY = 7, 371a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_VPC_ONLY = 8, 372a69c5ed2SRob Clark PERF_PC_PASS1_TF_STALL_CYCLES = 9, 373a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_FOR_INDEX = 10, 374a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11, 375a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12, 376a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_FOR_POSITION = 13, 377a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_DI = 14, 378a69c5ed2SRob Clark PERF_PC_VIS_STREAMS_LOADED = 15, 379a69c5ed2SRob Clark PERF_PC_INSTANCES = 16, 380a69c5ed2SRob Clark PERF_PC_VPC_PRIMITIVES = 17, 381a69c5ed2SRob Clark PERF_PC_DEAD_PRIM = 18, 382a69c5ed2SRob Clark PERF_PC_LIVE_PRIM = 19, 383a69c5ed2SRob Clark PERF_PC_VERTEX_HITS = 20, 384a69c5ed2SRob Clark PERF_PC_IA_VERTICES = 21, 385a69c5ed2SRob Clark PERF_PC_IA_PRIMITIVES = 22, 386a69c5ed2SRob Clark PERF_PC_GS_PRIMITIVES = 23, 387a69c5ed2SRob Clark PERF_PC_HS_INVOCATIONS = 24, 388a69c5ed2SRob Clark PERF_PC_DS_INVOCATIONS = 25, 389a69c5ed2SRob Clark PERF_PC_VS_INVOCATIONS = 26, 390a69c5ed2SRob Clark PERF_PC_GS_INVOCATIONS = 27, 391a69c5ed2SRob Clark PERF_PC_DS_PRIMITIVES = 28, 392a69c5ed2SRob Clark PERF_PC_VPC_POS_DATA_TRANSACTION = 29, 393a69c5ed2SRob Clark PERF_PC_3D_DRAWCALLS = 30, 394a69c5ed2SRob Clark PERF_PC_2D_DRAWCALLS = 31, 395a69c5ed2SRob Clark PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32, 396a69c5ed2SRob Clark PERF_TESS_BUSY_CYCLES = 33, 397a69c5ed2SRob Clark PERF_TESS_WORKING_CYCLES = 34, 398a69c5ed2SRob Clark PERF_TESS_STALL_CYCLES_PC = 35, 399a69c5ed2SRob Clark PERF_TESS_STARVE_CYCLES_PC = 36, 400a69c5ed2SRob Clark PERF_PC_TSE_TRANSACTION = 37, 401a69c5ed2SRob Clark PERF_PC_TSE_VERTEX = 38, 402a69c5ed2SRob Clark PERF_PC_TESS_PC_UV_TRANS = 39, 403a69c5ed2SRob Clark PERF_PC_TESS_PC_UV_PATCHES = 40, 404a69c5ed2SRob Clark PERF_PC_TESS_FACTOR_TRANS = 41, 405a69c5ed2SRob Clark }; 406a69c5ed2SRob Clark 407a69c5ed2SRob Clark enum a6xx_vfd_perfcounter_select { 408a69c5ed2SRob Clark PERF_VFD_BUSY_CYCLES = 0, 409a69c5ed2SRob Clark PERF_VFD_STALL_CYCLES_UCHE = 1, 410a69c5ed2SRob Clark PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2, 411a69c5ed2SRob Clark PERF_VFD_STALL_CYCLES_SP_INFO = 3, 412a69c5ed2SRob Clark PERF_VFD_STALL_CYCLES_SP_ATTR = 4, 413a69c5ed2SRob Clark PERF_VFD_STARVE_CYCLES_UCHE = 5, 414a69c5ed2SRob Clark PERF_VFD_RBUFFER_FULL = 6, 415a69c5ed2SRob Clark PERF_VFD_ATTR_INFO_FIFO_FULL = 7, 416a69c5ed2SRob Clark PERF_VFD_DECODED_ATTRIBUTE_BYTES = 8, 417a69c5ed2SRob Clark PERF_VFD_NUM_ATTRIBUTES = 9, 418a69c5ed2SRob Clark PERF_VFD_UPPER_SHADER_FIBERS = 10, 419a69c5ed2SRob Clark PERF_VFD_LOWER_SHADER_FIBERS = 11, 420a69c5ed2SRob Clark PERF_VFD_MODE_0_FIBERS = 12, 421a69c5ed2SRob Clark PERF_VFD_MODE_1_FIBERS = 13, 422a69c5ed2SRob Clark PERF_VFD_MODE_2_FIBERS = 14, 423a69c5ed2SRob Clark PERF_VFD_MODE_3_FIBERS = 15, 424a69c5ed2SRob Clark PERF_VFD_MODE_4_FIBERS = 16, 425a69c5ed2SRob Clark PERF_VFD_TOTAL_VERTICES = 17, 426a69c5ed2SRob Clark PERF_VFDP_STALL_CYCLES_VFD = 18, 427a69c5ed2SRob Clark PERF_VFDP_STALL_CYCLES_VFD_INDEX = 19, 428a69c5ed2SRob Clark PERF_VFDP_STALL_CYCLES_VFD_PROG = 20, 429a69c5ed2SRob Clark PERF_VFDP_STARVE_CYCLES_PC = 21, 430a69c5ed2SRob Clark PERF_VFDP_VS_STAGE_WAVES = 22, 431a69c5ed2SRob Clark }; 432a69c5ed2SRob Clark 433ccdf7e28SRob Clark enum a6xx_hlsq_perfcounter_select { 434a69c5ed2SRob Clark PERF_HLSQ_BUSY_CYCLES = 0, 435a69c5ed2SRob Clark PERF_HLSQ_STALL_CYCLES_UCHE = 1, 436a69c5ed2SRob Clark PERF_HLSQ_STALL_CYCLES_SP_STATE = 2, 437a69c5ed2SRob Clark PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3, 438a69c5ed2SRob Clark PERF_HLSQ_UCHE_LATENCY_CYCLES = 4, 439a69c5ed2SRob Clark PERF_HLSQ_UCHE_LATENCY_COUNT = 5, 440a69c5ed2SRob Clark PERF_HLSQ_FS_STAGE_1X_WAVES = 6, 441a69c5ed2SRob Clark PERF_HLSQ_FS_STAGE_2X_WAVES = 7, 442a69c5ed2SRob Clark PERF_HLSQ_QUADS = 8, 443a69c5ed2SRob Clark PERF_HLSQ_CS_INVOCATIONS = 9, 444a69c5ed2SRob Clark PERF_HLSQ_COMPUTE_DRAWCALLS = 10, 445a69c5ed2SRob Clark PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11, 446a69c5ed2SRob Clark PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12, 447a69c5ed2SRob Clark PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13, 448a69c5ed2SRob Clark PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14, 449a69c5ed2SRob Clark PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15, 450a69c5ed2SRob Clark PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16, 451a69c5ed2SRob Clark PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17, 452a69c5ed2SRob Clark PERF_HLSQ_STALL_CYCLES_VPC = 18, 453a69c5ed2SRob Clark PERF_HLSQ_PIXELS = 19, 454a69c5ed2SRob Clark PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = 20, 455a69c5ed2SRob Clark }; 456a69c5ed2SRob Clark 457a69c5ed2SRob Clark enum a6xx_vpc_perfcounter_select { 458a69c5ed2SRob Clark PERF_VPC_BUSY_CYCLES = 0, 459a69c5ed2SRob Clark PERF_VPC_WORKING_CYCLES = 1, 460a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_UCHE = 2, 461a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_VFD_WACK = 3, 462a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4, 463a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_PC = 5, 464a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_SP_LM = 6, 465a69c5ed2SRob Clark PERF_VPC_STARVE_CYCLES_SP = 7, 466a69c5ed2SRob Clark PERF_VPC_STARVE_CYCLES_LRZ = 8, 467a69c5ed2SRob Clark PERF_VPC_PC_PRIMITIVES = 9, 468a69c5ed2SRob Clark PERF_VPC_SP_COMPONENTS = 10, 469a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_VPCRAM_POS = 11, 470a69c5ed2SRob Clark PERF_VPC_LRZ_ASSIGN_PRIMITIVES = 12, 471a69c5ed2SRob Clark PERF_VPC_RB_VISIBLE_PRIMITIVES = 13, 472a69c5ed2SRob Clark PERF_VPC_LM_TRANSACTION = 14, 473a69c5ed2SRob Clark PERF_VPC_STREAMOUT_TRANSACTION = 15, 474a69c5ed2SRob Clark PERF_VPC_VS_BUSY_CYCLES = 16, 475a69c5ed2SRob Clark PERF_VPC_PS_BUSY_CYCLES = 17, 476a69c5ed2SRob Clark PERF_VPC_VS_WORKING_CYCLES = 18, 477a69c5ed2SRob Clark PERF_VPC_PS_WORKING_CYCLES = 19, 478a69c5ed2SRob Clark PERF_VPC_STARVE_CYCLES_RB = 20, 479a69c5ed2SRob Clark PERF_VPC_NUM_VPCRAM_READ_POS = 21, 480a69c5ed2SRob Clark PERF_VPC_WIT_FULL_CYCLES = 22, 481a69c5ed2SRob Clark PERF_VPC_VPCRAM_FULL_CYCLES = 23, 482a69c5ed2SRob Clark PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = 24, 483a69c5ed2SRob Clark PERF_VPC_NUM_VPCRAM_WRITE = 25, 484a69c5ed2SRob Clark PERF_VPC_NUM_VPCRAM_READ_SO = 26, 485a69c5ed2SRob Clark PERF_VPC_NUM_ATTR_REQ_LM = 27, 486a69c5ed2SRob Clark }; 487a69c5ed2SRob Clark 488a69c5ed2SRob Clark enum a6xx_tse_perfcounter_select { 489a69c5ed2SRob Clark PERF_TSE_BUSY_CYCLES = 0, 490a69c5ed2SRob Clark PERF_TSE_CLIPPING_CYCLES = 1, 491a69c5ed2SRob Clark PERF_TSE_STALL_CYCLES_RAS = 2, 492a69c5ed2SRob Clark PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3, 493a69c5ed2SRob Clark PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4, 494a69c5ed2SRob Clark PERF_TSE_STARVE_CYCLES_PC = 5, 495a69c5ed2SRob Clark PERF_TSE_INPUT_PRIM = 6, 496a69c5ed2SRob Clark PERF_TSE_INPUT_NULL_PRIM = 7, 497a69c5ed2SRob Clark PERF_TSE_TRIVAL_REJ_PRIM = 8, 498a69c5ed2SRob Clark PERF_TSE_CLIPPED_PRIM = 9, 499a69c5ed2SRob Clark PERF_TSE_ZERO_AREA_PRIM = 10, 500a69c5ed2SRob Clark PERF_TSE_FACENESS_CULLED_PRIM = 11, 501a69c5ed2SRob Clark PERF_TSE_ZERO_PIXEL_PRIM = 12, 502a69c5ed2SRob Clark PERF_TSE_OUTPUT_NULL_PRIM = 13, 503a69c5ed2SRob Clark PERF_TSE_OUTPUT_VISIBLE_PRIM = 14, 504a69c5ed2SRob Clark PERF_TSE_CINVOCATION = 15, 505a69c5ed2SRob Clark PERF_TSE_CPRIMITIVES = 16, 506a69c5ed2SRob Clark PERF_TSE_2D_INPUT_PRIM = 17, 507a69c5ed2SRob Clark PERF_TSE_2D_ALIVE_CYCLES = 18, 508a69c5ed2SRob Clark PERF_TSE_CLIP_PLANES = 19, 509a69c5ed2SRob Clark }; 510a69c5ed2SRob Clark 511a69c5ed2SRob Clark enum a6xx_ras_perfcounter_select { 512a69c5ed2SRob Clark PERF_RAS_BUSY_CYCLES = 0, 513a69c5ed2SRob Clark PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1, 514a69c5ed2SRob Clark PERF_RAS_STALL_CYCLES_LRZ = 2, 515a69c5ed2SRob Clark PERF_RAS_STARVE_CYCLES_TSE = 3, 516a69c5ed2SRob Clark PERF_RAS_SUPER_TILES = 4, 517a69c5ed2SRob Clark PERF_RAS_8X4_TILES = 5, 518a69c5ed2SRob Clark PERF_RAS_MASKGEN_ACTIVE = 6, 519a69c5ed2SRob Clark PERF_RAS_FULLY_COVERED_SUPER_TILES = 7, 520a69c5ed2SRob Clark PERF_RAS_FULLY_COVERED_8X4_TILES = 8, 521a69c5ed2SRob Clark PERF_RAS_PRIM_KILLED_INVISILBE = 9, 522a69c5ed2SRob Clark PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 10, 523a69c5ed2SRob Clark PERF_RAS_LRZ_INTF_WORKING_CYCLES = 11, 524a69c5ed2SRob Clark PERF_RAS_BLOCKS = 12, 525a69c5ed2SRob Clark }; 526a69c5ed2SRob Clark 527a69c5ed2SRob Clark enum a6xx_uche_perfcounter_select { 528a69c5ed2SRob Clark PERF_UCHE_BUSY_CYCLES = 0, 529a69c5ed2SRob Clark PERF_UCHE_STALL_CYCLES_ARBITER = 1, 530a69c5ed2SRob Clark PERF_UCHE_VBIF_LATENCY_CYCLES = 2, 531a69c5ed2SRob Clark PERF_UCHE_VBIF_LATENCY_SAMPLES = 3, 532a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_TP = 4, 533a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_VFD = 5, 534a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6, 535a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_LRZ = 7, 536a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_SP = 8, 537a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_TP = 9, 538a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_VFD = 10, 539a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_HLSQ = 11, 540a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_LRZ = 12, 541a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_SP = 13, 542a69c5ed2SRob Clark PERF_UCHE_WRITE_REQUESTS_LRZ = 14, 543a69c5ed2SRob Clark PERF_UCHE_WRITE_REQUESTS_SP = 15, 544a69c5ed2SRob Clark PERF_UCHE_WRITE_REQUESTS_VPC = 16, 545a69c5ed2SRob Clark PERF_UCHE_WRITE_REQUESTS_VSC = 17, 546a69c5ed2SRob Clark PERF_UCHE_EVICTS = 18, 547a69c5ed2SRob Clark PERF_UCHE_BANK_REQ0 = 19, 548a69c5ed2SRob Clark PERF_UCHE_BANK_REQ1 = 20, 549a69c5ed2SRob Clark PERF_UCHE_BANK_REQ2 = 21, 550a69c5ed2SRob Clark PERF_UCHE_BANK_REQ3 = 22, 551a69c5ed2SRob Clark PERF_UCHE_BANK_REQ4 = 23, 552a69c5ed2SRob Clark PERF_UCHE_BANK_REQ5 = 24, 553a69c5ed2SRob Clark PERF_UCHE_BANK_REQ6 = 25, 554a69c5ed2SRob Clark PERF_UCHE_BANK_REQ7 = 26, 555a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_CH0 = 27, 556a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_CH1 = 28, 557a69c5ed2SRob Clark PERF_UCHE_GMEM_READ_BEATS = 29, 558a69c5ed2SRob Clark PERF_UCHE_TPH_REF_FULL = 30, 559a69c5ed2SRob Clark PERF_UCHE_TPH_VICTIM_FULL = 31, 560a69c5ed2SRob Clark PERF_UCHE_TPH_EXT_FULL = 32, 561a69c5ed2SRob Clark PERF_UCHE_VBIF_STALL_WRITE_DATA = 33, 562a69c5ed2SRob Clark PERF_UCHE_DCMP_LATENCY_SAMPLES = 34, 563a69c5ed2SRob Clark PERF_UCHE_DCMP_LATENCY_CYCLES = 35, 564a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_PC = 36, 565a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_PC = 37, 566a69c5ed2SRob Clark PERF_UCHE_RAM_READ_REQ = 38, 567a69c5ed2SRob Clark PERF_UCHE_RAM_WRITE_REQ = 39, 568a69c5ed2SRob Clark }; 569a69c5ed2SRob Clark 570a69c5ed2SRob Clark enum a6xx_tp_perfcounter_select { 571a69c5ed2SRob Clark PERF_TP_BUSY_CYCLES = 0, 572a69c5ed2SRob Clark PERF_TP_STALL_CYCLES_UCHE = 1, 573a69c5ed2SRob Clark PERF_TP_LATENCY_CYCLES = 2, 574a69c5ed2SRob Clark PERF_TP_LATENCY_TRANS = 3, 575a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4, 576a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5, 577a69c5ed2SRob Clark PERF_TP_L1_CACHELINE_REQUESTS = 6, 578a69c5ed2SRob Clark PERF_TP_L1_CACHELINE_MISSES = 7, 579a69c5ed2SRob Clark PERF_TP_SP_TP_TRANS = 8, 580a69c5ed2SRob Clark PERF_TP_TP_SP_TRANS = 9, 581a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS = 10, 582a69c5ed2SRob Clark PERF_TP_FILTER_WORKLOAD_16BIT = 11, 583a69c5ed2SRob Clark PERF_TP_FILTER_WORKLOAD_32BIT = 12, 584a69c5ed2SRob Clark PERF_TP_QUADS_RECEIVED = 13, 585a69c5ed2SRob Clark PERF_TP_QUADS_OFFSET = 14, 586a69c5ed2SRob Clark PERF_TP_QUADS_SHADOW = 15, 587a69c5ed2SRob Clark PERF_TP_QUADS_ARRAY = 16, 588a69c5ed2SRob Clark PERF_TP_QUADS_GRADIENT = 17, 589a69c5ed2SRob Clark PERF_TP_QUADS_1D = 18, 590a69c5ed2SRob Clark PERF_TP_QUADS_2D = 19, 591a69c5ed2SRob Clark PERF_TP_QUADS_BUFFER = 20, 592a69c5ed2SRob Clark PERF_TP_QUADS_3D = 21, 593a69c5ed2SRob Clark PERF_TP_QUADS_CUBE = 22, 594a69c5ed2SRob Clark PERF_TP_DIVERGENT_QUADS_RECEIVED = 23, 595a69c5ed2SRob Clark PERF_TP_PRT_NON_RESIDENT_EVENTS = 24, 596a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_POINT = 25, 597a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_BILINEAR = 26, 598a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_MIP = 27, 599a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_ANISO = 28, 600a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 29, 601a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_REQUESTS = 30, 602a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_MISSES = 31, 603a69c5ed2SRob Clark PERF_TP_L1_5_L2_REQUESTS = 32, 604a69c5ed2SRob Clark PERF_TP_2D_OUTPUT_PIXELS = 33, 605a69c5ed2SRob Clark PERF_TP_2D_OUTPUT_PIXELS_POINT = 34, 606a69c5ed2SRob Clark PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 35, 607a69c5ed2SRob Clark PERF_TP_2D_FILTER_WORKLOAD_16BIT = 36, 608a69c5ed2SRob Clark PERF_TP_2D_FILTER_WORKLOAD_32BIT = 37, 609a69c5ed2SRob Clark PERF_TP_TPA2TPC_TRANS = 38, 610a69c5ed2SRob Clark PERF_TP_L1_MISSES_ASTC_1TILE = 39, 611a69c5ed2SRob Clark PERF_TP_L1_MISSES_ASTC_2TILE = 40, 612a69c5ed2SRob Clark PERF_TP_L1_MISSES_ASTC_4TILE = 41, 613a69c5ed2SRob Clark PERF_TP_L1_5_L2_COMPRESS_REQS = 42, 614a69c5ed2SRob Clark PERF_TP_L1_5_L2_COMPRESS_MISS = 43, 615a69c5ed2SRob Clark PERF_TP_L1_BANK_CONFLICT = 44, 616a69c5ed2SRob Clark PERF_TP_L1_5_MISS_LATENCY_CYCLES = 45, 617a69c5ed2SRob Clark PERF_TP_L1_5_MISS_LATENCY_TRANS = 46, 618a69c5ed2SRob Clark PERF_TP_QUADS_CONSTANT_MULTIPLIED = 47, 619a69c5ed2SRob Clark PERF_TP_FRONTEND_WORKING_CYCLES = 48, 620a69c5ed2SRob Clark PERF_TP_L1_TAG_WORKING_CYCLES = 49, 621a69c5ed2SRob Clark PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 50, 622a69c5ed2SRob Clark PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 51, 623a69c5ed2SRob Clark PERF_TP_BACKEND_WORKING_CYCLES = 52, 624a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_WORKING_CYCLES = 53, 625a69c5ed2SRob Clark PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54, 626a69c5ed2SRob Clark PERF_TP_STARVE_CYCLES_SP = 55, 627a69c5ed2SRob Clark PERF_TP_STARVE_CYCLES_UCHE = 56, 628a69c5ed2SRob Clark }; 629a69c5ed2SRob Clark 630a69c5ed2SRob Clark enum a6xx_sp_perfcounter_select { 631a69c5ed2SRob Clark PERF_SP_BUSY_CYCLES = 0, 632a69c5ed2SRob Clark PERF_SP_ALU_WORKING_CYCLES = 1, 633a69c5ed2SRob Clark PERF_SP_EFU_WORKING_CYCLES = 2, 634a69c5ed2SRob Clark PERF_SP_STALL_CYCLES_VPC = 3, 635a69c5ed2SRob Clark PERF_SP_STALL_CYCLES_TP = 4, 636a69c5ed2SRob Clark PERF_SP_STALL_CYCLES_UCHE = 5, 637a69c5ed2SRob Clark PERF_SP_STALL_CYCLES_RB = 6, 638a69c5ed2SRob Clark PERF_SP_NON_EXECUTION_CYCLES = 7, 639a69c5ed2SRob Clark PERF_SP_WAVE_CONTEXTS = 8, 640a69c5ed2SRob Clark PERF_SP_WAVE_CONTEXT_CYCLES = 9, 641a69c5ed2SRob Clark PERF_SP_FS_STAGE_WAVE_CYCLES = 10, 642a69c5ed2SRob Clark PERF_SP_FS_STAGE_WAVE_SAMPLES = 11, 643a69c5ed2SRob Clark PERF_SP_VS_STAGE_WAVE_CYCLES = 12, 644a69c5ed2SRob Clark PERF_SP_VS_STAGE_WAVE_SAMPLES = 13, 645a69c5ed2SRob Clark PERF_SP_FS_STAGE_DURATION_CYCLES = 14, 646a69c5ed2SRob Clark PERF_SP_VS_STAGE_DURATION_CYCLES = 15, 647a69c5ed2SRob Clark PERF_SP_WAVE_CTRL_CYCLES = 16, 648a69c5ed2SRob Clark PERF_SP_WAVE_LOAD_CYCLES = 17, 649a69c5ed2SRob Clark PERF_SP_WAVE_EMIT_CYCLES = 18, 650a69c5ed2SRob Clark PERF_SP_WAVE_NOP_CYCLES = 19, 651a69c5ed2SRob Clark PERF_SP_WAVE_WAIT_CYCLES = 20, 652a69c5ed2SRob Clark PERF_SP_WAVE_FETCH_CYCLES = 21, 653a69c5ed2SRob Clark PERF_SP_WAVE_IDLE_CYCLES = 22, 654a69c5ed2SRob Clark PERF_SP_WAVE_END_CYCLES = 23, 655a69c5ed2SRob Clark PERF_SP_WAVE_LONG_SYNC_CYCLES = 24, 656a69c5ed2SRob Clark PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25, 657a69c5ed2SRob Clark PERF_SP_WAVE_JOIN_CYCLES = 26, 658a69c5ed2SRob Clark PERF_SP_LM_LOAD_INSTRUCTIONS = 27, 659a69c5ed2SRob Clark PERF_SP_LM_STORE_INSTRUCTIONS = 28, 660a69c5ed2SRob Clark PERF_SP_LM_ATOMICS = 29, 661a69c5ed2SRob Clark PERF_SP_GM_LOAD_INSTRUCTIONS = 30, 662a69c5ed2SRob Clark PERF_SP_GM_STORE_INSTRUCTIONS = 31, 663a69c5ed2SRob Clark PERF_SP_GM_ATOMICS = 32, 664a69c5ed2SRob Clark PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33, 665a69c5ed2SRob Clark PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34, 666a69c5ed2SRob Clark PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35, 667a69c5ed2SRob Clark PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36, 668a69c5ed2SRob Clark PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37, 669a69c5ed2SRob Clark PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38, 670a69c5ed2SRob Clark PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39, 671a69c5ed2SRob Clark PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40, 672a69c5ed2SRob Clark PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41, 673a69c5ed2SRob Clark PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42, 674a69c5ed2SRob Clark PERF_SP_VS_INSTRUCTIONS = 43, 675a69c5ed2SRob Clark PERF_SP_FS_INSTRUCTIONS = 44, 676a69c5ed2SRob Clark PERF_SP_ADDR_LOCK_COUNT = 45, 677a69c5ed2SRob Clark PERF_SP_UCHE_READ_TRANS = 46, 678a69c5ed2SRob Clark PERF_SP_UCHE_WRITE_TRANS = 47, 679a69c5ed2SRob Clark PERF_SP_EXPORT_VPC_TRANS = 48, 680a69c5ed2SRob Clark PERF_SP_EXPORT_RB_TRANS = 49, 681a69c5ed2SRob Clark PERF_SP_PIXELS_KILLED = 50, 682a69c5ed2SRob Clark PERF_SP_ICL1_REQUESTS = 51, 683a69c5ed2SRob Clark PERF_SP_ICL1_MISSES = 52, 684a69c5ed2SRob Clark PERF_SP_HS_INSTRUCTIONS = 53, 685a69c5ed2SRob Clark PERF_SP_DS_INSTRUCTIONS = 54, 686a69c5ed2SRob Clark PERF_SP_GS_INSTRUCTIONS = 55, 687a69c5ed2SRob Clark PERF_SP_CS_INSTRUCTIONS = 56, 688a69c5ed2SRob Clark PERF_SP_GPR_READ = 57, 689a69c5ed2SRob Clark PERF_SP_GPR_WRITE = 58, 690a69c5ed2SRob Clark PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59, 691a69c5ed2SRob Clark PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60, 692a69c5ed2SRob Clark PERF_SP_LM_BANK_CONFLICTS = 61, 693a69c5ed2SRob Clark PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62, 694a69c5ed2SRob Clark PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63, 695a69c5ed2SRob Clark PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64, 696a69c5ed2SRob Clark PERF_SP_LM_WORKING_CYCLES = 65, 697a69c5ed2SRob Clark PERF_SP_DISPATCHER_WORKING_CYCLES = 66, 698a69c5ed2SRob Clark PERF_SP_SEQUENCER_WORKING_CYCLES = 67, 699a69c5ed2SRob Clark PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68, 700a69c5ed2SRob Clark PERF_SP_STARVE_CYCLES_HLSQ = 69, 701a69c5ed2SRob Clark PERF_SP_NON_EXECUTION_LS_CYCLES = 70, 702a69c5ed2SRob Clark PERF_SP_WORKING_EU = 71, 703a69c5ed2SRob Clark PERF_SP_ANY_EU_WORKING = 72, 704a69c5ed2SRob Clark PERF_SP_WORKING_EU_FS_STAGE = 73, 705a69c5ed2SRob Clark PERF_SP_ANY_EU_WORKING_FS_STAGE = 74, 706a69c5ed2SRob Clark PERF_SP_WORKING_EU_VS_STAGE = 75, 707a69c5ed2SRob Clark PERF_SP_ANY_EU_WORKING_VS_STAGE = 76, 708a69c5ed2SRob Clark PERF_SP_WORKING_EU_CS_STAGE = 77, 709a69c5ed2SRob Clark PERF_SP_ANY_EU_WORKING_CS_STAGE = 78, 710a69c5ed2SRob Clark PERF_SP_GPR_READ_PREFETCH = 79, 711a69c5ed2SRob Clark PERF_SP_GPR_READ_CONFLICT = 80, 712a69c5ed2SRob Clark PERF_SP_GPR_WRITE_CONFLICT = 81, 713a69c5ed2SRob Clark PERF_SP_GM_LOAD_LATENCY_CYCLES = 82, 714a69c5ed2SRob Clark PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83, 715a69c5ed2SRob Clark PERF_SP_EXECUTABLE_WAVES = 84, 716a69c5ed2SRob Clark }; 717a69c5ed2SRob Clark 718a69c5ed2SRob Clark enum a6xx_rb_perfcounter_select { 719a69c5ed2SRob Clark PERF_RB_BUSY_CYCLES = 0, 720a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_HLSQ = 1, 721a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_FIFO0_FULL = 2, 722a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_FIFO1_FULL = 3, 723a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_FIFO2_FULL = 4, 724a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_SP = 5, 725a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_LRZ_TILE = 6, 726a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_CCU = 7, 727a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_Z_PLANE = 8, 728a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_BARY_PLANE = 9, 729a69c5ed2SRob Clark PERF_RB_Z_WORKLOAD = 10, 730a69c5ed2SRob Clark PERF_RB_HLSQ_ACTIVE = 11, 731a69c5ed2SRob Clark PERF_RB_Z_READ = 12, 732a69c5ed2SRob Clark PERF_RB_Z_WRITE = 13, 733a69c5ed2SRob Clark PERF_RB_C_READ = 14, 734a69c5ed2SRob Clark PERF_RB_C_WRITE = 15, 735a69c5ed2SRob Clark PERF_RB_TOTAL_PASS = 16, 736a69c5ed2SRob Clark PERF_RB_Z_PASS = 17, 737a69c5ed2SRob Clark PERF_RB_Z_FAIL = 18, 738a69c5ed2SRob Clark PERF_RB_S_FAIL = 19, 739a69c5ed2SRob Clark PERF_RB_BLENDED_FXP_COMPONENTS = 20, 740a69c5ed2SRob Clark PERF_RB_BLENDED_FP16_COMPONENTS = 21, 741a69c5ed2SRob Clark PERF_RB_PS_INVOCATIONS = 22, 742a69c5ed2SRob Clark PERF_RB_2D_ALIVE_CYCLES = 23, 743a69c5ed2SRob Clark PERF_RB_2D_STALL_CYCLES_A2D = 24, 744a69c5ed2SRob Clark PERF_RB_2D_STARVE_CYCLES_SRC = 25, 745a69c5ed2SRob Clark PERF_RB_2D_STARVE_CYCLES_SP = 26, 746a69c5ed2SRob Clark PERF_RB_2D_STARVE_CYCLES_DST = 27, 747a69c5ed2SRob Clark PERF_RB_2D_VALID_PIXELS = 28, 748a69c5ed2SRob Clark PERF_RB_3D_PIXELS = 29, 749a69c5ed2SRob Clark PERF_RB_BLENDER_WORKING_CYCLES = 30, 750a69c5ed2SRob Clark PERF_RB_ZPROC_WORKING_CYCLES = 31, 751a69c5ed2SRob Clark PERF_RB_CPROC_WORKING_CYCLES = 32, 752a69c5ed2SRob Clark PERF_RB_SAMPLER_WORKING_CYCLES = 33, 753a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 34, 754a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 35, 755a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 36, 756a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 37, 757a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_VPC = 38, 758a69c5ed2SRob Clark PERF_RB_2D_INPUT_TRANS = 39, 759a69c5ed2SRob Clark PERF_RB_2D_OUTPUT_RB_DST_TRANS = 40, 760a69c5ed2SRob Clark PERF_RB_2D_OUTPUT_RB_SRC_TRANS = 41, 761a69c5ed2SRob Clark PERF_RB_BLENDED_FP32_COMPONENTS = 42, 762a69c5ed2SRob Clark PERF_RB_COLOR_PIX_TILES = 43, 763a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU = 44, 764a69c5ed2SRob Clark PERF_RB_EARLY_Z_ARB3_GRANT = 45, 765a69c5ed2SRob Clark PERF_RB_LATE_Z_ARB3_GRANT = 46, 766a69c5ed2SRob Clark PERF_RB_EARLY_Z_SKIP_GRANT = 47, 767a69c5ed2SRob Clark }; 768a69c5ed2SRob Clark 769a69c5ed2SRob Clark enum a6xx_vsc_perfcounter_select { 770a69c5ed2SRob Clark PERF_VSC_BUSY_CYCLES = 0, 771a69c5ed2SRob Clark PERF_VSC_WORKING_CYCLES = 1, 772a69c5ed2SRob Clark PERF_VSC_STALL_CYCLES_UCHE = 2, 773a69c5ed2SRob Clark PERF_VSC_EOT_NUM = 3, 774a69c5ed2SRob Clark PERF_VSC_INPUT_TILES = 4, 775a69c5ed2SRob Clark }; 776a69c5ed2SRob Clark 777a69c5ed2SRob Clark enum a6xx_ccu_perfcounter_select { 778a69c5ed2SRob Clark PERF_CCU_BUSY_CYCLES = 0, 779a69c5ed2SRob Clark PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1, 780a69c5ed2SRob Clark PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2, 781a69c5ed2SRob Clark PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3, 782a69c5ed2SRob Clark PERF_CCU_DEPTH_BLOCKS = 4, 783a69c5ed2SRob Clark PERF_CCU_COLOR_BLOCKS = 5, 784a69c5ed2SRob Clark PERF_CCU_DEPTH_BLOCK_HIT = 6, 785a69c5ed2SRob Clark PERF_CCU_COLOR_BLOCK_HIT = 7, 786a69c5ed2SRob Clark PERF_CCU_PARTIAL_BLOCK_READ = 8, 787a69c5ed2SRob Clark PERF_CCU_GMEM_READ = 9, 788a69c5ed2SRob Clark PERF_CCU_GMEM_WRITE = 10, 789a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11, 790a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12, 791a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13, 792a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14, 793a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15, 794a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG5_COUNT = 16, 795a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG6_COUNT = 17, 796a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG8_COUNT = 18, 797a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG0_COUNT = 19, 798a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG1_COUNT = 20, 799a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG2_COUNT = 21, 800a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG3_COUNT = 22, 801a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG4_COUNT = 23, 802a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG5_COUNT = 24, 803a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG6_COUNT = 25, 804a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG8_COUNT = 26, 805a69c5ed2SRob Clark PERF_CCU_2D_RD_REQ = 27, 806a69c5ed2SRob Clark PERF_CCU_2D_WR_REQ = 28, 807a69c5ed2SRob Clark }; 808a69c5ed2SRob Clark 809a69c5ed2SRob Clark enum a6xx_lrz_perfcounter_select { 810a69c5ed2SRob Clark PERF_LRZ_BUSY_CYCLES = 0, 811a69c5ed2SRob Clark PERF_LRZ_STARVE_CYCLES_RAS = 1, 812a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_RB = 2, 813a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_VSC = 3, 814a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_VPC = 4, 815a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5, 816a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_UCHE = 6, 817a69c5ed2SRob Clark PERF_LRZ_LRZ_READ = 7, 818a69c5ed2SRob Clark PERF_LRZ_LRZ_WRITE = 8, 819a69c5ed2SRob Clark PERF_LRZ_READ_LATENCY = 9, 820a69c5ed2SRob Clark PERF_LRZ_MERGE_CACHE_UPDATING = 10, 821a69c5ed2SRob Clark PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11, 822a69c5ed2SRob Clark PERF_LRZ_PRIM_KILLED_BY_LRZ = 12, 823a69c5ed2SRob Clark PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13, 824a69c5ed2SRob Clark PERF_LRZ_FULL_8X8_TILES = 14, 825a69c5ed2SRob Clark PERF_LRZ_PARTIAL_8X8_TILES = 15, 826a69c5ed2SRob Clark PERF_LRZ_TILE_KILLED = 16, 827a69c5ed2SRob Clark PERF_LRZ_TOTAL_PIXEL = 17, 828a69c5ed2SRob Clark PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18, 829a69c5ed2SRob Clark PERF_LRZ_FULLY_COVERED_TILES = 19, 830a69c5ed2SRob Clark PERF_LRZ_PARTIAL_COVERED_TILES = 20, 831a69c5ed2SRob Clark PERF_LRZ_FEEDBACK_ACCEPT = 21, 832a69c5ed2SRob Clark PERF_LRZ_FEEDBACK_DISCARD = 22, 833a69c5ed2SRob Clark PERF_LRZ_FEEDBACK_STALL = 23, 834a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 24, 835a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_RB_BPLANE = 25, 836a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_VC = 26, 837a69c5ed2SRob Clark PERF_LRZ_RAS_MASK_TRANS = 27, 838a69c5ed2SRob Clark }; 839a69c5ed2SRob Clark 840a69c5ed2SRob Clark enum a6xx_cmp_perfcounter_select { 841a69c5ed2SRob Clark PERF_CMPDECMP_STALL_CYCLES_ARB = 0, 842a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1, 843a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2, 844a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3, 845a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4, 846a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_REQUEST = 5, 847a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6, 848a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_DATA = 7, 849a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_WRITE_DATA = 8, 850a69c5ed2SRob Clark PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9, 851a69c5ed2SRob Clark PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10, 852a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11, 853a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12, 854a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13, 855a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14, 856a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 15, 857a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 16, 858a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 17, 859a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 18, 860a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 19, 861a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 20, 862a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 21, 863a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 22, 864a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 23, 865a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 24, 866a69c5ed2SRob Clark PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 25, 867a69c5ed2SRob Clark PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 26, 868a69c5ed2SRob Clark PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 27, 869a69c5ed2SRob Clark PERF_CMPDECMP_2D_RD_DATA = 28, 870a69c5ed2SRob Clark PERF_CMPDECMP_2D_WR_DATA = 29, 871a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 30, 872a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 31, 873a69c5ed2SRob Clark PERF_CMPDECMP_2D_OUTPUT_TRANS = 32, 874a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 33, 875a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 34, 876a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 35, 877a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 36, 878a69c5ed2SRob Clark PERF_CMPDECMP_2D_BUSY_CYCLES = 37, 879a69c5ed2SRob Clark PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = 38, 880a69c5ed2SRob Clark PERF_CMPDECMP_2D_PIXELS = 39, 8812d756322SRob Clark }; 8822d756322SRob Clark 883c28c82e9SRob Clark enum a6xx_2d_ifmt { 884c28c82e9SRob Clark R2D_UNORM8 = 16, 885c28c82e9SRob Clark R2D_INT32 = 7, 886c28c82e9SRob Clark R2D_INT16 = 6, 887c28c82e9SRob Clark R2D_INT8 = 5, 888c28c82e9SRob Clark R2D_FLOAT32 = 4, 889c28c82e9SRob Clark R2D_FLOAT16 = 3, 890c28c82e9SRob Clark R2D_UNORM8_SRGB = 1, 891c28c82e9SRob Clark R2D_RAW = 0, 892c28c82e9SRob Clark }; 893c28c82e9SRob Clark 894c28c82e9SRob Clark enum a6xx_ztest_mode { 895c28c82e9SRob Clark A6XX_EARLY_Z = 0, 896c28c82e9SRob Clark A6XX_LATE_Z = 1, 897c28c82e9SRob Clark A6XX_EARLY_LRZ_LATE_Z = 2, 898c28c82e9SRob Clark }; 899c28c82e9SRob Clark 900*57cfe41cSRob Clark enum a6xx_sequenced_thread_dist { 901*57cfe41cSRob Clark DIST_SCREEN_COORD = 0, 902*57cfe41cSRob Clark DIST_ALL_TO_RB0 = 1, 903*57cfe41cSRob Clark }; 904*57cfe41cSRob Clark 905*57cfe41cSRob Clark enum a6xx_single_prim_mode { 906*57cfe41cSRob Clark NO_FLUSH = 0, 907*57cfe41cSRob Clark FLUSH_PER_OVERLAP_AND_OVERWRITE = 1, 908*57cfe41cSRob Clark FLUSH_PER_OVERLAP = 3, 909*57cfe41cSRob Clark }; 910*57cfe41cSRob Clark 911*57cfe41cSRob Clark enum a6xx_raster_mode { 912*57cfe41cSRob Clark TYPE_TILED = 0, 913*57cfe41cSRob Clark TYPE_WRITER = 1, 914*57cfe41cSRob Clark }; 915*57cfe41cSRob Clark 916*57cfe41cSRob Clark enum a6xx_raster_direction { 917*57cfe41cSRob Clark LR_TB = 0, 918*57cfe41cSRob Clark RL_TB = 1, 919*57cfe41cSRob Clark LR_BT = 2, 920*57cfe41cSRob Clark RB_BT = 3, 921*57cfe41cSRob Clark }; 922*57cfe41cSRob Clark 923*57cfe41cSRob Clark enum a6xx_render_mode { 924*57cfe41cSRob Clark RENDERING_PASS = 0, 925*57cfe41cSRob Clark BINNING_PASS = 1, 926*57cfe41cSRob Clark }; 927*57cfe41cSRob Clark 928*57cfe41cSRob Clark enum a6xx_buffers_location { 929*57cfe41cSRob Clark BUFFERS_IN_GMEM = 0, 930*57cfe41cSRob Clark BUFFERS_IN_SYSMEM = 3, 931*57cfe41cSRob Clark }; 932*57cfe41cSRob Clark 933*57cfe41cSRob Clark enum a6xx_fragcoord_sample_mode { 934*57cfe41cSRob Clark FRAGCOORD_CENTER = 0, 935*57cfe41cSRob Clark FRAGCOORD_SAMPLE = 3, 936*57cfe41cSRob Clark }; 937*57cfe41cSRob Clark 938c28c82e9SRob Clark enum a6xx_rotation { 939c28c82e9SRob Clark ROTATE_0 = 0, 940c28c82e9SRob Clark ROTATE_90 = 1, 941c28c82e9SRob Clark ROTATE_180 = 2, 942c28c82e9SRob Clark ROTATE_270 = 3, 943c28c82e9SRob Clark ROTATE_HFLIP = 4, 944c28c82e9SRob Clark ROTATE_VFLIP = 5, 945c28c82e9SRob Clark }; 946c28c82e9SRob Clark 947c28c82e9SRob Clark enum a6xx_tess_spacing { 948c28c82e9SRob Clark TESS_EQUAL = 0, 949c28c82e9SRob Clark TESS_FRACTIONAL_ODD = 2, 950c28c82e9SRob Clark TESS_FRACTIONAL_EVEN = 3, 951c28c82e9SRob Clark }; 952c28c82e9SRob Clark 953c28c82e9SRob Clark enum a6xx_tess_output { 954c28c82e9SRob Clark TESS_POINTS = 0, 955c28c82e9SRob Clark TESS_LINES = 1, 956c28c82e9SRob Clark TESS_CW_TRIS = 2, 957c28c82e9SRob Clark TESS_CCW_TRIS = 3, 958c28c82e9SRob Clark }; 959c28c82e9SRob Clark 960cc4c26d4SRob Clark enum a6xx_threadsize { 961cc4c26d4SRob Clark THREAD64 = 0, 962cc4c26d4SRob Clark THREAD128 = 1, 963cc4c26d4SRob Clark }; 964cc4c26d4SRob Clark 965*57cfe41cSRob Clark enum a6xx_isam_mode { 966*57cfe41cSRob Clark ISAMMODE_GL = 2, 967*57cfe41cSRob Clark }; 968*57cfe41cSRob Clark 9692d756322SRob Clark enum a6xx_tex_filter { 9702d756322SRob Clark A6XX_TEX_NEAREST = 0, 9712d756322SRob Clark A6XX_TEX_LINEAR = 1, 9722d756322SRob Clark A6XX_TEX_ANISO = 2, 973c28c82e9SRob Clark A6XX_TEX_CUBIC = 3, 9742d756322SRob Clark }; 9752d756322SRob Clark 9762d756322SRob Clark enum a6xx_tex_clamp { 9772d756322SRob Clark A6XX_TEX_REPEAT = 0, 9782d756322SRob Clark A6XX_TEX_CLAMP_TO_EDGE = 1, 9792d756322SRob Clark A6XX_TEX_MIRROR_REPEAT = 2, 9802d756322SRob Clark A6XX_TEX_CLAMP_TO_BORDER = 3, 9812d756322SRob Clark A6XX_TEX_MIRROR_CLAMP = 4, 9822d756322SRob Clark }; 9832d756322SRob Clark 9842d756322SRob Clark enum a6xx_tex_aniso { 9852d756322SRob Clark A6XX_TEX_ANISO_1 = 0, 9862d756322SRob Clark A6XX_TEX_ANISO_2 = 1, 9872d756322SRob Clark A6XX_TEX_ANISO_4 = 2, 9882d756322SRob Clark A6XX_TEX_ANISO_8 = 3, 9892d756322SRob Clark A6XX_TEX_ANISO_16 = 4, 9902d756322SRob Clark }; 9912d756322SRob Clark 992c28c82e9SRob Clark enum a6xx_reduction_mode { 993c28c82e9SRob Clark A6XX_REDUCTION_MODE_AVERAGE = 0, 994c28c82e9SRob Clark A6XX_REDUCTION_MODE_MIN = 1, 995c28c82e9SRob Clark A6XX_REDUCTION_MODE_MAX = 2, 996c28c82e9SRob Clark }; 997c28c82e9SRob Clark 9982d756322SRob Clark enum a6xx_tex_swiz { 9992d756322SRob Clark A6XX_TEX_X = 0, 10002d756322SRob Clark A6XX_TEX_Y = 1, 10012d756322SRob Clark A6XX_TEX_Z = 2, 10022d756322SRob Clark A6XX_TEX_W = 3, 10032d756322SRob Clark A6XX_TEX_ZERO = 4, 10042d756322SRob Clark A6XX_TEX_ONE = 5, 10052d756322SRob Clark }; 10062d756322SRob Clark 10072d756322SRob Clark enum a6xx_tex_type { 10082d756322SRob Clark A6XX_TEX_1D = 0, 10092d756322SRob Clark A6XX_TEX_2D = 1, 10102d756322SRob Clark A6XX_TEX_CUBE = 2, 10112d756322SRob Clark A6XX_TEX_3D = 3, 1012*57cfe41cSRob Clark A6XX_TEX_BUFFER = 4, 10132d756322SRob Clark }; 10142d756322SRob Clark 10152d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001 10162d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR 0x00000002 10172d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW 0x00000040 10182d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080 10192d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_SW 0x00000100 10202d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200 10212d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400 10222d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800 10232d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000 10242d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_IB2 0x00002000 10252d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_IB1 0x00004000 10262d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_RB 0x00008000 10272d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000 10282d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000 10292d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000 10302d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000 10312d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT 0x00800000 10322d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000 10332d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000 10342d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000 10352d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000 10362d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000 10372d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000 10382d756322SRob Clark #define A6XX_CP_INT_CP_OPCODE_ERROR 0x00000001 10392d756322SRob Clark #define A6XX_CP_INT_CP_UCODE_ERROR 0x00000002 10402d756322SRob Clark #define A6XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004 10412d756322SRob Clark #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010 10422d756322SRob Clark #define A6XX_CP_INT_CP_AHB_ERROR 0x00000020 10432d756322SRob Clark #define A6XX_CP_INT_CP_VSD_PARITY_ERROR 0x00000040 10442d756322SRob Clark #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR 0x00000080 10452d756322SRob Clark #define REG_A6XX_CP_RB_BASE 0x00000800 10462d756322SRob Clark 10472d756322SRob Clark #define REG_A6XX_CP_RB_BASE_HI 0x00000801 10482d756322SRob Clark 10492d756322SRob Clark #define REG_A6XX_CP_RB_CNTL 0x00000802 10502d756322SRob Clark 10512d756322SRob Clark #define REG_A6XX_CP_RB_RPTR_ADDR_LO 0x00000804 10522d756322SRob Clark 10532d756322SRob Clark #define REG_A6XX_CP_RB_RPTR_ADDR_HI 0x00000805 10542d756322SRob Clark 10552d756322SRob Clark #define REG_A6XX_CP_RB_RPTR 0x00000806 10562d756322SRob Clark 10572d756322SRob Clark #define REG_A6XX_CP_RB_WPTR 0x00000807 10582d756322SRob Clark 10592d756322SRob Clark #define REG_A6XX_CP_SQE_CNTL 0x00000808 10602d756322SRob Clark 1061c28c82e9SRob Clark #define REG_A6XX_CP_CP2GMU_STATUS 0x00000812 1062c28c82e9SRob Clark #define A6XX_CP_CP2GMU_STATUS_IFPC 0x00000001 1063c28c82e9SRob Clark 10642d756322SRob Clark #define REG_A6XX_CP_HW_FAULT 0x00000821 10652d756322SRob Clark 10662d756322SRob Clark #define REG_A6XX_CP_INTERRUPT_STATUS 0x00000823 10672d756322SRob Clark 10682d756322SRob Clark #define REG_A6XX_CP_PROTECT_STATUS 0x00000824 10692d756322SRob Clark 1070cc4c26d4SRob Clark #define REG_A6XX_CP_SQE_INSTR_BASE 0x00000830 10712d756322SRob Clark 10722d756322SRob Clark #define REG_A6XX_CP_MISC_CNTL 0x00000840 10732d756322SRob Clark 107424e6938eSJonathan Marek #define REG_A6XX_CP_APRIV_CNTL 0x00000844 107524e6938eSJonathan Marek 10762d756322SRob Clark #define REG_A6XX_CP_ROQ_THRESHOLDS_1 0x000008c1 1077c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK 0x000000ff 1078c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT 0 1079c28c82e9SRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_LO(uint32_t val) 1080c28c82e9SRob Clark { 1081c28c82e9SRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK; 1082c28c82e9SRob Clark } 1083c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MASK 0x0000ff00 1084c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__SHIFT 8 1085c28c82e9SRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_HI(uint32_t val) 1086c28c82e9SRob Clark { 1087c28c82e9SRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MASK; 1088c28c82e9SRob Clark } 1089c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK 0x00ff0000 1090c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT 16 1091c28c82e9SRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val) 1092c28c82e9SRob Clark { 1093c28c82e9SRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK; 1094c28c82e9SRob Clark } 1095c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK 0xff000000 1096c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT 24 1097c28c82e9SRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val) 1098c28c82e9SRob Clark { 1099c28c82e9SRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK; 1100c28c82e9SRob Clark } 11012d756322SRob Clark 11022d756322SRob Clark #define REG_A6XX_CP_ROQ_THRESHOLDS_2 0x000008c2 1103c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK 0x000001ff 1104c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT 0 1105c28c82e9SRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val) 1106c28c82e9SRob Clark { 1107c28c82e9SRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK; 1108c28c82e9SRob Clark } 1109c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK 0xffff0000 1110c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT 16 1111c28c82e9SRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val) 1112c28c82e9SRob Clark { 1113c28c82e9SRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK; 1114c28c82e9SRob Clark } 11152d756322SRob Clark 11162d756322SRob Clark #define REG_A6XX_CP_MEM_POOL_SIZE 0x000008c3 11172d756322SRob Clark 11182d756322SRob Clark #define REG_A6XX_CP_CHICKEN_DBG 0x00000841 11192d756322SRob Clark 11202d756322SRob Clark #define REG_A6XX_CP_ADDR_MODE_CNTL 0x00000842 11212d756322SRob Clark 11222d756322SRob Clark #define REG_A6XX_CP_DBG_ECO_CNTL 0x00000843 11232d756322SRob Clark 11242d756322SRob Clark #define REG_A6XX_CP_PROTECT_CNTL 0x0000084f 11252d756322SRob Clark 11262d756322SRob Clark static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; } 11272d756322SRob Clark 11282d756322SRob Clark static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; } 11292d756322SRob Clark 11302d756322SRob Clark static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; } 11312d756322SRob Clark 11322d756322SRob Clark static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; } 11332d756322SRob Clark #define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0003ffff 11342d756322SRob Clark #define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0 11352d756322SRob Clark static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) 11362d756322SRob Clark { 11372d756322SRob Clark return ((val) << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK; 11382d756322SRob Clark } 11392d756322SRob Clark #define A6XX_CP_PROTECT_REG_MASK_LEN__MASK 0x7ffc0000 11402d756322SRob Clark #define A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT 18 11412d756322SRob Clark static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) 11422d756322SRob Clark { 11432d756322SRob Clark return ((val) << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK; 11442d756322SRob Clark } 11452d756322SRob Clark #define A6XX_CP_PROTECT_REG_READ 0x80000000 11462d756322SRob Clark 11472d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_CNTL 0x000008a0 11482d756322SRob Clark 11492d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x000008a1 11502d756322SRob Clark 11512d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x000008a2 11522d756322SRob Clark 11532d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO 0x000008a3 11542d756322SRob Clark 11552d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI 0x000008a4 11562d756322SRob Clark 11572d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO 0x000008a5 11582d756322SRob Clark 11592d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI 0x000008a6 11602d756322SRob Clark 11612d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO 0x000008a7 11622d756322SRob Clark 11632d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI 0x000008a8 11642d756322SRob Clark 1165cc4c26d4SRob Clark static inline uint32_t REG_A6XX_CP_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008d0 + 0x1*i0; } 11662d756322SRob Clark 11672d756322SRob Clark #define REG_A6XX_CP_CRASH_SCRIPT_BASE_LO 0x00000900 11682d756322SRob Clark 11692d756322SRob Clark #define REG_A6XX_CP_CRASH_SCRIPT_BASE_HI 0x00000901 11702d756322SRob Clark 11712d756322SRob Clark #define REG_A6XX_CP_CRASH_DUMP_CNTL 0x00000902 11722d756322SRob Clark 11732d756322SRob Clark #define REG_A6XX_CP_CRASH_DUMP_STATUS 0x00000903 11742d756322SRob Clark 11752d756322SRob Clark #define REG_A6XX_CP_SQE_STAT_ADDR 0x00000908 11762d756322SRob Clark 11772d756322SRob Clark #define REG_A6XX_CP_SQE_STAT_DATA 0x00000909 11782d756322SRob Clark 11792d756322SRob Clark #define REG_A6XX_CP_DRAW_STATE_ADDR 0x0000090a 11802d756322SRob Clark 11812d756322SRob Clark #define REG_A6XX_CP_DRAW_STATE_DATA 0x0000090b 11822d756322SRob Clark 11832d756322SRob Clark #define REG_A6XX_CP_ROQ_DBG_ADDR 0x0000090c 11842d756322SRob Clark 11852d756322SRob Clark #define REG_A6XX_CP_ROQ_DBG_DATA 0x0000090d 11862d756322SRob Clark 11872d756322SRob Clark #define REG_A6XX_CP_MEM_POOL_DBG_ADDR 0x0000090e 11882d756322SRob Clark 11892d756322SRob Clark #define REG_A6XX_CP_MEM_POOL_DBG_DATA 0x0000090f 11902d756322SRob Clark 11912d756322SRob Clark #define REG_A6XX_CP_SQE_UCODE_DBG_ADDR 0x00000910 11922d756322SRob Clark 11932d756322SRob Clark #define REG_A6XX_CP_SQE_UCODE_DBG_DATA 0x00000911 11942d756322SRob Clark 11952d756322SRob Clark #define REG_A6XX_CP_IB1_BASE 0x00000928 11962d756322SRob Clark 11972d756322SRob Clark #define REG_A6XX_CP_IB1_BASE_HI 0x00000929 11982d756322SRob Clark 11992d756322SRob Clark #define REG_A6XX_CP_IB1_REM_SIZE 0x0000092a 12002d756322SRob Clark 12012d756322SRob Clark #define REG_A6XX_CP_IB2_BASE 0x0000092b 12022d756322SRob Clark 12032d756322SRob Clark #define REG_A6XX_CP_IB2_BASE_HI 0x0000092c 12042d756322SRob Clark 12052d756322SRob Clark #define REG_A6XX_CP_IB2_REM_SIZE 0x0000092d 12062d756322SRob Clark 1207c28c82e9SRob Clark #define REG_A6XX_CP_SDS_BASE 0x0000092e 1208c28c82e9SRob Clark 1209c28c82e9SRob Clark #define REG_A6XX_CP_SDS_BASE_HI 0x0000092f 1210c28c82e9SRob Clark 1211cc4c26d4SRob Clark #define REG_A6XX_CP_SDS_REM_SIZE 0x00000930 1212c28c82e9SRob Clark 1213cc4c26d4SRob Clark #define REG_A6XX_CP_MRB_BASE 0x00000931 1214c28c82e9SRob Clark 1215cc4c26d4SRob Clark #define REG_A6XX_CP_MRB_BASE_HI 0x00000932 1216c28c82e9SRob Clark 1217cc4c26d4SRob Clark #define REG_A6XX_CP_MRB_REM_SIZE 0x00000933 1218c28c82e9SRob Clark 1219cc4c26d4SRob Clark #define REG_A6XX_CP_VSD_BASE 0x00000934 1220cc4c26d4SRob Clark 1221cc4c26d4SRob Clark #define REG_A6XX_CP_VSD_BASE_HI 0x00000935 1222cc4c26d4SRob Clark 1223cc4c26d4SRob Clark #define REG_A6XX_CP_MRB_DWORDS 0x00000946 1224cc4c26d4SRob Clark 1225cc4c26d4SRob Clark #define REG_A6XX_CP_VSD_DWORDS 0x00000947 1226c28c82e9SRob Clark 1227c28c82e9SRob Clark #define REG_A6XX_CP_CSQ_IB1_STAT 0x00000949 1228c28c82e9SRob Clark #define A6XX_CP_CSQ_IB1_STAT_REM__MASK 0xffff0000 1229c28c82e9SRob Clark #define A6XX_CP_CSQ_IB1_STAT_REM__SHIFT 16 1230c28c82e9SRob Clark static inline uint32_t A6XX_CP_CSQ_IB1_STAT_REM(uint32_t val) 1231c28c82e9SRob Clark { 1232c28c82e9SRob Clark return ((val) << A6XX_CP_CSQ_IB1_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB1_STAT_REM__MASK; 1233c28c82e9SRob Clark } 1234c28c82e9SRob Clark 1235c28c82e9SRob Clark #define REG_A6XX_CP_CSQ_IB2_STAT 0x0000094a 1236c28c82e9SRob Clark #define A6XX_CP_CSQ_IB2_STAT_REM__MASK 0xffff0000 1237c28c82e9SRob Clark #define A6XX_CP_CSQ_IB2_STAT_REM__SHIFT 16 1238c28c82e9SRob Clark static inline uint32_t A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val) 1239c28c82e9SRob Clark { 1240c28c82e9SRob Clark return ((val) << A6XX_CP_CSQ_IB2_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB2_STAT_REM__MASK; 1241c28c82e9SRob Clark } 1242c28c82e9SRob Clark 1243cc4c26d4SRob Clark #define REG_A6XX_CP_MRQ_MRB_STAT 0x0000094c 1244cc4c26d4SRob Clark #define A6XX_CP_MRQ_MRB_STAT_REM__MASK 0xffff0000 1245cc4c26d4SRob Clark #define A6XX_CP_MRQ_MRB_STAT_REM__SHIFT 16 1246cc4c26d4SRob Clark static inline uint32_t A6XX_CP_MRQ_MRB_STAT_REM(uint32_t val) 1247cc4c26d4SRob Clark { 1248cc4c26d4SRob Clark return ((val) << A6XX_CP_MRQ_MRB_STAT_REM__SHIFT) & A6XX_CP_MRQ_MRB_STAT_REM__MASK; 1249cc4c26d4SRob Clark } 1250cc4c26d4SRob Clark 12512d756322SRob Clark #define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO 0x00000980 12522d756322SRob Clark 12532d756322SRob Clark #define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI 0x00000981 12542d756322SRob Clark 12552d756322SRob Clark #define REG_A6XX_CP_AHB_CNTL 0x0000098d 12562d756322SRob Clark 12572d756322SRob Clark #define REG_A6XX_CP_APERTURE_CNTL_HOST 0x00000a00 12582d756322SRob Clark 12592d756322SRob Clark #define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03 12602d756322SRob Clark 1261cc4c26d4SRob Clark #define REG_A6XX_CP_LPAC_PROG_FIFO_SIZE 0x00000b34 1262cc4c26d4SRob Clark 1263cc4c26d4SRob Clark #define REG_A6XX_CP_LPAC_SQE_INSTR_BASE 0x00000b82 1264cc4c26d4SRob Clark 12652d756322SRob Clark #define REG_A6XX_VSC_ADDR_MODE_CNTL 0x00000c01 12662d756322SRob Clark 12672d756322SRob Clark #define REG_A6XX_RBBM_INT_0_STATUS 0x00000201 12682d756322SRob Clark 12692d756322SRob Clark #define REG_A6XX_RBBM_STATUS 0x00000210 12702d756322SRob Clark #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x00800000 12712d756322SRob Clark #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x00400000 12722d756322SRob Clark #define A6XX_RBBM_STATUS_HLSQ_BUSY 0x00200000 12732d756322SRob Clark #define A6XX_RBBM_STATUS_VSC_BUSY 0x00100000 12742d756322SRob Clark #define A6XX_RBBM_STATUS_TPL1_BUSY 0x00080000 12752d756322SRob Clark #define A6XX_RBBM_STATUS_SP_BUSY 0x00040000 12762d756322SRob Clark #define A6XX_RBBM_STATUS_UCHE_BUSY 0x00020000 12772d756322SRob Clark #define A6XX_RBBM_STATUS_VPC_BUSY 0x00010000 12782d756322SRob Clark #define A6XX_RBBM_STATUS_VFD_BUSY 0x00008000 12792d756322SRob Clark #define A6XX_RBBM_STATUS_TESS_BUSY 0x00004000 12802d756322SRob Clark #define A6XX_RBBM_STATUS_PC_VSD_BUSY 0x00002000 12812d756322SRob Clark #define A6XX_RBBM_STATUS_PC_DCALL_BUSY 0x00001000 12822d756322SRob Clark #define A6XX_RBBM_STATUS_COM_DCOM_BUSY 0x00000800 12832d756322SRob Clark #define A6XX_RBBM_STATUS_LRZ_BUSY 0x00000400 12842d756322SRob Clark #define A6XX_RBBM_STATUS_A2D_BUSY 0x00000200 12852d756322SRob Clark #define A6XX_RBBM_STATUS_CCU_BUSY 0x00000100 12862d756322SRob Clark #define A6XX_RBBM_STATUS_RB_BUSY 0x00000080 12872d756322SRob Clark #define A6XX_RBBM_STATUS_RAS_BUSY 0x00000040 12882d756322SRob Clark #define A6XX_RBBM_STATUS_TSE_BUSY 0x00000020 12892d756322SRob Clark #define A6XX_RBBM_STATUS_VBIF_BUSY 0x00000010 12902d756322SRob Clark #define A6XX_RBBM_STATUS_GFX_DBGC_BUSY 0x00000008 12912d756322SRob Clark #define A6XX_RBBM_STATUS_CP_BUSY 0x00000004 12922d756322SRob Clark #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER 0x00000002 12932d756322SRob Clark #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER 0x00000001 12942d756322SRob Clark 12952d756322SRob Clark #define REG_A6XX_RBBM_STATUS3 0x00000213 1296c28c82e9SRob Clark #define A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT 0x01000000 12972d756322SRob Clark 12982d756322SRob Clark #define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215 12992d756322SRob Clark 1300cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000400 + 0x2*i0; } 13012d756322SRob Clark 1302cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000041c + 0x2*i0; } 13032d756322SRob Clark 1304cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000424 + 0x2*i0; } 13052d756322SRob Clark 1306cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000434 + 0x2*i0; } 13072d756322SRob Clark 1308cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000444 + 0x2*i0; } 13092d756322SRob Clark 1310cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000450 + 0x2*i0; } 13112d756322SRob Clark 1312cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000045c + 0x2*i0; } 13132d756322SRob Clark 1314cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000466 + 0x2*i0; } 13152d756322SRob Clark 1316cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000046e + 0x2*i0; } 13172d756322SRob Clark 1318cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000476 + 0x2*i0; } 13192d756322SRob Clark 1320cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000048e + 0x2*i0; } 13212d756322SRob Clark 1322cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000004a6 + 0x2*i0; } 13232d756322SRob Clark 1324cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000004d6 + 0x2*i0; } 13252d756322SRob Clark 1326cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000004e6 + 0x2*i0; } 13272d756322SRob Clark 1328cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000004ea + 0x2*i0; } 13292d756322SRob Clark 1330cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000004f2 + 0x2*i0; } 13312d756322SRob Clark 13322d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500 13332d756322SRob Clark 13342d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 0x00000501 13352d756322SRob Clark 13362d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 0x00000502 13372d756322SRob Clark 13382d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 0x00000503 13392d756322SRob Clark 13402d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 0x00000504 13412d756322SRob Clark 13422d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000505 13432d756322SRob Clark 13442d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506 13452d756322SRob Clark 1346cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00000507 + 0x1*i0; } 13472d756322SRob Clark 13482d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b 13492d756322SRob Clark 1350*57cfe41cSRob Clark #define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD 0x0000050e 1351*57cfe41cSRob Clark 1352*57cfe41cSRob Clark #define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS 0x0000050f 1353*57cfe41cSRob Clark 13542d756322SRob Clark #define REG_A6XX_RBBM_ISDB_CNT 0x00000533 13552d756322SRob Clark 1356c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_0_LO 0x00000540 1357c28c82e9SRob Clark 1358c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_0_HI 0x00000541 1359c28c82e9SRob Clark 1360c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_1_LO 0x00000542 1361c28c82e9SRob Clark 1362c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_1_HI 0x00000543 1363c28c82e9SRob Clark 1364c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_2_LO 0x00000544 1365c28c82e9SRob Clark 1366c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_2_HI 0x00000545 1367c28c82e9SRob Clark 1368c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_3_LO 0x00000546 1369c28c82e9SRob Clark 1370c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_3_HI 0x00000547 1371c28c82e9SRob Clark 1372c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_4_LO 0x00000548 1373c28c82e9SRob Clark 1374c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_4_HI 0x00000549 1375c28c82e9SRob Clark 1376c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_5_LO 0x0000054a 1377c28c82e9SRob Clark 1378c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_5_HI 0x0000054b 1379c28c82e9SRob Clark 1380c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_6_LO 0x0000054c 1381c28c82e9SRob Clark 1382c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_6_HI 0x0000054d 1383c28c82e9SRob Clark 1384c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_7_LO 0x0000054e 1385c28c82e9SRob Clark 1386c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_7_HI 0x0000054f 1387c28c82e9SRob Clark 1388c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_8_LO 0x00000550 1389c28c82e9SRob Clark 1390c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_8_HI 0x00000551 1391c28c82e9SRob Clark 1392c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_9_LO 0x00000552 1393c28c82e9SRob Clark 1394c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_9_HI 0x00000553 1395c28c82e9SRob Clark 1396c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_10_LO 0x00000554 1397c28c82e9SRob Clark 1398c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_10_HI 0x00000555 1399c28c82e9SRob Clark 14002d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TRUST_CNTL 0x0000f400 14012d756322SRob Clark 14022d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800 14032d756322SRob Clark 14042d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801 14052d756322SRob Clark 14062d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802 14072d756322SRob Clark 14082d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_CNTL 0x0000f803 14092d756322SRob Clark 14102d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810 14112d756322SRob Clark 14122d756322SRob Clark #define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL 0x00000010 14132d756322SRob Clark 141424e6938eSJonathan Marek #define REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL 0x00000011 141524e6938eSJonathan Marek 1416c28c82e9SRob Clark #define REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD 0x0000001c 1417c28c82e9SRob Clark #define A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE 0x00000001 1418c28c82e9SRob Clark 14192d756322SRob Clark #define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000001f 14202d756322SRob Clark 14212d756322SRob Clark #define REG_A6XX_RBBM_INT_CLEAR_CMD 0x00000037 14222d756322SRob Clark 14232d756322SRob Clark #define REG_A6XX_RBBM_INT_0_MASK 0x00000038 14242d756322SRob Clark 14252d756322SRob Clark #define REG_A6XX_RBBM_SP_HYST_CNT 0x00000042 14262d756322SRob Clark 14272d756322SRob Clark #define REG_A6XX_RBBM_SW_RESET_CMD 0x00000043 14282d756322SRob Clark 14292d756322SRob Clark #define REG_A6XX_RBBM_RAC_THRESHOLD_CNT 0x00000044 14302d756322SRob Clark 14312d756322SRob Clark #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 14322d756322SRob Clark 14332d756322SRob Clark #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046 14342d756322SRob Clark 14352d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae 14362d756322SRob Clark 14372d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0 14382d756322SRob Clark 14392d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_SP1 0x000000b1 14402d756322SRob Clark 14412d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_SP2 0x000000b2 14422d756322SRob Clark 14432d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_SP3 0x000000b3 14442d756322SRob Clark 14452d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_SP0 0x000000b4 14462d756322SRob Clark 14472d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_SP1 0x000000b5 14482d756322SRob Clark 14492d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_SP2 0x000000b6 14502d756322SRob Clark 14512d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_SP3 0x000000b7 14522d756322SRob Clark 14532d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_SP0 0x000000b8 14542d756322SRob Clark 14552d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_SP1 0x000000b9 14562d756322SRob Clark 14572d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_SP2 0x000000ba 14582d756322SRob Clark 14592d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_SP3 0x000000bb 14602d756322SRob Clark 14612d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_SP0 0x000000bc 14622d756322SRob Clark 14632d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_SP1 0x000000bd 14642d756322SRob Clark 14652d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_SP2 0x000000be 14662d756322SRob Clark 14672d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_SP3 0x000000bf 14682d756322SRob Clark 14692d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TP0 0x000000c0 14702d756322SRob Clark 14712d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TP1 0x000000c1 14722d756322SRob Clark 14732d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TP2 0x000000c2 14742d756322SRob Clark 14752d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TP3 0x000000c3 14762d756322SRob Clark 14772d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_TP0 0x000000c4 14782d756322SRob Clark 14792d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_TP1 0x000000c5 14802d756322SRob Clark 14812d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_TP2 0x000000c6 14822d756322SRob Clark 14832d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_TP3 0x000000c7 14842d756322SRob Clark 14852d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_TP0 0x000000c8 14862d756322SRob Clark 14872d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_TP1 0x000000c9 14882d756322SRob Clark 14892d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_TP2 0x000000ca 14902d756322SRob Clark 14912d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_TP3 0x000000cb 14922d756322SRob Clark 14932d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_TP0 0x000000cc 14942d756322SRob Clark 14952d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_TP1 0x000000cd 14962d756322SRob Clark 14972d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_TP2 0x000000ce 14982d756322SRob Clark 14992d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_TP3 0x000000cf 15002d756322SRob Clark 15012d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TP0 0x000000d0 15022d756322SRob Clark 15032d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TP1 0x000000d1 15042d756322SRob Clark 15052d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TP2 0x000000d2 15062d756322SRob Clark 15072d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TP3 0x000000d3 15082d756322SRob Clark 15092d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY2_TP0 0x000000d4 15102d756322SRob Clark 15112d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY2_TP1 0x000000d5 15122d756322SRob Clark 15132d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY2_TP2 0x000000d6 15142d756322SRob Clark 15152d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY2_TP3 0x000000d7 15162d756322SRob Clark 15172d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY3_TP0 0x000000d8 15182d756322SRob Clark 15192d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY3_TP1 0x000000d9 15202d756322SRob Clark 15212d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY3_TP2 0x000000da 15222d756322SRob Clark 15232d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY3_TP3 0x000000db 15242d756322SRob Clark 15252d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY4_TP0 0x000000dc 15262d756322SRob Clark 15272d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY4_TP1 0x000000dd 15282d756322SRob Clark 15292d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY4_TP2 0x000000de 15302d756322SRob Clark 15312d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY4_TP3 0x000000df 15322d756322SRob Clark 15332d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TP0 0x000000e0 15342d756322SRob Clark 15352d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TP1 0x000000e1 15362d756322SRob Clark 15372d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TP2 0x000000e2 15382d756322SRob Clark 15392d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TP3 0x000000e3 15402d756322SRob Clark 15412d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST2_TP0 0x000000e4 15422d756322SRob Clark 15432d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST2_TP1 0x000000e5 15442d756322SRob Clark 15452d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST2_TP2 0x000000e6 15462d756322SRob Clark 15472d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST2_TP3 0x000000e7 15482d756322SRob Clark 15492d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST3_TP0 0x000000e8 15502d756322SRob Clark 15512d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST3_TP1 0x000000e9 15522d756322SRob Clark 15532d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST3_TP2 0x000000ea 15542d756322SRob Clark 15552d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST3_TP3 0x000000eb 15562d756322SRob Clark 15572d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST4_TP0 0x000000ec 15582d756322SRob Clark 15592d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST4_TP1 0x000000ed 15602d756322SRob Clark 15612d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST4_TP2 0x000000ee 15622d756322SRob Clark 15632d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST4_TP3 0x000000ef 15642d756322SRob Clark 15652d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RB0 0x000000f0 15662d756322SRob Clark 15672d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RB1 0x000000f1 15682d756322SRob Clark 15692d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RB2 0x000000f2 15702d756322SRob Clark 15712d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RB3 0x000000f3 15722d756322SRob Clark 15732d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RB0 0x000000f4 15742d756322SRob Clark 15752d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RB1 0x000000f5 15762d756322SRob Clark 15772d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RB2 0x000000f6 15782d756322SRob Clark 15792d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RB3 0x000000f7 15802d756322SRob Clark 15812d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_CCU0 0x000000f8 15822d756322SRob Clark 15832d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_CCU1 0x000000f9 15842d756322SRob Clark 15852d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_CCU2 0x000000fa 15862d756322SRob Clark 15872d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_CCU3 0x000000fb 15882d756322SRob Clark 15892d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000100 15902d756322SRob Clark 15912d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000101 15922d756322SRob Clark 15932d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000102 15942d756322SRob Clark 15952d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000103 15962d756322SRob Clark 15972d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RAC 0x00000104 15982d756322SRob Clark 15992d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RAC 0x00000105 16002d756322SRob Clark 16012d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_RAC 0x00000106 16022d756322SRob Clark 16032d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RAC 0x00000107 16042d756322SRob Clark 16052d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000108 16062d756322SRob Clark 16072d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000109 16082d756322SRob Clark 16092d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000010a 16102d756322SRob Clark 16112d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_UCHE 0x0000010b 16122d756322SRob Clark 16132d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE 0x0000010c 16142d756322SRob Clark 16152d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE 0x0000010d 16162d756322SRob Clark 16172d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE 0x0000010e 16182d756322SRob Clark 16192d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_UCHE 0x0000010f 16202d756322SRob Clark 16212d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_UCHE 0x00000110 16222d756322SRob Clark 16232d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_MODE_VFD 0x00000111 16242d756322SRob Clark 16252d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_VFD 0x00000112 16262d756322SRob Clark 16272d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_VFD 0x00000113 16282d756322SRob Clark 16292d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_MODE_GPC 0x00000114 16302d756322SRob Clark 16312d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_GPC 0x00000115 16322d756322SRob Clark 16332d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_GPC 0x00000116 16342d756322SRob Clark 16352d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2 0x00000117 16362d756322SRob Clark 16372d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX 0x00000118 16382d756322SRob Clark 16392d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX 0x00000119 16402d756322SRob Clark 16412d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX 0x0000011a 16422d756322SRob Clark 16432d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_MODE_HLSQ 0x0000011b 16442d756322SRob Clark 16452d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ 0x0000011c 16462d756322SRob Clark 1647c28c82e9SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_HLSQ 0x0000011d 1648c28c82e9SRob Clark 1649c28c82e9SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE 0x00000120 1650c28c82e9SRob Clark 1651c28c82e9SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE 0x00000121 1652c28c82e9SRob Clark 1653c28c82e9SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122 1654c28c82e9SRob Clark 16552d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A 0x00000600 16562d756322SRob Clark 16572d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B 0x00000601 16582d756322SRob Clark 16592d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C 0x00000602 16602d756322SRob Clark 16612d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D 0x00000603 16622d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK 0x000000ff 16632d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT 0 16642d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val) 16652d756322SRob Clark { 16662d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK; 16672d756322SRob Clark } 16682d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK 0x0000ff00 16692d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT 8 16702d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val) 16712d756322SRob Clark { 16722d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK; 16732d756322SRob Clark } 16742d756322SRob Clark 16752d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT 0x00000604 16762d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f 16772d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0 16782d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) 16792d756322SRob Clark { 16802d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; 16812d756322SRob Clark } 16822d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000 16832d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12 16842d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) 16852d756322SRob Clark { 16862d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; 16872d756322SRob Clark } 16882d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000 16892d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28 16902d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) 16912d756322SRob Clark { 16922d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; 16932d756322SRob Clark } 16942d756322SRob Clark 16952d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM 0x00000605 16962d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000 16972d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24 16982d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) 16992d756322SRob Clark { 17002d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; 17012d756322SRob Clark } 17022d756322SRob Clark 17032d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 0x00000608 17042d756322SRob Clark 17052d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 0x00000609 17062d756322SRob Clark 17072d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 0x0000060a 17082d756322SRob Clark 17092d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 0x0000060b 17102d756322SRob Clark 17112d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 0x0000060c 17122d756322SRob Clark 17132d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 0x0000060d 17142d756322SRob Clark 17152d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 0x0000060e 17162d756322SRob Clark 17172d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 0x0000060f 17182d756322SRob Clark 17192d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000610 17202d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f 17212d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0 17222d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) 17232d756322SRob Clark { 17242d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; 17252d756322SRob Clark } 17262d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0 17272d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4 17282d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) 17292d756322SRob Clark { 17302d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; 17312d756322SRob Clark } 17322d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00 17332d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8 17342d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) 17352d756322SRob Clark { 17362d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; 17372d756322SRob Clark } 17382d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000 17392d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12 17402d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) 17412d756322SRob Clark { 17422d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; 17432d756322SRob Clark } 17442d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000 17452d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16 17462d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) 17472d756322SRob Clark { 17482d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; 17492d756322SRob Clark } 17502d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000 17512d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20 17522d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) 17532d756322SRob Clark { 17542d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; 17552d756322SRob Clark } 17562d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000 17572d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24 17582d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) 17592d756322SRob Clark { 17602d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; 17612d756322SRob Clark } 17622d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000 17632d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28 17642d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) 17652d756322SRob Clark { 17662d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; 17672d756322SRob Clark } 17682d756322SRob Clark 17692d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000611 17702d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f 17712d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0 17722d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) 17732d756322SRob Clark { 17742d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; 17752d756322SRob Clark } 17762d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0 17772d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4 17782d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) 17792d756322SRob Clark { 17802d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; 17812d756322SRob Clark } 17822d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00 17832d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8 17842d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) 17852d756322SRob Clark { 17862d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; 17872d756322SRob Clark } 17882d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000 17892d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12 17902d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) 17912d756322SRob Clark { 17922d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; 17932d756322SRob Clark } 17942d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000 17952d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16 17962d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) 17972d756322SRob Clark { 17982d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; 17992d756322SRob Clark } 18002d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000 18012d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20 18022d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) 18032d756322SRob Clark { 18042d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; 18052d756322SRob Clark } 18062d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000 18072d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24 18082d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) 18092d756322SRob Clark { 18102d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; 18112d756322SRob Clark } 18122d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000 18132d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28 18142d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) 18152d756322SRob Clark { 18162d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; 18172d756322SRob Clark } 18182d756322SRob Clark 18192d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000062f 18202d756322SRob Clark 18212d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630 18222d756322SRob Clark 1823cc4c26d4SRob Clark static inline uint32_t REG_A6XX_VSC_PERFCTR_VSC_SEL(uint32_t i0) { return 0x00000cd8 + 0x1*i0; } 18242d756322SRob Clark 18252d756322SRob Clark #define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800 18262d756322SRob Clark 18272d756322SRob Clark #define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000 18282d756322SRob Clark 18292d756322SRob Clark #define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00 18302d756322SRob Clark 18312d756322SRob Clark #define REG_A6XX_UCHE_MODE_CNTL 0x00000e01 18322d756322SRob Clark 18332d756322SRob Clark #define REG_A6XX_UCHE_WRITE_RANGE_MAX_LO 0x00000e05 18342d756322SRob Clark 18352d756322SRob Clark #define REG_A6XX_UCHE_WRITE_RANGE_MAX_HI 0x00000e06 18362d756322SRob Clark 18372d756322SRob Clark #define REG_A6XX_UCHE_WRITE_THRU_BASE_LO 0x00000e07 18382d756322SRob Clark 18392d756322SRob Clark #define REG_A6XX_UCHE_WRITE_THRU_BASE_HI 0x00000e08 18402d756322SRob Clark 18412d756322SRob Clark #define REG_A6XX_UCHE_TRAP_BASE_LO 0x00000e09 18422d756322SRob Clark 18432d756322SRob Clark #define REG_A6XX_UCHE_TRAP_BASE_HI 0x00000e0a 18442d756322SRob Clark 18452d756322SRob Clark #define REG_A6XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e0b 18462d756322SRob Clark 18472d756322SRob Clark #define REG_A6XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e0c 18482d756322SRob Clark 18492d756322SRob Clark #define REG_A6XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e0d 18502d756322SRob Clark 18512d756322SRob Clark #define REG_A6XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e0e 18522d756322SRob Clark 18532d756322SRob Clark #define REG_A6XX_UCHE_CACHE_WAYS 0x00000e17 18542d756322SRob Clark 18552d756322SRob Clark #define REG_A6XX_UCHE_FILTER_CNTL 0x00000e18 18562d756322SRob Clark 18572d756322SRob Clark #define REG_A6XX_UCHE_CLIENT_PF 0x00000e19 18582d756322SRob Clark #define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK 0x000000ff 18592d756322SRob Clark #define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT 0 18602d756322SRob Clark static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val) 18612d756322SRob Clark { 18622d756322SRob Clark return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK; 18632d756322SRob Clark } 18642d756322SRob Clark 1865cc4c26d4SRob Clark static inline uint32_t REG_A6XX_UCHE_PERFCTR_UCHE_SEL(uint32_t i0) { return 0x00000e1c + 0x1*i0; } 18662d756322SRob Clark 1867cc4c26d4SRob Clark #define REG_A6XX_UCHE_CMDQ_CONFIG 0x00000e3c 18682d756322SRob Clark 18692d756322SRob Clark #define REG_A6XX_VBIF_VERSION 0x00003000 18702d756322SRob Clark 1871a69c5ed2SRob Clark #define REG_A6XX_VBIF_CLKON 0x00003001 1872a69c5ed2SRob Clark #define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000002 1873a69c5ed2SRob Clark 18742d756322SRob Clark #define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 18752d756322SRob Clark 18762d756322SRob Clark #define REG_A6XX_VBIF_XIN_HALT_CTRL0 0x00003080 18772d756322SRob Clark 18782d756322SRob Clark #define REG_A6XX_VBIF_XIN_HALT_CTRL1 0x00003081 18792d756322SRob Clark 1880a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084 1881a69c5ed2SRob Clark 1882a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS1_CTRL0 0x00003085 1883a69c5ed2SRob Clark 1884a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS1_CTRL1 0x00003086 1885a69c5ed2SRob Clark #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK 0x0000000f 1886a69c5ed2SRob Clark #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT 0 1887a69c5ed2SRob Clark static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val) 1888a69c5ed2SRob Clark { 1889a69c5ed2SRob Clark return ((val) << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK; 1890a69c5ed2SRob Clark } 1891a69c5ed2SRob Clark 1892a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS2_CTRL0 0x00003087 1893a69c5ed2SRob Clark 1894a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS2_CTRL1 0x00003088 1895a69c5ed2SRob Clark #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK 0x000001ff 1896a69c5ed2SRob Clark #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT 0 1897a69c5ed2SRob Clark static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val) 1898a69c5ed2SRob Clark { 1899a69c5ed2SRob Clark return ((val) << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK; 1900a69c5ed2SRob Clark } 1901a69c5ed2SRob Clark 1902a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS_OUT 0x0000308c 1903a69c5ed2SRob Clark 19042d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_SEL0 0x000030d0 19052d756322SRob Clark 19062d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_SEL1 0x000030d1 19072d756322SRob Clark 19082d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_SEL2 0x000030d2 19092d756322SRob Clark 19102d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_SEL3 0x000030d3 19112d756322SRob Clark 19122d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_LOW0 0x000030d8 19132d756322SRob Clark 19142d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_LOW1 0x000030d9 19152d756322SRob Clark 19162d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_LOW2 0x000030da 19172d756322SRob Clark 19182d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_LOW3 0x000030db 19192d756322SRob Clark 19202d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_HIGH0 0x000030e0 19212d756322SRob Clark 19222d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_HIGH1 0x000030e1 19232d756322SRob Clark 19242d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_HIGH2 0x000030e2 19252d756322SRob Clark 19262d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_HIGH3 0x000030e3 19272d756322SRob Clark 19282d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_EN0 0x00003100 19292d756322SRob Clark 19302d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_EN1 0x00003101 19312d756322SRob Clark 19322d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_EN2 0x00003102 19332d756322SRob Clark 19342d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110 19352d756322SRob Clark 19362d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111 19372d756322SRob Clark 19382d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112 19392d756322SRob Clark 19402d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118 19412d756322SRob Clark 19422d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119 19432d756322SRob Clark 19442d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a 19452d756322SRob Clark 1946cc4c26d4SRob Clark #define REG_A6XX_GBIF_SCACHE_CNTL0 0x00003c01 1947cc4c26d4SRob Clark 1948e812744cSSharat Masetty #define REG_A6XX_GBIF_SCACHE_CNTL1 0x00003c02 1949e812744cSSharat Masetty 1950e812744cSSharat Masetty #define REG_A6XX_GBIF_QSB_SIDE0 0x00003c03 1951e812744cSSharat Masetty 1952e812744cSSharat Masetty #define REG_A6XX_GBIF_QSB_SIDE1 0x00003c04 1953e812744cSSharat Masetty 1954e812744cSSharat Masetty #define REG_A6XX_GBIF_QSB_SIDE2 0x00003c05 1955e812744cSSharat Masetty 1956e812744cSSharat Masetty #define REG_A6XX_GBIF_QSB_SIDE3 0x00003c06 1957e812744cSSharat Masetty 1958e812744cSSharat Masetty #define REG_A6XX_GBIF_HALT 0x00003c45 1959e812744cSSharat Masetty 1960e812744cSSharat Masetty #define REG_A6XX_GBIF_HALT_ACK 0x00003c46 1961e812744cSSharat Masetty 1962e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_PWR_CNT_EN 0x00003cc0 1963e812744cSSharat Masetty 1964e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_SEL 0x00003cc2 1965e812744cSSharat Masetty 1966e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_PWR_CNT_SEL 0x00003cc3 1967e812744cSSharat Masetty 1968e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_LOW0 0x00003cc4 1969e812744cSSharat Masetty 1970e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_LOW1 0x00003cc5 1971e812744cSSharat Masetty 1972e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_LOW2 0x00003cc6 1973e812744cSSharat Masetty 1974e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_LOW3 0x00003cc7 1975e812744cSSharat Masetty 1976e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_HIGH0 0x00003cc8 1977e812744cSSharat Masetty 1978e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_HIGH1 0x00003cc9 1979e812744cSSharat Masetty 1980e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_HIGH2 0x00003cca 1981e812744cSSharat Masetty 1982e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_HIGH3 0x00003ccb 1983e812744cSSharat Masetty 1984e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_LOW0 0x00003ccc 1985e812744cSSharat Masetty 1986e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_LOW1 0x00003ccd 1987e812744cSSharat Masetty 1988e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_LOW2 0x00003cce 1989e812744cSSharat Masetty 1990e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_HIGH0 0x00003ccf 1991e812744cSSharat Masetty 1992e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_HIGH1 0x00003cd0 1993e812744cSSharat Masetty 1994e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_HIGH2 0x00003cd1 1995e812744cSSharat Masetty 1996*57cfe41cSRob Clark #define REG_A6XX_VSC_DBG_ECO_CNTL 0x00000c00 1997*57cfe41cSRob Clark 19982d756322SRob Clark #define REG_A6XX_VSC_BIN_SIZE 0x00000c02 19992d756322SRob Clark #define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff 20002d756322SRob Clark #define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 20012d756322SRob Clark static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 20022d756322SRob Clark { 20032d756322SRob Clark return ((val >> 5) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK; 20042d756322SRob Clark } 20052d756322SRob Clark #define A6XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001ff00 20062d756322SRob Clark #define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT 8 20072d756322SRob Clark static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 20082d756322SRob Clark { 20092d756322SRob Clark return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK; 20102d756322SRob Clark } 20112d756322SRob Clark 2012c28c82e9SRob Clark #define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS 0x00000c03 20132d756322SRob Clark 20142d756322SRob Clark #define REG_A6XX_VSC_BIN_COUNT 0x00000c06 20152d756322SRob Clark #define A6XX_VSC_BIN_COUNT_NX__MASK 0x000007fe 20162d756322SRob Clark #define A6XX_VSC_BIN_COUNT_NX__SHIFT 1 20172d756322SRob Clark static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val) 20182d756322SRob Clark { 20192d756322SRob Clark return ((val) << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK; 20202d756322SRob Clark } 20212d756322SRob Clark #define A6XX_VSC_BIN_COUNT_NY__MASK 0x001ff800 20222d756322SRob Clark #define A6XX_VSC_BIN_COUNT_NY__SHIFT 11 20232d756322SRob Clark static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val) 20242d756322SRob Clark { 20252d756322SRob Clark return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK; 20262d756322SRob Clark } 20272d756322SRob Clark 20282d756322SRob Clark static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 20292d756322SRob Clark 20302d756322SRob Clark static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 20312d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff 20322d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0 20332d756322SRob Clark static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) 20342d756322SRob Clark { 20352d756322SRob Clark return ((val) << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK; 20362d756322SRob Clark } 20372d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00 20382d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10 20392d756322SRob Clark static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) 20402d756322SRob Clark { 20412d756322SRob Clark return ((val) << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK; 20422d756322SRob Clark } 20432d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_W__MASK 0x03f00000 20442d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20 20452d756322SRob Clark static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) 20462d756322SRob Clark { 20472d756322SRob Clark return ((val) << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK; 20482d756322SRob Clark } 20492d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_H__MASK 0xfc000000 20502d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT 26 20512d756322SRob Clark static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) 20522d756322SRob Clark { 20532d756322SRob Clark return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK; 20542d756322SRob Clark } 20552d756322SRob Clark 2056c28c82e9SRob Clark #define REG_A6XX_VSC_PRIM_STRM_ADDRESS 0x00000c30 2057a69c5ed2SRob Clark 2058c28c82e9SRob Clark #define REG_A6XX_VSC_PRIM_STRM_PITCH 0x00000c32 20592d756322SRob Clark 2060c28c82e9SRob Clark #define REG_A6XX_VSC_PRIM_STRM_LIMIT 0x00000c33 20612d756322SRob Clark 2062c28c82e9SRob Clark #define REG_A6XX_VSC_DRAW_STRM_ADDRESS 0x00000c34 2063a69c5ed2SRob Clark 2064c28c82e9SRob Clark #define REG_A6XX_VSC_DRAW_STRM_PITCH 0x00000c36 20652d756322SRob Clark 2066c28c82e9SRob Clark #define REG_A6XX_VSC_DRAW_STRM_LIMIT 0x00000c37 2067c28c82e9SRob Clark 2068c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_STATE(uint32_t i0) { return 0x00000c38 + 0x1*i0; } 2069c28c82e9SRob Clark 2070c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_STATE_REG(uint32_t i0) { return 0x00000c38 + 0x1*i0; } 2071c28c82e9SRob Clark 2072c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE(uint32_t i0) { return 0x00000c58 + 0x1*i0; } 2073c28c82e9SRob Clark 2074c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0) { return 0x00000c58 + 0x1*i0; } 2075c28c82e9SRob Clark 2076c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; } 2077c28c82e9SRob Clark 2078c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; } 20792d756322SRob Clark 20802d756322SRob Clark #define REG_A6XX_UCHE_UNKNOWN_0E12 0x00000e12 20812d756322SRob Clark 2082c28c82e9SRob Clark #define REG_A6XX_GRAS_CL_CNTL 0x00008000 2083c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_CLIP_DISABLE 0x00000001 2084c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE 0x00000002 2085c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE 0x00000004 2086c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_UNK5 0x00000020 2087c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040 2088c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE 0x00000080 2089c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE 0x00000100 2090c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE 0x00000200 2091a69c5ed2SRob Clark 2092c28c82e9SRob Clark #define REG_A6XX_GRAS_VS_CL_CNTL 0x00008001 2093c28c82e9SRob Clark #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK 0x000000ff 2094c28c82e9SRob Clark #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT 0 2095c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val) 2096c28c82e9SRob Clark { 2097c28c82e9SRob Clark return ((val) << A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK; 2098c28c82e9SRob Clark } 2099c28c82e9SRob Clark #define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK 0x0000ff00 2100c28c82e9SRob Clark #define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT 8 2101c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val) 2102c28c82e9SRob Clark { 2103c28c82e9SRob Clark return ((val) << A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK; 2104c28c82e9SRob Clark } 21052d756322SRob Clark 2106c28c82e9SRob Clark #define REG_A6XX_GRAS_DS_CL_CNTL 0x00008002 2107c28c82e9SRob Clark #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK 0x000000ff 2108c28c82e9SRob Clark #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT 0 2109c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(uint32_t val) 2110c28c82e9SRob Clark { 2111c28c82e9SRob Clark return ((val) << A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK; 2112c28c82e9SRob Clark } 2113c28c82e9SRob Clark #define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK 0x0000ff00 2114c28c82e9SRob Clark #define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT 8 2115c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CULL_MASK(uint32_t val) 2116c28c82e9SRob Clark { 2117c28c82e9SRob Clark return ((val) << A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK; 2118c28c82e9SRob Clark } 2119c28c82e9SRob Clark 2120c28c82e9SRob Clark #define REG_A6XX_GRAS_GS_CL_CNTL 0x00008003 2121c28c82e9SRob Clark #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK 0x000000ff 2122c28c82e9SRob Clark #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT 0 2123c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(uint32_t val) 2124c28c82e9SRob Clark { 2125c28c82e9SRob Clark return ((val) << A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK; 2126c28c82e9SRob Clark } 2127c28c82e9SRob Clark #define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK 0x0000ff00 2128c28c82e9SRob Clark #define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT 8 2129c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CULL_MASK(uint32_t val) 2130c28c82e9SRob Clark { 2131c28c82e9SRob Clark return ((val) << A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK; 2132c28c82e9SRob Clark } 2133c28c82e9SRob Clark 2134c28c82e9SRob Clark #define REG_A6XX_GRAS_MAX_LAYER_INDEX 0x00008004 21352d756322SRob Clark 21362d756322SRob Clark #define REG_A6XX_GRAS_CNTL 0x00008005 2137c28c82e9SRob Clark #define A6XX_GRAS_CNTL_IJ_PERSP_PIXEL 0x00000001 2138c28c82e9SRob Clark #define A6XX_GRAS_CNTL_IJ_PERSP_CENTROID 0x00000002 2139c28c82e9SRob Clark #define A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE 0x00000004 2140*57cfe41cSRob Clark #define A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL 0x00000008 2141*57cfe41cSRob Clark #define A6XX_GRAS_CNTL_IJ_LINEAR_CENTROID 0x00000010 2142*57cfe41cSRob Clark #define A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE 0x00000020 2143c28c82e9SRob Clark #define A6XX_GRAS_CNTL_COORD_MASK__MASK 0x000003c0 2144c28c82e9SRob Clark #define A6XX_GRAS_CNTL_COORD_MASK__SHIFT 6 2145c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CNTL_COORD_MASK(uint32_t val) 2146c28c82e9SRob Clark { 2147c28c82e9SRob Clark return ((val) << A6XX_GRAS_CNTL_COORD_MASK__SHIFT) & A6XX_GRAS_CNTL_COORD_MASK__MASK; 2148c28c82e9SRob Clark } 21492d756322SRob Clark 21502d756322SRob Clark #define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x00008006 2151c28c82e9SRob Clark #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000001ff 21522d756322SRob Clark #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0 21532d756322SRob Clark static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val) 21542d756322SRob Clark { 21552d756322SRob Clark return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK; 21562d756322SRob Clark } 2157c28c82e9SRob Clark #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x0007fc00 21582d756322SRob Clark #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10 21592d756322SRob Clark static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) 21602d756322SRob Clark { 21612d756322SRob Clark return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK; 21622d756322SRob Clark } 21632d756322SRob Clark 2164c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT(uint32_t i0) { return 0x00008010 + 0x6*i0; } 2165c28c82e9SRob Clark 2166c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0) { return 0x00008010 + 0x6*i0; } 2167c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff 2168c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0 2169c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET(float val) 21702d756322SRob Clark { 2171c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET__MASK; 21722d756322SRob Clark } 21732d756322SRob Clark 2174c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XSCALE(uint32_t i0) { return 0x00008011 + 0x6*i0; } 2175c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff 2176c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_XSCALE__SHIFT 0 2177c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE(float val) 21782d756322SRob Clark { 2179c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE__MASK; 21802d756322SRob Clark } 21812d756322SRob Clark 2182c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YOFFSET(uint32_t i0) { return 0x00008012 + 0x6*i0; } 2183c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff 2184c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0 2185c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET(float val) 21862d756322SRob Clark { 2187c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET__MASK; 21882d756322SRob Clark } 21892d756322SRob Clark 2190c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YSCALE(uint32_t i0) { return 0x00008013 + 0x6*i0; } 2191c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff 2192c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_YSCALE__SHIFT 0 2193c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE(float val) 21942d756322SRob Clark { 2195c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE__MASK; 21962d756322SRob Clark } 21972d756322SRob Clark 2198c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZOFFSET(uint32_t i0) { return 0x00008014 + 0x6*i0; } 2199c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff 2200c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0 2201c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET(float val) 22022d756322SRob Clark { 2203c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET__MASK; 22042d756322SRob Clark } 22052d756322SRob Clark 2206c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZSCALE(uint32_t i0) { return 0x00008015 + 0x6*i0; } 2207c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff 2208c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0 2209c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE(float val) 22102d756322SRob Clark { 2211c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE__MASK; 2212c28c82e9SRob Clark } 2213c28c82e9SRob Clark 2214c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP(uint32_t i0) { return 0x00008070 + 0x2*i0; } 2215c28c82e9SRob Clark 2216c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0) { return 0x00008070 + 0x2*i0; } 2217c28c82e9SRob Clark #define A6XX_GRAS_CL_Z_CLAMP_MIN__MASK 0xffffffff 2218c28c82e9SRob Clark #define A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT 0 2219c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MIN(float val) 2220c28c82e9SRob Clark { 2221c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MIN__MASK; 2222c28c82e9SRob Clark } 2223c28c82e9SRob Clark 2224c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MAX(uint32_t i0) { return 0x00008071 + 0x2*i0; } 2225c28c82e9SRob Clark #define A6XX_GRAS_CL_Z_CLAMP_MAX__MASK 0xffffffff 2226c28c82e9SRob Clark #define A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT 0 2227c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MAX(float val) 2228c28c82e9SRob Clark { 2229c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MAX__MASK; 22302d756322SRob Clark } 22312d756322SRob Clark 22322d756322SRob Clark #define REG_A6XX_GRAS_SU_CNTL 0x00008090 22332d756322SRob Clark #define A6XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001 22342d756322SRob Clark #define A6XX_GRAS_SU_CNTL_CULL_BACK 0x00000002 22352d756322SRob Clark #define A6XX_GRAS_SU_CNTL_FRONT_CW 0x00000004 22362d756322SRob Clark #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8 22372d756322SRob Clark #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3 22382d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) 22392d756322SRob Clark { 22402d756322SRob Clark return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK; 22412d756322SRob Clark } 22422d756322SRob Clark #define A6XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800 2243c28c82e9SRob Clark #define A6XX_GRAS_SU_CNTL_UNK12__MASK 0x00001000 2244c28c82e9SRob Clark #define A6XX_GRAS_SU_CNTL_UNK12__SHIFT 12 2245c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SU_CNTL_UNK12(uint32_t val) 2246c28c82e9SRob Clark { 2247c28c82e9SRob Clark return ((val) << A6XX_GRAS_SU_CNTL_UNK12__SHIFT) & A6XX_GRAS_SU_CNTL_UNK12__MASK; 2248c28c82e9SRob Clark } 2249*57cfe41cSRob Clark #define A6XX_GRAS_SU_CNTL_LINE_MODE__MASK 0x00002000 2250*57cfe41cSRob Clark #define A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT 13 2251*57cfe41cSRob Clark static inline uint32_t A6XX_GRAS_SU_CNTL_LINE_MODE(enum a5xx_line_mode val) 2252*57cfe41cSRob Clark { 2253*57cfe41cSRob Clark return ((val) << A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT) & A6XX_GRAS_SU_CNTL_LINE_MODE__MASK; 2254*57cfe41cSRob Clark } 2255cc4c26d4SRob Clark #define A6XX_GRAS_SU_CNTL_UNK15__MASK 0x00018000 2256c28c82e9SRob Clark #define A6XX_GRAS_SU_CNTL_UNK15__SHIFT 15 2257c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SU_CNTL_UNK15(uint32_t val) 2258c28c82e9SRob Clark { 2259c28c82e9SRob Clark return ((val) << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK; 2260c28c82e9SRob Clark } 2261cc4c26d4SRob Clark #define A6XX_GRAS_SU_CNTL_UNK17 0x00020000 2262cc4c26d4SRob Clark #define A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE 0x00040000 2263cc4c26d4SRob Clark #define A6XX_GRAS_SU_CNTL_UNK19__MASK 0x00780000 2264cc4c26d4SRob Clark #define A6XX_GRAS_SU_CNTL_UNK19__SHIFT 19 2265cc4c26d4SRob Clark static inline uint32_t A6XX_GRAS_SU_CNTL_UNK19(uint32_t val) 2266cc4c26d4SRob Clark { 2267cc4c26d4SRob Clark return ((val) << A6XX_GRAS_SU_CNTL_UNK19__SHIFT) & A6XX_GRAS_SU_CNTL_UNK19__MASK; 2268cc4c26d4SRob Clark } 22692d756322SRob Clark 22702d756322SRob Clark #define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091 22712d756322SRob Clark #define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 22722d756322SRob Clark #define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 22732d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val) 22742d756322SRob Clark { 22752d756322SRob Clark return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 22762d756322SRob Clark } 22772d756322SRob Clark #define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 22782d756322SRob Clark #define A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 22792d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MAX(float val) 22802d756322SRob Clark { 22812d756322SRob Clark return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 22822d756322SRob Clark } 22832d756322SRob Clark 22842d756322SRob Clark #define REG_A6XX_GRAS_SU_POINT_SIZE 0x00008092 2285c28c82e9SRob Clark #define A6XX_GRAS_SU_POINT_SIZE__MASK 0x0000ffff 22862d756322SRob Clark #define A6XX_GRAS_SU_POINT_SIZE__SHIFT 0 22872d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val) 22882d756322SRob Clark { 22892d756322SRob Clark return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK; 22902d756322SRob Clark } 22912d756322SRob Clark 2292a69c5ed2SRob Clark #define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL 0x00008094 2293c28c82e9SRob Clark #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003 2294c28c82e9SRob Clark #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0 2295c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val) 2296c28c82e9SRob Clark { 2297c28c82e9SRob Clark return ((val) << A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK; 2298c28c82e9SRob Clark } 2299a69c5ed2SRob Clark 23002d756322SRob Clark #define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE 0x00008095 23012d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff 23022d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 23032d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val) 23042d756322SRob Clark { 23052d756322SRob Clark return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; 23062d756322SRob Clark } 23072d756322SRob Clark 23082d756322SRob Clark #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00008096 23092d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 23102d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 23112d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 23122d756322SRob Clark { 23132d756322SRob Clark return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 23142d756322SRob Clark } 23152d756322SRob Clark 23162d756322SRob Clark #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x00008097 23172d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff 23182d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0 23192d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val) 23202d756322SRob Clark { 23212d756322SRob Clark return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK; 23222d756322SRob Clark } 23232d756322SRob Clark 23242d756322SRob Clark #define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO 0x00008098 23252d756322SRob Clark #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 23262d756322SRob Clark #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 23272d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) 23282d756322SRob Clark { 23292d756322SRob Clark return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; 23302d756322SRob Clark } 2331c28c82e9SRob Clark #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000008 2332c28c82e9SRob Clark #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT 3 2333c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3(uint32_t val) 2334c28c82e9SRob Clark { 2335c28c82e9SRob Clark return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK; 2336c28c82e9SRob Clark } 23372d756322SRob Clark 2338*57cfe41cSRob Clark #define REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x00008099 2339*57cfe41cSRob Clark #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN 0x00000001 2340*57cfe41cSRob Clark #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK 0x00000006 2341*57cfe41cSRob Clark #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT 1 2342*57cfe41cSRob Clark static inline uint32_t A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT(uint32_t val) 2343*57cfe41cSRob Clark { 2344*57cfe41cSRob Clark return ((val) << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK; 2345*57cfe41cSRob Clark } 2346*57cfe41cSRob Clark #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_INNERCONSERVATIVERASEN 0x00000008 2347*57cfe41cSRob Clark #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK 0x00000030 2348*57cfe41cSRob Clark #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT 4 2349*57cfe41cSRob Clark static inline uint32_t A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4(uint32_t val) 2350*57cfe41cSRob Clark { 2351*57cfe41cSRob Clark return ((val) << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK; 2352*57cfe41cSRob Clark } 23532d756322SRob Clark 2354*57cfe41cSRob Clark #define REG_A6XX_GRAS_SU_PATH_RENDERING_CNTL 0x0000809a 2355*57cfe41cSRob Clark #define A6XX_GRAS_SU_PATH_RENDERING_CNTL_UNK0 0x00000001 2356*57cfe41cSRob Clark #define A6XX_GRAS_SU_PATH_RENDERING_CNTL_LINELENGTHEN 0x00000002 2357c28c82e9SRob Clark 2358c28c82e9SRob Clark #define REG_A6XX_GRAS_VS_LAYER_CNTL 0x0000809b 2359c28c82e9SRob Clark #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER 0x00000001 2360c28c82e9SRob Clark #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW 0x00000002 2361c28c82e9SRob Clark 2362c28c82e9SRob Clark #define REG_A6XX_GRAS_GS_LAYER_CNTL 0x0000809c 2363c28c82e9SRob Clark #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER 0x00000001 2364c28c82e9SRob Clark #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW 0x00000002 2365c28c82e9SRob Clark 2366c28c82e9SRob Clark #define REG_A6XX_GRAS_DS_LAYER_CNTL 0x0000809d 2367c28c82e9SRob Clark #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER 0x00000001 2368c28c82e9SRob Clark #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW 0x00000002 23692d756322SRob Clark 2370*57cfe41cSRob Clark #define REG_A6XX_GRAS_SC_CNTL 0x000080a0 2371*57cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK 0x00000007 2372*57cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT 0 2373*57cfe41cSRob Clark static inline uint32_t A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(uint32_t val) 2374*57cfe41cSRob Clark { 2375*57cfe41cSRob Clark return ((val) << A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK; 2376*57cfe41cSRob Clark } 2377*57cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK 0x00000018 2378*57cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT 3 2379*57cfe41cSRob Clark static inline uint32_t A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE(enum a6xx_single_prim_mode val) 2380*57cfe41cSRob Clark { 2381*57cfe41cSRob Clark return ((val) << A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK; 2382*57cfe41cSRob Clark } 2383*57cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK 0x00000020 2384*57cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT 5 2385*57cfe41cSRob Clark static inline uint32_t A6XX_GRAS_SC_CNTL_RASTER_MODE(enum a6xx_raster_mode val) 2386*57cfe41cSRob Clark { 2387*57cfe41cSRob Clark return ((val) << A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK; 2388*57cfe41cSRob Clark } 2389*57cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK 0x000000c0 2390*57cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT 6 2391*57cfe41cSRob Clark static inline uint32_t A6XX_GRAS_SC_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val) 2392*57cfe41cSRob Clark { 2393*57cfe41cSRob Clark return ((val) << A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK; 2394*57cfe41cSRob Clark } 2395*57cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK 0x00000100 2396*57cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT 8 2397*57cfe41cSRob Clark static inline uint32_t A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION(enum a6xx_sequenced_thread_dist val) 2398*57cfe41cSRob Clark { 2399*57cfe41cSRob Clark return ((val) << A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT) & A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK; 2400*57cfe41cSRob Clark } 2401*57cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_UNK9__MASK 0x00000e00 2402*57cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_UNK9__SHIFT 9 2403*57cfe41cSRob Clark static inline uint32_t A6XX_GRAS_SC_CNTL_UNK9(uint32_t val) 2404*57cfe41cSRob Clark { 2405*57cfe41cSRob Clark return ((val) << A6XX_GRAS_SC_CNTL_UNK9__SHIFT) & A6XX_GRAS_SC_CNTL_UNK9__MASK; 2406*57cfe41cSRob Clark } 2407*57cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_EARLYVIZOUTEN 0x00001000 2408a69c5ed2SRob Clark 2409c28c82e9SRob Clark #define REG_A6XX_GRAS_BIN_CONTROL 0x000080a1 2410c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_BINW__MASK 0x0000003f 2411c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT 0 2412c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val) 2413c28c82e9SRob Clark { 2414c28c82e9SRob Clark return ((val >> 5) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK; 2415c28c82e9SRob Clark } 2416c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_BINH__MASK 0x00007f00 2417c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT 8 2418c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val) 2419c28c82e9SRob Clark { 2420c28c82e9SRob Clark return ((val >> 4) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK; 2421c28c82e9SRob Clark } 2422*57cfe41cSRob Clark #define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000 2423*57cfe41cSRob Clark #define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT 18 2424*57cfe41cSRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val) 2425c28c82e9SRob Clark { 2426*57cfe41cSRob Clark return ((val) << A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK; 2427c28c82e9SRob Clark } 2428*57cfe41cSRob Clark #define A6XX_GRAS_BIN_CONTROL_FORCE_LRZ_WRITE_DIS 0x00200000 2429*57cfe41cSRob Clark #define A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK 0x00c00000 2430*57cfe41cSRob Clark #define A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT 22 2431*57cfe41cSRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val) 2432c28c82e9SRob Clark { 2433*57cfe41cSRob Clark return ((val) << A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK; 2434c28c82e9SRob Clark } 2435*57cfe41cSRob Clark #define A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK 0x07000000 2436*57cfe41cSRob Clark #define A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT 24 2437*57cfe41cSRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val) 2438c28c82e9SRob Clark { 2439*57cfe41cSRob Clark return ((val) << A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK; 2440*57cfe41cSRob Clark } 2441*57cfe41cSRob Clark #define A6XX_GRAS_BIN_CONTROL_UNK27__MASK 0x08000000 2442*57cfe41cSRob Clark #define A6XX_GRAS_BIN_CONTROL_UNK27__SHIFT 27 2443*57cfe41cSRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK27(uint32_t val) 2444*57cfe41cSRob Clark { 2445*57cfe41cSRob Clark return ((val) << A6XX_GRAS_BIN_CONTROL_UNK27__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK27__MASK; 2446c28c82e9SRob Clark } 2447c28c82e9SRob Clark 24482d756322SRob Clark #define REG_A6XX_GRAS_RAS_MSAA_CNTL 0x000080a2 24492d756322SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 24502d756322SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 24512d756322SRob Clark static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 24522d756322SRob Clark { 24532d756322SRob Clark return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK; 24542d756322SRob Clark } 2455c28c82e9SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK 0x00000004 2456c28c82e9SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT 2 2457c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK2(uint32_t val) 2458c28c82e9SRob Clark { 2459c28c82e9SRob Clark return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK; 2460c28c82e9SRob Clark } 2461c28c82e9SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK 0x00000008 2462c28c82e9SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT 3 2463c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK3(uint32_t val) 2464c28c82e9SRob Clark { 2465c28c82e9SRob Clark return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK; 2466c28c82e9SRob Clark } 24672d756322SRob Clark 24682d756322SRob Clark #define REG_A6XX_GRAS_DEST_MSAA_CNTL 0x000080a3 24692d756322SRob Clark #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 24702d756322SRob Clark #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 24712d756322SRob Clark static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 24722d756322SRob Clark { 24732d756322SRob Clark return ((val) << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK; 24742d756322SRob Clark } 24752d756322SRob Clark #define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 24762d756322SRob Clark 2477c28c82e9SRob Clark #define REG_A6XX_GRAS_SAMPLE_CONFIG 0x000080a4 2478c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_CONFIG_UNK0 0x00000001 2479c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002 24802d756322SRob Clark 2481c28c82e9SRob Clark #define REG_A6XX_GRAS_SAMPLE_LOCATION_0 0x000080a5 2482c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f 2483c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 2484c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) 2485c28c82e9SRob Clark { 2486c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; 2487c28c82e9SRob Clark } 2488c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 2489c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 2490c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) 2491c28c82e9SRob Clark { 2492c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; 2493c28c82e9SRob Clark } 2494c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 2495c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 2496c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) 2497c28c82e9SRob Clark { 2498c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; 2499c28c82e9SRob Clark } 2500c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 2501c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 2502c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) 2503c28c82e9SRob Clark { 2504c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; 2505c28c82e9SRob Clark } 2506c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 2507c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 2508c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) 2509c28c82e9SRob Clark { 2510c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; 2511c28c82e9SRob Clark } 2512c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 2513c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 2514c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) 2515c28c82e9SRob Clark { 2516c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; 2517c28c82e9SRob Clark } 2518c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 2519c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 2520c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) 2521c28c82e9SRob Clark { 2522c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; 2523c28c82e9SRob Clark } 2524c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 2525c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 2526c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) 2527c28c82e9SRob Clark { 2528c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; 2529c28c82e9SRob Clark } 25302d756322SRob Clark 2531c28c82e9SRob Clark #define REG_A6XX_GRAS_SAMPLE_LOCATION_1 0x000080a6 2532c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f 2533c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 2534c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) 2535c28c82e9SRob Clark { 2536c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; 2537c28c82e9SRob Clark } 2538c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 2539c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 2540c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) 2541c28c82e9SRob Clark { 2542c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; 2543c28c82e9SRob Clark } 2544c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 2545c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 2546c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) 2547c28c82e9SRob Clark { 2548c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; 2549c28c82e9SRob Clark } 2550c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 2551c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 2552c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) 2553c28c82e9SRob Clark { 2554c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; 2555c28c82e9SRob Clark } 2556c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 2557c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 2558c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) 2559c28c82e9SRob Clark { 2560c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; 2561c28c82e9SRob Clark } 2562c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 2563c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 2564c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) 2565c28c82e9SRob Clark { 2566c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; 2567c28c82e9SRob Clark } 2568c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 2569c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 2570c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) 2571c28c82e9SRob Clark { 2572c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; 2573c28c82e9SRob Clark } 2574c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 2575c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 2576c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) 2577c28c82e9SRob Clark { 2578c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; 2579c28c82e9SRob Clark } 25802d756322SRob Clark 25812d756322SRob Clark #define REG_A6XX_GRAS_UNKNOWN_80AF 0x000080af 25822d756322SRob Clark 2583c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR(uint32_t i0) { return 0x000080b0 + 0x2*i0; } 2584c28c82e9SRob Clark 2585c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0) { return 0x000080b0 + 0x2*i0; } 2586c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x0000ffff 2587c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 2588c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 25892d756322SRob Clark { 2590c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; 25912d756322SRob Clark } 2592c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0xffff0000 2593c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 2594c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 25952d756322SRob Clark { 2596c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; 25972d756322SRob Clark } 25982d756322SRob Clark 2599c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR(uint32_t i0) { return 0x000080b1 + 0x2*i0; } 2600c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x0000ffff 2601c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 2602c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 26032d756322SRob Clark { 2604c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; 26052d756322SRob Clark } 2606c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0xffff0000 2607c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 2608c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 26092d756322SRob Clark { 2610c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; 26112d756322SRob Clark } 26122d756322SRob Clark 2613c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(uint32_t i0) { return 0x000080d0 + 0x2*i0; } 2614c28c82e9SRob Clark 2615c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0) { return 0x000080d0 + 0x2*i0; } 2616c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK 0x0000ffff 2617c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT 0 2618c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(uint32_t val) 26192d756322SRob Clark { 2620c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK; 26212d756322SRob Clark } 2622c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK 0xffff0000 2623c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT 16 2624c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(uint32_t val) 26252d756322SRob Clark { 2626c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK; 26272d756322SRob Clark } 26282d756322SRob Clark 2629c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(uint32_t i0) { return 0x000080d1 + 0x2*i0; } 2630c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK 0x0000ffff 2631c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT 0 2632c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X(uint32_t val) 26332d756322SRob Clark { 2634c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK; 26352d756322SRob Clark } 2636c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK 0xffff0000 2637c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT 16 2638c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y(uint32_t val) 26392d756322SRob Clark { 2640c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK; 26412d756322SRob Clark } 26422d756322SRob Clark 26432d756322SRob Clark #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL 0x000080f0 2644c28c82e9SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00003fff 26452d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 26462d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 26472d756322SRob Clark { 26482d756322SRob Clark return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 26492d756322SRob Clark } 2650c28c82e9SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x3fff0000 26512d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 26522d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 26532d756322SRob Clark { 26542d756322SRob Clark return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 26552d756322SRob Clark } 26562d756322SRob Clark 26572d756322SRob Clark #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR 0x000080f1 2658c28c82e9SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00003fff 26592d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 26602d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 26612d756322SRob Clark { 26622d756322SRob Clark return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 26632d756322SRob Clark } 2664c28c82e9SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x3fff0000 26652d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 26662d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 26672d756322SRob Clark { 26682d756322SRob Clark return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 26692d756322SRob Clark } 26702d756322SRob Clark 26712d756322SRob Clark #define REG_A6XX_GRAS_LRZ_CNTL 0x00008100 26722d756322SRob Clark #define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001 26732d756322SRob Clark #define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002 26742d756322SRob Clark #define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004 2675c28c82e9SRob Clark #define A6XX_GRAS_LRZ_CNTL_FC_ENABLE 0x00000008 2676c28c82e9SRob Clark #define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE 0x00000010 2677cc4c26d4SRob Clark #define A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE 0x00000020 2678cc4c26d4SRob Clark #define A6XX_GRAS_LRZ_CNTL_UNK6__MASK 0x000003c0 2679cc4c26d4SRob Clark #define A6XX_GRAS_LRZ_CNTL_UNK6__SHIFT 6 2680cc4c26d4SRob Clark static inline uint32_t A6XX_GRAS_LRZ_CNTL_UNK6(uint32_t val) 2681c28c82e9SRob Clark { 2682cc4c26d4SRob Clark return ((val) << A6XX_GRAS_LRZ_CNTL_UNK6__SHIFT) & A6XX_GRAS_LRZ_CNTL_UNK6__MASK; 2683c28c82e9SRob Clark } 26842d756322SRob Clark 2685*57cfe41cSRob Clark #define REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL 0x00008101 2686*57cfe41cSRob Clark #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_SAMPLEID 0x00000001 2687*57cfe41cSRob Clark #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK 0x00000006 2688*57cfe41cSRob Clark #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT 1 2689*57cfe41cSRob Clark static inline uint32_t A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val) 26902d756322SRob Clark { 2691*57cfe41cSRob Clark return ((val) << A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK; 2692*57cfe41cSRob Clark } 2693*57cfe41cSRob Clark 2694*57cfe41cSRob Clark #define REG_A6XX_GRAS_LRZ_MRT_BUF_INFO_0 0x00008102 2695*57cfe41cSRob Clark #define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK 0x000000ff 2696*57cfe41cSRob Clark #define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT 0 2697*57cfe41cSRob Clark static inline uint32_t A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT(enum a6xx_format val) 2698*57cfe41cSRob Clark { 2699*57cfe41cSRob Clark return ((val) << A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT) & A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK; 27002d756322SRob Clark } 27012d756322SRob Clark 2702c28c82e9SRob Clark #define REG_A6XX_GRAS_LRZ_BUFFER_BASE 0x00008103 2703c28c82e9SRob Clark #define A6XX_GRAS_LRZ_BUFFER_BASE__MASK 0xffffffff 2704c28c82e9SRob Clark #define A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT 0 2705c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_LRZ_BUFFER_BASE(uint32_t val) 2706c28c82e9SRob Clark { 2707c28c82e9SRob Clark return ((val) << A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_BUFFER_BASE__MASK; 2708c28c82e9SRob Clark } 2709c28c82e9SRob Clark 27102d756322SRob Clark #define REG_A6XX_GRAS_LRZ_BUFFER_PITCH 0x00008105 2711c28c82e9SRob Clark #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK 0x000000ff 27122d756322SRob Clark #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT 0 27132d756322SRob Clark static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val) 27142d756322SRob Clark { 27152d756322SRob Clark return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK; 27162d756322SRob Clark } 2717c28c82e9SRob Clark #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffffc00 2718c28c82e9SRob Clark #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT 10 27192d756322SRob Clark static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 27202d756322SRob Clark { 2721c28c82e9SRob Clark return ((val >> 4) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK; 27222d756322SRob Clark } 27232d756322SRob Clark 2724c28c82e9SRob Clark #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE 0x00008106 2725c28c82e9SRob Clark #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK 0xffffffff 2726c28c82e9SRob Clark #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT 0 2727c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(uint32_t val) 2728c28c82e9SRob Clark { 2729c28c82e9SRob Clark return ((val) << A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK; 2730c28c82e9SRob Clark } 2731c28c82e9SRob Clark 2732c28c82e9SRob Clark #define REG_A6XX_GRAS_SAMPLE_CNTL 0x00008109 2733c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001 2734c28c82e9SRob Clark 2735c28c82e9SRob Clark #define REG_A6XX_GRAS_UNKNOWN_810A 0x0000810a 2736c28c82e9SRob Clark #define A6XX_GRAS_UNKNOWN_810A_UNK0__MASK 0x000007ff 2737c28c82e9SRob Clark #define A6XX_GRAS_UNKNOWN_810A_UNK0__SHIFT 0 2738c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK0(uint32_t val) 2739c28c82e9SRob Clark { 2740c28c82e9SRob Clark return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK0__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK0__MASK; 2741c28c82e9SRob Clark } 2742c28c82e9SRob Clark #define A6XX_GRAS_UNKNOWN_810A_UNK16__MASK 0x07ff0000 2743c28c82e9SRob Clark #define A6XX_GRAS_UNKNOWN_810A_UNK16__SHIFT 16 2744c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK16(uint32_t val) 2745c28c82e9SRob Clark { 2746c28c82e9SRob Clark return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK16__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK16__MASK; 2747c28c82e9SRob Clark } 2748c28c82e9SRob Clark #define A6XX_GRAS_UNKNOWN_810A_UNK28__MASK 0xf0000000 2749c28c82e9SRob Clark #define A6XX_GRAS_UNKNOWN_810A_UNK28__SHIFT 28 2750c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK28(uint32_t val) 2751c28c82e9SRob Clark { 2752c28c82e9SRob Clark return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK28__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK28__MASK; 2753c28c82e9SRob Clark } 2754a69c5ed2SRob Clark 2755a69c5ed2SRob Clark #define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110 2756a69c5ed2SRob Clark 27572d756322SRob Clark #define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400 2758c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK 0x00000007 2759c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT 0 2760c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val) 2761c28c82e9SRob Clark { 2762c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK; 2763c28c82e9SRob Clark } 2764*57cfe41cSRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_OVERWRITEEN 0x00000008 2765*57cfe41cSRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK 0x00000070 2766*57cfe41cSRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT 4 2767*57cfe41cSRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK4(uint32_t val) 2768c28c82e9SRob Clark { 2769*57cfe41cSRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK; 2770c28c82e9SRob Clark } 2771c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR 0x00000080 2772ccdf7e28SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00 2773ccdf7e28SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8 2774c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val) 2775ccdf7e28SRob Clark { 2776ccdf7e28SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK; 2777ccdf7e28SRob Clark } 2778ccdf7e28SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR 0x00010000 2779c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK 0x00060000 2780c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT 17 2781c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK17(uint32_t val) 2782c28c82e9SRob Clark { 2783c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK; 2784c28c82e9SRob Clark } 2785c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_D24S8 0x00080000 2786c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK 0x00f00000 2787c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT 20 2788c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_MASK(uint32_t val) 2789c28c82e9SRob Clark { 2790c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK; 2791c28c82e9SRob Clark } 2792c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK 0x1f000000 2793c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT 24 2794c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val) 2795c28c82e9SRob Clark { 2796c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK; 2797c28c82e9SRob Clark } 2798*57cfe41cSRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK 0x20000000 2799*57cfe41cSRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT 29 2800*57cfe41cSRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val) 2801c28c82e9SRob Clark { 2802*57cfe41cSRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK; 2803c28c82e9SRob Clark } 28042d756322SRob Clark 28052d756322SRob Clark #define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401 28062d756322SRob Clark 28072d756322SRob Clark #define REG_A6XX_GRAS_2D_SRC_BR_X 0x00008402 28082d756322SRob Clark 28092d756322SRob Clark #define REG_A6XX_GRAS_2D_SRC_TL_Y 0x00008403 28102d756322SRob Clark 28112d756322SRob Clark #define REG_A6XX_GRAS_2D_SRC_BR_Y 0x00008404 28122d756322SRob Clark 28132d756322SRob Clark #define REG_A6XX_GRAS_2D_DST_TL 0x00008405 2814c28c82e9SRob Clark #define A6XX_GRAS_2D_DST_TL_X__MASK 0x00003fff 28152d756322SRob Clark #define A6XX_GRAS_2D_DST_TL_X__SHIFT 0 28162d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val) 28172d756322SRob Clark { 28182d756322SRob Clark return ((val) << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK; 28192d756322SRob Clark } 2820c28c82e9SRob Clark #define A6XX_GRAS_2D_DST_TL_Y__MASK 0x3fff0000 28212d756322SRob Clark #define A6XX_GRAS_2D_DST_TL_Y__SHIFT 16 28222d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val) 28232d756322SRob Clark { 28242d756322SRob Clark return ((val) << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK; 28252d756322SRob Clark } 28262d756322SRob Clark 28272d756322SRob Clark #define REG_A6XX_GRAS_2D_DST_BR 0x00008406 2828c28c82e9SRob Clark #define A6XX_GRAS_2D_DST_BR_X__MASK 0x00003fff 28292d756322SRob Clark #define A6XX_GRAS_2D_DST_BR_X__SHIFT 0 28302d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val) 28312d756322SRob Clark { 28322d756322SRob Clark return ((val) << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK; 28332d756322SRob Clark } 2834c28c82e9SRob Clark #define A6XX_GRAS_2D_DST_BR_Y__MASK 0x3fff0000 28352d756322SRob Clark #define A6XX_GRAS_2D_DST_BR_Y__SHIFT 16 28362d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val) 28372d756322SRob Clark { 28382d756322SRob Clark return ((val) << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK; 28392d756322SRob Clark } 28402d756322SRob Clark 2841c28c82e9SRob Clark #define REG_A6XX_GRAS_2D_UNKNOWN_8407 0x00008407 2842c28c82e9SRob Clark 2843c28c82e9SRob Clark #define REG_A6XX_GRAS_2D_UNKNOWN_8408 0x00008408 2844c28c82e9SRob Clark 2845c28c82e9SRob Clark #define REG_A6XX_GRAS_2D_UNKNOWN_8409 0x00008409 2846c28c82e9SRob Clark 2847c28c82e9SRob Clark #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_1 0x0000840a 2848c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK 0x00003fff 2849c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT 0 2850c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_X(uint32_t val) 28512d756322SRob Clark { 2852c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK; 28532d756322SRob Clark } 2854c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK 0x3fff0000 2855c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT 16 2856c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(uint32_t val) 28572d756322SRob Clark { 2858c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK; 28592d756322SRob Clark } 28602d756322SRob Clark 2861c28c82e9SRob Clark #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_2 0x0000840b 2862c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK 0x00003fff 2863c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT 0 2864c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_X(uint32_t val) 28652d756322SRob Clark { 2866c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK; 28672d756322SRob Clark } 2868c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK 0x3fff0000 2869c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT 16 2870c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val) 28712d756322SRob Clark { 2872c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK; 28732d756322SRob Clark } 28742d756322SRob Clark 2875*57cfe41cSRob Clark #define REG_A6XX_GRAS_DBG_ECO_CNTL 0x00008600 2876*57cfe41cSRob Clark #define A6XX_GRAS_DBG_ECO_CNTL_UNK7 0x00000080 2877*57cfe41cSRob Clark #define A6XX_GRAS_DBG_ECO_CNTL_LRZCACHELOCKDIS 0x00000800 28782d756322SRob Clark 2879c28c82e9SRob Clark #define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601 2880c28c82e9SRob Clark 2881cc4c26d4SRob Clark static inline uint32_t REG_A6XX_GRAS_PERFCTR_TSE_SEL(uint32_t i0) { return 0x00008610 + 0x1*i0; } 2882c28c82e9SRob Clark 2883cc4c26d4SRob Clark static inline uint32_t REG_A6XX_GRAS_PERFCTR_RAS_SEL(uint32_t i0) { return 0x00008614 + 0x1*i0; } 2884c28c82e9SRob Clark 2885cc4c26d4SRob Clark static inline uint32_t REG_A6XX_GRAS_PERFCTR_LRZ_SEL(uint32_t i0) { return 0x00008618 + 0x1*i0; } 2886c28c82e9SRob Clark 2887a69c5ed2SRob Clark #define REG_A6XX_RB_BIN_CONTROL 0x00008800 2888c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f 2889a69c5ed2SRob Clark #define A6XX_RB_BIN_CONTROL_BINW__SHIFT 0 2890a69c5ed2SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val) 2891a69c5ed2SRob Clark { 2892a69c5ed2SRob Clark return ((val >> 5) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK; 2893a69c5ed2SRob Clark } 2894c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL_BINH__MASK 0x00007f00 2895a69c5ed2SRob Clark #define A6XX_RB_BIN_CONTROL_BINH__SHIFT 8 2896a69c5ed2SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val) 2897a69c5ed2SRob Clark { 2898a69c5ed2SRob Clark return ((val >> 4) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK; 2899a69c5ed2SRob Clark } 2900*57cfe41cSRob Clark #define A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000 2901*57cfe41cSRob Clark #define A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT 18 2902*57cfe41cSRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val) 2903c28c82e9SRob Clark { 2904*57cfe41cSRob Clark return ((val) << A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK; 2905c28c82e9SRob Clark } 2906*57cfe41cSRob Clark #define A6XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS 0x00200000 2907*57cfe41cSRob Clark #define A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK 0x00c00000 2908*57cfe41cSRob Clark #define A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT 22 2909*57cfe41cSRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val) 2910c28c82e9SRob Clark { 2911*57cfe41cSRob Clark return ((val) << A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK; 2912c28c82e9SRob Clark } 2913*57cfe41cSRob Clark #define A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK 0x07000000 2914*57cfe41cSRob Clark #define A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT 24 2915*57cfe41cSRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val) 2916c28c82e9SRob Clark { 2917*57cfe41cSRob Clark return ((val) << A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK; 2918c28c82e9SRob Clark } 2919a69c5ed2SRob Clark 2920a69c5ed2SRob Clark #define REG_A6XX_RB_RENDER_CNTL 0x00008801 2921*57cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK 0x00000038 2922*57cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT 3 2923*57cfe41cSRob Clark static inline uint32_t A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE(uint32_t val) 2924c28c82e9SRob Clark { 2925*57cfe41cSRob Clark return ((val) << A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK; 2926c28c82e9SRob Clark } 2927*57cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_EARLYVIZOUTEN 0x00000040 2928a69c5ed2SRob Clark #define A6XX_RB_RENDER_CNTL_BINNING 0x00000080 2929*57cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_UNK8__MASK 0x00000700 2930c28c82e9SRob Clark #define A6XX_RB_RENDER_CNTL_UNK8__SHIFT 8 2931c28c82e9SRob Clark static inline uint32_t A6XX_RB_RENDER_CNTL_UNK8(uint32_t val) 2932c28c82e9SRob Clark { 2933c28c82e9SRob Clark return ((val) << A6XX_RB_RENDER_CNTL_UNK8__SHIFT) & A6XX_RB_RENDER_CNTL_UNK8__MASK; 2934c28c82e9SRob Clark } 2935*57cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK 0x00000100 2936*57cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT 8 2937*57cfe41cSRob Clark static inline uint32_t A6XX_RB_RENDER_CNTL_RASTER_MODE(enum a6xx_raster_mode val) 2938*57cfe41cSRob Clark { 2939*57cfe41cSRob Clark return ((val) << A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK; 2940*57cfe41cSRob Clark } 2941*57cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK 0x00000600 2942*57cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT 9 2943*57cfe41cSRob Clark static inline uint32_t A6XX_RB_RENDER_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val) 2944*57cfe41cSRob Clark { 2945*57cfe41cSRob Clark return ((val) << A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK; 2946*57cfe41cSRob Clark } 2947*57cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_CONSERVATIVERASEN 0x00000800 2948*57cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN 0x00001000 2949a69c5ed2SRob Clark #define A6XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000 2950a69c5ed2SRob Clark #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000 2951a69c5ed2SRob Clark #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16 2952a69c5ed2SRob Clark static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val) 2953a69c5ed2SRob Clark { 2954a69c5ed2SRob Clark return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK; 2955a69c5ed2SRob Clark } 2956a69c5ed2SRob Clark 29572d756322SRob Clark #define REG_A6XX_RB_RAS_MSAA_CNTL 0x00008802 29582d756322SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 29592d756322SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 29602d756322SRob Clark static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 29612d756322SRob Clark { 29622d756322SRob Clark return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK; 29632d756322SRob Clark } 2964c28c82e9SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK 0x00000004 2965c28c82e9SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT 2 2966c28c82e9SRob Clark static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK2(uint32_t val) 2967c28c82e9SRob Clark { 2968c28c82e9SRob Clark return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK; 2969c28c82e9SRob Clark } 2970c28c82e9SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK 0x00000008 2971c28c82e9SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT 3 2972c28c82e9SRob Clark static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK3(uint32_t val) 2973c28c82e9SRob Clark { 2974c28c82e9SRob Clark return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK; 2975c28c82e9SRob Clark } 29762d756322SRob Clark 29772d756322SRob Clark #define REG_A6XX_RB_DEST_MSAA_CNTL 0x00008803 29782d756322SRob Clark #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 29792d756322SRob Clark #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 29802d756322SRob Clark static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 29812d756322SRob Clark { 29822d756322SRob Clark return ((val) << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK; 29832d756322SRob Clark } 29842d756322SRob Clark #define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 29852d756322SRob Clark 2986c28c82e9SRob Clark #define REG_A6XX_RB_SAMPLE_CONFIG 0x00008804 2987c28c82e9SRob Clark #define A6XX_RB_SAMPLE_CONFIG_UNK0 0x00000001 2988c28c82e9SRob Clark #define A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002 29892d756322SRob Clark 2990c28c82e9SRob Clark #define REG_A6XX_RB_SAMPLE_LOCATION_0 0x00008805 2991c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f 2992c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 2993c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) 2994c28c82e9SRob Clark { 2995c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; 2996c28c82e9SRob Clark } 2997c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 2998c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 2999c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) 3000c28c82e9SRob Clark { 3001c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; 3002c28c82e9SRob Clark } 3003c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 3004c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 3005c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) 3006c28c82e9SRob Clark { 3007c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; 3008c28c82e9SRob Clark } 3009c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 3010c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 3011c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) 3012c28c82e9SRob Clark { 3013c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; 3014c28c82e9SRob Clark } 3015c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 3016c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 3017c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) 3018c28c82e9SRob Clark { 3019c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; 3020c28c82e9SRob Clark } 3021c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 3022c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 3023c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) 3024c28c82e9SRob Clark { 3025c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; 3026c28c82e9SRob Clark } 3027c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 3028c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 3029c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) 3030c28c82e9SRob Clark { 3031c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; 3032c28c82e9SRob Clark } 3033c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 3034c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 3035c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) 3036c28c82e9SRob Clark { 3037c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; 3038c28c82e9SRob Clark } 30392d756322SRob Clark 3040c28c82e9SRob Clark #define REG_A6XX_RB_SAMPLE_LOCATION_1 0x00008806 3041c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f 3042c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 3043c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) 3044c28c82e9SRob Clark { 3045c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; 3046c28c82e9SRob Clark } 3047c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 3048c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 3049c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) 3050c28c82e9SRob Clark { 3051c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; 3052c28c82e9SRob Clark } 3053c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 3054c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 3055c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) 3056c28c82e9SRob Clark { 3057c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; 3058c28c82e9SRob Clark } 3059c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 3060c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 3061c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) 3062c28c82e9SRob Clark { 3063c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; 3064c28c82e9SRob Clark } 3065c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 3066c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 3067c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) 3068c28c82e9SRob Clark { 3069c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; 3070c28c82e9SRob Clark } 3071c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 3072c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 3073c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) 3074c28c82e9SRob Clark { 3075c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; 3076c28c82e9SRob Clark } 3077c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 3078c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 3079c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) 3080c28c82e9SRob Clark { 3081c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; 3082c28c82e9SRob Clark } 3083c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 3084c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 3085c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) 3086c28c82e9SRob Clark { 3087c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; 3088c28c82e9SRob Clark } 30892d756322SRob Clark 30902d756322SRob Clark #define REG_A6XX_RB_RENDER_CONTROL0 0x00008809 3091c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL 0x00000001 3092c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID 0x00000002 3093c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE 0x00000004 3094*57cfe41cSRob Clark #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL 0x00000008 3095*57cfe41cSRob Clark #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID 0x00000010 3096*57cfe41cSRob Clark #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE 0x00000020 3097c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK 0x000003c0 3098c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT 6 3099c28c82e9SRob Clark static inline uint32_t A6XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val) 3100c28c82e9SRob Clark { 3101c28c82e9SRob Clark return ((val) << A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK; 3102c28c82e9SRob Clark } 31032d756322SRob Clark #define A6XX_RB_RENDER_CONTROL0_UNK10 0x00000400 31042d756322SRob Clark 31052d756322SRob Clark #define REG_A6XX_RB_RENDER_CONTROL1 0x0000880a 31062d756322SRob Clark #define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001 3107c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL1_UNK1 0x00000002 3108c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL1_FACENESS 0x00000004 31092d756322SRob Clark #define A6XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000008 3110*57cfe41cSRob Clark #define A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK 0x00000030 3111*57cfe41cSRob Clark #define A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT 4 3112*57cfe41cSRob Clark static inline uint32_t A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val) 3113*57cfe41cSRob Clark { 3114*57cfe41cSRob Clark return ((val) << A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK; 3115*57cfe41cSRob Clark } 3116c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL1_SIZE 0x00000040 3117*57cfe41cSRob Clark #define A6XX_RB_RENDER_CONTROL1_LINELENGTHEN 0x00000080 3118*57cfe41cSRob Clark #define A6XX_RB_RENDER_CONTROL1_FOVEATION 0x00000100 31192d756322SRob Clark 31202d756322SRob Clark #define REG_A6XX_RB_FS_OUTPUT_CNTL0 0x0000880b 3121c28c82e9SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001 31222d756322SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z 0x00000002 3123c28c82e9SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK 0x00000004 3124c28c82e9SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF 0x00000008 31252d756322SRob Clark 31262d756322SRob Clark #define REG_A6XX_RB_FS_OUTPUT_CNTL1 0x0000880c 31272d756322SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f 31282d756322SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT 0 31292d756322SRob Clark static inline uint32_t A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val) 31302d756322SRob Clark { 31312d756322SRob Clark return ((val) << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK; 31322d756322SRob Clark } 31332d756322SRob Clark 31342d756322SRob Clark #define REG_A6XX_RB_RENDER_COMPONENTS 0x0000880d 31352d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f 31362d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0 31372d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) 31382d756322SRob Clark { 31392d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK; 31402d756322SRob Clark } 31412d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0 31422d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4 31432d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) 31442d756322SRob Clark { 31452d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK; 31462d756322SRob Clark } 31472d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00 31482d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8 31492d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) 31502d756322SRob Clark { 31512d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK; 31522d756322SRob Clark } 31532d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000 31542d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12 31552d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) 31562d756322SRob Clark { 31572d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK; 31582d756322SRob Clark } 31592d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000 31602d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16 31612d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) 31622d756322SRob Clark { 31632d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK; 31642d756322SRob Clark } 31652d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000 31662d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20 31672d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) 31682d756322SRob Clark { 31692d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK; 31702d756322SRob Clark } 31712d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000 31722d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24 31732d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) 31742d756322SRob Clark { 31752d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK; 31762d756322SRob Clark } 31772d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000 31782d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28 31792d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) 31802d756322SRob Clark { 31812d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK; 31822d756322SRob Clark } 31832d756322SRob Clark 31842d756322SRob Clark #define REG_A6XX_RB_DITHER_CNTL 0x0000880e 31852d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK 0x00000003 31862d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT 0 31872d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val) 31882d756322SRob Clark { 31892d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK; 31902d756322SRob Clark } 31912d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK 0x0000000c 31922d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT 2 31932d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val) 31942d756322SRob Clark { 31952d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK; 31962d756322SRob Clark } 31972d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK 0x00000030 31982d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT 4 31992d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val) 32002d756322SRob Clark { 32012d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK; 32022d756322SRob Clark } 32032d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK 0x000000c0 32042d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT 6 32052d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val) 32062d756322SRob Clark { 32072d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK; 32082d756322SRob Clark } 32092d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK 0x00000300 32102d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT 8 32112d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val) 32122d756322SRob Clark { 32132d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK; 32142d756322SRob Clark } 32152d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK 0x00000c00 32162d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT 10 32172d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val) 32182d756322SRob Clark { 32192d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK; 32202d756322SRob Clark } 32212d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK 0x00001000 32222d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT 12 32232d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val) 32242d756322SRob Clark { 32252d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK; 32262d756322SRob Clark } 32272d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK 0x0000c000 32282d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT 14 32292d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val) 32302d756322SRob Clark { 32312d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK; 32322d756322SRob Clark } 32332d756322SRob Clark 32342d756322SRob Clark #define REG_A6XX_RB_SRGB_CNTL 0x0000880f 32352d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT0 0x00000001 32362d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT1 0x00000002 32372d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT2 0x00000004 32382d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT3 0x00000008 32392d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT4 0x00000010 32402d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT5 0x00000020 32412d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT6 0x00000040 32422d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT7 0x00000080 32432d756322SRob Clark 3244c28c82e9SRob Clark #define REG_A6XX_RB_SAMPLE_CNTL 0x00008810 3245c28c82e9SRob Clark #define A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001 3246a69c5ed2SRob Clark 3247a69c5ed2SRob Clark #define REG_A6XX_RB_UNKNOWN_8811 0x00008811 3248a69c5ed2SRob Clark 32492d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8818 0x00008818 32502d756322SRob Clark 32512d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8819 0x00008819 32522d756322SRob Clark 32532d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881A 0x0000881a 32542d756322SRob Clark 32552d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881B 0x0000881b 32562d756322SRob Clark 32572d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881C 0x0000881c 32582d756322SRob Clark 32592d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881D 0x0000881d 32602d756322SRob Clark 32612d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881E 0x0000881e 32622d756322SRob Clark 32632d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; } 32642d756322SRob Clark 32652d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; } 32662d756322SRob Clark #define A6XX_RB_MRT_CONTROL_BLEND 0x00000001 32672d756322SRob Clark #define A6XX_RB_MRT_CONTROL_BLEND2 0x00000002 32682d756322SRob Clark #define A6XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004 32692d756322SRob Clark #define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078 32702d756322SRob Clark #define A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3 32712d756322SRob Clark static inline uint32_t A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) 32722d756322SRob Clark { 32732d756322SRob Clark return ((val) << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK; 32742d756322SRob Clark } 32752d756322SRob Clark #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780 32762d756322SRob Clark #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7 32772d756322SRob Clark static inline uint32_t A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 32782d756322SRob Clark { 32792d756322SRob Clark return ((val) << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 32802d756322SRob Clark } 32812d756322SRob Clark 32822d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; } 32832d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 32842d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 32852d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 32862d756322SRob Clark { 32872d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 32882d756322SRob Clark } 32892d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 32902d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 32912d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 32922d756322SRob Clark { 32932d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 32942d756322SRob Clark } 32952d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 32962d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 32972d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 32982d756322SRob Clark { 32992d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 33002d756322SRob Clark } 33012d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 33022d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 33032d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 33042d756322SRob Clark { 33052d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 33062d756322SRob Clark } 33072d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 33082d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 33092d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 33102d756322SRob Clark { 33112d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 33122d756322SRob Clark } 33132d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 33142d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 33152d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 33162d756322SRob Clark { 33172d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 33182d756322SRob Clark } 33192d756322SRob Clark 33202d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; } 33212d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff 33222d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 3323c28c82e9SRob Clark static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val) 33242d756322SRob Clark { 33252d756322SRob Clark return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 33262d756322SRob Clark } 33272d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300 33282d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8 33292d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val) 33302d756322SRob Clark { 33312d756322SRob Clark return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 33322d756322SRob Clark } 3333c28c82e9SRob Clark #define A6XX_RB_MRT_BUF_INFO_UNK10__MASK 0x00000400 3334c28c82e9SRob Clark #define A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT 10 3335c28c82e9SRob Clark static inline uint32_t A6XX_RB_MRT_BUF_INFO_UNK10(uint32_t val) 3336c28c82e9SRob Clark { 3337c28c82e9SRob Clark return ((val) << A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT) & A6XX_RB_MRT_BUF_INFO_UNK10__MASK; 3338c28c82e9SRob Clark } 33392d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000 33402d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13 33412d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 33422d756322SRob Clark { 33432d756322SRob Clark return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 33442d756322SRob Clark } 33452d756322SRob Clark 33462d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; } 3347c28c82e9SRob Clark #define A6XX_RB_MRT_PITCH__MASK 0x0000ffff 33482d756322SRob Clark #define A6XX_RB_MRT_PITCH__SHIFT 0 33492d756322SRob Clark static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val) 33502d756322SRob Clark { 33512d756322SRob Clark return ((val >> 6) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK; 33522d756322SRob Clark } 33532d756322SRob Clark 33542d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; } 3355c28c82e9SRob Clark #define A6XX_RB_MRT_ARRAY_PITCH__MASK 0x1fffffff 33562d756322SRob Clark #define A6XX_RB_MRT_ARRAY_PITCH__SHIFT 0 33572d756322SRob Clark static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val) 33582d756322SRob Clark { 33592d756322SRob Clark return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK; 33602d756322SRob Clark } 33612d756322SRob Clark 3362c28c82e9SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; } 3363c28c82e9SRob Clark #define A6XX_RB_MRT_BASE__MASK 0xffffffff 3364c28c82e9SRob Clark #define A6XX_RB_MRT_BASE__SHIFT 0 3365c28c82e9SRob Clark static inline uint32_t A6XX_RB_MRT_BASE(uint32_t val) 3366c28c82e9SRob Clark { 3367c28c82e9SRob Clark return ((val) << A6XX_RB_MRT_BASE__SHIFT) & A6XX_RB_MRT_BASE__MASK; 3368c28c82e9SRob Clark } 3369c28c82e9SRob Clark 33702d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; } 3371c28c82e9SRob Clark #define A6XX_RB_MRT_BASE_GMEM__MASK 0xfffff000 3372c28c82e9SRob Clark #define A6XX_RB_MRT_BASE_GMEM__SHIFT 12 3373c28c82e9SRob Clark static inline uint32_t A6XX_RB_MRT_BASE_GMEM(uint32_t val) 3374c28c82e9SRob Clark { 3375c28c82e9SRob Clark return ((val >> 12) << A6XX_RB_MRT_BASE_GMEM__SHIFT) & A6XX_RB_MRT_BASE_GMEM__MASK; 3376c28c82e9SRob Clark } 33772d756322SRob Clark 33782d756322SRob Clark #define REG_A6XX_RB_BLEND_RED_F32 0x00008860 33792d756322SRob Clark #define A6XX_RB_BLEND_RED_F32__MASK 0xffffffff 33802d756322SRob Clark #define A6XX_RB_BLEND_RED_F32__SHIFT 0 33812d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_RED_F32(float val) 33822d756322SRob Clark { 33832d756322SRob Clark return ((fui(val)) << A6XX_RB_BLEND_RED_F32__SHIFT) & A6XX_RB_BLEND_RED_F32__MASK; 33842d756322SRob Clark } 33852d756322SRob Clark 33862d756322SRob Clark #define REG_A6XX_RB_BLEND_GREEN_F32 0x00008861 33872d756322SRob Clark #define A6XX_RB_BLEND_GREEN_F32__MASK 0xffffffff 33882d756322SRob Clark #define A6XX_RB_BLEND_GREEN_F32__SHIFT 0 33892d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_GREEN_F32(float val) 33902d756322SRob Clark { 33912d756322SRob Clark return ((fui(val)) << A6XX_RB_BLEND_GREEN_F32__SHIFT) & A6XX_RB_BLEND_GREEN_F32__MASK; 33922d756322SRob Clark } 33932d756322SRob Clark 33942d756322SRob Clark #define REG_A6XX_RB_BLEND_BLUE_F32 0x00008862 33952d756322SRob Clark #define A6XX_RB_BLEND_BLUE_F32__MASK 0xffffffff 33962d756322SRob Clark #define A6XX_RB_BLEND_BLUE_F32__SHIFT 0 33972d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_BLUE_F32(float val) 33982d756322SRob Clark { 33992d756322SRob Clark return ((fui(val)) << A6XX_RB_BLEND_BLUE_F32__SHIFT) & A6XX_RB_BLEND_BLUE_F32__MASK; 34002d756322SRob Clark } 34012d756322SRob Clark 34022d756322SRob Clark #define REG_A6XX_RB_BLEND_ALPHA_F32 0x00008863 34032d756322SRob Clark #define A6XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff 34042d756322SRob Clark #define A6XX_RB_BLEND_ALPHA_F32__SHIFT 0 34052d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_ALPHA_F32(float val) 34062d756322SRob Clark { 34072d756322SRob Clark return ((fui(val)) << A6XX_RB_BLEND_ALPHA_F32__SHIFT) & A6XX_RB_BLEND_ALPHA_F32__MASK; 34082d756322SRob Clark } 34092d756322SRob Clark 34102d756322SRob Clark #define REG_A6XX_RB_ALPHA_CONTROL 0x00008864 34112d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff 34122d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 34132d756322SRob Clark static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) 34142d756322SRob Clark { 34152d756322SRob Clark return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; 34162d756322SRob Clark } 34172d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 34182d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 34192d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 34202d756322SRob Clark static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 34212d756322SRob Clark { 34222d756322SRob Clark return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; 34232d756322SRob Clark } 34242d756322SRob Clark 34252d756322SRob Clark #define REG_A6XX_RB_BLEND_CNTL 0x00008865 34262d756322SRob Clark #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff 34272d756322SRob Clark #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 34282d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val) 34292d756322SRob Clark { 34302d756322SRob Clark return ((val) << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK; 34312d756322SRob Clark } 34322d756322SRob Clark #define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100 3433c28c82e9SRob Clark #define A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200 3434ccdf7e28SRob Clark #define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 3435c28c82e9SRob Clark #define A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE 0x00000800 34362d756322SRob Clark #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000 34372d756322SRob Clark #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16 34382d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val) 34392d756322SRob Clark { 34402d756322SRob Clark return ((val) << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK; 34412d756322SRob Clark } 34422d756322SRob Clark 3443a69c5ed2SRob Clark #define REG_A6XX_RB_DEPTH_PLANE_CNTL 0x00008870 3444c28c82e9SRob Clark #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003 3445c28c82e9SRob Clark #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0 3446c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val) 3447c28c82e9SRob Clark { 3448c28c82e9SRob Clark return ((val) << A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK; 3449c28c82e9SRob Clark } 3450a69c5ed2SRob Clark 34512d756322SRob Clark #define REG_A6XX_RB_DEPTH_CNTL 0x00008871 3452*57cfe41cSRob Clark #define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000001 34532d756322SRob Clark #define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002 34542d756322SRob Clark #define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c 34552d756322SRob Clark #define A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2 34562d756322SRob Clark static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) 34572d756322SRob Clark { 34582d756322SRob Clark return ((val) << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK; 34592d756322SRob Clark } 3460c28c82e9SRob Clark #define A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE 0x00000020 3461*57cfe41cSRob Clark #define A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE 0x00000040 3462c28c82e9SRob Clark #define A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE 0x00000080 34632d756322SRob Clark 34642d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_INFO 0x00008872 34652d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 34662d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 34672d756322SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) 34682d756322SRob Clark { 34692d756322SRob Clark return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; 34702d756322SRob Clark } 3471c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000018 3472c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT 3 3473c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val) 3474c28c82e9SRob Clark { 3475c28c82e9SRob Clark return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK; 3476c28c82e9SRob Clark } 34772d756322SRob Clark 34782d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_PITCH 0x00008873 3479c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_PITCH__MASK 0x00003fff 34802d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0 34812d756322SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) 34822d756322SRob Clark { 34832d756322SRob Clark return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK; 34842d756322SRob Clark } 34852d756322SRob Clark 34862d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x00008874 3487c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0x0fffffff 34882d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0 34892d756322SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) 34902d756322SRob Clark { 34912d756322SRob Clark return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; 34922d756322SRob Clark } 34932d756322SRob Clark 3494c28c82e9SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_BASE 0x00008875 3495c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_BASE__MASK 0xffffffff 3496c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_BASE__SHIFT 0 3497c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE(uint32_t val) 3498c28c82e9SRob Clark { 3499c28c82e9SRob Clark return ((val) << A6XX_RB_DEPTH_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE__MASK; 3500c28c82e9SRob Clark } 3501c28c82e9SRob Clark 35022d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM 0x00008877 3503c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK 0xfffff000 3504c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT 12 3505c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE_GMEM(uint32_t val) 3506c28c82e9SRob Clark { 3507c28c82e9SRob Clark return ((val >> 12) << A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK; 3508c28c82e9SRob Clark } 35092d756322SRob Clark 3510c28c82e9SRob Clark #define REG_A6XX_RB_Z_BOUNDS_MIN 0x00008878 3511c28c82e9SRob Clark #define A6XX_RB_Z_BOUNDS_MIN__MASK 0xffffffff 3512c28c82e9SRob Clark #define A6XX_RB_Z_BOUNDS_MIN__SHIFT 0 3513c28c82e9SRob Clark static inline uint32_t A6XX_RB_Z_BOUNDS_MIN(float val) 3514c28c82e9SRob Clark { 3515c28c82e9SRob Clark return ((fui(val)) << A6XX_RB_Z_BOUNDS_MIN__SHIFT) & A6XX_RB_Z_BOUNDS_MIN__MASK; 3516c28c82e9SRob Clark } 35172d756322SRob Clark 3518c28c82e9SRob Clark #define REG_A6XX_RB_Z_BOUNDS_MAX 0x00008879 3519c28c82e9SRob Clark #define A6XX_RB_Z_BOUNDS_MAX__MASK 0xffffffff 3520c28c82e9SRob Clark #define A6XX_RB_Z_BOUNDS_MAX__SHIFT 0 3521c28c82e9SRob Clark static inline uint32_t A6XX_RB_Z_BOUNDS_MAX(float val) 3522c28c82e9SRob Clark { 3523c28c82e9SRob Clark return ((fui(val)) << A6XX_RB_Z_BOUNDS_MAX__SHIFT) & A6XX_RB_Z_BOUNDS_MAX__MASK; 3524c28c82e9SRob Clark } 35252d756322SRob Clark 35262d756322SRob Clark #define REG_A6XX_RB_STENCIL_CONTROL 0x00008880 35272d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 35282d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 35292d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 35302d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 35312d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 35322d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 35332d756322SRob Clark { 35342d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC__MASK; 35352d756322SRob Clark } 35362d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 35372d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 35382d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 35392d756322SRob Clark { 35402d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL__MASK; 35412d756322SRob Clark } 35422d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 35432d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 35442d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 35452d756322SRob Clark { 35462d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK; 35472d756322SRob Clark } 35482d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 35492d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 35502d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 35512d756322SRob Clark { 35522d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 35532d756322SRob Clark } 35542d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 35552d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 35562d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 35572d756322SRob Clark { 35582d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 35592d756322SRob Clark } 35602d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 35612d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 35622d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 35632d756322SRob Clark { 35642d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 35652d756322SRob Clark } 35662d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 35672d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 35682d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 35692d756322SRob Clark { 35702d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 35712d756322SRob Clark } 35722d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 35732d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 35742d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 35752d756322SRob Clark { 35762d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 35772d756322SRob Clark } 35782d756322SRob Clark 35792d756322SRob Clark #define REG_A6XX_RB_STENCIL_INFO 0x00008881 35802d756322SRob Clark #define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 3581c28c82e9SRob Clark #define A6XX_RB_STENCIL_INFO_UNK1 0x00000002 35822d756322SRob Clark 35832d756322SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_PITCH 0x00008882 3584c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_PITCH__MASK 0x00000fff 35852d756322SRob Clark #define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT 0 35862d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val) 35872d756322SRob Clark { 35882d756322SRob Clark return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK; 35892d756322SRob Clark } 35902d756322SRob Clark 35912d756322SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH 0x00008883 3592c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK 0x00ffffff 35932d756322SRob Clark #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT 0 35942d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val) 35952d756322SRob Clark { 35962d756322SRob Clark return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK; 35972d756322SRob Clark } 35982d756322SRob Clark 3599c28c82e9SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_BASE 0x00008884 3600c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_BASE__MASK 0xffffffff 3601c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_BASE__SHIFT 0 3602c28c82e9SRob Clark static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE(uint32_t val) 3603c28c82e9SRob Clark { 3604c28c82e9SRob Clark return ((val) << A6XX_RB_STENCIL_BUFFER_BASE__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE__MASK; 3605c28c82e9SRob Clark } 3606c28c82e9SRob Clark 36072d756322SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM 0x00008886 3608c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK 0xfffff000 3609c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT 12 3610c28c82e9SRob Clark static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE_GMEM(uint32_t val) 3611c28c82e9SRob Clark { 3612c28c82e9SRob Clark return ((val >> 12) << A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK; 3613c28c82e9SRob Clark } 36142d756322SRob Clark 36152d756322SRob Clark #define REG_A6XX_RB_STENCILREF 0x00008887 36162d756322SRob Clark #define A6XX_RB_STENCILREF_REF__MASK 0x000000ff 36172d756322SRob Clark #define A6XX_RB_STENCILREF_REF__SHIFT 0 36182d756322SRob Clark static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val) 36192d756322SRob Clark { 36202d756322SRob Clark return ((val) << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK; 36212d756322SRob Clark } 3622a69c5ed2SRob Clark #define A6XX_RB_STENCILREF_BFREF__MASK 0x0000ff00 3623a69c5ed2SRob Clark #define A6XX_RB_STENCILREF_BFREF__SHIFT 8 3624a69c5ed2SRob Clark static inline uint32_t A6XX_RB_STENCILREF_BFREF(uint32_t val) 3625a69c5ed2SRob Clark { 3626a69c5ed2SRob Clark return ((val) << A6XX_RB_STENCILREF_BFREF__SHIFT) & A6XX_RB_STENCILREF_BFREF__MASK; 3627a69c5ed2SRob Clark } 36282d756322SRob Clark 36292d756322SRob Clark #define REG_A6XX_RB_STENCILMASK 0x00008888 36302d756322SRob Clark #define A6XX_RB_STENCILMASK_MASK__MASK 0x000000ff 36312d756322SRob Clark #define A6XX_RB_STENCILMASK_MASK__SHIFT 0 36322d756322SRob Clark static inline uint32_t A6XX_RB_STENCILMASK_MASK(uint32_t val) 36332d756322SRob Clark { 36342d756322SRob Clark return ((val) << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK; 36352d756322SRob Clark } 3636a69c5ed2SRob Clark #define A6XX_RB_STENCILMASK_BFMASK__MASK 0x0000ff00 3637a69c5ed2SRob Clark #define A6XX_RB_STENCILMASK_BFMASK__SHIFT 8 3638a69c5ed2SRob Clark static inline uint32_t A6XX_RB_STENCILMASK_BFMASK(uint32_t val) 3639a69c5ed2SRob Clark { 3640a69c5ed2SRob Clark return ((val) << A6XX_RB_STENCILMASK_BFMASK__SHIFT) & A6XX_RB_STENCILMASK_BFMASK__MASK; 3641a69c5ed2SRob Clark } 36422d756322SRob Clark 36432d756322SRob Clark #define REG_A6XX_RB_STENCILWRMASK 0x00008889 36442d756322SRob Clark #define A6XX_RB_STENCILWRMASK_WRMASK__MASK 0x000000ff 36452d756322SRob Clark #define A6XX_RB_STENCILWRMASK_WRMASK__SHIFT 0 36462d756322SRob Clark static inline uint32_t A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val) 36472d756322SRob Clark { 36482d756322SRob Clark return ((val) << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK; 36492d756322SRob Clark } 3650a69c5ed2SRob Clark #define A6XX_RB_STENCILWRMASK_BFWRMASK__MASK 0x0000ff00 3651a69c5ed2SRob Clark #define A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT 8 3652a69c5ed2SRob Clark static inline uint32_t A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val) 3653a69c5ed2SRob Clark { 3654a69c5ed2SRob Clark return ((val) << A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_BFWRMASK__MASK; 3655a69c5ed2SRob Clark } 36562d756322SRob Clark 36572d756322SRob Clark #define REG_A6XX_RB_WINDOW_OFFSET 0x00008890 3658c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET_X__MASK 0x00003fff 36592d756322SRob Clark #define A6XX_RB_WINDOW_OFFSET_X__SHIFT 0 36602d756322SRob Clark static inline uint32_t A6XX_RB_WINDOW_OFFSET_X(uint32_t val) 36612d756322SRob Clark { 36622d756322SRob Clark return ((val) << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK; 36632d756322SRob Clark } 3664c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET_Y__MASK 0x3fff0000 36652d756322SRob Clark #define A6XX_RB_WINDOW_OFFSET_Y__SHIFT 16 36662d756322SRob Clark static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val) 36672d756322SRob Clark { 36682d756322SRob Clark return ((val) << A6XX_RB_WINDOW_OFFSET_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET_Y__MASK; 36692d756322SRob Clark } 36702d756322SRob Clark 36712d756322SRob Clark #define REG_A6XX_RB_SAMPLE_COUNT_CONTROL 0x00008891 3672c28c82e9SRob Clark #define A6XX_RB_SAMPLE_COUNT_CONTROL_UNK0 0x00000001 36732d756322SRob Clark #define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 36742d756322SRob Clark 3675ccdf7e28SRob Clark #define REG_A6XX_RB_LRZ_CNTL 0x00008898 3676ccdf7e28SRob Clark #define A6XX_RB_LRZ_CNTL_ENABLE 0x00000001 3677ccdf7e28SRob Clark 3678c28c82e9SRob Clark #define REG_A6XX_RB_Z_CLAMP_MIN 0x000088c0 3679c28c82e9SRob Clark #define A6XX_RB_Z_CLAMP_MIN__MASK 0xffffffff 3680c28c82e9SRob Clark #define A6XX_RB_Z_CLAMP_MIN__SHIFT 0 3681c28c82e9SRob Clark static inline uint32_t A6XX_RB_Z_CLAMP_MIN(float val) 3682c28c82e9SRob Clark { 3683c28c82e9SRob Clark return ((fui(val)) << A6XX_RB_Z_CLAMP_MIN__SHIFT) & A6XX_RB_Z_CLAMP_MIN__MASK; 3684c28c82e9SRob Clark } 3685c28c82e9SRob Clark 3686c28c82e9SRob Clark #define REG_A6XX_RB_Z_CLAMP_MAX 0x000088c1 3687c28c82e9SRob Clark #define A6XX_RB_Z_CLAMP_MAX__MASK 0xffffffff 3688c28c82e9SRob Clark #define A6XX_RB_Z_CLAMP_MAX__SHIFT 0 3689c28c82e9SRob Clark static inline uint32_t A6XX_RB_Z_CLAMP_MAX(float val) 3690c28c82e9SRob Clark { 3691c28c82e9SRob Clark return ((fui(val)) << A6XX_RB_Z_CLAMP_MAX__SHIFT) & A6XX_RB_Z_CLAMP_MAX__MASK; 3692c28c82e9SRob Clark } 3693c28c82e9SRob Clark 36942d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_88D0 0x000088d0 3695c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_88D0_UNK0__MASK 0x00001fff 3696c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT 0 3697c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK0(uint32_t val) 3698c28c82e9SRob Clark { 3699c28c82e9SRob Clark return ((val) << A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK0__MASK; 3700c28c82e9SRob Clark } 3701c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_88D0_UNK16__MASK 0x07ff0000 3702c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT 16 3703c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK16(uint32_t val) 3704c28c82e9SRob Clark { 3705c28c82e9SRob Clark return ((val) << A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK16__MASK; 3706c28c82e9SRob Clark } 37072d756322SRob Clark 37082d756322SRob Clark #define REG_A6XX_RB_BLIT_SCISSOR_TL 0x000088d1 3709c28c82e9SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_X__MASK 0x00003fff 37102d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT 0 37112d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val) 37122d756322SRob Clark { 37132d756322SRob Clark return ((val) << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK; 37142d756322SRob Clark } 3715c28c82e9SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK 0x3fff0000 37162d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT 16 37172d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val) 37182d756322SRob Clark { 37192d756322SRob Clark return ((val) << A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_Y__MASK; 37202d756322SRob Clark } 37212d756322SRob Clark 37222d756322SRob Clark #define REG_A6XX_RB_BLIT_SCISSOR_BR 0x000088d2 3723c28c82e9SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_X__MASK 0x00003fff 37242d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT 0 37252d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val) 37262d756322SRob Clark { 37272d756322SRob Clark return ((val) << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK; 37282d756322SRob Clark } 3729c28c82e9SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK 0x3fff0000 37302d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT 16 37312d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val) 37322d756322SRob Clark { 37332d756322SRob Clark return ((val) << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK; 37342d756322SRob Clark } 37352d756322SRob Clark 3736c28c82e9SRob Clark #define REG_A6XX_RB_BIN_CONTROL2 0x000088d3 3737c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL2_BINW__MASK 0x0000003f 3738c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL2_BINW__SHIFT 0 3739c28c82e9SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val) 3740c28c82e9SRob Clark { 3741c28c82e9SRob Clark return ((val >> 5) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK; 3742c28c82e9SRob Clark } 3743c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL2_BINH__MASK 0x00007f00 3744c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL2_BINH__SHIFT 8 3745c28c82e9SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val) 3746c28c82e9SRob Clark { 3747c28c82e9SRob Clark return ((val >> 4) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK; 3748c28c82e9SRob Clark } 3749c28c82e9SRob Clark 3750c28c82e9SRob Clark #define REG_A6XX_RB_WINDOW_OFFSET2 0x000088d4 3751c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET2_X__MASK 0x00003fff 3752c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET2_X__SHIFT 0 3753c28c82e9SRob Clark static inline uint32_t A6XX_RB_WINDOW_OFFSET2_X(uint32_t val) 3754c28c82e9SRob Clark { 3755c28c82e9SRob Clark return ((val) << A6XX_RB_WINDOW_OFFSET2_X__SHIFT) & A6XX_RB_WINDOW_OFFSET2_X__MASK; 3756c28c82e9SRob Clark } 3757c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET2_Y__MASK 0x3fff0000 3758c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET2_Y__SHIFT 16 3759c28c82e9SRob Clark static inline uint32_t A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val) 3760c28c82e9SRob Clark { 3761c28c82e9SRob Clark return ((val) << A6XX_RB_WINDOW_OFFSET2_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET2_Y__MASK; 3762c28c82e9SRob Clark } 3763c28c82e9SRob Clark 3764ccdf7e28SRob Clark #define REG_A6XX_RB_MSAA_CNTL 0x000088d5 3765ccdf7e28SRob Clark #define A6XX_RB_MSAA_CNTL_SAMPLES__MASK 0x00000018 3766ccdf7e28SRob Clark #define A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT 3 3767ccdf7e28SRob Clark static inline uint32_t A6XX_RB_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 3768ccdf7e28SRob Clark { 3769ccdf7e28SRob Clark return ((val) << A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_MSAA_CNTL_SAMPLES__MASK; 3770ccdf7e28SRob Clark } 3771ccdf7e28SRob Clark 37722d756322SRob Clark #define REG_A6XX_RB_BLIT_BASE_GMEM 0x000088d6 3773c28c82e9SRob Clark #define A6XX_RB_BLIT_BASE_GMEM__MASK 0xfffff000 3774c28c82e9SRob Clark #define A6XX_RB_BLIT_BASE_GMEM__SHIFT 12 3775c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_BASE_GMEM(uint32_t val) 3776c28c82e9SRob Clark { 3777c28c82e9SRob Clark return ((val >> 12) << A6XX_RB_BLIT_BASE_GMEM__SHIFT) & A6XX_RB_BLIT_BASE_GMEM__MASK; 3778c28c82e9SRob Clark } 37792d756322SRob Clark 37802d756322SRob Clark #define REG_A6XX_RB_BLIT_DST_INFO 0x000088d7 37812d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK 0x00000003 37822d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT 0 37832d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) 37842d756322SRob Clark { 37852d756322SRob Clark return ((val) << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK; 37862d756322SRob Clark } 37872d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_FLAGS 0x00000004 3788ccdf7e28SRob Clark #define A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK 0x00000018 3789ccdf7e28SRob Clark #define A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT 3 3790ccdf7e28SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) 3791ccdf7e28SRob Clark { 3792ccdf7e28SRob Clark return ((val) << A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK; 3793ccdf7e28SRob Clark } 37942d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK 0x00000060 37952d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT 5 37962d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) 37972d756322SRob Clark { 37982d756322SRob Clark return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK; 37992d756322SRob Clark } 3800c28c82e9SRob Clark #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK 0x00007f80 3801c28c82e9SRob Clark #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT 7 3802c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_format val) 3803c28c82e9SRob Clark { 3804c28c82e9SRob Clark return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK; 3805c28c82e9SRob Clark } 3806c28c82e9SRob Clark #define A6XX_RB_BLIT_DST_INFO_UNK15 0x00008000 3807c28c82e9SRob Clark 3808c28c82e9SRob Clark #define REG_A6XX_RB_BLIT_DST 0x000088d8 3809c28c82e9SRob Clark #define A6XX_RB_BLIT_DST__MASK 0xffffffff 3810c28c82e9SRob Clark #define A6XX_RB_BLIT_DST__SHIFT 0 3811c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_DST(uint32_t val) 3812c28c82e9SRob Clark { 3813c28c82e9SRob Clark return ((val) << A6XX_RB_BLIT_DST__SHIFT) & A6XX_RB_BLIT_DST__MASK; 3814c28c82e9SRob Clark } 38152d756322SRob Clark 38162d756322SRob Clark #define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da 3817c28c82e9SRob Clark #define A6XX_RB_BLIT_DST_PITCH__MASK 0x0000ffff 38182d756322SRob Clark #define A6XX_RB_BLIT_DST_PITCH__SHIFT 0 38192d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val) 38202d756322SRob Clark { 38212d756322SRob Clark return ((val >> 6) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK; 38222d756322SRob Clark } 38232d756322SRob Clark 38242d756322SRob Clark #define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH 0x000088db 3825c28c82e9SRob Clark #define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0x1fffffff 38262d756322SRob Clark #define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0 38272d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) 38282d756322SRob Clark { 38292d756322SRob Clark return ((val >> 6) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK; 38302d756322SRob Clark } 38312d756322SRob Clark 3832c28c82e9SRob Clark #define REG_A6XX_RB_BLIT_FLAG_DST 0x000088dc 3833c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST__MASK 0xffffffff 3834c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST__SHIFT 0 3835c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_FLAG_DST(uint32_t val) 3836c28c82e9SRob Clark { 3837c28c82e9SRob Clark return ((val) << A6XX_RB_BLIT_FLAG_DST__SHIFT) & A6XX_RB_BLIT_FLAG_DST__MASK; 3838c28c82e9SRob Clark } 3839c28c82e9SRob Clark 3840c28c82e9SRob Clark #define REG_A6XX_RB_BLIT_FLAG_DST_PITCH 0x000088de 3841c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK 0x000007ff 3842c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT 0 3843c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val) 3844c28c82e9SRob Clark { 3845c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK; 3846c28c82e9SRob Clark } 3847c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK 0x0ffff800 3848c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT 11 3849c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val) 3850c28c82e9SRob Clark { 3851c28c82e9SRob Clark return ((val >> 7) << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK; 3852c28c82e9SRob Clark } 3853c28c82e9SRob Clark 38542d756322SRob Clark #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 0x000088df 38552d756322SRob Clark 38562d756322SRob Clark #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1 0x000088e0 38572d756322SRob Clark 38582d756322SRob Clark #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2 0x000088e1 38592d756322SRob Clark 38602d756322SRob Clark #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3 0x000088e2 38612d756322SRob Clark 38622d756322SRob Clark #define REG_A6XX_RB_BLIT_INFO 0x000088e3 38632d756322SRob Clark #define A6XX_RB_BLIT_INFO_UNK0 0x00000001 3864a69c5ed2SRob Clark #define A6XX_RB_BLIT_INFO_GMEM 0x00000002 3865cc4c26d4SRob Clark #define A6XX_RB_BLIT_INFO_SAMPLE_0 0x00000004 3866a69c5ed2SRob Clark #define A6XX_RB_BLIT_INFO_DEPTH 0x00000008 3867a69c5ed2SRob Clark #define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK 0x000000f0 3868a69c5ed2SRob Clark #define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT 4 3869a69c5ed2SRob Clark static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val) 38702d756322SRob Clark { 3871a69c5ed2SRob Clark return ((val) << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK; 38722d756322SRob Clark } 3873c28c82e9SRob Clark #define A6XX_RB_BLIT_INFO_UNK8__MASK 0x00000300 3874c28c82e9SRob Clark #define A6XX_RB_BLIT_INFO_UNK8__SHIFT 8 3875c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_INFO_UNK8(uint32_t val) 3876c28c82e9SRob Clark { 3877c28c82e9SRob Clark return ((val) << A6XX_RB_BLIT_INFO_UNK8__SHIFT) & A6XX_RB_BLIT_INFO_UNK8__MASK; 3878c28c82e9SRob Clark } 3879c28c82e9SRob Clark #define A6XX_RB_BLIT_INFO_UNK12__MASK 0x0000f000 3880c28c82e9SRob Clark #define A6XX_RB_BLIT_INFO_UNK12__SHIFT 12 3881c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_INFO_UNK12(uint32_t val) 3882c28c82e9SRob Clark { 3883c28c82e9SRob Clark return ((val) << A6XX_RB_BLIT_INFO_UNK12__SHIFT) & A6XX_RB_BLIT_INFO_UNK12__MASK; 3884c28c82e9SRob Clark } 38852d756322SRob Clark 38862d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_88F0 0x000088f0 38872d756322SRob Clark 3888c28c82e9SRob Clark #define REG_A6XX_RB_UNK_FLAG_BUFFER_BASE 0x000088f1 3889c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK 0xffffffff 3890c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT 0 3891c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_BASE(uint32_t val) 3892c28c82e9SRob Clark { 3893c28c82e9SRob Clark return ((val) << A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK; 3894c28c82e9SRob Clark } 3895c28c82e9SRob Clark 3896c28c82e9SRob Clark #define REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH 0x000088f3 3897c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff 3898c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 3899c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(uint32_t val) 3900c28c82e9SRob Clark { 3901c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK; 3902c28c82e9SRob Clark } 3903c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x00fff800 3904c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 3905c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 3906c28c82e9SRob Clark { 3907c28c82e9SRob Clark return ((val >> 7) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; 3908c28c82e9SRob Clark } 3909c28c82e9SRob Clark 3910c28c82e9SRob Clark #define REG_A6XX_RB_UNKNOWN_88F4 0x000088f4 3911c28c82e9SRob Clark 3912c28c82e9SRob Clark #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE 0x00008900 3913c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK 0xffffffff 3914c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT 0 3915c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_BASE(uint32_t val) 3916c28c82e9SRob Clark { 3917c28c82e9SRob Clark return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK; 3918c28c82e9SRob Clark } 3919c28c82e9SRob Clark 39202d756322SRob Clark #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x00008902 3921c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK 0x0000007f 3922c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 3923c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val) 3924c28c82e9SRob Clark { 3925c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK; 3926c28c82e9SRob Clark } 3927c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK 0x00000700 3928c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT 8 3929c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8(uint32_t val) 3930c28c82e9SRob Clark { 3931c28c82e9SRob Clark return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK; 3932c28c82e9SRob Clark } 3933c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x0ffff800 3934c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 3935c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 3936c28c82e9SRob Clark { 3937c28c82e9SRob Clark return ((val >> 7) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; 3938c28c82e9SRob Clark } 39392d756322SRob Clark 39402d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; } 39412d756322SRob Clark 3942c28c82e9SRob Clark static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; } 3943c28c82e9SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK 0xffffffff 3944c28c82e9SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT 0 3945c28c82e9SRob Clark static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t val) 3946c28c82e9SRob Clark { 3947c28c82e9SRob Clark return ((val) << A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK; 3948c28c82e9SRob Clark } 3949c28c82e9SRob Clark 39502d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; } 39512d756322SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff 39522d756322SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 39532d756322SRob Clark static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val) 39542d756322SRob Clark { 3955c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK; 39562d756322SRob Clark } 3957c28c82e9SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffff800 39582d756322SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 39592d756322SRob Clark static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 39602d756322SRob Clark { 3961c28c82e9SRob Clark return ((val >> 7) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; 39622d756322SRob Clark } 39632d756322SRob Clark 3964c28c82e9SRob Clark #define REG_A6XX_RB_SAMPLE_COUNT_ADDR 0x00008927 3965c28c82e9SRob Clark #define A6XX_RB_SAMPLE_COUNT_ADDR__MASK 0xffffffff 3966c28c82e9SRob Clark #define A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT 0 3967c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_COUNT_ADDR(uint32_t val) 3968c28c82e9SRob Clark { 3969c28c82e9SRob Clark return ((val) << A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT) & A6XX_RB_SAMPLE_COUNT_ADDR__MASK; 3970c28c82e9SRob Clark } 3971c28c82e9SRob Clark 3972*57cfe41cSRob Clark #define REG_A6XX_RB_UNKNOWN_8A00 0x00008a00 3973*57cfe41cSRob Clark 3974*57cfe41cSRob Clark #define REG_A6XX_RB_UNKNOWN_8A10 0x00008a10 3975*57cfe41cSRob Clark 3976*57cfe41cSRob Clark #define REG_A6XX_RB_UNKNOWN_8A20 0x00008a20 3977*57cfe41cSRob Clark 3978*57cfe41cSRob Clark #define REG_A6XX_RB_UNKNOWN_8A30 0x00008a30 3979*57cfe41cSRob Clark 39802d756322SRob Clark #define REG_A6XX_RB_2D_BLIT_CNTL 0x00008c00 3981c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK 0x00000007 3982c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT 0 3983c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val) 3984c28c82e9SRob Clark { 3985c28c82e9SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK; 3986c28c82e9SRob Clark } 3987*57cfe41cSRob Clark #define A6XX_RB_2D_BLIT_CNTL_OVERWRITEEN 0x00000008 3988*57cfe41cSRob Clark #define A6XX_RB_2D_BLIT_CNTL_UNK4__MASK 0x00000070 3989*57cfe41cSRob Clark #define A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT 4 3990*57cfe41cSRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK4(uint32_t val) 3991c28c82e9SRob Clark { 3992*57cfe41cSRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK4__MASK; 3993c28c82e9SRob Clark } 3994c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR 0x00000080 39952d756322SRob Clark #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00 39962d756322SRob Clark #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8 3997c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val) 39982d756322SRob Clark { 39992d756322SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK; 40002d756322SRob Clark } 4001ccdf7e28SRob Clark #define A6XX_RB_2D_BLIT_CNTL_SCISSOR 0x00010000 4002c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_UNK17__MASK 0x00060000 4003c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT 17 4004c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK17(uint32_t val) 4005c28c82e9SRob Clark { 4006c28c82e9SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK17__MASK; 4007c28c82e9SRob Clark } 4008c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_D24S8 0x00080000 4009c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_MASK__MASK 0x00f00000 4010c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT 20 4011c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_MASK(uint32_t val) 4012c28c82e9SRob Clark { 4013c28c82e9SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_RB_2D_BLIT_CNTL_MASK__MASK; 4014c28c82e9SRob Clark } 4015c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_IFMT__MASK 0x1f000000 4016c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT 24 4017c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val) 4018c28c82e9SRob Clark { 4019c28c82e9SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_IFMT__MASK; 4020c28c82e9SRob Clark } 4021*57cfe41cSRob Clark #define A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK 0x20000000 4022*57cfe41cSRob Clark #define A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT 29 4023*57cfe41cSRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val) 4024c28c82e9SRob Clark { 4025*57cfe41cSRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK; 4026c28c82e9SRob Clark } 4027ccdf7e28SRob Clark 4028c28c82e9SRob Clark #define REG_A6XX_RB_2D_UNKNOWN_8C01 0x00008c01 40292d756322SRob Clark 40302d756322SRob Clark #define REG_A6XX_RB_2D_DST_INFO 0x00008c17 40312d756322SRob Clark #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff 40322d756322SRob Clark #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0 4033c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_format val) 40342d756322SRob Clark { 40352d756322SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK; 40362d756322SRob Clark } 40372d756322SRob Clark #define A6XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300 40382d756322SRob Clark #define A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8 40392d756322SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) 40402d756322SRob Clark { 40412d756322SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_2D_DST_INFO_TILE_MODE__MASK; 40422d756322SRob Clark } 40432d756322SRob Clark #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00 40442d756322SRob Clark #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10 40452d756322SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) 40462d756322SRob Clark { 40472d756322SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK; 40482d756322SRob Clark } 40492d756322SRob Clark #define A6XX_RB_2D_DST_INFO_FLAGS 0x00001000 4050c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_SRGB 0x00002000 4051c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_SAMPLES__MASK 0x0000c000 4052c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT 14 4053c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) 4054c28c82e9SRob Clark { 4055c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_2D_DST_INFO_SAMPLES__MASK; 4056c28c82e9SRob Clark } 4057c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_FILTER 0x00010000 4058cc4c26d4SRob Clark #define A6XX_RB_2D_DST_INFO_UNK17 0x00020000 4059c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE 0x00040000 4060cc4c26d4SRob Clark #define A6XX_RB_2D_DST_INFO_UNK19 0x00080000 4061c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_UNK20 0x00100000 4062cc4c26d4SRob Clark #define A6XX_RB_2D_DST_INFO_UNK21 0x00200000 4063c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_UNK22 0x00400000 4064cc4c26d4SRob Clark #define A6XX_RB_2D_DST_INFO_UNK23__MASK 0x07800000 4065cc4c26d4SRob Clark #define A6XX_RB_2D_DST_INFO_UNK23__SHIFT 23 4066cc4c26d4SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_UNK23(uint32_t val) 4067cc4c26d4SRob Clark { 4068cc4c26d4SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_UNK23__SHIFT) & A6XX_RB_2D_DST_INFO_UNK23__MASK; 4069cc4c26d4SRob Clark } 4070cc4c26d4SRob Clark #define A6XX_RB_2D_DST_INFO_UNK28 0x10000000 40712d756322SRob Clark 4072c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST 0x00008c18 4073c28c82e9SRob Clark #define A6XX_RB_2D_DST__MASK 0xffffffff 4074c28c82e9SRob Clark #define A6XX_RB_2D_DST__SHIFT 0 4075c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST(uint32_t val) 40762d756322SRob Clark { 4077c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST__SHIFT) & A6XX_RB_2D_DST__MASK; 4078c28c82e9SRob Clark } 4079c28c82e9SRob Clark 4080c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_PITCH 0x00008c1a 4081c28c82e9SRob Clark #define A6XX_RB_2D_DST_PITCH__MASK 0x0000ffff 4082c28c82e9SRob Clark #define A6XX_RB_2D_DST_PITCH__SHIFT 0 4083c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_PITCH(uint32_t val) 4084c28c82e9SRob Clark { 4085c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_2D_DST_PITCH__SHIFT) & A6XX_RB_2D_DST_PITCH__MASK; 4086c28c82e9SRob Clark } 4087c28c82e9SRob Clark 4088c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_PLANE1 0x00008c1b 4089c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE1__MASK 0xffffffff 4090c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE1__SHIFT 0 4091c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_PLANE1(uint32_t val) 4092c28c82e9SRob Clark { 4093c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST_PLANE1__SHIFT) & A6XX_RB_2D_DST_PLANE1__MASK; 4094c28c82e9SRob Clark } 4095c28c82e9SRob Clark 4096c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_PLANE_PITCH 0x00008c1d 4097c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE_PITCH__MASK 0x0000ffff 4098c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE_PITCH__SHIFT 0 4099c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_PLANE_PITCH(uint32_t val) 4100c28c82e9SRob Clark { 4101c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_2D_DST_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_PLANE_PITCH__MASK; 4102c28c82e9SRob Clark } 4103c28c82e9SRob Clark 4104c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_PLANE2 0x00008c1e 4105c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE2__MASK 0xffffffff 4106c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE2__SHIFT 0 4107c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_PLANE2(uint32_t val) 4108c28c82e9SRob Clark { 4109c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST_PLANE2__SHIFT) & A6XX_RB_2D_DST_PLANE2__MASK; 41102d756322SRob Clark } 41112d756322SRob Clark 4112c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_FLAGS 0x00008c20 4113c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS__MASK 0xffffffff 4114c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS__SHIFT 0 4115c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_FLAGS(uint32_t val) 4116c28c82e9SRob Clark { 4117c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST_FLAGS__SHIFT) & A6XX_RB_2D_DST_FLAGS__MASK; 4118c28c82e9SRob Clark } 4119c28c82e9SRob Clark 4120c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_FLAGS_PITCH 0x00008c22 4121c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PITCH__MASK 0x000000ff 4122c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT 0 4123c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_FLAGS_PITCH(uint32_t val) 4124c28c82e9SRob Clark { 4125c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH__MASK; 4126c28c82e9SRob Clark } 4127c28c82e9SRob Clark 4128c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_FLAGS_PLANE 0x00008c23 4129c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PLANE__MASK 0xffffffff 4130c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT 0 4131c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE(uint32_t val) 4132c28c82e9SRob Clark { 4133c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE__MASK; 4134c28c82e9SRob Clark } 4135c28c82e9SRob Clark 4136c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH 0x00008c25 4137c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK 0x000000ff 4138c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT 0 4139c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(uint32_t val) 4140c28c82e9SRob Clark { 4141c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK; 4142c28c82e9SRob Clark } 4143c28c82e9SRob Clark 41442d756322SRob Clark #define REG_A6XX_RB_2D_SRC_SOLID_C0 0x00008c2c 41452d756322SRob Clark 41462d756322SRob Clark #define REG_A6XX_RB_2D_SRC_SOLID_C1 0x00008c2d 41472d756322SRob Clark 41482d756322SRob Clark #define REG_A6XX_RB_2D_SRC_SOLID_C2 0x00008c2e 41492d756322SRob Clark 41502d756322SRob Clark #define REG_A6XX_RB_2D_SRC_SOLID_C3 0x00008c2f 41512d756322SRob Clark 41522d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8E01 0x00008e01 41532d756322SRob Clark 4154a69c5ed2SRob Clark #define REG_A6XX_RB_UNKNOWN_8E04 0x00008e04 4155a69c5ed2SRob Clark 4156c28c82e9SRob Clark #define REG_A6XX_RB_ADDR_MODE_CNTL 0x00008e05 4157c28c82e9SRob Clark 41582d756322SRob Clark #define REG_A6XX_RB_CCU_CNTL 0x00008e07 4159*57cfe41cSRob Clark #define A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK 0xff800000 4160*57cfe41cSRob Clark #define A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT 23 4161*57cfe41cSRob Clark static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_OFFSET(uint32_t val) 4162c28c82e9SRob Clark { 4163*57cfe41cSRob Clark return ((val >> 12) << A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK; 4164*57cfe41cSRob Clark } 4165*57cfe41cSRob Clark #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK 0x001ff000 4166*57cfe41cSRob Clark #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT 12 4167*57cfe41cSRob Clark static inline uint32_t A6XX_RB_CCU_CNTL_DEPTH_OFFSET(uint32_t val) 4168*57cfe41cSRob Clark { 4169*57cfe41cSRob Clark return ((val >> 12) << A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK; 4170c28c82e9SRob Clark } 4171c28c82e9SRob Clark #define A6XX_RB_CCU_CNTL_GMEM 0x00400000 4172c28c82e9SRob Clark #define A6XX_RB_CCU_CNTL_UNK2 0x00000004 41732d756322SRob Clark 4174c28c82e9SRob Clark #define REG_A6XX_RB_NC_MODE_CNTL 0x00008e08 4175c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_MODE 0x00000001 4176c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006 4177c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT 1 4178c28c82e9SRob Clark static inline uint32_t A6XX_RB_NC_MODE_CNTL_LOWER_BIT(uint32_t val) 4179c28c82e9SRob Clark { 4180c28c82e9SRob Clark return ((val) << A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK; 4181c28c82e9SRob Clark } 4182c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008 4183c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_AMSBC 0x00000010 4184c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000400 4185c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT 10 4186c28c82e9SRob Clark static inline uint32_t A6XX_RB_NC_MODE_CNTL_UPPER_BIT(uint32_t val) 4187c28c82e9SRob Clark { 4188c28c82e9SRob Clark return ((val) << A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK; 4189c28c82e9SRob Clark } 4190c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR 0x00000800 4191c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_UNK12__MASK 0x00003000 4192c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT 12 4193c28c82e9SRob Clark static inline uint32_t A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val) 4194c28c82e9SRob Clark { 4195c28c82e9SRob Clark return ((val) << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK; 4196c28c82e9SRob Clark } 41972d756322SRob Clark 4198cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RB_PERFCTR_RB_SEL(uint32_t i0) { return 0x00008e10 + 0x1*i0; } 4199c28c82e9SRob Clark 4200cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RB_PERFCTR_CCU_SEL(uint32_t i0) { return 0x00008e18 + 0x1*i0; } 4201c28c82e9SRob Clark 4202c28c82e9SRob Clark #define REG_A6XX_RB_UNKNOWN_8E28 0x00008e28 4203c28c82e9SRob Clark 4204cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RB_PERFCTR_CMP_SEL(uint32_t i0) { return 0x00008e2c + 0x1*i0; } 4205c28c82e9SRob Clark 4206c28c82e9SRob Clark #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST 0x00008e3b 4207c28c82e9SRob Clark 4208c28c82e9SRob Clark #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD 0x00008e3d 4209c28c82e9SRob Clark 4210c28c82e9SRob Clark #define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x00008e50 4211c28c82e9SRob Clark 4212c28c82e9SRob Clark #define REG_A6XX_RB_UNKNOWN_8E51 0x00008e51 4213c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_8E51__MASK 0xffffffff 4214c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_8E51__SHIFT 0 4215c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNKNOWN_8E51(uint32_t val) 4216c28c82e9SRob Clark { 4217c28c82e9SRob Clark return ((val) << A6XX_RB_UNKNOWN_8E51__SHIFT) & A6XX_RB_UNKNOWN_8E51__MASK; 4218c28c82e9SRob Clark } 4219c28c82e9SRob Clark 4220*57cfe41cSRob Clark #define REG_A6XX_VPC_GS_PARAM 0x00009100 4221*57cfe41cSRob Clark #define A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK 0x000000ff 4222*57cfe41cSRob Clark #define A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT 0 4223*57cfe41cSRob Clark static inline uint32_t A6XX_VPC_GS_PARAM_LINELENGTHLOC(uint32_t val) 4224*57cfe41cSRob Clark { 4225*57cfe41cSRob Clark return ((val) << A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT) & A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK; 4226*57cfe41cSRob Clark } 4227c28c82e9SRob Clark 4228c28c82e9SRob Clark #define REG_A6XX_VPC_VS_CLIP_CNTL 0x00009101 4229c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff 4230c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT 0 4231c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(uint32_t val) 4232c28c82e9SRob Clark { 4233c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK; 4234c28c82e9SRob Clark } 4235c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00 4236c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8 4237c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) 4238c28c82e9SRob Clark { 4239c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK; 4240c28c82e9SRob Clark } 4241c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000 4242c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16 4243c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) 4244c28c82e9SRob Clark { 4245c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; 4246c28c82e9SRob Clark } 4247c28c82e9SRob Clark 4248c28c82e9SRob Clark #define REG_A6XX_VPC_GS_CLIP_CNTL 0x00009102 4249c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff 4250c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT 0 4251c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK(uint32_t val) 4252c28c82e9SRob Clark { 4253c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK; 4254c28c82e9SRob Clark } 4255c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00 4256c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8 4257c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) 4258c28c82e9SRob Clark { 4259c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK; 4260c28c82e9SRob Clark } 4261c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000 4262c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16 4263c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) 4264c28c82e9SRob Clark { 4265c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; 4266c28c82e9SRob Clark } 4267c28c82e9SRob Clark 4268c28c82e9SRob Clark #define REG_A6XX_VPC_DS_CLIP_CNTL 0x00009103 4269c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff 4270c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT 0 4271c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK(uint32_t val) 4272c28c82e9SRob Clark { 4273c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK; 4274c28c82e9SRob Clark } 4275c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00 4276c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8 4277c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) 4278c28c82e9SRob Clark { 4279c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK; 4280c28c82e9SRob Clark } 4281c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000 4282c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16 4283c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) 4284c28c82e9SRob Clark { 4285c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; 4286c28c82e9SRob Clark } 4287c28c82e9SRob Clark 4288c28c82e9SRob Clark #define REG_A6XX_VPC_VS_LAYER_CNTL 0x00009104 4289c28c82e9SRob Clark #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff 4290c28c82e9SRob Clark #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT 0 4291c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(uint32_t val) 4292c28c82e9SRob Clark { 4293c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK; 4294c28c82e9SRob Clark } 4295c28c82e9SRob Clark #define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00 4296c28c82e9SRob Clark #define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT 8 4297c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(uint32_t val) 4298c28c82e9SRob Clark { 4299c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK; 4300c28c82e9SRob Clark } 4301c28c82e9SRob Clark 4302c28c82e9SRob Clark #define REG_A6XX_VPC_GS_LAYER_CNTL 0x00009105 4303c28c82e9SRob Clark #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff 4304c28c82e9SRob Clark #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT 0 4305c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(uint32_t val) 4306c28c82e9SRob Clark { 4307c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK; 4308c28c82e9SRob Clark } 4309c28c82e9SRob Clark #define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00 4310c28c82e9SRob Clark #define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT 8 4311c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(uint32_t val) 4312c28c82e9SRob Clark { 4313c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK; 4314c28c82e9SRob Clark } 4315c28c82e9SRob Clark 4316c28c82e9SRob Clark #define REG_A6XX_VPC_DS_LAYER_CNTL 0x00009106 4317c28c82e9SRob Clark #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff 4318c28c82e9SRob Clark #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT 0 4319c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_LAYERLOC(uint32_t val) 4320c28c82e9SRob Clark { 4321c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK; 4322c28c82e9SRob Clark } 4323c28c82e9SRob Clark #define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00 4324c28c82e9SRob Clark #define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT 8 4325c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val) 4326c28c82e9SRob Clark { 4327c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK; 4328c28c82e9SRob Clark } 43292d756322SRob Clark 4330a69c5ed2SRob Clark #define REG_A6XX_VPC_UNKNOWN_9107 0x00009107 4331cc4c26d4SRob Clark #define A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD 0x00000001 4332cc4c26d4SRob Clark #define A6XX_VPC_UNKNOWN_9107_UNK2 0x00000004 4333a69c5ed2SRob Clark 4334c28c82e9SRob Clark #define REG_A6XX_VPC_POLYGON_MODE 0x00009108 4335c28c82e9SRob Clark #define A6XX_VPC_POLYGON_MODE_MODE__MASK 0x00000003 4336c28c82e9SRob Clark #define A6XX_VPC_POLYGON_MODE_MODE__SHIFT 0 4337c28c82e9SRob Clark static inline uint32_t A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) 4338c28c82e9SRob Clark { 4339c28c82e9SRob Clark return ((val) << A6XX_VPC_POLYGON_MODE_MODE__SHIFT) & A6XX_VPC_POLYGON_MODE_MODE__MASK; 4340c28c82e9SRob Clark } 43412d756322SRob Clark 43422d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; } 43432d756322SRob Clark 43442d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; } 43452d756322SRob Clark 43462d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; } 43472d756322SRob Clark 43482d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; } 43492d756322SRob Clark 43502d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9210 0x00009210 43512d756322SRob Clark 43522d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9211 0x00009211 43532d756322SRob Clark 43542d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; } 43552d756322SRob Clark 43562d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; } 43572d756322SRob Clark 43582d756322SRob Clark #define REG_A6XX_VPC_SO_CNTL 0x00009216 4359cc4c26d4SRob Clark #define A6XX_VPC_SO_CNTL_ADDR__MASK 0x000000ff 4360cc4c26d4SRob Clark #define A6XX_VPC_SO_CNTL_ADDR__SHIFT 0 4361cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_SO_CNTL_ADDR(uint32_t val) 4362c28c82e9SRob Clark { 4363cc4c26d4SRob Clark return ((val) << A6XX_VPC_SO_CNTL_ADDR__SHIFT) & A6XX_VPC_SO_CNTL_ADDR__MASK; 4364c28c82e9SRob Clark } 4365cc4c26d4SRob Clark #define A6XX_VPC_SO_CNTL_RESET 0x00010000 43662d756322SRob Clark 43672d756322SRob Clark #define REG_A6XX_VPC_SO_PROG 0x00009217 43682d756322SRob Clark #define A6XX_VPC_SO_PROG_A_BUF__MASK 0x00000003 43692d756322SRob Clark #define A6XX_VPC_SO_PROG_A_BUF__SHIFT 0 43702d756322SRob Clark static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val) 43712d756322SRob Clark { 43722d756322SRob Clark return ((val) << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK; 43732d756322SRob Clark } 43742d756322SRob Clark #define A6XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc 43752d756322SRob Clark #define A6XX_VPC_SO_PROG_A_OFF__SHIFT 2 43762d756322SRob Clark static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val) 43772d756322SRob Clark { 43782d756322SRob Clark return ((val >> 2) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK; 43792d756322SRob Clark } 43802d756322SRob Clark #define A6XX_VPC_SO_PROG_A_EN 0x00000800 43812d756322SRob Clark #define A6XX_VPC_SO_PROG_B_BUF__MASK 0x00003000 43822d756322SRob Clark #define A6XX_VPC_SO_PROG_B_BUF__SHIFT 12 43832d756322SRob Clark static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val) 43842d756322SRob Clark { 43852d756322SRob Clark return ((val) << A6XX_VPC_SO_PROG_B_BUF__SHIFT) & A6XX_VPC_SO_PROG_B_BUF__MASK; 43862d756322SRob Clark } 43872d756322SRob Clark #define A6XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000 43882d756322SRob Clark #define A6XX_VPC_SO_PROG_B_OFF__SHIFT 14 43892d756322SRob Clark static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val) 43902d756322SRob Clark { 43912d756322SRob Clark return ((val >> 2) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK; 43922d756322SRob Clark } 43932d756322SRob Clark #define A6XX_VPC_SO_PROG_B_EN 0x00800000 43942d756322SRob Clark 4395c28c82e9SRob Clark #define REG_A6XX_VPC_SO_STREAM_COUNTS 0x00009218 4396c28c82e9SRob Clark #define A6XX_VPC_SO_STREAM_COUNTS__MASK 0xffffffff 4397c28c82e9SRob Clark #define A6XX_VPC_SO_STREAM_COUNTS__SHIFT 0 4398c28c82e9SRob Clark static inline uint32_t A6XX_VPC_SO_STREAM_COUNTS(uint32_t val) 4399c28c82e9SRob Clark { 4400c28c82e9SRob Clark return ((val) << A6XX_VPC_SO_STREAM_COUNTS__SHIFT) & A6XX_VPC_SO_STREAM_COUNTS__MASK; 4401c28c82e9SRob Clark } 4402c28c82e9SRob Clark 44032d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; } 44042d756322SRob Clark 4405c28c82e9SRob Clark static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0) { return 0x0000921a + 0x7*i0; } 4406c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_BASE__MASK 0xffffffff 4407c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_BASE__SHIFT 0 4408c28c82e9SRob Clark static inline uint32_t A6XX_VPC_SO_BUFFER_BASE(uint32_t val) 4409c28c82e9SRob Clark { 4410c28c82e9SRob Clark return ((val) << A6XX_VPC_SO_BUFFER_BASE__SHIFT) & A6XX_VPC_SO_BUFFER_BASE__MASK; 4411c28c82e9SRob Clark } 4412c28c82e9SRob Clark 44132d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; } 4414c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_SIZE__MASK 0xfffffffc 4415c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_SIZE__SHIFT 2 4416c28c82e9SRob Clark static inline uint32_t A6XX_VPC_SO_BUFFER_SIZE(uint32_t val) 4417c28c82e9SRob Clark { 4418c28c82e9SRob Clark return ((val >> 2) << A6XX_VPC_SO_BUFFER_SIZE__SHIFT) & A6XX_VPC_SO_BUFFER_SIZE__MASK; 4419c28c82e9SRob Clark } 44202d756322SRob Clark 44212d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000921d + 0x7*i0; } 44222d756322SRob Clark 44232d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; } 4424c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_OFFSET__MASK 0xfffffffc 4425c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_OFFSET__SHIFT 2 4426c28c82e9SRob Clark static inline uint32_t A6XX_VPC_SO_BUFFER_OFFSET(uint32_t val) 4427c28c82e9SRob Clark { 4428c28c82e9SRob Clark return ((val >> 2) << A6XX_VPC_SO_BUFFER_OFFSET__SHIFT) & A6XX_VPC_SO_BUFFER_OFFSET__MASK; 4429c28c82e9SRob Clark } 4430c28c82e9SRob Clark 4431c28c82e9SRob Clark static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0) { return 0x0000921f + 0x7*i0; } 4432c28c82e9SRob Clark #define A6XX_VPC_SO_FLUSH_BASE__MASK 0xffffffff 4433c28c82e9SRob Clark #define A6XX_VPC_SO_FLUSH_BASE__SHIFT 0 4434c28c82e9SRob Clark static inline uint32_t A6XX_VPC_SO_FLUSH_BASE(uint32_t val) 4435c28c82e9SRob Clark { 4436c28c82e9SRob Clark return ((val) << A6XX_VPC_SO_FLUSH_BASE__SHIFT) & A6XX_VPC_SO_FLUSH_BASE__MASK; 4437c28c82e9SRob Clark } 44382d756322SRob Clark 4439c28c82e9SRob Clark #define REG_A6XX_VPC_POINT_COORD_INVERT 0x00009236 4440c28c82e9SRob Clark #define A6XX_VPC_POINT_COORD_INVERT_INVERT 0x00000001 44412d756322SRob Clark 44422d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9300 0x00009300 44432d756322SRob Clark 4444c28c82e9SRob Clark #define REG_A6XX_VPC_VS_PACK 0x00009301 4445c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK 0x000000ff 4446c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT 0 4447c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_PACK_STRIDE_IN_VPC(uint32_t val) 44482d756322SRob Clark { 4449c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK; 44502d756322SRob Clark } 4451c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_POSITIONLOC__MASK 0x0000ff00 4452c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT 8 4453c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_PACK_POSITIONLOC(uint32_t val) 44542d756322SRob Clark { 4455c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_VS_PACK_POSITIONLOC__MASK; 44562d756322SRob Clark } 4457c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_PSIZELOC__MASK 0x00ff0000 4458c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_PSIZELOC__SHIFT 16 4459c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_PACK_PSIZELOC(uint32_t val) 44602d756322SRob Clark { 4461c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_VS_PACK_PSIZELOC__MASK; 4462c28c82e9SRob Clark } 4463cc4c26d4SRob Clark #define A6XX_VPC_VS_PACK_EXTRAPOS__MASK 0x0f000000 4464cc4c26d4SRob Clark #define A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT 24 4465cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_VS_PACK_EXTRAPOS(uint32_t val) 4466c28c82e9SRob Clark { 4467cc4c26d4SRob Clark return ((val) << A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_VS_PACK_EXTRAPOS__MASK; 4468c28c82e9SRob Clark } 4469c28c82e9SRob Clark 4470c28c82e9SRob Clark #define REG_A6XX_VPC_GS_PACK 0x00009302 4471c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK 0x000000ff 4472c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT 0 4473c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_PACK_STRIDE_IN_VPC(uint32_t val) 4474c28c82e9SRob Clark { 4475c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK; 4476c28c82e9SRob Clark } 4477c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_POSITIONLOC__MASK 0x0000ff00 4478c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT 8 4479c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_PACK_POSITIONLOC(uint32_t val) 4480c28c82e9SRob Clark { 4481c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_GS_PACK_POSITIONLOC__MASK; 4482c28c82e9SRob Clark } 4483c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_PSIZELOC__MASK 0x00ff0000 4484c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_PSIZELOC__SHIFT 16 4485c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_PACK_PSIZELOC(uint32_t val) 4486c28c82e9SRob Clark { 4487c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_GS_PACK_PSIZELOC__MASK; 4488c28c82e9SRob Clark } 4489cc4c26d4SRob Clark #define A6XX_VPC_GS_PACK_EXTRAPOS__MASK 0x0f000000 4490cc4c26d4SRob Clark #define A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT 24 4491cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_GS_PACK_EXTRAPOS(uint32_t val) 4492c28c82e9SRob Clark { 4493cc4c26d4SRob Clark return ((val) << A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_GS_PACK_EXTRAPOS__MASK; 4494c28c82e9SRob Clark } 4495c28c82e9SRob Clark 4496c28c82e9SRob Clark #define REG_A6XX_VPC_DS_PACK 0x00009303 4497c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK 0x000000ff 4498c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT 0 4499c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_PACK_STRIDE_IN_VPC(uint32_t val) 4500c28c82e9SRob Clark { 4501c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK; 4502c28c82e9SRob Clark } 4503c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_POSITIONLOC__MASK 0x0000ff00 4504c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT 8 4505c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_PACK_POSITIONLOC(uint32_t val) 4506c28c82e9SRob Clark { 4507c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_DS_PACK_POSITIONLOC__MASK; 4508c28c82e9SRob Clark } 4509c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_PSIZELOC__MASK 0x00ff0000 4510c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_PSIZELOC__SHIFT 16 4511c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_PACK_PSIZELOC(uint32_t val) 4512c28c82e9SRob Clark { 4513c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_DS_PACK_PSIZELOC__MASK; 4514c28c82e9SRob Clark } 4515cc4c26d4SRob Clark #define A6XX_VPC_DS_PACK_EXTRAPOS__MASK 0x0f000000 4516cc4c26d4SRob Clark #define A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT 24 4517cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_DS_PACK_EXTRAPOS(uint32_t val) 4518c28c82e9SRob Clark { 4519cc4c26d4SRob Clark return ((val) << A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_DS_PACK_EXTRAPOS__MASK; 45202d756322SRob Clark } 45212d756322SRob Clark 45222d756322SRob Clark #define REG_A6XX_VPC_CNTL_0 0x00009304 45232d756322SRob Clark #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK 0x000000ff 45242d756322SRob Clark #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT 0 45252d756322SRob Clark static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val) 45262d756322SRob Clark { 45272d756322SRob Clark return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK; 45282d756322SRob Clark } 4529c28c82e9SRob Clark #define A6XX_VPC_CNTL_0_PRIMIDLOC__MASK 0x0000ff00 4530c28c82e9SRob Clark #define A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT 8 4531c28c82e9SRob Clark static inline uint32_t A6XX_VPC_CNTL_0_PRIMIDLOC(uint32_t val) 4532c28c82e9SRob Clark { 4533c28c82e9SRob Clark return ((val) << A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT) & A6XX_VPC_CNTL_0_PRIMIDLOC__MASK; 4534c28c82e9SRob Clark } 45352d756322SRob Clark #define A6XX_VPC_CNTL_0_VARYING 0x00010000 4536cc4c26d4SRob Clark #define A6XX_VPC_CNTL_0_VIEWIDLOC__MASK 0xff000000 4537cc4c26d4SRob Clark #define A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT 24 4538cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_CNTL_0_VIEWIDLOC(uint32_t val) 4539c28c82e9SRob Clark { 4540cc4c26d4SRob Clark return ((val) << A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT) & A6XX_VPC_CNTL_0_VIEWIDLOC__MASK; 4541c28c82e9SRob Clark } 45422d756322SRob Clark 4543cc4c26d4SRob Clark #define REG_A6XX_VPC_SO_STREAM_CNTL 0x00009305 4544cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK 0x00000007 4545cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT 0 4546cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(uint32_t val) 4547c28c82e9SRob Clark { 4548cc4c26d4SRob Clark return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK; 4549cc4c26d4SRob Clark } 4550cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK 0x00000038 4551cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT 3 4552cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(uint32_t val) 4553cc4c26d4SRob Clark { 4554cc4c26d4SRob Clark return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK; 4555cc4c26d4SRob Clark } 4556cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK 0x000001c0 4557cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT 6 4558cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(uint32_t val) 4559cc4c26d4SRob Clark { 4560cc4c26d4SRob Clark return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK; 4561cc4c26d4SRob Clark } 4562cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK 0x00000e00 4563cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT 9 4564cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(uint32_t val) 4565cc4c26d4SRob Clark { 4566cc4c26d4SRob Clark return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK; 4567cc4c26d4SRob Clark } 4568cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK 0x00078000 4569cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT 15 4570cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val) 4571cc4c26d4SRob Clark { 4572cc4c26d4SRob Clark return ((val) << A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK; 4573c28c82e9SRob Clark } 45742d756322SRob Clark 4575c28c82e9SRob Clark #define REG_A6XX_VPC_SO_DISABLE 0x00009306 4576c28c82e9SRob Clark #define A6XX_VPC_SO_DISABLE_DISABLE 0x00000001 4577a69c5ed2SRob Clark 45782d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9600 0x00009600 45792d756322SRob Clark 4580c28c82e9SRob Clark #define REG_A6XX_VPC_ADDR_MODE_CNTL 0x00009601 4581c28c82e9SRob Clark 45822d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9602 0x00009602 45832d756322SRob Clark 4584c28c82e9SRob Clark #define REG_A6XX_VPC_UNKNOWN_9603 0x00009603 4585c28c82e9SRob Clark 4586cc4c26d4SRob Clark static inline uint32_t REG_A6XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) { return 0x00009604 + 0x1*i0; } 4587c28c82e9SRob Clark 4588c28c82e9SRob Clark #define REG_A6XX_PC_TESS_NUM_VERTEX 0x00009800 4589c28c82e9SRob Clark 4590cc4c26d4SRob Clark #define REG_A6XX_PC_HS_INPUT_SIZE 0x00009801 4591cc4c26d4SRob Clark #define A6XX_PC_HS_INPUT_SIZE_SIZE__MASK 0x000007ff 4592cc4c26d4SRob Clark #define A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT 0 4593cc4c26d4SRob Clark static inline uint32_t A6XX_PC_HS_INPUT_SIZE_SIZE(uint32_t val) 4594c28c82e9SRob Clark { 4595cc4c26d4SRob Clark return ((val) << A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT) & A6XX_PC_HS_INPUT_SIZE_SIZE__MASK; 4596c28c82e9SRob Clark } 4597cc4c26d4SRob Clark #define A6XX_PC_HS_INPUT_SIZE_UNK13__MASK 0x00002000 4598cc4c26d4SRob Clark #define A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT 13 4599cc4c26d4SRob Clark static inline uint32_t A6XX_PC_HS_INPUT_SIZE_UNK13(uint32_t val) 4600c28c82e9SRob Clark { 4601cc4c26d4SRob Clark return ((val) << A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT) & A6XX_PC_HS_INPUT_SIZE_UNK13__MASK; 4602c28c82e9SRob Clark } 4603c28c82e9SRob Clark 4604c28c82e9SRob Clark #define REG_A6XX_PC_TESS_CNTL 0x00009802 4605c28c82e9SRob Clark #define A6XX_PC_TESS_CNTL_SPACING__MASK 0x00000003 4606c28c82e9SRob Clark #define A6XX_PC_TESS_CNTL_SPACING__SHIFT 0 4607c28c82e9SRob Clark static inline uint32_t A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val) 4608c28c82e9SRob Clark { 4609c28c82e9SRob Clark return ((val) << A6XX_PC_TESS_CNTL_SPACING__SHIFT) & A6XX_PC_TESS_CNTL_SPACING__MASK; 4610c28c82e9SRob Clark } 4611c28c82e9SRob Clark #define A6XX_PC_TESS_CNTL_OUTPUT__MASK 0x0000000c 4612c28c82e9SRob Clark #define A6XX_PC_TESS_CNTL_OUTPUT__SHIFT 2 4613c28c82e9SRob Clark static inline uint32_t A6XX_PC_TESS_CNTL_OUTPUT(enum a6xx_tess_output val) 4614c28c82e9SRob Clark { 4615c28c82e9SRob Clark return ((val) << A6XX_PC_TESS_CNTL_OUTPUT__SHIFT) & A6XX_PC_TESS_CNTL_OUTPUT__MASK; 4616c28c82e9SRob Clark } 46172d756322SRob Clark 46182d756322SRob Clark #define REG_A6XX_PC_RESTART_INDEX 0x00009803 46192d756322SRob Clark 46202d756322SRob Clark #define REG_A6XX_PC_MODE_CNTL 0x00009804 46212d756322SRob Clark 4622*57cfe41cSRob Clark #define REG_A6XX_PC_POWER_CNTL 0x00009805 46232d756322SRob Clark 4624c28c82e9SRob Clark #define REG_A6XX_PC_PRIMID_PASSTHRU 0x00009806 4625c28c82e9SRob Clark 4626*57cfe41cSRob Clark #define REG_A6XX_PC_SO_STREAM_CNTL 0x00009808 4627*57cfe41cSRob Clark #define A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE 0x00008000 4628*57cfe41cSRob Clark 4629*57cfe41cSRob Clark #define REG_A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL 0x0000980a 4630*57cfe41cSRob Clark #define A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN 0x00000001 4631*57cfe41cSRob Clark 4632c28c82e9SRob Clark #define REG_A6XX_PC_DRAW_CMD 0x00009840 4633c28c82e9SRob Clark #define A6XX_PC_DRAW_CMD_STATE_ID__MASK 0x000000ff 4634c28c82e9SRob Clark #define A6XX_PC_DRAW_CMD_STATE_ID__SHIFT 0 4635c28c82e9SRob Clark static inline uint32_t A6XX_PC_DRAW_CMD_STATE_ID(uint32_t val) 4636c28c82e9SRob Clark { 4637c28c82e9SRob Clark return ((val) << A6XX_PC_DRAW_CMD_STATE_ID__SHIFT) & A6XX_PC_DRAW_CMD_STATE_ID__MASK; 4638c28c82e9SRob Clark } 4639c28c82e9SRob Clark 4640c28c82e9SRob Clark #define REG_A6XX_PC_DISPATCH_CMD 0x00009841 4641c28c82e9SRob Clark #define A6XX_PC_DISPATCH_CMD_STATE_ID__MASK 0x000000ff 4642c28c82e9SRob Clark #define A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT 0 4643c28c82e9SRob Clark static inline uint32_t A6XX_PC_DISPATCH_CMD_STATE_ID(uint32_t val) 4644c28c82e9SRob Clark { 4645c28c82e9SRob Clark return ((val) << A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_PC_DISPATCH_CMD_STATE_ID__MASK; 4646c28c82e9SRob Clark } 4647c28c82e9SRob Clark 4648c28c82e9SRob Clark #define REG_A6XX_PC_EVENT_CMD 0x00009842 4649c28c82e9SRob Clark #define A6XX_PC_EVENT_CMD_STATE_ID__MASK 0x00ff0000 4650c28c82e9SRob Clark #define A6XX_PC_EVENT_CMD_STATE_ID__SHIFT 16 4651c28c82e9SRob Clark static inline uint32_t A6XX_PC_EVENT_CMD_STATE_ID(uint32_t val) 4652c28c82e9SRob Clark { 4653c28c82e9SRob Clark return ((val) << A6XX_PC_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_EVENT_CMD_STATE_ID__MASK; 4654c28c82e9SRob Clark } 4655c28c82e9SRob Clark #define A6XX_PC_EVENT_CMD_EVENT__MASK 0x0000007f 4656c28c82e9SRob Clark #define A6XX_PC_EVENT_CMD_EVENT__SHIFT 0 4657c28c82e9SRob Clark static inline uint32_t A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val) 4658c28c82e9SRob Clark { 4659c28c82e9SRob Clark return ((val) << A6XX_PC_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_EVENT_CMD_EVENT__MASK; 4660c28c82e9SRob Clark } 4661c28c82e9SRob Clark 4662cc4c26d4SRob Clark #define REG_A6XX_PC_MARKER 0x00009880 4663cc4c26d4SRob Clark 4664c28c82e9SRob Clark #define REG_A6XX_PC_POLYGON_MODE 0x00009981 4665c28c82e9SRob Clark #define A6XX_PC_POLYGON_MODE_MODE__MASK 0x00000003 4666c28c82e9SRob Clark #define A6XX_PC_POLYGON_MODE_MODE__SHIFT 0 4667c28c82e9SRob Clark static inline uint32_t A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) 4668c28c82e9SRob Clark { 4669c28c82e9SRob Clark return ((val) << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK; 4670c28c82e9SRob Clark } 4671a69c5ed2SRob Clark 4672cc4c26d4SRob Clark #define REG_A6XX_PC_RASTER_CNTL 0x00009980 4673cc4c26d4SRob Clark #define A6XX_PC_RASTER_CNTL_STREAM__MASK 0x00000003 4674cc4c26d4SRob Clark #define A6XX_PC_RASTER_CNTL_STREAM__SHIFT 0 4675cc4c26d4SRob Clark static inline uint32_t A6XX_PC_RASTER_CNTL_STREAM(uint32_t val) 4676cc4c26d4SRob Clark { 4677cc4c26d4SRob Clark return ((val) << A6XX_PC_RASTER_CNTL_STREAM__SHIFT) & A6XX_PC_RASTER_CNTL_STREAM__MASK; 4678cc4c26d4SRob Clark } 4679cc4c26d4SRob Clark #define A6XX_PC_RASTER_CNTL_DISCARD 0x00000004 4680a69c5ed2SRob Clark 46812d756322SRob Clark #define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00 46822d756322SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001 46832d756322SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002 4684c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_0_TESS_UPPER_LEFT_DOMAIN_ORIGIN 0x00000004 4685c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_0_UNK3 0x00000008 46862d756322SRob Clark 4687c28c82e9SRob Clark #define REG_A6XX_PC_VS_OUT_CNTL 0x00009b01 4688c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff 4689c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 4690c28c82e9SRob Clark static inline uint32_t A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) 46912d756322SRob Clark { 4692c28c82e9SRob Clark return ((val) << A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK; 46932d756322SRob Clark } 4694c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_PSIZE 0x00000100 4695c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_LAYER 0x00000200 4696c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_VIEW 0x00000400 4697c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID 0x00000800 4698c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 4699c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT 16 4700c28c82e9SRob Clark static inline uint32_t A6XX_PC_VS_OUT_CNTL_CLIP_MASK(uint32_t val) 4701c28c82e9SRob Clark { 4702c28c82e9SRob Clark return ((val) << A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK; 4703c28c82e9SRob Clark } 47042d756322SRob Clark 4705c28c82e9SRob Clark #define REG_A6XX_PC_GS_OUT_CNTL 0x00009b02 4706c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff 4707c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 4708c28c82e9SRob Clark static inline uint32_t A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) 4709c28c82e9SRob Clark { 4710c28c82e9SRob Clark return ((val) << A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK; 4711c28c82e9SRob Clark } 4712c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_PSIZE 0x00000100 4713c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_LAYER 0x00000200 4714c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_VIEW 0x00000400 4715c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID 0x00000800 4716c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 4717c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT 16 4718c28c82e9SRob Clark static inline uint32_t A6XX_PC_GS_OUT_CNTL_CLIP_MASK(uint32_t val) 4719c28c82e9SRob Clark { 4720c28c82e9SRob Clark return ((val) << A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK; 4721c28c82e9SRob Clark } 4722c28c82e9SRob Clark 4723*57cfe41cSRob Clark #define REG_A6XX_PC_HS_OUT_CNTL 0x00009b03 4724*57cfe41cSRob Clark #define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff 4725*57cfe41cSRob Clark #define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 4726*57cfe41cSRob Clark static inline uint32_t A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) 4727*57cfe41cSRob Clark { 4728*57cfe41cSRob Clark return ((val) << A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK; 4729*57cfe41cSRob Clark } 4730*57cfe41cSRob Clark #define A6XX_PC_HS_OUT_CNTL_PSIZE 0x00000100 4731*57cfe41cSRob Clark #define A6XX_PC_HS_OUT_CNTL_LAYER 0x00000200 4732*57cfe41cSRob Clark #define A6XX_PC_HS_OUT_CNTL_VIEW 0x00000400 4733*57cfe41cSRob Clark #define A6XX_PC_HS_OUT_CNTL_PRIMITIVE_ID 0x00000800 4734*57cfe41cSRob Clark #define A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 4735*57cfe41cSRob Clark #define A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT 16 4736*57cfe41cSRob Clark static inline uint32_t A6XX_PC_HS_OUT_CNTL_CLIP_MASK(uint32_t val) 4737*57cfe41cSRob Clark { 4738*57cfe41cSRob Clark return ((val) << A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK; 4739*57cfe41cSRob Clark } 4740c28c82e9SRob Clark 4741c28c82e9SRob Clark #define REG_A6XX_PC_DS_OUT_CNTL 0x00009b04 4742c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff 4743c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 4744c28c82e9SRob Clark static inline uint32_t A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) 4745c28c82e9SRob Clark { 4746c28c82e9SRob Clark return ((val) << A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK; 4747c28c82e9SRob Clark } 4748c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_PSIZE 0x00000100 4749c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_LAYER 0x00000200 4750c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_VIEW 0x00000400 4751c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID 0x00000800 4752c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 4753c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT 16 4754c28c82e9SRob Clark static inline uint32_t A6XX_PC_DS_OUT_CNTL_CLIP_MASK(uint32_t val) 4755c28c82e9SRob Clark { 4756c28c82e9SRob Clark return ((val) << A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK; 4757c28c82e9SRob Clark } 4758c28c82e9SRob Clark 4759c28c82e9SRob Clark #define REG_A6XX_PC_PRIMITIVE_CNTL_5 0x00009b05 4760c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK 0x000000ff 4761c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT 0 4762c28c82e9SRob Clark static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val) 4763c28c82e9SRob Clark { 4764c28c82e9SRob Clark return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK; 4765c28c82e9SRob Clark } 4766c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK 0x00007c00 4767c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT 10 4768c28c82e9SRob Clark static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val) 4769c28c82e9SRob Clark { 4770c28c82e9SRob Clark return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK; 4771c28c82e9SRob Clark } 4772*57cfe41cSRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_LINELENGTHEN 0x00008000 4773c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK 0x00030000 4774c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT 16 4775c28c82e9SRob Clark static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val) 4776c28c82e9SRob Clark { 4777c28c82e9SRob Clark return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK; 4778c28c82e9SRob Clark } 4779c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK 0x00040000 4780c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT 18 4781c28c82e9SRob Clark static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_UNK18(uint32_t val) 4782c28c82e9SRob Clark { 4783c28c82e9SRob Clark return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK; 4784c28c82e9SRob Clark } 4785c28c82e9SRob Clark 4786c28c82e9SRob Clark #define REG_A6XX_PC_PRIMITIVE_CNTL_6 0x00009b06 4787c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK 0x000007ff 4788c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT 0 4789c28c82e9SRob Clark static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(uint32_t val) 4790c28c82e9SRob Clark { 4791c28c82e9SRob Clark return ((val) << A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK; 4792c28c82e9SRob Clark } 47932d756322SRob Clark 4794cc4c26d4SRob Clark #define REG_A6XX_PC_MULTIVIEW_CNTL 0x00009b07 4795cc4c26d4SRob Clark #define A6XX_PC_MULTIVIEW_CNTL_ENABLE 0x00000001 4796cc4c26d4SRob Clark #define A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002 4797cc4c26d4SRob Clark #define A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c 4798cc4c26d4SRob Clark #define A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT 2 4799cc4c26d4SRob Clark static inline uint32_t A6XX_PC_MULTIVIEW_CNTL_VIEWS(uint32_t val) 4800cc4c26d4SRob Clark { 4801cc4c26d4SRob Clark return ((val) << A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK; 4802cc4c26d4SRob Clark } 48032d756322SRob Clark 4804cc4c26d4SRob Clark #define REG_A6XX_PC_MULTIVIEW_MASK 0x00009b08 4805c28c82e9SRob Clark 4806c28c82e9SRob Clark #define REG_A6XX_PC_2D_EVENT_CMD 0x00009c00 4807c28c82e9SRob Clark #define A6XX_PC_2D_EVENT_CMD_EVENT__MASK 0x0000007f 4808c28c82e9SRob Clark #define A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT 0 4809c28c82e9SRob Clark static inline uint32_t A6XX_PC_2D_EVENT_CMD_EVENT(enum vgt_event_type val) 4810c28c82e9SRob Clark { 4811c28c82e9SRob Clark return ((val) << A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_2D_EVENT_CMD_EVENT__MASK; 4812c28c82e9SRob Clark } 4813c28c82e9SRob Clark #define A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00 4814c28c82e9SRob Clark #define A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT 8 4815c28c82e9SRob Clark static inline uint32_t A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val) 4816c28c82e9SRob Clark { 4817c28c82e9SRob Clark return ((val) << A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK; 4818c28c82e9SRob Clark } 4819c28c82e9SRob Clark 4820c28c82e9SRob Clark #define REG_A6XX_PC_DBG_ECO_CNTL 0x00009e00 4821c28c82e9SRob Clark 4822c28c82e9SRob Clark #define REG_A6XX_PC_ADDR_MODE_CNTL 0x00009e01 4823c28c82e9SRob Clark 4824cc4c26d4SRob Clark #define REG_A6XX_PC_DRAW_INDX_BASE 0x00009e04 48252d756322SRob Clark 4826cc4c26d4SRob Clark #define REG_A6XX_PC_DRAW_FIRST_INDX 0x00009e06 4827cc4c26d4SRob Clark 4828cc4c26d4SRob Clark #define REG_A6XX_PC_DRAW_MAX_INDICES 0x00009e07 48292d756322SRob Clark 4830c28c82e9SRob Clark #define REG_A6XX_PC_TESSFACTOR_ADDR 0x00009e08 4831c28c82e9SRob Clark #define A6XX_PC_TESSFACTOR_ADDR__MASK 0xffffffff 4832c28c82e9SRob Clark #define A6XX_PC_TESSFACTOR_ADDR__SHIFT 0 4833c28c82e9SRob Clark static inline uint32_t A6XX_PC_TESSFACTOR_ADDR(uint32_t val) 4834c28c82e9SRob Clark { 4835c28c82e9SRob Clark return ((val) << A6XX_PC_TESSFACTOR_ADDR__SHIFT) & A6XX_PC_TESSFACTOR_ADDR__MASK; 4836c28c82e9SRob Clark } 4837c28c82e9SRob Clark 4838cc4c26d4SRob Clark #define REG_A6XX_PC_DRAW_INITIATOR 0x00009e0b 4839cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f 4840cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 4841cc4c26d4SRob Clark static inline uint32_t A6XX_PC_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) 4842cc4c26d4SRob Clark { 4843cc4c26d4SRob Clark return ((val) << A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK; 4844cc4c26d4SRob Clark } 4845cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 4846cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 4847cc4c26d4SRob Clark static inline uint32_t A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) 4848cc4c26d4SRob Clark { 4849cc4c26d4SRob Clark return ((val) << A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK; 4850cc4c26d4SRob Clark } 4851cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK 0x00000300 4852cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT 8 4853cc4c26d4SRob Clark static inline uint32_t A6XX_PC_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) 4854cc4c26d4SRob Clark { 4855cc4c26d4SRob Clark return ((val) << A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT) & A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK; 4856cc4c26d4SRob Clark } 4857cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000c00 4858cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT 10 4859cc4c26d4SRob Clark static inline uint32_t A6XX_PC_DRAW_INITIATOR_INDEX_SIZE(enum a4xx_index_size val) 4860cc4c26d4SRob Clark { 4861cc4c26d4SRob Clark return ((val) << A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK; 4862cc4c26d4SRob Clark } 4863cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK 0x00003000 4864cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT 12 4865cc4c26d4SRob Clark static inline uint32_t A6XX_PC_DRAW_INITIATOR_PATCH_TYPE(enum a6xx_patch_type val) 4866cc4c26d4SRob Clark { 4867cc4c26d4SRob Clark return ((val) << A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK; 4868cc4c26d4SRob Clark } 4869cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_GS_ENABLE 0x00010000 4870cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_TESS_ENABLE 0x00020000 4871cc4c26d4SRob Clark 4872cc4c26d4SRob Clark #define REG_A6XX_PC_DRAW_NUM_INSTANCES 0x00009e0c 4873cc4c26d4SRob Clark 4874cc4c26d4SRob Clark #define REG_A6XX_PC_DRAW_NUM_INDICES 0x00009e0d 4875cc4c26d4SRob Clark 4876c28c82e9SRob Clark #define REG_A6XX_PC_VSTREAM_CONTROL 0x00009e11 4877c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_UNK0__MASK 0x0000ffff 4878c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT 0 4879c28c82e9SRob Clark static inline uint32_t A6XX_PC_VSTREAM_CONTROL_UNK0(uint32_t val) 4880c28c82e9SRob Clark { 4881c28c82e9SRob Clark return ((val) << A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT) & A6XX_PC_VSTREAM_CONTROL_UNK0__MASK; 4882c28c82e9SRob Clark } 4883c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK 0x003f0000 4884c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT 16 4885c28c82e9SRob Clark static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_SIZE(uint32_t val) 4886c28c82e9SRob Clark { 4887c28c82e9SRob Clark return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK; 4888c28c82e9SRob Clark } 4889c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK 0x07c00000 4890c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT 22 4891c28c82e9SRob Clark static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_N(uint32_t val) 4892c28c82e9SRob Clark { 4893c28c82e9SRob Clark return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK; 4894c28c82e9SRob Clark } 4895c28c82e9SRob Clark 4896c28c82e9SRob Clark #define REG_A6XX_PC_BIN_PRIM_STRM 0x00009e12 4897c28c82e9SRob Clark #define A6XX_PC_BIN_PRIM_STRM__MASK 0xffffffff 4898c28c82e9SRob Clark #define A6XX_PC_BIN_PRIM_STRM__SHIFT 0 4899c28c82e9SRob Clark static inline uint32_t A6XX_PC_BIN_PRIM_STRM(uint32_t val) 4900c28c82e9SRob Clark { 4901c28c82e9SRob Clark return ((val) << A6XX_PC_BIN_PRIM_STRM__SHIFT) & A6XX_PC_BIN_PRIM_STRM__MASK; 4902c28c82e9SRob Clark } 4903c28c82e9SRob Clark 4904c28c82e9SRob Clark #define REG_A6XX_PC_BIN_DRAW_STRM 0x00009e14 4905c28c82e9SRob Clark #define A6XX_PC_BIN_DRAW_STRM__MASK 0xffffffff 4906c28c82e9SRob Clark #define A6XX_PC_BIN_DRAW_STRM__SHIFT 0 4907c28c82e9SRob Clark static inline uint32_t A6XX_PC_BIN_DRAW_STRM(uint32_t val) 4908c28c82e9SRob Clark { 4909c28c82e9SRob Clark return ((val) << A6XX_PC_BIN_DRAW_STRM__SHIFT) & A6XX_PC_BIN_DRAW_STRM__MASK; 4910c28c82e9SRob Clark } 4911c28c82e9SRob Clark 4912cc4c26d4SRob Clark #define REG_A6XX_PC_VISIBILITY_OVERRIDE 0x00009e1c 4913cc4c26d4SRob Clark #define A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE 0x00000001 4914c28c82e9SRob Clark 4915cc4c26d4SRob Clark static inline uint32_t REG_A6XX_PC_PERFCTR_PC_SEL(uint32_t i0) { return 0x00009e34 + 0x1*i0; } 4916c28c82e9SRob Clark 49172d756322SRob Clark #define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72 49182d756322SRob Clark 49192d756322SRob Clark #define REG_A6XX_VFD_CONTROL_0 0x0000a000 4920c28c82e9SRob Clark #define A6XX_VFD_CONTROL_0_FETCH_CNT__MASK 0x0000003f 4921c28c82e9SRob Clark #define A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT 0 4922c28c82e9SRob Clark static inline uint32_t A6XX_VFD_CONTROL_0_FETCH_CNT(uint32_t val) 49232d756322SRob Clark { 4924c28c82e9SRob Clark return ((val) << A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT) & A6XX_VFD_CONTROL_0_FETCH_CNT__MASK; 4925c28c82e9SRob Clark } 4926c28c82e9SRob Clark #define A6XX_VFD_CONTROL_0_DECODE_CNT__MASK 0x00003f00 4927c28c82e9SRob Clark #define A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT 8 4928c28c82e9SRob Clark static inline uint32_t A6XX_VFD_CONTROL_0_DECODE_CNT(uint32_t val) 4929c28c82e9SRob Clark { 4930c28c82e9SRob Clark return ((val) << A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT) & A6XX_VFD_CONTROL_0_DECODE_CNT__MASK; 49312d756322SRob Clark } 49322d756322SRob Clark 49332d756322SRob Clark #define REG_A6XX_VFD_CONTROL_1 0x0000a001 49342d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff 49352d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0 49362d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 49372d756322SRob Clark { 49382d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VTX__MASK; 49392d756322SRob Clark } 49402d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00 49412d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4INST__SHIFT 8 49422d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 49432d756322SRob Clark { 49442d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK; 49452d756322SRob Clark } 49462d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000 49472d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16 49482d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val) 49492d756322SRob Clark { 49502d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK; 49512d756322SRob Clark } 4952cc4c26d4SRob Clark #define A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK 0xff000000 4953cc4c26d4SRob Clark #define A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT 24 4954cc4c26d4SRob Clark static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VIEWID(uint32_t val) 4955cc4c26d4SRob Clark { 4956cc4c26d4SRob Clark return ((val) << A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK; 4957cc4c26d4SRob Clark } 49582d756322SRob Clark 49592d756322SRob Clark #define REG_A6XX_VFD_CONTROL_2 0x0000a002 4960*57cfe41cSRob Clark #define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK 0x000000ff 4961*57cfe41cSRob Clark #define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT 0 4962*57cfe41cSRob Clark static inline uint32_t A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID(uint32_t val) 49632d756322SRob Clark { 4964*57cfe41cSRob Clark return ((val) << A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK; 4965c28c82e9SRob Clark } 4966c28c82e9SRob Clark #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK 0x0000ff00 4967c28c82e9SRob Clark #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT 8 4968c28c82e9SRob Clark static inline uint32_t A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val) 4969c28c82e9SRob Clark { 4970c28c82e9SRob Clark return ((val) << A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK; 49712d756322SRob Clark } 49722d756322SRob Clark 49732d756322SRob Clark #define REG_A6XX_VFD_CONTROL_3 0x0000a003 4974*57cfe41cSRob Clark #define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK 0x000000ff 4975*57cfe41cSRob Clark #define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT 0 4976*57cfe41cSRob Clark static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPRIMID(uint32_t val) 4977cc4c26d4SRob Clark { 4978*57cfe41cSRob Clark return ((val) << A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK; 4979cc4c26d4SRob Clark } 4980*57cfe41cSRob Clark #define A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK 0x0000ff00 4981*57cfe41cSRob Clark #define A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT 8 4982*57cfe41cSRob Clark static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID(uint32_t val) 49832d756322SRob Clark { 4984*57cfe41cSRob Clark return ((val) << A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK; 49852d756322SRob Clark } 49862d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000 49872d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16 49882d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) 49892d756322SRob Clark { 49902d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSX__MASK; 49912d756322SRob Clark } 49922d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000 49932d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24 49942d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) 49952d756322SRob Clark { 49962d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK; 49972d756322SRob Clark } 49982d756322SRob Clark 49992d756322SRob Clark #define REG_A6XX_VFD_CONTROL_4 0x0000a004 5000cc4c26d4SRob Clark #define A6XX_VFD_CONTROL_4_UNK0__MASK 0x000000ff 5001cc4c26d4SRob Clark #define A6XX_VFD_CONTROL_4_UNK0__SHIFT 0 5002cc4c26d4SRob Clark static inline uint32_t A6XX_VFD_CONTROL_4_UNK0(uint32_t val) 5003cc4c26d4SRob Clark { 5004cc4c26d4SRob Clark return ((val) << A6XX_VFD_CONTROL_4_UNK0__SHIFT) & A6XX_VFD_CONTROL_4_UNK0__MASK; 5005cc4c26d4SRob Clark } 50062d756322SRob Clark 50072d756322SRob Clark #define REG_A6XX_VFD_CONTROL_5 0x0000a005 5008c28c82e9SRob Clark #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK 0x000000ff 5009c28c82e9SRob Clark #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT 0 5010c28c82e9SRob Clark static inline uint32_t A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val) 5011c28c82e9SRob Clark { 5012c28c82e9SRob Clark return ((val) << A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT) & A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK; 5013c28c82e9SRob Clark } 5014cc4c26d4SRob Clark #define A6XX_VFD_CONTROL_5_UNK8__MASK 0x0000ff00 5015cc4c26d4SRob Clark #define A6XX_VFD_CONTROL_5_UNK8__SHIFT 8 5016cc4c26d4SRob Clark static inline uint32_t A6XX_VFD_CONTROL_5_UNK8(uint32_t val) 5017cc4c26d4SRob Clark { 5018cc4c26d4SRob Clark return ((val) << A6XX_VFD_CONTROL_5_UNK8__SHIFT) & A6XX_VFD_CONTROL_5_UNK8__MASK; 5019cc4c26d4SRob Clark } 50202d756322SRob Clark 50212d756322SRob Clark #define REG_A6XX_VFD_CONTROL_6 0x0000a006 5022c28c82e9SRob Clark #define A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU 0x00000001 50232d756322SRob Clark 50242d756322SRob Clark #define REG_A6XX_VFD_MODE_CNTL 0x0000a007 5025*57cfe41cSRob Clark #define A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK 0x00000007 5026*57cfe41cSRob Clark #define A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT 0 5027*57cfe41cSRob Clark static inline uint32_t A6XX_VFD_MODE_CNTL_RENDER_MODE(enum a6xx_render_mode val) 5028*57cfe41cSRob Clark { 5029*57cfe41cSRob Clark return ((val) << A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT) & A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK; 5030*57cfe41cSRob Clark } 50312d756322SRob Clark 5032cc4c26d4SRob Clark #define REG_A6XX_VFD_MULTIVIEW_CNTL 0x0000a008 5033cc4c26d4SRob Clark #define A6XX_VFD_MULTIVIEW_CNTL_ENABLE 0x00000001 5034cc4c26d4SRob Clark #define A6XX_VFD_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002 5035cc4c26d4SRob Clark #define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c 5036cc4c26d4SRob Clark #define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT 2 5037cc4c26d4SRob Clark static inline uint32_t A6XX_VFD_MULTIVIEW_CNTL_VIEWS(uint32_t val) 5038cc4c26d4SRob Clark { 5039cc4c26d4SRob Clark return ((val) << A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK; 5040cc4c26d4SRob Clark } 50412d756322SRob Clark 5042c28c82e9SRob Clark #define REG_A6XX_VFD_ADD_OFFSET 0x0000a009 5043c28c82e9SRob Clark #define A6XX_VFD_ADD_OFFSET_VERTEX 0x00000001 5044c28c82e9SRob Clark #define A6XX_VFD_ADD_OFFSET_INSTANCE 0x00000002 5045a69c5ed2SRob Clark 50462d756322SRob Clark #define REG_A6XX_VFD_INDEX_OFFSET 0x0000a00e 50472d756322SRob Clark 50482d756322SRob Clark #define REG_A6XX_VFD_INSTANCE_START_OFFSET 0x0000a00f 50492d756322SRob Clark 50502d756322SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; } 50512d756322SRob Clark 5052c28c82e9SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; } 5053cc4c26d4SRob Clark #define A6XX_VFD_FETCH_BASE__MASK 0xffffffff 5054cc4c26d4SRob Clark #define A6XX_VFD_FETCH_BASE__SHIFT 0 5055cc4c26d4SRob Clark static inline uint32_t A6XX_VFD_FETCH_BASE(uint32_t val) 5056cc4c26d4SRob Clark { 5057cc4c26d4SRob Clark return ((val) << A6XX_VFD_FETCH_BASE__SHIFT) & A6XX_VFD_FETCH_BASE__MASK; 5058cc4c26d4SRob Clark } 50592d756322SRob Clark 50602d756322SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; } 50612d756322SRob Clark 50622d756322SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; } 50632d756322SRob Clark 50642d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; } 50652d756322SRob Clark 50662d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; } 50672d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f 50682d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_IDX__SHIFT 0 50692d756322SRob Clark static inline uint32_t A6XX_VFD_DECODE_INSTR_IDX(uint32_t val) 50702d756322SRob Clark { 50712d756322SRob Clark return ((val) << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK; 50722d756322SRob Clark } 5073c28c82e9SRob Clark #define A6XX_VFD_DECODE_INSTR_OFFSET__MASK 0x0001ffe0 5074c28c82e9SRob Clark #define A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT 5 5075c28c82e9SRob Clark static inline uint32_t A6XX_VFD_DECODE_INSTR_OFFSET(uint32_t val) 5076c28c82e9SRob Clark { 5077c28c82e9SRob Clark return ((val) << A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT) & A6XX_VFD_DECODE_INSTR_OFFSET__MASK; 5078c28c82e9SRob Clark } 50792d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_INSTANCED 0x00020000 50802d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000 50812d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20 5082c28c82e9SRob Clark static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_format val) 50832d756322SRob Clark { 50842d756322SRob Clark return ((val) << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK; 50852d756322SRob Clark } 50862d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000 50872d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_SWAP__SHIFT 28 50882d756322SRob Clark static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 50892d756322SRob Clark { 50902d756322SRob Clark return ((val) << A6XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A6XX_VFD_DECODE_INSTR_SWAP__MASK; 50912d756322SRob Clark } 50922d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_UNK30 0x40000000 50932d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_FLOAT 0x80000000 50942d756322SRob Clark 50952d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; } 50962d756322SRob Clark 50972d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } 50982d756322SRob Clark 50992d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } 51002d756322SRob Clark #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f 51012d756322SRob Clark #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0 51022d756322SRob Clark static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val) 51032d756322SRob Clark { 51042d756322SRob Clark return ((val) << A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK; 51052d756322SRob Clark } 51062d756322SRob Clark #define A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0 51072d756322SRob Clark #define A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4 51082d756322SRob Clark static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) 51092d756322SRob Clark { 51102d756322SRob Clark return ((val) << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK; 51112d756322SRob Clark } 51122d756322SRob Clark 5113*57cfe41cSRob Clark #define REG_A6XX_VFD_POWER_CNTL 0x0000a0f8 51142d756322SRob Clark 5115cc4c26d4SRob Clark #define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601 5116cc4c26d4SRob Clark 5117cc4c26d4SRob Clark static inline uint32_t REG_A6XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) { return 0x0000a610 + 0x1*i0; } 5118cc4c26d4SRob Clark 5119c28c82e9SRob Clark #define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800 5120cc4c26d4SRob Clark #define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x00100000 5121cc4c26d4SRob Clark #define A6XX_SP_VS_CTRL_REG0_UNK21 0x00200000 5122cc4c26d4SRob Clark #define A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 5123cc4c26d4SRob Clark #define A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 5124cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 5125cc4c26d4SRob Clark { 5126cc4c26d4SRob Clark return ((val) << A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK; 5127cc4c26d4SRob Clark } 5128c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 5129c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 5130c28c82e9SRob Clark static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 51312d756322SRob Clark { 5132c28c82e9SRob Clark return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 5133c28c82e9SRob Clark } 5134c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 5135c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 5136c28c82e9SRob Clark static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 5137c28c82e9SRob Clark { 5138c28c82e9SRob Clark return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 5139c28c82e9SRob Clark } 5140cc4c26d4SRob Clark #define A6XX_SP_VS_CTRL_REG0_UNK13 0x00002000 5141c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 5142c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14 5143c28c82e9SRob Clark static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val) 5144c28c82e9SRob Clark { 5145c28c82e9SRob Clark return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK; 5146c28c82e9SRob Clark } 5147c28c82e9SRob Clark 5148c28c82e9SRob Clark #define REG_A6XX_SP_VS_BRANCH_COND 0x0000a801 5149c28c82e9SRob Clark 5150c28c82e9SRob Clark #define REG_A6XX_SP_VS_PRIMITIVE_CNTL 0x0000a802 5151c28c82e9SRob Clark #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f 5152c28c82e9SRob Clark #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT 0 5153c28c82e9SRob Clark static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_OUT(uint32_t val) 5154c28c82e9SRob Clark { 5155c28c82e9SRob Clark return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK; 51562d756322SRob Clark } 5157cc4c26d4SRob Clark #define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0 5158cc4c26d4SRob Clark #define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6 5159cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) 5160cc4c26d4SRob Clark { 5161cc4c26d4SRob Clark return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; 5162cc4c26d4SRob Clark } 51632d756322SRob Clark 51642d756322SRob Clark static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; } 51652d756322SRob Clark 51662d756322SRob Clark static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; } 51672d756322SRob Clark #define A6XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff 51682d756322SRob Clark #define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 51692d756322SRob Clark static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 51702d756322SRob Clark { 51712d756322SRob Clark return ((val) << A6XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_A_REGID__MASK; 51722d756322SRob Clark } 51732d756322SRob Clark #define A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00 51742d756322SRob Clark #define A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8 51752d756322SRob Clark static inline uint32_t A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 51762d756322SRob Clark { 51772d756322SRob Clark return ((val) << A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 51782d756322SRob Clark } 51792d756322SRob Clark #define A6XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000 51802d756322SRob Clark #define A6XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 51812d756322SRob Clark static inline uint32_t A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 51822d756322SRob Clark { 51832d756322SRob Clark return ((val) << A6XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_B_REGID__MASK; 51842d756322SRob Clark } 51852d756322SRob Clark #define A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000 51862d756322SRob Clark #define A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24 51872d756322SRob Clark static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 51882d756322SRob Clark { 51892d756322SRob Clark return ((val) << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 51902d756322SRob Clark } 51912d756322SRob Clark 51922d756322SRob Clark static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; } 51932d756322SRob Clark 51942d756322SRob Clark static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; } 51952d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 51962d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 51972d756322SRob Clark static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 51982d756322SRob Clark { 51992d756322SRob Clark return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 52002d756322SRob Clark } 52012d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 52022d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 52032d756322SRob Clark static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 52042d756322SRob Clark { 52052d756322SRob Clark return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 52062d756322SRob Clark } 52072d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 52082d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 52092d756322SRob Clark static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 52102d756322SRob Clark { 52112d756322SRob Clark return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 52122d756322SRob Clark } 52132d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 52142d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 52152d756322SRob Clark static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 52162d756322SRob Clark { 52172d756322SRob Clark return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 52182d756322SRob Clark } 52192d756322SRob Clark 5220cc4c26d4SRob Clark #define REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET 0x0000a81b 5221a69c5ed2SRob Clark 5222cc4c26d4SRob Clark #define REG_A6XX_SP_VS_OBJ_START 0x0000a81c 5223cc4c26d4SRob Clark #define A6XX_SP_VS_OBJ_START__MASK 0xffffffff 5224cc4c26d4SRob Clark #define A6XX_SP_VS_OBJ_START__SHIFT 0 5225cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_OBJ_START(uint32_t val) 5226cc4c26d4SRob Clark { 5227cc4c26d4SRob Clark return ((val) << A6XX_SP_VS_OBJ_START__SHIFT) & A6XX_SP_VS_OBJ_START__MASK; 5228cc4c26d4SRob Clark } 52292d756322SRob Clark 5230cc4c26d4SRob Clark #define REG_A6XX_SP_VS_PVT_MEM_PARAM 0x0000a81e 5231cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 5232cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 5233cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 5234cc4c26d4SRob Clark { 5235cc4c26d4SRob Clark return ((val >> 9) << A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 5236cc4c26d4SRob Clark } 5237cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 5238cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 5239cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 5240cc4c26d4SRob Clark { 5241cc4c26d4SRob Clark return ((val) << A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 5242cc4c26d4SRob Clark } 5243cc4c26d4SRob Clark 5244cc4c26d4SRob Clark #define REG_A6XX_SP_VS_PVT_MEM_ADDR 0x0000a81f 5245cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_ADDR__MASK 0xffffffff 5246cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_ADDR__SHIFT 0 5247cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_PVT_MEM_ADDR(uint32_t val) 5248cc4c26d4SRob Clark { 5249cc4c26d4SRob Clark return ((val) << A6XX_SP_VS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_VS_PVT_MEM_ADDR__MASK; 5250cc4c26d4SRob Clark } 5251cc4c26d4SRob Clark 5252cc4c26d4SRob Clark #define REG_A6XX_SP_VS_PVT_MEM_SIZE 0x0000a821 5253cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 5254cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 5255cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 5256cc4c26d4SRob Clark { 5257cc4c26d4SRob Clark return ((val >> 12) << A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 5258cc4c26d4SRob Clark } 5259cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 52602d756322SRob Clark 52612d756322SRob Clark #define REG_A6XX_SP_VS_TEX_COUNT 0x0000a822 52622d756322SRob Clark 52632d756322SRob Clark #define REG_A6XX_SP_VS_CONFIG 0x0000a823 5264c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_BINDLESS_TEX 0x00000001 5265c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_BINDLESS_SAMP 0x00000002 5266c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_BINDLESS_IBO 0x00000004 5267c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_BINDLESS_UBO 0x00000008 52682d756322SRob Clark #define A6XX_SP_VS_CONFIG_ENABLED 0x00000100 52692d756322SRob Clark #define A6XX_SP_VS_CONFIG_NTEX__MASK 0x0001fe00 52702d756322SRob Clark #define A6XX_SP_VS_CONFIG_NTEX__SHIFT 9 52712d756322SRob Clark static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val) 52722d756322SRob Clark { 52732d756322SRob Clark return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK; 52742d756322SRob Clark } 5275c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_NSAMP__MASK 0x003e0000 52762d756322SRob Clark #define A6XX_SP_VS_CONFIG_NSAMP__SHIFT 17 52772d756322SRob Clark static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val) 52782d756322SRob Clark { 52792d756322SRob Clark return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK; 52802d756322SRob Clark } 5281cc4c26d4SRob Clark #define A6XX_SP_VS_CONFIG_NIBO__MASK 0x1fc00000 5282c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_NIBO__SHIFT 22 5283c28c82e9SRob Clark static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val) 5284c28c82e9SRob Clark { 5285c28c82e9SRob Clark return ((val) << A6XX_SP_VS_CONFIG_NIBO__SHIFT) & A6XX_SP_VS_CONFIG_NIBO__MASK; 5286c28c82e9SRob Clark } 52872d756322SRob Clark 52882d756322SRob Clark #define REG_A6XX_SP_VS_INSTRLEN 0x0000a824 52892d756322SRob Clark 5290cc4c26d4SRob Clark #define REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET 0x0000a825 5291*57cfe41cSRob Clark #define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 5292*57cfe41cSRob Clark #define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 5293*57cfe41cSRob Clark static inline uint32_t A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 5294cc4c26d4SRob Clark { 5295*57cfe41cSRob Clark return ((val >> 11) << A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 5296cc4c26d4SRob Clark } 5297cc4c26d4SRob Clark 52982d756322SRob Clark #define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830 5299cc4c26d4SRob Clark #define A6XX_SP_HS_CTRL_REG0_UNK20 0x00100000 5300cc4c26d4SRob Clark #define A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK 0x00000001 5301cc4c26d4SRob Clark #define A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT 0 5302cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 5303cc4c26d4SRob Clark { 5304cc4c26d4SRob Clark return ((val) << A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK; 5305cc4c26d4SRob Clark } 53062d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 53072d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 53082d756322SRob Clark static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 53092d756322SRob Clark { 53102d756322SRob Clark return ((val) << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 53112d756322SRob Clark } 53122d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 53132d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 53142d756322SRob Clark static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 53152d756322SRob Clark { 53162d756322SRob Clark return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 53172d756322SRob Clark } 5318cc4c26d4SRob Clark #define A6XX_SP_HS_CTRL_REG0_UNK13 0x00002000 53192d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 53202d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 14 53212d756322SRob Clark static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val) 53222d756322SRob Clark { 53232d756322SRob Clark return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK; 53242d756322SRob Clark } 5325cc4c26d4SRob Clark 5326cc4c26d4SRob Clark #define REG_A6XX_SP_HS_WAVE_INPUT_SIZE 0x0000a831 5327cc4c26d4SRob Clark 5328cc4c26d4SRob Clark #define REG_A6XX_SP_HS_BRANCH_COND 0x0000a832 5329cc4c26d4SRob Clark 5330cc4c26d4SRob Clark #define REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET 0x0000a833 5331cc4c26d4SRob Clark 5332cc4c26d4SRob Clark #define REG_A6XX_SP_HS_OBJ_START 0x0000a834 5333cc4c26d4SRob Clark #define A6XX_SP_HS_OBJ_START__MASK 0xffffffff 5334cc4c26d4SRob Clark #define A6XX_SP_HS_OBJ_START__SHIFT 0 5335cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_OBJ_START(uint32_t val) 53362d756322SRob Clark { 5337cc4c26d4SRob Clark return ((val) << A6XX_SP_HS_OBJ_START__SHIFT) & A6XX_SP_HS_OBJ_START__MASK; 53382d756322SRob Clark } 53392d756322SRob Clark 5340cc4c26d4SRob Clark #define REG_A6XX_SP_HS_PVT_MEM_PARAM 0x0000a836 5341cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 5342cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 5343cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 5344cc4c26d4SRob Clark { 5345cc4c26d4SRob Clark return ((val >> 9) << A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 5346cc4c26d4SRob Clark } 5347cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 5348cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 5349cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 5350cc4c26d4SRob Clark { 5351cc4c26d4SRob Clark return ((val) << A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 5352cc4c26d4SRob Clark } 53532d756322SRob Clark 5354cc4c26d4SRob Clark #define REG_A6XX_SP_HS_PVT_MEM_ADDR 0x0000a837 5355cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_ADDR__MASK 0xffffffff 5356cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_ADDR__SHIFT 0 5357cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_PVT_MEM_ADDR(uint32_t val) 5358cc4c26d4SRob Clark { 5359cc4c26d4SRob Clark return ((val) << A6XX_SP_HS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_HS_PVT_MEM_ADDR__MASK; 5360cc4c26d4SRob Clark } 5361c28c82e9SRob Clark 5362cc4c26d4SRob Clark #define REG_A6XX_SP_HS_PVT_MEM_SIZE 0x0000a839 5363cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 5364cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 5365cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 5366cc4c26d4SRob Clark { 5367cc4c26d4SRob Clark return ((val >> 12) << A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 5368cc4c26d4SRob Clark } 5369cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 53702d756322SRob Clark 53712d756322SRob Clark #define REG_A6XX_SP_HS_TEX_COUNT 0x0000a83a 53722d756322SRob Clark 53732d756322SRob Clark #define REG_A6XX_SP_HS_CONFIG 0x0000a83b 5374c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_BINDLESS_TEX 0x00000001 5375c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_BINDLESS_SAMP 0x00000002 5376c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_BINDLESS_IBO 0x00000004 5377c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_BINDLESS_UBO 0x00000008 53782d756322SRob Clark #define A6XX_SP_HS_CONFIG_ENABLED 0x00000100 53792d756322SRob Clark #define A6XX_SP_HS_CONFIG_NTEX__MASK 0x0001fe00 53802d756322SRob Clark #define A6XX_SP_HS_CONFIG_NTEX__SHIFT 9 53812d756322SRob Clark static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val) 53822d756322SRob Clark { 53832d756322SRob Clark return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK; 53842d756322SRob Clark } 5385c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_NSAMP__MASK 0x003e0000 53862d756322SRob Clark #define A6XX_SP_HS_CONFIG_NSAMP__SHIFT 17 53872d756322SRob Clark static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val) 53882d756322SRob Clark { 53892d756322SRob Clark return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK; 53902d756322SRob Clark } 5391cc4c26d4SRob Clark #define A6XX_SP_HS_CONFIG_NIBO__MASK 0x1fc00000 5392c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_NIBO__SHIFT 22 5393c28c82e9SRob Clark static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val) 5394c28c82e9SRob Clark { 5395c28c82e9SRob Clark return ((val) << A6XX_SP_HS_CONFIG_NIBO__SHIFT) & A6XX_SP_HS_CONFIG_NIBO__MASK; 5396c28c82e9SRob Clark } 53972d756322SRob Clark 53982d756322SRob Clark #define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c 53992d756322SRob Clark 5400cc4c26d4SRob Clark #define REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET 0x0000a83d 5401*57cfe41cSRob Clark #define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 5402*57cfe41cSRob Clark #define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 5403*57cfe41cSRob Clark static inline uint32_t A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 5404cc4c26d4SRob Clark { 5405*57cfe41cSRob Clark return ((val >> 11) << A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 5406cc4c26d4SRob Clark } 5407cc4c26d4SRob Clark 54082d756322SRob Clark #define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840 5409cc4c26d4SRob Clark #define A6XX_SP_DS_CTRL_REG0_MERGEDREGS 0x00100000 5410cc4c26d4SRob Clark #define A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK 0x00000001 5411cc4c26d4SRob Clark #define A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT 0 5412cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 5413cc4c26d4SRob Clark { 5414cc4c26d4SRob Clark return ((val) << A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK; 5415cc4c26d4SRob Clark } 54162d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 54172d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 54182d756322SRob Clark static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 54192d756322SRob Clark { 54202d756322SRob Clark return ((val) << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 54212d756322SRob Clark } 54222d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 54232d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 54242d756322SRob Clark static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 54252d756322SRob Clark { 54262d756322SRob Clark return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 54272d756322SRob Clark } 5428cc4c26d4SRob Clark #define A6XX_SP_DS_CTRL_REG0_UNK13 0x00002000 54292d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 54302d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 14 54312d756322SRob Clark static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val) 54322d756322SRob Clark { 54332d756322SRob Clark return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK; 54342d756322SRob Clark } 5435cc4c26d4SRob Clark 5436cc4c26d4SRob Clark #define REG_A6XX_SP_DS_BRANCH_COND 0x0000a841 54372d756322SRob Clark 5438c28c82e9SRob Clark #define REG_A6XX_SP_DS_PRIMITIVE_CNTL 0x0000a842 5439c28c82e9SRob Clark #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f 5440c28c82e9SRob Clark #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT 0 5441c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_OUT(uint32_t val) 5442c28c82e9SRob Clark { 5443c28c82e9SRob Clark return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK; 5444c28c82e9SRob Clark } 5445cc4c26d4SRob Clark #define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0 5446cc4c26d4SRob Clark #define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6 5447cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) 5448cc4c26d4SRob Clark { 5449cc4c26d4SRob Clark return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; 5450cc4c26d4SRob Clark } 5451c28c82e9SRob Clark 5452c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; } 5453c28c82e9SRob Clark 5454c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000a843 + 0x1*i0; } 5455c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_A_REGID__MASK 0x000000ff 5456c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_A_REGID__SHIFT 0 5457c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_OUT_REG_A_REGID(uint32_t val) 5458c28c82e9SRob Clark { 5459c28c82e9SRob Clark return ((val) << A6XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_A_REGID__MASK; 5460c28c82e9SRob Clark } 5461c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00000f00 5462c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 8 5463c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val) 5464c28c82e9SRob Clark { 5465c28c82e9SRob Clark return ((val) << A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK; 5466c28c82e9SRob Clark } 5467c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_B_REGID__MASK 0x00ff0000 5468c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_B_REGID__SHIFT 16 5469c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_OUT_REG_B_REGID(uint32_t val) 5470c28c82e9SRob Clark { 5471c28c82e9SRob Clark return ((val) << A6XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_B_REGID__MASK; 5472c28c82e9SRob Clark } 5473c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x0f000000 5474c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 24 5475c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val) 5476c28c82e9SRob Clark { 5477c28c82e9SRob Clark return ((val) << A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK; 5478c28c82e9SRob Clark } 5479c28c82e9SRob Clark 5480c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000a853 + 0x1*i0; } 5481c28c82e9SRob Clark 5482c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000a853 + 0x1*i0; } 5483c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 5484c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0 5485c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val) 5486c28c82e9SRob Clark { 5487c28c82e9SRob Clark return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK; 5488c28c82e9SRob Clark } 5489c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 5490c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8 5491c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val) 5492c28c82e9SRob Clark { 5493c28c82e9SRob Clark return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK; 5494c28c82e9SRob Clark } 5495c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 5496c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16 5497c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val) 5498c28c82e9SRob Clark { 5499c28c82e9SRob Clark return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK; 5500c28c82e9SRob Clark } 5501c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 5502c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24 5503c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) 5504c28c82e9SRob Clark { 5505c28c82e9SRob Clark return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK; 5506c28c82e9SRob Clark } 5507c28c82e9SRob Clark 5508cc4c26d4SRob Clark #define REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET 0x0000a85b 5509c28c82e9SRob Clark 5510cc4c26d4SRob Clark #define REG_A6XX_SP_DS_OBJ_START 0x0000a85c 5511cc4c26d4SRob Clark #define A6XX_SP_DS_OBJ_START__MASK 0xffffffff 5512cc4c26d4SRob Clark #define A6XX_SP_DS_OBJ_START__SHIFT 0 5513cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_OBJ_START(uint32_t val) 5514cc4c26d4SRob Clark { 5515cc4c26d4SRob Clark return ((val) << A6XX_SP_DS_OBJ_START__SHIFT) & A6XX_SP_DS_OBJ_START__MASK; 5516cc4c26d4SRob Clark } 55172d756322SRob Clark 5518cc4c26d4SRob Clark #define REG_A6XX_SP_DS_PVT_MEM_PARAM 0x0000a85e 5519cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 5520cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 5521cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 5522cc4c26d4SRob Clark { 5523cc4c26d4SRob Clark return ((val >> 9) << A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 5524cc4c26d4SRob Clark } 5525cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 5526cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 5527cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 5528cc4c26d4SRob Clark { 5529cc4c26d4SRob Clark return ((val) << A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 5530cc4c26d4SRob Clark } 5531cc4c26d4SRob Clark 5532cc4c26d4SRob Clark #define REG_A6XX_SP_DS_PVT_MEM_ADDR 0x0000a85f 5533cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_ADDR__MASK 0xffffffff 5534cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_ADDR__SHIFT 0 5535cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_PVT_MEM_ADDR(uint32_t val) 5536cc4c26d4SRob Clark { 5537cc4c26d4SRob Clark return ((val) << A6XX_SP_DS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_DS_PVT_MEM_ADDR__MASK; 5538cc4c26d4SRob Clark } 5539cc4c26d4SRob Clark 5540cc4c26d4SRob Clark #define REG_A6XX_SP_DS_PVT_MEM_SIZE 0x0000a861 5541cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 5542cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 5543cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 5544cc4c26d4SRob Clark { 5545cc4c26d4SRob Clark return ((val >> 12) << A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 5546cc4c26d4SRob Clark } 5547cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 55482d756322SRob Clark 55492d756322SRob Clark #define REG_A6XX_SP_DS_TEX_COUNT 0x0000a862 55502d756322SRob Clark 55512d756322SRob Clark #define REG_A6XX_SP_DS_CONFIG 0x0000a863 5552c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_BINDLESS_TEX 0x00000001 5553c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_BINDLESS_SAMP 0x00000002 5554c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_BINDLESS_IBO 0x00000004 5555c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_BINDLESS_UBO 0x00000008 55562d756322SRob Clark #define A6XX_SP_DS_CONFIG_ENABLED 0x00000100 55572d756322SRob Clark #define A6XX_SP_DS_CONFIG_NTEX__MASK 0x0001fe00 55582d756322SRob Clark #define A6XX_SP_DS_CONFIG_NTEX__SHIFT 9 55592d756322SRob Clark static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val) 55602d756322SRob Clark { 55612d756322SRob Clark return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK; 55622d756322SRob Clark } 5563c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_NSAMP__MASK 0x003e0000 55642d756322SRob Clark #define A6XX_SP_DS_CONFIG_NSAMP__SHIFT 17 55652d756322SRob Clark static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val) 55662d756322SRob Clark { 55672d756322SRob Clark return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK; 55682d756322SRob Clark } 5569cc4c26d4SRob Clark #define A6XX_SP_DS_CONFIG_NIBO__MASK 0x1fc00000 5570c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_NIBO__SHIFT 22 5571c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val) 5572c28c82e9SRob Clark { 5573c28c82e9SRob Clark return ((val) << A6XX_SP_DS_CONFIG_NIBO__SHIFT) & A6XX_SP_DS_CONFIG_NIBO__MASK; 5574c28c82e9SRob Clark } 55752d756322SRob Clark 55762d756322SRob Clark #define REG_A6XX_SP_DS_INSTRLEN 0x0000a864 55772d756322SRob Clark 5578cc4c26d4SRob Clark #define REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET 0x0000a865 5579*57cfe41cSRob Clark #define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 5580*57cfe41cSRob Clark #define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 5581*57cfe41cSRob Clark static inline uint32_t A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 5582cc4c26d4SRob Clark { 5583*57cfe41cSRob Clark return ((val >> 11) << A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 5584cc4c26d4SRob Clark } 5585cc4c26d4SRob Clark 55862d756322SRob Clark #define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870 5587cc4c26d4SRob Clark #define A6XX_SP_GS_CTRL_REG0_UNK20 0x00100000 5588cc4c26d4SRob Clark #define A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK 0x00000001 5589cc4c26d4SRob Clark #define A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT 0 5590cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 5591cc4c26d4SRob Clark { 5592cc4c26d4SRob Clark return ((val) << A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK; 5593cc4c26d4SRob Clark } 55942d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 55952d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 55962d756322SRob Clark static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 55972d756322SRob Clark { 55982d756322SRob Clark return ((val) << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 55992d756322SRob Clark } 56002d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 56012d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 56022d756322SRob Clark static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 56032d756322SRob Clark { 56042d756322SRob Clark return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 56052d756322SRob Clark } 5606cc4c26d4SRob Clark #define A6XX_SP_GS_CTRL_REG0_UNK13 0x00002000 56072d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 56082d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 14 56092d756322SRob Clark static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val) 56102d756322SRob Clark { 56112d756322SRob Clark return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK; 56122d756322SRob Clark } 56132d756322SRob Clark 5614c28c82e9SRob Clark #define REG_A6XX_SP_GS_PRIM_SIZE 0x0000a871 5615c28c82e9SRob Clark 5616c28c82e9SRob Clark #define REG_A6XX_SP_GS_BRANCH_COND 0x0000a872 5617c28c82e9SRob Clark 5618c28c82e9SRob Clark #define REG_A6XX_SP_GS_PRIMITIVE_CNTL 0x0000a873 5619c28c82e9SRob Clark #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f 5620c28c82e9SRob Clark #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT 0 5621c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_OUT(uint32_t val) 5622c28c82e9SRob Clark { 5623c28c82e9SRob Clark return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK; 5624c28c82e9SRob Clark } 5625c28c82e9SRob Clark #define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0 5626c28c82e9SRob Clark #define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6 5627c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) 5628c28c82e9SRob Clark { 5629c28c82e9SRob Clark return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; 5630c28c82e9SRob Clark } 5631c28c82e9SRob Clark 5632c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_GS_OUT(uint32_t i0) { return 0x0000a874 + 0x1*i0; } 5633c28c82e9SRob Clark 5634c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_GS_OUT_REG(uint32_t i0) { return 0x0000a874 + 0x1*i0; } 5635c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_A_REGID__MASK 0x000000ff 5636c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_A_REGID__SHIFT 0 5637c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_OUT_REG_A_REGID(uint32_t val) 5638c28c82e9SRob Clark { 5639c28c82e9SRob Clark return ((val) << A6XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_A_REGID__MASK; 5640c28c82e9SRob Clark } 5641c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00000f00 5642c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 8 5643c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val) 5644c28c82e9SRob Clark { 5645c28c82e9SRob Clark return ((val) << A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK; 5646c28c82e9SRob Clark } 5647c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_B_REGID__MASK 0x00ff0000 5648c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_B_REGID__SHIFT 16 5649c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_OUT_REG_B_REGID(uint32_t val) 5650c28c82e9SRob Clark { 5651c28c82e9SRob Clark return ((val) << A6XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_B_REGID__MASK; 5652c28c82e9SRob Clark } 5653c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x0f000000 5654c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 24 5655c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val) 5656c28c82e9SRob Clark { 5657c28c82e9SRob Clark return ((val) << A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK; 5658c28c82e9SRob Clark } 5659c28c82e9SRob Clark 5660c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_GS_VPC_DST(uint32_t i0) { return 0x0000a884 + 0x1*i0; } 5661c28c82e9SRob Clark 5662c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x0000a884 + 0x1*i0; } 5663c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 5664c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0 5665c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val) 5666c28c82e9SRob Clark { 5667c28c82e9SRob Clark return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK; 5668c28c82e9SRob Clark } 5669c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 5670c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8 5671c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val) 5672c28c82e9SRob Clark { 5673c28c82e9SRob Clark return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK; 5674c28c82e9SRob Clark } 5675c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 5676c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16 5677c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val) 5678c28c82e9SRob Clark { 5679c28c82e9SRob Clark return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK; 5680c28c82e9SRob Clark } 5681c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 5682c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24 5683c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) 5684c28c82e9SRob Clark { 5685c28c82e9SRob Clark return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK; 5686c28c82e9SRob Clark } 56872d756322SRob Clark 5688cc4c26d4SRob Clark #define REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET 0x0000a88c 56892d756322SRob Clark 5690cc4c26d4SRob Clark #define REG_A6XX_SP_GS_OBJ_START 0x0000a88d 5691cc4c26d4SRob Clark #define A6XX_SP_GS_OBJ_START__MASK 0xffffffff 5692cc4c26d4SRob Clark #define A6XX_SP_GS_OBJ_START__SHIFT 0 5693cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_OBJ_START(uint32_t val) 5694cc4c26d4SRob Clark { 5695cc4c26d4SRob Clark return ((val) << A6XX_SP_GS_OBJ_START__SHIFT) & A6XX_SP_GS_OBJ_START__MASK; 5696cc4c26d4SRob Clark } 5697cc4c26d4SRob Clark 5698cc4c26d4SRob Clark #define REG_A6XX_SP_GS_PVT_MEM_PARAM 0x0000a88f 5699cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 5700cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 5701cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 5702cc4c26d4SRob Clark { 5703cc4c26d4SRob Clark return ((val >> 9) << A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 5704cc4c26d4SRob Clark } 5705cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 5706cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 5707cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 5708cc4c26d4SRob Clark { 5709cc4c26d4SRob Clark return ((val) << A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 5710cc4c26d4SRob Clark } 5711cc4c26d4SRob Clark 5712cc4c26d4SRob Clark #define REG_A6XX_SP_GS_PVT_MEM_ADDR 0x0000a890 5713cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_ADDR__MASK 0xffffffff 5714cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_ADDR__SHIFT 0 5715cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_PVT_MEM_ADDR(uint32_t val) 5716cc4c26d4SRob Clark { 5717cc4c26d4SRob Clark return ((val) << A6XX_SP_GS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_GS_PVT_MEM_ADDR__MASK; 5718cc4c26d4SRob Clark } 5719cc4c26d4SRob Clark 5720cc4c26d4SRob Clark #define REG_A6XX_SP_GS_PVT_MEM_SIZE 0x0000a892 5721cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 5722cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 5723cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 5724cc4c26d4SRob Clark { 5725cc4c26d4SRob Clark return ((val >> 12) << A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 5726cc4c26d4SRob Clark } 5727cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 57282d756322SRob Clark 57292d756322SRob Clark #define REG_A6XX_SP_GS_TEX_COUNT 0x0000a893 57302d756322SRob Clark 57312d756322SRob Clark #define REG_A6XX_SP_GS_CONFIG 0x0000a894 5732c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_BINDLESS_TEX 0x00000001 5733c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_BINDLESS_SAMP 0x00000002 5734c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_BINDLESS_IBO 0x00000004 5735c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_BINDLESS_UBO 0x00000008 57362d756322SRob Clark #define A6XX_SP_GS_CONFIG_ENABLED 0x00000100 57372d756322SRob Clark #define A6XX_SP_GS_CONFIG_NTEX__MASK 0x0001fe00 57382d756322SRob Clark #define A6XX_SP_GS_CONFIG_NTEX__SHIFT 9 57392d756322SRob Clark static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val) 57402d756322SRob Clark { 57412d756322SRob Clark return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK; 57422d756322SRob Clark } 5743c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_NSAMP__MASK 0x003e0000 57442d756322SRob Clark #define A6XX_SP_GS_CONFIG_NSAMP__SHIFT 17 57452d756322SRob Clark static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val) 57462d756322SRob Clark { 57472d756322SRob Clark return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK; 57482d756322SRob Clark } 5749cc4c26d4SRob Clark #define A6XX_SP_GS_CONFIG_NIBO__MASK 0x1fc00000 5750c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_NIBO__SHIFT 22 5751c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val) 5752c28c82e9SRob Clark { 5753c28c82e9SRob Clark return ((val) << A6XX_SP_GS_CONFIG_NIBO__SHIFT) & A6XX_SP_GS_CONFIG_NIBO__MASK; 5754c28c82e9SRob Clark } 57552d756322SRob Clark 57562d756322SRob Clark #define REG_A6XX_SP_GS_INSTRLEN 0x0000a895 57572d756322SRob Clark 5758cc4c26d4SRob Clark #define REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET 0x0000a896 5759*57cfe41cSRob Clark #define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 5760*57cfe41cSRob Clark #define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 5761*57cfe41cSRob Clark static inline uint32_t A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 5762cc4c26d4SRob Clark { 5763*57cfe41cSRob Clark return ((val >> 11) << A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 5764cc4c26d4SRob Clark } 57652d756322SRob Clark 5766cc4c26d4SRob Clark #define REG_A6XX_SP_VS_TEX_SAMP 0x0000a8a0 5767cc4c26d4SRob Clark #define A6XX_SP_VS_TEX_SAMP__MASK 0xffffffff 5768cc4c26d4SRob Clark #define A6XX_SP_VS_TEX_SAMP__SHIFT 0 5769cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_TEX_SAMP(uint32_t val) 5770cc4c26d4SRob Clark { 5771cc4c26d4SRob Clark return ((val) << A6XX_SP_VS_TEX_SAMP__SHIFT) & A6XX_SP_VS_TEX_SAMP__MASK; 5772cc4c26d4SRob Clark } 57732d756322SRob Clark 5774cc4c26d4SRob Clark #define REG_A6XX_SP_HS_TEX_SAMP 0x0000a8a2 5775cc4c26d4SRob Clark #define A6XX_SP_HS_TEX_SAMP__MASK 0xffffffff 5776cc4c26d4SRob Clark #define A6XX_SP_HS_TEX_SAMP__SHIFT 0 5777cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_TEX_SAMP(uint32_t val) 5778cc4c26d4SRob Clark { 5779cc4c26d4SRob Clark return ((val) << A6XX_SP_HS_TEX_SAMP__SHIFT) & A6XX_SP_HS_TEX_SAMP__MASK; 5780cc4c26d4SRob Clark } 57812d756322SRob Clark 5782cc4c26d4SRob Clark #define REG_A6XX_SP_DS_TEX_SAMP 0x0000a8a4 5783cc4c26d4SRob Clark #define A6XX_SP_DS_TEX_SAMP__MASK 0xffffffff 5784cc4c26d4SRob Clark #define A6XX_SP_DS_TEX_SAMP__SHIFT 0 5785cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_TEX_SAMP(uint32_t val) 5786cc4c26d4SRob Clark { 5787cc4c26d4SRob Clark return ((val) << A6XX_SP_DS_TEX_SAMP__SHIFT) & A6XX_SP_DS_TEX_SAMP__MASK; 5788cc4c26d4SRob Clark } 57892d756322SRob Clark 5790cc4c26d4SRob Clark #define REG_A6XX_SP_GS_TEX_SAMP 0x0000a8a6 5791cc4c26d4SRob Clark #define A6XX_SP_GS_TEX_SAMP__MASK 0xffffffff 5792cc4c26d4SRob Clark #define A6XX_SP_GS_TEX_SAMP__SHIFT 0 5793cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_TEX_SAMP(uint32_t val) 5794cc4c26d4SRob Clark { 5795cc4c26d4SRob Clark return ((val) << A6XX_SP_GS_TEX_SAMP__SHIFT) & A6XX_SP_GS_TEX_SAMP__MASK; 5796cc4c26d4SRob Clark } 57972d756322SRob Clark 5798cc4c26d4SRob Clark #define REG_A6XX_SP_VS_TEX_CONST 0x0000a8a8 5799cc4c26d4SRob Clark #define A6XX_SP_VS_TEX_CONST__MASK 0xffffffff 5800cc4c26d4SRob Clark #define A6XX_SP_VS_TEX_CONST__SHIFT 0 5801cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_TEX_CONST(uint32_t val) 5802cc4c26d4SRob Clark { 5803cc4c26d4SRob Clark return ((val) << A6XX_SP_VS_TEX_CONST__SHIFT) & A6XX_SP_VS_TEX_CONST__MASK; 5804cc4c26d4SRob Clark } 58052d756322SRob Clark 5806cc4c26d4SRob Clark #define REG_A6XX_SP_HS_TEX_CONST 0x0000a8aa 5807cc4c26d4SRob Clark #define A6XX_SP_HS_TEX_CONST__MASK 0xffffffff 5808cc4c26d4SRob Clark #define A6XX_SP_HS_TEX_CONST__SHIFT 0 5809cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_TEX_CONST(uint32_t val) 5810cc4c26d4SRob Clark { 5811cc4c26d4SRob Clark return ((val) << A6XX_SP_HS_TEX_CONST__SHIFT) & A6XX_SP_HS_TEX_CONST__MASK; 5812cc4c26d4SRob Clark } 58132d756322SRob Clark 5814cc4c26d4SRob Clark #define REG_A6XX_SP_DS_TEX_CONST 0x0000a8ac 5815cc4c26d4SRob Clark #define A6XX_SP_DS_TEX_CONST__MASK 0xffffffff 5816cc4c26d4SRob Clark #define A6XX_SP_DS_TEX_CONST__SHIFT 0 5817cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_TEX_CONST(uint32_t val) 5818cc4c26d4SRob Clark { 5819cc4c26d4SRob Clark return ((val) << A6XX_SP_DS_TEX_CONST__SHIFT) & A6XX_SP_DS_TEX_CONST__MASK; 5820cc4c26d4SRob Clark } 58212d756322SRob Clark 5822cc4c26d4SRob Clark #define REG_A6XX_SP_GS_TEX_CONST 0x0000a8ae 5823cc4c26d4SRob Clark #define A6XX_SP_GS_TEX_CONST__MASK 0xffffffff 5824cc4c26d4SRob Clark #define A6XX_SP_GS_TEX_CONST__SHIFT 0 5825cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_TEX_CONST(uint32_t val) 5826cc4c26d4SRob Clark { 5827cc4c26d4SRob Clark return ((val) << A6XX_SP_GS_TEX_CONST__SHIFT) & A6XX_SP_GS_TEX_CONST__MASK; 5828cc4c26d4SRob Clark } 58292d756322SRob Clark 58302d756322SRob Clark #define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980 5831cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 5832cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 5833cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) 5834cc4c26d4SRob Clark { 5835cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 5836cc4c26d4SRob Clark } 5837cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_UNK21 0x00200000 5838cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000 5839cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_DIFF_FINE 0x00800000 5840cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_UNK24 0x01000000 5841cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_UNK25 0x02000000 5842cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000 5843cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_UNK27__MASK 0x18000000 5844cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_UNK27__SHIFT 27 5845cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_UNK27(uint32_t val) 5846cc4c26d4SRob Clark { 5847cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_UNK27__SHIFT) & A6XX_SP_FS_CTRL_REG0_UNK27__MASK; 5848cc4c26d4SRob Clark } 5849cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000 5850cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 5851cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 5852cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 5853cc4c26d4SRob Clark { 5854cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK; 5855cc4c26d4SRob Clark } 58562d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 58572d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 58582d756322SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 58592d756322SRob Clark { 58602d756322SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 58612d756322SRob Clark } 58622d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 58632d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 58642d756322SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 58652d756322SRob Clark { 58662d756322SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 58672d756322SRob Clark } 5868cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_UNK13 0x00002000 58692d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 58702d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 14 58712d756322SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) 58722d756322SRob Clark { 58732d756322SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK; 58742d756322SRob Clark } 58752d756322SRob Clark 5876c28c82e9SRob Clark #define REG_A6XX_SP_FS_BRANCH_COND 0x0000a981 5877c28c82e9SRob Clark 5878cc4c26d4SRob Clark #define REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET 0x0000a982 5879a69c5ed2SRob Clark 5880cc4c26d4SRob Clark #define REG_A6XX_SP_FS_OBJ_START 0x0000a983 5881cc4c26d4SRob Clark #define A6XX_SP_FS_OBJ_START__MASK 0xffffffff 5882cc4c26d4SRob Clark #define A6XX_SP_FS_OBJ_START__SHIFT 0 5883cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_OBJ_START(uint32_t val) 5884cc4c26d4SRob Clark { 5885cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_OBJ_START__SHIFT) & A6XX_SP_FS_OBJ_START__MASK; 5886cc4c26d4SRob Clark } 58872d756322SRob Clark 5888cc4c26d4SRob Clark #define REG_A6XX_SP_FS_PVT_MEM_PARAM 0x0000a985 5889cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 5890cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 5891cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 5892cc4c26d4SRob Clark { 5893cc4c26d4SRob Clark return ((val >> 9) << A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 5894cc4c26d4SRob Clark } 5895cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 5896cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 5897cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 5898cc4c26d4SRob Clark { 5899cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 5900cc4c26d4SRob Clark } 5901cc4c26d4SRob Clark 5902cc4c26d4SRob Clark #define REG_A6XX_SP_FS_PVT_MEM_ADDR 0x0000a986 5903cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_ADDR__MASK 0xffffffff 5904cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_ADDR__SHIFT 0 5905cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_PVT_MEM_ADDR(uint32_t val) 5906cc4c26d4SRob Clark { 5907cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_FS_PVT_MEM_ADDR__MASK; 5908cc4c26d4SRob Clark } 5909cc4c26d4SRob Clark 5910cc4c26d4SRob Clark #define REG_A6XX_SP_FS_PVT_MEM_SIZE 0x0000a988 5911cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 5912cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 5913cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 5914cc4c26d4SRob Clark { 5915cc4c26d4SRob Clark return ((val >> 12) << A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 5916cc4c26d4SRob Clark } 5917cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 59182d756322SRob Clark 59192d756322SRob Clark #define REG_A6XX_SP_BLEND_CNTL 0x0000a989 5920cc4c26d4SRob Clark #define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff 5921cc4c26d4SRob Clark #define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 5922cc4c26d4SRob Clark static inline uint32_t A6XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val) 5923cc4c26d4SRob Clark { 5924cc4c26d4SRob Clark return ((val) << A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK; 5925cc4c26d4SRob Clark } 59262d756322SRob Clark #define A6XX_SP_BLEND_CNTL_UNK8 0x00000100 5927c28c82e9SRob Clark #define A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200 5928ccdf7e28SRob Clark #define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 59292d756322SRob Clark 59302d756322SRob Clark #define REG_A6XX_SP_SRGB_CNTL 0x0000a98a 59312d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT0 0x00000001 59322d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT1 0x00000002 59332d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT2 0x00000004 59342d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT3 0x00000008 59352d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT4 0x00000010 59362d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT5 0x00000020 59372d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT6 0x00000040 59382d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT7 0x00000080 59392d756322SRob Clark 59402d756322SRob Clark #define REG_A6XX_SP_FS_RENDER_COMPONENTS 0x0000a98b 59412d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK 0x0000000f 59422d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT 0 59432d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val) 59442d756322SRob Clark { 59452d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK; 59462d756322SRob Clark } 59472d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK 0x000000f0 59482d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT 4 59492d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val) 59502d756322SRob Clark { 59512d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK; 59522d756322SRob Clark } 59532d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK 0x00000f00 59542d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT 8 59552d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val) 59562d756322SRob Clark { 59572d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK; 59582d756322SRob Clark } 59592d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK 0x0000f000 59602d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT 12 59612d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val) 59622d756322SRob Clark { 59632d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK; 59642d756322SRob Clark } 59652d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK 0x000f0000 59662d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT 16 59672d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val) 59682d756322SRob Clark { 59692d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK; 59702d756322SRob Clark } 59712d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK 0x00f00000 59722d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT 20 59732d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val) 59742d756322SRob Clark { 59752d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK; 59762d756322SRob Clark } 59772d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK 0x0f000000 59782d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT 24 59792d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val) 59802d756322SRob Clark { 59812d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK; 59822d756322SRob Clark } 59832d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK 0xf0000000 59842d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT 28 59852d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val) 59862d756322SRob Clark { 59872d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK; 59882d756322SRob Clark } 59892d756322SRob Clark 59902d756322SRob Clark #define REG_A6XX_SP_FS_OUTPUT_CNTL0 0x0000a98c 5991c28c82e9SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001 59922d756322SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK 0x0000ff00 59932d756322SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT 8 59942d756322SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val) 59952d756322SRob Clark { 59962d756322SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK; 59972d756322SRob Clark } 5998c28c82e9SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK 0x00ff0000 5999c28c82e9SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT 16 6000c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(uint32_t val) 6001c28c82e9SRob Clark { 6002c28c82e9SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK; 6003c28c82e9SRob Clark } 6004c28c82e9SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK 0xff000000 6005c28c82e9SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT 24 6006c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(uint32_t val) 6007c28c82e9SRob Clark { 6008c28c82e9SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK; 6009c28c82e9SRob Clark } 60102d756322SRob Clark 60112d756322SRob Clark #define REG_A6XX_SP_FS_OUTPUT_CNTL1 0x0000a98d 60122d756322SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f 60132d756322SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT 0 60142d756322SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val) 60152d756322SRob Clark { 60162d756322SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK; 60172d756322SRob Clark } 60182d756322SRob Clark 6019cc4c26d4SRob Clark static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; } 6020cc4c26d4SRob Clark 6021cc4c26d4SRob Clark static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; } 6022cc4c26d4SRob Clark #define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff 6023cc4c26d4SRob Clark #define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0 6024cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) 6025cc4c26d4SRob Clark { 6026cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK; 6027cc4c26d4SRob Clark } 6028cc4c26d4SRob Clark #define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100 6029cc4c26d4SRob Clark 60302d756322SRob Clark static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; } 60312d756322SRob Clark 60322d756322SRob Clark static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; } 60332d756322SRob Clark #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff 60342d756322SRob Clark #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0 6035c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val) 60362d756322SRob Clark { 60372d756322SRob Clark return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK; 60382d756322SRob Clark } 60392d756322SRob Clark #define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100 60402d756322SRob Clark #define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200 6041cc4c26d4SRob Clark #define A6XX_SP_FS_MRT_REG_UNK10 0x00000400 6042a69c5ed2SRob Clark 6043c28c82e9SRob Clark #define REG_A6XX_SP_FS_PREFETCH_CNTL 0x0000a99e 6044c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK 0x00000007 6045c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT 0 6046c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_COUNT(uint32_t val) 6047c28c82e9SRob Clark { 6048c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK; 6049c28c82e9SRob Clark } 6050c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_UNK3 0x00000008 6051c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK 0x00000ff0 6052c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT 4 6053c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK4(uint32_t val) 6054c28c82e9SRob Clark { 6055c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK; 6056c28c82e9SRob Clark } 6057cc4c26d4SRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_UNK12__MASK 0x00007000 6058cc4c26d4SRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_UNK12__SHIFT 12 6059cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK12(uint32_t val) 6060cc4c26d4SRob Clark { 6061cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK12__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK12__MASK; 6062cc4c26d4SRob Clark } 6063c28c82e9SRob Clark 6064c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_FS_PREFETCH(uint32_t i0) { return 0x0000a99f + 0x1*i0; } 6065c28c82e9SRob Clark 6066c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; } 6067c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_SRC__MASK 0x0000007f 6068c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT 0 6069c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val) 6070c28c82e9SRob Clark { 6071c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SRC__MASK; 6072c28c82e9SRob Clark } 6073c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK 0x00000780 6074c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT 7 6075c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val) 6076c28c82e9SRob Clark { 6077c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK; 6078c28c82e9SRob Clark } 6079c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK 0x0000f800 6080c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT 11 6081c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val) 6082c28c82e9SRob Clark { 6083c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK; 6084c28c82e9SRob Clark } 6085c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_DST__MASK 0x003f0000 6086c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT 16 6087c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_DST(uint32_t val) 6088c28c82e9SRob Clark { 6089c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_DST__MASK; 6090c28c82e9SRob Clark } 6091c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK 0x03c00000 6092c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT 22 6093c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val) 6094c28c82e9SRob Clark { 6095c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK; 6096c28c82e9SRob Clark } 6097c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_HALF 0x04000000 6098c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_CMD__MASK 0xf8000000 6099c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT 27 6100c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_CMD(uint32_t val) 6101c28c82e9SRob Clark { 6102c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_CMD__MASK; 6103c28c82e9SRob Clark } 6104c28c82e9SRob Clark 6105c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; } 6106c28c82e9SRob Clark 6107c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; } 6108cc4c26d4SRob Clark #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK 0x0000ffff 6109c28c82e9SRob Clark #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT 0 6110c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val) 6111c28c82e9SRob Clark { 6112c28c82e9SRob Clark return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK; 6113c28c82e9SRob Clark } 6114cc4c26d4SRob Clark #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK 0xffff0000 6115c28c82e9SRob Clark #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT 16 6116c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val) 6117c28c82e9SRob Clark { 6118c28c82e9SRob Clark return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK; 6119c28c82e9SRob Clark } 61202d756322SRob Clark 61212d756322SRob Clark #define REG_A6XX_SP_FS_TEX_COUNT 0x0000a9a7 61222d756322SRob Clark 61232d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8 61242d756322SRob Clark 6125cc4c26d4SRob Clark #define REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET 0x0000a9a9 6126*57cfe41cSRob Clark #define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 6127*57cfe41cSRob Clark #define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 6128*57cfe41cSRob Clark static inline uint32_t A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 6129c28c82e9SRob Clark { 6130*57cfe41cSRob Clark return ((val >> 11) << A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 6131c28c82e9SRob Clark } 6132c28c82e9SRob Clark 61332d756322SRob Clark #define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0 6134cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000 6135cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20 6136cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) 6137cc4c26d4SRob Clark { 6138cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK; 6139cc4c26d4SRob Clark } 6140cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_UNK21 0x00200000 6141cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_UNK22 0x00400000 6142cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_SEPARATEPROLOG 0x00800000 6143cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000 6144cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK 0x00000001 6145cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT 0 6146cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 6147cc4c26d4SRob Clark { 6148cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK; 6149cc4c26d4SRob Clark } 61502d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 61512d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 61522d756322SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 61532d756322SRob Clark { 61542d756322SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 61552d756322SRob Clark } 61562d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 61572d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 61582d756322SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 61592d756322SRob Clark { 61602d756322SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 61612d756322SRob Clark } 6162cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_UNK13 0x00002000 61632d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 61642d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 14 61652d756322SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val) 61662d756322SRob Clark { 61672d756322SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK; 61682d756322SRob Clark } 6169cc4c26d4SRob Clark 6170cc4c26d4SRob Clark #define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1 6171cc4c26d4SRob Clark #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK 0x0000001f 6172cc4c26d4SRob Clark #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT 0 6173cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(uint32_t val) 61742d756322SRob Clark { 6175cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK; 61762d756322SRob Clark } 6177cc4c26d4SRob Clark #define A6XX_SP_CS_UNKNOWN_A9B1_UNK5 0x00000020 6178cc4c26d4SRob Clark #define A6XX_SP_CS_UNKNOWN_A9B1_UNK6 0x00000040 61792d756322SRob Clark 6180cc4c26d4SRob Clark #define REG_A6XX_SP_CS_BRANCH_COND 0x0000a9b2 61812d756322SRob Clark 6182cc4c26d4SRob Clark #define REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET 0x0000a9b3 6183cc4c26d4SRob Clark 6184cc4c26d4SRob Clark #define REG_A6XX_SP_CS_OBJ_START 0x0000a9b4 6185cc4c26d4SRob Clark #define A6XX_SP_CS_OBJ_START__MASK 0xffffffff 6186cc4c26d4SRob Clark #define A6XX_SP_CS_OBJ_START__SHIFT 0 6187cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_OBJ_START(uint32_t val) 6188cc4c26d4SRob Clark { 6189cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_OBJ_START__SHIFT) & A6XX_SP_CS_OBJ_START__MASK; 6190cc4c26d4SRob Clark } 6191cc4c26d4SRob Clark 6192cc4c26d4SRob Clark #define REG_A6XX_SP_CS_PVT_MEM_PARAM 0x0000a9b6 6193cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 6194cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 6195cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 6196cc4c26d4SRob Clark { 6197cc4c26d4SRob Clark return ((val >> 9) << A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 6198cc4c26d4SRob Clark } 6199cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 6200cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 6201cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 6202cc4c26d4SRob Clark { 6203cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 6204cc4c26d4SRob Clark } 6205cc4c26d4SRob Clark 6206cc4c26d4SRob Clark #define REG_A6XX_SP_CS_PVT_MEM_ADDR 0x0000a9b7 6207cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_ADDR__MASK 0xffffffff 6208cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_ADDR__SHIFT 0 6209cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_PVT_MEM_ADDR(uint32_t val) 6210cc4c26d4SRob Clark { 6211cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_CS_PVT_MEM_ADDR__MASK; 6212cc4c26d4SRob Clark } 6213cc4c26d4SRob Clark 6214cc4c26d4SRob Clark #define REG_A6XX_SP_CS_PVT_MEM_SIZE 0x0000a9b9 6215cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 6216cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 6217cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 6218cc4c26d4SRob Clark { 6219cc4c26d4SRob Clark return ((val >> 12) << A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 6220cc4c26d4SRob Clark } 6221cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 6222cc4c26d4SRob Clark 6223cc4c26d4SRob Clark #define REG_A6XX_SP_CS_TEX_COUNT 0x0000a9ba 62242d756322SRob Clark 6225c28c82e9SRob Clark #define REG_A6XX_SP_CS_CONFIG 0x0000a9bb 6226c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_BINDLESS_TEX 0x00000001 6227c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_BINDLESS_SAMP 0x00000002 6228c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_BINDLESS_IBO 0x00000004 6229c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_BINDLESS_UBO 0x00000008 6230c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_ENABLED 0x00000100 6231c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_NTEX__MASK 0x0001fe00 6232c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_NTEX__SHIFT 9 6233c28c82e9SRob Clark static inline uint32_t A6XX_SP_CS_CONFIG_NTEX(uint32_t val) 6234c28c82e9SRob Clark { 6235c28c82e9SRob Clark return ((val) << A6XX_SP_CS_CONFIG_NTEX__SHIFT) & A6XX_SP_CS_CONFIG_NTEX__MASK; 6236c28c82e9SRob Clark } 6237c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_NSAMP__MASK 0x003e0000 6238c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_NSAMP__SHIFT 17 6239c28c82e9SRob Clark static inline uint32_t A6XX_SP_CS_CONFIG_NSAMP(uint32_t val) 6240c28c82e9SRob Clark { 6241c28c82e9SRob Clark return ((val) << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK; 6242c28c82e9SRob Clark } 6243cc4c26d4SRob Clark #define A6XX_SP_CS_CONFIG_NIBO__MASK 0x1fc00000 6244c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_NIBO__SHIFT 22 6245c28c82e9SRob Clark static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val) 6246c28c82e9SRob Clark { 6247c28c82e9SRob Clark return ((val) << A6XX_SP_CS_CONFIG_NIBO__SHIFT) & A6XX_SP_CS_CONFIG_NIBO__MASK; 6248c28c82e9SRob Clark } 6249c28c82e9SRob Clark 62502d756322SRob Clark #define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc 62512d756322SRob Clark 6252cc4c26d4SRob Clark #define REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET 0x0000a9bd 6253*57cfe41cSRob Clark #define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 6254*57cfe41cSRob Clark #define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 6255*57cfe41cSRob Clark static inline uint32_t A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 6256cc4c26d4SRob Clark { 6257*57cfe41cSRob Clark return ((val >> 11) << A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 6258cc4c26d4SRob Clark } 6259c28c82e9SRob Clark 6260*57cfe41cSRob Clark #define REG_A6XX_SP_CS_CNTL_0 0x0000a9c2 6261*57cfe41cSRob Clark #define A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff 6262*57cfe41cSRob Clark #define A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT 0 6263*57cfe41cSRob Clark static inline uint32_t A6XX_SP_CS_CNTL_0_WGIDCONSTID(uint32_t val) 6264*57cfe41cSRob Clark { 6265*57cfe41cSRob Clark return ((val) << A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK; 6266*57cfe41cSRob Clark } 6267*57cfe41cSRob Clark #define A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK 0x0000ff00 6268*57cfe41cSRob Clark #define A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT 8 6269*57cfe41cSRob Clark static inline uint32_t A6XX_SP_CS_CNTL_0_WGSIZECONSTID(uint32_t val) 6270*57cfe41cSRob Clark { 6271*57cfe41cSRob Clark return ((val) << A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK; 6272*57cfe41cSRob Clark } 6273*57cfe41cSRob Clark #define A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK 0x00ff0000 6274*57cfe41cSRob Clark #define A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT 16 6275*57cfe41cSRob Clark static inline uint32_t A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val) 6276*57cfe41cSRob Clark { 6277*57cfe41cSRob Clark return ((val) << A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK; 6278*57cfe41cSRob Clark } 6279*57cfe41cSRob Clark #define A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000 6280*57cfe41cSRob Clark #define A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT 24 6281*57cfe41cSRob Clark static inline uint32_t A6XX_SP_CS_CNTL_0_LOCALIDREGID(uint32_t val) 6282*57cfe41cSRob Clark { 6283*57cfe41cSRob Clark return ((val) << A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK; 6284*57cfe41cSRob Clark } 6285*57cfe41cSRob Clark 6286*57cfe41cSRob Clark #define REG_A6XX_SP_CS_CNTL_1 0x0000a9c3 6287*57cfe41cSRob Clark #define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff 6288*57cfe41cSRob Clark #define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0 6289*57cfe41cSRob Clark static inline uint32_t A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) 6290*57cfe41cSRob Clark { 6291*57cfe41cSRob Clark return ((val) << A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK; 6292*57cfe41cSRob Clark } 6293*57cfe41cSRob Clark #define A6XX_SP_CS_CNTL_1_SINGLE_SP_CORE 0x00000100 6294*57cfe41cSRob Clark #define A6XX_SP_CS_CNTL_1_THREADSIZE__MASK 0x00000200 6295*57cfe41cSRob Clark #define A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT 9 6296*57cfe41cSRob Clark static inline uint32_t A6XX_SP_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) 6297*57cfe41cSRob Clark { 6298*57cfe41cSRob Clark return ((val) << A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_SP_CS_CNTL_1_THREADSIZE__MASK; 6299*57cfe41cSRob Clark } 6300*57cfe41cSRob Clark #define A6XX_SP_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400 6301*57cfe41cSRob Clark 6302cc4c26d4SRob Clark #define REG_A6XX_SP_FS_TEX_SAMP 0x0000a9e0 6303cc4c26d4SRob Clark #define A6XX_SP_FS_TEX_SAMP__MASK 0xffffffff 6304cc4c26d4SRob Clark #define A6XX_SP_FS_TEX_SAMP__SHIFT 0 6305cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_TEX_SAMP(uint32_t val) 6306cc4c26d4SRob Clark { 6307cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_TEX_SAMP__SHIFT) & A6XX_SP_FS_TEX_SAMP__MASK; 6308cc4c26d4SRob Clark } 6309cc4c26d4SRob Clark 6310cc4c26d4SRob Clark #define REG_A6XX_SP_CS_TEX_SAMP 0x0000a9e2 6311cc4c26d4SRob Clark #define A6XX_SP_CS_TEX_SAMP__MASK 0xffffffff 6312cc4c26d4SRob Clark #define A6XX_SP_CS_TEX_SAMP__SHIFT 0 6313cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_TEX_SAMP(uint32_t val) 6314cc4c26d4SRob Clark { 6315cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_TEX_SAMP__SHIFT) & A6XX_SP_CS_TEX_SAMP__MASK; 6316cc4c26d4SRob Clark } 6317cc4c26d4SRob Clark 6318cc4c26d4SRob Clark #define REG_A6XX_SP_FS_TEX_CONST 0x0000a9e4 6319cc4c26d4SRob Clark #define A6XX_SP_FS_TEX_CONST__MASK 0xffffffff 6320cc4c26d4SRob Clark #define A6XX_SP_FS_TEX_CONST__SHIFT 0 6321cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_TEX_CONST(uint32_t val) 6322cc4c26d4SRob Clark { 6323cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_TEX_CONST__SHIFT) & A6XX_SP_FS_TEX_CONST__MASK; 6324cc4c26d4SRob Clark } 6325cc4c26d4SRob Clark 6326cc4c26d4SRob Clark #define REG_A6XX_SP_CS_TEX_CONST 0x0000a9e6 6327cc4c26d4SRob Clark #define A6XX_SP_CS_TEX_CONST__MASK 0xffffffff 6328cc4c26d4SRob Clark #define A6XX_SP_CS_TEX_CONST__SHIFT 0 6329cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_TEX_CONST(uint32_t val) 6330cc4c26d4SRob Clark { 6331cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_TEX_CONST__SHIFT) & A6XX_SP_CS_TEX_CONST__MASK; 6332cc4c26d4SRob Clark } 6333cc4c26d4SRob Clark 6334cc4c26d4SRob Clark static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; } 6335cc4c26d4SRob Clark 6336cc4c26d4SRob Clark static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; } 6337cc4c26d4SRob Clark 6338cc4c26d4SRob Clark #define REG_A6XX_SP_CS_IBO 0x0000a9f2 6339cc4c26d4SRob Clark #define A6XX_SP_CS_IBO__MASK 0xffffffff 6340cc4c26d4SRob Clark #define A6XX_SP_CS_IBO__SHIFT 0 6341cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_IBO(uint32_t val) 6342cc4c26d4SRob Clark { 6343cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_IBO__SHIFT) & A6XX_SP_CS_IBO__MASK; 6344cc4c26d4SRob Clark } 6345c28c82e9SRob Clark 6346c28c82e9SRob Clark #define REG_A6XX_SP_CS_IBO_COUNT 0x0000aa00 6347c28c82e9SRob Clark 6348cc4c26d4SRob Clark #define REG_A6XX_SP_MODE_CONTROL 0x0000ab00 6349cc4c26d4SRob Clark #define A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE 0x00000001 6350*57cfe41cSRob Clark #define A6XX_SP_MODE_CONTROL_ISAMMODE__MASK 0x00000006 6351*57cfe41cSRob Clark #define A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT 1 6352*57cfe41cSRob Clark static inline uint32_t A6XX_SP_MODE_CONTROL_ISAMMODE(enum a6xx_isam_mode val) 6353*57cfe41cSRob Clark { 6354*57cfe41cSRob Clark return ((val) << A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT) & A6XX_SP_MODE_CONTROL_ISAMMODE__MASK; 6355*57cfe41cSRob Clark } 6356cc4c26d4SRob Clark #define A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE 0x00000008 63572d756322SRob Clark 63582d756322SRob Clark #define REG_A6XX_SP_FS_CONFIG 0x0000ab04 6359c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_BINDLESS_TEX 0x00000001 6360c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_BINDLESS_SAMP 0x00000002 6361c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_BINDLESS_IBO 0x00000004 6362c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_BINDLESS_UBO 0x00000008 63632d756322SRob Clark #define A6XX_SP_FS_CONFIG_ENABLED 0x00000100 63642d756322SRob Clark #define A6XX_SP_FS_CONFIG_NTEX__MASK 0x0001fe00 63652d756322SRob Clark #define A6XX_SP_FS_CONFIG_NTEX__SHIFT 9 63662d756322SRob Clark static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val) 63672d756322SRob Clark { 63682d756322SRob Clark return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK; 63692d756322SRob Clark } 6370c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_NSAMP__MASK 0x003e0000 63712d756322SRob Clark #define A6XX_SP_FS_CONFIG_NSAMP__SHIFT 17 63722d756322SRob Clark static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val) 63732d756322SRob Clark { 63742d756322SRob Clark return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK; 63752d756322SRob Clark } 6376cc4c26d4SRob Clark #define A6XX_SP_FS_CONFIG_NIBO__MASK 0x1fc00000 6377c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_NIBO__SHIFT 22 6378c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val) 6379c28c82e9SRob Clark { 6380c28c82e9SRob Clark return ((val) << A6XX_SP_FS_CONFIG_NIBO__SHIFT) & A6XX_SP_FS_CONFIG_NIBO__MASK; 6381c28c82e9SRob Clark } 63822d756322SRob Clark 63832d756322SRob Clark #define REG_A6XX_SP_FS_INSTRLEN 0x0000ab05 63842d756322SRob Clark 6385c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_BINDLESS_BASE(uint32_t i0) { return 0x0000ab10 + 0x2*i0; } 6386a69c5ed2SRob Clark 6387c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; } 6388c28c82e9SRob Clark 6389cc4c26d4SRob Clark #define REG_A6XX_SP_IBO 0x0000ab1a 6390cc4c26d4SRob Clark #define A6XX_SP_IBO__MASK 0xffffffff 6391cc4c26d4SRob Clark #define A6XX_SP_IBO__SHIFT 0 6392cc4c26d4SRob Clark static inline uint32_t A6XX_SP_IBO(uint32_t val) 6393cc4c26d4SRob Clark { 6394cc4c26d4SRob Clark return ((val) << A6XX_SP_IBO__SHIFT) & A6XX_SP_IBO__MASK; 6395cc4c26d4SRob Clark } 6396c28c82e9SRob Clark 6397c28c82e9SRob Clark #define REG_A6XX_SP_IBO_COUNT 0x0000ab20 6398c28c82e9SRob Clark 6399c28c82e9SRob Clark #define REG_A6XX_SP_2D_DST_FORMAT 0x0000acc0 6400c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_NORM 0x00000001 6401c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_SINT 0x00000002 6402c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_UINT 0x00000004 6403c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK 0x000007f8 6404c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT 3 6405c28c82e9SRob Clark static inline uint32_t A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val) 6406c28c82e9SRob Clark { 6407c28c82e9SRob Clark return ((val) << A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT) & A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK; 6408c28c82e9SRob Clark } 6409c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_SRGB 0x00000800 6410c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_MASK__MASK 0x0000f000 6411c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_MASK__SHIFT 12 6412c28c82e9SRob Clark static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val) 6413c28c82e9SRob Clark { 6414c28c82e9SRob Clark return ((val) << A6XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A6XX_SP_2D_DST_FORMAT_MASK__MASK; 6415c28c82e9SRob Clark } 6416ccdf7e28SRob Clark 64172d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_AE00 0x0000ae00 64182d756322SRob Clark 6419cc4c26d4SRob Clark #define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01 6420cc4c26d4SRob Clark 6421cc4c26d4SRob Clark #define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02 6422cc4c26d4SRob Clark 6423*57cfe41cSRob Clark #define REG_A6XX_SP_CHICKEN_BITS 0x0000ae03 6424a69c5ed2SRob Clark 6425cc4c26d4SRob Clark #define REG_A6XX_SP_FLOAT_CNTL 0x0000ae04 6426cc4c26d4SRob Clark #define A6XX_SP_FLOAT_CNTL_F16_NO_INF 0x00000008 64272d756322SRob Clark 6428cc4c26d4SRob Clark #define REG_A6XX_SP_PERFCTR_ENABLE 0x0000ae0f 6429cc4c26d4SRob Clark #define A6XX_SP_PERFCTR_ENABLE_VS 0x00000001 6430cc4c26d4SRob Clark #define A6XX_SP_PERFCTR_ENABLE_HS 0x00000002 6431cc4c26d4SRob Clark #define A6XX_SP_PERFCTR_ENABLE_DS 0x00000004 6432cc4c26d4SRob Clark #define A6XX_SP_PERFCTR_ENABLE_GS 0x00000008 6433cc4c26d4SRob Clark #define A6XX_SP_PERFCTR_ENABLE_FS 0x00000010 6434cc4c26d4SRob Clark #define A6XX_SP_PERFCTR_ENABLE_CS 0x00000020 6435cc4c26d4SRob Clark 6436cc4c26d4SRob Clark static inline uint32_t REG_A6XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae10 + 0x1*i0; } 64372d756322SRob Clark 6438*57cfe41cSRob Clark #define REG_A6XX_SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE 0x0000be22 6439*57cfe41cSRob Clark 6440c28c82e9SRob Clark #define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR 0x0000b180 6441cc4c26d4SRob Clark #define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff 6442cc4c26d4SRob Clark #define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0 6443cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(uint32_t val) 6444cc4c26d4SRob Clark { 6445cc4c26d4SRob Clark return ((val) << A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK; 6446cc4c26d4SRob Clark } 6447c28c82e9SRob Clark 64482d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_B182 0x0000b182 64492d756322SRob Clark 6450a69c5ed2SRob Clark #define REG_A6XX_SP_UNKNOWN_B183 0x0000b183 6451a69c5ed2SRob Clark 6452cc4c26d4SRob Clark #define REG_A6XX_SP_UNKNOWN_B190 0x0000b190 6453cc4c26d4SRob Clark 6454cc4c26d4SRob Clark #define REG_A6XX_SP_UNKNOWN_B191 0x0000b191 6455cc4c26d4SRob Clark 64562d756322SRob Clark #define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300 64572d756322SRob Clark #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 64582d756322SRob Clark #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 64592d756322SRob Clark static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 64602d756322SRob Clark { 64612d756322SRob Clark return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK; 64622d756322SRob Clark } 6463cc4c26d4SRob Clark #define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK 0x0000000c 6464cc4c26d4SRob Clark #define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT 2 6465cc4c26d4SRob Clark static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_UNK2(uint32_t val) 6466cc4c26d4SRob Clark { 6467cc4c26d4SRob Clark return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK; 6468cc4c26d4SRob Clark } 64692d756322SRob Clark 64702d756322SRob Clark #define REG_A6XX_SP_TP_DEST_MSAA_CNTL 0x0000b301 64712d756322SRob Clark #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 64722d756322SRob Clark #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 64732d756322SRob Clark static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 64742d756322SRob Clark { 64752d756322SRob Clark return ((val) << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK; 64762d756322SRob Clark } 64772d756322SRob Clark #define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 64782d756322SRob Clark 6479c28c82e9SRob Clark #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR 0x0000b302 6480cc4c26d4SRob Clark #define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff 6481cc4c26d4SRob Clark #define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0 6482cc4c26d4SRob Clark static inline uint32_t A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(uint32_t val) 6483cc4c26d4SRob Clark { 6484cc4c26d4SRob Clark return ((val) << A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK; 6485cc4c26d4SRob Clark } 64862d756322SRob Clark 6487c28c82e9SRob Clark #define REG_A6XX_SP_TP_SAMPLE_CONFIG 0x0000b304 6488c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_CONFIG_UNK0 0x00000001 6489c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002 6490c28c82e9SRob Clark 6491c28c82e9SRob Clark #define REG_A6XX_SP_TP_SAMPLE_LOCATION_0 0x0000b305 6492c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f 6493c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 6494c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) 6495c28c82e9SRob Clark { 6496c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; 6497c28c82e9SRob Clark } 6498c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 6499c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 6500c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) 6501c28c82e9SRob Clark { 6502c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; 6503c28c82e9SRob Clark } 6504c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 6505c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 6506c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) 6507c28c82e9SRob Clark { 6508c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; 6509c28c82e9SRob Clark } 6510c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 6511c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 6512c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) 6513c28c82e9SRob Clark { 6514c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; 6515c28c82e9SRob Clark } 6516c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 6517c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 6518c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) 6519c28c82e9SRob Clark { 6520c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; 6521c28c82e9SRob Clark } 6522c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 6523c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 6524c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) 6525c28c82e9SRob Clark { 6526c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; 6527c28c82e9SRob Clark } 6528c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 6529c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 6530c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) 6531c28c82e9SRob Clark { 6532c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; 6533c28c82e9SRob Clark } 6534c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 6535c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 6536c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) 6537c28c82e9SRob Clark { 6538c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; 6539c28c82e9SRob Clark } 6540c28c82e9SRob Clark 6541c28c82e9SRob Clark #define REG_A6XX_SP_TP_SAMPLE_LOCATION_1 0x0000b306 6542c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f 6543c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 6544c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) 6545c28c82e9SRob Clark { 6546c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; 6547c28c82e9SRob Clark } 6548c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 6549c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 6550c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) 6551c28c82e9SRob Clark { 6552c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; 6553c28c82e9SRob Clark } 6554c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 6555c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 6556c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) 6557c28c82e9SRob Clark { 6558c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; 6559c28c82e9SRob Clark } 6560c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 6561c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 6562c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) 6563c28c82e9SRob Clark { 6564c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; 6565c28c82e9SRob Clark } 6566c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 6567c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 6568c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) 6569c28c82e9SRob Clark { 6570c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; 6571c28c82e9SRob Clark } 6572c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 6573c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 6574c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) 6575c28c82e9SRob Clark { 6576c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; 6577c28c82e9SRob Clark } 6578c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 6579c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 6580c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) 6581c28c82e9SRob Clark { 6582c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; 6583c28c82e9SRob Clark } 6584c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 6585c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 6586c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) 6587c28c82e9SRob Clark { 6588c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; 6589c28c82e9SRob Clark } 65902d756322SRob Clark 6591cc4c26d4SRob Clark #define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307 6592cc4c26d4SRob Clark #define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00003fff 6593cc4c26d4SRob Clark #define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0 6594cc4c26d4SRob Clark static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val) 6595cc4c26d4SRob Clark { 6596cc4c26d4SRob Clark return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK; 6597cc4c26d4SRob Clark } 6598cc4c26d4SRob Clark #define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x3fff0000 6599cc4c26d4SRob Clark #define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16 6600cc4c26d4SRob Clark static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val) 6601cc4c26d4SRob Clark { 6602cc4c26d4SRob Clark return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK; 6603cc4c26d4SRob Clark } 6604cc4c26d4SRob Clark 6605*57cfe41cSRob Clark #define REG_A6XX_SP_TP_MODE_CNTL 0x0000b309 6606*57cfe41cSRob Clark #define A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK 0x00000003 6607*57cfe41cSRob Clark #define A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT 0 6608*57cfe41cSRob Clark static inline uint32_t A6XX_SP_TP_MODE_CNTL_ISAMMODE(enum a6xx_isam_mode val) 6609*57cfe41cSRob Clark { 6610*57cfe41cSRob Clark return ((val) << A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT) & A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK; 6611*57cfe41cSRob Clark } 6612*57cfe41cSRob Clark #define A6XX_SP_TP_MODE_CNTL_UNK3__MASK 0x000000fc 6613*57cfe41cSRob Clark #define A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT 2 6614*57cfe41cSRob Clark static inline uint32_t A6XX_SP_TP_MODE_CNTL_UNK3(uint32_t val) 6615*57cfe41cSRob Clark { 6616*57cfe41cSRob Clark return ((val) << A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT) & A6XX_SP_TP_MODE_CNTL_UNK3__MASK; 6617*57cfe41cSRob Clark } 6618a69c5ed2SRob Clark 66192d756322SRob Clark #define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0 66202d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff 66212d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 6622c28c82e9SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val) 66232d756322SRob Clark { 66242d756322SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK; 66252d756322SRob Clark } 66262d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300 66272d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT 8 66282d756322SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val) 66292d756322SRob Clark { 66302d756322SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK; 66312d756322SRob Clark } 66322d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00 66332d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10 66342d756322SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) 66352d756322SRob Clark { 66362d756322SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK; 66372d756322SRob Clark } 66382d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000 6639c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_SRGB 0x00002000 6640c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK 0x0000c000 6641c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT 14 6642c28c82e9SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val) 6643c28c82e9SRob Clark { 6644c28c82e9SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK; 6645c28c82e9SRob Clark } 6646ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000 6647cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK17 0x00020000 6648c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE 0x00040000 6649cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK19 0x00080000 6650c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK20 0x00100000 6651cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK21 0x00200000 6652c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK22 0x00400000 6653cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK 0x07800000 6654cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT 23 6655cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val) 6656cc4c26d4SRob Clark { 6657cc4c26d4SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK; 6658cc4c26d4SRob Clark } 6659cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK28 0x10000000 6660ccdf7e28SRob Clark 6661ccdf7e28SRob Clark #define REG_A6XX_SP_PS_2D_SRC_SIZE 0x0000b4c1 6662ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff 6663ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT 0 6664ccdf7e28SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val) 6665ccdf7e28SRob Clark { 6666ccdf7e28SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK; 6667ccdf7e28SRob Clark } 6668ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK 0x3fff8000 6669ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT 15 6670ccdf7e28SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val) 6671ccdf7e28SRob Clark { 6672ccdf7e28SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK; 6673ccdf7e28SRob Clark } 66742d756322SRob Clark 6675c28c82e9SRob Clark #define REG_A6XX_SP_PS_2D_SRC 0x0000b4c2 6676cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC__MASK 0xffffffff 6677cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC__SHIFT 0 6678cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC(uint32_t val) 6679cc4c26d4SRob Clark { 6680cc4c26d4SRob Clark return ((val) << A6XX_SP_PS_2D_SRC__SHIFT) & A6XX_SP_PS_2D_SRC__MASK; 6681cc4c26d4SRob Clark } 6682c28c82e9SRob Clark 6683ccdf7e28SRob Clark #define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4 6684cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK 0x000001ff 6685cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT 0 6686cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val) 6687cc4c26d4SRob Clark { 6688cc4c26d4SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK; 6689cc4c26d4SRob Clark } 6690cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x00fffe00 6691ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9 6692ccdf7e28SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val) 6693ccdf7e28SRob Clark { 6694ccdf7e28SRob Clark return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK; 6695ccdf7e28SRob Clark } 6696ccdf7e28SRob Clark 6697cc4c26d4SRob Clark #define REG_A6XX_SP_PS_2D_SRC_PLANE1 0x0000b4c5 6698cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PLANE1__MASK 0xffffffff 6699cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PLANE1__SHIFT 0 6700cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE1(uint32_t val) 6701cc4c26d4SRob Clark { 6702cc4c26d4SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_PLANE1__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE1__MASK; 6703cc4c26d4SRob Clark } 67042d756322SRob Clark 6705cc4c26d4SRob Clark #define REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH 0x0000b4c7 6706cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK 0x00000fff 6707cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT 0 6708cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val) 6709cc4c26d4SRob Clark { 6710cc4c26d4SRob Clark return ((val >> 6) << A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK; 6711cc4c26d4SRob Clark } 6712cc4c26d4SRob Clark 6713cc4c26d4SRob Clark #define REG_A6XX_SP_PS_2D_SRC_PLANE2 0x0000b4c8 6714cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PLANE2__MASK 0xffffffff 6715cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PLANE2__SHIFT 0 6716cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE2(uint32_t val) 6717cc4c26d4SRob Clark { 6718cc4c26d4SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_PLANE2__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE2__MASK; 6719cc4c26d4SRob Clark } 67202d756322SRob Clark 6721c28c82e9SRob Clark #define REG_A6XX_SP_PS_2D_SRC_FLAGS 0x0000b4ca 6722cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_FLAGS__MASK 0xffffffff 6723cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_FLAGS__SHIFT 0 6724cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS(uint32_t val) 6725cc4c26d4SRob Clark { 6726cc4c26d4SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_FLAGS__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS__MASK; 6727cc4c26d4SRob Clark } 6728c28c82e9SRob Clark 6729c28c82e9SRob Clark #define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b4cc 6730cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK 0x000000ff 6731cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT 0 6732cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val) 6733c28c82e9SRob Clark { 6734cc4c26d4SRob Clark return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK; 6735c28c82e9SRob Clark } 6736c28c82e9SRob Clark 6737cc4c26d4SRob Clark #define REG_A6XX_SP_PS_UNKNOWN_B4CD 0x0000b4cd 67382d756322SRob Clark 6739cc4c26d4SRob Clark #define REG_A6XX_SP_PS_UNKNOWN_B4CE 0x0000b4ce 6740cc4c26d4SRob Clark 6741cc4c26d4SRob Clark #define REG_A6XX_SP_PS_UNKNOWN_B4CF 0x0000b4cf 6742cc4c26d4SRob Clark 6743cc4c26d4SRob Clark #define REG_A6XX_SP_PS_UNKNOWN_B4D0 0x0000b4d0 6744cc4c26d4SRob Clark 6745cc4c26d4SRob Clark #define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1 6746cc4c26d4SRob Clark #define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00003fff 6747cc4c26d4SRob Clark #define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0 6748cc4c26d4SRob Clark static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val) 6749cc4c26d4SRob Clark { 6750cc4c26d4SRob Clark return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK; 6751cc4c26d4SRob Clark } 6752cc4c26d4SRob Clark #define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x3fff0000 6753cc4c26d4SRob Clark #define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16 6754cc4c26d4SRob Clark static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val) 6755cc4c26d4SRob Clark { 6756cc4c26d4SRob Clark return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK; 6757cc4c26d4SRob Clark } 6758cc4c26d4SRob Clark 6759*57cfe41cSRob Clark #define REG_A6XX_TPL1_DBG_ECO_CNTL 0x0000b600 6760cc4c26d4SRob Clark 6761cc4c26d4SRob Clark #define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601 6762cc4c26d4SRob Clark 6763cc4c26d4SRob Clark #define REG_A6XX_TPL1_UNKNOWN_B602 0x0000b602 6764cc4c26d4SRob Clark 6765cc4c26d4SRob Clark #define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604 6766cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_MODE 0x00000001 6767cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006 6768cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT 1 6769cc4c26d4SRob Clark static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT(uint32_t val) 6770cc4c26d4SRob Clark { 6771cc4c26d4SRob Clark return ((val) << A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK; 6772cc4c26d4SRob Clark } 6773cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008 6774cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000010 6775cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT 4 6776cc4c26d4SRob Clark static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT(uint32_t val) 6777cc4c26d4SRob Clark { 6778cc4c26d4SRob Clark return ((val) << A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK; 6779cc4c26d4SRob Clark } 6780cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK 0x000000c0 6781cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT 6 6782cc4c26d4SRob Clark static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UNK6(uint32_t val) 6783cc4c26d4SRob Clark { 6784cc4c26d4SRob Clark return ((val) << A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK; 6785cc4c26d4SRob Clark } 6786cc4c26d4SRob Clark 6787cc4c26d4SRob Clark #define REG_A6XX_TPL1_UNKNOWN_B605 0x0000b605 6788cc4c26d4SRob Clark 6789cc4c26d4SRob Clark #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608 6790cc4c26d4SRob Clark 6791cc4c26d4SRob Clark #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609 6792cc4c26d4SRob Clark 6793cc4c26d4SRob Clark #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a 6794cc4c26d4SRob Clark 6795cc4c26d4SRob Clark #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b 6796cc4c26d4SRob Clark 6797cc4c26d4SRob Clark #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c 6798cc4c26d4SRob Clark 6799cc4c26d4SRob Clark static inline uint32_t REG_A6XX_TPL1_PERFCTR_TP_SEL(uint32_t i0) { return 0x0000b610 + 0x1*i0; } 68002d756322SRob Clark 68012d756322SRob Clark #define REG_A6XX_HLSQ_VS_CNTL 0x0000b800 68022d756322SRob Clark #define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff 68032d756322SRob Clark #define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0 68042d756322SRob Clark static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val) 68052d756322SRob Clark { 68062d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK; 68072d756322SRob Clark } 6808c28c82e9SRob Clark #define A6XX_HLSQ_VS_CNTL_ENABLED 0x00000100 68092d756322SRob Clark 68102d756322SRob Clark #define REG_A6XX_HLSQ_HS_CNTL 0x0000b801 68112d756322SRob Clark #define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff 68122d756322SRob Clark #define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0 68132d756322SRob Clark static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val) 68142d756322SRob Clark { 68152d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK; 68162d756322SRob Clark } 6817c28c82e9SRob Clark #define A6XX_HLSQ_HS_CNTL_ENABLED 0x00000100 68182d756322SRob Clark 68192d756322SRob Clark #define REG_A6XX_HLSQ_DS_CNTL 0x0000b802 68202d756322SRob Clark #define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff 68212d756322SRob Clark #define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0 68222d756322SRob Clark static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val) 68232d756322SRob Clark { 68242d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK; 68252d756322SRob Clark } 6826c28c82e9SRob Clark #define A6XX_HLSQ_DS_CNTL_ENABLED 0x00000100 68272d756322SRob Clark 68282d756322SRob Clark #define REG_A6XX_HLSQ_GS_CNTL 0x0000b803 68292d756322SRob Clark #define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff 68302d756322SRob Clark #define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0 68312d756322SRob Clark static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val) 68322d756322SRob Clark { 68332d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK; 68342d756322SRob Clark } 6835c28c82e9SRob Clark #define A6XX_HLSQ_GS_CNTL_ENABLED 0x00000100 6836c28c82e9SRob Clark 6837c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD 0x0000b820 6838c28c82e9SRob Clark 6839c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR 0x0000b821 6840cc4c26d4SRob Clark #define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK 0xffffffff 6841cc4c26d4SRob Clark #define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT 0 6842cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR(uint32_t val) 6843cc4c26d4SRob Clark { 6844cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK; 6845cc4c26d4SRob Clark } 6846c28c82e9SRob Clark 6847c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA 0x0000b823 68482d756322SRob Clark 6849cc4c26d4SRob Clark #define REG_A6XX_HLSQ_FS_CNTL_0 0x0000b980 6850cc4c26d4SRob Clark #define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK 0x00000001 6851cc4c26d4SRob Clark #define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT 0 6852cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val) 6853cc4c26d4SRob Clark { 6854cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK; 6855cc4c26d4SRob Clark } 6856cc4c26d4SRob Clark #define A6XX_HLSQ_FS_CNTL_0_VARYINGS 0x00000002 6857cc4c26d4SRob Clark #define A6XX_HLSQ_FS_CNTL_0_UNK2__MASK 0x00000ffc 6858cc4c26d4SRob Clark #define A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT 2 6859cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val) 6860cc4c26d4SRob Clark { 6861cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A6XX_HLSQ_FS_CNTL_0_UNK2__MASK; 6862cc4c26d4SRob Clark } 6863cc4c26d4SRob Clark 6864cc4c26d4SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_B981 0x0000b981 6865a69c5ed2SRob Clark 68662d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982 68672d756322SRob Clark 68682d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_2_REG 0x0000b983 68692d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff 68702d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0 68712d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) 68722d756322SRob Clark { 68732d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; 68742d756322SRob Clark } 68752d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00 68762d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8 68772d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) 68782d756322SRob Clark { 68792d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK; 68802d756322SRob Clark } 68812d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000 68822d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16 68832d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) 68842d756322SRob Clark { 68852d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK; 68862d756322SRob Clark } 6887c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK 0xff000000 6888c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT 24 6889c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SIZE(uint32_t val) 6890c28c82e9SRob Clark { 6891c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK; 6892c28c82e9SRob Clark } 68932d756322SRob Clark 68942d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_3_REG 0x0000b984 6895c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff 6896c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0 6897c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val) 68982d756322SRob Clark { 6899c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK; 6900c28c82e9SRob Clark } 6901c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00 6902c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8 6903c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val) 6904c28c82e9SRob Clark { 6905c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK; 6906c28c82e9SRob Clark } 6907c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000 6908c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16 6909c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val) 6910c28c82e9SRob Clark { 6911c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK; 6912c28c82e9SRob Clark } 6913c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000 6914c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24 6915c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) 6916c28c82e9SRob Clark { 6917c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK; 69182d756322SRob Clark } 69192d756322SRob Clark 69202d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_4_REG 0x0000b985 6921c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff 6922c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0 6923c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val) 6924c28c82e9SRob Clark { 6925c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK; 6926c28c82e9SRob Clark } 6927c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00 6928c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8 6929c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val) 6930c28c82e9SRob Clark { 6931c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK; 6932c28c82e9SRob Clark } 69332d756322SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000 69342d756322SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16 69352d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) 69362d756322SRob Clark { 69372d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK; 69382d756322SRob Clark } 69392d756322SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000 69402d756322SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24 69412d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) 69422d756322SRob Clark { 69432d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; 69442d756322SRob Clark } 69452d756322SRob Clark 69462d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986 6947*57cfe41cSRob Clark #define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK 0x000000ff 6948*57cfe41cSRob Clark #define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT 0 6949*57cfe41cSRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val) 6950cc4c26d4SRob Clark { 6951*57cfe41cSRob Clark return ((val) << A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK; 6952cc4c26d4SRob Clark } 6953*57cfe41cSRob Clark #define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK 0x0000ff00 6954*57cfe41cSRob Clark #define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT 8 6955*57cfe41cSRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val) 6956cc4c26d4SRob Clark { 6957*57cfe41cSRob Clark return ((val) << A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK; 6958cc4c26d4SRob Clark } 69592d756322SRob Clark 6960c28c82e9SRob Clark #define REG_A6XX_HLSQ_CS_CNTL 0x0000b987 6961c28c82e9SRob Clark #define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff 6962c28c82e9SRob Clark #define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0 6963c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val) 6964c28c82e9SRob Clark { 6965c28c82e9SRob Clark return ((val >> 2) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK; 6966c28c82e9SRob Clark } 6967c28c82e9SRob Clark #define A6XX_HLSQ_CS_CNTL_ENABLED 0x00000100 6968c28c82e9SRob Clark 69692d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_0 0x0000b990 69702d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003 69712d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0 69722d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) 69732d756322SRob Clark { 69742d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK; 69752d756322SRob Clark } 69762d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc 69772d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2 69782d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) 69792d756322SRob Clark { 69802d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK; 69812d756322SRob Clark } 69822d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000 69832d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12 69842d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) 69852d756322SRob Clark { 69862d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK; 69872d756322SRob Clark } 69882d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000 69892d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22 69902d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) 69912d756322SRob Clark { 69922d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK; 69932d756322SRob Clark } 69942d756322SRob Clark 69952d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_1 0x0000b991 69962d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff 69972d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0 69982d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val) 69992d756322SRob Clark { 70002d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK; 70012d756322SRob Clark } 70022d756322SRob Clark 70032d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_2 0x0000b992 70042d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff 70052d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0 70062d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val) 70072d756322SRob Clark { 70082d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK; 70092d756322SRob Clark } 70102d756322SRob Clark 70112d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_3 0x0000b993 70122d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff 70132d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0 70142d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val) 70152d756322SRob Clark { 70162d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK; 70172d756322SRob Clark } 70182d756322SRob Clark 70192d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_4 0x0000b994 70202d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff 70212d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0 70222d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val) 70232d756322SRob Clark { 70242d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK; 70252d756322SRob Clark } 70262d756322SRob Clark 70272d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_5 0x0000b995 70282d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff 70292d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0 70302d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val) 70312d756322SRob Clark { 70322d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK; 70332d756322SRob Clark } 70342d756322SRob Clark 70352d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_6 0x0000b996 70362d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff 70372d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0 70382d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val) 70392d756322SRob Clark { 70402d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK; 70412d756322SRob Clark } 70422d756322SRob Clark 70432d756322SRob Clark #define REG_A6XX_HLSQ_CS_CNTL_0 0x0000b997 70442d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff 70452d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0 70462d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val) 70472d756322SRob Clark { 70482d756322SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK; 70492d756322SRob Clark } 7050cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK 0x0000ff00 7051cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT 8 7052cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(uint32_t val) 70532d756322SRob Clark { 7054cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK; 70552d756322SRob Clark } 7056cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK 0x00ff0000 7057cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT 16 7058cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val) 70592d756322SRob Clark { 7060cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK; 70612d756322SRob Clark } 70622d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000 70632d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24 70642d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) 70652d756322SRob Clark { 70662d756322SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK; 70672d756322SRob Clark } 70682d756322SRob Clark 7069cc4c26d4SRob Clark #define REG_A6XX_HLSQ_CS_CNTL_1 0x0000b998 7070cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff 7071cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0 7072cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) 7073cc4c26d4SRob Clark { 7074cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK; 7075cc4c26d4SRob Clark } 7076cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_1_SINGLE_SP_CORE 0x00000100 7077cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK 0x00000200 7078cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT 9 7079cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) 7080cc4c26d4SRob Clark { 7081cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK; 7082cc4c26d4SRob Clark } 7083cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400 7084c28c82e9SRob Clark 70852d756322SRob Clark #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X 0x0000b999 70862d756322SRob Clark 70872d756322SRob Clark #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000b99a 70882d756322SRob Clark 70892d756322SRob Clark #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000b99b 70902d756322SRob Clark 7091c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD 0x0000b9a0 7092c28c82e9SRob Clark 7093c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR 0x0000b9a1 7094cc4c26d4SRob Clark #define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK 0xffffffff 7095cc4c26d4SRob Clark #define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT 0 7096cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR(uint32_t val) 7097cc4c26d4SRob Clark { 7098cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK; 7099cc4c26d4SRob Clark } 7100c28c82e9SRob Clark 7101c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA 0x0000b9a3 7102c28c82e9SRob Clark 7103c28c82e9SRob Clark static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; } 7104c28c82e9SRob Clark 7105c28c82e9SRob Clark static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; } 7106c28c82e9SRob Clark 7107*57cfe41cSRob Clark #define REG_A6XX_HLSQ_CS_UNKNOWN_B9D0 0x0000b9d0 7108*57cfe41cSRob Clark #define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK 0x0000001f 7109*57cfe41cSRob Clark #define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT 0 7110*57cfe41cSRob Clark static inline uint32_t A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE(uint32_t val) 7111*57cfe41cSRob Clark { 7112*57cfe41cSRob Clark return ((val) << A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT) & A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK; 7113*57cfe41cSRob Clark } 7114*57cfe41cSRob Clark #define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK5 0x00000020 7115*57cfe41cSRob Clark #define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK6 0x00000040 7116*57cfe41cSRob Clark 7117c28c82e9SRob Clark #define REG_A6XX_HLSQ_DRAW_CMD 0x0000bb00 7118c28c82e9SRob Clark #define A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK 0x000000ff 7119c28c82e9SRob Clark #define A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT 0 7120c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_DRAW_CMD_STATE_ID(uint32_t val) 7121c28c82e9SRob Clark { 7122c28c82e9SRob Clark return ((val) << A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK; 7123c28c82e9SRob Clark } 7124c28c82e9SRob Clark 7125c28c82e9SRob Clark #define REG_A6XX_HLSQ_DISPATCH_CMD 0x0000bb01 7126c28c82e9SRob Clark #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK 0x000000ff 7127c28c82e9SRob Clark #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT 0 7128c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_DISPATCH_CMD_STATE_ID(uint32_t val) 7129c28c82e9SRob Clark { 7130c28c82e9SRob Clark return ((val) << A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK; 7131c28c82e9SRob Clark } 7132c28c82e9SRob Clark 7133c28c82e9SRob Clark #define REG_A6XX_HLSQ_EVENT_CMD 0x0000bb02 7134c28c82e9SRob Clark #define A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK 0x00ff0000 7135c28c82e9SRob Clark #define A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT 16 7136c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_EVENT_CMD_STATE_ID(uint32_t val) 7137c28c82e9SRob Clark { 7138c28c82e9SRob Clark return ((val) << A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK; 7139c28c82e9SRob Clark } 7140c28c82e9SRob Clark #define A6XX_HLSQ_EVENT_CMD_EVENT__MASK 0x0000007f 7141c28c82e9SRob Clark #define A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT 0 7142c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_EVENT_CMD_EVENT(enum vgt_event_type val) 7143c28c82e9SRob Clark { 7144c28c82e9SRob Clark return ((val) << A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_EVENT_CMD_EVENT__MASK; 7145c28c82e9SRob Clark } 7146c28c82e9SRob Clark 7147c28c82e9SRob Clark #define REG_A6XX_HLSQ_INVALIDATE_CMD 0x0000bb08 7148c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_VS_STATE 0x00000001 7149c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_HS_STATE 0x00000002 7150c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_DS_STATE 0x00000004 7151c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_GS_STATE 0x00000008 7152c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_FS_STATE 0x00000010 7153c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_CS_STATE 0x00000020 7154c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_CS_IBO 0x00000040 7155c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO 0x00000080 7156c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_CS_SHARED_CONST 0x00080000 7157c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_GFX_SHARED_CONST 0x00000100 7158c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK 0x00003e00 7159c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT 9 7160c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val) 7161c28c82e9SRob Clark { 7162c28c82e9SRob Clark return ((val) << A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK; 7163c28c82e9SRob Clark } 7164c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK 0x0007c000 7165c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT 14 7166c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val) 7167c28c82e9SRob Clark { 7168c28c82e9SRob Clark return ((val) << A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK; 7169c28c82e9SRob Clark } 71702d756322SRob Clark 71712d756322SRob Clark #define REG_A6XX_HLSQ_FS_CNTL 0x0000bb10 71722d756322SRob Clark #define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff 71732d756322SRob Clark #define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0 71742d756322SRob Clark static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val) 71752d756322SRob Clark { 71762d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK; 71772d756322SRob Clark } 7178c28c82e9SRob Clark #define A6XX_HLSQ_FS_CNTL_ENABLED 0x00000100 71792d756322SRob Clark 7180c28c82e9SRob Clark #define REG_A6XX_HLSQ_SHARED_CONSTS 0x0000bb11 7181c28c82e9SRob Clark #define A6XX_HLSQ_SHARED_CONSTS_ENABLE 0x00000001 7182c28c82e9SRob Clark 7183c28c82e9SRob Clark static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE(uint32_t i0) { return 0x0000bb20 + 0x2*i0; } 7184c28c82e9SRob Clark 7185c28c82e9SRob Clark static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000bb20 + 0x2*i0; } 7186c28c82e9SRob Clark 7187c28c82e9SRob Clark #define REG_A6XX_HLSQ_2D_EVENT_CMD 0x0000bd80 7188c28c82e9SRob Clark #define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00 7189c28c82e9SRob Clark #define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT 8 7190c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_STATE_ID(uint32_t val) 7191c28c82e9SRob Clark { 7192c28c82e9SRob Clark return ((val) << A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK; 7193c28c82e9SRob Clark } 7194c28c82e9SRob Clark #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK 0x0000007f 7195c28c82e9SRob Clark #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT 0 7196c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val) 7197c28c82e9SRob Clark { 7198c28c82e9SRob Clark return ((val) << A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK; 7199c28c82e9SRob Clark } 72002d756322SRob Clark 72012d756322SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_BE00 0x0000be00 72022d756322SRob Clark 72032d756322SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_BE01 0x0000be01 72042d756322SRob Clark 72052d756322SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_BE04 0x0000be04 72062d756322SRob Clark 7207cc4c26d4SRob Clark #define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05 7208cc4c26d4SRob Clark 7209cc4c26d4SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_BE08 0x0000be08 7210cc4c26d4SRob Clark 7211cc4c26d4SRob Clark static inline uint32_t REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000be10 + 0x1*i0; } 7212cc4c26d4SRob Clark 7213*57cfe41cSRob Clark #define REG_A6XX_HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE 0x0000be22 7214*57cfe41cSRob Clark 7215c28c82e9SRob Clark #define REG_A6XX_CP_EVENT_START 0x0000d600 7216c28c82e9SRob Clark #define A6XX_CP_EVENT_START_STATE_ID__MASK 0x000000ff 7217c28c82e9SRob Clark #define A6XX_CP_EVENT_START_STATE_ID__SHIFT 0 7218c28c82e9SRob Clark static inline uint32_t A6XX_CP_EVENT_START_STATE_ID(uint32_t val) 7219c28c82e9SRob Clark { 7220c28c82e9SRob Clark return ((val) << A6XX_CP_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_EVENT_START_STATE_ID__MASK; 7221c28c82e9SRob Clark } 7222c28c82e9SRob Clark 7223c28c82e9SRob Clark #define REG_A6XX_CP_EVENT_END 0x0000d601 7224c28c82e9SRob Clark #define A6XX_CP_EVENT_END_STATE_ID__MASK 0x000000ff 7225c28c82e9SRob Clark #define A6XX_CP_EVENT_END_STATE_ID__SHIFT 0 7226c28c82e9SRob Clark static inline uint32_t A6XX_CP_EVENT_END_STATE_ID(uint32_t val) 7227c28c82e9SRob Clark { 7228c28c82e9SRob Clark return ((val) << A6XX_CP_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_EVENT_END_STATE_ID__MASK; 7229c28c82e9SRob Clark } 7230c28c82e9SRob Clark 7231c28c82e9SRob Clark #define REG_A6XX_CP_2D_EVENT_START 0x0000d700 7232c28c82e9SRob Clark #define A6XX_CP_2D_EVENT_START_STATE_ID__MASK 0x000000ff 7233c28c82e9SRob Clark #define A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT 0 7234c28c82e9SRob Clark static inline uint32_t A6XX_CP_2D_EVENT_START_STATE_ID(uint32_t val) 7235c28c82e9SRob Clark { 7236c28c82e9SRob Clark return ((val) << A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_START_STATE_ID__MASK; 7237c28c82e9SRob Clark } 7238c28c82e9SRob Clark 7239c28c82e9SRob Clark #define REG_A6XX_CP_2D_EVENT_END 0x0000d701 7240c28c82e9SRob Clark #define A6XX_CP_2D_EVENT_END_STATE_ID__MASK 0x000000ff 7241c28c82e9SRob Clark #define A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT 0 7242c28c82e9SRob Clark static inline uint32_t A6XX_CP_2D_EVENT_END_STATE_ID(uint32_t val) 7243c28c82e9SRob Clark { 7244c28c82e9SRob Clark return ((val) << A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_END_STATE_ID__MASK; 7245c28c82e9SRob Clark } 7246c28c82e9SRob Clark 72472d756322SRob Clark #define REG_A6XX_TEX_SAMP_0 0x00000000 72482d756322SRob Clark #define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 72492d756322SRob Clark #define A6XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 72502d756322SRob Clark #define A6XX_TEX_SAMP_0_XY_MAG__SHIFT 1 72512d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val) 72522d756322SRob Clark { 72532d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_XY_MAG__SHIFT) & A6XX_TEX_SAMP_0_XY_MAG__MASK; 72542d756322SRob Clark } 72552d756322SRob Clark #define A6XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 72562d756322SRob Clark #define A6XX_TEX_SAMP_0_XY_MIN__SHIFT 3 72572d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val) 72582d756322SRob Clark { 72592d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_XY_MIN__SHIFT) & A6XX_TEX_SAMP_0_XY_MIN__MASK; 72602d756322SRob Clark } 72612d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 72622d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_S__SHIFT 5 72632d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val) 72642d756322SRob Clark { 72652d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_WRAP_S__SHIFT) & A6XX_TEX_SAMP_0_WRAP_S__MASK; 72662d756322SRob Clark } 72672d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 72682d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_T__SHIFT 8 72692d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val) 72702d756322SRob Clark { 72712d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_WRAP_T__SHIFT) & A6XX_TEX_SAMP_0_WRAP_T__MASK; 72722d756322SRob Clark } 72732d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 72742d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_R__SHIFT 11 72752d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val) 72762d756322SRob Clark { 72772d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_WRAP_R__SHIFT) & A6XX_TEX_SAMP_0_WRAP_R__MASK; 72782d756322SRob Clark } 72792d756322SRob Clark #define A6XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 72802d756322SRob Clark #define A6XX_TEX_SAMP_0_ANISO__SHIFT 14 72812d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val) 72822d756322SRob Clark { 72832d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_ANISO__SHIFT) & A6XX_TEX_SAMP_0_ANISO__MASK; 72842d756322SRob Clark } 72852d756322SRob Clark #define A6XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000 72862d756322SRob Clark #define A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19 72872d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val) 72882d756322SRob Clark { 72892d756322SRob Clark return ((((int32_t)(val * 256.0))) << A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A6XX_TEX_SAMP_0_LOD_BIAS__MASK; 72902d756322SRob Clark } 72912d756322SRob Clark 72922d756322SRob Clark #define REG_A6XX_TEX_SAMP_1 0x00000001 7293*57cfe41cSRob Clark #define A6XX_TEX_SAMP_1_CLAMPENABLE 0x00000001 72942d756322SRob Clark #define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e 72952d756322SRob Clark #define A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 72962d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) 72972d756322SRob Clark { 72982d756322SRob Clark return ((val) << A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK; 72992d756322SRob Clark } 73002d756322SRob Clark #define A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010 73012d756322SRob Clark #define A6XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 73022d756322SRob Clark #define A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 73032d756322SRob Clark #define A6XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 73042d756322SRob Clark #define A6XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 73052d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_1_MAX_LOD(float val) 73062d756322SRob Clark { 73072d756322SRob Clark return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK; 73082d756322SRob Clark } 73092d756322SRob Clark #define A6XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 73102d756322SRob Clark #define A6XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 73112d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_1_MIN_LOD(float val) 73122d756322SRob Clark { 73132d756322SRob Clark return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK; 73142d756322SRob Clark } 73152d756322SRob Clark 73162d756322SRob Clark #define REG_A6XX_TEX_SAMP_2 0x00000002 7317c28c82e9SRob Clark #define A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK 0x00000003 7318c28c82e9SRob Clark #define A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT 0 7319c28c82e9SRob Clark static inline uint32_t A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode val) 7320c28c82e9SRob Clark { 7321c28c82e9SRob Clark return ((val) << A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT) & A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK; 7322c28c82e9SRob Clark } 7323c28c82e9SRob Clark #define A6XX_TEX_SAMP_2_CHROMA_LINEAR 0x00000020 7324cc4c26d4SRob Clark #define A6XX_TEX_SAMP_2_BCOLOR__MASK 0xffffff80 7325cc4c26d4SRob Clark #define A6XX_TEX_SAMP_2_BCOLOR__SHIFT 7 7326cc4c26d4SRob Clark static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR(uint32_t val) 73272d756322SRob Clark { 7328cc4c26d4SRob Clark return ((val) << A6XX_TEX_SAMP_2_BCOLOR__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR__MASK; 73292d756322SRob Clark } 73302d756322SRob Clark 73312d756322SRob Clark #define REG_A6XX_TEX_SAMP_3 0x00000003 73322d756322SRob Clark 73332d756322SRob Clark #define REG_A6XX_TEX_CONST_0 0x00000000 73342d756322SRob Clark #define A6XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003 73352d756322SRob Clark #define A6XX_TEX_CONST_0_TILE_MODE__SHIFT 0 73362d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val) 73372d756322SRob Clark { 73382d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_TILE_MODE__SHIFT) & A6XX_TEX_CONST_0_TILE_MODE__MASK; 73392d756322SRob Clark } 73402d756322SRob Clark #define A6XX_TEX_CONST_0_SRGB 0x00000004 73412d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 73422d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_X__SHIFT 4 73432d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val) 73442d756322SRob Clark { 73452d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWIZ_X__SHIFT) & A6XX_TEX_CONST_0_SWIZ_X__MASK; 73462d756322SRob Clark } 73472d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 73482d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 73492d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val) 73502d756322SRob Clark { 73512d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Y__MASK; 73522d756322SRob Clark } 73532d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 73542d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 73552d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val) 73562d756322SRob Clark { 73572d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Z__MASK; 73582d756322SRob Clark } 73592d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 73602d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_W__SHIFT 13 73612d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val) 73622d756322SRob Clark { 73632d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWIZ_W__SHIFT) & A6XX_TEX_CONST_0_SWIZ_W__MASK; 73642d756322SRob Clark } 73652d756322SRob Clark #define A6XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 73662d756322SRob Clark #define A6XX_TEX_CONST_0_MIPLVLS__SHIFT 16 73672d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val) 73682d756322SRob Clark { 73692d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK; 73702d756322SRob Clark } 7371c28c82e9SRob Clark #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X 0x00010000 7372c28c82e9SRob Clark #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y 0x00040000 7373ccdf7e28SRob Clark #define A6XX_TEX_CONST_0_SAMPLES__MASK 0x00300000 7374ccdf7e28SRob Clark #define A6XX_TEX_CONST_0_SAMPLES__SHIFT 20 7375ccdf7e28SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val) 7376ccdf7e28SRob Clark { 7377ccdf7e28SRob Clark return ((val) << A6XX_TEX_CONST_0_SAMPLES__SHIFT) & A6XX_TEX_CONST_0_SAMPLES__MASK; 7378ccdf7e28SRob Clark } 73792d756322SRob Clark #define A6XX_TEX_CONST_0_FMT__MASK 0x3fc00000 73802d756322SRob Clark #define A6XX_TEX_CONST_0_FMT__SHIFT 22 7381c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_format val) 73822d756322SRob Clark { 73832d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK; 73842d756322SRob Clark } 73852d756322SRob Clark #define A6XX_TEX_CONST_0_SWAP__MASK 0xc0000000 73862d756322SRob Clark #define A6XX_TEX_CONST_0_SWAP__SHIFT 30 73872d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val) 73882d756322SRob Clark { 73892d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWAP__SHIFT) & A6XX_TEX_CONST_0_SWAP__MASK; 73902d756322SRob Clark } 73912d756322SRob Clark 73922d756322SRob Clark #define REG_A6XX_TEX_CONST_1 0x00000001 73932d756322SRob Clark #define A6XX_TEX_CONST_1_WIDTH__MASK 0x00007fff 73942d756322SRob Clark #define A6XX_TEX_CONST_1_WIDTH__SHIFT 0 73952d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_1_WIDTH(uint32_t val) 73962d756322SRob Clark { 73972d756322SRob Clark return ((val) << A6XX_TEX_CONST_1_WIDTH__SHIFT) & A6XX_TEX_CONST_1_WIDTH__MASK; 73982d756322SRob Clark } 73992d756322SRob Clark #define A6XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000 74002d756322SRob Clark #define A6XX_TEX_CONST_1_HEIGHT__SHIFT 15 74012d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val) 74022d756322SRob Clark { 74032d756322SRob Clark return ((val) << A6XX_TEX_CONST_1_HEIGHT__SHIFT) & A6XX_TEX_CONST_1_HEIGHT__MASK; 74042d756322SRob Clark } 74052d756322SRob Clark 74062d756322SRob Clark #define REG_A6XX_TEX_CONST_2 0x00000002 7407*57cfe41cSRob Clark #define A6XX_TEX_CONST_2_BUFFER 0x00000010 7408c28c82e9SRob Clark #define A6XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f 7409c28c82e9SRob Clark #define A6XX_TEX_CONST_2_PITCHALIGN__SHIFT 0 7410c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_2_PITCHALIGN(uint32_t val) 74112d756322SRob Clark { 7412c28c82e9SRob Clark return ((val) << A6XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A6XX_TEX_CONST_2_PITCHALIGN__MASK; 74132d756322SRob Clark } 74142d756322SRob Clark #define A6XX_TEX_CONST_2_PITCH__MASK 0x1fffff80 74152d756322SRob Clark #define A6XX_TEX_CONST_2_PITCH__SHIFT 7 74162d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_2_PITCH(uint32_t val) 74172d756322SRob Clark { 74182d756322SRob Clark return ((val) << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK; 74192d756322SRob Clark } 7420*57cfe41cSRob Clark #define A6XX_TEX_CONST_2_TYPE__MASK 0xe0000000 74212d756322SRob Clark #define A6XX_TEX_CONST_2_TYPE__SHIFT 29 74222d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val) 74232d756322SRob Clark { 74242d756322SRob Clark return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK; 74252d756322SRob Clark } 74262d756322SRob Clark 74272d756322SRob Clark #define REG_A6XX_TEX_CONST_3 0x00000003 74282d756322SRob Clark #define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff 74292d756322SRob Clark #define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0 74302d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) 74312d756322SRob Clark { 74322d756322SRob Clark return ((val >> 12) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK; 74332d756322SRob Clark } 7434c28c82e9SRob Clark #define A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000 7435c28c82e9SRob Clark #define A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23 7436c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val) 7437c28c82e9SRob Clark { 7438c28c82e9SRob Clark return ((val >> 12) << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK; 7439c28c82e9SRob Clark } 7440c28c82e9SRob Clark #define A6XX_TEX_CONST_3_TILE_ALL 0x08000000 74412d756322SRob Clark #define A6XX_TEX_CONST_3_FLAG 0x10000000 74422d756322SRob Clark 74432d756322SRob Clark #define REG_A6XX_TEX_CONST_4 0x00000004 74442d756322SRob Clark #define A6XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0 74452d756322SRob Clark #define A6XX_TEX_CONST_4_BASE_LO__SHIFT 5 74462d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val) 74472d756322SRob Clark { 74482d756322SRob Clark return ((val >> 5) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK; 74492d756322SRob Clark } 74502d756322SRob Clark 74512d756322SRob Clark #define REG_A6XX_TEX_CONST_5 0x00000005 74522d756322SRob Clark #define A6XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff 74532d756322SRob Clark #define A6XX_TEX_CONST_5_BASE_HI__SHIFT 0 74542d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_5_BASE_HI(uint32_t val) 74552d756322SRob Clark { 74562d756322SRob Clark return ((val) << A6XX_TEX_CONST_5_BASE_HI__SHIFT) & A6XX_TEX_CONST_5_BASE_HI__MASK; 74572d756322SRob Clark } 74582d756322SRob Clark #define A6XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000 74592d756322SRob Clark #define A6XX_TEX_CONST_5_DEPTH__SHIFT 17 74602d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_5_DEPTH(uint32_t val) 74612d756322SRob Clark { 74622d756322SRob Clark return ((val) << A6XX_TEX_CONST_5_DEPTH__SHIFT) & A6XX_TEX_CONST_5_DEPTH__MASK; 74632d756322SRob Clark } 74642d756322SRob Clark 74652d756322SRob Clark #define REG_A6XX_TEX_CONST_6 0x00000006 7466c28c82e9SRob Clark #define A6XX_TEX_CONST_6_PLANE_PITCH__MASK 0xffffff00 7467c28c82e9SRob Clark #define A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT 8 7468c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_6_PLANE_PITCH(uint32_t val) 7469c28c82e9SRob Clark { 7470c28c82e9SRob Clark return ((val) << A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT) & A6XX_TEX_CONST_6_PLANE_PITCH__MASK; 7471c28c82e9SRob Clark } 74722d756322SRob Clark 74732d756322SRob Clark #define REG_A6XX_TEX_CONST_7 0x00000007 74742d756322SRob Clark #define A6XX_TEX_CONST_7_FLAG_LO__MASK 0xffffffe0 74752d756322SRob Clark #define A6XX_TEX_CONST_7_FLAG_LO__SHIFT 5 74762d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val) 74772d756322SRob Clark { 74782d756322SRob Clark return ((val >> 5) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK; 74792d756322SRob Clark } 74802d756322SRob Clark 74812d756322SRob Clark #define REG_A6XX_TEX_CONST_8 0x00000008 7482a69c5ed2SRob Clark #define A6XX_TEX_CONST_8_FLAG_HI__MASK 0x0001ffff 7483a69c5ed2SRob Clark #define A6XX_TEX_CONST_8_FLAG_HI__SHIFT 0 7484a69c5ed2SRob Clark static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val) 74852d756322SRob Clark { 7486a69c5ed2SRob Clark return ((val) << A6XX_TEX_CONST_8_FLAG_HI__SHIFT) & A6XX_TEX_CONST_8_FLAG_HI__MASK; 74872d756322SRob Clark } 74882d756322SRob Clark 74892d756322SRob Clark #define REG_A6XX_TEX_CONST_9 0x00000009 7490c28c82e9SRob Clark #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff 7491c28c82e9SRob Clark #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0 7492c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) 7493c28c82e9SRob Clark { 7494c28c82e9SRob Clark return ((val >> 4) << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK; 7495c28c82e9SRob Clark } 74962d756322SRob Clark 74972d756322SRob Clark #define REG_A6XX_TEX_CONST_10 0x0000000a 7498c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK 0x0000007f 7499c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT 0 7500c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val) 7501c28c82e9SRob Clark { 7502c28c82e9SRob Clark return ((val >> 6) << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK; 7503c28c82e9SRob Clark } 7504c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK 0x00000f00 7505c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT 8 7506c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(uint32_t val) 7507c28c82e9SRob Clark { 7508c28c82e9SRob Clark return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK; 7509c28c82e9SRob Clark } 7510c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK 0x0000f000 7511c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT 12 7512c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(uint32_t val) 7513c28c82e9SRob Clark { 7514c28c82e9SRob Clark return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK; 7515c28c82e9SRob Clark } 75162d756322SRob Clark 75172d756322SRob Clark #define REG_A6XX_TEX_CONST_11 0x0000000b 75182d756322SRob Clark 75192d756322SRob Clark #define REG_A6XX_TEX_CONST_12 0x0000000c 75202d756322SRob Clark 75212d756322SRob Clark #define REG_A6XX_TEX_CONST_13 0x0000000d 75222d756322SRob Clark 75232d756322SRob Clark #define REG_A6XX_TEX_CONST_14 0x0000000e 75242d756322SRob Clark 75252d756322SRob Clark #define REG_A6XX_TEX_CONST_15 0x0000000f 75262d756322SRob Clark 7527c28c82e9SRob Clark #define REG_A6XX_UBO_0 0x00000000 7528c28c82e9SRob Clark #define A6XX_UBO_0_BASE_LO__MASK 0xffffffff 7529c28c82e9SRob Clark #define A6XX_UBO_0_BASE_LO__SHIFT 0 7530c28c82e9SRob Clark static inline uint32_t A6XX_UBO_0_BASE_LO(uint32_t val) 7531c28c82e9SRob Clark { 7532c28c82e9SRob Clark return ((val) << A6XX_UBO_0_BASE_LO__SHIFT) & A6XX_UBO_0_BASE_LO__MASK; 7533c28c82e9SRob Clark } 7534c28c82e9SRob Clark 7535c28c82e9SRob Clark #define REG_A6XX_UBO_1 0x00000001 7536c28c82e9SRob Clark #define A6XX_UBO_1_BASE_HI__MASK 0x0001ffff 7537c28c82e9SRob Clark #define A6XX_UBO_1_BASE_HI__SHIFT 0 7538c28c82e9SRob Clark static inline uint32_t A6XX_UBO_1_BASE_HI(uint32_t val) 7539c28c82e9SRob Clark { 7540c28c82e9SRob Clark return ((val) << A6XX_UBO_1_BASE_HI__SHIFT) & A6XX_UBO_1_BASE_HI__MASK; 7541c28c82e9SRob Clark } 7542c28c82e9SRob Clark #define A6XX_UBO_1_SIZE__MASK 0xfffe0000 7543c28c82e9SRob Clark #define A6XX_UBO_1_SIZE__SHIFT 17 7544c28c82e9SRob Clark static inline uint32_t A6XX_UBO_1_SIZE(uint32_t val) 7545c28c82e9SRob Clark { 7546c28c82e9SRob Clark return ((val) << A6XX_UBO_1_SIZE__SHIFT) & A6XX_UBO_1_SIZE__MASK; 7547c28c82e9SRob Clark } 7548c28c82e9SRob Clark 7549a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_ENABLE_PDC 0x00001140 7550a69c5ed2SRob Clark 7551a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_SEQ_START_ADDR 0x00001148 7552a69c5ed2SRob Clark 7553a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CONTROL 0x00001540 7554a69c5ed2SRob Clark 7555a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK 0x00001541 7556a69c5ed2SRob Clark 7557a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK 0x00001542 7558a69c5ed2SRob Clark 7559a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID 0x00001543 7560a69c5ed2SRob Clark 7561a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR 0x00001544 7562a69c5ed2SRob Clark 7563a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA 0x00001545 7564a69c5ed2SRob Clark 7565a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CONTROL 0x00001572 7566a69c5ed2SRob Clark 7567a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK 0x00001573 7568a69c5ed2SRob Clark 7569a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK 0x00001574 7570a69c5ed2SRob Clark 7571a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID 0x00001575 7572a69c5ed2SRob Clark 7573a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR 0x00001576 7574a69c5ed2SRob Clark 7575a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA 0x00001577 7576a69c5ed2SRob Clark 7577a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CONTROL 0x000015a4 7578a69c5ed2SRob Clark 7579a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK 0x000015a5 7580a69c5ed2SRob Clark 7581a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK 0x000015a6 7582a69c5ed2SRob Clark 7583a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID 0x000015a7 7584a69c5ed2SRob Clark 7585a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR 0x000015a8 7586a69c5ed2SRob Clark 7587a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA 0x000015a9 7588a69c5ed2SRob Clark 7589a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CONTROL 0x000015d6 7590a69c5ed2SRob Clark 7591a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK 0x000015d7 7592a69c5ed2SRob Clark 7593a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK 0x000015d8 7594a69c5ed2SRob Clark 7595a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID 0x000015d9 7596a69c5ed2SRob Clark 7597a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR 0x000015da 7598a69c5ed2SRob Clark 7599a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA 0x000015db 7600a69c5ed2SRob Clark 7601a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x00000000 7602a69c5ed2SRob Clark 7603a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A 0x00000000 7604a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK 0x000000ff 7605a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT 0 7606a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val) 7607a69c5ed2SRob Clark { 7608a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK; 7609a69c5ed2SRob Clark } 7610a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK 0x0000ff00 7611a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT 8 7612a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val) 7613a69c5ed2SRob Clark { 7614a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK; 7615a69c5ed2SRob Clark } 7616a69c5ed2SRob Clark 7617a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B 0x00000001 7618a69c5ed2SRob Clark 7619a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C 0x00000002 7620a69c5ed2SRob Clark 7621a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D 0x00000003 7622a69c5ed2SRob Clark 7623a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT 0x00000004 7624a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f 7625a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0 7626a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) 7627a69c5ed2SRob Clark { 7628a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; 7629a69c5ed2SRob Clark } 7630a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000 7631a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12 7632a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) 7633a69c5ed2SRob Clark { 7634a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; 7635a69c5ed2SRob Clark } 7636a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000 7637a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28 7638a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) 7639a69c5ed2SRob Clark { 7640a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; 7641a69c5ed2SRob Clark } 7642a69c5ed2SRob Clark 7643a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM 0x00000005 7644a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000 7645a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24 7646a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) 7647a69c5ed2SRob Clark { 7648a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; 7649a69c5ed2SRob Clark } 7650a69c5ed2SRob Clark 7651a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 0x00000008 7652a69c5ed2SRob Clark 7653a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 0x00000009 7654a69c5ed2SRob Clark 7655a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 0x0000000a 7656a69c5ed2SRob Clark 7657a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 0x0000000b 7658a69c5ed2SRob Clark 7659a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 0x0000000c 7660a69c5ed2SRob Clark 7661a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 0x0000000d 7662a69c5ed2SRob Clark 7663a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 0x0000000e 7664a69c5ed2SRob Clark 7665a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 0x0000000f 7666a69c5ed2SRob Clark 7667a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000010 7668a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f 7669a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0 7670a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) 7671a69c5ed2SRob Clark { 7672a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; 7673a69c5ed2SRob Clark } 7674a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0 7675a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4 7676a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) 7677a69c5ed2SRob Clark { 7678a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; 7679a69c5ed2SRob Clark } 7680a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00 7681a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8 7682a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) 7683a69c5ed2SRob Clark { 7684a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; 7685a69c5ed2SRob Clark } 7686a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000 7687a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12 7688a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) 7689a69c5ed2SRob Clark { 7690a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; 7691a69c5ed2SRob Clark } 7692a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000 7693a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16 7694a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) 7695a69c5ed2SRob Clark { 7696a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; 7697a69c5ed2SRob Clark } 7698a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000 7699a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20 7700a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) 7701a69c5ed2SRob Clark { 7702a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; 7703a69c5ed2SRob Clark } 7704a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000 7705a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24 7706a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) 7707a69c5ed2SRob Clark { 7708a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; 7709a69c5ed2SRob Clark } 7710a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000 7711a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28 7712a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) 7713a69c5ed2SRob Clark { 7714a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; 7715a69c5ed2SRob Clark } 7716a69c5ed2SRob Clark 7717a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000011 7718a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f 7719a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0 7720a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) 7721a69c5ed2SRob Clark { 7722a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; 7723a69c5ed2SRob Clark } 7724a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0 7725a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4 7726a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) 7727a69c5ed2SRob Clark { 7728a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; 7729a69c5ed2SRob Clark } 7730a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00 7731a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8 7732a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) 7733a69c5ed2SRob Clark { 7734a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; 7735a69c5ed2SRob Clark } 7736a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000 7737a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12 7738a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) 7739a69c5ed2SRob Clark { 7740a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; 7741a69c5ed2SRob Clark } 7742a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000 7743a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16 7744a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) 7745a69c5ed2SRob Clark { 7746a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; 7747a69c5ed2SRob Clark } 7748a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000 7749a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20 7750a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) 7751a69c5ed2SRob Clark { 7752a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; 7753a69c5ed2SRob Clark } 7754a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000 7755a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24 7756a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) 7757a69c5ed2SRob Clark { 7758a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; 7759a69c5ed2SRob Clark } 7760a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000 7761a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28 7762a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) 7763a69c5ed2SRob Clark { 7764a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; 7765a69c5ed2SRob Clark } 7766a69c5ed2SRob Clark 7767a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000002f 7768a69c5ed2SRob Clark 7769a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000030 7770a69c5ed2SRob Clark 7771ccdf7e28SRob Clark #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 0x00000001 7772ccdf7e28SRob Clark 7773ccdf7e28SRob Clark #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 0x00000002 7774ccdf7e28SRob Clark 77752d756322SRob Clark 77762d756322SRob Clark #endif /* A6XX_XML */ 7777