12d756322SRob Clark #ifndef A6XX_XML 22d756322SRob Clark #define A6XX_XML 32d756322SRob Clark 42d756322SRob Clark /* Autogenerated file, DO NOT EDIT manually! 52d756322SRob Clark 62d756322SRob Clark This file was generated by the rules-ng-ng headergen tool in this git repository: 72d756322SRob Clark http://github.com/freedreno/envytools/ 82d756322SRob Clark git clone https://github.com/freedreno/envytools.git 92d756322SRob Clark 102d756322SRob Clark The rules-ng-ng source files this header was generated from are: 1157cfe41cSRob Clark - /home/robclark/tmp/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-01-30 18:25:22) 1257cfe41cSRob Clark - /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2020-12-31 19:26:32) 1357cfe41cSRob Clark - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-06-21 15:24:24) 1457cfe41cSRob Clark - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14609 bytes, from 2021-11-24 23:05:10) 1557cfe41cSRob Clark - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 69086 bytes, from 2022-03-03 16:41:33) 1657cfe41cSRob Clark - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2021-11-24 23:05:10) 1757cfe41cSRob Clark - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113358 bytes, from 2022-01-31 23:06:21) 1857cfe41cSRob Clark - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149512 bytes, from 2022-01-31 23:06:21) 1957cfe41cSRob Clark - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx.xml ( 184954 bytes, from 2022-03-03 16:41:33) 2057cfe41cSRob Clark - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-07-22 15:21:56) 2157cfe41cSRob Clark - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-01-30 18:25:22) 2257cfe41cSRob Clark - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-07-22 15:21:56) 2357cfe41cSRob Clark - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-07-22 15:21:56) 242d756322SRob Clark 2557cfe41cSRob Clark Copyright (C) 2013-2022 by the following authors: 262d756322SRob Clark - Rob Clark <robdclark@gmail.com> (robclark) 272d756322SRob Clark - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 282d756322SRob Clark 292d756322SRob Clark Permission is hereby granted, free of charge, to any person obtaining 302d756322SRob Clark a copy of this software and associated documentation files (the 312d756322SRob Clark "Software"), to deal in the Software without restriction, including 322d756322SRob Clark without limitation the rights to use, copy, modify, merge, publish, 332d756322SRob Clark distribute, sublicense, and/or sell copies of the Software, and to 342d756322SRob Clark permit persons to whom the Software is furnished to do so, subject to 352d756322SRob Clark the following conditions: 362d756322SRob Clark 372d756322SRob Clark The above copyright notice and this permission notice (including the 382d756322SRob Clark next paragraph) shall be included in all copies or substantial 392d756322SRob Clark portions of the Software. 402d756322SRob Clark 412d756322SRob Clark THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 422d756322SRob Clark EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 432d756322SRob Clark MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 442d756322SRob Clark IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 452d756322SRob Clark LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 462d756322SRob Clark OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 472d756322SRob Clark WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 482d756322SRob Clark */ 492d756322SRob Clark 502d756322SRob Clark 512d756322SRob Clark enum a6xx_tile_mode { 522d756322SRob Clark TILE6_LINEAR = 0, 532d756322SRob Clark TILE6_2 = 2, 542d756322SRob Clark TILE6_3 = 3, 552d756322SRob Clark }; 562d756322SRob Clark 57c28c82e9SRob Clark enum a6xx_format { 58c28c82e9SRob Clark FMT6_A8_UNORM = 2, 59c28c82e9SRob Clark FMT6_8_UNORM = 3, 60c28c82e9SRob Clark FMT6_8_SNORM = 4, 61c28c82e9SRob Clark FMT6_8_UINT = 5, 62c28c82e9SRob Clark FMT6_8_SINT = 6, 63c28c82e9SRob Clark FMT6_4_4_4_4_UNORM = 8, 64c28c82e9SRob Clark FMT6_5_5_5_1_UNORM = 10, 65c28c82e9SRob Clark FMT6_1_5_5_5_UNORM = 12, 66c28c82e9SRob Clark FMT6_5_6_5_UNORM = 14, 67c28c82e9SRob Clark FMT6_8_8_UNORM = 15, 68c28c82e9SRob Clark FMT6_8_8_SNORM = 16, 69c28c82e9SRob Clark FMT6_8_8_UINT = 17, 70c28c82e9SRob Clark FMT6_8_8_SINT = 18, 71c28c82e9SRob Clark FMT6_L8_A8_UNORM = 19, 72c28c82e9SRob Clark FMT6_16_UNORM = 21, 73c28c82e9SRob Clark FMT6_16_SNORM = 22, 74c28c82e9SRob Clark FMT6_16_FLOAT = 23, 75c28c82e9SRob Clark FMT6_16_UINT = 24, 76c28c82e9SRob Clark FMT6_16_SINT = 25, 77c28c82e9SRob Clark FMT6_8_8_8_UNORM = 33, 78c28c82e9SRob Clark FMT6_8_8_8_SNORM = 34, 79c28c82e9SRob Clark FMT6_8_8_8_UINT = 35, 80c28c82e9SRob Clark FMT6_8_8_8_SINT = 36, 81c28c82e9SRob Clark FMT6_8_8_8_8_UNORM = 48, 82c28c82e9SRob Clark FMT6_8_8_8_X8_UNORM = 49, 83c28c82e9SRob Clark FMT6_8_8_8_8_SNORM = 50, 84c28c82e9SRob Clark FMT6_8_8_8_8_UINT = 51, 85c28c82e9SRob Clark FMT6_8_8_8_8_SINT = 52, 86c28c82e9SRob Clark FMT6_9_9_9_E5_FLOAT = 53, 87c28c82e9SRob Clark FMT6_10_10_10_2_UNORM = 54, 88c28c82e9SRob Clark FMT6_10_10_10_2_UNORM_DEST = 55, 89c28c82e9SRob Clark FMT6_10_10_10_2_SNORM = 57, 90c28c82e9SRob Clark FMT6_10_10_10_2_UINT = 58, 91c28c82e9SRob Clark FMT6_10_10_10_2_SINT = 59, 92c28c82e9SRob Clark FMT6_11_11_10_FLOAT = 66, 93c28c82e9SRob Clark FMT6_16_16_UNORM = 67, 94c28c82e9SRob Clark FMT6_16_16_SNORM = 68, 95c28c82e9SRob Clark FMT6_16_16_FLOAT = 69, 96c28c82e9SRob Clark FMT6_16_16_UINT = 70, 97c28c82e9SRob Clark FMT6_16_16_SINT = 71, 98c28c82e9SRob Clark FMT6_32_UNORM = 72, 99c28c82e9SRob Clark FMT6_32_SNORM = 73, 100c28c82e9SRob Clark FMT6_32_FLOAT = 74, 101c28c82e9SRob Clark FMT6_32_UINT = 75, 102c28c82e9SRob Clark FMT6_32_SINT = 76, 103c28c82e9SRob Clark FMT6_32_FIXED = 77, 104c28c82e9SRob Clark FMT6_16_16_16_UNORM = 88, 105c28c82e9SRob Clark FMT6_16_16_16_SNORM = 89, 106c28c82e9SRob Clark FMT6_16_16_16_FLOAT = 90, 107c28c82e9SRob Clark FMT6_16_16_16_UINT = 91, 108c28c82e9SRob Clark FMT6_16_16_16_SINT = 92, 109c28c82e9SRob Clark FMT6_16_16_16_16_UNORM = 96, 110c28c82e9SRob Clark FMT6_16_16_16_16_SNORM = 97, 111c28c82e9SRob Clark FMT6_16_16_16_16_FLOAT = 98, 112c28c82e9SRob Clark FMT6_16_16_16_16_UINT = 99, 113c28c82e9SRob Clark FMT6_16_16_16_16_SINT = 100, 114c28c82e9SRob Clark FMT6_32_32_UNORM = 101, 115c28c82e9SRob Clark FMT6_32_32_SNORM = 102, 116c28c82e9SRob Clark FMT6_32_32_FLOAT = 103, 117c28c82e9SRob Clark FMT6_32_32_UINT = 104, 118c28c82e9SRob Clark FMT6_32_32_SINT = 105, 119c28c82e9SRob Clark FMT6_32_32_FIXED = 106, 120c28c82e9SRob Clark FMT6_32_32_32_UNORM = 112, 121c28c82e9SRob Clark FMT6_32_32_32_SNORM = 113, 122c28c82e9SRob Clark FMT6_32_32_32_UINT = 114, 123c28c82e9SRob Clark FMT6_32_32_32_SINT = 115, 124c28c82e9SRob Clark FMT6_32_32_32_FLOAT = 116, 125c28c82e9SRob Clark FMT6_32_32_32_FIXED = 117, 126c28c82e9SRob Clark FMT6_32_32_32_32_UNORM = 128, 127c28c82e9SRob Clark FMT6_32_32_32_32_SNORM = 129, 128c28c82e9SRob Clark FMT6_32_32_32_32_FLOAT = 130, 129c28c82e9SRob Clark FMT6_32_32_32_32_UINT = 131, 130c28c82e9SRob Clark FMT6_32_32_32_32_SINT = 132, 131c28c82e9SRob Clark FMT6_32_32_32_32_FIXED = 133, 132c28c82e9SRob Clark FMT6_G8R8B8R8_422_UNORM = 140, 133c28c82e9SRob Clark FMT6_R8G8R8B8_422_UNORM = 141, 134c28c82e9SRob Clark FMT6_R8_G8B8_2PLANE_420_UNORM = 142, 13557cfe41cSRob Clark FMT6_NV21 = 143, 136c28c82e9SRob Clark FMT6_R8_G8_B8_3PLANE_420_UNORM = 144, 137c28c82e9SRob Clark FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 = 145, 13857cfe41cSRob Clark FMT6_NV12_Y = 148, 13957cfe41cSRob Clark FMT6_NV12_UV = 149, 14057cfe41cSRob Clark FMT6_NV12_VU = 150, 14157cfe41cSRob Clark FMT6_NV12_4R = 151, 14257cfe41cSRob Clark FMT6_NV12_4R_Y = 152, 14357cfe41cSRob Clark FMT6_NV12_4R_UV = 153, 14457cfe41cSRob Clark FMT6_P010 = 154, 14557cfe41cSRob Clark FMT6_P010_Y = 155, 14657cfe41cSRob Clark FMT6_P010_UV = 156, 14757cfe41cSRob Clark FMT6_TP10 = 157, 14857cfe41cSRob Clark FMT6_TP10_Y = 158, 14957cfe41cSRob Clark FMT6_TP10_UV = 159, 150c28c82e9SRob Clark FMT6_Z24_UNORM_S8_UINT = 160, 151c28c82e9SRob Clark FMT6_ETC2_RG11_UNORM = 171, 152c28c82e9SRob Clark FMT6_ETC2_RG11_SNORM = 172, 153c28c82e9SRob Clark FMT6_ETC2_R11_UNORM = 173, 154c28c82e9SRob Clark FMT6_ETC2_R11_SNORM = 174, 155c28c82e9SRob Clark FMT6_ETC1 = 175, 156c28c82e9SRob Clark FMT6_ETC2_RGB8 = 176, 157c28c82e9SRob Clark FMT6_ETC2_RGBA8 = 177, 158c28c82e9SRob Clark FMT6_ETC2_RGB8A1 = 178, 159c28c82e9SRob Clark FMT6_DXT1 = 179, 160c28c82e9SRob Clark FMT6_DXT3 = 180, 161c28c82e9SRob Clark FMT6_DXT5 = 181, 162c28c82e9SRob Clark FMT6_RGTC1_UNORM = 183, 163c28c82e9SRob Clark FMT6_RGTC1_SNORM = 184, 164c28c82e9SRob Clark FMT6_RGTC2_UNORM = 187, 165c28c82e9SRob Clark FMT6_RGTC2_SNORM = 188, 166c28c82e9SRob Clark FMT6_BPTC_UFLOAT = 190, 167c28c82e9SRob Clark FMT6_BPTC_FLOAT = 191, 168c28c82e9SRob Clark FMT6_BPTC = 192, 169c28c82e9SRob Clark FMT6_ASTC_4x4 = 193, 170c28c82e9SRob Clark FMT6_ASTC_5x4 = 194, 171c28c82e9SRob Clark FMT6_ASTC_5x5 = 195, 172c28c82e9SRob Clark FMT6_ASTC_6x5 = 196, 173c28c82e9SRob Clark FMT6_ASTC_6x6 = 197, 174c28c82e9SRob Clark FMT6_ASTC_8x5 = 198, 175c28c82e9SRob Clark FMT6_ASTC_8x6 = 199, 176c28c82e9SRob Clark FMT6_ASTC_8x8 = 200, 177c28c82e9SRob Clark FMT6_ASTC_10x5 = 201, 178c28c82e9SRob Clark FMT6_ASTC_10x6 = 202, 179c28c82e9SRob Clark FMT6_ASTC_10x8 = 203, 180c28c82e9SRob Clark FMT6_ASTC_10x10 = 204, 181c28c82e9SRob Clark FMT6_ASTC_12x10 = 205, 182c28c82e9SRob Clark FMT6_ASTC_12x12 = 206, 183cc4c26d4SRob Clark FMT6_Z24_UINT_S8_UINT = 234, 184c28c82e9SRob Clark FMT6_NONE = 255, 1852d756322SRob Clark }; 1862d756322SRob Clark 187c28c82e9SRob Clark enum a6xx_polygon_mode { 188c28c82e9SRob Clark POLYMODE6_POINTS = 1, 189c28c82e9SRob Clark POLYMODE6_LINES = 2, 190c28c82e9SRob Clark POLYMODE6_TRIANGLES = 3, 1912d756322SRob Clark }; 1922d756322SRob Clark 1932d756322SRob Clark enum a6xx_depth_format { 1942d756322SRob Clark DEPTH6_NONE = 0, 1952d756322SRob Clark DEPTH6_16 = 1, 1962d756322SRob Clark DEPTH6_24_8 = 2, 1972d756322SRob Clark DEPTH6_32 = 4, 1982d756322SRob Clark }; 1992d756322SRob Clark 200a69c5ed2SRob Clark enum a6xx_shader_id { 201a69c5ed2SRob Clark A6XX_TP0_TMO_DATA = 9, 202a69c5ed2SRob Clark A6XX_TP0_SMO_DATA = 10, 203a69c5ed2SRob Clark A6XX_TP0_MIPMAP_BASE_DATA = 11, 204a69c5ed2SRob Clark A6XX_TP1_TMO_DATA = 25, 205a69c5ed2SRob Clark A6XX_TP1_SMO_DATA = 26, 206a69c5ed2SRob Clark A6XX_TP1_MIPMAP_BASE_DATA = 27, 207a69c5ed2SRob Clark A6XX_SP_INST_DATA = 41, 208a69c5ed2SRob Clark A6XX_SP_LB_0_DATA = 42, 209a69c5ed2SRob Clark A6XX_SP_LB_1_DATA = 43, 210a69c5ed2SRob Clark A6XX_SP_LB_2_DATA = 44, 211a69c5ed2SRob Clark A6XX_SP_LB_3_DATA = 45, 212a69c5ed2SRob Clark A6XX_SP_LB_4_DATA = 46, 213a69c5ed2SRob Clark A6XX_SP_LB_5_DATA = 47, 214a69c5ed2SRob Clark A6XX_SP_CB_BINDLESS_DATA = 48, 215a69c5ed2SRob Clark A6XX_SP_CB_LEGACY_DATA = 49, 216a69c5ed2SRob Clark A6XX_SP_UAV_DATA = 50, 217a69c5ed2SRob Clark A6XX_SP_INST_TAG = 51, 218a69c5ed2SRob Clark A6XX_SP_CB_BINDLESS_TAG = 52, 219a69c5ed2SRob Clark A6XX_SP_TMO_UMO_TAG = 53, 220a69c5ed2SRob Clark A6XX_SP_SMO_TAG = 54, 221a69c5ed2SRob Clark A6XX_SP_STATE_DATA = 55, 222a69c5ed2SRob Clark A6XX_HLSQ_CHUNK_CVS_RAM = 73, 223a69c5ed2SRob Clark A6XX_HLSQ_CHUNK_CPS_RAM = 74, 224a69c5ed2SRob Clark A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75, 225a69c5ed2SRob Clark A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76, 226a69c5ed2SRob Clark A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77, 227a69c5ed2SRob Clark A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78, 228a69c5ed2SRob Clark A6XX_HLSQ_CVS_MISC_RAM = 80, 229a69c5ed2SRob Clark A6XX_HLSQ_CPS_MISC_RAM = 81, 230a69c5ed2SRob Clark A6XX_HLSQ_INST_RAM = 82, 231a69c5ed2SRob Clark A6XX_HLSQ_GFX_CVS_CONST_RAM = 83, 232a69c5ed2SRob Clark A6XX_HLSQ_GFX_CPS_CONST_RAM = 84, 233a69c5ed2SRob Clark A6XX_HLSQ_CVS_MISC_RAM_TAG = 85, 234a69c5ed2SRob Clark A6XX_HLSQ_CPS_MISC_RAM_TAG = 86, 235a69c5ed2SRob Clark A6XX_HLSQ_INST_RAM_TAG = 87, 236a69c5ed2SRob Clark A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88, 237a69c5ed2SRob Clark A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89, 238a69c5ed2SRob Clark A6XX_HLSQ_PWR_REST_RAM = 90, 239a69c5ed2SRob Clark A6XX_HLSQ_PWR_REST_TAG = 91, 240a69c5ed2SRob Clark A6XX_HLSQ_DATAPATH_META = 96, 241a69c5ed2SRob Clark A6XX_HLSQ_FRONTEND_META = 97, 242a69c5ed2SRob Clark A6XX_HLSQ_INDIRECT_META = 98, 243a69c5ed2SRob Clark A6XX_HLSQ_BACKEND_META = 99, 244a69c5ed2SRob Clark }; 245a69c5ed2SRob Clark 246a69c5ed2SRob Clark enum a6xx_debugbus_id { 247a69c5ed2SRob Clark A6XX_DBGBUS_CP = 1, 248a69c5ed2SRob Clark A6XX_DBGBUS_RBBM = 2, 249a69c5ed2SRob Clark A6XX_DBGBUS_VBIF = 3, 250a69c5ed2SRob Clark A6XX_DBGBUS_HLSQ = 4, 251a69c5ed2SRob Clark A6XX_DBGBUS_UCHE = 5, 252a69c5ed2SRob Clark A6XX_DBGBUS_DPM = 6, 253a69c5ed2SRob Clark A6XX_DBGBUS_TESS = 7, 254a69c5ed2SRob Clark A6XX_DBGBUS_PC = 8, 255a69c5ed2SRob Clark A6XX_DBGBUS_VFDP = 9, 256a69c5ed2SRob Clark A6XX_DBGBUS_VPC = 10, 257a69c5ed2SRob Clark A6XX_DBGBUS_TSE = 11, 258a69c5ed2SRob Clark A6XX_DBGBUS_RAS = 12, 259a69c5ed2SRob Clark A6XX_DBGBUS_VSC = 13, 260a69c5ed2SRob Clark A6XX_DBGBUS_COM = 14, 261a69c5ed2SRob Clark A6XX_DBGBUS_LRZ = 16, 262a69c5ed2SRob Clark A6XX_DBGBUS_A2D = 17, 263a69c5ed2SRob Clark A6XX_DBGBUS_CCUFCHE = 18, 264a69c5ed2SRob Clark A6XX_DBGBUS_GMU_CX = 19, 265a69c5ed2SRob Clark A6XX_DBGBUS_RBP = 20, 266a69c5ed2SRob Clark A6XX_DBGBUS_DCS = 21, 267a69c5ed2SRob Clark A6XX_DBGBUS_DBGC = 22, 268a69c5ed2SRob Clark A6XX_DBGBUS_CX = 23, 269a69c5ed2SRob Clark A6XX_DBGBUS_GMU_GX = 24, 270a69c5ed2SRob Clark A6XX_DBGBUS_TPFCHE = 25, 271a69c5ed2SRob Clark A6XX_DBGBUS_GBIF_GX = 26, 272a69c5ed2SRob Clark A6XX_DBGBUS_GPC = 29, 273a69c5ed2SRob Clark A6XX_DBGBUS_LARC = 30, 274a69c5ed2SRob Clark A6XX_DBGBUS_HLSQ_SPTP = 31, 275a69c5ed2SRob Clark A6XX_DBGBUS_RB_0 = 32, 276a69c5ed2SRob Clark A6XX_DBGBUS_RB_1 = 33, 277a69c5ed2SRob Clark A6XX_DBGBUS_UCHE_WRAPPER = 36, 278a69c5ed2SRob Clark A6XX_DBGBUS_CCU_0 = 40, 279a69c5ed2SRob Clark A6XX_DBGBUS_CCU_1 = 41, 280a69c5ed2SRob Clark A6XX_DBGBUS_VFD_0 = 56, 281a69c5ed2SRob Clark A6XX_DBGBUS_VFD_1 = 57, 282a69c5ed2SRob Clark A6XX_DBGBUS_VFD_2 = 58, 283a69c5ed2SRob Clark A6XX_DBGBUS_VFD_3 = 59, 284a69c5ed2SRob Clark A6XX_DBGBUS_SP_0 = 64, 285a69c5ed2SRob Clark A6XX_DBGBUS_SP_1 = 65, 286a69c5ed2SRob Clark A6XX_DBGBUS_TPL1_0 = 72, 287a69c5ed2SRob Clark A6XX_DBGBUS_TPL1_1 = 73, 288a69c5ed2SRob Clark A6XX_DBGBUS_TPL1_2 = 74, 289a69c5ed2SRob Clark A6XX_DBGBUS_TPL1_3 = 75, 290a69c5ed2SRob Clark }; 291a69c5ed2SRob Clark 2922d756322SRob Clark enum a6xx_cp_perfcounter_select { 2932d756322SRob Clark PERF_CP_ALWAYS_COUNT = 0, 294a69c5ed2SRob Clark PERF_CP_BUSY_GFX_CORE_IDLE = 1, 295a69c5ed2SRob Clark PERF_CP_BUSY_CYCLES = 2, 296a69c5ed2SRob Clark PERF_CP_NUM_PREEMPTIONS = 3, 297a69c5ed2SRob Clark PERF_CP_PREEMPTION_REACTION_DELAY = 4, 298a69c5ed2SRob Clark PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 5, 299a69c5ed2SRob Clark PERF_CP_PREEMPTION_SWITCH_IN_TIME = 6, 300a69c5ed2SRob Clark PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 7, 301a69c5ed2SRob Clark PERF_CP_PREDICATED_DRAWS_KILLED = 8, 302a69c5ed2SRob Clark PERF_CP_MODE_SWITCH = 9, 303a69c5ed2SRob Clark PERF_CP_ZPASS_DONE = 10, 304a69c5ed2SRob Clark PERF_CP_CONTEXT_DONE = 11, 305a69c5ed2SRob Clark PERF_CP_CACHE_FLUSH = 12, 306a69c5ed2SRob Clark PERF_CP_LONG_PREEMPTIONS = 13, 307a69c5ed2SRob Clark PERF_CP_SQE_I_CACHE_STARVE = 14, 308a69c5ed2SRob Clark PERF_CP_SQE_IDLE = 15, 309a69c5ed2SRob Clark PERF_CP_SQE_PM4_STARVE_RB_IB = 16, 310a69c5ed2SRob Clark PERF_CP_SQE_PM4_STARVE_SDS = 17, 311a69c5ed2SRob Clark PERF_CP_SQE_MRB_STARVE = 18, 312a69c5ed2SRob Clark PERF_CP_SQE_RRB_STARVE = 19, 313a69c5ed2SRob Clark PERF_CP_SQE_VSD_STARVE = 20, 314a69c5ed2SRob Clark PERF_CP_VSD_DECODE_STARVE = 21, 315a69c5ed2SRob Clark PERF_CP_SQE_PIPE_OUT_STALL = 22, 316a69c5ed2SRob Clark PERF_CP_SQE_SYNC_STALL = 23, 317a69c5ed2SRob Clark PERF_CP_SQE_PM4_WFI_STALL = 24, 318a69c5ed2SRob Clark PERF_CP_SQE_SYS_WFI_STALL = 25, 319a69c5ed2SRob Clark PERF_CP_SQE_T4_EXEC = 26, 320a69c5ed2SRob Clark PERF_CP_SQE_LOAD_STATE_EXEC = 27, 321a69c5ed2SRob Clark PERF_CP_SQE_SAVE_SDS_STATE = 28, 322a69c5ed2SRob Clark PERF_CP_SQE_DRAW_EXEC = 29, 323a69c5ed2SRob Clark PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 30, 324a69c5ed2SRob Clark PERF_CP_SQE_EXEC_PROFILED = 31, 325a69c5ed2SRob Clark PERF_CP_MEMORY_POOL_EMPTY = 32, 326a69c5ed2SRob Clark PERF_CP_MEMORY_POOL_SYNC_STALL = 33, 327a69c5ed2SRob Clark PERF_CP_MEMORY_POOL_ABOVE_THRESH = 34, 328a69c5ed2SRob Clark PERF_CP_AHB_WR_STALL_PRE_DRAWS = 35, 329a69c5ed2SRob Clark PERF_CP_AHB_STALL_SQE_GMU = 36, 330a69c5ed2SRob Clark PERF_CP_AHB_STALL_SQE_WR_OTHER = 37, 331a69c5ed2SRob Clark PERF_CP_AHB_STALL_SQE_RD_OTHER = 38, 332a69c5ed2SRob Clark PERF_CP_CLUSTER0_EMPTY = 39, 333a69c5ed2SRob Clark PERF_CP_CLUSTER1_EMPTY = 40, 334a69c5ed2SRob Clark PERF_CP_CLUSTER2_EMPTY = 41, 335a69c5ed2SRob Clark PERF_CP_CLUSTER3_EMPTY = 42, 336a69c5ed2SRob Clark PERF_CP_CLUSTER4_EMPTY = 43, 337a69c5ed2SRob Clark PERF_CP_CLUSTER5_EMPTY = 44, 338a69c5ed2SRob Clark PERF_CP_PM4_DATA = 45, 339a69c5ed2SRob Clark PERF_CP_PM4_HEADERS = 46, 340a69c5ed2SRob Clark PERF_CP_VBIF_READ_BEATS = 47, 341a69c5ed2SRob Clark PERF_CP_VBIF_WRITE_BEATS = 48, 342a69c5ed2SRob Clark PERF_CP_SQE_INSTR_COUNTER = 49, 343a69c5ed2SRob Clark }; 344a69c5ed2SRob Clark 345a69c5ed2SRob Clark enum a6xx_rbbm_perfcounter_select { 346a69c5ed2SRob Clark PERF_RBBM_ALWAYS_COUNT = 0, 347a69c5ed2SRob Clark PERF_RBBM_ALWAYS_ON = 1, 348a69c5ed2SRob Clark PERF_RBBM_TSE_BUSY = 2, 349a69c5ed2SRob Clark PERF_RBBM_RAS_BUSY = 3, 350a69c5ed2SRob Clark PERF_RBBM_PC_DCALL_BUSY = 4, 351a69c5ed2SRob Clark PERF_RBBM_PC_VSD_BUSY = 5, 352a69c5ed2SRob Clark PERF_RBBM_STATUS_MASKED = 6, 353a69c5ed2SRob Clark PERF_RBBM_COM_BUSY = 7, 354a69c5ed2SRob Clark PERF_RBBM_DCOM_BUSY = 8, 355a69c5ed2SRob Clark PERF_RBBM_VBIF_BUSY = 9, 356a69c5ed2SRob Clark PERF_RBBM_VSC_BUSY = 10, 357a69c5ed2SRob Clark PERF_RBBM_TESS_BUSY = 11, 358a69c5ed2SRob Clark PERF_RBBM_UCHE_BUSY = 12, 359a69c5ed2SRob Clark PERF_RBBM_HLSQ_BUSY = 13, 360a69c5ed2SRob Clark }; 361a69c5ed2SRob Clark 362a69c5ed2SRob Clark enum a6xx_pc_perfcounter_select { 363a69c5ed2SRob Clark PERF_PC_BUSY_CYCLES = 0, 364a69c5ed2SRob Clark PERF_PC_WORKING_CYCLES = 1, 365a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_VFD = 2, 366a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_TSE = 3, 367a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_VPC = 4, 368a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_UCHE = 5, 369a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_TESS = 6, 370a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_TSE_ONLY = 7, 371a69c5ed2SRob Clark PERF_PC_STALL_CYCLES_VPC_ONLY = 8, 372a69c5ed2SRob Clark PERF_PC_PASS1_TF_STALL_CYCLES = 9, 373a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_FOR_INDEX = 10, 374a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11, 375a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12, 376a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_FOR_POSITION = 13, 377a69c5ed2SRob Clark PERF_PC_STARVE_CYCLES_DI = 14, 378a69c5ed2SRob Clark PERF_PC_VIS_STREAMS_LOADED = 15, 379a69c5ed2SRob Clark PERF_PC_INSTANCES = 16, 380a69c5ed2SRob Clark PERF_PC_VPC_PRIMITIVES = 17, 381a69c5ed2SRob Clark PERF_PC_DEAD_PRIM = 18, 382a69c5ed2SRob Clark PERF_PC_LIVE_PRIM = 19, 383a69c5ed2SRob Clark PERF_PC_VERTEX_HITS = 20, 384a69c5ed2SRob Clark PERF_PC_IA_VERTICES = 21, 385a69c5ed2SRob Clark PERF_PC_IA_PRIMITIVES = 22, 386a69c5ed2SRob Clark PERF_PC_GS_PRIMITIVES = 23, 387a69c5ed2SRob Clark PERF_PC_HS_INVOCATIONS = 24, 388a69c5ed2SRob Clark PERF_PC_DS_INVOCATIONS = 25, 389a69c5ed2SRob Clark PERF_PC_VS_INVOCATIONS = 26, 390a69c5ed2SRob Clark PERF_PC_GS_INVOCATIONS = 27, 391a69c5ed2SRob Clark PERF_PC_DS_PRIMITIVES = 28, 392a69c5ed2SRob Clark PERF_PC_VPC_POS_DATA_TRANSACTION = 29, 393a69c5ed2SRob Clark PERF_PC_3D_DRAWCALLS = 30, 394a69c5ed2SRob Clark PERF_PC_2D_DRAWCALLS = 31, 395a69c5ed2SRob Clark PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32, 396a69c5ed2SRob Clark PERF_TESS_BUSY_CYCLES = 33, 397a69c5ed2SRob Clark PERF_TESS_WORKING_CYCLES = 34, 398a69c5ed2SRob Clark PERF_TESS_STALL_CYCLES_PC = 35, 399a69c5ed2SRob Clark PERF_TESS_STARVE_CYCLES_PC = 36, 400a69c5ed2SRob Clark PERF_PC_TSE_TRANSACTION = 37, 401a69c5ed2SRob Clark PERF_PC_TSE_VERTEX = 38, 402a69c5ed2SRob Clark PERF_PC_TESS_PC_UV_TRANS = 39, 403a69c5ed2SRob Clark PERF_PC_TESS_PC_UV_PATCHES = 40, 404a69c5ed2SRob Clark PERF_PC_TESS_FACTOR_TRANS = 41, 405a69c5ed2SRob Clark }; 406a69c5ed2SRob Clark 407a69c5ed2SRob Clark enum a6xx_vfd_perfcounter_select { 408a69c5ed2SRob Clark PERF_VFD_BUSY_CYCLES = 0, 409a69c5ed2SRob Clark PERF_VFD_STALL_CYCLES_UCHE = 1, 410a69c5ed2SRob Clark PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2, 411a69c5ed2SRob Clark PERF_VFD_STALL_CYCLES_SP_INFO = 3, 412a69c5ed2SRob Clark PERF_VFD_STALL_CYCLES_SP_ATTR = 4, 413a69c5ed2SRob Clark PERF_VFD_STARVE_CYCLES_UCHE = 5, 414a69c5ed2SRob Clark PERF_VFD_RBUFFER_FULL = 6, 415a69c5ed2SRob Clark PERF_VFD_ATTR_INFO_FIFO_FULL = 7, 416a69c5ed2SRob Clark PERF_VFD_DECODED_ATTRIBUTE_BYTES = 8, 417a69c5ed2SRob Clark PERF_VFD_NUM_ATTRIBUTES = 9, 418a69c5ed2SRob Clark PERF_VFD_UPPER_SHADER_FIBERS = 10, 419a69c5ed2SRob Clark PERF_VFD_LOWER_SHADER_FIBERS = 11, 420a69c5ed2SRob Clark PERF_VFD_MODE_0_FIBERS = 12, 421a69c5ed2SRob Clark PERF_VFD_MODE_1_FIBERS = 13, 422a69c5ed2SRob Clark PERF_VFD_MODE_2_FIBERS = 14, 423a69c5ed2SRob Clark PERF_VFD_MODE_3_FIBERS = 15, 424a69c5ed2SRob Clark PERF_VFD_MODE_4_FIBERS = 16, 425a69c5ed2SRob Clark PERF_VFD_TOTAL_VERTICES = 17, 426a69c5ed2SRob Clark PERF_VFDP_STALL_CYCLES_VFD = 18, 427a69c5ed2SRob Clark PERF_VFDP_STALL_CYCLES_VFD_INDEX = 19, 428a69c5ed2SRob Clark PERF_VFDP_STALL_CYCLES_VFD_PROG = 20, 429a69c5ed2SRob Clark PERF_VFDP_STARVE_CYCLES_PC = 21, 430a69c5ed2SRob Clark PERF_VFDP_VS_STAGE_WAVES = 22, 431a69c5ed2SRob Clark }; 432a69c5ed2SRob Clark 433ccdf7e28SRob Clark enum a6xx_hlsq_perfcounter_select { 434a69c5ed2SRob Clark PERF_HLSQ_BUSY_CYCLES = 0, 435a69c5ed2SRob Clark PERF_HLSQ_STALL_CYCLES_UCHE = 1, 436a69c5ed2SRob Clark PERF_HLSQ_STALL_CYCLES_SP_STATE = 2, 437a69c5ed2SRob Clark PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3, 438a69c5ed2SRob Clark PERF_HLSQ_UCHE_LATENCY_CYCLES = 4, 439a69c5ed2SRob Clark PERF_HLSQ_UCHE_LATENCY_COUNT = 5, 440a69c5ed2SRob Clark PERF_HLSQ_FS_STAGE_1X_WAVES = 6, 441a69c5ed2SRob Clark PERF_HLSQ_FS_STAGE_2X_WAVES = 7, 442a69c5ed2SRob Clark PERF_HLSQ_QUADS = 8, 443a69c5ed2SRob Clark PERF_HLSQ_CS_INVOCATIONS = 9, 444a69c5ed2SRob Clark PERF_HLSQ_COMPUTE_DRAWCALLS = 10, 445a69c5ed2SRob Clark PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11, 446a69c5ed2SRob Clark PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12, 447a69c5ed2SRob Clark PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13, 448a69c5ed2SRob Clark PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14, 449a69c5ed2SRob Clark PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15, 450a69c5ed2SRob Clark PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16, 451a69c5ed2SRob Clark PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17, 452a69c5ed2SRob Clark PERF_HLSQ_STALL_CYCLES_VPC = 18, 453a69c5ed2SRob Clark PERF_HLSQ_PIXELS = 19, 454a69c5ed2SRob Clark PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = 20, 455a69c5ed2SRob Clark }; 456a69c5ed2SRob Clark 457a69c5ed2SRob Clark enum a6xx_vpc_perfcounter_select { 458a69c5ed2SRob Clark PERF_VPC_BUSY_CYCLES = 0, 459a69c5ed2SRob Clark PERF_VPC_WORKING_CYCLES = 1, 460a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_UCHE = 2, 461a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_VFD_WACK = 3, 462a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4, 463a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_PC = 5, 464a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_SP_LM = 6, 465a69c5ed2SRob Clark PERF_VPC_STARVE_CYCLES_SP = 7, 466a69c5ed2SRob Clark PERF_VPC_STARVE_CYCLES_LRZ = 8, 467a69c5ed2SRob Clark PERF_VPC_PC_PRIMITIVES = 9, 468a69c5ed2SRob Clark PERF_VPC_SP_COMPONENTS = 10, 469a69c5ed2SRob Clark PERF_VPC_STALL_CYCLES_VPCRAM_POS = 11, 470a69c5ed2SRob Clark PERF_VPC_LRZ_ASSIGN_PRIMITIVES = 12, 471a69c5ed2SRob Clark PERF_VPC_RB_VISIBLE_PRIMITIVES = 13, 472a69c5ed2SRob Clark PERF_VPC_LM_TRANSACTION = 14, 473a69c5ed2SRob Clark PERF_VPC_STREAMOUT_TRANSACTION = 15, 474a69c5ed2SRob Clark PERF_VPC_VS_BUSY_CYCLES = 16, 475a69c5ed2SRob Clark PERF_VPC_PS_BUSY_CYCLES = 17, 476a69c5ed2SRob Clark PERF_VPC_VS_WORKING_CYCLES = 18, 477a69c5ed2SRob Clark PERF_VPC_PS_WORKING_CYCLES = 19, 478a69c5ed2SRob Clark PERF_VPC_STARVE_CYCLES_RB = 20, 479a69c5ed2SRob Clark PERF_VPC_NUM_VPCRAM_READ_POS = 21, 480a69c5ed2SRob Clark PERF_VPC_WIT_FULL_CYCLES = 22, 481a69c5ed2SRob Clark PERF_VPC_VPCRAM_FULL_CYCLES = 23, 482a69c5ed2SRob Clark PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = 24, 483a69c5ed2SRob Clark PERF_VPC_NUM_VPCRAM_WRITE = 25, 484a69c5ed2SRob Clark PERF_VPC_NUM_VPCRAM_READ_SO = 26, 485a69c5ed2SRob Clark PERF_VPC_NUM_ATTR_REQ_LM = 27, 486a69c5ed2SRob Clark }; 487a69c5ed2SRob Clark 488a69c5ed2SRob Clark enum a6xx_tse_perfcounter_select { 489a69c5ed2SRob Clark PERF_TSE_BUSY_CYCLES = 0, 490a69c5ed2SRob Clark PERF_TSE_CLIPPING_CYCLES = 1, 491a69c5ed2SRob Clark PERF_TSE_STALL_CYCLES_RAS = 2, 492a69c5ed2SRob Clark PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3, 493a69c5ed2SRob Clark PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4, 494a69c5ed2SRob Clark PERF_TSE_STARVE_CYCLES_PC = 5, 495a69c5ed2SRob Clark PERF_TSE_INPUT_PRIM = 6, 496a69c5ed2SRob Clark PERF_TSE_INPUT_NULL_PRIM = 7, 497a69c5ed2SRob Clark PERF_TSE_TRIVAL_REJ_PRIM = 8, 498a69c5ed2SRob Clark PERF_TSE_CLIPPED_PRIM = 9, 499a69c5ed2SRob Clark PERF_TSE_ZERO_AREA_PRIM = 10, 500a69c5ed2SRob Clark PERF_TSE_FACENESS_CULLED_PRIM = 11, 501a69c5ed2SRob Clark PERF_TSE_ZERO_PIXEL_PRIM = 12, 502a69c5ed2SRob Clark PERF_TSE_OUTPUT_NULL_PRIM = 13, 503a69c5ed2SRob Clark PERF_TSE_OUTPUT_VISIBLE_PRIM = 14, 504a69c5ed2SRob Clark PERF_TSE_CINVOCATION = 15, 505a69c5ed2SRob Clark PERF_TSE_CPRIMITIVES = 16, 506a69c5ed2SRob Clark PERF_TSE_2D_INPUT_PRIM = 17, 507a69c5ed2SRob Clark PERF_TSE_2D_ALIVE_CYCLES = 18, 508a69c5ed2SRob Clark PERF_TSE_CLIP_PLANES = 19, 509a69c5ed2SRob Clark }; 510a69c5ed2SRob Clark 511a69c5ed2SRob Clark enum a6xx_ras_perfcounter_select { 512a69c5ed2SRob Clark PERF_RAS_BUSY_CYCLES = 0, 513a69c5ed2SRob Clark PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1, 514a69c5ed2SRob Clark PERF_RAS_STALL_CYCLES_LRZ = 2, 515a69c5ed2SRob Clark PERF_RAS_STARVE_CYCLES_TSE = 3, 516a69c5ed2SRob Clark PERF_RAS_SUPER_TILES = 4, 517a69c5ed2SRob Clark PERF_RAS_8X4_TILES = 5, 518a69c5ed2SRob Clark PERF_RAS_MASKGEN_ACTIVE = 6, 519a69c5ed2SRob Clark PERF_RAS_FULLY_COVERED_SUPER_TILES = 7, 520a69c5ed2SRob Clark PERF_RAS_FULLY_COVERED_8X4_TILES = 8, 521a69c5ed2SRob Clark PERF_RAS_PRIM_KILLED_INVISILBE = 9, 522a69c5ed2SRob Clark PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 10, 523a69c5ed2SRob Clark PERF_RAS_LRZ_INTF_WORKING_CYCLES = 11, 524a69c5ed2SRob Clark PERF_RAS_BLOCKS = 12, 525a69c5ed2SRob Clark }; 526a69c5ed2SRob Clark 527a69c5ed2SRob Clark enum a6xx_uche_perfcounter_select { 528a69c5ed2SRob Clark PERF_UCHE_BUSY_CYCLES = 0, 529a69c5ed2SRob Clark PERF_UCHE_STALL_CYCLES_ARBITER = 1, 530a69c5ed2SRob Clark PERF_UCHE_VBIF_LATENCY_CYCLES = 2, 531a69c5ed2SRob Clark PERF_UCHE_VBIF_LATENCY_SAMPLES = 3, 532a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_TP = 4, 533a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_VFD = 5, 534a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6, 535a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_LRZ = 7, 536a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_SP = 8, 537a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_TP = 9, 538a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_VFD = 10, 539a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_HLSQ = 11, 540a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_LRZ = 12, 541a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_SP = 13, 542a69c5ed2SRob Clark PERF_UCHE_WRITE_REQUESTS_LRZ = 14, 543a69c5ed2SRob Clark PERF_UCHE_WRITE_REQUESTS_SP = 15, 544a69c5ed2SRob Clark PERF_UCHE_WRITE_REQUESTS_VPC = 16, 545a69c5ed2SRob Clark PERF_UCHE_WRITE_REQUESTS_VSC = 17, 546a69c5ed2SRob Clark PERF_UCHE_EVICTS = 18, 547a69c5ed2SRob Clark PERF_UCHE_BANK_REQ0 = 19, 548a69c5ed2SRob Clark PERF_UCHE_BANK_REQ1 = 20, 549a69c5ed2SRob Clark PERF_UCHE_BANK_REQ2 = 21, 550a69c5ed2SRob Clark PERF_UCHE_BANK_REQ3 = 22, 551a69c5ed2SRob Clark PERF_UCHE_BANK_REQ4 = 23, 552a69c5ed2SRob Clark PERF_UCHE_BANK_REQ5 = 24, 553a69c5ed2SRob Clark PERF_UCHE_BANK_REQ6 = 25, 554a69c5ed2SRob Clark PERF_UCHE_BANK_REQ7 = 26, 555a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_CH0 = 27, 556a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_CH1 = 28, 557a69c5ed2SRob Clark PERF_UCHE_GMEM_READ_BEATS = 29, 558a69c5ed2SRob Clark PERF_UCHE_TPH_REF_FULL = 30, 559a69c5ed2SRob Clark PERF_UCHE_TPH_VICTIM_FULL = 31, 560a69c5ed2SRob Clark PERF_UCHE_TPH_EXT_FULL = 32, 561a69c5ed2SRob Clark PERF_UCHE_VBIF_STALL_WRITE_DATA = 33, 562a69c5ed2SRob Clark PERF_UCHE_DCMP_LATENCY_SAMPLES = 34, 563a69c5ed2SRob Clark PERF_UCHE_DCMP_LATENCY_CYCLES = 35, 564a69c5ed2SRob Clark PERF_UCHE_VBIF_READ_BEATS_PC = 36, 565a69c5ed2SRob Clark PERF_UCHE_READ_REQUESTS_PC = 37, 566a69c5ed2SRob Clark PERF_UCHE_RAM_READ_REQ = 38, 567a69c5ed2SRob Clark PERF_UCHE_RAM_WRITE_REQ = 39, 568a69c5ed2SRob Clark }; 569a69c5ed2SRob Clark 570a69c5ed2SRob Clark enum a6xx_tp_perfcounter_select { 571a69c5ed2SRob Clark PERF_TP_BUSY_CYCLES = 0, 572a69c5ed2SRob Clark PERF_TP_STALL_CYCLES_UCHE = 1, 573a69c5ed2SRob Clark PERF_TP_LATENCY_CYCLES = 2, 574a69c5ed2SRob Clark PERF_TP_LATENCY_TRANS = 3, 575a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4, 576a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5, 577a69c5ed2SRob Clark PERF_TP_L1_CACHELINE_REQUESTS = 6, 578a69c5ed2SRob Clark PERF_TP_L1_CACHELINE_MISSES = 7, 579a69c5ed2SRob Clark PERF_TP_SP_TP_TRANS = 8, 580a69c5ed2SRob Clark PERF_TP_TP_SP_TRANS = 9, 581a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS = 10, 582a69c5ed2SRob Clark PERF_TP_FILTER_WORKLOAD_16BIT = 11, 583a69c5ed2SRob Clark PERF_TP_FILTER_WORKLOAD_32BIT = 12, 584a69c5ed2SRob Clark PERF_TP_QUADS_RECEIVED = 13, 585a69c5ed2SRob Clark PERF_TP_QUADS_OFFSET = 14, 586a69c5ed2SRob Clark PERF_TP_QUADS_SHADOW = 15, 587a69c5ed2SRob Clark PERF_TP_QUADS_ARRAY = 16, 588a69c5ed2SRob Clark PERF_TP_QUADS_GRADIENT = 17, 589a69c5ed2SRob Clark PERF_TP_QUADS_1D = 18, 590a69c5ed2SRob Clark PERF_TP_QUADS_2D = 19, 591a69c5ed2SRob Clark PERF_TP_QUADS_BUFFER = 20, 592a69c5ed2SRob Clark PERF_TP_QUADS_3D = 21, 593a69c5ed2SRob Clark PERF_TP_QUADS_CUBE = 22, 594a69c5ed2SRob Clark PERF_TP_DIVERGENT_QUADS_RECEIVED = 23, 595a69c5ed2SRob Clark PERF_TP_PRT_NON_RESIDENT_EVENTS = 24, 596a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_POINT = 25, 597a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_BILINEAR = 26, 598a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_MIP = 27, 599a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_ANISO = 28, 600a69c5ed2SRob Clark PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 29, 601a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_REQUESTS = 30, 602a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_MISSES = 31, 603a69c5ed2SRob Clark PERF_TP_L1_5_L2_REQUESTS = 32, 604a69c5ed2SRob Clark PERF_TP_2D_OUTPUT_PIXELS = 33, 605a69c5ed2SRob Clark PERF_TP_2D_OUTPUT_PIXELS_POINT = 34, 606a69c5ed2SRob Clark PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 35, 607a69c5ed2SRob Clark PERF_TP_2D_FILTER_WORKLOAD_16BIT = 36, 608a69c5ed2SRob Clark PERF_TP_2D_FILTER_WORKLOAD_32BIT = 37, 609a69c5ed2SRob Clark PERF_TP_TPA2TPC_TRANS = 38, 610a69c5ed2SRob Clark PERF_TP_L1_MISSES_ASTC_1TILE = 39, 611a69c5ed2SRob Clark PERF_TP_L1_MISSES_ASTC_2TILE = 40, 612a69c5ed2SRob Clark PERF_TP_L1_MISSES_ASTC_4TILE = 41, 613a69c5ed2SRob Clark PERF_TP_L1_5_L2_COMPRESS_REQS = 42, 614a69c5ed2SRob Clark PERF_TP_L1_5_L2_COMPRESS_MISS = 43, 615a69c5ed2SRob Clark PERF_TP_L1_BANK_CONFLICT = 44, 616a69c5ed2SRob Clark PERF_TP_L1_5_MISS_LATENCY_CYCLES = 45, 617a69c5ed2SRob Clark PERF_TP_L1_5_MISS_LATENCY_TRANS = 46, 618a69c5ed2SRob Clark PERF_TP_QUADS_CONSTANT_MULTIPLIED = 47, 619a69c5ed2SRob Clark PERF_TP_FRONTEND_WORKING_CYCLES = 48, 620a69c5ed2SRob Clark PERF_TP_L1_TAG_WORKING_CYCLES = 49, 621a69c5ed2SRob Clark PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 50, 622a69c5ed2SRob Clark PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 51, 623a69c5ed2SRob Clark PERF_TP_BACKEND_WORKING_CYCLES = 52, 624a69c5ed2SRob Clark PERF_TP_FLAG_CACHE_WORKING_CYCLES = 53, 625a69c5ed2SRob Clark PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54, 626a69c5ed2SRob Clark PERF_TP_STARVE_CYCLES_SP = 55, 627a69c5ed2SRob Clark PERF_TP_STARVE_CYCLES_UCHE = 56, 628a69c5ed2SRob Clark }; 629a69c5ed2SRob Clark 630a69c5ed2SRob Clark enum a6xx_sp_perfcounter_select { 631a69c5ed2SRob Clark PERF_SP_BUSY_CYCLES = 0, 632a69c5ed2SRob Clark PERF_SP_ALU_WORKING_CYCLES = 1, 633a69c5ed2SRob Clark PERF_SP_EFU_WORKING_CYCLES = 2, 634a69c5ed2SRob Clark PERF_SP_STALL_CYCLES_VPC = 3, 635a69c5ed2SRob Clark PERF_SP_STALL_CYCLES_TP = 4, 636a69c5ed2SRob Clark PERF_SP_STALL_CYCLES_UCHE = 5, 637a69c5ed2SRob Clark PERF_SP_STALL_CYCLES_RB = 6, 638a69c5ed2SRob Clark PERF_SP_NON_EXECUTION_CYCLES = 7, 639a69c5ed2SRob Clark PERF_SP_WAVE_CONTEXTS = 8, 640a69c5ed2SRob Clark PERF_SP_WAVE_CONTEXT_CYCLES = 9, 641a69c5ed2SRob Clark PERF_SP_FS_STAGE_WAVE_CYCLES = 10, 642a69c5ed2SRob Clark PERF_SP_FS_STAGE_WAVE_SAMPLES = 11, 643a69c5ed2SRob Clark PERF_SP_VS_STAGE_WAVE_CYCLES = 12, 644a69c5ed2SRob Clark PERF_SP_VS_STAGE_WAVE_SAMPLES = 13, 645a69c5ed2SRob Clark PERF_SP_FS_STAGE_DURATION_CYCLES = 14, 646a69c5ed2SRob Clark PERF_SP_VS_STAGE_DURATION_CYCLES = 15, 647a69c5ed2SRob Clark PERF_SP_WAVE_CTRL_CYCLES = 16, 648a69c5ed2SRob Clark PERF_SP_WAVE_LOAD_CYCLES = 17, 649a69c5ed2SRob Clark PERF_SP_WAVE_EMIT_CYCLES = 18, 650a69c5ed2SRob Clark PERF_SP_WAVE_NOP_CYCLES = 19, 651a69c5ed2SRob Clark PERF_SP_WAVE_WAIT_CYCLES = 20, 652a69c5ed2SRob Clark PERF_SP_WAVE_FETCH_CYCLES = 21, 653a69c5ed2SRob Clark PERF_SP_WAVE_IDLE_CYCLES = 22, 654a69c5ed2SRob Clark PERF_SP_WAVE_END_CYCLES = 23, 655a69c5ed2SRob Clark PERF_SP_WAVE_LONG_SYNC_CYCLES = 24, 656a69c5ed2SRob Clark PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25, 657a69c5ed2SRob Clark PERF_SP_WAVE_JOIN_CYCLES = 26, 658a69c5ed2SRob Clark PERF_SP_LM_LOAD_INSTRUCTIONS = 27, 659a69c5ed2SRob Clark PERF_SP_LM_STORE_INSTRUCTIONS = 28, 660a69c5ed2SRob Clark PERF_SP_LM_ATOMICS = 29, 661a69c5ed2SRob Clark PERF_SP_GM_LOAD_INSTRUCTIONS = 30, 662a69c5ed2SRob Clark PERF_SP_GM_STORE_INSTRUCTIONS = 31, 663a69c5ed2SRob Clark PERF_SP_GM_ATOMICS = 32, 664a69c5ed2SRob Clark PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33, 665a69c5ed2SRob Clark PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34, 666a69c5ed2SRob Clark PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35, 667a69c5ed2SRob Clark PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36, 668a69c5ed2SRob Clark PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37, 669a69c5ed2SRob Clark PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38, 670a69c5ed2SRob Clark PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39, 671a69c5ed2SRob Clark PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40, 672a69c5ed2SRob Clark PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41, 673a69c5ed2SRob Clark PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42, 674a69c5ed2SRob Clark PERF_SP_VS_INSTRUCTIONS = 43, 675a69c5ed2SRob Clark PERF_SP_FS_INSTRUCTIONS = 44, 676a69c5ed2SRob Clark PERF_SP_ADDR_LOCK_COUNT = 45, 677a69c5ed2SRob Clark PERF_SP_UCHE_READ_TRANS = 46, 678a69c5ed2SRob Clark PERF_SP_UCHE_WRITE_TRANS = 47, 679a69c5ed2SRob Clark PERF_SP_EXPORT_VPC_TRANS = 48, 680a69c5ed2SRob Clark PERF_SP_EXPORT_RB_TRANS = 49, 681a69c5ed2SRob Clark PERF_SP_PIXELS_KILLED = 50, 682a69c5ed2SRob Clark PERF_SP_ICL1_REQUESTS = 51, 683a69c5ed2SRob Clark PERF_SP_ICL1_MISSES = 52, 684a69c5ed2SRob Clark PERF_SP_HS_INSTRUCTIONS = 53, 685a69c5ed2SRob Clark PERF_SP_DS_INSTRUCTIONS = 54, 686a69c5ed2SRob Clark PERF_SP_GS_INSTRUCTIONS = 55, 687a69c5ed2SRob Clark PERF_SP_CS_INSTRUCTIONS = 56, 688a69c5ed2SRob Clark PERF_SP_GPR_READ = 57, 689a69c5ed2SRob Clark PERF_SP_GPR_WRITE = 58, 690a69c5ed2SRob Clark PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59, 691a69c5ed2SRob Clark PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60, 692a69c5ed2SRob Clark PERF_SP_LM_BANK_CONFLICTS = 61, 693a69c5ed2SRob Clark PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62, 694a69c5ed2SRob Clark PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63, 695a69c5ed2SRob Clark PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64, 696a69c5ed2SRob Clark PERF_SP_LM_WORKING_CYCLES = 65, 697a69c5ed2SRob Clark PERF_SP_DISPATCHER_WORKING_CYCLES = 66, 698a69c5ed2SRob Clark PERF_SP_SEQUENCER_WORKING_CYCLES = 67, 699a69c5ed2SRob Clark PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68, 700a69c5ed2SRob Clark PERF_SP_STARVE_CYCLES_HLSQ = 69, 701a69c5ed2SRob Clark PERF_SP_NON_EXECUTION_LS_CYCLES = 70, 702a69c5ed2SRob Clark PERF_SP_WORKING_EU = 71, 703a69c5ed2SRob Clark PERF_SP_ANY_EU_WORKING = 72, 704a69c5ed2SRob Clark PERF_SP_WORKING_EU_FS_STAGE = 73, 705a69c5ed2SRob Clark PERF_SP_ANY_EU_WORKING_FS_STAGE = 74, 706a69c5ed2SRob Clark PERF_SP_WORKING_EU_VS_STAGE = 75, 707a69c5ed2SRob Clark PERF_SP_ANY_EU_WORKING_VS_STAGE = 76, 708a69c5ed2SRob Clark PERF_SP_WORKING_EU_CS_STAGE = 77, 709a69c5ed2SRob Clark PERF_SP_ANY_EU_WORKING_CS_STAGE = 78, 710a69c5ed2SRob Clark PERF_SP_GPR_READ_PREFETCH = 79, 711a69c5ed2SRob Clark PERF_SP_GPR_READ_CONFLICT = 80, 712a69c5ed2SRob Clark PERF_SP_GPR_WRITE_CONFLICT = 81, 713a69c5ed2SRob Clark PERF_SP_GM_LOAD_LATENCY_CYCLES = 82, 714a69c5ed2SRob Clark PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83, 715a69c5ed2SRob Clark PERF_SP_EXECUTABLE_WAVES = 84, 716a69c5ed2SRob Clark }; 717a69c5ed2SRob Clark 718a69c5ed2SRob Clark enum a6xx_rb_perfcounter_select { 719a69c5ed2SRob Clark PERF_RB_BUSY_CYCLES = 0, 720a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_HLSQ = 1, 721a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_FIFO0_FULL = 2, 722a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_FIFO1_FULL = 3, 723a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_FIFO2_FULL = 4, 724a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_SP = 5, 725a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_LRZ_TILE = 6, 726a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_CCU = 7, 727a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_Z_PLANE = 8, 728a69c5ed2SRob Clark PERF_RB_STARVE_CYCLES_BARY_PLANE = 9, 729a69c5ed2SRob Clark PERF_RB_Z_WORKLOAD = 10, 730a69c5ed2SRob Clark PERF_RB_HLSQ_ACTIVE = 11, 731a69c5ed2SRob Clark PERF_RB_Z_READ = 12, 732a69c5ed2SRob Clark PERF_RB_Z_WRITE = 13, 733a69c5ed2SRob Clark PERF_RB_C_READ = 14, 734a69c5ed2SRob Clark PERF_RB_C_WRITE = 15, 735a69c5ed2SRob Clark PERF_RB_TOTAL_PASS = 16, 736a69c5ed2SRob Clark PERF_RB_Z_PASS = 17, 737a69c5ed2SRob Clark PERF_RB_Z_FAIL = 18, 738a69c5ed2SRob Clark PERF_RB_S_FAIL = 19, 739a69c5ed2SRob Clark PERF_RB_BLENDED_FXP_COMPONENTS = 20, 740a69c5ed2SRob Clark PERF_RB_BLENDED_FP16_COMPONENTS = 21, 741a69c5ed2SRob Clark PERF_RB_PS_INVOCATIONS = 22, 742a69c5ed2SRob Clark PERF_RB_2D_ALIVE_CYCLES = 23, 743a69c5ed2SRob Clark PERF_RB_2D_STALL_CYCLES_A2D = 24, 744a69c5ed2SRob Clark PERF_RB_2D_STARVE_CYCLES_SRC = 25, 745a69c5ed2SRob Clark PERF_RB_2D_STARVE_CYCLES_SP = 26, 746a69c5ed2SRob Clark PERF_RB_2D_STARVE_CYCLES_DST = 27, 747a69c5ed2SRob Clark PERF_RB_2D_VALID_PIXELS = 28, 748a69c5ed2SRob Clark PERF_RB_3D_PIXELS = 29, 749a69c5ed2SRob Clark PERF_RB_BLENDER_WORKING_CYCLES = 30, 750a69c5ed2SRob Clark PERF_RB_ZPROC_WORKING_CYCLES = 31, 751a69c5ed2SRob Clark PERF_RB_CPROC_WORKING_CYCLES = 32, 752a69c5ed2SRob Clark PERF_RB_SAMPLER_WORKING_CYCLES = 33, 753a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 34, 754a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 35, 755a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 36, 756a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 37, 757a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_VPC = 38, 758a69c5ed2SRob Clark PERF_RB_2D_INPUT_TRANS = 39, 759a69c5ed2SRob Clark PERF_RB_2D_OUTPUT_RB_DST_TRANS = 40, 760a69c5ed2SRob Clark PERF_RB_2D_OUTPUT_RB_SRC_TRANS = 41, 761a69c5ed2SRob Clark PERF_RB_BLENDED_FP32_COMPONENTS = 42, 762a69c5ed2SRob Clark PERF_RB_COLOR_PIX_TILES = 43, 763a69c5ed2SRob Clark PERF_RB_STALL_CYCLES_CCU = 44, 764a69c5ed2SRob Clark PERF_RB_EARLY_Z_ARB3_GRANT = 45, 765a69c5ed2SRob Clark PERF_RB_LATE_Z_ARB3_GRANT = 46, 766a69c5ed2SRob Clark PERF_RB_EARLY_Z_SKIP_GRANT = 47, 767a69c5ed2SRob Clark }; 768a69c5ed2SRob Clark 769a69c5ed2SRob Clark enum a6xx_vsc_perfcounter_select { 770a69c5ed2SRob Clark PERF_VSC_BUSY_CYCLES = 0, 771a69c5ed2SRob Clark PERF_VSC_WORKING_CYCLES = 1, 772a69c5ed2SRob Clark PERF_VSC_STALL_CYCLES_UCHE = 2, 773a69c5ed2SRob Clark PERF_VSC_EOT_NUM = 3, 774a69c5ed2SRob Clark PERF_VSC_INPUT_TILES = 4, 775a69c5ed2SRob Clark }; 776a69c5ed2SRob Clark 777a69c5ed2SRob Clark enum a6xx_ccu_perfcounter_select { 778a69c5ed2SRob Clark PERF_CCU_BUSY_CYCLES = 0, 779a69c5ed2SRob Clark PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1, 780a69c5ed2SRob Clark PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2, 781a69c5ed2SRob Clark PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3, 782a69c5ed2SRob Clark PERF_CCU_DEPTH_BLOCKS = 4, 783a69c5ed2SRob Clark PERF_CCU_COLOR_BLOCKS = 5, 784a69c5ed2SRob Clark PERF_CCU_DEPTH_BLOCK_HIT = 6, 785a69c5ed2SRob Clark PERF_CCU_COLOR_BLOCK_HIT = 7, 786a69c5ed2SRob Clark PERF_CCU_PARTIAL_BLOCK_READ = 8, 787a69c5ed2SRob Clark PERF_CCU_GMEM_READ = 9, 788a69c5ed2SRob Clark PERF_CCU_GMEM_WRITE = 10, 789a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11, 790a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12, 791a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13, 792a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14, 793a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15, 794a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG5_COUNT = 16, 795a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG6_COUNT = 17, 796a69c5ed2SRob Clark PERF_CCU_DEPTH_READ_FLAG8_COUNT = 18, 797a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG0_COUNT = 19, 798a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG1_COUNT = 20, 799a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG2_COUNT = 21, 800a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG3_COUNT = 22, 801a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG4_COUNT = 23, 802a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG5_COUNT = 24, 803a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG6_COUNT = 25, 804a69c5ed2SRob Clark PERF_CCU_COLOR_READ_FLAG8_COUNT = 26, 805a69c5ed2SRob Clark PERF_CCU_2D_RD_REQ = 27, 806a69c5ed2SRob Clark PERF_CCU_2D_WR_REQ = 28, 807a69c5ed2SRob Clark }; 808a69c5ed2SRob Clark 809a69c5ed2SRob Clark enum a6xx_lrz_perfcounter_select { 810a69c5ed2SRob Clark PERF_LRZ_BUSY_CYCLES = 0, 811a69c5ed2SRob Clark PERF_LRZ_STARVE_CYCLES_RAS = 1, 812a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_RB = 2, 813a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_VSC = 3, 814a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_VPC = 4, 815a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5, 816a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_UCHE = 6, 817a69c5ed2SRob Clark PERF_LRZ_LRZ_READ = 7, 818a69c5ed2SRob Clark PERF_LRZ_LRZ_WRITE = 8, 819a69c5ed2SRob Clark PERF_LRZ_READ_LATENCY = 9, 820a69c5ed2SRob Clark PERF_LRZ_MERGE_CACHE_UPDATING = 10, 821a69c5ed2SRob Clark PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11, 822a69c5ed2SRob Clark PERF_LRZ_PRIM_KILLED_BY_LRZ = 12, 823a69c5ed2SRob Clark PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13, 824a69c5ed2SRob Clark PERF_LRZ_FULL_8X8_TILES = 14, 825a69c5ed2SRob Clark PERF_LRZ_PARTIAL_8X8_TILES = 15, 826a69c5ed2SRob Clark PERF_LRZ_TILE_KILLED = 16, 827a69c5ed2SRob Clark PERF_LRZ_TOTAL_PIXEL = 17, 828a69c5ed2SRob Clark PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18, 829a69c5ed2SRob Clark PERF_LRZ_FULLY_COVERED_TILES = 19, 830a69c5ed2SRob Clark PERF_LRZ_PARTIAL_COVERED_TILES = 20, 831a69c5ed2SRob Clark PERF_LRZ_FEEDBACK_ACCEPT = 21, 832a69c5ed2SRob Clark PERF_LRZ_FEEDBACK_DISCARD = 22, 833a69c5ed2SRob Clark PERF_LRZ_FEEDBACK_STALL = 23, 834a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 24, 835a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_RB_BPLANE = 25, 836a69c5ed2SRob Clark PERF_LRZ_STALL_CYCLES_VC = 26, 837a69c5ed2SRob Clark PERF_LRZ_RAS_MASK_TRANS = 27, 838a69c5ed2SRob Clark }; 839a69c5ed2SRob Clark 840a69c5ed2SRob Clark enum a6xx_cmp_perfcounter_select { 841a69c5ed2SRob Clark PERF_CMPDECMP_STALL_CYCLES_ARB = 0, 842a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1, 843a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2, 844a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3, 845a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4, 846a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_REQUEST = 5, 847a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6, 848a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_DATA = 7, 849a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_WRITE_DATA = 8, 850a69c5ed2SRob Clark PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9, 851a69c5ed2SRob Clark PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10, 852a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11, 853a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12, 854a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13, 855a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14, 856a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 15, 857a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 16, 858a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 17, 859a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 18, 860a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 19, 861a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 20, 862a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 21, 863a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 22, 864a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 23, 865a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 24, 866a69c5ed2SRob Clark PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 25, 867a69c5ed2SRob Clark PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 26, 868a69c5ed2SRob Clark PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 27, 869a69c5ed2SRob Clark PERF_CMPDECMP_2D_RD_DATA = 28, 870a69c5ed2SRob Clark PERF_CMPDECMP_2D_WR_DATA = 29, 871a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 30, 872a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 31, 873a69c5ed2SRob Clark PERF_CMPDECMP_2D_OUTPUT_TRANS = 32, 874a69c5ed2SRob Clark PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 33, 875a69c5ed2SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 34, 876a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 35, 877a69c5ed2SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 36, 878a69c5ed2SRob Clark PERF_CMPDECMP_2D_BUSY_CYCLES = 37, 879a69c5ed2SRob Clark PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = 38, 880a69c5ed2SRob Clark PERF_CMPDECMP_2D_PIXELS = 39, 8812d756322SRob Clark }; 8822d756322SRob Clark 883c28c82e9SRob Clark enum a6xx_2d_ifmt { 884c28c82e9SRob Clark R2D_UNORM8 = 16, 885c28c82e9SRob Clark R2D_INT32 = 7, 886c28c82e9SRob Clark R2D_INT16 = 6, 887c28c82e9SRob Clark R2D_INT8 = 5, 888c28c82e9SRob Clark R2D_FLOAT32 = 4, 889c28c82e9SRob Clark R2D_FLOAT16 = 3, 890c28c82e9SRob Clark R2D_UNORM8_SRGB = 1, 891c28c82e9SRob Clark R2D_RAW = 0, 892c28c82e9SRob Clark }; 893c28c82e9SRob Clark 894c28c82e9SRob Clark enum a6xx_ztest_mode { 895c28c82e9SRob Clark A6XX_EARLY_Z = 0, 896c28c82e9SRob Clark A6XX_LATE_Z = 1, 897c28c82e9SRob Clark A6XX_EARLY_LRZ_LATE_Z = 2, 898c28c82e9SRob Clark }; 899c28c82e9SRob Clark 90057cfe41cSRob Clark enum a6xx_sequenced_thread_dist { 90157cfe41cSRob Clark DIST_SCREEN_COORD = 0, 90257cfe41cSRob Clark DIST_ALL_TO_RB0 = 1, 90357cfe41cSRob Clark }; 90457cfe41cSRob Clark 90557cfe41cSRob Clark enum a6xx_single_prim_mode { 90657cfe41cSRob Clark NO_FLUSH = 0, 90757cfe41cSRob Clark FLUSH_PER_OVERLAP_AND_OVERWRITE = 1, 90857cfe41cSRob Clark FLUSH_PER_OVERLAP = 3, 90957cfe41cSRob Clark }; 91057cfe41cSRob Clark 91157cfe41cSRob Clark enum a6xx_raster_mode { 91257cfe41cSRob Clark TYPE_TILED = 0, 91357cfe41cSRob Clark TYPE_WRITER = 1, 91457cfe41cSRob Clark }; 91557cfe41cSRob Clark 91657cfe41cSRob Clark enum a6xx_raster_direction { 91757cfe41cSRob Clark LR_TB = 0, 91857cfe41cSRob Clark RL_TB = 1, 91957cfe41cSRob Clark LR_BT = 2, 92057cfe41cSRob Clark RB_BT = 3, 92157cfe41cSRob Clark }; 92257cfe41cSRob Clark 92357cfe41cSRob Clark enum a6xx_render_mode { 92457cfe41cSRob Clark RENDERING_PASS = 0, 92557cfe41cSRob Clark BINNING_PASS = 1, 92657cfe41cSRob Clark }; 92757cfe41cSRob Clark 92857cfe41cSRob Clark enum a6xx_buffers_location { 92957cfe41cSRob Clark BUFFERS_IN_GMEM = 0, 93057cfe41cSRob Clark BUFFERS_IN_SYSMEM = 3, 93157cfe41cSRob Clark }; 93257cfe41cSRob Clark 93357cfe41cSRob Clark enum a6xx_fragcoord_sample_mode { 93457cfe41cSRob Clark FRAGCOORD_CENTER = 0, 93557cfe41cSRob Clark FRAGCOORD_SAMPLE = 3, 93657cfe41cSRob Clark }; 93757cfe41cSRob Clark 938c28c82e9SRob Clark enum a6xx_rotation { 939c28c82e9SRob Clark ROTATE_0 = 0, 940c28c82e9SRob Clark ROTATE_90 = 1, 941c28c82e9SRob Clark ROTATE_180 = 2, 942c28c82e9SRob Clark ROTATE_270 = 3, 943c28c82e9SRob Clark ROTATE_HFLIP = 4, 944c28c82e9SRob Clark ROTATE_VFLIP = 5, 945c28c82e9SRob Clark }; 946c28c82e9SRob Clark 947c28c82e9SRob Clark enum a6xx_tess_spacing { 948c28c82e9SRob Clark TESS_EQUAL = 0, 949c28c82e9SRob Clark TESS_FRACTIONAL_ODD = 2, 950c28c82e9SRob Clark TESS_FRACTIONAL_EVEN = 3, 951c28c82e9SRob Clark }; 952c28c82e9SRob Clark 953c28c82e9SRob Clark enum a6xx_tess_output { 954c28c82e9SRob Clark TESS_POINTS = 0, 955c28c82e9SRob Clark TESS_LINES = 1, 956c28c82e9SRob Clark TESS_CW_TRIS = 2, 957c28c82e9SRob Clark TESS_CCW_TRIS = 3, 958c28c82e9SRob Clark }; 959c28c82e9SRob Clark 960cc4c26d4SRob Clark enum a6xx_threadsize { 961cc4c26d4SRob Clark THREAD64 = 0, 962cc4c26d4SRob Clark THREAD128 = 1, 963cc4c26d4SRob Clark }; 964cc4c26d4SRob Clark 96557cfe41cSRob Clark enum a6xx_isam_mode { 96657cfe41cSRob Clark ISAMMODE_GL = 2, 96757cfe41cSRob Clark }; 96857cfe41cSRob Clark 9692d756322SRob Clark enum a6xx_tex_filter { 9702d756322SRob Clark A6XX_TEX_NEAREST = 0, 9712d756322SRob Clark A6XX_TEX_LINEAR = 1, 9722d756322SRob Clark A6XX_TEX_ANISO = 2, 973c28c82e9SRob Clark A6XX_TEX_CUBIC = 3, 9742d756322SRob Clark }; 9752d756322SRob Clark 9762d756322SRob Clark enum a6xx_tex_clamp { 9772d756322SRob Clark A6XX_TEX_REPEAT = 0, 9782d756322SRob Clark A6XX_TEX_CLAMP_TO_EDGE = 1, 9792d756322SRob Clark A6XX_TEX_MIRROR_REPEAT = 2, 9802d756322SRob Clark A6XX_TEX_CLAMP_TO_BORDER = 3, 9812d756322SRob Clark A6XX_TEX_MIRROR_CLAMP = 4, 9822d756322SRob Clark }; 9832d756322SRob Clark 9842d756322SRob Clark enum a6xx_tex_aniso { 9852d756322SRob Clark A6XX_TEX_ANISO_1 = 0, 9862d756322SRob Clark A6XX_TEX_ANISO_2 = 1, 9872d756322SRob Clark A6XX_TEX_ANISO_4 = 2, 9882d756322SRob Clark A6XX_TEX_ANISO_8 = 3, 9892d756322SRob Clark A6XX_TEX_ANISO_16 = 4, 9902d756322SRob Clark }; 9912d756322SRob Clark 992c28c82e9SRob Clark enum a6xx_reduction_mode { 993c28c82e9SRob Clark A6XX_REDUCTION_MODE_AVERAGE = 0, 994c28c82e9SRob Clark A6XX_REDUCTION_MODE_MIN = 1, 995c28c82e9SRob Clark A6XX_REDUCTION_MODE_MAX = 2, 996c28c82e9SRob Clark }; 997c28c82e9SRob Clark 9982d756322SRob Clark enum a6xx_tex_swiz { 9992d756322SRob Clark A6XX_TEX_X = 0, 10002d756322SRob Clark A6XX_TEX_Y = 1, 10012d756322SRob Clark A6XX_TEX_Z = 2, 10022d756322SRob Clark A6XX_TEX_W = 3, 10032d756322SRob Clark A6XX_TEX_ZERO = 4, 10042d756322SRob Clark A6XX_TEX_ONE = 5, 10052d756322SRob Clark }; 10062d756322SRob Clark 10072d756322SRob Clark enum a6xx_tex_type { 10082d756322SRob Clark A6XX_TEX_1D = 0, 10092d756322SRob Clark A6XX_TEX_2D = 1, 10102d756322SRob Clark A6XX_TEX_CUBE = 2, 10112d756322SRob Clark A6XX_TEX_3D = 3, 101257cfe41cSRob Clark A6XX_TEX_BUFFER = 4, 10132d756322SRob Clark }; 10142d756322SRob Clark 10152d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001 10162d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR 0x00000002 10172d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW 0x00000040 10182d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080 10192d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_SW 0x00000100 10202d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200 10212d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400 10222d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800 10232d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000 10242d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_IB2 0x00002000 10252d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_IB1 0x00004000 10262d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_RB 0x00008000 10272d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000 10282d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000 10292d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000 10302d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000 10312d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT 0x00800000 10322d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000 10332d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000 10342d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000 10352d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000 10362d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000 10372d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000 10382d756322SRob Clark #define A6XX_CP_INT_CP_OPCODE_ERROR 0x00000001 10392d756322SRob Clark #define A6XX_CP_INT_CP_UCODE_ERROR 0x00000002 10402d756322SRob Clark #define A6XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004 10412d756322SRob Clark #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010 10422d756322SRob Clark #define A6XX_CP_INT_CP_AHB_ERROR 0x00000020 10432d756322SRob Clark #define A6XX_CP_INT_CP_VSD_PARITY_ERROR 0x00000040 10442d756322SRob Clark #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR 0x00000080 10452d756322SRob Clark #define REG_A6XX_CP_RB_BASE 0x00000800 10462d756322SRob Clark 10472d756322SRob Clark #define REG_A6XX_CP_RB_BASE_HI 0x00000801 10482d756322SRob Clark 10492d756322SRob Clark #define REG_A6XX_CP_RB_CNTL 0x00000802 10502d756322SRob Clark 10512d756322SRob Clark #define REG_A6XX_CP_RB_RPTR_ADDR_LO 0x00000804 10522d756322SRob Clark 10532d756322SRob Clark #define REG_A6XX_CP_RB_RPTR_ADDR_HI 0x00000805 10542d756322SRob Clark 10552d756322SRob Clark #define REG_A6XX_CP_RB_RPTR 0x00000806 10562d756322SRob Clark 10572d756322SRob Clark #define REG_A6XX_CP_RB_WPTR 0x00000807 10582d756322SRob Clark 10592d756322SRob Clark #define REG_A6XX_CP_SQE_CNTL 0x00000808 10602d756322SRob Clark 1061c28c82e9SRob Clark #define REG_A6XX_CP_CP2GMU_STATUS 0x00000812 1062c28c82e9SRob Clark #define A6XX_CP_CP2GMU_STATUS_IFPC 0x00000001 1063c28c82e9SRob Clark 10642d756322SRob Clark #define REG_A6XX_CP_HW_FAULT 0x00000821 10652d756322SRob Clark 10662d756322SRob Clark #define REG_A6XX_CP_INTERRUPT_STATUS 0x00000823 10672d756322SRob Clark 10682d756322SRob Clark #define REG_A6XX_CP_PROTECT_STATUS 0x00000824 10692d756322SRob Clark 1070cc4c26d4SRob Clark #define REG_A6XX_CP_SQE_INSTR_BASE 0x00000830 10712d756322SRob Clark 10722d756322SRob Clark #define REG_A6XX_CP_MISC_CNTL 0x00000840 10732d756322SRob Clark 107424e6938eSJonathan Marek #define REG_A6XX_CP_APRIV_CNTL 0x00000844 107524e6938eSJonathan Marek 10762d756322SRob Clark #define REG_A6XX_CP_ROQ_THRESHOLDS_1 0x000008c1 1077c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK 0x000000ff 1078c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT 0 1079c28c82e9SRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_LO(uint32_t val) 1080c28c82e9SRob Clark { 1081c28c82e9SRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK; 1082c28c82e9SRob Clark } 1083c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MASK 0x0000ff00 1084c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__SHIFT 8 1085c28c82e9SRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_RB_HI(uint32_t val) 1086c28c82e9SRob Clark { 1087c28c82e9SRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MASK; 1088c28c82e9SRob Clark } 1089c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK 0x00ff0000 1090c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT 16 1091c28c82e9SRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val) 1092c28c82e9SRob Clark { 1093c28c82e9SRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK; 1094c28c82e9SRob Clark } 1095c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK 0xff000000 1096c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT 24 1097c28c82e9SRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val) 1098c28c82e9SRob Clark { 1099c28c82e9SRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK; 1100c28c82e9SRob Clark } 11012d756322SRob Clark 11022d756322SRob Clark #define REG_A6XX_CP_ROQ_THRESHOLDS_2 0x000008c2 1103c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK 0x000001ff 1104c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT 0 1105c28c82e9SRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val) 1106c28c82e9SRob Clark { 1107c28c82e9SRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK; 1108c28c82e9SRob Clark } 1109c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK 0xffff0000 1110c28c82e9SRob Clark #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT 16 1111c28c82e9SRob Clark static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val) 1112c28c82e9SRob Clark { 1113c28c82e9SRob Clark return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK; 1114c28c82e9SRob Clark } 11152d756322SRob Clark 11162d756322SRob Clark #define REG_A6XX_CP_MEM_POOL_SIZE 0x000008c3 11172d756322SRob Clark 11182d756322SRob Clark #define REG_A6XX_CP_CHICKEN_DBG 0x00000841 11192d756322SRob Clark 11202d756322SRob Clark #define REG_A6XX_CP_ADDR_MODE_CNTL 0x00000842 11212d756322SRob Clark 11222d756322SRob Clark #define REG_A6XX_CP_DBG_ECO_CNTL 0x00000843 11232d756322SRob Clark 11242d756322SRob Clark #define REG_A6XX_CP_PROTECT_CNTL 0x0000084f 11252d756322SRob Clark 11262d756322SRob Clark static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; } 11272d756322SRob Clark 11282d756322SRob Clark static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; } 11292d756322SRob Clark 11302d756322SRob Clark static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; } 11312d756322SRob Clark 11322d756322SRob Clark static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; } 11332d756322SRob Clark #define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0003ffff 11342d756322SRob Clark #define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0 11352d756322SRob Clark static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) 11362d756322SRob Clark { 11372d756322SRob Clark return ((val) << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK; 11382d756322SRob Clark } 11392d756322SRob Clark #define A6XX_CP_PROTECT_REG_MASK_LEN__MASK 0x7ffc0000 11402d756322SRob Clark #define A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT 18 11412d756322SRob Clark static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) 11422d756322SRob Clark { 11432d756322SRob Clark return ((val) << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK; 11442d756322SRob Clark } 11452d756322SRob Clark #define A6XX_CP_PROTECT_REG_READ 0x80000000 11462d756322SRob Clark 11472d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_CNTL 0x000008a0 11482d756322SRob Clark 11492d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x000008a1 11502d756322SRob Clark 11512d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x000008a2 11522d756322SRob Clark 11532d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO 0x000008a3 11542d756322SRob Clark 11552d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI 0x000008a4 11562d756322SRob Clark 11572d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO 0x000008a5 11582d756322SRob Clark 11592d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI 0x000008a6 11602d756322SRob Clark 11612d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO 0x000008a7 11622d756322SRob Clark 11632d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI 0x000008a8 11642d756322SRob Clark 1165cc4c26d4SRob Clark static inline uint32_t REG_A6XX_CP_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008d0 + 0x1*i0; } 11662d756322SRob Clark 11672d756322SRob Clark #define REG_A6XX_CP_CRASH_SCRIPT_BASE_LO 0x00000900 11682d756322SRob Clark 11692d756322SRob Clark #define REG_A6XX_CP_CRASH_SCRIPT_BASE_HI 0x00000901 11702d756322SRob Clark 11712d756322SRob Clark #define REG_A6XX_CP_CRASH_DUMP_CNTL 0x00000902 11722d756322SRob Clark 11732d756322SRob Clark #define REG_A6XX_CP_CRASH_DUMP_STATUS 0x00000903 11742d756322SRob Clark 11752d756322SRob Clark #define REG_A6XX_CP_SQE_STAT_ADDR 0x00000908 11762d756322SRob Clark 11772d756322SRob Clark #define REG_A6XX_CP_SQE_STAT_DATA 0x00000909 11782d756322SRob Clark 11792d756322SRob Clark #define REG_A6XX_CP_DRAW_STATE_ADDR 0x0000090a 11802d756322SRob Clark 11812d756322SRob Clark #define REG_A6XX_CP_DRAW_STATE_DATA 0x0000090b 11822d756322SRob Clark 11832d756322SRob Clark #define REG_A6XX_CP_ROQ_DBG_ADDR 0x0000090c 11842d756322SRob Clark 11852d756322SRob Clark #define REG_A6XX_CP_ROQ_DBG_DATA 0x0000090d 11862d756322SRob Clark 11872d756322SRob Clark #define REG_A6XX_CP_MEM_POOL_DBG_ADDR 0x0000090e 11882d756322SRob Clark 11892d756322SRob Clark #define REG_A6XX_CP_MEM_POOL_DBG_DATA 0x0000090f 11902d756322SRob Clark 11912d756322SRob Clark #define REG_A6XX_CP_SQE_UCODE_DBG_ADDR 0x00000910 11922d756322SRob Clark 11932d756322SRob Clark #define REG_A6XX_CP_SQE_UCODE_DBG_DATA 0x00000911 11942d756322SRob Clark 11952d756322SRob Clark #define REG_A6XX_CP_IB1_BASE 0x00000928 11962d756322SRob Clark 11972d756322SRob Clark #define REG_A6XX_CP_IB1_BASE_HI 0x00000929 11982d756322SRob Clark 11992d756322SRob Clark #define REG_A6XX_CP_IB1_REM_SIZE 0x0000092a 12002d756322SRob Clark 12012d756322SRob Clark #define REG_A6XX_CP_IB2_BASE 0x0000092b 12022d756322SRob Clark 12032d756322SRob Clark #define REG_A6XX_CP_IB2_BASE_HI 0x0000092c 12042d756322SRob Clark 12052d756322SRob Clark #define REG_A6XX_CP_IB2_REM_SIZE 0x0000092d 12062d756322SRob Clark 1207c28c82e9SRob Clark #define REG_A6XX_CP_SDS_BASE 0x0000092e 1208c28c82e9SRob Clark 1209c28c82e9SRob Clark #define REG_A6XX_CP_SDS_BASE_HI 0x0000092f 1210c28c82e9SRob Clark 1211cc4c26d4SRob Clark #define REG_A6XX_CP_SDS_REM_SIZE 0x00000930 1212c28c82e9SRob Clark 1213cc4c26d4SRob Clark #define REG_A6XX_CP_MRB_BASE 0x00000931 1214c28c82e9SRob Clark 1215cc4c26d4SRob Clark #define REG_A6XX_CP_MRB_BASE_HI 0x00000932 1216c28c82e9SRob Clark 1217cc4c26d4SRob Clark #define REG_A6XX_CP_MRB_REM_SIZE 0x00000933 1218c28c82e9SRob Clark 1219cc4c26d4SRob Clark #define REG_A6XX_CP_VSD_BASE 0x00000934 1220cc4c26d4SRob Clark 1221cc4c26d4SRob Clark #define REG_A6XX_CP_VSD_BASE_HI 0x00000935 1222cc4c26d4SRob Clark 1223cc4c26d4SRob Clark #define REG_A6XX_CP_MRB_DWORDS 0x00000946 1224cc4c26d4SRob Clark 1225cc4c26d4SRob Clark #define REG_A6XX_CP_VSD_DWORDS 0x00000947 1226c28c82e9SRob Clark 1227c28c82e9SRob Clark #define REG_A6XX_CP_CSQ_IB1_STAT 0x00000949 1228c28c82e9SRob Clark #define A6XX_CP_CSQ_IB1_STAT_REM__MASK 0xffff0000 1229c28c82e9SRob Clark #define A6XX_CP_CSQ_IB1_STAT_REM__SHIFT 16 1230c28c82e9SRob Clark static inline uint32_t A6XX_CP_CSQ_IB1_STAT_REM(uint32_t val) 1231c28c82e9SRob Clark { 1232c28c82e9SRob Clark return ((val) << A6XX_CP_CSQ_IB1_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB1_STAT_REM__MASK; 1233c28c82e9SRob Clark } 1234c28c82e9SRob Clark 1235c28c82e9SRob Clark #define REG_A6XX_CP_CSQ_IB2_STAT 0x0000094a 1236c28c82e9SRob Clark #define A6XX_CP_CSQ_IB2_STAT_REM__MASK 0xffff0000 1237c28c82e9SRob Clark #define A6XX_CP_CSQ_IB2_STAT_REM__SHIFT 16 1238c28c82e9SRob Clark static inline uint32_t A6XX_CP_CSQ_IB2_STAT_REM(uint32_t val) 1239c28c82e9SRob Clark { 1240c28c82e9SRob Clark return ((val) << A6XX_CP_CSQ_IB2_STAT_REM__SHIFT) & A6XX_CP_CSQ_IB2_STAT_REM__MASK; 1241c28c82e9SRob Clark } 1242c28c82e9SRob Clark 1243cc4c26d4SRob Clark #define REG_A6XX_CP_MRQ_MRB_STAT 0x0000094c 1244cc4c26d4SRob Clark #define A6XX_CP_MRQ_MRB_STAT_REM__MASK 0xffff0000 1245cc4c26d4SRob Clark #define A6XX_CP_MRQ_MRB_STAT_REM__SHIFT 16 1246cc4c26d4SRob Clark static inline uint32_t A6XX_CP_MRQ_MRB_STAT_REM(uint32_t val) 1247cc4c26d4SRob Clark { 1248cc4c26d4SRob Clark return ((val) << A6XX_CP_MRQ_MRB_STAT_REM__SHIFT) & A6XX_CP_MRQ_MRB_STAT_REM__MASK; 1249cc4c26d4SRob Clark } 1250cc4c26d4SRob Clark 12512d756322SRob Clark #define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO 0x00000980 12522d756322SRob Clark 12532d756322SRob Clark #define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI 0x00000981 12542d756322SRob Clark 12552d756322SRob Clark #define REG_A6XX_CP_AHB_CNTL 0x0000098d 12562d756322SRob Clark 12572d756322SRob Clark #define REG_A6XX_CP_APERTURE_CNTL_HOST 0x00000a00 12582d756322SRob Clark 12592d756322SRob Clark #define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03 12602d756322SRob Clark 1261cc4c26d4SRob Clark #define REG_A6XX_CP_LPAC_PROG_FIFO_SIZE 0x00000b34 1262cc4c26d4SRob Clark 1263cc4c26d4SRob Clark #define REG_A6XX_CP_LPAC_SQE_INSTR_BASE 0x00000b82 1264cc4c26d4SRob Clark 12652d756322SRob Clark #define REG_A6XX_VSC_ADDR_MODE_CNTL 0x00000c01 12662d756322SRob Clark 12672d756322SRob Clark #define REG_A6XX_RBBM_INT_0_STATUS 0x00000201 12682d756322SRob Clark 12692d756322SRob Clark #define REG_A6XX_RBBM_STATUS 0x00000210 12702d756322SRob Clark #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x00800000 12712d756322SRob Clark #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x00400000 12722d756322SRob Clark #define A6XX_RBBM_STATUS_HLSQ_BUSY 0x00200000 12732d756322SRob Clark #define A6XX_RBBM_STATUS_VSC_BUSY 0x00100000 12742d756322SRob Clark #define A6XX_RBBM_STATUS_TPL1_BUSY 0x00080000 12752d756322SRob Clark #define A6XX_RBBM_STATUS_SP_BUSY 0x00040000 12762d756322SRob Clark #define A6XX_RBBM_STATUS_UCHE_BUSY 0x00020000 12772d756322SRob Clark #define A6XX_RBBM_STATUS_VPC_BUSY 0x00010000 12782d756322SRob Clark #define A6XX_RBBM_STATUS_VFD_BUSY 0x00008000 12792d756322SRob Clark #define A6XX_RBBM_STATUS_TESS_BUSY 0x00004000 12802d756322SRob Clark #define A6XX_RBBM_STATUS_PC_VSD_BUSY 0x00002000 12812d756322SRob Clark #define A6XX_RBBM_STATUS_PC_DCALL_BUSY 0x00001000 12822d756322SRob Clark #define A6XX_RBBM_STATUS_COM_DCOM_BUSY 0x00000800 12832d756322SRob Clark #define A6XX_RBBM_STATUS_LRZ_BUSY 0x00000400 12842d756322SRob Clark #define A6XX_RBBM_STATUS_A2D_BUSY 0x00000200 12852d756322SRob Clark #define A6XX_RBBM_STATUS_CCU_BUSY 0x00000100 12862d756322SRob Clark #define A6XX_RBBM_STATUS_RB_BUSY 0x00000080 12872d756322SRob Clark #define A6XX_RBBM_STATUS_RAS_BUSY 0x00000040 12882d756322SRob Clark #define A6XX_RBBM_STATUS_TSE_BUSY 0x00000020 12892d756322SRob Clark #define A6XX_RBBM_STATUS_VBIF_BUSY 0x00000010 12902d756322SRob Clark #define A6XX_RBBM_STATUS_GFX_DBGC_BUSY 0x00000008 12912d756322SRob Clark #define A6XX_RBBM_STATUS_CP_BUSY 0x00000004 12922d756322SRob Clark #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER 0x00000002 12932d756322SRob Clark #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER 0x00000001 12942d756322SRob Clark 12952d756322SRob Clark #define REG_A6XX_RBBM_STATUS3 0x00000213 1296c28c82e9SRob Clark #define A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT 0x01000000 12972d756322SRob Clark 12982d756322SRob Clark #define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215 12992d756322SRob Clark 1300cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000400 + 0x2*i0; } 13012d756322SRob Clark 1302cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000041c + 0x2*i0; } 13032d756322SRob Clark 1304cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000424 + 0x2*i0; } 13052d756322SRob Clark 1306cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000434 + 0x2*i0; } 13072d756322SRob Clark 1308cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000444 + 0x2*i0; } 13092d756322SRob Clark 1310cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000450 + 0x2*i0; } 13112d756322SRob Clark 1312cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000045c + 0x2*i0; } 13132d756322SRob Clark 1314cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000466 + 0x2*i0; } 13152d756322SRob Clark 1316cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000046e + 0x2*i0; } 13172d756322SRob Clark 1318cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000476 + 0x2*i0; } 13192d756322SRob Clark 1320cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000048e + 0x2*i0; } 13212d756322SRob Clark 1322cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000004a6 + 0x2*i0; } 13232d756322SRob Clark 1324cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000004d6 + 0x2*i0; } 13252d756322SRob Clark 1326cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000004e6 + 0x2*i0; } 13272d756322SRob Clark 1328cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000004ea + 0x2*i0; } 13292d756322SRob Clark 1330cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000004f2 + 0x2*i0; } 13312d756322SRob Clark 13322d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500 13332d756322SRob Clark 13342d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 0x00000501 13352d756322SRob Clark 13362d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 0x00000502 13372d756322SRob Clark 13382d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 0x00000503 13392d756322SRob Clark 13402d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 0x00000504 13412d756322SRob Clark 13422d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000505 13432d756322SRob Clark 13442d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506 13452d756322SRob Clark 1346cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00000507 + 0x1*i0; } 13472d756322SRob Clark 13482d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b 13492d756322SRob Clark 135057cfe41cSRob Clark #define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD 0x0000050e 135157cfe41cSRob Clark 135257cfe41cSRob Clark #define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS 0x0000050f 135357cfe41cSRob Clark 13542d756322SRob Clark #define REG_A6XX_RBBM_ISDB_CNT 0x00000533 13552d756322SRob Clark 1356c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_0_LO 0x00000540 1357c28c82e9SRob Clark 1358c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_0_HI 0x00000541 1359c28c82e9SRob Clark 1360c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_1_LO 0x00000542 1361c28c82e9SRob Clark 1362c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_1_HI 0x00000543 1363c28c82e9SRob Clark 1364c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_2_LO 0x00000544 1365c28c82e9SRob Clark 1366c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_2_HI 0x00000545 1367c28c82e9SRob Clark 1368c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_3_LO 0x00000546 1369c28c82e9SRob Clark 1370c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_3_HI 0x00000547 1371c28c82e9SRob Clark 1372c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_4_LO 0x00000548 1373c28c82e9SRob Clark 1374c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_4_HI 0x00000549 1375c28c82e9SRob Clark 1376c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_5_LO 0x0000054a 1377c28c82e9SRob Clark 1378c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_5_HI 0x0000054b 1379c28c82e9SRob Clark 1380c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_6_LO 0x0000054c 1381c28c82e9SRob Clark 1382c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_6_HI 0x0000054d 1383c28c82e9SRob Clark 1384c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_7_LO 0x0000054e 1385c28c82e9SRob Clark 1386c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_7_HI 0x0000054f 1387c28c82e9SRob Clark 1388c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_8_LO 0x00000550 1389c28c82e9SRob Clark 1390c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_8_HI 0x00000551 1391c28c82e9SRob Clark 1392c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_9_LO 0x00000552 1393c28c82e9SRob Clark 1394c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_9_HI 0x00000553 1395c28c82e9SRob Clark 1396c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_10_LO 0x00000554 1397c28c82e9SRob Clark 1398c28c82e9SRob Clark #define REG_A6XX_RBBM_PRIMCTR_10_HI 0x00000555 1399c28c82e9SRob Clark 14002d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TRUST_CNTL 0x0000f400 14012d756322SRob Clark 14022d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800 14032d756322SRob Clark 14042d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801 14052d756322SRob Clark 14062d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802 14072d756322SRob Clark 14082d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_CNTL 0x0000f803 14092d756322SRob Clark 14102d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810 14112d756322SRob Clark 14122d756322SRob Clark #define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL 0x00000010 14132d756322SRob Clark 141424e6938eSJonathan Marek #define REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL 0x00000011 141524e6938eSJonathan Marek 1416*3a9dd708SAkhil P Oommen #define REG_A6XX_RBBM_GBIF_HALT 0x00000016 1417*3a9dd708SAkhil P Oommen 1418*3a9dd708SAkhil P Oommen #define REG_A6XX_RBBM_GBIF_HALT_ACK 0x00000017 1419*3a9dd708SAkhil P Oommen 1420c28c82e9SRob Clark #define REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD 0x0000001c 1421c28c82e9SRob Clark #define A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE 0x00000001 1422c28c82e9SRob Clark 14232d756322SRob Clark #define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000001f 14242d756322SRob Clark 14252d756322SRob Clark #define REG_A6XX_RBBM_INT_CLEAR_CMD 0x00000037 14262d756322SRob Clark 14272d756322SRob Clark #define REG_A6XX_RBBM_INT_0_MASK 0x00000038 14282d756322SRob Clark 14292d756322SRob Clark #define REG_A6XX_RBBM_SP_HYST_CNT 0x00000042 14302d756322SRob Clark 14312d756322SRob Clark #define REG_A6XX_RBBM_SW_RESET_CMD 0x00000043 14322d756322SRob Clark 14332d756322SRob Clark #define REG_A6XX_RBBM_RAC_THRESHOLD_CNT 0x00000044 14342d756322SRob Clark 14352d756322SRob Clark #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 14362d756322SRob Clark 14372d756322SRob Clark #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046 14382d756322SRob Clark 14392d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae 14402d756322SRob Clark 14412d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0 14422d756322SRob Clark 14432d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_SP1 0x000000b1 14442d756322SRob Clark 14452d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_SP2 0x000000b2 14462d756322SRob Clark 14472d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_SP3 0x000000b3 14482d756322SRob Clark 14492d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_SP0 0x000000b4 14502d756322SRob Clark 14512d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_SP1 0x000000b5 14522d756322SRob Clark 14532d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_SP2 0x000000b6 14542d756322SRob Clark 14552d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_SP3 0x000000b7 14562d756322SRob Clark 14572d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_SP0 0x000000b8 14582d756322SRob Clark 14592d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_SP1 0x000000b9 14602d756322SRob Clark 14612d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_SP2 0x000000ba 14622d756322SRob Clark 14632d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_SP3 0x000000bb 14642d756322SRob Clark 14652d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_SP0 0x000000bc 14662d756322SRob Clark 14672d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_SP1 0x000000bd 14682d756322SRob Clark 14692d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_SP2 0x000000be 14702d756322SRob Clark 14712d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_SP3 0x000000bf 14722d756322SRob Clark 14732d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TP0 0x000000c0 14742d756322SRob Clark 14752d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TP1 0x000000c1 14762d756322SRob Clark 14772d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TP2 0x000000c2 14782d756322SRob Clark 14792d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TP3 0x000000c3 14802d756322SRob Clark 14812d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_TP0 0x000000c4 14822d756322SRob Clark 14832d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_TP1 0x000000c5 14842d756322SRob Clark 14852d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_TP2 0x000000c6 14862d756322SRob Clark 14872d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_TP3 0x000000c7 14882d756322SRob Clark 14892d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_TP0 0x000000c8 14902d756322SRob Clark 14912d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_TP1 0x000000c9 14922d756322SRob Clark 14932d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_TP2 0x000000ca 14942d756322SRob Clark 14952d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_TP3 0x000000cb 14962d756322SRob Clark 14972d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_TP0 0x000000cc 14982d756322SRob Clark 14992d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_TP1 0x000000cd 15002d756322SRob Clark 15012d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_TP2 0x000000ce 15022d756322SRob Clark 15032d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_TP3 0x000000cf 15042d756322SRob Clark 15052d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TP0 0x000000d0 15062d756322SRob Clark 15072d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TP1 0x000000d1 15082d756322SRob Clark 15092d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TP2 0x000000d2 15102d756322SRob Clark 15112d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TP3 0x000000d3 15122d756322SRob Clark 15132d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY2_TP0 0x000000d4 15142d756322SRob Clark 15152d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY2_TP1 0x000000d5 15162d756322SRob Clark 15172d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY2_TP2 0x000000d6 15182d756322SRob Clark 15192d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY2_TP3 0x000000d7 15202d756322SRob Clark 15212d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY3_TP0 0x000000d8 15222d756322SRob Clark 15232d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY3_TP1 0x000000d9 15242d756322SRob Clark 15252d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY3_TP2 0x000000da 15262d756322SRob Clark 15272d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY3_TP3 0x000000db 15282d756322SRob Clark 15292d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY4_TP0 0x000000dc 15302d756322SRob Clark 15312d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY4_TP1 0x000000dd 15322d756322SRob Clark 15332d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY4_TP2 0x000000de 15342d756322SRob Clark 15352d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY4_TP3 0x000000df 15362d756322SRob Clark 15372d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TP0 0x000000e0 15382d756322SRob Clark 15392d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TP1 0x000000e1 15402d756322SRob Clark 15412d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TP2 0x000000e2 15422d756322SRob Clark 15432d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TP3 0x000000e3 15442d756322SRob Clark 15452d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST2_TP0 0x000000e4 15462d756322SRob Clark 15472d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST2_TP1 0x000000e5 15482d756322SRob Clark 15492d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST2_TP2 0x000000e6 15502d756322SRob Clark 15512d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST2_TP3 0x000000e7 15522d756322SRob Clark 15532d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST3_TP0 0x000000e8 15542d756322SRob Clark 15552d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST3_TP1 0x000000e9 15562d756322SRob Clark 15572d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST3_TP2 0x000000ea 15582d756322SRob Clark 15592d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST3_TP3 0x000000eb 15602d756322SRob Clark 15612d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST4_TP0 0x000000ec 15622d756322SRob Clark 15632d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST4_TP1 0x000000ed 15642d756322SRob Clark 15652d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST4_TP2 0x000000ee 15662d756322SRob Clark 15672d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST4_TP3 0x000000ef 15682d756322SRob Clark 15692d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RB0 0x000000f0 15702d756322SRob Clark 15712d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RB1 0x000000f1 15722d756322SRob Clark 15732d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RB2 0x000000f2 15742d756322SRob Clark 15752d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RB3 0x000000f3 15762d756322SRob Clark 15772d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RB0 0x000000f4 15782d756322SRob Clark 15792d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RB1 0x000000f5 15802d756322SRob Clark 15812d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RB2 0x000000f6 15822d756322SRob Clark 15832d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RB3 0x000000f7 15842d756322SRob Clark 15852d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_CCU0 0x000000f8 15862d756322SRob Clark 15872d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_CCU1 0x000000f9 15882d756322SRob Clark 15892d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_CCU2 0x000000fa 15902d756322SRob Clark 15912d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_CCU3 0x000000fb 15922d756322SRob Clark 15932d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000100 15942d756322SRob Clark 15952d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000101 15962d756322SRob Clark 15972d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000102 15982d756322SRob Clark 15992d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000103 16002d756322SRob Clark 16012d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RAC 0x00000104 16022d756322SRob Clark 16032d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RAC 0x00000105 16042d756322SRob Clark 16052d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_RAC 0x00000106 16062d756322SRob Clark 16072d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RAC 0x00000107 16082d756322SRob Clark 16092d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000108 16102d756322SRob Clark 16112d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000109 16122d756322SRob Clark 16132d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000010a 16142d756322SRob Clark 16152d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_UCHE 0x0000010b 16162d756322SRob Clark 16172d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE 0x0000010c 16182d756322SRob Clark 16192d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE 0x0000010d 16202d756322SRob Clark 16212d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE 0x0000010e 16222d756322SRob Clark 16232d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_UCHE 0x0000010f 16242d756322SRob Clark 16252d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_UCHE 0x00000110 16262d756322SRob Clark 16272d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_MODE_VFD 0x00000111 16282d756322SRob Clark 16292d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_VFD 0x00000112 16302d756322SRob Clark 16312d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_VFD 0x00000113 16322d756322SRob Clark 16332d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_MODE_GPC 0x00000114 16342d756322SRob Clark 16352d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_GPC 0x00000115 16362d756322SRob Clark 16372d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_GPC 0x00000116 16382d756322SRob Clark 16392d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2 0x00000117 16402d756322SRob Clark 16412d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX 0x00000118 16422d756322SRob Clark 16432d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX 0x00000119 16442d756322SRob Clark 16452d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX 0x0000011a 16462d756322SRob Clark 16472d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_MODE_HLSQ 0x0000011b 16482d756322SRob Clark 16492d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ 0x0000011c 16502d756322SRob Clark 1651c28c82e9SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_HLSQ 0x0000011d 1652c28c82e9SRob Clark 1653c28c82e9SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE 0x00000120 1654c28c82e9SRob Clark 1655c28c82e9SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE 0x00000121 1656c28c82e9SRob Clark 1657c28c82e9SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122 1658c28c82e9SRob Clark 16592d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A 0x00000600 16602d756322SRob Clark 16612d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B 0x00000601 16622d756322SRob Clark 16632d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C 0x00000602 16642d756322SRob Clark 16652d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D 0x00000603 16662d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK 0x000000ff 16672d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT 0 16682d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val) 16692d756322SRob Clark { 16702d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK; 16712d756322SRob Clark } 16722d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK 0x0000ff00 16732d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT 8 16742d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val) 16752d756322SRob Clark { 16762d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK; 16772d756322SRob Clark } 16782d756322SRob Clark 16792d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT 0x00000604 16802d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f 16812d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0 16822d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) 16832d756322SRob Clark { 16842d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; 16852d756322SRob Clark } 16862d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000 16872d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12 16882d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) 16892d756322SRob Clark { 16902d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; 16912d756322SRob Clark } 16922d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000 16932d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28 16942d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) 16952d756322SRob Clark { 16962d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; 16972d756322SRob Clark } 16982d756322SRob Clark 16992d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM 0x00000605 17002d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000 17012d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24 17022d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) 17032d756322SRob Clark { 17042d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; 17052d756322SRob Clark } 17062d756322SRob Clark 17072d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 0x00000608 17082d756322SRob Clark 17092d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 0x00000609 17102d756322SRob Clark 17112d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 0x0000060a 17122d756322SRob Clark 17132d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 0x0000060b 17142d756322SRob Clark 17152d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 0x0000060c 17162d756322SRob Clark 17172d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 0x0000060d 17182d756322SRob Clark 17192d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 0x0000060e 17202d756322SRob Clark 17212d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 0x0000060f 17222d756322SRob Clark 17232d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000610 17242d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f 17252d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0 17262d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) 17272d756322SRob Clark { 17282d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; 17292d756322SRob Clark } 17302d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0 17312d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4 17322d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) 17332d756322SRob Clark { 17342d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; 17352d756322SRob Clark } 17362d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00 17372d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8 17382d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) 17392d756322SRob Clark { 17402d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; 17412d756322SRob Clark } 17422d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000 17432d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12 17442d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) 17452d756322SRob Clark { 17462d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; 17472d756322SRob Clark } 17482d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000 17492d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16 17502d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) 17512d756322SRob Clark { 17522d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; 17532d756322SRob Clark } 17542d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000 17552d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20 17562d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) 17572d756322SRob Clark { 17582d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; 17592d756322SRob Clark } 17602d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000 17612d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24 17622d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) 17632d756322SRob Clark { 17642d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; 17652d756322SRob Clark } 17662d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000 17672d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28 17682d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) 17692d756322SRob Clark { 17702d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; 17712d756322SRob Clark } 17722d756322SRob Clark 17732d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000611 17742d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f 17752d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0 17762d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) 17772d756322SRob Clark { 17782d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; 17792d756322SRob Clark } 17802d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0 17812d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4 17822d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) 17832d756322SRob Clark { 17842d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; 17852d756322SRob Clark } 17862d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00 17872d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8 17882d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) 17892d756322SRob Clark { 17902d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; 17912d756322SRob Clark } 17922d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000 17932d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12 17942d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) 17952d756322SRob Clark { 17962d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; 17972d756322SRob Clark } 17982d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000 17992d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16 18002d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) 18012d756322SRob Clark { 18022d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; 18032d756322SRob Clark } 18042d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000 18052d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20 18062d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) 18072d756322SRob Clark { 18082d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; 18092d756322SRob Clark } 18102d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000 18112d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24 18122d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) 18132d756322SRob Clark { 18142d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; 18152d756322SRob Clark } 18162d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000 18172d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28 18182d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) 18192d756322SRob Clark { 18202d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; 18212d756322SRob Clark } 18222d756322SRob Clark 18232d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000062f 18242d756322SRob Clark 18252d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630 18262d756322SRob Clark 1827cc4c26d4SRob Clark static inline uint32_t REG_A6XX_VSC_PERFCTR_VSC_SEL(uint32_t i0) { return 0x00000cd8 + 0x1*i0; } 18282d756322SRob Clark 18292d756322SRob Clark #define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800 18302d756322SRob Clark 18312d756322SRob Clark #define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000 18322d756322SRob Clark 18332d756322SRob Clark #define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00 18342d756322SRob Clark 18352d756322SRob Clark #define REG_A6XX_UCHE_MODE_CNTL 0x00000e01 18362d756322SRob Clark 18372d756322SRob Clark #define REG_A6XX_UCHE_WRITE_RANGE_MAX_LO 0x00000e05 18382d756322SRob Clark 18392d756322SRob Clark #define REG_A6XX_UCHE_WRITE_RANGE_MAX_HI 0x00000e06 18402d756322SRob Clark 18412d756322SRob Clark #define REG_A6XX_UCHE_WRITE_THRU_BASE_LO 0x00000e07 18422d756322SRob Clark 18432d756322SRob Clark #define REG_A6XX_UCHE_WRITE_THRU_BASE_HI 0x00000e08 18442d756322SRob Clark 18452d756322SRob Clark #define REG_A6XX_UCHE_TRAP_BASE_LO 0x00000e09 18462d756322SRob Clark 18472d756322SRob Clark #define REG_A6XX_UCHE_TRAP_BASE_HI 0x00000e0a 18482d756322SRob Clark 18492d756322SRob Clark #define REG_A6XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e0b 18502d756322SRob Clark 18512d756322SRob Clark #define REG_A6XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e0c 18522d756322SRob Clark 18532d756322SRob Clark #define REG_A6XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e0d 18542d756322SRob Clark 18552d756322SRob Clark #define REG_A6XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e0e 18562d756322SRob Clark 18572d756322SRob Clark #define REG_A6XX_UCHE_CACHE_WAYS 0x00000e17 18582d756322SRob Clark 18592d756322SRob Clark #define REG_A6XX_UCHE_FILTER_CNTL 0x00000e18 18602d756322SRob Clark 18612d756322SRob Clark #define REG_A6XX_UCHE_CLIENT_PF 0x00000e19 18622d756322SRob Clark #define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK 0x000000ff 18632d756322SRob Clark #define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT 0 18642d756322SRob Clark static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val) 18652d756322SRob Clark { 18662d756322SRob Clark return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK; 18672d756322SRob Clark } 18682d756322SRob Clark 1869cc4c26d4SRob Clark static inline uint32_t REG_A6XX_UCHE_PERFCTR_UCHE_SEL(uint32_t i0) { return 0x00000e1c + 0x1*i0; } 18702d756322SRob Clark 1871cc4c26d4SRob Clark #define REG_A6XX_UCHE_CMDQ_CONFIG 0x00000e3c 18722d756322SRob Clark 18732d756322SRob Clark #define REG_A6XX_VBIF_VERSION 0x00003000 18742d756322SRob Clark 1875a69c5ed2SRob Clark #define REG_A6XX_VBIF_CLKON 0x00003001 1876a69c5ed2SRob Clark #define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000002 1877a69c5ed2SRob Clark 18782d756322SRob Clark #define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 18792d756322SRob Clark 18802d756322SRob Clark #define REG_A6XX_VBIF_XIN_HALT_CTRL0 0x00003080 18812d756322SRob Clark 18822d756322SRob Clark #define REG_A6XX_VBIF_XIN_HALT_CTRL1 0x00003081 18832d756322SRob Clark 1884a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084 1885a69c5ed2SRob Clark 1886a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS1_CTRL0 0x00003085 1887a69c5ed2SRob Clark 1888a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS1_CTRL1 0x00003086 1889a69c5ed2SRob Clark #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK 0x0000000f 1890a69c5ed2SRob Clark #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT 0 1891a69c5ed2SRob Clark static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val) 1892a69c5ed2SRob Clark { 1893a69c5ed2SRob Clark return ((val) << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK; 1894a69c5ed2SRob Clark } 1895a69c5ed2SRob Clark 1896a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS2_CTRL0 0x00003087 1897a69c5ed2SRob Clark 1898a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS2_CTRL1 0x00003088 1899a69c5ed2SRob Clark #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK 0x000001ff 1900a69c5ed2SRob Clark #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT 0 1901a69c5ed2SRob Clark static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val) 1902a69c5ed2SRob Clark { 1903a69c5ed2SRob Clark return ((val) << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK; 1904a69c5ed2SRob Clark } 1905a69c5ed2SRob Clark 1906a69c5ed2SRob Clark #define REG_A6XX_VBIF_TEST_BUS_OUT 0x0000308c 1907a69c5ed2SRob Clark 19082d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_SEL0 0x000030d0 19092d756322SRob Clark 19102d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_SEL1 0x000030d1 19112d756322SRob Clark 19122d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_SEL2 0x000030d2 19132d756322SRob Clark 19142d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_SEL3 0x000030d3 19152d756322SRob Clark 19162d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_LOW0 0x000030d8 19172d756322SRob Clark 19182d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_LOW1 0x000030d9 19192d756322SRob Clark 19202d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_LOW2 0x000030da 19212d756322SRob Clark 19222d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_LOW3 0x000030db 19232d756322SRob Clark 19242d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_HIGH0 0x000030e0 19252d756322SRob Clark 19262d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_HIGH1 0x000030e1 19272d756322SRob Clark 19282d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_HIGH2 0x000030e2 19292d756322SRob Clark 19302d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_HIGH3 0x000030e3 19312d756322SRob Clark 19322d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_EN0 0x00003100 19332d756322SRob Clark 19342d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_EN1 0x00003101 19352d756322SRob Clark 19362d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_EN2 0x00003102 19372d756322SRob Clark 19382d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110 19392d756322SRob Clark 19402d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111 19412d756322SRob Clark 19422d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112 19432d756322SRob Clark 19442d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118 19452d756322SRob Clark 19462d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119 19472d756322SRob Clark 19482d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a 19492d756322SRob Clark 1950cc4c26d4SRob Clark #define REG_A6XX_GBIF_SCACHE_CNTL0 0x00003c01 1951cc4c26d4SRob Clark 1952e812744cSSharat Masetty #define REG_A6XX_GBIF_SCACHE_CNTL1 0x00003c02 1953e812744cSSharat Masetty 1954e812744cSSharat Masetty #define REG_A6XX_GBIF_QSB_SIDE0 0x00003c03 1955e812744cSSharat Masetty 1956e812744cSSharat Masetty #define REG_A6XX_GBIF_QSB_SIDE1 0x00003c04 1957e812744cSSharat Masetty 1958e812744cSSharat Masetty #define REG_A6XX_GBIF_QSB_SIDE2 0x00003c05 1959e812744cSSharat Masetty 1960e812744cSSharat Masetty #define REG_A6XX_GBIF_QSB_SIDE3 0x00003c06 1961e812744cSSharat Masetty 1962e812744cSSharat Masetty #define REG_A6XX_GBIF_HALT 0x00003c45 1963e812744cSSharat Masetty 1964e812744cSSharat Masetty #define REG_A6XX_GBIF_HALT_ACK 0x00003c46 1965e812744cSSharat Masetty 1966e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_PWR_CNT_EN 0x00003cc0 1967e812744cSSharat Masetty 1968e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_SEL 0x00003cc2 1969e812744cSSharat Masetty 1970e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_PWR_CNT_SEL 0x00003cc3 1971e812744cSSharat Masetty 1972e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_LOW0 0x00003cc4 1973e812744cSSharat Masetty 1974e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_LOW1 0x00003cc5 1975e812744cSSharat Masetty 1976e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_LOW2 0x00003cc6 1977e812744cSSharat Masetty 1978e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_LOW3 0x00003cc7 1979e812744cSSharat Masetty 1980e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_HIGH0 0x00003cc8 1981e812744cSSharat Masetty 1982e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_HIGH1 0x00003cc9 1983e812744cSSharat Masetty 1984e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_HIGH2 0x00003cca 1985e812744cSSharat Masetty 1986e812744cSSharat Masetty #define REG_A6XX_GBIF_PERF_CNT_HIGH3 0x00003ccb 1987e812744cSSharat Masetty 1988e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_LOW0 0x00003ccc 1989e812744cSSharat Masetty 1990e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_LOW1 0x00003ccd 1991e812744cSSharat Masetty 1992e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_LOW2 0x00003cce 1993e812744cSSharat Masetty 1994e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_HIGH0 0x00003ccf 1995e812744cSSharat Masetty 1996e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_HIGH1 0x00003cd0 1997e812744cSSharat Masetty 1998e812744cSSharat Masetty #define REG_A6XX_GBIF_PWR_CNT_HIGH2 0x00003cd1 1999e812744cSSharat Masetty 200057cfe41cSRob Clark #define REG_A6XX_VSC_DBG_ECO_CNTL 0x00000c00 200157cfe41cSRob Clark 20022d756322SRob Clark #define REG_A6XX_VSC_BIN_SIZE 0x00000c02 20032d756322SRob Clark #define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff 20042d756322SRob Clark #define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 20052d756322SRob Clark static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 20062d756322SRob Clark { 20072d756322SRob Clark return ((val >> 5) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK; 20082d756322SRob Clark } 20092d756322SRob Clark #define A6XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001ff00 20102d756322SRob Clark #define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT 8 20112d756322SRob Clark static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 20122d756322SRob Clark { 20132d756322SRob Clark return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK; 20142d756322SRob Clark } 20152d756322SRob Clark 2016c28c82e9SRob Clark #define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS 0x00000c03 20172d756322SRob Clark 20182d756322SRob Clark #define REG_A6XX_VSC_BIN_COUNT 0x00000c06 20192d756322SRob Clark #define A6XX_VSC_BIN_COUNT_NX__MASK 0x000007fe 20202d756322SRob Clark #define A6XX_VSC_BIN_COUNT_NX__SHIFT 1 20212d756322SRob Clark static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val) 20222d756322SRob Clark { 20232d756322SRob Clark return ((val) << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK; 20242d756322SRob Clark } 20252d756322SRob Clark #define A6XX_VSC_BIN_COUNT_NY__MASK 0x001ff800 20262d756322SRob Clark #define A6XX_VSC_BIN_COUNT_NY__SHIFT 11 20272d756322SRob Clark static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val) 20282d756322SRob Clark { 20292d756322SRob Clark return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK; 20302d756322SRob Clark } 20312d756322SRob Clark 20322d756322SRob Clark static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 20332d756322SRob Clark 20342d756322SRob Clark static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 20352d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff 20362d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0 20372d756322SRob Clark static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) 20382d756322SRob Clark { 20392d756322SRob Clark return ((val) << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK; 20402d756322SRob Clark } 20412d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00 20422d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10 20432d756322SRob Clark static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) 20442d756322SRob Clark { 20452d756322SRob Clark return ((val) << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK; 20462d756322SRob Clark } 20472d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_W__MASK 0x03f00000 20482d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20 20492d756322SRob Clark static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) 20502d756322SRob Clark { 20512d756322SRob Clark return ((val) << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK; 20522d756322SRob Clark } 20532d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_H__MASK 0xfc000000 20542d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT 26 20552d756322SRob Clark static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) 20562d756322SRob Clark { 20572d756322SRob Clark return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK; 20582d756322SRob Clark } 20592d756322SRob Clark 2060c28c82e9SRob Clark #define REG_A6XX_VSC_PRIM_STRM_ADDRESS 0x00000c30 2061a69c5ed2SRob Clark 2062c28c82e9SRob Clark #define REG_A6XX_VSC_PRIM_STRM_PITCH 0x00000c32 20632d756322SRob Clark 2064c28c82e9SRob Clark #define REG_A6XX_VSC_PRIM_STRM_LIMIT 0x00000c33 20652d756322SRob Clark 2066c28c82e9SRob Clark #define REG_A6XX_VSC_DRAW_STRM_ADDRESS 0x00000c34 2067a69c5ed2SRob Clark 2068c28c82e9SRob Clark #define REG_A6XX_VSC_DRAW_STRM_PITCH 0x00000c36 20692d756322SRob Clark 2070c28c82e9SRob Clark #define REG_A6XX_VSC_DRAW_STRM_LIMIT 0x00000c37 2071c28c82e9SRob Clark 2072c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_STATE(uint32_t i0) { return 0x00000c38 + 0x1*i0; } 2073c28c82e9SRob Clark 2074c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_STATE_REG(uint32_t i0) { return 0x00000c38 + 0x1*i0; } 2075c28c82e9SRob Clark 2076c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE(uint32_t i0) { return 0x00000c58 + 0x1*i0; } 2077c28c82e9SRob Clark 2078c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0) { return 0x00000c58 + 0x1*i0; } 2079c28c82e9SRob Clark 2080c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; } 2081c28c82e9SRob Clark 2082c28c82e9SRob Clark static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; } 20832d756322SRob Clark 20842d756322SRob Clark #define REG_A6XX_UCHE_UNKNOWN_0E12 0x00000e12 20852d756322SRob Clark 2086c28c82e9SRob Clark #define REG_A6XX_GRAS_CL_CNTL 0x00008000 2087c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_CLIP_DISABLE 0x00000001 2088c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE 0x00000002 2089c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE 0x00000004 2090c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_UNK5 0x00000020 2091c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040 2092c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE 0x00000080 2093c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE 0x00000100 2094c28c82e9SRob Clark #define A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE 0x00000200 2095a69c5ed2SRob Clark 2096c28c82e9SRob Clark #define REG_A6XX_GRAS_VS_CL_CNTL 0x00008001 2097c28c82e9SRob Clark #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK 0x000000ff 2098c28c82e9SRob Clark #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT 0 2099c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val) 2100c28c82e9SRob Clark { 2101c28c82e9SRob Clark return ((val) << A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK; 2102c28c82e9SRob Clark } 2103c28c82e9SRob Clark #define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK 0x0000ff00 2104c28c82e9SRob Clark #define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT 8 2105c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val) 2106c28c82e9SRob Clark { 2107c28c82e9SRob Clark return ((val) << A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK; 2108c28c82e9SRob Clark } 21092d756322SRob Clark 2110c28c82e9SRob Clark #define REG_A6XX_GRAS_DS_CL_CNTL 0x00008002 2111c28c82e9SRob Clark #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK 0x000000ff 2112c28c82e9SRob Clark #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT 0 2113c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(uint32_t val) 2114c28c82e9SRob Clark { 2115c28c82e9SRob Clark return ((val) << A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK; 2116c28c82e9SRob Clark } 2117c28c82e9SRob Clark #define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK 0x0000ff00 2118c28c82e9SRob Clark #define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT 8 2119c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CULL_MASK(uint32_t val) 2120c28c82e9SRob Clark { 2121c28c82e9SRob Clark return ((val) << A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK; 2122c28c82e9SRob Clark } 2123c28c82e9SRob Clark 2124c28c82e9SRob Clark #define REG_A6XX_GRAS_GS_CL_CNTL 0x00008003 2125c28c82e9SRob Clark #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK 0x000000ff 2126c28c82e9SRob Clark #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT 0 2127c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(uint32_t val) 2128c28c82e9SRob Clark { 2129c28c82e9SRob Clark return ((val) << A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK; 2130c28c82e9SRob Clark } 2131c28c82e9SRob Clark #define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK 0x0000ff00 2132c28c82e9SRob Clark #define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT 8 2133c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CULL_MASK(uint32_t val) 2134c28c82e9SRob Clark { 2135c28c82e9SRob Clark return ((val) << A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK; 2136c28c82e9SRob Clark } 2137c28c82e9SRob Clark 2138c28c82e9SRob Clark #define REG_A6XX_GRAS_MAX_LAYER_INDEX 0x00008004 21392d756322SRob Clark 21402d756322SRob Clark #define REG_A6XX_GRAS_CNTL 0x00008005 2141c28c82e9SRob Clark #define A6XX_GRAS_CNTL_IJ_PERSP_PIXEL 0x00000001 2142c28c82e9SRob Clark #define A6XX_GRAS_CNTL_IJ_PERSP_CENTROID 0x00000002 2143c28c82e9SRob Clark #define A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE 0x00000004 214457cfe41cSRob Clark #define A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL 0x00000008 214557cfe41cSRob Clark #define A6XX_GRAS_CNTL_IJ_LINEAR_CENTROID 0x00000010 214657cfe41cSRob Clark #define A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE 0x00000020 2147c28c82e9SRob Clark #define A6XX_GRAS_CNTL_COORD_MASK__MASK 0x000003c0 2148c28c82e9SRob Clark #define A6XX_GRAS_CNTL_COORD_MASK__SHIFT 6 2149c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CNTL_COORD_MASK(uint32_t val) 2150c28c82e9SRob Clark { 2151c28c82e9SRob Clark return ((val) << A6XX_GRAS_CNTL_COORD_MASK__SHIFT) & A6XX_GRAS_CNTL_COORD_MASK__MASK; 2152c28c82e9SRob Clark } 21532d756322SRob Clark 21542d756322SRob Clark #define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x00008006 2155c28c82e9SRob Clark #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000001ff 21562d756322SRob Clark #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0 21572d756322SRob Clark static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val) 21582d756322SRob Clark { 21592d756322SRob Clark return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK; 21602d756322SRob Clark } 2161c28c82e9SRob Clark #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x0007fc00 21622d756322SRob Clark #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10 21632d756322SRob Clark static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) 21642d756322SRob Clark { 21652d756322SRob Clark return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK; 21662d756322SRob Clark } 21672d756322SRob Clark 2168c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT(uint32_t i0) { return 0x00008010 + 0x6*i0; } 2169c28c82e9SRob Clark 2170c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0) { return 0x00008010 + 0x6*i0; } 2171c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff 2172c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0 2173c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET(float val) 21742d756322SRob Clark { 2175c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET__MASK; 21762d756322SRob Clark } 21772d756322SRob Clark 2178c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XSCALE(uint32_t i0) { return 0x00008011 + 0x6*i0; } 2179c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff 2180c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_XSCALE__SHIFT 0 2181c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE(float val) 21822d756322SRob Clark { 2183c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE__MASK; 21842d756322SRob Clark } 21852d756322SRob Clark 2186c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YOFFSET(uint32_t i0) { return 0x00008012 + 0x6*i0; } 2187c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff 2188c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0 2189c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET(float val) 21902d756322SRob Clark { 2191c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET__MASK; 21922d756322SRob Clark } 21932d756322SRob Clark 2194c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YSCALE(uint32_t i0) { return 0x00008013 + 0x6*i0; } 2195c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff 2196c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_YSCALE__SHIFT 0 2197c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE(float val) 21982d756322SRob Clark { 2199c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE__MASK; 22002d756322SRob Clark } 22012d756322SRob Clark 2202c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZOFFSET(uint32_t i0) { return 0x00008014 + 0x6*i0; } 2203c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff 2204c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0 2205c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET(float val) 22062d756322SRob Clark { 2207c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET__MASK; 22082d756322SRob Clark } 22092d756322SRob Clark 2210c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZSCALE(uint32_t i0) { return 0x00008015 + 0x6*i0; } 2211c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff 2212c28c82e9SRob Clark #define A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0 2213c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE(float val) 22142d756322SRob Clark { 2215c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE__MASK; 2216c28c82e9SRob Clark } 2217c28c82e9SRob Clark 2218c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP(uint32_t i0) { return 0x00008070 + 0x2*i0; } 2219c28c82e9SRob Clark 2220c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0) { return 0x00008070 + 0x2*i0; } 2221c28c82e9SRob Clark #define A6XX_GRAS_CL_Z_CLAMP_MIN__MASK 0xffffffff 2222c28c82e9SRob Clark #define A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT 0 2223c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MIN(float val) 2224c28c82e9SRob Clark { 2225c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MIN__MASK; 2226c28c82e9SRob Clark } 2227c28c82e9SRob Clark 2228c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MAX(uint32_t i0) { return 0x00008071 + 0x2*i0; } 2229c28c82e9SRob Clark #define A6XX_GRAS_CL_Z_CLAMP_MAX__MASK 0xffffffff 2230c28c82e9SRob Clark #define A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT 0 2231c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MAX(float val) 2232c28c82e9SRob Clark { 2233c28c82e9SRob Clark return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MAX__MASK; 22342d756322SRob Clark } 22352d756322SRob Clark 22362d756322SRob Clark #define REG_A6XX_GRAS_SU_CNTL 0x00008090 22372d756322SRob Clark #define A6XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001 22382d756322SRob Clark #define A6XX_GRAS_SU_CNTL_CULL_BACK 0x00000002 22392d756322SRob Clark #define A6XX_GRAS_SU_CNTL_FRONT_CW 0x00000004 22402d756322SRob Clark #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8 22412d756322SRob Clark #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3 22422d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) 22432d756322SRob Clark { 22442d756322SRob Clark return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK; 22452d756322SRob Clark } 22462d756322SRob Clark #define A6XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800 2247c28c82e9SRob Clark #define A6XX_GRAS_SU_CNTL_UNK12__MASK 0x00001000 2248c28c82e9SRob Clark #define A6XX_GRAS_SU_CNTL_UNK12__SHIFT 12 2249c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SU_CNTL_UNK12(uint32_t val) 2250c28c82e9SRob Clark { 2251c28c82e9SRob Clark return ((val) << A6XX_GRAS_SU_CNTL_UNK12__SHIFT) & A6XX_GRAS_SU_CNTL_UNK12__MASK; 2252c28c82e9SRob Clark } 225357cfe41cSRob Clark #define A6XX_GRAS_SU_CNTL_LINE_MODE__MASK 0x00002000 225457cfe41cSRob Clark #define A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT 13 225557cfe41cSRob Clark static inline uint32_t A6XX_GRAS_SU_CNTL_LINE_MODE(enum a5xx_line_mode val) 225657cfe41cSRob Clark { 225757cfe41cSRob Clark return ((val) << A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT) & A6XX_GRAS_SU_CNTL_LINE_MODE__MASK; 225857cfe41cSRob Clark } 2259cc4c26d4SRob Clark #define A6XX_GRAS_SU_CNTL_UNK15__MASK 0x00018000 2260c28c82e9SRob Clark #define A6XX_GRAS_SU_CNTL_UNK15__SHIFT 15 2261c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SU_CNTL_UNK15(uint32_t val) 2262c28c82e9SRob Clark { 2263c28c82e9SRob Clark return ((val) << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK; 2264c28c82e9SRob Clark } 2265cc4c26d4SRob Clark #define A6XX_GRAS_SU_CNTL_UNK17 0x00020000 2266cc4c26d4SRob Clark #define A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE 0x00040000 2267cc4c26d4SRob Clark #define A6XX_GRAS_SU_CNTL_UNK19__MASK 0x00780000 2268cc4c26d4SRob Clark #define A6XX_GRAS_SU_CNTL_UNK19__SHIFT 19 2269cc4c26d4SRob Clark static inline uint32_t A6XX_GRAS_SU_CNTL_UNK19(uint32_t val) 2270cc4c26d4SRob Clark { 2271cc4c26d4SRob Clark return ((val) << A6XX_GRAS_SU_CNTL_UNK19__SHIFT) & A6XX_GRAS_SU_CNTL_UNK19__MASK; 2272cc4c26d4SRob Clark } 22732d756322SRob Clark 22742d756322SRob Clark #define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091 22752d756322SRob Clark #define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 22762d756322SRob Clark #define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 22772d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val) 22782d756322SRob Clark { 22792d756322SRob Clark return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 22802d756322SRob Clark } 22812d756322SRob Clark #define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 22822d756322SRob Clark #define A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 22832d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MAX(float val) 22842d756322SRob Clark { 22852d756322SRob Clark return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 22862d756322SRob Clark } 22872d756322SRob Clark 22882d756322SRob Clark #define REG_A6XX_GRAS_SU_POINT_SIZE 0x00008092 2289c28c82e9SRob Clark #define A6XX_GRAS_SU_POINT_SIZE__MASK 0x0000ffff 22902d756322SRob Clark #define A6XX_GRAS_SU_POINT_SIZE__SHIFT 0 22912d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val) 22922d756322SRob Clark { 22932d756322SRob Clark return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK; 22942d756322SRob Clark } 22952d756322SRob Clark 2296a69c5ed2SRob Clark #define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL 0x00008094 2297c28c82e9SRob Clark #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003 2298c28c82e9SRob Clark #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0 2299c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val) 2300c28c82e9SRob Clark { 2301c28c82e9SRob Clark return ((val) << A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK; 2302c28c82e9SRob Clark } 2303a69c5ed2SRob Clark 23042d756322SRob Clark #define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE 0x00008095 23052d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff 23062d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 23072d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val) 23082d756322SRob Clark { 23092d756322SRob Clark return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; 23102d756322SRob Clark } 23112d756322SRob Clark 23122d756322SRob Clark #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00008096 23132d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 23142d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 23152d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 23162d756322SRob Clark { 23172d756322SRob Clark return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 23182d756322SRob Clark } 23192d756322SRob Clark 23202d756322SRob Clark #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x00008097 23212d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff 23222d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0 23232d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val) 23242d756322SRob Clark { 23252d756322SRob Clark return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK; 23262d756322SRob Clark } 23272d756322SRob Clark 23282d756322SRob Clark #define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO 0x00008098 23292d756322SRob Clark #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 23302d756322SRob Clark #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 23312d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) 23322d756322SRob Clark { 23332d756322SRob Clark return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; 23342d756322SRob Clark } 2335c28c82e9SRob Clark #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000008 2336c28c82e9SRob Clark #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT 3 2337c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3(uint32_t val) 2338c28c82e9SRob Clark { 2339c28c82e9SRob Clark return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK; 2340c28c82e9SRob Clark } 23412d756322SRob Clark 234257cfe41cSRob Clark #define REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x00008099 234357cfe41cSRob Clark #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN 0x00000001 234457cfe41cSRob Clark #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK 0x00000006 234557cfe41cSRob Clark #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT 1 234657cfe41cSRob Clark static inline uint32_t A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT(uint32_t val) 234757cfe41cSRob Clark { 234857cfe41cSRob Clark return ((val) << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK; 234957cfe41cSRob Clark } 235057cfe41cSRob Clark #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_INNERCONSERVATIVERASEN 0x00000008 235157cfe41cSRob Clark #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK 0x00000030 235257cfe41cSRob Clark #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT 4 235357cfe41cSRob Clark static inline uint32_t A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4(uint32_t val) 235457cfe41cSRob Clark { 235557cfe41cSRob Clark return ((val) << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK; 235657cfe41cSRob Clark } 23572d756322SRob Clark 235857cfe41cSRob Clark #define REG_A6XX_GRAS_SU_PATH_RENDERING_CNTL 0x0000809a 235957cfe41cSRob Clark #define A6XX_GRAS_SU_PATH_RENDERING_CNTL_UNK0 0x00000001 236057cfe41cSRob Clark #define A6XX_GRAS_SU_PATH_RENDERING_CNTL_LINELENGTHEN 0x00000002 2361c28c82e9SRob Clark 2362c28c82e9SRob Clark #define REG_A6XX_GRAS_VS_LAYER_CNTL 0x0000809b 2363c28c82e9SRob Clark #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER 0x00000001 2364c28c82e9SRob Clark #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW 0x00000002 2365c28c82e9SRob Clark 2366c28c82e9SRob Clark #define REG_A6XX_GRAS_GS_LAYER_CNTL 0x0000809c 2367c28c82e9SRob Clark #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER 0x00000001 2368c28c82e9SRob Clark #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW 0x00000002 2369c28c82e9SRob Clark 2370c28c82e9SRob Clark #define REG_A6XX_GRAS_DS_LAYER_CNTL 0x0000809d 2371c28c82e9SRob Clark #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER 0x00000001 2372c28c82e9SRob Clark #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW 0x00000002 23732d756322SRob Clark 237457cfe41cSRob Clark #define REG_A6XX_GRAS_SC_CNTL 0x000080a0 237557cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK 0x00000007 237657cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT 0 237757cfe41cSRob Clark static inline uint32_t A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(uint32_t val) 237857cfe41cSRob Clark { 237957cfe41cSRob Clark return ((val) << A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK; 238057cfe41cSRob Clark } 238157cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK 0x00000018 238257cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT 3 238357cfe41cSRob Clark static inline uint32_t A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE(enum a6xx_single_prim_mode val) 238457cfe41cSRob Clark { 238557cfe41cSRob Clark return ((val) << A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK; 238657cfe41cSRob Clark } 238757cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK 0x00000020 238857cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT 5 238957cfe41cSRob Clark static inline uint32_t A6XX_GRAS_SC_CNTL_RASTER_MODE(enum a6xx_raster_mode val) 239057cfe41cSRob Clark { 239157cfe41cSRob Clark return ((val) << A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK; 239257cfe41cSRob Clark } 239357cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK 0x000000c0 239457cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT 6 239557cfe41cSRob Clark static inline uint32_t A6XX_GRAS_SC_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val) 239657cfe41cSRob Clark { 239757cfe41cSRob Clark return ((val) << A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK; 239857cfe41cSRob Clark } 239957cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK 0x00000100 240057cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT 8 240157cfe41cSRob Clark static inline uint32_t A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION(enum a6xx_sequenced_thread_dist val) 240257cfe41cSRob Clark { 240357cfe41cSRob Clark return ((val) << A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT) & A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK; 240457cfe41cSRob Clark } 240557cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_UNK9__MASK 0x00000e00 240657cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_UNK9__SHIFT 9 240757cfe41cSRob Clark static inline uint32_t A6XX_GRAS_SC_CNTL_UNK9(uint32_t val) 240857cfe41cSRob Clark { 240957cfe41cSRob Clark return ((val) << A6XX_GRAS_SC_CNTL_UNK9__SHIFT) & A6XX_GRAS_SC_CNTL_UNK9__MASK; 241057cfe41cSRob Clark } 241157cfe41cSRob Clark #define A6XX_GRAS_SC_CNTL_EARLYVIZOUTEN 0x00001000 2412a69c5ed2SRob Clark 2413c28c82e9SRob Clark #define REG_A6XX_GRAS_BIN_CONTROL 0x000080a1 2414c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_BINW__MASK 0x0000003f 2415c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT 0 2416c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val) 2417c28c82e9SRob Clark { 2418c28c82e9SRob Clark return ((val >> 5) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK; 2419c28c82e9SRob Clark } 2420c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_BINH__MASK 0x00007f00 2421c28c82e9SRob Clark #define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT 8 2422c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val) 2423c28c82e9SRob Clark { 2424c28c82e9SRob Clark return ((val >> 4) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK; 2425c28c82e9SRob Clark } 242657cfe41cSRob Clark #define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000 242757cfe41cSRob Clark #define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT 18 242857cfe41cSRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val) 2429c28c82e9SRob Clark { 243057cfe41cSRob Clark return ((val) << A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK; 2431c28c82e9SRob Clark } 243257cfe41cSRob Clark #define A6XX_GRAS_BIN_CONTROL_FORCE_LRZ_WRITE_DIS 0x00200000 243357cfe41cSRob Clark #define A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK 0x00c00000 243457cfe41cSRob Clark #define A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT 22 243557cfe41cSRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val) 2436c28c82e9SRob Clark { 243757cfe41cSRob Clark return ((val) << A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK; 2438c28c82e9SRob Clark } 243957cfe41cSRob Clark #define A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK 0x07000000 244057cfe41cSRob Clark #define A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT 24 244157cfe41cSRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val) 2442c28c82e9SRob Clark { 244357cfe41cSRob Clark return ((val) << A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK; 244457cfe41cSRob Clark } 244557cfe41cSRob Clark #define A6XX_GRAS_BIN_CONTROL_UNK27__MASK 0x08000000 244657cfe41cSRob Clark #define A6XX_GRAS_BIN_CONTROL_UNK27__SHIFT 27 244757cfe41cSRob Clark static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK27(uint32_t val) 244857cfe41cSRob Clark { 244957cfe41cSRob Clark return ((val) << A6XX_GRAS_BIN_CONTROL_UNK27__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK27__MASK; 2450c28c82e9SRob Clark } 2451c28c82e9SRob Clark 24522d756322SRob Clark #define REG_A6XX_GRAS_RAS_MSAA_CNTL 0x000080a2 24532d756322SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 24542d756322SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 24552d756322SRob Clark static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 24562d756322SRob Clark { 24572d756322SRob Clark return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK; 24582d756322SRob Clark } 2459c28c82e9SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK 0x00000004 2460c28c82e9SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT 2 2461c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK2(uint32_t val) 2462c28c82e9SRob Clark { 2463c28c82e9SRob Clark return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK; 2464c28c82e9SRob Clark } 2465c28c82e9SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK 0x00000008 2466c28c82e9SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT 3 2467c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK3(uint32_t val) 2468c28c82e9SRob Clark { 2469c28c82e9SRob Clark return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK; 2470c28c82e9SRob Clark } 24712d756322SRob Clark 24722d756322SRob Clark #define REG_A6XX_GRAS_DEST_MSAA_CNTL 0x000080a3 24732d756322SRob Clark #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 24742d756322SRob Clark #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 24752d756322SRob Clark static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 24762d756322SRob Clark { 24772d756322SRob Clark return ((val) << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK; 24782d756322SRob Clark } 24792d756322SRob Clark #define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 24802d756322SRob Clark 2481c28c82e9SRob Clark #define REG_A6XX_GRAS_SAMPLE_CONFIG 0x000080a4 2482c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_CONFIG_UNK0 0x00000001 2483c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002 24842d756322SRob Clark 2485c28c82e9SRob Clark #define REG_A6XX_GRAS_SAMPLE_LOCATION_0 0x000080a5 2486c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f 2487c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 2488c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) 2489c28c82e9SRob Clark { 2490c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; 2491c28c82e9SRob Clark } 2492c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 2493c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 2494c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) 2495c28c82e9SRob Clark { 2496c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; 2497c28c82e9SRob Clark } 2498c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 2499c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 2500c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) 2501c28c82e9SRob Clark { 2502c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; 2503c28c82e9SRob Clark } 2504c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 2505c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 2506c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) 2507c28c82e9SRob Clark { 2508c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; 2509c28c82e9SRob Clark } 2510c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 2511c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 2512c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) 2513c28c82e9SRob Clark { 2514c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; 2515c28c82e9SRob Clark } 2516c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 2517c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 2518c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) 2519c28c82e9SRob Clark { 2520c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; 2521c28c82e9SRob Clark } 2522c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 2523c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 2524c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) 2525c28c82e9SRob Clark { 2526c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; 2527c28c82e9SRob Clark } 2528c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 2529c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 2530c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) 2531c28c82e9SRob Clark { 2532c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; 2533c28c82e9SRob Clark } 25342d756322SRob Clark 2535c28c82e9SRob Clark #define REG_A6XX_GRAS_SAMPLE_LOCATION_1 0x000080a6 2536c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f 2537c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 2538c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) 2539c28c82e9SRob Clark { 2540c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; 2541c28c82e9SRob Clark } 2542c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 2543c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 2544c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) 2545c28c82e9SRob Clark { 2546c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; 2547c28c82e9SRob Clark } 2548c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 2549c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 2550c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) 2551c28c82e9SRob Clark { 2552c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; 2553c28c82e9SRob Clark } 2554c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 2555c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 2556c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) 2557c28c82e9SRob Clark { 2558c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; 2559c28c82e9SRob Clark } 2560c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 2561c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 2562c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) 2563c28c82e9SRob Clark { 2564c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; 2565c28c82e9SRob Clark } 2566c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 2567c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 2568c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) 2569c28c82e9SRob Clark { 2570c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; 2571c28c82e9SRob Clark } 2572c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 2573c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 2574c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) 2575c28c82e9SRob Clark { 2576c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; 2577c28c82e9SRob Clark } 2578c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 2579c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 2580c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) 2581c28c82e9SRob Clark { 2582c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; 2583c28c82e9SRob Clark } 25842d756322SRob Clark 25852d756322SRob Clark #define REG_A6XX_GRAS_UNKNOWN_80AF 0x000080af 25862d756322SRob Clark 2587c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR(uint32_t i0) { return 0x000080b0 + 0x2*i0; } 2588c28c82e9SRob Clark 2589c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0) { return 0x000080b0 + 0x2*i0; } 2590c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x0000ffff 2591c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 2592c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 25932d756322SRob Clark { 2594c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; 25952d756322SRob Clark } 2596c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0xffff0000 2597c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 2598c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 25992d756322SRob Clark { 2600c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; 26012d756322SRob Clark } 26022d756322SRob Clark 2603c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR(uint32_t i0) { return 0x000080b1 + 0x2*i0; } 2604c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x0000ffff 2605c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 2606c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 26072d756322SRob Clark { 2608c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; 26092d756322SRob Clark } 2610c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0xffff0000 2611c28c82e9SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 2612c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 26132d756322SRob Clark { 2614c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; 26152d756322SRob Clark } 26162d756322SRob Clark 2617c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(uint32_t i0) { return 0x000080d0 + 0x2*i0; } 2618c28c82e9SRob Clark 2619c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0) { return 0x000080d0 + 0x2*i0; } 2620c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK 0x0000ffff 2621c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT 0 2622c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(uint32_t val) 26232d756322SRob Clark { 2624c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK; 26252d756322SRob Clark } 2626c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK 0xffff0000 2627c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT 16 2628c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(uint32_t val) 26292d756322SRob Clark { 2630c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK; 26312d756322SRob Clark } 26322d756322SRob Clark 2633c28c82e9SRob Clark static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(uint32_t i0) { return 0x000080d1 + 0x2*i0; } 2634c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK 0x0000ffff 2635c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT 0 2636c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X(uint32_t val) 26372d756322SRob Clark { 2638c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK; 26392d756322SRob Clark } 2640c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK 0xffff0000 2641c28c82e9SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT 16 2642c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y(uint32_t val) 26432d756322SRob Clark { 2644c28c82e9SRob Clark return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK; 26452d756322SRob Clark } 26462d756322SRob Clark 26472d756322SRob Clark #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL 0x000080f0 2648c28c82e9SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00003fff 26492d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 26502d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 26512d756322SRob Clark { 26522d756322SRob Clark return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 26532d756322SRob Clark } 2654c28c82e9SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x3fff0000 26552d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 26562d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 26572d756322SRob Clark { 26582d756322SRob Clark return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 26592d756322SRob Clark } 26602d756322SRob Clark 26612d756322SRob Clark #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR 0x000080f1 2662c28c82e9SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00003fff 26632d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 26642d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 26652d756322SRob Clark { 26662d756322SRob Clark return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 26672d756322SRob Clark } 2668c28c82e9SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x3fff0000 26692d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 26702d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 26712d756322SRob Clark { 26722d756322SRob Clark return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 26732d756322SRob Clark } 26742d756322SRob Clark 26752d756322SRob Clark #define REG_A6XX_GRAS_LRZ_CNTL 0x00008100 26762d756322SRob Clark #define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001 26772d756322SRob Clark #define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002 26782d756322SRob Clark #define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004 2679c28c82e9SRob Clark #define A6XX_GRAS_LRZ_CNTL_FC_ENABLE 0x00000008 2680c28c82e9SRob Clark #define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE 0x00000010 2681cc4c26d4SRob Clark #define A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE 0x00000020 2682cc4c26d4SRob Clark #define A6XX_GRAS_LRZ_CNTL_UNK6__MASK 0x000003c0 2683cc4c26d4SRob Clark #define A6XX_GRAS_LRZ_CNTL_UNK6__SHIFT 6 2684cc4c26d4SRob Clark static inline uint32_t A6XX_GRAS_LRZ_CNTL_UNK6(uint32_t val) 2685c28c82e9SRob Clark { 2686cc4c26d4SRob Clark return ((val) << A6XX_GRAS_LRZ_CNTL_UNK6__SHIFT) & A6XX_GRAS_LRZ_CNTL_UNK6__MASK; 2687c28c82e9SRob Clark } 26882d756322SRob Clark 268957cfe41cSRob Clark #define REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL 0x00008101 269057cfe41cSRob Clark #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_SAMPLEID 0x00000001 269157cfe41cSRob Clark #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK 0x00000006 269257cfe41cSRob Clark #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT 1 269357cfe41cSRob Clark static inline uint32_t A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val) 26942d756322SRob Clark { 269557cfe41cSRob Clark return ((val) << A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK; 269657cfe41cSRob Clark } 269757cfe41cSRob Clark 269857cfe41cSRob Clark #define REG_A6XX_GRAS_LRZ_MRT_BUF_INFO_0 0x00008102 269957cfe41cSRob Clark #define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK 0x000000ff 270057cfe41cSRob Clark #define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT 0 270157cfe41cSRob Clark static inline uint32_t A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT(enum a6xx_format val) 270257cfe41cSRob Clark { 270357cfe41cSRob Clark return ((val) << A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT) & A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK; 27042d756322SRob Clark } 27052d756322SRob Clark 2706c28c82e9SRob Clark #define REG_A6XX_GRAS_LRZ_BUFFER_BASE 0x00008103 2707c28c82e9SRob Clark #define A6XX_GRAS_LRZ_BUFFER_BASE__MASK 0xffffffff 2708c28c82e9SRob Clark #define A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT 0 2709c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_LRZ_BUFFER_BASE(uint32_t val) 2710c28c82e9SRob Clark { 2711c28c82e9SRob Clark return ((val) << A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_BUFFER_BASE__MASK; 2712c28c82e9SRob Clark } 2713c28c82e9SRob Clark 27142d756322SRob Clark #define REG_A6XX_GRAS_LRZ_BUFFER_PITCH 0x00008105 2715c28c82e9SRob Clark #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK 0x000000ff 27162d756322SRob Clark #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT 0 27172d756322SRob Clark static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val) 27182d756322SRob Clark { 27192d756322SRob Clark return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK; 27202d756322SRob Clark } 2721c28c82e9SRob Clark #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffffc00 2722c28c82e9SRob Clark #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT 10 27232d756322SRob Clark static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 27242d756322SRob Clark { 2725c28c82e9SRob Clark return ((val >> 4) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK; 27262d756322SRob Clark } 27272d756322SRob Clark 2728c28c82e9SRob Clark #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE 0x00008106 2729c28c82e9SRob Clark #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK 0xffffffff 2730c28c82e9SRob Clark #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT 0 2731c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(uint32_t val) 2732c28c82e9SRob Clark { 2733c28c82e9SRob Clark return ((val) << A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK; 2734c28c82e9SRob Clark } 2735c28c82e9SRob Clark 2736c28c82e9SRob Clark #define REG_A6XX_GRAS_SAMPLE_CNTL 0x00008109 2737c28c82e9SRob Clark #define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001 2738c28c82e9SRob Clark 2739c28c82e9SRob Clark #define REG_A6XX_GRAS_UNKNOWN_810A 0x0000810a 2740c28c82e9SRob Clark #define A6XX_GRAS_UNKNOWN_810A_UNK0__MASK 0x000007ff 2741c28c82e9SRob Clark #define A6XX_GRAS_UNKNOWN_810A_UNK0__SHIFT 0 2742c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK0(uint32_t val) 2743c28c82e9SRob Clark { 2744c28c82e9SRob Clark return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK0__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK0__MASK; 2745c28c82e9SRob Clark } 2746c28c82e9SRob Clark #define A6XX_GRAS_UNKNOWN_810A_UNK16__MASK 0x07ff0000 2747c28c82e9SRob Clark #define A6XX_GRAS_UNKNOWN_810A_UNK16__SHIFT 16 2748c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK16(uint32_t val) 2749c28c82e9SRob Clark { 2750c28c82e9SRob Clark return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK16__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK16__MASK; 2751c28c82e9SRob Clark } 2752c28c82e9SRob Clark #define A6XX_GRAS_UNKNOWN_810A_UNK28__MASK 0xf0000000 2753c28c82e9SRob Clark #define A6XX_GRAS_UNKNOWN_810A_UNK28__SHIFT 28 2754c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_UNKNOWN_810A_UNK28(uint32_t val) 2755c28c82e9SRob Clark { 2756c28c82e9SRob Clark return ((val) << A6XX_GRAS_UNKNOWN_810A_UNK28__SHIFT) & A6XX_GRAS_UNKNOWN_810A_UNK28__MASK; 2757c28c82e9SRob Clark } 2758a69c5ed2SRob Clark 2759a69c5ed2SRob Clark #define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110 2760a69c5ed2SRob Clark 27612d756322SRob Clark #define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400 2762c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK 0x00000007 2763c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT 0 2764c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val) 2765c28c82e9SRob Clark { 2766c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK; 2767c28c82e9SRob Clark } 276857cfe41cSRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_OVERWRITEEN 0x00000008 276957cfe41cSRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK 0x00000070 277057cfe41cSRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT 4 277157cfe41cSRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK4(uint32_t val) 2772c28c82e9SRob Clark { 277357cfe41cSRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK; 2774c28c82e9SRob Clark } 2775c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR 0x00000080 2776ccdf7e28SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00 2777ccdf7e28SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8 2778c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val) 2779ccdf7e28SRob Clark { 2780ccdf7e28SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK; 2781ccdf7e28SRob Clark } 2782ccdf7e28SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR 0x00010000 2783c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK 0x00060000 2784c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT 17 2785c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK17(uint32_t val) 2786c28c82e9SRob Clark { 2787c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK; 2788c28c82e9SRob Clark } 2789c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_D24S8 0x00080000 2790c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK 0x00f00000 2791c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT 20 2792c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_MASK(uint32_t val) 2793c28c82e9SRob Clark { 2794c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK; 2795c28c82e9SRob Clark } 2796c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK 0x1f000000 2797c28c82e9SRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT 24 2798c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val) 2799c28c82e9SRob Clark { 2800c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK; 2801c28c82e9SRob Clark } 280257cfe41cSRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK 0x20000000 280357cfe41cSRob Clark #define A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT 29 280457cfe41cSRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val) 2805c28c82e9SRob Clark { 280657cfe41cSRob Clark return ((val) << A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK; 2807c28c82e9SRob Clark } 28082d756322SRob Clark 28092d756322SRob Clark #define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401 28102d756322SRob Clark 28112d756322SRob Clark #define REG_A6XX_GRAS_2D_SRC_BR_X 0x00008402 28122d756322SRob Clark 28132d756322SRob Clark #define REG_A6XX_GRAS_2D_SRC_TL_Y 0x00008403 28142d756322SRob Clark 28152d756322SRob Clark #define REG_A6XX_GRAS_2D_SRC_BR_Y 0x00008404 28162d756322SRob Clark 28172d756322SRob Clark #define REG_A6XX_GRAS_2D_DST_TL 0x00008405 2818c28c82e9SRob Clark #define A6XX_GRAS_2D_DST_TL_X__MASK 0x00003fff 28192d756322SRob Clark #define A6XX_GRAS_2D_DST_TL_X__SHIFT 0 28202d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val) 28212d756322SRob Clark { 28222d756322SRob Clark return ((val) << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK; 28232d756322SRob Clark } 2824c28c82e9SRob Clark #define A6XX_GRAS_2D_DST_TL_Y__MASK 0x3fff0000 28252d756322SRob Clark #define A6XX_GRAS_2D_DST_TL_Y__SHIFT 16 28262d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val) 28272d756322SRob Clark { 28282d756322SRob Clark return ((val) << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK; 28292d756322SRob Clark } 28302d756322SRob Clark 28312d756322SRob Clark #define REG_A6XX_GRAS_2D_DST_BR 0x00008406 2832c28c82e9SRob Clark #define A6XX_GRAS_2D_DST_BR_X__MASK 0x00003fff 28332d756322SRob Clark #define A6XX_GRAS_2D_DST_BR_X__SHIFT 0 28342d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val) 28352d756322SRob Clark { 28362d756322SRob Clark return ((val) << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK; 28372d756322SRob Clark } 2838c28c82e9SRob Clark #define A6XX_GRAS_2D_DST_BR_Y__MASK 0x3fff0000 28392d756322SRob Clark #define A6XX_GRAS_2D_DST_BR_Y__SHIFT 16 28402d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val) 28412d756322SRob Clark { 28422d756322SRob Clark return ((val) << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK; 28432d756322SRob Clark } 28442d756322SRob Clark 2845c28c82e9SRob Clark #define REG_A6XX_GRAS_2D_UNKNOWN_8407 0x00008407 2846c28c82e9SRob Clark 2847c28c82e9SRob Clark #define REG_A6XX_GRAS_2D_UNKNOWN_8408 0x00008408 2848c28c82e9SRob Clark 2849c28c82e9SRob Clark #define REG_A6XX_GRAS_2D_UNKNOWN_8409 0x00008409 2850c28c82e9SRob Clark 2851c28c82e9SRob Clark #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_1 0x0000840a 2852c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK 0x00003fff 2853c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT 0 2854c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_X(uint32_t val) 28552d756322SRob Clark { 2856c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK; 28572d756322SRob Clark } 2858c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK 0x3fff0000 2859c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT 16 2860c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(uint32_t val) 28612d756322SRob Clark { 2862c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK; 28632d756322SRob Clark } 28642d756322SRob Clark 2865c28c82e9SRob Clark #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_2 0x0000840b 2866c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK 0x00003fff 2867c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT 0 2868c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_X(uint32_t val) 28692d756322SRob Clark { 2870c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK; 28712d756322SRob Clark } 2872c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK 0x3fff0000 2873c28c82e9SRob Clark #define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT 16 2874c28c82e9SRob Clark static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val) 28752d756322SRob Clark { 2876c28c82e9SRob Clark return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK; 28772d756322SRob Clark } 28782d756322SRob Clark 287957cfe41cSRob Clark #define REG_A6XX_GRAS_DBG_ECO_CNTL 0x00008600 288057cfe41cSRob Clark #define A6XX_GRAS_DBG_ECO_CNTL_UNK7 0x00000080 288157cfe41cSRob Clark #define A6XX_GRAS_DBG_ECO_CNTL_LRZCACHELOCKDIS 0x00000800 28822d756322SRob Clark 2883c28c82e9SRob Clark #define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601 2884c28c82e9SRob Clark 2885cc4c26d4SRob Clark static inline uint32_t REG_A6XX_GRAS_PERFCTR_TSE_SEL(uint32_t i0) { return 0x00008610 + 0x1*i0; } 2886c28c82e9SRob Clark 2887cc4c26d4SRob Clark static inline uint32_t REG_A6XX_GRAS_PERFCTR_RAS_SEL(uint32_t i0) { return 0x00008614 + 0x1*i0; } 2888c28c82e9SRob Clark 2889cc4c26d4SRob Clark static inline uint32_t REG_A6XX_GRAS_PERFCTR_LRZ_SEL(uint32_t i0) { return 0x00008618 + 0x1*i0; } 2890c28c82e9SRob Clark 2891a69c5ed2SRob Clark #define REG_A6XX_RB_BIN_CONTROL 0x00008800 2892c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f 2893a69c5ed2SRob Clark #define A6XX_RB_BIN_CONTROL_BINW__SHIFT 0 2894a69c5ed2SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val) 2895a69c5ed2SRob Clark { 2896a69c5ed2SRob Clark return ((val >> 5) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK; 2897a69c5ed2SRob Clark } 2898c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL_BINH__MASK 0x00007f00 2899a69c5ed2SRob Clark #define A6XX_RB_BIN_CONTROL_BINH__SHIFT 8 2900a69c5ed2SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val) 2901a69c5ed2SRob Clark { 2902a69c5ed2SRob Clark return ((val >> 4) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK; 2903a69c5ed2SRob Clark } 290457cfe41cSRob Clark #define A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000 290557cfe41cSRob Clark #define A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT 18 290657cfe41cSRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val) 2907c28c82e9SRob Clark { 290857cfe41cSRob Clark return ((val) << A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK; 2909c28c82e9SRob Clark } 291057cfe41cSRob Clark #define A6XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS 0x00200000 291157cfe41cSRob Clark #define A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK 0x00c00000 291257cfe41cSRob Clark #define A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT 22 291357cfe41cSRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val) 2914c28c82e9SRob Clark { 291557cfe41cSRob Clark return ((val) << A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK; 2916c28c82e9SRob Clark } 291757cfe41cSRob Clark #define A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK 0x07000000 291857cfe41cSRob Clark #define A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT 24 291957cfe41cSRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val) 2920c28c82e9SRob Clark { 292157cfe41cSRob Clark return ((val) << A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK; 2922c28c82e9SRob Clark } 2923a69c5ed2SRob Clark 2924a69c5ed2SRob Clark #define REG_A6XX_RB_RENDER_CNTL 0x00008801 292557cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK 0x00000038 292657cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT 3 292757cfe41cSRob Clark static inline uint32_t A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE(uint32_t val) 2928c28c82e9SRob Clark { 292957cfe41cSRob Clark return ((val) << A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK; 2930c28c82e9SRob Clark } 293157cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_EARLYVIZOUTEN 0x00000040 2932a69c5ed2SRob Clark #define A6XX_RB_RENDER_CNTL_BINNING 0x00000080 293357cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_UNK8__MASK 0x00000700 2934c28c82e9SRob Clark #define A6XX_RB_RENDER_CNTL_UNK8__SHIFT 8 2935c28c82e9SRob Clark static inline uint32_t A6XX_RB_RENDER_CNTL_UNK8(uint32_t val) 2936c28c82e9SRob Clark { 2937c28c82e9SRob Clark return ((val) << A6XX_RB_RENDER_CNTL_UNK8__SHIFT) & A6XX_RB_RENDER_CNTL_UNK8__MASK; 2938c28c82e9SRob Clark } 293957cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK 0x00000100 294057cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT 8 294157cfe41cSRob Clark static inline uint32_t A6XX_RB_RENDER_CNTL_RASTER_MODE(enum a6xx_raster_mode val) 294257cfe41cSRob Clark { 294357cfe41cSRob Clark return ((val) << A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK; 294457cfe41cSRob Clark } 294557cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK 0x00000600 294657cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT 9 294757cfe41cSRob Clark static inline uint32_t A6XX_RB_RENDER_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val) 294857cfe41cSRob Clark { 294957cfe41cSRob Clark return ((val) << A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK; 295057cfe41cSRob Clark } 295157cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_CONSERVATIVERASEN 0x00000800 295257cfe41cSRob Clark #define A6XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN 0x00001000 2953a69c5ed2SRob Clark #define A6XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000 2954a69c5ed2SRob Clark #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000 2955a69c5ed2SRob Clark #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16 2956a69c5ed2SRob Clark static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val) 2957a69c5ed2SRob Clark { 2958a69c5ed2SRob Clark return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK; 2959a69c5ed2SRob Clark } 2960a69c5ed2SRob Clark 29612d756322SRob Clark #define REG_A6XX_RB_RAS_MSAA_CNTL 0x00008802 29622d756322SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 29632d756322SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 29642d756322SRob Clark static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 29652d756322SRob Clark { 29662d756322SRob Clark return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK; 29672d756322SRob Clark } 2968c28c82e9SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK 0x00000004 2969c28c82e9SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT 2 2970c28c82e9SRob Clark static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK2(uint32_t val) 2971c28c82e9SRob Clark { 2972c28c82e9SRob Clark return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK; 2973c28c82e9SRob Clark } 2974c28c82e9SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK 0x00000008 2975c28c82e9SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT 3 2976c28c82e9SRob Clark static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK3(uint32_t val) 2977c28c82e9SRob Clark { 2978c28c82e9SRob Clark return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK; 2979c28c82e9SRob Clark } 29802d756322SRob Clark 29812d756322SRob Clark #define REG_A6XX_RB_DEST_MSAA_CNTL 0x00008803 29822d756322SRob Clark #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 29832d756322SRob Clark #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 29842d756322SRob Clark static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 29852d756322SRob Clark { 29862d756322SRob Clark return ((val) << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK; 29872d756322SRob Clark } 29882d756322SRob Clark #define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 29892d756322SRob Clark 2990c28c82e9SRob Clark #define REG_A6XX_RB_SAMPLE_CONFIG 0x00008804 2991c28c82e9SRob Clark #define A6XX_RB_SAMPLE_CONFIG_UNK0 0x00000001 2992c28c82e9SRob Clark #define A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002 29932d756322SRob Clark 2994c28c82e9SRob Clark #define REG_A6XX_RB_SAMPLE_LOCATION_0 0x00008805 2995c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f 2996c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 2997c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) 2998c28c82e9SRob Clark { 2999c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; 3000c28c82e9SRob Clark } 3001c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 3002c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 3003c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) 3004c28c82e9SRob Clark { 3005c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; 3006c28c82e9SRob Clark } 3007c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 3008c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 3009c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) 3010c28c82e9SRob Clark { 3011c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; 3012c28c82e9SRob Clark } 3013c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 3014c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 3015c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) 3016c28c82e9SRob Clark { 3017c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; 3018c28c82e9SRob Clark } 3019c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 3020c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 3021c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) 3022c28c82e9SRob Clark { 3023c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; 3024c28c82e9SRob Clark } 3025c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 3026c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 3027c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) 3028c28c82e9SRob Clark { 3029c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; 3030c28c82e9SRob Clark } 3031c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 3032c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 3033c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) 3034c28c82e9SRob Clark { 3035c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; 3036c28c82e9SRob Clark } 3037c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 3038c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 3039c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) 3040c28c82e9SRob Clark { 3041c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; 3042c28c82e9SRob Clark } 30432d756322SRob Clark 3044c28c82e9SRob Clark #define REG_A6XX_RB_SAMPLE_LOCATION_1 0x00008806 3045c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f 3046c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 3047c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) 3048c28c82e9SRob Clark { 3049c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; 3050c28c82e9SRob Clark } 3051c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 3052c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 3053c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) 3054c28c82e9SRob Clark { 3055c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; 3056c28c82e9SRob Clark } 3057c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 3058c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 3059c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) 3060c28c82e9SRob Clark { 3061c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; 3062c28c82e9SRob Clark } 3063c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 3064c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 3065c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) 3066c28c82e9SRob Clark { 3067c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; 3068c28c82e9SRob Clark } 3069c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 3070c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 3071c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) 3072c28c82e9SRob Clark { 3073c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; 3074c28c82e9SRob Clark } 3075c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 3076c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 3077c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) 3078c28c82e9SRob Clark { 3079c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; 3080c28c82e9SRob Clark } 3081c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 3082c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 3083c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) 3084c28c82e9SRob Clark { 3085c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; 3086c28c82e9SRob Clark } 3087c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 3088c28c82e9SRob Clark #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 3089c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) 3090c28c82e9SRob Clark { 3091c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; 3092c28c82e9SRob Clark } 30932d756322SRob Clark 30942d756322SRob Clark #define REG_A6XX_RB_RENDER_CONTROL0 0x00008809 3095c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL 0x00000001 3096c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID 0x00000002 3097c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE 0x00000004 309857cfe41cSRob Clark #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL 0x00000008 309957cfe41cSRob Clark #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID 0x00000010 310057cfe41cSRob Clark #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE 0x00000020 3101c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK 0x000003c0 3102c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT 6 3103c28c82e9SRob Clark static inline uint32_t A6XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val) 3104c28c82e9SRob Clark { 3105c28c82e9SRob Clark return ((val) << A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK; 3106c28c82e9SRob Clark } 31072d756322SRob Clark #define A6XX_RB_RENDER_CONTROL0_UNK10 0x00000400 31082d756322SRob Clark 31092d756322SRob Clark #define REG_A6XX_RB_RENDER_CONTROL1 0x0000880a 31102d756322SRob Clark #define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001 3111c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL1_UNK1 0x00000002 3112c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL1_FACENESS 0x00000004 31132d756322SRob Clark #define A6XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000008 311457cfe41cSRob Clark #define A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK 0x00000030 311557cfe41cSRob Clark #define A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT 4 311657cfe41cSRob Clark static inline uint32_t A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val) 311757cfe41cSRob Clark { 311857cfe41cSRob Clark return ((val) << A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK; 311957cfe41cSRob Clark } 3120c28c82e9SRob Clark #define A6XX_RB_RENDER_CONTROL1_SIZE 0x00000040 312157cfe41cSRob Clark #define A6XX_RB_RENDER_CONTROL1_LINELENGTHEN 0x00000080 312257cfe41cSRob Clark #define A6XX_RB_RENDER_CONTROL1_FOVEATION 0x00000100 31232d756322SRob Clark 31242d756322SRob Clark #define REG_A6XX_RB_FS_OUTPUT_CNTL0 0x0000880b 3125c28c82e9SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001 31262d756322SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z 0x00000002 3127c28c82e9SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK 0x00000004 3128c28c82e9SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF 0x00000008 31292d756322SRob Clark 31302d756322SRob Clark #define REG_A6XX_RB_FS_OUTPUT_CNTL1 0x0000880c 31312d756322SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f 31322d756322SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT 0 31332d756322SRob Clark static inline uint32_t A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val) 31342d756322SRob Clark { 31352d756322SRob Clark return ((val) << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK; 31362d756322SRob Clark } 31372d756322SRob Clark 31382d756322SRob Clark #define REG_A6XX_RB_RENDER_COMPONENTS 0x0000880d 31392d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f 31402d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0 31412d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) 31422d756322SRob Clark { 31432d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK; 31442d756322SRob Clark } 31452d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0 31462d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4 31472d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) 31482d756322SRob Clark { 31492d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK; 31502d756322SRob Clark } 31512d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00 31522d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8 31532d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) 31542d756322SRob Clark { 31552d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK; 31562d756322SRob Clark } 31572d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000 31582d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12 31592d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) 31602d756322SRob Clark { 31612d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK; 31622d756322SRob Clark } 31632d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000 31642d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16 31652d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) 31662d756322SRob Clark { 31672d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK; 31682d756322SRob Clark } 31692d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000 31702d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20 31712d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) 31722d756322SRob Clark { 31732d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK; 31742d756322SRob Clark } 31752d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000 31762d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24 31772d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) 31782d756322SRob Clark { 31792d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK; 31802d756322SRob Clark } 31812d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000 31822d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28 31832d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) 31842d756322SRob Clark { 31852d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK; 31862d756322SRob Clark } 31872d756322SRob Clark 31882d756322SRob Clark #define REG_A6XX_RB_DITHER_CNTL 0x0000880e 31892d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK 0x00000003 31902d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT 0 31912d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val) 31922d756322SRob Clark { 31932d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK; 31942d756322SRob Clark } 31952d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK 0x0000000c 31962d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT 2 31972d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val) 31982d756322SRob Clark { 31992d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK; 32002d756322SRob Clark } 32012d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK 0x00000030 32022d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT 4 32032d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val) 32042d756322SRob Clark { 32052d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK; 32062d756322SRob Clark } 32072d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK 0x000000c0 32082d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT 6 32092d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val) 32102d756322SRob Clark { 32112d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK; 32122d756322SRob Clark } 32132d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK 0x00000300 32142d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT 8 32152d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val) 32162d756322SRob Clark { 32172d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK; 32182d756322SRob Clark } 32192d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK 0x00000c00 32202d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT 10 32212d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val) 32222d756322SRob Clark { 32232d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK; 32242d756322SRob Clark } 32252d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK 0x00001000 32262d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT 12 32272d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val) 32282d756322SRob Clark { 32292d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK; 32302d756322SRob Clark } 32312d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK 0x0000c000 32322d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT 14 32332d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val) 32342d756322SRob Clark { 32352d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK; 32362d756322SRob Clark } 32372d756322SRob Clark 32382d756322SRob Clark #define REG_A6XX_RB_SRGB_CNTL 0x0000880f 32392d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT0 0x00000001 32402d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT1 0x00000002 32412d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT2 0x00000004 32422d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT3 0x00000008 32432d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT4 0x00000010 32442d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT5 0x00000020 32452d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT6 0x00000040 32462d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT7 0x00000080 32472d756322SRob Clark 3248c28c82e9SRob Clark #define REG_A6XX_RB_SAMPLE_CNTL 0x00008810 3249c28c82e9SRob Clark #define A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001 3250a69c5ed2SRob Clark 3251a69c5ed2SRob Clark #define REG_A6XX_RB_UNKNOWN_8811 0x00008811 3252a69c5ed2SRob Clark 32532d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8818 0x00008818 32542d756322SRob Clark 32552d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8819 0x00008819 32562d756322SRob Clark 32572d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881A 0x0000881a 32582d756322SRob Clark 32592d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881B 0x0000881b 32602d756322SRob Clark 32612d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881C 0x0000881c 32622d756322SRob Clark 32632d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881D 0x0000881d 32642d756322SRob Clark 32652d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881E 0x0000881e 32662d756322SRob Clark 32672d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; } 32682d756322SRob Clark 32692d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; } 32702d756322SRob Clark #define A6XX_RB_MRT_CONTROL_BLEND 0x00000001 32712d756322SRob Clark #define A6XX_RB_MRT_CONTROL_BLEND2 0x00000002 32722d756322SRob Clark #define A6XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004 32732d756322SRob Clark #define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078 32742d756322SRob Clark #define A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3 32752d756322SRob Clark static inline uint32_t A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) 32762d756322SRob Clark { 32772d756322SRob Clark return ((val) << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK; 32782d756322SRob Clark } 32792d756322SRob Clark #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780 32802d756322SRob Clark #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7 32812d756322SRob Clark static inline uint32_t A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 32822d756322SRob Clark { 32832d756322SRob Clark return ((val) << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 32842d756322SRob Clark } 32852d756322SRob Clark 32862d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; } 32872d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 32882d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 32892d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 32902d756322SRob Clark { 32912d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 32922d756322SRob Clark } 32932d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 32942d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 32952d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 32962d756322SRob Clark { 32972d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 32982d756322SRob Clark } 32992d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 33002d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 33012d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 33022d756322SRob Clark { 33032d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 33042d756322SRob Clark } 33052d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 33062d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 33072d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 33082d756322SRob Clark { 33092d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 33102d756322SRob Clark } 33112d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 33122d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 33132d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 33142d756322SRob Clark { 33152d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 33162d756322SRob Clark } 33172d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 33182d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 33192d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 33202d756322SRob Clark { 33212d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 33222d756322SRob Clark } 33232d756322SRob Clark 33242d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; } 33252d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff 33262d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 3327c28c82e9SRob Clark static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val) 33282d756322SRob Clark { 33292d756322SRob Clark return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 33302d756322SRob Clark } 33312d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300 33322d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8 33332d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val) 33342d756322SRob Clark { 33352d756322SRob Clark return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 33362d756322SRob Clark } 3337c28c82e9SRob Clark #define A6XX_RB_MRT_BUF_INFO_UNK10__MASK 0x00000400 3338c28c82e9SRob Clark #define A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT 10 3339c28c82e9SRob Clark static inline uint32_t A6XX_RB_MRT_BUF_INFO_UNK10(uint32_t val) 3340c28c82e9SRob Clark { 3341c28c82e9SRob Clark return ((val) << A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT) & A6XX_RB_MRT_BUF_INFO_UNK10__MASK; 3342c28c82e9SRob Clark } 33432d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000 33442d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13 33452d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 33462d756322SRob Clark { 33472d756322SRob Clark return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 33482d756322SRob Clark } 33492d756322SRob Clark 33502d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; } 3351c28c82e9SRob Clark #define A6XX_RB_MRT_PITCH__MASK 0x0000ffff 33522d756322SRob Clark #define A6XX_RB_MRT_PITCH__SHIFT 0 33532d756322SRob Clark static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val) 33542d756322SRob Clark { 33552d756322SRob Clark return ((val >> 6) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK; 33562d756322SRob Clark } 33572d756322SRob Clark 33582d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; } 3359c28c82e9SRob Clark #define A6XX_RB_MRT_ARRAY_PITCH__MASK 0x1fffffff 33602d756322SRob Clark #define A6XX_RB_MRT_ARRAY_PITCH__SHIFT 0 33612d756322SRob Clark static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val) 33622d756322SRob Clark { 33632d756322SRob Clark return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK; 33642d756322SRob Clark } 33652d756322SRob Clark 3366c28c82e9SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; } 3367c28c82e9SRob Clark #define A6XX_RB_MRT_BASE__MASK 0xffffffff 3368c28c82e9SRob Clark #define A6XX_RB_MRT_BASE__SHIFT 0 3369c28c82e9SRob Clark static inline uint32_t A6XX_RB_MRT_BASE(uint32_t val) 3370c28c82e9SRob Clark { 3371c28c82e9SRob Clark return ((val) << A6XX_RB_MRT_BASE__SHIFT) & A6XX_RB_MRT_BASE__MASK; 3372c28c82e9SRob Clark } 3373c28c82e9SRob Clark 33742d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; } 3375c28c82e9SRob Clark #define A6XX_RB_MRT_BASE_GMEM__MASK 0xfffff000 3376c28c82e9SRob Clark #define A6XX_RB_MRT_BASE_GMEM__SHIFT 12 3377c28c82e9SRob Clark static inline uint32_t A6XX_RB_MRT_BASE_GMEM(uint32_t val) 3378c28c82e9SRob Clark { 3379c28c82e9SRob Clark return ((val >> 12) << A6XX_RB_MRT_BASE_GMEM__SHIFT) & A6XX_RB_MRT_BASE_GMEM__MASK; 3380c28c82e9SRob Clark } 33812d756322SRob Clark 33822d756322SRob Clark #define REG_A6XX_RB_BLEND_RED_F32 0x00008860 33832d756322SRob Clark #define A6XX_RB_BLEND_RED_F32__MASK 0xffffffff 33842d756322SRob Clark #define A6XX_RB_BLEND_RED_F32__SHIFT 0 33852d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_RED_F32(float val) 33862d756322SRob Clark { 33872d756322SRob Clark return ((fui(val)) << A6XX_RB_BLEND_RED_F32__SHIFT) & A6XX_RB_BLEND_RED_F32__MASK; 33882d756322SRob Clark } 33892d756322SRob Clark 33902d756322SRob Clark #define REG_A6XX_RB_BLEND_GREEN_F32 0x00008861 33912d756322SRob Clark #define A6XX_RB_BLEND_GREEN_F32__MASK 0xffffffff 33922d756322SRob Clark #define A6XX_RB_BLEND_GREEN_F32__SHIFT 0 33932d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_GREEN_F32(float val) 33942d756322SRob Clark { 33952d756322SRob Clark return ((fui(val)) << A6XX_RB_BLEND_GREEN_F32__SHIFT) & A6XX_RB_BLEND_GREEN_F32__MASK; 33962d756322SRob Clark } 33972d756322SRob Clark 33982d756322SRob Clark #define REG_A6XX_RB_BLEND_BLUE_F32 0x00008862 33992d756322SRob Clark #define A6XX_RB_BLEND_BLUE_F32__MASK 0xffffffff 34002d756322SRob Clark #define A6XX_RB_BLEND_BLUE_F32__SHIFT 0 34012d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_BLUE_F32(float val) 34022d756322SRob Clark { 34032d756322SRob Clark return ((fui(val)) << A6XX_RB_BLEND_BLUE_F32__SHIFT) & A6XX_RB_BLEND_BLUE_F32__MASK; 34042d756322SRob Clark } 34052d756322SRob Clark 34062d756322SRob Clark #define REG_A6XX_RB_BLEND_ALPHA_F32 0x00008863 34072d756322SRob Clark #define A6XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff 34082d756322SRob Clark #define A6XX_RB_BLEND_ALPHA_F32__SHIFT 0 34092d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_ALPHA_F32(float val) 34102d756322SRob Clark { 34112d756322SRob Clark return ((fui(val)) << A6XX_RB_BLEND_ALPHA_F32__SHIFT) & A6XX_RB_BLEND_ALPHA_F32__MASK; 34122d756322SRob Clark } 34132d756322SRob Clark 34142d756322SRob Clark #define REG_A6XX_RB_ALPHA_CONTROL 0x00008864 34152d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff 34162d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 34172d756322SRob Clark static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) 34182d756322SRob Clark { 34192d756322SRob Clark return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; 34202d756322SRob Clark } 34212d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 34222d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 34232d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 34242d756322SRob Clark static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 34252d756322SRob Clark { 34262d756322SRob Clark return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; 34272d756322SRob Clark } 34282d756322SRob Clark 34292d756322SRob Clark #define REG_A6XX_RB_BLEND_CNTL 0x00008865 34302d756322SRob Clark #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff 34312d756322SRob Clark #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 34322d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val) 34332d756322SRob Clark { 34342d756322SRob Clark return ((val) << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK; 34352d756322SRob Clark } 34362d756322SRob Clark #define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100 3437c28c82e9SRob Clark #define A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200 3438ccdf7e28SRob Clark #define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 3439c28c82e9SRob Clark #define A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE 0x00000800 34402d756322SRob Clark #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000 34412d756322SRob Clark #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16 34422d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val) 34432d756322SRob Clark { 34442d756322SRob Clark return ((val) << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK; 34452d756322SRob Clark } 34462d756322SRob Clark 3447a69c5ed2SRob Clark #define REG_A6XX_RB_DEPTH_PLANE_CNTL 0x00008870 3448c28c82e9SRob Clark #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003 3449c28c82e9SRob Clark #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0 3450c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val) 3451c28c82e9SRob Clark { 3452c28c82e9SRob Clark return ((val) << A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK; 3453c28c82e9SRob Clark } 3454a69c5ed2SRob Clark 34552d756322SRob Clark #define REG_A6XX_RB_DEPTH_CNTL 0x00008871 345657cfe41cSRob Clark #define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000001 34572d756322SRob Clark #define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002 34582d756322SRob Clark #define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c 34592d756322SRob Clark #define A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2 34602d756322SRob Clark static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) 34612d756322SRob Clark { 34622d756322SRob Clark return ((val) << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK; 34632d756322SRob Clark } 3464c28c82e9SRob Clark #define A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE 0x00000020 346557cfe41cSRob Clark #define A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE 0x00000040 3466c28c82e9SRob Clark #define A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE 0x00000080 34672d756322SRob Clark 34682d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_INFO 0x00008872 34692d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 34702d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 34712d756322SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) 34722d756322SRob Clark { 34732d756322SRob Clark return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; 34742d756322SRob Clark } 3475c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000018 3476c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT 3 3477c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val) 3478c28c82e9SRob Clark { 3479c28c82e9SRob Clark return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK; 3480c28c82e9SRob Clark } 34812d756322SRob Clark 34822d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_PITCH 0x00008873 3483c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_PITCH__MASK 0x00003fff 34842d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0 34852d756322SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) 34862d756322SRob Clark { 34872d756322SRob Clark return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK; 34882d756322SRob Clark } 34892d756322SRob Clark 34902d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x00008874 3491c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0x0fffffff 34922d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0 34932d756322SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) 34942d756322SRob Clark { 34952d756322SRob Clark return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; 34962d756322SRob Clark } 34972d756322SRob Clark 3498c28c82e9SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_BASE 0x00008875 3499c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_BASE__MASK 0xffffffff 3500c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_BASE__SHIFT 0 3501c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE(uint32_t val) 3502c28c82e9SRob Clark { 3503c28c82e9SRob Clark return ((val) << A6XX_RB_DEPTH_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE__MASK; 3504c28c82e9SRob Clark } 3505c28c82e9SRob Clark 35062d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM 0x00008877 3507c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK 0xfffff000 3508c28c82e9SRob Clark #define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT 12 3509c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE_GMEM(uint32_t val) 3510c28c82e9SRob Clark { 3511c28c82e9SRob Clark return ((val >> 12) << A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK; 3512c28c82e9SRob Clark } 35132d756322SRob Clark 3514c28c82e9SRob Clark #define REG_A6XX_RB_Z_BOUNDS_MIN 0x00008878 3515c28c82e9SRob Clark #define A6XX_RB_Z_BOUNDS_MIN__MASK 0xffffffff 3516c28c82e9SRob Clark #define A6XX_RB_Z_BOUNDS_MIN__SHIFT 0 3517c28c82e9SRob Clark static inline uint32_t A6XX_RB_Z_BOUNDS_MIN(float val) 3518c28c82e9SRob Clark { 3519c28c82e9SRob Clark return ((fui(val)) << A6XX_RB_Z_BOUNDS_MIN__SHIFT) & A6XX_RB_Z_BOUNDS_MIN__MASK; 3520c28c82e9SRob Clark } 35212d756322SRob Clark 3522c28c82e9SRob Clark #define REG_A6XX_RB_Z_BOUNDS_MAX 0x00008879 3523c28c82e9SRob Clark #define A6XX_RB_Z_BOUNDS_MAX__MASK 0xffffffff 3524c28c82e9SRob Clark #define A6XX_RB_Z_BOUNDS_MAX__SHIFT 0 3525c28c82e9SRob Clark static inline uint32_t A6XX_RB_Z_BOUNDS_MAX(float val) 3526c28c82e9SRob Clark { 3527c28c82e9SRob Clark return ((fui(val)) << A6XX_RB_Z_BOUNDS_MAX__SHIFT) & A6XX_RB_Z_BOUNDS_MAX__MASK; 3528c28c82e9SRob Clark } 35292d756322SRob Clark 35302d756322SRob Clark #define REG_A6XX_RB_STENCIL_CONTROL 0x00008880 35312d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 35322d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 35332d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 35342d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 35352d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 35362d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 35372d756322SRob Clark { 35382d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC__MASK; 35392d756322SRob Clark } 35402d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 35412d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 35422d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 35432d756322SRob Clark { 35442d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL__MASK; 35452d756322SRob Clark } 35462d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 35472d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 35482d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 35492d756322SRob Clark { 35502d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK; 35512d756322SRob Clark } 35522d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 35532d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 35542d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 35552d756322SRob Clark { 35562d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 35572d756322SRob Clark } 35582d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 35592d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 35602d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 35612d756322SRob Clark { 35622d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 35632d756322SRob Clark } 35642d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 35652d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 35662d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 35672d756322SRob Clark { 35682d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 35692d756322SRob Clark } 35702d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 35712d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 35722d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 35732d756322SRob Clark { 35742d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 35752d756322SRob Clark } 35762d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 35772d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 35782d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 35792d756322SRob Clark { 35802d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 35812d756322SRob Clark } 35822d756322SRob Clark 35832d756322SRob Clark #define REG_A6XX_RB_STENCIL_INFO 0x00008881 35842d756322SRob Clark #define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 3585c28c82e9SRob Clark #define A6XX_RB_STENCIL_INFO_UNK1 0x00000002 35862d756322SRob Clark 35872d756322SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_PITCH 0x00008882 3588c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_PITCH__MASK 0x00000fff 35892d756322SRob Clark #define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT 0 35902d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val) 35912d756322SRob Clark { 35922d756322SRob Clark return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK; 35932d756322SRob Clark } 35942d756322SRob Clark 35952d756322SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH 0x00008883 3596c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK 0x00ffffff 35972d756322SRob Clark #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT 0 35982d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val) 35992d756322SRob Clark { 36002d756322SRob Clark return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK; 36012d756322SRob Clark } 36022d756322SRob Clark 3603c28c82e9SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_BASE 0x00008884 3604c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_BASE__MASK 0xffffffff 3605c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_BASE__SHIFT 0 3606c28c82e9SRob Clark static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE(uint32_t val) 3607c28c82e9SRob Clark { 3608c28c82e9SRob Clark return ((val) << A6XX_RB_STENCIL_BUFFER_BASE__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE__MASK; 3609c28c82e9SRob Clark } 3610c28c82e9SRob Clark 36112d756322SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM 0x00008886 3612c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK 0xfffff000 3613c28c82e9SRob Clark #define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT 12 3614c28c82e9SRob Clark static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE_GMEM(uint32_t val) 3615c28c82e9SRob Clark { 3616c28c82e9SRob Clark return ((val >> 12) << A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK; 3617c28c82e9SRob Clark } 36182d756322SRob Clark 36192d756322SRob Clark #define REG_A6XX_RB_STENCILREF 0x00008887 36202d756322SRob Clark #define A6XX_RB_STENCILREF_REF__MASK 0x000000ff 36212d756322SRob Clark #define A6XX_RB_STENCILREF_REF__SHIFT 0 36222d756322SRob Clark static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val) 36232d756322SRob Clark { 36242d756322SRob Clark return ((val) << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK; 36252d756322SRob Clark } 3626a69c5ed2SRob Clark #define A6XX_RB_STENCILREF_BFREF__MASK 0x0000ff00 3627a69c5ed2SRob Clark #define A6XX_RB_STENCILREF_BFREF__SHIFT 8 3628a69c5ed2SRob Clark static inline uint32_t A6XX_RB_STENCILREF_BFREF(uint32_t val) 3629a69c5ed2SRob Clark { 3630a69c5ed2SRob Clark return ((val) << A6XX_RB_STENCILREF_BFREF__SHIFT) & A6XX_RB_STENCILREF_BFREF__MASK; 3631a69c5ed2SRob Clark } 36322d756322SRob Clark 36332d756322SRob Clark #define REG_A6XX_RB_STENCILMASK 0x00008888 36342d756322SRob Clark #define A6XX_RB_STENCILMASK_MASK__MASK 0x000000ff 36352d756322SRob Clark #define A6XX_RB_STENCILMASK_MASK__SHIFT 0 36362d756322SRob Clark static inline uint32_t A6XX_RB_STENCILMASK_MASK(uint32_t val) 36372d756322SRob Clark { 36382d756322SRob Clark return ((val) << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK; 36392d756322SRob Clark } 3640a69c5ed2SRob Clark #define A6XX_RB_STENCILMASK_BFMASK__MASK 0x0000ff00 3641a69c5ed2SRob Clark #define A6XX_RB_STENCILMASK_BFMASK__SHIFT 8 3642a69c5ed2SRob Clark static inline uint32_t A6XX_RB_STENCILMASK_BFMASK(uint32_t val) 3643a69c5ed2SRob Clark { 3644a69c5ed2SRob Clark return ((val) << A6XX_RB_STENCILMASK_BFMASK__SHIFT) & A6XX_RB_STENCILMASK_BFMASK__MASK; 3645a69c5ed2SRob Clark } 36462d756322SRob Clark 36472d756322SRob Clark #define REG_A6XX_RB_STENCILWRMASK 0x00008889 36482d756322SRob Clark #define A6XX_RB_STENCILWRMASK_WRMASK__MASK 0x000000ff 36492d756322SRob Clark #define A6XX_RB_STENCILWRMASK_WRMASK__SHIFT 0 36502d756322SRob Clark static inline uint32_t A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val) 36512d756322SRob Clark { 36522d756322SRob Clark return ((val) << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK; 36532d756322SRob Clark } 3654a69c5ed2SRob Clark #define A6XX_RB_STENCILWRMASK_BFWRMASK__MASK 0x0000ff00 3655a69c5ed2SRob Clark #define A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT 8 3656a69c5ed2SRob Clark static inline uint32_t A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val) 3657a69c5ed2SRob Clark { 3658a69c5ed2SRob Clark return ((val) << A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_BFWRMASK__MASK; 3659a69c5ed2SRob Clark } 36602d756322SRob Clark 36612d756322SRob Clark #define REG_A6XX_RB_WINDOW_OFFSET 0x00008890 3662c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET_X__MASK 0x00003fff 36632d756322SRob Clark #define A6XX_RB_WINDOW_OFFSET_X__SHIFT 0 36642d756322SRob Clark static inline uint32_t A6XX_RB_WINDOW_OFFSET_X(uint32_t val) 36652d756322SRob Clark { 36662d756322SRob Clark return ((val) << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK; 36672d756322SRob Clark } 3668c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET_Y__MASK 0x3fff0000 36692d756322SRob Clark #define A6XX_RB_WINDOW_OFFSET_Y__SHIFT 16 36702d756322SRob Clark static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val) 36712d756322SRob Clark { 36722d756322SRob Clark return ((val) << A6XX_RB_WINDOW_OFFSET_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET_Y__MASK; 36732d756322SRob Clark } 36742d756322SRob Clark 36752d756322SRob Clark #define REG_A6XX_RB_SAMPLE_COUNT_CONTROL 0x00008891 3676c28c82e9SRob Clark #define A6XX_RB_SAMPLE_COUNT_CONTROL_UNK0 0x00000001 36772d756322SRob Clark #define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 36782d756322SRob Clark 3679ccdf7e28SRob Clark #define REG_A6XX_RB_LRZ_CNTL 0x00008898 3680ccdf7e28SRob Clark #define A6XX_RB_LRZ_CNTL_ENABLE 0x00000001 3681ccdf7e28SRob Clark 3682c28c82e9SRob Clark #define REG_A6XX_RB_Z_CLAMP_MIN 0x000088c0 3683c28c82e9SRob Clark #define A6XX_RB_Z_CLAMP_MIN__MASK 0xffffffff 3684c28c82e9SRob Clark #define A6XX_RB_Z_CLAMP_MIN__SHIFT 0 3685c28c82e9SRob Clark static inline uint32_t A6XX_RB_Z_CLAMP_MIN(float val) 3686c28c82e9SRob Clark { 3687c28c82e9SRob Clark return ((fui(val)) << A6XX_RB_Z_CLAMP_MIN__SHIFT) & A6XX_RB_Z_CLAMP_MIN__MASK; 3688c28c82e9SRob Clark } 3689c28c82e9SRob Clark 3690c28c82e9SRob Clark #define REG_A6XX_RB_Z_CLAMP_MAX 0x000088c1 3691c28c82e9SRob Clark #define A6XX_RB_Z_CLAMP_MAX__MASK 0xffffffff 3692c28c82e9SRob Clark #define A6XX_RB_Z_CLAMP_MAX__SHIFT 0 3693c28c82e9SRob Clark static inline uint32_t A6XX_RB_Z_CLAMP_MAX(float val) 3694c28c82e9SRob Clark { 3695c28c82e9SRob Clark return ((fui(val)) << A6XX_RB_Z_CLAMP_MAX__SHIFT) & A6XX_RB_Z_CLAMP_MAX__MASK; 3696c28c82e9SRob Clark } 3697c28c82e9SRob Clark 36982d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_88D0 0x000088d0 3699c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_88D0_UNK0__MASK 0x00001fff 3700c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT 0 3701c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK0(uint32_t val) 3702c28c82e9SRob Clark { 3703c28c82e9SRob Clark return ((val) << A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK0__MASK; 3704c28c82e9SRob Clark } 3705c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_88D0_UNK16__MASK 0x07ff0000 3706c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT 16 3707c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK16(uint32_t val) 3708c28c82e9SRob Clark { 3709c28c82e9SRob Clark return ((val) << A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK16__MASK; 3710c28c82e9SRob Clark } 37112d756322SRob Clark 37122d756322SRob Clark #define REG_A6XX_RB_BLIT_SCISSOR_TL 0x000088d1 3713c28c82e9SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_X__MASK 0x00003fff 37142d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT 0 37152d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val) 37162d756322SRob Clark { 37172d756322SRob Clark return ((val) << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK; 37182d756322SRob Clark } 3719c28c82e9SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK 0x3fff0000 37202d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT 16 37212d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val) 37222d756322SRob Clark { 37232d756322SRob Clark return ((val) << A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_Y__MASK; 37242d756322SRob Clark } 37252d756322SRob Clark 37262d756322SRob Clark #define REG_A6XX_RB_BLIT_SCISSOR_BR 0x000088d2 3727c28c82e9SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_X__MASK 0x00003fff 37282d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT 0 37292d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val) 37302d756322SRob Clark { 37312d756322SRob Clark return ((val) << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK; 37322d756322SRob Clark } 3733c28c82e9SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK 0x3fff0000 37342d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT 16 37352d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val) 37362d756322SRob Clark { 37372d756322SRob Clark return ((val) << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK; 37382d756322SRob Clark } 37392d756322SRob Clark 3740c28c82e9SRob Clark #define REG_A6XX_RB_BIN_CONTROL2 0x000088d3 3741c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL2_BINW__MASK 0x0000003f 3742c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL2_BINW__SHIFT 0 3743c28c82e9SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val) 3744c28c82e9SRob Clark { 3745c28c82e9SRob Clark return ((val >> 5) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK; 3746c28c82e9SRob Clark } 3747c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL2_BINH__MASK 0x00007f00 3748c28c82e9SRob Clark #define A6XX_RB_BIN_CONTROL2_BINH__SHIFT 8 3749c28c82e9SRob Clark static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val) 3750c28c82e9SRob Clark { 3751c28c82e9SRob Clark return ((val >> 4) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK; 3752c28c82e9SRob Clark } 3753c28c82e9SRob Clark 3754c28c82e9SRob Clark #define REG_A6XX_RB_WINDOW_OFFSET2 0x000088d4 3755c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET2_X__MASK 0x00003fff 3756c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET2_X__SHIFT 0 3757c28c82e9SRob Clark static inline uint32_t A6XX_RB_WINDOW_OFFSET2_X(uint32_t val) 3758c28c82e9SRob Clark { 3759c28c82e9SRob Clark return ((val) << A6XX_RB_WINDOW_OFFSET2_X__SHIFT) & A6XX_RB_WINDOW_OFFSET2_X__MASK; 3760c28c82e9SRob Clark } 3761c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET2_Y__MASK 0x3fff0000 3762c28c82e9SRob Clark #define A6XX_RB_WINDOW_OFFSET2_Y__SHIFT 16 3763c28c82e9SRob Clark static inline uint32_t A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val) 3764c28c82e9SRob Clark { 3765c28c82e9SRob Clark return ((val) << A6XX_RB_WINDOW_OFFSET2_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET2_Y__MASK; 3766c28c82e9SRob Clark } 3767c28c82e9SRob Clark 3768ccdf7e28SRob Clark #define REG_A6XX_RB_MSAA_CNTL 0x000088d5 3769ccdf7e28SRob Clark #define A6XX_RB_MSAA_CNTL_SAMPLES__MASK 0x00000018 3770ccdf7e28SRob Clark #define A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT 3 3771ccdf7e28SRob Clark static inline uint32_t A6XX_RB_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 3772ccdf7e28SRob Clark { 3773ccdf7e28SRob Clark return ((val) << A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_MSAA_CNTL_SAMPLES__MASK; 3774ccdf7e28SRob Clark } 3775ccdf7e28SRob Clark 37762d756322SRob Clark #define REG_A6XX_RB_BLIT_BASE_GMEM 0x000088d6 3777c28c82e9SRob Clark #define A6XX_RB_BLIT_BASE_GMEM__MASK 0xfffff000 3778c28c82e9SRob Clark #define A6XX_RB_BLIT_BASE_GMEM__SHIFT 12 3779c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_BASE_GMEM(uint32_t val) 3780c28c82e9SRob Clark { 3781c28c82e9SRob Clark return ((val >> 12) << A6XX_RB_BLIT_BASE_GMEM__SHIFT) & A6XX_RB_BLIT_BASE_GMEM__MASK; 3782c28c82e9SRob Clark } 37832d756322SRob Clark 37842d756322SRob Clark #define REG_A6XX_RB_BLIT_DST_INFO 0x000088d7 37852d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK 0x00000003 37862d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT 0 37872d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) 37882d756322SRob Clark { 37892d756322SRob Clark return ((val) << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK; 37902d756322SRob Clark } 37912d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_FLAGS 0x00000004 3792ccdf7e28SRob Clark #define A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK 0x00000018 3793ccdf7e28SRob Clark #define A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT 3 3794ccdf7e28SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) 3795ccdf7e28SRob Clark { 3796ccdf7e28SRob Clark return ((val) << A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK; 3797ccdf7e28SRob Clark } 37982d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK 0x00000060 37992d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT 5 38002d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) 38012d756322SRob Clark { 38022d756322SRob Clark return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK; 38032d756322SRob Clark } 3804c28c82e9SRob Clark #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK 0x00007f80 3805c28c82e9SRob Clark #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT 7 3806c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_format val) 3807c28c82e9SRob Clark { 3808c28c82e9SRob Clark return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK; 3809c28c82e9SRob Clark } 3810c28c82e9SRob Clark #define A6XX_RB_BLIT_DST_INFO_UNK15 0x00008000 3811c28c82e9SRob Clark 3812c28c82e9SRob Clark #define REG_A6XX_RB_BLIT_DST 0x000088d8 3813c28c82e9SRob Clark #define A6XX_RB_BLIT_DST__MASK 0xffffffff 3814c28c82e9SRob Clark #define A6XX_RB_BLIT_DST__SHIFT 0 3815c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_DST(uint32_t val) 3816c28c82e9SRob Clark { 3817c28c82e9SRob Clark return ((val) << A6XX_RB_BLIT_DST__SHIFT) & A6XX_RB_BLIT_DST__MASK; 3818c28c82e9SRob Clark } 38192d756322SRob Clark 38202d756322SRob Clark #define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da 3821c28c82e9SRob Clark #define A6XX_RB_BLIT_DST_PITCH__MASK 0x0000ffff 38222d756322SRob Clark #define A6XX_RB_BLIT_DST_PITCH__SHIFT 0 38232d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val) 38242d756322SRob Clark { 38252d756322SRob Clark return ((val >> 6) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK; 38262d756322SRob Clark } 38272d756322SRob Clark 38282d756322SRob Clark #define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH 0x000088db 3829c28c82e9SRob Clark #define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0x1fffffff 38302d756322SRob Clark #define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0 38312d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) 38322d756322SRob Clark { 38332d756322SRob Clark return ((val >> 6) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK; 38342d756322SRob Clark } 38352d756322SRob Clark 3836c28c82e9SRob Clark #define REG_A6XX_RB_BLIT_FLAG_DST 0x000088dc 3837c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST__MASK 0xffffffff 3838c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST__SHIFT 0 3839c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_FLAG_DST(uint32_t val) 3840c28c82e9SRob Clark { 3841c28c82e9SRob Clark return ((val) << A6XX_RB_BLIT_FLAG_DST__SHIFT) & A6XX_RB_BLIT_FLAG_DST__MASK; 3842c28c82e9SRob Clark } 3843c28c82e9SRob Clark 3844c28c82e9SRob Clark #define REG_A6XX_RB_BLIT_FLAG_DST_PITCH 0x000088de 3845c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK 0x000007ff 3846c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT 0 3847c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val) 3848c28c82e9SRob Clark { 3849c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK; 3850c28c82e9SRob Clark } 3851c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK 0x0ffff800 3852c28c82e9SRob Clark #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT 11 3853c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val) 3854c28c82e9SRob Clark { 3855c28c82e9SRob Clark return ((val >> 7) << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK; 3856c28c82e9SRob Clark } 3857c28c82e9SRob Clark 38582d756322SRob Clark #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 0x000088df 38592d756322SRob Clark 38602d756322SRob Clark #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1 0x000088e0 38612d756322SRob Clark 38622d756322SRob Clark #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2 0x000088e1 38632d756322SRob Clark 38642d756322SRob Clark #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3 0x000088e2 38652d756322SRob Clark 38662d756322SRob Clark #define REG_A6XX_RB_BLIT_INFO 0x000088e3 38672d756322SRob Clark #define A6XX_RB_BLIT_INFO_UNK0 0x00000001 3868a69c5ed2SRob Clark #define A6XX_RB_BLIT_INFO_GMEM 0x00000002 3869cc4c26d4SRob Clark #define A6XX_RB_BLIT_INFO_SAMPLE_0 0x00000004 3870a69c5ed2SRob Clark #define A6XX_RB_BLIT_INFO_DEPTH 0x00000008 3871a69c5ed2SRob Clark #define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK 0x000000f0 3872a69c5ed2SRob Clark #define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT 4 3873a69c5ed2SRob Clark static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val) 38742d756322SRob Clark { 3875a69c5ed2SRob Clark return ((val) << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK; 38762d756322SRob Clark } 3877c28c82e9SRob Clark #define A6XX_RB_BLIT_INFO_UNK8__MASK 0x00000300 3878c28c82e9SRob Clark #define A6XX_RB_BLIT_INFO_UNK8__SHIFT 8 3879c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_INFO_UNK8(uint32_t val) 3880c28c82e9SRob Clark { 3881c28c82e9SRob Clark return ((val) << A6XX_RB_BLIT_INFO_UNK8__SHIFT) & A6XX_RB_BLIT_INFO_UNK8__MASK; 3882c28c82e9SRob Clark } 3883c28c82e9SRob Clark #define A6XX_RB_BLIT_INFO_UNK12__MASK 0x0000f000 3884c28c82e9SRob Clark #define A6XX_RB_BLIT_INFO_UNK12__SHIFT 12 3885c28c82e9SRob Clark static inline uint32_t A6XX_RB_BLIT_INFO_UNK12(uint32_t val) 3886c28c82e9SRob Clark { 3887c28c82e9SRob Clark return ((val) << A6XX_RB_BLIT_INFO_UNK12__SHIFT) & A6XX_RB_BLIT_INFO_UNK12__MASK; 3888c28c82e9SRob Clark } 38892d756322SRob Clark 38902d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_88F0 0x000088f0 38912d756322SRob Clark 3892c28c82e9SRob Clark #define REG_A6XX_RB_UNK_FLAG_BUFFER_BASE 0x000088f1 3893c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK 0xffffffff 3894c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT 0 3895c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_BASE(uint32_t val) 3896c28c82e9SRob Clark { 3897c28c82e9SRob Clark return ((val) << A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK; 3898c28c82e9SRob Clark } 3899c28c82e9SRob Clark 3900c28c82e9SRob Clark #define REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH 0x000088f3 3901c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff 3902c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 3903c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(uint32_t val) 3904c28c82e9SRob Clark { 3905c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK; 3906c28c82e9SRob Clark } 3907c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x00fff800 3908c28c82e9SRob Clark #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 3909c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 3910c28c82e9SRob Clark { 3911c28c82e9SRob Clark return ((val >> 7) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; 3912c28c82e9SRob Clark } 3913c28c82e9SRob Clark 3914c28c82e9SRob Clark #define REG_A6XX_RB_UNKNOWN_88F4 0x000088f4 3915c28c82e9SRob Clark 3916c28c82e9SRob Clark #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE 0x00008900 3917c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK 0xffffffff 3918c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT 0 3919c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_BASE(uint32_t val) 3920c28c82e9SRob Clark { 3921c28c82e9SRob Clark return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK; 3922c28c82e9SRob Clark } 3923c28c82e9SRob Clark 39242d756322SRob Clark #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x00008902 3925c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK 0x0000007f 3926c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 3927c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val) 3928c28c82e9SRob Clark { 3929c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK; 3930c28c82e9SRob Clark } 3931c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK 0x00000700 3932c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT 8 3933c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8(uint32_t val) 3934c28c82e9SRob Clark { 3935c28c82e9SRob Clark return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK; 3936c28c82e9SRob Clark } 3937c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x0ffff800 3938c28c82e9SRob Clark #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 3939c28c82e9SRob Clark static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 3940c28c82e9SRob Clark { 3941c28c82e9SRob Clark return ((val >> 7) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; 3942c28c82e9SRob Clark } 39432d756322SRob Clark 39442d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; } 39452d756322SRob Clark 3946c28c82e9SRob Clark static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; } 3947c28c82e9SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK 0xffffffff 3948c28c82e9SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT 0 3949c28c82e9SRob Clark static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t val) 3950c28c82e9SRob Clark { 3951c28c82e9SRob Clark return ((val) << A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK; 3952c28c82e9SRob Clark } 3953c28c82e9SRob Clark 39542d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; } 39552d756322SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff 39562d756322SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 39572d756322SRob Clark static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val) 39582d756322SRob Clark { 3959c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK; 39602d756322SRob Clark } 3961c28c82e9SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffff800 39622d756322SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 39632d756322SRob Clark static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 39642d756322SRob Clark { 3965c28c82e9SRob Clark return ((val >> 7) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; 39662d756322SRob Clark } 39672d756322SRob Clark 3968c28c82e9SRob Clark #define REG_A6XX_RB_SAMPLE_COUNT_ADDR 0x00008927 3969c28c82e9SRob Clark #define A6XX_RB_SAMPLE_COUNT_ADDR__MASK 0xffffffff 3970c28c82e9SRob Clark #define A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT 0 3971c28c82e9SRob Clark static inline uint32_t A6XX_RB_SAMPLE_COUNT_ADDR(uint32_t val) 3972c28c82e9SRob Clark { 3973c28c82e9SRob Clark return ((val) << A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT) & A6XX_RB_SAMPLE_COUNT_ADDR__MASK; 3974c28c82e9SRob Clark } 3975c28c82e9SRob Clark 397657cfe41cSRob Clark #define REG_A6XX_RB_UNKNOWN_8A00 0x00008a00 397757cfe41cSRob Clark 397857cfe41cSRob Clark #define REG_A6XX_RB_UNKNOWN_8A10 0x00008a10 397957cfe41cSRob Clark 398057cfe41cSRob Clark #define REG_A6XX_RB_UNKNOWN_8A20 0x00008a20 398157cfe41cSRob Clark 398257cfe41cSRob Clark #define REG_A6XX_RB_UNKNOWN_8A30 0x00008a30 398357cfe41cSRob Clark 39842d756322SRob Clark #define REG_A6XX_RB_2D_BLIT_CNTL 0x00008c00 3985c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK 0x00000007 3986c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT 0 3987c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val) 3988c28c82e9SRob Clark { 3989c28c82e9SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK; 3990c28c82e9SRob Clark } 399157cfe41cSRob Clark #define A6XX_RB_2D_BLIT_CNTL_OVERWRITEEN 0x00000008 399257cfe41cSRob Clark #define A6XX_RB_2D_BLIT_CNTL_UNK4__MASK 0x00000070 399357cfe41cSRob Clark #define A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT 4 399457cfe41cSRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK4(uint32_t val) 3995c28c82e9SRob Clark { 399657cfe41cSRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK4__MASK; 3997c28c82e9SRob Clark } 3998c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR 0x00000080 39992d756322SRob Clark #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00 40002d756322SRob Clark #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8 4001c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val) 40022d756322SRob Clark { 40032d756322SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK; 40042d756322SRob Clark } 4005ccdf7e28SRob Clark #define A6XX_RB_2D_BLIT_CNTL_SCISSOR 0x00010000 4006c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_UNK17__MASK 0x00060000 4007c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT 17 4008c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK17(uint32_t val) 4009c28c82e9SRob Clark { 4010c28c82e9SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK17__MASK; 4011c28c82e9SRob Clark } 4012c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_D24S8 0x00080000 4013c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_MASK__MASK 0x00f00000 4014c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT 20 4015c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_MASK(uint32_t val) 4016c28c82e9SRob Clark { 4017c28c82e9SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_RB_2D_BLIT_CNTL_MASK__MASK; 4018c28c82e9SRob Clark } 4019c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_IFMT__MASK 0x1f000000 4020c28c82e9SRob Clark #define A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT 24 4021c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val) 4022c28c82e9SRob Clark { 4023c28c82e9SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_IFMT__MASK; 4024c28c82e9SRob Clark } 402557cfe41cSRob Clark #define A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK 0x20000000 402657cfe41cSRob Clark #define A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT 29 402757cfe41cSRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val) 4028c28c82e9SRob Clark { 402957cfe41cSRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK; 4030c28c82e9SRob Clark } 4031ccdf7e28SRob Clark 4032c28c82e9SRob Clark #define REG_A6XX_RB_2D_UNKNOWN_8C01 0x00008c01 40332d756322SRob Clark 40342d756322SRob Clark #define REG_A6XX_RB_2D_DST_INFO 0x00008c17 40352d756322SRob Clark #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff 40362d756322SRob Clark #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0 4037c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_format val) 40382d756322SRob Clark { 40392d756322SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK; 40402d756322SRob Clark } 40412d756322SRob Clark #define A6XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300 40422d756322SRob Clark #define A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8 40432d756322SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) 40442d756322SRob Clark { 40452d756322SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_2D_DST_INFO_TILE_MODE__MASK; 40462d756322SRob Clark } 40472d756322SRob Clark #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00 40482d756322SRob Clark #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10 40492d756322SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) 40502d756322SRob Clark { 40512d756322SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK; 40522d756322SRob Clark } 40532d756322SRob Clark #define A6XX_RB_2D_DST_INFO_FLAGS 0x00001000 4054c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_SRGB 0x00002000 4055c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_SAMPLES__MASK 0x0000c000 4056c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT 14 4057c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) 4058c28c82e9SRob Clark { 4059c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_2D_DST_INFO_SAMPLES__MASK; 4060c28c82e9SRob Clark } 4061c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_FILTER 0x00010000 4062cc4c26d4SRob Clark #define A6XX_RB_2D_DST_INFO_UNK17 0x00020000 4063c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE 0x00040000 4064cc4c26d4SRob Clark #define A6XX_RB_2D_DST_INFO_UNK19 0x00080000 4065c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_UNK20 0x00100000 4066cc4c26d4SRob Clark #define A6XX_RB_2D_DST_INFO_UNK21 0x00200000 4067c28c82e9SRob Clark #define A6XX_RB_2D_DST_INFO_UNK22 0x00400000 4068cc4c26d4SRob Clark #define A6XX_RB_2D_DST_INFO_UNK23__MASK 0x07800000 4069cc4c26d4SRob Clark #define A6XX_RB_2D_DST_INFO_UNK23__SHIFT 23 4070cc4c26d4SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_UNK23(uint32_t val) 4071cc4c26d4SRob Clark { 4072cc4c26d4SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_UNK23__SHIFT) & A6XX_RB_2D_DST_INFO_UNK23__MASK; 4073cc4c26d4SRob Clark } 4074cc4c26d4SRob Clark #define A6XX_RB_2D_DST_INFO_UNK28 0x10000000 40752d756322SRob Clark 4076c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST 0x00008c18 4077c28c82e9SRob Clark #define A6XX_RB_2D_DST__MASK 0xffffffff 4078c28c82e9SRob Clark #define A6XX_RB_2D_DST__SHIFT 0 4079c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST(uint32_t val) 40802d756322SRob Clark { 4081c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST__SHIFT) & A6XX_RB_2D_DST__MASK; 4082c28c82e9SRob Clark } 4083c28c82e9SRob Clark 4084c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_PITCH 0x00008c1a 4085c28c82e9SRob Clark #define A6XX_RB_2D_DST_PITCH__MASK 0x0000ffff 4086c28c82e9SRob Clark #define A6XX_RB_2D_DST_PITCH__SHIFT 0 4087c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_PITCH(uint32_t val) 4088c28c82e9SRob Clark { 4089c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_2D_DST_PITCH__SHIFT) & A6XX_RB_2D_DST_PITCH__MASK; 4090c28c82e9SRob Clark } 4091c28c82e9SRob Clark 4092c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_PLANE1 0x00008c1b 4093c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE1__MASK 0xffffffff 4094c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE1__SHIFT 0 4095c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_PLANE1(uint32_t val) 4096c28c82e9SRob Clark { 4097c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST_PLANE1__SHIFT) & A6XX_RB_2D_DST_PLANE1__MASK; 4098c28c82e9SRob Clark } 4099c28c82e9SRob Clark 4100c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_PLANE_PITCH 0x00008c1d 4101c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE_PITCH__MASK 0x0000ffff 4102c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE_PITCH__SHIFT 0 4103c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_PLANE_PITCH(uint32_t val) 4104c28c82e9SRob Clark { 4105c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_2D_DST_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_PLANE_PITCH__MASK; 4106c28c82e9SRob Clark } 4107c28c82e9SRob Clark 4108c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_PLANE2 0x00008c1e 4109c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE2__MASK 0xffffffff 4110c28c82e9SRob Clark #define A6XX_RB_2D_DST_PLANE2__SHIFT 0 4111c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_PLANE2(uint32_t val) 4112c28c82e9SRob Clark { 4113c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST_PLANE2__SHIFT) & A6XX_RB_2D_DST_PLANE2__MASK; 41142d756322SRob Clark } 41152d756322SRob Clark 4116c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_FLAGS 0x00008c20 4117c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS__MASK 0xffffffff 4118c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS__SHIFT 0 4119c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_FLAGS(uint32_t val) 4120c28c82e9SRob Clark { 4121c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST_FLAGS__SHIFT) & A6XX_RB_2D_DST_FLAGS__MASK; 4122c28c82e9SRob Clark } 4123c28c82e9SRob Clark 4124c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_FLAGS_PITCH 0x00008c22 4125c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PITCH__MASK 0x000000ff 4126c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT 0 4127c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_FLAGS_PITCH(uint32_t val) 4128c28c82e9SRob Clark { 4129c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH__MASK; 4130c28c82e9SRob Clark } 4131c28c82e9SRob Clark 4132c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_FLAGS_PLANE 0x00008c23 4133c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PLANE__MASK 0xffffffff 4134c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT 0 4135c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE(uint32_t val) 4136c28c82e9SRob Clark { 4137c28c82e9SRob Clark return ((val) << A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE__MASK; 4138c28c82e9SRob Clark } 4139c28c82e9SRob Clark 4140c28c82e9SRob Clark #define REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH 0x00008c25 4141c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK 0x000000ff 4142c28c82e9SRob Clark #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT 0 4143c28c82e9SRob Clark static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(uint32_t val) 4144c28c82e9SRob Clark { 4145c28c82e9SRob Clark return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK; 4146c28c82e9SRob Clark } 4147c28c82e9SRob Clark 41482d756322SRob Clark #define REG_A6XX_RB_2D_SRC_SOLID_C0 0x00008c2c 41492d756322SRob Clark 41502d756322SRob Clark #define REG_A6XX_RB_2D_SRC_SOLID_C1 0x00008c2d 41512d756322SRob Clark 41522d756322SRob Clark #define REG_A6XX_RB_2D_SRC_SOLID_C2 0x00008c2e 41532d756322SRob Clark 41542d756322SRob Clark #define REG_A6XX_RB_2D_SRC_SOLID_C3 0x00008c2f 41552d756322SRob Clark 41562d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8E01 0x00008e01 41572d756322SRob Clark 4158a69c5ed2SRob Clark #define REG_A6XX_RB_UNKNOWN_8E04 0x00008e04 4159a69c5ed2SRob Clark 4160c28c82e9SRob Clark #define REG_A6XX_RB_ADDR_MODE_CNTL 0x00008e05 4161c28c82e9SRob Clark 41622d756322SRob Clark #define REG_A6XX_RB_CCU_CNTL 0x00008e07 416357cfe41cSRob Clark #define A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK 0xff800000 416457cfe41cSRob Clark #define A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT 23 416557cfe41cSRob Clark static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_OFFSET(uint32_t val) 4166c28c82e9SRob Clark { 416757cfe41cSRob Clark return ((val >> 12) << A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK; 416857cfe41cSRob Clark } 416957cfe41cSRob Clark #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK 0x001ff000 417057cfe41cSRob Clark #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT 12 417157cfe41cSRob Clark static inline uint32_t A6XX_RB_CCU_CNTL_DEPTH_OFFSET(uint32_t val) 417257cfe41cSRob Clark { 417357cfe41cSRob Clark return ((val >> 12) << A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK; 4174c28c82e9SRob Clark } 4175c28c82e9SRob Clark #define A6XX_RB_CCU_CNTL_GMEM 0x00400000 4176c28c82e9SRob Clark #define A6XX_RB_CCU_CNTL_UNK2 0x00000004 41772d756322SRob Clark 4178c28c82e9SRob Clark #define REG_A6XX_RB_NC_MODE_CNTL 0x00008e08 4179c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_MODE 0x00000001 4180c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006 4181c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT 1 4182c28c82e9SRob Clark static inline uint32_t A6XX_RB_NC_MODE_CNTL_LOWER_BIT(uint32_t val) 4183c28c82e9SRob Clark { 4184c28c82e9SRob Clark return ((val) << A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK; 4185c28c82e9SRob Clark } 4186c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008 4187c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_AMSBC 0x00000010 4188c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000400 4189c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT 10 4190c28c82e9SRob Clark static inline uint32_t A6XX_RB_NC_MODE_CNTL_UPPER_BIT(uint32_t val) 4191c28c82e9SRob Clark { 4192c28c82e9SRob Clark return ((val) << A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK; 4193c28c82e9SRob Clark } 4194c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR 0x00000800 4195c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_UNK12__MASK 0x00003000 4196c28c82e9SRob Clark #define A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT 12 4197c28c82e9SRob Clark static inline uint32_t A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val) 4198c28c82e9SRob Clark { 4199c28c82e9SRob Clark return ((val) << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK; 4200c28c82e9SRob Clark } 42012d756322SRob Clark 4202cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RB_PERFCTR_RB_SEL(uint32_t i0) { return 0x00008e10 + 0x1*i0; } 4203c28c82e9SRob Clark 4204cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RB_PERFCTR_CCU_SEL(uint32_t i0) { return 0x00008e18 + 0x1*i0; } 4205c28c82e9SRob Clark 4206c28c82e9SRob Clark #define REG_A6XX_RB_UNKNOWN_8E28 0x00008e28 4207c28c82e9SRob Clark 4208cc4c26d4SRob Clark static inline uint32_t REG_A6XX_RB_PERFCTR_CMP_SEL(uint32_t i0) { return 0x00008e2c + 0x1*i0; } 4209c28c82e9SRob Clark 4210c28c82e9SRob Clark #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST 0x00008e3b 4211c28c82e9SRob Clark 4212c28c82e9SRob Clark #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD 0x00008e3d 4213c28c82e9SRob Clark 4214c28c82e9SRob Clark #define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x00008e50 4215c28c82e9SRob Clark 4216c28c82e9SRob Clark #define REG_A6XX_RB_UNKNOWN_8E51 0x00008e51 4217c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_8E51__MASK 0xffffffff 4218c28c82e9SRob Clark #define A6XX_RB_UNKNOWN_8E51__SHIFT 0 4219c28c82e9SRob Clark static inline uint32_t A6XX_RB_UNKNOWN_8E51(uint32_t val) 4220c28c82e9SRob Clark { 4221c28c82e9SRob Clark return ((val) << A6XX_RB_UNKNOWN_8E51__SHIFT) & A6XX_RB_UNKNOWN_8E51__MASK; 4222c28c82e9SRob Clark } 4223c28c82e9SRob Clark 422457cfe41cSRob Clark #define REG_A6XX_VPC_GS_PARAM 0x00009100 422557cfe41cSRob Clark #define A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK 0x000000ff 422657cfe41cSRob Clark #define A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT 0 422757cfe41cSRob Clark static inline uint32_t A6XX_VPC_GS_PARAM_LINELENGTHLOC(uint32_t val) 422857cfe41cSRob Clark { 422957cfe41cSRob Clark return ((val) << A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT) & A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK; 423057cfe41cSRob Clark } 4231c28c82e9SRob Clark 4232c28c82e9SRob Clark #define REG_A6XX_VPC_VS_CLIP_CNTL 0x00009101 4233c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff 4234c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT 0 4235c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(uint32_t val) 4236c28c82e9SRob Clark { 4237c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK; 4238c28c82e9SRob Clark } 4239c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00 4240c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8 4241c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) 4242c28c82e9SRob Clark { 4243c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK; 4244c28c82e9SRob Clark } 4245c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000 4246c28c82e9SRob Clark #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16 4247c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) 4248c28c82e9SRob Clark { 4249c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; 4250c28c82e9SRob Clark } 4251c28c82e9SRob Clark 4252c28c82e9SRob Clark #define REG_A6XX_VPC_GS_CLIP_CNTL 0x00009102 4253c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff 4254c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT 0 4255c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK(uint32_t val) 4256c28c82e9SRob Clark { 4257c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK; 4258c28c82e9SRob Clark } 4259c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00 4260c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8 4261c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) 4262c28c82e9SRob Clark { 4263c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK; 4264c28c82e9SRob Clark } 4265c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000 4266c28c82e9SRob Clark #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16 4267c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) 4268c28c82e9SRob Clark { 4269c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; 4270c28c82e9SRob Clark } 4271c28c82e9SRob Clark 4272c28c82e9SRob Clark #define REG_A6XX_VPC_DS_CLIP_CNTL 0x00009103 4273c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff 4274c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT 0 4275c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK(uint32_t val) 4276c28c82e9SRob Clark { 4277c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK; 4278c28c82e9SRob Clark } 4279c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00 4280c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8 4281c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) 4282c28c82e9SRob Clark { 4283c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK; 4284c28c82e9SRob Clark } 4285c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000 4286c28c82e9SRob Clark #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16 4287c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) 4288c28c82e9SRob Clark { 4289c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; 4290c28c82e9SRob Clark } 4291c28c82e9SRob Clark 4292c28c82e9SRob Clark #define REG_A6XX_VPC_VS_LAYER_CNTL 0x00009104 4293c28c82e9SRob Clark #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff 4294c28c82e9SRob Clark #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT 0 4295c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(uint32_t val) 4296c28c82e9SRob Clark { 4297c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK; 4298c28c82e9SRob Clark } 4299c28c82e9SRob Clark #define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00 4300c28c82e9SRob Clark #define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT 8 4301c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(uint32_t val) 4302c28c82e9SRob Clark { 4303c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK; 4304c28c82e9SRob Clark } 4305c28c82e9SRob Clark 4306c28c82e9SRob Clark #define REG_A6XX_VPC_GS_LAYER_CNTL 0x00009105 4307c28c82e9SRob Clark #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff 4308c28c82e9SRob Clark #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT 0 4309c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(uint32_t val) 4310c28c82e9SRob Clark { 4311c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK; 4312c28c82e9SRob Clark } 4313c28c82e9SRob Clark #define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00 4314c28c82e9SRob Clark #define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT 8 4315c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(uint32_t val) 4316c28c82e9SRob Clark { 4317c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK; 4318c28c82e9SRob Clark } 4319c28c82e9SRob Clark 4320c28c82e9SRob Clark #define REG_A6XX_VPC_DS_LAYER_CNTL 0x00009106 4321c28c82e9SRob Clark #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff 4322c28c82e9SRob Clark #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT 0 4323c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_LAYERLOC(uint32_t val) 4324c28c82e9SRob Clark { 4325c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK; 4326c28c82e9SRob Clark } 4327c28c82e9SRob Clark #define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00 4328c28c82e9SRob Clark #define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT 8 4329c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val) 4330c28c82e9SRob Clark { 4331c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK; 4332c28c82e9SRob Clark } 43332d756322SRob Clark 4334a69c5ed2SRob Clark #define REG_A6XX_VPC_UNKNOWN_9107 0x00009107 4335cc4c26d4SRob Clark #define A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD 0x00000001 4336cc4c26d4SRob Clark #define A6XX_VPC_UNKNOWN_9107_UNK2 0x00000004 4337a69c5ed2SRob Clark 4338c28c82e9SRob Clark #define REG_A6XX_VPC_POLYGON_MODE 0x00009108 4339c28c82e9SRob Clark #define A6XX_VPC_POLYGON_MODE_MODE__MASK 0x00000003 4340c28c82e9SRob Clark #define A6XX_VPC_POLYGON_MODE_MODE__SHIFT 0 4341c28c82e9SRob Clark static inline uint32_t A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) 4342c28c82e9SRob Clark { 4343c28c82e9SRob Clark return ((val) << A6XX_VPC_POLYGON_MODE_MODE__SHIFT) & A6XX_VPC_POLYGON_MODE_MODE__MASK; 4344c28c82e9SRob Clark } 43452d756322SRob Clark 43462d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; } 43472d756322SRob Clark 43482d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; } 43492d756322SRob Clark 43502d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; } 43512d756322SRob Clark 43522d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; } 43532d756322SRob Clark 43542d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9210 0x00009210 43552d756322SRob Clark 43562d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9211 0x00009211 43572d756322SRob Clark 43582d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; } 43592d756322SRob Clark 43602d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; } 43612d756322SRob Clark 43622d756322SRob Clark #define REG_A6XX_VPC_SO_CNTL 0x00009216 4363cc4c26d4SRob Clark #define A6XX_VPC_SO_CNTL_ADDR__MASK 0x000000ff 4364cc4c26d4SRob Clark #define A6XX_VPC_SO_CNTL_ADDR__SHIFT 0 4365cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_SO_CNTL_ADDR(uint32_t val) 4366c28c82e9SRob Clark { 4367cc4c26d4SRob Clark return ((val) << A6XX_VPC_SO_CNTL_ADDR__SHIFT) & A6XX_VPC_SO_CNTL_ADDR__MASK; 4368c28c82e9SRob Clark } 4369cc4c26d4SRob Clark #define A6XX_VPC_SO_CNTL_RESET 0x00010000 43702d756322SRob Clark 43712d756322SRob Clark #define REG_A6XX_VPC_SO_PROG 0x00009217 43722d756322SRob Clark #define A6XX_VPC_SO_PROG_A_BUF__MASK 0x00000003 43732d756322SRob Clark #define A6XX_VPC_SO_PROG_A_BUF__SHIFT 0 43742d756322SRob Clark static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val) 43752d756322SRob Clark { 43762d756322SRob Clark return ((val) << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK; 43772d756322SRob Clark } 43782d756322SRob Clark #define A6XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc 43792d756322SRob Clark #define A6XX_VPC_SO_PROG_A_OFF__SHIFT 2 43802d756322SRob Clark static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val) 43812d756322SRob Clark { 43822d756322SRob Clark return ((val >> 2) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK; 43832d756322SRob Clark } 43842d756322SRob Clark #define A6XX_VPC_SO_PROG_A_EN 0x00000800 43852d756322SRob Clark #define A6XX_VPC_SO_PROG_B_BUF__MASK 0x00003000 43862d756322SRob Clark #define A6XX_VPC_SO_PROG_B_BUF__SHIFT 12 43872d756322SRob Clark static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val) 43882d756322SRob Clark { 43892d756322SRob Clark return ((val) << A6XX_VPC_SO_PROG_B_BUF__SHIFT) & A6XX_VPC_SO_PROG_B_BUF__MASK; 43902d756322SRob Clark } 43912d756322SRob Clark #define A6XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000 43922d756322SRob Clark #define A6XX_VPC_SO_PROG_B_OFF__SHIFT 14 43932d756322SRob Clark static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val) 43942d756322SRob Clark { 43952d756322SRob Clark return ((val >> 2) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK; 43962d756322SRob Clark } 43972d756322SRob Clark #define A6XX_VPC_SO_PROG_B_EN 0x00800000 43982d756322SRob Clark 4399c28c82e9SRob Clark #define REG_A6XX_VPC_SO_STREAM_COUNTS 0x00009218 4400c28c82e9SRob Clark #define A6XX_VPC_SO_STREAM_COUNTS__MASK 0xffffffff 4401c28c82e9SRob Clark #define A6XX_VPC_SO_STREAM_COUNTS__SHIFT 0 4402c28c82e9SRob Clark static inline uint32_t A6XX_VPC_SO_STREAM_COUNTS(uint32_t val) 4403c28c82e9SRob Clark { 4404c28c82e9SRob Clark return ((val) << A6XX_VPC_SO_STREAM_COUNTS__SHIFT) & A6XX_VPC_SO_STREAM_COUNTS__MASK; 4405c28c82e9SRob Clark } 4406c28c82e9SRob Clark 44072d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; } 44082d756322SRob Clark 4409c28c82e9SRob Clark static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0) { return 0x0000921a + 0x7*i0; } 4410c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_BASE__MASK 0xffffffff 4411c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_BASE__SHIFT 0 4412c28c82e9SRob Clark static inline uint32_t A6XX_VPC_SO_BUFFER_BASE(uint32_t val) 4413c28c82e9SRob Clark { 4414c28c82e9SRob Clark return ((val) << A6XX_VPC_SO_BUFFER_BASE__SHIFT) & A6XX_VPC_SO_BUFFER_BASE__MASK; 4415c28c82e9SRob Clark } 4416c28c82e9SRob Clark 44172d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; } 4418c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_SIZE__MASK 0xfffffffc 4419c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_SIZE__SHIFT 2 4420c28c82e9SRob Clark static inline uint32_t A6XX_VPC_SO_BUFFER_SIZE(uint32_t val) 4421c28c82e9SRob Clark { 4422c28c82e9SRob Clark return ((val >> 2) << A6XX_VPC_SO_BUFFER_SIZE__SHIFT) & A6XX_VPC_SO_BUFFER_SIZE__MASK; 4423c28c82e9SRob Clark } 44242d756322SRob Clark 44252d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000921d + 0x7*i0; } 44262d756322SRob Clark 44272d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; } 4428c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_OFFSET__MASK 0xfffffffc 4429c28c82e9SRob Clark #define A6XX_VPC_SO_BUFFER_OFFSET__SHIFT 2 4430c28c82e9SRob Clark static inline uint32_t A6XX_VPC_SO_BUFFER_OFFSET(uint32_t val) 4431c28c82e9SRob Clark { 4432c28c82e9SRob Clark return ((val >> 2) << A6XX_VPC_SO_BUFFER_OFFSET__SHIFT) & A6XX_VPC_SO_BUFFER_OFFSET__MASK; 4433c28c82e9SRob Clark } 4434c28c82e9SRob Clark 4435c28c82e9SRob Clark static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0) { return 0x0000921f + 0x7*i0; } 4436c28c82e9SRob Clark #define A6XX_VPC_SO_FLUSH_BASE__MASK 0xffffffff 4437c28c82e9SRob Clark #define A6XX_VPC_SO_FLUSH_BASE__SHIFT 0 4438c28c82e9SRob Clark static inline uint32_t A6XX_VPC_SO_FLUSH_BASE(uint32_t val) 4439c28c82e9SRob Clark { 4440c28c82e9SRob Clark return ((val) << A6XX_VPC_SO_FLUSH_BASE__SHIFT) & A6XX_VPC_SO_FLUSH_BASE__MASK; 4441c28c82e9SRob Clark } 44422d756322SRob Clark 4443c28c82e9SRob Clark #define REG_A6XX_VPC_POINT_COORD_INVERT 0x00009236 4444c28c82e9SRob Clark #define A6XX_VPC_POINT_COORD_INVERT_INVERT 0x00000001 44452d756322SRob Clark 44462d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9300 0x00009300 44472d756322SRob Clark 4448c28c82e9SRob Clark #define REG_A6XX_VPC_VS_PACK 0x00009301 4449c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK 0x000000ff 4450c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT 0 4451c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_PACK_STRIDE_IN_VPC(uint32_t val) 44522d756322SRob Clark { 4453c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK; 44542d756322SRob Clark } 4455c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_POSITIONLOC__MASK 0x0000ff00 4456c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT 8 4457c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_PACK_POSITIONLOC(uint32_t val) 44582d756322SRob Clark { 4459c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_VS_PACK_POSITIONLOC__MASK; 44602d756322SRob Clark } 4461c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_PSIZELOC__MASK 0x00ff0000 4462c28c82e9SRob Clark #define A6XX_VPC_VS_PACK_PSIZELOC__SHIFT 16 4463c28c82e9SRob Clark static inline uint32_t A6XX_VPC_VS_PACK_PSIZELOC(uint32_t val) 44642d756322SRob Clark { 4465c28c82e9SRob Clark return ((val) << A6XX_VPC_VS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_VS_PACK_PSIZELOC__MASK; 4466c28c82e9SRob Clark } 4467cc4c26d4SRob Clark #define A6XX_VPC_VS_PACK_EXTRAPOS__MASK 0x0f000000 4468cc4c26d4SRob Clark #define A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT 24 4469cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_VS_PACK_EXTRAPOS(uint32_t val) 4470c28c82e9SRob Clark { 4471cc4c26d4SRob Clark return ((val) << A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_VS_PACK_EXTRAPOS__MASK; 4472c28c82e9SRob Clark } 4473c28c82e9SRob Clark 4474c28c82e9SRob Clark #define REG_A6XX_VPC_GS_PACK 0x00009302 4475c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK 0x000000ff 4476c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT 0 4477c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_PACK_STRIDE_IN_VPC(uint32_t val) 4478c28c82e9SRob Clark { 4479c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK; 4480c28c82e9SRob Clark } 4481c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_POSITIONLOC__MASK 0x0000ff00 4482c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT 8 4483c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_PACK_POSITIONLOC(uint32_t val) 4484c28c82e9SRob Clark { 4485c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_GS_PACK_POSITIONLOC__MASK; 4486c28c82e9SRob Clark } 4487c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_PSIZELOC__MASK 0x00ff0000 4488c28c82e9SRob Clark #define A6XX_VPC_GS_PACK_PSIZELOC__SHIFT 16 4489c28c82e9SRob Clark static inline uint32_t A6XX_VPC_GS_PACK_PSIZELOC(uint32_t val) 4490c28c82e9SRob Clark { 4491c28c82e9SRob Clark return ((val) << A6XX_VPC_GS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_GS_PACK_PSIZELOC__MASK; 4492c28c82e9SRob Clark } 4493cc4c26d4SRob Clark #define A6XX_VPC_GS_PACK_EXTRAPOS__MASK 0x0f000000 4494cc4c26d4SRob Clark #define A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT 24 4495cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_GS_PACK_EXTRAPOS(uint32_t val) 4496c28c82e9SRob Clark { 4497cc4c26d4SRob Clark return ((val) << A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_GS_PACK_EXTRAPOS__MASK; 4498c28c82e9SRob Clark } 4499c28c82e9SRob Clark 4500c28c82e9SRob Clark #define REG_A6XX_VPC_DS_PACK 0x00009303 4501c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK 0x000000ff 4502c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT 0 4503c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_PACK_STRIDE_IN_VPC(uint32_t val) 4504c28c82e9SRob Clark { 4505c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK; 4506c28c82e9SRob Clark } 4507c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_POSITIONLOC__MASK 0x0000ff00 4508c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT 8 4509c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_PACK_POSITIONLOC(uint32_t val) 4510c28c82e9SRob Clark { 4511c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_DS_PACK_POSITIONLOC__MASK; 4512c28c82e9SRob Clark } 4513c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_PSIZELOC__MASK 0x00ff0000 4514c28c82e9SRob Clark #define A6XX_VPC_DS_PACK_PSIZELOC__SHIFT 16 4515c28c82e9SRob Clark static inline uint32_t A6XX_VPC_DS_PACK_PSIZELOC(uint32_t val) 4516c28c82e9SRob Clark { 4517c28c82e9SRob Clark return ((val) << A6XX_VPC_DS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_DS_PACK_PSIZELOC__MASK; 4518c28c82e9SRob Clark } 4519cc4c26d4SRob Clark #define A6XX_VPC_DS_PACK_EXTRAPOS__MASK 0x0f000000 4520cc4c26d4SRob Clark #define A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT 24 4521cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_DS_PACK_EXTRAPOS(uint32_t val) 4522c28c82e9SRob Clark { 4523cc4c26d4SRob Clark return ((val) << A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_DS_PACK_EXTRAPOS__MASK; 45242d756322SRob Clark } 45252d756322SRob Clark 45262d756322SRob Clark #define REG_A6XX_VPC_CNTL_0 0x00009304 45272d756322SRob Clark #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK 0x000000ff 45282d756322SRob Clark #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT 0 45292d756322SRob Clark static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val) 45302d756322SRob Clark { 45312d756322SRob Clark return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK; 45322d756322SRob Clark } 4533c28c82e9SRob Clark #define A6XX_VPC_CNTL_0_PRIMIDLOC__MASK 0x0000ff00 4534c28c82e9SRob Clark #define A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT 8 4535c28c82e9SRob Clark static inline uint32_t A6XX_VPC_CNTL_0_PRIMIDLOC(uint32_t val) 4536c28c82e9SRob Clark { 4537c28c82e9SRob Clark return ((val) << A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT) & A6XX_VPC_CNTL_0_PRIMIDLOC__MASK; 4538c28c82e9SRob Clark } 45392d756322SRob Clark #define A6XX_VPC_CNTL_0_VARYING 0x00010000 4540cc4c26d4SRob Clark #define A6XX_VPC_CNTL_0_VIEWIDLOC__MASK 0xff000000 4541cc4c26d4SRob Clark #define A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT 24 4542cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_CNTL_0_VIEWIDLOC(uint32_t val) 4543c28c82e9SRob Clark { 4544cc4c26d4SRob Clark return ((val) << A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT) & A6XX_VPC_CNTL_0_VIEWIDLOC__MASK; 4545c28c82e9SRob Clark } 45462d756322SRob Clark 4547cc4c26d4SRob Clark #define REG_A6XX_VPC_SO_STREAM_CNTL 0x00009305 4548cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK 0x00000007 4549cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT 0 4550cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(uint32_t val) 4551c28c82e9SRob Clark { 4552cc4c26d4SRob Clark return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK; 4553cc4c26d4SRob Clark } 4554cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK 0x00000038 4555cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT 3 4556cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(uint32_t val) 4557cc4c26d4SRob Clark { 4558cc4c26d4SRob Clark return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK; 4559cc4c26d4SRob Clark } 4560cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK 0x000001c0 4561cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT 6 4562cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(uint32_t val) 4563cc4c26d4SRob Clark { 4564cc4c26d4SRob Clark return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK; 4565cc4c26d4SRob Clark } 4566cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK 0x00000e00 4567cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT 9 4568cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(uint32_t val) 4569cc4c26d4SRob Clark { 4570cc4c26d4SRob Clark return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK; 4571cc4c26d4SRob Clark } 4572cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK 0x00078000 4573cc4c26d4SRob Clark #define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT 15 4574cc4c26d4SRob Clark static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val) 4575cc4c26d4SRob Clark { 4576cc4c26d4SRob Clark return ((val) << A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK; 4577c28c82e9SRob Clark } 45782d756322SRob Clark 4579c28c82e9SRob Clark #define REG_A6XX_VPC_SO_DISABLE 0x00009306 4580c28c82e9SRob Clark #define A6XX_VPC_SO_DISABLE_DISABLE 0x00000001 4581a69c5ed2SRob Clark 45822d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9600 0x00009600 45832d756322SRob Clark 4584c28c82e9SRob Clark #define REG_A6XX_VPC_ADDR_MODE_CNTL 0x00009601 4585c28c82e9SRob Clark 45862d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9602 0x00009602 45872d756322SRob Clark 4588c28c82e9SRob Clark #define REG_A6XX_VPC_UNKNOWN_9603 0x00009603 4589c28c82e9SRob Clark 4590cc4c26d4SRob Clark static inline uint32_t REG_A6XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) { return 0x00009604 + 0x1*i0; } 4591c28c82e9SRob Clark 4592c28c82e9SRob Clark #define REG_A6XX_PC_TESS_NUM_VERTEX 0x00009800 4593c28c82e9SRob Clark 4594cc4c26d4SRob Clark #define REG_A6XX_PC_HS_INPUT_SIZE 0x00009801 4595cc4c26d4SRob Clark #define A6XX_PC_HS_INPUT_SIZE_SIZE__MASK 0x000007ff 4596cc4c26d4SRob Clark #define A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT 0 4597cc4c26d4SRob Clark static inline uint32_t A6XX_PC_HS_INPUT_SIZE_SIZE(uint32_t val) 4598c28c82e9SRob Clark { 4599cc4c26d4SRob Clark return ((val) << A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT) & A6XX_PC_HS_INPUT_SIZE_SIZE__MASK; 4600c28c82e9SRob Clark } 4601cc4c26d4SRob Clark #define A6XX_PC_HS_INPUT_SIZE_UNK13__MASK 0x00002000 4602cc4c26d4SRob Clark #define A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT 13 4603cc4c26d4SRob Clark static inline uint32_t A6XX_PC_HS_INPUT_SIZE_UNK13(uint32_t val) 4604c28c82e9SRob Clark { 4605cc4c26d4SRob Clark return ((val) << A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT) & A6XX_PC_HS_INPUT_SIZE_UNK13__MASK; 4606c28c82e9SRob Clark } 4607c28c82e9SRob Clark 4608c28c82e9SRob Clark #define REG_A6XX_PC_TESS_CNTL 0x00009802 4609c28c82e9SRob Clark #define A6XX_PC_TESS_CNTL_SPACING__MASK 0x00000003 4610c28c82e9SRob Clark #define A6XX_PC_TESS_CNTL_SPACING__SHIFT 0 4611c28c82e9SRob Clark static inline uint32_t A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val) 4612c28c82e9SRob Clark { 4613c28c82e9SRob Clark return ((val) << A6XX_PC_TESS_CNTL_SPACING__SHIFT) & A6XX_PC_TESS_CNTL_SPACING__MASK; 4614c28c82e9SRob Clark } 4615c28c82e9SRob Clark #define A6XX_PC_TESS_CNTL_OUTPUT__MASK 0x0000000c 4616c28c82e9SRob Clark #define A6XX_PC_TESS_CNTL_OUTPUT__SHIFT 2 4617c28c82e9SRob Clark static inline uint32_t A6XX_PC_TESS_CNTL_OUTPUT(enum a6xx_tess_output val) 4618c28c82e9SRob Clark { 4619c28c82e9SRob Clark return ((val) << A6XX_PC_TESS_CNTL_OUTPUT__SHIFT) & A6XX_PC_TESS_CNTL_OUTPUT__MASK; 4620c28c82e9SRob Clark } 46212d756322SRob Clark 46222d756322SRob Clark #define REG_A6XX_PC_RESTART_INDEX 0x00009803 46232d756322SRob Clark 46242d756322SRob Clark #define REG_A6XX_PC_MODE_CNTL 0x00009804 46252d756322SRob Clark 462657cfe41cSRob Clark #define REG_A6XX_PC_POWER_CNTL 0x00009805 46272d756322SRob Clark 4628c28c82e9SRob Clark #define REG_A6XX_PC_PRIMID_PASSTHRU 0x00009806 4629c28c82e9SRob Clark 463057cfe41cSRob Clark #define REG_A6XX_PC_SO_STREAM_CNTL 0x00009808 463157cfe41cSRob Clark #define A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE 0x00008000 463257cfe41cSRob Clark 463357cfe41cSRob Clark #define REG_A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL 0x0000980a 463457cfe41cSRob Clark #define A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN 0x00000001 463557cfe41cSRob Clark 4636c28c82e9SRob Clark #define REG_A6XX_PC_DRAW_CMD 0x00009840 4637c28c82e9SRob Clark #define A6XX_PC_DRAW_CMD_STATE_ID__MASK 0x000000ff 4638c28c82e9SRob Clark #define A6XX_PC_DRAW_CMD_STATE_ID__SHIFT 0 4639c28c82e9SRob Clark static inline uint32_t A6XX_PC_DRAW_CMD_STATE_ID(uint32_t val) 4640c28c82e9SRob Clark { 4641c28c82e9SRob Clark return ((val) << A6XX_PC_DRAW_CMD_STATE_ID__SHIFT) & A6XX_PC_DRAW_CMD_STATE_ID__MASK; 4642c28c82e9SRob Clark } 4643c28c82e9SRob Clark 4644c28c82e9SRob Clark #define REG_A6XX_PC_DISPATCH_CMD 0x00009841 4645c28c82e9SRob Clark #define A6XX_PC_DISPATCH_CMD_STATE_ID__MASK 0x000000ff 4646c28c82e9SRob Clark #define A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT 0 4647c28c82e9SRob Clark static inline uint32_t A6XX_PC_DISPATCH_CMD_STATE_ID(uint32_t val) 4648c28c82e9SRob Clark { 4649c28c82e9SRob Clark return ((val) << A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_PC_DISPATCH_CMD_STATE_ID__MASK; 4650c28c82e9SRob Clark } 4651c28c82e9SRob Clark 4652c28c82e9SRob Clark #define REG_A6XX_PC_EVENT_CMD 0x00009842 4653c28c82e9SRob Clark #define A6XX_PC_EVENT_CMD_STATE_ID__MASK 0x00ff0000 4654c28c82e9SRob Clark #define A6XX_PC_EVENT_CMD_STATE_ID__SHIFT 16 4655c28c82e9SRob Clark static inline uint32_t A6XX_PC_EVENT_CMD_STATE_ID(uint32_t val) 4656c28c82e9SRob Clark { 4657c28c82e9SRob Clark return ((val) << A6XX_PC_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_EVENT_CMD_STATE_ID__MASK; 4658c28c82e9SRob Clark } 4659c28c82e9SRob Clark #define A6XX_PC_EVENT_CMD_EVENT__MASK 0x0000007f 4660c28c82e9SRob Clark #define A6XX_PC_EVENT_CMD_EVENT__SHIFT 0 4661c28c82e9SRob Clark static inline uint32_t A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val) 4662c28c82e9SRob Clark { 4663c28c82e9SRob Clark return ((val) << A6XX_PC_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_EVENT_CMD_EVENT__MASK; 4664c28c82e9SRob Clark } 4665c28c82e9SRob Clark 4666cc4c26d4SRob Clark #define REG_A6XX_PC_MARKER 0x00009880 4667cc4c26d4SRob Clark 4668c28c82e9SRob Clark #define REG_A6XX_PC_POLYGON_MODE 0x00009981 4669c28c82e9SRob Clark #define A6XX_PC_POLYGON_MODE_MODE__MASK 0x00000003 4670c28c82e9SRob Clark #define A6XX_PC_POLYGON_MODE_MODE__SHIFT 0 4671c28c82e9SRob Clark static inline uint32_t A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) 4672c28c82e9SRob Clark { 4673c28c82e9SRob Clark return ((val) << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK; 4674c28c82e9SRob Clark } 4675a69c5ed2SRob Clark 4676cc4c26d4SRob Clark #define REG_A6XX_PC_RASTER_CNTL 0x00009980 4677cc4c26d4SRob Clark #define A6XX_PC_RASTER_CNTL_STREAM__MASK 0x00000003 4678cc4c26d4SRob Clark #define A6XX_PC_RASTER_CNTL_STREAM__SHIFT 0 4679cc4c26d4SRob Clark static inline uint32_t A6XX_PC_RASTER_CNTL_STREAM(uint32_t val) 4680cc4c26d4SRob Clark { 4681cc4c26d4SRob Clark return ((val) << A6XX_PC_RASTER_CNTL_STREAM__SHIFT) & A6XX_PC_RASTER_CNTL_STREAM__MASK; 4682cc4c26d4SRob Clark } 4683cc4c26d4SRob Clark #define A6XX_PC_RASTER_CNTL_DISCARD 0x00000004 4684a69c5ed2SRob Clark 46852d756322SRob Clark #define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00 46862d756322SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001 46872d756322SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002 4688c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_0_TESS_UPPER_LEFT_DOMAIN_ORIGIN 0x00000004 4689c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_0_UNK3 0x00000008 46902d756322SRob Clark 4691c28c82e9SRob Clark #define REG_A6XX_PC_VS_OUT_CNTL 0x00009b01 4692c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff 4693c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 4694c28c82e9SRob Clark static inline uint32_t A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) 46952d756322SRob Clark { 4696c28c82e9SRob Clark return ((val) << A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK; 46972d756322SRob Clark } 4698c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_PSIZE 0x00000100 4699c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_LAYER 0x00000200 4700c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_VIEW 0x00000400 4701c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID 0x00000800 4702c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 4703c28c82e9SRob Clark #define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT 16 4704c28c82e9SRob Clark static inline uint32_t A6XX_PC_VS_OUT_CNTL_CLIP_MASK(uint32_t val) 4705c28c82e9SRob Clark { 4706c28c82e9SRob Clark return ((val) << A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK; 4707c28c82e9SRob Clark } 47082d756322SRob Clark 4709c28c82e9SRob Clark #define REG_A6XX_PC_GS_OUT_CNTL 0x00009b02 4710c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff 4711c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 4712c28c82e9SRob Clark static inline uint32_t A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) 4713c28c82e9SRob Clark { 4714c28c82e9SRob Clark return ((val) << A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK; 4715c28c82e9SRob Clark } 4716c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_PSIZE 0x00000100 4717c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_LAYER 0x00000200 4718c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_VIEW 0x00000400 4719c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID 0x00000800 4720c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 4721c28c82e9SRob Clark #define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT 16 4722c28c82e9SRob Clark static inline uint32_t A6XX_PC_GS_OUT_CNTL_CLIP_MASK(uint32_t val) 4723c28c82e9SRob Clark { 4724c28c82e9SRob Clark return ((val) << A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK; 4725c28c82e9SRob Clark } 4726c28c82e9SRob Clark 472757cfe41cSRob Clark #define REG_A6XX_PC_HS_OUT_CNTL 0x00009b03 472857cfe41cSRob Clark #define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff 472957cfe41cSRob Clark #define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 473057cfe41cSRob Clark static inline uint32_t A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) 473157cfe41cSRob Clark { 473257cfe41cSRob Clark return ((val) << A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK; 473357cfe41cSRob Clark } 473457cfe41cSRob Clark #define A6XX_PC_HS_OUT_CNTL_PSIZE 0x00000100 473557cfe41cSRob Clark #define A6XX_PC_HS_OUT_CNTL_LAYER 0x00000200 473657cfe41cSRob Clark #define A6XX_PC_HS_OUT_CNTL_VIEW 0x00000400 473757cfe41cSRob Clark #define A6XX_PC_HS_OUT_CNTL_PRIMITIVE_ID 0x00000800 473857cfe41cSRob Clark #define A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 473957cfe41cSRob Clark #define A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT 16 474057cfe41cSRob Clark static inline uint32_t A6XX_PC_HS_OUT_CNTL_CLIP_MASK(uint32_t val) 474157cfe41cSRob Clark { 474257cfe41cSRob Clark return ((val) << A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK; 474357cfe41cSRob Clark } 4744c28c82e9SRob Clark 4745c28c82e9SRob Clark #define REG_A6XX_PC_DS_OUT_CNTL 0x00009b04 4746c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff 4747c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 4748c28c82e9SRob Clark static inline uint32_t A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) 4749c28c82e9SRob Clark { 4750c28c82e9SRob Clark return ((val) << A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK; 4751c28c82e9SRob Clark } 4752c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_PSIZE 0x00000100 4753c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_LAYER 0x00000200 4754c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_VIEW 0x00000400 4755c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID 0x00000800 4756c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 4757c28c82e9SRob Clark #define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT 16 4758c28c82e9SRob Clark static inline uint32_t A6XX_PC_DS_OUT_CNTL_CLIP_MASK(uint32_t val) 4759c28c82e9SRob Clark { 4760c28c82e9SRob Clark return ((val) << A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK; 4761c28c82e9SRob Clark } 4762c28c82e9SRob Clark 4763c28c82e9SRob Clark #define REG_A6XX_PC_PRIMITIVE_CNTL_5 0x00009b05 4764c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK 0x000000ff 4765c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT 0 4766c28c82e9SRob Clark static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val) 4767c28c82e9SRob Clark { 4768c28c82e9SRob Clark return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK; 4769c28c82e9SRob Clark } 4770c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK 0x00007c00 4771c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT 10 4772c28c82e9SRob Clark static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val) 4773c28c82e9SRob Clark { 4774c28c82e9SRob Clark return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK; 4775c28c82e9SRob Clark } 477657cfe41cSRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_LINELENGTHEN 0x00008000 4777c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK 0x00030000 4778c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT 16 4779c28c82e9SRob Clark static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val) 4780c28c82e9SRob Clark { 4781c28c82e9SRob Clark return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK; 4782c28c82e9SRob Clark } 4783c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK 0x00040000 4784c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT 18 4785c28c82e9SRob Clark static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_UNK18(uint32_t val) 4786c28c82e9SRob Clark { 4787c28c82e9SRob Clark return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK; 4788c28c82e9SRob Clark } 4789c28c82e9SRob Clark 4790c28c82e9SRob Clark #define REG_A6XX_PC_PRIMITIVE_CNTL_6 0x00009b06 4791c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK 0x000007ff 4792c28c82e9SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT 0 4793c28c82e9SRob Clark static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(uint32_t val) 4794c28c82e9SRob Clark { 4795c28c82e9SRob Clark return ((val) << A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK; 4796c28c82e9SRob Clark } 47972d756322SRob Clark 4798cc4c26d4SRob Clark #define REG_A6XX_PC_MULTIVIEW_CNTL 0x00009b07 4799cc4c26d4SRob Clark #define A6XX_PC_MULTIVIEW_CNTL_ENABLE 0x00000001 4800cc4c26d4SRob Clark #define A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002 4801cc4c26d4SRob Clark #define A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c 4802cc4c26d4SRob Clark #define A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT 2 4803cc4c26d4SRob Clark static inline uint32_t A6XX_PC_MULTIVIEW_CNTL_VIEWS(uint32_t val) 4804cc4c26d4SRob Clark { 4805cc4c26d4SRob Clark return ((val) << A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK; 4806cc4c26d4SRob Clark } 48072d756322SRob Clark 4808cc4c26d4SRob Clark #define REG_A6XX_PC_MULTIVIEW_MASK 0x00009b08 4809c28c82e9SRob Clark 4810c28c82e9SRob Clark #define REG_A6XX_PC_2D_EVENT_CMD 0x00009c00 4811c28c82e9SRob Clark #define A6XX_PC_2D_EVENT_CMD_EVENT__MASK 0x0000007f 4812c28c82e9SRob Clark #define A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT 0 4813c28c82e9SRob Clark static inline uint32_t A6XX_PC_2D_EVENT_CMD_EVENT(enum vgt_event_type val) 4814c28c82e9SRob Clark { 4815c28c82e9SRob Clark return ((val) << A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_2D_EVENT_CMD_EVENT__MASK; 4816c28c82e9SRob Clark } 4817c28c82e9SRob Clark #define A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00 4818c28c82e9SRob Clark #define A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT 8 4819c28c82e9SRob Clark static inline uint32_t A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val) 4820c28c82e9SRob Clark { 4821c28c82e9SRob Clark return ((val) << A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK; 4822c28c82e9SRob Clark } 4823c28c82e9SRob Clark 4824c28c82e9SRob Clark #define REG_A6XX_PC_DBG_ECO_CNTL 0x00009e00 4825c28c82e9SRob Clark 4826c28c82e9SRob Clark #define REG_A6XX_PC_ADDR_MODE_CNTL 0x00009e01 4827c28c82e9SRob Clark 4828cc4c26d4SRob Clark #define REG_A6XX_PC_DRAW_INDX_BASE 0x00009e04 48292d756322SRob Clark 4830cc4c26d4SRob Clark #define REG_A6XX_PC_DRAW_FIRST_INDX 0x00009e06 4831cc4c26d4SRob Clark 4832cc4c26d4SRob Clark #define REG_A6XX_PC_DRAW_MAX_INDICES 0x00009e07 48332d756322SRob Clark 4834c28c82e9SRob Clark #define REG_A6XX_PC_TESSFACTOR_ADDR 0x00009e08 4835c28c82e9SRob Clark #define A6XX_PC_TESSFACTOR_ADDR__MASK 0xffffffff 4836c28c82e9SRob Clark #define A6XX_PC_TESSFACTOR_ADDR__SHIFT 0 4837c28c82e9SRob Clark static inline uint32_t A6XX_PC_TESSFACTOR_ADDR(uint32_t val) 4838c28c82e9SRob Clark { 4839c28c82e9SRob Clark return ((val) << A6XX_PC_TESSFACTOR_ADDR__SHIFT) & A6XX_PC_TESSFACTOR_ADDR__MASK; 4840c28c82e9SRob Clark } 4841c28c82e9SRob Clark 4842cc4c26d4SRob Clark #define REG_A6XX_PC_DRAW_INITIATOR 0x00009e0b 4843cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f 4844cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 4845cc4c26d4SRob Clark static inline uint32_t A6XX_PC_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) 4846cc4c26d4SRob Clark { 4847cc4c26d4SRob Clark return ((val) << A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK; 4848cc4c26d4SRob Clark } 4849cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 4850cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 4851cc4c26d4SRob Clark static inline uint32_t A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) 4852cc4c26d4SRob Clark { 4853cc4c26d4SRob Clark return ((val) << A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK; 4854cc4c26d4SRob Clark } 4855cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK 0x00000300 4856cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT 8 4857cc4c26d4SRob Clark static inline uint32_t A6XX_PC_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) 4858cc4c26d4SRob Clark { 4859cc4c26d4SRob Clark return ((val) << A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT) & A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK; 4860cc4c26d4SRob Clark } 4861cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000c00 4862cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT 10 4863cc4c26d4SRob Clark static inline uint32_t A6XX_PC_DRAW_INITIATOR_INDEX_SIZE(enum a4xx_index_size val) 4864cc4c26d4SRob Clark { 4865cc4c26d4SRob Clark return ((val) << A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK; 4866cc4c26d4SRob Clark } 4867cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK 0x00003000 4868cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT 12 4869cc4c26d4SRob Clark static inline uint32_t A6XX_PC_DRAW_INITIATOR_PATCH_TYPE(enum a6xx_patch_type val) 4870cc4c26d4SRob Clark { 4871cc4c26d4SRob Clark return ((val) << A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK; 4872cc4c26d4SRob Clark } 4873cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_GS_ENABLE 0x00010000 4874cc4c26d4SRob Clark #define A6XX_PC_DRAW_INITIATOR_TESS_ENABLE 0x00020000 4875cc4c26d4SRob Clark 4876cc4c26d4SRob Clark #define REG_A6XX_PC_DRAW_NUM_INSTANCES 0x00009e0c 4877cc4c26d4SRob Clark 4878cc4c26d4SRob Clark #define REG_A6XX_PC_DRAW_NUM_INDICES 0x00009e0d 4879cc4c26d4SRob Clark 4880c28c82e9SRob Clark #define REG_A6XX_PC_VSTREAM_CONTROL 0x00009e11 4881c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_UNK0__MASK 0x0000ffff 4882c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT 0 4883c28c82e9SRob Clark static inline uint32_t A6XX_PC_VSTREAM_CONTROL_UNK0(uint32_t val) 4884c28c82e9SRob Clark { 4885c28c82e9SRob Clark return ((val) << A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT) & A6XX_PC_VSTREAM_CONTROL_UNK0__MASK; 4886c28c82e9SRob Clark } 4887c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK 0x003f0000 4888c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT 16 4889c28c82e9SRob Clark static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_SIZE(uint32_t val) 4890c28c82e9SRob Clark { 4891c28c82e9SRob Clark return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK; 4892c28c82e9SRob Clark } 4893c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK 0x07c00000 4894c28c82e9SRob Clark #define A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT 22 4895c28c82e9SRob Clark static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_N(uint32_t val) 4896c28c82e9SRob Clark { 4897c28c82e9SRob Clark return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK; 4898c28c82e9SRob Clark } 4899c28c82e9SRob Clark 4900c28c82e9SRob Clark #define REG_A6XX_PC_BIN_PRIM_STRM 0x00009e12 4901c28c82e9SRob Clark #define A6XX_PC_BIN_PRIM_STRM__MASK 0xffffffff 4902c28c82e9SRob Clark #define A6XX_PC_BIN_PRIM_STRM__SHIFT 0 4903c28c82e9SRob Clark static inline uint32_t A6XX_PC_BIN_PRIM_STRM(uint32_t val) 4904c28c82e9SRob Clark { 4905c28c82e9SRob Clark return ((val) << A6XX_PC_BIN_PRIM_STRM__SHIFT) & A6XX_PC_BIN_PRIM_STRM__MASK; 4906c28c82e9SRob Clark } 4907c28c82e9SRob Clark 4908c28c82e9SRob Clark #define REG_A6XX_PC_BIN_DRAW_STRM 0x00009e14 4909c28c82e9SRob Clark #define A6XX_PC_BIN_DRAW_STRM__MASK 0xffffffff 4910c28c82e9SRob Clark #define A6XX_PC_BIN_DRAW_STRM__SHIFT 0 4911c28c82e9SRob Clark static inline uint32_t A6XX_PC_BIN_DRAW_STRM(uint32_t val) 4912c28c82e9SRob Clark { 4913c28c82e9SRob Clark return ((val) << A6XX_PC_BIN_DRAW_STRM__SHIFT) & A6XX_PC_BIN_DRAW_STRM__MASK; 4914c28c82e9SRob Clark } 4915c28c82e9SRob Clark 4916cc4c26d4SRob Clark #define REG_A6XX_PC_VISIBILITY_OVERRIDE 0x00009e1c 4917cc4c26d4SRob Clark #define A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE 0x00000001 4918c28c82e9SRob Clark 4919cc4c26d4SRob Clark static inline uint32_t REG_A6XX_PC_PERFCTR_PC_SEL(uint32_t i0) { return 0x00009e34 + 0x1*i0; } 4920c28c82e9SRob Clark 49212d756322SRob Clark #define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72 49222d756322SRob Clark 49232d756322SRob Clark #define REG_A6XX_VFD_CONTROL_0 0x0000a000 4924c28c82e9SRob Clark #define A6XX_VFD_CONTROL_0_FETCH_CNT__MASK 0x0000003f 4925c28c82e9SRob Clark #define A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT 0 4926c28c82e9SRob Clark static inline uint32_t A6XX_VFD_CONTROL_0_FETCH_CNT(uint32_t val) 49272d756322SRob Clark { 4928c28c82e9SRob Clark return ((val) << A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT) & A6XX_VFD_CONTROL_0_FETCH_CNT__MASK; 4929c28c82e9SRob Clark } 4930c28c82e9SRob Clark #define A6XX_VFD_CONTROL_0_DECODE_CNT__MASK 0x00003f00 4931c28c82e9SRob Clark #define A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT 8 4932c28c82e9SRob Clark static inline uint32_t A6XX_VFD_CONTROL_0_DECODE_CNT(uint32_t val) 4933c28c82e9SRob Clark { 4934c28c82e9SRob Clark return ((val) << A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT) & A6XX_VFD_CONTROL_0_DECODE_CNT__MASK; 49352d756322SRob Clark } 49362d756322SRob Clark 49372d756322SRob Clark #define REG_A6XX_VFD_CONTROL_1 0x0000a001 49382d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff 49392d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0 49402d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 49412d756322SRob Clark { 49422d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VTX__MASK; 49432d756322SRob Clark } 49442d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00 49452d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4INST__SHIFT 8 49462d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 49472d756322SRob Clark { 49482d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK; 49492d756322SRob Clark } 49502d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000 49512d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16 49522d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val) 49532d756322SRob Clark { 49542d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK; 49552d756322SRob Clark } 4956cc4c26d4SRob Clark #define A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK 0xff000000 4957cc4c26d4SRob Clark #define A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT 24 4958cc4c26d4SRob Clark static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VIEWID(uint32_t val) 4959cc4c26d4SRob Clark { 4960cc4c26d4SRob Clark return ((val) << A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK; 4961cc4c26d4SRob Clark } 49622d756322SRob Clark 49632d756322SRob Clark #define REG_A6XX_VFD_CONTROL_2 0x0000a002 496457cfe41cSRob Clark #define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK 0x000000ff 496557cfe41cSRob Clark #define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT 0 496657cfe41cSRob Clark static inline uint32_t A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID(uint32_t val) 49672d756322SRob Clark { 496857cfe41cSRob Clark return ((val) << A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK; 4969c28c82e9SRob Clark } 4970c28c82e9SRob Clark #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK 0x0000ff00 4971c28c82e9SRob Clark #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT 8 4972c28c82e9SRob Clark static inline uint32_t A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val) 4973c28c82e9SRob Clark { 4974c28c82e9SRob Clark return ((val) << A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK; 49752d756322SRob Clark } 49762d756322SRob Clark 49772d756322SRob Clark #define REG_A6XX_VFD_CONTROL_3 0x0000a003 497857cfe41cSRob Clark #define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK 0x000000ff 497957cfe41cSRob Clark #define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT 0 498057cfe41cSRob Clark static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPRIMID(uint32_t val) 4981cc4c26d4SRob Clark { 498257cfe41cSRob Clark return ((val) << A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK; 4983cc4c26d4SRob Clark } 498457cfe41cSRob Clark #define A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK 0x0000ff00 498557cfe41cSRob Clark #define A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT 8 498657cfe41cSRob Clark static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID(uint32_t val) 49872d756322SRob Clark { 498857cfe41cSRob Clark return ((val) << A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK; 49892d756322SRob Clark } 49902d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000 49912d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16 49922d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) 49932d756322SRob Clark { 49942d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSX__MASK; 49952d756322SRob Clark } 49962d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000 49972d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24 49982d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) 49992d756322SRob Clark { 50002d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK; 50012d756322SRob Clark } 50022d756322SRob Clark 50032d756322SRob Clark #define REG_A6XX_VFD_CONTROL_4 0x0000a004 5004cc4c26d4SRob Clark #define A6XX_VFD_CONTROL_4_UNK0__MASK 0x000000ff 5005cc4c26d4SRob Clark #define A6XX_VFD_CONTROL_4_UNK0__SHIFT 0 5006cc4c26d4SRob Clark static inline uint32_t A6XX_VFD_CONTROL_4_UNK0(uint32_t val) 5007cc4c26d4SRob Clark { 5008cc4c26d4SRob Clark return ((val) << A6XX_VFD_CONTROL_4_UNK0__SHIFT) & A6XX_VFD_CONTROL_4_UNK0__MASK; 5009cc4c26d4SRob Clark } 50102d756322SRob Clark 50112d756322SRob Clark #define REG_A6XX_VFD_CONTROL_5 0x0000a005 5012c28c82e9SRob Clark #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK 0x000000ff 5013c28c82e9SRob Clark #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT 0 5014c28c82e9SRob Clark static inline uint32_t A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val) 5015c28c82e9SRob Clark { 5016c28c82e9SRob Clark return ((val) << A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT) & A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK; 5017c28c82e9SRob Clark } 5018cc4c26d4SRob Clark #define A6XX_VFD_CONTROL_5_UNK8__MASK 0x0000ff00 5019cc4c26d4SRob Clark #define A6XX_VFD_CONTROL_5_UNK8__SHIFT 8 5020cc4c26d4SRob Clark static inline uint32_t A6XX_VFD_CONTROL_5_UNK8(uint32_t val) 5021cc4c26d4SRob Clark { 5022cc4c26d4SRob Clark return ((val) << A6XX_VFD_CONTROL_5_UNK8__SHIFT) & A6XX_VFD_CONTROL_5_UNK8__MASK; 5023cc4c26d4SRob Clark } 50242d756322SRob Clark 50252d756322SRob Clark #define REG_A6XX_VFD_CONTROL_6 0x0000a006 5026c28c82e9SRob Clark #define A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU 0x00000001 50272d756322SRob Clark 50282d756322SRob Clark #define REG_A6XX_VFD_MODE_CNTL 0x0000a007 502957cfe41cSRob Clark #define A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK 0x00000007 503057cfe41cSRob Clark #define A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT 0 503157cfe41cSRob Clark static inline uint32_t A6XX_VFD_MODE_CNTL_RENDER_MODE(enum a6xx_render_mode val) 503257cfe41cSRob Clark { 503357cfe41cSRob Clark return ((val) << A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT) & A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK; 503457cfe41cSRob Clark } 50352d756322SRob Clark 5036cc4c26d4SRob Clark #define REG_A6XX_VFD_MULTIVIEW_CNTL 0x0000a008 5037cc4c26d4SRob Clark #define A6XX_VFD_MULTIVIEW_CNTL_ENABLE 0x00000001 5038cc4c26d4SRob Clark #define A6XX_VFD_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002 5039cc4c26d4SRob Clark #define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c 5040cc4c26d4SRob Clark #define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT 2 5041cc4c26d4SRob Clark static inline uint32_t A6XX_VFD_MULTIVIEW_CNTL_VIEWS(uint32_t val) 5042cc4c26d4SRob Clark { 5043cc4c26d4SRob Clark return ((val) << A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK; 5044cc4c26d4SRob Clark } 50452d756322SRob Clark 5046c28c82e9SRob Clark #define REG_A6XX_VFD_ADD_OFFSET 0x0000a009 5047c28c82e9SRob Clark #define A6XX_VFD_ADD_OFFSET_VERTEX 0x00000001 5048c28c82e9SRob Clark #define A6XX_VFD_ADD_OFFSET_INSTANCE 0x00000002 5049a69c5ed2SRob Clark 50502d756322SRob Clark #define REG_A6XX_VFD_INDEX_OFFSET 0x0000a00e 50512d756322SRob Clark 50522d756322SRob Clark #define REG_A6XX_VFD_INSTANCE_START_OFFSET 0x0000a00f 50532d756322SRob Clark 50542d756322SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; } 50552d756322SRob Clark 5056c28c82e9SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; } 5057cc4c26d4SRob Clark #define A6XX_VFD_FETCH_BASE__MASK 0xffffffff 5058cc4c26d4SRob Clark #define A6XX_VFD_FETCH_BASE__SHIFT 0 5059cc4c26d4SRob Clark static inline uint32_t A6XX_VFD_FETCH_BASE(uint32_t val) 5060cc4c26d4SRob Clark { 5061cc4c26d4SRob Clark return ((val) << A6XX_VFD_FETCH_BASE__SHIFT) & A6XX_VFD_FETCH_BASE__MASK; 5062cc4c26d4SRob Clark } 50632d756322SRob Clark 50642d756322SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; } 50652d756322SRob Clark 50662d756322SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; } 50672d756322SRob Clark 50682d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; } 50692d756322SRob Clark 50702d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; } 50712d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f 50722d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_IDX__SHIFT 0 50732d756322SRob Clark static inline uint32_t A6XX_VFD_DECODE_INSTR_IDX(uint32_t val) 50742d756322SRob Clark { 50752d756322SRob Clark return ((val) << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK; 50762d756322SRob Clark } 5077c28c82e9SRob Clark #define A6XX_VFD_DECODE_INSTR_OFFSET__MASK 0x0001ffe0 5078c28c82e9SRob Clark #define A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT 5 5079c28c82e9SRob Clark static inline uint32_t A6XX_VFD_DECODE_INSTR_OFFSET(uint32_t val) 5080c28c82e9SRob Clark { 5081c28c82e9SRob Clark return ((val) << A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT) & A6XX_VFD_DECODE_INSTR_OFFSET__MASK; 5082c28c82e9SRob Clark } 50832d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_INSTANCED 0x00020000 50842d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000 50852d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20 5086c28c82e9SRob Clark static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_format val) 50872d756322SRob Clark { 50882d756322SRob Clark return ((val) << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK; 50892d756322SRob Clark } 50902d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000 50912d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_SWAP__SHIFT 28 50922d756322SRob Clark static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 50932d756322SRob Clark { 50942d756322SRob Clark return ((val) << A6XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A6XX_VFD_DECODE_INSTR_SWAP__MASK; 50952d756322SRob Clark } 50962d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_UNK30 0x40000000 50972d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_FLOAT 0x80000000 50982d756322SRob Clark 50992d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; } 51002d756322SRob Clark 51012d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } 51022d756322SRob Clark 51032d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } 51042d756322SRob Clark #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f 51052d756322SRob Clark #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0 51062d756322SRob Clark static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val) 51072d756322SRob Clark { 51082d756322SRob Clark return ((val) << A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK; 51092d756322SRob Clark } 51102d756322SRob Clark #define A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0 51112d756322SRob Clark #define A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4 51122d756322SRob Clark static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) 51132d756322SRob Clark { 51142d756322SRob Clark return ((val) << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK; 51152d756322SRob Clark } 51162d756322SRob Clark 511757cfe41cSRob Clark #define REG_A6XX_VFD_POWER_CNTL 0x0000a0f8 51182d756322SRob Clark 5119cc4c26d4SRob Clark #define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601 5120cc4c26d4SRob Clark 5121cc4c26d4SRob Clark static inline uint32_t REG_A6XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) { return 0x0000a610 + 0x1*i0; } 5122cc4c26d4SRob Clark 5123c28c82e9SRob Clark #define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800 5124cc4c26d4SRob Clark #define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x00100000 5125cc4c26d4SRob Clark #define A6XX_SP_VS_CTRL_REG0_UNK21 0x00200000 5126cc4c26d4SRob Clark #define A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 5127cc4c26d4SRob Clark #define A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 5128cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 5129cc4c26d4SRob Clark { 5130cc4c26d4SRob Clark return ((val) << A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK; 5131cc4c26d4SRob Clark } 5132c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 5133c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 5134c28c82e9SRob Clark static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 51352d756322SRob Clark { 5136c28c82e9SRob Clark return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 5137c28c82e9SRob Clark } 5138c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 5139c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 5140c28c82e9SRob Clark static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 5141c28c82e9SRob Clark { 5142c28c82e9SRob Clark return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 5143c28c82e9SRob Clark } 5144cc4c26d4SRob Clark #define A6XX_SP_VS_CTRL_REG0_UNK13 0x00002000 5145c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 5146c28c82e9SRob Clark #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14 5147c28c82e9SRob Clark static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val) 5148c28c82e9SRob Clark { 5149c28c82e9SRob Clark return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK; 5150c28c82e9SRob Clark } 5151c28c82e9SRob Clark 5152c28c82e9SRob Clark #define REG_A6XX_SP_VS_BRANCH_COND 0x0000a801 5153c28c82e9SRob Clark 5154c28c82e9SRob Clark #define REG_A6XX_SP_VS_PRIMITIVE_CNTL 0x0000a802 5155c28c82e9SRob Clark #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f 5156c28c82e9SRob Clark #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT 0 5157c28c82e9SRob Clark static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_OUT(uint32_t val) 5158c28c82e9SRob Clark { 5159c28c82e9SRob Clark return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK; 51602d756322SRob Clark } 5161cc4c26d4SRob Clark #define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0 5162cc4c26d4SRob Clark #define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6 5163cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) 5164cc4c26d4SRob Clark { 5165cc4c26d4SRob Clark return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; 5166cc4c26d4SRob Clark } 51672d756322SRob Clark 51682d756322SRob Clark static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; } 51692d756322SRob Clark 51702d756322SRob Clark static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; } 51712d756322SRob Clark #define A6XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff 51722d756322SRob Clark #define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 51732d756322SRob Clark static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 51742d756322SRob Clark { 51752d756322SRob Clark return ((val) << A6XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_A_REGID__MASK; 51762d756322SRob Clark } 51772d756322SRob Clark #define A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00 51782d756322SRob Clark #define A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8 51792d756322SRob Clark static inline uint32_t A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 51802d756322SRob Clark { 51812d756322SRob Clark return ((val) << A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 51822d756322SRob Clark } 51832d756322SRob Clark #define A6XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000 51842d756322SRob Clark #define A6XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 51852d756322SRob Clark static inline uint32_t A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 51862d756322SRob Clark { 51872d756322SRob Clark return ((val) << A6XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_B_REGID__MASK; 51882d756322SRob Clark } 51892d756322SRob Clark #define A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000 51902d756322SRob Clark #define A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24 51912d756322SRob Clark static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 51922d756322SRob Clark { 51932d756322SRob Clark return ((val) << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 51942d756322SRob Clark } 51952d756322SRob Clark 51962d756322SRob Clark static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; } 51972d756322SRob Clark 51982d756322SRob Clark static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; } 51992d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 52002d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 52012d756322SRob Clark static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 52022d756322SRob Clark { 52032d756322SRob Clark return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 52042d756322SRob Clark } 52052d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 52062d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 52072d756322SRob Clark static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 52082d756322SRob Clark { 52092d756322SRob Clark return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 52102d756322SRob Clark } 52112d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 52122d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 52132d756322SRob Clark static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 52142d756322SRob Clark { 52152d756322SRob Clark return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 52162d756322SRob Clark } 52172d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 52182d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 52192d756322SRob Clark static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 52202d756322SRob Clark { 52212d756322SRob Clark return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 52222d756322SRob Clark } 52232d756322SRob Clark 5224cc4c26d4SRob Clark #define REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET 0x0000a81b 5225a69c5ed2SRob Clark 5226cc4c26d4SRob Clark #define REG_A6XX_SP_VS_OBJ_START 0x0000a81c 5227cc4c26d4SRob Clark #define A6XX_SP_VS_OBJ_START__MASK 0xffffffff 5228cc4c26d4SRob Clark #define A6XX_SP_VS_OBJ_START__SHIFT 0 5229cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_OBJ_START(uint32_t val) 5230cc4c26d4SRob Clark { 5231cc4c26d4SRob Clark return ((val) << A6XX_SP_VS_OBJ_START__SHIFT) & A6XX_SP_VS_OBJ_START__MASK; 5232cc4c26d4SRob Clark } 52332d756322SRob Clark 5234cc4c26d4SRob Clark #define REG_A6XX_SP_VS_PVT_MEM_PARAM 0x0000a81e 5235cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 5236cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 5237cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 5238cc4c26d4SRob Clark { 5239cc4c26d4SRob Clark return ((val >> 9) << A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 5240cc4c26d4SRob Clark } 5241cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 5242cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 5243cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 5244cc4c26d4SRob Clark { 5245cc4c26d4SRob Clark return ((val) << A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 5246cc4c26d4SRob Clark } 5247cc4c26d4SRob Clark 5248cc4c26d4SRob Clark #define REG_A6XX_SP_VS_PVT_MEM_ADDR 0x0000a81f 5249cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_ADDR__MASK 0xffffffff 5250cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_ADDR__SHIFT 0 5251cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_PVT_MEM_ADDR(uint32_t val) 5252cc4c26d4SRob Clark { 5253cc4c26d4SRob Clark return ((val) << A6XX_SP_VS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_VS_PVT_MEM_ADDR__MASK; 5254cc4c26d4SRob Clark } 5255cc4c26d4SRob Clark 5256cc4c26d4SRob Clark #define REG_A6XX_SP_VS_PVT_MEM_SIZE 0x0000a821 5257cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 5258cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 5259cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 5260cc4c26d4SRob Clark { 5261cc4c26d4SRob Clark return ((val >> 12) << A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 5262cc4c26d4SRob Clark } 5263cc4c26d4SRob Clark #define A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 52642d756322SRob Clark 52652d756322SRob Clark #define REG_A6XX_SP_VS_TEX_COUNT 0x0000a822 52662d756322SRob Clark 52672d756322SRob Clark #define REG_A6XX_SP_VS_CONFIG 0x0000a823 5268c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_BINDLESS_TEX 0x00000001 5269c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_BINDLESS_SAMP 0x00000002 5270c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_BINDLESS_IBO 0x00000004 5271c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_BINDLESS_UBO 0x00000008 52722d756322SRob Clark #define A6XX_SP_VS_CONFIG_ENABLED 0x00000100 52732d756322SRob Clark #define A6XX_SP_VS_CONFIG_NTEX__MASK 0x0001fe00 52742d756322SRob Clark #define A6XX_SP_VS_CONFIG_NTEX__SHIFT 9 52752d756322SRob Clark static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val) 52762d756322SRob Clark { 52772d756322SRob Clark return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK; 52782d756322SRob Clark } 5279c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_NSAMP__MASK 0x003e0000 52802d756322SRob Clark #define A6XX_SP_VS_CONFIG_NSAMP__SHIFT 17 52812d756322SRob Clark static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val) 52822d756322SRob Clark { 52832d756322SRob Clark return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK; 52842d756322SRob Clark } 5285cc4c26d4SRob Clark #define A6XX_SP_VS_CONFIG_NIBO__MASK 0x1fc00000 5286c28c82e9SRob Clark #define A6XX_SP_VS_CONFIG_NIBO__SHIFT 22 5287c28c82e9SRob Clark static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val) 5288c28c82e9SRob Clark { 5289c28c82e9SRob Clark return ((val) << A6XX_SP_VS_CONFIG_NIBO__SHIFT) & A6XX_SP_VS_CONFIG_NIBO__MASK; 5290c28c82e9SRob Clark } 52912d756322SRob Clark 52922d756322SRob Clark #define REG_A6XX_SP_VS_INSTRLEN 0x0000a824 52932d756322SRob Clark 5294cc4c26d4SRob Clark #define REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET 0x0000a825 529557cfe41cSRob Clark #define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 529657cfe41cSRob Clark #define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 529757cfe41cSRob Clark static inline uint32_t A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 5298cc4c26d4SRob Clark { 529957cfe41cSRob Clark return ((val >> 11) << A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 5300cc4c26d4SRob Clark } 5301cc4c26d4SRob Clark 53022d756322SRob Clark #define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830 5303cc4c26d4SRob Clark #define A6XX_SP_HS_CTRL_REG0_UNK20 0x00100000 5304cc4c26d4SRob Clark #define A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK 0x00000001 5305cc4c26d4SRob Clark #define A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT 0 5306cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 5307cc4c26d4SRob Clark { 5308cc4c26d4SRob Clark return ((val) << A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK; 5309cc4c26d4SRob Clark } 53102d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 53112d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 53122d756322SRob Clark static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 53132d756322SRob Clark { 53142d756322SRob Clark return ((val) << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 53152d756322SRob Clark } 53162d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 53172d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 53182d756322SRob Clark static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 53192d756322SRob Clark { 53202d756322SRob Clark return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 53212d756322SRob Clark } 5322cc4c26d4SRob Clark #define A6XX_SP_HS_CTRL_REG0_UNK13 0x00002000 53232d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 53242d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 14 53252d756322SRob Clark static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val) 53262d756322SRob Clark { 53272d756322SRob Clark return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK; 53282d756322SRob Clark } 5329cc4c26d4SRob Clark 5330cc4c26d4SRob Clark #define REG_A6XX_SP_HS_WAVE_INPUT_SIZE 0x0000a831 5331cc4c26d4SRob Clark 5332cc4c26d4SRob Clark #define REG_A6XX_SP_HS_BRANCH_COND 0x0000a832 5333cc4c26d4SRob Clark 5334cc4c26d4SRob Clark #define REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET 0x0000a833 5335cc4c26d4SRob Clark 5336cc4c26d4SRob Clark #define REG_A6XX_SP_HS_OBJ_START 0x0000a834 5337cc4c26d4SRob Clark #define A6XX_SP_HS_OBJ_START__MASK 0xffffffff 5338cc4c26d4SRob Clark #define A6XX_SP_HS_OBJ_START__SHIFT 0 5339cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_OBJ_START(uint32_t val) 53402d756322SRob Clark { 5341cc4c26d4SRob Clark return ((val) << A6XX_SP_HS_OBJ_START__SHIFT) & A6XX_SP_HS_OBJ_START__MASK; 53422d756322SRob Clark } 53432d756322SRob Clark 5344cc4c26d4SRob Clark #define REG_A6XX_SP_HS_PVT_MEM_PARAM 0x0000a836 5345cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 5346cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 5347cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 5348cc4c26d4SRob Clark { 5349cc4c26d4SRob Clark return ((val >> 9) << A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 5350cc4c26d4SRob Clark } 5351cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 5352cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 5353cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 5354cc4c26d4SRob Clark { 5355cc4c26d4SRob Clark return ((val) << A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 5356cc4c26d4SRob Clark } 53572d756322SRob Clark 5358cc4c26d4SRob Clark #define REG_A6XX_SP_HS_PVT_MEM_ADDR 0x0000a837 5359cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_ADDR__MASK 0xffffffff 5360cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_ADDR__SHIFT 0 5361cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_PVT_MEM_ADDR(uint32_t val) 5362cc4c26d4SRob Clark { 5363cc4c26d4SRob Clark return ((val) << A6XX_SP_HS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_HS_PVT_MEM_ADDR__MASK; 5364cc4c26d4SRob Clark } 5365c28c82e9SRob Clark 5366cc4c26d4SRob Clark #define REG_A6XX_SP_HS_PVT_MEM_SIZE 0x0000a839 5367cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 5368cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 5369cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 5370cc4c26d4SRob Clark { 5371cc4c26d4SRob Clark return ((val >> 12) << A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 5372cc4c26d4SRob Clark } 5373cc4c26d4SRob Clark #define A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 53742d756322SRob Clark 53752d756322SRob Clark #define REG_A6XX_SP_HS_TEX_COUNT 0x0000a83a 53762d756322SRob Clark 53772d756322SRob Clark #define REG_A6XX_SP_HS_CONFIG 0x0000a83b 5378c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_BINDLESS_TEX 0x00000001 5379c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_BINDLESS_SAMP 0x00000002 5380c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_BINDLESS_IBO 0x00000004 5381c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_BINDLESS_UBO 0x00000008 53822d756322SRob Clark #define A6XX_SP_HS_CONFIG_ENABLED 0x00000100 53832d756322SRob Clark #define A6XX_SP_HS_CONFIG_NTEX__MASK 0x0001fe00 53842d756322SRob Clark #define A6XX_SP_HS_CONFIG_NTEX__SHIFT 9 53852d756322SRob Clark static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val) 53862d756322SRob Clark { 53872d756322SRob Clark return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK; 53882d756322SRob Clark } 5389c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_NSAMP__MASK 0x003e0000 53902d756322SRob Clark #define A6XX_SP_HS_CONFIG_NSAMP__SHIFT 17 53912d756322SRob Clark static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val) 53922d756322SRob Clark { 53932d756322SRob Clark return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK; 53942d756322SRob Clark } 5395cc4c26d4SRob Clark #define A6XX_SP_HS_CONFIG_NIBO__MASK 0x1fc00000 5396c28c82e9SRob Clark #define A6XX_SP_HS_CONFIG_NIBO__SHIFT 22 5397c28c82e9SRob Clark static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val) 5398c28c82e9SRob Clark { 5399c28c82e9SRob Clark return ((val) << A6XX_SP_HS_CONFIG_NIBO__SHIFT) & A6XX_SP_HS_CONFIG_NIBO__MASK; 5400c28c82e9SRob Clark } 54012d756322SRob Clark 54022d756322SRob Clark #define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c 54032d756322SRob Clark 5404cc4c26d4SRob Clark #define REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET 0x0000a83d 540557cfe41cSRob Clark #define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 540657cfe41cSRob Clark #define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 540757cfe41cSRob Clark static inline uint32_t A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 5408cc4c26d4SRob Clark { 540957cfe41cSRob Clark return ((val >> 11) << A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 5410cc4c26d4SRob Clark } 5411cc4c26d4SRob Clark 54122d756322SRob Clark #define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840 5413cc4c26d4SRob Clark #define A6XX_SP_DS_CTRL_REG0_MERGEDREGS 0x00100000 5414cc4c26d4SRob Clark #define A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK 0x00000001 5415cc4c26d4SRob Clark #define A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT 0 5416cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 5417cc4c26d4SRob Clark { 5418cc4c26d4SRob Clark return ((val) << A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK; 5419cc4c26d4SRob Clark } 54202d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 54212d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 54222d756322SRob Clark static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 54232d756322SRob Clark { 54242d756322SRob Clark return ((val) << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 54252d756322SRob Clark } 54262d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 54272d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 54282d756322SRob Clark static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 54292d756322SRob Clark { 54302d756322SRob Clark return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 54312d756322SRob Clark } 5432cc4c26d4SRob Clark #define A6XX_SP_DS_CTRL_REG0_UNK13 0x00002000 54332d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 54342d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 14 54352d756322SRob Clark static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val) 54362d756322SRob Clark { 54372d756322SRob Clark return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK; 54382d756322SRob Clark } 5439cc4c26d4SRob Clark 5440cc4c26d4SRob Clark #define REG_A6XX_SP_DS_BRANCH_COND 0x0000a841 54412d756322SRob Clark 5442c28c82e9SRob Clark #define REG_A6XX_SP_DS_PRIMITIVE_CNTL 0x0000a842 5443c28c82e9SRob Clark #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f 5444c28c82e9SRob Clark #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT 0 5445c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_OUT(uint32_t val) 5446c28c82e9SRob Clark { 5447c28c82e9SRob Clark return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK; 5448c28c82e9SRob Clark } 5449cc4c26d4SRob Clark #define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0 5450cc4c26d4SRob Clark #define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6 5451cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) 5452cc4c26d4SRob Clark { 5453cc4c26d4SRob Clark return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; 5454cc4c26d4SRob Clark } 5455c28c82e9SRob Clark 5456c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; } 5457c28c82e9SRob Clark 5458c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000a843 + 0x1*i0; } 5459c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_A_REGID__MASK 0x000000ff 5460c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_A_REGID__SHIFT 0 5461c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_OUT_REG_A_REGID(uint32_t val) 5462c28c82e9SRob Clark { 5463c28c82e9SRob Clark return ((val) << A6XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_A_REGID__MASK; 5464c28c82e9SRob Clark } 5465c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00000f00 5466c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 8 5467c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val) 5468c28c82e9SRob Clark { 5469c28c82e9SRob Clark return ((val) << A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK; 5470c28c82e9SRob Clark } 5471c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_B_REGID__MASK 0x00ff0000 5472c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_B_REGID__SHIFT 16 5473c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_OUT_REG_B_REGID(uint32_t val) 5474c28c82e9SRob Clark { 5475c28c82e9SRob Clark return ((val) << A6XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_B_REGID__MASK; 5476c28c82e9SRob Clark } 5477c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x0f000000 5478c28c82e9SRob Clark #define A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 24 5479c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val) 5480c28c82e9SRob Clark { 5481c28c82e9SRob Clark return ((val) << A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK; 5482c28c82e9SRob Clark } 5483c28c82e9SRob Clark 5484c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000a853 + 0x1*i0; } 5485c28c82e9SRob Clark 5486c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000a853 + 0x1*i0; } 5487c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 5488c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0 5489c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val) 5490c28c82e9SRob Clark { 5491c28c82e9SRob Clark return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK; 5492c28c82e9SRob Clark } 5493c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 5494c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8 5495c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val) 5496c28c82e9SRob Clark { 5497c28c82e9SRob Clark return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK; 5498c28c82e9SRob Clark } 5499c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 5500c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16 5501c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val) 5502c28c82e9SRob Clark { 5503c28c82e9SRob Clark return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK; 5504c28c82e9SRob Clark } 5505c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 5506c28c82e9SRob Clark #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24 5507c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) 5508c28c82e9SRob Clark { 5509c28c82e9SRob Clark return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK; 5510c28c82e9SRob Clark } 5511c28c82e9SRob Clark 5512cc4c26d4SRob Clark #define REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET 0x0000a85b 5513c28c82e9SRob Clark 5514cc4c26d4SRob Clark #define REG_A6XX_SP_DS_OBJ_START 0x0000a85c 5515cc4c26d4SRob Clark #define A6XX_SP_DS_OBJ_START__MASK 0xffffffff 5516cc4c26d4SRob Clark #define A6XX_SP_DS_OBJ_START__SHIFT 0 5517cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_OBJ_START(uint32_t val) 5518cc4c26d4SRob Clark { 5519cc4c26d4SRob Clark return ((val) << A6XX_SP_DS_OBJ_START__SHIFT) & A6XX_SP_DS_OBJ_START__MASK; 5520cc4c26d4SRob Clark } 55212d756322SRob Clark 5522cc4c26d4SRob Clark #define REG_A6XX_SP_DS_PVT_MEM_PARAM 0x0000a85e 5523cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 5524cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 5525cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 5526cc4c26d4SRob Clark { 5527cc4c26d4SRob Clark return ((val >> 9) << A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 5528cc4c26d4SRob Clark } 5529cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 5530cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 5531cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 5532cc4c26d4SRob Clark { 5533cc4c26d4SRob Clark return ((val) << A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 5534cc4c26d4SRob Clark } 5535cc4c26d4SRob Clark 5536cc4c26d4SRob Clark #define REG_A6XX_SP_DS_PVT_MEM_ADDR 0x0000a85f 5537cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_ADDR__MASK 0xffffffff 5538cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_ADDR__SHIFT 0 5539cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_PVT_MEM_ADDR(uint32_t val) 5540cc4c26d4SRob Clark { 5541cc4c26d4SRob Clark return ((val) << A6XX_SP_DS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_DS_PVT_MEM_ADDR__MASK; 5542cc4c26d4SRob Clark } 5543cc4c26d4SRob Clark 5544cc4c26d4SRob Clark #define REG_A6XX_SP_DS_PVT_MEM_SIZE 0x0000a861 5545cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 5546cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 5547cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 5548cc4c26d4SRob Clark { 5549cc4c26d4SRob Clark return ((val >> 12) << A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 5550cc4c26d4SRob Clark } 5551cc4c26d4SRob Clark #define A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 55522d756322SRob Clark 55532d756322SRob Clark #define REG_A6XX_SP_DS_TEX_COUNT 0x0000a862 55542d756322SRob Clark 55552d756322SRob Clark #define REG_A6XX_SP_DS_CONFIG 0x0000a863 5556c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_BINDLESS_TEX 0x00000001 5557c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_BINDLESS_SAMP 0x00000002 5558c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_BINDLESS_IBO 0x00000004 5559c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_BINDLESS_UBO 0x00000008 55602d756322SRob Clark #define A6XX_SP_DS_CONFIG_ENABLED 0x00000100 55612d756322SRob Clark #define A6XX_SP_DS_CONFIG_NTEX__MASK 0x0001fe00 55622d756322SRob Clark #define A6XX_SP_DS_CONFIG_NTEX__SHIFT 9 55632d756322SRob Clark static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val) 55642d756322SRob Clark { 55652d756322SRob Clark return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK; 55662d756322SRob Clark } 5567c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_NSAMP__MASK 0x003e0000 55682d756322SRob Clark #define A6XX_SP_DS_CONFIG_NSAMP__SHIFT 17 55692d756322SRob Clark static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val) 55702d756322SRob Clark { 55712d756322SRob Clark return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK; 55722d756322SRob Clark } 5573cc4c26d4SRob Clark #define A6XX_SP_DS_CONFIG_NIBO__MASK 0x1fc00000 5574c28c82e9SRob Clark #define A6XX_SP_DS_CONFIG_NIBO__SHIFT 22 5575c28c82e9SRob Clark static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val) 5576c28c82e9SRob Clark { 5577c28c82e9SRob Clark return ((val) << A6XX_SP_DS_CONFIG_NIBO__SHIFT) & A6XX_SP_DS_CONFIG_NIBO__MASK; 5578c28c82e9SRob Clark } 55792d756322SRob Clark 55802d756322SRob Clark #define REG_A6XX_SP_DS_INSTRLEN 0x0000a864 55812d756322SRob Clark 5582cc4c26d4SRob Clark #define REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET 0x0000a865 558357cfe41cSRob Clark #define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 558457cfe41cSRob Clark #define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 558557cfe41cSRob Clark static inline uint32_t A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 5586cc4c26d4SRob Clark { 558757cfe41cSRob Clark return ((val >> 11) << A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 5588cc4c26d4SRob Clark } 5589cc4c26d4SRob Clark 55902d756322SRob Clark #define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870 5591cc4c26d4SRob Clark #define A6XX_SP_GS_CTRL_REG0_UNK20 0x00100000 5592cc4c26d4SRob Clark #define A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK 0x00000001 5593cc4c26d4SRob Clark #define A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT 0 5594cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 5595cc4c26d4SRob Clark { 5596cc4c26d4SRob Clark return ((val) << A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK; 5597cc4c26d4SRob Clark } 55982d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 55992d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 56002d756322SRob Clark static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 56012d756322SRob Clark { 56022d756322SRob Clark return ((val) << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 56032d756322SRob Clark } 56042d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 56052d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 56062d756322SRob Clark static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 56072d756322SRob Clark { 56082d756322SRob Clark return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 56092d756322SRob Clark } 5610cc4c26d4SRob Clark #define A6XX_SP_GS_CTRL_REG0_UNK13 0x00002000 56112d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 56122d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 14 56132d756322SRob Clark static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val) 56142d756322SRob Clark { 56152d756322SRob Clark return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK; 56162d756322SRob Clark } 56172d756322SRob Clark 5618c28c82e9SRob Clark #define REG_A6XX_SP_GS_PRIM_SIZE 0x0000a871 5619c28c82e9SRob Clark 5620c28c82e9SRob Clark #define REG_A6XX_SP_GS_BRANCH_COND 0x0000a872 5621c28c82e9SRob Clark 5622c28c82e9SRob Clark #define REG_A6XX_SP_GS_PRIMITIVE_CNTL 0x0000a873 5623c28c82e9SRob Clark #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f 5624c28c82e9SRob Clark #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT 0 5625c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_OUT(uint32_t val) 5626c28c82e9SRob Clark { 5627c28c82e9SRob Clark return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK; 5628c28c82e9SRob Clark } 5629c28c82e9SRob Clark #define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0 5630c28c82e9SRob Clark #define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6 5631c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) 5632c28c82e9SRob Clark { 5633c28c82e9SRob Clark return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; 5634c28c82e9SRob Clark } 5635c28c82e9SRob Clark 5636c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_GS_OUT(uint32_t i0) { return 0x0000a874 + 0x1*i0; } 5637c28c82e9SRob Clark 5638c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_GS_OUT_REG(uint32_t i0) { return 0x0000a874 + 0x1*i0; } 5639c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_A_REGID__MASK 0x000000ff 5640c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_A_REGID__SHIFT 0 5641c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_OUT_REG_A_REGID(uint32_t val) 5642c28c82e9SRob Clark { 5643c28c82e9SRob Clark return ((val) << A6XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_A_REGID__MASK; 5644c28c82e9SRob Clark } 5645c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00000f00 5646c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 8 5647c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val) 5648c28c82e9SRob Clark { 5649c28c82e9SRob Clark return ((val) << A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK; 5650c28c82e9SRob Clark } 5651c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_B_REGID__MASK 0x00ff0000 5652c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_B_REGID__SHIFT 16 5653c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_OUT_REG_B_REGID(uint32_t val) 5654c28c82e9SRob Clark { 5655c28c82e9SRob Clark return ((val) << A6XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_B_REGID__MASK; 5656c28c82e9SRob Clark } 5657c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x0f000000 5658c28c82e9SRob Clark #define A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 24 5659c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val) 5660c28c82e9SRob Clark { 5661c28c82e9SRob Clark return ((val) << A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK; 5662c28c82e9SRob Clark } 5663c28c82e9SRob Clark 5664c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_GS_VPC_DST(uint32_t i0) { return 0x0000a884 + 0x1*i0; } 5665c28c82e9SRob Clark 5666c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x0000a884 + 0x1*i0; } 5667c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 5668c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0 5669c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val) 5670c28c82e9SRob Clark { 5671c28c82e9SRob Clark return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK; 5672c28c82e9SRob Clark } 5673c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 5674c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8 5675c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val) 5676c28c82e9SRob Clark { 5677c28c82e9SRob Clark return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK; 5678c28c82e9SRob Clark } 5679c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 5680c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16 5681c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val) 5682c28c82e9SRob Clark { 5683c28c82e9SRob Clark return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK; 5684c28c82e9SRob Clark } 5685c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 5686c28c82e9SRob Clark #define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24 5687c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) 5688c28c82e9SRob Clark { 5689c28c82e9SRob Clark return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK; 5690c28c82e9SRob Clark } 56912d756322SRob Clark 5692cc4c26d4SRob Clark #define REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET 0x0000a88c 56932d756322SRob Clark 5694cc4c26d4SRob Clark #define REG_A6XX_SP_GS_OBJ_START 0x0000a88d 5695cc4c26d4SRob Clark #define A6XX_SP_GS_OBJ_START__MASK 0xffffffff 5696cc4c26d4SRob Clark #define A6XX_SP_GS_OBJ_START__SHIFT 0 5697cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_OBJ_START(uint32_t val) 5698cc4c26d4SRob Clark { 5699cc4c26d4SRob Clark return ((val) << A6XX_SP_GS_OBJ_START__SHIFT) & A6XX_SP_GS_OBJ_START__MASK; 5700cc4c26d4SRob Clark } 5701cc4c26d4SRob Clark 5702cc4c26d4SRob Clark #define REG_A6XX_SP_GS_PVT_MEM_PARAM 0x0000a88f 5703cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 5704cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 5705cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 5706cc4c26d4SRob Clark { 5707cc4c26d4SRob Clark return ((val >> 9) << A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 5708cc4c26d4SRob Clark } 5709cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 5710cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 5711cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 5712cc4c26d4SRob Clark { 5713cc4c26d4SRob Clark return ((val) << A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 5714cc4c26d4SRob Clark } 5715cc4c26d4SRob Clark 5716cc4c26d4SRob Clark #define REG_A6XX_SP_GS_PVT_MEM_ADDR 0x0000a890 5717cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_ADDR__MASK 0xffffffff 5718cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_ADDR__SHIFT 0 5719cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_PVT_MEM_ADDR(uint32_t val) 5720cc4c26d4SRob Clark { 5721cc4c26d4SRob Clark return ((val) << A6XX_SP_GS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_GS_PVT_MEM_ADDR__MASK; 5722cc4c26d4SRob Clark } 5723cc4c26d4SRob Clark 5724cc4c26d4SRob Clark #define REG_A6XX_SP_GS_PVT_MEM_SIZE 0x0000a892 5725cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 5726cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 5727cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 5728cc4c26d4SRob Clark { 5729cc4c26d4SRob Clark return ((val >> 12) << A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 5730cc4c26d4SRob Clark } 5731cc4c26d4SRob Clark #define A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 57322d756322SRob Clark 57332d756322SRob Clark #define REG_A6XX_SP_GS_TEX_COUNT 0x0000a893 57342d756322SRob Clark 57352d756322SRob Clark #define REG_A6XX_SP_GS_CONFIG 0x0000a894 5736c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_BINDLESS_TEX 0x00000001 5737c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_BINDLESS_SAMP 0x00000002 5738c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_BINDLESS_IBO 0x00000004 5739c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_BINDLESS_UBO 0x00000008 57402d756322SRob Clark #define A6XX_SP_GS_CONFIG_ENABLED 0x00000100 57412d756322SRob Clark #define A6XX_SP_GS_CONFIG_NTEX__MASK 0x0001fe00 57422d756322SRob Clark #define A6XX_SP_GS_CONFIG_NTEX__SHIFT 9 57432d756322SRob Clark static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val) 57442d756322SRob Clark { 57452d756322SRob Clark return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK; 57462d756322SRob Clark } 5747c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_NSAMP__MASK 0x003e0000 57482d756322SRob Clark #define A6XX_SP_GS_CONFIG_NSAMP__SHIFT 17 57492d756322SRob Clark static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val) 57502d756322SRob Clark { 57512d756322SRob Clark return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK; 57522d756322SRob Clark } 5753cc4c26d4SRob Clark #define A6XX_SP_GS_CONFIG_NIBO__MASK 0x1fc00000 5754c28c82e9SRob Clark #define A6XX_SP_GS_CONFIG_NIBO__SHIFT 22 5755c28c82e9SRob Clark static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val) 5756c28c82e9SRob Clark { 5757c28c82e9SRob Clark return ((val) << A6XX_SP_GS_CONFIG_NIBO__SHIFT) & A6XX_SP_GS_CONFIG_NIBO__MASK; 5758c28c82e9SRob Clark } 57592d756322SRob Clark 57602d756322SRob Clark #define REG_A6XX_SP_GS_INSTRLEN 0x0000a895 57612d756322SRob Clark 5762cc4c26d4SRob Clark #define REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET 0x0000a896 576357cfe41cSRob Clark #define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 576457cfe41cSRob Clark #define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 576557cfe41cSRob Clark static inline uint32_t A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 5766cc4c26d4SRob Clark { 576757cfe41cSRob Clark return ((val >> 11) << A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 5768cc4c26d4SRob Clark } 57692d756322SRob Clark 5770cc4c26d4SRob Clark #define REG_A6XX_SP_VS_TEX_SAMP 0x0000a8a0 5771cc4c26d4SRob Clark #define A6XX_SP_VS_TEX_SAMP__MASK 0xffffffff 5772cc4c26d4SRob Clark #define A6XX_SP_VS_TEX_SAMP__SHIFT 0 5773cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_TEX_SAMP(uint32_t val) 5774cc4c26d4SRob Clark { 5775cc4c26d4SRob Clark return ((val) << A6XX_SP_VS_TEX_SAMP__SHIFT) & A6XX_SP_VS_TEX_SAMP__MASK; 5776cc4c26d4SRob Clark } 57772d756322SRob Clark 5778cc4c26d4SRob Clark #define REG_A6XX_SP_HS_TEX_SAMP 0x0000a8a2 5779cc4c26d4SRob Clark #define A6XX_SP_HS_TEX_SAMP__MASK 0xffffffff 5780cc4c26d4SRob Clark #define A6XX_SP_HS_TEX_SAMP__SHIFT 0 5781cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_TEX_SAMP(uint32_t val) 5782cc4c26d4SRob Clark { 5783cc4c26d4SRob Clark return ((val) << A6XX_SP_HS_TEX_SAMP__SHIFT) & A6XX_SP_HS_TEX_SAMP__MASK; 5784cc4c26d4SRob Clark } 57852d756322SRob Clark 5786cc4c26d4SRob Clark #define REG_A6XX_SP_DS_TEX_SAMP 0x0000a8a4 5787cc4c26d4SRob Clark #define A6XX_SP_DS_TEX_SAMP__MASK 0xffffffff 5788cc4c26d4SRob Clark #define A6XX_SP_DS_TEX_SAMP__SHIFT 0 5789cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_TEX_SAMP(uint32_t val) 5790cc4c26d4SRob Clark { 5791cc4c26d4SRob Clark return ((val) << A6XX_SP_DS_TEX_SAMP__SHIFT) & A6XX_SP_DS_TEX_SAMP__MASK; 5792cc4c26d4SRob Clark } 57932d756322SRob Clark 5794cc4c26d4SRob Clark #define REG_A6XX_SP_GS_TEX_SAMP 0x0000a8a6 5795cc4c26d4SRob Clark #define A6XX_SP_GS_TEX_SAMP__MASK 0xffffffff 5796cc4c26d4SRob Clark #define A6XX_SP_GS_TEX_SAMP__SHIFT 0 5797cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_TEX_SAMP(uint32_t val) 5798cc4c26d4SRob Clark { 5799cc4c26d4SRob Clark return ((val) << A6XX_SP_GS_TEX_SAMP__SHIFT) & A6XX_SP_GS_TEX_SAMP__MASK; 5800cc4c26d4SRob Clark } 58012d756322SRob Clark 5802cc4c26d4SRob Clark #define REG_A6XX_SP_VS_TEX_CONST 0x0000a8a8 5803cc4c26d4SRob Clark #define A6XX_SP_VS_TEX_CONST__MASK 0xffffffff 5804cc4c26d4SRob Clark #define A6XX_SP_VS_TEX_CONST__SHIFT 0 5805cc4c26d4SRob Clark static inline uint32_t A6XX_SP_VS_TEX_CONST(uint32_t val) 5806cc4c26d4SRob Clark { 5807cc4c26d4SRob Clark return ((val) << A6XX_SP_VS_TEX_CONST__SHIFT) & A6XX_SP_VS_TEX_CONST__MASK; 5808cc4c26d4SRob Clark } 58092d756322SRob Clark 5810cc4c26d4SRob Clark #define REG_A6XX_SP_HS_TEX_CONST 0x0000a8aa 5811cc4c26d4SRob Clark #define A6XX_SP_HS_TEX_CONST__MASK 0xffffffff 5812cc4c26d4SRob Clark #define A6XX_SP_HS_TEX_CONST__SHIFT 0 5813cc4c26d4SRob Clark static inline uint32_t A6XX_SP_HS_TEX_CONST(uint32_t val) 5814cc4c26d4SRob Clark { 5815cc4c26d4SRob Clark return ((val) << A6XX_SP_HS_TEX_CONST__SHIFT) & A6XX_SP_HS_TEX_CONST__MASK; 5816cc4c26d4SRob Clark } 58172d756322SRob Clark 5818cc4c26d4SRob Clark #define REG_A6XX_SP_DS_TEX_CONST 0x0000a8ac 5819cc4c26d4SRob Clark #define A6XX_SP_DS_TEX_CONST__MASK 0xffffffff 5820cc4c26d4SRob Clark #define A6XX_SP_DS_TEX_CONST__SHIFT 0 5821cc4c26d4SRob Clark static inline uint32_t A6XX_SP_DS_TEX_CONST(uint32_t val) 5822cc4c26d4SRob Clark { 5823cc4c26d4SRob Clark return ((val) << A6XX_SP_DS_TEX_CONST__SHIFT) & A6XX_SP_DS_TEX_CONST__MASK; 5824cc4c26d4SRob Clark } 58252d756322SRob Clark 5826cc4c26d4SRob Clark #define REG_A6XX_SP_GS_TEX_CONST 0x0000a8ae 5827cc4c26d4SRob Clark #define A6XX_SP_GS_TEX_CONST__MASK 0xffffffff 5828cc4c26d4SRob Clark #define A6XX_SP_GS_TEX_CONST__SHIFT 0 5829cc4c26d4SRob Clark static inline uint32_t A6XX_SP_GS_TEX_CONST(uint32_t val) 5830cc4c26d4SRob Clark { 5831cc4c26d4SRob Clark return ((val) << A6XX_SP_GS_TEX_CONST__SHIFT) & A6XX_SP_GS_TEX_CONST__MASK; 5832cc4c26d4SRob Clark } 58332d756322SRob Clark 58342d756322SRob Clark #define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980 5835cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 5836cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 5837cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) 5838cc4c26d4SRob Clark { 5839cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 5840cc4c26d4SRob Clark } 5841cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_UNK21 0x00200000 5842cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000 5843cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_DIFF_FINE 0x00800000 5844cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_UNK24 0x01000000 5845cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_UNK25 0x02000000 5846cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000 5847cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_UNK27__MASK 0x18000000 5848cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_UNK27__SHIFT 27 5849cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_UNK27(uint32_t val) 5850cc4c26d4SRob Clark { 5851cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_UNK27__SHIFT) & A6XX_SP_FS_CTRL_REG0_UNK27__MASK; 5852cc4c26d4SRob Clark } 5853cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000 5854cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 5855cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 5856cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 5857cc4c26d4SRob Clark { 5858cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK; 5859cc4c26d4SRob Clark } 58602d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 58612d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 58622d756322SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 58632d756322SRob Clark { 58642d756322SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 58652d756322SRob Clark } 58662d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 58672d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 58682d756322SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 58692d756322SRob Clark { 58702d756322SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 58712d756322SRob Clark } 5872cc4c26d4SRob Clark #define A6XX_SP_FS_CTRL_REG0_UNK13 0x00002000 58732d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 58742d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 14 58752d756322SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) 58762d756322SRob Clark { 58772d756322SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK; 58782d756322SRob Clark } 58792d756322SRob Clark 5880c28c82e9SRob Clark #define REG_A6XX_SP_FS_BRANCH_COND 0x0000a981 5881c28c82e9SRob Clark 5882cc4c26d4SRob Clark #define REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET 0x0000a982 5883a69c5ed2SRob Clark 5884cc4c26d4SRob Clark #define REG_A6XX_SP_FS_OBJ_START 0x0000a983 5885cc4c26d4SRob Clark #define A6XX_SP_FS_OBJ_START__MASK 0xffffffff 5886cc4c26d4SRob Clark #define A6XX_SP_FS_OBJ_START__SHIFT 0 5887cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_OBJ_START(uint32_t val) 5888cc4c26d4SRob Clark { 5889cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_OBJ_START__SHIFT) & A6XX_SP_FS_OBJ_START__MASK; 5890cc4c26d4SRob Clark } 58912d756322SRob Clark 5892cc4c26d4SRob Clark #define REG_A6XX_SP_FS_PVT_MEM_PARAM 0x0000a985 5893cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 5894cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 5895cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 5896cc4c26d4SRob Clark { 5897cc4c26d4SRob Clark return ((val >> 9) << A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 5898cc4c26d4SRob Clark } 5899cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 5900cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 5901cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 5902cc4c26d4SRob Clark { 5903cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 5904cc4c26d4SRob Clark } 5905cc4c26d4SRob Clark 5906cc4c26d4SRob Clark #define REG_A6XX_SP_FS_PVT_MEM_ADDR 0x0000a986 5907cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_ADDR__MASK 0xffffffff 5908cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_ADDR__SHIFT 0 5909cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_PVT_MEM_ADDR(uint32_t val) 5910cc4c26d4SRob Clark { 5911cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_FS_PVT_MEM_ADDR__MASK; 5912cc4c26d4SRob Clark } 5913cc4c26d4SRob Clark 5914cc4c26d4SRob Clark #define REG_A6XX_SP_FS_PVT_MEM_SIZE 0x0000a988 5915cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 5916cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 5917cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 5918cc4c26d4SRob Clark { 5919cc4c26d4SRob Clark return ((val >> 12) << A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 5920cc4c26d4SRob Clark } 5921cc4c26d4SRob Clark #define A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 59222d756322SRob Clark 59232d756322SRob Clark #define REG_A6XX_SP_BLEND_CNTL 0x0000a989 5924cc4c26d4SRob Clark #define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff 5925cc4c26d4SRob Clark #define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 5926cc4c26d4SRob Clark static inline uint32_t A6XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val) 5927cc4c26d4SRob Clark { 5928cc4c26d4SRob Clark return ((val) << A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK; 5929cc4c26d4SRob Clark } 59302d756322SRob Clark #define A6XX_SP_BLEND_CNTL_UNK8 0x00000100 5931c28c82e9SRob Clark #define A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200 5932ccdf7e28SRob Clark #define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 59332d756322SRob Clark 59342d756322SRob Clark #define REG_A6XX_SP_SRGB_CNTL 0x0000a98a 59352d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT0 0x00000001 59362d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT1 0x00000002 59372d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT2 0x00000004 59382d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT3 0x00000008 59392d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT4 0x00000010 59402d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT5 0x00000020 59412d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT6 0x00000040 59422d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT7 0x00000080 59432d756322SRob Clark 59442d756322SRob Clark #define REG_A6XX_SP_FS_RENDER_COMPONENTS 0x0000a98b 59452d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK 0x0000000f 59462d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT 0 59472d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val) 59482d756322SRob Clark { 59492d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK; 59502d756322SRob Clark } 59512d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK 0x000000f0 59522d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT 4 59532d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val) 59542d756322SRob Clark { 59552d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK; 59562d756322SRob Clark } 59572d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK 0x00000f00 59582d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT 8 59592d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val) 59602d756322SRob Clark { 59612d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK; 59622d756322SRob Clark } 59632d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK 0x0000f000 59642d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT 12 59652d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val) 59662d756322SRob Clark { 59672d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK; 59682d756322SRob Clark } 59692d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK 0x000f0000 59702d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT 16 59712d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val) 59722d756322SRob Clark { 59732d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK; 59742d756322SRob Clark } 59752d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK 0x00f00000 59762d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT 20 59772d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val) 59782d756322SRob Clark { 59792d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK; 59802d756322SRob Clark } 59812d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK 0x0f000000 59822d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT 24 59832d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val) 59842d756322SRob Clark { 59852d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK; 59862d756322SRob Clark } 59872d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK 0xf0000000 59882d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT 28 59892d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val) 59902d756322SRob Clark { 59912d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK; 59922d756322SRob Clark } 59932d756322SRob Clark 59942d756322SRob Clark #define REG_A6XX_SP_FS_OUTPUT_CNTL0 0x0000a98c 5995c28c82e9SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001 59962d756322SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK 0x0000ff00 59972d756322SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT 8 59982d756322SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val) 59992d756322SRob Clark { 60002d756322SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK; 60012d756322SRob Clark } 6002c28c82e9SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK 0x00ff0000 6003c28c82e9SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT 16 6004c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(uint32_t val) 6005c28c82e9SRob Clark { 6006c28c82e9SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK; 6007c28c82e9SRob Clark } 6008c28c82e9SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK 0xff000000 6009c28c82e9SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT 24 6010c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(uint32_t val) 6011c28c82e9SRob Clark { 6012c28c82e9SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK; 6013c28c82e9SRob Clark } 60142d756322SRob Clark 60152d756322SRob Clark #define REG_A6XX_SP_FS_OUTPUT_CNTL1 0x0000a98d 60162d756322SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f 60172d756322SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT 0 60182d756322SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val) 60192d756322SRob Clark { 60202d756322SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK; 60212d756322SRob Clark } 60222d756322SRob Clark 6023cc4c26d4SRob Clark static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; } 6024cc4c26d4SRob Clark 6025cc4c26d4SRob Clark static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; } 6026cc4c26d4SRob Clark #define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff 6027cc4c26d4SRob Clark #define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0 6028cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) 6029cc4c26d4SRob Clark { 6030cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK; 6031cc4c26d4SRob Clark } 6032cc4c26d4SRob Clark #define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100 6033cc4c26d4SRob Clark 60342d756322SRob Clark static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; } 60352d756322SRob Clark 60362d756322SRob Clark static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; } 60372d756322SRob Clark #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff 60382d756322SRob Clark #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0 6039c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val) 60402d756322SRob Clark { 60412d756322SRob Clark return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK; 60422d756322SRob Clark } 60432d756322SRob Clark #define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100 60442d756322SRob Clark #define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200 6045cc4c26d4SRob Clark #define A6XX_SP_FS_MRT_REG_UNK10 0x00000400 6046a69c5ed2SRob Clark 6047c28c82e9SRob Clark #define REG_A6XX_SP_FS_PREFETCH_CNTL 0x0000a99e 6048c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK 0x00000007 6049c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT 0 6050c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_COUNT(uint32_t val) 6051c28c82e9SRob Clark { 6052c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK; 6053c28c82e9SRob Clark } 6054c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_UNK3 0x00000008 6055c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK 0x00000ff0 6056c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT 4 6057c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK4(uint32_t val) 6058c28c82e9SRob Clark { 6059c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK4__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK; 6060c28c82e9SRob Clark } 6061cc4c26d4SRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_UNK12__MASK 0x00007000 6062cc4c26d4SRob Clark #define A6XX_SP_FS_PREFETCH_CNTL_UNK12__SHIFT 12 6063cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK12(uint32_t val) 6064cc4c26d4SRob Clark { 6065cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK12__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK12__MASK; 6066cc4c26d4SRob Clark } 6067c28c82e9SRob Clark 6068c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_FS_PREFETCH(uint32_t i0) { return 0x0000a99f + 0x1*i0; } 6069c28c82e9SRob Clark 6070c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; } 6071c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_SRC__MASK 0x0000007f 6072c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT 0 6073c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val) 6074c28c82e9SRob Clark { 6075c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SRC__MASK; 6076c28c82e9SRob Clark } 6077c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK 0x00000780 6078c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT 7 6079c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val) 6080c28c82e9SRob Clark { 6081c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK; 6082c28c82e9SRob Clark } 6083c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK 0x0000f800 6084c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT 11 6085c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val) 6086c28c82e9SRob Clark { 6087c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK; 6088c28c82e9SRob Clark } 6089c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_DST__MASK 0x003f0000 6090c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT 16 6091c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_DST(uint32_t val) 6092c28c82e9SRob Clark { 6093c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_DST__MASK; 6094c28c82e9SRob Clark } 6095c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK 0x03c00000 6096c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT 22 6097c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val) 6098c28c82e9SRob Clark { 6099c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK; 6100c28c82e9SRob Clark } 6101c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_HALF 0x04000000 6102c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_CMD__MASK 0xf8000000 6103c28c82e9SRob Clark #define A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT 27 6104c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_CMD(uint32_t val) 6105c28c82e9SRob Clark { 6106c28c82e9SRob Clark return ((val) << A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_CMD__MASK; 6107c28c82e9SRob Clark } 6108c28c82e9SRob Clark 6109c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; } 6110c28c82e9SRob Clark 6111c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; } 6112cc4c26d4SRob Clark #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK 0x0000ffff 6113c28c82e9SRob Clark #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT 0 6114c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val) 6115c28c82e9SRob Clark { 6116c28c82e9SRob Clark return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK; 6117c28c82e9SRob Clark } 6118cc4c26d4SRob Clark #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK 0xffff0000 6119c28c82e9SRob Clark #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT 16 6120c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val) 6121c28c82e9SRob Clark { 6122c28c82e9SRob Clark return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK; 6123c28c82e9SRob Clark } 61242d756322SRob Clark 61252d756322SRob Clark #define REG_A6XX_SP_FS_TEX_COUNT 0x0000a9a7 61262d756322SRob Clark 61272d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8 61282d756322SRob Clark 6129cc4c26d4SRob Clark #define REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET 0x0000a9a9 613057cfe41cSRob Clark #define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 613157cfe41cSRob Clark #define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 613257cfe41cSRob Clark static inline uint32_t A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 6133c28c82e9SRob Clark { 613457cfe41cSRob Clark return ((val >> 11) << A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 6135c28c82e9SRob Clark } 6136c28c82e9SRob Clark 61372d756322SRob Clark #define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0 6138cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000 6139cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20 6140cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) 6141cc4c26d4SRob Clark { 6142cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK; 6143cc4c26d4SRob Clark } 6144cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_UNK21 0x00200000 6145cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_UNK22 0x00400000 6146cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_SEPARATEPROLOG 0x00800000 6147cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000 6148cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK 0x00000001 6149cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT 0 6150cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 6151cc4c26d4SRob Clark { 6152cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK; 6153cc4c26d4SRob Clark } 61542d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 61552d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 61562d756322SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 61572d756322SRob Clark { 61582d756322SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 61592d756322SRob Clark } 61602d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 61612d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 61622d756322SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 61632d756322SRob Clark { 61642d756322SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 61652d756322SRob Clark } 6166cc4c26d4SRob Clark #define A6XX_SP_CS_CTRL_REG0_UNK13 0x00002000 61672d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 61682d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 14 61692d756322SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val) 61702d756322SRob Clark { 61712d756322SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK; 61722d756322SRob Clark } 6173cc4c26d4SRob Clark 6174cc4c26d4SRob Clark #define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1 6175cc4c26d4SRob Clark #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK 0x0000001f 6176cc4c26d4SRob Clark #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT 0 6177cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(uint32_t val) 61782d756322SRob Clark { 6179cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK; 61802d756322SRob Clark } 6181cc4c26d4SRob Clark #define A6XX_SP_CS_UNKNOWN_A9B1_UNK5 0x00000020 6182cc4c26d4SRob Clark #define A6XX_SP_CS_UNKNOWN_A9B1_UNK6 0x00000040 61832d756322SRob Clark 6184cc4c26d4SRob Clark #define REG_A6XX_SP_CS_BRANCH_COND 0x0000a9b2 61852d756322SRob Clark 6186cc4c26d4SRob Clark #define REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET 0x0000a9b3 6187cc4c26d4SRob Clark 6188cc4c26d4SRob Clark #define REG_A6XX_SP_CS_OBJ_START 0x0000a9b4 6189cc4c26d4SRob Clark #define A6XX_SP_CS_OBJ_START__MASK 0xffffffff 6190cc4c26d4SRob Clark #define A6XX_SP_CS_OBJ_START__SHIFT 0 6191cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_OBJ_START(uint32_t val) 6192cc4c26d4SRob Clark { 6193cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_OBJ_START__SHIFT) & A6XX_SP_CS_OBJ_START__MASK; 6194cc4c26d4SRob Clark } 6195cc4c26d4SRob Clark 6196cc4c26d4SRob Clark #define REG_A6XX_SP_CS_PVT_MEM_PARAM 0x0000a9b6 6197cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff 6198cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 6199cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) 6200cc4c26d4SRob Clark { 6201cc4c26d4SRob Clark return ((val >> 9) << A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; 6202cc4c26d4SRob Clark } 6203cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 6204cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 6205cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) 6206cc4c26d4SRob Clark { 6207cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; 6208cc4c26d4SRob Clark } 6209cc4c26d4SRob Clark 6210cc4c26d4SRob Clark #define REG_A6XX_SP_CS_PVT_MEM_ADDR 0x0000a9b7 6211cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_ADDR__MASK 0xffffffff 6212cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_ADDR__SHIFT 0 6213cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_PVT_MEM_ADDR(uint32_t val) 6214cc4c26d4SRob Clark { 6215cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_CS_PVT_MEM_ADDR__MASK; 6216cc4c26d4SRob Clark } 6217cc4c26d4SRob Clark 6218cc4c26d4SRob Clark #define REG_A6XX_SP_CS_PVT_MEM_SIZE 0x0000a9b9 6219cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff 6220cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 6221cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) 6222cc4c26d4SRob Clark { 6223cc4c26d4SRob Clark return ((val >> 12) << A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; 6224cc4c26d4SRob Clark } 6225cc4c26d4SRob Clark #define A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 6226cc4c26d4SRob Clark 6227cc4c26d4SRob Clark #define REG_A6XX_SP_CS_TEX_COUNT 0x0000a9ba 62282d756322SRob Clark 6229c28c82e9SRob Clark #define REG_A6XX_SP_CS_CONFIG 0x0000a9bb 6230c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_BINDLESS_TEX 0x00000001 6231c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_BINDLESS_SAMP 0x00000002 6232c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_BINDLESS_IBO 0x00000004 6233c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_BINDLESS_UBO 0x00000008 6234c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_ENABLED 0x00000100 6235c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_NTEX__MASK 0x0001fe00 6236c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_NTEX__SHIFT 9 6237c28c82e9SRob Clark static inline uint32_t A6XX_SP_CS_CONFIG_NTEX(uint32_t val) 6238c28c82e9SRob Clark { 6239c28c82e9SRob Clark return ((val) << A6XX_SP_CS_CONFIG_NTEX__SHIFT) & A6XX_SP_CS_CONFIG_NTEX__MASK; 6240c28c82e9SRob Clark } 6241c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_NSAMP__MASK 0x003e0000 6242c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_NSAMP__SHIFT 17 6243c28c82e9SRob Clark static inline uint32_t A6XX_SP_CS_CONFIG_NSAMP(uint32_t val) 6244c28c82e9SRob Clark { 6245c28c82e9SRob Clark return ((val) << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK; 6246c28c82e9SRob Clark } 6247cc4c26d4SRob Clark #define A6XX_SP_CS_CONFIG_NIBO__MASK 0x1fc00000 6248c28c82e9SRob Clark #define A6XX_SP_CS_CONFIG_NIBO__SHIFT 22 6249c28c82e9SRob Clark static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val) 6250c28c82e9SRob Clark { 6251c28c82e9SRob Clark return ((val) << A6XX_SP_CS_CONFIG_NIBO__SHIFT) & A6XX_SP_CS_CONFIG_NIBO__MASK; 6252c28c82e9SRob Clark } 6253c28c82e9SRob Clark 62542d756322SRob Clark #define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc 62552d756322SRob Clark 6256cc4c26d4SRob Clark #define REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET 0x0000a9bd 625757cfe41cSRob Clark #define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff 625857cfe41cSRob Clark #define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 625957cfe41cSRob Clark static inline uint32_t A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) 6260cc4c26d4SRob Clark { 626157cfe41cSRob Clark return ((val >> 11) << A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; 6262cc4c26d4SRob Clark } 6263c28c82e9SRob Clark 626457cfe41cSRob Clark #define REG_A6XX_SP_CS_CNTL_0 0x0000a9c2 626557cfe41cSRob Clark #define A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff 626657cfe41cSRob Clark #define A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT 0 626757cfe41cSRob Clark static inline uint32_t A6XX_SP_CS_CNTL_0_WGIDCONSTID(uint32_t val) 626857cfe41cSRob Clark { 626957cfe41cSRob Clark return ((val) << A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK; 627057cfe41cSRob Clark } 627157cfe41cSRob Clark #define A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK 0x0000ff00 627257cfe41cSRob Clark #define A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT 8 627357cfe41cSRob Clark static inline uint32_t A6XX_SP_CS_CNTL_0_WGSIZECONSTID(uint32_t val) 627457cfe41cSRob Clark { 627557cfe41cSRob Clark return ((val) << A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK; 627657cfe41cSRob Clark } 627757cfe41cSRob Clark #define A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK 0x00ff0000 627857cfe41cSRob Clark #define A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT 16 627957cfe41cSRob Clark static inline uint32_t A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val) 628057cfe41cSRob Clark { 628157cfe41cSRob Clark return ((val) << A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK; 628257cfe41cSRob Clark } 628357cfe41cSRob Clark #define A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000 628457cfe41cSRob Clark #define A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT 24 628557cfe41cSRob Clark static inline uint32_t A6XX_SP_CS_CNTL_0_LOCALIDREGID(uint32_t val) 628657cfe41cSRob Clark { 628757cfe41cSRob Clark return ((val) << A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK; 628857cfe41cSRob Clark } 628957cfe41cSRob Clark 629057cfe41cSRob Clark #define REG_A6XX_SP_CS_CNTL_1 0x0000a9c3 629157cfe41cSRob Clark #define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff 629257cfe41cSRob Clark #define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0 629357cfe41cSRob Clark static inline uint32_t A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) 629457cfe41cSRob Clark { 629557cfe41cSRob Clark return ((val) << A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK; 629657cfe41cSRob Clark } 629757cfe41cSRob Clark #define A6XX_SP_CS_CNTL_1_SINGLE_SP_CORE 0x00000100 629857cfe41cSRob Clark #define A6XX_SP_CS_CNTL_1_THREADSIZE__MASK 0x00000200 629957cfe41cSRob Clark #define A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT 9 630057cfe41cSRob Clark static inline uint32_t A6XX_SP_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) 630157cfe41cSRob Clark { 630257cfe41cSRob Clark return ((val) << A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_SP_CS_CNTL_1_THREADSIZE__MASK; 630357cfe41cSRob Clark } 630457cfe41cSRob Clark #define A6XX_SP_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400 630557cfe41cSRob Clark 6306cc4c26d4SRob Clark #define REG_A6XX_SP_FS_TEX_SAMP 0x0000a9e0 6307cc4c26d4SRob Clark #define A6XX_SP_FS_TEX_SAMP__MASK 0xffffffff 6308cc4c26d4SRob Clark #define A6XX_SP_FS_TEX_SAMP__SHIFT 0 6309cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_TEX_SAMP(uint32_t val) 6310cc4c26d4SRob Clark { 6311cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_TEX_SAMP__SHIFT) & A6XX_SP_FS_TEX_SAMP__MASK; 6312cc4c26d4SRob Clark } 6313cc4c26d4SRob Clark 6314cc4c26d4SRob Clark #define REG_A6XX_SP_CS_TEX_SAMP 0x0000a9e2 6315cc4c26d4SRob Clark #define A6XX_SP_CS_TEX_SAMP__MASK 0xffffffff 6316cc4c26d4SRob Clark #define A6XX_SP_CS_TEX_SAMP__SHIFT 0 6317cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_TEX_SAMP(uint32_t val) 6318cc4c26d4SRob Clark { 6319cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_TEX_SAMP__SHIFT) & A6XX_SP_CS_TEX_SAMP__MASK; 6320cc4c26d4SRob Clark } 6321cc4c26d4SRob Clark 6322cc4c26d4SRob Clark #define REG_A6XX_SP_FS_TEX_CONST 0x0000a9e4 6323cc4c26d4SRob Clark #define A6XX_SP_FS_TEX_CONST__MASK 0xffffffff 6324cc4c26d4SRob Clark #define A6XX_SP_FS_TEX_CONST__SHIFT 0 6325cc4c26d4SRob Clark static inline uint32_t A6XX_SP_FS_TEX_CONST(uint32_t val) 6326cc4c26d4SRob Clark { 6327cc4c26d4SRob Clark return ((val) << A6XX_SP_FS_TEX_CONST__SHIFT) & A6XX_SP_FS_TEX_CONST__MASK; 6328cc4c26d4SRob Clark } 6329cc4c26d4SRob Clark 6330cc4c26d4SRob Clark #define REG_A6XX_SP_CS_TEX_CONST 0x0000a9e6 6331cc4c26d4SRob Clark #define A6XX_SP_CS_TEX_CONST__MASK 0xffffffff 6332cc4c26d4SRob Clark #define A6XX_SP_CS_TEX_CONST__SHIFT 0 6333cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_TEX_CONST(uint32_t val) 6334cc4c26d4SRob Clark { 6335cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_TEX_CONST__SHIFT) & A6XX_SP_CS_TEX_CONST__MASK; 6336cc4c26d4SRob Clark } 6337cc4c26d4SRob Clark 6338cc4c26d4SRob Clark static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; } 6339cc4c26d4SRob Clark 6340cc4c26d4SRob Clark static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; } 6341cc4c26d4SRob Clark 6342cc4c26d4SRob Clark #define REG_A6XX_SP_CS_IBO 0x0000a9f2 6343cc4c26d4SRob Clark #define A6XX_SP_CS_IBO__MASK 0xffffffff 6344cc4c26d4SRob Clark #define A6XX_SP_CS_IBO__SHIFT 0 6345cc4c26d4SRob Clark static inline uint32_t A6XX_SP_CS_IBO(uint32_t val) 6346cc4c26d4SRob Clark { 6347cc4c26d4SRob Clark return ((val) << A6XX_SP_CS_IBO__SHIFT) & A6XX_SP_CS_IBO__MASK; 6348cc4c26d4SRob Clark } 6349c28c82e9SRob Clark 6350c28c82e9SRob Clark #define REG_A6XX_SP_CS_IBO_COUNT 0x0000aa00 6351c28c82e9SRob Clark 6352cc4c26d4SRob Clark #define REG_A6XX_SP_MODE_CONTROL 0x0000ab00 6353cc4c26d4SRob Clark #define A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE 0x00000001 635457cfe41cSRob Clark #define A6XX_SP_MODE_CONTROL_ISAMMODE__MASK 0x00000006 635557cfe41cSRob Clark #define A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT 1 635657cfe41cSRob Clark static inline uint32_t A6XX_SP_MODE_CONTROL_ISAMMODE(enum a6xx_isam_mode val) 635757cfe41cSRob Clark { 635857cfe41cSRob Clark return ((val) << A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT) & A6XX_SP_MODE_CONTROL_ISAMMODE__MASK; 635957cfe41cSRob Clark } 6360cc4c26d4SRob Clark #define A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE 0x00000008 63612d756322SRob Clark 63622d756322SRob Clark #define REG_A6XX_SP_FS_CONFIG 0x0000ab04 6363c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_BINDLESS_TEX 0x00000001 6364c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_BINDLESS_SAMP 0x00000002 6365c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_BINDLESS_IBO 0x00000004 6366c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_BINDLESS_UBO 0x00000008 63672d756322SRob Clark #define A6XX_SP_FS_CONFIG_ENABLED 0x00000100 63682d756322SRob Clark #define A6XX_SP_FS_CONFIG_NTEX__MASK 0x0001fe00 63692d756322SRob Clark #define A6XX_SP_FS_CONFIG_NTEX__SHIFT 9 63702d756322SRob Clark static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val) 63712d756322SRob Clark { 63722d756322SRob Clark return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK; 63732d756322SRob Clark } 6374c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_NSAMP__MASK 0x003e0000 63752d756322SRob Clark #define A6XX_SP_FS_CONFIG_NSAMP__SHIFT 17 63762d756322SRob Clark static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val) 63772d756322SRob Clark { 63782d756322SRob Clark return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK; 63792d756322SRob Clark } 6380cc4c26d4SRob Clark #define A6XX_SP_FS_CONFIG_NIBO__MASK 0x1fc00000 6381c28c82e9SRob Clark #define A6XX_SP_FS_CONFIG_NIBO__SHIFT 22 6382c28c82e9SRob Clark static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val) 6383c28c82e9SRob Clark { 6384c28c82e9SRob Clark return ((val) << A6XX_SP_FS_CONFIG_NIBO__SHIFT) & A6XX_SP_FS_CONFIG_NIBO__MASK; 6385c28c82e9SRob Clark } 63862d756322SRob Clark 63872d756322SRob Clark #define REG_A6XX_SP_FS_INSTRLEN 0x0000ab05 63882d756322SRob Clark 6389c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_BINDLESS_BASE(uint32_t i0) { return 0x0000ab10 + 0x2*i0; } 6390a69c5ed2SRob Clark 6391c28c82e9SRob Clark static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; } 6392c28c82e9SRob Clark 6393cc4c26d4SRob Clark #define REG_A6XX_SP_IBO 0x0000ab1a 6394cc4c26d4SRob Clark #define A6XX_SP_IBO__MASK 0xffffffff 6395cc4c26d4SRob Clark #define A6XX_SP_IBO__SHIFT 0 6396cc4c26d4SRob Clark static inline uint32_t A6XX_SP_IBO(uint32_t val) 6397cc4c26d4SRob Clark { 6398cc4c26d4SRob Clark return ((val) << A6XX_SP_IBO__SHIFT) & A6XX_SP_IBO__MASK; 6399cc4c26d4SRob Clark } 6400c28c82e9SRob Clark 6401c28c82e9SRob Clark #define REG_A6XX_SP_IBO_COUNT 0x0000ab20 6402c28c82e9SRob Clark 6403c28c82e9SRob Clark #define REG_A6XX_SP_2D_DST_FORMAT 0x0000acc0 6404c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_NORM 0x00000001 6405c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_SINT 0x00000002 6406c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_UINT 0x00000004 6407c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK 0x000007f8 6408c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT 3 6409c28c82e9SRob Clark static inline uint32_t A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val) 6410c28c82e9SRob Clark { 6411c28c82e9SRob Clark return ((val) << A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT) & A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK; 6412c28c82e9SRob Clark } 6413c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_SRGB 0x00000800 6414c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_MASK__MASK 0x0000f000 6415c28c82e9SRob Clark #define A6XX_SP_2D_DST_FORMAT_MASK__SHIFT 12 6416c28c82e9SRob Clark static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val) 6417c28c82e9SRob Clark { 6418c28c82e9SRob Clark return ((val) << A6XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A6XX_SP_2D_DST_FORMAT_MASK__MASK; 6419c28c82e9SRob Clark } 6420ccdf7e28SRob Clark 64212d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_AE00 0x0000ae00 64222d756322SRob Clark 6423cc4c26d4SRob Clark #define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01 6424cc4c26d4SRob Clark 6425cc4c26d4SRob Clark #define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02 6426cc4c26d4SRob Clark 642757cfe41cSRob Clark #define REG_A6XX_SP_CHICKEN_BITS 0x0000ae03 6428a69c5ed2SRob Clark 6429cc4c26d4SRob Clark #define REG_A6XX_SP_FLOAT_CNTL 0x0000ae04 6430cc4c26d4SRob Clark #define A6XX_SP_FLOAT_CNTL_F16_NO_INF 0x00000008 64312d756322SRob Clark 6432cc4c26d4SRob Clark #define REG_A6XX_SP_PERFCTR_ENABLE 0x0000ae0f 6433cc4c26d4SRob Clark #define A6XX_SP_PERFCTR_ENABLE_VS 0x00000001 6434cc4c26d4SRob Clark #define A6XX_SP_PERFCTR_ENABLE_HS 0x00000002 6435cc4c26d4SRob Clark #define A6XX_SP_PERFCTR_ENABLE_DS 0x00000004 6436cc4c26d4SRob Clark #define A6XX_SP_PERFCTR_ENABLE_GS 0x00000008 6437cc4c26d4SRob Clark #define A6XX_SP_PERFCTR_ENABLE_FS 0x00000010 6438cc4c26d4SRob Clark #define A6XX_SP_PERFCTR_ENABLE_CS 0x00000020 6439cc4c26d4SRob Clark 6440cc4c26d4SRob Clark static inline uint32_t REG_A6XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae10 + 0x1*i0; } 64412d756322SRob Clark 644257cfe41cSRob Clark #define REG_A6XX_SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE 0x0000be22 644357cfe41cSRob Clark 6444c28c82e9SRob Clark #define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR 0x0000b180 6445cc4c26d4SRob Clark #define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff 6446cc4c26d4SRob Clark #define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0 6447cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(uint32_t val) 6448cc4c26d4SRob Clark { 6449cc4c26d4SRob Clark return ((val) << A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK; 6450cc4c26d4SRob Clark } 6451c28c82e9SRob Clark 64522d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_B182 0x0000b182 64532d756322SRob Clark 6454a69c5ed2SRob Clark #define REG_A6XX_SP_UNKNOWN_B183 0x0000b183 6455a69c5ed2SRob Clark 6456cc4c26d4SRob Clark #define REG_A6XX_SP_UNKNOWN_B190 0x0000b190 6457cc4c26d4SRob Clark 6458cc4c26d4SRob Clark #define REG_A6XX_SP_UNKNOWN_B191 0x0000b191 6459cc4c26d4SRob Clark 64602d756322SRob Clark #define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300 64612d756322SRob Clark #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 64622d756322SRob Clark #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 64632d756322SRob Clark static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 64642d756322SRob Clark { 64652d756322SRob Clark return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK; 64662d756322SRob Clark } 6467cc4c26d4SRob Clark #define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK 0x0000000c 6468cc4c26d4SRob Clark #define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT 2 6469cc4c26d4SRob Clark static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_UNK2(uint32_t val) 6470cc4c26d4SRob Clark { 6471cc4c26d4SRob Clark return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK; 6472cc4c26d4SRob Clark } 64732d756322SRob Clark 64742d756322SRob Clark #define REG_A6XX_SP_TP_DEST_MSAA_CNTL 0x0000b301 64752d756322SRob Clark #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 64762d756322SRob Clark #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 64772d756322SRob Clark static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 64782d756322SRob Clark { 64792d756322SRob Clark return ((val) << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK; 64802d756322SRob Clark } 64812d756322SRob Clark #define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 64822d756322SRob Clark 6483c28c82e9SRob Clark #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR 0x0000b302 6484cc4c26d4SRob Clark #define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff 6485cc4c26d4SRob Clark #define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0 6486cc4c26d4SRob Clark static inline uint32_t A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(uint32_t val) 6487cc4c26d4SRob Clark { 6488cc4c26d4SRob Clark return ((val) << A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK; 6489cc4c26d4SRob Clark } 64902d756322SRob Clark 6491c28c82e9SRob Clark #define REG_A6XX_SP_TP_SAMPLE_CONFIG 0x0000b304 6492c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_CONFIG_UNK0 0x00000001 6493c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002 6494c28c82e9SRob Clark 6495c28c82e9SRob Clark #define REG_A6XX_SP_TP_SAMPLE_LOCATION_0 0x0000b305 6496c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f 6497c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 6498c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) 6499c28c82e9SRob Clark { 6500c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; 6501c28c82e9SRob Clark } 6502c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 6503c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 6504c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) 6505c28c82e9SRob Clark { 6506c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; 6507c28c82e9SRob Clark } 6508c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 6509c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 6510c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) 6511c28c82e9SRob Clark { 6512c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; 6513c28c82e9SRob Clark } 6514c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 6515c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 6516c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) 6517c28c82e9SRob Clark { 6518c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; 6519c28c82e9SRob Clark } 6520c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 6521c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 6522c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) 6523c28c82e9SRob Clark { 6524c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; 6525c28c82e9SRob Clark } 6526c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 6527c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 6528c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) 6529c28c82e9SRob Clark { 6530c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; 6531c28c82e9SRob Clark } 6532c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 6533c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 6534c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) 6535c28c82e9SRob Clark { 6536c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; 6537c28c82e9SRob Clark } 6538c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 6539c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 6540c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) 6541c28c82e9SRob Clark { 6542c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; 6543c28c82e9SRob Clark } 6544c28c82e9SRob Clark 6545c28c82e9SRob Clark #define REG_A6XX_SP_TP_SAMPLE_LOCATION_1 0x0000b306 6546c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f 6547c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 6548c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) 6549c28c82e9SRob Clark { 6550c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; 6551c28c82e9SRob Clark } 6552c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 6553c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 6554c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) 6555c28c82e9SRob Clark { 6556c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; 6557c28c82e9SRob Clark } 6558c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 6559c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 6560c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) 6561c28c82e9SRob Clark { 6562c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; 6563c28c82e9SRob Clark } 6564c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 6565c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 6566c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) 6567c28c82e9SRob Clark { 6568c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; 6569c28c82e9SRob Clark } 6570c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 6571c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 6572c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) 6573c28c82e9SRob Clark { 6574c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; 6575c28c82e9SRob Clark } 6576c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 6577c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 6578c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) 6579c28c82e9SRob Clark { 6580c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; 6581c28c82e9SRob Clark } 6582c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 6583c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 6584c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) 6585c28c82e9SRob Clark { 6586c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; 6587c28c82e9SRob Clark } 6588c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 6589c28c82e9SRob Clark #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 6590c28c82e9SRob Clark static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) 6591c28c82e9SRob Clark { 6592c28c82e9SRob Clark return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; 6593c28c82e9SRob Clark } 65942d756322SRob Clark 6595cc4c26d4SRob Clark #define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307 6596cc4c26d4SRob Clark #define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00003fff 6597cc4c26d4SRob Clark #define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0 6598cc4c26d4SRob Clark static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val) 6599cc4c26d4SRob Clark { 6600cc4c26d4SRob Clark return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK; 6601cc4c26d4SRob Clark } 6602cc4c26d4SRob Clark #define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x3fff0000 6603cc4c26d4SRob Clark #define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16 6604cc4c26d4SRob Clark static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val) 6605cc4c26d4SRob Clark { 6606cc4c26d4SRob Clark return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK; 6607cc4c26d4SRob Clark } 6608cc4c26d4SRob Clark 660957cfe41cSRob Clark #define REG_A6XX_SP_TP_MODE_CNTL 0x0000b309 661057cfe41cSRob Clark #define A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK 0x00000003 661157cfe41cSRob Clark #define A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT 0 661257cfe41cSRob Clark static inline uint32_t A6XX_SP_TP_MODE_CNTL_ISAMMODE(enum a6xx_isam_mode val) 661357cfe41cSRob Clark { 661457cfe41cSRob Clark return ((val) << A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT) & A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK; 661557cfe41cSRob Clark } 661657cfe41cSRob Clark #define A6XX_SP_TP_MODE_CNTL_UNK3__MASK 0x000000fc 661757cfe41cSRob Clark #define A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT 2 661857cfe41cSRob Clark static inline uint32_t A6XX_SP_TP_MODE_CNTL_UNK3(uint32_t val) 661957cfe41cSRob Clark { 662057cfe41cSRob Clark return ((val) << A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT) & A6XX_SP_TP_MODE_CNTL_UNK3__MASK; 662157cfe41cSRob Clark } 6622a69c5ed2SRob Clark 66232d756322SRob Clark #define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0 66242d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff 66252d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 6626c28c82e9SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val) 66272d756322SRob Clark { 66282d756322SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK; 66292d756322SRob Clark } 66302d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300 66312d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT 8 66322d756322SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val) 66332d756322SRob Clark { 66342d756322SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK; 66352d756322SRob Clark } 66362d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00 66372d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10 66382d756322SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) 66392d756322SRob Clark { 66402d756322SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK; 66412d756322SRob Clark } 66422d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000 6643c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_SRGB 0x00002000 6644c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK 0x0000c000 6645c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT 14 6646c28c82e9SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val) 6647c28c82e9SRob Clark { 6648c28c82e9SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK; 6649c28c82e9SRob Clark } 6650ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000 6651cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK17 0x00020000 6652c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE 0x00040000 6653cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK19 0x00080000 6654c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK20 0x00100000 6655cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK21 0x00200000 6656c28c82e9SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK22 0x00400000 6657cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK 0x07800000 6658cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT 23 6659cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val) 6660cc4c26d4SRob Clark { 6661cc4c26d4SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK; 6662cc4c26d4SRob Clark } 6663cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_UNK28 0x10000000 6664ccdf7e28SRob Clark 6665ccdf7e28SRob Clark #define REG_A6XX_SP_PS_2D_SRC_SIZE 0x0000b4c1 6666ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff 6667ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT 0 6668ccdf7e28SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val) 6669ccdf7e28SRob Clark { 6670ccdf7e28SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK; 6671ccdf7e28SRob Clark } 6672ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK 0x3fff8000 6673ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT 15 6674ccdf7e28SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val) 6675ccdf7e28SRob Clark { 6676ccdf7e28SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK; 6677ccdf7e28SRob Clark } 66782d756322SRob Clark 6679c28c82e9SRob Clark #define REG_A6XX_SP_PS_2D_SRC 0x0000b4c2 6680cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC__MASK 0xffffffff 6681cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC__SHIFT 0 6682cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC(uint32_t val) 6683cc4c26d4SRob Clark { 6684cc4c26d4SRob Clark return ((val) << A6XX_SP_PS_2D_SRC__SHIFT) & A6XX_SP_PS_2D_SRC__MASK; 6685cc4c26d4SRob Clark } 6686c28c82e9SRob Clark 6687ccdf7e28SRob Clark #define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4 6688cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK 0x000001ff 6689cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT 0 6690cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val) 6691cc4c26d4SRob Clark { 6692cc4c26d4SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK; 6693cc4c26d4SRob Clark } 6694cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x00fffe00 6695ccdf7e28SRob Clark #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9 6696ccdf7e28SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val) 6697ccdf7e28SRob Clark { 6698ccdf7e28SRob Clark return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK; 6699ccdf7e28SRob Clark } 6700ccdf7e28SRob Clark 6701cc4c26d4SRob Clark #define REG_A6XX_SP_PS_2D_SRC_PLANE1 0x0000b4c5 6702cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PLANE1__MASK 0xffffffff 6703cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PLANE1__SHIFT 0 6704cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE1(uint32_t val) 6705cc4c26d4SRob Clark { 6706cc4c26d4SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_PLANE1__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE1__MASK; 6707cc4c26d4SRob Clark } 67082d756322SRob Clark 6709cc4c26d4SRob Clark #define REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH 0x0000b4c7 6710cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK 0x00000fff 6711cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT 0 6712cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val) 6713cc4c26d4SRob Clark { 6714cc4c26d4SRob Clark return ((val >> 6) << A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK; 6715cc4c26d4SRob Clark } 6716cc4c26d4SRob Clark 6717cc4c26d4SRob Clark #define REG_A6XX_SP_PS_2D_SRC_PLANE2 0x0000b4c8 6718cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PLANE2__MASK 0xffffffff 6719cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_PLANE2__SHIFT 0 6720cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE2(uint32_t val) 6721cc4c26d4SRob Clark { 6722cc4c26d4SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_PLANE2__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE2__MASK; 6723cc4c26d4SRob Clark } 67242d756322SRob Clark 6725c28c82e9SRob Clark #define REG_A6XX_SP_PS_2D_SRC_FLAGS 0x0000b4ca 6726cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_FLAGS__MASK 0xffffffff 6727cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_FLAGS__SHIFT 0 6728cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS(uint32_t val) 6729cc4c26d4SRob Clark { 6730cc4c26d4SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_FLAGS__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS__MASK; 6731cc4c26d4SRob Clark } 6732c28c82e9SRob Clark 6733c28c82e9SRob Clark #define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b4cc 6734cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK 0x000000ff 6735cc4c26d4SRob Clark #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT 0 6736cc4c26d4SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val) 6737c28c82e9SRob Clark { 6738cc4c26d4SRob Clark return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK; 6739c28c82e9SRob Clark } 6740c28c82e9SRob Clark 6741cc4c26d4SRob Clark #define REG_A6XX_SP_PS_UNKNOWN_B4CD 0x0000b4cd 67422d756322SRob Clark 6743cc4c26d4SRob Clark #define REG_A6XX_SP_PS_UNKNOWN_B4CE 0x0000b4ce 6744cc4c26d4SRob Clark 6745cc4c26d4SRob Clark #define REG_A6XX_SP_PS_UNKNOWN_B4CF 0x0000b4cf 6746cc4c26d4SRob Clark 6747cc4c26d4SRob Clark #define REG_A6XX_SP_PS_UNKNOWN_B4D0 0x0000b4d0 6748cc4c26d4SRob Clark 6749cc4c26d4SRob Clark #define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1 6750cc4c26d4SRob Clark #define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00003fff 6751cc4c26d4SRob Clark #define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0 6752cc4c26d4SRob Clark static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val) 6753cc4c26d4SRob Clark { 6754cc4c26d4SRob Clark return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK; 6755cc4c26d4SRob Clark } 6756cc4c26d4SRob Clark #define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x3fff0000 6757cc4c26d4SRob Clark #define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16 6758cc4c26d4SRob Clark static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val) 6759cc4c26d4SRob Clark { 6760cc4c26d4SRob Clark return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK; 6761cc4c26d4SRob Clark } 6762cc4c26d4SRob Clark 676357cfe41cSRob Clark #define REG_A6XX_TPL1_DBG_ECO_CNTL 0x0000b600 6764cc4c26d4SRob Clark 6765cc4c26d4SRob Clark #define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601 6766cc4c26d4SRob Clark 6767cc4c26d4SRob Clark #define REG_A6XX_TPL1_UNKNOWN_B602 0x0000b602 6768cc4c26d4SRob Clark 6769cc4c26d4SRob Clark #define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604 6770cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_MODE 0x00000001 6771cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006 6772cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT 1 6773cc4c26d4SRob Clark static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT(uint32_t val) 6774cc4c26d4SRob Clark { 6775cc4c26d4SRob Clark return ((val) << A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK; 6776cc4c26d4SRob Clark } 6777cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008 6778cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000010 6779cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT 4 6780cc4c26d4SRob Clark static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT(uint32_t val) 6781cc4c26d4SRob Clark { 6782cc4c26d4SRob Clark return ((val) << A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK; 6783cc4c26d4SRob Clark } 6784cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK 0x000000c0 6785cc4c26d4SRob Clark #define A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT 6 6786cc4c26d4SRob Clark static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UNK6(uint32_t val) 6787cc4c26d4SRob Clark { 6788cc4c26d4SRob Clark return ((val) << A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK; 6789cc4c26d4SRob Clark } 6790cc4c26d4SRob Clark 6791cc4c26d4SRob Clark #define REG_A6XX_TPL1_UNKNOWN_B605 0x0000b605 6792cc4c26d4SRob Clark 6793cc4c26d4SRob Clark #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608 6794cc4c26d4SRob Clark 6795cc4c26d4SRob Clark #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609 6796cc4c26d4SRob Clark 6797cc4c26d4SRob Clark #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a 6798cc4c26d4SRob Clark 6799cc4c26d4SRob Clark #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b 6800cc4c26d4SRob Clark 6801cc4c26d4SRob Clark #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c 6802cc4c26d4SRob Clark 6803cc4c26d4SRob Clark static inline uint32_t REG_A6XX_TPL1_PERFCTR_TP_SEL(uint32_t i0) { return 0x0000b610 + 0x1*i0; } 68042d756322SRob Clark 68052d756322SRob Clark #define REG_A6XX_HLSQ_VS_CNTL 0x0000b800 68062d756322SRob Clark #define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff 68072d756322SRob Clark #define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0 68082d756322SRob Clark static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val) 68092d756322SRob Clark { 68102d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK; 68112d756322SRob Clark } 6812c28c82e9SRob Clark #define A6XX_HLSQ_VS_CNTL_ENABLED 0x00000100 68132d756322SRob Clark 68142d756322SRob Clark #define REG_A6XX_HLSQ_HS_CNTL 0x0000b801 68152d756322SRob Clark #define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff 68162d756322SRob Clark #define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0 68172d756322SRob Clark static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val) 68182d756322SRob Clark { 68192d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK; 68202d756322SRob Clark } 6821c28c82e9SRob Clark #define A6XX_HLSQ_HS_CNTL_ENABLED 0x00000100 68222d756322SRob Clark 68232d756322SRob Clark #define REG_A6XX_HLSQ_DS_CNTL 0x0000b802 68242d756322SRob Clark #define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff 68252d756322SRob Clark #define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0 68262d756322SRob Clark static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val) 68272d756322SRob Clark { 68282d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK; 68292d756322SRob Clark } 6830c28c82e9SRob Clark #define A6XX_HLSQ_DS_CNTL_ENABLED 0x00000100 68312d756322SRob Clark 68322d756322SRob Clark #define REG_A6XX_HLSQ_GS_CNTL 0x0000b803 68332d756322SRob Clark #define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff 68342d756322SRob Clark #define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0 68352d756322SRob Clark static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val) 68362d756322SRob Clark { 68372d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK; 68382d756322SRob Clark } 6839c28c82e9SRob Clark #define A6XX_HLSQ_GS_CNTL_ENABLED 0x00000100 6840c28c82e9SRob Clark 6841c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD 0x0000b820 6842c28c82e9SRob Clark 6843c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR 0x0000b821 6844cc4c26d4SRob Clark #define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK 0xffffffff 6845cc4c26d4SRob Clark #define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT 0 6846cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR(uint32_t val) 6847cc4c26d4SRob Clark { 6848cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK; 6849cc4c26d4SRob Clark } 6850c28c82e9SRob Clark 6851c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA 0x0000b823 68522d756322SRob Clark 6853cc4c26d4SRob Clark #define REG_A6XX_HLSQ_FS_CNTL_0 0x0000b980 6854cc4c26d4SRob Clark #define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK 0x00000001 6855cc4c26d4SRob Clark #define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT 0 6856cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val) 6857cc4c26d4SRob Clark { 6858cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK; 6859cc4c26d4SRob Clark } 6860cc4c26d4SRob Clark #define A6XX_HLSQ_FS_CNTL_0_VARYINGS 0x00000002 6861cc4c26d4SRob Clark #define A6XX_HLSQ_FS_CNTL_0_UNK2__MASK 0x00000ffc 6862cc4c26d4SRob Clark #define A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT 2 6863cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val) 6864cc4c26d4SRob Clark { 6865cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A6XX_HLSQ_FS_CNTL_0_UNK2__MASK; 6866cc4c26d4SRob Clark } 6867cc4c26d4SRob Clark 6868cc4c26d4SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_B981 0x0000b981 6869a69c5ed2SRob Clark 68702d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982 68712d756322SRob Clark 68722d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_2_REG 0x0000b983 68732d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff 68742d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0 68752d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) 68762d756322SRob Clark { 68772d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; 68782d756322SRob Clark } 68792d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00 68802d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8 68812d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) 68822d756322SRob Clark { 68832d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK; 68842d756322SRob Clark } 68852d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000 68862d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16 68872d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) 68882d756322SRob Clark { 68892d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK; 68902d756322SRob Clark } 6891c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK 0xff000000 6892c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT 24 6893c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SIZE(uint32_t val) 6894c28c82e9SRob Clark { 6895c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK; 6896c28c82e9SRob Clark } 68972d756322SRob Clark 68982d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_3_REG 0x0000b984 6899c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff 6900c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0 6901c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val) 69022d756322SRob Clark { 6903c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK; 6904c28c82e9SRob Clark } 6905c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00 6906c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8 6907c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val) 6908c28c82e9SRob Clark { 6909c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK; 6910c28c82e9SRob Clark } 6911c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000 6912c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16 6913c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val) 6914c28c82e9SRob Clark { 6915c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK; 6916c28c82e9SRob Clark } 6917c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000 6918c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24 6919c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) 6920c28c82e9SRob Clark { 6921c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK; 69222d756322SRob Clark } 69232d756322SRob Clark 69242d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_4_REG 0x0000b985 6925c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff 6926c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0 6927c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val) 6928c28c82e9SRob Clark { 6929c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK; 6930c28c82e9SRob Clark } 6931c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00 6932c28c82e9SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8 6933c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val) 6934c28c82e9SRob Clark { 6935c28c82e9SRob Clark return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK; 6936c28c82e9SRob Clark } 69372d756322SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000 69382d756322SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16 69392d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) 69402d756322SRob Clark { 69412d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK; 69422d756322SRob Clark } 69432d756322SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000 69442d756322SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24 69452d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) 69462d756322SRob Clark { 69472d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; 69482d756322SRob Clark } 69492d756322SRob Clark 69502d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986 695157cfe41cSRob Clark #define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK 0x000000ff 695257cfe41cSRob Clark #define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT 0 695357cfe41cSRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val) 6954cc4c26d4SRob Clark { 695557cfe41cSRob Clark return ((val) << A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK; 6956cc4c26d4SRob Clark } 695757cfe41cSRob Clark #define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK 0x0000ff00 695857cfe41cSRob Clark #define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT 8 695957cfe41cSRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val) 6960cc4c26d4SRob Clark { 696157cfe41cSRob Clark return ((val) << A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK; 6962cc4c26d4SRob Clark } 69632d756322SRob Clark 6964c28c82e9SRob Clark #define REG_A6XX_HLSQ_CS_CNTL 0x0000b987 6965c28c82e9SRob Clark #define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff 6966c28c82e9SRob Clark #define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0 6967c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val) 6968c28c82e9SRob Clark { 6969c28c82e9SRob Clark return ((val >> 2) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK; 6970c28c82e9SRob Clark } 6971c28c82e9SRob Clark #define A6XX_HLSQ_CS_CNTL_ENABLED 0x00000100 6972c28c82e9SRob Clark 69732d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_0 0x0000b990 69742d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003 69752d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0 69762d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) 69772d756322SRob Clark { 69782d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK; 69792d756322SRob Clark } 69802d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc 69812d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2 69822d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) 69832d756322SRob Clark { 69842d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK; 69852d756322SRob Clark } 69862d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000 69872d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12 69882d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) 69892d756322SRob Clark { 69902d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK; 69912d756322SRob Clark } 69922d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000 69932d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22 69942d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) 69952d756322SRob Clark { 69962d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK; 69972d756322SRob Clark } 69982d756322SRob Clark 69992d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_1 0x0000b991 70002d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff 70012d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0 70022d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val) 70032d756322SRob Clark { 70042d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK; 70052d756322SRob Clark } 70062d756322SRob Clark 70072d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_2 0x0000b992 70082d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff 70092d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0 70102d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val) 70112d756322SRob Clark { 70122d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK; 70132d756322SRob Clark } 70142d756322SRob Clark 70152d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_3 0x0000b993 70162d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff 70172d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0 70182d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val) 70192d756322SRob Clark { 70202d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK; 70212d756322SRob Clark } 70222d756322SRob Clark 70232d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_4 0x0000b994 70242d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff 70252d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0 70262d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val) 70272d756322SRob Clark { 70282d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK; 70292d756322SRob Clark } 70302d756322SRob Clark 70312d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_5 0x0000b995 70322d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff 70332d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0 70342d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val) 70352d756322SRob Clark { 70362d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK; 70372d756322SRob Clark } 70382d756322SRob Clark 70392d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_6 0x0000b996 70402d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff 70412d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0 70422d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val) 70432d756322SRob Clark { 70442d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK; 70452d756322SRob Clark } 70462d756322SRob Clark 70472d756322SRob Clark #define REG_A6XX_HLSQ_CS_CNTL_0 0x0000b997 70482d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff 70492d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0 70502d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val) 70512d756322SRob Clark { 70522d756322SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK; 70532d756322SRob Clark } 7054cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK 0x0000ff00 7055cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT 8 7056cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(uint32_t val) 70572d756322SRob Clark { 7058cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK; 70592d756322SRob Clark } 7060cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK 0x00ff0000 7061cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT 16 7062cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val) 70632d756322SRob Clark { 7064cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK; 70652d756322SRob Clark } 70662d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000 70672d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24 70682d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) 70692d756322SRob Clark { 70702d756322SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK; 70712d756322SRob Clark } 70722d756322SRob Clark 7073cc4c26d4SRob Clark #define REG_A6XX_HLSQ_CS_CNTL_1 0x0000b998 7074cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff 7075cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0 7076cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) 7077cc4c26d4SRob Clark { 7078cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK; 7079cc4c26d4SRob Clark } 7080cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_1_SINGLE_SP_CORE 0x00000100 7081cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK 0x00000200 7082cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT 9 7083cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) 7084cc4c26d4SRob Clark { 7085cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK; 7086cc4c26d4SRob Clark } 7087cc4c26d4SRob Clark #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400 7088c28c82e9SRob Clark 70892d756322SRob Clark #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X 0x0000b999 70902d756322SRob Clark 70912d756322SRob Clark #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000b99a 70922d756322SRob Clark 70932d756322SRob Clark #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000b99b 70942d756322SRob Clark 7095c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD 0x0000b9a0 7096c28c82e9SRob Clark 7097c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR 0x0000b9a1 7098cc4c26d4SRob Clark #define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK 0xffffffff 7099cc4c26d4SRob Clark #define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT 0 7100cc4c26d4SRob Clark static inline uint32_t A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR(uint32_t val) 7101cc4c26d4SRob Clark { 7102cc4c26d4SRob Clark return ((val) << A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK; 7103cc4c26d4SRob Clark } 7104c28c82e9SRob Clark 7105c28c82e9SRob Clark #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA 0x0000b9a3 7106c28c82e9SRob Clark 7107c28c82e9SRob Clark static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; } 7108c28c82e9SRob Clark 7109c28c82e9SRob Clark static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; } 7110c28c82e9SRob Clark 711157cfe41cSRob Clark #define REG_A6XX_HLSQ_CS_UNKNOWN_B9D0 0x0000b9d0 711257cfe41cSRob Clark #define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK 0x0000001f 711357cfe41cSRob Clark #define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT 0 711457cfe41cSRob Clark static inline uint32_t A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE(uint32_t val) 711557cfe41cSRob Clark { 711657cfe41cSRob Clark return ((val) << A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT) & A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK; 711757cfe41cSRob Clark } 711857cfe41cSRob Clark #define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK5 0x00000020 711957cfe41cSRob Clark #define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK6 0x00000040 712057cfe41cSRob Clark 7121c28c82e9SRob Clark #define REG_A6XX_HLSQ_DRAW_CMD 0x0000bb00 7122c28c82e9SRob Clark #define A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK 0x000000ff 7123c28c82e9SRob Clark #define A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT 0 7124c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_DRAW_CMD_STATE_ID(uint32_t val) 7125c28c82e9SRob Clark { 7126c28c82e9SRob Clark return ((val) << A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK; 7127c28c82e9SRob Clark } 7128c28c82e9SRob Clark 7129c28c82e9SRob Clark #define REG_A6XX_HLSQ_DISPATCH_CMD 0x0000bb01 7130c28c82e9SRob Clark #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK 0x000000ff 7131c28c82e9SRob Clark #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT 0 7132c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_DISPATCH_CMD_STATE_ID(uint32_t val) 7133c28c82e9SRob Clark { 7134c28c82e9SRob Clark return ((val) << A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK; 7135c28c82e9SRob Clark } 7136c28c82e9SRob Clark 7137c28c82e9SRob Clark #define REG_A6XX_HLSQ_EVENT_CMD 0x0000bb02 7138c28c82e9SRob Clark #define A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK 0x00ff0000 7139c28c82e9SRob Clark #define A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT 16 7140c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_EVENT_CMD_STATE_ID(uint32_t val) 7141c28c82e9SRob Clark { 7142c28c82e9SRob Clark return ((val) << A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK; 7143c28c82e9SRob Clark } 7144c28c82e9SRob Clark #define A6XX_HLSQ_EVENT_CMD_EVENT__MASK 0x0000007f 7145c28c82e9SRob Clark #define A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT 0 7146c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_EVENT_CMD_EVENT(enum vgt_event_type val) 7147c28c82e9SRob Clark { 7148c28c82e9SRob Clark return ((val) << A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_EVENT_CMD_EVENT__MASK; 7149c28c82e9SRob Clark } 7150c28c82e9SRob Clark 7151c28c82e9SRob Clark #define REG_A6XX_HLSQ_INVALIDATE_CMD 0x0000bb08 7152c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_VS_STATE 0x00000001 7153c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_HS_STATE 0x00000002 7154c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_DS_STATE 0x00000004 7155c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_GS_STATE 0x00000008 7156c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_FS_STATE 0x00000010 7157c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_CS_STATE 0x00000020 7158c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_CS_IBO 0x00000040 7159c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO 0x00000080 7160c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_CS_SHARED_CONST 0x00080000 7161c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_GFX_SHARED_CONST 0x00000100 7162c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK 0x00003e00 7163c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT 9 7164c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val) 7165c28c82e9SRob Clark { 7166c28c82e9SRob Clark return ((val) << A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK; 7167c28c82e9SRob Clark } 7168c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK 0x0007c000 7169c28c82e9SRob Clark #define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT 14 7170c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val) 7171c28c82e9SRob Clark { 7172c28c82e9SRob Clark return ((val) << A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK; 7173c28c82e9SRob Clark } 71742d756322SRob Clark 71752d756322SRob Clark #define REG_A6XX_HLSQ_FS_CNTL 0x0000bb10 71762d756322SRob Clark #define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff 71772d756322SRob Clark #define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0 71782d756322SRob Clark static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val) 71792d756322SRob Clark { 71802d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK; 71812d756322SRob Clark } 7182c28c82e9SRob Clark #define A6XX_HLSQ_FS_CNTL_ENABLED 0x00000100 71832d756322SRob Clark 7184c28c82e9SRob Clark #define REG_A6XX_HLSQ_SHARED_CONSTS 0x0000bb11 7185c28c82e9SRob Clark #define A6XX_HLSQ_SHARED_CONSTS_ENABLE 0x00000001 7186c28c82e9SRob Clark 7187c28c82e9SRob Clark static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE(uint32_t i0) { return 0x0000bb20 + 0x2*i0; } 7188c28c82e9SRob Clark 7189c28c82e9SRob Clark static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000bb20 + 0x2*i0; } 7190c28c82e9SRob Clark 7191c28c82e9SRob Clark #define REG_A6XX_HLSQ_2D_EVENT_CMD 0x0000bd80 7192c28c82e9SRob Clark #define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00 7193c28c82e9SRob Clark #define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT 8 7194c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_STATE_ID(uint32_t val) 7195c28c82e9SRob Clark { 7196c28c82e9SRob Clark return ((val) << A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK; 7197c28c82e9SRob Clark } 7198c28c82e9SRob Clark #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK 0x0000007f 7199c28c82e9SRob Clark #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT 0 7200c28c82e9SRob Clark static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val) 7201c28c82e9SRob Clark { 7202c28c82e9SRob Clark return ((val) << A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK; 7203c28c82e9SRob Clark } 72042d756322SRob Clark 72052d756322SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_BE00 0x0000be00 72062d756322SRob Clark 72072d756322SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_BE01 0x0000be01 72082d756322SRob Clark 72092d756322SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_BE04 0x0000be04 72102d756322SRob Clark 7211cc4c26d4SRob Clark #define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05 7212cc4c26d4SRob Clark 7213cc4c26d4SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_BE08 0x0000be08 7214cc4c26d4SRob Clark 7215cc4c26d4SRob Clark static inline uint32_t REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000be10 + 0x1*i0; } 7216cc4c26d4SRob Clark 721757cfe41cSRob Clark #define REG_A6XX_HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE 0x0000be22 721857cfe41cSRob Clark 7219c28c82e9SRob Clark #define REG_A6XX_CP_EVENT_START 0x0000d600 7220c28c82e9SRob Clark #define A6XX_CP_EVENT_START_STATE_ID__MASK 0x000000ff 7221c28c82e9SRob Clark #define A6XX_CP_EVENT_START_STATE_ID__SHIFT 0 7222c28c82e9SRob Clark static inline uint32_t A6XX_CP_EVENT_START_STATE_ID(uint32_t val) 7223c28c82e9SRob Clark { 7224c28c82e9SRob Clark return ((val) << A6XX_CP_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_EVENT_START_STATE_ID__MASK; 7225c28c82e9SRob Clark } 7226c28c82e9SRob Clark 7227c28c82e9SRob Clark #define REG_A6XX_CP_EVENT_END 0x0000d601 7228c28c82e9SRob Clark #define A6XX_CP_EVENT_END_STATE_ID__MASK 0x000000ff 7229c28c82e9SRob Clark #define A6XX_CP_EVENT_END_STATE_ID__SHIFT 0 7230c28c82e9SRob Clark static inline uint32_t A6XX_CP_EVENT_END_STATE_ID(uint32_t val) 7231c28c82e9SRob Clark { 7232c28c82e9SRob Clark return ((val) << A6XX_CP_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_EVENT_END_STATE_ID__MASK; 7233c28c82e9SRob Clark } 7234c28c82e9SRob Clark 7235c28c82e9SRob Clark #define REG_A6XX_CP_2D_EVENT_START 0x0000d700 7236c28c82e9SRob Clark #define A6XX_CP_2D_EVENT_START_STATE_ID__MASK 0x000000ff 7237c28c82e9SRob Clark #define A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT 0 7238c28c82e9SRob Clark static inline uint32_t A6XX_CP_2D_EVENT_START_STATE_ID(uint32_t val) 7239c28c82e9SRob Clark { 7240c28c82e9SRob Clark return ((val) << A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_START_STATE_ID__MASK; 7241c28c82e9SRob Clark } 7242c28c82e9SRob Clark 7243c28c82e9SRob Clark #define REG_A6XX_CP_2D_EVENT_END 0x0000d701 7244c28c82e9SRob Clark #define A6XX_CP_2D_EVENT_END_STATE_ID__MASK 0x000000ff 7245c28c82e9SRob Clark #define A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT 0 7246c28c82e9SRob Clark static inline uint32_t A6XX_CP_2D_EVENT_END_STATE_ID(uint32_t val) 7247c28c82e9SRob Clark { 7248c28c82e9SRob Clark return ((val) << A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_END_STATE_ID__MASK; 7249c28c82e9SRob Clark } 7250c28c82e9SRob Clark 72512d756322SRob Clark #define REG_A6XX_TEX_SAMP_0 0x00000000 72522d756322SRob Clark #define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 72532d756322SRob Clark #define A6XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 72542d756322SRob Clark #define A6XX_TEX_SAMP_0_XY_MAG__SHIFT 1 72552d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val) 72562d756322SRob Clark { 72572d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_XY_MAG__SHIFT) & A6XX_TEX_SAMP_0_XY_MAG__MASK; 72582d756322SRob Clark } 72592d756322SRob Clark #define A6XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 72602d756322SRob Clark #define A6XX_TEX_SAMP_0_XY_MIN__SHIFT 3 72612d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val) 72622d756322SRob Clark { 72632d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_XY_MIN__SHIFT) & A6XX_TEX_SAMP_0_XY_MIN__MASK; 72642d756322SRob Clark } 72652d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 72662d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_S__SHIFT 5 72672d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val) 72682d756322SRob Clark { 72692d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_WRAP_S__SHIFT) & A6XX_TEX_SAMP_0_WRAP_S__MASK; 72702d756322SRob Clark } 72712d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 72722d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_T__SHIFT 8 72732d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val) 72742d756322SRob Clark { 72752d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_WRAP_T__SHIFT) & A6XX_TEX_SAMP_0_WRAP_T__MASK; 72762d756322SRob Clark } 72772d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 72782d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_R__SHIFT 11 72792d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val) 72802d756322SRob Clark { 72812d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_WRAP_R__SHIFT) & A6XX_TEX_SAMP_0_WRAP_R__MASK; 72822d756322SRob Clark } 72832d756322SRob Clark #define A6XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 72842d756322SRob Clark #define A6XX_TEX_SAMP_0_ANISO__SHIFT 14 72852d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val) 72862d756322SRob Clark { 72872d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_ANISO__SHIFT) & A6XX_TEX_SAMP_0_ANISO__MASK; 72882d756322SRob Clark } 72892d756322SRob Clark #define A6XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000 72902d756322SRob Clark #define A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19 72912d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val) 72922d756322SRob Clark { 72932d756322SRob Clark return ((((int32_t)(val * 256.0))) << A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A6XX_TEX_SAMP_0_LOD_BIAS__MASK; 72942d756322SRob Clark } 72952d756322SRob Clark 72962d756322SRob Clark #define REG_A6XX_TEX_SAMP_1 0x00000001 729757cfe41cSRob Clark #define A6XX_TEX_SAMP_1_CLAMPENABLE 0x00000001 72982d756322SRob Clark #define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e 72992d756322SRob Clark #define A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 73002d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) 73012d756322SRob Clark { 73022d756322SRob Clark return ((val) << A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK; 73032d756322SRob Clark } 73042d756322SRob Clark #define A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010 73052d756322SRob Clark #define A6XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 73062d756322SRob Clark #define A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 73072d756322SRob Clark #define A6XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 73082d756322SRob Clark #define A6XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 73092d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_1_MAX_LOD(float val) 73102d756322SRob Clark { 73112d756322SRob Clark return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK; 73122d756322SRob Clark } 73132d756322SRob Clark #define A6XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 73142d756322SRob Clark #define A6XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 73152d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_1_MIN_LOD(float val) 73162d756322SRob Clark { 73172d756322SRob Clark return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK; 73182d756322SRob Clark } 73192d756322SRob Clark 73202d756322SRob Clark #define REG_A6XX_TEX_SAMP_2 0x00000002 7321c28c82e9SRob Clark #define A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK 0x00000003 7322c28c82e9SRob Clark #define A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT 0 7323c28c82e9SRob Clark static inline uint32_t A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode val) 7324c28c82e9SRob Clark { 7325c28c82e9SRob Clark return ((val) << A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT) & A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK; 7326c28c82e9SRob Clark } 7327c28c82e9SRob Clark #define A6XX_TEX_SAMP_2_CHROMA_LINEAR 0x00000020 7328cc4c26d4SRob Clark #define A6XX_TEX_SAMP_2_BCOLOR__MASK 0xffffff80 7329cc4c26d4SRob Clark #define A6XX_TEX_SAMP_2_BCOLOR__SHIFT 7 7330cc4c26d4SRob Clark static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR(uint32_t val) 73312d756322SRob Clark { 7332cc4c26d4SRob Clark return ((val) << A6XX_TEX_SAMP_2_BCOLOR__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR__MASK; 73332d756322SRob Clark } 73342d756322SRob Clark 73352d756322SRob Clark #define REG_A6XX_TEX_SAMP_3 0x00000003 73362d756322SRob Clark 73372d756322SRob Clark #define REG_A6XX_TEX_CONST_0 0x00000000 73382d756322SRob Clark #define A6XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003 73392d756322SRob Clark #define A6XX_TEX_CONST_0_TILE_MODE__SHIFT 0 73402d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val) 73412d756322SRob Clark { 73422d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_TILE_MODE__SHIFT) & A6XX_TEX_CONST_0_TILE_MODE__MASK; 73432d756322SRob Clark } 73442d756322SRob Clark #define A6XX_TEX_CONST_0_SRGB 0x00000004 73452d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 73462d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_X__SHIFT 4 73472d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val) 73482d756322SRob Clark { 73492d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWIZ_X__SHIFT) & A6XX_TEX_CONST_0_SWIZ_X__MASK; 73502d756322SRob Clark } 73512d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 73522d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 73532d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val) 73542d756322SRob Clark { 73552d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Y__MASK; 73562d756322SRob Clark } 73572d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 73582d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 73592d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val) 73602d756322SRob Clark { 73612d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Z__MASK; 73622d756322SRob Clark } 73632d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 73642d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_W__SHIFT 13 73652d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val) 73662d756322SRob Clark { 73672d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWIZ_W__SHIFT) & A6XX_TEX_CONST_0_SWIZ_W__MASK; 73682d756322SRob Clark } 73692d756322SRob Clark #define A6XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 73702d756322SRob Clark #define A6XX_TEX_CONST_0_MIPLVLS__SHIFT 16 73712d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val) 73722d756322SRob Clark { 73732d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK; 73742d756322SRob Clark } 7375c28c82e9SRob Clark #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X 0x00010000 7376c28c82e9SRob Clark #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y 0x00040000 7377ccdf7e28SRob Clark #define A6XX_TEX_CONST_0_SAMPLES__MASK 0x00300000 7378ccdf7e28SRob Clark #define A6XX_TEX_CONST_0_SAMPLES__SHIFT 20 7379ccdf7e28SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val) 7380ccdf7e28SRob Clark { 7381ccdf7e28SRob Clark return ((val) << A6XX_TEX_CONST_0_SAMPLES__SHIFT) & A6XX_TEX_CONST_0_SAMPLES__MASK; 7382ccdf7e28SRob Clark } 73832d756322SRob Clark #define A6XX_TEX_CONST_0_FMT__MASK 0x3fc00000 73842d756322SRob Clark #define A6XX_TEX_CONST_0_FMT__SHIFT 22 7385c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_format val) 73862d756322SRob Clark { 73872d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK; 73882d756322SRob Clark } 73892d756322SRob Clark #define A6XX_TEX_CONST_0_SWAP__MASK 0xc0000000 73902d756322SRob Clark #define A6XX_TEX_CONST_0_SWAP__SHIFT 30 73912d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val) 73922d756322SRob Clark { 73932d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWAP__SHIFT) & A6XX_TEX_CONST_0_SWAP__MASK; 73942d756322SRob Clark } 73952d756322SRob Clark 73962d756322SRob Clark #define REG_A6XX_TEX_CONST_1 0x00000001 73972d756322SRob Clark #define A6XX_TEX_CONST_1_WIDTH__MASK 0x00007fff 73982d756322SRob Clark #define A6XX_TEX_CONST_1_WIDTH__SHIFT 0 73992d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_1_WIDTH(uint32_t val) 74002d756322SRob Clark { 74012d756322SRob Clark return ((val) << A6XX_TEX_CONST_1_WIDTH__SHIFT) & A6XX_TEX_CONST_1_WIDTH__MASK; 74022d756322SRob Clark } 74032d756322SRob Clark #define A6XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000 74042d756322SRob Clark #define A6XX_TEX_CONST_1_HEIGHT__SHIFT 15 74052d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val) 74062d756322SRob Clark { 74072d756322SRob Clark return ((val) << A6XX_TEX_CONST_1_HEIGHT__SHIFT) & A6XX_TEX_CONST_1_HEIGHT__MASK; 74082d756322SRob Clark } 74092d756322SRob Clark 74102d756322SRob Clark #define REG_A6XX_TEX_CONST_2 0x00000002 741157cfe41cSRob Clark #define A6XX_TEX_CONST_2_BUFFER 0x00000010 7412c28c82e9SRob Clark #define A6XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f 7413c28c82e9SRob Clark #define A6XX_TEX_CONST_2_PITCHALIGN__SHIFT 0 7414c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_2_PITCHALIGN(uint32_t val) 74152d756322SRob Clark { 7416c28c82e9SRob Clark return ((val) << A6XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A6XX_TEX_CONST_2_PITCHALIGN__MASK; 74172d756322SRob Clark } 74182d756322SRob Clark #define A6XX_TEX_CONST_2_PITCH__MASK 0x1fffff80 74192d756322SRob Clark #define A6XX_TEX_CONST_2_PITCH__SHIFT 7 74202d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_2_PITCH(uint32_t val) 74212d756322SRob Clark { 74222d756322SRob Clark return ((val) << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK; 74232d756322SRob Clark } 742457cfe41cSRob Clark #define A6XX_TEX_CONST_2_TYPE__MASK 0xe0000000 74252d756322SRob Clark #define A6XX_TEX_CONST_2_TYPE__SHIFT 29 74262d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val) 74272d756322SRob Clark { 74282d756322SRob Clark return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK; 74292d756322SRob Clark } 74302d756322SRob Clark 74312d756322SRob Clark #define REG_A6XX_TEX_CONST_3 0x00000003 74322d756322SRob Clark #define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff 74332d756322SRob Clark #define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0 74342d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) 74352d756322SRob Clark { 74362d756322SRob Clark return ((val >> 12) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK; 74372d756322SRob Clark } 7438c28c82e9SRob Clark #define A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000 7439c28c82e9SRob Clark #define A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23 7440c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val) 7441c28c82e9SRob Clark { 7442c28c82e9SRob Clark return ((val >> 12) << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK; 7443c28c82e9SRob Clark } 7444c28c82e9SRob Clark #define A6XX_TEX_CONST_3_TILE_ALL 0x08000000 74452d756322SRob Clark #define A6XX_TEX_CONST_3_FLAG 0x10000000 74462d756322SRob Clark 74472d756322SRob Clark #define REG_A6XX_TEX_CONST_4 0x00000004 74482d756322SRob Clark #define A6XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0 74492d756322SRob Clark #define A6XX_TEX_CONST_4_BASE_LO__SHIFT 5 74502d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val) 74512d756322SRob Clark { 74522d756322SRob Clark return ((val >> 5) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK; 74532d756322SRob Clark } 74542d756322SRob Clark 74552d756322SRob Clark #define REG_A6XX_TEX_CONST_5 0x00000005 74562d756322SRob Clark #define A6XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff 74572d756322SRob Clark #define A6XX_TEX_CONST_5_BASE_HI__SHIFT 0 74582d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_5_BASE_HI(uint32_t val) 74592d756322SRob Clark { 74602d756322SRob Clark return ((val) << A6XX_TEX_CONST_5_BASE_HI__SHIFT) & A6XX_TEX_CONST_5_BASE_HI__MASK; 74612d756322SRob Clark } 74622d756322SRob Clark #define A6XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000 74632d756322SRob Clark #define A6XX_TEX_CONST_5_DEPTH__SHIFT 17 74642d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_5_DEPTH(uint32_t val) 74652d756322SRob Clark { 74662d756322SRob Clark return ((val) << A6XX_TEX_CONST_5_DEPTH__SHIFT) & A6XX_TEX_CONST_5_DEPTH__MASK; 74672d756322SRob Clark } 74682d756322SRob Clark 74692d756322SRob Clark #define REG_A6XX_TEX_CONST_6 0x00000006 7470c28c82e9SRob Clark #define A6XX_TEX_CONST_6_PLANE_PITCH__MASK 0xffffff00 7471c28c82e9SRob Clark #define A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT 8 7472c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_6_PLANE_PITCH(uint32_t val) 7473c28c82e9SRob Clark { 7474c28c82e9SRob Clark return ((val) << A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT) & A6XX_TEX_CONST_6_PLANE_PITCH__MASK; 7475c28c82e9SRob Clark } 74762d756322SRob Clark 74772d756322SRob Clark #define REG_A6XX_TEX_CONST_7 0x00000007 74782d756322SRob Clark #define A6XX_TEX_CONST_7_FLAG_LO__MASK 0xffffffe0 74792d756322SRob Clark #define A6XX_TEX_CONST_7_FLAG_LO__SHIFT 5 74802d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val) 74812d756322SRob Clark { 74822d756322SRob Clark return ((val >> 5) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK; 74832d756322SRob Clark } 74842d756322SRob Clark 74852d756322SRob Clark #define REG_A6XX_TEX_CONST_8 0x00000008 7486a69c5ed2SRob Clark #define A6XX_TEX_CONST_8_FLAG_HI__MASK 0x0001ffff 7487a69c5ed2SRob Clark #define A6XX_TEX_CONST_8_FLAG_HI__SHIFT 0 7488a69c5ed2SRob Clark static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val) 74892d756322SRob Clark { 7490a69c5ed2SRob Clark return ((val) << A6XX_TEX_CONST_8_FLAG_HI__SHIFT) & A6XX_TEX_CONST_8_FLAG_HI__MASK; 74912d756322SRob Clark } 74922d756322SRob Clark 74932d756322SRob Clark #define REG_A6XX_TEX_CONST_9 0x00000009 7494c28c82e9SRob Clark #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff 7495c28c82e9SRob Clark #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0 7496c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) 7497c28c82e9SRob Clark { 7498c28c82e9SRob Clark return ((val >> 4) << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK; 7499c28c82e9SRob Clark } 75002d756322SRob Clark 75012d756322SRob Clark #define REG_A6XX_TEX_CONST_10 0x0000000a 7502c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK 0x0000007f 7503c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT 0 7504c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val) 7505c28c82e9SRob Clark { 7506c28c82e9SRob Clark return ((val >> 6) << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK; 7507c28c82e9SRob Clark } 7508c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK 0x00000f00 7509c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT 8 7510c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(uint32_t val) 7511c28c82e9SRob Clark { 7512c28c82e9SRob Clark return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK; 7513c28c82e9SRob Clark } 7514c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK 0x0000f000 7515c28c82e9SRob Clark #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT 12 7516c28c82e9SRob Clark static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(uint32_t val) 7517c28c82e9SRob Clark { 7518c28c82e9SRob Clark return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK; 7519c28c82e9SRob Clark } 75202d756322SRob Clark 75212d756322SRob Clark #define REG_A6XX_TEX_CONST_11 0x0000000b 75222d756322SRob Clark 75232d756322SRob Clark #define REG_A6XX_TEX_CONST_12 0x0000000c 75242d756322SRob Clark 75252d756322SRob Clark #define REG_A6XX_TEX_CONST_13 0x0000000d 75262d756322SRob Clark 75272d756322SRob Clark #define REG_A6XX_TEX_CONST_14 0x0000000e 75282d756322SRob Clark 75292d756322SRob Clark #define REG_A6XX_TEX_CONST_15 0x0000000f 75302d756322SRob Clark 7531c28c82e9SRob Clark #define REG_A6XX_UBO_0 0x00000000 7532c28c82e9SRob Clark #define A6XX_UBO_0_BASE_LO__MASK 0xffffffff 7533c28c82e9SRob Clark #define A6XX_UBO_0_BASE_LO__SHIFT 0 7534c28c82e9SRob Clark static inline uint32_t A6XX_UBO_0_BASE_LO(uint32_t val) 7535c28c82e9SRob Clark { 7536c28c82e9SRob Clark return ((val) << A6XX_UBO_0_BASE_LO__SHIFT) & A6XX_UBO_0_BASE_LO__MASK; 7537c28c82e9SRob Clark } 7538c28c82e9SRob Clark 7539c28c82e9SRob Clark #define REG_A6XX_UBO_1 0x00000001 7540c28c82e9SRob Clark #define A6XX_UBO_1_BASE_HI__MASK 0x0001ffff 7541c28c82e9SRob Clark #define A6XX_UBO_1_BASE_HI__SHIFT 0 7542c28c82e9SRob Clark static inline uint32_t A6XX_UBO_1_BASE_HI(uint32_t val) 7543c28c82e9SRob Clark { 7544c28c82e9SRob Clark return ((val) << A6XX_UBO_1_BASE_HI__SHIFT) & A6XX_UBO_1_BASE_HI__MASK; 7545c28c82e9SRob Clark } 7546c28c82e9SRob Clark #define A6XX_UBO_1_SIZE__MASK 0xfffe0000 7547c28c82e9SRob Clark #define A6XX_UBO_1_SIZE__SHIFT 17 7548c28c82e9SRob Clark static inline uint32_t A6XX_UBO_1_SIZE(uint32_t val) 7549c28c82e9SRob Clark { 7550c28c82e9SRob Clark return ((val) << A6XX_UBO_1_SIZE__SHIFT) & A6XX_UBO_1_SIZE__MASK; 7551c28c82e9SRob Clark } 7552c28c82e9SRob Clark 7553a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_ENABLE_PDC 0x00001140 7554a69c5ed2SRob Clark 7555a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_SEQ_START_ADDR 0x00001148 7556a69c5ed2SRob Clark 7557a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CONTROL 0x00001540 7558a69c5ed2SRob Clark 7559a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK 0x00001541 7560a69c5ed2SRob Clark 7561a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK 0x00001542 7562a69c5ed2SRob Clark 7563a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID 0x00001543 7564a69c5ed2SRob Clark 7565a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR 0x00001544 7566a69c5ed2SRob Clark 7567a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA 0x00001545 7568a69c5ed2SRob Clark 7569a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CONTROL 0x00001572 7570a69c5ed2SRob Clark 7571a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK 0x00001573 7572a69c5ed2SRob Clark 7573a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK 0x00001574 7574a69c5ed2SRob Clark 7575a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID 0x00001575 7576a69c5ed2SRob Clark 7577a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR 0x00001576 7578a69c5ed2SRob Clark 7579a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA 0x00001577 7580a69c5ed2SRob Clark 7581a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CONTROL 0x000015a4 7582a69c5ed2SRob Clark 7583a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK 0x000015a5 7584a69c5ed2SRob Clark 7585a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK 0x000015a6 7586a69c5ed2SRob Clark 7587a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID 0x000015a7 7588a69c5ed2SRob Clark 7589a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR 0x000015a8 7590a69c5ed2SRob Clark 7591a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA 0x000015a9 7592a69c5ed2SRob Clark 7593a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CONTROL 0x000015d6 7594a69c5ed2SRob Clark 7595a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK 0x000015d7 7596a69c5ed2SRob Clark 7597a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK 0x000015d8 7598a69c5ed2SRob Clark 7599a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID 0x000015d9 7600a69c5ed2SRob Clark 7601a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR 0x000015da 7602a69c5ed2SRob Clark 7603a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA 0x000015db 7604a69c5ed2SRob Clark 7605a69c5ed2SRob Clark #define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x00000000 7606a69c5ed2SRob Clark 7607a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A 0x00000000 7608a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK 0x000000ff 7609a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT 0 7610a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val) 7611a69c5ed2SRob Clark { 7612a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK; 7613a69c5ed2SRob Clark } 7614a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK 0x0000ff00 7615a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT 8 7616a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val) 7617a69c5ed2SRob Clark { 7618a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK; 7619a69c5ed2SRob Clark } 7620a69c5ed2SRob Clark 7621a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B 0x00000001 7622a69c5ed2SRob Clark 7623a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C 0x00000002 7624a69c5ed2SRob Clark 7625a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D 0x00000003 7626a69c5ed2SRob Clark 7627a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT 0x00000004 7628a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f 7629a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0 7630a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) 7631a69c5ed2SRob Clark { 7632a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; 7633a69c5ed2SRob Clark } 7634a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000 7635a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12 7636a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) 7637a69c5ed2SRob Clark { 7638a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; 7639a69c5ed2SRob Clark } 7640a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000 7641a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28 7642a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) 7643a69c5ed2SRob Clark { 7644a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; 7645a69c5ed2SRob Clark } 7646a69c5ed2SRob Clark 7647a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM 0x00000005 7648a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000 7649a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24 7650a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) 7651a69c5ed2SRob Clark { 7652a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; 7653a69c5ed2SRob Clark } 7654a69c5ed2SRob Clark 7655a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 0x00000008 7656a69c5ed2SRob Clark 7657a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 0x00000009 7658a69c5ed2SRob Clark 7659a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 0x0000000a 7660a69c5ed2SRob Clark 7661a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 0x0000000b 7662a69c5ed2SRob Clark 7663a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 0x0000000c 7664a69c5ed2SRob Clark 7665a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 0x0000000d 7666a69c5ed2SRob Clark 7667a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 0x0000000e 7668a69c5ed2SRob Clark 7669a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 0x0000000f 7670a69c5ed2SRob Clark 7671a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000010 7672a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f 7673a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0 7674a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) 7675a69c5ed2SRob Clark { 7676a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; 7677a69c5ed2SRob Clark } 7678a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0 7679a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4 7680a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) 7681a69c5ed2SRob Clark { 7682a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; 7683a69c5ed2SRob Clark } 7684a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00 7685a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8 7686a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) 7687a69c5ed2SRob Clark { 7688a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; 7689a69c5ed2SRob Clark } 7690a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000 7691a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12 7692a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) 7693a69c5ed2SRob Clark { 7694a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; 7695a69c5ed2SRob Clark } 7696a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000 7697a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16 7698a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) 7699a69c5ed2SRob Clark { 7700a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; 7701a69c5ed2SRob Clark } 7702a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000 7703a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20 7704a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) 7705a69c5ed2SRob Clark { 7706a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; 7707a69c5ed2SRob Clark } 7708a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000 7709a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24 7710a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) 7711a69c5ed2SRob Clark { 7712a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; 7713a69c5ed2SRob Clark } 7714a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000 7715a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28 7716a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) 7717a69c5ed2SRob Clark { 7718a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; 7719a69c5ed2SRob Clark } 7720a69c5ed2SRob Clark 7721a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000011 7722a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f 7723a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0 7724a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) 7725a69c5ed2SRob Clark { 7726a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; 7727a69c5ed2SRob Clark } 7728a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0 7729a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4 7730a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) 7731a69c5ed2SRob Clark { 7732a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; 7733a69c5ed2SRob Clark } 7734a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00 7735a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8 7736a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) 7737a69c5ed2SRob Clark { 7738a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; 7739a69c5ed2SRob Clark } 7740a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000 7741a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12 7742a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) 7743a69c5ed2SRob Clark { 7744a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; 7745a69c5ed2SRob Clark } 7746a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000 7747a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16 7748a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) 7749a69c5ed2SRob Clark { 7750a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; 7751a69c5ed2SRob Clark } 7752a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000 7753a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20 7754a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) 7755a69c5ed2SRob Clark { 7756a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; 7757a69c5ed2SRob Clark } 7758a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000 7759a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24 7760a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) 7761a69c5ed2SRob Clark { 7762a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; 7763a69c5ed2SRob Clark } 7764a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000 7765a69c5ed2SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28 7766a69c5ed2SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) 7767a69c5ed2SRob Clark { 7768a69c5ed2SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; 7769a69c5ed2SRob Clark } 7770a69c5ed2SRob Clark 7771a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000002f 7772a69c5ed2SRob Clark 7773a69c5ed2SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000030 7774a69c5ed2SRob Clark 7775ccdf7e28SRob Clark #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 0x00000001 7776ccdf7e28SRob Clark 7777ccdf7e28SRob Clark #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 0x00000002 7778ccdf7e28SRob Clark 77792d756322SRob Clark 77802d756322SRob Clark #endif /* A6XX_XML */ 7781