12d756322SRob Clark #ifndef A6XX_XML 22d756322SRob Clark #define A6XX_XML 32d756322SRob Clark 42d756322SRob Clark /* Autogenerated file, DO NOT EDIT manually! 52d756322SRob Clark 62d756322SRob Clark This file was generated by the rules-ng-ng headergen tool in this git repository: 72d756322SRob Clark http://github.com/freedreno/envytools/ 82d756322SRob Clark git clone https://github.com/freedreno/envytools.git 92d756322SRob Clark 102d756322SRob Clark The rules-ng-ng source files this header was generated from are: 112d756322SRob Clark - /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13) 122d756322SRob Clark - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13) 132d756322SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13) 142d756322SRob Clark - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13) 152d756322SRob Clark - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-06 18:45:45) 162d756322SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13) 172d756322SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13) 182d756322SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-08-06 18:45:45) 192d756322SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 101627 bytes, from 2018-08-06 18:45:45) 202d756322SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-07-03 19:37:13) 212d756322SRob Clark - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13) 222d756322SRob Clark 232d756322SRob Clark Copyright (C) 2013-2018 by the following authors: 242d756322SRob Clark - Rob Clark <robdclark@gmail.com> (robclark) 252d756322SRob Clark - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 262d756322SRob Clark 272d756322SRob Clark Permission is hereby granted, free of charge, to any person obtaining 282d756322SRob Clark a copy of this software and associated documentation files (the 292d756322SRob Clark "Software"), to deal in the Software without restriction, including 302d756322SRob Clark without limitation the rights to use, copy, modify, merge, publish, 312d756322SRob Clark distribute, sublicense, and/or sell copies of the Software, and to 322d756322SRob Clark permit persons to whom the Software is furnished to do so, subject to 332d756322SRob Clark the following conditions: 342d756322SRob Clark 352d756322SRob Clark The above copyright notice and this permission notice (including the 362d756322SRob Clark next paragraph) shall be included in all copies or substantial 372d756322SRob Clark portions of the Software. 382d756322SRob Clark 392d756322SRob Clark THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 402d756322SRob Clark EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 412d756322SRob Clark MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 422d756322SRob Clark IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 432d756322SRob Clark LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 442d756322SRob Clark OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 452d756322SRob Clark WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 462d756322SRob Clark */ 472d756322SRob Clark 482d756322SRob Clark 492d756322SRob Clark enum a6xx_color_fmt { 502d756322SRob Clark RB6_A8_UNORM = 2, 512d756322SRob Clark RB6_R8_UNORM = 3, 522d756322SRob Clark RB6_R8_SNORM = 4, 532d756322SRob Clark RB6_R8_UINT = 5, 542d756322SRob Clark RB6_R8_SINT = 6, 552d756322SRob Clark RB6_R4G4B4A4_UNORM = 8, 562d756322SRob Clark RB6_R5G5B5A1_UNORM = 10, 572d756322SRob Clark RB6_R5G6B5_UNORM = 14, 582d756322SRob Clark RB6_R8G8_UNORM = 15, 592d756322SRob Clark RB6_R8G8_SNORM = 16, 602d756322SRob Clark RB6_R8G8_UINT = 17, 612d756322SRob Clark RB6_R8G8_SINT = 18, 622d756322SRob Clark RB6_R16_UNORM = 21, 632d756322SRob Clark RB6_R16_SNORM = 22, 642d756322SRob Clark RB6_R16_FLOAT = 23, 652d756322SRob Clark RB6_R16_UINT = 24, 662d756322SRob Clark RB6_R16_SINT = 25, 672d756322SRob Clark RB6_R8G8B8A8_UNORM = 48, 682d756322SRob Clark RB6_R8G8B8_UNORM = 49, 692d756322SRob Clark RB6_R8G8B8A8_SNORM = 50, 702d756322SRob Clark RB6_R8G8B8A8_UINT = 51, 712d756322SRob Clark RB6_R8G8B8A8_SINT = 52, 722d756322SRob Clark RB6_R10G10B10A2_UNORM = 55, 732d756322SRob Clark RB6_R10G10B10A2_UINT = 58, 742d756322SRob Clark RB6_R11G11B10_FLOAT = 66, 752d756322SRob Clark RB6_R16G16_UNORM = 67, 762d756322SRob Clark RB6_R16G16_SNORM = 68, 772d756322SRob Clark RB6_R16G16_FLOAT = 69, 782d756322SRob Clark RB6_R16G16_UINT = 70, 792d756322SRob Clark RB6_R16G16_SINT = 71, 802d756322SRob Clark RB6_R32_FLOAT = 74, 812d756322SRob Clark RB6_R32_UINT = 75, 822d756322SRob Clark RB6_R32_SINT = 76, 832d756322SRob Clark RB6_R16G16B16A16_UNORM = 96, 842d756322SRob Clark RB6_R16G16B16A16_SNORM = 97, 852d756322SRob Clark RB6_R16G16B16A16_FLOAT = 98, 862d756322SRob Clark RB6_R16G16B16A16_UINT = 99, 872d756322SRob Clark RB6_R16G16B16A16_SINT = 100, 882d756322SRob Clark RB6_R32G32_FLOAT = 103, 892d756322SRob Clark RB6_R32G32_UINT = 104, 902d756322SRob Clark RB6_R32G32_SINT = 105, 912d756322SRob Clark RB6_R32G32B32A32_FLOAT = 130, 922d756322SRob Clark RB6_R32G32B32A32_UINT = 131, 932d756322SRob Clark RB6_R32G32B32A32_SINT = 132, 942d756322SRob Clark RB6_X8Z24_UNORM = 160, 952d756322SRob Clark }; 962d756322SRob Clark 972d756322SRob Clark enum a6xx_tile_mode { 982d756322SRob Clark TILE6_LINEAR = 0, 992d756322SRob Clark TILE6_2 = 2, 1002d756322SRob Clark TILE6_3 = 3, 1012d756322SRob Clark }; 1022d756322SRob Clark 1032d756322SRob Clark enum a6xx_vtx_fmt { 1042d756322SRob Clark VFMT6_8_UNORM = 3, 1052d756322SRob Clark VFMT6_8_SNORM = 4, 1062d756322SRob Clark VFMT6_8_UINT = 5, 1072d756322SRob Clark VFMT6_8_SINT = 6, 1082d756322SRob Clark VFMT6_8_8_UNORM = 15, 1092d756322SRob Clark VFMT6_8_8_SNORM = 16, 1102d756322SRob Clark VFMT6_8_8_UINT = 17, 1112d756322SRob Clark VFMT6_8_8_SINT = 18, 1122d756322SRob Clark VFMT6_16_UNORM = 21, 1132d756322SRob Clark VFMT6_16_SNORM = 22, 1142d756322SRob Clark VFMT6_16_FLOAT = 23, 1152d756322SRob Clark VFMT6_16_UINT = 24, 1162d756322SRob Clark VFMT6_16_SINT = 25, 1172d756322SRob Clark VFMT6_8_8_8_UNORM = 33, 1182d756322SRob Clark VFMT6_8_8_8_SNORM = 34, 1192d756322SRob Clark VFMT6_8_8_8_UINT = 35, 1202d756322SRob Clark VFMT6_8_8_8_SINT = 36, 1212d756322SRob Clark VFMT6_8_8_8_8_UNORM = 48, 1222d756322SRob Clark VFMT6_8_8_8_8_SNORM = 50, 1232d756322SRob Clark VFMT6_8_8_8_8_UINT = 51, 1242d756322SRob Clark VFMT6_8_8_8_8_SINT = 52, 1252d756322SRob Clark VFMT6_10_10_10_2_UNORM = 54, 1262d756322SRob Clark VFMT6_10_10_10_2_SNORM = 57, 1272d756322SRob Clark VFMT6_10_10_10_2_UINT = 58, 1282d756322SRob Clark VFMT6_10_10_10_2_SINT = 59, 1292d756322SRob Clark VFMT6_11_11_10_FLOAT = 66, 1302d756322SRob Clark VFMT6_16_16_UNORM = 67, 1312d756322SRob Clark VFMT6_16_16_SNORM = 68, 1322d756322SRob Clark VFMT6_16_16_FLOAT = 69, 1332d756322SRob Clark VFMT6_16_16_UINT = 70, 1342d756322SRob Clark VFMT6_16_16_SINT = 71, 1352d756322SRob Clark VFMT6_32_UNORM = 72, 1362d756322SRob Clark VFMT6_32_SNORM = 73, 1372d756322SRob Clark VFMT6_32_FLOAT = 74, 1382d756322SRob Clark VFMT6_32_UINT = 75, 1392d756322SRob Clark VFMT6_32_SINT = 76, 1402d756322SRob Clark VFMT6_32_FIXED = 77, 1412d756322SRob Clark VFMT6_16_16_16_UNORM = 88, 1422d756322SRob Clark VFMT6_16_16_16_SNORM = 89, 1432d756322SRob Clark VFMT6_16_16_16_FLOAT = 90, 1442d756322SRob Clark VFMT6_16_16_16_UINT = 91, 1452d756322SRob Clark VFMT6_16_16_16_SINT = 92, 1462d756322SRob Clark VFMT6_16_16_16_16_UNORM = 96, 1472d756322SRob Clark VFMT6_16_16_16_16_SNORM = 97, 1482d756322SRob Clark VFMT6_16_16_16_16_FLOAT = 98, 1492d756322SRob Clark VFMT6_16_16_16_16_UINT = 99, 1502d756322SRob Clark VFMT6_16_16_16_16_SINT = 100, 1512d756322SRob Clark VFMT6_32_32_UNORM = 101, 1522d756322SRob Clark VFMT6_32_32_SNORM = 102, 1532d756322SRob Clark VFMT6_32_32_FLOAT = 103, 1542d756322SRob Clark VFMT6_32_32_UINT = 104, 1552d756322SRob Clark VFMT6_32_32_SINT = 105, 1562d756322SRob Clark VFMT6_32_32_FIXED = 106, 1572d756322SRob Clark VFMT6_32_32_32_UNORM = 112, 1582d756322SRob Clark VFMT6_32_32_32_SNORM = 113, 1592d756322SRob Clark VFMT6_32_32_32_UINT = 114, 1602d756322SRob Clark VFMT6_32_32_32_SINT = 115, 1612d756322SRob Clark VFMT6_32_32_32_FLOAT = 116, 1622d756322SRob Clark VFMT6_32_32_32_FIXED = 117, 1632d756322SRob Clark VFMT6_32_32_32_32_UNORM = 128, 1642d756322SRob Clark VFMT6_32_32_32_32_SNORM = 129, 1652d756322SRob Clark VFMT6_32_32_32_32_FLOAT = 130, 1662d756322SRob Clark VFMT6_32_32_32_32_UINT = 131, 1672d756322SRob Clark VFMT6_32_32_32_32_SINT = 132, 1682d756322SRob Clark VFMT6_32_32_32_32_FIXED = 133, 1692d756322SRob Clark }; 1702d756322SRob Clark 1712d756322SRob Clark enum a6xx_tex_fmt { 1722d756322SRob Clark TFMT6_A8_UNORM = 2, 1732d756322SRob Clark TFMT6_8_UNORM = 3, 1742d756322SRob Clark TFMT6_8_SNORM = 4, 1752d756322SRob Clark TFMT6_8_UINT = 5, 1762d756322SRob Clark TFMT6_8_SINT = 6, 1772d756322SRob Clark TFMT6_4_4_4_4_UNORM = 8, 1782d756322SRob Clark TFMT6_5_5_5_1_UNORM = 10, 1792d756322SRob Clark TFMT6_5_6_5_UNORM = 14, 1802d756322SRob Clark TFMT6_8_8_UNORM = 15, 1812d756322SRob Clark TFMT6_8_8_SNORM = 16, 1822d756322SRob Clark TFMT6_8_8_UINT = 17, 1832d756322SRob Clark TFMT6_8_8_SINT = 18, 1842d756322SRob Clark TFMT6_L8_A8_UNORM = 19, 1852d756322SRob Clark TFMT6_16_UNORM = 21, 1862d756322SRob Clark TFMT6_16_SNORM = 22, 1872d756322SRob Clark TFMT6_16_FLOAT = 23, 1882d756322SRob Clark TFMT6_16_UINT = 24, 1892d756322SRob Clark TFMT6_16_SINT = 25, 1902d756322SRob Clark TFMT6_8_8_8_8_UNORM = 48, 1912d756322SRob Clark TFMT6_8_8_8_UNORM = 49, 1922d756322SRob Clark TFMT6_8_8_8_8_SNORM = 50, 1932d756322SRob Clark TFMT6_8_8_8_8_UINT = 51, 1942d756322SRob Clark TFMT6_8_8_8_8_SINT = 52, 1952d756322SRob Clark TFMT6_9_9_9_E5_FLOAT = 53, 1962d756322SRob Clark TFMT6_10_10_10_2_UNORM = 54, 1972d756322SRob Clark TFMT6_10_10_10_2_UINT = 58, 1982d756322SRob Clark TFMT6_11_11_10_FLOAT = 66, 1992d756322SRob Clark TFMT6_16_16_UNORM = 67, 2002d756322SRob Clark TFMT6_16_16_SNORM = 68, 2012d756322SRob Clark TFMT6_16_16_FLOAT = 69, 2022d756322SRob Clark TFMT6_16_16_UINT = 70, 2032d756322SRob Clark TFMT6_16_16_SINT = 71, 2042d756322SRob Clark TFMT6_32_FLOAT = 74, 2052d756322SRob Clark TFMT6_32_UINT = 75, 2062d756322SRob Clark TFMT6_32_SINT = 76, 2072d756322SRob Clark TFMT6_16_16_16_16_UNORM = 96, 2082d756322SRob Clark TFMT6_16_16_16_16_SNORM = 97, 2092d756322SRob Clark TFMT6_16_16_16_16_FLOAT = 98, 2102d756322SRob Clark TFMT6_16_16_16_16_UINT = 99, 2112d756322SRob Clark TFMT6_16_16_16_16_SINT = 100, 2122d756322SRob Clark TFMT6_32_32_FLOAT = 103, 2132d756322SRob Clark TFMT6_32_32_UINT = 104, 2142d756322SRob Clark TFMT6_32_32_SINT = 105, 2152d756322SRob Clark TFMT6_32_32_32_UINT = 114, 2162d756322SRob Clark TFMT6_32_32_32_SINT = 115, 2172d756322SRob Clark TFMT6_32_32_32_FLOAT = 116, 2182d756322SRob Clark TFMT6_32_32_32_32_FLOAT = 130, 2192d756322SRob Clark TFMT6_32_32_32_32_UINT = 131, 2202d756322SRob Clark TFMT6_32_32_32_32_SINT = 132, 2212d756322SRob Clark TFMT6_X8Z24_UNORM = 160, 2222d756322SRob Clark TFMT6_ETC2_RG11_UNORM = 171, 2232d756322SRob Clark TFMT6_ETC2_RG11_SNORM = 172, 2242d756322SRob Clark TFMT6_ETC2_R11_UNORM = 173, 2252d756322SRob Clark TFMT6_ETC2_R11_SNORM = 174, 2262d756322SRob Clark TFMT6_ETC1 = 175, 2272d756322SRob Clark TFMT6_ETC2_RGB8 = 176, 2282d756322SRob Clark TFMT6_ETC2_RGBA8 = 177, 2292d756322SRob Clark TFMT6_ETC2_RGB8A1 = 178, 2302d756322SRob Clark TFMT6_DXT1 = 179, 2312d756322SRob Clark TFMT6_DXT3 = 180, 2322d756322SRob Clark TFMT6_DXT5 = 181, 2332d756322SRob Clark TFMT6_RGTC1_UNORM = 183, 2342d756322SRob Clark TFMT6_RGTC1_SNORM = 184, 2352d756322SRob Clark TFMT6_RGTC2_UNORM = 187, 2362d756322SRob Clark TFMT6_RGTC2_SNORM = 188, 2372d756322SRob Clark TFMT6_BPTC_UFLOAT = 190, 2382d756322SRob Clark TFMT6_BPTC_FLOAT = 191, 2392d756322SRob Clark TFMT6_BPTC = 192, 2402d756322SRob Clark TFMT6_ASTC_4x4 = 193, 2412d756322SRob Clark TFMT6_ASTC_5x4 = 194, 2422d756322SRob Clark TFMT6_ASTC_5x5 = 195, 2432d756322SRob Clark TFMT6_ASTC_6x5 = 196, 2442d756322SRob Clark TFMT6_ASTC_6x6 = 197, 2452d756322SRob Clark TFMT6_ASTC_8x5 = 198, 2462d756322SRob Clark TFMT6_ASTC_8x6 = 199, 2472d756322SRob Clark TFMT6_ASTC_8x8 = 200, 2482d756322SRob Clark TFMT6_ASTC_10x5 = 201, 2492d756322SRob Clark TFMT6_ASTC_10x6 = 202, 2502d756322SRob Clark TFMT6_ASTC_10x8 = 203, 2512d756322SRob Clark TFMT6_ASTC_10x10 = 204, 2522d756322SRob Clark TFMT6_ASTC_12x10 = 205, 2532d756322SRob Clark TFMT6_ASTC_12x12 = 206, 2542d756322SRob Clark }; 2552d756322SRob Clark 2562d756322SRob Clark enum a6xx_tex_fetchsize { 2572d756322SRob Clark TFETCH6_1_BYTE = 0, 2582d756322SRob Clark TFETCH6_2_BYTE = 1, 2592d756322SRob Clark TFETCH6_4_BYTE = 2, 2602d756322SRob Clark TFETCH6_8_BYTE = 3, 2612d756322SRob Clark TFETCH6_16_BYTE = 4, 2622d756322SRob Clark }; 2632d756322SRob Clark 2642d756322SRob Clark enum a6xx_depth_format { 2652d756322SRob Clark DEPTH6_NONE = 0, 2662d756322SRob Clark DEPTH6_16 = 1, 2672d756322SRob Clark DEPTH6_24_8 = 2, 2682d756322SRob Clark DEPTH6_32 = 4, 2692d756322SRob Clark }; 2702d756322SRob Clark 2712d756322SRob Clark enum a6xx_cp_perfcounter_select { 2722d756322SRob Clark PERF_CP_ALWAYS_COUNT = 0, 2732d756322SRob Clark }; 2742d756322SRob Clark 2752d756322SRob Clark enum a6xx_tex_filter { 2762d756322SRob Clark A6XX_TEX_NEAREST = 0, 2772d756322SRob Clark A6XX_TEX_LINEAR = 1, 2782d756322SRob Clark A6XX_TEX_ANISO = 2, 2792d756322SRob Clark }; 2802d756322SRob Clark 2812d756322SRob Clark enum a6xx_tex_clamp { 2822d756322SRob Clark A6XX_TEX_REPEAT = 0, 2832d756322SRob Clark A6XX_TEX_CLAMP_TO_EDGE = 1, 2842d756322SRob Clark A6XX_TEX_MIRROR_REPEAT = 2, 2852d756322SRob Clark A6XX_TEX_CLAMP_TO_BORDER = 3, 2862d756322SRob Clark A6XX_TEX_MIRROR_CLAMP = 4, 2872d756322SRob Clark }; 2882d756322SRob Clark 2892d756322SRob Clark enum a6xx_tex_aniso { 2902d756322SRob Clark A6XX_TEX_ANISO_1 = 0, 2912d756322SRob Clark A6XX_TEX_ANISO_2 = 1, 2922d756322SRob Clark A6XX_TEX_ANISO_4 = 2, 2932d756322SRob Clark A6XX_TEX_ANISO_8 = 3, 2942d756322SRob Clark A6XX_TEX_ANISO_16 = 4, 2952d756322SRob Clark }; 2962d756322SRob Clark 2972d756322SRob Clark enum a6xx_tex_swiz { 2982d756322SRob Clark A6XX_TEX_X = 0, 2992d756322SRob Clark A6XX_TEX_Y = 1, 3002d756322SRob Clark A6XX_TEX_Z = 2, 3012d756322SRob Clark A6XX_TEX_W = 3, 3022d756322SRob Clark A6XX_TEX_ZERO = 4, 3032d756322SRob Clark A6XX_TEX_ONE = 5, 3042d756322SRob Clark }; 3052d756322SRob Clark 3062d756322SRob Clark enum a6xx_tex_type { 3072d756322SRob Clark A6XX_TEX_1D = 0, 3082d756322SRob Clark A6XX_TEX_2D = 1, 3092d756322SRob Clark A6XX_TEX_CUBE = 2, 3102d756322SRob Clark A6XX_TEX_3D = 3, 3112d756322SRob Clark }; 3122d756322SRob Clark 3132d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001 3142d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR 0x00000002 3152d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW 0x00000040 3162d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080 3172d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_SW 0x00000100 3182d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200 3192d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400 3202d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800 3212d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000 3222d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_IB2 0x00002000 3232d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_IB1 0x00004000 3242d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_RB 0x00008000 3252d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000 3262d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000 3272d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000 3282d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000 3292d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT 0x00800000 3302d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000 3312d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000 3322d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000 3332d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000 3342d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000 3352d756322SRob Clark #define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000 3362d756322SRob Clark #define A6XX_CP_INT_CP_OPCODE_ERROR 0x00000001 3372d756322SRob Clark #define A6XX_CP_INT_CP_UCODE_ERROR 0x00000002 3382d756322SRob Clark #define A6XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004 3392d756322SRob Clark #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010 3402d756322SRob Clark #define A6XX_CP_INT_CP_AHB_ERROR 0x00000020 3412d756322SRob Clark #define A6XX_CP_INT_CP_VSD_PARITY_ERROR 0x00000040 3422d756322SRob Clark #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR 0x00000080 3432d756322SRob Clark #define REG_A6XX_CP_RB_BASE 0x00000800 3442d756322SRob Clark 3452d756322SRob Clark #define REG_A6XX_CP_RB_BASE_HI 0x00000801 3462d756322SRob Clark 3472d756322SRob Clark #define REG_A6XX_CP_RB_CNTL 0x00000802 3482d756322SRob Clark 3492d756322SRob Clark #define REG_A6XX_CP_RB_RPTR_ADDR_LO 0x00000804 3502d756322SRob Clark 3512d756322SRob Clark #define REG_A6XX_CP_RB_RPTR_ADDR_HI 0x00000805 3522d756322SRob Clark 3532d756322SRob Clark #define REG_A6XX_CP_RB_RPTR 0x00000806 3542d756322SRob Clark 3552d756322SRob Clark #define REG_A6XX_CP_RB_WPTR 0x00000807 3562d756322SRob Clark 3572d756322SRob Clark #define REG_A6XX_CP_SQE_CNTL 0x00000808 3582d756322SRob Clark 3592d756322SRob Clark #define REG_A6XX_CP_HW_FAULT 0x00000821 3602d756322SRob Clark 3612d756322SRob Clark #define REG_A6XX_CP_INTERRUPT_STATUS 0x00000823 3622d756322SRob Clark 3632d756322SRob Clark #define REG_A6XX_CP_PROTECT_STATUS 0x00000824 3642d756322SRob Clark 3652d756322SRob Clark #define REG_A6XX_CP_SQE_INSTR_BASE_LO 0x00000830 3662d756322SRob Clark 3672d756322SRob Clark #define REG_A6XX_CP_SQE_INSTR_BASE_HI 0x00000831 3682d756322SRob Clark 3692d756322SRob Clark #define REG_A6XX_CP_MISC_CNTL 0x00000840 3702d756322SRob Clark 3712d756322SRob Clark #define REG_A6XX_CP_ROQ_THRESHOLDS_1 0x000008c1 3722d756322SRob Clark 3732d756322SRob Clark #define REG_A6XX_CP_ROQ_THRESHOLDS_2 0x000008c2 3742d756322SRob Clark 3752d756322SRob Clark #define REG_A6XX_CP_MEM_POOL_SIZE 0x000008c3 3762d756322SRob Clark 3772d756322SRob Clark #define REG_A6XX_CP_CHICKEN_DBG 0x00000841 3782d756322SRob Clark 3792d756322SRob Clark #define REG_A6XX_CP_ADDR_MODE_CNTL 0x00000842 3802d756322SRob Clark 3812d756322SRob Clark #define REG_A6XX_CP_DBG_ECO_CNTL 0x00000843 3822d756322SRob Clark 3832d756322SRob Clark #define REG_A6XX_CP_PROTECT_CNTL 0x0000084f 3842d756322SRob Clark 3852d756322SRob Clark static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; } 3862d756322SRob Clark 3872d756322SRob Clark static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; } 3882d756322SRob Clark 3892d756322SRob Clark static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; } 3902d756322SRob Clark 3912d756322SRob Clark static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; } 3922d756322SRob Clark #define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0003ffff 3932d756322SRob Clark #define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0 3942d756322SRob Clark static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) 3952d756322SRob Clark { 3962d756322SRob Clark return ((val) << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK; 3972d756322SRob Clark } 3982d756322SRob Clark #define A6XX_CP_PROTECT_REG_MASK_LEN__MASK 0x7ffc0000 3992d756322SRob Clark #define A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT 18 4002d756322SRob Clark static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) 4012d756322SRob Clark { 4022d756322SRob Clark return ((val) << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK; 4032d756322SRob Clark } 4042d756322SRob Clark #define A6XX_CP_PROTECT_REG_READ 0x80000000 4052d756322SRob Clark 4062d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_CNTL 0x000008a0 4072d756322SRob Clark 4082d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x000008a1 4092d756322SRob Clark 4102d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x000008a2 4112d756322SRob Clark 4122d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO 0x000008a3 4132d756322SRob Clark 4142d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI 0x000008a4 4152d756322SRob Clark 4162d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO 0x000008a5 4172d756322SRob Clark 4182d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI 0x000008a6 4192d756322SRob Clark 4202d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO 0x000008a7 4212d756322SRob Clark 4222d756322SRob Clark #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI 0x000008a8 4232d756322SRob Clark 4242d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_0 0x000008d0 4252d756322SRob Clark 4262d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_1 0x000008d1 4272d756322SRob Clark 4282d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_2 0x000008d2 4292d756322SRob Clark 4302d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_3 0x000008d3 4312d756322SRob Clark 4322d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_4 0x000008d4 4332d756322SRob Clark 4342d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_5 0x000008d5 4352d756322SRob Clark 4362d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_6 0x000008d6 4372d756322SRob Clark 4382d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_7 0x000008d7 4392d756322SRob Clark 4402d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_8 0x000008d8 4412d756322SRob Clark 4422d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_9 0x000008d9 4432d756322SRob Clark 4442d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_10 0x000008da 4452d756322SRob Clark 4462d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_11 0x000008db 4472d756322SRob Clark 4482d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_12 0x000008dc 4492d756322SRob Clark 4502d756322SRob Clark #define REG_A6XX_CP_PERFCTR_CP_SEL_13 0x000008dd 4512d756322SRob Clark 4522d756322SRob Clark #define REG_A6XX_CP_CRASH_SCRIPT_BASE_LO 0x00000900 4532d756322SRob Clark 4542d756322SRob Clark #define REG_A6XX_CP_CRASH_SCRIPT_BASE_HI 0x00000901 4552d756322SRob Clark 4562d756322SRob Clark #define REG_A6XX_CP_CRASH_DUMP_CNTL 0x00000902 4572d756322SRob Clark 4582d756322SRob Clark #define REG_A6XX_CP_CRASH_DUMP_STATUS 0x00000903 4592d756322SRob Clark 4602d756322SRob Clark #define REG_A6XX_CP_SQE_STAT_ADDR 0x00000908 4612d756322SRob Clark 4622d756322SRob Clark #define REG_A6XX_CP_SQE_STAT_DATA 0x00000909 4632d756322SRob Clark 4642d756322SRob Clark #define REG_A6XX_CP_DRAW_STATE_ADDR 0x0000090a 4652d756322SRob Clark 4662d756322SRob Clark #define REG_A6XX_CP_DRAW_STATE_DATA 0x0000090b 4672d756322SRob Clark 4682d756322SRob Clark #define REG_A6XX_CP_ROQ_DBG_ADDR 0x0000090c 4692d756322SRob Clark 4702d756322SRob Clark #define REG_A6XX_CP_ROQ_DBG_DATA 0x0000090d 4712d756322SRob Clark 4722d756322SRob Clark #define REG_A6XX_CP_MEM_POOL_DBG_ADDR 0x0000090e 4732d756322SRob Clark 4742d756322SRob Clark #define REG_A6XX_CP_MEM_POOL_DBG_DATA 0x0000090f 4752d756322SRob Clark 4762d756322SRob Clark #define REG_A6XX_CP_SQE_UCODE_DBG_ADDR 0x00000910 4772d756322SRob Clark 4782d756322SRob Clark #define REG_A6XX_CP_SQE_UCODE_DBG_DATA 0x00000911 4792d756322SRob Clark 4802d756322SRob Clark #define REG_A6XX_CP_IB1_BASE 0x00000928 4812d756322SRob Clark 4822d756322SRob Clark #define REG_A6XX_CP_IB1_BASE_HI 0x00000929 4832d756322SRob Clark 4842d756322SRob Clark #define REG_A6XX_CP_IB1_REM_SIZE 0x0000092a 4852d756322SRob Clark 4862d756322SRob Clark #define REG_A6XX_CP_IB2_BASE 0x0000092b 4872d756322SRob Clark 4882d756322SRob Clark #define REG_A6XX_CP_IB2_BASE_HI 0x0000092c 4892d756322SRob Clark 4902d756322SRob Clark #define REG_A6XX_CP_IB2_REM_SIZE 0x0000092d 4912d756322SRob Clark 4922d756322SRob Clark #define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO 0x00000980 4932d756322SRob Clark 4942d756322SRob Clark #define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI 0x00000981 4952d756322SRob Clark 4962d756322SRob Clark #define REG_A6XX_CP_AHB_CNTL 0x0000098d 4972d756322SRob Clark 4982d756322SRob Clark #define REG_A6XX_CP_APERTURE_CNTL_HOST 0x00000a00 4992d756322SRob Clark 5002d756322SRob Clark #define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03 5012d756322SRob Clark 5022d756322SRob Clark #define REG_A6XX_VSC_ADDR_MODE_CNTL 0x00000c01 5032d756322SRob Clark 5042d756322SRob Clark #define REG_A6XX_RBBM_INT_0_STATUS 0x00000201 5052d756322SRob Clark 5062d756322SRob Clark #define REG_A6XX_RBBM_STATUS 0x00000210 5072d756322SRob Clark #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x00800000 5082d756322SRob Clark #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x00400000 5092d756322SRob Clark #define A6XX_RBBM_STATUS_HLSQ_BUSY 0x00200000 5102d756322SRob Clark #define A6XX_RBBM_STATUS_VSC_BUSY 0x00100000 5112d756322SRob Clark #define A6XX_RBBM_STATUS_TPL1_BUSY 0x00080000 5122d756322SRob Clark #define A6XX_RBBM_STATUS_SP_BUSY 0x00040000 5132d756322SRob Clark #define A6XX_RBBM_STATUS_UCHE_BUSY 0x00020000 5142d756322SRob Clark #define A6XX_RBBM_STATUS_VPC_BUSY 0x00010000 5152d756322SRob Clark #define A6XX_RBBM_STATUS_VFD_BUSY 0x00008000 5162d756322SRob Clark #define A6XX_RBBM_STATUS_TESS_BUSY 0x00004000 5172d756322SRob Clark #define A6XX_RBBM_STATUS_PC_VSD_BUSY 0x00002000 5182d756322SRob Clark #define A6XX_RBBM_STATUS_PC_DCALL_BUSY 0x00001000 5192d756322SRob Clark #define A6XX_RBBM_STATUS_COM_DCOM_BUSY 0x00000800 5202d756322SRob Clark #define A6XX_RBBM_STATUS_LRZ_BUSY 0x00000400 5212d756322SRob Clark #define A6XX_RBBM_STATUS_A2D_BUSY 0x00000200 5222d756322SRob Clark #define A6XX_RBBM_STATUS_CCU_BUSY 0x00000100 5232d756322SRob Clark #define A6XX_RBBM_STATUS_RB_BUSY 0x00000080 5242d756322SRob Clark #define A6XX_RBBM_STATUS_RAS_BUSY 0x00000040 5252d756322SRob Clark #define A6XX_RBBM_STATUS_TSE_BUSY 0x00000020 5262d756322SRob Clark #define A6XX_RBBM_STATUS_VBIF_BUSY 0x00000010 5272d756322SRob Clark #define A6XX_RBBM_STATUS_GFX_DBGC_BUSY 0x00000008 5282d756322SRob Clark #define A6XX_RBBM_STATUS_CP_BUSY 0x00000004 5292d756322SRob Clark #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER 0x00000002 5302d756322SRob Clark #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER 0x00000001 5312d756322SRob Clark 5322d756322SRob Clark #define REG_A6XX_RBBM_STATUS3 0x00000213 5332d756322SRob Clark 5342d756322SRob Clark #define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215 5352d756322SRob Clark 5362d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_0_LO 0x00000400 5372d756322SRob Clark 5382d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_0_HI 0x00000401 5392d756322SRob Clark 5402d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_1_LO 0x00000402 5412d756322SRob Clark 5422d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_1_HI 0x00000403 5432d756322SRob Clark 5442d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_2_LO 0x00000404 5452d756322SRob Clark 5462d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_2_HI 0x00000405 5472d756322SRob Clark 5482d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_3_LO 0x00000406 5492d756322SRob Clark 5502d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_3_HI 0x00000407 5512d756322SRob Clark 5522d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_4_LO 0x00000408 5532d756322SRob Clark 5542d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_4_HI 0x00000409 5552d756322SRob Clark 5562d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_5_LO 0x0000040a 5572d756322SRob Clark 5582d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_5_HI 0x0000040b 5592d756322SRob Clark 5602d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_6_LO 0x0000040c 5612d756322SRob Clark 5622d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_6_HI 0x0000040d 5632d756322SRob Clark 5642d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_7_LO 0x0000040e 5652d756322SRob Clark 5662d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_7_HI 0x0000040f 5672d756322SRob Clark 5682d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_8_LO 0x00000410 5692d756322SRob Clark 5702d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_8_HI 0x00000411 5712d756322SRob Clark 5722d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_9_LO 0x00000412 5732d756322SRob Clark 5742d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_9_HI 0x00000413 5752d756322SRob Clark 5762d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_10_LO 0x00000414 5772d756322SRob Clark 5782d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_10_HI 0x00000415 5792d756322SRob Clark 5802d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_11_LO 0x00000416 5812d756322SRob Clark 5822d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_11_HI 0x00000417 5832d756322SRob Clark 5842d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_12_LO 0x00000418 5852d756322SRob Clark 5862d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_12_HI 0x00000419 5872d756322SRob Clark 5882d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_13_LO 0x0000041a 5892d756322SRob Clark 5902d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CP_13_HI 0x0000041b 5912d756322SRob Clark 5922d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_0_LO 0x0000041c 5932d756322SRob Clark 5942d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_0_HI 0x0000041d 5952d756322SRob Clark 5962d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_1_LO 0x0000041e 5972d756322SRob Clark 5982d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_1_HI 0x0000041f 5992d756322SRob Clark 6002d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_2_LO 0x00000420 6012d756322SRob Clark 6022d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_2_HI 0x00000421 6032d756322SRob Clark 6042d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_3_LO 0x00000422 6052d756322SRob Clark 6062d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_3_HI 0x00000423 6072d756322SRob Clark 6082d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_0_LO 0x00000424 6092d756322SRob Clark 6102d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_0_HI 0x00000425 6112d756322SRob Clark 6122d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_1_LO 0x00000426 6132d756322SRob Clark 6142d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_1_HI 0x00000427 6152d756322SRob Clark 6162d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_2_LO 0x00000428 6172d756322SRob Clark 6182d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_2_HI 0x00000429 6192d756322SRob Clark 6202d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_3_LO 0x0000042a 6212d756322SRob Clark 6222d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_3_HI 0x0000042b 6232d756322SRob Clark 6242d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_4_LO 0x0000042c 6252d756322SRob Clark 6262d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_4_HI 0x0000042d 6272d756322SRob Clark 6282d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_5_LO 0x0000042e 6292d756322SRob Clark 6302d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_5_HI 0x0000042f 6312d756322SRob Clark 6322d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_6_LO 0x00000430 6332d756322SRob Clark 6342d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_6_HI 0x00000431 6352d756322SRob Clark 6362d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_7_LO 0x00000432 6372d756322SRob Clark 6382d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_PC_7_HI 0x00000433 6392d756322SRob Clark 6402d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_0_LO 0x00000434 6412d756322SRob Clark 6422d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_0_HI 0x00000435 6432d756322SRob Clark 6442d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_1_LO 0x00000436 6452d756322SRob Clark 6462d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_1_HI 0x00000437 6472d756322SRob Clark 6482d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_2_LO 0x00000438 6492d756322SRob Clark 6502d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_2_HI 0x00000439 6512d756322SRob Clark 6522d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_3_LO 0x0000043a 6532d756322SRob Clark 6542d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_3_HI 0x0000043b 6552d756322SRob Clark 6562d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_4_LO 0x0000043c 6572d756322SRob Clark 6582d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_4_HI 0x0000043d 6592d756322SRob Clark 6602d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_5_LO 0x0000043e 6612d756322SRob Clark 6622d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_5_HI 0x0000043f 6632d756322SRob Clark 6642d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_6_LO 0x00000440 6652d756322SRob Clark 6662d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_6_HI 0x00000441 6672d756322SRob Clark 6682d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_7_LO 0x00000442 6692d756322SRob Clark 6702d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VFD_7_HI 0x00000443 6712d756322SRob Clark 6722d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_0_LO 0x00000444 6732d756322SRob Clark 6742d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_0_HI 0x00000445 6752d756322SRob Clark 6762d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_1_LO 0x00000446 6772d756322SRob Clark 6782d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_1_HI 0x00000447 6792d756322SRob Clark 6802d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_2_LO 0x00000448 6812d756322SRob Clark 6822d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_2_HI 0x00000449 6832d756322SRob Clark 6842d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_3_LO 0x0000044a 6852d756322SRob Clark 6862d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_3_HI 0x0000044b 6872d756322SRob Clark 6882d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_4_LO 0x0000044c 6892d756322SRob Clark 6902d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_4_HI 0x0000044d 6912d756322SRob Clark 6922d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_5_LO 0x0000044e 6932d756322SRob Clark 6942d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_HLSQ_5_HI 0x0000044f 6952d756322SRob Clark 6962d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_0_LO 0x00000450 6972d756322SRob Clark 6982d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_0_HI 0x00000451 6992d756322SRob Clark 7002d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_1_LO 0x00000452 7012d756322SRob Clark 7022d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_1_HI 0x00000453 7032d756322SRob Clark 7042d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_2_LO 0x00000454 7052d756322SRob Clark 7062d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_2_HI 0x00000455 7072d756322SRob Clark 7082d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_3_LO 0x00000456 7092d756322SRob Clark 7102d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_3_HI 0x00000457 7112d756322SRob Clark 7122d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_4_LO 0x00000458 7132d756322SRob Clark 7142d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_4_HI 0x00000459 7152d756322SRob Clark 7162d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_5_LO 0x0000045a 7172d756322SRob Clark 7182d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VPC_5_HI 0x0000045b 7192d756322SRob Clark 7202d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_0_LO 0x0000045c 7212d756322SRob Clark 7222d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_0_HI 0x0000045d 7232d756322SRob Clark 7242d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_1_LO 0x0000045e 7252d756322SRob Clark 7262d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_1_HI 0x0000045f 7272d756322SRob Clark 7282d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_2_LO 0x00000460 7292d756322SRob Clark 7302d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_2_HI 0x00000461 7312d756322SRob Clark 7322d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_3_LO 0x00000462 7332d756322SRob Clark 7342d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_3_HI 0x00000463 7352d756322SRob Clark 7362d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_4_LO 0x00000464 7372d756322SRob Clark 7382d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_4_HI 0x00000465 7392d756322SRob Clark 7402d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_0_LO 0x00000466 7412d756322SRob Clark 7422d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_0_HI 0x00000467 7432d756322SRob Clark 7442d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_1_LO 0x00000468 7452d756322SRob Clark 7462d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_1_HI 0x00000469 7472d756322SRob Clark 7482d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_2_LO 0x0000046a 7492d756322SRob Clark 7502d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CCU_4_HI 0x00000465 7512d756322SRob Clark 7522d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_0_LO 0x00000466 7532d756322SRob Clark 7542d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_0_HI 0x00000467 7552d756322SRob Clark 7562d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_1_LO 0x00000468 7572d756322SRob Clark 7582d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_1_HI 0x00000469 7592d756322SRob Clark 7602d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_2_LO 0x0000046a 7612d756322SRob Clark 7622d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_2_HI 0x0000046b 7632d756322SRob Clark 7642d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_3_LO 0x0000046c 7652d756322SRob Clark 7662d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TSE_3_HI 0x0000046d 7672d756322SRob Clark 7682d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RAS_0_LO 0x0000046e 7692d756322SRob Clark 7702d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RAS_0_HI 0x0000046f 7712d756322SRob Clark 7722d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RAS_1_LO 0x00000470 7732d756322SRob Clark 7742d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RAS_1_HI 0x00000471 7752d756322SRob Clark 7762d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RAS_2_LO 0x00000472 7772d756322SRob Clark 7782d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RAS_2_HI 0x00000473 7792d756322SRob Clark 7802d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RAS_3_LO 0x00000474 7812d756322SRob Clark 7822d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RAS_3_HI 0x00000475 7832d756322SRob Clark 7842d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_0_LO 0x00000476 7852d756322SRob Clark 7862d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_0_HI 0x00000477 7872d756322SRob Clark 7882d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_1_LO 0x00000478 7892d756322SRob Clark 7902d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_1_HI 0x00000479 7912d756322SRob Clark 7922d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_2_LO 0x0000047a 7932d756322SRob Clark 7942d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_2_HI 0x0000047b 7952d756322SRob Clark 7962d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_3_LO 0x0000047c 7972d756322SRob Clark 7982d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_3_HI 0x0000047d 7992d756322SRob Clark 8002d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_4_LO 0x0000047e 8012d756322SRob Clark 8022d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_4_HI 0x0000047f 8032d756322SRob Clark 8042d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_5_LO 0x00000480 8052d756322SRob Clark 8062d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_5_HI 0x00000481 8072d756322SRob Clark 8082d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_6_LO 0x00000482 8092d756322SRob Clark 8102d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_6_HI 0x00000483 8112d756322SRob Clark 8122d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_7_LO 0x00000484 8132d756322SRob Clark 8142d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_7_HI 0x00000485 8152d756322SRob Clark 8162d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_8_LO 0x00000486 8172d756322SRob Clark 8182d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_8_HI 0x00000487 8192d756322SRob Clark 8202d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_9_LO 0x00000488 8212d756322SRob Clark 8222d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_9_HI 0x00000489 8232d756322SRob Clark 8242d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_10_LO 0x0000048a 8252d756322SRob Clark 8262d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_10_HI 0x0000048b 8272d756322SRob Clark 8282d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_11_LO 0x0000048c 8292d756322SRob Clark 8302d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_UCHE_11_HI 0x0000048d 8312d756322SRob Clark 8322d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_0_LO 0x0000048e 8332d756322SRob Clark 8342d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_0_HI 0x0000048f 8352d756322SRob Clark 8362d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_1_LO 0x00000490 8372d756322SRob Clark 8382d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_1_HI 0x00000491 8392d756322SRob Clark 8402d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_2_LO 0x00000492 8412d756322SRob Clark 8422d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_2_HI 0x00000493 8432d756322SRob Clark 8442d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_3_LO 0x00000494 8452d756322SRob Clark 8462d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_3_HI 0x00000495 8472d756322SRob Clark 8482d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_4_LO 0x00000496 8492d756322SRob Clark 8502d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_4_HI 0x00000497 8512d756322SRob Clark 8522d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_5_LO 0x00000498 8532d756322SRob Clark 8542d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_5_HI 0x00000499 8552d756322SRob Clark 8562d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_6_LO 0x0000049a 8572d756322SRob Clark 8582d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_6_HI 0x0000049b 8592d756322SRob Clark 8602d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_7_LO 0x0000049c 8612d756322SRob Clark 8622d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_7_HI 0x0000049d 8632d756322SRob Clark 8642d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_8_LO 0x0000049e 8652d756322SRob Clark 8662d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_8_HI 0x0000049f 8672d756322SRob Clark 8682d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_9_LO 0x000004a0 8692d756322SRob Clark 8702d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_9_HI 0x000004a1 8712d756322SRob Clark 8722d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_10_LO 0x000004a2 8732d756322SRob Clark 8742d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_10_HI 0x000004a3 8752d756322SRob Clark 8762d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_11_LO 0x000004a4 8772d756322SRob Clark 8782d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_TP_11_HI 0x000004a5 8792d756322SRob Clark 8802d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_0_LO 0x000004a6 8812d756322SRob Clark 8822d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_0_HI 0x000004a7 8832d756322SRob Clark 8842d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_1_LO 0x000004a8 8852d756322SRob Clark 8862d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_1_HI 0x000004a9 8872d756322SRob Clark 8882d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_2_LO 0x000004aa 8892d756322SRob Clark 8902d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_2_HI 0x000004ab 8912d756322SRob Clark 8922d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_3_LO 0x000004ac 8932d756322SRob Clark 8942d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_3_HI 0x000004ad 8952d756322SRob Clark 8962d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_4_LO 0x000004ae 8972d756322SRob Clark 8982d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_4_HI 0x000004af 8992d756322SRob Clark 9002d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_5_LO 0x000004b0 9012d756322SRob Clark 9022d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_5_HI 0x000004b1 9032d756322SRob Clark 9042d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_6_LO 0x000004b2 9052d756322SRob Clark 9062d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_6_HI 0x000004b3 9072d756322SRob Clark 9082d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_7_LO 0x000004b4 9092d756322SRob Clark 9102d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_7_HI 0x000004b5 9112d756322SRob Clark 9122d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_8_LO 0x000004b6 9132d756322SRob Clark 9142d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_8_HI 0x000004b7 9152d756322SRob Clark 9162d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_9_LO 0x000004b8 9172d756322SRob Clark 9182d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_9_HI 0x000004b9 9192d756322SRob Clark 9202d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_10_LO 0x000004ba 9212d756322SRob Clark 9222d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_10_HI 0x000004bb 9232d756322SRob Clark 9242d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_11_LO 0x000004bc 9252d756322SRob Clark 9262d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_11_HI 0x000004bd 9272d756322SRob Clark 9282d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_12_LO 0x000004be 9292d756322SRob Clark 9302d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_12_HI 0x000004bf 9312d756322SRob Clark 9322d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_13_LO 0x000004c0 9332d756322SRob Clark 9342d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_13_HI 0x000004c1 9352d756322SRob Clark 9362d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_14_LO 0x000004c2 9372d756322SRob Clark 9382d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_14_HI 0x000004c3 9392d756322SRob Clark 9402d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_15_LO 0x000004c4 9412d756322SRob Clark 9422d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_15_HI 0x000004c5 9432d756322SRob Clark 9442d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_16_LO 0x000004c6 9452d756322SRob Clark 9462d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_16_HI 0x000004c7 9472d756322SRob Clark 9482d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_17_LO 0x000004c8 9492d756322SRob Clark 9502d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_17_HI 0x000004c9 9512d756322SRob Clark 9522d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_18_LO 0x000004ca 9532d756322SRob Clark 9542d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_18_HI 0x000004cb 9552d756322SRob Clark 9562d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_19_LO 0x000004cc 9572d756322SRob Clark 9582d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_19_HI 0x000004cd 9592d756322SRob Clark 9602d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_20_LO 0x000004ce 9612d756322SRob Clark 9622d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_20_HI 0x000004cf 9632d756322SRob Clark 9642d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_21_LO 0x000004d0 9652d756322SRob Clark 9662d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_21_HI 0x000004d1 9672d756322SRob Clark 9682d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_22_LO 0x000004d2 9692d756322SRob Clark 9702d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_22_HI 0x000004d3 9712d756322SRob Clark 9722d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_23_LO 0x000004d4 9732d756322SRob Clark 9742d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_SP_23_HI 0x000004d5 9752d756322SRob Clark 9762d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_0_LO 0x000004d6 9772d756322SRob Clark 9782d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_0_HI 0x000004d7 9792d756322SRob Clark 9802d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_1_LO 0x000004d8 9812d756322SRob Clark 9822d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_1_HI 0x000004d9 9832d756322SRob Clark 9842d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_2_LO 0x000004da 9852d756322SRob Clark 9862d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_2_HI 0x000004db 9872d756322SRob Clark 9882d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_3_LO 0x000004dc 9892d756322SRob Clark 9902d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_3_HI 0x000004dd 9912d756322SRob Clark 9922d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_4_LO 0x000004de 9932d756322SRob Clark 9942d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_4_HI 0x000004df 9952d756322SRob Clark 9962d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_5_LO 0x000004e0 9972d756322SRob Clark 9982d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_5_HI 0x000004e1 9992d756322SRob Clark 10002d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_6_LO 0x000004e2 10012d756322SRob Clark 10022d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_6_HI 0x000004e3 10032d756322SRob Clark 10042d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_7_LO 0x000004e4 10052d756322SRob Clark 10062d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RB_7_HI 0x000004e5 10072d756322SRob Clark 10082d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VSC_0_LO 0x000004e6 10092d756322SRob Clark 10102d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VSC_0_HI 0x000004e7 10112d756322SRob Clark 10122d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VSC_1_LO 0x000004e8 10132d756322SRob Clark 10142d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_VSC_1_HI 0x000004e9 10152d756322SRob Clark 10162d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LRZ_0_LO 0x000004ea 10172d756322SRob Clark 10182d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LRZ_0_HI 0x000004eb 10192d756322SRob Clark 10202d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LRZ_1_LO 0x000004ec 10212d756322SRob Clark 10222d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LRZ_1_HI 0x000004ed 10232d756322SRob Clark 10242d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LRZ_2_LO 0x000004ee 10252d756322SRob Clark 10262d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LRZ_2_HI 0x000004ef 10272d756322SRob Clark 10282d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LRZ_3_LO 0x000004f0 10292d756322SRob Clark 10302d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LRZ_3_HI 0x000004f1 10312d756322SRob Clark 10322d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CMP_0_LO 0x000004f2 10332d756322SRob Clark 10342d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CMP_0_HI 0x000004f3 10352d756322SRob Clark 10362d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CMP_1_LO 0x000004f4 10372d756322SRob Clark 10382d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CMP_1_HI 0x000004f5 10392d756322SRob Clark 10402d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CMP_2_LO 0x000004f6 10412d756322SRob Clark 10422d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CMP_2_HI 0x000004f7 10432d756322SRob Clark 10442d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CMP_3_LO 0x000004f8 10452d756322SRob Clark 10462d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CMP_3_HI 0x000004f9 10472d756322SRob Clark 10482d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500 10492d756322SRob Clark 10502d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 0x00000501 10512d756322SRob Clark 10522d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 0x00000502 10532d756322SRob Clark 10542d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 0x00000503 10552d756322SRob Clark 10562d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 0x00000504 10572d756322SRob Clark 10582d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000505 10592d756322SRob Clark 10602d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506 10612d756322SRob Clark 10622d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000507 10632d756322SRob Clark 10642d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000508 10652d756322SRob Clark 10662d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000509 10672d756322SRob Clark 10682d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000050a 10692d756322SRob Clark 10702d756322SRob Clark #define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b 10712d756322SRob Clark 10722d756322SRob Clark #define REG_A6XX_RBBM_ISDB_CNT 0x00000533 10732d756322SRob Clark 10742d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TRUST_CNTL 0x0000f400 10752d756322SRob Clark 10762d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800 10772d756322SRob Clark 10782d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801 10792d756322SRob Clark 10802d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802 10812d756322SRob Clark 10822d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_CNTL 0x0000f803 10832d756322SRob Clark 10842d756322SRob Clark #define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810 10852d756322SRob Clark 10862d756322SRob Clark #define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL 0x00000010 10872d756322SRob Clark 10882d756322SRob Clark #define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000001f 10892d756322SRob Clark 10902d756322SRob Clark #define REG_A6XX_RBBM_INT_CLEAR_CMD 0x00000037 10912d756322SRob Clark 10922d756322SRob Clark #define REG_A6XX_RBBM_INT_0_MASK 0x00000038 10932d756322SRob Clark 10942d756322SRob Clark #define REG_A6XX_RBBM_SP_HYST_CNT 0x00000042 10952d756322SRob Clark 10962d756322SRob Clark #define REG_A6XX_RBBM_SW_RESET_CMD 0x00000043 10972d756322SRob Clark 10982d756322SRob Clark #define REG_A6XX_RBBM_RAC_THRESHOLD_CNT 0x00000044 10992d756322SRob Clark 11002d756322SRob Clark #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 11012d756322SRob Clark 11022d756322SRob Clark #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046 11032d756322SRob Clark 11042d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae 11052d756322SRob Clark 11062d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0 11072d756322SRob Clark 11082d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_SP1 0x000000b1 11092d756322SRob Clark 11102d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_SP2 0x000000b2 11112d756322SRob Clark 11122d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_SP3 0x000000b3 11132d756322SRob Clark 11142d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_SP0 0x000000b4 11152d756322SRob Clark 11162d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_SP1 0x000000b5 11172d756322SRob Clark 11182d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_SP2 0x000000b6 11192d756322SRob Clark 11202d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_SP3 0x000000b7 11212d756322SRob Clark 11222d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_SP0 0x000000b8 11232d756322SRob Clark 11242d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_SP1 0x000000b9 11252d756322SRob Clark 11262d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_SP2 0x000000ba 11272d756322SRob Clark 11282d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_SP3 0x000000bb 11292d756322SRob Clark 11302d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_SP0 0x000000bc 11312d756322SRob Clark 11322d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_SP1 0x000000bd 11332d756322SRob Clark 11342d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_SP2 0x000000be 11352d756322SRob Clark 11362d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_SP3 0x000000bf 11372d756322SRob Clark 11382d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TP0 0x000000c0 11392d756322SRob Clark 11402d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TP1 0x000000c1 11412d756322SRob Clark 11422d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TP2 0x000000c2 11432d756322SRob Clark 11442d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TP3 0x000000c3 11452d756322SRob Clark 11462d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_TP0 0x000000c4 11472d756322SRob Clark 11482d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_TP1 0x000000c5 11492d756322SRob Clark 11502d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_TP2 0x000000c6 11512d756322SRob Clark 11522d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_TP3 0x000000c7 11532d756322SRob Clark 11542d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_TP0 0x000000c8 11552d756322SRob Clark 11562d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_TP1 0x000000c9 11572d756322SRob Clark 11582d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_TP2 0x000000ca 11592d756322SRob Clark 11602d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_TP3 0x000000cb 11612d756322SRob Clark 11622d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_TP0 0x000000cc 11632d756322SRob Clark 11642d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_TP1 0x000000cd 11652d756322SRob Clark 11662d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_TP2 0x000000ce 11672d756322SRob Clark 11682d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_TP3 0x000000cf 11692d756322SRob Clark 11702d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TP0 0x000000d0 11712d756322SRob Clark 11722d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TP1 0x000000d1 11732d756322SRob Clark 11742d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TP2 0x000000d2 11752d756322SRob Clark 11762d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TP3 0x000000d3 11772d756322SRob Clark 11782d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY2_TP0 0x000000d4 11792d756322SRob Clark 11802d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY2_TP1 0x000000d5 11812d756322SRob Clark 11822d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY2_TP2 0x000000d6 11832d756322SRob Clark 11842d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY2_TP3 0x000000d7 11852d756322SRob Clark 11862d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY3_TP0 0x000000d8 11872d756322SRob Clark 11882d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY3_TP1 0x000000d9 11892d756322SRob Clark 11902d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY3_TP2 0x000000da 11912d756322SRob Clark 11922d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY3_TP3 0x000000db 11932d756322SRob Clark 11942d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY4_TP0 0x000000dc 11952d756322SRob Clark 11962d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY4_TP1 0x000000dd 11972d756322SRob Clark 11982d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY4_TP2 0x000000de 11992d756322SRob Clark 12002d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY4_TP3 0x000000df 12012d756322SRob Clark 12022d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TP0 0x000000e0 12032d756322SRob Clark 12042d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TP1 0x000000e1 12052d756322SRob Clark 12062d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TP2 0x000000e2 12072d756322SRob Clark 12082d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TP3 0x000000e3 12092d756322SRob Clark 12102d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST2_TP0 0x000000e4 12112d756322SRob Clark 12122d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST2_TP1 0x000000e5 12132d756322SRob Clark 12142d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST2_TP2 0x000000e6 12152d756322SRob Clark 12162d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST2_TP3 0x000000e7 12172d756322SRob Clark 12182d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST3_TP0 0x000000e8 12192d756322SRob Clark 12202d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST3_TP1 0x000000e9 12212d756322SRob Clark 12222d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST3_TP2 0x000000ea 12232d756322SRob Clark 12242d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST3_TP3 0x000000eb 12252d756322SRob Clark 12262d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST4_TP0 0x000000ec 12272d756322SRob Clark 12282d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST4_TP1 0x000000ed 12292d756322SRob Clark 12302d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST4_TP2 0x000000ee 12312d756322SRob Clark 12322d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST4_TP3 0x000000ef 12332d756322SRob Clark 12342d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RB0 0x000000f0 12352d756322SRob Clark 12362d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RB1 0x000000f1 12372d756322SRob Clark 12382d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RB2 0x000000f2 12392d756322SRob Clark 12402d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RB3 0x000000f3 12412d756322SRob Clark 12422d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RB0 0x000000f4 12432d756322SRob Clark 12442d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RB1 0x000000f5 12452d756322SRob Clark 12462d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RB2 0x000000f6 12472d756322SRob Clark 12482d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RB3 0x000000f7 12492d756322SRob Clark 12502d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_CCU0 0x000000f8 12512d756322SRob Clark 12522d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_CCU1 0x000000f9 12532d756322SRob Clark 12542d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_CCU2 0x000000fa 12552d756322SRob Clark 12562d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_CCU3 0x000000fb 12572d756322SRob Clark 12582d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000100 12592d756322SRob Clark 12602d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000101 12612d756322SRob Clark 12622d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000102 12632d756322SRob Clark 12642d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000103 12652d756322SRob Clark 12662d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_RAC 0x00000104 12672d756322SRob Clark 12682d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_RAC 0x00000105 12692d756322SRob Clark 12702d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_RAC 0x00000106 12712d756322SRob Clark 12722d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_RAC 0x00000107 12732d756322SRob Clark 12742d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000108 12752d756322SRob Clark 12762d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000109 12772d756322SRob Clark 12782d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000010a 12792d756322SRob Clark 12802d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_UCHE 0x0000010b 12812d756322SRob Clark 12822d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE 0x0000010c 12832d756322SRob Clark 12842d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE 0x0000010d 12852d756322SRob Clark 12862d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE 0x0000010e 12872d756322SRob Clark 12882d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_UCHE 0x0000010f 12892d756322SRob Clark 12902d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_UCHE 0x00000110 12912d756322SRob Clark 12922d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_MODE_VFD 0x00000111 12932d756322SRob Clark 12942d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_VFD 0x00000112 12952d756322SRob Clark 12962d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_VFD 0x00000113 12972d756322SRob Clark 12982d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_MODE_GPC 0x00000114 12992d756322SRob Clark 13002d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_GPC 0x00000115 13012d756322SRob Clark 13022d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_GPC 0x00000116 13032d756322SRob Clark 13042d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2 0x00000117 13052d756322SRob Clark 13062d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX 0x00000118 13072d756322SRob Clark 13082d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX 0x00000119 13092d756322SRob Clark 13102d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX 0x0000011a 13112d756322SRob Clark 13122d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_MODE_HLSQ 0x0000011b 13132d756322SRob Clark 13142d756322SRob Clark #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ 0x0000011c 13152d756322SRob Clark 13162d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A 0x00000600 13172d756322SRob Clark 13182d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B 0x00000601 13192d756322SRob Clark 13202d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C 0x00000602 13212d756322SRob Clark 13222d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D 0x00000603 13232d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK 0x000000ff 13242d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT 0 13252d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val) 13262d756322SRob Clark { 13272d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK; 13282d756322SRob Clark } 13292d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK 0x0000ff00 13302d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT 8 13312d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val) 13322d756322SRob Clark { 13332d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK; 13342d756322SRob Clark } 13352d756322SRob Clark 13362d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT 0x00000604 13372d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f 13382d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0 13392d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) 13402d756322SRob Clark { 13412d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; 13422d756322SRob Clark } 13432d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000 13442d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12 13452d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) 13462d756322SRob Clark { 13472d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; 13482d756322SRob Clark } 13492d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000 13502d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28 13512d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) 13522d756322SRob Clark { 13532d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; 13542d756322SRob Clark } 13552d756322SRob Clark 13562d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM 0x00000605 13572d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000 13582d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24 13592d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) 13602d756322SRob Clark { 13612d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; 13622d756322SRob Clark } 13632d756322SRob Clark 13642d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 0x00000608 13652d756322SRob Clark 13662d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 0x00000609 13672d756322SRob Clark 13682d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 0x0000060a 13692d756322SRob Clark 13702d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 0x0000060b 13712d756322SRob Clark 13722d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 0x0000060c 13732d756322SRob Clark 13742d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 0x0000060d 13752d756322SRob Clark 13762d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 0x0000060e 13772d756322SRob Clark 13782d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 0x0000060f 13792d756322SRob Clark 13802d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000610 13812d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f 13822d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0 13832d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) 13842d756322SRob Clark { 13852d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; 13862d756322SRob Clark } 13872d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0 13882d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4 13892d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) 13902d756322SRob Clark { 13912d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; 13922d756322SRob Clark } 13932d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00 13942d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8 13952d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) 13962d756322SRob Clark { 13972d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; 13982d756322SRob Clark } 13992d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000 14002d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12 14012d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) 14022d756322SRob Clark { 14032d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; 14042d756322SRob Clark } 14052d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000 14062d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16 14072d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) 14082d756322SRob Clark { 14092d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; 14102d756322SRob Clark } 14112d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000 14122d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20 14132d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) 14142d756322SRob Clark { 14152d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; 14162d756322SRob Clark } 14172d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000 14182d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24 14192d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) 14202d756322SRob Clark { 14212d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; 14222d756322SRob Clark } 14232d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000 14242d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28 14252d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) 14262d756322SRob Clark { 14272d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; 14282d756322SRob Clark } 14292d756322SRob Clark 14302d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000611 14312d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f 14322d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0 14332d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) 14342d756322SRob Clark { 14352d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; 14362d756322SRob Clark } 14372d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0 14382d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4 14392d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) 14402d756322SRob Clark { 14412d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; 14422d756322SRob Clark } 14432d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00 14442d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8 14452d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) 14462d756322SRob Clark { 14472d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; 14482d756322SRob Clark } 14492d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000 14502d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12 14512d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) 14522d756322SRob Clark { 14532d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; 14542d756322SRob Clark } 14552d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000 14562d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16 14572d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) 14582d756322SRob Clark { 14592d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; 14602d756322SRob Clark } 14612d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000 14622d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20 14632d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) 14642d756322SRob Clark { 14652d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; 14662d756322SRob Clark } 14672d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000 14682d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24 14692d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) 14702d756322SRob Clark { 14712d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; 14722d756322SRob Clark } 14732d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000 14742d756322SRob Clark #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28 14752d756322SRob Clark static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) 14762d756322SRob Clark { 14772d756322SRob Clark return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; 14782d756322SRob Clark } 14792d756322SRob Clark 14802d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000062f 14812d756322SRob Clark 14822d756322SRob Clark #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630 14832d756322SRob Clark 14842d756322SRob Clark #define REG_A6XX_VSC_PERFCTR_VSC_SEL_0 0x00000cd8 14852d756322SRob Clark 14862d756322SRob Clark #define REG_A6XX_VSC_PERFCTR_VSC_SEL_1 0x00000cd9 14872d756322SRob Clark 14882d756322SRob Clark #define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601 14892d756322SRob Clark 14902d756322SRob Clark #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_0 0x00008610 14912d756322SRob Clark 14922d756322SRob Clark #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_1 0x00008611 14932d756322SRob Clark 14942d756322SRob Clark #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_2 0x00008612 14952d756322SRob Clark 14962d756322SRob Clark #define REG_A6XX_GRAS_PERFCTR_TSE_SEL_3 0x00008613 14972d756322SRob Clark 14982d756322SRob Clark #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_0 0x00008614 14992d756322SRob Clark 15002d756322SRob Clark #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_1 0x00008615 15012d756322SRob Clark 15022d756322SRob Clark #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_2 0x00008616 15032d756322SRob Clark 15042d756322SRob Clark #define REG_A6XX_GRAS_PERFCTR_RAS_SEL_3 0x00008617 15052d756322SRob Clark 15062d756322SRob Clark #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_0 0x00008618 15072d756322SRob Clark 15082d756322SRob Clark #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_1 0x00008619 15092d756322SRob Clark 15102d756322SRob Clark #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_2 0x0000861a 15112d756322SRob Clark 15122d756322SRob Clark #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL_3 0x0000861b 15132d756322SRob Clark 15142d756322SRob Clark #define REG_A6XX_RB_ADDR_MODE_CNTL 0x00008e05 15152d756322SRob Clark 15162d756322SRob Clark #define REG_A6XX_RB_NC_MODE_CNTL 0x00008e08 15172d756322SRob Clark 15182d756322SRob Clark #define REG_A6XX_RB_PERFCTR_RB_SEL_0 0x00008e10 15192d756322SRob Clark 15202d756322SRob Clark #define REG_A6XX_RB_PERFCTR_RB_SEL_1 0x00008e11 15212d756322SRob Clark 15222d756322SRob Clark #define REG_A6XX_RB_PERFCTR_RB_SEL_2 0x00008e12 15232d756322SRob Clark 15242d756322SRob Clark #define REG_A6XX_RB_PERFCTR_RB_SEL_3 0x00008e13 15252d756322SRob Clark 15262d756322SRob Clark #define REG_A6XX_RB_PERFCTR_RB_SEL_4 0x00008e14 15272d756322SRob Clark 15282d756322SRob Clark #define REG_A6XX_RB_PERFCTR_RB_SEL_5 0x00008e15 15292d756322SRob Clark 15302d756322SRob Clark #define REG_A6XX_RB_PERFCTR_RB_SEL_6 0x00008e16 15312d756322SRob Clark 15322d756322SRob Clark #define REG_A6XX_RB_PERFCTR_RB_SEL_7 0x00008e17 15332d756322SRob Clark 15342d756322SRob Clark #define REG_A6XX_RB_PERFCTR_CCU_SEL_0 0x00008e18 15352d756322SRob Clark 15362d756322SRob Clark #define REG_A6XX_RB_PERFCTR_CCU_SEL_1 0x00008e19 15372d756322SRob Clark 15382d756322SRob Clark #define REG_A6XX_RB_PERFCTR_CCU_SEL_2 0x00008e1a 15392d756322SRob Clark 15402d756322SRob Clark #define REG_A6XX_RB_PERFCTR_CCU_SEL_3 0x00008e1b 15412d756322SRob Clark 15422d756322SRob Clark #define REG_A6XX_RB_PERFCTR_CCU_SEL_4 0x00008e1c 15432d756322SRob Clark 15442d756322SRob Clark #define REG_A6XX_RB_PERFCTR_CMP_SEL_0 0x00008e2c 15452d756322SRob Clark 15462d756322SRob Clark #define REG_A6XX_RB_PERFCTR_CMP_SEL_1 0x00008e2d 15472d756322SRob Clark 15482d756322SRob Clark #define REG_A6XX_RB_PERFCTR_CMP_SEL_2 0x00008e2e 15492d756322SRob Clark 15502d756322SRob Clark #define REG_A6XX_RB_PERFCTR_CMP_SEL_3 0x00008e2f 15512d756322SRob Clark 15522d756322SRob Clark #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD 0x00008e3d 15532d756322SRob Clark 15542d756322SRob Clark #define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x00008e50 15552d756322SRob Clark 15562d756322SRob Clark #define REG_A6XX_PC_DBG_ECO_CNTL 0x00009e00 15572d756322SRob Clark 15582d756322SRob Clark #define REG_A6XX_PC_ADDR_MODE_CNTL 0x00009e01 15592d756322SRob Clark 15602d756322SRob Clark #define REG_A6XX_PC_PERFCTR_PC_SEL_0 0x00009e34 15612d756322SRob Clark 15622d756322SRob Clark #define REG_A6XX_PC_PERFCTR_PC_SEL_1 0x00009e35 15632d756322SRob Clark 15642d756322SRob Clark #define REG_A6XX_PC_PERFCTR_PC_SEL_2 0x00009e36 15652d756322SRob Clark 15662d756322SRob Clark #define REG_A6XX_PC_PERFCTR_PC_SEL_3 0x00009e37 15672d756322SRob Clark 15682d756322SRob Clark #define REG_A6XX_PC_PERFCTR_PC_SEL_4 0x00009e38 15692d756322SRob Clark 15702d756322SRob Clark #define REG_A6XX_PC_PERFCTR_PC_SEL_5 0x00009e39 15712d756322SRob Clark 15722d756322SRob Clark #define REG_A6XX_PC_PERFCTR_PC_SEL_6 0x00009e3a 15732d756322SRob Clark 15742d756322SRob Clark #define REG_A6XX_PC_PERFCTR_PC_SEL_7 0x00009e3b 15752d756322SRob Clark 15762d756322SRob Clark #define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05 15772d756322SRob Clark 15782d756322SRob Clark #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x0000be10 15792d756322SRob Clark 15802d756322SRob Clark #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x0000be11 15812d756322SRob Clark 15822d756322SRob Clark #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x0000be12 15832d756322SRob Clark 15842d756322SRob Clark #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x0000be13 15852d756322SRob Clark 15862d756322SRob Clark #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x0000be14 15872d756322SRob Clark 15882d756322SRob Clark #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x0000be15 15892d756322SRob Clark 15902d756322SRob Clark #define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800 15912d756322SRob Clark 15922d756322SRob Clark #define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000 15932d756322SRob Clark 15942d756322SRob Clark #define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601 15952d756322SRob Clark 15962d756322SRob Clark #define REG_A6XX_VFD_PERFCTR_VFD_SEL_0 0x0000a610 15972d756322SRob Clark 15982d756322SRob Clark #define REG_A6XX_VFD_PERFCTR_VFD_SEL_1 0x0000a611 15992d756322SRob Clark 16002d756322SRob Clark #define REG_A6XX_VFD_PERFCTR_VFD_SEL_2 0x0000a612 16012d756322SRob Clark 16022d756322SRob Clark #define REG_A6XX_VFD_PERFCTR_VFD_SEL_3 0x0000a613 16032d756322SRob Clark 16042d756322SRob Clark #define REG_A6XX_VFD_PERFCTR_VFD_SEL_4 0x0000a614 16052d756322SRob Clark 16062d756322SRob Clark #define REG_A6XX_VFD_PERFCTR_VFD_SEL_5 0x0000a615 16072d756322SRob Clark 16082d756322SRob Clark #define REG_A6XX_VFD_PERFCTR_VFD_SEL_6 0x0000a616 16092d756322SRob Clark 16102d756322SRob Clark #define REG_A6XX_VFD_PERFCTR_VFD_SEL_7 0x0000a617 16112d756322SRob Clark 16122d756322SRob Clark #define REG_A6XX_VPC_ADDR_MODE_CNTL 0x00009601 16132d756322SRob Clark 16142d756322SRob Clark #define REG_A6XX_VPC_PERFCTR_VPC_SEL_0 0x00009604 16152d756322SRob Clark 16162d756322SRob Clark #define REG_A6XX_VPC_PERFCTR_VPC_SEL_1 0x00009605 16172d756322SRob Clark 16182d756322SRob Clark #define REG_A6XX_VPC_PERFCTR_VPC_SEL_2 0x00009606 16192d756322SRob Clark 16202d756322SRob Clark #define REG_A6XX_VPC_PERFCTR_VPC_SEL_3 0x00009607 16212d756322SRob Clark 16222d756322SRob Clark #define REG_A6XX_VPC_PERFCTR_VPC_SEL_4 0x00009608 16232d756322SRob Clark 16242d756322SRob Clark #define REG_A6XX_VPC_PERFCTR_VPC_SEL_5 0x00009609 16252d756322SRob Clark 16262d756322SRob Clark #define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00 16272d756322SRob Clark 16282d756322SRob Clark #define REG_A6XX_UCHE_MODE_CNTL 0x00000e01 16292d756322SRob Clark 16302d756322SRob Clark #define REG_A6XX_UCHE_WRITE_RANGE_MAX_LO 0x00000e05 16312d756322SRob Clark 16322d756322SRob Clark #define REG_A6XX_UCHE_WRITE_RANGE_MAX_HI 0x00000e06 16332d756322SRob Clark 16342d756322SRob Clark #define REG_A6XX_UCHE_WRITE_THRU_BASE_LO 0x00000e07 16352d756322SRob Clark 16362d756322SRob Clark #define REG_A6XX_UCHE_WRITE_THRU_BASE_HI 0x00000e08 16372d756322SRob Clark 16382d756322SRob Clark #define REG_A6XX_UCHE_TRAP_BASE_LO 0x00000e09 16392d756322SRob Clark 16402d756322SRob Clark #define REG_A6XX_UCHE_TRAP_BASE_HI 0x00000e0a 16412d756322SRob Clark 16422d756322SRob Clark #define REG_A6XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e0b 16432d756322SRob Clark 16442d756322SRob Clark #define REG_A6XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e0c 16452d756322SRob Clark 16462d756322SRob Clark #define REG_A6XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e0d 16472d756322SRob Clark 16482d756322SRob Clark #define REG_A6XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e0e 16492d756322SRob Clark 16502d756322SRob Clark #define REG_A6XX_UCHE_CACHE_WAYS 0x00000e17 16512d756322SRob Clark 16522d756322SRob Clark #define REG_A6XX_UCHE_FILTER_CNTL 0x00000e18 16532d756322SRob Clark 16542d756322SRob Clark #define REG_A6XX_UCHE_CLIENT_PF 0x00000e19 16552d756322SRob Clark #define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK 0x000000ff 16562d756322SRob Clark #define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT 0 16572d756322SRob Clark static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val) 16582d756322SRob Clark { 16592d756322SRob Clark return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK; 16602d756322SRob Clark } 16612d756322SRob Clark 16622d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e1c 16632d756322SRob Clark 16642d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e1d 16652d756322SRob Clark 16662d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e1e 16672d756322SRob Clark 16682d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e1f 16692d756322SRob Clark 16702d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e20 16712d756322SRob Clark 16722d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e21 16732d756322SRob Clark 16742d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e22 16752d756322SRob Clark 16762d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e23 16772d756322SRob Clark 16782d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_8 0x00000e24 16792d756322SRob Clark 16802d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_9 0x00000e25 16812d756322SRob Clark 16822d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_10 0x00000e26 16832d756322SRob Clark 16842d756322SRob Clark #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_11 0x00000e27 16852d756322SRob Clark 16862d756322SRob Clark #define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01 16872d756322SRob Clark 16882d756322SRob Clark #define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02 16892d756322SRob Clark 16902d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_0 0x0000ae10 16912d756322SRob Clark 16922d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_1 0x0000ae11 16932d756322SRob Clark 16942d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_2 0x0000ae12 16952d756322SRob Clark 16962d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_3 0x0000ae13 16972d756322SRob Clark 16982d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_4 0x0000ae14 16992d756322SRob Clark 17002d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_5 0x0000ae15 17012d756322SRob Clark 17022d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_6 0x0000ae16 17032d756322SRob Clark 17042d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_7 0x0000ae17 17052d756322SRob Clark 17062d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_8 0x0000ae18 17072d756322SRob Clark 17082d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_9 0x0000ae19 17092d756322SRob Clark 17102d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_10 0x0000ae1a 17112d756322SRob Clark 17122d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_11 0x0000ae1b 17132d756322SRob Clark 17142d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_12 0x0000ae1c 17152d756322SRob Clark 17162d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_13 0x0000ae1d 17172d756322SRob Clark 17182d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_14 0x0000ae1e 17192d756322SRob Clark 17202d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_15 0x0000ae1f 17212d756322SRob Clark 17222d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_16 0x0000ae20 17232d756322SRob Clark 17242d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_17 0x0000ae21 17252d756322SRob Clark 17262d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_18 0x0000ae22 17272d756322SRob Clark 17282d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_19 0x0000ae23 17292d756322SRob Clark 17302d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_20 0x0000ae24 17312d756322SRob Clark 17322d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_21 0x0000ae25 17332d756322SRob Clark 17342d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_22 0x0000ae26 17352d756322SRob Clark 17362d756322SRob Clark #define REG_A6XX_SP_PERFCTR_SP_SEL_23 0x0000ae27 17372d756322SRob Clark 17382d756322SRob Clark #define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601 17392d756322SRob Clark 17402d756322SRob Clark #define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604 17412d756322SRob Clark 17422d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_0 0x0000b610 17432d756322SRob Clark 17442d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_1 0x0000b611 17452d756322SRob Clark 17462d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_2 0x0000b612 17472d756322SRob Clark 17482d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_3 0x0000b613 17492d756322SRob Clark 17502d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_4 0x0000b614 17512d756322SRob Clark 17522d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_5 0x0000b615 17532d756322SRob Clark 17542d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_6 0x0000b616 17552d756322SRob Clark 17562d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_7 0x0000b617 17572d756322SRob Clark 17582d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_8 0x0000b618 17592d756322SRob Clark 17602d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_9 0x0000b619 17612d756322SRob Clark 17622d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_10 0x0000b61a 17632d756322SRob Clark 17642d756322SRob Clark #define REG_A6XX_TPL1_PERFCTR_TP_SEL_11 0x0000b61b 17652d756322SRob Clark 17662d756322SRob Clark #define REG_A6XX_VBIF_VERSION 0x00003000 17672d756322SRob Clark 17682d756322SRob Clark #define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 17692d756322SRob Clark 17702d756322SRob Clark #define REG_A6XX_VBIF_XIN_HALT_CTRL0 0x00003080 17712d756322SRob Clark 17722d756322SRob Clark #define REG_A6XX_VBIF_XIN_HALT_CTRL1 0x00003081 17732d756322SRob Clark 17742d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_SEL0 0x000030d0 17752d756322SRob Clark 17762d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_SEL1 0x000030d1 17772d756322SRob Clark 17782d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_SEL2 0x000030d2 17792d756322SRob Clark 17802d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_SEL3 0x000030d3 17812d756322SRob Clark 17822d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_LOW0 0x000030d8 17832d756322SRob Clark 17842d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_LOW1 0x000030d9 17852d756322SRob Clark 17862d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_LOW2 0x000030da 17872d756322SRob Clark 17882d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_LOW3 0x000030db 17892d756322SRob Clark 17902d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_HIGH0 0x000030e0 17912d756322SRob Clark 17922d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_HIGH1 0x000030e1 17932d756322SRob Clark 17942d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_HIGH2 0x000030e2 17952d756322SRob Clark 17962d756322SRob Clark #define REG_A6XX_VBIF_PERF_CNT_HIGH3 0x000030e3 17972d756322SRob Clark 17982d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_EN0 0x00003100 17992d756322SRob Clark 18002d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_EN1 0x00003101 18012d756322SRob Clark 18022d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_EN2 0x00003102 18032d756322SRob Clark 18042d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110 18052d756322SRob Clark 18062d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111 18072d756322SRob Clark 18082d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112 18092d756322SRob Clark 18102d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118 18112d756322SRob Clark 18122d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119 18132d756322SRob Clark 18142d756322SRob Clark #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a 18152d756322SRob Clark 18162d756322SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A 0x00018400 18172d756322SRob Clark 18182d756322SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B 0x00018401 18192d756322SRob Clark 18202d756322SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C 0x00018402 18212d756322SRob Clark 18222d756322SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D 0x00018403 18232d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK 0x000000ff 18242d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT 0 18252d756322SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val) 18262d756322SRob Clark { 18272d756322SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK; 18282d756322SRob Clark } 18292d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK 0x0000ff00 18302d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT 8 18312d756322SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val) 18322d756322SRob Clark { 18332d756322SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK; 18342d756322SRob Clark } 18352d756322SRob Clark 18362d756322SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT 0x00018404 18372d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f 18382d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0 18392d756322SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) 18402d756322SRob Clark { 18412d756322SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; 18422d756322SRob Clark } 18432d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000 18442d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12 18452d756322SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) 18462d756322SRob Clark { 18472d756322SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; 18482d756322SRob Clark } 18492d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000 18502d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28 18512d756322SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) 18522d756322SRob Clark { 18532d756322SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; 18542d756322SRob Clark } 18552d756322SRob Clark 18562d756322SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM 0x00018405 18572d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000 18582d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24 18592d756322SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) 18602d756322SRob Clark { 18612d756322SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; 18622d756322SRob Clark } 18632d756322SRob Clark 18642d756322SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 0x00018408 18652d756322SRob Clark 18662d756322SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 0x00018409 18672d756322SRob Clark 18682d756322SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 0x0001840a 18692d756322SRob Clark 18702d756322SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 0x0001840b 18712d756322SRob Clark 18722d756322SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 0x0001840c 18732d756322SRob Clark 18742d756322SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 0x0001840d 18752d756322SRob Clark 18762d756322SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 0x0001840e 18772d756322SRob Clark 18782d756322SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 0x0001840f 18792d756322SRob Clark 18802d756322SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 0x00018410 18812d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f 18822d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0 18832d756322SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) 18842d756322SRob Clark { 18852d756322SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; 18862d756322SRob Clark } 18872d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0 18882d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4 18892d756322SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) 18902d756322SRob Clark { 18912d756322SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; 18922d756322SRob Clark } 18932d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00 18942d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8 18952d756322SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) 18962d756322SRob Clark { 18972d756322SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; 18982d756322SRob Clark } 18992d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000 19002d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12 19012d756322SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) 19022d756322SRob Clark { 19032d756322SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; 19042d756322SRob Clark } 19052d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000 19062d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16 19072d756322SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) 19082d756322SRob Clark { 19092d756322SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; 19102d756322SRob Clark } 19112d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000 19122d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20 19132d756322SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) 19142d756322SRob Clark { 19152d756322SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; 19162d756322SRob Clark } 19172d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000 19182d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24 19192d756322SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) 19202d756322SRob Clark { 19212d756322SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; 19222d756322SRob Clark } 19232d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000 19242d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28 19252d756322SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) 19262d756322SRob Clark { 19272d756322SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; 19282d756322SRob Clark } 19292d756322SRob Clark 19302d756322SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 0x00018411 19312d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f 19322d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0 19332d756322SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) 19342d756322SRob Clark { 19352d756322SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; 19362d756322SRob Clark } 19372d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0 19382d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4 19392d756322SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) 19402d756322SRob Clark { 19412d756322SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; 19422d756322SRob Clark } 19432d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00 19442d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8 19452d756322SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) 19462d756322SRob Clark { 19472d756322SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; 19482d756322SRob Clark } 19492d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000 19502d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12 19512d756322SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) 19522d756322SRob Clark { 19532d756322SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; 19542d756322SRob Clark } 19552d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000 19562d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16 19572d756322SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) 19582d756322SRob Clark { 19592d756322SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; 19602d756322SRob Clark } 19612d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000 19622d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20 19632d756322SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) 19642d756322SRob Clark { 19652d756322SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; 19662d756322SRob Clark } 19672d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000 19682d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24 19692d756322SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) 19702d756322SRob Clark { 19712d756322SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; 19722d756322SRob Clark } 19732d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000 19742d756322SRob Clark #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28 19752d756322SRob Clark static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) 19762d756322SRob Clark { 19772d756322SRob Clark return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; 19782d756322SRob Clark } 19792d756322SRob Clark 19802d756322SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0001842f 19812d756322SRob Clark 19822d756322SRob Clark #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00018430 19832d756322SRob Clark 19842d756322SRob Clark #define REG_A6XX_PDC_GPU_ENABLE_PDC 0x00021140 19852d756322SRob Clark 19862d756322SRob Clark #define REG_A6XX_PDC_GPU_SEQ_START_ADDR 0x00021148 19872d756322SRob Clark 19882d756322SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CONTROL 0x00021540 19892d756322SRob Clark 19902d756322SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK 0x00021541 19912d756322SRob Clark 19922d756322SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK 0x00021542 19932d756322SRob Clark 19942d756322SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID 0x00021543 19952d756322SRob Clark 19962d756322SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR 0x00021544 19972d756322SRob Clark 19982d756322SRob Clark #define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA 0x00021545 19992d756322SRob Clark 20002d756322SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CONTROL 0x00021572 20012d756322SRob Clark 20022d756322SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK 0x00021573 20032d756322SRob Clark 20042d756322SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK 0x00021574 20052d756322SRob Clark 20062d756322SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID 0x00021575 20072d756322SRob Clark 20082d756322SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR 0x00021576 20092d756322SRob Clark 20102d756322SRob Clark #define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA 0x00021577 20112d756322SRob Clark 20122d756322SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CONTROL 0x000215a4 20132d756322SRob Clark 20142d756322SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK 0x000215a5 20152d756322SRob Clark 20162d756322SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK 0x000215a6 20172d756322SRob Clark 20182d756322SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID 0x000215a7 20192d756322SRob Clark 20202d756322SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR 0x000215a8 20212d756322SRob Clark 20222d756322SRob Clark #define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA 0x000215a9 20232d756322SRob Clark 20242d756322SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CONTROL 0x000215d6 20252d756322SRob Clark 20262d756322SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK 0x000215d7 20272d756322SRob Clark 20282d756322SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK 0x000215d8 20292d756322SRob Clark 20302d756322SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID 0x000215d9 20312d756322SRob Clark 20322d756322SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR 0x000215da 20332d756322SRob Clark 20342d756322SRob Clark #define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA 0x000215db 20352d756322SRob Clark 20362d756322SRob Clark #define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x000a0000 20372d756322SRob Clark 20382d756322SRob Clark #define REG_A6XX_X1_WINDOW_OFFSET 0x000088d4 20392d756322SRob Clark #define A6XX_X1_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 20402d756322SRob Clark #define A6XX_X1_WINDOW_OFFSET_X__MASK 0x00007fff 20412d756322SRob Clark #define A6XX_X1_WINDOW_OFFSET_X__SHIFT 0 20422d756322SRob Clark static inline uint32_t A6XX_X1_WINDOW_OFFSET_X(uint32_t val) 20432d756322SRob Clark { 20442d756322SRob Clark return ((val) << A6XX_X1_WINDOW_OFFSET_X__SHIFT) & A6XX_X1_WINDOW_OFFSET_X__MASK; 20452d756322SRob Clark } 20462d756322SRob Clark #define A6XX_X1_WINDOW_OFFSET_Y__MASK 0x7fff0000 20472d756322SRob Clark #define A6XX_X1_WINDOW_OFFSET_Y__SHIFT 16 20482d756322SRob Clark static inline uint32_t A6XX_X1_WINDOW_OFFSET_Y(uint32_t val) 20492d756322SRob Clark { 20502d756322SRob Clark return ((val) << A6XX_X1_WINDOW_OFFSET_Y__SHIFT) & A6XX_X1_WINDOW_OFFSET_Y__MASK; 20512d756322SRob Clark } 20522d756322SRob Clark 20532d756322SRob Clark #define REG_A6XX_X2_WINDOW_OFFSET 0x0000b4d1 20542d756322SRob Clark #define A6XX_X2_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 20552d756322SRob Clark #define A6XX_X2_WINDOW_OFFSET_X__MASK 0x00007fff 20562d756322SRob Clark #define A6XX_X2_WINDOW_OFFSET_X__SHIFT 0 20572d756322SRob Clark static inline uint32_t A6XX_X2_WINDOW_OFFSET_X(uint32_t val) 20582d756322SRob Clark { 20592d756322SRob Clark return ((val) << A6XX_X2_WINDOW_OFFSET_X__SHIFT) & A6XX_X2_WINDOW_OFFSET_X__MASK; 20602d756322SRob Clark } 20612d756322SRob Clark #define A6XX_X2_WINDOW_OFFSET_Y__MASK 0x7fff0000 20622d756322SRob Clark #define A6XX_X2_WINDOW_OFFSET_Y__SHIFT 16 20632d756322SRob Clark static inline uint32_t A6XX_X2_WINDOW_OFFSET_Y(uint32_t val) 20642d756322SRob Clark { 20652d756322SRob Clark return ((val) << A6XX_X2_WINDOW_OFFSET_Y__SHIFT) & A6XX_X2_WINDOW_OFFSET_Y__MASK; 20662d756322SRob Clark } 20672d756322SRob Clark 20682d756322SRob Clark #define REG_A6XX_X3_WINDOW_OFFSET 0x0000b307 20692d756322SRob Clark #define A6XX_X3_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 20702d756322SRob Clark #define A6XX_X3_WINDOW_OFFSET_X__MASK 0x00007fff 20712d756322SRob Clark #define A6XX_X3_WINDOW_OFFSET_X__SHIFT 0 20722d756322SRob Clark static inline uint32_t A6XX_X3_WINDOW_OFFSET_X(uint32_t val) 20732d756322SRob Clark { 20742d756322SRob Clark return ((val) << A6XX_X3_WINDOW_OFFSET_X__SHIFT) & A6XX_X3_WINDOW_OFFSET_X__MASK; 20752d756322SRob Clark } 20762d756322SRob Clark #define A6XX_X3_WINDOW_OFFSET_Y__MASK 0x7fff0000 20772d756322SRob Clark #define A6XX_X3_WINDOW_OFFSET_Y__SHIFT 16 20782d756322SRob Clark static inline uint32_t A6XX_X3_WINDOW_OFFSET_Y(uint32_t val) 20792d756322SRob Clark { 20802d756322SRob Clark return ((val) << A6XX_X3_WINDOW_OFFSET_Y__SHIFT) & A6XX_X3_WINDOW_OFFSET_Y__MASK; 20812d756322SRob Clark } 20822d756322SRob Clark 20832d756322SRob Clark #define REG_A6XX_X1_BIN_SIZE 0x000080a1 20842d756322SRob Clark #define A6XX_X1_BIN_SIZE_WIDTH__MASK 0x000000ff 20852d756322SRob Clark #define A6XX_X1_BIN_SIZE_WIDTH__SHIFT 0 20862d756322SRob Clark static inline uint32_t A6XX_X1_BIN_SIZE_WIDTH(uint32_t val) 20872d756322SRob Clark { 20882d756322SRob Clark return ((val >> 5) << A6XX_X1_BIN_SIZE_WIDTH__SHIFT) & A6XX_X1_BIN_SIZE_WIDTH__MASK; 20892d756322SRob Clark } 20902d756322SRob Clark #define A6XX_X1_BIN_SIZE_HEIGHT__MASK 0x0001ff00 20912d756322SRob Clark #define A6XX_X1_BIN_SIZE_HEIGHT__SHIFT 8 20922d756322SRob Clark static inline uint32_t A6XX_X1_BIN_SIZE_HEIGHT(uint32_t val) 20932d756322SRob Clark { 20942d756322SRob Clark return ((val >> 4) << A6XX_X1_BIN_SIZE_HEIGHT__SHIFT) & A6XX_X1_BIN_SIZE_HEIGHT__MASK; 20952d756322SRob Clark } 20962d756322SRob Clark 20972d756322SRob Clark #define REG_A6XX_X2_BIN_SIZE 0x00008800 20982d756322SRob Clark #define A6XX_X2_BIN_SIZE_WIDTH__MASK 0x000000ff 20992d756322SRob Clark #define A6XX_X2_BIN_SIZE_WIDTH__SHIFT 0 21002d756322SRob Clark static inline uint32_t A6XX_X2_BIN_SIZE_WIDTH(uint32_t val) 21012d756322SRob Clark { 21022d756322SRob Clark return ((val >> 5) << A6XX_X2_BIN_SIZE_WIDTH__SHIFT) & A6XX_X2_BIN_SIZE_WIDTH__MASK; 21032d756322SRob Clark } 21042d756322SRob Clark #define A6XX_X2_BIN_SIZE_HEIGHT__MASK 0x0001ff00 21052d756322SRob Clark #define A6XX_X2_BIN_SIZE_HEIGHT__SHIFT 8 21062d756322SRob Clark static inline uint32_t A6XX_X2_BIN_SIZE_HEIGHT(uint32_t val) 21072d756322SRob Clark { 21082d756322SRob Clark return ((val >> 4) << A6XX_X2_BIN_SIZE_HEIGHT__SHIFT) & A6XX_X2_BIN_SIZE_HEIGHT__MASK; 21092d756322SRob Clark } 21102d756322SRob Clark 21112d756322SRob Clark #define REG_A6XX_X3_BIN_SIZE 0x000088d3 21122d756322SRob Clark #define A6XX_X3_BIN_SIZE_WIDTH__MASK 0x000000ff 21132d756322SRob Clark #define A6XX_X3_BIN_SIZE_WIDTH__SHIFT 0 21142d756322SRob Clark static inline uint32_t A6XX_X3_BIN_SIZE_WIDTH(uint32_t val) 21152d756322SRob Clark { 21162d756322SRob Clark return ((val >> 5) << A6XX_X3_BIN_SIZE_WIDTH__SHIFT) & A6XX_X3_BIN_SIZE_WIDTH__MASK; 21172d756322SRob Clark } 21182d756322SRob Clark #define A6XX_X3_BIN_SIZE_HEIGHT__MASK 0x0001ff00 21192d756322SRob Clark #define A6XX_X3_BIN_SIZE_HEIGHT__SHIFT 8 21202d756322SRob Clark static inline uint32_t A6XX_X3_BIN_SIZE_HEIGHT(uint32_t val) 21212d756322SRob Clark { 21222d756322SRob Clark return ((val >> 4) << A6XX_X3_BIN_SIZE_HEIGHT__SHIFT) & A6XX_X3_BIN_SIZE_HEIGHT__MASK; 21232d756322SRob Clark } 21242d756322SRob Clark 21252d756322SRob Clark #define REG_A6XX_VSC_BIN_SIZE 0x00000c02 21262d756322SRob Clark #define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff 21272d756322SRob Clark #define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 21282d756322SRob Clark static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 21292d756322SRob Clark { 21302d756322SRob Clark return ((val >> 5) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK; 21312d756322SRob Clark } 21322d756322SRob Clark #define A6XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001ff00 21332d756322SRob Clark #define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT 8 21342d756322SRob Clark static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 21352d756322SRob Clark { 21362d756322SRob Clark return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK; 21372d756322SRob Clark } 21382d756322SRob Clark 21392d756322SRob Clark #define REG_A6XX_VSC_SIZE_ADDRESS_LO 0x00000c03 21402d756322SRob Clark 21412d756322SRob Clark #define REG_A6XX_VSC_SIZE_ADDRESS_HI 0x00000c04 21422d756322SRob Clark 21432d756322SRob Clark #define REG_A6XX_VSC_BIN_COUNT 0x00000c06 21442d756322SRob Clark #define A6XX_VSC_BIN_COUNT_NX__MASK 0x000007fe 21452d756322SRob Clark #define A6XX_VSC_BIN_COUNT_NX__SHIFT 1 21462d756322SRob Clark static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val) 21472d756322SRob Clark { 21482d756322SRob Clark return ((val) << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK; 21492d756322SRob Clark } 21502d756322SRob Clark #define A6XX_VSC_BIN_COUNT_NY__MASK 0x001ff800 21512d756322SRob Clark #define A6XX_VSC_BIN_COUNT_NY__SHIFT 11 21522d756322SRob Clark static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val) 21532d756322SRob Clark { 21542d756322SRob Clark return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK; 21552d756322SRob Clark } 21562d756322SRob Clark 21572d756322SRob Clark static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 21582d756322SRob Clark 21592d756322SRob Clark static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 21602d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff 21612d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0 21622d756322SRob Clark static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) 21632d756322SRob Clark { 21642d756322SRob Clark return ((val) << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK; 21652d756322SRob Clark } 21662d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00 21672d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10 21682d756322SRob Clark static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) 21692d756322SRob Clark { 21702d756322SRob Clark return ((val) << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK; 21712d756322SRob Clark } 21722d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_W__MASK 0x03f00000 21732d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20 21742d756322SRob Clark static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) 21752d756322SRob Clark { 21762d756322SRob Clark return ((val) << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK; 21772d756322SRob Clark } 21782d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_H__MASK 0xfc000000 21792d756322SRob Clark #define A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT 26 21802d756322SRob Clark static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) 21812d756322SRob Clark { 21822d756322SRob Clark return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK; 21832d756322SRob Clark } 21842d756322SRob Clark 21852d756322SRob Clark #define REG_A6XX_VSC_XXX_ADDRESS_LO 0x00000c30 21862d756322SRob Clark 21872d756322SRob Clark #define REG_A6XX_VSC_XXX_ADDRESS_HI 0x00000c31 21882d756322SRob Clark 21892d756322SRob Clark #define REG_A6XX_VSC_XXX_PITCH 0x00000c32 21902d756322SRob Clark 21912d756322SRob Clark #define REG_A6XX_VSC_PIPE_DATA_ADDRESS_LO 0x00000c34 21922d756322SRob Clark 21932d756322SRob Clark #define REG_A6XX_VSC_PIPE_DATA_ADDRESS_HI 0x00000c35 21942d756322SRob Clark 21952d756322SRob Clark #define REG_A6XX_VSC_PIPE_DATA_PITCH 0x00000c36 21962d756322SRob Clark 21972d756322SRob Clark static inline uint32_t REG_A6XX_VSC_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; } 21982d756322SRob Clark 21992d756322SRob Clark static inline uint32_t REG_A6XX_VSC_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; } 22002d756322SRob Clark 22012d756322SRob Clark #define REG_A6XX_UCHE_UNKNOWN_0E12 0x00000e12 22022d756322SRob Clark 22032d756322SRob Clark #define REG_A6XX_GRAS_UNKNOWN_8001 0x00008001 22042d756322SRob Clark 22052d756322SRob Clark #define REG_A6XX_GRAS_UNKNOWN_8004 0x00008004 22062d756322SRob Clark 22072d756322SRob Clark #define REG_A6XX_GRAS_CNTL 0x00008005 22082d756322SRob Clark #define A6XX_GRAS_CNTL_VARYING 0x00000001 22092d756322SRob Clark #define A6XX_GRAS_CNTL_XCOORD 0x00000040 22102d756322SRob Clark #define A6XX_GRAS_CNTL_YCOORD 0x00000080 22112d756322SRob Clark #define A6XX_GRAS_CNTL_ZCOORD 0x00000100 22122d756322SRob Clark #define A6XX_GRAS_CNTL_WCOORD 0x00000200 22132d756322SRob Clark 22142d756322SRob Clark #define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x00008006 22152d756322SRob Clark #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff 22162d756322SRob Clark #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0 22172d756322SRob Clark static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val) 22182d756322SRob Clark { 22192d756322SRob Clark return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK; 22202d756322SRob Clark } 22212d756322SRob Clark #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x000ffc00 22222d756322SRob Clark #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10 22232d756322SRob Clark static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) 22242d756322SRob Clark { 22252d756322SRob Clark return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK; 22262d756322SRob Clark } 22272d756322SRob Clark 22282d756322SRob Clark #define REG_A6XX_GRAS_CL_VPORT_XOFFSET_0 0x00008010 22292d756322SRob Clark #define A6XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff 22302d756322SRob Clark #define A6XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0 22312d756322SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET_0(float val) 22322d756322SRob Clark { 22332d756322SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET_0__MASK; 22342d756322SRob Clark } 22352d756322SRob Clark 22362d756322SRob Clark #define REG_A6XX_GRAS_CL_VPORT_XSCALE_0 0x00008011 22372d756322SRob Clark #define A6XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff 22382d756322SRob Clark #define A6XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0 22392d756322SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE_0(float val) 22402d756322SRob Clark { 22412d756322SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE_0__MASK; 22422d756322SRob Clark } 22432d756322SRob Clark 22442d756322SRob Clark #define REG_A6XX_GRAS_CL_VPORT_YOFFSET_0 0x00008012 22452d756322SRob Clark #define A6XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff 22462d756322SRob Clark #define A6XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0 22472d756322SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET_0(float val) 22482d756322SRob Clark { 22492d756322SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET_0__MASK; 22502d756322SRob Clark } 22512d756322SRob Clark 22522d756322SRob Clark #define REG_A6XX_GRAS_CL_VPORT_YSCALE_0 0x00008013 22532d756322SRob Clark #define A6XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff 22542d756322SRob Clark #define A6XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0 22552d756322SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE_0(float val) 22562d756322SRob Clark { 22572d756322SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE_0__MASK; 22582d756322SRob Clark } 22592d756322SRob Clark 22602d756322SRob Clark #define REG_A6XX_GRAS_CL_VPORT_ZOFFSET_0 0x00008014 22612d756322SRob Clark #define A6XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff 22622d756322SRob Clark #define A6XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0 22632d756322SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET_0(float val) 22642d756322SRob Clark { 22652d756322SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET_0__MASK; 22662d756322SRob Clark } 22672d756322SRob Clark 22682d756322SRob Clark #define REG_A6XX_GRAS_CL_VPORT_ZSCALE_0 0x00008015 22692d756322SRob Clark #define A6XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff 22702d756322SRob Clark #define A6XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0 22712d756322SRob Clark static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE_0(float val) 22722d756322SRob Clark { 22732d756322SRob Clark return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE_0__MASK; 22742d756322SRob Clark } 22752d756322SRob Clark 22762d756322SRob Clark #define REG_A6XX_GRAS_SU_CNTL 0x00008090 22772d756322SRob Clark #define A6XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001 22782d756322SRob Clark #define A6XX_GRAS_SU_CNTL_CULL_BACK 0x00000002 22792d756322SRob Clark #define A6XX_GRAS_SU_CNTL_FRONT_CW 0x00000004 22802d756322SRob Clark #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8 22812d756322SRob Clark #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3 22822d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) 22832d756322SRob Clark { 22842d756322SRob Clark return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK; 22852d756322SRob Clark } 22862d756322SRob Clark #define A6XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800 22872d756322SRob Clark #define A6XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000 22882d756322SRob Clark 22892d756322SRob Clark #define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091 22902d756322SRob Clark #define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 22912d756322SRob Clark #define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 22922d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val) 22932d756322SRob Clark { 22942d756322SRob Clark return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 22952d756322SRob Clark } 22962d756322SRob Clark #define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 22972d756322SRob Clark #define A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 22982d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MAX(float val) 22992d756322SRob Clark { 23002d756322SRob Clark return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 23012d756322SRob Clark } 23022d756322SRob Clark 23032d756322SRob Clark #define REG_A6XX_GRAS_SU_POINT_SIZE 0x00008092 23042d756322SRob Clark #define A6XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff 23052d756322SRob Clark #define A6XX_GRAS_SU_POINT_SIZE__SHIFT 0 23062d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val) 23072d756322SRob Clark { 23082d756322SRob Clark return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK; 23092d756322SRob Clark } 23102d756322SRob Clark 23112d756322SRob Clark #define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE 0x00008095 23122d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff 23132d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 23142d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val) 23152d756322SRob Clark { 23162d756322SRob Clark return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; 23172d756322SRob Clark } 23182d756322SRob Clark 23192d756322SRob Clark #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00008096 23202d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 23212d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 23222d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 23232d756322SRob Clark { 23242d756322SRob Clark return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 23252d756322SRob Clark } 23262d756322SRob Clark 23272d756322SRob Clark #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x00008097 23282d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff 23292d756322SRob Clark #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0 23302d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val) 23312d756322SRob Clark { 23322d756322SRob Clark return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK; 23332d756322SRob Clark } 23342d756322SRob Clark 23352d756322SRob Clark #define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO 0x00008098 23362d756322SRob Clark #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 23372d756322SRob Clark #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 23382d756322SRob Clark static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) 23392d756322SRob Clark { 23402d756322SRob Clark return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; 23412d756322SRob Clark } 23422d756322SRob Clark 23432d756322SRob Clark #define REG_A6XX_GRAS_UNKNOWN_8099 0x00008099 23442d756322SRob Clark 23452d756322SRob Clark #define REG_A6XX_GRAS_UNKNOWN_809B 0x0000809b 23462d756322SRob Clark 23472d756322SRob Clark #define REG_A6XX_GRAS_RAS_MSAA_CNTL 0x000080a2 23482d756322SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 23492d756322SRob Clark #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 23502d756322SRob Clark static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 23512d756322SRob Clark { 23522d756322SRob Clark return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK; 23532d756322SRob Clark } 23542d756322SRob Clark 23552d756322SRob Clark #define REG_A6XX_GRAS_DEST_MSAA_CNTL 0x000080a3 23562d756322SRob Clark #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 23572d756322SRob Clark #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 23582d756322SRob Clark static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 23592d756322SRob Clark { 23602d756322SRob Clark return ((val) << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK; 23612d756322SRob Clark } 23622d756322SRob Clark #define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 23632d756322SRob Clark 23642d756322SRob Clark #define REG_A6XX_GRAS_UNKNOWN_80A4 0x000080a4 23652d756322SRob Clark 23662d756322SRob Clark #define REG_A6XX_GRAS_UNKNOWN_80A5 0x000080a5 23672d756322SRob Clark 23682d756322SRob Clark #define REG_A6XX_GRAS_UNKNOWN_80A6 0x000080a6 23692d756322SRob Clark 23702d756322SRob Clark #define REG_A6XX_GRAS_UNKNOWN_80AF 0x000080af 23712d756322SRob Clark 23722d756322SRob Clark #define REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0 0x000080b0 23732d756322SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000 23742d756322SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK 0x00007fff 23752d756322SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT 0 23762d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val) 23772d756322SRob Clark { 23782d756322SRob Clark return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK; 23792d756322SRob Clark } 23802d756322SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK 0x7fff0000 23812d756322SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT 16 23822d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val) 23832d756322SRob Clark { 23842d756322SRob Clark return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK; 23852d756322SRob Clark } 23862d756322SRob Clark 23872d756322SRob Clark #define REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0 0x000080b1 23882d756322SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000 23892d756322SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK 0x00007fff 23902d756322SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT 0 23912d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val) 23922d756322SRob Clark { 23932d756322SRob Clark return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK; 23942d756322SRob Clark } 23952d756322SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK 0x7fff0000 23962d756322SRob Clark #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT 16 23972d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val) 23982d756322SRob Clark { 23992d756322SRob Clark return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK; 24002d756322SRob Clark } 24012d756322SRob Clark 24022d756322SRob Clark #define REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0 0x000080d0 24032d756322SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000 24042d756322SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK 0x00007fff 24052d756322SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT 0 24062d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val) 24072d756322SRob Clark { 24082d756322SRob Clark return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK; 24092d756322SRob Clark } 24102d756322SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK 0x7fff0000 24112d756322SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT 16 24122d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val) 24132d756322SRob Clark { 24142d756322SRob Clark return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK; 24152d756322SRob Clark } 24162d756322SRob Clark 24172d756322SRob Clark #define REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0 0x000080d1 24182d756322SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000 24192d756322SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK 0x00007fff 24202d756322SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT 0 24212d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val) 24222d756322SRob Clark { 24232d756322SRob Clark return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK; 24242d756322SRob Clark } 24252d756322SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK 0x7fff0000 24262d756322SRob Clark #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT 16 24272d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val) 24282d756322SRob Clark { 24292d756322SRob Clark return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK; 24302d756322SRob Clark } 24312d756322SRob Clark 24322d756322SRob Clark #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL 0x000080f0 24332d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 24342d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 24352d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 24362d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 24372d756322SRob Clark { 24382d756322SRob Clark return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 24392d756322SRob Clark } 24402d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 24412d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 24422d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 24432d756322SRob Clark { 24442d756322SRob Clark return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 24452d756322SRob Clark } 24462d756322SRob Clark 24472d756322SRob Clark #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR 0x000080f1 24482d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 24492d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 24502d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 24512d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 24522d756322SRob Clark { 24532d756322SRob Clark return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 24542d756322SRob Clark } 24552d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 24562d756322SRob Clark #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 24572d756322SRob Clark static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 24582d756322SRob Clark { 24592d756322SRob Clark return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 24602d756322SRob Clark } 24612d756322SRob Clark 24622d756322SRob Clark #define REG_A6XX_GRAS_LRZ_CNTL 0x00008100 24632d756322SRob Clark #define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001 24642d756322SRob Clark #define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002 24652d756322SRob Clark #define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004 24662d756322SRob Clark 24672d756322SRob Clark #define REG_A6XX_GRAS_2D_BLIT_INFO 0x00008102 24682d756322SRob Clark #define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK 0x000000ff 24692d756322SRob Clark #define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT 0 24702d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) 24712d756322SRob Clark { 24722d756322SRob Clark return ((val) << A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK; 24732d756322SRob Clark } 24742d756322SRob Clark 24752d756322SRob Clark #define REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO 0x00008103 24762d756322SRob Clark 24772d756322SRob Clark #define REG_A6XX_GRAS_LRZ_BUFFER_BASE_HI 0x00008104 24782d756322SRob Clark 24792d756322SRob Clark #define REG_A6XX_GRAS_LRZ_BUFFER_PITCH 0x00008105 24802d756322SRob Clark #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK 0x000007ff 24812d756322SRob Clark #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT 0 24822d756322SRob Clark static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val) 24832d756322SRob Clark { 24842d756322SRob Clark return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK; 24852d756322SRob Clark } 24862d756322SRob Clark #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK 0x003ff800 24872d756322SRob Clark #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 24882d756322SRob Clark static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 24892d756322SRob Clark { 24902d756322SRob Clark return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK; 24912d756322SRob Clark } 24922d756322SRob Clark 24932d756322SRob Clark #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x00008106 24942d756322SRob Clark 24952d756322SRob Clark #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x00008107 24962d756322SRob Clark 24972d756322SRob Clark #define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400 24982d756322SRob Clark 24992d756322SRob Clark #define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401 25002d756322SRob Clark #define A6XX_GRAS_2D_SRC_TL_X_X__MASK 0x00ffff00 25012d756322SRob Clark #define A6XX_GRAS_2D_SRC_TL_X_X__SHIFT 8 25022d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_SRC_TL_X_X(uint32_t val) 25032d756322SRob Clark { 25042d756322SRob Clark return ((val) << A6XX_GRAS_2D_SRC_TL_X_X__SHIFT) & A6XX_GRAS_2D_SRC_TL_X_X__MASK; 25052d756322SRob Clark } 25062d756322SRob Clark 25072d756322SRob Clark #define REG_A6XX_GRAS_2D_SRC_BR_X 0x00008402 25082d756322SRob Clark #define A6XX_GRAS_2D_SRC_BR_X_X__MASK 0x00ffff00 25092d756322SRob Clark #define A6XX_GRAS_2D_SRC_BR_X_X__SHIFT 8 25102d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_SRC_BR_X_X(uint32_t val) 25112d756322SRob Clark { 25122d756322SRob Clark return ((val) << A6XX_GRAS_2D_SRC_BR_X_X__SHIFT) & A6XX_GRAS_2D_SRC_BR_X_X__MASK; 25132d756322SRob Clark } 25142d756322SRob Clark 25152d756322SRob Clark #define REG_A6XX_GRAS_2D_SRC_TL_Y 0x00008403 25162d756322SRob Clark #define A6XX_GRAS_2D_SRC_TL_Y_Y__MASK 0x00ffff00 25172d756322SRob Clark #define A6XX_GRAS_2D_SRC_TL_Y_Y__SHIFT 8 25182d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_SRC_TL_Y_Y(uint32_t val) 25192d756322SRob Clark { 25202d756322SRob Clark return ((val) << A6XX_GRAS_2D_SRC_TL_Y_Y__SHIFT) & A6XX_GRAS_2D_SRC_TL_Y_Y__MASK; 25212d756322SRob Clark } 25222d756322SRob Clark 25232d756322SRob Clark #define REG_A6XX_GRAS_2D_SRC_BR_Y 0x00008404 25242d756322SRob Clark #define A6XX_GRAS_2D_SRC_BR_Y_Y__MASK 0x00ffff00 25252d756322SRob Clark #define A6XX_GRAS_2D_SRC_BR_Y_Y__SHIFT 8 25262d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_SRC_BR_Y_Y(uint32_t val) 25272d756322SRob Clark { 25282d756322SRob Clark return ((val) << A6XX_GRAS_2D_SRC_BR_Y_Y__SHIFT) & A6XX_GRAS_2D_SRC_BR_Y_Y__MASK; 25292d756322SRob Clark } 25302d756322SRob Clark 25312d756322SRob Clark #define REG_A6XX_GRAS_2D_DST_TL 0x00008405 25322d756322SRob Clark #define A6XX_GRAS_2D_DST_TL_WINDOW_OFFSET_DISABLE 0x80000000 25332d756322SRob Clark #define A6XX_GRAS_2D_DST_TL_X__MASK 0x00007fff 25342d756322SRob Clark #define A6XX_GRAS_2D_DST_TL_X__SHIFT 0 25352d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val) 25362d756322SRob Clark { 25372d756322SRob Clark return ((val) << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK; 25382d756322SRob Clark } 25392d756322SRob Clark #define A6XX_GRAS_2D_DST_TL_Y__MASK 0x7fff0000 25402d756322SRob Clark #define A6XX_GRAS_2D_DST_TL_Y__SHIFT 16 25412d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val) 25422d756322SRob Clark { 25432d756322SRob Clark return ((val) << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK; 25442d756322SRob Clark } 25452d756322SRob Clark 25462d756322SRob Clark #define REG_A6XX_GRAS_2D_DST_BR 0x00008406 25472d756322SRob Clark #define A6XX_GRAS_2D_DST_BR_WINDOW_OFFSET_DISABLE 0x80000000 25482d756322SRob Clark #define A6XX_GRAS_2D_DST_BR_X__MASK 0x00007fff 25492d756322SRob Clark #define A6XX_GRAS_2D_DST_BR_X__SHIFT 0 25502d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val) 25512d756322SRob Clark { 25522d756322SRob Clark return ((val) << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK; 25532d756322SRob Clark } 25542d756322SRob Clark #define A6XX_GRAS_2D_DST_BR_Y__MASK 0x7fff0000 25552d756322SRob Clark #define A6XX_GRAS_2D_DST_BR_Y__SHIFT 16 25562d756322SRob Clark static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val) 25572d756322SRob Clark { 25582d756322SRob Clark return ((val) << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK; 25592d756322SRob Clark } 25602d756322SRob Clark 25612d756322SRob Clark #define REG_A6XX_GRAS_RESOLVE_CNTL_1 0x0000840a 25622d756322SRob Clark #define A6XX_GRAS_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE 0x80000000 25632d756322SRob Clark #define A6XX_GRAS_RESOLVE_CNTL_1_X__MASK 0x00007fff 25642d756322SRob Clark #define A6XX_GRAS_RESOLVE_CNTL_1_X__SHIFT 0 25652d756322SRob Clark static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_1_X(uint32_t val) 25662d756322SRob Clark { 25672d756322SRob Clark return ((val) << A6XX_GRAS_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_1_X__MASK; 25682d756322SRob Clark } 25692d756322SRob Clark #define A6XX_GRAS_RESOLVE_CNTL_1_Y__MASK 0x7fff0000 25702d756322SRob Clark #define A6XX_GRAS_RESOLVE_CNTL_1_Y__SHIFT 16 25712d756322SRob Clark static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_1_Y(uint32_t val) 25722d756322SRob Clark { 25732d756322SRob Clark return ((val) << A6XX_GRAS_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_1_Y__MASK; 25742d756322SRob Clark } 25752d756322SRob Clark 25762d756322SRob Clark #define REG_A6XX_GRAS_RESOLVE_CNTL_2 0x0000840b 25772d756322SRob Clark #define A6XX_GRAS_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE 0x80000000 25782d756322SRob Clark #define A6XX_GRAS_RESOLVE_CNTL_2_X__MASK 0x00007fff 25792d756322SRob Clark #define A6XX_GRAS_RESOLVE_CNTL_2_X__SHIFT 0 25802d756322SRob Clark static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_2_X(uint32_t val) 25812d756322SRob Clark { 25822d756322SRob Clark return ((val) << A6XX_GRAS_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_2_X__MASK; 25832d756322SRob Clark } 25842d756322SRob Clark #define A6XX_GRAS_RESOLVE_CNTL_2_Y__MASK 0x7fff0000 25852d756322SRob Clark #define A6XX_GRAS_RESOLVE_CNTL_2_Y__SHIFT 16 25862d756322SRob Clark static inline uint32_t A6XX_GRAS_RESOLVE_CNTL_2_Y(uint32_t val) 25872d756322SRob Clark { 25882d756322SRob Clark return ((val) << A6XX_GRAS_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_RESOLVE_CNTL_2_Y__MASK; 25892d756322SRob Clark } 25902d756322SRob Clark 25912d756322SRob Clark #define REG_A6XX_GRAS_UNKNOWN_8600 0x00008600 25922d756322SRob Clark 25932d756322SRob Clark #define REG_A6XX_RB_RAS_MSAA_CNTL 0x00008802 25942d756322SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 25952d756322SRob Clark #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 25962d756322SRob Clark static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 25972d756322SRob Clark { 25982d756322SRob Clark return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK; 25992d756322SRob Clark } 26002d756322SRob Clark 26012d756322SRob Clark #define REG_A6XX_RB_DEST_MSAA_CNTL 0x00008803 26022d756322SRob Clark #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 26032d756322SRob Clark #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 26042d756322SRob Clark static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 26052d756322SRob Clark { 26062d756322SRob Clark return ((val) << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK; 26072d756322SRob Clark } 26082d756322SRob Clark #define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 26092d756322SRob Clark 26102d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8804 0x00008804 26112d756322SRob Clark 26122d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8805 0x00008805 26132d756322SRob Clark 26142d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8806 0x00008806 26152d756322SRob Clark 26162d756322SRob Clark #define REG_A6XX_RB_RENDER_CONTROL0 0x00008809 26172d756322SRob Clark #define A6XX_RB_RENDER_CONTROL0_VARYING 0x00000001 26182d756322SRob Clark #define A6XX_RB_RENDER_CONTROL0_XCOORD 0x00000040 26192d756322SRob Clark #define A6XX_RB_RENDER_CONTROL0_YCOORD 0x00000080 26202d756322SRob Clark #define A6XX_RB_RENDER_CONTROL0_ZCOORD 0x00000100 26212d756322SRob Clark #define A6XX_RB_RENDER_CONTROL0_WCOORD 0x00000200 26222d756322SRob Clark #define A6XX_RB_RENDER_CONTROL0_UNK10 0x00000400 26232d756322SRob Clark 26242d756322SRob Clark #define REG_A6XX_RB_RENDER_CONTROL1 0x0000880a 26252d756322SRob Clark #define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001 26262d756322SRob Clark #define A6XX_RB_RENDER_CONTROL1_FACENESS 0x00000002 26272d756322SRob Clark #define A6XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000008 26282d756322SRob Clark 26292d756322SRob Clark #define REG_A6XX_RB_FS_OUTPUT_CNTL0 0x0000880b 26302d756322SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z 0x00000002 26312d756322SRob Clark 26322d756322SRob Clark #define REG_A6XX_RB_FS_OUTPUT_CNTL1 0x0000880c 26332d756322SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f 26342d756322SRob Clark #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT 0 26352d756322SRob Clark static inline uint32_t A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val) 26362d756322SRob Clark { 26372d756322SRob Clark return ((val) << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK; 26382d756322SRob Clark } 26392d756322SRob Clark 26402d756322SRob Clark #define REG_A6XX_RB_RENDER_COMPONENTS 0x0000880d 26412d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f 26422d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0 26432d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) 26442d756322SRob Clark { 26452d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK; 26462d756322SRob Clark } 26472d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0 26482d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4 26492d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) 26502d756322SRob Clark { 26512d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK; 26522d756322SRob Clark } 26532d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00 26542d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8 26552d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) 26562d756322SRob Clark { 26572d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK; 26582d756322SRob Clark } 26592d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000 26602d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12 26612d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) 26622d756322SRob Clark { 26632d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK; 26642d756322SRob Clark } 26652d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000 26662d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16 26672d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) 26682d756322SRob Clark { 26692d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK; 26702d756322SRob Clark } 26712d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000 26722d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20 26732d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) 26742d756322SRob Clark { 26752d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK; 26762d756322SRob Clark } 26772d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000 26782d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24 26792d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) 26802d756322SRob Clark { 26812d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK; 26822d756322SRob Clark } 26832d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000 26842d756322SRob Clark #define A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28 26852d756322SRob Clark static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) 26862d756322SRob Clark { 26872d756322SRob Clark return ((val) << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK; 26882d756322SRob Clark } 26892d756322SRob Clark 26902d756322SRob Clark #define REG_A6XX_RB_DITHER_CNTL 0x0000880e 26912d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK 0x00000003 26922d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT 0 26932d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val) 26942d756322SRob Clark { 26952d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK; 26962d756322SRob Clark } 26972d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK 0x0000000c 26982d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT 2 26992d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val) 27002d756322SRob Clark { 27012d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK; 27022d756322SRob Clark } 27032d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK 0x00000030 27042d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT 4 27052d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val) 27062d756322SRob Clark { 27072d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK; 27082d756322SRob Clark } 27092d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK 0x000000c0 27102d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT 6 27112d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val) 27122d756322SRob Clark { 27132d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK; 27142d756322SRob Clark } 27152d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK 0x00000300 27162d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT 8 27172d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val) 27182d756322SRob Clark { 27192d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK; 27202d756322SRob Clark } 27212d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK 0x00000c00 27222d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT 10 27232d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val) 27242d756322SRob Clark { 27252d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK; 27262d756322SRob Clark } 27272d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK 0x00001000 27282d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT 12 27292d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val) 27302d756322SRob Clark { 27312d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK; 27322d756322SRob Clark } 27332d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK 0x0000c000 27342d756322SRob Clark #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT 14 27352d756322SRob Clark static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val) 27362d756322SRob Clark { 27372d756322SRob Clark return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK; 27382d756322SRob Clark } 27392d756322SRob Clark 27402d756322SRob Clark #define REG_A6XX_RB_SRGB_CNTL 0x0000880f 27412d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT0 0x00000001 27422d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT1 0x00000002 27432d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT2 0x00000004 27442d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT3 0x00000008 27452d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT4 0x00000010 27462d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT5 0x00000020 27472d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT6 0x00000040 27482d756322SRob Clark #define A6XX_RB_SRGB_CNTL_SRGB_MRT7 0x00000080 27492d756322SRob Clark 27502d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8818 0x00008818 27512d756322SRob Clark 27522d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8819 0x00008819 27532d756322SRob Clark 27542d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881A 0x0000881a 27552d756322SRob Clark 27562d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881B 0x0000881b 27572d756322SRob Clark 27582d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881C 0x0000881c 27592d756322SRob Clark 27602d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881D 0x0000881d 27612d756322SRob Clark 27622d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_881E 0x0000881e 27632d756322SRob Clark 27642d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; } 27652d756322SRob Clark 27662d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; } 27672d756322SRob Clark #define A6XX_RB_MRT_CONTROL_BLEND 0x00000001 27682d756322SRob Clark #define A6XX_RB_MRT_CONTROL_BLEND2 0x00000002 27692d756322SRob Clark #define A6XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004 27702d756322SRob Clark #define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078 27712d756322SRob Clark #define A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3 27722d756322SRob Clark static inline uint32_t A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) 27732d756322SRob Clark { 27742d756322SRob Clark return ((val) << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK; 27752d756322SRob Clark } 27762d756322SRob Clark #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780 27772d756322SRob Clark #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7 27782d756322SRob Clark static inline uint32_t A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 27792d756322SRob Clark { 27802d756322SRob Clark return ((val) << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 27812d756322SRob Clark } 27822d756322SRob Clark 27832d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; } 27842d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 27852d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 27862d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 27872d756322SRob Clark { 27882d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 27892d756322SRob Clark } 27902d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 27912d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 27922d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 27932d756322SRob Clark { 27942d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 27952d756322SRob Clark } 27962d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 27972d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 27982d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 27992d756322SRob Clark { 28002d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 28012d756322SRob Clark } 28022d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 28032d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 28042d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 28052d756322SRob Clark { 28062d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 28072d756322SRob Clark } 28082d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 28092d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 28102d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 28112d756322SRob Clark { 28122d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 28132d756322SRob Clark } 28142d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 28152d756322SRob Clark #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 28162d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 28172d756322SRob Clark { 28182d756322SRob Clark return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 28192d756322SRob Clark } 28202d756322SRob Clark 28212d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; } 28222d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff 28232d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 28242d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) 28252d756322SRob Clark { 28262d756322SRob Clark return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 28272d756322SRob Clark } 28282d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300 28292d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8 28302d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val) 28312d756322SRob Clark { 28322d756322SRob Clark return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 28332d756322SRob Clark } 28342d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000 28352d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13 28362d756322SRob Clark static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 28372d756322SRob Clark { 28382d756322SRob Clark return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 28392d756322SRob Clark } 28402d756322SRob Clark #define A6XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00008000 28412d756322SRob Clark 28422d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; } 28432d756322SRob Clark #define A6XX_RB_MRT_PITCH__MASK 0xffffffff 28442d756322SRob Clark #define A6XX_RB_MRT_PITCH__SHIFT 0 28452d756322SRob Clark static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val) 28462d756322SRob Clark { 28472d756322SRob Clark return ((val >> 6) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK; 28482d756322SRob Clark } 28492d756322SRob Clark 28502d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; } 28512d756322SRob Clark #define A6XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff 28522d756322SRob Clark #define A6XX_RB_MRT_ARRAY_PITCH__SHIFT 0 28532d756322SRob Clark static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val) 28542d756322SRob Clark { 28552d756322SRob Clark return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK; 28562d756322SRob Clark } 28572d756322SRob Clark 28582d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x00008825 + 0x8*i0; } 28592d756322SRob Clark 28602d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x00008826 + 0x8*i0; } 28612d756322SRob Clark 28622d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; } 28632d756322SRob Clark 28642d756322SRob Clark #define REG_A6XX_RB_BLEND_RED_F32 0x00008860 28652d756322SRob Clark #define A6XX_RB_BLEND_RED_F32__MASK 0xffffffff 28662d756322SRob Clark #define A6XX_RB_BLEND_RED_F32__SHIFT 0 28672d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_RED_F32(float val) 28682d756322SRob Clark { 28692d756322SRob Clark return ((fui(val)) << A6XX_RB_BLEND_RED_F32__SHIFT) & A6XX_RB_BLEND_RED_F32__MASK; 28702d756322SRob Clark } 28712d756322SRob Clark 28722d756322SRob Clark #define REG_A6XX_RB_BLEND_GREEN_F32 0x00008861 28732d756322SRob Clark #define A6XX_RB_BLEND_GREEN_F32__MASK 0xffffffff 28742d756322SRob Clark #define A6XX_RB_BLEND_GREEN_F32__SHIFT 0 28752d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_GREEN_F32(float val) 28762d756322SRob Clark { 28772d756322SRob Clark return ((fui(val)) << A6XX_RB_BLEND_GREEN_F32__SHIFT) & A6XX_RB_BLEND_GREEN_F32__MASK; 28782d756322SRob Clark } 28792d756322SRob Clark 28802d756322SRob Clark #define REG_A6XX_RB_BLEND_BLUE_F32 0x00008862 28812d756322SRob Clark #define A6XX_RB_BLEND_BLUE_F32__MASK 0xffffffff 28822d756322SRob Clark #define A6XX_RB_BLEND_BLUE_F32__SHIFT 0 28832d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_BLUE_F32(float val) 28842d756322SRob Clark { 28852d756322SRob Clark return ((fui(val)) << A6XX_RB_BLEND_BLUE_F32__SHIFT) & A6XX_RB_BLEND_BLUE_F32__MASK; 28862d756322SRob Clark } 28872d756322SRob Clark 28882d756322SRob Clark #define REG_A6XX_RB_BLEND_ALPHA_F32 0x00008863 28892d756322SRob Clark #define A6XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff 28902d756322SRob Clark #define A6XX_RB_BLEND_ALPHA_F32__SHIFT 0 28912d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_ALPHA_F32(float val) 28922d756322SRob Clark { 28932d756322SRob Clark return ((fui(val)) << A6XX_RB_BLEND_ALPHA_F32__SHIFT) & A6XX_RB_BLEND_ALPHA_F32__MASK; 28942d756322SRob Clark } 28952d756322SRob Clark 28962d756322SRob Clark #define REG_A6XX_RB_ALPHA_CONTROL 0x00008864 28972d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff 28982d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 28992d756322SRob Clark static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) 29002d756322SRob Clark { 29012d756322SRob Clark return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; 29022d756322SRob Clark } 29032d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 29042d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 29052d756322SRob Clark #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 29062d756322SRob Clark static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 29072d756322SRob Clark { 29082d756322SRob Clark return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; 29092d756322SRob Clark } 29102d756322SRob Clark 29112d756322SRob Clark #define REG_A6XX_RB_BLEND_CNTL 0x00008865 29122d756322SRob Clark #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff 29132d756322SRob Clark #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 29142d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val) 29152d756322SRob Clark { 29162d756322SRob Clark return ((val) << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK; 29172d756322SRob Clark } 29182d756322SRob Clark #define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100 29192d756322SRob Clark #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000 29202d756322SRob Clark #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16 29212d756322SRob Clark static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val) 29222d756322SRob Clark { 29232d756322SRob Clark return ((val) << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK; 29242d756322SRob Clark } 29252d756322SRob Clark 29262d756322SRob Clark #define REG_A6XX_RB_DEPTH_CNTL 0x00008871 29272d756322SRob Clark #define A6XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001 29282d756322SRob Clark #define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002 29292d756322SRob Clark #define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c 29302d756322SRob Clark #define A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2 29312d756322SRob Clark static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) 29322d756322SRob Clark { 29332d756322SRob Clark return ((val) << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK; 29342d756322SRob Clark } 29352d756322SRob Clark #define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040 29362d756322SRob Clark 29372d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_INFO 0x00008872 29382d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 29392d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 29402d756322SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) 29412d756322SRob Clark { 29422d756322SRob Clark return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; 29432d756322SRob Clark } 29442d756322SRob Clark 29452d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_PITCH 0x00008873 29462d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_PITCH__MASK 0xffffffff 29472d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0 29482d756322SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) 29492d756322SRob Clark { 29502d756322SRob Clark return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK; 29512d756322SRob Clark } 29522d756322SRob Clark 29532d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x00008874 29542d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0xffffffff 29552d756322SRob Clark #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0 29562d756322SRob Clark static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) 29572d756322SRob Clark { 29582d756322SRob Clark return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; 29592d756322SRob Clark } 29602d756322SRob Clark 29612d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_BASE_LO 0x00008875 29622d756322SRob Clark 29632d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_BASE_HI 0x00008876 29642d756322SRob Clark 29652d756322SRob Clark #define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM 0x00008877 29662d756322SRob Clark 29672d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8878 0x00008878 29682d756322SRob Clark 29692d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8879 0x00008879 29702d756322SRob Clark 29712d756322SRob Clark #define REG_A6XX_RB_STENCIL_CONTROL 0x00008880 29722d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 29732d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 29742d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 29752d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 29762d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 29772d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 29782d756322SRob Clark { 29792d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC__MASK; 29802d756322SRob Clark } 29812d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 29822d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 29832d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 29842d756322SRob Clark { 29852d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL__MASK; 29862d756322SRob Clark } 29872d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 29882d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 29892d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 29902d756322SRob Clark { 29912d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK; 29922d756322SRob Clark } 29932d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 29942d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 29952d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 29962d756322SRob Clark { 29972d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 29982d756322SRob Clark } 29992d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 30002d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 30012d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 30022d756322SRob Clark { 30032d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 30042d756322SRob Clark } 30052d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 30062d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 30072d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 30082d756322SRob Clark { 30092d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 30102d756322SRob Clark } 30112d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 30122d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 30132d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 30142d756322SRob Clark { 30152d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 30162d756322SRob Clark } 30172d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 30182d756322SRob Clark #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 30192d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 30202d756322SRob Clark { 30212d756322SRob Clark return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 30222d756322SRob Clark } 30232d756322SRob Clark 30242d756322SRob Clark #define REG_A6XX_RB_STENCIL_INFO 0x00008881 30252d756322SRob Clark #define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 30262d756322SRob Clark 30272d756322SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_PITCH 0x00008882 30282d756322SRob Clark #define A6XX_RB_STENCIL_BUFFER_PITCH__MASK 0xffffffff 30292d756322SRob Clark #define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT 0 30302d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val) 30312d756322SRob Clark { 30322d756322SRob Clark return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK; 30332d756322SRob Clark } 30342d756322SRob Clark 30352d756322SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH 0x00008883 30362d756322SRob Clark #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK 0xffffffff 30372d756322SRob Clark #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT 0 30382d756322SRob Clark static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val) 30392d756322SRob Clark { 30402d756322SRob Clark return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK; 30412d756322SRob Clark } 30422d756322SRob Clark 30432d756322SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_BASE_LO 0x00008884 30442d756322SRob Clark 30452d756322SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_BASE_HI 0x00008885 30462d756322SRob Clark 30472d756322SRob Clark #define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM 0x00008886 30482d756322SRob Clark 30492d756322SRob Clark #define REG_A6XX_RB_STENCILREF 0x00008887 30502d756322SRob Clark #define A6XX_RB_STENCILREF_REF__MASK 0x000000ff 30512d756322SRob Clark #define A6XX_RB_STENCILREF_REF__SHIFT 0 30522d756322SRob Clark static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val) 30532d756322SRob Clark { 30542d756322SRob Clark return ((val) << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK; 30552d756322SRob Clark } 30562d756322SRob Clark 30572d756322SRob Clark #define REG_A6XX_RB_STENCILMASK 0x00008888 30582d756322SRob Clark #define A6XX_RB_STENCILMASK_MASK__MASK 0x000000ff 30592d756322SRob Clark #define A6XX_RB_STENCILMASK_MASK__SHIFT 0 30602d756322SRob Clark static inline uint32_t A6XX_RB_STENCILMASK_MASK(uint32_t val) 30612d756322SRob Clark { 30622d756322SRob Clark return ((val) << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK; 30632d756322SRob Clark } 30642d756322SRob Clark 30652d756322SRob Clark #define REG_A6XX_RB_STENCILWRMASK 0x00008889 30662d756322SRob Clark #define A6XX_RB_STENCILWRMASK_WRMASK__MASK 0x000000ff 30672d756322SRob Clark #define A6XX_RB_STENCILWRMASK_WRMASK__SHIFT 0 30682d756322SRob Clark static inline uint32_t A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val) 30692d756322SRob Clark { 30702d756322SRob Clark return ((val) << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK; 30712d756322SRob Clark } 30722d756322SRob Clark 30732d756322SRob Clark #define REG_A6XX_RB_WINDOW_OFFSET 0x00008890 30742d756322SRob Clark #define A6XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 30752d756322SRob Clark #define A6XX_RB_WINDOW_OFFSET_X__MASK 0x00007fff 30762d756322SRob Clark #define A6XX_RB_WINDOW_OFFSET_X__SHIFT 0 30772d756322SRob Clark static inline uint32_t A6XX_RB_WINDOW_OFFSET_X(uint32_t val) 30782d756322SRob Clark { 30792d756322SRob Clark return ((val) << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK; 30802d756322SRob Clark } 30812d756322SRob Clark #define A6XX_RB_WINDOW_OFFSET_Y__MASK 0x7fff0000 30822d756322SRob Clark #define A6XX_RB_WINDOW_OFFSET_Y__SHIFT 16 30832d756322SRob Clark static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val) 30842d756322SRob Clark { 30852d756322SRob Clark return ((val) << A6XX_RB_WINDOW_OFFSET_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET_Y__MASK; 30862d756322SRob Clark } 30872d756322SRob Clark 30882d756322SRob Clark #define REG_A6XX_RB_SAMPLE_COUNT_CONTROL 0x00008891 30892d756322SRob Clark #define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 30902d756322SRob Clark 30912d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_88D0 0x000088d0 30922d756322SRob Clark 30932d756322SRob Clark #define REG_A6XX_RB_BLIT_SCISSOR_TL 0x000088d1 30942d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 30952d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_X__MASK 0x00007fff 30962d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT 0 30972d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val) 30982d756322SRob Clark { 30992d756322SRob Clark return ((val) << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK; 31002d756322SRob Clark } 31012d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK 0x7fff0000 31022d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT 16 31032d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val) 31042d756322SRob Clark { 31052d756322SRob Clark return ((val) << A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_Y__MASK; 31062d756322SRob Clark } 31072d756322SRob Clark 31082d756322SRob Clark #define REG_A6XX_RB_BLIT_SCISSOR_BR 0x000088d2 31092d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 31102d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_X__MASK 0x00007fff 31112d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT 0 31122d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val) 31132d756322SRob Clark { 31142d756322SRob Clark return ((val) << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK; 31152d756322SRob Clark } 31162d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK 0x7fff0000 31172d756322SRob Clark #define A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT 16 31182d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val) 31192d756322SRob Clark { 31202d756322SRob Clark return ((val) << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK; 31212d756322SRob Clark } 31222d756322SRob Clark 31232d756322SRob Clark #define REG_A6XX_RB_BLIT_BASE_GMEM 0x000088d6 31242d756322SRob Clark 31252d756322SRob Clark #define REG_A6XX_RB_BLIT_DST_INFO 0x000088d7 31262d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK 0x00000003 31272d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT 0 31282d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) 31292d756322SRob Clark { 31302d756322SRob Clark return ((val) << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK; 31312d756322SRob Clark } 31322d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_FLAGS 0x00000004 31332d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK 0x00007f80 31342d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT 7 31352d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) 31362d756322SRob Clark { 31372d756322SRob Clark return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK; 31382d756322SRob Clark } 31392d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK 0x00000060 31402d756322SRob Clark #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT 5 31412d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) 31422d756322SRob Clark { 31432d756322SRob Clark return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK; 31442d756322SRob Clark } 31452d756322SRob Clark 31462d756322SRob Clark #define REG_A6XX_RB_BLIT_DST_LO 0x000088d8 31472d756322SRob Clark 31482d756322SRob Clark #define REG_A6XX_RB_BLIT_DST_HI 0x000088d9 31492d756322SRob Clark 31502d756322SRob Clark #define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da 31512d756322SRob Clark #define A6XX_RB_BLIT_DST_PITCH__MASK 0xffffffff 31522d756322SRob Clark #define A6XX_RB_BLIT_DST_PITCH__SHIFT 0 31532d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val) 31542d756322SRob Clark { 31552d756322SRob Clark return ((val >> 6) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK; 31562d756322SRob Clark } 31572d756322SRob Clark 31582d756322SRob Clark #define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH 0x000088db 31592d756322SRob Clark #define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0xffffffff 31602d756322SRob Clark #define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0 31612d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) 31622d756322SRob Clark { 31632d756322SRob Clark return ((val >> 6) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK; 31642d756322SRob Clark } 31652d756322SRob Clark 31662d756322SRob Clark #define REG_A6XX_RB_BLIT_FLAG_DST_LO 0x000088dc 31672d756322SRob Clark 31682d756322SRob Clark #define REG_A6XX_RB_BLIT_FLAG_DST_HI 0x000088dd 31692d756322SRob Clark 31702d756322SRob Clark #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 0x000088df 31712d756322SRob Clark 31722d756322SRob Clark #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1 0x000088e0 31732d756322SRob Clark 31742d756322SRob Clark #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2 0x000088e1 31752d756322SRob Clark 31762d756322SRob Clark #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3 0x000088e2 31772d756322SRob Clark 31782d756322SRob Clark #define REG_A6XX_RB_BLIT_INFO 0x000088e3 31792d756322SRob Clark #define A6XX_RB_BLIT_INFO_UNK0 0x00000001 31802d756322SRob Clark #define A6XX_RB_BLIT_INFO_FAST_CLEAR 0x00000002 31812d756322SRob Clark #define A6XX_RB_BLIT_INFO_INTEGER 0x00000004 31822d756322SRob Clark #define A6XX_RB_BLIT_INFO_UNK3 0x00000008 31832d756322SRob Clark #define A6XX_RB_BLIT_INFO_MASK__MASK 0x000000f0 31842d756322SRob Clark #define A6XX_RB_BLIT_INFO_MASK__SHIFT 4 31852d756322SRob Clark static inline uint32_t A6XX_RB_BLIT_INFO_MASK(uint32_t val) 31862d756322SRob Clark { 31872d756322SRob Clark return ((val) << A6XX_RB_BLIT_INFO_MASK__SHIFT) & A6XX_RB_BLIT_INFO_MASK__MASK; 31882d756322SRob Clark } 31892d756322SRob Clark 31902d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_88F0 0x000088f0 31912d756322SRob Clark 31922d756322SRob Clark #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x00008900 31932d756322SRob Clark 31942d756322SRob Clark #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x00008901 31952d756322SRob Clark 31962d756322SRob Clark #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x00008902 31972d756322SRob Clark 31982d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; } 31992d756322SRob Clark 32002d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x00008903 + 0x3*i0; } 32012d756322SRob Clark 32022d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x00008904 + 0x3*i0; } 32032d756322SRob Clark 32042d756322SRob Clark static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; } 32052d756322SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff 32062d756322SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 32072d756322SRob Clark static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val) 32082d756322SRob Clark { 32092d756322SRob Clark return ((val >> 5) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK; 32102d756322SRob Clark } 32112d756322SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x003ff800 32122d756322SRob Clark #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 32132d756322SRob Clark static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) 32142d756322SRob Clark { 32152d756322SRob Clark return ((val >> 5) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; 32162d756322SRob Clark } 32172d756322SRob Clark 32182d756322SRob Clark #define REG_A6XX_RB_SAMPLE_COUNT_ADDR_LO 0x00008927 32192d756322SRob Clark 32202d756322SRob Clark #define REG_A6XX_RB_SAMPLE_COUNT_ADDR_HI 0x00008928 32212d756322SRob Clark 32222d756322SRob Clark #define REG_A6XX_RB_2D_BLIT_CNTL 0x00008c00 32232d756322SRob Clark #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00 32242d756322SRob Clark #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8 32252d756322SRob Clark static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_color_fmt val) 32262d756322SRob Clark { 32272d756322SRob Clark return ((val) << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK; 32282d756322SRob Clark } 32292d756322SRob Clark 32302d756322SRob Clark #define REG_A6XX_RB_2D_DST_INFO 0x00008c17 32312d756322SRob Clark #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff 32322d756322SRob Clark #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0 32332d756322SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) 32342d756322SRob Clark { 32352d756322SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK; 32362d756322SRob Clark } 32372d756322SRob Clark #define A6XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300 32382d756322SRob Clark #define A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8 32392d756322SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) 32402d756322SRob Clark { 32412d756322SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_2D_DST_INFO_TILE_MODE__MASK; 32422d756322SRob Clark } 32432d756322SRob Clark #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00 32442d756322SRob Clark #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10 32452d756322SRob Clark static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) 32462d756322SRob Clark { 32472d756322SRob Clark return ((val) << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK; 32482d756322SRob Clark } 32492d756322SRob Clark #define A6XX_RB_2D_DST_INFO_FLAGS 0x00001000 32502d756322SRob Clark 32512d756322SRob Clark #define REG_A6XX_RB_2D_DST_LO 0x00008c18 32522d756322SRob Clark 32532d756322SRob Clark #define REG_A6XX_RB_2D_DST_HI 0x00008c19 32542d756322SRob Clark 32552d756322SRob Clark #define REG_A6XX_RB_2D_DST_SIZE 0x00008c1a 32562d756322SRob Clark #define A6XX_RB_2D_DST_SIZE_PITCH__MASK 0x0000ffff 32572d756322SRob Clark #define A6XX_RB_2D_DST_SIZE_PITCH__SHIFT 0 32582d756322SRob Clark static inline uint32_t A6XX_RB_2D_DST_SIZE_PITCH(uint32_t val) 32592d756322SRob Clark { 32602d756322SRob Clark return ((val >> 6) << A6XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A6XX_RB_2D_DST_SIZE_PITCH__MASK; 32612d756322SRob Clark } 32622d756322SRob Clark 32632d756322SRob Clark #define REG_A6XX_RB_2D_DST_FLAGS_LO 0x00008c20 32642d756322SRob Clark 32652d756322SRob Clark #define REG_A6XX_RB_2D_DST_FLAGS_HI 0x00008c21 32662d756322SRob Clark 32672d756322SRob Clark #define REG_A6XX_RB_2D_SRC_SOLID_C0 0x00008c2c 32682d756322SRob Clark 32692d756322SRob Clark #define REG_A6XX_RB_2D_SRC_SOLID_C1 0x00008c2d 32702d756322SRob Clark 32712d756322SRob Clark #define REG_A6XX_RB_2D_SRC_SOLID_C2 0x00008c2e 32722d756322SRob Clark 32732d756322SRob Clark #define REG_A6XX_RB_2D_SRC_SOLID_C3 0x00008c2f 32742d756322SRob Clark 32752d756322SRob Clark #define REG_A6XX_RB_UNKNOWN_8E01 0x00008e01 32762d756322SRob Clark 32772d756322SRob Clark #define REG_A6XX_RB_CCU_CNTL 0x00008e07 32782d756322SRob Clark 32792d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9101 0x00009101 32802d756322SRob Clark 32812d756322SRob Clark #define REG_A6XX_VPC_GS_SIV_CNTL 0x00009104 32822d756322SRob Clark 32832d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9108 0x00009108 32842d756322SRob Clark 32852d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; } 32862d756322SRob Clark 32872d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; } 32882d756322SRob Clark 32892d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; } 32902d756322SRob Clark 32912d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; } 32922d756322SRob Clark 32932d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9210 0x00009210 32942d756322SRob Clark 32952d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9211 0x00009211 32962d756322SRob Clark 32972d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; } 32982d756322SRob Clark 32992d756322SRob Clark static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; } 33002d756322SRob Clark 33012d756322SRob Clark #define REG_A6XX_VPC_SO_CNTL 0x00009216 33022d756322SRob Clark #define A6XX_VPC_SO_CNTL_ENABLE 0x00010000 33032d756322SRob Clark 33042d756322SRob Clark #define REG_A6XX_VPC_SO_PROG 0x00009217 33052d756322SRob Clark #define A6XX_VPC_SO_PROG_A_BUF__MASK 0x00000003 33062d756322SRob Clark #define A6XX_VPC_SO_PROG_A_BUF__SHIFT 0 33072d756322SRob Clark static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val) 33082d756322SRob Clark { 33092d756322SRob Clark return ((val) << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK; 33102d756322SRob Clark } 33112d756322SRob Clark #define A6XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc 33122d756322SRob Clark #define A6XX_VPC_SO_PROG_A_OFF__SHIFT 2 33132d756322SRob Clark static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val) 33142d756322SRob Clark { 33152d756322SRob Clark return ((val >> 2) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK; 33162d756322SRob Clark } 33172d756322SRob Clark #define A6XX_VPC_SO_PROG_A_EN 0x00000800 33182d756322SRob Clark #define A6XX_VPC_SO_PROG_B_BUF__MASK 0x00003000 33192d756322SRob Clark #define A6XX_VPC_SO_PROG_B_BUF__SHIFT 12 33202d756322SRob Clark static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val) 33212d756322SRob Clark { 33222d756322SRob Clark return ((val) << A6XX_VPC_SO_PROG_B_BUF__SHIFT) & A6XX_VPC_SO_PROG_B_BUF__MASK; 33232d756322SRob Clark } 33242d756322SRob Clark #define A6XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000 33252d756322SRob Clark #define A6XX_VPC_SO_PROG_B_OFF__SHIFT 14 33262d756322SRob Clark static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val) 33272d756322SRob Clark { 33282d756322SRob Clark return ((val >> 2) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK; 33292d756322SRob Clark } 33302d756322SRob Clark #define A6XX_VPC_SO_PROG_B_EN 0x00800000 33312d756322SRob Clark 33322d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; } 33332d756322SRob Clark 33342d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000921a + 0x7*i0; } 33352d756322SRob Clark 33362d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000921b + 0x7*i0; } 33372d756322SRob Clark 33382d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; } 33392d756322SRob Clark 33402d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000921d + 0x7*i0; } 33412d756322SRob Clark 33422d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; } 33432d756322SRob Clark 33442d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000921f + 0x7*i0; } 33452d756322SRob Clark 33462d756322SRob Clark static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x00009220 + 0x7*i0; } 33472d756322SRob Clark 33482d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9236 0x00009236 33492d756322SRob Clark 33502d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9300 0x00009300 33512d756322SRob Clark 33522d756322SRob Clark #define REG_A6XX_VPC_PACK 0x00009301 33532d756322SRob Clark #define A6XX_VPC_PACK_STRIDE_IN_VPC__MASK 0x000000ff 33542d756322SRob Clark #define A6XX_VPC_PACK_STRIDE_IN_VPC__SHIFT 0 33552d756322SRob Clark static inline uint32_t A6XX_VPC_PACK_STRIDE_IN_VPC(uint32_t val) 33562d756322SRob Clark { 33572d756322SRob Clark return ((val) << A6XX_VPC_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_PACK_STRIDE_IN_VPC__MASK; 33582d756322SRob Clark } 33592d756322SRob Clark #define A6XX_VPC_PACK_NUMNONPOSVAR__MASK 0x0000ff00 33602d756322SRob Clark #define A6XX_VPC_PACK_NUMNONPOSVAR__SHIFT 8 33612d756322SRob Clark static inline uint32_t A6XX_VPC_PACK_NUMNONPOSVAR(uint32_t val) 33622d756322SRob Clark { 33632d756322SRob Clark return ((val) << A6XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A6XX_VPC_PACK_NUMNONPOSVAR__MASK; 33642d756322SRob Clark } 33652d756322SRob Clark #define A6XX_VPC_PACK_PSIZELOC__MASK 0x00ff0000 33662d756322SRob Clark #define A6XX_VPC_PACK_PSIZELOC__SHIFT 16 33672d756322SRob Clark static inline uint32_t A6XX_VPC_PACK_PSIZELOC(uint32_t val) 33682d756322SRob Clark { 33692d756322SRob Clark return ((val) << A6XX_VPC_PACK_PSIZELOC__SHIFT) & A6XX_VPC_PACK_PSIZELOC__MASK; 33702d756322SRob Clark } 33712d756322SRob Clark 33722d756322SRob Clark #define REG_A6XX_VPC_CNTL_0 0x00009304 33732d756322SRob Clark #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK 0x000000ff 33742d756322SRob Clark #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT 0 33752d756322SRob Clark static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val) 33762d756322SRob Clark { 33772d756322SRob Clark return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK; 33782d756322SRob Clark } 33792d756322SRob Clark #define A6XX_VPC_CNTL_0_VARYING 0x00010000 33802d756322SRob Clark 33812d756322SRob Clark #define REG_A6XX_VPC_SO_BUF_CNTL 0x00009305 33822d756322SRob Clark #define A6XX_VPC_SO_BUF_CNTL_BUF0 0x00000001 33832d756322SRob Clark #define A6XX_VPC_SO_BUF_CNTL_BUF1 0x00000008 33842d756322SRob Clark #define A6XX_VPC_SO_BUF_CNTL_BUF2 0x00000040 33852d756322SRob Clark #define A6XX_VPC_SO_BUF_CNTL_BUF3 0x00000200 33862d756322SRob Clark #define A6XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000 33872d756322SRob Clark 33882d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9600 0x00009600 33892d756322SRob Clark 33902d756322SRob Clark #define REG_A6XX_VPC_UNKNOWN_9602 0x00009602 33912d756322SRob Clark 33922d756322SRob Clark #define REG_A6XX_PC_UNKNOWN_9801 0x00009801 33932d756322SRob Clark 33942d756322SRob Clark #define REG_A6XX_PC_RESTART_INDEX 0x00009803 33952d756322SRob Clark 33962d756322SRob Clark #define REG_A6XX_PC_MODE_CNTL 0x00009804 33972d756322SRob Clark 33982d756322SRob Clark #define REG_A6XX_PC_UNKNOWN_9805 0x00009805 33992d756322SRob Clark 34002d756322SRob Clark #define REG_A6XX_PC_UNKNOWN_9981 0x00009981 34012d756322SRob Clark 34022d756322SRob Clark #define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00 34032d756322SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001 34042d756322SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002 34052d756322SRob Clark 34062d756322SRob Clark #define REG_A6XX_PC_PRIMITIVE_CNTL_1 0x00009b01 34072d756322SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__MASK 0x0000007f 34082d756322SRob Clark #define A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__SHIFT 0 34092d756322SRob Clark static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(uint32_t val) 34102d756322SRob Clark { 34112d756322SRob Clark return ((val) << A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC__MASK; 34122d756322SRob Clark } 34132d756322SRob Clark 34142d756322SRob Clark #define REG_A6XX_PC_UNKNOWN_9B06 0x00009b06 34152d756322SRob Clark 34162d756322SRob Clark #define REG_A6XX_PC_UNKNOWN_9B07 0x00009b07 34172d756322SRob Clark 34182d756322SRob Clark #define REG_A6XX_PC_TESSFACTOR_ADDR_LO 0x00009e08 34192d756322SRob Clark 34202d756322SRob Clark #define REG_A6XX_PC_TESSFACTOR_ADDR_HI 0x00009e09 34212d756322SRob Clark 34222d756322SRob Clark #define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72 34232d756322SRob Clark 34242d756322SRob Clark #define REG_A6XX_VFD_CONTROL_0 0x0000a000 34252d756322SRob Clark #define A6XX_VFD_CONTROL_0_VTXCNT__MASK 0x0000003f 34262d756322SRob Clark #define A6XX_VFD_CONTROL_0_VTXCNT__SHIFT 0 34272d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_0_VTXCNT(uint32_t val) 34282d756322SRob Clark { 34292d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A6XX_VFD_CONTROL_0_VTXCNT__MASK; 34302d756322SRob Clark } 34312d756322SRob Clark 34322d756322SRob Clark #define REG_A6XX_VFD_CONTROL_1 0x0000a001 34332d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff 34342d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0 34352d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 34362d756322SRob Clark { 34372d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VTX__MASK; 34382d756322SRob Clark } 34392d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00 34402d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4INST__SHIFT 8 34412d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 34422d756322SRob Clark { 34432d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK; 34442d756322SRob Clark } 34452d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000 34462d756322SRob Clark #define A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16 34472d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val) 34482d756322SRob Clark { 34492d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK; 34502d756322SRob Clark } 34512d756322SRob Clark 34522d756322SRob Clark #define REG_A6XX_VFD_CONTROL_2 0x0000a002 34532d756322SRob Clark #define A6XX_VFD_CONTROL_2_REGID_PATCHID__MASK 0x000000ff 34542d756322SRob Clark #define A6XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT 0 34552d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_2_REGID_PATCHID(uint32_t val) 34562d756322SRob Clark { 34572d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_PATCHID__MASK; 34582d756322SRob Clark } 34592d756322SRob Clark 34602d756322SRob Clark #define REG_A6XX_VFD_CONTROL_3 0x0000a003 34612d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_PATCHID__MASK 0x0000ff00 34622d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT 8 34632d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_3_REGID_PATCHID(uint32_t val) 34642d756322SRob Clark { 34652d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_PATCHID__MASK; 34662d756322SRob Clark } 34672d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000 34682d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16 34692d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) 34702d756322SRob Clark { 34712d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSX__MASK; 34722d756322SRob Clark } 34732d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000 34742d756322SRob Clark #define A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24 34752d756322SRob Clark static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) 34762d756322SRob Clark { 34772d756322SRob Clark return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK; 34782d756322SRob Clark } 34792d756322SRob Clark 34802d756322SRob Clark #define REG_A6XX_VFD_CONTROL_4 0x0000a004 34812d756322SRob Clark 34822d756322SRob Clark #define REG_A6XX_VFD_CONTROL_5 0x0000a005 34832d756322SRob Clark 34842d756322SRob Clark #define REG_A6XX_VFD_CONTROL_6 0x0000a006 34852d756322SRob Clark 34862d756322SRob Clark #define REG_A6XX_VFD_MODE_CNTL 0x0000a007 34872d756322SRob Clark #define A6XX_VFD_MODE_CNTL_BINNING_PASS 0x00000001 34882d756322SRob Clark 34892d756322SRob Clark #define REG_A6XX_VFD_UNKNOWN_A008 0x0000a008 34902d756322SRob Clark 34912d756322SRob Clark #define REG_A6XX_VFD_INDEX_OFFSET 0x0000a00e 34922d756322SRob Clark 34932d756322SRob Clark #define REG_A6XX_VFD_INSTANCE_START_OFFSET 0x0000a00f 34942d756322SRob Clark 34952d756322SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; } 34962d756322SRob Clark 34972d756322SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000a010 + 0x4*i0; } 34982d756322SRob Clark 34992d756322SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000a011 + 0x4*i0; } 35002d756322SRob Clark 35012d756322SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; } 35022d756322SRob Clark 35032d756322SRob Clark static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; } 35042d756322SRob Clark 35052d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; } 35062d756322SRob Clark 35072d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; } 35082d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f 35092d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_IDX__SHIFT 0 35102d756322SRob Clark static inline uint32_t A6XX_VFD_DECODE_INSTR_IDX(uint32_t val) 35112d756322SRob Clark { 35122d756322SRob Clark return ((val) << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK; 35132d756322SRob Clark } 35142d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_INSTANCED 0x00020000 35152d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000 35162d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20 35172d756322SRob Clark static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_vtx_fmt val) 35182d756322SRob Clark { 35192d756322SRob Clark return ((val) << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK; 35202d756322SRob Clark } 35212d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000 35222d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_SWAP__SHIFT 28 35232d756322SRob Clark static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 35242d756322SRob Clark { 35252d756322SRob Clark return ((val) << A6XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A6XX_VFD_DECODE_INSTR_SWAP__MASK; 35262d756322SRob Clark } 35272d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_UNK30 0x40000000 35282d756322SRob Clark #define A6XX_VFD_DECODE_INSTR_FLOAT 0x80000000 35292d756322SRob Clark 35302d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; } 35312d756322SRob Clark 35322d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } 35332d756322SRob Clark 35342d756322SRob Clark static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } 35352d756322SRob Clark #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f 35362d756322SRob Clark #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0 35372d756322SRob Clark static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val) 35382d756322SRob Clark { 35392d756322SRob Clark return ((val) << A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK; 35402d756322SRob Clark } 35412d756322SRob Clark #define A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0 35422d756322SRob Clark #define A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4 35432d756322SRob Clark static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) 35442d756322SRob Clark { 35452d756322SRob Clark return ((val) << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK; 35462d756322SRob Clark } 35472d756322SRob Clark 35482d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_A0F8 0x0000a0f8 35492d756322SRob Clark 35502d756322SRob Clark #define REG_A6XX_SP_PRIMITIVE_CNTL 0x0000a802 35512d756322SRob Clark #define A6XX_SP_PRIMITIVE_CNTL_VSOUT__MASK 0x0000001f 35522d756322SRob Clark #define A6XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT 0 35532d756322SRob Clark static inline uint32_t A6XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val) 35542d756322SRob Clark { 35552d756322SRob Clark return ((val) << A6XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT) & A6XX_SP_PRIMITIVE_CNTL_VSOUT__MASK; 35562d756322SRob Clark } 35572d756322SRob Clark 35582d756322SRob Clark static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; } 35592d756322SRob Clark 35602d756322SRob Clark static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; } 35612d756322SRob Clark #define A6XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff 35622d756322SRob Clark #define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 35632d756322SRob Clark static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 35642d756322SRob Clark { 35652d756322SRob Clark return ((val) << A6XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_A_REGID__MASK; 35662d756322SRob Clark } 35672d756322SRob Clark #define A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00 35682d756322SRob Clark #define A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8 35692d756322SRob Clark static inline uint32_t A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 35702d756322SRob Clark { 35712d756322SRob Clark return ((val) << A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 35722d756322SRob Clark } 35732d756322SRob Clark #define A6XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000 35742d756322SRob Clark #define A6XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 35752d756322SRob Clark static inline uint32_t A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 35762d756322SRob Clark { 35772d756322SRob Clark return ((val) << A6XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_B_REGID__MASK; 35782d756322SRob Clark } 35792d756322SRob Clark #define A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000 35802d756322SRob Clark #define A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24 35812d756322SRob Clark static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 35822d756322SRob Clark { 35832d756322SRob Clark return ((val) << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 35842d756322SRob Clark } 35852d756322SRob Clark 35862d756322SRob Clark static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; } 35872d756322SRob Clark 35882d756322SRob Clark static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; } 35892d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 35902d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 35912d756322SRob Clark static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 35922d756322SRob Clark { 35932d756322SRob Clark return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 35942d756322SRob Clark } 35952d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 35962d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 35972d756322SRob Clark static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 35982d756322SRob Clark { 35992d756322SRob Clark return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 36002d756322SRob Clark } 36012d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 36022d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 36032d756322SRob Clark static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 36042d756322SRob Clark { 36052d756322SRob Clark return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 36062d756322SRob Clark } 36072d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 36082d756322SRob Clark #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 36092d756322SRob Clark static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 36102d756322SRob Clark { 36112d756322SRob Clark return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 36122d756322SRob Clark } 36132d756322SRob Clark 36142d756322SRob Clark #define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800 36152d756322SRob Clark #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 36162d756322SRob Clark #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 36172d756322SRob Clark static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 36182d756322SRob Clark { 36192d756322SRob Clark return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 36202d756322SRob Clark } 36212d756322SRob Clark #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 36222d756322SRob Clark #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 36232d756322SRob Clark static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 36242d756322SRob Clark { 36252d756322SRob Clark return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 36262d756322SRob Clark } 36272d756322SRob Clark #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 36282d756322SRob Clark #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14 36292d756322SRob Clark static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val) 36302d756322SRob Clark { 36312d756322SRob Clark return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK; 36322d756322SRob Clark } 36332d756322SRob Clark #define A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000 36342d756322SRob Clark #define A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20 36352d756322SRob Clark static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 36362d756322SRob Clark { 36372d756322SRob Clark return ((val) << A6XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; 36382d756322SRob Clark } 36392d756322SRob Clark #define A6XX_SP_VS_CTRL_REG0_VARYING 0x00400000 36402d756322SRob Clark #define A6XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x04000000 36412d756322SRob Clark #define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x80000000 36422d756322SRob Clark 36432d756322SRob Clark #define REG_A6XX_SP_VS_OBJ_START_LO 0x0000a81c 36442d756322SRob Clark 36452d756322SRob Clark #define REG_A6XX_SP_VS_OBJ_START_HI 0x0000a81d 36462d756322SRob Clark 36472d756322SRob Clark #define REG_A6XX_SP_VS_TEX_COUNT 0x0000a822 36482d756322SRob Clark 36492d756322SRob Clark #define REG_A6XX_SP_VS_CONFIG 0x0000a823 36502d756322SRob Clark #define A6XX_SP_VS_CONFIG_ENABLED 0x00000100 36512d756322SRob Clark #define A6XX_SP_VS_CONFIG_NTEX__MASK 0x0001fe00 36522d756322SRob Clark #define A6XX_SP_VS_CONFIG_NTEX__SHIFT 9 36532d756322SRob Clark static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val) 36542d756322SRob Clark { 36552d756322SRob Clark return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK; 36562d756322SRob Clark } 36572d756322SRob Clark #define A6XX_SP_VS_CONFIG_NSAMP__MASK 0x01fe0000 36582d756322SRob Clark #define A6XX_SP_VS_CONFIG_NSAMP__SHIFT 17 36592d756322SRob Clark static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val) 36602d756322SRob Clark { 36612d756322SRob Clark return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK; 36622d756322SRob Clark } 36632d756322SRob Clark 36642d756322SRob Clark #define REG_A6XX_SP_VS_INSTRLEN 0x0000a824 36652d756322SRob Clark 36662d756322SRob Clark #define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830 36672d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 36682d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 36692d756322SRob Clark static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 36702d756322SRob Clark { 36712d756322SRob Clark return ((val) << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 36722d756322SRob Clark } 36732d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 36742d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 36752d756322SRob Clark static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 36762d756322SRob Clark { 36772d756322SRob Clark return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 36782d756322SRob Clark } 36792d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 36802d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 14 36812d756322SRob Clark static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val) 36822d756322SRob Clark { 36832d756322SRob Clark return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK; 36842d756322SRob Clark } 36852d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK 0x00100000 36862d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT 20 36872d756322SRob Clark static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 36882d756322SRob Clark { 36892d756322SRob Clark return ((val) << A6XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADSIZE__MASK; 36902d756322SRob Clark } 36912d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_VARYING 0x00400000 36922d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_PIXLODENABLE 0x04000000 36932d756322SRob Clark #define A6XX_SP_HS_CTRL_REG0_MERGEDREGS 0x80000000 36942d756322SRob Clark 36952d756322SRob Clark #define REG_A6XX_SP_HS_UNKNOWN_A831 0x0000a831 36962d756322SRob Clark 36972d756322SRob Clark #define REG_A6XX_SP_HS_OBJ_START_LO 0x0000a834 36982d756322SRob Clark 36992d756322SRob Clark #define REG_A6XX_SP_HS_OBJ_START_HI 0x0000a835 37002d756322SRob Clark 37012d756322SRob Clark #define REG_A6XX_SP_HS_TEX_COUNT 0x0000a83a 37022d756322SRob Clark 37032d756322SRob Clark #define REG_A6XX_SP_HS_CONFIG 0x0000a83b 37042d756322SRob Clark #define A6XX_SP_HS_CONFIG_ENABLED 0x00000100 37052d756322SRob Clark #define A6XX_SP_HS_CONFIG_NTEX__MASK 0x0001fe00 37062d756322SRob Clark #define A6XX_SP_HS_CONFIG_NTEX__SHIFT 9 37072d756322SRob Clark static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val) 37082d756322SRob Clark { 37092d756322SRob Clark return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK; 37102d756322SRob Clark } 37112d756322SRob Clark #define A6XX_SP_HS_CONFIG_NSAMP__MASK 0x01fe0000 37122d756322SRob Clark #define A6XX_SP_HS_CONFIG_NSAMP__SHIFT 17 37132d756322SRob Clark static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val) 37142d756322SRob Clark { 37152d756322SRob Clark return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK; 37162d756322SRob Clark } 37172d756322SRob Clark 37182d756322SRob Clark #define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c 37192d756322SRob Clark 37202d756322SRob Clark #define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840 37212d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 37222d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 37232d756322SRob Clark static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 37242d756322SRob Clark { 37252d756322SRob Clark return ((val) << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 37262d756322SRob Clark } 37272d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 37282d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 37292d756322SRob Clark static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 37302d756322SRob Clark { 37312d756322SRob Clark return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 37322d756322SRob Clark } 37332d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 37342d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 14 37352d756322SRob Clark static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val) 37362d756322SRob Clark { 37372d756322SRob Clark return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK; 37382d756322SRob Clark } 37392d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK 0x00100000 37402d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT 20 37412d756322SRob Clark static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 37422d756322SRob Clark { 37432d756322SRob Clark return ((val) << A6XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADSIZE__MASK; 37442d756322SRob Clark } 37452d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_VARYING 0x00400000 37462d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_PIXLODENABLE 0x04000000 37472d756322SRob Clark #define A6XX_SP_DS_CTRL_REG0_MERGEDREGS 0x80000000 37482d756322SRob Clark 37492d756322SRob Clark #define REG_A6XX_SP_DS_OBJ_START_LO 0x0000a85c 37502d756322SRob Clark 37512d756322SRob Clark #define REG_A6XX_SP_DS_OBJ_START_HI 0x0000a85d 37522d756322SRob Clark 37532d756322SRob Clark #define REG_A6XX_SP_DS_TEX_COUNT 0x0000a862 37542d756322SRob Clark 37552d756322SRob Clark #define REG_A6XX_SP_DS_CONFIG 0x0000a863 37562d756322SRob Clark #define A6XX_SP_DS_CONFIG_ENABLED 0x00000100 37572d756322SRob Clark #define A6XX_SP_DS_CONFIG_NTEX__MASK 0x0001fe00 37582d756322SRob Clark #define A6XX_SP_DS_CONFIG_NTEX__SHIFT 9 37592d756322SRob Clark static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val) 37602d756322SRob Clark { 37612d756322SRob Clark return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK; 37622d756322SRob Clark } 37632d756322SRob Clark #define A6XX_SP_DS_CONFIG_NSAMP__MASK 0x01fe0000 37642d756322SRob Clark #define A6XX_SP_DS_CONFIG_NSAMP__SHIFT 17 37652d756322SRob Clark static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val) 37662d756322SRob Clark { 37672d756322SRob Clark return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK; 37682d756322SRob Clark } 37692d756322SRob Clark 37702d756322SRob Clark #define REG_A6XX_SP_DS_INSTRLEN 0x0000a864 37712d756322SRob Clark 37722d756322SRob Clark #define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870 37732d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 37742d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 37752d756322SRob Clark static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 37762d756322SRob Clark { 37772d756322SRob Clark return ((val) << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 37782d756322SRob Clark } 37792d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 37802d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 37812d756322SRob Clark static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 37822d756322SRob Clark { 37832d756322SRob Clark return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 37842d756322SRob Clark } 37852d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 37862d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 14 37872d756322SRob Clark static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val) 37882d756322SRob Clark { 37892d756322SRob Clark return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK; 37902d756322SRob Clark } 37912d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK 0x00100000 37922d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT 20 37932d756322SRob Clark static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 37942d756322SRob Clark { 37952d756322SRob Clark return ((val) << A6XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADSIZE__MASK; 37962d756322SRob Clark } 37972d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_VARYING 0x00400000 37982d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_PIXLODENABLE 0x04000000 37992d756322SRob Clark #define A6XX_SP_GS_CTRL_REG0_MERGEDREGS 0x80000000 38002d756322SRob Clark 38012d756322SRob Clark #define REG_A6XX_SP_GS_UNKNOWN_A871 0x0000a871 38022d756322SRob Clark 38032d756322SRob Clark #define REG_A6XX_SP_GS_OBJ_START_LO 0x0000a88d 38042d756322SRob Clark 38052d756322SRob Clark #define REG_A6XX_SP_GS_OBJ_START_HI 0x0000a88e 38062d756322SRob Clark 38072d756322SRob Clark #define REG_A6XX_SP_GS_TEX_COUNT 0x0000a893 38082d756322SRob Clark 38092d756322SRob Clark #define REG_A6XX_SP_GS_CONFIG 0x0000a894 38102d756322SRob Clark #define A6XX_SP_GS_CONFIG_ENABLED 0x00000100 38112d756322SRob Clark #define A6XX_SP_GS_CONFIG_NTEX__MASK 0x0001fe00 38122d756322SRob Clark #define A6XX_SP_GS_CONFIG_NTEX__SHIFT 9 38132d756322SRob Clark static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val) 38142d756322SRob Clark { 38152d756322SRob Clark return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK; 38162d756322SRob Clark } 38172d756322SRob Clark #define A6XX_SP_GS_CONFIG_NSAMP__MASK 0x01fe0000 38182d756322SRob Clark #define A6XX_SP_GS_CONFIG_NSAMP__SHIFT 17 38192d756322SRob Clark static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val) 38202d756322SRob Clark { 38212d756322SRob Clark return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK; 38222d756322SRob Clark } 38232d756322SRob Clark 38242d756322SRob Clark #define REG_A6XX_SP_GS_INSTRLEN 0x0000a895 38252d756322SRob Clark 38262d756322SRob Clark #define REG_A6XX_SP_VS_TEX_SAMP_LO 0x0000a8a0 38272d756322SRob Clark 38282d756322SRob Clark #define REG_A6XX_SP_VS_TEX_SAMP_HI 0x0000a8a1 38292d756322SRob Clark 38302d756322SRob Clark #define REG_A6XX_SP_HS_TEX_SAMP_LO 0x0000a8a2 38312d756322SRob Clark 38322d756322SRob Clark #define REG_A6XX_SP_HS_TEX_SAMP_HI 0x0000a8a3 38332d756322SRob Clark 38342d756322SRob Clark #define REG_A6XX_SP_DS_TEX_SAMP_LO 0x0000a8a4 38352d756322SRob Clark 38362d756322SRob Clark #define REG_A6XX_SP_DS_TEX_SAMP_HI 0x0000a8a5 38372d756322SRob Clark 38382d756322SRob Clark #define REG_A6XX_SP_GS_TEX_SAMP_LO 0x0000a8a6 38392d756322SRob Clark 38402d756322SRob Clark #define REG_A6XX_SP_GS_TEX_SAMP_HI 0x0000a8a7 38412d756322SRob Clark 38422d756322SRob Clark #define REG_A6XX_SP_VS_TEX_CONST_LO 0x0000a8a8 38432d756322SRob Clark 38442d756322SRob Clark #define REG_A6XX_SP_VS_TEX_CONST_HI 0x0000a8a9 38452d756322SRob Clark 38462d756322SRob Clark #define REG_A6XX_SP_HS_TEX_CONST_LO 0x0000a8aa 38472d756322SRob Clark 38482d756322SRob Clark #define REG_A6XX_SP_HS_TEX_CONST_HI 0x0000a8ab 38492d756322SRob Clark 38502d756322SRob Clark #define REG_A6XX_SP_DS_TEX_CONST_LO 0x0000a8ac 38512d756322SRob Clark 38522d756322SRob Clark #define REG_A6XX_SP_DS_TEX_CONST_HI 0x0000a8ad 38532d756322SRob Clark 38542d756322SRob Clark #define REG_A6XX_SP_GS_TEX_CONST_LO 0x0000a8ae 38552d756322SRob Clark 38562d756322SRob Clark #define REG_A6XX_SP_GS_TEX_CONST_HI 0x0000a8af 38572d756322SRob Clark 38582d756322SRob Clark #define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980 38592d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 38602d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 38612d756322SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 38622d756322SRob Clark { 38632d756322SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 38642d756322SRob Clark } 38652d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 38662d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 38672d756322SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 38682d756322SRob Clark { 38692d756322SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 38702d756322SRob Clark } 38712d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 38722d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 14 38732d756322SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) 38742d756322SRob Clark { 38752d756322SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK; 38762d756322SRob Clark } 38772d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 38782d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 38792d756322SRob Clark static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 38802d756322SRob Clark { 38812d756322SRob Clark return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 38822d756322SRob Clark } 38832d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000 38842d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000 38852d756322SRob Clark #define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000 38862d756322SRob Clark 38872d756322SRob Clark #define REG_A6XX_SP_FS_OBJ_START_LO 0x0000a983 38882d756322SRob Clark 38892d756322SRob Clark #define REG_A6XX_SP_FS_OBJ_START_HI 0x0000a984 38902d756322SRob Clark 38912d756322SRob Clark #define REG_A6XX_SP_BLEND_CNTL 0x0000a989 38922d756322SRob Clark #define A6XX_SP_BLEND_CNTL_ENABLED 0x00000001 38932d756322SRob Clark #define A6XX_SP_BLEND_CNTL_UNK8 0x00000100 38942d756322SRob Clark 38952d756322SRob Clark #define REG_A6XX_SP_SRGB_CNTL 0x0000a98a 38962d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT0 0x00000001 38972d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT1 0x00000002 38982d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT2 0x00000004 38992d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT3 0x00000008 39002d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT4 0x00000010 39012d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT5 0x00000020 39022d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT6 0x00000040 39032d756322SRob Clark #define A6XX_SP_SRGB_CNTL_SRGB_MRT7 0x00000080 39042d756322SRob Clark 39052d756322SRob Clark #define REG_A6XX_SP_FS_RENDER_COMPONENTS 0x0000a98b 39062d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK 0x0000000f 39072d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT 0 39082d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val) 39092d756322SRob Clark { 39102d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK; 39112d756322SRob Clark } 39122d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK 0x000000f0 39132d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT 4 39142d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val) 39152d756322SRob Clark { 39162d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK; 39172d756322SRob Clark } 39182d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK 0x00000f00 39192d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT 8 39202d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val) 39212d756322SRob Clark { 39222d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK; 39232d756322SRob Clark } 39242d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK 0x0000f000 39252d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT 12 39262d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val) 39272d756322SRob Clark { 39282d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK; 39292d756322SRob Clark } 39302d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK 0x000f0000 39312d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT 16 39322d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val) 39332d756322SRob Clark { 39342d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK; 39352d756322SRob Clark } 39362d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK 0x00f00000 39372d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT 20 39382d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val) 39392d756322SRob Clark { 39402d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK; 39412d756322SRob Clark } 39422d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK 0x0f000000 39432d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT 24 39442d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val) 39452d756322SRob Clark { 39462d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK; 39472d756322SRob Clark } 39482d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK 0xf0000000 39492d756322SRob Clark #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT 28 39502d756322SRob Clark static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val) 39512d756322SRob Clark { 39522d756322SRob Clark return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK; 39532d756322SRob Clark } 39542d756322SRob Clark 39552d756322SRob Clark #define REG_A6XX_SP_FS_OUTPUT_CNTL0 0x0000a98c 39562d756322SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK 0x0000ff00 39572d756322SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT 8 39582d756322SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val) 39592d756322SRob Clark { 39602d756322SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK; 39612d756322SRob Clark } 39622d756322SRob Clark 39632d756322SRob Clark #define REG_A6XX_SP_FS_OUTPUT_CNTL1 0x0000a98d 39642d756322SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f 39652d756322SRob Clark #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT 0 39662d756322SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val) 39672d756322SRob Clark { 39682d756322SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK; 39692d756322SRob Clark } 39702d756322SRob Clark 39712d756322SRob Clark static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; } 39722d756322SRob Clark 39732d756322SRob Clark static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; } 39742d756322SRob Clark #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff 39752d756322SRob Clark #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0 39762d756322SRob Clark static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_color_fmt val) 39772d756322SRob Clark { 39782d756322SRob Clark return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK; 39792d756322SRob Clark } 39802d756322SRob Clark #define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100 39812d756322SRob Clark #define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200 39822d756322SRob Clark #define A6XX_SP_FS_MRT_REG_COLOR_SRGB 0x00000400 39832d756322SRob Clark 39842d756322SRob Clark #define REG_A6XX_SP_FS_TEX_COUNT 0x0000a9a7 39852d756322SRob Clark 39862d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8 39872d756322SRob Clark 39882d756322SRob Clark #define REG_A6XX_SP_FS_TEX_SAMP_LO 0x0000a9e0 39892d756322SRob Clark 39902d756322SRob Clark #define REG_A6XX_SP_FS_TEX_SAMP_HI 0x0000a9e1 39912d756322SRob Clark 39922d756322SRob Clark #define REG_A6XX_SP_CS_TEX_SAMP_LO 0x0000a9e2 39932d756322SRob Clark 39942d756322SRob Clark #define REG_A6XX_SP_CS_TEX_SAMP_HI 0x0000a9e3 39952d756322SRob Clark 39962d756322SRob Clark #define REG_A6XX_SP_FS_TEX_CONST_LO 0x0000a9e4 39972d756322SRob Clark 39982d756322SRob Clark #define REG_A6XX_SP_FS_TEX_CONST_HI 0x0000a9e5 39992d756322SRob Clark 40002d756322SRob Clark #define REG_A6XX_SP_CS_TEX_CONST_LO 0x0000a9e6 40012d756322SRob Clark 40022d756322SRob Clark #define REG_A6XX_SP_CS_TEX_CONST_HI 0x0000a9e7 40032d756322SRob Clark 40042d756322SRob Clark static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; } 40052d756322SRob Clark 40062d756322SRob Clark static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; } 40072d756322SRob Clark #define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff 40082d756322SRob Clark #define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0 40092d756322SRob Clark static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) 40102d756322SRob Clark { 40112d756322SRob Clark return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK; 40122d756322SRob Clark } 40132d756322SRob Clark #define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100 40142d756322SRob Clark 40152d756322SRob Clark #define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0 40162d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e 40172d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1 40182d756322SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 40192d756322SRob Clark { 40202d756322SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 40212d756322SRob Clark } 40222d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80 40232d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7 40242d756322SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 40252d756322SRob Clark { 40262d756322SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 40272d756322SRob Clark } 40282d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 40292d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 14 40302d756322SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val) 40312d756322SRob Clark { 40322d756322SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK; 40332d756322SRob Clark } 40342d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000 40352d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20 40362d756322SRob Clark static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 40372d756322SRob Clark { 40382d756322SRob Clark return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK; 40392d756322SRob Clark } 40402d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_VARYING 0x00400000 40412d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x04000000 40422d756322SRob Clark #define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000 40432d756322SRob Clark 40442d756322SRob Clark #define REG_A6XX_SP_CS_OBJ_START_LO 0x0000a9b4 40452d756322SRob Clark 40462d756322SRob Clark #define REG_A6XX_SP_CS_OBJ_START_HI 0x0000a9b5 40472d756322SRob Clark 40482d756322SRob Clark #define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc 40492d756322SRob Clark 40502d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_AB00 0x0000ab00 40512d756322SRob Clark 40522d756322SRob Clark #define REG_A6XX_SP_FS_CONFIG 0x0000ab04 40532d756322SRob Clark #define A6XX_SP_FS_CONFIG_ENABLED 0x00000100 40542d756322SRob Clark #define A6XX_SP_FS_CONFIG_NTEX__MASK 0x0001fe00 40552d756322SRob Clark #define A6XX_SP_FS_CONFIG_NTEX__SHIFT 9 40562d756322SRob Clark static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val) 40572d756322SRob Clark { 40582d756322SRob Clark return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK; 40592d756322SRob Clark } 40602d756322SRob Clark #define A6XX_SP_FS_CONFIG_NSAMP__MASK 0x01fe0000 40612d756322SRob Clark #define A6XX_SP_FS_CONFIG_NSAMP__SHIFT 17 40622d756322SRob Clark static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val) 40632d756322SRob Clark { 40642d756322SRob Clark return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK; 40652d756322SRob Clark } 40662d756322SRob Clark 40672d756322SRob Clark #define REG_A6XX_SP_FS_INSTRLEN 0x0000ab05 40682d756322SRob Clark 40692d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_AE00 0x0000ae00 40702d756322SRob Clark 40712d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_AE04 0x0000ae04 40722d756322SRob Clark 40732d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_AE0F 0x0000ae0f 40742d756322SRob Clark 40752d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_B182 0x0000b182 40762d756322SRob Clark 40772d756322SRob Clark #define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300 40782d756322SRob Clark #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 40792d756322SRob Clark #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 40802d756322SRob Clark static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 40812d756322SRob Clark { 40822d756322SRob Clark return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK; 40832d756322SRob Clark } 40842d756322SRob Clark 40852d756322SRob Clark #define REG_A6XX_SP_TP_DEST_MSAA_CNTL 0x0000b301 40862d756322SRob Clark #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 40872d756322SRob Clark #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 40882d756322SRob Clark static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 40892d756322SRob Clark { 40902d756322SRob Clark return ((val) << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK; 40912d756322SRob Clark } 40922d756322SRob Clark #define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 40932d756322SRob Clark 40942d756322SRob Clark #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO 0x0000b302 40952d756322SRob Clark 40962d756322SRob Clark #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_HI 0x0000b303 40972d756322SRob Clark 40982d756322SRob Clark #define REG_A6XX_SP_TP_UNKNOWN_B304 0x0000b304 40992d756322SRob Clark 41002d756322SRob Clark #define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0 41012d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff 41022d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 41032d756322SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_color_fmt val) 41042d756322SRob Clark { 41052d756322SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK; 41062d756322SRob Clark } 41072d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300 41082d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT 8 41092d756322SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val) 41102d756322SRob Clark { 41112d756322SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK; 41122d756322SRob Clark } 41132d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00 41142d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10 41152d756322SRob Clark static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) 41162d756322SRob Clark { 41172d756322SRob Clark return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK; 41182d756322SRob Clark } 41192d756322SRob Clark #define A6XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000 41202d756322SRob Clark 41212d756322SRob Clark #define REG_A6XX_SP_PS_2D_SRC_LO 0x0000b4c2 41222d756322SRob Clark 41232d756322SRob Clark #define REG_A6XX_SP_PS_2D_SRC_HI 0x0000b4c3 41242d756322SRob Clark 41252d756322SRob Clark #define REG_A6XX_SP_PS_2D_SRC_FLAGS_LO 0x0000b4ca 41262d756322SRob Clark 41272d756322SRob Clark #define REG_A6XX_SP_PS_2D_SRC_FLAGS_HI 0x0000b4cb 41282d756322SRob Clark 41292d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_B600 0x0000b600 41302d756322SRob Clark 41312d756322SRob Clark #define REG_A6XX_SP_UNKNOWN_B605 0x0000b605 41322d756322SRob Clark 41332d756322SRob Clark #define REG_A6XX_HLSQ_VS_CNTL 0x0000b800 41342d756322SRob Clark #define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff 41352d756322SRob Clark #define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0 41362d756322SRob Clark static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val) 41372d756322SRob Clark { 41382d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK; 41392d756322SRob Clark } 41402d756322SRob Clark 41412d756322SRob Clark #define REG_A6XX_HLSQ_HS_CNTL 0x0000b801 41422d756322SRob Clark #define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff 41432d756322SRob Clark #define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0 41442d756322SRob Clark static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val) 41452d756322SRob Clark { 41462d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK; 41472d756322SRob Clark } 41482d756322SRob Clark 41492d756322SRob Clark #define REG_A6XX_HLSQ_DS_CNTL 0x0000b802 41502d756322SRob Clark #define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff 41512d756322SRob Clark #define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0 41522d756322SRob Clark static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val) 41532d756322SRob Clark { 41542d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK; 41552d756322SRob Clark } 41562d756322SRob Clark 41572d756322SRob Clark #define REG_A6XX_HLSQ_GS_CNTL 0x0000b803 41582d756322SRob Clark #define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff 41592d756322SRob Clark #define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0 41602d756322SRob Clark static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val) 41612d756322SRob Clark { 41622d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK; 41632d756322SRob Clark } 41642d756322SRob Clark 41652d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982 41662d756322SRob Clark 41672d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_2_REG 0x0000b983 41682d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff 41692d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0 41702d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) 41712d756322SRob Clark { 41722d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; 41732d756322SRob Clark } 41742d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00 41752d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8 41762d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) 41772d756322SRob Clark { 41782d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK; 41792d756322SRob Clark } 41802d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000 41812d756322SRob Clark #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16 41822d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) 41832d756322SRob Clark { 41842d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK; 41852d756322SRob Clark } 41862d756322SRob Clark 41872d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_3_REG 0x0000b984 41882d756322SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK 0x000000ff 41892d756322SRob Clark #define A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT 0 41902d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val) 41912d756322SRob Clark { 41922d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK; 41932d756322SRob Clark } 41942d756322SRob Clark 41952d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_4_REG 0x0000b985 41962d756322SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000 41972d756322SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16 41982d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) 41992d756322SRob Clark { 42002d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK; 42012d756322SRob Clark } 42022d756322SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000 42032d756322SRob Clark #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24 42042d756322SRob Clark static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) 42052d756322SRob Clark { 42062d756322SRob Clark return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; 42072d756322SRob Clark } 42082d756322SRob Clark 42092d756322SRob Clark #define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986 42102d756322SRob Clark 42112d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_0 0x0000b990 42122d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003 42132d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0 42142d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) 42152d756322SRob Clark { 42162d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK; 42172d756322SRob Clark } 42182d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc 42192d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2 42202d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) 42212d756322SRob Clark { 42222d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK; 42232d756322SRob Clark } 42242d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000 42252d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12 42262d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) 42272d756322SRob Clark { 42282d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK; 42292d756322SRob Clark } 42302d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000 42312d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22 42322d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) 42332d756322SRob Clark { 42342d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK; 42352d756322SRob Clark } 42362d756322SRob Clark 42372d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_1 0x0000b991 42382d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff 42392d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0 42402d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val) 42412d756322SRob Clark { 42422d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK; 42432d756322SRob Clark } 42442d756322SRob Clark 42452d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_2 0x0000b992 42462d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff 42472d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0 42482d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val) 42492d756322SRob Clark { 42502d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK; 42512d756322SRob Clark } 42522d756322SRob Clark 42532d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_3 0x0000b993 42542d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff 42552d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0 42562d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val) 42572d756322SRob Clark { 42582d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK; 42592d756322SRob Clark } 42602d756322SRob Clark 42612d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_4 0x0000b994 42622d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff 42632d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0 42642d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val) 42652d756322SRob Clark { 42662d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK; 42672d756322SRob Clark } 42682d756322SRob Clark 42692d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_5 0x0000b995 42702d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff 42712d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0 42722d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val) 42732d756322SRob Clark { 42742d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK; 42752d756322SRob Clark } 42762d756322SRob Clark 42772d756322SRob Clark #define REG_A6XX_HLSQ_CS_NDRANGE_6 0x0000b996 42782d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff 42792d756322SRob Clark #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0 42802d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val) 42812d756322SRob Clark { 42822d756322SRob Clark return ((val) << A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK; 42832d756322SRob Clark } 42842d756322SRob Clark 42852d756322SRob Clark #define REG_A6XX_HLSQ_CS_CNTL_0 0x0000b997 42862d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff 42872d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0 42882d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val) 42892d756322SRob Clark { 42902d756322SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK; 42912d756322SRob Clark } 42922d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_UNK0__MASK 0x0000ff00 42932d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT 8 42942d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val) 42952d756322SRob Clark { 42962d756322SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK0__MASK; 42972d756322SRob Clark } 42982d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_UNK1__MASK 0x00ff0000 42992d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT 16 43002d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val) 43012d756322SRob Clark { 43022d756322SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A6XX_HLSQ_CS_CNTL_0_UNK1__MASK; 43032d756322SRob Clark } 43042d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000 43052d756322SRob Clark #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24 43062d756322SRob Clark static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) 43072d756322SRob Clark { 43082d756322SRob Clark return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK; 43092d756322SRob Clark } 43102d756322SRob Clark 43112d756322SRob Clark #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X 0x0000b999 43122d756322SRob Clark 43132d756322SRob Clark #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000b99a 43142d756322SRob Clark 43152d756322SRob Clark #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000b99b 43162d756322SRob Clark 43172d756322SRob Clark #define REG_A6XX_HLSQ_UPDATE_CNTL 0x0000bb08 43182d756322SRob Clark 43192d756322SRob Clark #define REG_A6XX_HLSQ_FS_CNTL 0x0000bb10 43202d756322SRob Clark #define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff 43212d756322SRob Clark #define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0 43222d756322SRob Clark static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val) 43232d756322SRob Clark { 43242d756322SRob Clark return ((val >> 2) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK; 43252d756322SRob Clark } 43262d756322SRob Clark 43272d756322SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_BB11 0x0000bb11 43282d756322SRob Clark 43292d756322SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_BE00 0x0000be00 43302d756322SRob Clark 43312d756322SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_BE01 0x0000be01 43322d756322SRob Clark 43332d756322SRob Clark #define REG_A6XX_HLSQ_UNKNOWN_BE04 0x0000be04 43342d756322SRob Clark 43352d756322SRob Clark #define REG_A6XX_TEX_SAMP_0 0x00000000 43362d756322SRob Clark #define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 43372d756322SRob Clark #define A6XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 43382d756322SRob Clark #define A6XX_TEX_SAMP_0_XY_MAG__SHIFT 1 43392d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val) 43402d756322SRob Clark { 43412d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_XY_MAG__SHIFT) & A6XX_TEX_SAMP_0_XY_MAG__MASK; 43422d756322SRob Clark } 43432d756322SRob Clark #define A6XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 43442d756322SRob Clark #define A6XX_TEX_SAMP_0_XY_MIN__SHIFT 3 43452d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val) 43462d756322SRob Clark { 43472d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_XY_MIN__SHIFT) & A6XX_TEX_SAMP_0_XY_MIN__MASK; 43482d756322SRob Clark } 43492d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 43502d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_S__SHIFT 5 43512d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val) 43522d756322SRob Clark { 43532d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_WRAP_S__SHIFT) & A6XX_TEX_SAMP_0_WRAP_S__MASK; 43542d756322SRob Clark } 43552d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 43562d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_T__SHIFT 8 43572d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val) 43582d756322SRob Clark { 43592d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_WRAP_T__SHIFT) & A6XX_TEX_SAMP_0_WRAP_T__MASK; 43602d756322SRob Clark } 43612d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 43622d756322SRob Clark #define A6XX_TEX_SAMP_0_WRAP_R__SHIFT 11 43632d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val) 43642d756322SRob Clark { 43652d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_WRAP_R__SHIFT) & A6XX_TEX_SAMP_0_WRAP_R__MASK; 43662d756322SRob Clark } 43672d756322SRob Clark #define A6XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 43682d756322SRob Clark #define A6XX_TEX_SAMP_0_ANISO__SHIFT 14 43692d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val) 43702d756322SRob Clark { 43712d756322SRob Clark return ((val) << A6XX_TEX_SAMP_0_ANISO__SHIFT) & A6XX_TEX_SAMP_0_ANISO__MASK; 43722d756322SRob Clark } 43732d756322SRob Clark #define A6XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000 43742d756322SRob Clark #define A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19 43752d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val) 43762d756322SRob Clark { 43772d756322SRob Clark return ((((int32_t)(val * 256.0))) << A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A6XX_TEX_SAMP_0_LOD_BIAS__MASK; 43782d756322SRob Clark } 43792d756322SRob Clark 43802d756322SRob Clark #define REG_A6XX_TEX_SAMP_1 0x00000001 43812d756322SRob Clark #define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e 43822d756322SRob Clark #define A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 43832d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) 43842d756322SRob Clark { 43852d756322SRob Clark return ((val) << A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK; 43862d756322SRob Clark } 43872d756322SRob Clark #define A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010 43882d756322SRob Clark #define A6XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 43892d756322SRob Clark #define A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 43902d756322SRob Clark #define A6XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 43912d756322SRob Clark #define A6XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 43922d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_1_MAX_LOD(float val) 43932d756322SRob Clark { 43942d756322SRob Clark return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK; 43952d756322SRob Clark } 43962d756322SRob Clark #define A6XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 43972d756322SRob Clark #define A6XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 43982d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_1_MIN_LOD(float val) 43992d756322SRob Clark { 44002d756322SRob Clark return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK; 44012d756322SRob Clark } 44022d756322SRob Clark 44032d756322SRob Clark #define REG_A6XX_TEX_SAMP_2 0x00000002 44042d756322SRob Clark #define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xfffffff0 44052d756322SRob Clark #define A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 4 44062d756322SRob Clark static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val) 44072d756322SRob Clark { 44082d756322SRob Clark return ((val) << A6XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK; 44092d756322SRob Clark } 44102d756322SRob Clark 44112d756322SRob Clark #define REG_A6XX_TEX_SAMP_3 0x00000003 44122d756322SRob Clark 44132d756322SRob Clark #define REG_A6XX_TEX_CONST_0 0x00000000 44142d756322SRob Clark #define A6XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003 44152d756322SRob Clark #define A6XX_TEX_CONST_0_TILE_MODE__SHIFT 0 44162d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val) 44172d756322SRob Clark { 44182d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_TILE_MODE__SHIFT) & A6XX_TEX_CONST_0_TILE_MODE__MASK; 44192d756322SRob Clark } 44202d756322SRob Clark #define A6XX_TEX_CONST_0_SRGB 0x00000004 44212d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 44222d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_X__SHIFT 4 44232d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val) 44242d756322SRob Clark { 44252d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWIZ_X__SHIFT) & A6XX_TEX_CONST_0_SWIZ_X__MASK; 44262d756322SRob Clark } 44272d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 44282d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 44292d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val) 44302d756322SRob Clark { 44312d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Y__MASK; 44322d756322SRob Clark } 44332d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 44342d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 44352d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val) 44362d756322SRob Clark { 44372d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Z__MASK; 44382d756322SRob Clark } 44392d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 44402d756322SRob Clark #define A6XX_TEX_CONST_0_SWIZ_W__SHIFT 13 44412d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val) 44422d756322SRob Clark { 44432d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWIZ_W__SHIFT) & A6XX_TEX_CONST_0_SWIZ_W__MASK; 44442d756322SRob Clark } 44452d756322SRob Clark #define A6XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 44462d756322SRob Clark #define A6XX_TEX_CONST_0_MIPLVLS__SHIFT 16 44472d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val) 44482d756322SRob Clark { 44492d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK; 44502d756322SRob Clark } 44512d756322SRob Clark #define A6XX_TEX_CONST_0_FMT__MASK 0x3fc00000 44522d756322SRob Clark #define A6XX_TEX_CONST_0_FMT__SHIFT 22 44532d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_tex_fmt val) 44542d756322SRob Clark { 44552d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK; 44562d756322SRob Clark } 44572d756322SRob Clark #define A6XX_TEX_CONST_0_SWAP__MASK 0xc0000000 44582d756322SRob Clark #define A6XX_TEX_CONST_0_SWAP__SHIFT 30 44592d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val) 44602d756322SRob Clark { 44612d756322SRob Clark return ((val) << A6XX_TEX_CONST_0_SWAP__SHIFT) & A6XX_TEX_CONST_0_SWAP__MASK; 44622d756322SRob Clark } 44632d756322SRob Clark 44642d756322SRob Clark #define REG_A6XX_TEX_CONST_1 0x00000001 44652d756322SRob Clark #define A6XX_TEX_CONST_1_WIDTH__MASK 0x00007fff 44662d756322SRob Clark #define A6XX_TEX_CONST_1_WIDTH__SHIFT 0 44672d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_1_WIDTH(uint32_t val) 44682d756322SRob Clark { 44692d756322SRob Clark return ((val) << A6XX_TEX_CONST_1_WIDTH__SHIFT) & A6XX_TEX_CONST_1_WIDTH__MASK; 44702d756322SRob Clark } 44712d756322SRob Clark #define A6XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000 44722d756322SRob Clark #define A6XX_TEX_CONST_1_HEIGHT__SHIFT 15 44732d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val) 44742d756322SRob Clark { 44752d756322SRob Clark return ((val) << A6XX_TEX_CONST_1_HEIGHT__SHIFT) & A6XX_TEX_CONST_1_HEIGHT__MASK; 44762d756322SRob Clark } 44772d756322SRob Clark 44782d756322SRob Clark #define REG_A6XX_TEX_CONST_2 0x00000002 44792d756322SRob Clark #define A6XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f 44802d756322SRob Clark #define A6XX_TEX_CONST_2_FETCHSIZE__SHIFT 0 44812d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_2_FETCHSIZE(enum a6xx_tex_fetchsize val) 44822d756322SRob Clark { 44832d756322SRob Clark return ((val) << A6XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A6XX_TEX_CONST_2_FETCHSIZE__MASK; 44842d756322SRob Clark } 44852d756322SRob Clark #define A6XX_TEX_CONST_2_PITCH__MASK 0x1fffff80 44862d756322SRob Clark #define A6XX_TEX_CONST_2_PITCH__SHIFT 7 44872d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_2_PITCH(uint32_t val) 44882d756322SRob Clark { 44892d756322SRob Clark return ((val) << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK; 44902d756322SRob Clark } 44912d756322SRob Clark #define A6XX_TEX_CONST_2_TYPE__MASK 0x60000000 44922d756322SRob Clark #define A6XX_TEX_CONST_2_TYPE__SHIFT 29 44932d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val) 44942d756322SRob Clark { 44952d756322SRob Clark return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK; 44962d756322SRob Clark } 44972d756322SRob Clark 44982d756322SRob Clark #define REG_A6XX_TEX_CONST_3 0x00000003 44992d756322SRob Clark #define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff 45002d756322SRob Clark #define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0 45012d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) 45022d756322SRob Clark { 45032d756322SRob Clark return ((val >> 12) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK; 45042d756322SRob Clark } 45052d756322SRob Clark #define A6XX_TEX_CONST_3_FLAG 0x10000000 45062d756322SRob Clark 45072d756322SRob Clark #define REG_A6XX_TEX_CONST_4 0x00000004 45082d756322SRob Clark #define A6XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0 45092d756322SRob Clark #define A6XX_TEX_CONST_4_BASE_LO__SHIFT 5 45102d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val) 45112d756322SRob Clark { 45122d756322SRob Clark return ((val >> 5) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK; 45132d756322SRob Clark } 45142d756322SRob Clark 45152d756322SRob Clark #define REG_A6XX_TEX_CONST_5 0x00000005 45162d756322SRob Clark #define A6XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff 45172d756322SRob Clark #define A6XX_TEX_CONST_5_BASE_HI__SHIFT 0 45182d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_5_BASE_HI(uint32_t val) 45192d756322SRob Clark { 45202d756322SRob Clark return ((val) << A6XX_TEX_CONST_5_BASE_HI__SHIFT) & A6XX_TEX_CONST_5_BASE_HI__MASK; 45212d756322SRob Clark } 45222d756322SRob Clark #define A6XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000 45232d756322SRob Clark #define A6XX_TEX_CONST_5_DEPTH__SHIFT 17 45242d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_5_DEPTH(uint32_t val) 45252d756322SRob Clark { 45262d756322SRob Clark return ((val) << A6XX_TEX_CONST_5_DEPTH__SHIFT) & A6XX_TEX_CONST_5_DEPTH__MASK; 45272d756322SRob Clark } 45282d756322SRob Clark 45292d756322SRob Clark #define REG_A6XX_TEX_CONST_6 0x00000006 45302d756322SRob Clark 45312d756322SRob Clark #define REG_A6XX_TEX_CONST_7 0x00000007 45322d756322SRob Clark #define A6XX_TEX_CONST_7_FLAG_LO__MASK 0xffffffe0 45332d756322SRob Clark #define A6XX_TEX_CONST_7_FLAG_LO__SHIFT 5 45342d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val) 45352d756322SRob Clark { 45362d756322SRob Clark return ((val >> 5) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK; 45372d756322SRob Clark } 45382d756322SRob Clark 45392d756322SRob Clark #define REG_A6XX_TEX_CONST_8 0x00000008 45402d756322SRob Clark #define A6XX_TEX_CONST_8_BASE_HI__MASK 0x0001ffff 45412d756322SRob Clark #define A6XX_TEX_CONST_8_BASE_HI__SHIFT 0 45422d756322SRob Clark static inline uint32_t A6XX_TEX_CONST_8_BASE_HI(uint32_t val) 45432d756322SRob Clark { 45442d756322SRob Clark return ((val) << A6XX_TEX_CONST_8_BASE_HI__SHIFT) & A6XX_TEX_CONST_8_BASE_HI__MASK; 45452d756322SRob Clark } 45462d756322SRob Clark 45472d756322SRob Clark #define REG_A6XX_TEX_CONST_9 0x00000009 45482d756322SRob Clark 45492d756322SRob Clark #define REG_A6XX_TEX_CONST_10 0x0000000a 45502d756322SRob Clark 45512d756322SRob Clark #define REG_A6XX_TEX_CONST_11 0x0000000b 45522d756322SRob Clark 45532d756322SRob Clark #define REG_A6XX_TEX_CONST_12 0x0000000c 45542d756322SRob Clark 45552d756322SRob Clark #define REG_A6XX_TEX_CONST_13 0x0000000d 45562d756322SRob Clark 45572d756322SRob Clark #define REG_A6XX_TEX_CONST_14 0x0000000e 45582d756322SRob Clark 45592d756322SRob Clark #define REG_A6XX_TEX_CONST_15 0x0000000f 45602d756322SRob Clark 45612d756322SRob Clark 45622d756322SRob Clark #endif /* A6XX_XML */ 4563