1 #ifndef A5XX_XML 2 #define A5XX_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27) 13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27) 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27) 15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-06-06 18:26:14) 16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27) 17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59) 18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 139480 bytes, from 2017-06-16 12:44:39) 19 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27) 20 21 Copyright (C) 2013-2017 by the following authors: 22 - Rob Clark <robdclark@gmail.com> (robclark) 23 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 24 25 Permission is hereby granted, free of charge, to any person obtaining 26 a copy of this software and associated documentation files (the 27 "Software"), to deal in the Software without restriction, including 28 without limitation the rights to use, copy, modify, merge, publish, 29 distribute, sublicense, and/or sell copies of the Software, and to 30 permit persons to whom the Software is furnished to do so, subject to 31 the following conditions: 32 33 The above copyright notice and this permission notice (including the 34 next paragraph) shall be included in all copies or substantial 35 portions of the Software. 36 37 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 38 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 39 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 40 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 41 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 42 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 43 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 44 */ 45 46 47 enum a5xx_color_fmt { 48 RB5_A8_UNORM = 2, 49 RB5_R8_UNORM = 3, 50 RB5_R8_SNORM = 4, 51 RB5_R8_UINT = 5, 52 RB5_R8_SINT = 6, 53 RB5_R4G4B4A4_UNORM = 8, 54 RB5_R5G5B5A1_UNORM = 10, 55 RB5_R5G6B5_UNORM = 14, 56 RB5_R8G8_UNORM = 15, 57 RB5_R8G8_SNORM = 16, 58 RB5_R8G8_UINT = 17, 59 RB5_R8G8_SINT = 18, 60 RB5_R16_UNORM = 21, 61 RB5_R16_SNORM = 22, 62 RB5_R16_FLOAT = 23, 63 RB5_R16_UINT = 24, 64 RB5_R16_SINT = 25, 65 RB5_R8G8B8A8_UNORM = 48, 66 RB5_R8G8B8_UNORM = 49, 67 RB5_R8G8B8A8_SNORM = 50, 68 RB5_R8G8B8A8_UINT = 51, 69 RB5_R8G8B8A8_SINT = 52, 70 RB5_R10G10B10A2_UNORM = 55, 71 RB5_R10G10B10A2_UINT = 58, 72 RB5_R11G11B10_FLOAT = 66, 73 RB5_R16G16_UNORM = 67, 74 RB5_R16G16_SNORM = 68, 75 RB5_R16G16_FLOAT = 69, 76 RB5_R16G16_UINT = 70, 77 RB5_R16G16_SINT = 71, 78 RB5_R32_FLOAT = 74, 79 RB5_R32_UINT = 75, 80 RB5_R32_SINT = 76, 81 RB5_R16G16B16A16_UNORM = 96, 82 RB5_R16G16B16A16_SNORM = 97, 83 RB5_R16G16B16A16_FLOAT = 98, 84 RB5_R16G16B16A16_UINT = 99, 85 RB5_R16G16B16A16_SINT = 100, 86 RB5_R32G32_FLOAT = 103, 87 RB5_R32G32_UINT = 104, 88 RB5_R32G32_SINT = 105, 89 RB5_R32G32B32A32_FLOAT = 130, 90 RB5_R32G32B32A32_UINT = 131, 91 RB5_R32G32B32A32_SINT = 132, 92 }; 93 94 enum a5xx_tile_mode { 95 TILE5_LINEAR = 0, 96 TILE5_2 = 2, 97 TILE5_3 = 3, 98 }; 99 100 enum a5xx_vtx_fmt { 101 VFMT5_8_UNORM = 3, 102 VFMT5_8_SNORM = 4, 103 VFMT5_8_UINT = 5, 104 VFMT5_8_SINT = 6, 105 VFMT5_8_8_UNORM = 15, 106 VFMT5_8_8_SNORM = 16, 107 VFMT5_8_8_UINT = 17, 108 VFMT5_8_8_SINT = 18, 109 VFMT5_16_UNORM = 21, 110 VFMT5_16_SNORM = 22, 111 VFMT5_16_FLOAT = 23, 112 VFMT5_16_UINT = 24, 113 VFMT5_16_SINT = 25, 114 VFMT5_8_8_8_UNORM = 33, 115 VFMT5_8_8_8_SNORM = 34, 116 VFMT5_8_8_8_UINT = 35, 117 VFMT5_8_8_8_SINT = 36, 118 VFMT5_8_8_8_8_UNORM = 48, 119 VFMT5_8_8_8_8_SNORM = 50, 120 VFMT5_8_8_8_8_UINT = 51, 121 VFMT5_8_8_8_8_SINT = 52, 122 VFMT5_16_16_UNORM = 67, 123 VFMT5_16_16_SNORM = 68, 124 VFMT5_16_16_FLOAT = 69, 125 VFMT5_16_16_UINT = 70, 126 VFMT5_16_16_SINT = 71, 127 VFMT5_32_UNORM = 72, 128 VFMT5_32_SNORM = 73, 129 VFMT5_32_FLOAT = 74, 130 VFMT5_32_UINT = 75, 131 VFMT5_32_SINT = 76, 132 VFMT5_32_FIXED = 77, 133 VFMT5_16_16_16_UNORM = 88, 134 VFMT5_16_16_16_SNORM = 89, 135 VFMT5_16_16_16_FLOAT = 90, 136 VFMT5_16_16_16_UINT = 91, 137 VFMT5_16_16_16_SINT = 92, 138 VFMT5_16_16_16_16_UNORM = 96, 139 VFMT5_16_16_16_16_SNORM = 97, 140 VFMT5_16_16_16_16_FLOAT = 98, 141 VFMT5_16_16_16_16_UINT = 99, 142 VFMT5_16_16_16_16_SINT = 100, 143 VFMT5_32_32_UNORM = 101, 144 VFMT5_32_32_SNORM = 102, 145 VFMT5_32_32_FLOAT = 103, 146 VFMT5_32_32_UINT = 104, 147 VFMT5_32_32_SINT = 105, 148 VFMT5_32_32_FIXED = 106, 149 VFMT5_32_32_32_UNORM = 112, 150 VFMT5_32_32_32_SNORM = 113, 151 VFMT5_32_32_32_UINT = 114, 152 VFMT5_32_32_32_SINT = 115, 153 VFMT5_32_32_32_FLOAT = 116, 154 VFMT5_32_32_32_FIXED = 117, 155 VFMT5_32_32_32_32_UNORM = 128, 156 VFMT5_32_32_32_32_SNORM = 129, 157 VFMT5_32_32_32_32_FLOAT = 130, 158 VFMT5_32_32_32_32_UINT = 131, 159 VFMT5_32_32_32_32_SINT = 132, 160 VFMT5_32_32_32_32_FIXED = 133, 161 }; 162 163 enum a5xx_tex_fmt { 164 TFMT5_A8_UNORM = 2, 165 TFMT5_8_UNORM = 3, 166 TFMT5_8_SNORM = 4, 167 TFMT5_8_UINT = 5, 168 TFMT5_8_SINT = 6, 169 TFMT5_4_4_4_4_UNORM = 8, 170 TFMT5_5_5_5_1_UNORM = 10, 171 TFMT5_5_6_5_UNORM = 14, 172 TFMT5_8_8_UNORM = 15, 173 TFMT5_8_8_SNORM = 16, 174 TFMT5_8_8_UINT = 17, 175 TFMT5_8_8_SINT = 18, 176 TFMT5_L8_A8_UNORM = 19, 177 TFMT5_16_UNORM = 21, 178 TFMT5_16_SNORM = 22, 179 TFMT5_16_FLOAT = 23, 180 TFMT5_16_UINT = 24, 181 TFMT5_16_SINT = 25, 182 TFMT5_8_8_8_8_UNORM = 48, 183 TFMT5_8_8_8_UNORM = 49, 184 TFMT5_8_8_8_8_SNORM = 50, 185 TFMT5_8_8_8_8_UINT = 51, 186 TFMT5_8_8_8_8_SINT = 52, 187 TFMT5_9_9_9_E5_FLOAT = 53, 188 TFMT5_10_10_10_2_UNORM = 54, 189 TFMT5_10_10_10_2_UINT = 58, 190 TFMT5_11_11_10_FLOAT = 66, 191 TFMT5_16_16_UNORM = 67, 192 TFMT5_16_16_SNORM = 68, 193 TFMT5_16_16_FLOAT = 69, 194 TFMT5_16_16_UINT = 70, 195 TFMT5_16_16_SINT = 71, 196 TFMT5_32_FLOAT = 74, 197 TFMT5_32_UINT = 75, 198 TFMT5_32_SINT = 76, 199 TFMT5_16_16_16_16_UNORM = 96, 200 TFMT5_16_16_16_16_SNORM = 97, 201 TFMT5_16_16_16_16_FLOAT = 98, 202 TFMT5_16_16_16_16_UINT = 99, 203 TFMT5_16_16_16_16_SINT = 100, 204 TFMT5_32_32_FLOAT = 103, 205 TFMT5_32_32_UINT = 104, 206 TFMT5_32_32_SINT = 105, 207 TFMT5_32_32_32_32_FLOAT = 130, 208 TFMT5_32_32_32_32_UINT = 131, 209 TFMT5_32_32_32_32_SINT = 132, 210 TFMT5_X8Z24_UNORM = 160, 211 TFMT5_RGTC1_UNORM = 183, 212 TFMT5_RGTC1_SNORM = 184, 213 TFMT5_RGTC2_UNORM = 187, 214 TFMT5_RGTC2_SNORM = 188, 215 }; 216 217 enum a5xx_tex_fetchsize { 218 TFETCH5_1_BYTE = 0, 219 TFETCH5_2_BYTE = 1, 220 TFETCH5_4_BYTE = 2, 221 TFETCH5_8_BYTE = 3, 222 TFETCH5_16_BYTE = 4, 223 }; 224 225 enum a5xx_depth_format { 226 DEPTH5_NONE = 0, 227 DEPTH5_16 = 1, 228 DEPTH5_24_8 = 2, 229 DEPTH5_32 = 4, 230 }; 231 232 enum a5xx_blit_buf { 233 BLIT_MRT0 = 0, 234 BLIT_MRT1 = 1, 235 BLIT_MRT2 = 2, 236 BLIT_MRT3 = 3, 237 BLIT_MRT4 = 4, 238 BLIT_MRT5 = 5, 239 BLIT_MRT6 = 6, 240 BLIT_MRT7 = 7, 241 BLIT_ZS = 8, 242 BLIT_Z32 = 9, 243 }; 244 245 enum a5xx_cp_perfcounter_select { 246 PERF_CP_ALWAYS_COUNT = 0, 247 PERF_CP_BUSY_GFX_CORE_IDLE = 1, 248 PERF_CP_BUSY_CYCLES = 2, 249 PERF_CP_PFP_IDLE = 3, 250 PERF_CP_PFP_BUSY_WORKING = 4, 251 PERF_CP_PFP_STALL_CYCLES_ANY = 5, 252 PERF_CP_PFP_STARVE_CYCLES_ANY = 6, 253 PERF_CP_PFP_ICACHE_MISS = 7, 254 PERF_CP_PFP_ICACHE_HIT = 8, 255 PERF_CP_PFP_MATCH_PM4_PKT_PROFILE = 9, 256 PERF_CP_ME_BUSY_WORKING = 10, 257 PERF_CP_ME_IDLE = 11, 258 PERF_CP_ME_STARVE_CYCLES_ANY = 12, 259 PERF_CP_ME_FIFO_EMPTY_PFP_IDLE = 13, 260 PERF_CP_ME_FIFO_EMPTY_PFP_BUSY = 14, 261 PERF_CP_ME_FIFO_FULL_ME_BUSY = 15, 262 PERF_CP_ME_FIFO_FULL_ME_NON_WORKING = 16, 263 PERF_CP_ME_STALL_CYCLES_ANY = 17, 264 PERF_CP_ME_ICACHE_MISS = 18, 265 PERF_CP_ME_ICACHE_HIT = 19, 266 PERF_CP_NUM_PREEMPTIONS = 20, 267 PERF_CP_PREEMPTION_REACTION_DELAY = 21, 268 PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 22, 269 PERF_CP_PREEMPTION_SWITCH_IN_TIME = 23, 270 PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 24, 271 PERF_CP_PREDICATED_DRAWS_KILLED = 25, 272 PERF_CP_MODE_SWITCH = 26, 273 PERF_CP_ZPASS_DONE = 27, 274 PERF_CP_CONTEXT_DONE = 28, 275 PERF_CP_CACHE_FLUSH = 29, 276 PERF_CP_LONG_PREEMPTIONS = 30, 277 }; 278 279 enum a5xx_rbbm_perfcounter_select { 280 PERF_RBBM_ALWAYS_COUNT = 0, 281 PERF_RBBM_ALWAYS_ON = 1, 282 PERF_RBBM_TSE_BUSY = 2, 283 PERF_RBBM_RAS_BUSY = 3, 284 PERF_RBBM_PC_DCALL_BUSY = 4, 285 PERF_RBBM_PC_VSD_BUSY = 5, 286 PERF_RBBM_STATUS_MASKED = 6, 287 PERF_RBBM_COM_BUSY = 7, 288 PERF_RBBM_DCOM_BUSY = 8, 289 PERF_RBBM_VBIF_BUSY = 9, 290 PERF_RBBM_VSC_BUSY = 10, 291 PERF_RBBM_TESS_BUSY = 11, 292 PERF_RBBM_UCHE_BUSY = 12, 293 PERF_RBBM_HLSQ_BUSY = 13, 294 }; 295 296 enum a5xx_pc_perfcounter_select { 297 PERF_PC_BUSY_CYCLES = 0, 298 PERF_PC_WORKING_CYCLES = 1, 299 PERF_PC_STALL_CYCLES_VFD = 2, 300 PERF_PC_STALL_CYCLES_TSE = 3, 301 PERF_PC_STALL_CYCLES_VPC = 4, 302 PERF_PC_STALL_CYCLES_UCHE = 5, 303 PERF_PC_STALL_CYCLES_TESS = 6, 304 PERF_PC_STALL_CYCLES_TSE_ONLY = 7, 305 PERF_PC_STALL_CYCLES_VPC_ONLY = 8, 306 PERF_PC_PASS1_TF_STALL_CYCLES = 9, 307 PERF_PC_STARVE_CYCLES_FOR_INDEX = 10, 308 PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11, 309 PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12, 310 PERF_PC_STARVE_CYCLES_FOR_POSITION = 13, 311 PERF_PC_STARVE_CYCLES_DI = 14, 312 PERF_PC_VIS_STREAMS_LOADED = 15, 313 PERF_PC_INSTANCES = 16, 314 PERF_PC_VPC_PRIMITIVES = 17, 315 PERF_PC_DEAD_PRIM = 18, 316 PERF_PC_LIVE_PRIM = 19, 317 PERF_PC_VERTEX_HITS = 20, 318 PERF_PC_IA_VERTICES = 21, 319 PERF_PC_IA_PRIMITIVES = 22, 320 PERF_PC_GS_PRIMITIVES = 23, 321 PERF_PC_HS_INVOCATIONS = 24, 322 PERF_PC_DS_INVOCATIONS = 25, 323 PERF_PC_VS_INVOCATIONS = 26, 324 PERF_PC_GS_INVOCATIONS = 27, 325 PERF_PC_DS_PRIMITIVES = 28, 326 PERF_PC_VPC_POS_DATA_TRANSACTION = 29, 327 PERF_PC_3D_DRAWCALLS = 30, 328 PERF_PC_2D_DRAWCALLS = 31, 329 PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32, 330 PERF_TESS_BUSY_CYCLES = 33, 331 PERF_TESS_WORKING_CYCLES = 34, 332 PERF_TESS_STALL_CYCLES_PC = 35, 333 PERF_TESS_STARVE_CYCLES_PC = 36, 334 }; 335 336 enum a5xx_vfd_perfcounter_select { 337 PERF_VFD_BUSY_CYCLES = 0, 338 PERF_VFD_STALL_CYCLES_UCHE = 1, 339 PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2, 340 PERF_VFD_STALL_CYCLES_MISS_VB = 3, 341 PERF_VFD_STALL_CYCLES_MISS_Q = 4, 342 PERF_VFD_STALL_CYCLES_SP_INFO = 5, 343 PERF_VFD_STALL_CYCLES_SP_ATTR = 6, 344 PERF_VFD_STALL_CYCLES_VFDP_VB = 7, 345 PERF_VFD_STALL_CYCLES_VFDP_Q = 8, 346 PERF_VFD_DECODER_PACKER_STALL = 9, 347 PERF_VFD_STARVE_CYCLES_UCHE = 10, 348 PERF_VFD_RBUFFER_FULL = 11, 349 PERF_VFD_ATTR_INFO_FIFO_FULL = 12, 350 PERF_VFD_DECODED_ATTRIBUTE_BYTES = 13, 351 PERF_VFD_NUM_ATTRIBUTES = 14, 352 PERF_VFD_INSTRUCTIONS = 15, 353 PERF_VFD_UPPER_SHADER_FIBERS = 16, 354 PERF_VFD_LOWER_SHADER_FIBERS = 17, 355 PERF_VFD_MODE_0_FIBERS = 18, 356 PERF_VFD_MODE_1_FIBERS = 19, 357 PERF_VFD_MODE_2_FIBERS = 20, 358 PERF_VFD_MODE_3_FIBERS = 21, 359 PERF_VFD_MODE_4_FIBERS = 22, 360 PERF_VFD_TOTAL_VERTICES = 23, 361 PERF_VFD_NUM_ATTR_MISS = 24, 362 PERF_VFD_1_BURST_REQ = 25, 363 PERF_VFDP_STALL_CYCLES_VFD = 26, 364 PERF_VFDP_STALL_CYCLES_VFD_INDEX = 27, 365 PERF_VFDP_STALL_CYCLES_VFD_PROG = 28, 366 PERF_VFDP_STARVE_CYCLES_PC = 29, 367 PERF_VFDP_VS_STAGE_32_WAVES = 30, 368 }; 369 370 enum a5xx_hlsq_perfcounter_select { 371 PERF_HLSQ_BUSY_CYCLES = 0, 372 PERF_HLSQ_STALL_CYCLES_UCHE = 1, 373 PERF_HLSQ_STALL_CYCLES_SP_STATE = 2, 374 PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3, 375 PERF_HLSQ_UCHE_LATENCY_CYCLES = 4, 376 PERF_HLSQ_UCHE_LATENCY_COUNT = 5, 377 PERF_HLSQ_FS_STAGE_32_WAVES = 6, 378 PERF_HLSQ_FS_STAGE_64_WAVES = 7, 379 PERF_HLSQ_QUADS = 8, 380 PERF_HLSQ_SP_STATE_COPY_TRANS_FS_STAGE = 9, 381 PERF_HLSQ_SP_STATE_COPY_TRANS_VS_STAGE = 10, 382 PERF_HLSQ_TP_STATE_COPY_TRANS_FS_STAGE = 11, 383 PERF_HLSQ_TP_STATE_COPY_TRANS_VS_STAGE = 12, 384 PERF_HLSQ_CS_INVOCATIONS = 13, 385 PERF_HLSQ_COMPUTE_DRAWCALLS = 14, 386 }; 387 388 enum a5xx_vpc_perfcounter_select { 389 PERF_VPC_BUSY_CYCLES = 0, 390 PERF_VPC_WORKING_CYCLES = 1, 391 PERF_VPC_STALL_CYCLES_UCHE = 2, 392 PERF_VPC_STALL_CYCLES_VFD_WACK = 3, 393 PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4, 394 PERF_VPC_STALL_CYCLES_PC = 5, 395 PERF_VPC_STALL_CYCLES_SP_LM = 6, 396 PERF_VPC_POS_EXPORT_STALL_CYCLES = 7, 397 PERF_VPC_STARVE_CYCLES_SP = 8, 398 PERF_VPC_STARVE_CYCLES_LRZ = 9, 399 PERF_VPC_PC_PRIMITIVES = 10, 400 PERF_VPC_SP_COMPONENTS = 11, 401 PERF_VPC_SP_LM_PRIMITIVES = 12, 402 PERF_VPC_SP_LM_COMPONENTS = 13, 403 PERF_VPC_SP_LM_DWORDS = 14, 404 PERF_VPC_STREAMOUT_COMPONENTS = 15, 405 PERF_VPC_GRANT_PHASES = 16, 406 }; 407 408 enum a5xx_tse_perfcounter_select { 409 PERF_TSE_BUSY_CYCLES = 0, 410 PERF_TSE_CLIPPING_CYCLES = 1, 411 PERF_TSE_STALL_CYCLES_RAS = 2, 412 PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3, 413 PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4, 414 PERF_TSE_STARVE_CYCLES_PC = 5, 415 PERF_TSE_INPUT_PRIM = 6, 416 PERF_TSE_INPUT_NULL_PRIM = 7, 417 PERF_TSE_TRIVAL_REJ_PRIM = 8, 418 PERF_TSE_CLIPPED_PRIM = 9, 419 PERF_TSE_ZERO_AREA_PRIM = 10, 420 PERF_TSE_FACENESS_CULLED_PRIM = 11, 421 PERF_TSE_ZERO_PIXEL_PRIM = 12, 422 PERF_TSE_OUTPUT_NULL_PRIM = 13, 423 PERF_TSE_OUTPUT_VISIBLE_PRIM = 14, 424 PERF_TSE_CINVOCATION = 15, 425 PERF_TSE_CPRIMITIVES = 16, 426 PERF_TSE_2D_INPUT_PRIM = 17, 427 PERF_TSE_2D_ALIVE_CLCLES = 18, 428 }; 429 430 enum a5xx_ras_perfcounter_select { 431 PERF_RAS_BUSY_CYCLES = 0, 432 PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1, 433 PERF_RAS_STALL_CYCLES_LRZ = 2, 434 PERF_RAS_STARVE_CYCLES_TSE = 3, 435 PERF_RAS_SUPER_TILES = 4, 436 PERF_RAS_8X4_TILES = 5, 437 PERF_RAS_MASKGEN_ACTIVE = 6, 438 PERF_RAS_FULLY_COVERED_SUPER_TILES = 7, 439 PERF_RAS_FULLY_COVERED_8X4_TILES = 8, 440 PERF_RAS_PRIM_KILLED_INVISILBE = 9, 441 }; 442 443 enum a5xx_lrz_perfcounter_select { 444 PERF_LRZ_BUSY_CYCLES = 0, 445 PERF_LRZ_STARVE_CYCLES_RAS = 1, 446 PERF_LRZ_STALL_CYCLES_RB = 2, 447 PERF_LRZ_STALL_CYCLES_VSC = 3, 448 PERF_LRZ_STALL_CYCLES_VPC = 4, 449 PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5, 450 PERF_LRZ_STALL_CYCLES_UCHE = 6, 451 PERF_LRZ_LRZ_READ = 7, 452 PERF_LRZ_LRZ_WRITE = 8, 453 PERF_LRZ_READ_LATENCY = 9, 454 PERF_LRZ_MERGE_CACHE_UPDATING = 10, 455 PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11, 456 PERF_LRZ_PRIM_KILLED_BY_LRZ = 12, 457 PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13, 458 PERF_LRZ_FULL_8X8_TILES = 14, 459 PERF_LRZ_PARTIAL_8X8_TILES = 15, 460 PERF_LRZ_TILE_KILLED = 16, 461 PERF_LRZ_TOTAL_PIXEL = 17, 462 PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18, 463 }; 464 465 enum a5xx_uche_perfcounter_select { 466 PERF_UCHE_BUSY_CYCLES = 0, 467 PERF_UCHE_STALL_CYCLES_VBIF = 1, 468 PERF_UCHE_VBIF_LATENCY_CYCLES = 2, 469 PERF_UCHE_VBIF_LATENCY_SAMPLES = 3, 470 PERF_UCHE_VBIF_READ_BEATS_TP = 4, 471 PERF_UCHE_VBIF_READ_BEATS_VFD = 5, 472 PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6, 473 PERF_UCHE_VBIF_READ_BEATS_LRZ = 7, 474 PERF_UCHE_VBIF_READ_BEATS_SP = 8, 475 PERF_UCHE_READ_REQUESTS_TP = 9, 476 PERF_UCHE_READ_REQUESTS_VFD = 10, 477 PERF_UCHE_READ_REQUESTS_HLSQ = 11, 478 PERF_UCHE_READ_REQUESTS_LRZ = 12, 479 PERF_UCHE_READ_REQUESTS_SP = 13, 480 PERF_UCHE_WRITE_REQUESTS_LRZ = 14, 481 PERF_UCHE_WRITE_REQUESTS_SP = 15, 482 PERF_UCHE_WRITE_REQUESTS_VPC = 16, 483 PERF_UCHE_WRITE_REQUESTS_VSC = 17, 484 PERF_UCHE_EVICTS = 18, 485 PERF_UCHE_BANK_REQ0 = 19, 486 PERF_UCHE_BANK_REQ1 = 20, 487 PERF_UCHE_BANK_REQ2 = 21, 488 PERF_UCHE_BANK_REQ3 = 22, 489 PERF_UCHE_BANK_REQ4 = 23, 490 PERF_UCHE_BANK_REQ5 = 24, 491 PERF_UCHE_BANK_REQ6 = 25, 492 PERF_UCHE_BANK_REQ7 = 26, 493 PERF_UCHE_VBIF_READ_BEATS_CH0 = 27, 494 PERF_UCHE_VBIF_READ_BEATS_CH1 = 28, 495 PERF_UCHE_GMEM_READ_BEATS = 29, 496 PERF_UCHE_FLAG_COUNT = 30, 497 }; 498 499 enum a5xx_tp_perfcounter_select { 500 PERF_TP_BUSY_CYCLES = 0, 501 PERF_TP_STALL_CYCLES_UCHE = 1, 502 PERF_TP_LATENCY_CYCLES = 2, 503 PERF_TP_LATENCY_TRANS = 3, 504 PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4, 505 PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5, 506 PERF_TP_L1_CACHELINE_REQUESTS = 6, 507 PERF_TP_L1_CACHELINE_MISSES = 7, 508 PERF_TP_SP_TP_TRANS = 8, 509 PERF_TP_TP_SP_TRANS = 9, 510 PERF_TP_OUTPUT_PIXELS = 10, 511 PERF_TP_FILTER_WORKLOAD_16BIT = 11, 512 PERF_TP_FILTER_WORKLOAD_32BIT = 12, 513 PERF_TP_QUADS_RECEIVED = 13, 514 PERF_TP_QUADS_OFFSET = 14, 515 PERF_TP_QUADS_SHADOW = 15, 516 PERF_TP_QUADS_ARRAY = 16, 517 PERF_TP_QUADS_GRADIENT = 17, 518 PERF_TP_QUADS_1D = 18, 519 PERF_TP_QUADS_2D = 19, 520 PERF_TP_QUADS_BUFFER = 20, 521 PERF_TP_QUADS_3D = 21, 522 PERF_TP_QUADS_CUBE = 22, 523 PERF_TP_STATE_CACHE_REQUESTS = 23, 524 PERF_TP_STATE_CACHE_MISSES = 24, 525 PERF_TP_DIVERGENT_QUADS_RECEIVED = 25, 526 PERF_TP_BINDLESS_STATE_CACHE_REQUESTS = 26, 527 PERF_TP_BINDLESS_STATE_CACHE_MISSES = 27, 528 PERF_TP_PRT_NON_RESIDENT_EVENTS = 28, 529 PERF_TP_OUTPUT_PIXELS_POINT = 29, 530 PERF_TP_OUTPUT_PIXELS_BILINEAR = 30, 531 PERF_TP_OUTPUT_PIXELS_MIP = 31, 532 PERF_TP_OUTPUT_PIXELS_ANISO = 32, 533 PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 33, 534 PERF_TP_FLAG_CACHE_REQUESTS = 34, 535 PERF_TP_FLAG_CACHE_MISSES = 35, 536 PERF_TP_L1_5_L2_REQUESTS = 36, 537 PERF_TP_2D_OUTPUT_PIXELS = 37, 538 PERF_TP_2D_OUTPUT_PIXELS_POINT = 38, 539 PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 39, 540 PERF_TP_2D_FILTER_WORKLOAD_16BIT = 40, 541 PERF_TP_2D_FILTER_WORKLOAD_32BIT = 41, 542 }; 543 544 enum a5xx_sp_perfcounter_select { 545 PERF_SP_BUSY_CYCLES = 0, 546 PERF_SP_ALU_WORKING_CYCLES = 1, 547 PERF_SP_EFU_WORKING_CYCLES = 2, 548 PERF_SP_STALL_CYCLES_VPC = 3, 549 PERF_SP_STALL_CYCLES_TP = 4, 550 PERF_SP_STALL_CYCLES_UCHE = 5, 551 PERF_SP_STALL_CYCLES_RB = 6, 552 PERF_SP_SCHEDULER_NON_WORKING = 7, 553 PERF_SP_WAVE_CONTEXTS = 8, 554 PERF_SP_WAVE_CONTEXT_CYCLES = 9, 555 PERF_SP_FS_STAGE_WAVE_CYCLES = 10, 556 PERF_SP_FS_STAGE_WAVE_SAMPLES = 11, 557 PERF_SP_VS_STAGE_WAVE_CYCLES = 12, 558 PERF_SP_VS_STAGE_WAVE_SAMPLES = 13, 559 PERF_SP_FS_STAGE_DURATION_CYCLES = 14, 560 PERF_SP_VS_STAGE_DURATION_CYCLES = 15, 561 PERF_SP_WAVE_CTRL_CYCLES = 16, 562 PERF_SP_WAVE_LOAD_CYCLES = 17, 563 PERF_SP_WAVE_EMIT_CYCLES = 18, 564 PERF_SP_WAVE_NOP_CYCLES = 19, 565 PERF_SP_WAVE_WAIT_CYCLES = 20, 566 PERF_SP_WAVE_FETCH_CYCLES = 21, 567 PERF_SP_WAVE_IDLE_CYCLES = 22, 568 PERF_SP_WAVE_END_CYCLES = 23, 569 PERF_SP_WAVE_LONG_SYNC_CYCLES = 24, 570 PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25, 571 PERF_SP_WAVE_JOIN_CYCLES = 26, 572 PERF_SP_LM_LOAD_INSTRUCTIONS = 27, 573 PERF_SP_LM_STORE_INSTRUCTIONS = 28, 574 PERF_SP_LM_ATOMICS = 29, 575 PERF_SP_GM_LOAD_INSTRUCTIONS = 30, 576 PERF_SP_GM_STORE_INSTRUCTIONS = 31, 577 PERF_SP_GM_ATOMICS = 32, 578 PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33, 579 PERF_SP_VS_STAGE_CFLOW_INSTRUCTIONS = 34, 580 PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 35, 581 PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 36, 582 PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 37, 583 PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 38, 584 PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 39, 585 PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 40, 586 PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 41, 587 PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 42, 588 PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 43, 589 PERF_SP_VS_INSTRUCTIONS = 44, 590 PERF_SP_FS_INSTRUCTIONS = 45, 591 PERF_SP_ADDR_LOCK_COUNT = 46, 592 PERF_SP_UCHE_READ_TRANS = 47, 593 PERF_SP_UCHE_WRITE_TRANS = 48, 594 PERF_SP_EXPORT_VPC_TRANS = 49, 595 PERF_SP_EXPORT_RB_TRANS = 50, 596 PERF_SP_PIXELS_KILLED = 51, 597 PERF_SP_ICL1_REQUESTS = 52, 598 PERF_SP_ICL1_MISSES = 53, 599 PERF_SP_ICL0_REQUESTS = 54, 600 PERF_SP_ICL0_MISSES = 55, 601 PERF_SP_HS_INSTRUCTIONS = 56, 602 PERF_SP_DS_INSTRUCTIONS = 57, 603 PERF_SP_GS_INSTRUCTIONS = 58, 604 PERF_SP_CS_INSTRUCTIONS = 59, 605 PERF_SP_GPR_READ = 60, 606 PERF_SP_GPR_WRITE = 61, 607 PERF_SP_LM_CH0_REQUESTS = 62, 608 PERF_SP_LM_CH1_REQUESTS = 63, 609 PERF_SP_LM_BANK_CONFLICTS = 64, 610 }; 611 612 enum a5xx_rb_perfcounter_select { 613 PERF_RB_BUSY_CYCLES = 0, 614 PERF_RB_STALL_CYCLES_CCU = 1, 615 PERF_RB_STALL_CYCLES_HLSQ = 2, 616 PERF_RB_STALL_CYCLES_FIFO0_FULL = 3, 617 PERF_RB_STALL_CYCLES_FIFO1_FULL = 4, 618 PERF_RB_STALL_CYCLES_FIFO2_FULL = 5, 619 PERF_RB_STARVE_CYCLES_SP = 6, 620 PERF_RB_STARVE_CYCLES_LRZ_TILE = 7, 621 PERF_RB_STARVE_CYCLES_CCU = 8, 622 PERF_RB_STARVE_CYCLES_Z_PLANE = 9, 623 PERF_RB_STARVE_CYCLES_BARY_PLANE = 10, 624 PERF_RB_Z_WORKLOAD = 11, 625 PERF_RB_HLSQ_ACTIVE = 12, 626 PERF_RB_Z_READ = 13, 627 PERF_RB_Z_WRITE = 14, 628 PERF_RB_C_READ = 15, 629 PERF_RB_C_WRITE = 16, 630 PERF_RB_TOTAL_PASS = 17, 631 PERF_RB_Z_PASS = 18, 632 PERF_RB_Z_FAIL = 19, 633 PERF_RB_S_FAIL = 20, 634 PERF_RB_BLENDED_FXP_COMPONENTS = 21, 635 PERF_RB_BLENDED_FP16_COMPONENTS = 22, 636 RB_RESERVED = 23, 637 PERF_RB_2D_ALIVE_CYCLES = 24, 638 PERF_RB_2D_STALL_CYCLES_A2D = 25, 639 PERF_RB_2D_STARVE_CYCLES_SRC = 26, 640 PERF_RB_2D_STARVE_CYCLES_SP = 27, 641 PERF_RB_2D_STARVE_CYCLES_DST = 28, 642 PERF_RB_2D_VALID_PIXELS = 29, 643 }; 644 645 enum a5xx_rb_samples_perfcounter_select { 646 TOTAL_SAMPLES = 0, 647 ZPASS_SAMPLES = 1, 648 ZFAIL_SAMPLES = 2, 649 SFAIL_SAMPLES = 3, 650 }; 651 652 enum a5xx_vsc_perfcounter_select { 653 PERF_VSC_BUSY_CYCLES = 0, 654 PERF_VSC_WORKING_CYCLES = 1, 655 PERF_VSC_STALL_CYCLES_UCHE = 2, 656 PERF_VSC_EOT_NUM = 3, 657 }; 658 659 enum a5xx_ccu_perfcounter_select { 660 PERF_CCU_BUSY_CYCLES = 0, 661 PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1, 662 PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2, 663 PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3, 664 PERF_CCU_DEPTH_BLOCKS = 4, 665 PERF_CCU_COLOR_BLOCKS = 5, 666 PERF_CCU_DEPTH_BLOCK_HIT = 6, 667 PERF_CCU_COLOR_BLOCK_HIT = 7, 668 PERF_CCU_PARTIAL_BLOCK_READ = 8, 669 PERF_CCU_GMEM_READ = 9, 670 PERF_CCU_GMEM_WRITE = 10, 671 PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11, 672 PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12, 673 PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13, 674 PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14, 675 PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15, 676 PERF_CCU_COLOR_READ_FLAG0_COUNT = 16, 677 PERF_CCU_COLOR_READ_FLAG1_COUNT = 17, 678 PERF_CCU_COLOR_READ_FLAG2_COUNT = 18, 679 PERF_CCU_COLOR_READ_FLAG3_COUNT = 19, 680 PERF_CCU_COLOR_READ_FLAG4_COUNT = 20, 681 PERF_CCU_2D_BUSY_CYCLES = 21, 682 PERF_CCU_2D_RD_REQ = 22, 683 PERF_CCU_2D_WR_REQ = 23, 684 PERF_CCU_2D_REORDER_STARVE_CYCLES = 24, 685 PERF_CCU_2D_PIXELS = 25, 686 }; 687 688 enum a5xx_cmp_perfcounter_select { 689 PERF_CMPDECMP_STALL_CYCLES_VBIF = 0, 690 PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1, 691 PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2, 692 PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3, 693 PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4, 694 PERF_CMPDECMP_VBIF_READ_REQUEST = 5, 695 PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6, 696 PERF_CMPDECMP_VBIF_READ_DATA = 7, 697 PERF_CMPDECMP_VBIF_WRITE_DATA = 8, 698 PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9, 699 PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10, 700 PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11, 701 PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12, 702 PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13, 703 PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14, 704 PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 15, 705 PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 16, 706 PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 17, 707 PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 18, 708 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 19, 709 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 20, 710 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 21, 711 PERF_CMPDECMP_2D_RD_DATA = 22, 712 PERF_CMPDECMP_2D_WR_DATA = 23, 713 }; 714 715 enum a5xx_vbif_perfcounter_select { 716 AXI_READ_REQUESTS_ID_0 = 0, 717 AXI_READ_REQUESTS_ID_1 = 1, 718 AXI_READ_REQUESTS_ID_2 = 2, 719 AXI_READ_REQUESTS_ID_3 = 3, 720 AXI_READ_REQUESTS_ID_4 = 4, 721 AXI_READ_REQUESTS_ID_5 = 5, 722 AXI_READ_REQUESTS_ID_6 = 6, 723 AXI_READ_REQUESTS_ID_7 = 7, 724 AXI_READ_REQUESTS_ID_8 = 8, 725 AXI_READ_REQUESTS_ID_9 = 9, 726 AXI_READ_REQUESTS_ID_10 = 10, 727 AXI_READ_REQUESTS_ID_11 = 11, 728 AXI_READ_REQUESTS_ID_12 = 12, 729 AXI_READ_REQUESTS_ID_13 = 13, 730 AXI_READ_REQUESTS_ID_14 = 14, 731 AXI_READ_REQUESTS_ID_15 = 15, 732 AXI0_READ_REQUESTS_TOTAL = 16, 733 AXI1_READ_REQUESTS_TOTAL = 17, 734 AXI2_READ_REQUESTS_TOTAL = 18, 735 AXI3_READ_REQUESTS_TOTAL = 19, 736 AXI_READ_REQUESTS_TOTAL = 20, 737 AXI_WRITE_REQUESTS_ID_0 = 21, 738 AXI_WRITE_REQUESTS_ID_1 = 22, 739 AXI_WRITE_REQUESTS_ID_2 = 23, 740 AXI_WRITE_REQUESTS_ID_3 = 24, 741 AXI_WRITE_REQUESTS_ID_4 = 25, 742 AXI_WRITE_REQUESTS_ID_5 = 26, 743 AXI_WRITE_REQUESTS_ID_6 = 27, 744 AXI_WRITE_REQUESTS_ID_7 = 28, 745 AXI_WRITE_REQUESTS_ID_8 = 29, 746 AXI_WRITE_REQUESTS_ID_9 = 30, 747 AXI_WRITE_REQUESTS_ID_10 = 31, 748 AXI_WRITE_REQUESTS_ID_11 = 32, 749 AXI_WRITE_REQUESTS_ID_12 = 33, 750 AXI_WRITE_REQUESTS_ID_13 = 34, 751 AXI_WRITE_REQUESTS_ID_14 = 35, 752 AXI_WRITE_REQUESTS_ID_15 = 36, 753 AXI0_WRITE_REQUESTS_TOTAL = 37, 754 AXI1_WRITE_REQUESTS_TOTAL = 38, 755 AXI2_WRITE_REQUESTS_TOTAL = 39, 756 AXI3_WRITE_REQUESTS_TOTAL = 40, 757 AXI_WRITE_REQUESTS_TOTAL = 41, 758 AXI_TOTAL_REQUESTS = 42, 759 AXI_READ_DATA_BEATS_ID_0 = 43, 760 AXI_READ_DATA_BEATS_ID_1 = 44, 761 AXI_READ_DATA_BEATS_ID_2 = 45, 762 AXI_READ_DATA_BEATS_ID_3 = 46, 763 AXI_READ_DATA_BEATS_ID_4 = 47, 764 AXI_READ_DATA_BEATS_ID_5 = 48, 765 AXI_READ_DATA_BEATS_ID_6 = 49, 766 AXI_READ_DATA_BEATS_ID_7 = 50, 767 AXI_READ_DATA_BEATS_ID_8 = 51, 768 AXI_READ_DATA_BEATS_ID_9 = 52, 769 AXI_READ_DATA_BEATS_ID_10 = 53, 770 AXI_READ_DATA_BEATS_ID_11 = 54, 771 AXI_READ_DATA_BEATS_ID_12 = 55, 772 AXI_READ_DATA_BEATS_ID_13 = 56, 773 AXI_READ_DATA_BEATS_ID_14 = 57, 774 AXI_READ_DATA_BEATS_ID_15 = 58, 775 AXI0_READ_DATA_BEATS_TOTAL = 59, 776 AXI1_READ_DATA_BEATS_TOTAL = 60, 777 AXI2_READ_DATA_BEATS_TOTAL = 61, 778 AXI3_READ_DATA_BEATS_TOTAL = 62, 779 AXI_READ_DATA_BEATS_TOTAL = 63, 780 AXI_WRITE_DATA_BEATS_ID_0 = 64, 781 AXI_WRITE_DATA_BEATS_ID_1 = 65, 782 AXI_WRITE_DATA_BEATS_ID_2 = 66, 783 AXI_WRITE_DATA_BEATS_ID_3 = 67, 784 AXI_WRITE_DATA_BEATS_ID_4 = 68, 785 AXI_WRITE_DATA_BEATS_ID_5 = 69, 786 AXI_WRITE_DATA_BEATS_ID_6 = 70, 787 AXI_WRITE_DATA_BEATS_ID_7 = 71, 788 AXI_WRITE_DATA_BEATS_ID_8 = 72, 789 AXI_WRITE_DATA_BEATS_ID_9 = 73, 790 AXI_WRITE_DATA_BEATS_ID_10 = 74, 791 AXI_WRITE_DATA_BEATS_ID_11 = 75, 792 AXI_WRITE_DATA_BEATS_ID_12 = 76, 793 AXI_WRITE_DATA_BEATS_ID_13 = 77, 794 AXI_WRITE_DATA_BEATS_ID_14 = 78, 795 AXI_WRITE_DATA_BEATS_ID_15 = 79, 796 AXI0_WRITE_DATA_BEATS_TOTAL = 80, 797 AXI1_WRITE_DATA_BEATS_TOTAL = 81, 798 AXI2_WRITE_DATA_BEATS_TOTAL = 82, 799 AXI3_WRITE_DATA_BEATS_TOTAL = 83, 800 AXI_WRITE_DATA_BEATS_TOTAL = 84, 801 AXI_DATA_BEATS_TOTAL = 85, 802 }; 803 804 enum a5xx_tex_filter { 805 A5XX_TEX_NEAREST = 0, 806 A5XX_TEX_LINEAR = 1, 807 A5XX_TEX_ANISO = 2, 808 }; 809 810 enum a5xx_tex_clamp { 811 A5XX_TEX_REPEAT = 0, 812 A5XX_TEX_CLAMP_TO_EDGE = 1, 813 A5XX_TEX_MIRROR_REPEAT = 2, 814 A5XX_TEX_CLAMP_TO_BORDER = 3, 815 A5XX_TEX_MIRROR_CLAMP = 4, 816 }; 817 818 enum a5xx_tex_aniso { 819 A5XX_TEX_ANISO_1 = 0, 820 A5XX_TEX_ANISO_2 = 1, 821 A5XX_TEX_ANISO_4 = 2, 822 A5XX_TEX_ANISO_8 = 3, 823 A5XX_TEX_ANISO_16 = 4, 824 }; 825 826 enum a5xx_tex_swiz { 827 A5XX_TEX_X = 0, 828 A5XX_TEX_Y = 1, 829 A5XX_TEX_Z = 2, 830 A5XX_TEX_W = 3, 831 A5XX_TEX_ZERO = 4, 832 A5XX_TEX_ONE = 5, 833 }; 834 835 enum a5xx_tex_type { 836 A5XX_TEX_1D = 0, 837 A5XX_TEX_2D = 1, 838 A5XX_TEX_CUBE = 2, 839 A5XX_TEX_3D = 3, 840 }; 841 842 #define A5XX_INT0_RBBM_GPU_IDLE 0x00000001 843 #define A5XX_INT0_RBBM_AHB_ERROR 0x00000002 844 #define A5XX_INT0_RBBM_TRANSFER_TIMEOUT 0x00000004 845 #define A5XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 846 #define A5XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 847 #define A5XX_INT0_RBBM_ETS_MS_TIMEOUT 0x00000020 848 #define A5XX_INT0_RBBM_ATB_ASYNC_OVERFLOW 0x00000040 849 #define A5XX_INT0_RBBM_GPC_ERROR 0x00000080 850 #define A5XX_INT0_CP_SW 0x00000100 851 #define A5XX_INT0_CP_HW_ERROR 0x00000200 852 #define A5XX_INT0_CP_CCU_FLUSH_DEPTH_TS 0x00000400 853 #define A5XX_INT0_CP_CCU_FLUSH_COLOR_TS 0x00000800 854 #define A5XX_INT0_CP_CCU_RESOLVE_TS 0x00001000 855 #define A5XX_INT0_CP_IB2 0x00002000 856 #define A5XX_INT0_CP_IB1 0x00004000 857 #define A5XX_INT0_CP_RB 0x00008000 858 #define A5XX_INT0_CP_UNUSED_1 0x00010000 859 #define A5XX_INT0_CP_RB_DONE_TS 0x00020000 860 #define A5XX_INT0_CP_WT_DONE_TS 0x00040000 861 #define A5XX_INT0_UNKNOWN_1 0x00080000 862 #define A5XX_INT0_CP_CACHE_FLUSH_TS 0x00100000 863 #define A5XX_INT0_UNUSED_2 0x00200000 864 #define A5XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00400000 865 #define A5XX_INT0_MISC_HANG_DETECT 0x00800000 866 #define A5XX_INT0_UCHE_OOB_ACCESS 0x01000000 867 #define A5XX_INT0_UCHE_TRAP_INTR 0x02000000 868 #define A5XX_INT0_DEBBUS_INTR_0 0x04000000 869 #define A5XX_INT0_DEBBUS_INTR_1 0x08000000 870 #define A5XX_INT0_GPMU_VOLTAGE_DROOP 0x10000000 871 #define A5XX_INT0_GPMU_FIRMWARE 0x20000000 872 #define A5XX_INT0_ISDB_CPU_IRQ 0x40000000 873 #define A5XX_INT0_ISDB_UNDER_DEBUG 0x80000000 874 #define A5XX_CP_INT_CP_OPCODE_ERROR 0x00000001 875 #define A5XX_CP_INT_CP_RESERVED_BIT_ERROR 0x00000002 876 #define A5XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004 877 #define A5XX_CP_INT_CP_DMA_ERROR 0x00000008 878 #define A5XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010 879 #define A5XX_CP_INT_CP_AHB_ERROR 0x00000020 880 #define REG_A5XX_CP_RB_BASE 0x00000800 881 882 #define REG_A5XX_CP_RB_BASE_HI 0x00000801 883 884 #define REG_A5XX_CP_RB_CNTL 0x00000802 885 886 #define REG_A5XX_CP_RB_RPTR_ADDR 0x00000804 887 888 #define REG_A5XX_CP_RB_RPTR_ADDR_HI 0x00000805 889 890 #define REG_A5XX_CP_RB_RPTR 0x00000806 891 892 #define REG_A5XX_CP_RB_WPTR 0x00000807 893 894 #define REG_A5XX_CP_PFP_STAT_ADDR 0x00000808 895 896 #define REG_A5XX_CP_PFP_STAT_DATA 0x00000809 897 898 #define REG_A5XX_CP_DRAW_STATE_ADDR 0x0000080b 899 900 #define REG_A5XX_CP_DRAW_STATE_DATA 0x0000080c 901 902 #define REG_A5XX_CP_CRASH_SCRIPT_BASE_LO 0x00000817 903 904 #define REG_A5XX_CP_CRASH_SCRIPT_BASE_HI 0x00000818 905 906 #define REG_A5XX_CP_CRASH_DUMP_CNTL 0x00000819 907 908 #define REG_A5XX_CP_ME_STAT_ADDR 0x0000081a 909 910 #define REG_A5XX_CP_ROQ_THRESHOLDS_1 0x0000081f 911 912 #define REG_A5XX_CP_ROQ_THRESHOLDS_2 0x00000820 913 914 #define REG_A5XX_CP_ROQ_DBG_ADDR 0x00000821 915 916 #define REG_A5XX_CP_ROQ_DBG_DATA 0x00000822 917 918 #define REG_A5XX_CP_MEQ_DBG_ADDR 0x00000823 919 920 #define REG_A5XX_CP_MEQ_DBG_DATA 0x00000824 921 922 #define REG_A5XX_CP_MEQ_THRESHOLDS 0x00000825 923 924 #define REG_A5XX_CP_MERCIU_SIZE 0x00000826 925 926 #define REG_A5XX_CP_MERCIU_DBG_ADDR 0x00000827 927 928 #define REG_A5XX_CP_MERCIU_DBG_DATA_1 0x00000828 929 930 #define REG_A5XX_CP_MERCIU_DBG_DATA_2 0x00000829 931 932 #define REG_A5XX_CP_PFP_UCODE_DBG_ADDR 0x0000082a 933 934 #define REG_A5XX_CP_PFP_UCODE_DBG_DATA 0x0000082b 935 936 #define REG_A5XX_CP_ME_UCODE_DBG_ADDR 0x0000082f 937 938 #define REG_A5XX_CP_ME_UCODE_DBG_DATA 0x00000830 939 940 #define REG_A5XX_CP_CNTL 0x00000831 941 942 #define REG_A5XX_CP_PFP_ME_CNTL 0x00000832 943 944 #define REG_A5XX_CP_CHICKEN_DBG 0x00000833 945 946 #define REG_A5XX_CP_PFP_INSTR_BASE_LO 0x00000835 947 948 #define REG_A5XX_CP_PFP_INSTR_BASE_HI 0x00000836 949 950 #define REG_A5XX_CP_ME_INSTR_BASE_LO 0x00000838 951 952 #define REG_A5XX_CP_ME_INSTR_BASE_HI 0x00000839 953 954 #define REG_A5XX_CP_CONTEXT_SWITCH_CNTL 0x0000083b 955 956 #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO 0x0000083c 957 958 #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI 0x0000083d 959 960 #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO 0x0000083e 961 962 #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_HI 0x0000083f 963 964 #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x00000840 965 966 #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x00000841 967 968 #define REG_A5XX_CP_ADDR_MODE_CNTL 0x00000860 969 970 #define REG_A5XX_CP_ME_STAT_DATA 0x00000b14 971 972 #define REG_A5XX_CP_WFI_PEND_CTR 0x00000b15 973 974 #define REG_A5XX_CP_INTERRUPT_STATUS 0x00000b18 975 976 #define REG_A5XX_CP_HW_FAULT 0x00000b1a 977 978 #define REG_A5XX_CP_PROTECT_STATUS 0x00000b1c 979 980 #define REG_A5XX_CP_IB1_BASE 0x00000b1f 981 982 #define REG_A5XX_CP_IB1_BASE_HI 0x00000b20 983 984 #define REG_A5XX_CP_IB1_BUFSZ 0x00000b21 985 986 #define REG_A5XX_CP_IB2_BASE 0x00000b22 987 988 #define REG_A5XX_CP_IB2_BASE_HI 0x00000b23 989 990 #define REG_A5XX_CP_IB2_BUFSZ 0x00000b24 991 992 static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0) { return 0x00000b78 + 0x1*i0; } 993 994 static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; } 995 996 static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0) { return 0x00000880 + 0x1*i0; } 997 998 static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; } 999 #define A5XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff 1000 #define A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0 1001 static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) 1002 { 1003 return ((val) << A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A5XX_CP_PROTECT_REG_BASE_ADDR__MASK; 1004 } 1005 #define A5XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000 1006 #define A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24 1007 static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) 1008 { 1009 return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK; 1010 } 1011 #define A5XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000 1012 #define A5XX_CP_PROTECT_REG_TRAP_READ 0x40000000 1013 1014 #define REG_A5XX_CP_PROTECT_CNTL 0x000008a0 1015 1016 #define REG_A5XX_CP_AHB_FAULT 0x00000b1b 1017 1018 #define REG_A5XX_CP_PERFCTR_CP_SEL_0 0x00000bb0 1019 1020 #define REG_A5XX_CP_PERFCTR_CP_SEL_1 0x00000bb1 1021 1022 #define REG_A5XX_CP_PERFCTR_CP_SEL_2 0x00000bb2 1023 1024 #define REG_A5XX_CP_PERFCTR_CP_SEL_3 0x00000bb3 1025 1026 #define REG_A5XX_CP_PERFCTR_CP_SEL_4 0x00000bb4 1027 1028 #define REG_A5XX_CP_PERFCTR_CP_SEL_5 0x00000bb5 1029 1030 #define REG_A5XX_CP_PERFCTR_CP_SEL_6 0x00000bb6 1031 1032 #define REG_A5XX_CP_PERFCTR_CP_SEL_7 0x00000bb7 1033 1034 #define REG_A5XX_VSC_ADDR_MODE_CNTL 0x00000bc1 1035 1036 #define REG_A5XX_CP_POWERCTR_CP_SEL_0 0x00000bba 1037 1038 #define REG_A5XX_CP_POWERCTR_CP_SEL_1 0x00000bbb 1039 1040 #define REG_A5XX_CP_POWERCTR_CP_SEL_2 0x00000bbc 1041 1042 #define REG_A5XX_CP_POWERCTR_CP_SEL_3 0x00000bbd 1043 1044 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_A 0x00000004 1045 1046 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_B 0x00000005 1047 1048 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_C 0x00000006 1049 1050 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_D 0x00000007 1051 1052 #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLT 0x00000008 1053 1054 #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLM 0x00000009 1055 1056 #define REG_A5XX_RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT 0x00000018 1057 1058 #define REG_A5XX_RBBM_CFG_DBGBUS_OPL 0x0000000a 1059 1060 #define REG_A5XX_RBBM_CFG_DBGBUS_OPE 0x0000000b 1061 1062 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_0 0x0000000c 1063 1064 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_1 0x0000000d 1065 1066 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_2 0x0000000e 1067 1068 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_3 0x0000000f 1069 1070 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_0 0x00000010 1071 1072 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_1 0x00000011 1073 1074 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_2 0x00000012 1075 1076 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_3 0x00000013 1077 1078 #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_0 0x00000014 1079 1080 #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_1 0x00000015 1081 1082 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_0 0x00000016 1083 1084 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_1 0x00000017 1085 1086 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_2 0x00000018 1087 1088 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_3 0x00000019 1089 1090 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_0 0x0000001a 1091 1092 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_1 0x0000001b 1093 1094 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_2 0x0000001c 1095 1096 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_3 0x0000001d 1097 1098 #define REG_A5XX_RBBM_CFG_DBGBUS_NIBBLEE 0x0000001e 1099 1100 #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC0 0x0000001f 1101 1102 #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC1 0x00000020 1103 1104 #define REG_A5XX_RBBM_CFG_DBGBUS_LOADREG 0x00000021 1105 1106 #define REG_A5XX_RBBM_CFG_DBGBUS_IDX 0x00000022 1107 1108 #define REG_A5XX_RBBM_CFG_DBGBUS_CLRC 0x00000023 1109 1110 #define REG_A5XX_RBBM_CFG_DBGBUS_LOADIVT 0x00000024 1111 1112 #define REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000002f 1113 1114 #define REG_A5XX_RBBM_INT_CLEAR_CMD 0x00000037 1115 1116 #define REG_A5XX_RBBM_INT_0_MASK 0x00000038 1117 #define A5XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001 1118 #define A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR 0x00000002 1119 #define A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT 0x00000004 1120 #define A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT 0x00000008 1121 #define A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT 0x00000010 1122 #define A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT 0x00000020 1123 #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW 0x00000040 1124 #define A5XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080 1125 #define A5XX_RBBM_INT_0_MASK_CP_SW 0x00000100 1126 #define A5XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200 1127 #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400 1128 #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800 1129 #define A5XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000 1130 #define A5XX_RBBM_INT_0_MASK_CP_IB2 0x00002000 1131 #define A5XX_RBBM_INT_0_MASK_CP_IB1 0x00004000 1132 #define A5XX_RBBM_INT_0_MASK_CP_RB 0x00008000 1133 #define A5XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000 1134 #define A5XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000 1135 #define A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000 1136 #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000 1137 #define A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT 0x00800000 1138 #define A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000 1139 #define A5XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000 1140 #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000 1141 #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000 1142 #define A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP 0x10000000 1143 #define A5XX_RBBM_INT_0_MASK_GPMU_FIRMWARE 0x20000000 1144 #define A5XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000 1145 #define A5XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000 1146 1147 #define REG_A5XX_RBBM_AHB_DBG_CNTL 0x0000003f 1148 1149 #define REG_A5XX_RBBM_EXT_VBIF_DBG_CNTL 0x00000041 1150 1151 #define REG_A5XX_RBBM_SW_RESET_CMD 0x00000043 1152 1153 #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 1154 1155 #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046 1156 1157 #define REG_A5XX_RBBM_DBG_LO_HI_GPIO 0x00000048 1158 1159 #define REG_A5XX_RBBM_EXT_TRACE_BUS_CNTL 0x00000049 1160 1161 #define REG_A5XX_RBBM_CLOCK_CNTL_TP0 0x0000004a 1162 1163 #define REG_A5XX_RBBM_CLOCK_CNTL_TP1 0x0000004b 1164 1165 #define REG_A5XX_RBBM_CLOCK_CNTL_TP2 0x0000004c 1166 1167 #define REG_A5XX_RBBM_CLOCK_CNTL_TP3 0x0000004d 1168 1169 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP0 0x0000004e 1170 1171 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP1 0x0000004f 1172 1173 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP2 0x00000050 1174 1175 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP3 0x00000051 1176 1177 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP0 0x00000052 1178 1179 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP1 0x00000053 1180 1181 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP2 0x00000054 1182 1183 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP3 0x00000055 1184 1185 #define REG_A5XX_RBBM_READ_AHB_THROUGH_DBG 0x00000059 1186 1187 #define REG_A5XX_RBBM_CLOCK_CNTL_UCHE 0x0000005a 1188 1189 #define REG_A5XX_RBBM_CLOCK_CNTL2_UCHE 0x0000005b 1190 1191 #define REG_A5XX_RBBM_CLOCK_CNTL3_UCHE 0x0000005c 1192 1193 #define REG_A5XX_RBBM_CLOCK_CNTL4_UCHE 0x0000005d 1194 1195 #define REG_A5XX_RBBM_CLOCK_HYST_UCHE 0x0000005e 1196 1197 #define REG_A5XX_RBBM_CLOCK_DELAY_UCHE 0x0000005f 1198 1199 #define REG_A5XX_RBBM_CLOCK_MODE_GPC 0x00000060 1200 1201 #define REG_A5XX_RBBM_CLOCK_DELAY_GPC 0x00000061 1202 1203 #define REG_A5XX_RBBM_CLOCK_HYST_GPC 0x00000062 1204 1205 #define REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000063 1206 1207 #define REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x00000064 1208 1209 #define REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000065 1210 1211 #define REG_A5XX_RBBM_CLOCK_DELAY_HLSQ 0x00000066 1212 1213 #define REG_A5XX_RBBM_CLOCK_CNTL 0x00000067 1214 1215 #define REG_A5XX_RBBM_CLOCK_CNTL_SP0 0x00000068 1216 1217 #define REG_A5XX_RBBM_CLOCK_CNTL_SP1 0x00000069 1218 1219 #define REG_A5XX_RBBM_CLOCK_CNTL_SP2 0x0000006a 1220 1221 #define REG_A5XX_RBBM_CLOCK_CNTL_SP3 0x0000006b 1222 1223 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP0 0x0000006c 1224 1225 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP1 0x0000006d 1226 1227 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP2 0x0000006e 1228 1229 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP3 0x0000006f 1230 1231 #define REG_A5XX_RBBM_CLOCK_HYST_SP0 0x00000070 1232 1233 #define REG_A5XX_RBBM_CLOCK_HYST_SP1 0x00000071 1234 1235 #define REG_A5XX_RBBM_CLOCK_HYST_SP2 0x00000072 1236 1237 #define REG_A5XX_RBBM_CLOCK_HYST_SP3 0x00000073 1238 1239 #define REG_A5XX_RBBM_CLOCK_DELAY_SP0 0x00000074 1240 1241 #define REG_A5XX_RBBM_CLOCK_DELAY_SP1 0x00000075 1242 1243 #define REG_A5XX_RBBM_CLOCK_DELAY_SP2 0x00000076 1244 1245 #define REG_A5XX_RBBM_CLOCK_DELAY_SP3 0x00000077 1246 1247 #define REG_A5XX_RBBM_CLOCK_CNTL_RB0 0x00000078 1248 1249 #define REG_A5XX_RBBM_CLOCK_CNTL_RB1 0x00000079 1250 1251 #define REG_A5XX_RBBM_CLOCK_CNTL_RB2 0x0000007a 1252 1253 #define REG_A5XX_RBBM_CLOCK_CNTL_RB3 0x0000007b 1254 1255 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB0 0x0000007c 1256 1257 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB1 0x0000007d 1258 1259 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB2 0x0000007e 1260 1261 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB3 0x0000007f 1262 1263 #define REG_A5XX_RBBM_CLOCK_HYST_RAC 0x00000080 1264 1265 #define REG_A5XX_RBBM_CLOCK_DELAY_RAC 0x00000081 1266 1267 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU0 0x00000082 1268 1269 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU1 0x00000083 1270 1271 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU2 0x00000084 1272 1273 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU3 0x00000085 1274 1275 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000086 1276 1277 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000087 1278 1279 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000088 1280 1281 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000089 1282 1283 #define REG_A5XX_RBBM_CLOCK_CNTL_RAC 0x0000008a 1284 1285 #define REG_A5XX_RBBM_CLOCK_CNTL2_RAC 0x0000008b 1286 1287 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0 0x0000008c 1288 1289 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1 0x0000008d 1290 1291 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2 0x0000008e 1292 1293 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3 0x0000008f 1294 1295 #define REG_A5XX_RBBM_CLOCK_HYST_VFD 0x00000090 1296 1297 #define REG_A5XX_RBBM_CLOCK_MODE_VFD 0x00000091 1298 1299 #define REG_A5XX_RBBM_CLOCK_DELAY_VFD 0x00000092 1300 1301 #define REG_A5XX_RBBM_AHB_CNTL0 0x00000093 1302 1303 #define REG_A5XX_RBBM_AHB_CNTL1 0x00000094 1304 1305 #define REG_A5XX_RBBM_AHB_CNTL2 0x00000095 1306 1307 #define REG_A5XX_RBBM_AHB_CMD 0x00000096 1308 1309 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11 0x0000009c 1310 1311 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12 0x0000009d 1312 1313 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13 0x0000009e 1314 1315 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14 0x0000009f 1316 1317 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15 0x000000a0 1318 1319 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16 0x000000a1 1320 1321 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17 0x000000a2 1322 1323 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18 0x000000a3 1324 1325 #define REG_A5XX_RBBM_CLOCK_DELAY_TP0 0x000000a4 1326 1327 #define REG_A5XX_RBBM_CLOCK_DELAY_TP1 0x000000a5 1328 1329 #define REG_A5XX_RBBM_CLOCK_DELAY_TP2 0x000000a6 1330 1331 #define REG_A5XX_RBBM_CLOCK_DELAY_TP3 0x000000a7 1332 1333 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP0 0x000000a8 1334 1335 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP1 0x000000a9 1336 1337 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP2 0x000000aa 1338 1339 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP3 0x000000ab 1340 1341 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP0 0x000000ac 1342 1343 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP1 0x000000ad 1344 1345 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP2 0x000000ae 1346 1347 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP3 0x000000af 1348 1349 #define REG_A5XX_RBBM_CLOCK_HYST_TP0 0x000000b0 1350 1351 #define REG_A5XX_RBBM_CLOCK_HYST_TP1 0x000000b1 1352 1353 #define REG_A5XX_RBBM_CLOCK_HYST_TP2 0x000000b2 1354 1355 #define REG_A5XX_RBBM_CLOCK_HYST_TP3 0x000000b3 1356 1357 #define REG_A5XX_RBBM_CLOCK_HYST2_TP0 0x000000b4 1358 1359 #define REG_A5XX_RBBM_CLOCK_HYST2_TP1 0x000000b5 1360 1361 #define REG_A5XX_RBBM_CLOCK_HYST2_TP2 0x000000b6 1362 1363 #define REG_A5XX_RBBM_CLOCK_HYST2_TP3 0x000000b7 1364 1365 #define REG_A5XX_RBBM_CLOCK_HYST3_TP0 0x000000b8 1366 1367 #define REG_A5XX_RBBM_CLOCK_HYST3_TP1 0x000000b9 1368 1369 #define REG_A5XX_RBBM_CLOCK_HYST3_TP2 0x000000ba 1370 1371 #define REG_A5XX_RBBM_CLOCK_HYST3_TP3 0x000000bb 1372 1373 #define REG_A5XX_RBBM_CLOCK_CNTL_GPMU 0x000000c8 1374 1375 #define REG_A5XX_RBBM_CLOCK_DELAY_GPMU 0x000000c9 1376 1377 #define REG_A5XX_RBBM_CLOCK_HYST_GPMU 0x000000ca 1378 1379 #define REG_A5XX_RBBM_PERFCTR_CP_0_LO 0x000003a0 1380 1381 #define REG_A5XX_RBBM_PERFCTR_CP_0_HI 0x000003a1 1382 1383 #define REG_A5XX_RBBM_PERFCTR_CP_1_LO 0x000003a2 1384 1385 #define REG_A5XX_RBBM_PERFCTR_CP_1_HI 0x000003a3 1386 1387 #define REG_A5XX_RBBM_PERFCTR_CP_2_LO 0x000003a4 1388 1389 #define REG_A5XX_RBBM_PERFCTR_CP_2_HI 0x000003a5 1390 1391 #define REG_A5XX_RBBM_PERFCTR_CP_3_LO 0x000003a6 1392 1393 #define REG_A5XX_RBBM_PERFCTR_CP_3_HI 0x000003a7 1394 1395 #define REG_A5XX_RBBM_PERFCTR_CP_4_LO 0x000003a8 1396 1397 #define REG_A5XX_RBBM_PERFCTR_CP_4_HI 0x000003a9 1398 1399 #define REG_A5XX_RBBM_PERFCTR_CP_5_LO 0x000003aa 1400 1401 #define REG_A5XX_RBBM_PERFCTR_CP_5_HI 0x000003ab 1402 1403 #define REG_A5XX_RBBM_PERFCTR_CP_6_LO 0x000003ac 1404 1405 #define REG_A5XX_RBBM_PERFCTR_CP_6_HI 0x000003ad 1406 1407 #define REG_A5XX_RBBM_PERFCTR_CP_7_LO 0x000003ae 1408 1409 #define REG_A5XX_RBBM_PERFCTR_CP_7_HI 0x000003af 1410 1411 #define REG_A5XX_RBBM_PERFCTR_RBBM_0_LO 0x000003b0 1412 1413 #define REG_A5XX_RBBM_PERFCTR_RBBM_0_HI 0x000003b1 1414 1415 #define REG_A5XX_RBBM_PERFCTR_RBBM_1_LO 0x000003b2 1416 1417 #define REG_A5XX_RBBM_PERFCTR_RBBM_1_HI 0x000003b3 1418 1419 #define REG_A5XX_RBBM_PERFCTR_RBBM_2_LO 0x000003b4 1420 1421 #define REG_A5XX_RBBM_PERFCTR_RBBM_2_HI 0x000003b5 1422 1423 #define REG_A5XX_RBBM_PERFCTR_RBBM_3_LO 0x000003b6 1424 1425 #define REG_A5XX_RBBM_PERFCTR_RBBM_3_HI 0x000003b7 1426 1427 #define REG_A5XX_RBBM_PERFCTR_PC_0_LO 0x000003b8 1428 1429 #define REG_A5XX_RBBM_PERFCTR_PC_0_HI 0x000003b9 1430 1431 #define REG_A5XX_RBBM_PERFCTR_PC_1_LO 0x000003ba 1432 1433 #define REG_A5XX_RBBM_PERFCTR_PC_1_HI 0x000003bb 1434 1435 #define REG_A5XX_RBBM_PERFCTR_PC_2_LO 0x000003bc 1436 1437 #define REG_A5XX_RBBM_PERFCTR_PC_2_HI 0x000003bd 1438 1439 #define REG_A5XX_RBBM_PERFCTR_PC_3_LO 0x000003be 1440 1441 #define REG_A5XX_RBBM_PERFCTR_PC_3_HI 0x000003bf 1442 1443 #define REG_A5XX_RBBM_PERFCTR_PC_4_LO 0x000003c0 1444 1445 #define REG_A5XX_RBBM_PERFCTR_PC_4_HI 0x000003c1 1446 1447 #define REG_A5XX_RBBM_PERFCTR_PC_5_LO 0x000003c2 1448 1449 #define REG_A5XX_RBBM_PERFCTR_PC_5_HI 0x000003c3 1450 1451 #define REG_A5XX_RBBM_PERFCTR_PC_6_LO 0x000003c4 1452 1453 #define REG_A5XX_RBBM_PERFCTR_PC_6_HI 0x000003c5 1454 1455 #define REG_A5XX_RBBM_PERFCTR_PC_7_LO 0x000003c6 1456 1457 #define REG_A5XX_RBBM_PERFCTR_PC_7_HI 0x000003c7 1458 1459 #define REG_A5XX_RBBM_PERFCTR_VFD_0_LO 0x000003c8 1460 1461 #define REG_A5XX_RBBM_PERFCTR_VFD_0_HI 0x000003c9 1462 1463 #define REG_A5XX_RBBM_PERFCTR_VFD_1_LO 0x000003ca 1464 1465 #define REG_A5XX_RBBM_PERFCTR_VFD_1_HI 0x000003cb 1466 1467 #define REG_A5XX_RBBM_PERFCTR_VFD_2_LO 0x000003cc 1468 1469 #define REG_A5XX_RBBM_PERFCTR_VFD_2_HI 0x000003cd 1470 1471 #define REG_A5XX_RBBM_PERFCTR_VFD_3_LO 0x000003ce 1472 1473 #define REG_A5XX_RBBM_PERFCTR_VFD_3_HI 0x000003cf 1474 1475 #define REG_A5XX_RBBM_PERFCTR_VFD_4_LO 0x000003d0 1476 1477 #define REG_A5XX_RBBM_PERFCTR_VFD_4_HI 0x000003d1 1478 1479 #define REG_A5XX_RBBM_PERFCTR_VFD_5_LO 0x000003d2 1480 1481 #define REG_A5XX_RBBM_PERFCTR_VFD_5_HI 0x000003d3 1482 1483 #define REG_A5XX_RBBM_PERFCTR_VFD_6_LO 0x000003d4 1484 1485 #define REG_A5XX_RBBM_PERFCTR_VFD_6_HI 0x000003d5 1486 1487 #define REG_A5XX_RBBM_PERFCTR_VFD_7_LO 0x000003d6 1488 1489 #define REG_A5XX_RBBM_PERFCTR_VFD_7_HI 0x000003d7 1490 1491 #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_LO 0x000003d8 1492 1493 #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_HI 0x000003d9 1494 1495 #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_LO 0x000003da 1496 1497 #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_HI 0x000003db 1498 1499 #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_LO 0x000003dc 1500 1501 #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_HI 0x000003dd 1502 1503 #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_LO 0x000003de 1504 1505 #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_HI 0x000003df 1506 1507 #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_LO 0x000003e0 1508 1509 #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_HI 0x000003e1 1510 1511 #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_LO 0x000003e2 1512 1513 #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_HI 0x000003e3 1514 1515 #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_LO 0x000003e4 1516 1517 #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_HI 0x000003e5 1518 1519 #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_LO 0x000003e6 1520 1521 #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_HI 0x000003e7 1522 1523 #define REG_A5XX_RBBM_PERFCTR_VPC_0_LO 0x000003e8 1524 1525 #define REG_A5XX_RBBM_PERFCTR_VPC_0_HI 0x000003e9 1526 1527 #define REG_A5XX_RBBM_PERFCTR_VPC_1_LO 0x000003ea 1528 1529 #define REG_A5XX_RBBM_PERFCTR_VPC_1_HI 0x000003eb 1530 1531 #define REG_A5XX_RBBM_PERFCTR_VPC_2_LO 0x000003ec 1532 1533 #define REG_A5XX_RBBM_PERFCTR_VPC_2_HI 0x000003ed 1534 1535 #define REG_A5XX_RBBM_PERFCTR_VPC_3_LO 0x000003ee 1536 1537 #define REG_A5XX_RBBM_PERFCTR_VPC_3_HI 0x000003ef 1538 1539 #define REG_A5XX_RBBM_PERFCTR_CCU_0_LO 0x000003f0 1540 1541 #define REG_A5XX_RBBM_PERFCTR_CCU_0_HI 0x000003f1 1542 1543 #define REG_A5XX_RBBM_PERFCTR_CCU_1_LO 0x000003f2 1544 1545 #define REG_A5XX_RBBM_PERFCTR_CCU_1_HI 0x000003f3 1546 1547 #define REG_A5XX_RBBM_PERFCTR_CCU_2_LO 0x000003f4 1548 1549 #define REG_A5XX_RBBM_PERFCTR_CCU_2_HI 0x000003f5 1550 1551 #define REG_A5XX_RBBM_PERFCTR_CCU_3_LO 0x000003f6 1552 1553 #define REG_A5XX_RBBM_PERFCTR_CCU_3_HI 0x000003f7 1554 1555 #define REG_A5XX_RBBM_PERFCTR_TSE_0_LO 0x000003f8 1556 1557 #define REG_A5XX_RBBM_PERFCTR_TSE_0_HI 0x000003f9 1558 1559 #define REG_A5XX_RBBM_PERFCTR_TSE_1_LO 0x000003fa 1560 1561 #define REG_A5XX_RBBM_PERFCTR_TSE_1_HI 0x000003fb 1562 1563 #define REG_A5XX_RBBM_PERFCTR_TSE_2_LO 0x000003fc 1564 1565 #define REG_A5XX_RBBM_PERFCTR_TSE_2_HI 0x000003fd 1566 1567 #define REG_A5XX_RBBM_PERFCTR_TSE_3_LO 0x000003fe 1568 1569 #define REG_A5XX_RBBM_PERFCTR_TSE_3_HI 0x000003ff 1570 1571 #define REG_A5XX_RBBM_PERFCTR_RAS_0_LO 0x00000400 1572 1573 #define REG_A5XX_RBBM_PERFCTR_RAS_0_HI 0x00000401 1574 1575 #define REG_A5XX_RBBM_PERFCTR_RAS_1_LO 0x00000402 1576 1577 #define REG_A5XX_RBBM_PERFCTR_RAS_1_HI 0x00000403 1578 1579 #define REG_A5XX_RBBM_PERFCTR_RAS_2_LO 0x00000404 1580 1581 #define REG_A5XX_RBBM_PERFCTR_RAS_2_HI 0x00000405 1582 1583 #define REG_A5XX_RBBM_PERFCTR_RAS_3_LO 0x00000406 1584 1585 #define REG_A5XX_RBBM_PERFCTR_RAS_3_HI 0x00000407 1586 1587 #define REG_A5XX_RBBM_PERFCTR_UCHE_0_LO 0x00000408 1588 1589 #define REG_A5XX_RBBM_PERFCTR_UCHE_0_HI 0x00000409 1590 1591 #define REG_A5XX_RBBM_PERFCTR_UCHE_1_LO 0x0000040a 1592 1593 #define REG_A5XX_RBBM_PERFCTR_UCHE_1_HI 0x0000040b 1594 1595 #define REG_A5XX_RBBM_PERFCTR_UCHE_2_LO 0x0000040c 1596 1597 #define REG_A5XX_RBBM_PERFCTR_UCHE_2_HI 0x0000040d 1598 1599 #define REG_A5XX_RBBM_PERFCTR_UCHE_3_LO 0x0000040e 1600 1601 #define REG_A5XX_RBBM_PERFCTR_UCHE_3_HI 0x0000040f 1602 1603 #define REG_A5XX_RBBM_PERFCTR_UCHE_4_LO 0x00000410 1604 1605 #define REG_A5XX_RBBM_PERFCTR_UCHE_4_HI 0x00000411 1606 1607 #define REG_A5XX_RBBM_PERFCTR_UCHE_5_LO 0x00000412 1608 1609 #define REG_A5XX_RBBM_PERFCTR_UCHE_5_HI 0x00000413 1610 1611 #define REG_A5XX_RBBM_PERFCTR_UCHE_6_LO 0x00000414 1612 1613 #define REG_A5XX_RBBM_PERFCTR_UCHE_6_HI 0x00000415 1614 1615 #define REG_A5XX_RBBM_PERFCTR_UCHE_7_LO 0x00000416 1616 1617 #define REG_A5XX_RBBM_PERFCTR_UCHE_7_HI 0x00000417 1618 1619 #define REG_A5XX_RBBM_PERFCTR_TP_0_LO 0x00000418 1620 1621 #define REG_A5XX_RBBM_PERFCTR_TP_0_HI 0x00000419 1622 1623 #define REG_A5XX_RBBM_PERFCTR_TP_1_LO 0x0000041a 1624 1625 #define REG_A5XX_RBBM_PERFCTR_TP_1_HI 0x0000041b 1626 1627 #define REG_A5XX_RBBM_PERFCTR_TP_2_LO 0x0000041c 1628 1629 #define REG_A5XX_RBBM_PERFCTR_TP_2_HI 0x0000041d 1630 1631 #define REG_A5XX_RBBM_PERFCTR_TP_3_LO 0x0000041e 1632 1633 #define REG_A5XX_RBBM_PERFCTR_TP_3_HI 0x0000041f 1634 1635 #define REG_A5XX_RBBM_PERFCTR_TP_4_LO 0x00000420 1636 1637 #define REG_A5XX_RBBM_PERFCTR_TP_4_HI 0x00000421 1638 1639 #define REG_A5XX_RBBM_PERFCTR_TP_5_LO 0x00000422 1640 1641 #define REG_A5XX_RBBM_PERFCTR_TP_5_HI 0x00000423 1642 1643 #define REG_A5XX_RBBM_PERFCTR_TP_6_LO 0x00000424 1644 1645 #define REG_A5XX_RBBM_PERFCTR_TP_6_HI 0x00000425 1646 1647 #define REG_A5XX_RBBM_PERFCTR_TP_7_LO 0x00000426 1648 1649 #define REG_A5XX_RBBM_PERFCTR_TP_7_HI 0x00000427 1650 1651 #define REG_A5XX_RBBM_PERFCTR_SP_0_LO 0x00000428 1652 1653 #define REG_A5XX_RBBM_PERFCTR_SP_0_HI 0x00000429 1654 1655 #define REG_A5XX_RBBM_PERFCTR_SP_1_LO 0x0000042a 1656 1657 #define REG_A5XX_RBBM_PERFCTR_SP_1_HI 0x0000042b 1658 1659 #define REG_A5XX_RBBM_PERFCTR_SP_2_LO 0x0000042c 1660 1661 #define REG_A5XX_RBBM_PERFCTR_SP_2_HI 0x0000042d 1662 1663 #define REG_A5XX_RBBM_PERFCTR_SP_3_LO 0x0000042e 1664 1665 #define REG_A5XX_RBBM_PERFCTR_SP_3_HI 0x0000042f 1666 1667 #define REG_A5XX_RBBM_PERFCTR_SP_4_LO 0x00000430 1668 1669 #define REG_A5XX_RBBM_PERFCTR_SP_4_HI 0x00000431 1670 1671 #define REG_A5XX_RBBM_PERFCTR_SP_5_LO 0x00000432 1672 1673 #define REG_A5XX_RBBM_PERFCTR_SP_5_HI 0x00000433 1674 1675 #define REG_A5XX_RBBM_PERFCTR_SP_6_LO 0x00000434 1676 1677 #define REG_A5XX_RBBM_PERFCTR_SP_6_HI 0x00000435 1678 1679 #define REG_A5XX_RBBM_PERFCTR_SP_7_LO 0x00000436 1680 1681 #define REG_A5XX_RBBM_PERFCTR_SP_7_HI 0x00000437 1682 1683 #define REG_A5XX_RBBM_PERFCTR_SP_8_LO 0x00000438 1684 1685 #define REG_A5XX_RBBM_PERFCTR_SP_8_HI 0x00000439 1686 1687 #define REG_A5XX_RBBM_PERFCTR_SP_9_LO 0x0000043a 1688 1689 #define REG_A5XX_RBBM_PERFCTR_SP_9_HI 0x0000043b 1690 1691 #define REG_A5XX_RBBM_PERFCTR_SP_10_LO 0x0000043c 1692 1693 #define REG_A5XX_RBBM_PERFCTR_SP_10_HI 0x0000043d 1694 1695 #define REG_A5XX_RBBM_PERFCTR_SP_11_LO 0x0000043e 1696 1697 #define REG_A5XX_RBBM_PERFCTR_SP_11_HI 0x0000043f 1698 1699 #define REG_A5XX_RBBM_PERFCTR_RB_0_LO 0x00000440 1700 1701 #define REG_A5XX_RBBM_PERFCTR_RB_0_HI 0x00000441 1702 1703 #define REG_A5XX_RBBM_PERFCTR_RB_1_LO 0x00000442 1704 1705 #define REG_A5XX_RBBM_PERFCTR_RB_1_HI 0x00000443 1706 1707 #define REG_A5XX_RBBM_PERFCTR_RB_2_LO 0x00000444 1708 1709 #define REG_A5XX_RBBM_PERFCTR_RB_2_HI 0x00000445 1710 1711 #define REG_A5XX_RBBM_PERFCTR_RB_3_LO 0x00000446 1712 1713 #define REG_A5XX_RBBM_PERFCTR_RB_3_HI 0x00000447 1714 1715 #define REG_A5XX_RBBM_PERFCTR_RB_4_LO 0x00000448 1716 1717 #define REG_A5XX_RBBM_PERFCTR_RB_4_HI 0x00000449 1718 1719 #define REG_A5XX_RBBM_PERFCTR_RB_5_LO 0x0000044a 1720 1721 #define REG_A5XX_RBBM_PERFCTR_RB_5_HI 0x0000044b 1722 1723 #define REG_A5XX_RBBM_PERFCTR_RB_6_LO 0x0000044c 1724 1725 #define REG_A5XX_RBBM_PERFCTR_RB_6_HI 0x0000044d 1726 1727 #define REG_A5XX_RBBM_PERFCTR_RB_7_LO 0x0000044e 1728 1729 #define REG_A5XX_RBBM_PERFCTR_RB_7_HI 0x0000044f 1730 1731 #define REG_A5XX_RBBM_PERFCTR_VSC_0_LO 0x00000450 1732 1733 #define REG_A5XX_RBBM_PERFCTR_VSC_0_HI 0x00000451 1734 1735 #define REG_A5XX_RBBM_PERFCTR_VSC_1_LO 0x00000452 1736 1737 #define REG_A5XX_RBBM_PERFCTR_VSC_1_HI 0x00000453 1738 1739 #define REG_A5XX_RBBM_PERFCTR_LRZ_0_LO 0x00000454 1740 1741 #define REG_A5XX_RBBM_PERFCTR_LRZ_0_HI 0x00000455 1742 1743 #define REG_A5XX_RBBM_PERFCTR_LRZ_1_LO 0x00000456 1744 1745 #define REG_A5XX_RBBM_PERFCTR_LRZ_1_HI 0x00000457 1746 1747 #define REG_A5XX_RBBM_PERFCTR_LRZ_2_LO 0x00000458 1748 1749 #define REG_A5XX_RBBM_PERFCTR_LRZ_2_HI 0x00000459 1750 1751 #define REG_A5XX_RBBM_PERFCTR_LRZ_3_LO 0x0000045a 1752 1753 #define REG_A5XX_RBBM_PERFCTR_LRZ_3_HI 0x0000045b 1754 1755 #define REG_A5XX_RBBM_PERFCTR_CMP_0_LO 0x0000045c 1756 1757 #define REG_A5XX_RBBM_PERFCTR_CMP_0_HI 0x0000045d 1758 1759 #define REG_A5XX_RBBM_PERFCTR_CMP_1_LO 0x0000045e 1760 1761 #define REG_A5XX_RBBM_PERFCTR_CMP_1_HI 0x0000045f 1762 1763 #define REG_A5XX_RBBM_PERFCTR_CMP_2_LO 0x00000460 1764 1765 #define REG_A5XX_RBBM_PERFCTR_CMP_2_HI 0x00000461 1766 1767 #define REG_A5XX_RBBM_PERFCTR_CMP_3_LO 0x00000462 1768 1769 #define REG_A5XX_RBBM_PERFCTR_CMP_3_HI 0x00000463 1770 1771 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b 1772 1773 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c 1774 1775 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d 1776 1777 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e 1778 1779 #define REG_A5XX_RBBM_ALWAYSON_COUNTER_LO 0x000004d2 1780 1781 #define REG_A5XX_RBBM_ALWAYSON_COUNTER_HI 0x000004d3 1782 1783 #define REG_A5XX_RBBM_STATUS 0x000004f5 1784 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x80000000 1785 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x40000000 1786 #define A5XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 1787 #define A5XX_RBBM_STATUS_VSC_BUSY 0x10000000 1788 #define A5XX_RBBM_STATUS_TPL1_BUSY 0x08000000 1789 #define A5XX_RBBM_STATUS_SP_BUSY 0x04000000 1790 #define A5XX_RBBM_STATUS_UCHE_BUSY 0x02000000 1791 #define A5XX_RBBM_STATUS_VPC_BUSY 0x01000000 1792 #define A5XX_RBBM_STATUS_VFDP_BUSY 0x00800000 1793 #define A5XX_RBBM_STATUS_VFD_BUSY 0x00400000 1794 #define A5XX_RBBM_STATUS_TESS_BUSY 0x00200000 1795 #define A5XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 1796 #define A5XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 1797 #define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY 0x00040000 1798 #define A5XX_RBBM_STATUS_DCOM_BUSY 0x00020000 1799 #define A5XX_RBBM_STATUS_COM_BUSY 0x00010000 1800 #define A5XX_RBBM_STATUS_LRZ_BUZY 0x00008000 1801 #define A5XX_RBBM_STATUS_A2D_DSP_BUSY 0x00004000 1802 #define A5XX_RBBM_STATUS_CCUFCHE_BUSY 0x00002000 1803 #define A5XX_RBBM_STATUS_RB_BUSY 0x00001000 1804 #define A5XX_RBBM_STATUS_RAS_BUSY 0x00000800 1805 #define A5XX_RBBM_STATUS_TSE_BUSY 0x00000400 1806 #define A5XX_RBBM_STATUS_VBIF_BUSY 0x00000200 1807 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST 0x00000100 1808 #define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST 0x00000080 1809 #define A5XX_RBBM_STATUS_CP_BUSY 0x00000040 1810 #define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY 0x00000020 1811 #define A5XX_RBBM_STATUS_CP_CRASH_BUSY 0x00000010 1812 #define A5XX_RBBM_STATUS_CP_ETS_BUSY 0x00000008 1813 #define A5XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 1814 #define A5XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 1815 #define A5XX_RBBM_STATUS_HI_BUSY 0x00000001 1816 1817 #define REG_A5XX_RBBM_STATUS3 0x00000530 1818 1819 #define REG_A5XX_RBBM_INT_0_STATUS 0x000004e1 1820 1821 #define REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS 0x000004f0 1822 1823 #define REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS 0x000004f1 1824 1825 #define REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS 0x000004f3 1826 1827 #define REG_A5XX_RBBM_AHB_ERROR_STATUS 0x000004f4 1828 1829 #define REG_A5XX_RBBM_PERFCTR_CNTL 0x00000464 1830 1831 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD0 0x00000465 1832 1833 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD1 0x00000466 1834 1835 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD2 0x00000467 1836 1837 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD3 0x00000468 1838 1839 #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000469 1840 1841 #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x0000046a 1842 1843 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b 1844 1845 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c 1846 1847 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d 1848 1849 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e 1850 1851 #define REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000046f 1852 1853 #define REG_A5XX_RBBM_AHB_ERROR 0x000004ed 1854 1855 #define REG_A5XX_RBBM_CFG_DBGBUS_EVENT_LOGIC 0x00000504 1856 1857 #define REG_A5XX_RBBM_CFG_DBGBUS_OVER 0x00000505 1858 1859 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT0 0x00000506 1860 1861 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT1 0x00000507 1862 1863 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT2 0x00000508 1864 1865 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT3 0x00000509 1866 1867 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT4 0x0000050a 1868 1869 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT5 0x0000050b 1870 1871 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_ADDR 0x0000050c 1872 1873 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF0 0x0000050d 1874 1875 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF1 0x0000050e 1876 1877 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF2 0x0000050f 1878 1879 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF3 0x00000510 1880 1881 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF4 0x00000511 1882 1883 #define REG_A5XX_RBBM_CFG_DBGBUS_MISR0 0x00000512 1884 1885 #define REG_A5XX_RBBM_CFG_DBGBUS_MISR1 0x00000513 1886 1887 #define REG_A5XX_RBBM_ISDB_CNT 0x00000533 1888 1889 #define REG_A5XX_RBBM_SECVID_TRUST_CONFIG 0x0000f000 1890 1891 #define REG_A5XX_RBBM_SECVID_TRUST_CNTL 0x0000f400 1892 1893 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800 1894 1895 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801 1896 1897 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802 1898 1899 #define REG_A5XX_RBBM_SECVID_TSB_CNTL 0x0000f803 1900 1901 #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_LO 0x0000f804 1902 1903 #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_HI 0x0000f805 1904 1905 #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_LO 0x0000f806 1906 1907 #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_HI 0x0000f807 1908 1909 #define REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810 1910 1911 #define REG_A5XX_VSC_BIN_SIZE 0x00000bc2 1912 #define A5XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff 1913 #define A5XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 1914 static inline uint32_t A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 1915 { 1916 return ((val >> 5) << A5XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A5XX_VSC_BIN_SIZE_WIDTH__MASK; 1917 } 1918 #define A5XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001fe00 1919 #define A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT 9 1920 static inline uint32_t A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 1921 { 1922 return ((val >> 5) << A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A5XX_VSC_BIN_SIZE_HEIGHT__MASK; 1923 } 1924 1925 #define REG_A5XX_VSC_SIZE_ADDRESS_LO 0x00000bc3 1926 1927 #define REG_A5XX_VSC_SIZE_ADDRESS_HI 0x00000bc4 1928 1929 #define REG_A5XX_UNKNOWN_0BC5 0x00000bc5 1930 1931 #define REG_A5XX_UNKNOWN_0BC6 0x00000bc6 1932 1933 static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; } 1934 1935 static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; } 1936 #define A5XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff 1937 #define A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0 1938 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) 1939 { 1940 return ((val) << A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_X__MASK; 1941 } 1942 #define A5XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00 1943 #define A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10 1944 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) 1945 { 1946 return ((val) << A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_Y__MASK; 1947 } 1948 #define A5XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000 1949 #define A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20 1950 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) 1951 { 1952 return ((val) << A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_W__MASK; 1953 } 1954 #define A5XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000 1955 #define A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24 1956 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) 1957 { 1958 return ((val) << A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_H__MASK; 1959 } 1960 1961 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000be0 + 0x2*i0; } 1962 1963 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0) { return 0x00000be0 + 0x2*i0; } 1964 1965 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0) { return 0x00000be1 + 0x2*i0; } 1966 1967 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c00 + 0x1*i0; } 1968 1969 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c00 + 0x1*i0; } 1970 1971 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_0 0x00000c60 1972 1973 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_1 0x00000c61 1974 1975 #define REG_A5XX_VSC_RESOLVE_CNTL 0x00000cdd 1976 #define A5XX_VSC_RESOLVE_CNTL_WINDOW_OFFSET_DISABLE 0x80000000 1977 #define A5XX_VSC_RESOLVE_CNTL_X__MASK 0x00007fff 1978 #define A5XX_VSC_RESOLVE_CNTL_X__SHIFT 0 1979 static inline uint32_t A5XX_VSC_RESOLVE_CNTL_X(uint32_t val) 1980 { 1981 return ((val) << A5XX_VSC_RESOLVE_CNTL_X__SHIFT) & A5XX_VSC_RESOLVE_CNTL_X__MASK; 1982 } 1983 #define A5XX_VSC_RESOLVE_CNTL_Y__MASK 0x7fff0000 1984 #define A5XX_VSC_RESOLVE_CNTL_Y__SHIFT 16 1985 static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val) 1986 { 1987 return ((val) << A5XX_VSC_RESOLVE_CNTL_Y__SHIFT) & A5XX_VSC_RESOLVE_CNTL_Y__MASK; 1988 } 1989 1990 #define REG_A5XX_GRAS_ADDR_MODE_CNTL 0x00000c81 1991 1992 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c90 1993 1994 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c91 1995 1996 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c92 1997 1998 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c93 1999 2000 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c94 2001 2002 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c95 2003 2004 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c96 2005 2006 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c97 2007 2008 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_0 0x00000c98 2009 2010 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_1 0x00000c99 2011 2012 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_2 0x00000c9a 2013 2014 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_3 0x00000c9b 2015 2016 #define REG_A5XX_RB_DBG_ECO_CNTL 0x00000cc4 2017 2018 #define REG_A5XX_RB_ADDR_MODE_CNTL 0x00000cc5 2019 2020 #define REG_A5XX_RB_MODE_CNTL 0x00000cc6 2021 2022 #define REG_A5XX_RB_CCU_CNTL 0x00000cc7 2023 2024 #define REG_A5XX_RB_PERFCTR_RB_SEL_0 0x00000cd0 2025 2026 #define REG_A5XX_RB_PERFCTR_RB_SEL_1 0x00000cd1 2027 2028 #define REG_A5XX_RB_PERFCTR_RB_SEL_2 0x00000cd2 2029 2030 #define REG_A5XX_RB_PERFCTR_RB_SEL_3 0x00000cd3 2031 2032 #define REG_A5XX_RB_PERFCTR_RB_SEL_4 0x00000cd4 2033 2034 #define REG_A5XX_RB_PERFCTR_RB_SEL_5 0x00000cd5 2035 2036 #define REG_A5XX_RB_PERFCTR_RB_SEL_6 0x00000cd6 2037 2038 #define REG_A5XX_RB_PERFCTR_RB_SEL_7 0x00000cd7 2039 2040 #define REG_A5XX_RB_PERFCTR_CCU_SEL_0 0x00000cd8 2041 2042 #define REG_A5XX_RB_PERFCTR_CCU_SEL_1 0x00000cd9 2043 2044 #define REG_A5XX_RB_PERFCTR_CCU_SEL_2 0x00000cda 2045 2046 #define REG_A5XX_RB_PERFCTR_CCU_SEL_3 0x00000cdb 2047 2048 #define REG_A5XX_RB_POWERCTR_RB_SEL_0 0x00000ce0 2049 2050 #define REG_A5XX_RB_POWERCTR_RB_SEL_1 0x00000ce1 2051 2052 #define REG_A5XX_RB_POWERCTR_RB_SEL_2 0x00000ce2 2053 2054 #define REG_A5XX_RB_POWERCTR_RB_SEL_3 0x00000ce3 2055 2056 #define REG_A5XX_RB_POWERCTR_CCU_SEL_0 0x00000ce4 2057 2058 #define REG_A5XX_RB_POWERCTR_CCU_SEL_1 0x00000ce5 2059 2060 #define REG_A5XX_RB_PERFCTR_CMP_SEL_0 0x00000cec 2061 2062 #define REG_A5XX_RB_PERFCTR_CMP_SEL_1 0x00000ced 2063 2064 #define REG_A5XX_RB_PERFCTR_CMP_SEL_2 0x00000cee 2065 2066 #define REG_A5XX_RB_PERFCTR_CMP_SEL_3 0x00000cef 2067 2068 #define REG_A5XX_PC_DBG_ECO_CNTL 0x00000d00 2069 #define A5XX_PC_DBG_ECO_CNTL_TWOPASSUSEWFI 0x00000100 2070 2071 #define REG_A5XX_PC_ADDR_MODE_CNTL 0x00000d01 2072 2073 #define REG_A5XX_PC_MODE_CNTL 0x00000d02 2074 2075 #define REG_A5XX_UNKNOWN_0D08 0x00000d08 2076 2077 #define REG_A5XX_UNKNOWN_0D09 0x00000d09 2078 2079 #define REG_A5XX_PC_PERFCTR_PC_SEL_0 0x00000d10 2080 2081 #define REG_A5XX_PC_PERFCTR_PC_SEL_1 0x00000d11 2082 2083 #define REG_A5XX_PC_PERFCTR_PC_SEL_2 0x00000d12 2084 2085 #define REG_A5XX_PC_PERFCTR_PC_SEL_3 0x00000d13 2086 2087 #define REG_A5XX_PC_PERFCTR_PC_SEL_4 0x00000d14 2088 2089 #define REG_A5XX_PC_PERFCTR_PC_SEL_5 0x00000d15 2090 2091 #define REG_A5XX_PC_PERFCTR_PC_SEL_6 0x00000d16 2092 2093 #define REG_A5XX_PC_PERFCTR_PC_SEL_7 0x00000d17 2094 2095 #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0 0x00000e00 2096 2097 #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_1 0x00000e01 2098 2099 #define REG_A5XX_HLSQ_ADDR_MODE_CNTL 0x00000e05 2100 2101 #define REG_A5XX_HLSQ_MODE_CNTL 0x00000e06 2102 2103 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e10 2104 2105 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e11 2106 2107 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e12 2108 2109 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e13 2110 2111 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e14 2112 2113 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e15 2114 2115 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e16 2116 2117 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e17 2118 2119 #define REG_A5XX_HLSQ_SPTP_RDSEL 0x00000f08 2120 2121 #define REG_A5XX_HLSQ_DBG_READ_SEL 0x0000bc00 2122 2123 #define REG_A5XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000a000 2124 2125 #define REG_A5XX_VFD_ADDR_MODE_CNTL 0x00000e41 2126 2127 #define REG_A5XX_VFD_MODE_CNTL 0x00000e42 2128 2129 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_0 0x00000e50 2130 2131 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_1 0x00000e51 2132 2133 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_2 0x00000e52 2134 2135 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_3 0x00000e53 2136 2137 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_4 0x00000e54 2138 2139 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_5 0x00000e55 2140 2141 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_6 0x00000e56 2142 2143 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_7 0x00000e57 2144 2145 #define REG_A5XX_VPC_DBG_ECO_CNTL 0x00000e60 2146 2147 #define REG_A5XX_VPC_ADDR_MODE_CNTL 0x00000e61 2148 2149 #define REG_A5XX_VPC_MODE_CNTL 0x00000e62 2150 #define A5XX_VPC_MODE_CNTL_BINNING_PASS 0x00000001 2151 2152 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_0 0x00000e64 2153 2154 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_1 0x00000e65 2155 2156 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_2 0x00000e66 2157 2158 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_3 0x00000e67 2159 2160 #define REG_A5XX_UCHE_ADDR_MODE_CNTL 0x00000e80 2161 2162 #define REG_A5XX_UCHE_SVM_CNTL 0x00000e82 2163 2164 #define REG_A5XX_UCHE_WRITE_THRU_BASE_LO 0x00000e87 2165 2166 #define REG_A5XX_UCHE_WRITE_THRU_BASE_HI 0x00000e88 2167 2168 #define REG_A5XX_UCHE_TRAP_BASE_LO 0x00000e89 2169 2170 #define REG_A5XX_UCHE_TRAP_BASE_HI 0x00000e8a 2171 2172 #define REG_A5XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e8b 2173 2174 #define REG_A5XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e8c 2175 2176 #define REG_A5XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e8d 2177 2178 #define REG_A5XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e8e 2179 2180 #define REG_A5XX_UCHE_DBG_ECO_CNTL_2 0x00000e8f 2181 2182 #define REG_A5XX_UCHE_DBG_ECO_CNTL 0x00000e90 2183 2184 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO 0x00000e91 2185 2186 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_HI 0x00000e92 2187 2188 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_LO 0x00000e93 2189 2190 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_HI 0x00000e94 2191 2192 #define REG_A5XX_UCHE_CACHE_INVALIDATE 0x00000e95 2193 2194 #define REG_A5XX_UCHE_CACHE_WAYS 0x00000e96 2195 2196 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000ea0 2197 2198 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000ea1 2199 2200 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000ea2 2201 2202 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000ea3 2203 2204 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000ea4 2205 2206 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000ea5 2207 2208 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000ea6 2209 2210 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000ea7 2211 2212 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_0 0x00000ea8 2213 2214 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_1 0x00000ea9 2215 2216 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_2 0x00000eaa 2217 2218 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_3 0x00000eab 2219 2220 #define REG_A5XX_UCHE_TRAP_LOG_LO 0x00000eb1 2221 2222 #define REG_A5XX_UCHE_TRAP_LOG_HI 0x00000eb2 2223 2224 #define REG_A5XX_SP_DBG_ECO_CNTL 0x00000ec0 2225 2226 #define REG_A5XX_SP_ADDR_MODE_CNTL 0x00000ec1 2227 2228 #define REG_A5XX_SP_MODE_CNTL 0x00000ec2 2229 2230 #define REG_A5XX_SP_PERFCTR_SP_SEL_0 0x00000ed0 2231 2232 #define REG_A5XX_SP_PERFCTR_SP_SEL_1 0x00000ed1 2233 2234 #define REG_A5XX_SP_PERFCTR_SP_SEL_2 0x00000ed2 2235 2236 #define REG_A5XX_SP_PERFCTR_SP_SEL_3 0x00000ed3 2237 2238 #define REG_A5XX_SP_PERFCTR_SP_SEL_4 0x00000ed4 2239 2240 #define REG_A5XX_SP_PERFCTR_SP_SEL_5 0x00000ed5 2241 2242 #define REG_A5XX_SP_PERFCTR_SP_SEL_6 0x00000ed6 2243 2244 #define REG_A5XX_SP_PERFCTR_SP_SEL_7 0x00000ed7 2245 2246 #define REG_A5XX_SP_PERFCTR_SP_SEL_8 0x00000ed8 2247 2248 #define REG_A5XX_SP_PERFCTR_SP_SEL_9 0x00000ed9 2249 2250 #define REG_A5XX_SP_PERFCTR_SP_SEL_10 0x00000eda 2251 2252 #define REG_A5XX_SP_PERFCTR_SP_SEL_11 0x00000edb 2253 2254 #define REG_A5XX_SP_POWERCTR_SP_SEL_0 0x00000edc 2255 2256 #define REG_A5XX_SP_POWERCTR_SP_SEL_1 0x00000edd 2257 2258 #define REG_A5XX_SP_POWERCTR_SP_SEL_2 0x00000ede 2259 2260 #define REG_A5XX_SP_POWERCTR_SP_SEL_3 0x00000edf 2261 2262 #define REG_A5XX_TPL1_ADDR_MODE_CNTL 0x00000f01 2263 2264 #define REG_A5XX_TPL1_MODE_CNTL 0x00000f02 2265 2266 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_0 0x00000f10 2267 2268 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_1 0x00000f11 2269 2270 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_2 0x00000f12 2271 2272 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_3 0x00000f13 2273 2274 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_4 0x00000f14 2275 2276 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_5 0x00000f15 2277 2278 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_6 0x00000f16 2279 2280 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_7 0x00000f17 2281 2282 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_0 0x00000f18 2283 2284 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_1 0x00000f19 2285 2286 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_2 0x00000f1a 2287 2288 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_3 0x00000f1b 2289 2290 #define REG_A5XX_VBIF_VERSION 0x00003000 2291 2292 #define REG_A5XX_VBIF_CLKON 0x00003001 2293 2294 #define REG_A5XX_VBIF_ABIT_SORT 0x00003028 2295 2296 #define REG_A5XX_VBIF_ABIT_SORT_CONF 0x00003029 2297 2298 #define REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049 2299 2300 #define REG_A5XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 2301 2302 #define REG_A5XX_VBIF_IN_RD_LIM_CONF0 0x0000302c 2303 2304 #define REG_A5XX_VBIF_IN_RD_LIM_CONF1 0x0000302d 2305 2306 #define REG_A5XX_VBIF_XIN_HALT_CTRL0 0x00003080 2307 2308 #define REG_A5XX_VBIF_XIN_HALT_CTRL1 0x00003081 2309 2310 #define REG_A5XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084 2311 2312 #define REG_A5XX_VBIF_TEST_BUS1_CTRL0 0x00003085 2313 2314 #define REG_A5XX_VBIF_TEST_BUS1_CTRL1 0x00003086 2315 2316 #define REG_A5XX_VBIF_TEST_BUS2_CTRL0 0x00003087 2317 2318 #define REG_A5XX_VBIF_TEST_BUS2_CTRL1 0x00003088 2319 2320 #define REG_A5XX_VBIF_TEST_BUS_OUT 0x0000308c 2321 2322 #define REG_A5XX_VBIF_PERF_CNT_EN0 0x000030c0 2323 2324 #define REG_A5XX_VBIF_PERF_CNT_EN1 0x000030c1 2325 2326 #define REG_A5XX_VBIF_PERF_CNT_EN2 0x000030c2 2327 2328 #define REG_A5XX_VBIF_PERF_CNT_EN3 0x000030c3 2329 2330 #define REG_A5XX_VBIF_PERF_CNT_SEL0 0x000030d0 2331 2332 #define REG_A5XX_VBIF_PERF_CNT_SEL1 0x000030d1 2333 2334 #define REG_A5XX_VBIF_PERF_CNT_SEL2 0x000030d2 2335 2336 #define REG_A5XX_VBIF_PERF_CNT_SEL3 0x000030d3 2337 2338 #define REG_A5XX_VBIF_PERF_CNT_LOW0 0x000030d8 2339 2340 #define REG_A5XX_VBIF_PERF_CNT_LOW1 0x000030d9 2341 2342 #define REG_A5XX_VBIF_PERF_CNT_LOW2 0x000030da 2343 2344 #define REG_A5XX_VBIF_PERF_CNT_LOW3 0x000030db 2345 2346 #define REG_A5XX_VBIF_PERF_CNT_HIGH0 0x000030e0 2347 2348 #define REG_A5XX_VBIF_PERF_CNT_HIGH1 0x000030e1 2349 2350 #define REG_A5XX_VBIF_PERF_CNT_HIGH2 0x000030e2 2351 2352 #define REG_A5XX_VBIF_PERF_CNT_HIGH3 0x000030e3 2353 2354 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN0 0x00003100 2355 2356 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN1 0x00003101 2357 2358 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN2 0x00003102 2359 2360 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110 2361 2362 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111 2363 2364 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112 2365 2366 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118 2367 2368 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119 2369 2370 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a 2371 2372 #define REG_A5XX_GPMU_INST_RAM_BASE 0x00008800 2373 2374 #define REG_A5XX_GPMU_DATA_RAM_BASE 0x00009800 2375 2376 #define REG_A5XX_GPMU_SP_POWER_CNTL 0x0000a881 2377 2378 #define REG_A5XX_GPMU_RBCCU_CLOCK_CNTL 0x0000a886 2379 2380 #define REG_A5XX_GPMU_RBCCU_POWER_CNTL 0x0000a887 2381 2382 #define REG_A5XX_GPMU_SP_PWR_CLK_STATUS 0x0000a88b 2383 #define A5XX_GPMU_SP_PWR_CLK_STATUS_PWR_ON 0x00100000 2384 2385 #define REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS 0x0000a88d 2386 #define A5XX_GPMU_RBCCU_PWR_CLK_STATUS_PWR_ON 0x00100000 2387 2388 #define REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY 0x0000a891 2389 2390 #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL 0x0000a892 2391 2392 #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST 0x0000a893 2393 2394 #define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL 0x0000a894 2395 2396 #define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3 2397 2398 #define REG_A5XX_GPMU_WFI_CONFIG 0x0000a8c1 2399 2400 #define REG_A5XX_GPMU_RBBM_INTR_INFO 0x0000a8d6 2401 2402 #define REG_A5XX_GPMU_CM3_SYSRESET 0x0000a8d8 2403 2404 #define REG_A5XX_GPMU_GENERAL_0 0x0000a8e0 2405 2406 #define REG_A5XX_GPMU_GENERAL_1 0x0000a8e1 2407 2408 #define REG_A5XX_SP_POWER_COUNTER_0_LO 0x0000a840 2409 2410 #define REG_A5XX_SP_POWER_COUNTER_0_HI 0x0000a841 2411 2412 #define REG_A5XX_SP_POWER_COUNTER_1_LO 0x0000a842 2413 2414 #define REG_A5XX_SP_POWER_COUNTER_1_HI 0x0000a843 2415 2416 #define REG_A5XX_SP_POWER_COUNTER_2_LO 0x0000a844 2417 2418 #define REG_A5XX_SP_POWER_COUNTER_2_HI 0x0000a845 2419 2420 #define REG_A5XX_SP_POWER_COUNTER_3_LO 0x0000a846 2421 2422 #define REG_A5XX_SP_POWER_COUNTER_3_HI 0x0000a847 2423 2424 #define REG_A5XX_TP_POWER_COUNTER_0_LO 0x0000a848 2425 2426 #define REG_A5XX_TP_POWER_COUNTER_0_HI 0x0000a849 2427 2428 #define REG_A5XX_TP_POWER_COUNTER_1_LO 0x0000a84a 2429 2430 #define REG_A5XX_TP_POWER_COUNTER_1_HI 0x0000a84b 2431 2432 #define REG_A5XX_TP_POWER_COUNTER_2_LO 0x0000a84c 2433 2434 #define REG_A5XX_TP_POWER_COUNTER_2_HI 0x0000a84d 2435 2436 #define REG_A5XX_TP_POWER_COUNTER_3_LO 0x0000a84e 2437 2438 #define REG_A5XX_TP_POWER_COUNTER_3_HI 0x0000a84f 2439 2440 #define REG_A5XX_RB_POWER_COUNTER_0_LO 0x0000a850 2441 2442 #define REG_A5XX_RB_POWER_COUNTER_0_HI 0x0000a851 2443 2444 #define REG_A5XX_RB_POWER_COUNTER_1_LO 0x0000a852 2445 2446 #define REG_A5XX_RB_POWER_COUNTER_1_HI 0x0000a853 2447 2448 #define REG_A5XX_RB_POWER_COUNTER_2_LO 0x0000a854 2449 2450 #define REG_A5XX_RB_POWER_COUNTER_2_HI 0x0000a855 2451 2452 #define REG_A5XX_RB_POWER_COUNTER_3_LO 0x0000a856 2453 2454 #define REG_A5XX_RB_POWER_COUNTER_3_HI 0x0000a857 2455 2456 #define REG_A5XX_CCU_POWER_COUNTER_0_LO 0x0000a858 2457 2458 #define REG_A5XX_CCU_POWER_COUNTER_0_HI 0x0000a859 2459 2460 #define REG_A5XX_CCU_POWER_COUNTER_1_LO 0x0000a85a 2461 2462 #define REG_A5XX_CCU_POWER_COUNTER_1_HI 0x0000a85b 2463 2464 #define REG_A5XX_UCHE_POWER_COUNTER_0_LO 0x0000a85c 2465 2466 #define REG_A5XX_UCHE_POWER_COUNTER_0_HI 0x0000a85d 2467 2468 #define REG_A5XX_UCHE_POWER_COUNTER_1_LO 0x0000a85e 2469 2470 #define REG_A5XX_UCHE_POWER_COUNTER_1_HI 0x0000a85f 2471 2472 #define REG_A5XX_UCHE_POWER_COUNTER_2_LO 0x0000a860 2473 2474 #define REG_A5XX_UCHE_POWER_COUNTER_2_HI 0x0000a861 2475 2476 #define REG_A5XX_UCHE_POWER_COUNTER_3_LO 0x0000a862 2477 2478 #define REG_A5XX_UCHE_POWER_COUNTER_3_HI 0x0000a863 2479 2480 #define REG_A5XX_CP_POWER_COUNTER_0_LO 0x0000a864 2481 2482 #define REG_A5XX_CP_POWER_COUNTER_0_HI 0x0000a865 2483 2484 #define REG_A5XX_CP_POWER_COUNTER_1_LO 0x0000a866 2485 2486 #define REG_A5XX_CP_POWER_COUNTER_1_HI 0x0000a867 2487 2488 #define REG_A5XX_CP_POWER_COUNTER_2_LO 0x0000a868 2489 2490 #define REG_A5XX_CP_POWER_COUNTER_2_HI 0x0000a869 2491 2492 #define REG_A5XX_CP_POWER_COUNTER_3_LO 0x0000a86a 2493 2494 #define REG_A5XX_CP_POWER_COUNTER_3_HI 0x0000a86b 2495 2496 #define REG_A5XX_GPMU_POWER_COUNTER_0_LO 0x0000a86c 2497 2498 #define REG_A5XX_GPMU_POWER_COUNTER_0_HI 0x0000a86d 2499 2500 #define REG_A5XX_GPMU_POWER_COUNTER_1_LO 0x0000a86e 2501 2502 #define REG_A5XX_GPMU_POWER_COUNTER_1_HI 0x0000a86f 2503 2504 #define REG_A5XX_GPMU_POWER_COUNTER_2_LO 0x0000a870 2505 2506 #define REG_A5XX_GPMU_POWER_COUNTER_2_HI 0x0000a871 2507 2508 #define REG_A5XX_GPMU_POWER_COUNTER_3_LO 0x0000a872 2509 2510 #define REG_A5XX_GPMU_POWER_COUNTER_3_HI 0x0000a873 2511 2512 #define REG_A5XX_GPMU_POWER_COUNTER_4_LO 0x0000a874 2513 2514 #define REG_A5XX_GPMU_POWER_COUNTER_4_HI 0x0000a875 2515 2516 #define REG_A5XX_GPMU_POWER_COUNTER_5_LO 0x0000a876 2517 2518 #define REG_A5XX_GPMU_POWER_COUNTER_5_HI 0x0000a877 2519 2520 #define REG_A5XX_GPMU_POWER_COUNTER_ENABLE 0x0000a878 2521 2522 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_LO 0x0000a879 2523 2524 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_HI 0x0000a87a 2525 2526 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_RESET 0x0000a87b 2527 2528 #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_0 0x0000a87c 2529 2530 #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_1 0x0000a87d 2531 2532 #define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3 2533 2534 #define REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL 0x0000a8a8 2535 2536 #define REG_A5XX_GPMU_TEMP_SENSOR_ID 0x0000ac00 2537 2538 #define REG_A5XX_GPMU_TEMP_SENSOR_CONFIG 0x0000ac01 2539 2540 #define REG_A5XX_GPMU_TEMP_VAL 0x0000ac02 2541 2542 #define REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD 0x0000ac03 2543 2544 #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_STATUS 0x0000ac05 2545 2546 #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK 0x0000ac06 2547 2548 #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_0_1 0x0000ac40 2549 2550 #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_2_3 0x0000ac41 2551 2552 #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_0_1 0x0000ac42 2553 2554 #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_2_3 0x0000ac43 2555 2556 #define REG_A5XX_GPMU_BASE_LEAKAGE 0x0000ac46 2557 2558 #define REG_A5XX_GPMU_GPMU_VOLTAGE 0x0000ac60 2559 2560 #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_STATUS 0x0000ac61 2561 2562 #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK 0x0000ac62 2563 2564 #define REG_A5XX_GPMU_GPMU_PWR_THRESHOLD 0x0000ac80 2565 2566 #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL 0x0000acc4 2567 2568 #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_STATUS 0x0000acc5 2569 2570 #define REG_A5XX_GDPM_CONFIG1 0x0000b80c 2571 2572 #define REG_A5XX_GDPM_CONFIG2 0x0000b80d 2573 2574 #define REG_A5XX_GDPM_INT_EN 0x0000b80f 2575 2576 #define REG_A5XX_GDPM_INT_MASK 0x0000b811 2577 2578 #define REG_A5XX_GPMU_BEC_ENABLE 0x0000b9a0 2579 2580 #define REG_A5XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000c41a 2581 2582 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 0x0000c41d 2583 2584 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 0x0000c41f 2585 2586 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 0x0000c421 2587 2588 #define REG_A5XX_GPU_CS_ENABLE_REG 0x0000c520 2589 2590 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x0000c557 2591 2592 #define REG_A5XX_GRAS_CL_CNTL 0x0000e000 2593 2594 #define REG_A5XX_UNKNOWN_E001 0x0000e001 2595 2596 #define REG_A5XX_UNKNOWN_E004 0x0000e004 2597 2598 #define REG_A5XX_GRAS_CNTL 0x0000e005 2599 #define A5XX_GRAS_CNTL_VARYING 0x00000001 2600 #define A5XX_GRAS_CNTL_UNK3 0x00000008 2601 #define A5XX_GRAS_CNTL_XCOORD 0x00000040 2602 #define A5XX_GRAS_CNTL_YCOORD 0x00000080 2603 #define A5XX_GRAS_CNTL_ZCOORD 0x00000100 2604 #define A5XX_GRAS_CNTL_WCOORD 0x00000200 2605 2606 #define REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x0000e006 2607 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff 2608 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0 2609 static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val) 2610 { 2611 return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK; 2612 } 2613 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x000ffc00 2614 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10 2615 static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) 2616 { 2617 return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK; 2618 } 2619 2620 #define REG_A5XX_GRAS_CL_VPORT_XOFFSET_0 0x0000e010 2621 #define A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff 2622 #define A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0 2623 static inline uint32_t A5XX_GRAS_CL_VPORT_XOFFSET_0(float val) 2624 { 2625 return ((fui(val)) << A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK; 2626 } 2627 2628 #define REG_A5XX_GRAS_CL_VPORT_XSCALE_0 0x0000e011 2629 #define A5XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff 2630 #define A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0 2631 static inline uint32_t A5XX_GRAS_CL_VPORT_XSCALE_0(float val) 2632 { 2633 return ((fui(val)) << A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_XSCALE_0__MASK; 2634 } 2635 2636 #define REG_A5XX_GRAS_CL_VPORT_YOFFSET_0 0x0000e012 2637 #define A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff 2638 #define A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0 2639 static inline uint32_t A5XX_GRAS_CL_VPORT_YOFFSET_0(float val) 2640 { 2641 return ((fui(val)) << A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK; 2642 } 2643 2644 #define REG_A5XX_GRAS_CL_VPORT_YSCALE_0 0x0000e013 2645 #define A5XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff 2646 #define A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0 2647 static inline uint32_t A5XX_GRAS_CL_VPORT_YSCALE_0(float val) 2648 { 2649 return ((fui(val)) << A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_YSCALE_0__MASK; 2650 } 2651 2652 #define REG_A5XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000e014 2653 #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff 2654 #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0 2655 static inline uint32_t A5XX_GRAS_CL_VPORT_ZOFFSET_0(float val) 2656 { 2657 return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK; 2658 } 2659 2660 #define REG_A5XX_GRAS_CL_VPORT_ZSCALE_0 0x0000e015 2661 #define A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff 2662 #define A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0 2663 static inline uint32_t A5XX_GRAS_CL_VPORT_ZSCALE_0(float val) 2664 { 2665 return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK; 2666 } 2667 2668 #define REG_A5XX_GRAS_SU_CNTL 0x0000e090 2669 #define A5XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001 2670 #define A5XX_GRAS_SU_CNTL_CULL_BACK 0x00000002 2671 #define A5XX_GRAS_SU_CNTL_FRONT_CW 0x00000004 2672 #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8 2673 #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3 2674 static inline uint32_t A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) 2675 { 2676 return ((((int32_t)(val * 4.0))) << A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK; 2677 } 2678 #define A5XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800 2679 #define A5XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000 2680 2681 #define REG_A5XX_GRAS_SU_POINT_MINMAX 0x0000e091 2682 #define A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 2683 #define A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 2684 static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MIN(float val) 2685 { 2686 return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 2687 } 2688 #define A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 2689 #define A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 2690 static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MAX(float val) 2691 { 2692 return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 2693 } 2694 2695 #define REG_A5XX_GRAS_SU_POINT_SIZE 0x0000e092 2696 #define A5XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff 2697 #define A5XX_GRAS_SU_POINT_SIZE__SHIFT 0 2698 static inline uint32_t A5XX_GRAS_SU_POINT_SIZE(float val) 2699 { 2700 return ((((int32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_SIZE__SHIFT) & A5XX_GRAS_SU_POINT_SIZE__MASK; 2701 } 2702 2703 #define REG_A5XX_UNKNOWN_E093 0x0000e093 2704 2705 #define REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL 0x0000e094 2706 #define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001 2707 #define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1 0x00000002 2708 2709 #define REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000e095 2710 #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff 2711 #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 2712 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_SCALE(float val) 2713 { 2714 return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; 2715 } 2716 2717 #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000e096 2718 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 2719 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 2720 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 2721 { 2722 return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 2723 } 2724 2725 #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x0000e097 2726 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff 2727 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0 2728 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val) 2729 { 2730 return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK; 2731 } 2732 2733 #define REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO 0x0000e098 2734 #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 2735 #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 2736 static inline uint32_t A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val) 2737 { 2738 return ((val) << A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; 2739 } 2740 2741 #define REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x0000e099 2742 2743 #define REG_A5XX_GRAS_SC_CNTL 0x0000e0a0 2744 #define A5XX_GRAS_SC_CNTL_BINNING_PASS 0x00000001 2745 #define A5XX_GRAS_SC_CNTL_SAMPLES_PASSED 0x00008000 2746 2747 #define REG_A5XX_GRAS_SC_BIN_CNTL 0x0000e0a1 2748 2749 #define REG_A5XX_GRAS_SC_RAS_MSAA_CNTL 0x0000e0a2 2750 #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 2751 #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 2752 static inline uint32_t A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 2753 { 2754 return ((val) << A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK; 2755 } 2756 2757 #define REG_A5XX_GRAS_SC_DEST_MSAA_CNTL 0x0000e0a3 2758 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 2759 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 2760 static inline uint32_t A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 2761 { 2762 return ((val) << A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK; 2763 } 2764 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 2765 2766 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL 0x0000e0a4 2767 2768 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0 0x0000e0aa 2769 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000 2770 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK 0x00007fff 2771 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT 0 2772 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val) 2773 { 2774 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK; 2775 } 2776 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK 0x7fff0000 2777 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT 16 2778 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val) 2779 { 2780 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK; 2781 } 2782 2783 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0 0x0000e0ab 2784 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000 2785 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK 0x00007fff 2786 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT 0 2787 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val) 2788 { 2789 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK; 2790 } 2791 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK 0x7fff0000 2792 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT 16 2793 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val) 2794 { 2795 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK; 2796 } 2797 2798 #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0 0x0000e0ca 2799 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000 2800 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK 0x00007fff 2801 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT 0 2802 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val) 2803 { 2804 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK; 2805 } 2806 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK 0x7fff0000 2807 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT 16 2808 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val) 2809 { 2810 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK; 2811 } 2812 2813 #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0 0x0000e0cb 2814 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000 2815 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK 0x00007fff 2816 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT 0 2817 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val) 2818 { 2819 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK; 2820 } 2821 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK 0x7fff0000 2822 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT 16 2823 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val) 2824 { 2825 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK; 2826 } 2827 2828 #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000e0ea 2829 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 2830 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 2831 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 2832 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 2833 { 2834 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 2835 } 2836 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 2837 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 2838 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 2839 { 2840 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 2841 } 2842 2843 #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000e0eb 2844 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 2845 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 2846 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 2847 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 2848 { 2849 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 2850 } 2851 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 2852 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 2853 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 2854 { 2855 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 2856 } 2857 2858 #define REG_A5XX_GRAS_LRZ_CNTL 0x0000e100 2859 #define A5XX_GRAS_LRZ_CNTL_ENABLE 0x00000001 2860 #define A5XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002 2861 #define A5XX_GRAS_LRZ_CNTL_GREATER 0x00000004 2862 2863 #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO 0x0000e101 2864 2865 #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_HI 0x0000e102 2866 2867 #define REG_A5XX_GRAS_LRZ_BUFFER_PITCH 0x0000e103 2868 #define A5XX_GRAS_LRZ_BUFFER_PITCH__MASK 0xffffffff 2869 #define A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT 0 2870 static inline uint32_t A5XX_GRAS_LRZ_BUFFER_PITCH(uint32_t val) 2871 { 2872 return ((val >> 5) << A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT) & A5XX_GRAS_LRZ_BUFFER_PITCH__MASK; 2873 } 2874 2875 #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x0000e104 2876 2877 #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x0000e105 2878 2879 #define REG_A5XX_RB_CNTL 0x0000e140 2880 #define A5XX_RB_CNTL_WIDTH__MASK 0x000000ff 2881 #define A5XX_RB_CNTL_WIDTH__SHIFT 0 2882 static inline uint32_t A5XX_RB_CNTL_WIDTH(uint32_t val) 2883 { 2884 return ((val >> 5) << A5XX_RB_CNTL_WIDTH__SHIFT) & A5XX_RB_CNTL_WIDTH__MASK; 2885 } 2886 #define A5XX_RB_CNTL_HEIGHT__MASK 0x0001fe00 2887 #define A5XX_RB_CNTL_HEIGHT__SHIFT 9 2888 static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val) 2889 { 2890 return ((val >> 5) << A5XX_RB_CNTL_HEIGHT__SHIFT) & A5XX_RB_CNTL_HEIGHT__MASK; 2891 } 2892 #define A5XX_RB_CNTL_BYPASS 0x00020000 2893 2894 #define REG_A5XX_RB_RENDER_CNTL 0x0000e141 2895 #define A5XX_RB_RENDER_CNTL_BINNING_PASS 0x00000001 2896 #define A5XX_RB_RENDER_CNTL_SAMPLES_PASSED 0x00000040 2897 #define A5XX_RB_RENDER_CNTL_DISABLE_COLOR_PIPE 0x00000080 2898 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000 2899 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH2 0x00008000 2900 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000 2901 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16 2902 static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val) 2903 { 2904 return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK; 2905 } 2906 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK 0xff000000 2907 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT 24 2908 static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS2(uint32_t val) 2909 { 2910 return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK; 2911 } 2912 2913 #define REG_A5XX_RB_RAS_MSAA_CNTL 0x0000e142 2914 #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 2915 #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 2916 static inline uint32_t A5XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 2917 { 2918 return ((val) << A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK; 2919 } 2920 2921 #define REG_A5XX_RB_DEST_MSAA_CNTL 0x0000e143 2922 #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 2923 #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 2924 static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 2925 { 2926 return ((val) << A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK; 2927 } 2928 #define A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 2929 2930 #define REG_A5XX_RB_RENDER_CONTROL0 0x0000e144 2931 #define A5XX_RB_RENDER_CONTROL0_VARYING 0x00000001 2932 #define A5XX_RB_RENDER_CONTROL0_UNK3 0x00000008 2933 #define A5XX_RB_RENDER_CONTROL0_XCOORD 0x00000040 2934 #define A5XX_RB_RENDER_CONTROL0_YCOORD 0x00000080 2935 #define A5XX_RB_RENDER_CONTROL0_ZCOORD 0x00000100 2936 #define A5XX_RB_RENDER_CONTROL0_WCOORD 0x00000200 2937 2938 #define REG_A5XX_RB_RENDER_CONTROL1 0x0000e145 2939 #define A5XX_RB_RENDER_CONTROL1_FACENESS 0x00000002 2940 2941 #define REG_A5XX_RB_FS_OUTPUT_CNTL 0x0000e146 2942 #define A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f 2943 #define A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT 0 2944 static inline uint32_t A5XX_RB_FS_OUTPUT_CNTL_MRT(uint32_t val) 2945 { 2946 return ((val) << A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK; 2947 } 2948 #define A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z 0x00000020 2949 2950 #define REG_A5XX_RB_RENDER_COMPONENTS 0x0000e147 2951 #define A5XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f 2952 #define A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0 2953 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) 2954 { 2955 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT0__MASK; 2956 } 2957 #define A5XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0 2958 #define A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4 2959 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) 2960 { 2961 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT1__MASK; 2962 } 2963 #define A5XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00 2964 #define A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8 2965 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) 2966 { 2967 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT2__MASK; 2968 } 2969 #define A5XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000 2970 #define A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12 2971 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) 2972 { 2973 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT3__MASK; 2974 } 2975 #define A5XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000 2976 #define A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16 2977 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) 2978 { 2979 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT4__MASK; 2980 } 2981 #define A5XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000 2982 #define A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20 2983 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) 2984 { 2985 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT5__MASK; 2986 } 2987 #define A5XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000 2988 #define A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24 2989 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) 2990 { 2991 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT6__MASK; 2992 } 2993 #define A5XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000 2994 #define A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28 2995 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) 2996 { 2997 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT7__MASK; 2998 } 2999 3000 static inline uint32_t REG_A5XX_RB_MRT(uint32_t i0) { return 0x0000e150 + 0x7*i0; } 3001 3002 static inline uint32_t REG_A5XX_RB_MRT_CONTROL(uint32_t i0) { return 0x0000e150 + 0x7*i0; } 3003 #define A5XX_RB_MRT_CONTROL_BLEND 0x00000001 3004 #define A5XX_RB_MRT_CONTROL_BLEND2 0x00000002 3005 #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780 3006 #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7 3007 static inline uint32_t A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 3008 { 3009 return ((val) << A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 3010 } 3011 3012 static inline uint32_t REG_A5XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x0000e151 + 0x7*i0; } 3013 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 3014 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 3015 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 3016 { 3017 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 3018 } 3019 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 3020 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 3021 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 3022 { 3023 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 3024 } 3025 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 3026 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 3027 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 3028 { 3029 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 3030 } 3031 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 3032 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 3033 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 3034 { 3035 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 3036 } 3037 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 3038 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 3039 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 3040 { 3041 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 3042 } 3043 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 3044 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 3045 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 3046 { 3047 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 3048 } 3049 3050 static inline uint32_t REG_A5XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x0000e152 + 0x7*i0; } 3051 #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff 3052 #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 3053 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) 3054 { 3055 return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 3056 } 3057 #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300 3058 #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8 3059 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a5xx_tile_mode val) 3060 { 3061 return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 3062 } 3063 #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000 3064 #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13 3065 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 3066 { 3067 return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 3068 } 3069 #define A5XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00008000 3070 3071 static inline uint32_t REG_A5XX_RB_MRT_PITCH(uint32_t i0) { return 0x0000e153 + 0x7*i0; } 3072 #define A5XX_RB_MRT_PITCH__MASK 0xffffffff 3073 #define A5XX_RB_MRT_PITCH__SHIFT 0 3074 static inline uint32_t A5XX_RB_MRT_PITCH(uint32_t val) 3075 { 3076 return ((val >> 6) << A5XX_RB_MRT_PITCH__SHIFT) & A5XX_RB_MRT_PITCH__MASK; 3077 } 3078 3079 static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x0000e154 + 0x7*i0; } 3080 #define A5XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff 3081 #define A5XX_RB_MRT_ARRAY_PITCH__SHIFT 0 3082 static inline uint32_t A5XX_RB_MRT_ARRAY_PITCH(uint32_t val) 3083 { 3084 return ((val >> 6) << A5XX_RB_MRT_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_ARRAY_PITCH__MASK; 3085 } 3086 3087 static inline uint32_t REG_A5XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x0000e155 + 0x7*i0; } 3088 3089 static inline uint32_t REG_A5XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x0000e156 + 0x7*i0; } 3090 3091 #define REG_A5XX_RB_BLEND_RED 0x0000e1a0 3092 #define A5XX_RB_BLEND_RED_UINT__MASK 0x000000ff 3093 #define A5XX_RB_BLEND_RED_UINT__SHIFT 0 3094 static inline uint32_t A5XX_RB_BLEND_RED_UINT(uint32_t val) 3095 { 3096 return ((val) << A5XX_RB_BLEND_RED_UINT__SHIFT) & A5XX_RB_BLEND_RED_UINT__MASK; 3097 } 3098 #define A5XX_RB_BLEND_RED_SINT__MASK 0x0000ff00 3099 #define A5XX_RB_BLEND_RED_SINT__SHIFT 8 3100 static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val) 3101 { 3102 return ((val) << A5XX_RB_BLEND_RED_SINT__SHIFT) & A5XX_RB_BLEND_RED_SINT__MASK; 3103 } 3104 #define A5XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 3105 #define A5XX_RB_BLEND_RED_FLOAT__SHIFT 16 3106 static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val) 3107 { 3108 return ((util_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK; 3109 } 3110 3111 #define REG_A5XX_RB_BLEND_RED_F32 0x0000e1a1 3112 #define A5XX_RB_BLEND_RED_F32__MASK 0xffffffff 3113 #define A5XX_RB_BLEND_RED_F32__SHIFT 0 3114 static inline uint32_t A5XX_RB_BLEND_RED_F32(float val) 3115 { 3116 return ((fui(val)) << A5XX_RB_BLEND_RED_F32__SHIFT) & A5XX_RB_BLEND_RED_F32__MASK; 3117 } 3118 3119 #define REG_A5XX_RB_BLEND_GREEN 0x0000e1a2 3120 #define A5XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff 3121 #define A5XX_RB_BLEND_GREEN_UINT__SHIFT 0 3122 static inline uint32_t A5XX_RB_BLEND_GREEN_UINT(uint32_t val) 3123 { 3124 return ((val) << A5XX_RB_BLEND_GREEN_UINT__SHIFT) & A5XX_RB_BLEND_GREEN_UINT__MASK; 3125 } 3126 #define A5XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00 3127 #define A5XX_RB_BLEND_GREEN_SINT__SHIFT 8 3128 static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val) 3129 { 3130 return ((val) << A5XX_RB_BLEND_GREEN_SINT__SHIFT) & A5XX_RB_BLEND_GREEN_SINT__MASK; 3131 } 3132 #define A5XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 3133 #define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 3134 static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val) 3135 { 3136 return ((util_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK; 3137 } 3138 3139 #define REG_A5XX_RB_BLEND_GREEN_F32 0x0000e1a3 3140 #define A5XX_RB_BLEND_GREEN_F32__MASK 0xffffffff 3141 #define A5XX_RB_BLEND_GREEN_F32__SHIFT 0 3142 static inline uint32_t A5XX_RB_BLEND_GREEN_F32(float val) 3143 { 3144 return ((fui(val)) << A5XX_RB_BLEND_GREEN_F32__SHIFT) & A5XX_RB_BLEND_GREEN_F32__MASK; 3145 } 3146 3147 #define REG_A5XX_RB_BLEND_BLUE 0x0000e1a4 3148 #define A5XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff 3149 #define A5XX_RB_BLEND_BLUE_UINT__SHIFT 0 3150 static inline uint32_t A5XX_RB_BLEND_BLUE_UINT(uint32_t val) 3151 { 3152 return ((val) << A5XX_RB_BLEND_BLUE_UINT__SHIFT) & A5XX_RB_BLEND_BLUE_UINT__MASK; 3153 } 3154 #define A5XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00 3155 #define A5XX_RB_BLEND_BLUE_SINT__SHIFT 8 3156 static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val) 3157 { 3158 return ((val) << A5XX_RB_BLEND_BLUE_SINT__SHIFT) & A5XX_RB_BLEND_BLUE_SINT__MASK; 3159 } 3160 #define A5XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 3161 #define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 3162 static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val) 3163 { 3164 return ((util_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK; 3165 } 3166 3167 #define REG_A5XX_RB_BLEND_BLUE_F32 0x0000e1a5 3168 #define A5XX_RB_BLEND_BLUE_F32__MASK 0xffffffff 3169 #define A5XX_RB_BLEND_BLUE_F32__SHIFT 0 3170 static inline uint32_t A5XX_RB_BLEND_BLUE_F32(float val) 3171 { 3172 return ((fui(val)) << A5XX_RB_BLEND_BLUE_F32__SHIFT) & A5XX_RB_BLEND_BLUE_F32__MASK; 3173 } 3174 3175 #define REG_A5XX_RB_BLEND_ALPHA 0x0000e1a6 3176 #define A5XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff 3177 #define A5XX_RB_BLEND_ALPHA_UINT__SHIFT 0 3178 static inline uint32_t A5XX_RB_BLEND_ALPHA_UINT(uint32_t val) 3179 { 3180 return ((val) << A5XX_RB_BLEND_ALPHA_UINT__SHIFT) & A5XX_RB_BLEND_ALPHA_UINT__MASK; 3181 } 3182 #define A5XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00 3183 #define A5XX_RB_BLEND_ALPHA_SINT__SHIFT 8 3184 static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val) 3185 { 3186 return ((val) << A5XX_RB_BLEND_ALPHA_SINT__SHIFT) & A5XX_RB_BLEND_ALPHA_SINT__MASK; 3187 } 3188 #define A5XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 3189 #define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 3190 static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val) 3191 { 3192 return ((util_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK; 3193 } 3194 3195 #define REG_A5XX_RB_BLEND_ALPHA_F32 0x0000e1a7 3196 #define A5XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff 3197 #define A5XX_RB_BLEND_ALPHA_F32__SHIFT 0 3198 static inline uint32_t A5XX_RB_BLEND_ALPHA_F32(float val) 3199 { 3200 return ((fui(val)) << A5XX_RB_BLEND_ALPHA_F32__SHIFT) & A5XX_RB_BLEND_ALPHA_F32__MASK; 3201 } 3202 3203 #define REG_A5XX_RB_ALPHA_CONTROL 0x0000e1a8 3204 #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff 3205 #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 3206 static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) 3207 { 3208 return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; 3209 } 3210 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 3211 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 3212 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 3213 static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 3214 { 3215 return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; 3216 } 3217 3218 #define REG_A5XX_RB_BLEND_CNTL 0x0000e1a9 3219 #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff 3220 #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 3221 static inline uint32_t A5XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val) 3222 { 3223 return ((val) << A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK; 3224 } 3225 #define A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100 3226 #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000 3227 #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16 3228 static inline uint32_t A5XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val) 3229 { 3230 return ((val) << A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK; 3231 } 3232 3233 #define REG_A5XX_RB_DEPTH_PLANE_CNTL 0x0000e1b0 3234 #define A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001 3235 #define A5XX_RB_DEPTH_PLANE_CNTL_UNK1 0x00000002 3236 3237 #define REG_A5XX_RB_DEPTH_CNTL 0x0000e1b1 3238 #define A5XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001 3239 #define A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002 3240 #define A5XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c 3241 #define A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2 3242 static inline uint32_t A5XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) 3243 { 3244 return ((val) << A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A5XX_RB_DEPTH_CNTL_ZFUNC__MASK; 3245 } 3246 #define A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040 3247 3248 #define REG_A5XX_RB_DEPTH_BUFFER_INFO 0x0000e1b2 3249 #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 3250 #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 3251 static inline uint32_t A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val) 3252 { 3253 return ((val) << A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; 3254 } 3255 3256 #define REG_A5XX_RB_DEPTH_BUFFER_BASE_LO 0x0000e1b3 3257 3258 #define REG_A5XX_RB_DEPTH_BUFFER_BASE_HI 0x0000e1b4 3259 3260 #define REG_A5XX_RB_DEPTH_BUFFER_PITCH 0x0000e1b5 3261 #define A5XX_RB_DEPTH_BUFFER_PITCH__MASK 0xffffffff 3262 #define A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0 3263 static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) 3264 { 3265 return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_PITCH__MASK; 3266 } 3267 3268 #define REG_A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x0000e1b6 3269 #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0xffffffff 3270 #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0 3271 static inline uint32_t A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) 3272 { 3273 return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; 3274 } 3275 3276 #define REG_A5XX_RB_STENCIL_CONTROL 0x0000e1c0 3277 #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 3278 #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 3279 #define A5XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 3280 #define A5XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 3281 #define A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 3282 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 3283 { 3284 return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC__MASK; 3285 } 3286 #define A5XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 3287 #define A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 3288 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 3289 { 3290 return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL__MASK; 3291 } 3292 #define A5XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 3293 #define A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 3294 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 3295 { 3296 return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS__MASK; 3297 } 3298 #define A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 3299 #define A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 3300 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 3301 { 3302 return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 3303 } 3304 #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 3305 #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 3306 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 3307 { 3308 return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 3309 } 3310 #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 3311 #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 3312 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 3313 { 3314 return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 3315 } 3316 #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 3317 #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 3318 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 3319 { 3320 return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 3321 } 3322 #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 3323 #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 3324 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 3325 { 3326 return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 3327 } 3328 3329 #define REG_A5XX_RB_STENCIL_INFO 0x0000e1c1 3330 #define A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 3331 3332 #define REG_A5XX_RB_STENCIL_BASE_LO 0x0000e1c2 3333 3334 #define REG_A5XX_RB_STENCIL_BASE_HI 0x0000e1c3 3335 3336 #define REG_A5XX_RB_STENCIL_PITCH 0x0000e1c4 3337 #define A5XX_RB_STENCIL_PITCH__MASK 0xffffffff 3338 #define A5XX_RB_STENCIL_PITCH__SHIFT 0 3339 static inline uint32_t A5XX_RB_STENCIL_PITCH(uint32_t val) 3340 { 3341 return ((val >> 6) << A5XX_RB_STENCIL_PITCH__SHIFT) & A5XX_RB_STENCIL_PITCH__MASK; 3342 } 3343 3344 #define REG_A5XX_RB_STENCIL_ARRAY_PITCH 0x0000e1c5 3345 #define A5XX_RB_STENCIL_ARRAY_PITCH__MASK 0xffffffff 3346 #define A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT 0 3347 static inline uint32_t A5XX_RB_STENCIL_ARRAY_PITCH(uint32_t val) 3348 { 3349 return ((val >> 6) << A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT) & A5XX_RB_STENCIL_ARRAY_PITCH__MASK; 3350 } 3351 3352 #define REG_A5XX_RB_STENCILREFMASK 0x0000e1c6 3353 #define A5XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 3354 #define A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 3355 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 3356 { 3357 return ((val) << A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILREF__MASK; 3358 } 3359 #define A5XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 3360 #define A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 3361 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 3362 { 3363 return ((val) << A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILMASK__MASK; 3364 } 3365 #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 3366 #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 3367 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 3368 { 3369 return ((val) << A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 3370 } 3371 3372 #define REG_A5XX_UNKNOWN_E1C7 0x0000e1c7 3373 3374 #define REG_A5XX_RB_WINDOW_OFFSET 0x0000e1d0 3375 #define A5XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 3376 #define A5XX_RB_WINDOW_OFFSET_X__MASK 0x00007fff 3377 #define A5XX_RB_WINDOW_OFFSET_X__SHIFT 0 3378 static inline uint32_t A5XX_RB_WINDOW_OFFSET_X(uint32_t val) 3379 { 3380 return ((val) << A5XX_RB_WINDOW_OFFSET_X__SHIFT) & A5XX_RB_WINDOW_OFFSET_X__MASK; 3381 } 3382 #define A5XX_RB_WINDOW_OFFSET_Y__MASK 0x7fff0000 3383 #define A5XX_RB_WINDOW_OFFSET_Y__SHIFT 16 3384 static inline uint32_t A5XX_RB_WINDOW_OFFSET_Y(uint32_t val) 3385 { 3386 return ((val) << A5XX_RB_WINDOW_OFFSET_Y__SHIFT) & A5XX_RB_WINDOW_OFFSET_Y__MASK; 3387 } 3388 3389 #define REG_A5XX_RB_SAMPLE_COUNT_CONTROL 0x0000e1d1 3390 #define A5XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 3391 3392 #define REG_A5XX_RB_BLIT_CNTL 0x0000e210 3393 #define A5XX_RB_BLIT_CNTL_BUF__MASK 0x0000000f 3394 #define A5XX_RB_BLIT_CNTL_BUF__SHIFT 0 3395 static inline uint32_t A5XX_RB_BLIT_CNTL_BUF(enum a5xx_blit_buf val) 3396 { 3397 return ((val) << A5XX_RB_BLIT_CNTL_BUF__SHIFT) & A5XX_RB_BLIT_CNTL_BUF__MASK; 3398 } 3399 3400 #define REG_A5XX_RB_RESOLVE_CNTL_1 0x0000e211 3401 #define A5XX_RB_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE 0x80000000 3402 #define A5XX_RB_RESOLVE_CNTL_1_X__MASK 0x00007fff 3403 #define A5XX_RB_RESOLVE_CNTL_1_X__SHIFT 0 3404 static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_X(uint32_t val) 3405 { 3406 return ((val) << A5XX_RB_RESOLVE_CNTL_1_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_X__MASK; 3407 } 3408 #define A5XX_RB_RESOLVE_CNTL_1_Y__MASK 0x7fff0000 3409 #define A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT 16 3410 static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_Y(uint32_t val) 3411 { 3412 return ((val) << A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_Y__MASK; 3413 } 3414 3415 #define REG_A5XX_RB_RESOLVE_CNTL_2 0x0000e212 3416 #define A5XX_RB_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE 0x80000000 3417 #define A5XX_RB_RESOLVE_CNTL_2_X__MASK 0x00007fff 3418 #define A5XX_RB_RESOLVE_CNTL_2_X__SHIFT 0 3419 static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_X(uint32_t val) 3420 { 3421 return ((val) << A5XX_RB_RESOLVE_CNTL_2_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_X__MASK; 3422 } 3423 #define A5XX_RB_RESOLVE_CNTL_2_Y__MASK 0x7fff0000 3424 #define A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT 16 3425 static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_Y(uint32_t val) 3426 { 3427 return ((val) << A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_Y__MASK; 3428 } 3429 3430 #define REG_A5XX_RB_RESOLVE_CNTL_3 0x0000e213 3431 3432 #define REG_A5XX_RB_BLIT_DST_LO 0x0000e214 3433 3434 #define REG_A5XX_RB_BLIT_DST_HI 0x0000e215 3435 3436 #define REG_A5XX_RB_BLIT_DST_PITCH 0x0000e216 3437 #define A5XX_RB_BLIT_DST_PITCH__MASK 0xffffffff 3438 #define A5XX_RB_BLIT_DST_PITCH__SHIFT 0 3439 static inline uint32_t A5XX_RB_BLIT_DST_PITCH(uint32_t val) 3440 { 3441 return ((val >> 6) << A5XX_RB_BLIT_DST_PITCH__SHIFT) & A5XX_RB_BLIT_DST_PITCH__MASK; 3442 } 3443 3444 #define REG_A5XX_RB_BLIT_DST_ARRAY_PITCH 0x0000e217 3445 #define A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0xffffffff 3446 #define A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0 3447 static inline uint32_t A5XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) 3448 { 3449 return ((val >> 6) << A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK; 3450 } 3451 3452 #define REG_A5XX_RB_CLEAR_COLOR_DW0 0x0000e218 3453 3454 #define REG_A5XX_RB_CLEAR_COLOR_DW1 0x0000e219 3455 3456 #define REG_A5XX_RB_CLEAR_COLOR_DW2 0x0000e21a 3457 3458 #define REG_A5XX_RB_CLEAR_COLOR_DW3 0x0000e21b 3459 3460 #define REG_A5XX_RB_CLEAR_CNTL 0x0000e21c 3461 #define A5XX_RB_CLEAR_CNTL_FAST_CLEAR 0x00000002 3462 #define A5XX_RB_CLEAR_CNTL_MASK__MASK 0x000000f0 3463 #define A5XX_RB_CLEAR_CNTL_MASK__SHIFT 4 3464 static inline uint32_t A5XX_RB_CLEAR_CNTL_MASK(uint32_t val) 3465 { 3466 return ((val) << A5XX_RB_CLEAR_CNTL_MASK__SHIFT) & A5XX_RB_CLEAR_CNTL_MASK__MASK; 3467 } 3468 3469 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x0000e240 3470 3471 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x0000e241 3472 3473 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x0000e242 3474 3475 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x0000e243 + 0x4*i0; } 3476 3477 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x0000e243 + 0x4*i0; } 3478 3479 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x0000e244 + 0x4*i0; } 3480 3481 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x0000e245 + 0x4*i0; } 3482 #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK 0xffffffff 3483 #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT 0 3484 static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t val) 3485 { 3486 return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK; 3487 } 3488 3489 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0) { return 0x0000e246 + 0x4*i0; } 3490 #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK 0xffffffff 3491 #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0 3492 static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) 3493 { 3494 return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK; 3495 } 3496 3497 #define REG_A5XX_RB_BLIT_FLAG_DST_LO 0x0000e263 3498 3499 #define REG_A5XX_RB_BLIT_FLAG_DST_HI 0x0000e264 3500 3501 #define REG_A5XX_RB_BLIT_FLAG_DST_PITCH 0x0000e265 3502 #define A5XX_RB_BLIT_FLAG_DST_PITCH__MASK 0xffffffff 3503 #define A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT 0 3504 static inline uint32_t A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val) 3505 { 3506 return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_PITCH__MASK; 3507 } 3508 3509 #define REG_A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH 0x0000e266 3510 #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK 0xffffffff 3511 #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT 0 3512 static inline uint32_t A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val) 3513 { 3514 return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK; 3515 } 3516 3517 #define REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO 0x0000e267 3518 3519 #define REG_A5XX_RB_SAMPLE_COUNT_ADDR_HI 0x0000e268 3520 3521 #define REG_A5XX_VPC_CNTL_0 0x0000e280 3522 #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK 0x0000007f 3523 #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT 0 3524 static inline uint32_t A5XX_VPC_CNTL_0_STRIDE_IN_VPC(uint32_t val) 3525 { 3526 return ((val) << A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT) & A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK; 3527 } 3528 #define A5XX_VPC_CNTL_0_VARYING 0x00000800 3529 3530 static inline uint32_t REG_A5XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x0000e282 + 0x1*i0; } 3531 3532 static inline uint32_t REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x0000e282 + 0x1*i0; } 3533 3534 static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000e28a + 0x1*i0; } 3535 3536 static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000e28a + 0x1*i0; } 3537 3538 #define REG_A5XX_UNKNOWN_E292 0x0000e292 3539 3540 #define REG_A5XX_UNKNOWN_E293 0x0000e293 3541 3542 static inline uint32_t REG_A5XX_VPC_VAR(uint32_t i0) { return 0x0000e294 + 0x1*i0; } 3543 3544 static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 + 0x1*i0; } 3545 3546 #define REG_A5XX_VPC_GS_SIV_CNTL 0x0000e298 3547 3548 #define REG_A5XX_UNKNOWN_E29A 0x0000e29a 3549 3550 #define REG_A5XX_VPC_PACK 0x0000e29d 3551 #define A5XX_VPC_PACK_NUMNONPOSVAR__MASK 0x000000ff 3552 #define A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT 0 3553 static inline uint32_t A5XX_VPC_PACK_NUMNONPOSVAR(uint32_t val) 3554 { 3555 return ((val) << A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A5XX_VPC_PACK_NUMNONPOSVAR__MASK; 3556 } 3557 #define A5XX_VPC_PACK_PSIZELOC__MASK 0x0000ff00 3558 #define A5XX_VPC_PACK_PSIZELOC__SHIFT 8 3559 static inline uint32_t A5XX_VPC_PACK_PSIZELOC(uint32_t val) 3560 { 3561 return ((val) << A5XX_VPC_PACK_PSIZELOC__SHIFT) & A5XX_VPC_PACK_PSIZELOC__MASK; 3562 } 3563 3564 #define REG_A5XX_VPC_FS_PRIMITIVEID_CNTL 0x0000e2a0 3565 3566 #define REG_A5XX_VPC_SO_BUF_CNTL 0x0000e2a1 3567 #define A5XX_VPC_SO_BUF_CNTL_BUF0 0x00000001 3568 #define A5XX_VPC_SO_BUF_CNTL_BUF1 0x00000008 3569 #define A5XX_VPC_SO_BUF_CNTL_BUF2 0x00000040 3570 #define A5XX_VPC_SO_BUF_CNTL_BUF3 0x00000200 3571 #define A5XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000 3572 3573 #define REG_A5XX_VPC_SO_OVERRIDE 0x0000e2a2 3574 #define A5XX_VPC_SO_OVERRIDE_SO_DISABLE 0x00000001 3575 3576 #define REG_A5XX_VPC_SO_CNTL 0x0000e2a3 3577 #define A5XX_VPC_SO_CNTL_ENABLE 0x00010000 3578 3579 #define REG_A5XX_VPC_SO_PROG 0x0000e2a4 3580 #define A5XX_VPC_SO_PROG_A_BUF__MASK 0x00000003 3581 #define A5XX_VPC_SO_PROG_A_BUF__SHIFT 0 3582 static inline uint32_t A5XX_VPC_SO_PROG_A_BUF(uint32_t val) 3583 { 3584 return ((val) << A5XX_VPC_SO_PROG_A_BUF__SHIFT) & A5XX_VPC_SO_PROG_A_BUF__MASK; 3585 } 3586 #define A5XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc 3587 #define A5XX_VPC_SO_PROG_A_OFF__SHIFT 2 3588 static inline uint32_t A5XX_VPC_SO_PROG_A_OFF(uint32_t val) 3589 { 3590 return ((val >> 2) << A5XX_VPC_SO_PROG_A_OFF__SHIFT) & A5XX_VPC_SO_PROG_A_OFF__MASK; 3591 } 3592 #define A5XX_VPC_SO_PROG_A_EN 0x00000800 3593 #define A5XX_VPC_SO_PROG_B_BUF__MASK 0x00003000 3594 #define A5XX_VPC_SO_PROG_B_BUF__SHIFT 12 3595 static inline uint32_t A5XX_VPC_SO_PROG_B_BUF(uint32_t val) 3596 { 3597 return ((val) << A5XX_VPC_SO_PROG_B_BUF__SHIFT) & A5XX_VPC_SO_PROG_B_BUF__MASK; 3598 } 3599 #define A5XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000 3600 #define A5XX_VPC_SO_PROG_B_OFF__SHIFT 14 3601 static inline uint32_t A5XX_VPC_SO_PROG_B_OFF(uint32_t val) 3602 { 3603 return ((val >> 2) << A5XX_VPC_SO_PROG_B_OFF__SHIFT) & A5XX_VPC_SO_PROG_B_OFF__MASK; 3604 } 3605 #define A5XX_VPC_SO_PROG_B_EN 0x00800000 3606 3607 static inline uint32_t REG_A5XX_VPC_SO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; } 3608 3609 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; } 3610 3611 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000e2a8 + 0x7*i0; } 3612 3613 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000e2a9 + 0x7*i0; } 3614 3615 static inline uint32_t REG_A5XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000e2aa + 0x7*i0; } 3616 3617 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000e2ab + 0x7*i0; } 3618 3619 static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000e2ac + 0x7*i0; } 3620 3621 static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x0000e2ad + 0x7*i0; } 3622 3623 #define REG_A5XX_PC_PRIMITIVE_CNTL 0x0000e384 3624 #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK 0x0000007f 3625 #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT 0 3626 static inline uint32_t A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val) 3627 { 3628 return ((val) << A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT) & A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK; 3629 } 3630 #define A5XX_PC_PRIMITIVE_CNTL_PROVOKING_VTX_LAST 0x00000400 3631 3632 #define REG_A5XX_PC_PRIM_VTX_CNTL 0x0000e385 3633 #define A5XX_PC_PRIM_VTX_CNTL_PSIZE 0x00000800 3634 3635 #define REG_A5XX_PC_RASTER_CNTL 0x0000e388 3636 3637 #define REG_A5XX_UNKNOWN_E389 0x0000e389 3638 3639 #define REG_A5XX_PC_RESTART_INDEX 0x0000e38c 3640 3641 #define REG_A5XX_UNKNOWN_E38D 0x0000e38d 3642 3643 #define REG_A5XX_PC_GS_PARAM 0x0000e38e 3644 3645 #define REG_A5XX_PC_HS_PARAM 0x0000e38f 3646 3647 #define REG_A5XX_PC_POWER_CNTL 0x0000e3b0 3648 3649 #define REG_A5XX_VFD_CONTROL_0 0x0000e400 3650 #define A5XX_VFD_CONTROL_0_VTXCNT__MASK 0x0000003f 3651 #define A5XX_VFD_CONTROL_0_VTXCNT__SHIFT 0 3652 static inline uint32_t A5XX_VFD_CONTROL_0_VTXCNT(uint32_t val) 3653 { 3654 return ((val) << A5XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A5XX_VFD_CONTROL_0_VTXCNT__MASK; 3655 } 3656 3657 #define REG_A5XX_VFD_CONTROL_1 0x0000e401 3658 #define A5XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff 3659 #define A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0 3660 static inline uint32_t A5XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 3661 { 3662 return ((val) << A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A5XX_VFD_CONTROL_1_REGID4VTX__MASK; 3663 } 3664 #define A5XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00 3665 #define A5XX_VFD_CONTROL_1_REGID4INST__SHIFT 8 3666 static inline uint32_t A5XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 3667 { 3668 return ((val) << A5XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A5XX_VFD_CONTROL_1_REGID4INST__MASK; 3669 } 3670 3671 #define REG_A5XX_VFD_CONTROL_2 0x0000e402 3672 3673 #define REG_A5XX_VFD_CONTROL_3 0x0000e403 3674 3675 #define REG_A5XX_VFD_CONTROL_4 0x0000e404 3676 3677 #define REG_A5XX_VFD_CONTROL_5 0x0000e405 3678 3679 #define REG_A5XX_VFD_INDEX_OFFSET 0x0000e408 3680 3681 #define REG_A5XX_VFD_INSTANCE_START_OFFSET 0x0000e409 3682 3683 static inline uint32_t REG_A5XX_VFD_FETCH(uint32_t i0) { return 0x0000e40a + 0x4*i0; } 3684 3685 static inline uint32_t REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000e40a + 0x4*i0; } 3686 3687 static inline uint32_t REG_A5XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000e40b + 0x4*i0; } 3688 3689 static inline uint32_t REG_A5XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000e40c + 0x4*i0; } 3690 3691 static inline uint32_t REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000e40d + 0x4*i0; } 3692 3693 static inline uint32_t REG_A5XX_VFD_DECODE(uint32_t i0) { return 0x0000e48a + 0x2*i0; } 3694 3695 static inline uint32_t REG_A5XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000e48a + 0x2*i0; } 3696 #define A5XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f 3697 #define A5XX_VFD_DECODE_INSTR_IDX__SHIFT 0 3698 static inline uint32_t A5XX_VFD_DECODE_INSTR_IDX(uint32_t val) 3699 { 3700 return ((val) << A5XX_VFD_DECODE_INSTR_IDX__SHIFT) & A5XX_VFD_DECODE_INSTR_IDX__MASK; 3701 } 3702 #define A5XX_VFD_DECODE_INSTR_INSTANCED 0x00020000 3703 #define A5XX_VFD_DECODE_INSTR_FORMAT__MASK 0x3ff00000 3704 #define A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20 3705 static inline uint32_t A5XX_VFD_DECODE_INSTR_FORMAT(enum a5xx_vtx_fmt val) 3706 { 3707 return ((val) << A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A5XX_VFD_DECODE_INSTR_FORMAT__MASK; 3708 } 3709 #define A5XX_VFD_DECODE_INSTR_UNK30 0x40000000 3710 #define A5XX_VFD_DECODE_INSTR_FLOAT 0x80000000 3711 3712 static inline uint32_t REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000e48b + 0x2*i0; } 3713 3714 static inline uint32_t REG_A5XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000e4ca + 0x1*i0; } 3715 3716 static inline uint32_t REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000e4ca + 0x1*i0; } 3717 #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f 3718 #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0 3719 static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val) 3720 { 3721 return ((val) << A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK; 3722 } 3723 #define A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0 3724 #define A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4 3725 static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) 3726 { 3727 return ((val) << A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK; 3728 } 3729 3730 #define REG_A5XX_VFD_POWER_CNTL 0x0000e4f0 3731 3732 #define REG_A5XX_SP_SP_CNTL 0x0000e580 3733 3734 #define REG_A5XX_SP_VS_CONFIG 0x0000e584 3735 #define A5XX_SP_VS_CONFIG_ENABLED 0x00000001 3736 #define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 3737 #define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 3738 static inline uint32_t A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 3739 { 3740 return ((val) << A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK; 3741 } 3742 #define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 3743 #define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT 8 3744 static inline uint32_t A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(uint32_t val) 3745 { 3746 return ((val) << A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK; 3747 } 3748 3749 #define REG_A5XX_SP_FS_CONFIG 0x0000e585 3750 #define A5XX_SP_FS_CONFIG_ENABLED 0x00000001 3751 #define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 3752 #define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 3753 static inline uint32_t A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 3754 { 3755 return ((val) << A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK; 3756 } 3757 #define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 3758 #define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT 8 3759 static inline uint32_t A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(uint32_t val) 3760 { 3761 return ((val) << A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK; 3762 } 3763 3764 #define REG_A5XX_SP_HS_CONFIG 0x0000e586 3765 #define A5XX_SP_HS_CONFIG_ENABLED 0x00000001 3766 #define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 3767 #define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 3768 static inline uint32_t A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 3769 { 3770 return ((val) << A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK; 3771 } 3772 #define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 3773 #define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT 8 3774 static inline uint32_t A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(uint32_t val) 3775 { 3776 return ((val) << A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK; 3777 } 3778 3779 #define REG_A5XX_SP_DS_CONFIG 0x0000e587 3780 #define A5XX_SP_DS_CONFIG_ENABLED 0x00000001 3781 #define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 3782 #define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 3783 static inline uint32_t A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 3784 { 3785 return ((val) << A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK; 3786 } 3787 #define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 3788 #define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT 8 3789 static inline uint32_t A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(uint32_t val) 3790 { 3791 return ((val) << A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK; 3792 } 3793 3794 #define REG_A5XX_SP_GS_CONFIG 0x0000e588 3795 #define A5XX_SP_GS_CONFIG_ENABLED 0x00000001 3796 #define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 3797 #define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 3798 static inline uint32_t A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 3799 { 3800 return ((val) << A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK; 3801 } 3802 #define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 3803 #define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT 8 3804 static inline uint32_t A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(uint32_t val) 3805 { 3806 return ((val) << A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK; 3807 } 3808 3809 #define REG_A5XX_SP_CS_CONFIG 0x0000e589 3810 #define A5XX_SP_CS_CONFIG_ENABLED 0x00000001 3811 #define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 3812 #define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 3813 static inline uint32_t A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 3814 { 3815 return ((val) << A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK; 3816 } 3817 #define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 3818 #define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT 8 3819 static inline uint32_t A5XX_SP_CS_CONFIG_SHADEROBJOFFSET(uint32_t val) 3820 { 3821 return ((val) << A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK; 3822 } 3823 3824 #define REG_A5XX_SP_VS_CONFIG_MAX_CONST 0x0000e58a 3825 3826 #define REG_A5XX_SP_FS_CONFIG_MAX_CONST 0x0000e58b 3827 3828 #define REG_A5XX_SP_VS_CTRL_REG0 0x0000e590 3829 #define A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00000008 3830 #define A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 3 3831 static inline uint32_t A5XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 3832 { 3833 return ((val) << A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; 3834 } 3835 #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 3836 #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 3837 static inline uint32_t A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 3838 { 3839 return ((val) << A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 3840 } 3841 #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 3842 #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 3843 static inline uint32_t A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 3844 { 3845 return ((val) << A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 3846 } 3847 #define A5XX_SP_VS_CTRL_REG0_VARYING 0x00010000 3848 #define A5XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00100000 3849 #define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000 3850 #define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 25 3851 static inline uint32_t A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val) 3852 { 3853 return ((val) << A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK; 3854 } 3855 3856 #define REG_A5XX_SP_PRIMITIVE_CNTL 0x0000e592 3857 #define A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK 0x0000001f 3858 #define A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT 0 3859 static inline uint32_t A5XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val) 3860 { 3861 return ((val) << A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT) & A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK; 3862 } 3863 3864 static inline uint32_t REG_A5XX_SP_VS_OUT(uint32_t i0) { return 0x0000e593 + 0x1*i0; } 3865 3866 static inline uint32_t REG_A5XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000e593 + 0x1*i0; } 3867 #define A5XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff 3868 #define A5XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 3869 static inline uint32_t A5XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 3870 { 3871 return ((val) << A5XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_A_REGID__MASK; 3872 } 3873 #define A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00 3874 #define A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8 3875 static inline uint32_t A5XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 3876 { 3877 return ((val) << A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 3878 } 3879 #define A5XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000 3880 #define A5XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 3881 static inline uint32_t A5XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 3882 { 3883 return ((val) << A5XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_B_REGID__MASK; 3884 } 3885 #define A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000 3886 #define A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24 3887 static inline uint32_t A5XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 3888 { 3889 return ((val) << A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 3890 } 3891 3892 static inline uint32_t REG_A5XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; } 3893 3894 static inline uint32_t REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; } 3895 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 3896 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 3897 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 3898 { 3899 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 3900 } 3901 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 3902 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 3903 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 3904 { 3905 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 3906 } 3907 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 3908 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 3909 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 3910 { 3911 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 3912 } 3913 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 3914 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 3915 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 3916 { 3917 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 3918 } 3919 3920 #define REG_A5XX_UNKNOWN_E5AB 0x0000e5ab 3921 3922 #define REG_A5XX_SP_VS_OBJ_START_LO 0x0000e5ac 3923 3924 #define REG_A5XX_SP_VS_OBJ_START_HI 0x0000e5ad 3925 3926 #define REG_A5XX_SP_FS_CTRL_REG0 0x0000e5c0 3927 #define A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00000008 3928 #define A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 3 3929 static inline uint32_t A5XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 3930 { 3931 return ((val) << A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 3932 } 3933 #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 3934 #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 3935 static inline uint32_t A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 3936 { 3937 return ((val) << A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 3938 } 3939 #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 3940 #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 3941 static inline uint32_t A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 3942 { 3943 return ((val) << A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 3944 } 3945 #define A5XX_SP_FS_CTRL_REG0_VARYING 0x00010000 3946 #define A5XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00100000 3947 #define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000 3948 #define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 25 3949 static inline uint32_t A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) 3950 { 3951 return ((val) << A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK; 3952 } 3953 3954 #define REG_A5XX_UNKNOWN_E5C2 0x0000e5c2 3955 3956 #define REG_A5XX_SP_FS_OBJ_START_LO 0x0000e5c3 3957 3958 #define REG_A5XX_SP_FS_OBJ_START_HI 0x0000e5c4 3959 3960 #define REG_A5XX_SP_BLEND_CNTL 0x0000e5c9 3961 #define A5XX_SP_BLEND_CNTL_ENABLED 0x00000001 3962 #define A5XX_SP_BLEND_CNTL_UNK8 0x00000100 3963 3964 #define REG_A5XX_SP_FS_OUTPUT_CNTL 0x0000e5ca 3965 #define A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f 3966 #define A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT 0 3967 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_MRT(uint32_t val) 3968 { 3969 return ((val) << A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK; 3970 } 3971 #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK 0x00001fe0 3972 #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT 5 3973 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(uint32_t val) 3974 { 3975 return ((val) << A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK; 3976 } 3977 #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK 0x001fe000 3978 #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT 13 3979 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(uint32_t val) 3980 { 3981 return ((val) << A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK; 3982 } 3983 3984 static inline uint32_t REG_A5XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000e5cb + 0x1*i0; } 3985 3986 static inline uint32_t REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000e5cb + 0x1*i0; } 3987 #define A5XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff 3988 #define A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0 3989 static inline uint32_t A5XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) 3990 { 3991 return ((val) << A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_REG_REGID__MASK; 3992 } 3993 #define A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100 3994 3995 static inline uint32_t REG_A5XX_SP_FS_MRT(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; } 3996 3997 static inline uint32_t REG_A5XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; } 3998 #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff 3999 #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0 4000 static inline uint32_t A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val) 4001 { 4002 return ((val) << A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK; 4003 } 4004 #define A5XX_SP_FS_MRT_REG_COLOR_SRGB 0x00000400 4005 4006 #define REG_A5XX_UNKNOWN_E5DB 0x0000e5db 4007 4008 #define REG_A5XX_UNKNOWN_E5F2 0x0000e5f2 4009 4010 #define REG_A5XX_SP_CS_OBJ_START_LO 0x0000e5f3 4011 4012 #define REG_A5XX_SP_CS_OBJ_START_HI 0x0000e5f4 4013 4014 #define REG_A5XX_SP_CS_CTRL_REG0 0x0000e5f0 4015 #define A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00000008 4016 #define A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 3 4017 static inline uint32_t A5XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 4018 { 4019 return ((val) << A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK; 4020 } 4021 #define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 4022 #define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 4023 static inline uint32_t A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 4024 { 4025 return ((val) << A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 4026 } 4027 #define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 4028 #define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 4029 static inline uint32_t A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 4030 { 4031 return ((val) << A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 4032 } 4033 #define A5XX_SP_CS_CTRL_REG0_VARYING 0x00010000 4034 #define A5XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x00100000 4035 #define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000 4036 #define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 25 4037 static inline uint32_t A5XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val) 4038 { 4039 return ((val) << A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK; 4040 } 4041 4042 #define REG_A5XX_UNKNOWN_E600 0x0000e600 4043 4044 #define REG_A5XX_UNKNOWN_E602 0x0000e602 4045 4046 #define REG_A5XX_SP_HS_OBJ_START_LO 0x0000e603 4047 4048 #define REG_A5XX_SP_HS_OBJ_START_HI 0x0000e604 4049 4050 #define REG_A5XX_UNKNOWN_E62B 0x0000e62b 4051 4052 #define REG_A5XX_SP_DS_OBJ_START_LO 0x0000e62c 4053 4054 #define REG_A5XX_SP_DS_OBJ_START_HI 0x0000e62d 4055 4056 #define REG_A5XX_UNKNOWN_E640 0x0000e640 4057 4058 #define REG_A5XX_UNKNOWN_E65B 0x0000e65b 4059 4060 #define REG_A5XX_SP_GS_OBJ_START_LO 0x0000e65c 4061 4062 #define REG_A5XX_SP_GS_OBJ_START_HI 0x0000e65d 4063 4064 #define REG_A5XX_TPL1_TP_RAS_MSAA_CNTL 0x0000e704 4065 #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 4066 #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 4067 static inline uint32_t A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 4068 { 4069 return ((val) << A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK; 4070 } 4071 4072 #define REG_A5XX_TPL1_TP_DEST_MSAA_CNTL 0x0000e705 4073 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 4074 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 4075 static inline uint32_t A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 4076 { 4077 return ((val) << A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK; 4078 } 4079 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 4080 4081 #define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO 0x0000e706 4082 4083 #define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_HI 0x0000e707 4084 4085 #define REG_A5XX_TPL1_VS_TEX_COUNT 0x0000e700 4086 4087 #define REG_A5XX_TPL1_HS_TEX_COUNT 0x0000e701 4088 4089 #define REG_A5XX_TPL1_DS_TEX_COUNT 0x0000e702 4090 4091 #define REG_A5XX_TPL1_GS_TEX_COUNT 0x0000e703 4092 4093 #define REG_A5XX_TPL1_VS_TEX_SAMP_LO 0x0000e722 4094 4095 #define REG_A5XX_TPL1_VS_TEX_SAMP_HI 0x0000e723 4096 4097 #define REG_A5XX_TPL1_HS_TEX_SAMP_LO 0x0000e724 4098 4099 #define REG_A5XX_TPL1_HS_TEX_SAMP_HI 0x0000e725 4100 4101 #define REG_A5XX_TPL1_DS_TEX_SAMP_LO 0x0000e726 4102 4103 #define REG_A5XX_TPL1_DS_TEX_SAMP_HI 0x0000e727 4104 4105 #define REG_A5XX_TPL1_GS_TEX_SAMP_LO 0x0000e728 4106 4107 #define REG_A5XX_TPL1_GS_TEX_SAMP_HI 0x0000e729 4108 4109 #define REG_A5XX_TPL1_VS_TEX_CONST_LO 0x0000e72a 4110 4111 #define REG_A5XX_TPL1_VS_TEX_CONST_HI 0x0000e72b 4112 4113 #define REG_A5XX_TPL1_HS_TEX_CONST_LO 0x0000e72c 4114 4115 #define REG_A5XX_TPL1_HS_TEX_CONST_HI 0x0000e72d 4116 4117 #define REG_A5XX_TPL1_DS_TEX_CONST_LO 0x0000e72e 4118 4119 #define REG_A5XX_TPL1_DS_TEX_CONST_HI 0x0000e72f 4120 4121 #define REG_A5XX_TPL1_GS_TEX_CONST_LO 0x0000e730 4122 4123 #define REG_A5XX_TPL1_GS_TEX_CONST_HI 0x0000e731 4124 4125 #define REG_A5XX_TPL1_FS_TEX_COUNT 0x0000e750 4126 4127 #define REG_A5XX_TPL1_CS_TEX_COUNT 0x0000e751 4128 4129 #define REG_A5XX_TPL1_FS_TEX_SAMP_LO 0x0000e75a 4130 4131 #define REG_A5XX_TPL1_FS_TEX_SAMP_HI 0x0000e75b 4132 4133 #define REG_A5XX_TPL1_CS_TEX_SAMP_LO 0x0000e75c 4134 4135 #define REG_A5XX_TPL1_CS_TEX_SAMP_HI 0x0000e75d 4136 4137 #define REG_A5XX_TPL1_FS_TEX_CONST_LO 0x0000e75e 4138 4139 #define REG_A5XX_TPL1_FS_TEX_CONST_HI 0x0000e75f 4140 4141 #define REG_A5XX_TPL1_CS_TEX_CONST_LO 0x0000e760 4142 4143 #define REG_A5XX_TPL1_CS_TEX_CONST_HI 0x0000e761 4144 4145 #define REG_A5XX_TPL1_TP_FS_ROTATION_CNTL 0x0000e764 4146 4147 #define REG_A5XX_HLSQ_CONTROL_0_REG 0x0000e784 4148 #define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000001 4149 #define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 0 4150 static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) 4151 { 4152 return ((val) << A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; 4153 } 4154 #define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK 0x00000004 4155 #define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT 2 4156 static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(enum a3xx_threadsize val) 4157 { 4158 return ((val) << A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK; 4159 } 4160 4161 #define REG_A5XX_HLSQ_CONTROL_1_REG 0x0000e785 4162 #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x0000003f 4163 #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT 0 4164 static inline uint32_t A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val) 4165 { 4166 return ((val) << A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK; 4167 } 4168 4169 #define REG_A5XX_HLSQ_CONTROL_2_REG 0x0000e786 4170 #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff 4171 #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0 4172 static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) 4173 { 4174 return ((val) << A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; 4175 } 4176 4177 #define REG_A5XX_HLSQ_CONTROL_3_REG 0x0000e787 4178 #define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK 0x000000ff 4179 #define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT 0 4180 static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val) 4181 { 4182 return ((val) << A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK; 4183 } 4184 4185 #define REG_A5XX_HLSQ_CONTROL_4_REG 0x0000e788 4186 #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000 4187 #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16 4188 static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) 4189 { 4190 return ((val) << A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK; 4191 } 4192 #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000 4193 #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24 4194 static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) 4195 { 4196 return ((val) << A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; 4197 } 4198 4199 #define REG_A5XX_HLSQ_UPDATE_CNTL 0x0000e78a 4200 4201 #define REG_A5XX_HLSQ_VS_CONFIG 0x0000e78b 4202 #define A5XX_HLSQ_VS_CONFIG_ENABLED 0x00000001 4203 #define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 4204 #define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 4205 static inline uint32_t A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 4206 { 4207 return ((val) << A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK; 4208 } 4209 #define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 4210 #define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT 8 4211 static inline uint32_t A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(uint32_t val) 4212 { 4213 return ((val) << A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK; 4214 } 4215 4216 #define REG_A5XX_HLSQ_FS_CONFIG 0x0000e78c 4217 #define A5XX_HLSQ_FS_CONFIG_ENABLED 0x00000001 4218 #define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 4219 #define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 4220 static inline uint32_t A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 4221 { 4222 return ((val) << A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK; 4223 } 4224 #define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 4225 #define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT 8 4226 static inline uint32_t A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(uint32_t val) 4227 { 4228 return ((val) << A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK; 4229 } 4230 4231 #define REG_A5XX_HLSQ_HS_CONFIG 0x0000e78d 4232 #define A5XX_HLSQ_HS_CONFIG_ENABLED 0x00000001 4233 #define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 4234 #define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 4235 static inline uint32_t A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 4236 { 4237 return ((val) << A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK; 4238 } 4239 #define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 4240 #define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT 8 4241 static inline uint32_t A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(uint32_t val) 4242 { 4243 return ((val) << A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK; 4244 } 4245 4246 #define REG_A5XX_HLSQ_DS_CONFIG 0x0000e78e 4247 #define A5XX_HLSQ_DS_CONFIG_ENABLED 0x00000001 4248 #define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 4249 #define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 4250 static inline uint32_t A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 4251 { 4252 return ((val) << A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK; 4253 } 4254 #define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 4255 #define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT 8 4256 static inline uint32_t A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(uint32_t val) 4257 { 4258 return ((val) << A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK; 4259 } 4260 4261 #define REG_A5XX_HLSQ_GS_CONFIG 0x0000e78f 4262 #define A5XX_HLSQ_GS_CONFIG_ENABLED 0x00000001 4263 #define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 4264 #define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 4265 static inline uint32_t A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 4266 { 4267 return ((val) << A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK; 4268 } 4269 #define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 4270 #define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT 8 4271 static inline uint32_t A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(uint32_t val) 4272 { 4273 return ((val) << A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK; 4274 } 4275 4276 #define REG_A5XX_HLSQ_CS_CONFIG 0x0000e790 4277 #define A5XX_HLSQ_CS_CONFIG_ENABLED 0x00000001 4278 #define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 4279 #define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 4280 static inline uint32_t A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 4281 { 4282 return ((val) << A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK; 4283 } 4284 #define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 4285 #define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT 8 4286 static inline uint32_t A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET(uint32_t val) 4287 { 4288 return ((val) << A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK; 4289 } 4290 4291 #define REG_A5XX_HLSQ_VS_CNTL 0x0000e791 4292 #define A5XX_HLSQ_VS_CNTL_SSBO_ENABLE 0x00000001 4293 #define A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK 0xfffffffe 4294 #define A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT 1 4295 static inline uint32_t A5XX_HLSQ_VS_CNTL_INSTRLEN(uint32_t val) 4296 { 4297 return ((val) << A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK; 4298 } 4299 4300 #define REG_A5XX_HLSQ_FS_CNTL 0x0000e792 4301 #define A5XX_HLSQ_FS_CNTL_SSBO_ENABLE 0x00000001 4302 #define A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK 0xfffffffe 4303 #define A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT 1 4304 static inline uint32_t A5XX_HLSQ_FS_CNTL_INSTRLEN(uint32_t val) 4305 { 4306 return ((val) << A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK; 4307 } 4308 4309 #define REG_A5XX_HLSQ_HS_CNTL 0x0000e793 4310 #define A5XX_HLSQ_HS_CNTL_SSBO_ENABLE 0x00000001 4311 #define A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK 0xfffffffe 4312 #define A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT 1 4313 static inline uint32_t A5XX_HLSQ_HS_CNTL_INSTRLEN(uint32_t val) 4314 { 4315 return ((val) << A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK; 4316 } 4317 4318 #define REG_A5XX_HLSQ_DS_CNTL 0x0000e794 4319 #define A5XX_HLSQ_DS_CNTL_SSBO_ENABLE 0x00000001 4320 #define A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK 0xfffffffe 4321 #define A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT 1 4322 static inline uint32_t A5XX_HLSQ_DS_CNTL_INSTRLEN(uint32_t val) 4323 { 4324 return ((val) << A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK; 4325 } 4326 4327 #define REG_A5XX_HLSQ_GS_CNTL 0x0000e795 4328 #define A5XX_HLSQ_GS_CNTL_SSBO_ENABLE 0x00000001 4329 #define A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK 0xfffffffe 4330 #define A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT 1 4331 static inline uint32_t A5XX_HLSQ_GS_CNTL_INSTRLEN(uint32_t val) 4332 { 4333 return ((val) << A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK; 4334 } 4335 4336 #define REG_A5XX_HLSQ_CS_CNTL 0x0000e796 4337 #define A5XX_HLSQ_CS_CNTL_SSBO_ENABLE 0x00000001 4338 #define A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK 0xfffffffe 4339 #define A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT 1 4340 static inline uint32_t A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val) 4341 { 4342 return ((val) << A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK; 4343 } 4344 4345 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_X 0x0000e7b9 4346 4347 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000e7ba 4348 4349 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000e7bb 4350 4351 #define REG_A5XX_HLSQ_CS_NDRANGE_0 0x0000e7b0 4352 #define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003 4353 #define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0 4354 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) 4355 { 4356 return ((val) << A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK; 4357 } 4358 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc 4359 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2 4360 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) 4361 { 4362 return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK; 4363 } 4364 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000 4365 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12 4366 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) 4367 { 4368 return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK; 4369 } 4370 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000 4371 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22 4372 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) 4373 { 4374 return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK; 4375 } 4376 4377 #define REG_A5XX_HLSQ_CS_NDRANGE_1 0x0000e7b1 4378 #define A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__MASK 0xffffffff 4379 #define A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__SHIFT 0 4380 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_1_SIZE_X(uint32_t val) 4381 { 4382 return ((val) << A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__SHIFT) & A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__MASK; 4383 } 4384 4385 #define REG_A5XX_HLSQ_CS_NDRANGE_2 0x0000e7b2 4386 4387 #define REG_A5XX_HLSQ_CS_NDRANGE_3 0x0000e7b3 4388 #define A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__MASK 0xffffffff 4389 #define A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__SHIFT 0 4390 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y(uint32_t val) 4391 { 4392 return ((val) << A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__SHIFT) & A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__MASK; 4393 } 4394 4395 #define REG_A5XX_HLSQ_CS_NDRANGE_4 0x0000e7b4 4396 4397 #define REG_A5XX_HLSQ_CS_NDRANGE_5 0x0000e7b5 4398 #define A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__MASK 0xffffffff 4399 #define A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__SHIFT 0 4400 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z(uint32_t val) 4401 { 4402 return ((val) << A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__SHIFT) & A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__MASK; 4403 } 4404 4405 #define REG_A5XX_HLSQ_CS_NDRANGE_6 0x0000e7b6 4406 4407 #define REG_A5XX_HLSQ_CS_CNTL_0 0x0000e7b7 4408 #define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff 4409 #define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0 4410 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val) 4411 { 4412 return ((val) << A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK; 4413 } 4414 #define A5XX_HLSQ_CS_CNTL_0_UNK0__MASK 0x0000ff00 4415 #define A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT 8 4416 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val) 4417 { 4418 return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK0__MASK; 4419 } 4420 #define A5XX_HLSQ_CS_CNTL_0_UNK1__MASK 0x00ff0000 4421 #define A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT 16 4422 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val) 4423 { 4424 return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK1__MASK; 4425 } 4426 #define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000 4427 #define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24 4428 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) 4429 { 4430 return ((val) << A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK; 4431 } 4432 4433 #define REG_A5XX_HLSQ_CS_CNTL_1 0x0000e7b8 4434 4435 #define REG_A5XX_UNKNOWN_E7C0 0x0000e7c0 4436 4437 #define REG_A5XX_HLSQ_VS_CONSTLEN 0x0000e7c3 4438 4439 #define REG_A5XX_HLSQ_VS_INSTRLEN 0x0000e7c4 4440 4441 #define REG_A5XX_UNKNOWN_E7C5 0x0000e7c5 4442 4443 #define REG_A5XX_HLSQ_HS_CONSTLEN 0x0000e7c8 4444 4445 #define REG_A5XX_HLSQ_HS_INSTRLEN 0x0000e7c9 4446 4447 #define REG_A5XX_UNKNOWN_E7CA 0x0000e7ca 4448 4449 #define REG_A5XX_HLSQ_DS_CONSTLEN 0x0000e7cd 4450 4451 #define REG_A5XX_HLSQ_DS_INSTRLEN 0x0000e7ce 4452 4453 #define REG_A5XX_UNKNOWN_E7CF 0x0000e7cf 4454 4455 #define REG_A5XX_HLSQ_GS_CONSTLEN 0x0000e7d2 4456 4457 #define REG_A5XX_HLSQ_GS_INSTRLEN 0x0000e7d3 4458 4459 #define REG_A5XX_UNKNOWN_E7D4 0x0000e7d4 4460 4461 #define REG_A5XX_HLSQ_FS_CONSTLEN 0x0000e7d7 4462 4463 #define REG_A5XX_HLSQ_FS_INSTRLEN 0x0000e7d8 4464 4465 #define REG_A5XX_UNKNOWN_E7D9 0x0000e7d9 4466 4467 #define REG_A5XX_HLSQ_CS_CONSTLEN 0x0000e7dc 4468 4469 #define REG_A5XX_HLSQ_CS_INSTRLEN 0x0000e7dd 4470 4471 #define REG_A5XX_RB_2D_SRC_SOLID_DW0 0x00002101 4472 4473 #define REG_A5XX_RB_2D_SRC_SOLID_DW1 0x00002102 4474 4475 #define REG_A5XX_RB_2D_SRC_SOLID_DW2 0x00002103 4476 4477 #define REG_A5XX_RB_2D_SRC_SOLID_DW3 0x00002104 4478 4479 #define REG_A5XX_RB_2D_SRC_INFO 0x00002107 4480 #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff 4481 #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 4482 static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) 4483 { 4484 return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK; 4485 } 4486 #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00 4487 #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT 10 4488 static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) 4489 { 4490 return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK; 4491 } 4492 4493 #define REG_A5XX_RB_2D_SRC_LO 0x00002108 4494 4495 #define REG_A5XX_RB_2D_SRC_HI 0x00002109 4496 4497 #define REG_A5XX_RB_2D_SRC_SIZE 0x0000210a 4498 #define A5XX_RB_2D_SRC_SIZE_PITCH__MASK 0x0000ffff 4499 #define A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT 0 4500 static inline uint32_t A5XX_RB_2D_SRC_SIZE_PITCH(uint32_t val) 4501 { 4502 return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_PITCH__MASK; 4503 } 4504 #define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK 0xffff0000 4505 #define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT 16 4506 static inline uint32_t A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(uint32_t val) 4507 { 4508 return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK; 4509 } 4510 4511 #define REG_A5XX_RB_2D_DST_INFO 0x00002110 4512 #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff 4513 #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0 4514 static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) 4515 { 4516 return ((val) << A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK; 4517 } 4518 #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00 4519 #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10 4520 static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) 4521 { 4522 return ((val) << A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK; 4523 } 4524 4525 #define REG_A5XX_RB_2D_DST_LO 0x00002111 4526 4527 #define REG_A5XX_RB_2D_DST_HI 0x00002112 4528 4529 #define REG_A5XX_RB_2D_DST_SIZE 0x00002113 4530 #define A5XX_RB_2D_DST_SIZE_PITCH__MASK 0x0000ffff 4531 #define A5XX_RB_2D_DST_SIZE_PITCH__SHIFT 0 4532 static inline uint32_t A5XX_RB_2D_DST_SIZE_PITCH(uint32_t val) 4533 { 4534 return ((val >> 6) << A5XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_PITCH__MASK; 4535 } 4536 #define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK 0xffff0000 4537 #define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT 16 4538 static inline uint32_t A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val) 4539 { 4540 return ((val >> 6) << A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK; 4541 } 4542 4543 #define REG_A5XX_RB_2D_SRC_FLAGS_LO 0x00002140 4544 4545 #define REG_A5XX_RB_2D_SRC_FLAGS_HI 0x00002141 4546 4547 #define REG_A5XX_RB_2D_DST_FLAGS_LO 0x00002143 4548 4549 #define REG_A5XX_RB_2D_DST_FLAGS_HI 0x00002144 4550 4551 #define REG_A5XX_GRAS_2D_SRC_INFO 0x00002181 4552 #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff 4553 #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 4554 static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) 4555 { 4556 return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK; 4557 } 4558 #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00 4559 #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10 4560 static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) 4561 { 4562 return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK; 4563 } 4564 4565 #define REG_A5XX_GRAS_2D_DST_INFO 0x00002182 4566 #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff 4567 #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT 0 4568 static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) 4569 { 4570 return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK; 4571 } 4572 #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00 4573 #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT 10 4574 static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) 4575 { 4576 return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK; 4577 } 4578 4579 #define REG_A5XX_UNKNOWN_2100 0x00002100 4580 4581 #define REG_A5XX_UNKNOWN_2180 0x00002180 4582 4583 #define REG_A5XX_UNKNOWN_2184 0x00002184 4584 4585 #define REG_A5XX_TEX_SAMP_0 0x00000000 4586 #define A5XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 4587 #define A5XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 4588 #define A5XX_TEX_SAMP_0_XY_MAG__SHIFT 1 4589 static inline uint32_t A5XX_TEX_SAMP_0_XY_MAG(enum a5xx_tex_filter val) 4590 { 4591 return ((val) << A5XX_TEX_SAMP_0_XY_MAG__SHIFT) & A5XX_TEX_SAMP_0_XY_MAG__MASK; 4592 } 4593 #define A5XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 4594 #define A5XX_TEX_SAMP_0_XY_MIN__SHIFT 3 4595 static inline uint32_t A5XX_TEX_SAMP_0_XY_MIN(enum a5xx_tex_filter val) 4596 { 4597 return ((val) << A5XX_TEX_SAMP_0_XY_MIN__SHIFT) & A5XX_TEX_SAMP_0_XY_MIN__MASK; 4598 } 4599 #define A5XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 4600 #define A5XX_TEX_SAMP_0_WRAP_S__SHIFT 5 4601 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_S(enum a5xx_tex_clamp val) 4602 { 4603 return ((val) << A5XX_TEX_SAMP_0_WRAP_S__SHIFT) & A5XX_TEX_SAMP_0_WRAP_S__MASK; 4604 } 4605 #define A5XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 4606 #define A5XX_TEX_SAMP_0_WRAP_T__SHIFT 8 4607 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_T(enum a5xx_tex_clamp val) 4608 { 4609 return ((val) << A5XX_TEX_SAMP_0_WRAP_T__SHIFT) & A5XX_TEX_SAMP_0_WRAP_T__MASK; 4610 } 4611 #define A5XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 4612 #define A5XX_TEX_SAMP_0_WRAP_R__SHIFT 11 4613 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_R(enum a5xx_tex_clamp val) 4614 { 4615 return ((val) << A5XX_TEX_SAMP_0_WRAP_R__SHIFT) & A5XX_TEX_SAMP_0_WRAP_R__MASK; 4616 } 4617 #define A5XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 4618 #define A5XX_TEX_SAMP_0_ANISO__SHIFT 14 4619 static inline uint32_t A5XX_TEX_SAMP_0_ANISO(enum a5xx_tex_aniso val) 4620 { 4621 return ((val) << A5XX_TEX_SAMP_0_ANISO__SHIFT) & A5XX_TEX_SAMP_0_ANISO__MASK; 4622 } 4623 #define A5XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000 4624 #define A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19 4625 static inline uint32_t A5XX_TEX_SAMP_0_LOD_BIAS(float val) 4626 { 4627 return ((((int32_t)(val * 256.0))) << A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A5XX_TEX_SAMP_0_LOD_BIAS__MASK; 4628 } 4629 4630 #define REG_A5XX_TEX_SAMP_1 0x00000001 4631 #define A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e 4632 #define A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 4633 static inline uint32_t A5XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) 4634 { 4635 return ((val) << A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK; 4636 } 4637 #define A5XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010 4638 #define A5XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 4639 #define A5XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 4640 #define A5XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 4641 #define A5XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 4642 static inline uint32_t A5XX_TEX_SAMP_1_MAX_LOD(float val) 4643 { 4644 return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A5XX_TEX_SAMP_1_MAX_LOD__MASK; 4645 } 4646 #define A5XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 4647 #define A5XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 4648 static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val) 4649 { 4650 return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A5XX_TEX_SAMP_1_MIN_LOD__MASK; 4651 } 4652 4653 #define REG_A5XX_TEX_SAMP_2 0x00000002 4654 #define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xfffffff0 4655 #define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 4 4656 static inline uint32_t A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val) 4657 { 4658 return ((val) << A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK; 4659 } 4660 4661 #define REG_A5XX_TEX_SAMP_3 0x00000003 4662 4663 #define REG_A5XX_TEX_CONST_0 0x00000000 4664 #define A5XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003 4665 #define A5XX_TEX_CONST_0_TILE_MODE__SHIFT 0 4666 static inline uint32_t A5XX_TEX_CONST_0_TILE_MODE(enum a5xx_tile_mode val) 4667 { 4668 return ((val) << A5XX_TEX_CONST_0_TILE_MODE__SHIFT) & A5XX_TEX_CONST_0_TILE_MODE__MASK; 4669 } 4670 #define A5XX_TEX_CONST_0_SRGB 0x00000004 4671 #define A5XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 4672 #define A5XX_TEX_CONST_0_SWIZ_X__SHIFT 4 4673 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_X(enum a5xx_tex_swiz val) 4674 { 4675 return ((val) << A5XX_TEX_CONST_0_SWIZ_X__SHIFT) & A5XX_TEX_CONST_0_SWIZ_X__MASK; 4676 } 4677 #define A5XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 4678 #define A5XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 4679 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Y(enum a5xx_tex_swiz val) 4680 { 4681 return ((val) << A5XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Y__MASK; 4682 } 4683 #define A5XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 4684 #define A5XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 4685 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Z(enum a5xx_tex_swiz val) 4686 { 4687 return ((val) << A5XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Z__MASK; 4688 } 4689 #define A5XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 4690 #define A5XX_TEX_CONST_0_SWIZ_W__SHIFT 13 4691 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_W(enum a5xx_tex_swiz val) 4692 { 4693 return ((val) << A5XX_TEX_CONST_0_SWIZ_W__SHIFT) & A5XX_TEX_CONST_0_SWIZ_W__MASK; 4694 } 4695 #define A5XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 4696 #define A5XX_TEX_CONST_0_MIPLVLS__SHIFT 16 4697 static inline uint32_t A5XX_TEX_CONST_0_MIPLVLS(uint32_t val) 4698 { 4699 return ((val) << A5XX_TEX_CONST_0_MIPLVLS__SHIFT) & A5XX_TEX_CONST_0_MIPLVLS__MASK; 4700 } 4701 #define A5XX_TEX_CONST_0_FMT__MASK 0x3fc00000 4702 #define A5XX_TEX_CONST_0_FMT__SHIFT 22 4703 static inline uint32_t A5XX_TEX_CONST_0_FMT(enum a5xx_tex_fmt val) 4704 { 4705 return ((val) << A5XX_TEX_CONST_0_FMT__SHIFT) & A5XX_TEX_CONST_0_FMT__MASK; 4706 } 4707 #define A5XX_TEX_CONST_0_SWAP__MASK 0xc0000000 4708 #define A5XX_TEX_CONST_0_SWAP__SHIFT 30 4709 static inline uint32_t A5XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val) 4710 { 4711 return ((val) << A5XX_TEX_CONST_0_SWAP__SHIFT) & A5XX_TEX_CONST_0_SWAP__MASK; 4712 } 4713 4714 #define REG_A5XX_TEX_CONST_1 0x00000001 4715 #define A5XX_TEX_CONST_1_WIDTH__MASK 0x00007fff 4716 #define A5XX_TEX_CONST_1_WIDTH__SHIFT 0 4717 static inline uint32_t A5XX_TEX_CONST_1_WIDTH(uint32_t val) 4718 { 4719 return ((val) << A5XX_TEX_CONST_1_WIDTH__SHIFT) & A5XX_TEX_CONST_1_WIDTH__MASK; 4720 } 4721 #define A5XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000 4722 #define A5XX_TEX_CONST_1_HEIGHT__SHIFT 15 4723 static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val) 4724 { 4725 return ((val) << A5XX_TEX_CONST_1_HEIGHT__SHIFT) & A5XX_TEX_CONST_1_HEIGHT__MASK; 4726 } 4727 4728 #define REG_A5XX_TEX_CONST_2 0x00000002 4729 #define A5XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f 4730 #define A5XX_TEX_CONST_2_FETCHSIZE__SHIFT 0 4731 static inline uint32_t A5XX_TEX_CONST_2_FETCHSIZE(enum a5xx_tex_fetchsize val) 4732 { 4733 return ((val) << A5XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A5XX_TEX_CONST_2_FETCHSIZE__MASK; 4734 } 4735 #define A5XX_TEX_CONST_2_PITCH__MASK 0x1fffff80 4736 #define A5XX_TEX_CONST_2_PITCH__SHIFT 7 4737 static inline uint32_t A5XX_TEX_CONST_2_PITCH(uint32_t val) 4738 { 4739 return ((val) << A5XX_TEX_CONST_2_PITCH__SHIFT) & A5XX_TEX_CONST_2_PITCH__MASK; 4740 } 4741 #define A5XX_TEX_CONST_2_TYPE__MASK 0x60000000 4742 #define A5XX_TEX_CONST_2_TYPE__SHIFT 29 4743 static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val) 4744 { 4745 return ((val) << A5XX_TEX_CONST_2_TYPE__SHIFT) & A5XX_TEX_CONST_2_TYPE__MASK; 4746 } 4747 4748 #define REG_A5XX_TEX_CONST_3 0x00000003 4749 #define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff 4750 #define A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0 4751 static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) 4752 { 4753 return ((val >> 12) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK; 4754 } 4755 #define A5XX_TEX_CONST_3_FLAG 0x10000000 4756 4757 #define REG_A5XX_TEX_CONST_4 0x00000004 4758 #define A5XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0 4759 #define A5XX_TEX_CONST_4_BASE_LO__SHIFT 5 4760 static inline uint32_t A5XX_TEX_CONST_4_BASE_LO(uint32_t val) 4761 { 4762 return ((val >> 5) << A5XX_TEX_CONST_4_BASE_LO__SHIFT) & A5XX_TEX_CONST_4_BASE_LO__MASK; 4763 } 4764 4765 #define REG_A5XX_TEX_CONST_5 0x00000005 4766 #define A5XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff 4767 #define A5XX_TEX_CONST_5_BASE_HI__SHIFT 0 4768 static inline uint32_t A5XX_TEX_CONST_5_BASE_HI(uint32_t val) 4769 { 4770 return ((val) << A5XX_TEX_CONST_5_BASE_HI__SHIFT) & A5XX_TEX_CONST_5_BASE_HI__MASK; 4771 } 4772 #define A5XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000 4773 #define A5XX_TEX_CONST_5_DEPTH__SHIFT 17 4774 static inline uint32_t A5XX_TEX_CONST_5_DEPTH(uint32_t val) 4775 { 4776 return ((val) << A5XX_TEX_CONST_5_DEPTH__SHIFT) & A5XX_TEX_CONST_5_DEPTH__MASK; 4777 } 4778 4779 #define REG_A5XX_TEX_CONST_6 0x00000006 4780 4781 #define REG_A5XX_TEX_CONST_7 0x00000007 4782 4783 #define REG_A5XX_TEX_CONST_8 0x00000008 4784 4785 #define REG_A5XX_TEX_CONST_9 0x00000009 4786 4787 #define REG_A5XX_TEX_CONST_10 0x0000000a 4788 4789 #define REG_A5XX_TEX_CONST_11 0x0000000b 4790 4791 4792 #endif /* A5XX_XML */ 4793