1a26ae754SRob Clark #ifndef A5XX_XML 2a26ae754SRob Clark #define A5XX_XML 3a26ae754SRob Clark 4a26ae754SRob Clark /* Autogenerated file, DO NOT EDIT manually! 5a26ae754SRob Clark 6a26ae754SRob Clark This file was generated by the rules-ng-ng headergen tool in this git repository: 7a26ae754SRob Clark http://github.com/freedreno/envytools/ 8a26ae754SRob Clark git clone https://github.com/freedreno/envytools.git 9a26ae754SRob Clark 10a26ae754SRob Clark The rules-ng-ng source files this header was generated from are: 11*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44) 12*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) 13*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44) 14*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44) 15*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57) 16*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44) 17*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44) 18*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02) 19*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19) 20*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08) 21*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44) 22*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36) 23*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13) 24a26ae754SRob Clark 25*cc4c26d4SRob Clark Copyright (C) 2013-2021 by the following authors: 26a26ae754SRob Clark - Rob Clark <robdclark@gmail.com> (robclark) 27a26ae754SRob Clark - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 28a26ae754SRob Clark 29a26ae754SRob Clark Permission is hereby granted, free of charge, to any person obtaining 30a26ae754SRob Clark a copy of this software and associated documentation files (the 31a26ae754SRob Clark "Software"), to deal in the Software without restriction, including 32a26ae754SRob Clark without limitation the rights to use, copy, modify, merge, publish, 33a26ae754SRob Clark distribute, sublicense, and/or sell copies of the Software, and to 34a26ae754SRob Clark permit persons to whom the Software is furnished to do so, subject to 35a26ae754SRob Clark the following conditions: 36a26ae754SRob Clark 37a26ae754SRob Clark The above copyright notice and this permission notice (including the 38a26ae754SRob Clark next paragraph) shall be included in all copies or substantial 39a26ae754SRob Clark portions of the Software. 40a26ae754SRob Clark 41a26ae754SRob Clark THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 42a26ae754SRob Clark EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 43a26ae754SRob Clark MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 44a26ae754SRob Clark IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 45a26ae754SRob Clark LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 46a26ae754SRob Clark OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 47a26ae754SRob Clark WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 48a26ae754SRob Clark */ 49a26ae754SRob Clark 50a26ae754SRob Clark 51a26ae754SRob Clark enum a5xx_color_fmt { 5252260ae4SRob Clark RB5_A8_UNORM = 2, 53a26ae754SRob Clark RB5_R8_UNORM = 3, 5452260ae4SRob Clark RB5_R8_SNORM = 4, 5552260ae4SRob Clark RB5_R8_UINT = 5, 5652260ae4SRob Clark RB5_R8_SINT = 6, 57a26ae754SRob Clark RB5_R4G4B4A4_UNORM = 8, 58a26ae754SRob Clark RB5_R5G5B5A1_UNORM = 10, 59a26ae754SRob Clark RB5_R5G6B5_UNORM = 14, 6052260ae4SRob Clark RB5_R8G8_UNORM = 15, 6152260ae4SRob Clark RB5_R8G8_SNORM = 16, 6252260ae4SRob Clark RB5_R8G8_UINT = 17, 6352260ae4SRob Clark RB5_R8G8_SINT = 18, 6452260ae4SRob Clark RB5_R16_UNORM = 21, 6552260ae4SRob Clark RB5_R16_SNORM = 22, 66a26ae754SRob Clark RB5_R16_FLOAT = 23, 6752260ae4SRob Clark RB5_R16_UINT = 24, 6852260ae4SRob Clark RB5_R16_SINT = 25, 69a26ae754SRob Clark RB5_R8G8B8A8_UNORM = 48, 70a26ae754SRob Clark RB5_R8G8B8_UNORM = 49, 7152260ae4SRob Clark RB5_R8G8B8A8_SNORM = 50, 72a26ae754SRob Clark RB5_R8G8B8A8_UINT = 51, 7352260ae4SRob Clark RB5_R8G8B8A8_SINT = 52, 7452260ae4SRob Clark RB5_R10G10B10A2_UNORM = 55, 75a26ae754SRob Clark RB5_R10G10B10A2_UINT = 58, 7652260ae4SRob Clark RB5_R11G11B10_FLOAT = 66, 7752260ae4SRob Clark RB5_R16G16_UNORM = 67, 7852260ae4SRob Clark RB5_R16G16_SNORM = 68, 79a26ae754SRob Clark RB5_R16G16_FLOAT = 69, 8052260ae4SRob Clark RB5_R16G16_UINT = 70, 8152260ae4SRob Clark RB5_R16G16_SINT = 71, 82a26ae754SRob Clark RB5_R32_FLOAT = 74, 8352260ae4SRob Clark RB5_R32_UINT = 75, 8452260ae4SRob Clark RB5_R32_SINT = 76, 8552260ae4SRob Clark RB5_R16G16B16A16_UNORM = 96, 8652260ae4SRob Clark RB5_R16G16B16A16_SNORM = 97, 87a26ae754SRob Clark RB5_R16G16B16A16_FLOAT = 98, 8852260ae4SRob Clark RB5_R16G16B16A16_UINT = 99, 8952260ae4SRob Clark RB5_R16G16B16A16_SINT = 100, 90a26ae754SRob Clark RB5_R32G32_FLOAT = 103, 9152260ae4SRob Clark RB5_R32G32_UINT = 104, 9252260ae4SRob Clark RB5_R32G32_SINT = 105, 93a26ae754SRob Clark RB5_R32G32B32A32_FLOAT = 130, 9452260ae4SRob Clark RB5_R32G32B32A32_UINT = 131, 9552260ae4SRob Clark RB5_R32G32B32A32_SINT = 132, 96c28c82e9SRob Clark RB5_NONE = 255, 97a26ae754SRob Clark }; 98a26ae754SRob Clark 99a26ae754SRob Clark enum a5xx_tile_mode { 100a26ae754SRob Clark TILE5_LINEAR = 0, 101a26ae754SRob Clark TILE5_2 = 2, 102a26ae754SRob Clark TILE5_3 = 3, 103a26ae754SRob Clark }; 104a26ae754SRob Clark 105a26ae754SRob Clark enum a5xx_vtx_fmt { 106a26ae754SRob Clark VFMT5_8_UNORM = 3, 107a26ae754SRob Clark VFMT5_8_SNORM = 4, 108a26ae754SRob Clark VFMT5_8_UINT = 5, 109a26ae754SRob Clark VFMT5_8_SINT = 6, 110a26ae754SRob Clark VFMT5_8_8_UNORM = 15, 111a26ae754SRob Clark VFMT5_8_8_SNORM = 16, 112a26ae754SRob Clark VFMT5_8_8_UINT = 17, 113a26ae754SRob Clark VFMT5_8_8_SINT = 18, 114a26ae754SRob Clark VFMT5_16_UNORM = 21, 115a26ae754SRob Clark VFMT5_16_SNORM = 22, 116a26ae754SRob Clark VFMT5_16_FLOAT = 23, 117a26ae754SRob Clark VFMT5_16_UINT = 24, 118a26ae754SRob Clark VFMT5_16_SINT = 25, 119a26ae754SRob Clark VFMT5_8_8_8_UNORM = 33, 120a26ae754SRob Clark VFMT5_8_8_8_SNORM = 34, 121a26ae754SRob Clark VFMT5_8_8_8_UINT = 35, 122a26ae754SRob Clark VFMT5_8_8_8_SINT = 36, 123a26ae754SRob Clark VFMT5_8_8_8_8_UNORM = 48, 124a26ae754SRob Clark VFMT5_8_8_8_8_SNORM = 50, 125a26ae754SRob Clark VFMT5_8_8_8_8_UINT = 51, 126a26ae754SRob Clark VFMT5_8_8_8_8_SINT = 52, 1272d756322SRob Clark VFMT5_10_10_10_2_UNORM = 54, 1282d756322SRob Clark VFMT5_10_10_10_2_SNORM = 57, 1292d756322SRob Clark VFMT5_10_10_10_2_UINT = 58, 1302d756322SRob Clark VFMT5_10_10_10_2_SINT = 59, 1312d756322SRob Clark VFMT5_11_11_10_FLOAT = 66, 132a26ae754SRob Clark VFMT5_16_16_UNORM = 67, 133a26ae754SRob Clark VFMT5_16_16_SNORM = 68, 134a26ae754SRob Clark VFMT5_16_16_FLOAT = 69, 135a26ae754SRob Clark VFMT5_16_16_UINT = 70, 136a26ae754SRob Clark VFMT5_16_16_SINT = 71, 137a26ae754SRob Clark VFMT5_32_UNORM = 72, 138a26ae754SRob Clark VFMT5_32_SNORM = 73, 139a26ae754SRob Clark VFMT5_32_FLOAT = 74, 140a26ae754SRob Clark VFMT5_32_UINT = 75, 141a26ae754SRob Clark VFMT5_32_SINT = 76, 142a26ae754SRob Clark VFMT5_32_FIXED = 77, 143a26ae754SRob Clark VFMT5_16_16_16_UNORM = 88, 144a26ae754SRob Clark VFMT5_16_16_16_SNORM = 89, 145a26ae754SRob Clark VFMT5_16_16_16_FLOAT = 90, 146a26ae754SRob Clark VFMT5_16_16_16_UINT = 91, 147a26ae754SRob Clark VFMT5_16_16_16_SINT = 92, 148a26ae754SRob Clark VFMT5_16_16_16_16_UNORM = 96, 149a26ae754SRob Clark VFMT5_16_16_16_16_SNORM = 97, 150a26ae754SRob Clark VFMT5_16_16_16_16_FLOAT = 98, 151a26ae754SRob Clark VFMT5_16_16_16_16_UINT = 99, 152a26ae754SRob Clark VFMT5_16_16_16_16_SINT = 100, 153a26ae754SRob Clark VFMT5_32_32_UNORM = 101, 154a26ae754SRob Clark VFMT5_32_32_SNORM = 102, 155a26ae754SRob Clark VFMT5_32_32_FLOAT = 103, 156a26ae754SRob Clark VFMT5_32_32_UINT = 104, 157a26ae754SRob Clark VFMT5_32_32_SINT = 105, 158a26ae754SRob Clark VFMT5_32_32_FIXED = 106, 159a26ae754SRob Clark VFMT5_32_32_32_UNORM = 112, 160a26ae754SRob Clark VFMT5_32_32_32_SNORM = 113, 161a26ae754SRob Clark VFMT5_32_32_32_UINT = 114, 162a26ae754SRob Clark VFMT5_32_32_32_SINT = 115, 163a26ae754SRob Clark VFMT5_32_32_32_FLOAT = 116, 164a26ae754SRob Clark VFMT5_32_32_32_FIXED = 117, 165a26ae754SRob Clark VFMT5_32_32_32_32_UNORM = 128, 166a26ae754SRob Clark VFMT5_32_32_32_32_SNORM = 129, 167a26ae754SRob Clark VFMT5_32_32_32_32_FLOAT = 130, 168a26ae754SRob Clark VFMT5_32_32_32_32_UINT = 131, 169a26ae754SRob Clark VFMT5_32_32_32_32_SINT = 132, 170a26ae754SRob Clark VFMT5_32_32_32_32_FIXED = 133, 171c28c82e9SRob Clark VFMT5_NONE = 255, 172a26ae754SRob Clark }; 173a26ae754SRob Clark 174a26ae754SRob Clark enum a5xx_tex_fmt { 175a26ae754SRob Clark TFMT5_A8_UNORM = 2, 176a26ae754SRob Clark TFMT5_8_UNORM = 3, 17752260ae4SRob Clark TFMT5_8_SNORM = 4, 17852260ae4SRob Clark TFMT5_8_UINT = 5, 17952260ae4SRob Clark TFMT5_8_SINT = 6, 180a26ae754SRob Clark TFMT5_4_4_4_4_UNORM = 8, 181a26ae754SRob Clark TFMT5_5_5_5_1_UNORM = 10, 182a26ae754SRob Clark TFMT5_5_6_5_UNORM = 14, 183a26ae754SRob Clark TFMT5_8_8_UNORM = 15, 184a26ae754SRob Clark TFMT5_8_8_SNORM = 16, 18552260ae4SRob Clark TFMT5_8_8_UINT = 17, 18652260ae4SRob Clark TFMT5_8_8_SINT = 18, 187a26ae754SRob Clark TFMT5_L8_A8_UNORM = 19, 18852260ae4SRob Clark TFMT5_16_UNORM = 21, 18952260ae4SRob Clark TFMT5_16_SNORM = 22, 190a26ae754SRob Clark TFMT5_16_FLOAT = 23, 19152260ae4SRob Clark TFMT5_16_UINT = 24, 19252260ae4SRob Clark TFMT5_16_SINT = 25, 193a26ae754SRob Clark TFMT5_8_8_8_8_UNORM = 48, 194a26ae754SRob Clark TFMT5_8_8_8_UNORM = 49, 19552260ae4SRob Clark TFMT5_8_8_8_8_SNORM = 50, 19652260ae4SRob Clark TFMT5_8_8_8_8_UINT = 51, 19752260ae4SRob Clark TFMT5_8_8_8_8_SINT = 52, 198a26ae754SRob Clark TFMT5_9_9_9_E5_FLOAT = 53, 199a26ae754SRob Clark TFMT5_10_10_10_2_UNORM = 54, 20052260ae4SRob Clark TFMT5_10_10_10_2_UINT = 58, 201a26ae754SRob Clark TFMT5_11_11_10_FLOAT = 66, 20252260ae4SRob Clark TFMT5_16_16_UNORM = 67, 20352260ae4SRob Clark TFMT5_16_16_SNORM = 68, 204a26ae754SRob Clark TFMT5_16_16_FLOAT = 69, 20552260ae4SRob Clark TFMT5_16_16_UINT = 70, 20652260ae4SRob Clark TFMT5_16_16_SINT = 71, 207a26ae754SRob Clark TFMT5_32_FLOAT = 74, 20852260ae4SRob Clark TFMT5_32_UINT = 75, 20952260ae4SRob Clark TFMT5_32_SINT = 76, 21052260ae4SRob Clark TFMT5_16_16_16_16_UNORM = 96, 21152260ae4SRob Clark TFMT5_16_16_16_16_SNORM = 97, 212a26ae754SRob Clark TFMT5_16_16_16_16_FLOAT = 98, 21352260ae4SRob Clark TFMT5_16_16_16_16_UINT = 99, 21452260ae4SRob Clark TFMT5_16_16_16_16_SINT = 100, 215a26ae754SRob Clark TFMT5_32_32_FLOAT = 103, 21652260ae4SRob Clark TFMT5_32_32_UINT = 104, 21752260ae4SRob Clark TFMT5_32_32_SINT = 105, 2182d756322SRob Clark TFMT5_32_32_32_UINT = 114, 2192d756322SRob Clark TFMT5_32_32_32_SINT = 115, 2202d756322SRob Clark TFMT5_32_32_32_FLOAT = 116, 221a26ae754SRob Clark TFMT5_32_32_32_32_FLOAT = 130, 22252260ae4SRob Clark TFMT5_32_32_32_32_UINT = 131, 22352260ae4SRob Clark TFMT5_32_32_32_32_SINT = 132, 224a26ae754SRob Clark TFMT5_X8Z24_UNORM = 160, 2252d756322SRob Clark TFMT5_ETC2_RG11_UNORM = 171, 2262d756322SRob Clark TFMT5_ETC2_RG11_SNORM = 172, 2272d756322SRob Clark TFMT5_ETC2_R11_UNORM = 173, 2282d756322SRob Clark TFMT5_ETC2_R11_SNORM = 174, 2292d756322SRob Clark TFMT5_ETC1 = 175, 2302d756322SRob Clark TFMT5_ETC2_RGB8 = 176, 2312d756322SRob Clark TFMT5_ETC2_RGBA8 = 177, 2322d756322SRob Clark TFMT5_ETC2_RGB8A1 = 178, 2332d756322SRob Clark TFMT5_DXT1 = 179, 2342d756322SRob Clark TFMT5_DXT3 = 180, 2352d756322SRob Clark TFMT5_DXT5 = 181, 23652260ae4SRob Clark TFMT5_RGTC1_UNORM = 183, 23752260ae4SRob Clark TFMT5_RGTC1_SNORM = 184, 23852260ae4SRob Clark TFMT5_RGTC2_UNORM = 187, 23952260ae4SRob Clark TFMT5_RGTC2_SNORM = 188, 2402d756322SRob Clark TFMT5_BPTC_UFLOAT = 190, 2412d756322SRob Clark TFMT5_BPTC_FLOAT = 191, 2422d756322SRob Clark TFMT5_BPTC = 192, 2432d756322SRob Clark TFMT5_ASTC_4x4 = 193, 2442d756322SRob Clark TFMT5_ASTC_5x4 = 194, 2452d756322SRob Clark TFMT5_ASTC_5x5 = 195, 2462d756322SRob Clark TFMT5_ASTC_6x5 = 196, 2472d756322SRob Clark TFMT5_ASTC_6x6 = 197, 2482d756322SRob Clark TFMT5_ASTC_8x5 = 198, 2492d756322SRob Clark TFMT5_ASTC_8x6 = 199, 2502d756322SRob Clark TFMT5_ASTC_8x8 = 200, 2512d756322SRob Clark TFMT5_ASTC_10x5 = 201, 2522d756322SRob Clark TFMT5_ASTC_10x6 = 202, 2532d756322SRob Clark TFMT5_ASTC_10x8 = 203, 2542d756322SRob Clark TFMT5_ASTC_10x10 = 204, 2552d756322SRob Clark TFMT5_ASTC_12x10 = 205, 2562d756322SRob Clark TFMT5_ASTC_12x12 = 206, 257c28c82e9SRob Clark TFMT5_NONE = 255, 258a26ae754SRob Clark }; 259a26ae754SRob Clark 260a26ae754SRob Clark enum a5xx_depth_format { 261a26ae754SRob Clark DEPTH5_NONE = 0, 262a26ae754SRob Clark DEPTH5_16 = 1, 263a26ae754SRob Clark DEPTH5_24_8 = 2, 264a26ae754SRob Clark DEPTH5_32 = 4, 265a26ae754SRob Clark }; 266a26ae754SRob Clark 267a26ae754SRob Clark enum a5xx_blit_buf { 268a26ae754SRob Clark BLIT_MRT0 = 0, 269a26ae754SRob Clark BLIT_MRT1 = 1, 270a26ae754SRob Clark BLIT_MRT2 = 2, 271a26ae754SRob Clark BLIT_MRT3 = 3, 272a26ae754SRob Clark BLIT_MRT4 = 4, 273a26ae754SRob Clark BLIT_MRT5 = 5, 274a26ae754SRob Clark BLIT_MRT6 = 6, 275a26ae754SRob Clark BLIT_MRT7 = 7, 276a26ae754SRob Clark BLIT_ZS = 8, 2772d756322SRob Clark BLIT_S = 9, 278a26ae754SRob Clark }; 279a26ae754SRob Clark 28052260ae4SRob Clark enum a5xx_cp_perfcounter_select { 28152260ae4SRob Clark PERF_CP_ALWAYS_COUNT = 0, 28252260ae4SRob Clark PERF_CP_BUSY_GFX_CORE_IDLE = 1, 28352260ae4SRob Clark PERF_CP_BUSY_CYCLES = 2, 28452260ae4SRob Clark PERF_CP_PFP_IDLE = 3, 28552260ae4SRob Clark PERF_CP_PFP_BUSY_WORKING = 4, 28652260ae4SRob Clark PERF_CP_PFP_STALL_CYCLES_ANY = 5, 28752260ae4SRob Clark PERF_CP_PFP_STARVE_CYCLES_ANY = 6, 28852260ae4SRob Clark PERF_CP_PFP_ICACHE_MISS = 7, 28952260ae4SRob Clark PERF_CP_PFP_ICACHE_HIT = 8, 29052260ae4SRob Clark PERF_CP_PFP_MATCH_PM4_PKT_PROFILE = 9, 29152260ae4SRob Clark PERF_CP_ME_BUSY_WORKING = 10, 29252260ae4SRob Clark PERF_CP_ME_IDLE = 11, 29352260ae4SRob Clark PERF_CP_ME_STARVE_CYCLES_ANY = 12, 29452260ae4SRob Clark PERF_CP_ME_FIFO_EMPTY_PFP_IDLE = 13, 29552260ae4SRob Clark PERF_CP_ME_FIFO_EMPTY_PFP_BUSY = 14, 29652260ae4SRob Clark PERF_CP_ME_FIFO_FULL_ME_BUSY = 15, 29752260ae4SRob Clark PERF_CP_ME_FIFO_FULL_ME_NON_WORKING = 16, 29852260ae4SRob Clark PERF_CP_ME_STALL_CYCLES_ANY = 17, 29952260ae4SRob Clark PERF_CP_ME_ICACHE_MISS = 18, 30052260ae4SRob Clark PERF_CP_ME_ICACHE_HIT = 19, 30152260ae4SRob Clark PERF_CP_NUM_PREEMPTIONS = 20, 30252260ae4SRob Clark PERF_CP_PREEMPTION_REACTION_DELAY = 21, 30352260ae4SRob Clark PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 22, 30452260ae4SRob Clark PERF_CP_PREEMPTION_SWITCH_IN_TIME = 23, 30552260ae4SRob Clark PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 24, 30652260ae4SRob Clark PERF_CP_PREDICATED_DRAWS_KILLED = 25, 30752260ae4SRob Clark PERF_CP_MODE_SWITCH = 26, 30852260ae4SRob Clark PERF_CP_ZPASS_DONE = 27, 30952260ae4SRob Clark PERF_CP_CONTEXT_DONE = 28, 31052260ae4SRob Clark PERF_CP_CACHE_FLUSH = 29, 31152260ae4SRob Clark PERF_CP_LONG_PREEMPTIONS = 30, 31252260ae4SRob Clark }; 31352260ae4SRob Clark 31452260ae4SRob Clark enum a5xx_rbbm_perfcounter_select { 31552260ae4SRob Clark PERF_RBBM_ALWAYS_COUNT = 0, 31652260ae4SRob Clark PERF_RBBM_ALWAYS_ON = 1, 31752260ae4SRob Clark PERF_RBBM_TSE_BUSY = 2, 31852260ae4SRob Clark PERF_RBBM_RAS_BUSY = 3, 31952260ae4SRob Clark PERF_RBBM_PC_DCALL_BUSY = 4, 32052260ae4SRob Clark PERF_RBBM_PC_VSD_BUSY = 5, 32152260ae4SRob Clark PERF_RBBM_STATUS_MASKED = 6, 32252260ae4SRob Clark PERF_RBBM_COM_BUSY = 7, 32352260ae4SRob Clark PERF_RBBM_DCOM_BUSY = 8, 32452260ae4SRob Clark PERF_RBBM_VBIF_BUSY = 9, 32552260ae4SRob Clark PERF_RBBM_VSC_BUSY = 10, 32652260ae4SRob Clark PERF_RBBM_TESS_BUSY = 11, 32752260ae4SRob Clark PERF_RBBM_UCHE_BUSY = 12, 32852260ae4SRob Clark PERF_RBBM_HLSQ_BUSY = 13, 32952260ae4SRob Clark }; 33052260ae4SRob Clark 33152260ae4SRob Clark enum a5xx_pc_perfcounter_select { 33252260ae4SRob Clark PERF_PC_BUSY_CYCLES = 0, 33352260ae4SRob Clark PERF_PC_WORKING_CYCLES = 1, 33452260ae4SRob Clark PERF_PC_STALL_CYCLES_VFD = 2, 33552260ae4SRob Clark PERF_PC_STALL_CYCLES_TSE = 3, 33652260ae4SRob Clark PERF_PC_STALL_CYCLES_VPC = 4, 33752260ae4SRob Clark PERF_PC_STALL_CYCLES_UCHE = 5, 33852260ae4SRob Clark PERF_PC_STALL_CYCLES_TESS = 6, 33952260ae4SRob Clark PERF_PC_STALL_CYCLES_TSE_ONLY = 7, 34052260ae4SRob Clark PERF_PC_STALL_CYCLES_VPC_ONLY = 8, 34152260ae4SRob Clark PERF_PC_PASS1_TF_STALL_CYCLES = 9, 34252260ae4SRob Clark PERF_PC_STARVE_CYCLES_FOR_INDEX = 10, 34352260ae4SRob Clark PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11, 34452260ae4SRob Clark PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12, 34552260ae4SRob Clark PERF_PC_STARVE_CYCLES_FOR_POSITION = 13, 34652260ae4SRob Clark PERF_PC_STARVE_CYCLES_DI = 14, 34752260ae4SRob Clark PERF_PC_VIS_STREAMS_LOADED = 15, 34852260ae4SRob Clark PERF_PC_INSTANCES = 16, 34952260ae4SRob Clark PERF_PC_VPC_PRIMITIVES = 17, 35052260ae4SRob Clark PERF_PC_DEAD_PRIM = 18, 35152260ae4SRob Clark PERF_PC_LIVE_PRIM = 19, 35252260ae4SRob Clark PERF_PC_VERTEX_HITS = 20, 35352260ae4SRob Clark PERF_PC_IA_VERTICES = 21, 35452260ae4SRob Clark PERF_PC_IA_PRIMITIVES = 22, 35552260ae4SRob Clark PERF_PC_GS_PRIMITIVES = 23, 35652260ae4SRob Clark PERF_PC_HS_INVOCATIONS = 24, 35752260ae4SRob Clark PERF_PC_DS_INVOCATIONS = 25, 35852260ae4SRob Clark PERF_PC_VS_INVOCATIONS = 26, 35952260ae4SRob Clark PERF_PC_GS_INVOCATIONS = 27, 36052260ae4SRob Clark PERF_PC_DS_PRIMITIVES = 28, 36152260ae4SRob Clark PERF_PC_VPC_POS_DATA_TRANSACTION = 29, 36252260ae4SRob Clark PERF_PC_3D_DRAWCALLS = 30, 36352260ae4SRob Clark PERF_PC_2D_DRAWCALLS = 31, 36452260ae4SRob Clark PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32, 36552260ae4SRob Clark PERF_TESS_BUSY_CYCLES = 33, 36652260ae4SRob Clark PERF_TESS_WORKING_CYCLES = 34, 36752260ae4SRob Clark PERF_TESS_STALL_CYCLES_PC = 35, 36852260ae4SRob Clark PERF_TESS_STARVE_CYCLES_PC = 36, 36952260ae4SRob Clark }; 37052260ae4SRob Clark 37152260ae4SRob Clark enum a5xx_vfd_perfcounter_select { 37252260ae4SRob Clark PERF_VFD_BUSY_CYCLES = 0, 37352260ae4SRob Clark PERF_VFD_STALL_CYCLES_UCHE = 1, 37452260ae4SRob Clark PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2, 37552260ae4SRob Clark PERF_VFD_STALL_CYCLES_MISS_VB = 3, 37652260ae4SRob Clark PERF_VFD_STALL_CYCLES_MISS_Q = 4, 37752260ae4SRob Clark PERF_VFD_STALL_CYCLES_SP_INFO = 5, 37852260ae4SRob Clark PERF_VFD_STALL_CYCLES_SP_ATTR = 6, 37952260ae4SRob Clark PERF_VFD_STALL_CYCLES_VFDP_VB = 7, 38052260ae4SRob Clark PERF_VFD_STALL_CYCLES_VFDP_Q = 8, 38152260ae4SRob Clark PERF_VFD_DECODER_PACKER_STALL = 9, 38252260ae4SRob Clark PERF_VFD_STARVE_CYCLES_UCHE = 10, 38352260ae4SRob Clark PERF_VFD_RBUFFER_FULL = 11, 38452260ae4SRob Clark PERF_VFD_ATTR_INFO_FIFO_FULL = 12, 38552260ae4SRob Clark PERF_VFD_DECODED_ATTRIBUTE_BYTES = 13, 38652260ae4SRob Clark PERF_VFD_NUM_ATTRIBUTES = 14, 38752260ae4SRob Clark PERF_VFD_INSTRUCTIONS = 15, 38852260ae4SRob Clark PERF_VFD_UPPER_SHADER_FIBERS = 16, 38952260ae4SRob Clark PERF_VFD_LOWER_SHADER_FIBERS = 17, 39052260ae4SRob Clark PERF_VFD_MODE_0_FIBERS = 18, 39152260ae4SRob Clark PERF_VFD_MODE_1_FIBERS = 19, 39252260ae4SRob Clark PERF_VFD_MODE_2_FIBERS = 20, 39352260ae4SRob Clark PERF_VFD_MODE_3_FIBERS = 21, 39452260ae4SRob Clark PERF_VFD_MODE_4_FIBERS = 22, 39552260ae4SRob Clark PERF_VFD_TOTAL_VERTICES = 23, 39652260ae4SRob Clark PERF_VFD_NUM_ATTR_MISS = 24, 39752260ae4SRob Clark PERF_VFD_1_BURST_REQ = 25, 39852260ae4SRob Clark PERF_VFDP_STALL_CYCLES_VFD = 26, 39952260ae4SRob Clark PERF_VFDP_STALL_CYCLES_VFD_INDEX = 27, 40052260ae4SRob Clark PERF_VFDP_STALL_CYCLES_VFD_PROG = 28, 40152260ae4SRob Clark PERF_VFDP_STARVE_CYCLES_PC = 29, 40252260ae4SRob Clark PERF_VFDP_VS_STAGE_32_WAVES = 30, 40352260ae4SRob Clark }; 40452260ae4SRob Clark 40552260ae4SRob Clark enum a5xx_hlsq_perfcounter_select { 40652260ae4SRob Clark PERF_HLSQ_BUSY_CYCLES = 0, 40752260ae4SRob Clark PERF_HLSQ_STALL_CYCLES_UCHE = 1, 40852260ae4SRob Clark PERF_HLSQ_STALL_CYCLES_SP_STATE = 2, 40952260ae4SRob Clark PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3, 41052260ae4SRob Clark PERF_HLSQ_UCHE_LATENCY_CYCLES = 4, 41152260ae4SRob Clark PERF_HLSQ_UCHE_LATENCY_COUNT = 5, 41252260ae4SRob Clark PERF_HLSQ_FS_STAGE_32_WAVES = 6, 41352260ae4SRob Clark PERF_HLSQ_FS_STAGE_64_WAVES = 7, 41452260ae4SRob Clark PERF_HLSQ_QUADS = 8, 41552260ae4SRob Clark PERF_HLSQ_SP_STATE_COPY_TRANS_FS_STAGE = 9, 41652260ae4SRob Clark PERF_HLSQ_SP_STATE_COPY_TRANS_VS_STAGE = 10, 41752260ae4SRob Clark PERF_HLSQ_TP_STATE_COPY_TRANS_FS_STAGE = 11, 41852260ae4SRob Clark PERF_HLSQ_TP_STATE_COPY_TRANS_VS_STAGE = 12, 41952260ae4SRob Clark PERF_HLSQ_CS_INVOCATIONS = 13, 42052260ae4SRob Clark PERF_HLSQ_COMPUTE_DRAWCALLS = 14, 42152260ae4SRob Clark }; 42252260ae4SRob Clark 42352260ae4SRob Clark enum a5xx_vpc_perfcounter_select { 42452260ae4SRob Clark PERF_VPC_BUSY_CYCLES = 0, 42552260ae4SRob Clark PERF_VPC_WORKING_CYCLES = 1, 42652260ae4SRob Clark PERF_VPC_STALL_CYCLES_UCHE = 2, 42752260ae4SRob Clark PERF_VPC_STALL_CYCLES_VFD_WACK = 3, 42852260ae4SRob Clark PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4, 42952260ae4SRob Clark PERF_VPC_STALL_CYCLES_PC = 5, 43052260ae4SRob Clark PERF_VPC_STALL_CYCLES_SP_LM = 6, 43152260ae4SRob Clark PERF_VPC_POS_EXPORT_STALL_CYCLES = 7, 43252260ae4SRob Clark PERF_VPC_STARVE_CYCLES_SP = 8, 43352260ae4SRob Clark PERF_VPC_STARVE_CYCLES_LRZ = 9, 43452260ae4SRob Clark PERF_VPC_PC_PRIMITIVES = 10, 43552260ae4SRob Clark PERF_VPC_SP_COMPONENTS = 11, 43652260ae4SRob Clark PERF_VPC_SP_LM_PRIMITIVES = 12, 43752260ae4SRob Clark PERF_VPC_SP_LM_COMPONENTS = 13, 43852260ae4SRob Clark PERF_VPC_SP_LM_DWORDS = 14, 43952260ae4SRob Clark PERF_VPC_STREAMOUT_COMPONENTS = 15, 44052260ae4SRob Clark PERF_VPC_GRANT_PHASES = 16, 44152260ae4SRob Clark }; 44252260ae4SRob Clark 44352260ae4SRob Clark enum a5xx_tse_perfcounter_select { 44452260ae4SRob Clark PERF_TSE_BUSY_CYCLES = 0, 44552260ae4SRob Clark PERF_TSE_CLIPPING_CYCLES = 1, 44652260ae4SRob Clark PERF_TSE_STALL_CYCLES_RAS = 2, 44752260ae4SRob Clark PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3, 44852260ae4SRob Clark PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4, 44952260ae4SRob Clark PERF_TSE_STARVE_CYCLES_PC = 5, 45052260ae4SRob Clark PERF_TSE_INPUT_PRIM = 6, 45152260ae4SRob Clark PERF_TSE_INPUT_NULL_PRIM = 7, 45252260ae4SRob Clark PERF_TSE_TRIVAL_REJ_PRIM = 8, 45352260ae4SRob Clark PERF_TSE_CLIPPED_PRIM = 9, 45452260ae4SRob Clark PERF_TSE_ZERO_AREA_PRIM = 10, 45552260ae4SRob Clark PERF_TSE_FACENESS_CULLED_PRIM = 11, 45652260ae4SRob Clark PERF_TSE_ZERO_PIXEL_PRIM = 12, 45752260ae4SRob Clark PERF_TSE_OUTPUT_NULL_PRIM = 13, 45852260ae4SRob Clark PERF_TSE_OUTPUT_VISIBLE_PRIM = 14, 45952260ae4SRob Clark PERF_TSE_CINVOCATION = 15, 46052260ae4SRob Clark PERF_TSE_CPRIMITIVES = 16, 46152260ae4SRob Clark PERF_TSE_2D_INPUT_PRIM = 17, 46252260ae4SRob Clark PERF_TSE_2D_ALIVE_CLCLES = 18, 46352260ae4SRob Clark }; 46452260ae4SRob Clark 46552260ae4SRob Clark enum a5xx_ras_perfcounter_select { 46652260ae4SRob Clark PERF_RAS_BUSY_CYCLES = 0, 46752260ae4SRob Clark PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1, 46852260ae4SRob Clark PERF_RAS_STALL_CYCLES_LRZ = 2, 46952260ae4SRob Clark PERF_RAS_STARVE_CYCLES_TSE = 3, 47052260ae4SRob Clark PERF_RAS_SUPER_TILES = 4, 47152260ae4SRob Clark PERF_RAS_8X4_TILES = 5, 47252260ae4SRob Clark PERF_RAS_MASKGEN_ACTIVE = 6, 47352260ae4SRob Clark PERF_RAS_FULLY_COVERED_SUPER_TILES = 7, 47452260ae4SRob Clark PERF_RAS_FULLY_COVERED_8X4_TILES = 8, 47552260ae4SRob Clark PERF_RAS_PRIM_KILLED_INVISILBE = 9, 47652260ae4SRob Clark }; 47752260ae4SRob Clark 47852260ae4SRob Clark enum a5xx_lrz_perfcounter_select { 47952260ae4SRob Clark PERF_LRZ_BUSY_CYCLES = 0, 48052260ae4SRob Clark PERF_LRZ_STARVE_CYCLES_RAS = 1, 48152260ae4SRob Clark PERF_LRZ_STALL_CYCLES_RB = 2, 48252260ae4SRob Clark PERF_LRZ_STALL_CYCLES_VSC = 3, 48352260ae4SRob Clark PERF_LRZ_STALL_CYCLES_VPC = 4, 48452260ae4SRob Clark PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5, 48552260ae4SRob Clark PERF_LRZ_STALL_CYCLES_UCHE = 6, 48652260ae4SRob Clark PERF_LRZ_LRZ_READ = 7, 48752260ae4SRob Clark PERF_LRZ_LRZ_WRITE = 8, 48852260ae4SRob Clark PERF_LRZ_READ_LATENCY = 9, 48952260ae4SRob Clark PERF_LRZ_MERGE_CACHE_UPDATING = 10, 49052260ae4SRob Clark PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11, 49152260ae4SRob Clark PERF_LRZ_PRIM_KILLED_BY_LRZ = 12, 49252260ae4SRob Clark PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13, 49352260ae4SRob Clark PERF_LRZ_FULL_8X8_TILES = 14, 49452260ae4SRob Clark PERF_LRZ_PARTIAL_8X8_TILES = 15, 49552260ae4SRob Clark PERF_LRZ_TILE_KILLED = 16, 49652260ae4SRob Clark PERF_LRZ_TOTAL_PIXEL = 17, 49752260ae4SRob Clark PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18, 49852260ae4SRob Clark }; 49952260ae4SRob Clark 50052260ae4SRob Clark enum a5xx_uche_perfcounter_select { 50152260ae4SRob Clark PERF_UCHE_BUSY_CYCLES = 0, 50252260ae4SRob Clark PERF_UCHE_STALL_CYCLES_VBIF = 1, 50352260ae4SRob Clark PERF_UCHE_VBIF_LATENCY_CYCLES = 2, 50452260ae4SRob Clark PERF_UCHE_VBIF_LATENCY_SAMPLES = 3, 50552260ae4SRob Clark PERF_UCHE_VBIF_READ_BEATS_TP = 4, 50652260ae4SRob Clark PERF_UCHE_VBIF_READ_BEATS_VFD = 5, 50752260ae4SRob Clark PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6, 50852260ae4SRob Clark PERF_UCHE_VBIF_READ_BEATS_LRZ = 7, 50952260ae4SRob Clark PERF_UCHE_VBIF_READ_BEATS_SP = 8, 51052260ae4SRob Clark PERF_UCHE_READ_REQUESTS_TP = 9, 51152260ae4SRob Clark PERF_UCHE_READ_REQUESTS_VFD = 10, 51252260ae4SRob Clark PERF_UCHE_READ_REQUESTS_HLSQ = 11, 51352260ae4SRob Clark PERF_UCHE_READ_REQUESTS_LRZ = 12, 51452260ae4SRob Clark PERF_UCHE_READ_REQUESTS_SP = 13, 51552260ae4SRob Clark PERF_UCHE_WRITE_REQUESTS_LRZ = 14, 51652260ae4SRob Clark PERF_UCHE_WRITE_REQUESTS_SP = 15, 51752260ae4SRob Clark PERF_UCHE_WRITE_REQUESTS_VPC = 16, 51852260ae4SRob Clark PERF_UCHE_WRITE_REQUESTS_VSC = 17, 51952260ae4SRob Clark PERF_UCHE_EVICTS = 18, 52052260ae4SRob Clark PERF_UCHE_BANK_REQ0 = 19, 52152260ae4SRob Clark PERF_UCHE_BANK_REQ1 = 20, 52252260ae4SRob Clark PERF_UCHE_BANK_REQ2 = 21, 52352260ae4SRob Clark PERF_UCHE_BANK_REQ3 = 22, 52452260ae4SRob Clark PERF_UCHE_BANK_REQ4 = 23, 52552260ae4SRob Clark PERF_UCHE_BANK_REQ5 = 24, 52652260ae4SRob Clark PERF_UCHE_BANK_REQ6 = 25, 52752260ae4SRob Clark PERF_UCHE_BANK_REQ7 = 26, 52852260ae4SRob Clark PERF_UCHE_VBIF_READ_BEATS_CH0 = 27, 52952260ae4SRob Clark PERF_UCHE_VBIF_READ_BEATS_CH1 = 28, 53052260ae4SRob Clark PERF_UCHE_GMEM_READ_BEATS = 29, 53152260ae4SRob Clark PERF_UCHE_FLAG_COUNT = 30, 53252260ae4SRob Clark }; 53352260ae4SRob Clark 53452260ae4SRob Clark enum a5xx_tp_perfcounter_select { 53552260ae4SRob Clark PERF_TP_BUSY_CYCLES = 0, 53652260ae4SRob Clark PERF_TP_STALL_CYCLES_UCHE = 1, 53752260ae4SRob Clark PERF_TP_LATENCY_CYCLES = 2, 53852260ae4SRob Clark PERF_TP_LATENCY_TRANS = 3, 53952260ae4SRob Clark PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4, 54052260ae4SRob Clark PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5, 54152260ae4SRob Clark PERF_TP_L1_CACHELINE_REQUESTS = 6, 54252260ae4SRob Clark PERF_TP_L1_CACHELINE_MISSES = 7, 54352260ae4SRob Clark PERF_TP_SP_TP_TRANS = 8, 54452260ae4SRob Clark PERF_TP_TP_SP_TRANS = 9, 54552260ae4SRob Clark PERF_TP_OUTPUT_PIXELS = 10, 54652260ae4SRob Clark PERF_TP_FILTER_WORKLOAD_16BIT = 11, 54752260ae4SRob Clark PERF_TP_FILTER_WORKLOAD_32BIT = 12, 54852260ae4SRob Clark PERF_TP_QUADS_RECEIVED = 13, 54952260ae4SRob Clark PERF_TP_QUADS_OFFSET = 14, 55052260ae4SRob Clark PERF_TP_QUADS_SHADOW = 15, 55152260ae4SRob Clark PERF_TP_QUADS_ARRAY = 16, 55252260ae4SRob Clark PERF_TP_QUADS_GRADIENT = 17, 55352260ae4SRob Clark PERF_TP_QUADS_1D = 18, 55452260ae4SRob Clark PERF_TP_QUADS_2D = 19, 55552260ae4SRob Clark PERF_TP_QUADS_BUFFER = 20, 55652260ae4SRob Clark PERF_TP_QUADS_3D = 21, 55752260ae4SRob Clark PERF_TP_QUADS_CUBE = 22, 55852260ae4SRob Clark PERF_TP_STATE_CACHE_REQUESTS = 23, 55952260ae4SRob Clark PERF_TP_STATE_CACHE_MISSES = 24, 56052260ae4SRob Clark PERF_TP_DIVERGENT_QUADS_RECEIVED = 25, 56152260ae4SRob Clark PERF_TP_BINDLESS_STATE_CACHE_REQUESTS = 26, 56252260ae4SRob Clark PERF_TP_BINDLESS_STATE_CACHE_MISSES = 27, 56352260ae4SRob Clark PERF_TP_PRT_NON_RESIDENT_EVENTS = 28, 56452260ae4SRob Clark PERF_TP_OUTPUT_PIXELS_POINT = 29, 56552260ae4SRob Clark PERF_TP_OUTPUT_PIXELS_BILINEAR = 30, 56652260ae4SRob Clark PERF_TP_OUTPUT_PIXELS_MIP = 31, 56752260ae4SRob Clark PERF_TP_OUTPUT_PIXELS_ANISO = 32, 56852260ae4SRob Clark PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 33, 56952260ae4SRob Clark PERF_TP_FLAG_CACHE_REQUESTS = 34, 57052260ae4SRob Clark PERF_TP_FLAG_CACHE_MISSES = 35, 57152260ae4SRob Clark PERF_TP_L1_5_L2_REQUESTS = 36, 57252260ae4SRob Clark PERF_TP_2D_OUTPUT_PIXELS = 37, 57352260ae4SRob Clark PERF_TP_2D_OUTPUT_PIXELS_POINT = 38, 57452260ae4SRob Clark PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 39, 57552260ae4SRob Clark PERF_TP_2D_FILTER_WORKLOAD_16BIT = 40, 57652260ae4SRob Clark PERF_TP_2D_FILTER_WORKLOAD_32BIT = 41, 57752260ae4SRob Clark }; 57852260ae4SRob Clark 57952260ae4SRob Clark enum a5xx_sp_perfcounter_select { 58052260ae4SRob Clark PERF_SP_BUSY_CYCLES = 0, 58152260ae4SRob Clark PERF_SP_ALU_WORKING_CYCLES = 1, 58252260ae4SRob Clark PERF_SP_EFU_WORKING_CYCLES = 2, 58352260ae4SRob Clark PERF_SP_STALL_CYCLES_VPC = 3, 58452260ae4SRob Clark PERF_SP_STALL_CYCLES_TP = 4, 58552260ae4SRob Clark PERF_SP_STALL_CYCLES_UCHE = 5, 58652260ae4SRob Clark PERF_SP_STALL_CYCLES_RB = 6, 58752260ae4SRob Clark PERF_SP_SCHEDULER_NON_WORKING = 7, 58852260ae4SRob Clark PERF_SP_WAVE_CONTEXTS = 8, 58952260ae4SRob Clark PERF_SP_WAVE_CONTEXT_CYCLES = 9, 59052260ae4SRob Clark PERF_SP_FS_STAGE_WAVE_CYCLES = 10, 59152260ae4SRob Clark PERF_SP_FS_STAGE_WAVE_SAMPLES = 11, 59252260ae4SRob Clark PERF_SP_VS_STAGE_WAVE_CYCLES = 12, 59352260ae4SRob Clark PERF_SP_VS_STAGE_WAVE_SAMPLES = 13, 59452260ae4SRob Clark PERF_SP_FS_STAGE_DURATION_CYCLES = 14, 59552260ae4SRob Clark PERF_SP_VS_STAGE_DURATION_CYCLES = 15, 59652260ae4SRob Clark PERF_SP_WAVE_CTRL_CYCLES = 16, 59752260ae4SRob Clark PERF_SP_WAVE_LOAD_CYCLES = 17, 59852260ae4SRob Clark PERF_SP_WAVE_EMIT_CYCLES = 18, 59952260ae4SRob Clark PERF_SP_WAVE_NOP_CYCLES = 19, 60052260ae4SRob Clark PERF_SP_WAVE_WAIT_CYCLES = 20, 60152260ae4SRob Clark PERF_SP_WAVE_FETCH_CYCLES = 21, 60252260ae4SRob Clark PERF_SP_WAVE_IDLE_CYCLES = 22, 60352260ae4SRob Clark PERF_SP_WAVE_END_CYCLES = 23, 60452260ae4SRob Clark PERF_SP_WAVE_LONG_SYNC_CYCLES = 24, 60552260ae4SRob Clark PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25, 60652260ae4SRob Clark PERF_SP_WAVE_JOIN_CYCLES = 26, 60752260ae4SRob Clark PERF_SP_LM_LOAD_INSTRUCTIONS = 27, 60852260ae4SRob Clark PERF_SP_LM_STORE_INSTRUCTIONS = 28, 60952260ae4SRob Clark PERF_SP_LM_ATOMICS = 29, 61052260ae4SRob Clark PERF_SP_GM_LOAD_INSTRUCTIONS = 30, 61152260ae4SRob Clark PERF_SP_GM_STORE_INSTRUCTIONS = 31, 61252260ae4SRob Clark PERF_SP_GM_ATOMICS = 32, 61352260ae4SRob Clark PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33, 61452260ae4SRob Clark PERF_SP_VS_STAGE_CFLOW_INSTRUCTIONS = 34, 61552260ae4SRob Clark PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 35, 61652260ae4SRob Clark PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 36, 61752260ae4SRob Clark PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 37, 61852260ae4SRob Clark PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 38, 61952260ae4SRob Clark PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 39, 62052260ae4SRob Clark PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 40, 62152260ae4SRob Clark PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 41, 62252260ae4SRob Clark PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 42, 62352260ae4SRob Clark PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 43, 62452260ae4SRob Clark PERF_SP_VS_INSTRUCTIONS = 44, 62552260ae4SRob Clark PERF_SP_FS_INSTRUCTIONS = 45, 62652260ae4SRob Clark PERF_SP_ADDR_LOCK_COUNT = 46, 62752260ae4SRob Clark PERF_SP_UCHE_READ_TRANS = 47, 62852260ae4SRob Clark PERF_SP_UCHE_WRITE_TRANS = 48, 62952260ae4SRob Clark PERF_SP_EXPORT_VPC_TRANS = 49, 63052260ae4SRob Clark PERF_SP_EXPORT_RB_TRANS = 50, 63152260ae4SRob Clark PERF_SP_PIXELS_KILLED = 51, 63252260ae4SRob Clark PERF_SP_ICL1_REQUESTS = 52, 63352260ae4SRob Clark PERF_SP_ICL1_MISSES = 53, 63452260ae4SRob Clark PERF_SP_ICL0_REQUESTS = 54, 63552260ae4SRob Clark PERF_SP_ICL0_MISSES = 55, 63652260ae4SRob Clark PERF_SP_HS_INSTRUCTIONS = 56, 63752260ae4SRob Clark PERF_SP_DS_INSTRUCTIONS = 57, 63852260ae4SRob Clark PERF_SP_GS_INSTRUCTIONS = 58, 63952260ae4SRob Clark PERF_SP_CS_INSTRUCTIONS = 59, 64052260ae4SRob Clark PERF_SP_GPR_READ = 60, 64152260ae4SRob Clark PERF_SP_GPR_WRITE = 61, 64252260ae4SRob Clark PERF_SP_LM_CH0_REQUESTS = 62, 64352260ae4SRob Clark PERF_SP_LM_CH1_REQUESTS = 63, 64452260ae4SRob Clark PERF_SP_LM_BANK_CONFLICTS = 64, 64552260ae4SRob Clark }; 64652260ae4SRob Clark 64752260ae4SRob Clark enum a5xx_rb_perfcounter_select { 64852260ae4SRob Clark PERF_RB_BUSY_CYCLES = 0, 64952260ae4SRob Clark PERF_RB_STALL_CYCLES_CCU = 1, 65052260ae4SRob Clark PERF_RB_STALL_CYCLES_HLSQ = 2, 65152260ae4SRob Clark PERF_RB_STALL_CYCLES_FIFO0_FULL = 3, 65252260ae4SRob Clark PERF_RB_STALL_CYCLES_FIFO1_FULL = 4, 65352260ae4SRob Clark PERF_RB_STALL_CYCLES_FIFO2_FULL = 5, 65452260ae4SRob Clark PERF_RB_STARVE_CYCLES_SP = 6, 65552260ae4SRob Clark PERF_RB_STARVE_CYCLES_LRZ_TILE = 7, 65652260ae4SRob Clark PERF_RB_STARVE_CYCLES_CCU = 8, 65752260ae4SRob Clark PERF_RB_STARVE_CYCLES_Z_PLANE = 9, 65852260ae4SRob Clark PERF_RB_STARVE_CYCLES_BARY_PLANE = 10, 65952260ae4SRob Clark PERF_RB_Z_WORKLOAD = 11, 66052260ae4SRob Clark PERF_RB_HLSQ_ACTIVE = 12, 66152260ae4SRob Clark PERF_RB_Z_READ = 13, 66252260ae4SRob Clark PERF_RB_Z_WRITE = 14, 66352260ae4SRob Clark PERF_RB_C_READ = 15, 66452260ae4SRob Clark PERF_RB_C_WRITE = 16, 66552260ae4SRob Clark PERF_RB_TOTAL_PASS = 17, 66652260ae4SRob Clark PERF_RB_Z_PASS = 18, 66752260ae4SRob Clark PERF_RB_Z_FAIL = 19, 66852260ae4SRob Clark PERF_RB_S_FAIL = 20, 66952260ae4SRob Clark PERF_RB_BLENDED_FXP_COMPONENTS = 21, 67052260ae4SRob Clark PERF_RB_BLENDED_FP16_COMPONENTS = 22, 67152260ae4SRob Clark RB_RESERVED = 23, 67252260ae4SRob Clark PERF_RB_2D_ALIVE_CYCLES = 24, 67352260ae4SRob Clark PERF_RB_2D_STALL_CYCLES_A2D = 25, 67452260ae4SRob Clark PERF_RB_2D_STARVE_CYCLES_SRC = 26, 67552260ae4SRob Clark PERF_RB_2D_STARVE_CYCLES_SP = 27, 67652260ae4SRob Clark PERF_RB_2D_STARVE_CYCLES_DST = 28, 67752260ae4SRob Clark PERF_RB_2D_VALID_PIXELS = 29, 67852260ae4SRob Clark }; 67952260ae4SRob Clark 68052260ae4SRob Clark enum a5xx_rb_samples_perfcounter_select { 68152260ae4SRob Clark TOTAL_SAMPLES = 0, 68252260ae4SRob Clark ZPASS_SAMPLES = 1, 68352260ae4SRob Clark ZFAIL_SAMPLES = 2, 68452260ae4SRob Clark SFAIL_SAMPLES = 3, 68552260ae4SRob Clark }; 68652260ae4SRob Clark 68752260ae4SRob Clark enum a5xx_vsc_perfcounter_select { 68852260ae4SRob Clark PERF_VSC_BUSY_CYCLES = 0, 68952260ae4SRob Clark PERF_VSC_WORKING_CYCLES = 1, 69052260ae4SRob Clark PERF_VSC_STALL_CYCLES_UCHE = 2, 69152260ae4SRob Clark PERF_VSC_EOT_NUM = 3, 69252260ae4SRob Clark }; 69352260ae4SRob Clark 69452260ae4SRob Clark enum a5xx_ccu_perfcounter_select { 69552260ae4SRob Clark PERF_CCU_BUSY_CYCLES = 0, 69652260ae4SRob Clark PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1, 69752260ae4SRob Clark PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2, 69852260ae4SRob Clark PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3, 69952260ae4SRob Clark PERF_CCU_DEPTH_BLOCKS = 4, 70052260ae4SRob Clark PERF_CCU_COLOR_BLOCKS = 5, 70152260ae4SRob Clark PERF_CCU_DEPTH_BLOCK_HIT = 6, 70252260ae4SRob Clark PERF_CCU_COLOR_BLOCK_HIT = 7, 70352260ae4SRob Clark PERF_CCU_PARTIAL_BLOCK_READ = 8, 70452260ae4SRob Clark PERF_CCU_GMEM_READ = 9, 70552260ae4SRob Clark PERF_CCU_GMEM_WRITE = 10, 70652260ae4SRob Clark PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11, 70752260ae4SRob Clark PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12, 70852260ae4SRob Clark PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13, 70952260ae4SRob Clark PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14, 71052260ae4SRob Clark PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15, 71152260ae4SRob Clark PERF_CCU_COLOR_READ_FLAG0_COUNT = 16, 71252260ae4SRob Clark PERF_CCU_COLOR_READ_FLAG1_COUNT = 17, 71352260ae4SRob Clark PERF_CCU_COLOR_READ_FLAG2_COUNT = 18, 71452260ae4SRob Clark PERF_CCU_COLOR_READ_FLAG3_COUNT = 19, 71552260ae4SRob Clark PERF_CCU_COLOR_READ_FLAG4_COUNT = 20, 71652260ae4SRob Clark PERF_CCU_2D_BUSY_CYCLES = 21, 71752260ae4SRob Clark PERF_CCU_2D_RD_REQ = 22, 71852260ae4SRob Clark PERF_CCU_2D_WR_REQ = 23, 71952260ae4SRob Clark PERF_CCU_2D_REORDER_STARVE_CYCLES = 24, 72052260ae4SRob Clark PERF_CCU_2D_PIXELS = 25, 72152260ae4SRob Clark }; 72252260ae4SRob Clark 72352260ae4SRob Clark enum a5xx_cmp_perfcounter_select { 72452260ae4SRob Clark PERF_CMPDECMP_STALL_CYCLES_VBIF = 0, 72552260ae4SRob Clark PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1, 72652260ae4SRob Clark PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2, 72752260ae4SRob Clark PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3, 72852260ae4SRob Clark PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4, 72952260ae4SRob Clark PERF_CMPDECMP_VBIF_READ_REQUEST = 5, 73052260ae4SRob Clark PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6, 73152260ae4SRob Clark PERF_CMPDECMP_VBIF_READ_DATA = 7, 73252260ae4SRob Clark PERF_CMPDECMP_VBIF_WRITE_DATA = 8, 73352260ae4SRob Clark PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9, 73452260ae4SRob Clark PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10, 73552260ae4SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11, 73652260ae4SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12, 73752260ae4SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13, 73852260ae4SRob Clark PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14, 73952260ae4SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 15, 74052260ae4SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 16, 74152260ae4SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 17, 74252260ae4SRob Clark PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 18, 74352260ae4SRob Clark PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 19, 74452260ae4SRob Clark PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 20, 74552260ae4SRob Clark PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 21, 74652260ae4SRob Clark PERF_CMPDECMP_2D_RD_DATA = 22, 74752260ae4SRob Clark PERF_CMPDECMP_2D_WR_DATA = 23, 74852260ae4SRob Clark }; 74952260ae4SRob Clark 75052260ae4SRob Clark enum a5xx_vbif_perfcounter_select { 75152260ae4SRob Clark AXI_READ_REQUESTS_ID_0 = 0, 75252260ae4SRob Clark AXI_READ_REQUESTS_ID_1 = 1, 75352260ae4SRob Clark AXI_READ_REQUESTS_ID_2 = 2, 75452260ae4SRob Clark AXI_READ_REQUESTS_ID_3 = 3, 75552260ae4SRob Clark AXI_READ_REQUESTS_ID_4 = 4, 75652260ae4SRob Clark AXI_READ_REQUESTS_ID_5 = 5, 75752260ae4SRob Clark AXI_READ_REQUESTS_ID_6 = 6, 75852260ae4SRob Clark AXI_READ_REQUESTS_ID_7 = 7, 75952260ae4SRob Clark AXI_READ_REQUESTS_ID_8 = 8, 76052260ae4SRob Clark AXI_READ_REQUESTS_ID_9 = 9, 76152260ae4SRob Clark AXI_READ_REQUESTS_ID_10 = 10, 76252260ae4SRob Clark AXI_READ_REQUESTS_ID_11 = 11, 76352260ae4SRob Clark AXI_READ_REQUESTS_ID_12 = 12, 76452260ae4SRob Clark AXI_READ_REQUESTS_ID_13 = 13, 76552260ae4SRob Clark AXI_READ_REQUESTS_ID_14 = 14, 76652260ae4SRob Clark AXI_READ_REQUESTS_ID_15 = 15, 76752260ae4SRob Clark AXI0_READ_REQUESTS_TOTAL = 16, 76852260ae4SRob Clark AXI1_READ_REQUESTS_TOTAL = 17, 76952260ae4SRob Clark AXI2_READ_REQUESTS_TOTAL = 18, 77052260ae4SRob Clark AXI3_READ_REQUESTS_TOTAL = 19, 77152260ae4SRob Clark AXI_READ_REQUESTS_TOTAL = 20, 77252260ae4SRob Clark AXI_WRITE_REQUESTS_ID_0 = 21, 77352260ae4SRob Clark AXI_WRITE_REQUESTS_ID_1 = 22, 77452260ae4SRob Clark AXI_WRITE_REQUESTS_ID_2 = 23, 77552260ae4SRob Clark AXI_WRITE_REQUESTS_ID_3 = 24, 77652260ae4SRob Clark AXI_WRITE_REQUESTS_ID_4 = 25, 77752260ae4SRob Clark AXI_WRITE_REQUESTS_ID_5 = 26, 77852260ae4SRob Clark AXI_WRITE_REQUESTS_ID_6 = 27, 77952260ae4SRob Clark AXI_WRITE_REQUESTS_ID_7 = 28, 78052260ae4SRob Clark AXI_WRITE_REQUESTS_ID_8 = 29, 78152260ae4SRob Clark AXI_WRITE_REQUESTS_ID_9 = 30, 78252260ae4SRob Clark AXI_WRITE_REQUESTS_ID_10 = 31, 78352260ae4SRob Clark AXI_WRITE_REQUESTS_ID_11 = 32, 78452260ae4SRob Clark AXI_WRITE_REQUESTS_ID_12 = 33, 78552260ae4SRob Clark AXI_WRITE_REQUESTS_ID_13 = 34, 78652260ae4SRob Clark AXI_WRITE_REQUESTS_ID_14 = 35, 78752260ae4SRob Clark AXI_WRITE_REQUESTS_ID_15 = 36, 78852260ae4SRob Clark AXI0_WRITE_REQUESTS_TOTAL = 37, 78952260ae4SRob Clark AXI1_WRITE_REQUESTS_TOTAL = 38, 79052260ae4SRob Clark AXI2_WRITE_REQUESTS_TOTAL = 39, 79152260ae4SRob Clark AXI3_WRITE_REQUESTS_TOTAL = 40, 79252260ae4SRob Clark AXI_WRITE_REQUESTS_TOTAL = 41, 79352260ae4SRob Clark AXI_TOTAL_REQUESTS = 42, 79452260ae4SRob Clark AXI_READ_DATA_BEATS_ID_0 = 43, 79552260ae4SRob Clark AXI_READ_DATA_BEATS_ID_1 = 44, 79652260ae4SRob Clark AXI_READ_DATA_BEATS_ID_2 = 45, 79752260ae4SRob Clark AXI_READ_DATA_BEATS_ID_3 = 46, 79852260ae4SRob Clark AXI_READ_DATA_BEATS_ID_4 = 47, 79952260ae4SRob Clark AXI_READ_DATA_BEATS_ID_5 = 48, 80052260ae4SRob Clark AXI_READ_DATA_BEATS_ID_6 = 49, 80152260ae4SRob Clark AXI_READ_DATA_BEATS_ID_7 = 50, 80252260ae4SRob Clark AXI_READ_DATA_BEATS_ID_8 = 51, 80352260ae4SRob Clark AXI_READ_DATA_BEATS_ID_9 = 52, 80452260ae4SRob Clark AXI_READ_DATA_BEATS_ID_10 = 53, 80552260ae4SRob Clark AXI_READ_DATA_BEATS_ID_11 = 54, 80652260ae4SRob Clark AXI_READ_DATA_BEATS_ID_12 = 55, 80752260ae4SRob Clark AXI_READ_DATA_BEATS_ID_13 = 56, 80852260ae4SRob Clark AXI_READ_DATA_BEATS_ID_14 = 57, 80952260ae4SRob Clark AXI_READ_DATA_BEATS_ID_15 = 58, 81052260ae4SRob Clark AXI0_READ_DATA_BEATS_TOTAL = 59, 81152260ae4SRob Clark AXI1_READ_DATA_BEATS_TOTAL = 60, 81252260ae4SRob Clark AXI2_READ_DATA_BEATS_TOTAL = 61, 81352260ae4SRob Clark AXI3_READ_DATA_BEATS_TOTAL = 62, 81452260ae4SRob Clark AXI_READ_DATA_BEATS_TOTAL = 63, 81552260ae4SRob Clark AXI_WRITE_DATA_BEATS_ID_0 = 64, 81652260ae4SRob Clark AXI_WRITE_DATA_BEATS_ID_1 = 65, 81752260ae4SRob Clark AXI_WRITE_DATA_BEATS_ID_2 = 66, 81852260ae4SRob Clark AXI_WRITE_DATA_BEATS_ID_3 = 67, 81952260ae4SRob Clark AXI_WRITE_DATA_BEATS_ID_4 = 68, 82052260ae4SRob Clark AXI_WRITE_DATA_BEATS_ID_5 = 69, 82152260ae4SRob Clark AXI_WRITE_DATA_BEATS_ID_6 = 70, 82252260ae4SRob Clark AXI_WRITE_DATA_BEATS_ID_7 = 71, 82352260ae4SRob Clark AXI_WRITE_DATA_BEATS_ID_8 = 72, 82452260ae4SRob Clark AXI_WRITE_DATA_BEATS_ID_9 = 73, 82552260ae4SRob Clark AXI_WRITE_DATA_BEATS_ID_10 = 74, 82652260ae4SRob Clark AXI_WRITE_DATA_BEATS_ID_11 = 75, 82752260ae4SRob Clark AXI_WRITE_DATA_BEATS_ID_12 = 76, 82852260ae4SRob Clark AXI_WRITE_DATA_BEATS_ID_13 = 77, 82952260ae4SRob Clark AXI_WRITE_DATA_BEATS_ID_14 = 78, 83052260ae4SRob Clark AXI_WRITE_DATA_BEATS_ID_15 = 79, 83152260ae4SRob Clark AXI0_WRITE_DATA_BEATS_TOTAL = 80, 83252260ae4SRob Clark AXI1_WRITE_DATA_BEATS_TOTAL = 81, 83352260ae4SRob Clark AXI2_WRITE_DATA_BEATS_TOTAL = 82, 83452260ae4SRob Clark AXI3_WRITE_DATA_BEATS_TOTAL = 83, 83552260ae4SRob Clark AXI_WRITE_DATA_BEATS_TOTAL = 84, 83652260ae4SRob Clark AXI_DATA_BEATS_TOTAL = 85, 83752260ae4SRob Clark }; 83852260ae4SRob Clark 839a26ae754SRob Clark enum a5xx_tex_filter { 840a26ae754SRob Clark A5XX_TEX_NEAREST = 0, 841a26ae754SRob Clark A5XX_TEX_LINEAR = 1, 842a26ae754SRob Clark A5XX_TEX_ANISO = 2, 843a26ae754SRob Clark }; 844a26ae754SRob Clark 845a26ae754SRob Clark enum a5xx_tex_clamp { 846a26ae754SRob Clark A5XX_TEX_REPEAT = 0, 847a26ae754SRob Clark A5XX_TEX_CLAMP_TO_EDGE = 1, 848a26ae754SRob Clark A5XX_TEX_MIRROR_REPEAT = 2, 849a26ae754SRob Clark A5XX_TEX_CLAMP_TO_BORDER = 3, 850a26ae754SRob Clark A5XX_TEX_MIRROR_CLAMP = 4, 851a26ae754SRob Clark }; 852a26ae754SRob Clark 853a26ae754SRob Clark enum a5xx_tex_aniso { 854a26ae754SRob Clark A5XX_TEX_ANISO_1 = 0, 855a26ae754SRob Clark A5XX_TEX_ANISO_2 = 1, 856a26ae754SRob Clark A5XX_TEX_ANISO_4 = 2, 857a26ae754SRob Clark A5XX_TEX_ANISO_8 = 3, 858a26ae754SRob Clark A5XX_TEX_ANISO_16 = 4, 859a26ae754SRob Clark }; 860a26ae754SRob Clark 861a26ae754SRob Clark enum a5xx_tex_swiz { 862a26ae754SRob Clark A5XX_TEX_X = 0, 863a26ae754SRob Clark A5XX_TEX_Y = 1, 864a26ae754SRob Clark A5XX_TEX_Z = 2, 865a26ae754SRob Clark A5XX_TEX_W = 3, 866a26ae754SRob Clark A5XX_TEX_ZERO = 4, 867a26ae754SRob Clark A5XX_TEX_ONE = 5, 868a26ae754SRob Clark }; 869a26ae754SRob Clark 870a26ae754SRob Clark enum a5xx_tex_type { 871a26ae754SRob Clark A5XX_TEX_1D = 0, 872a26ae754SRob Clark A5XX_TEX_2D = 1, 873a26ae754SRob Clark A5XX_TEX_CUBE = 2, 874a26ae754SRob Clark A5XX_TEX_3D = 3, 875a26ae754SRob Clark }; 876a26ae754SRob Clark 877a26ae754SRob Clark #define A5XX_INT0_RBBM_GPU_IDLE 0x00000001 878a26ae754SRob Clark #define A5XX_INT0_RBBM_AHB_ERROR 0x00000002 879a26ae754SRob Clark #define A5XX_INT0_RBBM_TRANSFER_TIMEOUT 0x00000004 880a26ae754SRob Clark #define A5XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 881a26ae754SRob Clark #define A5XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 882a26ae754SRob Clark #define A5XX_INT0_RBBM_ETS_MS_TIMEOUT 0x00000020 883a26ae754SRob Clark #define A5XX_INT0_RBBM_ATB_ASYNC_OVERFLOW 0x00000040 884a26ae754SRob Clark #define A5XX_INT0_RBBM_GPC_ERROR 0x00000080 885a26ae754SRob Clark #define A5XX_INT0_CP_SW 0x00000100 886a26ae754SRob Clark #define A5XX_INT0_CP_HW_ERROR 0x00000200 887a26ae754SRob Clark #define A5XX_INT0_CP_CCU_FLUSH_DEPTH_TS 0x00000400 888a26ae754SRob Clark #define A5XX_INT0_CP_CCU_FLUSH_COLOR_TS 0x00000800 889a26ae754SRob Clark #define A5XX_INT0_CP_CCU_RESOLVE_TS 0x00001000 890a26ae754SRob Clark #define A5XX_INT0_CP_IB2 0x00002000 891a26ae754SRob Clark #define A5XX_INT0_CP_IB1 0x00004000 892a26ae754SRob Clark #define A5XX_INT0_CP_RB 0x00008000 893a26ae754SRob Clark #define A5XX_INT0_CP_UNUSED_1 0x00010000 894a26ae754SRob Clark #define A5XX_INT0_CP_RB_DONE_TS 0x00020000 895a26ae754SRob Clark #define A5XX_INT0_CP_WT_DONE_TS 0x00040000 896a26ae754SRob Clark #define A5XX_INT0_UNKNOWN_1 0x00080000 897a26ae754SRob Clark #define A5XX_INT0_CP_CACHE_FLUSH_TS 0x00100000 898a26ae754SRob Clark #define A5XX_INT0_UNUSED_2 0x00200000 899a26ae754SRob Clark #define A5XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00400000 900a26ae754SRob Clark #define A5XX_INT0_MISC_HANG_DETECT 0x00800000 901a26ae754SRob Clark #define A5XX_INT0_UCHE_OOB_ACCESS 0x01000000 902a26ae754SRob Clark #define A5XX_INT0_UCHE_TRAP_INTR 0x02000000 903a26ae754SRob Clark #define A5XX_INT0_DEBBUS_INTR_0 0x04000000 904a26ae754SRob Clark #define A5XX_INT0_DEBBUS_INTR_1 0x08000000 905a26ae754SRob Clark #define A5XX_INT0_GPMU_VOLTAGE_DROOP 0x10000000 906a26ae754SRob Clark #define A5XX_INT0_GPMU_FIRMWARE 0x20000000 907a26ae754SRob Clark #define A5XX_INT0_ISDB_CPU_IRQ 0x40000000 908a26ae754SRob Clark #define A5XX_INT0_ISDB_UNDER_DEBUG 0x80000000 909a26ae754SRob Clark #define A5XX_CP_INT_CP_OPCODE_ERROR 0x00000001 910a26ae754SRob Clark #define A5XX_CP_INT_CP_RESERVED_BIT_ERROR 0x00000002 911a26ae754SRob Clark #define A5XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004 912a26ae754SRob Clark #define A5XX_CP_INT_CP_DMA_ERROR 0x00000008 913a26ae754SRob Clark #define A5XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010 914a26ae754SRob Clark #define A5XX_CP_INT_CP_AHB_ERROR 0x00000020 915a26ae754SRob Clark #define REG_A5XX_CP_RB_BASE 0x00000800 916a26ae754SRob Clark 917a26ae754SRob Clark #define REG_A5XX_CP_RB_BASE_HI 0x00000801 918a26ae754SRob Clark 919a26ae754SRob Clark #define REG_A5XX_CP_RB_CNTL 0x00000802 920a26ae754SRob Clark 921a26ae754SRob Clark #define REG_A5XX_CP_RB_RPTR_ADDR 0x00000804 922a26ae754SRob Clark 923a26ae754SRob Clark #define REG_A5XX_CP_RB_RPTR_ADDR_HI 0x00000805 924a26ae754SRob Clark 925a26ae754SRob Clark #define REG_A5XX_CP_RB_RPTR 0x00000806 926a26ae754SRob Clark 927a26ae754SRob Clark #define REG_A5XX_CP_RB_WPTR 0x00000807 928a26ae754SRob Clark 929a26ae754SRob Clark #define REG_A5XX_CP_PFP_STAT_ADDR 0x00000808 930a26ae754SRob Clark 931a26ae754SRob Clark #define REG_A5XX_CP_PFP_STAT_DATA 0x00000809 932a26ae754SRob Clark 933a26ae754SRob Clark #define REG_A5XX_CP_DRAW_STATE_ADDR 0x0000080b 934a26ae754SRob Clark 935a26ae754SRob Clark #define REG_A5XX_CP_DRAW_STATE_DATA 0x0000080c 936a26ae754SRob Clark 9372d756322SRob Clark #define REG_A5XX_CP_ME_NRT_ADDR_LO 0x0000080d 9382d756322SRob Clark 9392d756322SRob Clark #define REG_A5XX_CP_ME_NRT_ADDR_HI 0x0000080e 9402d756322SRob Clark 9412d756322SRob Clark #define REG_A5XX_CP_ME_NRT_DATA 0x00000810 9422d756322SRob Clark 943a26ae754SRob Clark #define REG_A5XX_CP_CRASH_SCRIPT_BASE_LO 0x00000817 944a26ae754SRob Clark 945a26ae754SRob Clark #define REG_A5XX_CP_CRASH_SCRIPT_BASE_HI 0x00000818 946a26ae754SRob Clark 947a26ae754SRob Clark #define REG_A5XX_CP_CRASH_DUMP_CNTL 0x00000819 948a26ae754SRob Clark 949a26ae754SRob Clark #define REG_A5XX_CP_ME_STAT_ADDR 0x0000081a 950a26ae754SRob Clark 951a26ae754SRob Clark #define REG_A5XX_CP_ROQ_THRESHOLDS_1 0x0000081f 952a26ae754SRob Clark 953a26ae754SRob Clark #define REG_A5XX_CP_ROQ_THRESHOLDS_2 0x00000820 954a26ae754SRob Clark 955a26ae754SRob Clark #define REG_A5XX_CP_ROQ_DBG_ADDR 0x00000821 956a26ae754SRob Clark 957a26ae754SRob Clark #define REG_A5XX_CP_ROQ_DBG_DATA 0x00000822 958a26ae754SRob Clark 959a26ae754SRob Clark #define REG_A5XX_CP_MEQ_DBG_ADDR 0x00000823 960a26ae754SRob Clark 961a26ae754SRob Clark #define REG_A5XX_CP_MEQ_DBG_DATA 0x00000824 962a26ae754SRob Clark 963a26ae754SRob Clark #define REG_A5XX_CP_MEQ_THRESHOLDS 0x00000825 964a26ae754SRob Clark 965a26ae754SRob Clark #define REG_A5XX_CP_MERCIU_SIZE 0x00000826 966a26ae754SRob Clark 967a26ae754SRob Clark #define REG_A5XX_CP_MERCIU_DBG_ADDR 0x00000827 968a26ae754SRob Clark 969a26ae754SRob Clark #define REG_A5XX_CP_MERCIU_DBG_DATA_1 0x00000828 970a26ae754SRob Clark 971a26ae754SRob Clark #define REG_A5XX_CP_MERCIU_DBG_DATA_2 0x00000829 972a26ae754SRob Clark 973a26ae754SRob Clark #define REG_A5XX_CP_PFP_UCODE_DBG_ADDR 0x0000082a 974a26ae754SRob Clark 975a26ae754SRob Clark #define REG_A5XX_CP_PFP_UCODE_DBG_DATA 0x0000082b 976a26ae754SRob Clark 977a26ae754SRob Clark #define REG_A5XX_CP_ME_UCODE_DBG_ADDR 0x0000082f 978a26ae754SRob Clark 979a26ae754SRob Clark #define REG_A5XX_CP_ME_UCODE_DBG_DATA 0x00000830 980a26ae754SRob Clark 981a26ae754SRob Clark #define REG_A5XX_CP_CNTL 0x00000831 982a26ae754SRob Clark 983a26ae754SRob Clark #define REG_A5XX_CP_PFP_ME_CNTL 0x00000832 984a26ae754SRob Clark 985a26ae754SRob Clark #define REG_A5XX_CP_CHICKEN_DBG 0x00000833 986a26ae754SRob Clark 987a26ae754SRob Clark #define REG_A5XX_CP_PFP_INSTR_BASE_LO 0x00000835 988a26ae754SRob Clark 989a26ae754SRob Clark #define REG_A5XX_CP_PFP_INSTR_BASE_HI 0x00000836 990a26ae754SRob Clark 991a26ae754SRob Clark #define REG_A5XX_CP_ME_INSTR_BASE_LO 0x00000838 992a26ae754SRob Clark 993a26ae754SRob Clark #define REG_A5XX_CP_ME_INSTR_BASE_HI 0x00000839 994a26ae754SRob Clark 995a26ae754SRob Clark #define REG_A5XX_CP_CONTEXT_SWITCH_CNTL 0x0000083b 996a26ae754SRob Clark 997a26ae754SRob Clark #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO 0x0000083c 998a26ae754SRob Clark 999a26ae754SRob Clark #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI 0x0000083d 1000a26ae754SRob Clark 1001a26ae754SRob Clark #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO 0x0000083e 1002a26ae754SRob Clark 1003a26ae754SRob Clark #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_HI 0x0000083f 1004a26ae754SRob Clark 1005a26ae754SRob Clark #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x00000840 1006a26ae754SRob Clark 1007a26ae754SRob Clark #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x00000841 1008a26ae754SRob Clark 1009a26ae754SRob Clark #define REG_A5XX_CP_ADDR_MODE_CNTL 0x00000860 1010a26ae754SRob Clark 1011a26ae754SRob Clark #define REG_A5XX_CP_ME_STAT_DATA 0x00000b14 1012a26ae754SRob Clark 1013a26ae754SRob Clark #define REG_A5XX_CP_WFI_PEND_CTR 0x00000b15 1014a26ae754SRob Clark 1015a26ae754SRob Clark #define REG_A5XX_CP_INTERRUPT_STATUS 0x00000b18 1016a26ae754SRob Clark 1017a26ae754SRob Clark #define REG_A5XX_CP_HW_FAULT 0x00000b1a 1018a26ae754SRob Clark 1019a26ae754SRob Clark #define REG_A5XX_CP_PROTECT_STATUS 0x00000b1c 1020a26ae754SRob Clark 1021a26ae754SRob Clark #define REG_A5XX_CP_IB1_BASE 0x00000b1f 1022a26ae754SRob Clark 1023a26ae754SRob Clark #define REG_A5XX_CP_IB1_BASE_HI 0x00000b20 1024a26ae754SRob Clark 1025a26ae754SRob Clark #define REG_A5XX_CP_IB1_BUFSZ 0x00000b21 1026a26ae754SRob Clark 1027a26ae754SRob Clark #define REG_A5XX_CP_IB2_BASE 0x00000b22 1028a26ae754SRob Clark 1029a26ae754SRob Clark #define REG_A5XX_CP_IB2_BASE_HI 0x00000b23 1030a26ae754SRob Clark 1031a26ae754SRob Clark #define REG_A5XX_CP_IB2_BUFSZ 0x00000b24 1032a26ae754SRob Clark 1033a26ae754SRob Clark static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0) { return 0x00000b78 + 0x1*i0; } 1034a26ae754SRob Clark 1035a26ae754SRob Clark static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; } 1036a26ae754SRob Clark 1037a26ae754SRob Clark static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0) { return 0x00000880 + 0x1*i0; } 1038a26ae754SRob Clark 1039a26ae754SRob Clark static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; } 1040a26ae754SRob Clark #define A5XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff 1041a26ae754SRob Clark #define A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0 1042a26ae754SRob Clark static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) 1043a26ae754SRob Clark { 1044a26ae754SRob Clark return ((val) << A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A5XX_CP_PROTECT_REG_BASE_ADDR__MASK; 1045a26ae754SRob Clark } 1046a26ae754SRob Clark #define A5XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000 1047a26ae754SRob Clark #define A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24 1048a26ae754SRob Clark static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) 1049a26ae754SRob Clark { 1050a26ae754SRob Clark return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK; 1051a26ae754SRob Clark } 1052c28c82e9SRob Clark #define A5XX_CP_PROTECT_REG_TRAP_WRITE__MASK 0x20000000 1053c28c82e9SRob Clark #define A5XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT 29 1054c28c82e9SRob Clark static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_WRITE(uint32_t val) 1055c28c82e9SRob Clark { 1056c28c82e9SRob Clark return ((val) << A5XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT) & A5XX_CP_PROTECT_REG_TRAP_WRITE__MASK; 1057c28c82e9SRob Clark } 1058c28c82e9SRob Clark #define A5XX_CP_PROTECT_REG_TRAP_READ__MASK 0x40000000 1059c28c82e9SRob Clark #define A5XX_CP_PROTECT_REG_TRAP_READ__SHIFT 30 1060c28c82e9SRob Clark static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_READ(uint32_t val) 1061c28c82e9SRob Clark { 1062c28c82e9SRob Clark return ((val) << A5XX_CP_PROTECT_REG_TRAP_READ__SHIFT) & A5XX_CP_PROTECT_REG_TRAP_READ__MASK; 1063c28c82e9SRob Clark } 1064a26ae754SRob Clark 1065a26ae754SRob Clark #define REG_A5XX_CP_PROTECT_CNTL 0x000008a0 1066a26ae754SRob Clark 1067a26ae754SRob Clark #define REG_A5XX_CP_AHB_FAULT 0x00000b1b 1068a26ae754SRob Clark 1069a26ae754SRob Clark #define REG_A5XX_CP_PERFCTR_CP_SEL_0 0x00000bb0 1070a26ae754SRob Clark 1071a26ae754SRob Clark #define REG_A5XX_CP_PERFCTR_CP_SEL_1 0x00000bb1 1072a26ae754SRob Clark 1073a26ae754SRob Clark #define REG_A5XX_CP_PERFCTR_CP_SEL_2 0x00000bb2 1074a26ae754SRob Clark 1075a26ae754SRob Clark #define REG_A5XX_CP_PERFCTR_CP_SEL_3 0x00000bb3 1076a26ae754SRob Clark 1077a26ae754SRob Clark #define REG_A5XX_CP_PERFCTR_CP_SEL_4 0x00000bb4 1078a26ae754SRob Clark 1079a26ae754SRob Clark #define REG_A5XX_CP_PERFCTR_CP_SEL_5 0x00000bb5 1080a26ae754SRob Clark 1081a26ae754SRob Clark #define REG_A5XX_CP_PERFCTR_CP_SEL_6 0x00000bb6 1082a26ae754SRob Clark 1083a26ae754SRob Clark #define REG_A5XX_CP_PERFCTR_CP_SEL_7 0x00000bb7 1084a26ae754SRob Clark 1085a26ae754SRob Clark #define REG_A5XX_VSC_ADDR_MODE_CNTL 0x00000bc1 1086a26ae754SRob Clark 1087a26ae754SRob Clark #define REG_A5XX_CP_POWERCTR_CP_SEL_0 0x00000bba 1088a26ae754SRob Clark 1089a26ae754SRob Clark #define REG_A5XX_CP_POWERCTR_CP_SEL_1 0x00000bbb 1090a26ae754SRob Clark 1091a26ae754SRob Clark #define REG_A5XX_CP_POWERCTR_CP_SEL_2 0x00000bbc 1092a26ae754SRob Clark 1093a26ae754SRob Clark #define REG_A5XX_CP_POWERCTR_CP_SEL_3 0x00000bbd 1094a26ae754SRob Clark 1095a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_A 0x00000004 1096a26ae754SRob Clark 1097a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_B 0x00000005 1098a26ae754SRob Clark 1099a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_C 0x00000006 1100a26ae754SRob Clark 1101a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_D 0x00000007 1102a26ae754SRob Clark 1103a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLT 0x00000008 1104a26ae754SRob Clark 1105a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLM 0x00000009 1106a26ae754SRob Clark 1107a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT 0x00000018 1108a26ae754SRob Clark 1109a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_OPL 0x0000000a 1110a26ae754SRob Clark 1111a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_OPE 0x0000000b 1112a26ae754SRob Clark 1113a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_0 0x0000000c 1114a26ae754SRob Clark 1115a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_1 0x0000000d 1116a26ae754SRob Clark 1117a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_2 0x0000000e 1118a26ae754SRob Clark 1119a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_3 0x0000000f 1120a26ae754SRob Clark 1121a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_0 0x00000010 1122a26ae754SRob Clark 1123a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_1 0x00000011 1124a26ae754SRob Clark 1125a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_2 0x00000012 1126a26ae754SRob Clark 1127a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_3 0x00000013 1128a26ae754SRob Clark 1129a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_0 0x00000014 1130a26ae754SRob Clark 1131a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_1 0x00000015 1132a26ae754SRob Clark 1133a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_0 0x00000016 1134a26ae754SRob Clark 1135a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_1 0x00000017 1136a26ae754SRob Clark 1137a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_2 0x00000018 1138a26ae754SRob Clark 1139a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_3 0x00000019 1140a26ae754SRob Clark 1141a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_0 0x0000001a 1142a26ae754SRob Clark 1143a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_1 0x0000001b 1144a26ae754SRob Clark 1145a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_2 0x0000001c 1146a26ae754SRob Clark 1147a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_3 0x0000001d 1148a26ae754SRob Clark 1149a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_NIBBLEE 0x0000001e 1150a26ae754SRob Clark 1151a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC0 0x0000001f 1152a26ae754SRob Clark 1153a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC1 0x00000020 1154a26ae754SRob Clark 1155a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_LOADREG 0x00000021 1156a26ae754SRob Clark 1157a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_IDX 0x00000022 1158a26ae754SRob Clark 1159a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_CLRC 0x00000023 1160a26ae754SRob Clark 1161a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_LOADIVT 0x00000024 1162a26ae754SRob Clark 1163a26ae754SRob Clark #define REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000002f 1164a26ae754SRob Clark 1165a26ae754SRob Clark #define REG_A5XX_RBBM_INT_CLEAR_CMD 0x00000037 1166a26ae754SRob Clark 1167a26ae754SRob Clark #define REG_A5XX_RBBM_INT_0_MASK 0x00000038 1168a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001 1169a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR 0x00000002 1170a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT 0x00000004 1171a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT 0x00000008 1172a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT 0x00000010 1173a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT 0x00000020 1174a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW 0x00000040 1175a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080 1176a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_CP_SW 0x00000100 1177a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200 1178a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400 1179a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800 1180a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000 1181a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_CP_IB2 0x00002000 1182a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_CP_IB1 0x00004000 1183a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_CP_RB 0x00008000 1184a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000 1185a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000 1186a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000 1187a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000 1188a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT 0x00800000 1189a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000 1190a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000 1191a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000 1192a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000 1193a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP 0x10000000 1194a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_GPMU_FIRMWARE 0x20000000 1195a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000 1196a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000 1197a26ae754SRob Clark 1198a26ae754SRob Clark #define REG_A5XX_RBBM_AHB_DBG_CNTL 0x0000003f 1199a26ae754SRob Clark 1200a26ae754SRob Clark #define REG_A5XX_RBBM_EXT_VBIF_DBG_CNTL 0x00000041 1201a26ae754SRob Clark 1202a26ae754SRob Clark #define REG_A5XX_RBBM_SW_RESET_CMD 0x00000043 1203a26ae754SRob Clark 1204a26ae754SRob Clark #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 1205a26ae754SRob Clark 1206a26ae754SRob Clark #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046 1207a26ae754SRob Clark 1208a26ae754SRob Clark #define REG_A5XX_RBBM_DBG_LO_HI_GPIO 0x00000048 1209a26ae754SRob Clark 1210a26ae754SRob Clark #define REG_A5XX_RBBM_EXT_TRACE_BUS_CNTL 0x00000049 1211a26ae754SRob Clark 1212a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_TP0 0x0000004a 1213a26ae754SRob Clark 1214a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_TP1 0x0000004b 1215a26ae754SRob Clark 1216a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_TP2 0x0000004c 1217a26ae754SRob Clark 1218a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_TP3 0x0000004d 1219a26ae754SRob Clark 1220a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL2_TP0 0x0000004e 1221a26ae754SRob Clark 1222a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL2_TP1 0x0000004f 1223a26ae754SRob Clark 1224a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL2_TP2 0x00000050 1225a26ae754SRob Clark 1226a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL2_TP3 0x00000051 1227a26ae754SRob Clark 1228a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL3_TP0 0x00000052 1229a26ae754SRob Clark 1230a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL3_TP1 0x00000053 1231a26ae754SRob Clark 1232a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL3_TP2 0x00000054 1233a26ae754SRob Clark 1234a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL3_TP3 0x00000055 1235a26ae754SRob Clark 1236a26ae754SRob Clark #define REG_A5XX_RBBM_READ_AHB_THROUGH_DBG 0x00000059 1237a26ae754SRob Clark 1238a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_UCHE 0x0000005a 1239a26ae754SRob Clark 1240a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL2_UCHE 0x0000005b 1241a26ae754SRob Clark 1242a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL3_UCHE 0x0000005c 1243a26ae754SRob Clark 1244a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL4_UCHE 0x0000005d 1245a26ae754SRob Clark 1246a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_UCHE 0x0000005e 1247a26ae754SRob Clark 1248a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_UCHE 0x0000005f 1249a26ae754SRob Clark 1250a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_MODE_GPC 0x00000060 1251a26ae754SRob Clark 1252a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_GPC 0x00000061 1253a26ae754SRob Clark 1254a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_GPC 0x00000062 1255a26ae754SRob Clark 1256a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000063 1257a26ae754SRob Clark 1258a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x00000064 1259a26ae754SRob Clark 1260a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000065 1261a26ae754SRob Clark 1262a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_HLSQ 0x00000066 1263a26ae754SRob Clark 1264a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL 0x00000067 1265a26ae754SRob Clark 1266a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_SP0 0x00000068 1267a26ae754SRob Clark 1268a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_SP1 0x00000069 1269a26ae754SRob Clark 1270a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_SP2 0x0000006a 1271a26ae754SRob Clark 1272a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_SP3 0x0000006b 1273a26ae754SRob Clark 1274a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL2_SP0 0x0000006c 1275a26ae754SRob Clark 1276a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL2_SP1 0x0000006d 1277a26ae754SRob Clark 1278a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL2_SP2 0x0000006e 1279a26ae754SRob Clark 1280a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL2_SP3 0x0000006f 1281a26ae754SRob Clark 1282a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_SP0 0x00000070 1283a26ae754SRob Clark 1284a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_SP1 0x00000071 1285a26ae754SRob Clark 1286a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_SP2 0x00000072 1287a26ae754SRob Clark 1288a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_SP3 0x00000073 1289a26ae754SRob Clark 1290a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_SP0 0x00000074 1291a26ae754SRob Clark 1292a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_SP1 0x00000075 1293a26ae754SRob Clark 1294a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_SP2 0x00000076 1295a26ae754SRob Clark 1296a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_SP3 0x00000077 1297a26ae754SRob Clark 1298a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_RB0 0x00000078 1299a26ae754SRob Clark 1300a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_RB1 0x00000079 1301a26ae754SRob Clark 1302a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_RB2 0x0000007a 1303a26ae754SRob Clark 1304a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_RB3 0x0000007b 1305a26ae754SRob Clark 1306a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL2_RB0 0x0000007c 1307a26ae754SRob Clark 1308a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL2_RB1 0x0000007d 1309a26ae754SRob Clark 1310a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL2_RB2 0x0000007e 1311a26ae754SRob Clark 1312a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL2_RB3 0x0000007f 1313a26ae754SRob Clark 1314a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_RAC 0x00000080 1315a26ae754SRob Clark 1316a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_RAC 0x00000081 1317a26ae754SRob Clark 1318a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_CCU0 0x00000082 1319a26ae754SRob Clark 1320a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_CCU1 0x00000083 1321a26ae754SRob Clark 1322a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_CCU2 0x00000084 1323a26ae754SRob Clark 1324a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_CCU3 0x00000085 1325a26ae754SRob Clark 1326a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000086 1327a26ae754SRob Clark 1328a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000087 1329a26ae754SRob Clark 1330a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000088 1331a26ae754SRob Clark 1332a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000089 1333a26ae754SRob Clark 1334a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_RAC 0x0000008a 1335a26ae754SRob Clark 1336a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL2_RAC 0x0000008b 1337a26ae754SRob Clark 1338a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0 0x0000008c 1339a26ae754SRob Clark 1340a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1 0x0000008d 1341a26ae754SRob Clark 1342a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2 0x0000008e 1343a26ae754SRob Clark 1344a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3 0x0000008f 1345a26ae754SRob Clark 1346a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_VFD 0x00000090 1347a26ae754SRob Clark 1348a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_MODE_VFD 0x00000091 1349a26ae754SRob Clark 1350a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_VFD 0x00000092 1351a26ae754SRob Clark 1352a26ae754SRob Clark #define REG_A5XX_RBBM_AHB_CNTL0 0x00000093 1353a26ae754SRob Clark 1354a26ae754SRob Clark #define REG_A5XX_RBBM_AHB_CNTL1 0x00000094 1355a26ae754SRob Clark 1356a26ae754SRob Clark #define REG_A5XX_RBBM_AHB_CNTL2 0x00000095 1357a26ae754SRob Clark 1358a26ae754SRob Clark #define REG_A5XX_RBBM_AHB_CMD 0x00000096 1359a26ae754SRob Clark 1360a26ae754SRob Clark #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11 0x0000009c 1361a26ae754SRob Clark 1362a26ae754SRob Clark #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12 0x0000009d 1363a26ae754SRob Clark 1364a26ae754SRob Clark #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13 0x0000009e 1365a26ae754SRob Clark 1366a26ae754SRob Clark #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14 0x0000009f 1367a26ae754SRob Clark 1368a26ae754SRob Clark #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15 0x000000a0 1369a26ae754SRob Clark 1370a26ae754SRob Clark #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16 0x000000a1 1371a26ae754SRob Clark 1372a26ae754SRob Clark #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17 0x000000a2 1373a26ae754SRob Clark 1374a26ae754SRob Clark #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18 0x000000a3 1375a26ae754SRob Clark 1376a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_TP0 0x000000a4 1377a26ae754SRob Clark 1378a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_TP1 0x000000a5 1379a26ae754SRob Clark 1380a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_TP2 0x000000a6 1381a26ae754SRob Clark 1382a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_TP3 0x000000a7 1383a26ae754SRob Clark 1384a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY2_TP0 0x000000a8 1385a26ae754SRob Clark 1386a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY2_TP1 0x000000a9 1387a26ae754SRob Clark 1388a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY2_TP2 0x000000aa 1389a26ae754SRob Clark 1390a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY2_TP3 0x000000ab 1391a26ae754SRob Clark 1392a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY3_TP0 0x000000ac 1393a26ae754SRob Clark 1394a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY3_TP1 0x000000ad 1395a26ae754SRob Clark 1396a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY3_TP2 0x000000ae 1397a26ae754SRob Clark 1398a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY3_TP3 0x000000af 1399a26ae754SRob Clark 1400a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_TP0 0x000000b0 1401a26ae754SRob Clark 1402a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_TP1 0x000000b1 1403a26ae754SRob Clark 1404a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_TP2 0x000000b2 1405a26ae754SRob Clark 1406a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_TP3 0x000000b3 1407a26ae754SRob Clark 1408a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST2_TP0 0x000000b4 1409a26ae754SRob Clark 1410a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST2_TP1 0x000000b5 1411a26ae754SRob Clark 1412a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST2_TP2 0x000000b6 1413a26ae754SRob Clark 1414a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST2_TP3 0x000000b7 1415a26ae754SRob Clark 1416a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST3_TP0 0x000000b8 1417a26ae754SRob Clark 1418a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST3_TP1 0x000000b9 1419a26ae754SRob Clark 1420a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST3_TP2 0x000000ba 1421a26ae754SRob Clark 1422a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST3_TP3 0x000000bb 1423a26ae754SRob Clark 1424a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_GPMU 0x000000c8 1425a26ae754SRob Clark 1426a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_GPMU 0x000000c9 1427a26ae754SRob Clark 1428a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_GPMU 0x000000ca 1429a26ae754SRob Clark 1430a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_0_LO 0x000003a0 1431a26ae754SRob Clark 1432a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_0_HI 0x000003a1 1433a26ae754SRob Clark 1434a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_1_LO 0x000003a2 1435a26ae754SRob Clark 1436a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_1_HI 0x000003a3 1437a26ae754SRob Clark 1438a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_2_LO 0x000003a4 1439a26ae754SRob Clark 1440a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_2_HI 0x000003a5 1441a26ae754SRob Clark 1442a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_3_LO 0x000003a6 1443a26ae754SRob Clark 1444a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_3_HI 0x000003a7 1445a26ae754SRob Clark 1446a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_4_LO 0x000003a8 1447a26ae754SRob Clark 1448a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_4_HI 0x000003a9 1449a26ae754SRob Clark 1450a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_5_LO 0x000003aa 1451a26ae754SRob Clark 1452a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_5_HI 0x000003ab 1453a26ae754SRob Clark 1454a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_6_LO 0x000003ac 1455a26ae754SRob Clark 1456a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_6_HI 0x000003ad 1457a26ae754SRob Clark 1458a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_7_LO 0x000003ae 1459a26ae754SRob Clark 1460a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_7_HI 0x000003af 1461a26ae754SRob Clark 1462a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RBBM_0_LO 0x000003b0 1463a26ae754SRob Clark 1464a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RBBM_0_HI 0x000003b1 1465a26ae754SRob Clark 1466a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RBBM_1_LO 0x000003b2 1467a26ae754SRob Clark 1468a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RBBM_1_HI 0x000003b3 1469a26ae754SRob Clark 1470a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RBBM_2_LO 0x000003b4 1471a26ae754SRob Clark 1472a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RBBM_2_HI 0x000003b5 1473a26ae754SRob Clark 1474a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RBBM_3_LO 0x000003b6 1475a26ae754SRob Clark 1476a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RBBM_3_HI 0x000003b7 1477a26ae754SRob Clark 1478a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_0_LO 0x000003b8 1479a26ae754SRob Clark 1480a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_0_HI 0x000003b9 1481a26ae754SRob Clark 1482a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_1_LO 0x000003ba 1483a26ae754SRob Clark 1484a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_1_HI 0x000003bb 1485a26ae754SRob Clark 1486a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_2_LO 0x000003bc 1487a26ae754SRob Clark 1488a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_2_HI 0x000003bd 1489a26ae754SRob Clark 1490a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_3_LO 0x000003be 1491a26ae754SRob Clark 1492a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_3_HI 0x000003bf 1493a26ae754SRob Clark 1494a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_4_LO 0x000003c0 1495a26ae754SRob Clark 1496a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_4_HI 0x000003c1 1497a26ae754SRob Clark 1498a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_5_LO 0x000003c2 1499a26ae754SRob Clark 1500a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_5_HI 0x000003c3 1501a26ae754SRob Clark 1502a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_6_LO 0x000003c4 1503a26ae754SRob Clark 1504a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_6_HI 0x000003c5 1505a26ae754SRob Clark 1506a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_7_LO 0x000003c6 1507a26ae754SRob Clark 1508a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_7_HI 0x000003c7 1509a26ae754SRob Clark 1510a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_0_LO 0x000003c8 1511a26ae754SRob Clark 1512a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_0_HI 0x000003c9 1513a26ae754SRob Clark 1514a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_1_LO 0x000003ca 1515a26ae754SRob Clark 1516a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_1_HI 0x000003cb 1517a26ae754SRob Clark 1518a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_2_LO 0x000003cc 1519a26ae754SRob Clark 1520a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_2_HI 0x000003cd 1521a26ae754SRob Clark 1522a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_3_LO 0x000003ce 1523a26ae754SRob Clark 1524a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_3_HI 0x000003cf 1525a26ae754SRob Clark 1526a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_4_LO 0x000003d0 1527a26ae754SRob Clark 1528a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_4_HI 0x000003d1 1529a26ae754SRob Clark 1530a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_5_LO 0x000003d2 1531a26ae754SRob Clark 1532a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_5_HI 0x000003d3 1533a26ae754SRob Clark 1534a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_6_LO 0x000003d4 1535a26ae754SRob Clark 1536a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_6_HI 0x000003d5 1537a26ae754SRob Clark 1538a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_7_LO 0x000003d6 1539a26ae754SRob Clark 1540a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_7_HI 0x000003d7 1541a26ae754SRob Clark 1542a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_LO 0x000003d8 1543a26ae754SRob Clark 1544a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_HI 0x000003d9 1545a26ae754SRob Clark 1546a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_LO 0x000003da 1547a26ae754SRob Clark 1548a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_HI 0x000003db 1549a26ae754SRob Clark 1550a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_LO 0x000003dc 1551a26ae754SRob Clark 1552a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_HI 0x000003dd 1553a26ae754SRob Clark 1554a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_LO 0x000003de 1555a26ae754SRob Clark 1556a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_HI 0x000003df 1557a26ae754SRob Clark 1558a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_LO 0x000003e0 1559a26ae754SRob Clark 1560a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_HI 0x000003e1 1561a26ae754SRob Clark 1562a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_LO 0x000003e2 1563a26ae754SRob Clark 1564a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_HI 0x000003e3 1565a26ae754SRob Clark 1566a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_LO 0x000003e4 1567a26ae754SRob Clark 1568a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_HI 0x000003e5 1569a26ae754SRob Clark 1570a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_LO 0x000003e6 1571a26ae754SRob Clark 1572a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_HI 0x000003e7 1573a26ae754SRob Clark 1574a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VPC_0_LO 0x000003e8 1575a26ae754SRob Clark 1576a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VPC_0_HI 0x000003e9 1577a26ae754SRob Clark 1578a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VPC_1_LO 0x000003ea 1579a26ae754SRob Clark 1580a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VPC_1_HI 0x000003eb 1581a26ae754SRob Clark 1582a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VPC_2_LO 0x000003ec 1583a26ae754SRob Clark 1584a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VPC_2_HI 0x000003ed 1585a26ae754SRob Clark 1586a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VPC_3_LO 0x000003ee 1587a26ae754SRob Clark 1588a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VPC_3_HI 0x000003ef 1589a26ae754SRob Clark 1590a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CCU_0_LO 0x000003f0 1591a26ae754SRob Clark 1592a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CCU_0_HI 0x000003f1 1593a26ae754SRob Clark 1594a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CCU_1_LO 0x000003f2 1595a26ae754SRob Clark 1596a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CCU_1_HI 0x000003f3 1597a26ae754SRob Clark 1598a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CCU_2_LO 0x000003f4 1599a26ae754SRob Clark 1600a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CCU_2_HI 0x000003f5 1601a26ae754SRob Clark 1602a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CCU_3_LO 0x000003f6 1603a26ae754SRob Clark 1604a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CCU_3_HI 0x000003f7 1605a26ae754SRob Clark 1606a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TSE_0_LO 0x000003f8 1607a26ae754SRob Clark 1608a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TSE_0_HI 0x000003f9 1609a26ae754SRob Clark 1610a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TSE_1_LO 0x000003fa 1611a26ae754SRob Clark 1612a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TSE_1_HI 0x000003fb 1613a26ae754SRob Clark 1614a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TSE_2_LO 0x000003fc 1615a26ae754SRob Clark 1616a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TSE_2_HI 0x000003fd 1617a26ae754SRob Clark 1618a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TSE_3_LO 0x000003fe 1619a26ae754SRob Clark 1620a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TSE_3_HI 0x000003ff 1621a26ae754SRob Clark 1622a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RAS_0_LO 0x00000400 1623a26ae754SRob Clark 1624a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RAS_0_HI 0x00000401 1625a26ae754SRob Clark 1626a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RAS_1_LO 0x00000402 1627a26ae754SRob Clark 1628a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RAS_1_HI 0x00000403 1629a26ae754SRob Clark 1630a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RAS_2_LO 0x00000404 1631a26ae754SRob Clark 1632a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RAS_2_HI 0x00000405 1633a26ae754SRob Clark 1634a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RAS_3_LO 0x00000406 1635a26ae754SRob Clark 1636a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RAS_3_HI 0x00000407 1637a26ae754SRob Clark 1638a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_0_LO 0x00000408 1639a26ae754SRob Clark 1640a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_0_HI 0x00000409 1641a26ae754SRob Clark 1642a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_1_LO 0x0000040a 1643a26ae754SRob Clark 1644a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_1_HI 0x0000040b 1645a26ae754SRob Clark 1646a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_2_LO 0x0000040c 1647a26ae754SRob Clark 1648a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_2_HI 0x0000040d 1649a26ae754SRob Clark 1650a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_3_LO 0x0000040e 1651a26ae754SRob Clark 1652a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_3_HI 0x0000040f 1653a26ae754SRob Clark 1654a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_4_LO 0x00000410 1655a26ae754SRob Clark 1656a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_4_HI 0x00000411 1657a26ae754SRob Clark 1658a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_5_LO 0x00000412 1659a26ae754SRob Clark 1660a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_5_HI 0x00000413 1661a26ae754SRob Clark 1662a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_6_LO 0x00000414 1663a26ae754SRob Clark 1664a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_6_HI 0x00000415 1665a26ae754SRob Clark 1666a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_7_LO 0x00000416 1667a26ae754SRob Clark 1668a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_7_HI 0x00000417 1669a26ae754SRob Clark 1670a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_0_LO 0x00000418 1671a26ae754SRob Clark 1672a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_0_HI 0x00000419 1673a26ae754SRob Clark 1674a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_1_LO 0x0000041a 1675a26ae754SRob Clark 1676a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_1_HI 0x0000041b 1677a26ae754SRob Clark 1678a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_2_LO 0x0000041c 1679a26ae754SRob Clark 1680a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_2_HI 0x0000041d 1681a26ae754SRob Clark 1682a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_3_LO 0x0000041e 1683a26ae754SRob Clark 1684a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_3_HI 0x0000041f 1685a26ae754SRob Clark 1686a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_4_LO 0x00000420 1687a26ae754SRob Clark 1688a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_4_HI 0x00000421 1689a26ae754SRob Clark 1690a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_5_LO 0x00000422 1691a26ae754SRob Clark 1692a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_5_HI 0x00000423 1693a26ae754SRob Clark 1694a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_6_LO 0x00000424 1695a26ae754SRob Clark 1696a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_6_HI 0x00000425 1697a26ae754SRob Clark 1698a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_7_LO 0x00000426 1699a26ae754SRob Clark 1700a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_7_HI 0x00000427 1701a26ae754SRob Clark 1702a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_0_LO 0x00000428 1703a26ae754SRob Clark 1704a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_0_HI 0x00000429 1705a26ae754SRob Clark 1706a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_1_LO 0x0000042a 1707a26ae754SRob Clark 1708a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_1_HI 0x0000042b 1709a26ae754SRob Clark 1710a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_2_LO 0x0000042c 1711a26ae754SRob Clark 1712a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_2_HI 0x0000042d 1713a26ae754SRob Clark 1714a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_3_LO 0x0000042e 1715a26ae754SRob Clark 1716a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_3_HI 0x0000042f 1717a26ae754SRob Clark 1718a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_4_LO 0x00000430 1719a26ae754SRob Clark 1720a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_4_HI 0x00000431 1721a26ae754SRob Clark 1722a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_5_LO 0x00000432 1723a26ae754SRob Clark 1724a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_5_HI 0x00000433 1725a26ae754SRob Clark 1726a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_6_LO 0x00000434 1727a26ae754SRob Clark 1728a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_6_HI 0x00000435 1729a26ae754SRob Clark 1730a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_7_LO 0x00000436 1731a26ae754SRob Clark 1732a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_7_HI 0x00000437 1733a26ae754SRob Clark 1734a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_8_LO 0x00000438 1735a26ae754SRob Clark 1736a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_8_HI 0x00000439 1737a26ae754SRob Clark 1738a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_9_LO 0x0000043a 1739a26ae754SRob Clark 1740a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_9_HI 0x0000043b 1741a26ae754SRob Clark 1742a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_10_LO 0x0000043c 1743a26ae754SRob Clark 1744a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_10_HI 0x0000043d 1745a26ae754SRob Clark 1746a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_11_LO 0x0000043e 1747a26ae754SRob Clark 1748a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_11_HI 0x0000043f 1749a26ae754SRob Clark 1750a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_0_LO 0x00000440 1751a26ae754SRob Clark 1752a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_0_HI 0x00000441 1753a26ae754SRob Clark 1754a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_1_LO 0x00000442 1755a26ae754SRob Clark 1756a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_1_HI 0x00000443 1757a26ae754SRob Clark 1758a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_2_LO 0x00000444 1759a26ae754SRob Clark 1760a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_2_HI 0x00000445 1761a26ae754SRob Clark 1762a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_3_LO 0x00000446 1763a26ae754SRob Clark 1764a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_3_HI 0x00000447 1765a26ae754SRob Clark 1766a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_4_LO 0x00000448 1767a26ae754SRob Clark 1768a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_4_HI 0x00000449 1769a26ae754SRob Clark 1770a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_5_LO 0x0000044a 1771a26ae754SRob Clark 1772a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_5_HI 0x0000044b 1773a26ae754SRob Clark 1774a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_6_LO 0x0000044c 1775a26ae754SRob Clark 1776a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_6_HI 0x0000044d 1777a26ae754SRob Clark 1778a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_7_LO 0x0000044e 1779a26ae754SRob Clark 1780a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_7_HI 0x0000044f 1781a26ae754SRob Clark 1782a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VSC_0_LO 0x00000450 1783a26ae754SRob Clark 1784a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VSC_0_HI 0x00000451 1785a26ae754SRob Clark 1786a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VSC_1_LO 0x00000452 1787a26ae754SRob Clark 1788a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VSC_1_HI 0x00000453 1789a26ae754SRob Clark 1790a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_LRZ_0_LO 0x00000454 1791a26ae754SRob Clark 1792a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_LRZ_0_HI 0x00000455 1793a26ae754SRob Clark 1794a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_LRZ_1_LO 0x00000456 1795a26ae754SRob Clark 1796a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_LRZ_1_HI 0x00000457 1797a26ae754SRob Clark 1798a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_LRZ_2_LO 0x00000458 1799a26ae754SRob Clark 1800a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_LRZ_2_HI 0x00000459 1801a26ae754SRob Clark 1802a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_LRZ_3_LO 0x0000045a 1803a26ae754SRob Clark 1804a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_LRZ_3_HI 0x0000045b 1805a26ae754SRob Clark 1806a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CMP_0_LO 0x0000045c 1807a26ae754SRob Clark 1808a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CMP_0_HI 0x0000045d 1809a26ae754SRob Clark 1810a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CMP_1_LO 0x0000045e 1811a26ae754SRob Clark 1812a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CMP_1_HI 0x0000045f 1813a26ae754SRob Clark 1814a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CMP_2_LO 0x00000460 1815a26ae754SRob Clark 1816a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CMP_2_HI 0x00000461 1817a26ae754SRob Clark 1818a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CMP_3_LO 0x00000462 1819a26ae754SRob Clark 1820a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CMP_3_HI 0x00000463 1821a26ae754SRob Clark 1822a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b 1823a26ae754SRob Clark 1824a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c 1825a26ae754SRob Clark 1826a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d 1827a26ae754SRob Clark 1828a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e 1829a26ae754SRob Clark 1830a26ae754SRob Clark #define REG_A5XX_RBBM_ALWAYSON_COUNTER_LO 0x000004d2 1831a26ae754SRob Clark 1832a26ae754SRob Clark #define REG_A5XX_RBBM_ALWAYSON_COUNTER_HI 0x000004d3 1833a26ae754SRob Clark 1834a26ae754SRob Clark #define REG_A5XX_RBBM_STATUS 0x000004f5 1835c28c82e9SRob Clark #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__MASK 0x80000000 1836c28c82e9SRob Clark #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__SHIFT 31 1837c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB(uint32_t val) 1838c28c82e9SRob Clark { 1839c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__MASK; 1840c28c82e9SRob Clark } 1841c28c82e9SRob Clark #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__MASK 0x40000000 1842c28c82e9SRob Clark #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__SHIFT 30 1843c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP(uint32_t val) 1844c28c82e9SRob Clark { 1845c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__MASK; 1846c28c82e9SRob Clark } 1847c28c82e9SRob Clark #define A5XX_RBBM_STATUS_HLSQ_BUSY__MASK 0x20000000 1848c28c82e9SRob Clark #define A5XX_RBBM_STATUS_HLSQ_BUSY__SHIFT 29 1849c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_HLSQ_BUSY(uint32_t val) 1850c28c82e9SRob Clark { 1851c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_HLSQ_BUSY__SHIFT) & A5XX_RBBM_STATUS_HLSQ_BUSY__MASK; 1852c28c82e9SRob Clark } 1853c28c82e9SRob Clark #define A5XX_RBBM_STATUS_VSC_BUSY__MASK 0x10000000 1854c28c82e9SRob Clark #define A5XX_RBBM_STATUS_VSC_BUSY__SHIFT 28 1855c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_VSC_BUSY(uint32_t val) 1856c28c82e9SRob Clark { 1857c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_VSC_BUSY__SHIFT) & A5XX_RBBM_STATUS_VSC_BUSY__MASK; 1858c28c82e9SRob Clark } 1859c28c82e9SRob Clark #define A5XX_RBBM_STATUS_TPL1_BUSY__MASK 0x08000000 1860c28c82e9SRob Clark #define A5XX_RBBM_STATUS_TPL1_BUSY__SHIFT 27 1861c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_TPL1_BUSY(uint32_t val) 1862c28c82e9SRob Clark { 1863c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_TPL1_BUSY__SHIFT) & A5XX_RBBM_STATUS_TPL1_BUSY__MASK; 1864c28c82e9SRob Clark } 1865c28c82e9SRob Clark #define A5XX_RBBM_STATUS_SP_BUSY__MASK 0x04000000 1866c28c82e9SRob Clark #define A5XX_RBBM_STATUS_SP_BUSY__SHIFT 26 1867c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_SP_BUSY(uint32_t val) 1868c28c82e9SRob Clark { 1869c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_SP_BUSY__SHIFT) & A5XX_RBBM_STATUS_SP_BUSY__MASK; 1870c28c82e9SRob Clark } 1871c28c82e9SRob Clark #define A5XX_RBBM_STATUS_UCHE_BUSY__MASK 0x02000000 1872c28c82e9SRob Clark #define A5XX_RBBM_STATUS_UCHE_BUSY__SHIFT 25 1873c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_UCHE_BUSY(uint32_t val) 1874c28c82e9SRob Clark { 1875c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_UCHE_BUSY__SHIFT) & A5XX_RBBM_STATUS_UCHE_BUSY__MASK; 1876c28c82e9SRob Clark } 1877c28c82e9SRob Clark #define A5XX_RBBM_STATUS_VPC_BUSY__MASK 0x01000000 1878c28c82e9SRob Clark #define A5XX_RBBM_STATUS_VPC_BUSY__SHIFT 24 1879c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_VPC_BUSY(uint32_t val) 1880c28c82e9SRob Clark { 1881c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_VPC_BUSY__SHIFT) & A5XX_RBBM_STATUS_VPC_BUSY__MASK; 1882c28c82e9SRob Clark } 1883c28c82e9SRob Clark #define A5XX_RBBM_STATUS_VFDP_BUSY__MASK 0x00800000 1884c28c82e9SRob Clark #define A5XX_RBBM_STATUS_VFDP_BUSY__SHIFT 23 1885c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_VFDP_BUSY(uint32_t val) 1886c28c82e9SRob Clark { 1887c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_VFDP_BUSY__SHIFT) & A5XX_RBBM_STATUS_VFDP_BUSY__MASK; 1888c28c82e9SRob Clark } 1889c28c82e9SRob Clark #define A5XX_RBBM_STATUS_VFD_BUSY__MASK 0x00400000 1890c28c82e9SRob Clark #define A5XX_RBBM_STATUS_VFD_BUSY__SHIFT 22 1891c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_VFD_BUSY(uint32_t val) 1892c28c82e9SRob Clark { 1893c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_VFD_BUSY__SHIFT) & A5XX_RBBM_STATUS_VFD_BUSY__MASK; 1894c28c82e9SRob Clark } 1895c28c82e9SRob Clark #define A5XX_RBBM_STATUS_TESS_BUSY__MASK 0x00200000 1896c28c82e9SRob Clark #define A5XX_RBBM_STATUS_TESS_BUSY__SHIFT 21 1897c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_TESS_BUSY(uint32_t val) 1898c28c82e9SRob Clark { 1899c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_TESS_BUSY__SHIFT) & A5XX_RBBM_STATUS_TESS_BUSY__MASK; 1900c28c82e9SRob Clark } 1901c28c82e9SRob Clark #define A5XX_RBBM_STATUS_PC_VSD_BUSY__MASK 0x00100000 1902c28c82e9SRob Clark #define A5XX_RBBM_STATUS_PC_VSD_BUSY__SHIFT 20 1903c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_PC_VSD_BUSY(uint32_t val) 1904c28c82e9SRob Clark { 1905c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_PC_VSD_BUSY__SHIFT) & A5XX_RBBM_STATUS_PC_VSD_BUSY__MASK; 1906c28c82e9SRob Clark } 1907c28c82e9SRob Clark #define A5XX_RBBM_STATUS_PC_DCALL_BUSY__MASK 0x00080000 1908c28c82e9SRob Clark #define A5XX_RBBM_STATUS_PC_DCALL_BUSY__SHIFT 19 1909c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_PC_DCALL_BUSY(uint32_t val) 1910c28c82e9SRob Clark { 1911c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_PC_DCALL_BUSY__SHIFT) & A5XX_RBBM_STATUS_PC_DCALL_BUSY__MASK; 1912c28c82e9SRob Clark } 1913c28c82e9SRob Clark #define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__MASK 0x00040000 1914c28c82e9SRob Clark #define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__SHIFT 18 1915c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY(uint32_t val) 1916c28c82e9SRob Clark { 1917c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__SHIFT) & A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__MASK; 1918c28c82e9SRob Clark } 1919c28c82e9SRob Clark #define A5XX_RBBM_STATUS_DCOM_BUSY__MASK 0x00020000 1920c28c82e9SRob Clark #define A5XX_RBBM_STATUS_DCOM_BUSY__SHIFT 17 1921c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_DCOM_BUSY(uint32_t val) 1922c28c82e9SRob Clark { 1923c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_DCOM_BUSY__SHIFT) & A5XX_RBBM_STATUS_DCOM_BUSY__MASK; 1924c28c82e9SRob Clark } 1925c28c82e9SRob Clark #define A5XX_RBBM_STATUS_COM_BUSY__MASK 0x00010000 1926c28c82e9SRob Clark #define A5XX_RBBM_STATUS_COM_BUSY__SHIFT 16 1927c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_COM_BUSY(uint32_t val) 1928c28c82e9SRob Clark { 1929c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_COM_BUSY__SHIFT) & A5XX_RBBM_STATUS_COM_BUSY__MASK; 1930c28c82e9SRob Clark } 1931c28c82e9SRob Clark #define A5XX_RBBM_STATUS_LRZ_BUZY__MASK 0x00008000 1932c28c82e9SRob Clark #define A5XX_RBBM_STATUS_LRZ_BUZY__SHIFT 15 1933c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_LRZ_BUZY(uint32_t val) 1934c28c82e9SRob Clark { 1935c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_LRZ_BUZY__SHIFT) & A5XX_RBBM_STATUS_LRZ_BUZY__MASK; 1936c28c82e9SRob Clark } 1937c28c82e9SRob Clark #define A5XX_RBBM_STATUS_A2D_DSP_BUSY__MASK 0x00004000 1938c28c82e9SRob Clark #define A5XX_RBBM_STATUS_A2D_DSP_BUSY__SHIFT 14 1939c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_A2D_DSP_BUSY(uint32_t val) 1940c28c82e9SRob Clark { 1941c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_A2D_DSP_BUSY__SHIFT) & A5XX_RBBM_STATUS_A2D_DSP_BUSY__MASK; 1942c28c82e9SRob Clark } 1943c28c82e9SRob Clark #define A5XX_RBBM_STATUS_CCUFCHE_BUSY__MASK 0x00002000 1944c28c82e9SRob Clark #define A5XX_RBBM_STATUS_CCUFCHE_BUSY__SHIFT 13 1945c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_CCUFCHE_BUSY(uint32_t val) 1946c28c82e9SRob Clark { 1947c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_CCUFCHE_BUSY__SHIFT) & A5XX_RBBM_STATUS_CCUFCHE_BUSY__MASK; 1948c28c82e9SRob Clark } 1949c28c82e9SRob Clark #define A5XX_RBBM_STATUS_RB_BUSY__MASK 0x00001000 1950c28c82e9SRob Clark #define A5XX_RBBM_STATUS_RB_BUSY__SHIFT 12 1951c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_RB_BUSY(uint32_t val) 1952c28c82e9SRob Clark { 1953c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_RB_BUSY__SHIFT) & A5XX_RBBM_STATUS_RB_BUSY__MASK; 1954c28c82e9SRob Clark } 1955c28c82e9SRob Clark #define A5XX_RBBM_STATUS_RAS_BUSY__MASK 0x00000800 1956c28c82e9SRob Clark #define A5XX_RBBM_STATUS_RAS_BUSY__SHIFT 11 1957c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_RAS_BUSY(uint32_t val) 1958c28c82e9SRob Clark { 1959c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_RAS_BUSY__SHIFT) & A5XX_RBBM_STATUS_RAS_BUSY__MASK; 1960c28c82e9SRob Clark } 1961c28c82e9SRob Clark #define A5XX_RBBM_STATUS_TSE_BUSY__MASK 0x00000400 1962c28c82e9SRob Clark #define A5XX_RBBM_STATUS_TSE_BUSY__SHIFT 10 1963c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_TSE_BUSY(uint32_t val) 1964c28c82e9SRob Clark { 1965c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_TSE_BUSY__SHIFT) & A5XX_RBBM_STATUS_TSE_BUSY__MASK; 1966c28c82e9SRob Clark } 1967c28c82e9SRob Clark #define A5XX_RBBM_STATUS_VBIF_BUSY__MASK 0x00000200 1968c28c82e9SRob Clark #define A5XX_RBBM_STATUS_VBIF_BUSY__SHIFT 9 1969c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_VBIF_BUSY(uint32_t val) 1970c28c82e9SRob Clark { 1971c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_VBIF_BUSY__SHIFT) & A5XX_RBBM_STATUS_VBIF_BUSY__MASK; 1972c28c82e9SRob Clark } 1973c28c82e9SRob Clark #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__MASK 0x00000100 1974c28c82e9SRob Clark #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__SHIFT 8 1975c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST(uint32_t val) 1976c28c82e9SRob Clark { 1977c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__MASK; 1978c28c82e9SRob Clark } 1979c28c82e9SRob Clark #define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__MASK 0x00000080 1980c28c82e9SRob Clark #define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__SHIFT 7 1981c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST(uint32_t val) 1982c28c82e9SRob Clark { 1983c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__SHIFT) & A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__MASK; 1984c28c82e9SRob Clark } 1985c28c82e9SRob Clark #define A5XX_RBBM_STATUS_CP_BUSY__MASK 0x00000040 1986c28c82e9SRob Clark #define A5XX_RBBM_STATUS_CP_BUSY__SHIFT 6 1987c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_CP_BUSY(uint32_t val) 1988c28c82e9SRob Clark { 1989c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_CP_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_BUSY__MASK; 1990c28c82e9SRob Clark } 1991c28c82e9SRob Clark #define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__MASK 0x00000020 1992c28c82e9SRob Clark #define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__SHIFT 5 1993c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_GPMU_MASTER_BUSY(uint32_t val) 1994c28c82e9SRob Clark { 1995c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__SHIFT) & A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__MASK; 1996c28c82e9SRob Clark } 1997c28c82e9SRob Clark #define A5XX_RBBM_STATUS_CP_CRASH_BUSY__MASK 0x00000010 1998c28c82e9SRob Clark #define A5XX_RBBM_STATUS_CP_CRASH_BUSY__SHIFT 4 1999c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_CP_CRASH_BUSY(uint32_t val) 2000c28c82e9SRob Clark { 2001c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_CP_CRASH_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_CRASH_BUSY__MASK; 2002c28c82e9SRob Clark } 2003c28c82e9SRob Clark #define A5XX_RBBM_STATUS_CP_ETS_BUSY__MASK 0x00000008 2004c28c82e9SRob Clark #define A5XX_RBBM_STATUS_CP_ETS_BUSY__SHIFT 3 2005c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_CP_ETS_BUSY(uint32_t val) 2006c28c82e9SRob Clark { 2007c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_CP_ETS_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_ETS_BUSY__MASK; 2008c28c82e9SRob Clark } 2009c28c82e9SRob Clark #define A5XX_RBBM_STATUS_CP_PFP_BUSY__MASK 0x00000004 2010c28c82e9SRob Clark #define A5XX_RBBM_STATUS_CP_PFP_BUSY__SHIFT 2 2011c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_CP_PFP_BUSY(uint32_t val) 2012c28c82e9SRob Clark { 2013c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_CP_PFP_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_PFP_BUSY__MASK; 2014c28c82e9SRob Clark } 2015c28c82e9SRob Clark #define A5XX_RBBM_STATUS_CP_ME_BUSY__MASK 0x00000002 2016c28c82e9SRob Clark #define A5XX_RBBM_STATUS_CP_ME_BUSY__SHIFT 1 2017c28c82e9SRob Clark static inline uint32_t A5XX_RBBM_STATUS_CP_ME_BUSY(uint32_t val) 2018c28c82e9SRob Clark { 2019c28c82e9SRob Clark return ((val) << A5XX_RBBM_STATUS_CP_ME_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_ME_BUSY__MASK; 2020c28c82e9SRob Clark } 2021a26ae754SRob Clark #define A5XX_RBBM_STATUS_HI_BUSY 0x00000001 2022a26ae754SRob Clark 2023a26ae754SRob Clark #define REG_A5XX_RBBM_STATUS3 0x00000530 2024*cc4c26d4SRob Clark #define A5XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT 0x01000000 2025a26ae754SRob Clark 2026a26ae754SRob Clark #define REG_A5XX_RBBM_INT_0_STATUS 0x000004e1 2027a26ae754SRob Clark 2028a26ae754SRob Clark #define REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS 0x000004f0 2029a26ae754SRob Clark 2030a26ae754SRob Clark #define REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS 0x000004f1 2031a26ae754SRob Clark 2032a26ae754SRob Clark #define REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS 0x000004f3 2033a26ae754SRob Clark 2034a26ae754SRob Clark #define REG_A5XX_RBBM_AHB_ERROR_STATUS 0x000004f4 2035a26ae754SRob Clark 2036a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CNTL 0x00000464 2037a26ae754SRob Clark 2038a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD0 0x00000465 2039a26ae754SRob Clark 2040a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD1 0x00000466 2041a26ae754SRob Clark 2042a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD2 0x00000467 2043a26ae754SRob Clark 2044a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD3 0x00000468 2045a26ae754SRob Clark 2046a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000469 2047a26ae754SRob Clark 2048a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x0000046a 2049a26ae754SRob Clark 2050a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000046f 2051a26ae754SRob Clark 2052a26ae754SRob Clark #define REG_A5XX_RBBM_AHB_ERROR 0x000004ed 2053a26ae754SRob Clark 2054a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_EVENT_LOGIC 0x00000504 2055a26ae754SRob Clark 2056a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_OVER 0x00000505 2057a26ae754SRob Clark 2058a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT0 0x00000506 2059a26ae754SRob Clark 2060a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT1 0x00000507 2061a26ae754SRob Clark 2062a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT2 0x00000508 2063a26ae754SRob Clark 2064a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT3 0x00000509 2065a26ae754SRob Clark 2066a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT4 0x0000050a 2067a26ae754SRob Clark 2068a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT5 0x0000050b 2069a26ae754SRob Clark 2070a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_ADDR 0x0000050c 2071a26ae754SRob Clark 2072a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF0 0x0000050d 2073a26ae754SRob Clark 2074a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF1 0x0000050e 2075a26ae754SRob Clark 2076a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF2 0x0000050f 2077a26ae754SRob Clark 2078a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF3 0x00000510 2079a26ae754SRob Clark 2080a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF4 0x00000511 2081a26ae754SRob Clark 2082a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_MISR0 0x00000512 2083a26ae754SRob Clark 2084a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_MISR1 0x00000513 2085a26ae754SRob Clark 2086a26ae754SRob Clark #define REG_A5XX_RBBM_ISDB_CNT 0x00000533 2087a26ae754SRob Clark 2088a26ae754SRob Clark #define REG_A5XX_RBBM_SECVID_TRUST_CONFIG 0x0000f000 2089a26ae754SRob Clark 2090a26ae754SRob Clark #define REG_A5XX_RBBM_SECVID_TRUST_CNTL 0x0000f400 2091a26ae754SRob Clark 2092a26ae754SRob Clark #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800 2093a26ae754SRob Clark 2094a26ae754SRob Clark #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801 2095a26ae754SRob Clark 2096a26ae754SRob Clark #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802 2097a26ae754SRob Clark 2098a26ae754SRob Clark #define REG_A5XX_RBBM_SECVID_TSB_CNTL 0x0000f803 2099a26ae754SRob Clark 2100a26ae754SRob Clark #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_LO 0x0000f804 2101a26ae754SRob Clark 2102a26ae754SRob Clark #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_HI 0x0000f805 2103a26ae754SRob Clark 2104a26ae754SRob Clark #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_LO 0x0000f806 2105a26ae754SRob Clark 2106a26ae754SRob Clark #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_HI 0x0000f807 2107a26ae754SRob Clark 2108a26ae754SRob Clark #define REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810 2109a26ae754SRob Clark 211052260ae4SRob Clark #define REG_A5XX_VSC_BIN_SIZE 0x00000bc2 211152260ae4SRob Clark #define A5XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff 211252260ae4SRob Clark #define A5XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 211352260ae4SRob Clark static inline uint32_t A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 211452260ae4SRob Clark { 211552260ae4SRob Clark return ((val >> 5) << A5XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A5XX_VSC_BIN_SIZE_WIDTH__MASK; 211652260ae4SRob Clark } 211752260ae4SRob Clark #define A5XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001fe00 211852260ae4SRob Clark #define A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT 9 211952260ae4SRob Clark static inline uint32_t A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 212052260ae4SRob Clark { 212152260ae4SRob Clark return ((val >> 5) << A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A5XX_VSC_BIN_SIZE_HEIGHT__MASK; 212252260ae4SRob Clark } 212352260ae4SRob Clark 212452260ae4SRob Clark #define REG_A5XX_VSC_SIZE_ADDRESS_LO 0x00000bc3 212552260ae4SRob Clark 212652260ae4SRob Clark #define REG_A5XX_VSC_SIZE_ADDRESS_HI 0x00000bc4 212752260ae4SRob Clark 212852260ae4SRob Clark #define REG_A5XX_UNKNOWN_0BC5 0x00000bc5 212952260ae4SRob Clark 213052260ae4SRob Clark #define REG_A5XX_UNKNOWN_0BC6 0x00000bc6 213152260ae4SRob Clark 213252260ae4SRob Clark static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; } 213352260ae4SRob Clark 213452260ae4SRob Clark static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; } 213552260ae4SRob Clark #define A5XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff 213652260ae4SRob Clark #define A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0 213752260ae4SRob Clark static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) 213852260ae4SRob Clark { 213952260ae4SRob Clark return ((val) << A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_X__MASK; 214052260ae4SRob Clark } 214152260ae4SRob Clark #define A5XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00 214252260ae4SRob Clark #define A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10 214352260ae4SRob Clark static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) 214452260ae4SRob Clark { 214552260ae4SRob Clark return ((val) << A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_Y__MASK; 214652260ae4SRob Clark } 214752260ae4SRob Clark #define A5XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000 214852260ae4SRob Clark #define A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20 214952260ae4SRob Clark static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) 215052260ae4SRob Clark { 215152260ae4SRob Clark return ((val) << A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_W__MASK; 215252260ae4SRob Clark } 215352260ae4SRob Clark #define A5XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000 215452260ae4SRob Clark #define A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24 215552260ae4SRob Clark static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) 215652260ae4SRob Clark { 215752260ae4SRob Clark return ((val) << A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_H__MASK; 215852260ae4SRob Clark } 215952260ae4SRob Clark 216052260ae4SRob Clark static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000be0 + 0x2*i0; } 216152260ae4SRob Clark 216252260ae4SRob Clark static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0) { return 0x00000be0 + 0x2*i0; } 216352260ae4SRob Clark 216452260ae4SRob Clark static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0) { return 0x00000be1 + 0x2*i0; } 216552260ae4SRob Clark 216652260ae4SRob Clark static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c00 + 0x1*i0; } 216752260ae4SRob Clark 216852260ae4SRob Clark static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c00 + 0x1*i0; } 2169a26ae754SRob Clark 2170a26ae754SRob Clark #define REG_A5XX_VSC_PERFCTR_VSC_SEL_0 0x00000c60 2171a26ae754SRob Clark 2172a26ae754SRob Clark #define REG_A5XX_VSC_PERFCTR_VSC_SEL_1 0x00000c61 2173a26ae754SRob Clark 217452260ae4SRob Clark #define REG_A5XX_VSC_RESOLVE_CNTL 0x00000cdd 217552260ae4SRob Clark #define A5XX_VSC_RESOLVE_CNTL_WINDOW_OFFSET_DISABLE 0x80000000 217652260ae4SRob Clark #define A5XX_VSC_RESOLVE_CNTL_X__MASK 0x00007fff 217752260ae4SRob Clark #define A5XX_VSC_RESOLVE_CNTL_X__SHIFT 0 217852260ae4SRob Clark static inline uint32_t A5XX_VSC_RESOLVE_CNTL_X(uint32_t val) 2179a26ae754SRob Clark { 218052260ae4SRob Clark return ((val) << A5XX_VSC_RESOLVE_CNTL_X__SHIFT) & A5XX_VSC_RESOLVE_CNTL_X__MASK; 2181a26ae754SRob Clark } 218252260ae4SRob Clark #define A5XX_VSC_RESOLVE_CNTL_Y__MASK 0x7fff0000 218352260ae4SRob Clark #define A5XX_VSC_RESOLVE_CNTL_Y__SHIFT 16 218452260ae4SRob Clark static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val) 2185a26ae754SRob Clark { 218652260ae4SRob Clark return ((val) << A5XX_VSC_RESOLVE_CNTL_Y__SHIFT) & A5XX_VSC_RESOLVE_CNTL_Y__MASK; 2187a26ae754SRob Clark } 2188a26ae754SRob Clark 2189a26ae754SRob Clark #define REG_A5XX_GRAS_ADDR_MODE_CNTL 0x00000c81 2190a26ae754SRob Clark 2191a26ae754SRob Clark #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c90 2192a26ae754SRob Clark 2193a26ae754SRob Clark #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c91 2194a26ae754SRob Clark 2195a26ae754SRob Clark #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c92 2196a26ae754SRob Clark 2197a26ae754SRob Clark #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c93 2198a26ae754SRob Clark 2199a26ae754SRob Clark #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c94 2200a26ae754SRob Clark 2201a26ae754SRob Clark #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c95 2202a26ae754SRob Clark 2203a26ae754SRob Clark #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c96 2204a26ae754SRob Clark 2205a26ae754SRob Clark #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c97 2206a26ae754SRob Clark 2207a26ae754SRob Clark #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_0 0x00000c98 2208a26ae754SRob Clark 2209a26ae754SRob Clark #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_1 0x00000c99 2210a26ae754SRob Clark 2211a26ae754SRob Clark #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_2 0x00000c9a 2212a26ae754SRob Clark 2213a26ae754SRob Clark #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_3 0x00000c9b 2214a26ae754SRob Clark 2215a26ae754SRob Clark #define REG_A5XX_RB_DBG_ECO_CNTL 0x00000cc4 2216a26ae754SRob Clark 2217a26ae754SRob Clark #define REG_A5XX_RB_ADDR_MODE_CNTL 0x00000cc5 2218a26ae754SRob Clark 2219a26ae754SRob Clark #define REG_A5XX_RB_MODE_CNTL 0x00000cc6 2220a26ae754SRob Clark 2221a26ae754SRob Clark #define REG_A5XX_RB_CCU_CNTL 0x00000cc7 2222a26ae754SRob Clark 2223a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_RB_SEL_0 0x00000cd0 2224a26ae754SRob Clark 2225a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_RB_SEL_1 0x00000cd1 2226a26ae754SRob Clark 2227a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_RB_SEL_2 0x00000cd2 2228a26ae754SRob Clark 2229a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_RB_SEL_3 0x00000cd3 2230a26ae754SRob Clark 2231a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_RB_SEL_4 0x00000cd4 2232a26ae754SRob Clark 2233a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_RB_SEL_5 0x00000cd5 2234a26ae754SRob Clark 2235a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_RB_SEL_6 0x00000cd6 2236a26ae754SRob Clark 2237a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_RB_SEL_7 0x00000cd7 2238a26ae754SRob Clark 2239a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_CCU_SEL_0 0x00000cd8 2240a26ae754SRob Clark 2241a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_CCU_SEL_1 0x00000cd9 2242a26ae754SRob Clark 2243a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_CCU_SEL_2 0x00000cda 2244a26ae754SRob Clark 2245a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_CCU_SEL_3 0x00000cdb 2246a26ae754SRob Clark 2247a26ae754SRob Clark #define REG_A5XX_RB_POWERCTR_RB_SEL_0 0x00000ce0 2248a26ae754SRob Clark 2249a26ae754SRob Clark #define REG_A5XX_RB_POWERCTR_RB_SEL_1 0x00000ce1 2250a26ae754SRob Clark 2251a26ae754SRob Clark #define REG_A5XX_RB_POWERCTR_RB_SEL_2 0x00000ce2 2252a26ae754SRob Clark 2253a26ae754SRob Clark #define REG_A5XX_RB_POWERCTR_RB_SEL_3 0x00000ce3 2254a26ae754SRob Clark 2255a26ae754SRob Clark #define REG_A5XX_RB_POWERCTR_CCU_SEL_0 0x00000ce4 2256a26ae754SRob Clark 2257a26ae754SRob Clark #define REG_A5XX_RB_POWERCTR_CCU_SEL_1 0x00000ce5 2258a26ae754SRob Clark 2259a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_CMP_SEL_0 0x00000cec 2260a26ae754SRob Clark 2261a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_CMP_SEL_1 0x00000ced 2262a26ae754SRob Clark 2263a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_CMP_SEL_2 0x00000cee 2264a26ae754SRob Clark 2265a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_CMP_SEL_3 0x00000cef 2266a26ae754SRob Clark 2267a26ae754SRob Clark #define REG_A5XX_PC_DBG_ECO_CNTL 0x00000d00 2268a26ae754SRob Clark #define A5XX_PC_DBG_ECO_CNTL_TWOPASSUSEWFI 0x00000100 2269a26ae754SRob Clark 2270a26ae754SRob Clark #define REG_A5XX_PC_ADDR_MODE_CNTL 0x00000d01 2271a26ae754SRob Clark 2272a26ae754SRob Clark #define REG_A5XX_PC_MODE_CNTL 0x00000d02 2273a26ae754SRob Clark 22742d756322SRob Clark #define REG_A5XX_PC_INDEX_BUF_LO 0x00000d04 2275a26ae754SRob Clark 22762d756322SRob Clark #define REG_A5XX_PC_INDEX_BUF_HI 0x00000d05 22772d756322SRob Clark 22782d756322SRob Clark #define REG_A5XX_PC_START_INDEX 0x00000d06 22792d756322SRob Clark 22802d756322SRob Clark #define REG_A5XX_PC_MAX_INDEX 0x00000d07 22812d756322SRob Clark 22822d756322SRob Clark #define REG_A5XX_PC_TESSFACTOR_ADDR_LO 0x00000d08 22832d756322SRob Clark 22842d756322SRob Clark #define REG_A5XX_PC_TESSFACTOR_ADDR_HI 0x00000d09 2285a26ae754SRob Clark 2286a26ae754SRob Clark #define REG_A5XX_PC_PERFCTR_PC_SEL_0 0x00000d10 2287a26ae754SRob Clark 2288a26ae754SRob Clark #define REG_A5XX_PC_PERFCTR_PC_SEL_1 0x00000d11 2289a26ae754SRob Clark 2290a26ae754SRob Clark #define REG_A5XX_PC_PERFCTR_PC_SEL_2 0x00000d12 2291a26ae754SRob Clark 2292a26ae754SRob Clark #define REG_A5XX_PC_PERFCTR_PC_SEL_3 0x00000d13 2293a26ae754SRob Clark 2294a26ae754SRob Clark #define REG_A5XX_PC_PERFCTR_PC_SEL_4 0x00000d14 2295a26ae754SRob Clark 2296a26ae754SRob Clark #define REG_A5XX_PC_PERFCTR_PC_SEL_5 0x00000d15 2297a26ae754SRob Clark 2298a26ae754SRob Clark #define REG_A5XX_PC_PERFCTR_PC_SEL_6 0x00000d16 2299a26ae754SRob Clark 2300a26ae754SRob Clark #define REG_A5XX_PC_PERFCTR_PC_SEL_7 0x00000d17 2301a26ae754SRob Clark 2302a26ae754SRob Clark #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0 0x00000e00 2303a26ae754SRob Clark 2304a26ae754SRob Clark #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_1 0x00000e01 2305a26ae754SRob Clark 2306370063eeSJeffrey Hugo #define REG_A5XX_HLSQ_DBG_ECO_CNTL 0x00000e04 2307370063eeSJeffrey Hugo 2308a26ae754SRob Clark #define REG_A5XX_HLSQ_ADDR_MODE_CNTL 0x00000e05 2309a26ae754SRob Clark 2310a26ae754SRob Clark #define REG_A5XX_HLSQ_MODE_CNTL 0x00000e06 2311a26ae754SRob Clark 2312a26ae754SRob Clark #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e10 2313a26ae754SRob Clark 2314a26ae754SRob Clark #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e11 2315a26ae754SRob Clark 2316a26ae754SRob Clark #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e12 2317a26ae754SRob Clark 2318a26ae754SRob Clark #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e13 2319a26ae754SRob Clark 2320a26ae754SRob Clark #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e14 2321a26ae754SRob Clark 2322a26ae754SRob Clark #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e15 2323a26ae754SRob Clark 2324a26ae754SRob Clark #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e16 2325a26ae754SRob Clark 2326a26ae754SRob Clark #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e17 2327a26ae754SRob Clark 2328a26ae754SRob Clark #define REG_A5XX_HLSQ_SPTP_RDSEL 0x00000f08 2329a26ae754SRob Clark 2330a26ae754SRob Clark #define REG_A5XX_HLSQ_DBG_READ_SEL 0x0000bc00 2331a26ae754SRob Clark 2332a26ae754SRob Clark #define REG_A5XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000a000 2333a26ae754SRob Clark 2334a26ae754SRob Clark #define REG_A5XX_VFD_ADDR_MODE_CNTL 0x00000e41 2335a26ae754SRob Clark 2336a26ae754SRob Clark #define REG_A5XX_VFD_MODE_CNTL 0x00000e42 2337a26ae754SRob Clark 2338a26ae754SRob Clark #define REG_A5XX_VFD_PERFCTR_VFD_SEL_0 0x00000e50 2339a26ae754SRob Clark 2340a26ae754SRob Clark #define REG_A5XX_VFD_PERFCTR_VFD_SEL_1 0x00000e51 2341a26ae754SRob Clark 2342a26ae754SRob Clark #define REG_A5XX_VFD_PERFCTR_VFD_SEL_2 0x00000e52 2343a26ae754SRob Clark 2344a26ae754SRob Clark #define REG_A5XX_VFD_PERFCTR_VFD_SEL_3 0x00000e53 2345a26ae754SRob Clark 2346a26ae754SRob Clark #define REG_A5XX_VFD_PERFCTR_VFD_SEL_4 0x00000e54 2347a26ae754SRob Clark 2348a26ae754SRob Clark #define REG_A5XX_VFD_PERFCTR_VFD_SEL_5 0x00000e55 2349a26ae754SRob Clark 2350a26ae754SRob Clark #define REG_A5XX_VFD_PERFCTR_VFD_SEL_6 0x00000e56 2351a26ae754SRob Clark 2352a26ae754SRob Clark #define REG_A5XX_VFD_PERFCTR_VFD_SEL_7 0x00000e57 2353a26ae754SRob Clark 2354a26ae754SRob Clark #define REG_A5XX_VPC_DBG_ECO_CNTL 0x00000e60 2355*cc4c26d4SRob Clark #define A5XX_VPC_DBG_ECO_CNTL_ALLFLATOPTDIS 0x00000400 2356a26ae754SRob Clark 2357a26ae754SRob Clark #define REG_A5XX_VPC_ADDR_MODE_CNTL 0x00000e61 2358a26ae754SRob Clark 2359a26ae754SRob Clark #define REG_A5XX_VPC_MODE_CNTL 0x00000e62 236052260ae4SRob Clark #define A5XX_VPC_MODE_CNTL_BINNING_PASS 0x00000001 2361a26ae754SRob Clark 2362a26ae754SRob Clark #define REG_A5XX_VPC_PERFCTR_VPC_SEL_0 0x00000e64 2363a26ae754SRob Clark 2364a26ae754SRob Clark #define REG_A5XX_VPC_PERFCTR_VPC_SEL_1 0x00000e65 2365a26ae754SRob Clark 2366a26ae754SRob Clark #define REG_A5XX_VPC_PERFCTR_VPC_SEL_2 0x00000e66 2367a26ae754SRob Clark 2368a26ae754SRob Clark #define REG_A5XX_VPC_PERFCTR_VPC_SEL_3 0x00000e67 2369a26ae754SRob Clark 2370a26ae754SRob Clark #define REG_A5XX_UCHE_ADDR_MODE_CNTL 0x00000e80 2371a26ae754SRob Clark 23723f2bc385SKonrad Dybcio #define REG_A5XX_UCHE_MODE_CNTL 0x00000e81 23733f2bc385SKonrad Dybcio 2374a26ae754SRob Clark #define REG_A5XX_UCHE_SVM_CNTL 0x00000e82 2375a26ae754SRob Clark 2376a26ae754SRob Clark #define REG_A5XX_UCHE_WRITE_THRU_BASE_LO 0x00000e87 2377a26ae754SRob Clark 2378a26ae754SRob Clark #define REG_A5XX_UCHE_WRITE_THRU_BASE_HI 0x00000e88 2379a26ae754SRob Clark 2380a26ae754SRob Clark #define REG_A5XX_UCHE_TRAP_BASE_LO 0x00000e89 2381a26ae754SRob Clark 2382a26ae754SRob Clark #define REG_A5XX_UCHE_TRAP_BASE_HI 0x00000e8a 2383a26ae754SRob Clark 2384a26ae754SRob Clark #define REG_A5XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e8b 2385a26ae754SRob Clark 2386a26ae754SRob Clark #define REG_A5XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e8c 2387a26ae754SRob Clark 2388a26ae754SRob Clark #define REG_A5XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e8d 2389a26ae754SRob Clark 2390a26ae754SRob Clark #define REG_A5XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e8e 2391a26ae754SRob Clark 2392a26ae754SRob Clark #define REG_A5XX_UCHE_DBG_ECO_CNTL_2 0x00000e8f 2393a26ae754SRob Clark 2394a26ae754SRob Clark #define REG_A5XX_UCHE_DBG_ECO_CNTL 0x00000e90 2395a26ae754SRob Clark 2396a26ae754SRob Clark #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO 0x00000e91 2397a26ae754SRob Clark 2398a26ae754SRob Clark #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_HI 0x00000e92 2399a26ae754SRob Clark 2400a26ae754SRob Clark #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_LO 0x00000e93 2401a26ae754SRob Clark 2402a26ae754SRob Clark #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_HI 0x00000e94 2403a26ae754SRob Clark 2404a26ae754SRob Clark #define REG_A5XX_UCHE_CACHE_INVALIDATE 0x00000e95 2405a26ae754SRob Clark 2406a26ae754SRob Clark #define REG_A5XX_UCHE_CACHE_WAYS 0x00000e96 2407a26ae754SRob Clark 2408a26ae754SRob Clark #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000ea0 2409a26ae754SRob Clark 2410a26ae754SRob Clark #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000ea1 2411a26ae754SRob Clark 2412a26ae754SRob Clark #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000ea2 2413a26ae754SRob Clark 2414a26ae754SRob Clark #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000ea3 2415a26ae754SRob Clark 2416a26ae754SRob Clark #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000ea4 2417a26ae754SRob Clark 2418a26ae754SRob Clark #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000ea5 2419a26ae754SRob Clark 2420a26ae754SRob Clark #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000ea6 2421a26ae754SRob Clark 2422a26ae754SRob Clark #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000ea7 2423a26ae754SRob Clark 2424a26ae754SRob Clark #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_0 0x00000ea8 2425a26ae754SRob Clark 2426a26ae754SRob Clark #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_1 0x00000ea9 2427a26ae754SRob Clark 2428a26ae754SRob Clark #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_2 0x00000eaa 2429a26ae754SRob Clark 2430a26ae754SRob Clark #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_3 0x00000eab 2431a26ae754SRob Clark 2432a26ae754SRob Clark #define REG_A5XX_UCHE_TRAP_LOG_LO 0x00000eb1 2433a26ae754SRob Clark 2434a26ae754SRob Clark #define REG_A5XX_UCHE_TRAP_LOG_HI 0x00000eb2 2435a26ae754SRob Clark 2436a26ae754SRob Clark #define REG_A5XX_SP_DBG_ECO_CNTL 0x00000ec0 2437a26ae754SRob Clark 2438a26ae754SRob Clark #define REG_A5XX_SP_ADDR_MODE_CNTL 0x00000ec1 2439a26ae754SRob Clark 2440a26ae754SRob Clark #define REG_A5XX_SP_MODE_CNTL 0x00000ec2 2441a26ae754SRob Clark 2442a26ae754SRob Clark #define REG_A5XX_SP_PERFCTR_SP_SEL_0 0x00000ed0 2443a26ae754SRob Clark 2444a26ae754SRob Clark #define REG_A5XX_SP_PERFCTR_SP_SEL_1 0x00000ed1 2445a26ae754SRob Clark 2446a26ae754SRob Clark #define REG_A5XX_SP_PERFCTR_SP_SEL_2 0x00000ed2 2447a26ae754SRob Clark 2448a26ae754SRob Clark #define REG_A5XX_SP_PERFCTR_SP_SEL_3 0x00000ed3 2449a26ae754SRob Clark 2450a26ae754SRob Clark #define REG_A5XX_SP_PERFCTR_SP_SEL_4 0x00000ed4 2451a26ae754SRob Clark 2452a26ae754SRob Clark #define REG_A5XX_SP_PERFCTR_SP_SEL_5 0x00000ed5 2453a26ae754SRob Clark 2454a26ae754SRob Clark #define REG_A5XX_SP_PERFCTR_SP_SEL_6 0x00000ed6 2455a26ae754SRob Clark 2456a26ae754SRob Clark #define REG_A5XX_SP_PERFCTR_SP_SEL_7 0x00000ed7 2457a26ae754SRob Clark 2458a26ae754SRob Clark #define REG_A5XX_SP_PERFCTR_SP_SEL_8 0x00000ed8 2459a26ae754SRob Clark 2460a26ae754SRob Clark #define REG_A5XX_SP_PERFCTR_SP_SEL_9 0x00000ed9 2461a26ae754SRob Clark 2462a26ae754SRob Clark #define REG_A5XX_SP_PERFCTR_SP_SEL_10 0x00000eda 2463a26ae754SRob Clark 2464a26ae754SRob Clark #define REG_A5XX_SP_PERFCTR_SP_SEL_11 0x00000edb 2465a26ae754SRob Clark 2466a26ae754SRob Clark #define REG_A5XX_SP_POWERCTR_SP_SEL_0 0x00000edc 2467a26ae754SRob Clark 2468a26ae754SRob Clark #define REG_A5XX_SP_POWERCTR_SP_SEL_1 0x00000edd 2469a26ae754SRob Clark 2470a26ae754SRob Clark #define REG_A5XX_SP_POWERCTR_SP_SEL_2 0x00000ede 2471a26ae754SRob Clark 2472a26ae754SRob Clark #define REG_A5XX_SP_POWERCTR_SP_SEL_3 0x00000edf 2473a26ae754SRob Clark 2474a26ae754SRob Clark #define REG_A5XX_TPL1_ADDR_MODE_CNTL 0x00000f01 2475a26ae754SRob Clark 2476a26ae754SRob Clark #define REG_A5XX_TPL1_MODE_CNTL 0x00000f02 2477a26ae754SRob Clark 2478a26ae754SRob Clark #define REG_A5XX_TPL1_PERFCTR_TP_SEL_0 0x00000f10 2479a26ae754SRob Clark 2480a26ae754SRob Clark #define REG_A5XX_TPL1_PERFCTR_TP_SEL_1 0x00000f11 2481a26ae754SRob Clark 2482a26ae754SRob Clark #define REG_A5XX_TPL1_PERFCTR_TP_SEL_2 0x00000f12 2483a26ae754SRob Clark 2484a26ae754SRob Clark #define REG_A5XX_TPL1_PERFCTR_TP_SEL_3 0x00000f13 2485a26ae754SRob Clark 2486a26ae754SRob Clark #define REG_A5XX_TPL1_PERFCTR_TP_SEL_4 0x00000f14 2487a26ae754SRob Clark 2488a26ae754SRob Clark #define REG_A5XX_TPL1_PERFCTR_TP_SEL_5 0x00000f15 2489a26ae754SRob Clark 2490a26ae754SRob Clark #define REG_A5XX_TPL1_PERFCTR_TP_SEL_6 0x00000f16 2491a26ae754SRob Clark 2492a26ae754SRob Clark #define REG_A5XX_TPL1_PERFCTR_TP_SEL_7 0x00000f17 2493a26ae754SRob Clark 2494a26ae754SRob Clark #define REG_A5XX_TPL1_POWERCTR_TP_SEL_0 0x00000f18 2495a26ae754SRob Clark 2496a26ae754SRob Clark #define REG_A5XX_TPL1_POWERCTR_TP_SEL_1 0x00000f19 2497a26ae754SRob Clark 2498a26ae754SRob Clark #define REG_A5XX_TPL1_POWERCTR_TP_SEL_2 0x00000f1a 2499a26ae754SRob Clark 2500a26ae754SRob Clark #define REG_A5XX_TPL1_POWERCTR_TP_SEL_3 0x00000f1b 2501a26ae754SRob Clark 2502a26ae754SRob Clark #define REG_A5XX_VBIF_VERSION 0x00003000 2503a26ae754SRob Clark 2504a26ae754SRob Clark #define REG_A5XX_VBIF_CLKON 0x00003001 2505a26ae754SRob Clark 2506a26ae754SRob Clark #define REG_A5XX_VBIF_ABIT_SORT 0x00003028 2507a26ae754SRob Clark 2508a26ae754SRob Clark #define REG_A5XX_VBIF_ABIT_SORT_CONF 0x00003029 2509a26ae754SRob Clark 2510a26ae754SRob Clark #define REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049 2511a26ae754SRob Clark 2512a26ae754SRob Clark #define REG_A5XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 2513a26ae754SRob Clark 2514a26ae754SRob Clark #define REG_A5XX_VBIF_IN_RD_LIM_CONF0 0x0000302c 2515a26ae754SRob Clark 2516a26ae754SRob Clark #define REG_A5XX_VBIF_IN_RD_LIM_CONF1 0x0000302d 2517a26ae754SRob Clark 2518a26ae754SRob Clark #define REG_A5XX_VBIF_XIN_HALT_CTRL0 0x00003080 2519a26ae754SRob Clark 2520a26ae754SRob Clark #define REG_A5XX_VBIF_XIN_HALT_CTRL1 0x00003081 2521a26ae754SRob Clark 2522a26ae754SRob Clark #define REG_A5XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084 2523a26ae754SRob Clark 2524a26ae754SRob Clark #define REG_A5XX_VBIF_TEST_BUS1_CTRL0 0x00003085 2525a26ae754SRob Clark 2526a26ae754SRob Clark #define REG_A5XX_VBIF_TEST_BUS1_CTRL1 0x00003086 2527a26ae754SRob Clark 2528a26ae754SRob Clark #define REG_A5XX_VBIF_TEST_BUS2_CTRL0 0x00003087 2529a26ae754SRob Clark 2530a26ae754SRob Clark #define REG_A5XX_VBIF_TEST_BUS2_CTRL1 0x00003088 2531a26ae754SRob Clark 2532a26ae754SRob Clark #define REG_A5XX_VBIF_TEST_BUS_OUT 0x0000308c 2533a26ae754SRob Clark 253452260ae4SRob Clark #define REG_A5XX_VBIF_PERF_CNT_EN0 0x000030c0 253552260ae4SRob Clark 253652260ae4SRob Clark #define REG_A5XX_VBIF_PERF_CNT_EN1 0x000030c1 253752260ae4SRob Clark 253852260ae4SRob Clark #define REG_A5XX_VBIF_PERF_CNT_EN2 0x000030c2 253952260ae4SRob Clark 254052260ae4SRob Clark #define REG_A5XX_VBIF_PERF_CNT_EN3 0x000030c3 254152260ae4SRob Clark 25422d756322SRob Clark #define REG_A5XX_VBIF_PERF_CNT_CLR0 0x000030c8 25432d756322SRob Clark 25442d756322SRob Clark #define REG_A5XX_VBIF_PERF_CNT_CLR1 0x000030c9 25452d756322SRob Clark 25462d756322SRob Clark #define REG_A5XX_VBIF_PERF_CNT_CLR2 0x000030ca 25472d756322SRob Clark 25482d756322SRob Clark #define REG_A5XX_VBIF_PERF_CNT_CLR3 0x000030cb 25492d756322SRob Clark 2550a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_CNT_SEL0 0x000030d0 2551a26ae754SRob Clark 2552a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_CNT_SEL1 0x000030d1 2553a26ae754SRob Clark 2554a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_CNT_SEL2 0x000030d2 2555a26ae754SRob Clark 2556a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_CNT_SEL3 0x000030d3 2557a26ae754SRob Clark 2558a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_CNT_LOW0 0x000030d8 2559a26ae754SRob Clark 2560a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_CNT_LOW1 0x000030d9 2561a26ae754SRob Clark 2562a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_CNT_LOW2 0x000030da 2563a26ae754SRob Clark 2564a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_CNT_LOW3 0x000030db 2565a26ae754SRob Clark 2566a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_CNT_HIGH0 0x000030e0 2567a26ae754SRob Clark 2568a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_CNT_HIGH1 0x000030e1 2569a26ae754SRob Clark 2570a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_CNT_HIGH2 0x000030e2 2571a26ae754SRob Clark 2572a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_CNT_HIGH3 0x000030e3 2573a26ae754SRob Clark 2574a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_PWR_CNT_EN0 0x00003100 2575a26ae754SRob Clark 2576a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_PWR_CNT_EN1 0x00003101 2577a26ae754SRob Clark 2578a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_PWR_CNT_EN2 0x00003102 2579a26ae754SRob Clark 2580a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110 2581a26ae754SRob Clark 2582a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111 2583a26ae754SRob Clark 2584a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112 2585a26ae754SRob Clark 2586a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118 2587a26ae754SRob Clark 2588a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119 2589a26ae754SRob Clark 2590a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a 2591a26ae754SRob Clark 2592a26ae754SRob Clark #define REG_A5XX_GPMU_INST_RAM_BASE 0x00008800 2593a26ae754SRob Clark 2594a26ae754SRob Clark #define REG_A5XX_GPMU_DATA_RAM_BASE 0x00009800 2595a26ae754SRob Clark 2596a26ae754SRob Clark #define REG_A5XX_GPMU_SP_POWER_CNTL 0x0000a881 2597a26ae754SRob Clark 2598a26ae754SRob Clark #define REG_A5XX_GPMU_RBCCU_CLOCK_CNTL 0x0000a886 2599a26ae754SRob Clark 2600a26ae754SRob Clark #define REG_A5XX_GPMU_RBCCU_POWER_CNTL 0x0000a887 2601a26ae754SRob Clark 2602a26ae754SRob Clark #define REG_A5XX_GPMU_SP_PWR_CLK_STATUS 0x0000a88b 2603a26ae754SRob Clark #define A5XX_GPMU_SP_PWR_CLK_STATUS_PWR_ON 0x00100000 2604a26ae754SRob Clark 2605a26ae754SRob Clark #define REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS 0x0000a88d 2606a26ae754SRob Clark #define A5XX_GPMU_RBCCU_PWR_CLK_STATUS_PWR_ON 0x00100000 2607a26ae754SRob Clark 2608a26ae754SRob Clark #define REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY 0x0000a891 2609a26ae754SRob Clark 2610a26ae754SRob Clark #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL 0x0000a892 2611a26ae754SRob Clark 2612a26ae754SRob Clark #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST 0x0000a893 2613a26ae754SRob Clark 2614a26ae754SRob Clark #define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL 0x0000a894 2615a26ae754SRob Clark 2616a26ae754SRob Clark #define REG_A5XX_GPMU_WFI_CONFIG 0x0000a8c1 2617a26ae754SRob Clark 2618a26ae754SRob Clark #define REG_A5XX_GPMU_RBBM_INTR_INFO 0x0000a8d6 2619a26ae754SRob Clark 2620a26ae754SRob Clark #define REG_A5XX_GPMU_CM3_SYSRESET 0x0000a8d8 2621a26ae754SRob Clark 2622a26ae754SRob Clark #define REG_A5XX_GPMU_GENERAL_0 0x0000a8e0 2623a26ae754SRob Clark 2624a26ae754SRob Clark #define REG_A5XX_GPMU_GENERAL_1 0x0000a8e1 2625a26ae754SRob Clark 2626a26ae754SRob Clark #define REG_A5XX_SP_POWER_COUNTER_0_LO 0x0000a840 2627a26ae754SRob Clark 2628a26ae754SRob Clark #define REG_A5XX_SP_POWER_COUNTER_0_HI 0x0000a841 2629a26ae754SRob Clark 2630a26ae754SRob Clark #define REG_A5XX_SP_POWER_COUNTER_1_LO 0x0000a842 2631a26ae754SRob Clark 2632a26ae754SRob Clark #define REG_A5XX_SP_POWER_COUNTER_1_HI 0x0000a843 2633a26ae754SRob Clark 2634a26ae754SRob Clark #define REG_A5XX_SP_POWER_COUNTER_2_LO 0x0000a844 2635a26ae754SRob Clark 2636a26ae754SRob Clark #define REG_A5XX_SP_POWER_COUNTER_2_HI 0x0000a845 2637a26ae754SRob Clark 2638a26ae754SRob Clark #define REG_A5XX_SP_POWER_COUNTER_3_LO 0x0000a846 2639a26ae754SRob Clark 2640a26ae754SRob Clark #define REG_A5XX_SP_POWER_COUNTER_3_HI 0x0000a847 2641a26ae754SRob Clark 2642a26ae754SRob Clark #define REG_A5XX_TP_POWER_COUNTER_0_LO 0x0000a848 2643a26ae754SRob Clark 2644a26ae754SRob Clark #define REG_A5XX_TP_POWER_COUNTER_0_HI 0x0000a849 2645a26ae754SRob Clark 2646a26ae754SRob Clark #define REG_A5XX_TP_POWER_COUNTER_1_LO 0x0000a84a 2647a26ae754SRob Clark 2648a26ae754SRob Clark #define REG_A5XX_TP_POWER_COUNTER_1_HI 0x0000a84b 2649a26ae754SRob Clark 2650a26ae754SRob Clark #define REG_A5XX_TP_POWER_COUNTER_2_LO 0x0000a84c 2651a26ae754SRob Clark 2652a26ae754SRob Clark #define REG_A5XX_TP_POWER_COUNTER_2_HI 0x0000a84d 2653a26ae754SRob Clark 2654a26ae754SRob Clark #define REG_A5XX_TP_POWER_COUNTER_3_LO 0x0000a84e 2655a26ae754SRob Clark 2656a26ae754SRob Clark #define REG_A5XX_TP_POWER_COUNTER_3_HI 0x0000a84f 2657a26ae754SRob Clark 2658a26ae754SRob Clark #define REG_A5XX_RB_POWER_COUNTER_0_LO 0x0000a850 2659a26ae754SRob Clark 2660a26ae754SRob Clark #define REG_A5XX_RB_POWER_COUNTER_0_HI 0x0000a851 2661a26ae754SRob Clark 2662a26ae754SRob Clark #define REG_A5XX_RB_POWER_COUNTER_1_LO 0x0000a852 2663a26ae754SRob Clark 2664a26ae754SRob Clark #define REG_A5XX_RB_POWER_COUNTER_1_HI 0x0000a853 2665a26ae754SRob Clark 2666a26ae754SRob Clark #define REG_A5XX_RB_POWER_COUNTER_2_LO 0x0000a854 2667a26ae754SRob Clark 2668a26ae754SRob Clark #define REG_A5XX_RB_POWER_COUNTER_2_HI 0x0000a855 2669a26ae754SRob Clark 2670a26ae754SRob Clark #define REG_A5XX_RB_POWER_COUNTER_3_LO 0x0000a856 2671a26ae754SRob Clark 2672a26ae754SRob Clark #define REG_A5XX_RB_POWER_COUNTER_3_HI 0x0000a857 2673a26ae754SRob Clark 2674a26ae754SRob Clark #define REG_A5XX_CCU_POWER_COUNTER_0_LO 0x0000a858 2675a26ae754SRob Clark 2676a26ae754SRob Clark #define REG_A5XX_CCU_POWER_COUNTER_0_HI 0x0000a859 2677a26ae754SRob Clark 2678a26ae754SRob Clark #define REG_A5XX_CCU_POWER_COUNTER_1_LO 0x0000a85a 2679a26ae754SRob Clark 2680a26ae754SRob Clark #define REG_A5XX_CCU_POWER_COUNTER_1_HI 0x0000a85b 2681a26ae754SRob Clark 2682a26ae754SRob Clark #define REG_A5XX_UCHE_POWER_COUNTER_0_LO 0x0000a85c 2683a26ae754SRob Clark 2684a26ae754SRob Clark #define REG_A5XX_UCHE_POWER_COUNTER_0_HI 0x0000a85d 2685a26ae754SRob Clark 2686a26ae754SRob Clark #define REG_A5XX_UCHE_POWER_COUNTER_1_LO 0x0000a85e 2687a26ae754SRob Clark 2688a26ae754SRob Clark #define REG_A5XX_UCHE_POWER_COUNTER_1_HI 0x0000a85f 2689a26ae754SRob Clark 2690a26ae754SRob Clark #define REG_A5XX_UCHE_POWER_COUNTER_2_LO 0x0000a860 2691a26ae754SRob Clark 2692a26ae754SRob Clark #define REG_A5XX_UCHE_POWER_COUNTER_2_HI 0x0000a861 2693a26ae754SRob Clark 2694a26ae754SRob Clark #define REG_A5XX_UCHE_POWER_COUNTER_3_LO 0x0000a862 2695a26ae754SRob Clark 2696a26ae754SRob Clark #define REG_A5XX_UCHE_POWER_COUNTER_3_HI 0x0000a863 2697a26ae754SRob Clark 2698a26ae754SRob Clark #define REG_A5XX_CP_POWER_COUNTER_0_LO 0x0000a864 2699a26ae754SRob Clark 2700a26ae754SRob Clark #define REG_A5XX_CP_POWER_COUNTER_0_HI 0x0000a865 2701a26ae754SRob Clark 2702a26ae754SRob Clark #define REG_A5XX_CP_POWER_COUNTER_1_LO 0x0000a866 2703a26ae754SRob Clark 2704a26ae754SRob Clark #define REG_A5XX_CP_POWER_COUNTER_1_HI 0x0000a867 2705a26ae754SRob Clark 2706a26ae754SRob Clark #define REG_A5XX_CP_POWER_COUNTER_2_LO 0x0000a868 2707a26ae754SRob Clark 2708a26ae754SRob Clark #define REG_A5XX_CP_POWER_COUNTER_2_HI 0x0000a869 2709a26ae754SRob Clark 2710a26ae754SRob Clark #define REG_A5XX_CP_POWER_COUNTER_3_LO 0x0000a86a 2711a26ae754SRob Clark 2712a26ae754SRob Clark #define REG_A5XX_CP_POWER_COUNTER_3_HI 0x0000a86b 2713a26ae754SRob Clark 2714a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_0_LO 0x0000a86c 2715a26ae754SRob Clark 2716a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_0_HI 0x0000a86d 2717a26ae754SRob Clark 2718a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_1_LO 0x0000a86e 2719a26ae754SRob Clark 2720a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_1_HI 0x0000a86f 2721a26ae754SRob Clark 2722a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_2_LO 0x0000a870 2723a26ae754SRob Clark 2724a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_2_HI 0x0000a871 2725a26ae754SRob Clark 2726a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_3_LO 0x0000a872 2727a26ae754SRob Clark 2728a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_3_HI 0x0000a873 2729a26ae754SRob Clark 2730a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_4_LO 0x0000a874 2731a26ae754SRob Clark 2732a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_4_HI 0x0000a875 2733a26ae754SRob Clark 2734a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_5_LO 0x0000a876 2735a26ae754SRob Clark 2736a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_5_HI 0x0000a877 2737a26ae754SRob Clark 2738a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_ENABLE 0x0000a878 2739a26ae754SRob Clark 2740a26ae754SRob Clark #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_LO 0x0000a879 2741a26ae754SRob Clark 2742a26ae754SRob Clark #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_HI 0x0000a87a 2743a26ae754SRob Clark 2744a26ae754SRob Clark #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_RESET 0x0000a87b 2745a26ae754SRob Clark 2746a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_0 0x0000a87c 2747a26ae754SRob Clark 2748a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_1 0x0000a87d 2749a26ae754SRob Clark 2750a26ae754SRob Clark #define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3 2751a26ae754SRob Clark 2752a26ae754SRob Clark #define REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL 0x0000a8a8 2753a26ae754SRob Clark 2754a26ae754SRob Clark #define REG_A5XX_GPMU_TEMP_SENSOR_ID 0x0000ac00 2755a26ae754SRob Clark 2756a26ae754SRob Clark #define REG_A5XX_GPMU_TEMP_SENSOR_CONFIG 0x0000ac01 2757a26ae754SRob Clark 2758a26ae754SRob Clark #define REG_A5XX_GPMU_TEMP_VAL 0x0000ac02 2759a26ae754SRob Clark 2760a26ae754SRob Clark #define REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD 0x0000ac03 2761a26ae754SRob Clark 2762a26ae754SRob Clark #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_STATUS 0x0000ac05 2763a26ae754SRob Clark 2764a26ae754SRob Clark #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK 0x0000ac06 2765a26ae754SRob Clark 2766a26ae754SRob Clark #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_0_1 0x0000ac40 2767a26ae754SRob Clark 2768a26ae754SRob Clark #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_2_3 0x0000ac41 2769a26ae754SRob Clark 2770a26ae754SRob Clark #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_0_1 0x0000ac42 2771a26ae754SRob Clark 2772a26ae754SRob Clark #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_2_3 0x0000ac43 2773a26ae754SRob Clark 2774a26ae754SRob Clark #define REG_A5XX_GPMU_BASE_LEAKAGE 0x0000ac46 2775a26ae754SRob Clark 2776a26ae754SRob Clark #define REG_A5XX_GPMU_GPMU_VOLTAGE 0x0000ac60 2777a26ae754SRob Clark 2778a26ae754SRob Clark #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_STATUS 0x0000ac61 2779a26ae754SRob Clark 2780a26ae754SRob Clark #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK 0x0000ac62 2781a26ae754SRob Clark 2782a26ae754SRob Clark #define REG_A5XX_GPMU_GPMU_PWR_THRESHOLD 0x0000ac80 2783a26ae754SRob Clark 2784a26ae754SRob Clark #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL 0x0000acc4 2785a26ae754SRob Clark 2786a26ae754SRob Clark #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_STATUS 0x0000acc5 2787a26ae754SRob Clark 2788a26ae754SRob Clark #define REG_A5XX_GDPM_CONFIG1 0x0000b80c 2789a26ae754SRob Clark 2790a26ae754SRob Clark #define REG_A5XX_GDPM_CONFIG2 0x0000b80d 2791a26ae754SRob Clark 2792a26ae754SRob Clark #define REG_A5XX_GDPM_INT_EN 0x0000b80f 2793a26ae754SRob Clark 2794a26ae754SRob Clark #define REG_A5XX_GDPM_INT_MASK 0x0000b811 2795a26ae754SRob Clark 2796a26ae754SRob Clark #define REG_A5XX_GPMU_BEC_ENABLE 0x0000b9a0 2797a26ae754SRob Clark 2798a26ae754SRob Clark #define REG_A5XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000c41a 2799a26ae754SRob Clark 2800a26ae754SRob Clark #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 0x0000c41d 2801a26ae754SRob Clark 2802a26ae754SRob Clark #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 0x0000c41f 2803a26ae754SRob Clark 2804a26ae754SRob Clark #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 0x0000c421 2805a26ae754SRob Clark 2806a26ae754SRob Clark #define REG_A5XX_GPU_CS_ENABLE_REG 0x0000c520 2807a26ae754SRob Clark 2808a26ae754SRob Clark #define REG_A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x0000c557 2809a26ae754SRob Clark 2810a26ae754SRob Clark #define REG_A5XX_GRAS_CL_CNTL 0x0000e000 28112d756322SRob Clark #define A5XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040 2812a26ae754SRob Clark 2813*cc4c26d4SRob Clark #define REG_A5XX_GRAS_VS_CL_CNTL 0x0000e001 2814*cc4c26d4SRob Clark #define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK 0x000000ff 2815*cc4c26d4SRob Clark #define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT 0 2816*cc4c26d4SRob Clark static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val) 2817*cc4c26d4SRob Clark { 2818*cc4c26d4SRob Clark return ((val) << A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK; 2819*cc4c26d4SRob Clark } 2820*cc4c26d4SRob Clark #define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK 0x0000ff00 2821*cc4c26d4SRob Clark #define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT 8 2822*cc4c26d4SRob Clark static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val) 2823*cc4c26d4SRob Clark { 2824*cc4c26d4SRob Clark return ((val) << A5XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A5XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK; 2825*cc4c26d4SRob Clark } 2826a26ae754SRob Clark 2827a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E004 0x0000e004 2828a26ae754SRob Clark 2829a26ae754SRob Clark #define REG_A5XX_GRAS_CNTL 0x0000e005 2830c28c82e9SRob Clark #define A5XX_GRAS_CNTL_IJ_PERSP_PIXEL 0x00000001 2831c28c82e9SRob Clark #define A5XX_GRAS_CNTL_IJ_PERSP_CENTROID 0x00000002 2832c28c82e9SRob Clark #define A5XX_GRAS_CNTL_IJ_PERSP_SAMPLE 0x00000004 2833c28c82e9SRob Clark #define A5XX_GRAS_CNTL_SIZE 0x00000008 2834c28c82e9SRob Clark #define A5XX_GRAS_CNTL_COORD_MASK__MASK 0x000003c0 2835c28c82e9SRob Clark #define A5XX_GRAS_CNTL_COORD_MASK__SHIFT 6 2836c28c82e9SRob Clark static inline uint32_t A5XX_GRAS_CNTL_COORD_MASK(uint32_t val) 2837c28c82e9SRob Clark { 2838c28c82e9SRob Clark return ((val) << A5XX_GRAS_CNTL_COORD_MASK__SHIFT) & A5XX_GRAS_CNTL_COORD_MASK__MASK; 2839c28c82e9SRob Clark } 2840a26ae754SRob Clark 2841a26ae754SRob Clark #define REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x0000e006 2842a26ae754SRob Clark #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff 2843a26ae754SRob Clark #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0 2844a26ae754SRob Clark static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val) 2845a26ae754SRob Clark { 2846a26ae754SRob Clark return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK; 2847a26ae754SRob Clark } 2848a26ae754SRob Clark #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x000ffc00 2849a26ae754SRob Clark #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10 2850a26ae754SRob Clark static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) 2851a26ae754SRob Clark { 2852a26ae754SRob Clark return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK; 2853a26ae754SRob Clark } 2854a26ae754SRob Clark 2855a26ae754SRob Clark #define REG_A5XX_GRAS_CL_VPORT_XOFFSET_0 0x0000e010 2856a26ae754SRob Clark #define A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff 2857a26ae754SRob Clark #define A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0 2858a26ae754SRob Clark static inline uint32_t A5XX_GRAS_CL_VPORT_XOFFSET_0(float val) 2859a26ae754SRob Clark { 2860a26ae754SRob Clark return ((fui(val)) << A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK; 2861a26ae754SRob Clark } 2862a26ae754SRob Clark 2863a26ae754SRob Clark #define REG_A5XX_GRAS_CL_VPORT_XSCALE_0 0x0000e011 2864a26ae754SRob Clark #define A5XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff 2865a26ae754SRob Clark #define A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0 2866a26ae754SRob Clark static inline uint32_t A5XX_GRAS_CL_VPORT_XSCALE_0(float val) 2867a26ae754SRob Clark { 2868a26ae754SRob Clark return ((fui(val)) << A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_XSCALE_0__MASK; 2869a26ae754SRob Clark } 2870a26ae754SRob Clark 2871a26ae754SRob Clark #define REG_A5XX_GRAS_CL_VPORT_YOFFSET_0 0x0000e012 2872a26ae754SRob Clark #define A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff 2873a26ae754SRob Clark #define A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0 2874a26ae754SRob Clark static inline uint32_t A5XX_GRAS_CL_VPORT_YOFFSET_0(float val) 2875a26ae754SRob Clark { 2876a26ae754SRob Clark return ((fui(val)) << A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK; 2877a26ae754SRob Clark } 2878a26ae754SRob Clark 2879a26ae754SRob Clark #define REG_A5XX_GRAS_CL_VPORT_YSCALE_0 0x0000e013 2880a26ae754SRob Clark #define A5XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff 2881a26ae754SRob Clark #define A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0 2882a26ae754SRob Clark static inline uint32_t A5XX_GRAS_CL_VPORT_YSCALE_0(float val) 2883a26ae754SRob Clark { 2884a26ae754SRob Clark return ((fui(val)) << A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_YSCALE_0__MASK; 2885a26ae754SRob Clark } 2886a26ae754SRob Clark 2887a26ae754SRob Clark #define REG_A5XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000e014 2888a26ae754SRob Clark #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff 2889a26ae754SRob Clark #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0 2890a26ae754SRob Clark static inline uint32_t A5XX_GRAS_CL_VPORT_ZOFFSET_0(float val) 2891a26ae754SRob Clark { 2892a26ae754SRob Clark return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK; 2893a26ae754SRob Clark } 2894a26ae754SRob Clark 2895a26ae754SRob Clark #define REG_A5XX_GRAS_CL_VPORT_ZSCALE_0 0x0000e015 2896a26ae754SRob Clark #define A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff 2897a26ae754SRob Clark #define A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0 2898a26ae754SRob Clark static inline uint32_t A5XX_GRAS_CL_VPORT_ZSCALE_0(float val) 2899a26ae754SRob Clark { 2900a26ae754SRob Clark return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK; 2901a26ae754SRob Clark } 2902a26ae754SRob Clark 2903a26ae754SRob Clark #define REG_A5XX_GRAS_SU_CNTL 0x0000e090 290452260ae4SRob Clark #define A5XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001 290552260ae4SRob Clark #define A5XX_GRAS_SU_CNTL_CULL_BACK 0x00000002 2906a26ae754SRob Clark #define A5XX_GRAS_SU_CNTL_FRONT_CW 0x00000004 2907a26ae754SRob Clark #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8 2908a26ae754SRob Clark #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3 2909a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) 2910a26ae754SRob Clark { 2911a26ae754SRob Clark return ((((int32_t)(val * 4.0))) << A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK; 2912a26ae754SRob Clark } 2913a26ae754SRob Clark #define A5XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800 2914a26ae754SRob Clark #define A5XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000 2915a26ae754SRob Clark 2916a26ae754SRob Clark #define REG_A5XX_GRAS_SU_POINT_MINMAX 0x0000e091 2917a26ae754SRob Clark #define A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 2918a26ae754SRob Clark #define A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 2919a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MIN(float val) 2920a26ae754SRob Clark { 2921a26ae754SRob Clark return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 2922a26ae754SRob Clark } 2923a26ae754SRob Clark #define A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 2924a26ae754SRob Clark #define A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 2925a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MAX(float val) 2926a26ae754SRob Clark { 2927a26ae754SRob Clark return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 2928a26ae754SRob Clark } 2929a26ae754SRob Clark 2930a26ae754SRob Clark #define REG_A5XX_GRAS_SU_POINT_SIZE 0x0000e092 2931a26ae754SRob Clark #define A5XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff 2932a26ae754SRob Clark #define A5XX_GRAS_SU_POINT_SIZE__SHIFT 0 2933a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SU_POINT_SIZE(float val) 2934a26ae754SRob Clark { 2935a26ae754SRob Clark return ((((int32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_SIZE__SHIFT) & A5XX_GRAS_SU_POINT_SIZE__MASK; 2936a26ae754SRob Clark } 2937a26ae754SRob Clark 29382d756322SRob Clark #define REG_A5XX_GRAS_SU_LAYERED 0x0000e093 2939a26ae754SRob Clark 2940a26ae754SRob Clark #define REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL 0x0000e094 294152260ae4SRob Clark #define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001 294252260ae4SRob Clark #define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1 0x00000002 2943a26ae754SRob Clark 2944a26ae754SRob Clark #define REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000e095 2945a26ae754SRob Clark #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff 2946a26ae754SRob Clark #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 2947a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_SCALE(float val) 2948a26ae754SRob Clark { 2949a26ae754SRob Clark return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; 2950a26ae754SRob Clark } 2951a26ae754SRob Clark 2952a26ae754SRob Clark #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000e096 2953a26ae754SRob Clark #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 2954a26ae754SRob Clark #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 2955a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 2956a26ae754SRob Clark { 2957a26ae754SRob Clark return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 2958a26ae754SRob Clark } 2959a26ae754SRob Clark 2960a26ae754SRob Clark #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x0000e097 2961a26ae754SRob Clark #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff 2962a26ae754SRob Clark #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0 2963a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val) 2964a26ae754SRob Clark { 2965a26ae754SRob Clark return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK; 2966a26ae754SRob Clark } 2967a26ae754SRob Clark 2968a26ae754SRob Clark #define REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO 0x0000e098 2969a26ae754SRob Clark #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 2970a26ae754SRob Clark #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 2971a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val) 2972a26ae754SRob Clark { 2973a26ae754SRob Clark return ((val) << A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; 2974a26ae754SRob Clark } 2975a26ae754SRob Clark 2976a26ae754SRob Clark #define REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x0000e099 2977a26ae754SRob Clark 2978a26ae754SRob Clark #define REG_A5XX_GRAS_SC_CNTL 0x0000e0a0 297952260ae4SRob Clark #define A5XX_GRAS_SC_CNTL_BINNING_PASS 0x00000001 2980a26ae754SRob Clark #define A5XX_GRAS_SC_CNTL_SAMPLES_PASSED 0x00008000 2981a26ae754SRob Clark 2982a26ae754SRob Clark #define REG_A5XX_GRAS_SC_BIN_CNTL 0x0000e0a1 2983a26ae754SRob Clark 2984a26ae754SRob Clark #define REG_A5XX_GRAS_SC_RAS_MSAA_CNTL 0x0000e0a2 2985a26ae754SRob Clark #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 2986a26ae754SRob Clark #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 2987a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 2988a26ae754SRob Clark { 2989a26ae754SRob Clark return ((val) << A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK; 2990a26ae754SRob Clark } 2991a26ae754SRob Clark 2992a26ae754SRob Clark #define REG_A5XX_GRAS_SC_DEST_MSAA_CNTL 0x0000e0a3 2993a26ae754SRob Clark #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 2994a26ae754SRob Clark #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 2995a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 2996a26ae754SRob Clark { 2997a26ae754SRob Clark return ((val) << A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK; 2998a26ae754SRob Clark } 2999a26ae754SRob Clark #define A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 3000a26ae754SRob Clark 3001a26ae754SRob Clark #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL 0x0000e0a4 3002a26ae754SRob Clark 3003a26ae754SRob Clark #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0 0x0000e0aa 3004a26ae754SRob Clark #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000 3005a26ae754SRob Clark #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK 0x00007fff 3006a26ae754SRob Clark #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT 0 3007a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val) 3008a26ae754SRob Clark { 3009a26ae754SRob Clark return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK; 3010a26ae754SRob Clark } 3011a26ae754SRob Clark #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK 0x7fff0000 3012a26ae754SRob Clark #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT 16 3013a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val) 3014a26ae754SRob Clark { 3015a26ae754SRob Clark return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK; 3016a26ae754SRob Clark } 3017a26ae754SRob Clark 3018a26ae754SRob Clark #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0 0x0000e0ab 3019a26ae754SRob Clark #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000 3020a26ae754SRob Clark #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK 0x00007fff 3021a26ae754SRob Clark #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT 0 3022a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val) 3023a26ae754SRob Clark { 3024a26ae754SRob Clark return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK; 3025a26ae754SRob Clark } 3026a26ae754SRob Clark #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK 0x7fff0000 3027a26ae754SRob Clark #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT 16 3028a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val) 3029a26ae754SRob Clark { 3030a26ae754SRob Clark return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK; 3031a26ae754SRob Clark } 3032a26ae754SRob Clark 3033a26ae754SRob Clark #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0 0x0000e0ca 3034a26ae754SRob Clark #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000 3035a26ae754SRob Clark #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK 0x00007fff 3036a26ae754SRob Clark #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT 0 3037a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val) 3038a26ae754SRob Clark { 3039a26ae754SRob Clark return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK; 3040a26ae754SRob Clark } 3041a26ae754SRob Clark #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK 0x7fff0000 3042a26ae754SRob Clark #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT 16 3043a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val) 3044a26ae754SRob Clark { 3045a26ae754SRob Clark return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK; 3046a26ae754SRob Clark } 3047a26ae754SRob Clark 3048a26ae754SRob Clark #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0 0x0000e0cb 3049a26ae754SRob Clark #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000 3050a26ae754SRob Clark #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK 0x00007fff 3051a26ae754SRob Clark #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT 0 3052a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val) 3053a26ae754SRob Clark { 3054a26ae754SRob Clark return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK; 3055a26ae754SRob Clark } 3056a26ae754SRob Clark #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK 0x7fff0000 3057a26ae754SRob Clark #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT 16 3058a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val) 3059a26ae754SRob Clark { 3060a26ae754SRob Clark return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK; 3061a26ae754SRob Clark } 3062a26ae754SRob Clark 3063a26ae754SRob Clark #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000e0ea 3064a26ae754SRob Clark #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 3065a26ae754SRob Clark #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 3066a26ae754SRob Clark #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 3067a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 3068a26ae754SRob Clark { 3069a26ae754SRob Clark return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 3070a26ae754SRob Clark } 3071a26ae754SRob Clark #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 3072a26ae754SRob Clark #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 3073a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 3074a26ae754SRob Clark { 3075a26ae754SRob Clark return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 3076a26ae754SRob Clark } 3077a26ae754SRob Clark 3078a26ae754SRob Clark #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000e0eb 3079a26ae754SRob Clark #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 3080a26ae754SRob Clark #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 3081a26ae754SRob Clark #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 3082a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 3083a26ae754SRob Clark { 3084a26ae754SRob Clark return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 3085a26ae754SRob Clark } 3086a26ae754SRob Clark #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 3087a26ae754SRob Clark #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 3088a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 3089a26ae754SRob Clark { 3090a26ae754SRob Clark return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 3091a26ae754SRob Clark } 3092a26ae754SRob Clark 3093a26ae754SRob Clark #define REG_A5XX_GRAS_LRZ_CNTL 0x0000e100 309452260ae4SRob Clark #define A5XX_GRAS_LRZ_CNTL_ENABLE 0x00000001 309552260ae4SRob Clark #define A5XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002 309652260ae4SRob Clark #define A5XX_GRAS_LRZ_CNTL_GREATER 0x00000004 3097a26ae754SRob Clark 3098a26ae754SRob Clark #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO 0x0000e101 3099a26ae754SRob Clark 3100a26ae754SRob Clark #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_HI 0x0000e102 3101a26ae754SRob Clark 3102a26ae754SRob Clark #define REG_A5XX_GRAS_LRZ_BUFFER_PITCH 0x0000e103 310352260ae4SRob Clark #define A5XX_GRAS_LRZ_BUFFER_PITCH__MASK 0xffffffff 310452260ae4SRob Clark #define A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT 0 310552260ae4SRob Clark static inline uint32_t A5XX_GRAS_LRZ_BUFFER_PITCH(uint32_t val) 310652260ae4SRob Clark { 310752260ae4SRob Clark return ((val >> 5) << A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT) & A5XX_GRAS_LRZ_BUFFER_PITCH__MASK; 310852260ae4SRob Clark } 3109a26ae754SRob Clark 3110a26ae754SRob Clark #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x0000e104 3111a26ae754SRob Clark 3112a26ae754SRob Clark #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x0000e105 3113a26ae754SRob Clark 3114a26ae754SRob Clark #define REG_A5XX_RB_CNTL 0x0000e140 3115a26ae754SRob Clark #define A5XX_RB_CNTL_WIDTH__MASK 0x000000ff 3116a26ae754SRob Clark #define A5XX_RB_CNTL_WIDTH__SHIFT 0 3117a26ae754SRob Clark static inline uint32_t A5XX_RB_CNTL_WIDTH(uint32_t val) 3118a26ae754SRob Clark { 3119a26ae754SRob Clark return ((val >> 5) << A5XX_RB_CNTL_WIDTH__SHIFT) & A5XX_RB_CNTL_WIDTH__MASK; 3120a26ae754SRob Clark } 3121a26ae754SRob Clark #define A5XX_RB_CNTL_HEIGHT__MASK 0x0001fe00 3122a26ae754SRob Clark #define A5XX_RB_CNTL_HEIGHT__SHIFT 9 3123a26ae754SRob Clark static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val) 3124a26ae754SRob Clark { 3125a26ae754SRob Clark return ((val >> 5) << A5XX_RB_CNTL_HEIGHT__SHIFT) & A5XX_RB_CNTL_HEIGHT__MASK; 3126a26ae754SRob Clark } 3127a26ae754SRob Clark #define A5XX_RB_CNTL_BYPASS 0x00020000 3128a26ae754SRob Clark 3129a26ae754SRob Clark #define REG_A5XX_RB_RENDER_CNTL 0x0000e141 313052260ae4SRob Clark #define A5XX_RB_RENDER_CNTL_BINNING_PASS 0x00000001 3131a26ae754SRob Clark #define A5XX_RB_RENDER_CNTL_SAMPLES_PASSED 0x00000040 313252260ae4SRob Clark #define A5XX_RB_RENDER_CNTL_DISABLE_COLOR_PIPE 0x00000080 3133a26ae754SRob Clark #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000 3134a26ae754SRob Clark #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH2 0x00008000 3135a26ae754SRob Clark #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000 3136a26ae754SRob Clark #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16 3137a26ae754SRob Clark static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val) 3138a26ae754SRob Clark { 3139a26ae754SRob Clark return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK; 3140a26ae754SRob Clark } 3141a26ae754SRob Clark #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK 0xff000000 3142a26ae754SRob Clark #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT 24 3143a26ae754SRob Clark static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS2(uint32_t val) 3144a26ae754SRob Clark { 3145a26ae754SRob Clark return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK; 3146a26ae754SRob Clark } 3147a26ae754SRob Clark 3148a26ae754SRob Clark #define REG_A5XX_RB_RAS_MSAA_CNTL 0x0000e142 3149a26ae754SRob Clark #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 3150a26ae754SRob Clark #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 3151a26ae754SRob Clark static inline uint32_t A5XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 3152a26ae754SRob Clark { 3153a26ae754SRob Clark return ((val) << A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK; 3154a26ae754SRob Clark } 3155a26ae754SRob Clark 3156a26ae754SRob Clark #define REG_A5XX_RB_DEST_MSAA_CNTL 0x0000e143 3157a26ae754SRob Clark #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 3158a26ae754SRob Clark #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 3159a26ae754SRob Clark static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 3160a26ae754SRob Clark { 3161a26ae754SRob Clark return ((val) << A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK; 3162a26ae754SRob Clark } 3163a26ae754SRob Clark #define A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 3164a26ae754SRob Clark 3165a26ae754SRob Clark #define REG_A5XX_RB_RENDER_CONTROL0 0x0000e144 3166c28c82e9SRob Clark #define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL 0x00000001 3167c28c82e9SRob Clark #define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID 0x00000002 3168c28c82e9SRob Clark #define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE 0x00000004 3169c28c82e9SRob Clark #define A5XX_RB_RENDER_CONTROL0_SIZE 0x00000008 3170c28c82e9SRob Clark #define A5XX_RB_RENDER_CONTROL0_COORD_MASK__MASK 0x000003c0 3171c28c82e9SRob Clark #define A5XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT 6 3172c28c82e9SRob Clark static inline uint32_t A5XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val) 3173c28c82e9SRob Clark { 3174c28c82e9SRob Clark return ((val) << A5XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A5XX_RB_RENDER_CONTROL0_COORD_MASK__MASK; 3175c28c82e9SRob Clark } 3176a26ae754SRob Clark 3177a26ae754SRob Clark #define REG_A5XX_RB_RENDER_CONTROL1 0x0000e145 31782d756322SRob Clark #define A5XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001 3179a26ae754SRob Clark #define A5XX_RB_RENDER_CONTROL1_FACENESS 0x00000002 31802d756322SRob Clark #define A5XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000004 3181a26ae754SRob Clark 3182a26ae754SRob Clark #define REG_A5XX_RB_FS_OUTPUT_CNTL 0x0000e146 3183a26ae754SRob Clark #define A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f 3184a26ae754SRob Clark #define A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT 0 3185a26ae754SRob Clark static inline uint32_t A5XX_RB_FS_OUTPUT_CNTL_MRT(uint32_t val) 3186a26ae754SRob Clark { 3187a26ae754SRob Clark return ((val) << A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK; 3188a26ae754SRob Clark } 3189a26ae754SRob Clark #define A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z 0x00000020 3190a26ae754SRob Clark 3191a26ae754SRob Clark #define REG_A5XX_RB_RENDER_COMPONENTS 0x0000e147 3192a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f 3193a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0 3194a26ae754SRob Clark static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) 3195a26ae754SRob Clark { 3196a26ae754SRob Clark return ((val) << A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT0__MASK; 3197a26ae754SRob Clark } 3198a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0 3199a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4 3200a26ae754SRob Clark static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) 3201a26ae754SRob Clark { 3202a26ae754SRob Clark return ((val) << A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT1__MASK; 3203a26ae754SRob Clark } 3204a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00 3205a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8 3206a26ae754SRob Clark static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) 3207a26ae754SRob Clark { 3208a26ae754SRob Clark return ((val) << A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT2__MASK; 3209a26ae754SRob Clark } 3210a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000 3211a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12 3212a26ae754SRob Clark static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) 3213a26ae754SRob Clark { 3214a26ae754SRob Clark return ((val) << A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT3__MASK; 3215a26ae754SRob Clark } 3216a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000 3217a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16 3218a26ae754SRob Clark static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) 3219a26ae754SRob Clark { 3220a26ae754SRob Clark return ((val) << A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT4__MASK; 3221a26ae754SRob Clark } 3222a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000 3223a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20 3224a26ae754SRob Clark static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) 3225a26ae754SRob Clark { 3226a26ae754SRob Clark return ((val) << A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT5__MASK; 3227a26ae754SRob Clark } 3228a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000 3229a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24 3230a26ae754SRob Clark static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) 3231a26ae754SRob Clark { 3232a26ae754SRob Clark return ((val) << A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT6__MASK; 3233a26ae754SRob Clark } 3234a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000 3235a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28 3236a26ae754SRob Clark static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) 3237a26ae754SRob Clark { 3238a26ae754SRob Clark return ((val) << A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT7__MASK; 3239a26ae754SRob Clark } 3240a26ae754SRob Clark 3241a26ae754SRob Clark static inline uint32_t REG_A5XX_RB_MRT(uint32_t i0) { return 0x0000e150 + 0x7*i0; } 3242a26ae754SRob Clark 3243a26ae754SRob Clark static inline uint32_t REG_A5XX_RB_MRT_CONTROL(uint32_t i0) { return 0x0000e150 + 0x7*i0; } 3244a26ae754SRob Clark #define A5XX_RB_MRT_CONTROL_BLEND 0x00000001 3245a26ae754SRob Clark #define A5XX_RB_MRT_CONTROL_BLEND2 0x00000002 32462d756322SRob Clark #define A5XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004 32472d756322SRob Clark #define A5XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078 32482d756322SRob Clark #define A5XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3 32492d756322SRob Clark static inline uint32_t A5XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) 32502d756322SRob Clark { 32512d756322SRob Clark return ((val) << A5XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A5XX_RB_MRT_CONTROL_ROP_CODE__MASK; 32522d756322SRob Clark } 3253a26ae754SRob Clark #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780 3254a26ae754SRob Clark #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7 3255a26ae754SRob Clark static inline uint32_t A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 3256a26ae754SRob Clark { 3257a26ae754SRob Clark return ((val) << A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 3258a26ae754SRob Clark } 3259a26ae754SRob Clark 3260a26ae754SRob Clark static inline uint32_t REG_A5XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x0000e151 + 0x7*i0; } 3261a26ae754SRob Clark #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 3262a26ae754SRob Clark #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 3263a26ae754SRob Clark static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 3264a26ae754SRob Clark { 3265a26ae754SRob Clark return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 3266a26ae754SRob Clark } 3267a26ae754SRob Clark #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 3268a26ae754SRob Clark #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 3269a26ae754SRob Clark static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 3270a26ae754SRob Clark { 3271a26ae754SRob Clark return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 3272a26ae754SRob Clark } 3273a26ae754SRob Clark #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 3274a26ae754SRob Clark #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 3275a26ae754SRob Clark static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 3276a26ae754SRob Clark { 3277a26ae754SRob Clark return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 3278a26ae754SRob Clark } 3279a26ae754SRob Clark #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 3280a26ae754SRob Clark #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 3281a26ae754SRob Clark static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 3282a26ae754SRob Clark { 3283a26ae754SRob Clark return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 3284a26ae754SRob Clark } 3285a26ae754SRob Clark #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 3286a26ae754SRob Clark #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 3287a26ae754SRob Clark static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 3288a26ae754SRob Clark { 3289a26ae754SRob Clark return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 3290a26ae754SRob Clark } 3291a26ae754SRob Clark #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 3292a26ae754SRob Clark #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 3293a26ae754SRob Clark static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 3294a26ae754SRob Clark { 3295a26ae754SRob Clark return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 3296a26ae754SRob Clark } 3297a26ae754SRob Clark 3298a26ae754SRob Clark static inline uint32_t REG_A5XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x0000e152 + 0x7*i0; } 3299a26ae754SRob Clark #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff 3300a26ae754SRob Clark #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 3301a26ae754SRob Clark static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) 3302a26ae754SRob Clark { 3303a26ae754SRob Clark return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 3304a26ae754SRob Clark } 3305a26ae754SRob Clark #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300 3306a26ae754SRob Clark #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8 3307a26ae754SRob Clark static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a5xx_tile_mode val) 3308a26ae754SRob Clark { 3309a26ae754SRob Clark return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 3310a26ae754SRob Clark } 33112d756322SRob Clark #define A5XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00001800 33122d756322SRob Clark #define A5XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 11 33132d756322SRob Clark static inline uint32_t A5XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 33142d756322SRob Clark { 33152d756322SRob Clark return ((val) << A5XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK; 33162d756322SRob Clark } 3317a26ae754SRob Clark #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000 3318a26ae754SRob Clark #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13 3319a26ae754SRob Clark static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 3320a26ae754SRob Clark { 3321a26ae754SRob Clark return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 3322a26ae754SRob Clark } 3323a26ae754SRob Clark #define A5XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00008000 3324a26ae754SRob Clark 3325a26ae754SRob Clark static inline uint32_t REG_A5XX_RB_MRT_PITCH(uint32_t i0) { return 0x0000e153 + 0x7*i0; } 3326a26ae754SRob Clark #define A5XX_RB_MRT_PITCH__MASK 0xffffffff 3327a26ae754SRob Clark #define A5XX_RB_MRT_PITCH__SHIFT 0 3328a26ae754SRob Clark static inline uint32_t A5XX_RB_MRT_PITCH(uint32_t val) 3329a26ae754SRob Clark { 3330a26ae754SRob Clark return ((val >> 6) << A5XX_RB_MRT_PITCH__SHIFT) & A5XX_RB_MRT_PITCH__MASK; 3331a26ae754SRob Clark } 3332a26ae754SRob Clark 3333a26ae754SRob Clark static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x0000e154 + 0x7*i0; } 3334a26ae754SRob Clark #define A5XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff 3335a26ae754SRob Clark #define A5XX_RB_MRT_ARRAY_PITCH__SHIFT 0 3336a26ae754SRob Clark static inline uint32_t A5XX_RB_MRT_ARRAY_PITCH(uint32_t val) 3337a26ae754SRob Clark { 3338a26ae754SRob Clark return ((val >> 6) << A5XX_RB_MRT_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_ARRAY_PITCH__MASK; 3339a26ae754SRob Clark } 3340a26ae754SRob Clark 3341a26ae754SRob Clark static inline uint32_t REG_A5XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x0000e155 + 0x7*i0; } 3342a26ae754SRob Clark 3343a26ae754SRob Clark static inline uint32_t REG_A5XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x0000e156 + 0x7*i0; } 3344a26ae754SRob Clark 3345a26ae754SRob Clark #define REG_A5XX_RB_BLEND_RED 0x0000e1a0 3346a26ae754SRob Clark #define A5XX_RB_BLEND_RED_UINT__MASK 0x000000ff 3347a26ae754SRob Clark #define A5XX_RB_BLEND_RED_UINT__SHIFT 0 3348a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_RED_UINT(uint32_t val) 3349a26ae754SRob Clark { 3350a26ae754SRob Clark return ((val) << A5XX_RB_BLEND_RED_UINT__SHIFT) & A5XX_RB_BLEND_RED_UINT__MASK; 3351a26ae754SRob Clark } 3352a26ae754SRob Clark #define A5XX_RB_BLEND_RED_SINT__MASK 0x0000ff00 3353a26ae754SRob Clark #define A5XX_RB_BLEND_RED_SINT__SHIFT 8 3354a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val) 3355a26ae754SRob Clark { 3356a26ae754SRob Clark return ((val) << A5XX_RB_BLEND_RED_SINT__SHIFT) & A5XX_RB_BLEND_RED_SINT__MASK; 3357a26ae754SRob Clark } 3358a26ae754SRob Clark #define A5XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 3359a26ae754SRob Clark #define A5XX_RB_BLEND_RED_FLOAT__SHIFT 16 3360a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val) 3361a26ae754SRob Clark { 3362*cc4c26d4SRob Clark return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK; 3363a26ae754SRob Clark } 3364a26ae754SRob Clark 3365a26ae754SRob Clark #define REG_A5XX_RB_BLEND_RED_F32 0x0000e1a1 3366a26ae754SRob Clark #define A5XX_RB_BLEND_RED_F32__MASK 0xffffffff 3367a26ae754SRob Clark #define A5XX_RB_BLEND_RED_F32__SHIFT 0 3368a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_RED_F32(float val) 3369a26ae754SRob Clark { 3370a26ae754SRob Clark return ((fui(val)) << A5XX_RB_BLEND_RED_F32__SHIFT) & A5XX_RB_BLEND_RED_F32__MASK; 3371a26ae754SRob Clark } 3372a26ae754SRob Clark 3373a26ae754SRob Clark #define REG_A5XX_RB_BLEND_GREEN 0x0000e1a2 3374a26ae754SRob Clark #define A5XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff 3375a26ae754SRob Clark #define A5XX_RB_BLEND_GREEN_UINT__SHIFT 0 3376a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_GREEN_UINT(uint32_t val) 3377a26ae754SRob Clark { 3378a26ae754SRob Clark return ((val) << A5XX_RB_BLEND_GREEN_UINT__SHIFT) & A5XX_RB_BLEND_GREEN_UINT__MASK; 3379a26ae754SRob Clark } 3380a26ae754SRob Clark #define A5XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00 3381a26ae754SRob Clark #define A5XX_RB_BLEND_GREEN_SINT__SHIFT 8 3382a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val) 3383a26ae754SRob Clark { 3384a26ae754SRob Clark return ((val) << A5XX_RB_BLEND_GREEN_SINT__SHIFT) & A5XX_RB_BLEND_GREEN_SINT__MASK; 3385a26ae754SRob Clark } 3386a26ae754SRob Clark #define A5XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 3387a26ae754SRob Clark #define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 3388a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val) 3389a26ae754SRob Clark { 3390*cc4c26d4SRob Clark return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK; 3391a26ae754SRob Clark } 3392a26ae754SRob Clark 3393a26ae754SRob Clark #define REG_A5XX_RB_BLEND_GREEN_F32 0x0000e1a3 3394a26ae754SRob Clark #define A5XX_RB_BLEND_GREEN_F32__MASK 0xffffffff 3395a26ae754SRob Clark #define A5XX_RB_BLEND_GREEN_F32__SHIFT 0 3396a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_GREEN_F32(float val) 3397a26ae754SRob Clark { 3398a26ae754SRob Clark return ((fui(val)) << A5XX_RB_BLEND_GREEN_F32__SHIFT) & A5XX_RB_BLEND_GREEN_F32__MASK; 3399a26ae754SRob Clark } 3400a26ae754SRob Clark 3401a26ae754SRob Clark #define REG_A5XX_RB_BLEND_BLUE 0x0000e1a4 3402a26ae754SRob Clark #define A5XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff 3403a26ae754SRob Clark #define A5XX_RB_BLEND_BLUE_UINT__SHIFT 0 3404a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_BLUE_UINT(uint32_t val) 3405a26ae754SRob Clark { 3406a26ae754SRob Clark return ((val) << A5XX_RB_BLEND_BLUE_UINT__SHIFT) & A5XX_RB_BLEND_BLUE_UINT__MASK; 3407a26ae754SRob Clark } 3408a26ae754SRob Clark #define A5XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00 3409a26ae754SRob Clark #define A5XX_RB_BLEND_BLUE_SINT__SHIFT 8 3410a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val) 3411a26ae754SRob Clark { 3412a26ae754SRob Clark return ((val) << A5XX_RB_BLEND_BLUE_SINT__SHIFT) & A5XX_RB_BLEND_BLUE_SINT__MASK; 3413a26ae754SRob Clark } 3414a26ae754SRob Clark #define A5XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 3415a26ae754SRob Clark #define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 3416a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val) 3417a26ae754SRob Clark { 3418*cc4c26d4SRob Clark return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK; 3419a26ae754SRob Clark } 3420a26ae754SRob Clark 3421a26ae754SRob Clark #define REG_A5XX_RB_BLEND_BLUE_F32 0x0000e1a5 3422a26ae754SRob Clark #define A5XX_RB_BLEND_BLUE_F32__MASK 0xffffffff 3423a26ae754SRob Clark #define A5XX_RB_BLEND_BLUE_F32__SHIFT 0 3424a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_BLUE_F32(float val) 3425a26ae754SRob Clark { 3426a26ae754SRob Clark return ((fui(val)) << A5XX_RB_BLEND_BLUE_F32__SHIFT) & A5XX_RB_BLEND_BLUE_F32__MASK; 3427a26ae754SRob Clark } 3428a26ae754SRob Clark 3429a26ae754SRob Clark #define REG_A5XX_RB_BLEND_ALPHA 0x0000e1a6 3430a26ae754SRob Clark #define A5XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff 3431a26ae754SRob Clark #define A5XX_RB_BLEND_ALPHA_UINT__SHIFT 0 3432a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_ALPHA_UINT(uint32_t val) 3433a26ae754SRob Clark { 3434a26ae754SRob Clark return ((val) << A5XX_RB_BLEND_ALPHA_UINT__SHIFT) & A5XX_RB_BLEND_ALPHA_UINT__MASK; 3435a26ae754SRob Clark } 3436a26ae754SRob Clark #define A5XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00 3437a26ae754SRob Clark #define A5XX_RB_BLEND_ALPHA_SINT__SHIFT 8 3438a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val) 3439a26ae754SRob Clark { 3440a26ae754SRob Clark return ((val) << A5XX_RB_BLEND_ALPHA_SINT__SHIFT) & A5XX_RB_BLEND_ALPHA_SINT__MASK; 3441a26ae754SRob Clark } 3442a26ae754SRob Clark #define A5XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 3443a26ae754SRob Clark #define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 3444a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val) 3445a26ae754SRob Clark { 3446*cc4c26d4SRob Clark return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK; 3447a26ae754SRob Clark } 3448a26ae754SRob Clark 3449a26ae754SRob Clark #define REG_A5XX_RB_BLEND_ALPHA_F32 0x0000e1a7 3450a26ae754SRob Clark #define A5XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff 3451a26ae754SRob Clark #define A5XX_RB_BLEND_ALPHA_F32__SHIFT 0 3452a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_ALPHA_F32(float val) 3453a26ae754SRob Clark { 3454a26ae754SRob Clark return ((fui(val)) << A5XX_RB_BLEND_ALPHA_F32__SHIFT) & A5XX_RB_BLEND_ALPHA_F32__MASK; 3455a26ae754SRob Clark } 3456a26ae754SRob Clark 3457a26ae754SRob Clark #define REG_A5XX_RB_ALPHA_CONTROL 0x0000e1a8 3458a26ae754SRob Clark #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff 3459a26ae754SRob Clark #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 3460a26ae754SRob Clark static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) 3461a26ae754SRob Clark { 3462a26ae754SRob Clark return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; 3463a26ae754SRob Clark } 3464a26ae754SRob Clark #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 3465a26ae754SRob Clark #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 3466a26ae754SRob Clark #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 3467a26ae754SRob Clark static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 3468a26ae754SRob Clark { 3469a26ae754SRob Clark return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; 3470a26ae754SRob Clark } 3471a26ae754SRob Clark 3472a26ae754SRob Clark #define REG_A5XX_RB_BLEND_CNTL 0x0000e1a9 3473a26ae754SRob Clark #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff 3474a26ae754SRob Clark #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 3475a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val) 3476a26ae754SRob Clark { 3477a26ae754SRob Clark return ((val) << A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK; 3478a26ae754SRob Clark } 3479a26ae754SRob Clark #define A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100 34802d756322SRob Clark #define A5XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 3481a26ae754SRob Clark #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000 3482a26ae754SRob Clark #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16 3483a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val) 3484a26ae754SRob Clark { 3485a26ae754SRob Clark return ((val) << A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK; 3486a26ae754SRob Clark } 3487a26ae754SRob Clark 3488a26ae754SRob Clark #define REG_A5XX_RB_DEPTH_PLANE_CNTL 0x0000e1b0 3489a26ae754SRob Clark #define A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001 349052260ae4SRob Clark #define A5XX_RB_DEPTH_PLANE_CNTL_UNK1 0x00000002 3491a26ae754SRob Clark 3492a26ae754SRob Clark #define REG_A5XX_RB_DEPTH_CNTL 0x0000e1b1 3493a26ae754SRob Clark #define A5XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001 3494a26ae754SRob Clark #define A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002 3495a26ae754SRob Clark #define A5XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c 3496a26ae754SRob Clark #define A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2 3497a26ae754SRob Clark static inline uint32_t A5XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) 3498a26ae754SRob Clark { 3499a26ae754SRob Clark return ((val) << A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A5XX_RB_DEPTH_CNTL_ZFUNC__MASK; 3500a26ae754SRob Clark } 3501a26ae754SRob Clark #define A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040 3502a26ae754SRob Clark 3503a26ae754SRob Clark #define REG_A5XX_RB_DEPTH_BUFFER_INFO 0x0000e1b2 3504a26ae754SRob Clark #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 3505a26ae754SRob Clark #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 3506a26ae754SRob Clark static inline uint32_t A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val) 3507a26ae754SRob Clark { 3508a26ae754SRob Clark return ((val) << A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; 3509a26ae754SRob Clark } 3510a26ae754SRob Clark 3511a26ae754SRob Clark #define REG_A5XX_RB_DEPTH_BUFFER_BASE_LO 0x0000e1b3 3512a26ae754SRob Clark 3513a26ae754SRob Clark #define REG_A5XX_RB_DEPTH_BUFFER_BASE_HI 0x0000e1b4 3514a26ae754SRob Clark 3515a26ae754SRob Clark #define REG_A5XX_RB_DEPTH_BUFFER_PITCH 0x0000e1b5 3516a26ae754SRob Clark #define A5XX_RB_DEPTH_BUFFER_PITCH__MASK 0xffffffff 3517a26ae754SRob Clark #define A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0 3518a26ae754SRob Clark static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) 3519a26ae754SRob Clark { 352052260ae4SRob Clark return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_PITCH__MASK; 3521a26ae754SRob Clark } 3522a26ae754SRob Clark 3523a26ae754SRob Clark #define REG_A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x0000e1b6 3524a26ae754SRob Clark #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0xffffffff 3525a26ae754SRob Clark #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0 3526a26ae754SRob Clark static inline uint32_t A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) 3527a26ae754SRob Clark { 352852260ae4SRob Clark return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; 3529a26ae754SRob Clark } 3530a26ae754SRob Clark 3531a26ae754SRob Clark #define REG_A5XX_RB_STENCIL_CONTROL 0x0000e1c0 3532a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 3533a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 3534a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 3535a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 3536a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 3537a26ae754SRob Clark static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 3538a26ae754SRob Clark { 3539a26ae754SRob Clark return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC__MASK; 3540a26ae754SRob Clark } 3541a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 3542a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 3543a26ae754SRob Clark static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 3544a26ae754SRob Clark { 3545a26ae754SRob Clark return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL__MASK; 3546a26ae754SRob Clark } 3547a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 3548a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 3549a26ae754SRob Clark static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 3550a26ae754SRob Clark { 3551a26ae754SRob Clark return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS__MASK; 3552a26ae754SRob Clark } 3553a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 3554a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 3555a26ae754SRob Clark static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 3556a26ae754SRob Clark { 3557a26ae754SRob Clark return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 3558a26ae754SRob Clark } 3559a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 3560a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 3561a26ae754SRob Clark static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 3562a26ae754SRob Clark { 3563a26ae754SRob Clark return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 3564a26ae754SRob Clark } 3565a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 3566a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 3567a26ae754SRob Clark static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 3568a26ae754SRob Clark { 3569a26ae754SRob Clark return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 3570a26ae754SRob Clark } 3571a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 3572a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 3573a26ae754SRob Clark static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 3574a26ae754SRob Clark { 3575a26ae754SRob Clark return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 3576a26ae754SRob Clark } 3577a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 3578a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 3579a26ae754SRob Clark static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 3580a26ae754SRob Clark { 3581a26ae754SRob Clark return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 3582a26ae754SRob Clark } 3583a26ae754SRob Clark 3584a26ae754SRob Clark #define REG_A5XX_RB_STENCIL_INFO 0x0000e1c1 3585a26ae754SRob Clark #define A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 3586a26ae754SRob Clark 3587a26ae754SRob Clark #define REG_A5XX_RB_STENCIL_BASE_LO 0x0000e1c2 3588a26ae754SRob Clark 3589a26ae754SRob Clark #define REG_A5XX_RB_STENCIL_BASE_HI 0x0000e1c3 3590a26ae754SRob Clark 3591a26ae754SRob Clark #define REG_A5XX_RB_STENCIL_PITCH 0x0000e1c4 3592a26ae754SRob Clark #define A5XX_RB_STENCIL_PITCH__MASK 0xffffffff 3593a26ae754SRob Clark #define A5XX_RB_STENCIL_PITCH__SHIFT 0 3594a26ae754SRob Clark static inline uint32_t A5XX_RB_STENCIL_PITCH(uint32_t val) 3595a26ae754SRob Clark { 3596a26ae754SRob Clark return ((val >> 6) << A5XX_RB_STENCIL_PITCH__SHIFT) & A5XX_RB_STENCIL_PITCH__MASK; 3597a26ae754SRob Clark } 3598a26ae754SRob Clark 3599a26ae754SRob Clark #define REG_A5XX_RB_STENCIL_ARRAY_PITCH 0x0000e1c5 3600a26ae754SRob Clark #define A5XX_RB_STENCIL_ARRAY_PITCH__MASK 0xffffffff 3601a26ae754SRob Clark #define A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT 0 3602a26ae754SRob Clark static inline uint32_t A5XX_RB_STENCIL_ARRAY_PITCH(uint32_t val) 3603a26ae754SRob Clark { 3604a26ae754SRob Clark return ((val >> 6) << A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT) & A5XX_RB_STENCIL_ARRAY_PITCH__MASK; 3605a26ae754SRob Clark } 3606a26ae754SRob Clark 3607a26ae754SRob Clark #define REG_A5XX_RB_STENCILREFMASK 0x0000e1c6 3608a26ae754SRob Clark #define A5XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 3609a26ae754SRob Clark #define A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 3610a26ae754SRob Clark static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 3611a26ae754SRob Clark { 3612a26ae754SRob Clark return ((val) << A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILREF__MASK; 3613a26ae754SRob Clark } 3614a26ae754SRob Clark #define A5XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 3615a26ae754SRob Clark #define A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 3616a26ae754SRob Clark static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 3617a26ae754SRob Clark { 3618a26ae754SRob Clark return ((val) << A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILMASK__MASK; 3619a26ae754SRob Clark } 3620a26ae754SRob Clark #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 3621a26ae754SRob Clark #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 3622a26ae754SRob Clark static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 3623a26ae754SRob Clark { 3624a26ae754SRob Clark return ((val) << A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 3625a26ae754SRob Clark } 3626a26ae754SRob Clark 36272d756322SRob Clark #define REG_A5XX_RB_STENCILREFMASK_BF 0x0000e1c7 36282d756322SRob Clark #define A5XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 36292d756322SRob Clark #define A5XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 36302d756322SRob Clark static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 36312d756322SRob Clark { 36322d756322SRob Clark return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 36332d756322SRob Clark } 36342d756322SRob Clark #define A5XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 36352d756322SRob Clark #define A5XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 36362d756322SRob Clark static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 36372d756322SRob Clark { 36382d756322SRob Clark return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 36392d756322SRob Clark } 36402d756322SRob Clark #define A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 36412d756322SRob Clark #define A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 36422d756322SRob Clark static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 36432d756322SRob Clark { 36442d756322SRob Clark return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 36452d756322SRob Clark } 3646a26ae754SRob Clark 3647a26ae754SRob Clark #define REG_A5XX_RB_WINDOW_OFFSET 0x0000e1d0 3648a26ae754SRob Clark #define A5XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 3649a26ae754SRob Clark #define A5XX_RB_WINDOW_OFFSET_X__MASK 0x00007fff 3650a26ae754SRob Clark #define A5XX_RB_WINDOW_OFFSET_X__SHIFT 0 3651a26ae754SRob Clark static inline uint32_t A5XX_RB_WINDOW_OFFSET_X(uint32_t val) 3652a26ae754SRob Clark { 3653a26ae754SRob Clark return ((val) << A5XX_RB_WINDOW_OFFSET_X__SHIFT) & A5XX_RB_WINDOW_OFFSET_X__MASK; 3654a26ae754SRob Clark } 3655a26ae754SRob Clark #define A5XX_RB_WINDOW_OFFSET_Y__MASK 0x7fff0000 3656a26ae754SRob Clark #define A5XX_RB_WINDOW_OFFSET_Y__SHIFT 16 3657a26ae754SRob Clark static inline uint32_t A5XX_RB_WINDOW_OFFSET_Y(uint32_t val) 3658a26ae754SRob Clark { 3659a26ae754SRob Clark return ((val) << A5XX_RB_WINDOW_OFFSET_Y__SHIFT) & A5XX_RB_WINDOW_OFFSET_Y__MASK; 3660a26ae754SRob Clark } 3661a26ae754SRob Clark 366252260ae4SRob Clark #define REG_A5XX_RB_SAMPLE_COUNT_CONTROL 0x0000e1d1 366352260ae4SRob Clark #define A5XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 366452260ae4SRob Clark 3665a26ae754SRob Clark #define REG_A5XX_RB_BLIT_CNTL 0x0000e210 366652260ae4SRob Clark #define A5XX_RB_BLIT_CNTL_BUF__MASK 0x0000000f 3667a26ae754SRob Clark #define A5XX_RB_BLIT_CNTL_BUF__SHIFT 0 3668a26ae754SRob Clark static inline uint32_t A5XX_RB_BLIT_CNTL_BUF(enum a5xx_blit_buf val) 3669a26ae754SRob Clark { 3670a26ae754SRob Clark return ((val) << A5XX_RB_BLIT_CNTL_BUF__SHIFT) & A5XX_RB_BLIT_CNTL_BUF__MASK; 3671a26ae754SRob Clark } 3672a26ae754SRob Clark 3673a26ae754SRob Clark #define REG_A5XX_RB_RESOLVE_CNTL_1 0x0000e211 3674a26ae754SRob Clark #define A5XX_RB_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE 0x80000000 3675a26ae754SRob Clark #define A5XX_RB_RESOLVE_CNTL_1_X__MASK 0x00007fff 3676a26ae754SRob Clark #define A5XX_RB_RESOLVE_CNTL_1_X__SHIFT 0 3677a26ae754SRob Clark static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_X(uint32_t val) 3678a26ae754SRob Clark { 3679a26ae754SRob Clark return ((val) << A5XX_RB_RESOLVE_CNTL_1_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_X__MASK; 3680a26ae754SRob Clark } 3681a26ae754SRob Clark #define A5XX_RB_RESOLVE_CNTL_1_Y__MASK 0x7fff0000 3682a26ae754SRob Clark #define A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT 16 3683a26ae754SRob Clark static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_Y(uint32_t val) 3684a26ae754SRob Clark { 3685a26ae754SRob Clark return ((val) << A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_Y__MASK; 3686a26ae754SRob Clark } 3687a26ae754SRob Clark 3688a26ae754SRob Clark #define REG_A5XX_RB_RESOLVE_CNTL_2 0x0000e212 3689a26ae754SRob Clark #define A5XX_RB_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE 0x80000000 3690a26ae754SRob Clark #define A5XX_RB_RESOLVE_CNTL_2_X__MASK 0x00007fff 3691a26ae754SRob Clark #define A5XX_RB_RESOLVE_CNTL_2_X__SHIFT 0 3692a26ae754SRob Clark static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_X(uint32_t val) 3693a26ae754SRob Clark { 3694a26ae754SRob Clark return ((val) << A5XX_RB_RESOLVE_CNTL_2_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_X__MASK; 3695a26ae754SRob Clark } 3696a26ae754SRob Clark #define A5XX_RB_RESOLVE_CNTL_2_Y__MASK 0x7fff0000 3697a26ae754SRob Clark #define A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT 16 3698a26ae754SRob Clark static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_Y(uint32_t val) 3699a26ae754SRob Clark { 3700a26ae754SRob Clark return ((val) << A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_Y__MASK; 3701a26ae754SRob Clark } 3702a26ae754SRob Clark 3703a26ae754SRob Clark #define REG_A5XX_RB_RESOLVE_CNTL_3 0x0000e213 37042d756322SRob Clark #define A5XX_RB_RESOLVE_CNTL_3_TILED 0x00000001 3705a26ae754SRob Clark 3706a26ae754SRob Clark #define REG_A5XX_RB_BLIT_DST_LO 0x0000e214 3707a26ae754SRob Clark 3708a26ae754SRob Clark #define REG_A5XX_RB_BLIT_DST_HI 0x0000e215 3709a26ae754SRob Clark 3710a26ae754SRob Clark #define REG_A5XX_RB_BLIT_DST_PITCH 0x0000e216 3711a26ae754SRob Clark #define A5XX_RB_BLIT_DST_PITCH__MASK 0xffffffff 3712a26ae754SRob Clark #define A5XX_RB_BLIT_DST_PITCH__SHIFT 0 3713a26ae754SRob Clark static inline uint32_t A5XX_RB_BLIT_DST_PITCH(uint32_t val) 3714a26ae754SRob Clark { 3715a26ae754SRob Clark return ((val >> 6) << A5XX_RB_BLIT_DST_PITCH__SHIFT) & A5XX_RB_BLIT_DST_PITCH__MASK; 3716a26ae754SRob Clark } 3717a26ae754SRob Clark 3718a26ae754SRob Clark #define REG_A5XX_RB_BLIT_DST_ARRAY_PITCH 0x0000e217 3719a26ae754SRob Clark #define A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0xffffffff 3720a26ae754SRob Clark #define A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0 3721a26ae754SRob Clark static inline uint32_t A5XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) 3722a26ae754SRob Clark { 3723a26ae754SRob Clark return ((val >> 6) << A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK; 3724a26ae754SRob Clark } 3725a26ae754SRob Clark 3726a26ae754SRob Clark #define REG_A5XX_RB_CLEAR_COLOR_DW0 0x0000e218 3727a26ae754SRob Clark 3728a26ae754SRob Clark #define REG_A5XX_RB_CLEAR_COLOR_DW1 0x0000e219 3729a26ae754SRob Clark 3730a26ae754SRob Clark #define REG_A5XX_RB_CLEAR_COLOR_DW2 0x0000e21a 3731a26ae754SRob Clark 3732a26ae754SRob Clark #define REG_A5XX_RB_CLEAR_COLOR_DW3 0x0000e21b 3733a26ae754SRob Clark 3734a26ae754SRob Clark #define REG_A5XX_RB_CLEAR_CNTL 0x0000e21c 3735a26ae754SRob Clark #define A5XX_RB_CLEAR_CNTL_FAST_CLEAR 0x00000002 37362d756322SRob Clark #define A5XX_RB_CLEAR_CNTL_MSAA_RESOLVE 0x00000004 3737a26ae754SRob Clark #define A5XX_RB_CLEAR_CNTL_MASK__MASK 0x000000f0 3738a26ae754SRob Clark #define A5XX_RB_CLEAR_CNTL_MASK__SHIFT 4 3739a26ae754SRob Clark static inline uint32_t A5XX_RB_CLEAR_CNTL_MASK(uint32_t val) 3740a26ae754SRob Clark { 3741a26ae754SRob Clark return ((val) << A5XX_RB_CLEAR_CNTL_MASK__SHIFT) & A5XX_RB_CLEAR_CNTL_MASK__MASK; 3742a26ae754SRob Clark } 3743a26ae754SRob Clark 3744a26ae754SRob Clark #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x0000e240 3745a26ae754SRob Clark 3746a26ae754SRob Clark #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x0000e241 3747a26ae754SRob Clark 3748a26ae754SRob Clark #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x0000e242 3749a26ae754SRob Clark 3750a26ae754SRob Clark static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x0000e243 + 0x4*i0; } 3751a26ae754SRob Clark 3752a26ae754SRob Clark static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x0000e243 + 0x4*i0; } 3753a26ae754SRob Clark 3754a26ae754SRob Clark static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x0000e244 + 0x4*i0; } 3755a26ae754SRob Clark 3756a26ae754SRob Clark static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x0000e245 + 0x4*i0; } 3757a26ae754SRob Clark #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK 0xffffffff 3758a26ae754SRob Clark #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT 0 3759a26ae754SRob Clark static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t val) 3760a26ae754SRob Clark { 3761a26ae754SRob Clark return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK; 3762a26ae754SRob Clark } 3763a26ae754SRob Clark 3764a26ae754SRob Clark static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0) { return 0x0000e246 + 0x4*i0; } 3765a26ae754SRob Clark #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK 0xffffffff 3766a26ae754SRob Clark #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0 3767a26ae754SRob Clark static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) 3768a26ae754SRob Clark { 3769a26ae754SRob Clark return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK; 3770a26ae754SRob Clark } 3771a26ae754SRob Clark 3772a26ae754SRob Clark #define REG_A5XX_RB_BLIT_FLAG_DST_LO 0x0000e263 3773a26ae754SRob Clark 3774a26ae754SRob Clark #define REG_A5XX_RB_BLIT_FLAG_DST_HI 0x0000e264 3775a26ae754SRob Clark 3776a26ae754SRob Clark #define REG_A5XX_RB_BLIT_FLAG_DST_PITCH 0x0000e265 3777a26ae754SRob Clark #define A5XX_RB_BLIT_FLAG_DST_PITCH__MASK 0xffffffff 3778a26ae754SRob Clark #define A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT 0 3779a26ae754SRob Clark static inline uint32_t A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val) 3780a26ae754SRob Clark { 3781a26ae754SRob Clark return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_PITCH__MASK; 3782a26ae754SRob Clark } 3783a26ae754SRob Clark 3784a26ae754SRob Clark #define REG_A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH 0x0000e266 3785a26ae754SRob Clark #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK 0xffffffff 3786a26ae754SRob Clark #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT 0 3787a26ae754SRob Clark static inline uint32_t A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val) 3788a26ae754SRob Clark { 3789a26ae754SRob Clark return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK; 3790a26ae754SRob Clark } 3791a26ae754SRob Clark 379252260ae4SRob Clark #define REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO 0x0000e267 379352260ae4SRob Clark 379452260ae4SRob Clark #define REG_A5XX_RB_SAMPLE_COUNT_ADDR_HI 0x0000e268 379552260ae4SRob Clark 3796a26ae754SRob Clark #define REG_A5XX_VPC_CNTL_0 0x0000e280 3797a26ae754SRob Clark #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK 0x0000007f 3798a26ae754SRob Clark #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT 0 3799a26ae754SRob Clark static inline uint32_t A5XX_VPC_CNTL_0_STRIDE_IN_VPC(uint32_t val) 3800a26ae754SRob Clark { 3801a26ae754SRob Clark return ((val) << A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT) & A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK; 3802a26ae754SRob Clark } 3803a26ae754SRob Clark #define A5XX_VPC_CNTL_0_VARYING 0x00000800 3804a26ae754SRob Clark 3805a26ae754SRob Clark static inline uint32_t REG_A5XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x0000e282 + 0x1*i0; } 3806a26ae754SRob Clark 3807a26ae754SRob Clark static inline uint32_t REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x0000e282 + 0x1*i0; } 3808a26ae754SRob Clark 3809a26ae754SRob Clark static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000e28a + 0x1*i0; } 3810a26ae754SRob Clark 3811a26ae754SRob Clark static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000e28a + 0x1*i0; } 3812a26ae754SRob Clark 3813a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E292 0x0000e292 3814a26ae754SRob Clark 3815a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E293 0x0000e293 3816a26ae754SRob Clark 3817a26ae754SRob Clark static inline uint32_t REG_A5XX_VPC_VAR(uint32_t i0) { return 0x0000e294 + 0x1*i0; } 3818a26ae754SRob Clark 3819a26ae754SRob Clark static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 + 0x1*i0; } 3820a26ae754SRob Clark 3821a26ae754SRob Clark #define REG_A5XX_VPC_GS_SIV_CNTL 0x0000e298 3822a26ae754SRob Clark 3823*cc4c26d4SRob Clark #define REG_A5XX_VPC_CLIP_CNTL 0x0000e29a 3824*cc4c26d4SRob Clark #define A5XX_VPC_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff 3825*cc4c26d4SRob Clark #define A5XX_VPC_CLIP_CNTL_CLIP_MASK__SHIFT 0 3826*cc4c26d4SRob Clark static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_MASK(uint32_t val) 3827*cc4c26d4SRob Clark { 3828*cc4c26d4SRob Clark return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_MASK__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_MASK__MASK; 3829*cc4c26d4SRob Clark } 3830*cc4c26d4SRob Clark #define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00 3831*cc4c26d4SRob Clark #define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8 3832*cc4c26d4SRob Clark static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) 3833*cc4c26d4SRob Clark { 3834*cc4c26d4SRob Clark return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__MASK; 3835*cc4c26d4SRob Clark } 3836*cc4c26d4SRob Clark #define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000 3837*cc4c26d4SRob Clark #define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16 3838*cc4c26d4SRob Clark static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) 3839*cc4c26d4SRob Clark { 3840*cc4c26d4SRob Clark return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; 3841*cc4c26d4SRob Clark } 3842a26ae754SRob Clark 3843a26ae754SRob Clark #define REG_A5XX_VPC_PACK 0x0000e29d 3844a26ae754SRob Clark #define A5XX_VPC_PACK_NUMNONPOSVAR__MASK 0x000000ff 3845a26ae754SRob Clark #define A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT 0 3846a26ae754SRob Clark static inline uint32_t A5XX_VPC_PACK_NUMNONPOSVAR(uint32_t val) 3847a26ae754SRob Clark { 3848a26ae754SRob Clark return ((val) << A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A5XX_VPC_PACK_NUMNONPOSVAR__MASK; 3849a26ae754SRob Clark } 385052260ae4SRob Clark #define A5XX_VPC_PACK_PSIZELOC__MASK 0x0000ff00 385152260ae4SRob Clark #define A5XX_VPC_PACK_PSIZELOC__SHIFT 8 385252260ae4SRob Clark static inline uint32_t A5XX_VPC_PACK_PSIZELOC(uint32_t val) 385352260ae4SRob Clark { 385452260ae4SRob Clark return ((val) << A5XX_VPC_PACK_PSIZELOC__SHIFT) & A5XX_VPC_PACK_PSIZELOC__MASK; 385552260ae4SRob Clark } 3856a26ae754SRob Clark 3857a26ae754SRob Clark #define REG_A5XX_VPC_FS_PRIMITIVEID_CNTL 0x0000e2a0 3858a26ae754SRob Clark 385952260ae4SRob Clark #define REG_A5XX_VPC_SO_BUF_CNTL 0x0000e2a1 386052260ae4SRob Clark #define A5XX_VPC_SO_BUF_CNTL_BUF0 0x00000001 386152260ae4SRob Clark #define A5XX_VPC_SO_BUF_CNTL_BUF1 0x00000008 386252260ae4SRob Clark #define A5XX_VPC_SO_BUF_CNTL_BUF2 0x00000040 386352260ae4SRob Clark #define A5XX_VPC_SO_BUF_CNTL_BUF3 0x00000200 386452260ae4SRob Clark #define A5XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000 3865a26ae754SRob Clark 3866a26ae754SRob Clark #define REG_A5XX_VPC_SO_OVERRIDE 0x0000e2a2 386752260ae4SRob Clark #define A5XX_VPC_SO_OVERRIDE_SO_DISABLE 0x00000001 3868a26ae754SRob Clark 386952260ae4SRob Clark #define REG_A5XX_VPC_SO_CNTL 0x0000e2a3 387052260ae4SRob Clark #define A5XX_VPC_SO_CNTL_ENABLE 0x00010000 3871a26ae754SRob Clark 387252260ae4SRob Clark #define REG_A5XX_VPC_SO_PROG 0x0000e2a4 387352260ae4SRob Clark #define A5XX_VPC_SO_PROG_A_BUF__MASK 0x00000003 387452260ae4SRob Clark #define A5XX_VPC_SO_PROG_A_BUF__SHIFT 0 387552260ae4SRob Clark static inline uint32_t A5XX_VPC_SO_PROG_A_BUF(uint32_t val) 387652260ae4SRob Clark { 387752260ae4SRob Clark return ((val) << A5XX_VPC_SO_PROG_A_BUF__SHIFT) & A5XX_VPC_SO_PROG_A_BUF__MASK; 387852260ae4SRob Clark } 387952260ae4SRob Clark #define A5XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc 388052260ae4SRob Clark #define A5XX_VPC_SO_PROG_A_OFF__SHIFT 2 388152260ae4SRob Clark static inline uint32_t A5XX_VPC_SO_PROG_A_OFF(uint32_t val) 388252260ae4SRob Clark { 388352260ae4SRob Clark return ((val >> 2) << A5XX_VPC_SO_PROG_A_OFF__SHIFT) & A5XX_VPC_SO_PROG_A_OFF__MASK; 388452260ae4SRob Clark } 388552260ae4SRob Clark #define A5XX_VPC_SO_PROG_A_EN 0x00000800 388652260ae4SRob Clark #define A5XX_VPC_SO_PROG_B_BUF__MASK 0x00003000 388752260ae4SRob Clark #define A5XX_VPC_SO_PROG_B_BUF__SHIFT 12 388852260ae4SRob Clark static inline uint32_t A5XX_VPC_SO_PROG_B_BUF(uint32_t val) 388952260ae4SRob Clark { 389052260ae4SRob Clark return ((val) << A5XX_VPC_SO_PROG_B_BUF__SHIFT) & A5XX_VPC_SO_PROG_B_BUF__MASK; 389152260ae4SRob Clark } 389252260ae4SRob Clark #define A5XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000 389352260ae4SRob Clark #define A5XX_VPC_SO_PROG_B_OFF__SHIFT 14 389452260ae4SRob Clark static inline uint32_t A5XX_VPC_SO_PROG_B_OFF(uint32_t val) 389552260ae4SRob Clark { 389652260ae4SRob Clark return ((val >> 2) << A5XX_VPC_SO_PROG_B_OFF__SHIFT) & A5XX_VPC_SO_PROG_B_OFF__MASK; 389752260ae4SRob Clark } 389852260ae4SRob Clark #define A5XX_VPC_SO_PROG_B_EN 0x00800000 3899a26ae754SRob Clark 390052260ae4SRob Clark static inline uint32_t REG_A5XX_VPC_SO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; } 3901a26ae754SRob Clark 390252260ae4SRob Clark static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; } 3903a26ae754SRob Clark 390452260ae4SRob Clark static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000e2a8 + 0x7*i0; } 3905a26ae754SRob Clark 390652260ae4SRob Clark static inline uint32_t REG_A5XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000e2a9 + 0x7*i0; } 3907a26ae754SRob Clark 390852260ae4SRob Clark static inline uint32_t REG_A5XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000e2aa + 0x7*i0; } 3909a26ae754SRob Clark 391052260ae4SRob Clark static inline uint32_t REG_A5XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000e2ab + 0x7*i0; } 3911a26ae754SRob Clark 391252260ae4SRob Clark static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000e2ac + 0x7*i0; } 3913a26ae754SRob Clark 391452260ae4SRob Clark static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x0000e2ad + 0x7*i0; } 3915a26ae754SRob Clark 3916a26ae754SRob Clark #define REG_A5XX_PC_PRIMITIVE_CNTL 0x0000e384 3917a26ae754SRob Clark #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK 0x0000007f 3918a26ae754SRob Clark #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT 0 3919a26ae754SRob Clark static inline uint32_t A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val) 3920a26ae754SRob Clark { 3921a26ae754SRob Clark return ((val) << A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT) & A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK; 3922a26ae754SRob Clark } 39232d756322SRob Clark #define A5XX_PC_PRIMITIVE_CNTL_PRIMITIVE_RESTART 0x00000100 39242d756322SRob Clark #define A5XX_PC_PRIMITIVE_CNTL_COUNT_PRIMITIVES 0x00000200 392552260ae4SRob Clark #define A5XX_PC_PRIMITIVE_CNTL_PROVOKING_VTX_LAST 0x00000400 3926a26ae754SRob Clark 3927a26ae754SRob Clark #define REG_A5XX_PC_PRIM_VTX_CNTL 0x0000e385 3928a26ae754SRob Clark #define A5XX_PC_PRIM_VTX_CNTL_PSIZE 0x00000800 3929a26ae754SRob Clark 3930a26ae754SRob Clark #define REG_A5XX_PC_RASTER_CNTL 0x0000e388 39312d756322SRob Clark #define A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__MASK 0x00000007 39322d756322SRob Clark #define A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__SHIFT 0 39332d756322SRob Clark static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 39342d756322SRob Clark { 39352d756322SRob Clark return ((val) << A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__MASK; 39362d756322SRob Clark } 39372d756322SRob Clark #define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK 0x00000038 39382d756322SRob Clark #define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__SHIFT 3 39392d756322SRob Clark static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 39402d756322SRob Clark { 39412d756322SRob Clark return ((val) << A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK; 39422d756322SRob Clark } 39432d756322SRob Clark #define A5XX_PC_RASTER_CNTL_POLYMODE_ENABLE 0x00000040 3944a26ae754SRob Clark 3945*cc4c26d4SRob Clark #define REG_A5XX_PC_CLIP_CNTL 0x0000e389 3946*cc4c26d4SRob Clark #define A5XX_PC_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff 3947*cc4c26d4SRob Clark #define A5XX_PC_CLIP_CNTL_CLIP_MASK__SHIFT 0 3948*cc4c26d4SRob Clark static inline uint32_t A5XX_PC_CLIP_CNTL_CLIP_MASK(uint32_t val) 3949*cc4c26d4SRob Clark { 3950*cc4c26d4SRob Clark return ((val) << A5XX_PC_CLIP_CNTL_CLIP_MASK__SHIFT) & A5XX_PC_CLIP_CNTL_CLIP_MASK__MASK; 3951*cc4c26d4SRob Clark } 3952a26ae754SRob Clark 3953a26ae754SRob Clark #define REG_A5XX_PC_RESTART_INDEX 0x0000e38c 3954a26ae754SRob Clark 39552d756322SRob Clark #define REG_A5XX_PC_GS_LAYERED 0x0000e38d 3956a26ae754SRob Clark 3957a26ae754SRob Clark #define REG_A5XX_PC_GS_PARAM 0x0000e38e 39582d756322SRob Clark #define A5XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff 39592d756322SRob Clark #define A5XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0 39602d756322SRob Clark static inline uint32_t A5XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val) 39612d756322SRob Clark { 39622d756322SRob Clark return ((val) << A5XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A5XX_PC_GS_PARAM_MAX_VERTICES__MASK; 39632d756322SRob Clark } 39642d756322SRob Clark #define A5XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800 39652d756322SRob Clark #define A5XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11 39662d756322SRob Clark static inline uint32_t A5XX_PC_GS_PARAM_INVOCATIONS(uint32_t val) 39672d756322SRob Clark { 39682d756322SRob Clark return ((val) << A5XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A5XX_PC_GS_PARAM_INVOCATIONS__MASK; 39692d756322SRob Clark } 39702d756322SRob Clark #define A5XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000 39712d756322SRob Clark #define A5XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23 39722d756322SRob Clark static inline uint32_t A5XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val) 39732d756322SRob Clark { 39742d756322SRob Clark return ((val) << A5XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A5XX_PC_GS_PARAM_PRIMTYPE__MASK; 39752d756322SRob Clark } 3976a26ae754SRob Clark 3977a26ae754SRob Clark #define REG_A5XX_PC_HS_PARAM 0x0000e38f 39782d756322SRob Clark #define A5XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f 39792d756322SRob Clark #define A5XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0 39802d756322SRob Clark static inline uint32_t A5XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val) 39812d756322SRob Clark { 39822d756322SRob Clark return ((val) << A5XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A5XX_PC_HS_PARAM_VERTICES_OUT__MASK; 39832d756322SRob Clark } 39842d756322SRob Clark #define A5XX_PC_HS_PARAM_SPACING__MASK 0x00600000 39852d756322SRob Clark #define A5XX_PC_HS_PARAM_SPACING__SHIFT 21 39862d756322SRob Clark static inline uint32_t A5XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val) 39872d756322SRob Clark { 39882d756322SRob Clark return ((val) << A5XX_PC_HS_PARAM_SPACING__SHIFT) & A5XX_PC_HS_PARAM_SPACING__MASK; 39892d756322SRob Clark } 39902d756322SRob Clark #define A5XX_PC_HS_PARAM_CW 0x00800000 39912d756322SRob Clark #define A5XX_PC_HS_PARAM_CONNECTED 0x01000000 3992a26ae754SRob Clark 3993a26ae754SRob Clark #define REG_A5XX_PC_POWER_CNTL 0x0000e3b0 3994a26ae754SRob Clark 3995a26ae754SRob Clark #define REG_A5XX_VFD_CONTROL_0 0x0000e400 3996a26ae754SRob Clark #define A5XX_VFD_CONTROL_0_VTXCNT__MASK 0x0000003f 3997a26ae754SRob Clark #define A5XX_VFD_CONTROL_0_VTXCNT__SHIFT 0 3998a26ae754SRob Clark static inline uint32_t A5XX_VFD_CONTROL_0_VTXCNT(uint32_t val) 3999a26ae754SRob Clark { 4000a26ae754SRob Clark return ((val) << A5XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A5XX_VFD_CONTROL_0_VTXCNT__MASK; 4001a26ae754SRob Clark } 4002a26ae754SRob Clark 4003a26ae754SRob Clark #define REG_A5XX_VFD_CONTROL_1 0x0000e401 400452260ae4SRob Clark #define A5XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff 400552260ae4SRob Clark #define A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0 400652260ae4SRob Clark static inline uint32_t A5XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 400752260ae4SRob Clark { 400852260ae4SRob Clark return ((val) << A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A5XX_VFD_CONTROL_1_REGID4VTX__MASK; 400952260ae4SRob Clark } 4010a26ae754SRob Clark #define A5XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00 4011a26ae754SRob Clark #define A5XX_VFD_CONTROL_1_REGID4INST__SHIFT 8 4012a26ae754SRob Clark static inline uint32_t A5XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 4013a26ae754SRob Clark { 4014a26ae754SRob Clark return ((val) << A5XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A5XX_VFD_CONTROL_1_REGID4INST__MASK; 4015a26ae754SRob Clark } 40162d756322SRob Clark #define A5XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000 40172d756322SRob Clark #define A5XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16 40182d756322SRob Clark static inline uint32_t A5XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val) 40192d756322SRob Clark { 40202d756322SRob Clark return ((val) << A5XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A5XX_VFD_CONTROL_1_REGID4PRIMID__MASK; 40212d756322SRob Clark } 4022a26ae754SRob Clark 4023a26ae754SRob Clark #define REG_A5XX_VFD_CONTROL_2 0x0000e402 40242d756322SRob Clark #define A5XX_VFD_CONTROL_2_REGID_PATCHID__MASK 0x000000ff 40252d756322SRob Clark #define A5XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT 0 40262d756322SRob Clark static inline uint32_t A5XX_VFD_CONTROL_2_REGID_PATCHID(uint32_t val) 40272d756322SRob Clark { 40282d756322SRob Clark return ((val) << A5XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT) & A5XX_VFD_CONTROL_2_REGID_PATCHID__MASK; 40292d756322SRob Clark } 4030a26ae754SRob Clark 4031a26ae754SRob Clark #define REG_A5XX_VFD_CONTROL_3 0x0000e403 40322d756322SRob Clark #define A5XX_VFD_CONTROL_3_REGID_PATCHID__MASK 0x0000ff00 40332d756322SRob Clark #define A5XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT 8 40342d756322SRob Clark static inline uint32_t A5XX_VFD_CONTROL_3_REGID_PATCHID(uint32_t val) 40352d756322SRob Clark { 40362d756322SRob Clark return ((val) << A5XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT) & A5XX_VFD_CONTROL_3_REGID_PATCHID__MASK; 40372d756322SRob Clark } 40382d756322SRob Clark #define A5XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000 40392d756322SRob Clark #define A5XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16 40402d756322SRob Clark static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) 40412d756322SRob Clark { 40422d756322SRob Clark return ((val) << A5XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A5XX_VFD_CONTROL_3_REGID_TESSX__MASK; 40432d756322SRob Clark } 40442d756322SRob Clark #define A5XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000 40452d756322SRob Clark #define A5XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24 40462d756322SRob Clark static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) 40472d756322SRob Clark { 40482d756322SRob Clark return ((val) << A5XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A5XX_VFD_CONTROL_3_REGID_TESSY__MASK; 40492d756322SRob Clark } 4050a26ae754SRob Clark 4051a26ae754SRob Clark #define REG_A5XX_VFD_CONTROL_4 0x0000e404 4052a26ae754SRob Clark 4053a26ae754SRob Clark #define REG_A5XX_VFD_CONTROL_5 0x0000e405 4054a26ae754SRob Clark 4055a26ae754SRob Clark #define REG_A5XX_VFD_INDEX_OFFSET 0x0000e408 4056a26ae754SRob Clark 4057a26ae754SRob Clark #define REG_A5XX_VFD_INSTANCE_START_OFFSET 0x0000e409 4058a26ae754SRob Clark 4059a26ae754SRob Clark static inline uint32_t REG_A5XX_VFD_FETCH(uint32_t i0) { return 0x0000e40a + 0x4*i0; } 4060a26ae754SRob Clark 4061a26ae754SRob Clark static inline uint32_t REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000e40a + 0x4*i0; } 4062a26ae754SRob Clark 4063a26ae754SRob Clark static inline uint32_t REG_A5XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000e40b + 0x4*i0; } 4064a26ae754SRob Clark 4065a26ae754SRob Clark static inline uint32_t REG_A5XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000e40c + 0x4*i0; } 4066a26ae754SRob Clark 4067a26ae754SRob Clark static inline uint32_t REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000e40d + 0x4*i0; } 4068a26ae754SRob Clark 4069a26ae754SRob Clark static inline uint32_t REG_A5XX_VFD_DECODE(uint32_t i0) { return 0x0000e48a + 0x2*i0; } 4070a26ae754SRob Clark 4071a26ae754SRob Clark static inline uint32_t REG_A5XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000e48a + 0x2*i0; } 4072a26ae754SRob Clark #define A5XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f 4073a26ae754SRob Clark #define A5XX_VFD_DECODE_INSTR_IDX__SHIFT 0 4074a26ae754SRob Clark static inline uint32_t A5XX_VFD_DECODE_INSTR_IDX(uint32_t val) 4075a26ae754SRob Clark { 4076a26ae754SRob Clark return ((val) << A5XX_VFD_DECODE_INSTR_IDX__SHIFT) & A5XX_VFD_DECODE_INSTR_IDX__MASK; 4077a26ae754SRob Clark } 407852260ae4SRob Clark #define A5XX_VFD_DECODE_INSTR_INSTANCED 0x00020000 40792d756322SRob Clark #define A5XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000 4080a26ae754SRob Clark #define A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20 4081a26ae754SRob Clark static inline uint32_t A5XX_VFD_DECODE_INSTR_FORMAT(enum a5xx_vtx_fmt val) 4082a26ae754SRob Clark { 4083a26ae754SRob Clark return ((val) << A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A5XX_VFD_DECODE_INSTR_FORMAT__MASK; 4084a26ae754SRob Clark } 40852d756322SRob Clark #define A5XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000 40862d756322SRob Clark #define A5XX_VFD_DECODE_INSTR_SWAP__SHIFT 28 40872d756322SRob Clark static inline uint32_t A5XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 40882d756322SRob Clark { 40892d756322SRob Clark return ((val) << A5XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A5XX_VFD_DECODE_INSTR_SWAP__MASK; 40902d756322SRob Clark } 409152260ae4SRob Clark #define A5XX_VFD_DECODE_INSTR_UNK30 0x40000000 409252260ae4SRob Clark #define A5XX_VFD_DECODE_INSTR_FLOAT 0x80000000 4093a26ae754SRob Clark 4094a26ae754SRob Clark static inline uint32_t REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000e48b + 0x2*i0; } 4095a26ae754SRob Clark 4096a26ae754SRob Clark static inline uint32_t REG_A5XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000e4ca + 0x1*i0; } 4097a26ae754SRob Clark 4098a26ae754SRob Clark static inline uint32_t REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000e4ca + 0x1*i0; } 4099a26ae754SRob Clark #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f 4100a26ae754SRob Clark #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0 4101a26ae754SRob Clark static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val) 4102a26ae754SRob Clark { 4103a26ae754SRob Clark return ((val) << A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK; 4104a26ae754SRob Clark } 4105a26ae754SRob Clark #define A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0 4106a26ae754SRob Clark #define A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4 4107a26ae754SRob Clark static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) 4108a26ae754SRob Clark { 4109a26ae754SRob Clark return ((val) << A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK; 4110a26ae754SRob Clark } 4111a26ae754SRob Clark 4112a26ae754SRob Clark #define REG_A5XX_VFD_POWER_CNTL 0x0000e4f0 4113a26ae754SRob Clark 4114a26ae754SRob Clark #define REG_A5XX_SP_SP_CNTL 0x0000e580 4115a26ae754SRob Clark 411652260ae4SRob Clark #define REG_A5XX_SP_VS_CONFIG 0x0000e584 411752260ae4SRob Clark #define A5XX_SP_VS_CONFIG_ENABLED 0x00000001 411852260ae4SRob Clark #define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 411952260ae4SRob Clark #define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 412052260ae4SRob Clark static inline uint32_t A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 4121a26ae754SRob Clark { 412252260ae4SRob Clark return ((val) << A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK; 4123a26ae754SRob Clark } 412452260ae4SRob Clark #define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 412552260ae4SRob Clark #define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT 8 412652260ae4SRob Clark static inline uint32_t A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(uint32_t val) 4127a26ae754SRob Clark { 412852260ae4SRob Clark return ((val) << A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK; 4129a26ae754SRob Clark } 4130a26ae754SRob Clark 413152260ae4SRob Clark #define REG_A5XX_SP_FS_CONFIG 0x0000e585 413252260ae4SRob Clark #define A5XX_SP_FS_CONFIG_ENABLED 0x00000001 413352260ae4SRob Clark #define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 413452260ae4SRob Clark #define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 413552260ae4SRob Clark static inline uint32_t A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 4136a26ae754SRob Clark { 413752260ae4SRob Clark return ((val) << A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK; 4138a26ae754SRob Clark } 413952260ae4SRob Clark #define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 414052260ae4SRob Clark #define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT 8 414152260ae4SRob Clark static inline uint32_t A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(uint32_t val) 4142a26ae754SRob Clark { 414352260ae4SRob Clark return ((val) << A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK; 4144a26ae754SRob Clark } 4145a26ae754SRob Clark 414652260ae4SRob Clark #define REG_A5XX_SP_HS_CONFIG 0x0000e586 414752260ae4SRob Clark #define A5XX_SP_HS_CONFIG_ENABLED 0x00000001 414852260ae4SRob Clark #define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 414952260ae4SRob Clark #define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 415052260ae4SRob Clark static inline uint32_t A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 4151a26ae754SRob Clark { 415252260ae4SRob Clark return ((val) << A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK; 4153a26ae754SRob Clark } 415452260ae4SRob Clark #define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 415552260ae4SRob Clark #define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT 8 415652260ae4SRob Clark static inline uint32_t A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(uint32_t val) 4157a26ae754SRob Clark { 415852260ae4SRob Clark return ((val) << A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK; 4159a26ae754SRob Clark } 4160a26ae754SRob Clark 416152260ae4SRob Clark #define REG_A5XX_SP_DS_CONFIG 0x0000e587 416252260ae4SRob Clark #define A5XX_SP_DS_CONFIG_ENABLED 0x00000001 416352260ae4SRob Clark #define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 416452260ae4SRob Clark #define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 416552260ae4SRob Clark static inline uint32_t A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 4166a26ae754SRob Clark { 416752260ae4SRob Clark return ((val) << A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK; 4168a26ae754SRob Clark } 416952260ae4SRob Clark #define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 417052260ae4SRob Clark #define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT 8 417152260ae4SRob Clark static inline uint32_t A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(uint32_t val) 4172a26ae754SRob Clark { 417352260ae4SRob Clark return ((val) << A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK; 4174a26ae754SRob Clark } 4175a26ae754SRob Clark 417652260ae4SRob Clark #define REG_A5XX_SP_GS_CONFIG 0x0000e588 417752260ae4SRob Clark #define A5XX_SP_GS_CONFIG_ENABLED 0x00000001 417852260ae4SRob Clark #define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 417952260ae4SRob Clark #define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 418052260ae4SRob Clark static inline uint32_t A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 4181a26ae754SRob Clark { 418252260ae4SRob Clark return ((val) << A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK; 4183a26ae754SRob Clark } 418452260ae4SRob Clark #define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 418552260ae4SRob Clark #define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT 8 418652260ae4SRob Clark static inline uint32_t A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(uint32_t val) 4187a26ae754SRob Clark { 418852260ae4SRob Clark return ((val) << A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK; 4189a26ae754SRob Clark } 4190a26ae754SRob Clark 4191a26ae754SRob Clark #define REG_A5XX_SP_CS_CONFIG 0x0000e589 419252260ae4SRob Clark #define A5XX_SP_CS_CONFIG_ENABLED 0x00000001 419352260ae4SRob Clark #define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 419452260ae4SRob Clark #define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 419552260ae4SRob Clark static inline uint32_t A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 419652260ae4SRob Clark { 419752260ae4SRob Clark return ((val) << A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK; 419852260ae4SRob Clark } 419952260ae4SRob Clark #define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 420052260ae4SRob Clark #define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT 8 420152260ae4SRob Clark static inline uint32_t A5XX_SP_CS_CONFIG_SHADEROBJOFFSET(uint32_t val) 420252260ae4SRob Clark { 420352260ae4SRob Clark return ((val) << A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK; 420452260ae4SRob Clark } 4205a26ae754SRob Clark 4206a26ae754SRob Clark #define REG_A5XX_SP_VS_CONFIG_MAX_CONST 0x0000e58a 4207a26ae754SRob Clark 4208a26ae754SRob Clark #define REG_A5XX_SP_FS_CONFIG_MAX_CONST 0x0000e58b 4209a26ae754SRob Clark 4210a26ae754SRob Clark #define REG_A5XX_SP_VS_CTRL_REG0 0x0000e590 421152260ae4SRob Clark #define A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00000008 421252260ae4SRob Clark #define A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 3 421352260ae4SRob Clark static inline uint32_t A5XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 421452260ae4SRob Clark { 421552260ae4SRob Clark return ((val) << A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; 421652260ae4SRob Clark } 4217a26ae754SRob Clark #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 4218a26ae754SRob Clark #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 4219a26ae754SRob Clark static inline uint32_t A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 4220a26ae754SRob Clark { 4221a26ae754SRob Clark return ((val) << A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 4222a26ae754SRob Clark } 4223a26ae754SRob Clark #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 4224a26ae754SRob Clark #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 4225a26ae754SRob Clark static inline uint32_t A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 4226a26ae754SRob Clark { 4227a26ae754SRob Clark return ((val) << A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 4228a26ae754SRob Clark } 4229a26ae754SRob Clark #define A5XX_SP_VS_CTRL_REG0_VARYING 0x00010000 4230a26ae754SRob Clark #define A5XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00100000 423152260ae4SRob Clark #define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000 423252260ae4SRob Clark #define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 25 423352260ae4SRob Clark static inline uint32_t A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val) 423452260ae4SRob Clark { 423552260ae4SRob Clark return ((val) << A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK; 423652260ae4SRob Clark } 4237a26ae754SRob Clark 4238a26ae754SRob Clark #define REG_A5XX_SP_PRIMITIVE_CNTL 0x0000e592 423952260ae4SRob Clark #define A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK 0x0000001f 424052260ae4SRob Clark #define A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT 0 424152260ae4SRob Clark static inline uint32_t A5XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val) 4242a26ae754SRob Clark { 424352260ae4SRob Clark return ((val) << A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT) & A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK; 4244a26ae754SRob Clark } 4245a26ae754SRob Clark 4246a26ae754SRob Clark static inline uint32_t REG_A5XX_SP_VS_OUT(uint32_t i0) { return 0x0000e593 + 0x1*i0; } 4247a26ae754SRob Clark 4248a26ae754SRob Clark static inline uint32_t REG_A5XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000e593 + 0x1*i0; } 4249a26ae754SRob Clark #define A5XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff 4250a26ae754SRob Clark #define A5XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 4251a26ae754SRob Clark static inline uint32_t A5XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 4252a26ae754SRob Clark { 4253a26ae754SRob Clark return ((val) << A5XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_A_REGID__MASK; 4254a26ae754SRob Clark } 4255a26ae754SRob Clark #define A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00 4256a26ae754SRob Clark #define A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8 4257a26ae754SRob Clark static inline uint32_t A5XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 4258a26ae754SRob Clark { 4259a26ae754SRob Clark return ((val) << A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 4260a26ae754SRob Clark } 4261a26ae754SRob Clark #define A5XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000 4262a26ae754SRob Clark #define A5XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 4263a26ae754SRob Clark static inline uint32_t A5XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 4264a26ae754SRob Clark { 4265a26ae754SRob Clark return ((val) << A5XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_B_REGID__MASK; 4266a26ae754SRob Clark } 4267a26ae754SRob Clark #define A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000 4268a26ae754SRob Clark #define A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24 4269a26ae754SRob Clark static inline uint32_t A5XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 4270a26ae754SRob Clark { 4271a26ae754SRob Clark return ((val) << A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 4272a26ae754SRob Clark } 4273a26ae754SRob Clark 4274a26ae754SRob Clark static inline uint32_t REG_A5XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; } 4275a26ae754SRob Clark 4276a26ae754SRob Clark static inline uint32_t REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; } 4277a26ae754SRob Clark #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 4278a26ae754SRob Clark #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 4279a26ae754SRob Clark static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 4280a26ae754SRob Clark { 4281a26ae754SRob Clark return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 4282a26ae754SRob Clark } 4283a26ae754SRob Clark #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 4284a26ae754SRob Clark #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 4285a26ae754SRob Clark static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 4286a26ae754SRob Clark { 4287a26ae754SRob Clark return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 4288a26ae754SRob Clark } 4289a26ae754SRob Clark #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 4290a26ae754SRob Clark #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 4291a26ae754SRob Clark static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 4292a26ae754SRob Clark { 4293a26ae754SRob Clark return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 4294a26ae754SRob Clark } 4295a26ae754SRob Clark #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 4296a26ae754SRob Clark #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 4297a26ae754SRob Clark static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 4298a26ae754SRob Clark { 4299a26ae754SRob Clark return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 4300a26ae754SRob Clark } 4301a26ae754SRob Clark 4302a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E5AB 0x0000e5ab 4303a26ae754SRob Clark 4304a26ae754SRob Clark #define REG_A5XX_SP_VS_OBJ_START_LO 0x0000e5ac 4305a26ae754SRob Clark 4306a26ae754SRob Clark #define REG_A5XX_SP_VS_OBJ_START_HI 0x0000e5ad 4307a26ae754SRob Clark 4308a26ae754SRob Clark #define REG_A5XX_SP_FS_CTRL_REG0 0x0000e5c0 430952260ae4SRob Clark #define A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00000008 431052260ae4SRob Clark #define A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 3 431152260ae4SRob Clark static inline uint32_t A5XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 431252260ae4SRob Clark { 431352260ae4SRob Clark return ((val) << A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 431452260ae4SRob Clark } 4315a26ae754SRob Clark #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 4316a26ae754SRob Clark #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 4317a26ae754SRob Clark static inline uint32_t A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 4318a26ae754SRob Clark { 4319a26ae754SRob Clark return ((val) << A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 4320a26ae754SRob Clark } 4321a26ae754SRob Clark #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 4322a26ae754SRob Clark #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 4323a26ae754SRob Clark static inline uint32_t A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 4324a26ae754SRob Clark { 4325a26ae754SRob Clark return ((val) << A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 4326a26ae754SRob Clark } 4327a26ae754SRob Clark #define A5XX_SP_FS_CTRL_REG0_VARYING 0x00010000 4328a26ae754SRob Clark #define A5XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00100000 432952260ae4SRob Clark #define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000 433052260ae4SRob Clark #define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 25 433152260ae4SRob Clark static inline uint32_t A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) 433252260ae4SRob Clark { 433352260ae4SRob Clark return ((val) << A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK; 433452260ae4SRob Clark } 4335a26ae754SRob Clark 4336a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E5C2 0x0000e5c2 4337a26ae754SRob Clark 4338a26ae754SRob Clark #define REG_A5XX_SP_FS_OBJ_START_LO 0x0000e5c3 4339a26ae754SRob Clark 4340a26ae754SRob Clark #define REG_A5XX_SP_FS_OBJ_START_HI 0x0000e5c4 4341a26ae754SRob Clark 4342a26ae754SRob Clark #define REG_A5XX_SP_BLEND_CNTL 0x0000e5c9 4343*cc4c26d4SRob Clark #define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff 4344*cc4c26d4SRob Clark #define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 4345*cc4c26d4SRob Clark static inline uint32_t A5XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val) 4346*cc4c26d4SRob Clark { 4347*cc4c26d4SRob Clark return ((val) << A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK; 4348*cc4c26d4SRob Clark } 434952260ae4SRob Clark #define A5XX_SP_BLEND_CNTL_UNK8 0x00000100 43502d756322SRob Clark #define A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 4351a26ae754SRob Clark 4352a26ae754SRob Clark #define REG_A5XX_SP_FS_OUTPUT_CNTL 0x0000e5ca 4353a26ae754SRob Clark #define A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f 4354a26ae754SRob Clark #define A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT 0 4355a26ae754SRob Clark static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_MRT(uint32_t val) 4356a26ae754SRob Clark { 4357a26ae754SRob Clark return ((val) << A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK; 4358a26ae754SRob Clark } 4359a26ae754SRob Clark #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK 0x00001fe0 4360a26ae754SRob Clark #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT 5 4361a26ae754SRob Clark static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(uint32_t val) 4362a26ae754SRob Clark { 4363a26ae754SRob Clark return ((val) << A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK; 4364a26ae754SRob Clark } 4365a26ae754SRob Clark #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK 0x001fe000 4366a26ae754SRob Clark #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT 13 4367a26ae754SRob Clark static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(uint32_t val) 4368a26ae754SRob Clark { 4369a26ae754SRob Clark return ((val) << A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK; 4370a26ae754SRob Clark } 4371a26ae754SRob Clark 4372a26ae754SRob Clark static inline uint32_t REG_A5XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000e5cb + 0x1*i0; } 4373a26ae754SRob Clark 4374a26ae754SRob Clark static inline uint32_t REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000e5cb + 0x1*i0; } 4375a26ae754SRob Clark #define A5XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff 4376a26ae754SRob Clark #define A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0 4377a26ae754SRob Clark static inline uint32_t A5XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) 4378a26ae754SRob Clark { 4379a26ae754SRob Clark return ((val) << A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_REG_REGID__MASK; 4380a26ae754SRob Clark } 4381a26ae754SRob Clark #define A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100 4382a26ae754SRob Clark 4383a26ae754SRob Clark static inline uint32_t REG_A5XX_SP_FS_MRT(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; } 4384a26ae754SRob Clark 4385a26ae754SRob Clark static inline uint32_t REG_A5XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; } 4386a26ae754SRob Clark #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff 4387a26ae754SRob Clark #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0 4388a26ae754SRob Clark static inline uint32_t A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val) 4389a26ae754SRob Clark { 4390a26ae754SRob Clark return ((val) << A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK; 4391a26ae754SRob Clark } 43922d756322SRob Clark #define A5XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100 43932d756322SRob Clark #define A5XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200 439452260ae4SRob Clark #define A5XX_SP_FS_MRT_REG_COLOR_SRGB 0x00000400 4395a26ae754SRob Clark 4396a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E5DB 0x0000e5db 4397a26ae754SRob Clark 439852260ae4SRob Clark #define REG_A5XX_SP_CS_CTRL_REG0 0x0000e5f0 439952260ae4SRob Clark #define A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00000008 440052260ae4SRob Clark #define A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 3 440152260ae4SRob Clark static inline uint32_t A5XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 440252260ae4SRob Clark { 440352260ae4SRob Clark return ((val) << A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK; 440452260ae4SRob Clark } 440552260ae4SRob Clark #define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 440652260ae4SRob Clark #define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 440752260ae4SRob Clark static inline uint32_t A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 440852260ae4SRob Clark { 440952260ae4SRob Clark return ((val) << A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 441052260ae4SRob Clark } 441152260ae4SRob Clark #define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 441252260ae4SRob Clark #define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 441352260ae4SRob Clark static inline uint32_t A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 441452260ae4SRob Clark { 441552260ae4SRob Clark return ((val) << A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 441652260ae4SRob Clark } 441752260ae4SRob Clark #define A5XX_SP_CS_CTRL_REG0_VARYING 0x00010000 441852260ae4SRob Clark #define A5XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x00100000 441952260ae4SRob Clark #define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000 442052260ae4SRob Clark #define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 25 442152260ae4SRob Clark static inline uint32_t A5XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val) 442252260ae4SRob Clark { 442352260ae4SRob Clark return ((val) << A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK; 442452260ae4SRob Clark } 4425a26ae754SRob Clark 44262d756322SRob Clark #define REG_A5XX_UNKNOWN_E5F2 0x0000e5f2 44272d756322SRob Clark 44282d756322SRob Clark #define REG_A5XX_SP_CS_OBJ_START_LO 0x0000e5f3 44292d756322SRob Clark 44302d756322SRob Clark #define REG_A5XX_SP_CS_OBJ_START_HI 0x0000e5f4 44312d756322SRob Clark 44322d756322SRob Clark #define REG_A5XX_SP_HS_CTRL_REG0 0x0000e600 44332d756322SRob Clark #define A5XX_SP_HS_CTRL_REG0_THREADSIZE__MASK 0x00000008 44342d756322SRob Clark #define A5XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT 3 44352d756322SRob Clark static inline uint32_t A5XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 44362d756322SRob Clark { 44372d756322SRob Clark return ((val) << A5XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_HS_CTRL_REG0_THREADSIZE__MASK; 44382d756322SRob Clark } 44392d756322SRob Clark #define A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 44402d756322SRob Clark #define A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 44412d756322SRob Clark static inline uint32_t A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 44422d756322SRob Clark { 44432d756322SRob Clark return ((val) << A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 44442d756322SRob Clark } 44452d756322SRob Clark #define A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 44462d756322SRob Clark #define A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 44472d756322SRob Clark static inline uint32_t A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 44482d756322SRob Clark { 44492d756322SRob Clark return ((val) << A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 44502d756322SRob Clark } 44512d756322SRob Clark #define A5XX_SP_HS_CTRL_REG0_VARYING 0x00010000 44522d756322SRob Clark #define A5XX_SP_HS_CTRL_REG0_PIXLODENABLE 0x00100000 44532d756322SRob Clark #define A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000 44542d756322SRob Clark #define A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 25 44552d756322SRob Clark static inline uint32_t A5XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val) 44562d756322SRob Clark { 44572d756322SRob Clark return ((val) << A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK; 44582d756322SRob Clark } 4459a26ae754SRob Clark 446052260ae4SRob Clark #define REG_A5XX_UNKNOWN_E602 0x0000e602 446152260ae4SRob Clark 446252260ae4SRob Clark #define REG_A5XX_SP_HS_OBJ_START_LO 0x0000e603 446352260ae4SRob Clark 446452260ae4SRob Clark #define REG_A5XX_SP_HS_OBJ_START_HI 0x0000e604 446552260ae4SRob Clark 44662d756322SRob Clark #define REG_A5XX_SP_DS_CTRL_REG0 0x0000e610 44672d756322SRob Clark #define A5XX_SP_DS_CTRL_REG0_THREADSIZE__MASK 0x00000008 44682d756322SRob Clark #define A5XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT 3 44692d756322SRob Clark static inline uint32_t A5XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 44702d756322SRob Clark { 44712d756322SRob Clark return ((val) << A5XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_DS_CTRL_REG0_THREADSIZE__MASK; 44722d756322SRob Clark } 44732d756322SRob Clark #define A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 44742d756322SRob Clark #define A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 44752d756322SRob Clark static inline uint32_t A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 44762d756322SRob Clark { 44772d756322SRob Clark return ((val) << A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 44782d756322SRob Clark } 44792d756322SRob Clark #define A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 44802d756322SRob Clark #define A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 44812d756322SRob Clark static inline uint32_t A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 44822d756322SRob Clark { 44832d756322SRob Clark return ((val) << A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 44842d756322SRob Clark } 44852d756322SRob Clark #define A5XX_SP_DS_CTRL_REG0_VARYING 0x00010000 44862d756322SRob Clark #define A5XX_SP_DS_CTRL_REG0_PIXLODENABLE 0x00100000 44872d756322SRob Clark #define A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000 44882d756322SRob Clark #define A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 25 44892d756322SRob Clark static inline uint32_t A5XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val) 44902d756322SRob Clark { 44912d756322SRob Clark return ((val) << A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK; 44922d756322SRob Clark } 44932d756322SRob Clark 449452260ae4SRob Clark #define REG_A5XX_UNKNOWN_E62B 0x0000e62b 449552260ae4SRob Clark 449652260ae4SRob Clark #define REG_A5XX_SP_DS_OBJ_START_LO 0x0000e62c 449752260ae4SRob Clark 449852260ae4SRob Clark #define REG_A5XX_SP_DS_OBJ_START_HI 0x0000e62d 449952260ae4SRob Clark 45002d756322SRob Clark #define REG_A5XX_SP_GS_CTRL_REG0 0x0000e640 45012d756322SRob Clark #define A5XX_SP_GS_CTRL_REG0_THREADSIZE__MASK 0x00000008 45022d756322SRob Clark #define A5XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT 3 45032d756322SRob Clark static inline uint32_t A5XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 45042d756322SRob Clark { 45052d756322SRob Clark return ((val) << A5XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_GS_CTRL_REG0_THREADSIZE__MASK; 45062d756322SRob Clark } 45072d756322SRob Clark #define A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 45082d756322SRob Clark #define A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 45092d756322SRob Clark static inline uint32_t A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 45102d756322SRob Clark { 45112d756322SRob Clark return ((val) << A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 45122d756322SRob Clark } 45132d756322SRob Clark #define A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 45142d756322SRob Clark #define A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 45152d756322SRob Clark static inline uint32_t A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 45162d756322SRob Clark { 45172d756322SRob Clark return ((val) << A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 45182d756322SRob Clark } 45192d756322SRob Clark #define A5XX_SP_GS_CTRL_REG0_VARYING 0x00010000 45202d756322SRob Clark #define A5XX_SP_GS_CTRL_REG0_PIXLODENABLE 0x00100000 45212d756322SRob Clark #define A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000 45222d756322SRob Clark #define A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 25 45232d756322SRob Clark static inline uint32_t A5XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val) 45242d756322SRob Clark { 45252d756322SRob Clark return ((val) << A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK; 45262d756322SRob Clark } 4527a26ae754SRob Clark 452852260ae4SRob Clark #define REG_A5XX_UNKNOWN_E65B 0x0000e65b 452952260ae4SRob Clark 453052260ae4SRob Clark #define REG_A5XX_SP_GS_OBJ_START_LO 0x0000e65c 453152260ae4SRob Clark 453252260ae4SRob Clark #define REG_A5XX_SP_GS_OBJ_START_HI 0x0000e65d 453352260ae4SRob Clark 4534a26ae754SRob Clark #define REG_A5XX_TPL1_TP_RAS_MSAA_CNTL 0x0000e704 4535a26ae754SRob Clark #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 4536a26ae754SRob Clark #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 4537a26ae754SRob Clark static inline uint32_t A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 4538a26ae754SRob Clark { 4539a26ae754SRob Clark return ((val) << A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK; 4540a26ae754SRob Clark } 4541a26ae754SRob Clark 4542a26ae754SRob Clark #define REG_A5XX_TPL1_TP_DEST_MSAA_CNTL 0x0000e705 4543a26ae754SRob Clark #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 4544a26ae754SRob Clark #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 4545a26ae754SRob Clark static inline uint32_t A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 4546a26ae754SRob Clark { 4547a26ae754SRob Clark return ((val) << A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK; 4548a26ae754SRob Clark } 4549a26ae754SRob Clark #define A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 4550a26ae754SRob Clark 455152260ae4SRob Clark #define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO 0x0000e706 455252260ae4SRob Clark 455352260ae4SRob Clark #define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_HI 0x0000e707 455452260ae4SRob Clark 4555a26ae754SRob Clark #define REG_A5XX_TPL1_VS_TEX_COUNT 0x0000e700 4556a26ae754SRob Clark 455752260ae4SRob Clark #define REG_A5XX_TPL1_HS_TEX_COUNT 0x0000e701 455852260ae4SRob Clark 455952260ae4SRob Clark #define REG_A5XX_TPL1_DS_TEX_COUNT 0x0000e702 456052260ae4SRob Clark 456152260ae4SRob Clark #define REG_A5XX_TPL1_GS_TEX_COUNT 0x0000e703 456252260ae4SRob Clark 4563a26ae754SRob Clark #define REG_A5XX_TPL1_VS_TEX_SAMP_LO 0x0000e722 4564a26ae754SRob Clark 4565a26ae754SRob Clark #define REG_A5XX_TPL1_VS_TEX_SAMP_HI 0x0000e723 4566a26ae754SRob Clark 456752260ae4SRob Clark #define REG_A5XX_TPL1_HS_TEX_SAMP_LO 0x0000e724 456852260ae4SRob Clark 456952260ae4SRob Clark #define REG_A5XX_TPL1_HS_TEX_SAMP_HI 0x0000e725 457052260ae4SRob Clark 457152260ae4SRob Clark #define REG_A5XX_TPL1_DS_TEX_SAMP_LO 0x0000e726 457252260ae4SRob Clark 457352260ae4SRob Clark #define REG_A5XX_TPL1_DS_TEX_SAMP_HI 0x0000e727 457452260ae4SRob Clark 457552260ae4SRob Clark #define REG_A5XX_TPL1_GS_TEX_SAMP_LO 0x0000e728 457652260ae4SRob Clark 457752260ae4SRob Clark #define REG_A5XX_TPL1_GS_TEX_SAMP_HI 0x0000e729 457852260ae4SRob Clark 4579a26ae754SRob Clark #define REG_A5XX_TPL1_VS_TEX_CONST_LO 0x0000e72a 4580a26ae754SRob Clark 4581a26ae754SRob Clark #define REG_A5XX_TPL1_VS_TEX_CONST_HI 0x0000e72b 4582a26ae754SRob Clark 458352260ae4SRob Clark #define REG_A5XX_TPL1_HS_TEX_CONST_LO 0x0000e72c 458452260ae4SRob Clark 458552260ae4SRob Clark #define REG_A5XX_TPL1_HS_TEX_CONST_HI 0x0000e72d 458652260ae4SRob Clark 458752260ae4SRob Clark #define REG_A5XX_TPL1_DS_TEX_CONST_LO 0x0000e72e 458852260ae4SRob Clark 458952260ae4SRob Clark #define REG_A5XX_TPL1_DS_TEX_CONST_HI 0x0000e72f 459052260ae4SRob Clark 459152260ae4SRob Clark #define REG_A5XX_TPL1_GS_TEX_CONST_LO 0x0000e730 459252260ae4SRob Clark 459352260ae4SRob Clark #define REG_A5XX_TPL1_GS_TEX_CONST_HI 0x0000e731 459452260ae4SRob Clark 4595a26ae754SRob Clark #define REG_A5XX_TPL1_FS_TEX_COUNT 0x0000e750 4596a26ae754SRob Clark 459752260ae4SRob Clark #define REG_A5XX_TPL1_CS_TEX_COUNT 0x0000e751 459852260ae4SRob Clark 4599a26ae754SRob Clark #define REG_A5XX_TPL1_FS_TEX_SAMP_LO 0x0000e75a 4600a26ae754SRob Clark 4601a26ae754SRob Clark #define REG_A5XX_TPL1_FS_TEX_SAMP_HI 0x0000e75b 4602a26ae754SRob Clark 460352260ae4SRob Clark #define REG_A5XX_TPL1_CS_TEX_SAMP_LO 0x0000e75c 460452260ae4SRob Clark 460552260ae4SRob Clark #define REG_A5XX_TPL1_CS_TEX_SAMP_HI 0x0000e75d 460652260ae4SRob Clark 4607a26ae754SRob Clark #define REG_A5XX_TPL1_FS_TEX_CONST_LO 0x0000e75e 4608a26ae754SRob Clark 4609a26ae754SRob Clark #define REG_A5XX_TPL1_FS_TEX_CONST_HI 0x0000e75f 4610a26ae754SRob Clark 461152260ae4SRob Clark #define REG_A5XX_TPL1_CS_TEX_CONST_LO 0x0000e760 461252260ae4SRob Clark 461352260ae4SRob Clark #define REG_A5XX_TPL1_CS_TEX_CONST_HI 0x0000e761 461452260ae4SRob Clark 4615a26ae754SRob Clark #define REG_A5XX_TPL1_TP_FS_ROTATION_CNTL 0x0000e764 4616a26ae754SRob Clark 4617a26ae754SRob Clark #define REG_A5XX_HLSQ_CONTROL_0_REG 0x0000e784 461852260ae4SRob Clark #define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000001 461952260ae4SRob Clark #define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 0 462052260ae4SRob Clark static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) 462152260ae4SRob Clark { 462252260ae4SRob Clark return ((val) << A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; 462352260ae4SRob Clark } 462452260ae4SRob Clark #define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK 0x00000004 462552260ae4SRob Clark #define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT 2 462652260ae4SRob Clark static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(enum a3xx_threadsize val) 462752260ae4SRob Clark { 462852260ae4SRob Clark return ((val) << A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK; 462952260ae4SRob Clark } 4630a26ae754SRob Clark 4631a26ae754SRob Clark #define REG_A5XX_HLSQ_CONTROL_1_REG 0x0000e785 4632a26ae754SRob Clark #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x0000003f 4633a26ae754SRob Clark #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT 0 4634a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val) 4635a26ae754SRob Clark { 4636a26ae754SRob Clark return ((val) << A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK; 4637a26ae754SRob Clark } 4638a26ae754SRob Clark 4639a26ae754SRob Clark #define REG_A5XX_HLSQ_CONTROL_2_REG 0x0000e786 4640a26ae754SRob Clark #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff 4641a26ae754SRob Clark #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0 4642a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) 4643a26ae754SRob Clark { 4644a26ae754SRob Clark return ((val) << A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; 4645a26ae754SRob Clark } 46462d756322SRob Clark #define A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00 46472d756322SRob Clark #define A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8 46482d756322SRob Clark static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) 46492d756322SRob Clark { 46502d756322SRob Clark return ((val) << A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK; 46512d756322SRob Clark } 46522d756322SRob Clark #define A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000 46532d756322SRob Clark #define A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16 46542d756322SRob Clark static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) 46552d756322SRob Clark { 46562d756322SRob Clark return ((val) << A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK; 46572d756322SRob Clark } 4658c28c82e9SRob Clark #define A5XX_HLSQ_CONTROL_2_REG_SIZE__MASK 0xff000000 4659c28c82e9SRob Clark #define A5XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT 24 4660c28c82e9SRob Clark static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SIZE(uint32_t val) 4661c28c82e9SRob Clark { 4662c28c82e9SRob Clark return ((val) << A5XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SIZE__MASK; 4663c28c82e9SRob Clark } 4664a26ae754SRob Clark 4665a26ae754SRob Clark #define REG_A5XX_HLSQ_CONTROL_3_REG 0x0000e787 4666c28c82e9SRob Clark #define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff 4667c28c82e9SRob Clark #define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0 4668c28c82e9SRob Clark static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val) 4669a26ae754SRob Clark { 4670c28c82e9SRob Clark return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK; 4671c28c82e9SRob Clark } 4672c28c82e9SRob Clark #define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00 4673c28c82e9SRob Clark #define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8 4674c28c82e9SRob Clark static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val) 4675c28c82e9SRob Clark { 4676c28c82e9SRob Clark return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK; 4677c28c82e9SRob Clark } 4678c28c82e9SRob Clark #define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000 4679c28c82e9SRob Clark #define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16 4680c28c82e9SRob Clark static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val) 4681c28c82e9SRob Clark { 4682c28c82e9SRob Clark return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK; 4683c28c82e9SRob Clark } 4684c28c82e9SRob Clark #define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000 4685c28c82e9SRob Clark #define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24 4686c28c82e9SRob Clark static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) 4687c28c82e9SRob Clark { 4688c28c82e9SRob Clark return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK; 4689a26ae754SRob Clark } 4690a26ae754SRob Clark 4691a26ae754SRob Clark #define REG_A5XX_HLSQ_CONTROL_4_REG 0x0000e788 4692c28c82e9SRob Clark #define A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff 4693c28c82e9SRob Clark #define A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0 4694c28c82e9SRob Clark static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val) 4695c28c82e9SRob Clark { 4696c28c82e9SRob Clark return ((val) << A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK; 4697c28c82e9SRob Clark } 4698c28c82e9SRob Clark #define A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00 4699c28c82e9SRob Clark #define A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8 4700c28c82e9SRob Clark static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val) 4701c28c82e9SRob Clark { 4702c28c82e9SRob Clark return ((val) << A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK; 4703c28c82e9SRob Clark } 4704a26ae754SRob Clark #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000 4705a26ae754SRob Clark #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16 4706a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) 4707a26ae754SRob Clark { 4708a26ae754SRob Clark return ((val) << A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK; 4709a26ae754SRob Clark } 4710a26ae754SRob Clark #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000 4711a26ae754SRob Clark #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24 4712a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) 4713a26ae754SRob Clark { 4714a26ae754SRob Clark return ((val) << A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; 4715a26ae754SRob Clark } 4716a26ae754SRob Clark 4717a26ae754SRob Clark #define REG_A5XX_HLSQ_UPDATE_CNTL 0x0000e78a 4718a26ae754SRob Clark 471952260ae4SRob Clark #define REG_A5XX_HLSQ_VS_CONFIG 0x0000e78b 472052260ae4SRob Clark #define A5XX_HLSQ_VS_CONFIG_ENABLED 0x00000001 472152260ae4SRob Clark #define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 472252260ae4SRob Clark #define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 472352260ae4SRob Clark static inline uint32_t A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 4724a26ae754SRob Clark { 472552260ae4SRob Clark return ((val) << A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK; 4726a26ae754SRob Clark } 472752260ae4SRob Clark #define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 472852260ae4SRob Clark #define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT 8 472952260ae4SRob Clark static inline uint32_t A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(uint32_t val) 4730a26ae754SRob Clark { 473152260ae4SRob Clark return ((val) << A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK; 4732a26ae754SRob Clark } 4733a26ae754SRob Clark 473452260ae4SRob Clark #define REG_A5XX_HLSQ_FS_CONFIG 0x0000e78c 473552260ae4SRob Clark #define A5XX_HLSQ_FS_CONFIG_ENABLED 0x00000001 473652260ae4SRob Clark #define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 473752260ae4SRob Clark #define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 473852260ae4SRob Clark static inline uint32_t A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 4739a26ae754SRob Clark { 474052260ae4SRob Clark return ((val) << A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK; 4741a26ae754SRob Clark } 474252260ae4SRob Clark #define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 474352260ae4SRob Clark #define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT 8 474452260ae4SRob Clark static inline uint32_t A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(uint32_t val) 4745a26ae754SRob Clark { 474652260ae4SRob Clark return ((val) << A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK; 4747a26ae754SRob Clark } 4748a26ae754SRob Clark 474952260ae4SRob Clark #define REG_A5XX_HLSQ_HS_CONFIG 0x0000e78d 475052260ae4SRob Clark #define A5XX_HLSQ_HS_CONFIG_ENABLED 0x00000001 475152260ae4SRob Clark #define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 475252260ae4SRob Clark #define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 475352260ae4SRob Clark static inline uint32_t A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 4754a26ae754SRob Clark { 475552260ae4SRob Clark return ((val) << A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK; 4756a26ae754SRob Clark } 475752260ae4SRob Clark #define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 475852260ae4SRob Clark #define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT 8 475952260ae4SRob Clark static inline uint32_t A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(uint32_t val) 4760a26ae754SRob Clark { 476152260ae4SRob Clark return ((val) << A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK; 4762a26ae754SRob Clark } 4763a26ae754SRob Clark 476452260ae4SRob Clark #define REG_A5XX_HLSQ_DS_CONFIG 0x0000e78e 476552260ae4SRob Clark #define A5XX_HLSQ_DS_CONFIG_ENABLED 0x00000001 476652260ae4SRob Clark #define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 476752260ae4SRob Clark #define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 476852260ae4SRob Clark static inline uint32_t A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 4769a26ae754SRob Clark { 477052260ae4SRob Clark return ((val) << A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK; 4771a26ae754SRob Clark } 477252260ae4SRob Clark #define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 477352260ae4SRob Clark #define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT 8 477452260ae4SRob Clark static inline uint32_t A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(uint32_t val) 4775a26ae754SRob Clark { 477652260ae4SRob Clark return ((val) << A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK; 4777a26ae754SRob Clark } 4778a26ae754SRob Clark 477952260ae4SRob Clark #define REG_A5XX_HLSQ_GS_CONFIG 0x0000e78f 478052260ae4SRob Clark #define A5XX_HLSQ_GS_CONFIG_ENABLED 0x00000001 478152260ae4SRob Clark #define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 478252260ae4SRob Clark #define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 478352260ae4SRob Clark static inline uint32_t A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 4784a26ae754SRob Clark { 478552260ae4SRob Clark return ((val) << A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK; 4786a26ae754SRob Clark } 478752260ae4SRob Clark #define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 478852260ae4SRob Clark #define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT 8 478952260ae4SRob Clark static inline uint32_t A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(uint32_t val) 4790a26ae754SRob Clark { 479152260ae4SRob Clark return ((val) << A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK; 4792a26ae754SRob Clark } 4793a26ae754SRob Clark 4794a26ae754SRob Clark #define REG_A5XX_HLSQ_CS_CONFIG 0x0000e790 479552260ae4SRob Clark #define A5XX_HLSQ_CS_CONFIG_ENABLED 0x00000001 479652260ae4SRob Clark #define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe 479752260ae4SRob Clark #define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1 479852260ae4SRob Clark static inline uint32_t A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val) 479952260ae4SRob Clark { 480052260ae4SRob Clark return ((val) << A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK; 480152260ae4SRob Clark } 480252260ae4SRob Clark #define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00 480352260ae4SRob Clark #define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT 8 480452260ae4SRob Clark static inline uint32_t A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET(uint32_t val) 480552260ae4SRob Clark { 480652260ae4SRob Clark return ((val) << A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK; 480752260ae4SRob Clark } 4808a26ae754SRob Clark 4809a26ae754SRob Clark #define REG_A5XX_HLSQ_VS_CNTL 0x0000e791 481052260ae4SRob Clark #define A5XX_HLSQ_VS_CNTL_SSBO_ENABLE 0x00000001 4811a26ae754SRob Clark #define A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK 0xfffffffe 4812a26ae754SRob Clark #define A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT 1 4813a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_VS_CNTL_INSTRLEN(uint32_t val) 4814a26ae754SRob Clark { 4815a26ae754SRob Clark return ((val) << A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK; 4816a26ae754SRob Clark } 4817a26ae754SRob Clark 4818a26ae754SRob Clark #define REG_A5XX_HLSQ_FS_CNTL 0x0000e792 481952260ae4SRob Clark #define A5XX_HLSQ_FS_CNTL_SSBO_ENABLE 0x00000001 4820a26ae754SRob Clark #define A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK 0xfffffffe 4821a26ae754SRob Clark #define A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT 1 4822a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_FS_CNTL_INSTRLEN(uint32_t val) 4823a26ae754SRob Clark { 4824a26ae754SRob Clark return ((val) << A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK; 4825a26ae754SRob Clark } 4826a26ae754SRob Clark 4827a26ae754SRob Clark #define REG_A5XX_HLSQ_HS_CNTL 0x0000e793 482852260ae4SRob Clark #define A5XX_HLSQ_HS_CNTL_SSBO_ENABLE 0x00000001 4829a26ae754SRob Clark #define A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK 0xfffffffe 4830a26ae754SRob Clark #define A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT 1 4831a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_HS_CNTL_INSTRLEN(uint32_t val) 4832a26ae754SRob Clark { 4833a26ae754SRob Clark return ((val) << A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK; 4834a26ae754SRob Clark } 4835a26ae754SRob Clark 4836a26ae754SRob Clark #define REG_A5XX_HLSQ_DS_CNTL 0x0000e794 483752260ae4SRob Clark #define A5XX_HLSQ_DS_CNTL_SSBO_ENABLE 0x00000001 4838a26ae754SRob Clark #define A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK 0xfffffffe 4839a26ae754SRob Clark #define A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT 1 4840a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_DS_CNTL_INSTRLEN(uint32_t val) 4841a26ae754SRob Clark { 4842a26ae754SRob Clark return ((val) << A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK; 4843a26ae754SRob Clark } 4844a26ae754SRob Clark 4845a26ae754SRob Clark #define REG_A5XX_HLSQ_GS_CNTL 0x0000e795 484652260ae4SRob Clark #define A5XX_HLSQ_GS_CNTL_SSBO_ENABLE 0x00000001 4847a26ae754SRob Clark #define A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK 0xfffffffe 4848a26ae754SRob Clark #define A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT 1 4849a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_GS_CNTL_INSTRLEN(uint32_t val) 4850a26ae754SRob Clark { 4851a26ae754SRob Clark return ((val) << A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK; 4852a26ae754SRob Clark } 4853a26ae754SRob Clark 4854a26ae754SRob Clark #define REG_A5XX_HLSQ_CS_CNTL 0x0000e796 485552260ae4SRob Clark #define A5XX_HLSQ_CS_CNTL_SSBO_ENABLE 0x00000001 4856a26ae754SRob Clark #define A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK 0xfffffffe 4857a26ae754SRob Clark #define A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT 1 4858a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val) 4859a26ae754SRob Clark { 4860a26ae754SRob Clark return ((val) << A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK; 4861a26ae754SRob Clark } 4862a26ae754SRob Clark 4863a26ae754SRob Clark #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_X 0x0000e7b9 4864a26ae754SRob Clark 4865a26ae754SRob Clark #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000e7ba 4866a26ae754SRob Clark 4867a26ae754SRob Clark #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000e7bb 4868a26ae754SRob Clark 4869a26ae754SRob Clark #define REG_A5XX_HLSQ_CS_NDRANGE_0 0x0000e7b0 487052260ae4SRob Clark #define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003 487152260ae4SRob Clark #define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0 487252260ae4SRob Clark static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) 487352260ae4SRob Clark { 487452260ae4SRob Clark return ((val) << A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK; 487552260ae4SRob Clark } 487652260ae4SRob Clark #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc 487752260ae4SRob Clark #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2 487852260ae4SRob Clark static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) 487952260ae4SRob Clark { 488052260ae4SRob Clark return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK; 488152260ae4SRob Clark } 488252260ae4SRob Clark #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000 488352260ae4SRob Clark #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12 488452260ae4SRob Clark static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) 488552260ae4SRob Clark { 488652260ae4SRob Clark return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK; 488752260ae4SRob Clark } 488852260ae4SRob Clark #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000 488952260ae4SRob Clark #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22 489052260ae4SRob Clark static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) 489152260ae4SRob Clark { 489252260ae4SRob Clark return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK; 489352260ae4SRob Clark } 4894a26ae754SRob Clark 4895a26ae754SRob Clark #define REG_A5XX_HLSQ_CS_NDRANGE_1 0x0000e7b1 48962d756322SRob Clark #define A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff 48972d756322SRob Clark #define A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0 48982d756322SRob Clark static inline uint32_t A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val) 489952260ae4SRob Clark { 49002d756322SRob Clark return ((val) << A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK; 490152260ae4SRob Clark } 4902a26ae754SRob Clark 4903a26ae754SRob Clark #define REG_A5XX_HLSQ_CS_NDRANGE_2 0x0000e7b2 49042d756322SRob Clark #define A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff 49052d756322SRob Clark #define A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0 49062d756322SRob Clark static inline uint32_t A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val) 49072d756322SRob Clark { 49082d756322SRob Clark return ((val) << A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK; 49092d756322SRob Clark } 4910a26ae754SRob Clark 4911a26ae754SRob Clark #define REG_A5XX_HLSQ_CS_NDRANGE_3 0x0000e7b3 49122d756322SRob Clark #define A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff 49132d756322SRob Clark #define A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0 49142d756322SRob Clark static inline uint32_t A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val) 491552260ae4SRob Clark { 49162d756322SRob Clark return ((val) << A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK; 491752260ae4SRob Clark } 4918a26ae754SRob Clark 4919a26ae754SRob Clark #define REG_A5XX_HLSQ_CS_NDRANGE_4 0x0000e7b4 49202d756322SRob Clark #define A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff 49212d756322SRob Clark #define A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0 49222d756322SRob Clark static inline uint32_t A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val) 49232d756322SRob Clark { 49242d756322SRob Clark return ((val) << A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK; 49252d756322SRob Clark } 4926a26ae754SRob Clark 4927a26ae754SRob Clark #define REG_A5XX_HLSQ_CS_NDRANGE_5 0x0000e7b5 49282d756322SRob Clark #define A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff 49292d756322SRob Clark #define A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0 49302d756322SRob Clark static inline uint32_t A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val) 493152260ae4SRob Clark { 49322d756322SRob Clark return ((val) << A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK; 493352260ae4SRob Clark } 4934a26ae754SRob Clark 4935a26ae754SRob Clark #define REG_A5XX_HLSQ_CS_NDRANGE_6 0x0000e7b6 49362d756322SRob Clark #define A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff 49372d756322SRob Clark #define A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0 49382d756322SRob Clark static inline uint32_t A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val) 49392d756322SRob Clark { 49402d756322SRob Clark return ((val) << A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK; 49412d756322SRob Clark } 4942a26ae754SRob Clark 4943a26ae754SRob Clark #define REG_A5XX_HLSQ_CS_CNTL_0 0x0000e7b7 494452260ae4SRob Clark #define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff 494552260ae4SRob Clark #define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0 494652260ae4SRob Clark static inline uint32_t A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val) 494752260ae4SRob Clark { 494852260ae4SRob Clark return ((val) << A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK; 494952260ae4SRob Clark } 495052260ae4SRob Clark #define A5XX_HLSQ_CS_CNTL_0_UNK0__MASK 0x0000ff00 495152260ae4SRob Clark #define A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT 8 495252260ae4SRob Clark static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val) 495352260ae4SRob Clark { 495452260ae4SRob Clark return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK0__MASK; 495552260ae4SRob Clark } 495652260ae4SRob Clark #define A5XX_HLSQ_CS_CNTL_0_UNK1__MASK 0x00ff0000 495752260ae4SRob Clark #define A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT 16 495852260ae4SRob Clark static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val) 495952260ae4SRob Clark { 496052260ae4SRob Clark return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK1__MASK; 496152260ae4SRob Clark } 496252260ae4SRob Clark #define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000 496352260ae4SRob Clark #define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24 496452260ae4SRob Clark static inline uint32_t A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) 496552260ae4SRob Clark { 496652260ae4SRob Clark return ((val) << A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK; 496752260ae4SRob Clark } 4968a26ae754SRob Clark 4969a26ae754SRob Clark #define REG_A5XX_HLSQ_CS_CNTL_1 0x0000e7b8 4970a26ae754SRob Clark 4971a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E7C0 0x0000e7c0 4972a26ae754SRob Clark 4973a26ae754SRob Clark #define REG_A5XX_HLSQ_VS_CONSTLEN 0x0000e7c3 4974a26ae754SRob Clark 4975a26ae754SRob Clark #define REG_A5XX_HLSQ_VS_INSTRLEN 0x0000e7c4 4976a26ae754SRob Clark 4977a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E7C5 0x0000e7c5 4978a26ae754SRob Clark 4979a26ae754SRob Clark #define REG_A5XX_HLSQ_HS_CONSTLEN 0x0000e7c8 4980a26ae754SRob Clark 4981a26ae754SRob Clark #define REG_A5XX_HLSQ_HS_INSTRLEN 0x0000e7c9 4982a26ae754SRob Clark 498352260ae4SRob Clark #define REG_A5XX_UNKNOWN_E7CA 0x0000e7ca 498452260ae4SRob Clark 4985a26ae754SRob Clark #define REG_A5XX_HLSQ_DS_CONSTLEN 0x0000e7cd 4986a26ae754SRob Clark 4987a26ae754SRob Clark #define REG_A5XX_HLSQ_DS_INSTRLEN 0x0000e7ce 4988a26ae754SRob Clark 4989a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E7CF 0x0000e7cf 4990a26ae754SRob Clark 4991a26ae754SRob Clark #define REG_A5XX_HLSQ_GS_CONSTLEN 0x0000e7d2 4992a26ae754SRob Clark 4993a26ae754SRob Clark #define REG_A5XX_HLSQ_GS_INSTRLEN 0x0000e7d3 4994a26ae754SRob Clark 4995a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E7D4 0x0000e7d4 4996a26ae754SRob Clark 499752260ae4SRob Clark #define REG_A5XX_HLSQ_FS_CONSTLEN 0x0000e7d7 499852260ae4SRob Clark 499952260ae4SRob Clark #define REG_A5XX_HLSQ_FS_INSTRLEN 0x0000e7d8 500052260ae4SRob Clark 5001a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E7D9 0x0000e7d9 5002a26ae754SRob Clark 500352260ae4SRob Clark #define REG_A5XX_HLSQ_CS_CONSTLEN 0x0000e7dc 5004a26ae754SRob Clark 500552260ae4SRob Clark #define REG_A5XX_HLSQ_CS_INSTRLEN 0x0000e7dd 5006a26ae754SRob Clark 50072d756322SRob Clark #define REG_A5XX_RB_2D_BLIT_CNTL 0x00002100 50082d756322SRob Clark 500952260ae4SRob Clark #define REG_A5XX_RB_2D_SRC_SOLID_DW0 0x00002101 501052260ae4SRob Clark 501152260ae4SRob Clark #define REG_A5XX_RB_2D_SRC_SOLID_DW1 0x00002102 501252260ae4SRob Clark 501352260ae4SRob Clark #define REG_A5XX_RB_2D_SRC_SOLID_DW2 0x00002103 501452260ae4SRob Clark 501552260ae4SRob Clark #define REG_A5XX_RB_2D_SRC_SOLID_DW3 0x00002104 5016a26ae754SRob Clark 5017a26ae754SRob Clark #define REG_A5XX_RB_2D_SRC_INFO 0x00002107 5018a26ae754SRob Clark #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff 5019a26ae754SRob Clark #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 5020a26ae754SRob Clark static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) 5021a26ae754SRob Clark { 5022a26ae754SRob Clark return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK; 5023a26ae754SRob Clark } 50242d756322SRob Clark #define A5XX_RB_2D_SRC_INFO_TILE_MODE__MASK 0x00000300 50252d756322SRob Clark #define A5XX_RB_2D_SRC_INFO_TILE_MODE__SHIFT 8 50262d756322SRob Clark static inline uint32_t A5XX_RB_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val) 50272d756322SRob Clark { 50282d756322SRob Clark return ((val) << A5XX_RB_2D_SRC_INFO_TILE_MODE__SHIFT) & A5XX_RB_2D_SRC_INFO_TILE_MODE__MASK; 50292d756322SRob Clark } 5030a26ae754SRob Clark #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00 5031a26ae754SRob Clark #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT 10 5032a26ae754SRob Clark static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) 5033a26ae754SRob Clark { 5034a26ae754SRob Clark return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK; 5035a26ae754SRob Clark } 50362d756322SRob Clark #define A5XX_RB_2D_SRC_INFO_FLAGS 0x00001000 5037a26ae754SRob Clark 5038a26ae754SRob Clark #define REG_A5XX_RB_2D_SRC_LO 0x00002108 5039a26ae754SRob Clark 5040a26ae754SRob Clark #define REG_A5XX_RB_2D_SRC_HI 0x00002109 5041a26ae754SRob Clark 504252260ae4SRob Clark #define REG_A5XX_RB_2D_SRC_SIZE 0x0000210a 504352260ae4SRob Clark #define A5XX_RB_2D_SRC_SIZE_PITCH__MASK 0x0000ffff 504452260ae4SRob Clark #define A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT 0 504552260ae4SRob Clark static inline uint32_t A5XX_RB_2D_SRC_SIZE_PITCH(uint32_t val) 504652260ae4SRob Clark { 504752260ae4SRob Clark return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_PITCH__MASK; 504852260ae4SRob Clark } 504952260ae4SRob Clark #define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK 0xffff0000 505052260ae4SRob Clark #define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT 16 505152260ae4SRob Clark static inline uint32_t A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(uint32_t val) 505252260ae4SRob Clark { 505352260ae4SRob Clark return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK; 505452260ae4SRob Clark } 505552260ae4SRob Clark 5056a26ae754SRob Clark #define REG_A5XX_RB_2D_DST_INFO 0x00002110 5057a26ae754SRob Clark #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff 5058a26ae754SRob Clark #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0 5059a26ae754SRob Clark static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) 5060a26ae754SRob Clark { 5061a26ae754SRob Clark return ((val) << A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK; 5062a26ae754SRob Clark } 50632d756322SRob Clark #define A5XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300 50642d756322SRob Clark #define A5XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8 50652d756322SRob Clark static inline uint32_t A5XX_RB_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val) 50662d756322SRob Clark { 50672d756322SRob Clark return ((val) << A5XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A5XX_RB_2D_DST_INFO_TILE_MODE__MASK; 50682d756322SRob Clark } 5069a26ae754SRob Clark #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00 5070a26ae754SRob Clark #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10 5071a26ae754SRob Clark static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) 5072a26ae754SRob Clark { 5073a26ae754SRob Clark return ((val) << A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK; 5074a26ae754SRob Clark } 50752d756322SRob Clark #define A5XX_RB_2D_DST_INFO_FLAGS 0x00001000 5076a26ae754SRob Clark 5077a26ae754SRob Clark #define REG_A5XX_RB_2D_DST_LO 0x00002111 5078a26ae754SRob Clark 5079a26ae754SRob Clark #define REG_A5XX_RB_2D_DST_HI 0x00002112 5080a26ae754SRob Clark 508152260ae4SRob Clark #define REG_A5XX_RB_2D_DST_SIZE 0x00002113 508252260ae4SRob Clark #define A5XX_RB_2D_DST_SIZE_PITCH__MASK 0x0000ffff 508352260ae4SRob Clark #define A5XX_RB_2D_DST_SIZE_PITCH__SHIFT 0 508452260ae4SRob Clark static inline uint32_t A5XX_RB_2D_DST_SIZE_PITCH(uint32_t val) 508552260ae4SRob Clark { 508652260ae4SRob Clark return ((val >> 6) << A5XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_PITCH__MASK; 508752260ae4SRob Clark } 508852260ae4SRob Clark #define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK 0xffff0000 508952260ae4SRob Clark #define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT 16 509052260ae4SRob Clark static inline uint32_t A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val) 509152260ae4SRob Clark { 509252260ae4SRob Clark return ((val >> 6) << A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK; 509352260ae4SRob Clark } 509452260ae4SRob Clark 509552260ae4SRob Clark #define REG_A5XX_RB_2D_SRC_FLAGS_LO 0x00002140 509652260ae4SRob Clark 509752260ae4SRob Clark #define REG_A5XX_RB_2D_SRC_FLAGS_HI 0x00002141 509852260ae4SRob Clark 5099c28c82e9SRob Clark #define REG_A5XX_RB_2D_SRC_FLAGS_PITCH 0x00002142 5100c28c82e9SRob Clark #define A5XX_RB_2D_SRC_FLAGS_PITCH__MASK 0xffffffff 5101c28c82e9SRob Clark #define A5XX_RB_2D_SRC_FLAGS_PITCH__SHIFT 0 5102c28c82e9SRob Clark static inline uint32_t A5XX_RB_2D_SRC_FLAGS_PITCH(uint32_t val) 5103c28c82e9SRob Clark { 5104c28c82e9SRob Clark return ((val >> 6) << A5XX_RB_2D_SRC_FLAGS_PITCH__SHIFT) & A5XX_RB_2D_SRC_FLAGS_PITCH__MASK; 5105c28c82e9SRob Clark } 5106c28c82e9SRob Clark 5107a26ae754SRob Clark #define REG_A5XX_RB_2D_DST_FLAGS_LO 0x00002143 5108a26ae754SRob Clark 5109a26ae754SRob Clark #define REG_A5XX_RB_2D_DST_FLAGS_HI 0x00002144 5110a26ae754SRob Clark 5111c28c82e9SRob Clark #define REG_A5XX_RB_2D_DST_FLAGS_PITCH 0x00002145 5112c28c82e9SRob Clark #define A5XX_RB_2D_DST_FLAGS_PITCH__MASK 0xffffffff 5113c28c82e9SRob Clark #define A5XX_RB_2D_DST_FLAGS_PITCH__SHIFT 0 5114c28c82e9SRob Clark static inline uint32_t A5XX_RB_2D_DST_FLAGS_PITCH(uint32_t val) 5115c28c82e9SRob Clark { 5116c28c82e9SRob Clark return ((val >> 6) << A5XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A5XX_RB_2D_DST_FLAGS_PITCH__MASK; 5117c28c82e9SRob Clark } 5118c28c82e9SRob Clark 51192d756322SRob Clark #define REG_A5XX_GRAS_2D_BLIT_CNTL 0x00002180 51202d756322SRob Clark 5121a26ae754SRob Clark #define REG_A5XX_GRAS_2D_SRC_INFO 0x00002181 5122a26ae754SRob Clark #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff 5123a26ae754SRob Clark #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 5124a26ae754SRob Clark static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) 5125a26ae754SRob Clark { 5126a26ae754SRob Clark return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK; 5127a26ae754SRob Clark } 51282d756322SRob Clark #define A5XX_GRAS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300 51292d756322SRob Clark #define A5XX_GRAS_2D_SRC_INFO_TILE_MODE__SHIFT 8 51302d756322SRob Clark static inline uint32_t A5XX_GRAS_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val) 51312d756322SRob Clark { 51322d756322SRob Clark return ((val) << A5XX_GRAS_2D_SRC_INFO_TILE_MODE__SHIFT) & A5XX_GRAS_2D_SRC_INFO_TILE_MODE__MASK; 51332d756322SRob Clark } 5134a26ae754SRob Clark #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00 5135a26ae754SRob Clark #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10 5136a26ae754SRob Clark static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) 5137a26ae754SRob Clark { 5138a26ae754SRob Clark return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK; 5139a26ae754SRob Clark } 51402d756322SRob Clark #define A5XX_GRAS_2D_SRC_INFO_FLAGS 0x00001000 5141a26ae754SRob Clark 5142a26ae754SRob Clark #define REG_A5XX_GRAS_2D_DST_INFO 0x00002182 5143a26ae754SRob Clark #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff 5144a26ae754SRob Clark #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT 0 5145a26ae754SRob Clark static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) 5146a26ae754SRob Clark { 5147a26ae754SRob Clark return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK; 5148a26ae754SRob Clark } 51492d756322SRob Clark #define A5XX_GRAS_2D_DST_INFO_TILE_MODE__MASK 0x00000300 51502d756322SRob Clark #define A5XX_GRAS_2D_DST_INFO_TILE_MODE__SHIFT 8 51512d756322SRob Clark static inline uint32_t A5XX_GRAS_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val) 51522d756322SRob Clark { 51532d756322SRob Clark return ((val) << A5XX_GRAS_2D_DST_INFO_TILE_MODE__SHIFT) & A5XX_GRAS_2D_DST_INFO_TILE_MODE__MASK; 51542d756322SRob Clark } 5155a26ae754SRob Clark #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00 5156a26ae754SRob Clark #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT 10 5157a26ae754SRob Clark static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) 5158a26ae754SRob Clark { 5159a26ae754SRob Clark return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK; 5160a26ae754SRob Clark } 51612d756322SRob Clark #define A5XX_GRAS_2D_DST_INFO_FLAGS 0x00001000 5162a26ae754SRob Clark 516352260ae4SRob Clark #define REG_A5XX_UNKNOWN_2100 0x00002100 516452260ae4SRob Clark 516552260ae4SRob Clark #define REG_A5XX_UNKNOWN_2180 0x00002180 516652260ae4SRob Clark 516752260ae4SRob Clark #define REG_A5XX_UNKNOWN_2184 0x00002184 516852260ae4SRob Clark 5169a26ae754SRob Clark #define REG_A5XX_TEX_SAMP_0 0x00000000 5170a26ae754SRob Clark #define A5XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 5171a26ae754SRob Clark #define A5XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 5172a26ae754SRob Clark #define A5XX_TEX_SAMP_0_XY_MAG__SHIFT 1 5173a26ae754SRob Clark static inline uint32_t A5XX_TEX_SAMP_0_XY_MAG(enum a5xx_tex_filter val) 5174a26ae754SRob Clark { 5175a26ae754SRob Clark return ((val) << A5XX_TEX_SAMP_0_XY_MAG__SHIFT) & A5XX_TEX_SAMP_0_XY_MAG__MASK; 5176a26ae754SRob Clark } 5177a26ae754SRob Clark #define A5XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 5178a26ae754SRob Clark #define A5XX_TEX_SAMP_0_XY_MIN__SHIFT 3 5179a26ae754SRob Clark static inline uint32_t A5XX_TEX_SAMP_0_XY_MIN(enum a5xx_tex_filter val) 5180a26ae754SRob Clark { 5181a26ae754SRob Clark return ((val) << A5XX_TEX_SAMP_0_XY_MIN__SHIFT) & A5XX_TEX_SAMP_0_XY_MIN__MASK; 5182a26ae754SRob Clark } 5183a26ae754SRob Clark #define A5XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 5184a26ae754SRob Clark #define A5XX_TEX_SAMP_0_WRAP_S__SHIFT 5 5185a26ae754SRob Clark static inline uint32_t A5XX_TEX_SAMP_0_WRAP_S(enum a5xx_tex_clamp val) 5186a26ae754SRob Clark { 5187a26ae754SRob Clark return ((val) << A5XX_TEX_SAMP_0_WRAP_S__SHIFT) & A5XX_TEX_SAMP_0_WRAP_S__MASK; 5188a26ae754SRob Clark } 5189a26ae754SRob Clark #define A5XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 5190a26ae754SRob Clark #define A5XX_TEX_SAMP_0_WRAP_T__SHIFT 8 5191a26ae754SRob Clark static inline uint32_t A5XX_TEX_SAMP_0_WRAP_T(enum a5xx_tex_clamp val) 5192a26ae754SRob Clark { 5193a26ae754SRob Clark return ((val) << A5XX_TEX_SAMP_0_WRAP_T__SHIFT) & A5XX_TEX_SAMP_0_WRAP_T__MASK; 5194a26ae754SRob Clark } 5195a26ae754SRob Clark #define A5XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 5196a26ae754SRob Clark #define A5XX_TEX_SAMP_0_WRAP_R__SHIFT 11 5197a26ae754SRob Clark static inline uint32_t A5XX_TEX_SAMP_0_WRAP_R(enum a5xx_tex_clamp val) 5198a26ae754SRob Clark { 5199a26ae754SRob Clark return ((val) << A5XX_TEX_SAMP_0_WRAP_R__SHIFT) & A5XX_TEX_SAMP_0_WRAP_R__MASK; 5200a26ae754SRob Clark } 5201a26ae754SRob Clark #define A5XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 5202a26ae754SRob Clark #define A5XX_TEX_SAMP_0_ANISO__SHIFT 14 5203a26ae754SRob Clark static inline uint32_t A5XX_TEX_SAMP_0_ANISO(enum a5xx_tex_aniso val) 5204a26ae754SRob Clark { 5205a26ae754SRob Clark return ((val) << A5XX_TEX_SAMP_0_ANISO__SHIFT) & A5XX_TEX_SAMP_0_ANISO__MASK; 5206a26ae754SRob Clark } 5207a26ae754SRob Clark #define A5XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000 5208a26ae754SRob Clark #define A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19 5209a26ae754SRob Clark static inline uint32_t A5XX_TEX_SAMP_0_LOD_BIAS(float val) 5210a26ae754SRob Clark { 5211a26ae754SRob Clark return ((((int32_t)(val * 256.0))) << A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A5XX_TEX_SAMP_0_LOD_BIAS__MASK; 5212a26ae754SRob Clark } 5213a26ae754SRob Clark 5214a26ae754SRob Clark #define REG_A5XX_TEX_SAMP_1 0x00000001 5215a26ae754SRob Clark #define A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e 5216a26ae754SRob Clark #define A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 5217a26ae754SRob Clark static inline uint32_t A5XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) 5218a26ae754SRob Clark { 5219a26ae754SRob Clark return ((val) << A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK; 5220a26ae754SRob Clark } 5221a26ae754SRob Clark #define A5XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010 5222a26ae754SRob Clark #define A5XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 5223a26ae754SRob Clark #define A5XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 5224a26ae754SRob Clark #define A5XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 5225a26ae754SRob Clark #define A5XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 5226a26ae754SRob Clark static inline uint32_t A5XX_TEX_SAMP_1_MAX_LOD(float val) 5227a26ae754SRob Clark { 5228a26ae754SRob Clark return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A5XX_TEX_SAMP_1_MAX_LOD__MASK; 5229a26ae754SRob Clark } 5230a26ae754SRob Clark #define A5XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 5231a26ae754SRob Clark #define A5XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 5232a26ae754SRob Clark static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val) 5233a26ae754SRob Clark { 5234a26ae754SRob Clark return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A5XX_TEX_SAMP_1_MIN_LOD__MASK; 5235a26ae754SRob Clark } 5236a26ae754SRob Clark 5237a26ae754SRob Clark #define REG_A5XX_TEX_SAMP_2 0x00000002 5238*cc4c26d4SRob Clark #define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xffffff80 5239*cc4c26d4SRob Clark #define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 7 524052260ae4SRob Clark static inline uint32_t A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val) 524152260ae4SRob Clark { 524252260ae4SRob Clark return ((val) << A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK; 524352260ae4SRob Clark } 5244a26ae754SRob Clark 5245a26ae754SRob Clark #define REG_A5XX_TEX_SAMP_3 0x00000003 5246a26ae754SRob Clark 5247a26ae754SRob Clark #define REG_A5XX_TEX_CONST_0 0x00000000 5248a26ae754SRob Clark #define A5XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003 5249a26ae754SRob Clark #define A5XX_TEX_CONST_0_TILE_MODE__SHIFT 0 5250a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_0_TILE_MODE(enum a5xx_tile_mode val) 5251a26ae754SRob Clark { 5252a26ae754SRob Clark return ((val) << A5XX_TEX_CONST_0_TILE_MODE__SHIFT) & A5XX_TEX_CONST_0_TILE_MODE__MASK; 5253a26ae754SRob Clark } 5254a26ae754SRob Clark #define A5XX_TEX_CONST_0_SRGB 0x00000004 5255a26ae754SRob Clark #define A5XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 5256a26ae754SRob Clark #define A5XX_TEX_CONST_0_SWIZ_X__SHIFT 4 5257a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_0_SWIZ_X(enum a5xx_tex_swiz val) 5258a26ae754SRob Clark { 5259a26ae754SRob Clark return ((val) << A5XX_TEX_CONST_0_SWIZ_X__SHIFT) & A5XX_TEX_CONST_0_SWIZ_X__MASK; 5260a26ae754SRob Clark } 5261a26ae754SRob Clark #define A5XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 5262a26ae754SRob Clark #define A5XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 5263a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Y(enum a5xx_tex_swiz val) 5264a26ae754SRob Clark { 5265a26ae754SRob Clark return ((val) << A5XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Y__MASK; 5266a26ae754SRob Clark } 5267a26ae754SRob Clark #define A5XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 5268a26ae754SRob Clark #define A5XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 5269a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Z(enum a5xx_tex_swiz val) 5270a26ae754SRob Clark { 5271a26ae754SRob Clark return ((val) << A5XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Z__MASK; 5272a26ae754SRob Clark } 5273a26ae754SRob Clark #define A5XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 5274a26ae754SRob Clark #define A5XX_TEX_CONST_0_SWIZ_W__SHIFT 13 5275a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_0_SWIZ_W(enum a5xx_tex_swiz val) 5276a26ae754SRob Clark { 5277a26ae754SRob Clark return ((val) << A5XX_TEX_CONST_0_SWIZ_W__SHIFT) & A5XX_TEX_CONST_0_SWIZ_W__MASK; 5278a26ae754SRob Clark } 527952260ae4SRob Clark #define A5XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 528052260ae4SRob Clark #define A5XX_TEX_CONST_0_MIPLVLS__SHIFT 16 528152260ae4SRob Clark static inline uint32_t A5XX_TEX_CONST_0_MIPLVLS(uint32_t val) 528252260ae4SRob Clark { 528352260ae4SRob Clark return ((val) << A5XX_TEX_CONST_0_MIPLVLS__SHIFT) & A5XX_TEX_CONST_0_MIPLVLS__MASK; 528452260ae4SRob Clark } 52852d756322SRob Clark #define A5XX_TEX_CONST_0_SAMPLES__MASK 0x00300000 52862d756322SRob Clark #define A5XX_TEX_CONST_0_SAMPLES__SHIFT 20 52872d756322SRob Clark static inline uint32_t A5XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val) 52882d756322SRob Clark { 52892d756322SRob Clark return ((val) << A5XX_TEX_CONST_0_SAMPLES__SHIFT) & A5XX_TEX_CONST_0_SAMPLES__MASK; 52902d756322SRob Clark } 5291a26ae754SRob Clark #define A5XX_TEX_CONST_0_FMT__MASK 0x3fc00000 5292a26ae754SRob Clark #define A5XX_TEX_CONST_0_FMT__SHIFT 22 5293a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_0_FMT(enum a5xx_tex_fmt val) 5294a26ae754SRob Clark { 5295a26ae754SRob Clark return ((val) << A5XX_TEX_CONST_0_FMT__SHIFT) & A5XX_TEX_CONST_0_FMT__MASK; 5296a26ae754SRob Clark } 5297a26ae754SRob Clark #define A5XX_TEX_CONST_0_SWAP__MASK 0xc0000000 5298a26ae754SRob Clark #define A5XX_TEX_CONST_0_SWAP__SHIFT 30 5299a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val) 5300a26ae754SRob Clark { 5301a26ae754SRob Clark return ((val) << A5XX_TEX_CONST_0_SWAP__SHIFT) & A5XX_TEX_CONST_0_SWAP__MASK; 5302a26ae754SRob Clark } 5303a26ae754SRob Clark 5304a26ae754SRob Clark #define REG_A5XX_TEX_CONST_1 0x00000001 5305a26ae754SRob Clark #define A5XX_TEX_CONST_1_WIDTH__MASK 0x00007fff 5306a26ae754SRob Clark #define A5XX_TEX_CONST_1_WIDTH__SHIFT 0 5307a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_1_WIDTH(uint32_t val) 5308a26ae754SRob Clark { 5309a26ae754SRob Clark return ((val) << A5XX_TEX_CONST_1_WIDTH__SHIFT) & A5XX_TEX_CONST_1_WIDTH__MASK; 5310a26ae754SRob Clark } 5311a26ae754SRob Clark #define A5XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000 5312a26ae754SRob Clark #define A5XX_TEX_CONST_1_HEIGHT__SHIFT 15 5313a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val) 5314a26ae754SRob Clark { 5315a26ae754SRob Clark return ((val) << A5XX_TEX_CONST_1_HEIGHT__SHIFT) & A5XX_TEX_CONST_1_HEIGHT__MASK; 5316a26ae754SRob Clark } 5317a26ae754SRob Clark 5318a26ae754SRob Clark #define REG_A5XX_TEX_CONST_2 0x00000002 5319*cc4c26d4SRob Clark #define A5XX_TEX_CONST_2_UNK4 0x00000010 5320c28c82e9SRob Clark #define A5XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f 5321c28c82e9SRob Clark #define A5XX_TEX_CONST_2_PITCHALIGN__SHIFT 0 5322c28c82e9SRob Clark static inline uint32_t A5XX_TEX_CONST_2_PITCHALIGN(uint32_t val) 5323a26ae754SRob Clark { 5324c28c82e9SRob Clark return ((val) << A5XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A5XX_TEX_CONST_2_PITCHALIGN__MASK; 5325a26ae754SRob Clark } 5326a26ae754SRob Clark #define A5XX_TEX_CONST_2_PITCH__MASK 0x1fffff80 5327a26ae754SRob Clark #define A5XX_TEX_CONST_2_PITCH__SHIFT 7 5328a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_2_PITCH(uint32_t val) 5329a26ae754SRob Clark { 5330a26ae754SRob Clark return ((val) << A5XX_TEX_CONST_2_PITCH__SHIFT) & A5XX_TEX_CONST_2_PITCH__MASK; 5331a26ae754SRob Clark } 5332a26ae754SRob Clark #define A5XX_TEX_CONST_2_TYPE__MASK 0x60000000 5333a26ae754SRob Clark #define A5XX_TEX_CONST_2_TYPE__SHIFT 29 5334a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val) 5335a26ae754SRob Clark { 5336a26ae754SRob Clark return ((val) << A5XX_TEX_CONST_2_TYPE__SHIFT) & A5XX_TEX_CONST_2_TYPE__MASK; 5337a26ae754SRob Clark } 5338*cc4c26d4SRob Clark #define A5XX_TEX_CONST_2_UNK31 0x80000000 5339a26ae754SRob Clark 5340a26ae754SRob Clark #define REG_A5XX_TEX_CONST_3 0x00000003 5341a26ae754SRob Clark #define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff 5342a26ae754SRob Clark #define A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0 5343a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) 5344a26ae754SRob Clark { 5345a26ae754SRob Clark return ((val >> 12) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK; 5346a26ae754SRob Clark } 5347c28c82e9SRob Clark #define A5XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000 5348c28c82e9SRob Clark #define A5XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23 5349c28c82e9SRob Clark static inline uint32_t A5XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val) 5350c28c82e9SRob Clark { 5351c28c82e9SRob Clark return ((val >> 12) << A5XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A5XX_TEX_CONST_3_MIN_LAYERSZ__MASK; 5352c28c82e9SRob Clark } 5353c28c82e9SRob Clark #define A5XX_TEX_CONST_3_TILE_ALL 0x08000000 5354a26ae754SRob Clark #define A5XX_TEX_CONST_3_FLAG 0x10000000 5355a26ae754SRob Clark 5356a26ae754SRob Clark #define REG_A5XX_TEX_CONST_4 0x00000004 5357a26ae754SRob Clark #define A5XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0 5358a26ae754SRob Clark #define A5XX_TEX_CONST_4_BASE_LO__SHIFT 5 5359a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_4_BASE_LO(uint32_t val) 5360a26ae754SRob Clark { 5361a26ae754SRob Clark return ((val >> 5) << A5XX_TEX_CONST_4_BASE_LO__SHIFT) & A5XX_TEX_CONST_4_BASE_LO__MASK; 5362a26ae754SRob Clark } 5363a26ae754SRob Clark 5364a26ae754SRob Clark #define REG_A5XX_TEX_CONST_5 0x00000005 5365a26ae754SRob Clark #define A5XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff 5366a26ae754SRob Clark #define A5XX_TEX_CONST_5_BASE_HI__SHIFT 0 5367a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_5_BASE_HI(uint32_t val) 5368a26ae754SRob Clark { 5369a26ae754SRob Clark return ((val) << A5XX_TEX_CONST_5_BASE_HI__SHIFT) & A5XX_TEX_CONST_5_BASE_HI__MASK; 5370a26ae754SRob Clark } 5371a26ae754SRob Clark #define A5XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000 5372a26ae754SRob Clark #define A5XX_TEX_CONST_5_DEPTH__SHIFT 17 5373a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_5_DEPTH(uint32_t val) 5374a26ae754SRob Clark { 5375a26ae754SRob Clark return ((val) << A5XX_TEX_CONST_5_DEPTH__SHIFT) & A5XX_TEX_CONST_5_DEPTH__MASK; 5376a26ae754SRob Clark } 5377a26ae754SRob Clark 5378a26ae754SRob Clark #define REG_A5XX_TEX_CONST_6 0x00000006 5379a26ae754SRob Clark 5380a26ae754SRob Clark #define REG_A5XX_TEX_CONST_7 0x00000007 5381a26ae754SRob Clark 5382a26ae754SRob Clark #define REG_A5XX_TEX_CONST_8 0x00000008 5383a26ae754SRob Clark 5384a26ae754SRob Clark #define REG_A5XX_TEX_CONST_9 0x00000009 5385a26ae754SRob Clark 5386a26ae754SRob Clark #define REG_A5XX_TEX_CONST_10 0x0000000a 5387a26ae754SRob Clark 5388a26ae754SRob Clark #define REG_A5XX_TEX_CONST_11 0x0000000b 5389a26ae754SRob Clark 53902d756322SRob Clark #define REG_A5XX_SSBO_0_0 0x00000000 53912d756322SRob Clark #define A5XX_SSBO_0_0_BASE_LO__MASK 0xffffffe0 53922d756322SRob Clark #define A5XX_SSBO_0_0_BASE_LO__SHIFT 5 53932d756322SRob Clark static inline uint32_t A5XX_SSBO_0_0_BASE_LO(uint32_t val) 53942d756322SRob Clark { 53952d756322SRob Clark return ((val >> 5) << A5XX_SSBO_0_0_BASE_LO__SHIFT) & A5XX_SSBO_0_0_BASE_LO__MASK; 53962d756322SRob Clark } 53972d756322SRob Clark 53982d756322SRob Clark #define REG_A5XX_SSBO_0_1 0x00000001 53992d756322SRob Clark #define A5XX_SSBO_0_1_PITCH__MASK 0x003fffff 54002d756322SRob Clark #define A5XX_SSBO_0_1_PITCH__SHIFT 0 54012d756322SRob Clark static inline uint32_t A5XX_SSBO_0_1_PITCH(uint32_t val) 54022d756322SRob Clark { 54032d756322SRob Clark return ((val) << A5XX_SSBO_0_1_PITCH__SHIFT) & A5XX_SSBO_0_1_PITCH__MASK; 54042d756322SRob Clark } 54052d756322SRob Clark 54062d756322SRob Clark #define REG_A5XX_SSBO_0_2 0x00000002 54072d756322SRob Clark #define A5XX_SSBO_0_2_ARRAY_PITCH__MASK 0x03fff000 54082d756322SRob Clark #define A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT 12 54092d756322SRob Clark static inline uint32_t A5XX_SSBO_0_2_ARRAY_PITCH(uint32_t val) 54102d756322SRob Clark { 54112d756322SRob Clark return ((val >> 12) << A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A5XX_SSBO_0_2_ARRAY_PITCH__MASK; 54122d756322SRob Clark } 54132d756322SRob Clark 54142d756322SRob Clark #define REG_A5XX_SSBO_0_3 0x00000003 54152d756322SRob Clark #define A5XX_SSBO_0_3_CPP__MASK 0x0000003f 54162d756322SRob Clark #define A5XX_SSBO_0_3_CPP__SHIFT 0 54172d756322SRob Clark static inline uint32_t A5XX_SSBO_0_3_CPP(uint32_t val) 54182d756322SRob Clark { 54192d756322SRob Clark return ((val) << A5XX_SSBO_0_3_CPP__SHIFT) & A5XX_SSBO_0_3_CPP__MASK; 54202d756322SRob Clark } 54212d756322SRob Clark 54222d756322SRob Clark #define REG_A5XX_SSBO_1_0 0x00000000 54232d756322SRob Clark #define A5XX_SSBO_1_0_FMT__MASK 0x0000ff00 54242d756322SRob Clark #define A5XX_SSBO_1_0_FMT__SHIFT 8 54252d756322SRob Clark static inline uint32_t A5XX_SSBO_1_0_FMT(enum a5xx_tex_fmt val) 54262d756322SRob Clark { 54272d756322SRob Clark return ((val) << A5XX_SSBO_1_0_FMT__SHIFT) & A5XX_SSBO_1_0_FMT__MASK; 54282d756322SRob Clark } 54292d756322SRob Clark #define A5XX_SSBO_1_0_WIDTH__MASK 0xffff0000 54302d756322SRob Clark #define A5XX_SSBO_1_0_WIDTH__SHIFT 16 54312d756322SRob Clark static inline uint32_t A5XX_SSBO_1_0_WIDTH(uint32_t val) 54322d756322SRob Clark { 54332d756322SRob Clark return ((val) << A5XX_SSBO_1_0_WIDTH__SHIFT) & A5XX_SSBO_1_0_WIDTH__MASK; 54342d756322SRob Clark } 54352d756322SRob Clark 54362d756322SRob Clark #define REG_A5XX_SSBO_1_1 0x00000001 54372d756322SRob Clark #define A5XX_SSBO_1_1_HEIGHT__MASK 0x0000ffff 54382d756322SRob Clark #define A5XX_SSBO_1_1_HEIGHT__SHIFT 0 54392d756322SRob Clark static inline uint32_t A5XX_SSBO_1_1_HEIGHT(uint32_t val) 54402d756322SRob Clark { 54412d756322SRob Clark return ((val) << A5XX_SSBO_1_1_HEIGHT__SHIFT) & A5XX_SSBO_1_1_HEIGHT__MASK; 54422d756322SRob Clark } 54432d756322SRob Clark #define A5XX_SSBO_1_1_DEPTH__MASK 0xffff0000 54442d756322SRob Clark #define A5XX_SSBO_1_1_DEPTH__SHIFT 16 54452d756322SRob Clark static inline uint32_t A5XX_SSBO_1_1_DEPTH(uint32_t val) 54462d756322SRob Clark { 54472d756322SRob Clark return ((val) << A5XX_SSBO_1_1_DEPTH__SHIFT) & A5XX_SSBO_1_1_DEPTH__MASK; 54482d756322SRob Clark } 54492d756322SRob Clark 54502d756322SRob Clark #define REG_A5XX_SSBO_2_0 0x00000000 54512d756322SRob Clark #define A5XX_SSBO_2_0_BASE_LO__MASK 0xffffffff 54522d756322SRob Clark #define A5XX_SSBO_2_0_BASE_LO__SHIFT 0 54532d756322SRob Clark static inline uint32_t A5XX_SSBO_2_0_BASE_LO(uint32_t val) 54542d756322SRob Clark { 54552d756322SRob Clark return ((val) << A5XX_SSBO_2_0_BASE_LO__SHIFT) & A5XX_SSBO_2_0_BASE_LO__MASK; 54562d756322SRob Clark } 54572d756322SRob Clark 54582d756322SRob Clark #define REG_A5XX_SSBO_2_1 0x00000001 54592d756322SRob Clark #define A5XX_SSBO_2_1_BASE_HI__MASK 0xffffffff 54602d756322SRob Clark #define A5XX_SSBO_2_1_BASE_HI__SHIFT 0 54612d756322SRob Clark static inline uint32_t A5XX_SSBO_2_1_BASE_HI(uint32_t val) 54622d756322SRob Clark { 54632d756322SRob Clark return ((val) << A5XX_SSBO_2_1_BASE_HI__SHIFT) & A5XX_SSBO_2_1_BASE_HI__MASK; 54642d756322SRob Clark } 54652d756322SRob Clark 5466c28c82e9SRob Clark #define REG_A5XX_UBO_0 0x00000000 5467c28c82e9SRob Clark #define A5XX_UBO_0_BASE_LO__MASK 0xffffffff 5468c28c82e9SRob Clark #define A5XX_UBO_0_BASE_LO__SHIFT 0 5469c28c82e9SRob Clark static inline uint32_t A5XX_UBO_0_BASE_LO(uint32_t val) 5470c28c82e9SRob Clark { 5471c28c82e9SRob Clark return ((val) << A5XX_UBO_0_BASE_LO__SHIFT) & A5XX_UBO_0_BASE_LO__MASK; 5472c28c82e9SRob Clark } 5473c28c82e9SRob Clark 5474c28c82e9SRob Clark #define REG_A5XX_UBO_1 0x00000001 5475c28c82e9SRob Clark #define A5XX_UBO_1_BASE_HI__MASK 0x0001ffff 5476c28c82e9SRob Clark #define A5XX_UBO_1_BASE_HI__SHIFT 0 5477c28c82e9SRob Clark static inline uint32_t A5XX_UBO_1_BASE_HI(uint32_t val) 5478c28c82e9SRob Clark { 5479c28c82e9SRob Clark return ((val) << A5XX_UBO_1_BASE_HI__SHIFT) & A5XX_UBO_1_BASE_HI__MASK; 5480c28c82e9SRob Clark } 5481c28c82e9SRob Clark 5482a26ae754SRob Clark 5483a26ae754SRob Clark #endif /* A5XX_XML */ 5484