1a26ae754SRob Clark #ifndef A5XX_XML 2a26ae754SRob Clark #define A5XX_XML 3a26ae754SRob Clark 4a26ae754SRob Clark /* Autogenerated file, DO NOT EDIT manually! 5a26ae754SRob Clark 6a26ae754SRob Clark This file was generated by the rules-ng-ng headergen tool in this git repository: 7a26ae754SRob Clark http://github.com/freedreno/envytools/ 8a26ae754SRob Clark git clone https://github.com/freedreno/envytools.git 9a26ae754SRob Clark 10a26ae754SRob Clark The rules-ng-ng source files this header was generated from are: 11a26ae754SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44) 12a26ae754SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) 13a26ae754SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08) 14a26ae754SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08) 15a26ae754SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08) 16a26ae754SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08) 17a26ae754SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48) 18a26ae754SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05) 19a26ae754SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) 20a26ae754SRob Clark 21a26ae754SRob Clark Copyright (C) 2013-2016 by the following authors: 22a26ae754SRob Clark - Rob Clark <robdclark@gmail.com> (robclark) 23a26ae754SRob Clark - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 24a26ae754SRob Clark 25a26ae754SRob Clark Permission is hereby granted, free of charge, to any person obtaining 26a26ae754SRob Clark a copy of this software and associated documentation files (the 27a26ae754SRob Clark "Software"), to deal in the Software without restriction, including 28a26ae754SRob Clark without limitation the rights to use, copy, modify, merge, publish, 29a26ae754SRob Clark distribute, sublicense, and/or sell copies of the Software, and to 30a26ae754SRob Clark permit persons to whom the Software is furnished to do so, subject to 31a26ae754SRob Clark the following conditions: 32a26ae754SRob Clark 33a26ae754SRob Clark The above copyright notice and this permission notice (including the 34a26ae754SRob Clark next paragraph) shall be included in all copies or substantial 35a26ae754SRob Clark portions of the Software. 36a26ae754SRob Clark 37a26ae754SRob Clark THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 38a26ae754SRob Clark EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 39a26ae754SRob Clark MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 40a26ae754SRob Clark IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 41a26ae754SRob Clark LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 42a26ae754SRob Clark OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 43a26ae754SRob Clark WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 44a26ae754SRob Clark */ 45a26ae754SRob Clark 46a26ae754SRob Clark 47a26ae754SRob Clark enum a5xx_color_fmt { 48a26ae754SRob Clark RB5_R8_UNORM = 3, 49a26ae754SRob Clark RB5_R4G4B4A4_UNORM = 8, 50a26ae754SRob Clark RB5_R5G5B5A1_UNORM = 10, 51a26ae754SRob Clark RB5_R5G6B5_UNORM = 14, 52a26ae754SRob Clark RB5_R16_FLOAT = 23, 53a26ae754SRob Clark RB5_R8G8B8A8_UNORM = 48, 54a26ae754SRob Clark RB5_R8G8B8_UNORM = 49, 55a26ae754SRob Clark RB5_R8G8B8A8_UINT = 51, 56a26ae754SRob Clark RB5_R10G10B10A2_UINT = 58, 57a26ae754SRob Clark RB5_R16G16_FLOAT = 69, 58a26ae754SRob Clark RB5_R32_FLOAT = 74, 59a26ae754SRob Clark RB5_R16G16B16A16_FLOAT = 98, 60a26ae754SRob Clark RB5_R32G32_FLOAT = 103, 61a26ae754SRob Clark RB5_R32G32B32A32_FLOAT = 130, 62a26ae754SRob Clark }; 63a26ae754SRob Clark 64a26ae754SRob Clark enum a5xx_tile_mode { 65a26ae754SRob Clark TILE5_LINEAR = 0, 66a26ae754SRob Clark TILE5_2 = 2, 67a26ae754SRob Clark TILE5_3 = 3, 68a26ae754SRob Clark }; 69a26ae754SRob Clark 70a26ae754SRob Clark enum a5xx_vtx_fmt { 71a26ae754SRob Clark VFMT5_8_UNORM = 3, 72a26ae754SRob Clark VFMT5_8_SNORM = 4, 73a26ae754SRob Clark VFMT5_8_UINT = 5, 74a26ae754SRob Clark VFMT5_8_SINT = 6, 75a26ae754SRob Clark VFMT5_8_8_UNORM = 15, 76a26ae754SRob Clark VFMT5_8_8_SNORM = 16, 77a26ae754SRob Clark VFMT5_8_8_UINT = 17, 78a26ae754SRob Clark VFMT5_8_8_SINT = 18, 79a26ae754SRob Clark VFMT5_16_UNORM = 21, 80a26ae754SRob Clark VFMT5_16_SNORM = 22, 81a26ae754SRob Clark VFMT5_16_FLOAT = 23, 82a26ae754SRob Clark VFMT5_16_UINT = 24, 83a26ae754SRob Clark VFMT5_16_SINT = 25, 84a26ae754SRob Clark VFMT5_8_8_8_UNORM = 33, 85a26ae754SRob Clark VFMT5_8_8_8_SNORM = 34, 86a26ae754SRob Clark VFMT5_8_8_8_UINT = 35, 87a26ae754SRob Clark VFMT5_8_8_8_SINT = 36, 88a26ae754SRob Clark VFMT5_8_8_8_8_UNORM = 48, 89a26ae754SRob Clark VFMT5_8_8_8_8_SNORM = 50, 90a26ae754SRob Clark VFMT5_8_8_8_8_UINT = 51, 91a26ae754SRob Clark VFMT5_8_8_8_8_SINT = 52, 92a26ae754SRob Clark VFMT5_16_16_UNORM = 67, 93a26ae754SRob Clark VFMT5_16_16_SNORM = 68, 94a26ae754SRob Clark VFMT5_16_16_FLOAT = 69, 95a26ae754SRob Clark VFMT5_16_16_UINT = 70, 96a26ae754SRob Clark VFMT5_16_16_SINT = 71, 97a26ae754SRob Clark VFMT5_32_UNORM = 72, 98a26ae754SRob Clark VFMT5_32_SNORM = 73, 99a26ae754SRob Clark VFMT5_32_FLOAT = 74, 100a26ae754SRob Clark VFMT5_32_UINT = 75, 101a26ae754SRob Clark VFMT5_32_SINT = 76, 102a26ae754SRob Clark VFMT5_32_FIXED = 77, 103a26ae754SRob Clark VFMT5_16_16_16_UNORM = 88, 104a26ae754SRob Clark VFMT5_16_16_16_SNORM = 89, 105a26ae754SRob Clark VFMT5_16_16_16_FLOAT = 90, 106a26ae754SRob Clark VFMT5_16_16_16_UINT = 91, 107a26ae754SRob Clark VFMT5_16_16_16_SINT = 92, 108a26ae754SRob Clark VFMT5_16_16_16_16_UNORM = 96, 109a26ae754SRob Clark VFMT5_16_16_16_16_SNORM = 97, 110a26ae754SRob Clark VFMT5_16_16_16_16_FLOAT = 98, 111a26ae754SRob Clark VFMT5_16_16_16_16_UINT = 99, 112a26ae754SRob Clark VFMT5_16_16_16_16_SINT = 100, 113a26ae754SRob Clark VFMT5_32_32_UNORM = 101, 114a26ae754SRob Clark VFMT5_32_32_SNORM = 102, 115a26ae754SRob Clark VFMT5_32_32_FLOAT = 103, 116a26ae754SRob Clark VFMT5_32_32_UINT = 104, 117a26ae754SRob Clark VFMT5_32_32_SINT = 105, 118a26ae754SRob Clark VFMT5_32_32_FIXED = 106, 119a26ae754SRob Clark VFMT5_32_32_32_UNORM = 112, 120a26ae754SRob Clark VFMT5_32_32_32_SNORM = 113, 121a26ae754SRob Clark VFMT5_32_32_32_UINT = 114, 122a26ae754SRob Clark VFMT5_32_32_32_SINT = 115, 123a26ae754SRob Clark VFMT5_32_32_32_FLOAT = 116, 124a26ae754SRob Clark VFMT5_32_32_32_FIXED = 117, 125a26ae754SRob Clark VFMT5_32_32_32_32_UNORM = 128, 126a26ae754SRob Clark VFMT5_32_32_32_32_SNORM = 129, 127a26ae754SRob Clark VFMT5_32_32_32_32_FLOAT = 130, 128a26ae754SRob Clark VFMT5_32_32_32_32_UINT = 131, 129a26ae754SRob Clark VFMT5_32_32_32_32_SINT = 132, 130a26ae754SRob Clark VFMT5_32_32_32_32_FIXED = 133, 131a26ae754SRob Clark }; 132a26ae754SRob Clark 133a26ae754SRob Clark enum a5xx_tex_fmt { 134a26ae754SRob Clark TFMT5_A8_UNORM = 2, 135a26ae754SRob Clark TFMT5_8_UNORM = 3, 136a26ae754SRob Clark TFMT5_4_4_4_4_UNORM = 8, 137a26ae754SRob Clark TFMT5_5_5_5_1_UNORM = 10, 138a26ae754SRob Clark TFMT5_5_6_5_UNORM = 14, 139a26ae754SRob Clark TFMT5_8_8_UNORM = 15, 140a26ae754SRob Clark TFMT5_8_8_SNORM = 16, 141a26ae754SRob Clark TFMT5_L8_A8_UNORM = 19, 142a26ae754SRob Clark TFMT5_16_FLOAT = 23, 143a26ae754SRob Clark TFMT5_8_8_8_8_UNORM = 48, 144a26ae754SRob Clark TFMT5_8_8_8_UNORM = 49, 145a26ae754SRob Clark TFMT5_8_8_8_SNORM = 50, 146a26ae754SRob Clark TFMT5_9_9_9_E5_FLOAT = 53, 147a26ae754SRob Clark TFMT5_10_10_10_2_UNORM = 54, 148a26ae754SRob Clark TFMT5_11_11_10_FLOAT = 66, 149a26ae754SRob Clark TFMT5_16_16_FLOAT = 69, 150a26ae754SRob Clark TFMT5_32_FLOAT = 74, 151a26ae754SRob Clark TFMT5_16_16_16_16_FLOAT = 98, 152a26ae754SRob Clark TFMT5_32_32_FLOAT = 103, 153a26ae754SRob Clark TFMT5_32_32_32_32_FLOAT = 130, 154a26ae754SRob Clark TFMT5_X8Z24_UNORM = 160, 155a26ae754SRob Clark }; 156a26ae754SRob Clark 157a26ae754SRob Clark enum a5xx_tex_fetchsize { 158a26ae754SRob Clark TFETCH5_1_BYTE = 0, 159a26ae754SRob Clark TFETCH5_2_BYTE = 1, 160a26ae754SRob Clark TFETCH5_4_BYTE = 2, 161a26ae754SRob Clark TFETCH5_8_BYTE = 3, 162a26ae754SRob Clark TFETCH5_16_BYTE = 4, 163a26ae754SRob Clark }; 164a26ae754SRob Clark 165a26ae754SRob Clark enum a5xx_depth_format { 166a26ae754SRob Clark DEPTH5_NONE = 0, 167a26ae754SRob Clark DEPTH5_16 = 1, 168a26ae754SRob Clark DEPTH5_24_8 = 2, 169a26ae754SRob Clark DEPTH5_32 = 4, 170a26ae754SRob Clark }; 171a26ae754SRob Clark 172a26ae754SRob Clark enum a5xx_blit_buf { 173a26ae754SRob Clark BLIT_MRT0 = 0, 174a26ae754SRob Clark BLIT_MRT1 = 1, 175a26ae754SRob Clark BLIT_MRT2 = 2, 176a26ae754SRob Clark BLIT_MRT3 = 3, 177a26ae754SRob Clark BLIT_MRT4 = 4, 178a26ae754SRob Clark BLIT_MRT5 = 5, 179a26ae754SRob Clark BLIT_MRT6 = 6, 180a26ae754SRob Clark BLIT_MRT7 = 7, 181a26ae754SRob Clark BLIT_ZS = 8, 182a26ae754SRob Clark BLIT_Z32 = 9, 183a26ae754SRob Clark }; 184a26ae754SRob Clark 185a26ae754SRob Clark enum a5xx_tex_filter { 186a26ae754SRob Clark A5XX_TEX_NEAREST = 0, 187a26ae754SRob Clark A5XX_TEX_LINEAR = 1, 188a26ae754SRob Clark A5XX_TEX_ANISO = 2, 189a26ae754SRob Clark }; 190a26ae754SRob Clark 191a26ae754SRob Clark enum a5xx_tex_clamp { 192a26ae754SRob Clark A5XX_TEX_REPEAT = 0, 193a26ae754SRob Clark A5XX_TEX_CLAMP_TO_EDGE = 1, 194a26ae754SRob Clark A5XX_TEX_MIRROR_REPEAT = 2, 195a26ae754SRob Clark A5XX_TEX_CLAMP_TO_BORDER = 3, 196a26ae754SRob Clark A5XX_TEX_MIRROR_CLAMP = 4, 197a26ae754SRob Clark }; 198a26ae754SRob Clark 199a26ae754SRob Clark enum a5xx_tex_aniso { 200a26ae754SRob Clark A5XX_TEX_ANISO_1 = 0, 201a26ae754SRob Clark A5XX_TEX_ANISO_2 = 1, 202a26ae754SRob Clark A5XX_TEX_ANISO_4 = 2, 203a26ae754SRob Clark A5XX_TEX_ANISO_8 = 3, 204a26ae754SRob Clark A5XX_TEX_ANISO_16 = 4, 205a26ae754SRob Clark }; 206a26ae754SRob Clark 207a26ae754SRob Clark enum a5xx_tex_swiz { 208a26ae754SRob Clark A5XX_TEX_X = 0, 209a26ae754SRob Clark A5XX_TEX_Y = 1, 210a26ae754SRob Clark A5XX_TEX_Z = 2, 211a26ae754SRob Clark A5XX_TEX_W = 3, 212a26ae754SRob Clark A5XX_TEX_ZERO = 4, 213a26ae754SRob Clark A5XX_TEX_ONE = 5, 214a26ae754SRob Clark }; 215a26ae754SRob Clark 216a26ae754SRob Clark enum a5xx_tex_type { 217a26ae754SRob Clark A5XX_TEX_1D = 0, 218a26ae754SRob Clark A5XX_TEX_2D = 1, 219a26ae754SRob Clark A5XX_TEX_CUBE = 2, 220a26ae754SRob Clark A5XX_TEX_3D = 3, 221a26ae754SRob Clark }; 222a26ae754SRob Clark 223a26ae754SRob Clark #define A5XX_INT0_RBBM_GPU_IDLE 0x00000001 224a26ae754SRob Clark #define A5XX_INT0_RBBM_AHB_ERROR 0x00000002 225a26ae754SRob Clark #define A5XX_INT0_RBBM_TRANSFER_TIMEOUT 0x00000004 226a26ae754SRob Clark #define A5XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 227a26ae754SRob Clark #define A5XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 228a26ae754SRob Clark #define A5XX_INT0_RBBM_ETS_MS_TIMEOUT 0x00000020 229a26ae754SRob Clark #define A5XX_INT0_RBBM_ATB_ASYNC_OVERFLOW 0x00000040 230a26ae754SRob Clark #define A5XX_INT0_RBBM_GPC_ERROR 0x00000080 231a26ae754SRob Clark #define A5XX_INT0_CP_SW 0x00000100 232a26ae754SRob Clark #define A5XX_INT0_CP_HW_ERROR 0x00000200 233a26ae754SRob Clark #define A5XX_INT0_CP_CCU_FLUSH_DEPTH_TS 0x00000400 234a26ae754SRob Clark #define A5XX_INT0_CP_CCU_FLUSH_COLOR_TS 0x00000800 235a26ae754SRob Clark #define A5XX_INT0_CP_CCU_RESOLVE_TS 0x00001000 236a26ae754SRob Clark #define A5XX_INT0_CP_IB2 0x00002000 237a26ae754SRob Clark #define A5XX_INT0_CP_IB1 0x00004000 238a26ae754SRob Clark #define A5XX_INT0_CP_RB 0x00008000 239a26ae754SRob Clark #define A5XX_INT0_CP_UNUSED_1 0x00010000 240a26ae754SRob Clark #define A5XX_INT0_CP_RB_DONE_TS 0x00020000 241a26ae754SRob Clark #define A5XX_INT0_CP_WT_DONE_TS 0x00040000 242a26ae754SRob Clark #define A5XX_INT0_UNKNOWN_1 0x00080000 243a26ae754SRob Clark #define A5XX_INT0_CP_CACHE_FLUSH_TS 0x00100000 244a26ae754SRob Clark #define A5XX_INT0_UNUSED_2 0x00200000 245a26ae754SRob Clark #define A5XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00400000 246a26ae754SRob Clark #define A5XX_INT0_MISC_HANG_DETECT 0x00800000 247a26ae754SRob Clark #define A5XX_INT0_UCHE_OOB_ACCESS 0x01000000 248a26ae754SRob Clark #define A5XX_INT0_UCHE_TRAP_INTR 0x02000000 249a26ae754SRob Clark #define A5XX_INT0_DEBBUS_INTR_0 0x04000000 250a26ae754SRob Clark #define A5XX_INT0_DEBBUS_INTR_1 0x08000000 251a26ae754SRob Clark #define A5XX_INT0_GPMU_VOLTAGE_DROOP 0x10000000 252a26ae754SRob Clark #define A5XX_INT0_GPMU_FIRMWARE 0x20000000 253a26ae754SRob Clark #define A5XX_INT0_ISDB_CPU_IRQ 0x40000000 254a26ae754SRob Clark #define A5XX_INT0_ISDB_UNDER_DEBUG 0x80000000 255a26ae754SRob Clark #define A5XX_CP_INT_CP_OPCODE_ERROR 0x00000001 256a26ae754SRob Clark #define A5XX_CP_INT_CP_RESERVED_BIT_ERROR 0x00000002 257a26ae754SRob Clark #define A5XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004 258a26ae754SRob Clark #define A5XX_CP_INT_CP_DMA_ERROR 0x00000008 259a26ae754SRob Clark #define A5XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010 260a26ae754SRob Clark #define A5XX_CP_INT_CP_AHB_ERROR 0x00000020 261a26ae754SRob Clark #define REG_A5XX_CP_RB_BASE 0x00000800 262a26ae754SRob Clark 263a26ae754SRob Clark #define REG_A5XX_CP_RB_BASE_HI 0x00000801 264a26ae754SRob Clark 265a26ae754SRob Clark #define REG_A5XX_CP_RB_CNTL 0x00000802 266a26ae754SRob Clark 267a26ae754SRob Clark #define REG_A5XX_CP_RB_RPTR_ADDR 0x00000804 268a26ae754SRob Clark 269a26ae754SRob Clark #define REG_A5XX_CP_RB_RPTR_ADDR_HI 0x00000805 270a26ae754SRob Clark 271a26ae754SRob Clark #define REG_A5XX_CP_RB_RPTR 0x00000806 272a26ae754SRob Clark 273a26ae754SRob Clark #define REG_A5XX_CP_RB_WPTR 0x00000807 274a26ae754SRob Clark 275a26ae754SRob Clark #define REG_A5XX_CP_PFP_STAT_ADDR 0x00000808 276a26ae754SRob Clark 277a26ae754SRob Clark #define REG_A5XX_CP_PFP_STAT_DATA 0x00000809 278a26ae754SRob Clark 279a26ae754SRob Clark #define REG_A5XX_CP_DRAW_STATE_ADDR 0x0000080b 280a26ae754SRob Clark 281a26ae754SRob Clark #define REG_A5XX_CP_DRAW_STATE_DATA 0x0000080c 282a26ae754SRob Clark 283a26ae754SRob Clark #define REG_A5XX_CP_CRASH_SCRIPT_BASE_LO 0x00000817 284a26ae754SRob Clark 285a26ae754SRob Clark #define REG_A5XX_CP_CRASH_SCRIPT_BASE_HI 0x00000818 286a26ae754SRob Clark 287a26ae754SRob Clark #define REG_A5XX_CP_CRASH_DUMP_CNTL 0x00000819 288a26ae754SRob Clark 289a26ae754SRob Clark #define REG_A5XX_CP_ME_STAT_ADDR 0x0000081a 290a26ae754SRob Clark 291a26ae754SRob Clark #define REG_A5XX_CP_ROQ_THRESHOLDS_1 0x0000081f 292a26ae754SRob Clark 293a26ae754SRob Clark #define REG_A5XX_CP_ROQ_THRESHOLDS_2 0x00000820 294a26ae754SRob Clark 295a26ae754SRob Clark #define REG_A5XX_CP_ROQ_DBG_ADDR 0x00000821 296a26ae754SRob Clark 297a26ae754SRob Clark #define REG_A5XX_CP_ROQ_DBG_DATA 0x00000822 298a26ae754SRob Clark 299a26ae754SRob Clark #define REG_A5XX_CP_MEQ_DBG_ADDR 0x00000823 300a26ae754SRob Clark 301a26ae754SRob Clark #define REG_A5XX_CP_MEQ_DBG_DATA 0x00000824 302a26ae754SRob Clark 303a26ae754SRob Clark #define REG_A5XX_CP_MEQ_THRESHOLDS 0x00000825 304a26ae754SRob Clark 305a26ae754SRob Clark #define REG_A5XX_CP_MERCIU_SIZE 0x00000826 306a26ae754SRob Clark 307a26ae754SRob Clark #define REG_A5XX_CP_MERCIU_DBG_ADDR 0x00000827 308a26ae754SRob Clark 309a26ae754SRob Clark #define REG_A5XX_CP_MERCIU_DBG_DATA_1 0x00000828 310a26ae754SRob Clark 311a26ae754SRob Clark #define REG_A5XX_CP_MERCIU_DBG_DATA_2 0x00000829 312a26ae754SRob Clark 313a26ae754SRob Clark #define REG_A5XX_CP_PFP_UCODE_DBG_ADDR 0x0000082a 314a26ae754SRob Clark 315a26ae754SRob Clark #define REG_A5XX_CP_PFP_UCODE_DBG_DATA 0x0000082b 316a26ae754SRob Clark 317a26ae754SRob Clark #define REG_A5XX_CP_ME_UCODE_DBG_ADDR 0x0000082f 318a26ae754SRob Clark 319a26ae754SRob Clark #define REG_A5XX_CP_ME_UCODE_DBG_DATA 0x00000830 320a26ae754SRob Clark 321a26ae754SRob Clark #define REG_A5XX_CP_CNTL 0x00000831 322a26ae754SRob Clark 323a26ae754SRob Clark #define REG_A5XX_CP_PFP_ME_CNTL 0x00000832 324a26ae754SRob Clark 325a26ae754SRob Clark #define REG_A5XX_CP_CHICKEN_DBG 0x00000833 326a26ae754SRob Clark 327a26ae754SRob Clark #define REG_A5XX_CP_PFP_INSTR_BASE_LO 0x00000835 328a26ae754SRob Clark 329a26ae754SRob Clark #define REG_A5XX_CP_PFP_INSTR_BASE_HI 0x00000836 330a26ae754SRob Clark 331a26ae754SRob Clark #define REG_A5XX_CP_ME_INSTR_BASE_LO 0x00000838 332a26ae754SRob Clark 333a26ae754SRob Clark #define REG_A5XX_CP_ME_INSTR_BASE_HI 0x00000839 334a26ae754SRob Clark 335a26ae754SRob Clark #define REG_A5XX_CP_CONTEXT_SWITCH_CNTL 0x0000083b 336a26ae754SRob Clark 337a26ae754SRob Clark #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO 0x0000083c 338a26ae754SRob Clark 339a26ae754SRob Clark #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI 0x0000083d 340a26ae754SRob Clark 341a26ae754SRob Clark #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO 0x0000083e 342a26ae754SRob Clark 343a26ae754SRob Clark #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_HI 0x0000083f 344a26ae754SRob Clark 345a26ae754SRob Clark #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x00000840 346a26ae754SRob Clark 347a26ae754SRob Clark #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x00000841 348a26ae754SRob Clark 349a26ae754SRob Clark #define REG_A5XX_CP_ADDR_MODE_CNTL 0x00000860 350a26ae754SRob Clark 351a26ae754SRob Clark #define REG_A5XX_CP_ME_STAT_DATA 0x00000b14 352a26ae754SRob Clark 353a26ae754SRob Clark #define REG_A5XX_CP_WFI_PEND_CTR 0x00000b15 354a26ae754SRob Clark 355a26ae754SRob Clark #define REG_A5XX_CP_INTERRUPT_STATUS 0x00000b18 356a26ae754SRob Clark 357a26ae754SRob Clark #define REG_A5XX_CP_HW_FAULT 0x00000b1a 358a26ae754SRob Clark 359a26ae754SRob Clark #define REG_A5XX_CP_PROTECT_STATUS 0x00000b1c 360a26ae754SRob Clark 361a26ae754SRob Clark #define REG_A5XX_CP_IB1_BASE 0x00000b1f 362a26ae754SRob Clark 363a26ae754SRob Clark #define REG_A5XX_CP_IB1_BASE_HI 0x00000b20 364a26ae754SRob Clark 365a26ae754SRob Clark #define REG_A5XX_CP_IB1_BUFSZ 0x00000b21 366a26ae754SRob Clark 367a26ae754SRob Clark #define REG_A5XX_CP_IB2_BASE 0x00000b22 368a26ae754SRob Clark 369a26ae754SRob Clark #define REG_A5XX_CP_IB2_BASE_HI 0x00000b23 370a26ae754SRob Clark 371a26ae754SRob Clark #define REG_A5XX_CP_IB2_BUFSZ 0x00000b24 372a26ae754SRob Clark 373a26ae754SRob Clark static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0) { return 0x00000b78 + 0x1*i0; } 374a26ae754SRob Clark 375a26ae754SRob Clark static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; } 376a26ae754SRob Clark 377a26ae754SRob Clark static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0) { return 0x00000880 + 0x1*i0; } 378a26ae754SRob Clark 379a26ae754SRob Clark static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; } 380a26ae754SRob Clark #define A5XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff 381a26ae754SRob Clark #define A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0 382a26ae754SRob Clark static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) 383a26ae754SRob Clark { 384a26ae754SRob Clark return ((val) << A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A5XX_CP_PROTECT_REG_BASE_ADDR__MASK; 385a26ae754SRob Clark } 386a26ae754SRob Clark #define A5XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000 387a26ae754SRob Clark #define A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24 388a26ae754SRob Clark static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) 389a26ae754SRob Clark { 390a26ae754SRob Clark return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK; 391a26ae754SRob Clark } 392a26ae754SRob Clark #define A5XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000 393a26ae754SRob Clark #define A5XX_CP_PROTECT_REG_TRAP_READ 0x40000000 394a26ae754SRob Clark 395a26ae754SRob Clark #define REG_A5XX_CP_PROTECT_CNTL 0x000008a0 396a26ae754SRob Clark 397a26ae754SRob Clark #define REG_A5XX_CP_AHB_FAULT 0x00000b1b 398a26ae754SRob Clark 399a26ae754SRob Clark #define REG_A5XX_CP_PERFCTR_CP_SEL_0 0x00000bb0 400a26ae754SRob Clark 401a26ae754SRob Clark #define REG_A5XX_CP_PERFCTR_CP_SEL_1 0x00000bb1 402a26ae754SRob Clark 403a26ae754SRob Clark #define REG_A5XX_CP_PERFCTR_CP_SEL_2 0x00000bb2 404a26ae754SRob Clark 405a26ae754SRob Clark #define REG_A5XX_CP_PERFCTR_CP_SEL_3 0x00000bb3 406a26ae754SRob Clark 407a26ae754SRob Clark #define REG_A5XX_CP_PERFCTR_CP_SEL_4 0x00000bb4 408a26ae754SRob Clark 409a26ae754SRob Clark #define REG_A5XX_CP_PERFCTR_CP_SEL_5 0x00000bb5 410a26ae754SRob Clark 411a26ae754SRob Clark #define REG_A5XX_CP_PERFCTR_CP_SEL_6 0x00000bb6 412a26ae754SRob Clark 413a26ae754SRob Clark #define REG_A5XX_CP_PERFCTR_CP_SEL_7 0x00000bb7 414a26ae754SRob Clark 415a26ae754SRob Clark #define REG_A5XX_VSC_ADDR_MODE_CNTL 0x00000bc1 416a26ae754SRob Clark 417a26ae754SRob Clark #define REG_A5XX_CP_POWERCTR_CP_SEL_0 0x00000bba 418a26ae754SRob Clark 419a26ae754SRob Clark #define REG_A5XX_CP_POWERCTR_CP_SEL_1 0x00000bbb 420a26ae754SRob Clark 421a26ae754SRob Clark #define REG_A5XX_CP_POWERCTR_CP_SEL_2 0x00000bbc 422a26ae754SRob Clark 423a26ae754SRob Clark #define REG_A5XX_CP_POWERCTR_CP_SEL_3 0x00000bbd 424a26ae754SRob Clark 425a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_A 0x00000004 426a26ae754SRob Clark 427a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_B 0x00000005 428a26ae754SRob Clark 429a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_C 0x00000006 430a26ae754SRob Clark 431a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_D 0x00000007 432a26ae754SRob Clark 433a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLT 0x00000008 434a26ae754SRob Clark 435a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLM 0x00000009 436a26ae754SRob Clark 437a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT 0x00000018 438a26ae754SRob Clark 439a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_OPL 0x0000000a 440a26ae754SRob Clark 441a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_OPE 0x0000000b 442a26ae754SRob Clark 443a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_0 0x0000000c 444a26ae754SRob Clark 445a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_1 0x0000000d 446a26ae754SRob Clark 447a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_2 0x0000000e 448a26ae754SRob Clark 449a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_3 0x0000000f 450a26ae754SRob Clark 451a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_0 0x00000010 452a26ae754SRob Clark 453a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_1 0x00000011 454a26ae754SRob Clark 455a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_2 0x00000012 456a26ae754SRob Clark 457a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_3 0x00000013 458a26ae754SRob Clark 459a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_0 0x00000014 460a26ae754SRob Clark 461a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_1 0x00000015 462a26ae754SRob Clark 463a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_0 0x00000016 464a26ae754SRob Clark 465a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_1 0x00000017 466a26ae754SRob Clark 467a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_2 0x00000018 468a26ae754SRob Clark 469a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_3 0x00000019 470a26ae754SRob Clark 471a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_0 0x0000001a 472a26ae754SRob Clark 473a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_1 0x0000001b 474a26ae754SRob Clark 475a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_2 0x0000001c 476a26ae754SRob Clark 477a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_3 0x0000001d 478a26ae754SRob Clark 479a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_NIBBLEE 0x0000001e 480a26ae754SRob Clark 481a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC0 0x0000001f 482a26ae754SRob Clark 483a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC1 0x00000020 484a26ae754SRob Clark 485a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_LOADREG 0x00000021 486a26ae754SRob Clark 487a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_IDX 0x00000022 488a26ae754SRob Clark 489a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_CLRC 0x00000023 490a26ae754SRob Clark 491a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_LOADIVT 0x00000024 492a26ae754SRob Clark 493a26ae754SRob Clark #define REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000002f 494a26ae754SRob Clark 495a26ae754SRob Clark #define REG_A5XX_RBBM_INT_CLEAR_CMD 0x00000037 496a26ae754SRob Clark 497a26ae754SRob Clark #define REG_A5XX_RBBM_INT_0_MASK 0x00000038 498a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001 499a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR 0x00000002 500a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT 0x00000004 501a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT 0x00000008 502a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT 0x00000010 503a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT 0x00000020 504a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW 0x00000040 505a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080 506a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_CP_SW 0x00000100 507a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200 508a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400 509a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800 510a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000 511a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_CP_IB2 0x00002000 512a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_CP_IB1 0x00004000 513a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_CP_RB 0x00008000 514a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000 515a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000 516a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000 517a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000 518a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT 0x00800000 519a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000 520a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000 521a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000 522a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000 523a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP 0x10000000 524a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_GPMU_FIRMWARE 0x20000000 525a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000 526a26ae754SRob Clark #define A5XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000 527a26ae754SRob Clark 528a26ae754SRob Clark #define REG_A5XX_RBBM_AHB_DBG_CNTL 0x0000003f 529a26ae754SRob Clark 530a26ae754SRob Clark #define REG_A5XX_RBBM_EXT_VBIF_DBG_CNTL 0x00000041 531a26ae754SRob Clark 532a26ae754SRob Clark #define REG_A5XX_RBBM_SW_RESET_CMD 0x00000043 533a26ae754SRob Clark 534a26ae754SRob Clark #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 535a26ae754SRob Clark 536a26ae754SRob Clark #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046 537a26ae754SRob Clark 538a26ae754SRob Clark #define REG_A5XX_RBBM_DBG_LO_HI_GPIO 0x00000048 539a26ae754SRob Clark 540a26ae754SRob Clark #define REG_A5XX_RBBM_EXT_TRACE_BUS_CNTL 0x00000049 541a26ae754SRob Clark 542a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_TP0 0x0000004a 543a26ae754SRob Clark 544a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_TP1 0x0000004b 545a26ae754SRob Clark 546a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_TP2 0x0000004c 547a26ae754SRob Clark 548a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_TP3 0x0000004d 549a26ae754SRob Clark 550a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL2_TP0 0x0000004e 551a26ae754SRob Clark 552a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL2_TP1 0x0000004f 553a26ae754SRob Clark 554a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL2_TP2 0x00000050 555a26ae754SRob Clark 556a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL2_TP3 0x00000051 557a26ae754SRob Clark 558a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL3_TP0 0x00000052 559a26ae754SRob Clark 560a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL3_TP1 0x00000053 561a26ae754SRob Clark 562a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL3_TP2 0x00000054 563a26ae754SRob Clark 564a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL3_TP3 0x00000055 565a26ae754SRob Clark 566a26ae754SRob Clark #define REG_A5XX_RBBM_READ_AHB_THROUGH_DBG 0x00000059 567a26ae754SRob Clark 568a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_UCHE 0x0000005a 569a26ae754SRob Clark 570a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL2_UCHE 0x0000005b 571a26ae754SRob Clark 572a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL3_UCHE 0x0000005c 573a26ae754SRob Clark 574a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL4_UCHE 0x0000005d 575a26ae754SRob Clark 576a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_UCHE 0x0000005e 577a26ae754SRob Clark 578a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_UCHE 0x0000005f 579a26ae754SRob Clark 580a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_MODE_GPC 0x00000060 581a26ae754SRob Clark 582a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_GPC 0x00000061 583a26ae754SRob Clark 584a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_GPC 0x00000062 585a26ae754SRob Clark 586a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000063 587a26ae754SRob Clark 588a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x00000064 589a26ae754SRob Clark 590a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000065 591a26ae754SRob Clark 592a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_HLSQ 0x00000066 593a26ae754SRob Clark 594a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL 0x00000067 595a26ae754SRob Clark 596a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_SP0 0x00000068 597a26ae754SRob Clark 598a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_SP1 0x00000069 599a26ae754SRob Clark 600a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_SP2 0x0000006a 601a26ae754SRob Clark 602a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_SP3 0x0000006b 603a26ae754SRob Clark 604a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL2_SP0 0x0000006c 605a26ae754SRob Clark 606a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL2_SP1 0x0000006d 607a26ae754SRob Clark 608a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL2_SP2 0x0000006e 609a26ae754SRob Clark 610a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL2_SP3 0x0000006f 611a26ae754SRob Clark 612a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_SP0 0x00000070 613a26ae754SRob Clark 614a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_SP1 0x00000071 615a26ae754SRob Clark 616a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_SP2 0x00000072 617a26ae754SRob Clark 618a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_SP3 0x00000073 619a26ae754SRob Clark 620a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_SP0 0x00000074 621a26ae754SRob Clark 622a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_SP1 0x00000075 623a26ae754SRob Clark 624a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_SP2 0x00000076 625a26ae754SRob Clark 626a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_SP3 0x00000077 627a26ae754SRob Clark 628a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_RB0 0x00000078 629a26ae754SRob Clark 630a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_RB1 0x00000079 631a26ae754SRob Clark 632a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_RB2 0x0000007a 633a26ae754SRob Clark 634a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_RB3 0x0000007b 635a26ae754SRob Clark 636a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL2_RB0 0x0000007c 637a26ae754SRob Clark 638a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL2_RB1 0x0000007d 639a26ae754SRob Clark 640a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL2_RB2 0x0000007e 641a26ae754SRob Clark 642a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL2_RB3 0x0000007f 643a26ae754SRob Clark 644a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_RAC 0x00000080 645a26ae754SRob Clark 646a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_RAC 0x00000081 647a26ae754SRob Clark 648a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_CCU0 0x00000082 649a26ae754SRob Clark 650a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_CCU1 0x00000083 651a26ae754SRob Clark 652a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_CCU2 0x00000084 653a26ae754SRob Clark 654a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_CCU3 0x00000085 655a26ae754SRob Clark 656a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000086 657a26ae754SRob Clark 658a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000087 659a26ae754SRob Clark 660a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000088 661a26ae754SRob Clark 662a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000089 663a26ae754SRob Clark 664a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_RAC 0x0000008a 665a26ae754SRob Clark 666a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL2_RAC 0x0000008b 667a26ae754SRob Clark 668a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0 0x0000008c 669a26ae754SRob Clark 670a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1 0x0000008d 671a26ae754SRob Clark 672a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2 0x0000008e 673a26ae754SRob Clark 674a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3 0x0000008f 675a26ae754SRob Clark 676a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_VFD 0x00000090 677a26ae754SRob Clark 678a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_MODE_VFD 0x00000091 679a26ae754SRob Clark 680a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_VFD 0x00000092 681a26ae754SRob Clark 682a26ae754SRob Clark #define REG_A5XX_RBBM_AHB_CNTL0 0x00000093 683a26ae754SRob Clark 684a26ae754SRob Clark #define REG_A5XX_RBBM_AHB_CNTL1 0x00000094 685a26ae754SRob Clark 686a26ae754SRob Clark #define REG_A5XX_RBBM_AHB_CNTL2 0x00000095 687a26ae754SRob Clark 688a26ae754SRob Clark #define REG_A5XX_RBBM_AHB_CMD 0x00000096 689a26ae754SRob Clark 690a26ae754SRob Clark #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11 0x0000009c 691a26ae754SRob Clark 692a26ae754SRob Clark #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12 0x0000009d 693a26ae754SRob Clark 694a26ae754SRob Clark #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13 0x0000009e 695a26ae754SRob Clark 696a26ae754SRob Clark #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14 0x0000009f 697a26ae754SRob Clark 698a26ae754SRob Clark #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15 0x000000a0 699a26ae754SRob Clark 700a26ae754SRob Clark #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16 0x000000a1 701a26ae754SRob Clark 702a26ae754SRob Clark #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17 0x000000a2 703a26ae754SRob Clark 704a26ae754SRob Clark #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18 0x000000a3 705a26ae754SRob Clark 706a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_TP0 0x000000a4 707a26ae754SRob Clark 708a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_TP1 0x000000a5 709a26ae754SRob Clark 710a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_TP2 0x000000a6 711a26ae754SRob Clark 712a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_TP3 0x000000a7 713a26ae754SRob Clark 714a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY2_TP0 0x000000a8 715a26ae754SRob Clark 716a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY2_TP1 0x000000a9 717a26ae754SRob Clark 718a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY2_TP2 0x000000aa 719a26ae754SRob Clark 720a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY2_TP3 0x000000ab 721a26ae754SRob Clark 722a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY3_TP0 0x000000ac 723a26ae754SRob Clark 724a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY3_TP1 0x000000ad 725a26ae754SRob Clark 726a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY3_TP2 0x000000ae 727a26ae754SRob Clark 728a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY3_TP3 0x000000af 729a26ae754SRob Clark 730a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_TP0 0x000000b0 731a26ae754SRob Clark 732a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_TP1 0x000000b1 733a26ae754SRob Clark 734a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_TP2 0x000000b2 735a26ae754SRob Clark 736a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_TP3 0x000000b3 737a26ae754SRob Clark 738a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST2_TP0 0x000000b4 739a26ae754SRob Clark 740a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST2_TP1 0x000000b5 741a26ae754SRob Clark 742a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST2_TP2 0x000000b6 743a26ae754SRob Clark 744a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST2_TP3 0x000000b7 745a26ae754SRob Clark 746a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST3_TP0 0x000000b8 747a26ae754SRob Clark 748a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST3_TP1 0x000000b9 749a26ae754SRob Clark 750a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST3_TP2 0x000000ba 751a26ae754SRob Clark 752a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST3_TP3 0x000000bb 753a26ae754SRob Clark 754a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_CNTL_GPMU 0x000000c8 755a26ae754SRob Clark 756a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_DELAY_GPMU 0x000000c9 757a26ae754SRob Clark 758a26ae754SRob Clark #define REG_A5XX_RBBM_CLOCK_HYST_GPMU 0x000000ca 759a26ae754SRob Clark 760a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_0_LO 0x000003a0 761a26ae754SRob Clark 762a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_0_HI 0x000003a1 763a26ae754SRob Clark 764a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_1_LO 0x000003a2 765a26ae754SRob Clark 766a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_1_HI 0x000003a3 767a26ae754SRob Clark 768a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_2_LO 0x000003a4 769a26ae754SRob Clark 770a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_2_HI 0x000003a5 771a26ae754SRob Clark 772a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_3_LO 0x000003a6 773a26ae754SRob Clark 774a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_3_HI 0x000003a7 775a26ae754SRob Clark 776a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_4_LO 0x000003a8 777a26ae754SRob Clark 778a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_4_HI 0x000003a9 779a26ae754SRob Clark 780a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_5_LO 0x000003aa 781a26ae754SRob Clark 782a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_5_HI 0x000003ab 783a26ae754SRob Clark 784a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_6_LO 0x000003ac 785a26ae754SRob Clark 786a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_6_HI 0x000003ad 787a26ae754SRob Clark 788a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_7_LO 0x000003ae 789a26ae754SRob Clark 790a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CP_7_HI 0x000003af 791a26ae754SRob Clark 792a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RBBM_0_LO 0x000003b0 793a26ae754SRob Clark 794a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RBBM_0_HI 0x000003b1 795a26ae754SRob Clark 796a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RBBM_1_LO 0x000003b2 797a26ae754SRob Clark 798a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RBBM_1_HI 0x000003b3 799a26ae754SRob Clark 800a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RBBM_2_LO 0x000003b4 801a26ae754SRob Clark 802a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RBBM_2_HI 0x000003b5 803a26ae754SRob Clark 804a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RBBM_3_LO 0x000003b6 805a26ae754SRob Clark 806a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RBBM_3_HI 0x000003b7 807a26ae754SRob Clark 808a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_0_LO 0x000003b8 809a26ae754SRob Clark 810a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_0_HI 0x000003b9 811a26ae754SRob Clark 812a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_1_LO 0x000003ba 813a26ae754SRob Clark 814a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_1_HI 0x000003bb 815a26ae754SRob Clark 816a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_2_LO 0x000003bc 817a26ae754SRob Clark 818a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_2_HI 0x000003bd 819a26ae754SRob Clark 820a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_3_LO 0x000003be 821a26ae754SRob Clark 822a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_3_HI 0x000003bf 823a26ae754SRob Clark 824a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_4_LO 0x000003c0 825a26ae754SRob Clark 826a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_4_HI 0x000003c1 827a26ae754SRob Clark 828a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_5_LO 0x000003c2 829a26ae754SRob Clark 830a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_5_HI 0x000003c3 831a26ae754SRob Clark 832a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_6_LO 0x000003c4 833a26ae754SRob Clark 834a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_6_HI 0x000003c5 835a26ae754SRob Clark 836a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_7_LO 0x000003c6 837a26ae754SRob Clark 838a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_PC_7_HI 0x000003c7 839a26ae754SRob Clark 840a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_0_LO 0x000003c8 841a26ae754SRob Clark 842a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_0_HI 0x000003c9 843a26ae754SRob Clark 844a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_1_LO 0x000003ca 845a26ae754SRob Clark 846a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_1_HI 0x000003cb 847a26ae754SRob Clark 848a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_2_LO 0x000003cc 849a26ae754SRob Clark 850a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_2_HI 0x000003cd 851a26ae754SRob Clark 852a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_3_LO 0x000003ce 853a26ae754SRob Clark 854a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_3_HI 0x000003cf 855a26ae754SRob Clark 856a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_4_LO 0x000003d0 857a26ae754SRob Clark 858a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_4_HI 0x000003d1 859a26ae754SRob Clark 860a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_5_LO 0x000003d2 861a26ae754SRob Clark 862a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_5_HI 0x000003d3 863a26ae754SRob Clark 864a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_6_LO 0x000003d4 865a26ae754SRob Clark 866a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_6_HI 0x000003d5 867a26ae754SRob Clark 868a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_7_LO 0x000003d6 869a26ae754SRob Clark 870a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VFD_7_HI 0x000003d7 871a26ae754SRob Clark 872a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_LO 0x000003d8 873a26ae754SRob Clark 874a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_HI 0x000003d9 875a26ae754SRob Clark 876a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_LO 0x000003da 877a26ae754SRob Clark 878a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_HI 0x000003db 879a26ae754SRob Clark 880a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_LO 0x000003dc 881a26ae754SRob Clark 882a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_HI 0x000003dd 883a26ae754SRob Clark 884a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_LO 0x000003de 885a26ae754SRob Clark 886a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_HI 0x000003df 887a26ae754SRob Clark 888a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_LO 0x000003e0 889a26ae754SRob Clark 890a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_HI 0x000003e1 891a26ae754SRob Clark 892a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_LO 0x000003e2 893a26ae754SRob Clark 894a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_HI 0x000003e3 895a26ae754SRob Clark 896a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_LO 0x000003e4 897a26ae754SRob Clark 898a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_HI 0x000003e5 899a26ae754SRob Clark 900a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_LO 0x000003e6 901a26ae754SRob Clark 902a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_HI 0x000003e7 903a26ae754SRob Clark 904a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VPC_0_LO 0x000003e8 905a26ae754SRob Clark 906a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VPC_0_HI 0x000003e9 907a26ae754SRob Clark 908a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VPC_1_LO 0x000003ea 909a26ae754SRob Clark 910a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VPC_1_HI 0x000003eb 911a26ae754SRob Clark 912a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VPC_2_LO 0x000003ec 913a26ae754SRob Clark 914a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VPC_2_HI 0x000003ed 915a26ae754SRob Clark 916a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VPC_3_LO 0x000003ee 917a26ae754SRob Clark 918a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VPC_3_HI 0x000003ef 919a26ae754SRob Clark 920a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CCU_0_LO 0x000003f0 921a26ae754SRob Clark 922a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CCU_0_HI 0x000003f1 923a26ae754SRob Clark 924a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CCU_1_LO 0x000003f2 925a26ae754SRob Clark 926a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CCU_1_HI 0x000003f3 927a26ae754SRob Clark 928a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CCU_2_LO 0x000003f4 929a26ae754SRob Clark 930a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CCU_2_HI 0x000003f5 931a26ae754SRob Clark 932a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CCU_3_LO 0x000003f6 933a26ae754SRob Clark 934a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CCU_3_HI 0x000003f7 935a26ae754SRob Clark 936a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TSE_0_LO 0x000003f8 937a26ae754SRob Clark 938a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TSE_0_HI 0x000003f9 939a26ae754SRob Clark 940a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TSE_1_LO 0x000003fa 941a26ae754SRob Clark 942a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TSE_1_HI 0x000003fb 943a26ae754SRob Clark 944a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TSE_2_LO 0x000003fc 945a26ae754SRob Clark 946a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TSE_2_HI 0x000003fd 947a26ae754SRob Clark 948a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TSE_3_LO 0x000003fe 949a26ae754SRob Clark 950a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TSE_3_HI 0x000003ff 951a26ae754SRob Clark 952a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RAS_0_LO 0x00000400 953a26ae754SRob Clark 954a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RAS_0_HI 0x00000401 955a26ae754SRob Clark 956a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RAS_1_LO 0x00000402 957a26ae754SRob Clark 958a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RAS_1_HI 0x00000403 959a26ae754SRob Clark 960a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RAS_2_LO 0x00000404 961a26ae754SRob Clark 962a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RAS_2_HI 0x00000405 963a26ae754SRob Clark 964a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RAS_3_LO 0x00000406 965a26ae754SRob Clark 966a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RAS_3_HI 0x00000407 967a26ae754SRob Clark 968a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_0_LO 0x00000408 969a26ae754SRob Clark 970a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_0_HI 0x00000409 971a26ae754SRob Clark 972a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_1_LO 0x0000040a 973a26ae754SRob Clark 974a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_1_HI 0x0000040b 975a26ae754SRob Clark 976a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_2_LO 0x0000040c 977a26ae754SRob Clark 978a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_2_HI 0x0000040d 979a26ae754SRob Clark 980a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_3_LO 0x0000040e 981a26ae754SRob Clark 982a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_3_HI 0x0000040f 983a26ae754SRob Clark 984a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_4_LO 0x00000410 985a26ae754SRob Clark 986a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_4_HI 0x00000411 987a26ae754SRob Clark 988a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_5_LO 0x00000412 989a26ae754SRob Clark 990a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_5_HI 0x00000413 991a26ae754SRob Clark 992a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_6_LO 0x00000414 993a26ae754SRob Clark 994a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_6_HI 0x00000415 995a26ae754SRob Clark 996a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_7_LO 0x00000416 997a26ae754SRob Clark 998a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_UCHE_7_HI 0x00000417 999a26ae754SRob Clark 1000a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_0_LO 0x00000418 1001a26ae754SRob Clark 1002a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_0_HI 0x00000419 1003a26ae754SRob Clark 1004a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_1_LO 0x0000041a 1005a26ae754SRob Clark 1006a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_1_HI 0x0000041b 1007a26ae754SRob Clark 1008a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_2_LO 0x0000041c 1009a26ae754SRob Clark 1010a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_2_HI 0x0000041d 1011a26ae754SRob Clark 1012a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_3_LO 0x0000041e 1013a26ae754SRob Clark 1014a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_3_HI 0x0000041f 1015a26ae754SRob Clark 1016a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_4_LO 0x00000420 1017a26ae754SRob Clark 1018a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_4_HI 0x00000421 1019a26ae754SRob Clark 1020a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_5_LO 0x00000422 1021a26ae754SRob Clark 1022a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_5_HI 0x00000423 1023a26ae754SRob Clark 1024a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_6_LO 0x00000424 1025a26ae754SRob Clark 1026a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_6_HI 0x00000425 1027a26ae754SRob Clark 1028a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_7_LO 0x00000426 1029a26ae754SRob Clark 1030a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_TP_7_HI 0x00000427 1031a26ae754SRob Clark 1032a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_0_LO 0x00000428 1033a26ae754SRob Clark 1034a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_0_HI 0x00000429 1035a26ae754SRob Clark 1036a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_1_LO 0x0000042a 1037a26ae754SRob Clark 1038a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_1_HI 0x0000042b 1039a26ae754SRob Clark 1040a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_2_LO 0x0000042c 1041a26ae754SRob Clark 1042a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_2_HI 0x0000042d 1043a26ae754SRob Clark 1044a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_3_LO 0x0000042e 1045a26ae754SRob Clark 1046a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_3_HI 0x0000042f 1047a26ae754SRob Clark 1048a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_4_LO 0x00000430 1049a26ae754SRob Clark 1050a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_4_HI 0x00000431 1051a26ae754SRob Clark 1052a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_5_LO 0x00000432 1053a26ae754SRob Clark 1054a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_5_HI 0x00000433 1055a26ae754SRob Clark 1056a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_6_LO 0x00000434 1057a26ae754SRob Clark 1058a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_6_HI 0x00000435 1059a26ae754SRob Clark 1060a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_7_LO 0x00000436 1061a26ae754SRob Clark 1062a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_7_HI 0x00000437 1063a26ae754SRob Clark 1064a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_8_LO 0x00000438 1065a26ae754SRob Clark 1066a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_8_HI 0x00000439 1067a26ae754SRob Clark 1068a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_9_LO 0x0000043a 1069a26ae754SRob Clark 1070a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_9_HI 0x0000043b 1071a26ae754SRob Clark 1072a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_10_LO 0x0000043c 1073a26ae754SRob Clark 1074a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_10_HI 0x0000043d 1075a26ae754SRob Clark 1076a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_11_LO 0x0000043e 1077a26ae754SRob Clark 1078a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_SP_11_HI 0x0000043f 1079a26ae754SRob Clark 1080a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_0_LO 0x00000440 1081a26ae754SRob Clark 1082a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_0_HI 0x00000441 1083a26ae754SRob Clark 1084a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_1_LO 0x00000442 1085a26ae754SRob Clark 1086a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_1_HI 0x00000443 1087a26ae754SRob Clark 1088a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_2_LO 0x00000444 1089a26ae754SRob Clark 1090a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_2_HI 0x00000445 1091a26ae754SRob Clark 1092a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_3_LO 0x00000446 1093a26ae754SRob Clark 1094a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_3_HI 0x00000447 1095a26ae754SRob Clark 1096a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_4_LO 0x00000448 1097a26ae754SRob Clark 1098a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_4_HI 0x00000449 1099a26ae754SRob Clark 1100a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_5_LO 0x0000044a 1101a26ae754SRob Clark 1102a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_5_HI 0x0000044b 1103a26ae754SRob Clark 1104a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_6_LO 0x0000044c 1105a26ae754SRob Clark 1106a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_6_HI 0x0000044d 1107a26ae754SRob Clark 1108a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_7_LO 0x0000044e 1109a26ae754SRob Clark 1110a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RB_7_HI 0x0000044f 1111a26ae754SRob Clark 1112a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VSC_0_LO 0x00000450 1113a26ae754SRob Clark 1114a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VSC_0_HI 0x00000451 1115a26ae754SRob Clark 1116a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VSC_1_LO 0x00000452 1117a26ae754SRob Clark 1118a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_VSC_1_HI 0x00000453 1119a26ae754SRob Clark 1120a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_LRZ_0_LO 0x00000454 1121a26ae754SRob Clark 1122a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_LRZ_0_HI 0x00000455 1123a26ae754SRob Clark 1124a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_LRZ_1_LO 0x00000456 1125a26ae754SRob Clark 1126a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_LRZ_1_HI 0x00000457 1127a26ae754SRob Clark 1128a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_LRZ_2_LO 0x00000458 1129a26ae754SRob Clark 1130a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_LRZ_2_HI 0x00000459 1131a26ae754SRob Clark 1132a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_LRZ_3_LO 0x0000045a 1133a26ae754SRob Clark 1134a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_LRZ_3_HI 0x0000045b 1135a26ae754SRob Clark 1136a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CMP_0_LO 0x0000045c 1137a26ae754SRob Clark 1138a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CMP_0_HI 0x0000045d 1139a26ae754SRob Clark 1140a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CMP_1_LO 0x0000045e 1141a26ae754SRob Clark 1142a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CMP_1_HI 0x0000045f 1143a26ae754SRob Clark 1144a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CMP_2_LO 0x00000460 1145a26ae754SRob Clark 1146a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CMP_2_HI 0x00000461 1147a26ae754SRob Clark 1148a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CMP_3_LO 0x00000462 1149a26ae754SRob Clark 1150a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CMP_3_HI 0x00000463 1151a26ae754SRob Clark 1152a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b 1153a26ae754SRob Clark 1154a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c 1155a26ae754SRob Clark 1156a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d 1157a26ae754SRob Clark 1158a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e 1159a26ae754SRob Clark 1160a26ae754SRob Clark #define REG_A5XX_RBBM_ALWAYSON_COUNTER_LO 0x000004d2 1161a26ae754SRob Clark 1162a26ae754SRob Clark #define REG_A5XX_RBBM_ALWAYSON_COUNTER_HI 0x000004d3 1163a26ae754SRob Clark 1164a26ae754SRob Clark #define REG_A5XX_RBBM_STATUS 0x000004f5 1165a26ae754SRob Clark #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x80000000 1166a26ae754SRob Clark #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x40000000 1167a26ae754SRob Clark #define A5XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 1168a26ae754SRob Clark #define A5XX_RBBM_STATUS_VSC_BUSY 0x10000000 1169a26ae754SRob Clark #define A5XX_RBBM_STATUS_TPL1_BUSY 0x08000000 1170a26ae754SRob Clark #define A5XX_RBBM_STATUS_SP_BUSY 0x04000000 1171a26ae754SRob Clark #define A5XX_RBBM_STATUS_UCHE_BUSY 0x02000000 1172a26ae754SRob Clark #define A5XX_RBBM_STATUS_VPC_BUSY 0x01000000 1173a26ae754SRob Clark #define A5XX_RBBM_STATUS_VFDP_BUSY 0x00800000 1174a26ae754SRob Clark #define A5XX_RBBM_STATUS_VFD_BUSY 0x00400000 1175a26ae754SRob Clark #define A5XX_RBBM_STATUS_TESS_BUSY 0x00200000 1176a26ae754SRob Clark #define A5XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 1177a26ae754SRob Clark #define A5XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 1178a26ae754SRob Clark #define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY 0x00040000 1179a26ae754SRob Clark #define A5XX_RBBM_STATUS_DCOM_BUSY 0x00020000 1180a26ae754SRob Clark #define A5XX_RBBM_STATUS_COM_BUSY 0x00010000 1181a26ae754SRob Clark #define A5XX_RBBM_STATUS_LRZ_BUZY 0x00008000 1182a26ae754SRob Clark #define A5XX_RBBM_STATUS_A2D_DSP_BUSY 0x00004000 1183a26ae754SRob Clark #define A5XX_RBBM_STATUS_CCUFCHE_BUSY 0x00002000 1184a26ae754SRob Clark #define A5XX_RBBM_STATUS_RB_BUSY 0x00001000 1185a26ae754SRob Clark #define A5XX_RBBM_STATUS_RAS_BUSY 0x00000800 1186a26ae754SRob Clark #define A5XX_RBBM_STATUS_TSE_BUSY 0x00000400 1187a26ae754SRob Clark #define A5XX_RBBM_STATUS_VBIF_BUSY 0x00000200 1188a26ae754SRob Clark #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST 0x00000100 1189a26ae754SRob Clark #define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST 0x00000080 1190a26ae754SRob Clark #define A5XX_RBBM_STATUS_CP_BUSY 0x00000040 1191a26ae754SRob Clark #define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY 0x00000020 1192a26ae754SRob Clark #define A5XX_RBBM_STATUS_CP_CRASH_BUSY 0x00000010 1193a26ae754SRob Clark #define A5XX_RBBM_STATUS_CP_ETS_BUSY 0x00000008 1194a26ae754SRob Clark #define A5XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 1195a26ae754SRob Clark #define A5XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 1196a26ae754SRob Clark #define A5XX_RBBM_STATUS_HI_BUSY 0x00000001 1197a26ae754SRob Clark 1198a26ae754SRob Clark #define REG_A5XX_RBBM_STATUS3 0x00000530 1199a26ae754SRob Clark 1200a26ae754SRob Clark #define REG_A5XX_RBBM_INT_0_STATUS 0x000004e1 1201a26ae754SRob Clark 1202a26ae754SRob Clark #define REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS 0x000004f0 1203a26ae754SRob Clark 1204a26ae754SRob Clark #define REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS 0x000004f1 1205a26ae754SRob Clark 1206a26ae754SRob Clark #define REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS 0x000004f3 1207a26ae754SRob Clark 1208a26ae754SRob Clark #define REG_A5XX_RBBM_AHB_ERROR_STATUS 0x000004f4 1209a26ae754SRob Clark 1210a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_CNTL 0x00000464 1211a26ae754SRob Clark 1212a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD0 0x00000465 1213a26ae754SRob Clark 1214a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD1 0x00000466 1215a26ae754SRob Clark 1216a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD2 0x00000467 1217a26ae754SRob Clark 1218a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD3 0x00000468 1219a26ae754SRob Clark 1220a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000469 1221a26ae754SRob Clark 1222a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x0000046a 1223a26ae754SRob Clark 1224a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b 1225a26ae754SRob Clark 1226a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c 1227a26ae754SRob Clark 1228a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d 1229a26ae754SRob Clark 1230a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e 1231a26ae754SRob Clark 1232a26ae754SRob Clark #define REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000046f 1233a26ae754SRob Clark 1234a26ae754SRob Clark #define REG_A5XX_RBBM_AHB_ERROR 0x000004ed 1235a26ae754SRob Clark 1236a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_EVENT_LOGIC 0x00000504 1237a26ae754SRob Clark 1238a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_OVER 0x00000505 1239a26ae754SRob Clark 1240a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT0 0x00000506 1241a26ae754SRob Clark 1242a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT1 0x00000507 1243a26ae754SRob Clark 1244a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT2 0x00000508 1245a26ae754SRob Clark 1246a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT3 0x00000509 1247a26ae754SRob Clark 1248a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT4 0x0000050a 1249a26ae754SRob Clark 1250a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT5 0x0000050b 1251a26ae754SRob Clark 1252a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_ADDR 0x0000050c 1253a26ae754SRob Clark 1254a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF0 0x0000050d 1255a26ae754SRob Clark 1256a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF1 0x0000050e 1257a26ae754SRob Clark 1258a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF2 0x0000050f 1259a26ae754SRob Clark 1260a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF3 0x00000510 1261a26ae754SRob Clark 1262a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF4 0x00000511 1263a26ae754SRob Clark 1264a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_MISR0 0x00000512 1265a26ae754SRob Clark 1266a26ae754SRob Clark #define REG_A5XX_RBBM_CFG_DBGBUS_MISR1 0x00000513 1267a26ae754SRob Clark 1268a26ae754SRob Clark #define REG_A5XX_RBBM_ISDB_CNT 0x00000533 1269a26ae754SRob Clark 1270a26ae754SRob Clark #define REG_A5XX_RBBM_SECVID_TRUST_CONFIG 0x0000f000 1271a26ae754SRob Clark 1272a26ae754SRob Clark #define REG_A5XX_RBBM_SECVID_TRUST_CNTL 0x0000f400 1273a26ae754SRob Clark 1274a26ae754SRob Clark #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800 1275a26ae754SRob Clark 1276a26ae754SRob Clark #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801 1277a26ae754SRob Clark 1278a26ae754SRob Clark #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802 1279a26ae754SRob Clark 1280a26ae754SRob Clark #define REG_A5XX_RBBM_SECVID_TSB_CNTL 0x0000f803 1281a26ae754SRob Clark 1282a26ae754SRob Clark #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_LO 0x0000f804 1283a26ae754SRob Clark 1284a26ae754SRob Clark #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_HI 0x0000f805 1285a26ae754SRob Clark 1286a26ae754SRob Clark #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_LO 0x0000f806 1287a26ae754SRob Clark 1288a26ae754SRob Clark #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_HI 0x0000f807 1289a26ae754SRob Clark 1290a26ae754SRob Clark #define REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810 1291a26ae754SRob Clark 1292a26ae754SRob Clark #define REG_A5XX_VSC_PIPE_DATA_LENGTH_0 0x00000c00 1293a26ae754SRob Clark 1294a26ae754SRob Clark #define REG_A5XX_VSC_PERFCTR_VSC_SEL_0 0x00000c60 1295a26ae754SRob Clark 1296a26ae754SRob Clark #define REG_A5XX_VSC_PERFCTR_VSC_SEL_1 0x00000c61 1297a26ae754SRob Clark 1298a26ae754SRob Clark #define REG_A5XX_VSC_BIN_SIZE 0x00000cdd 1299a26ae754SRob Clark #define A5XX_VSC_BIN_SIZE_WINDOW_OFFSET_DISABLE 0x80000000 1300a26ae754SRob Clark #define A5XX_VSC_BIN_SIZE_X__MASK 0x00007fff 1301a26ae754SRob Clark #define A5XX_VSC_BIN_SIZE_X__SHIFT 0 1302a26ae754SRob Clark static inline uint32_t A5XX_VSC_BIN_SIZE_X(uint32_t val) 1303a26ae754SRob Clark { 1304a26ae754SRob Clark return ((val) << A5XX_VSC_BIN_SIZE_X__SHIFT) & A5XX_VSC_BIN_SIZE_X__MASK; 1305a26ae754SRob Clark } 1306a26ae754SRob Clark #define A5XX_VSC_BIN_SIZE_Y__MASK 0x7fff0000 1307a26ae754SRob Clark #define A5XX_VSC_BIN_SIZE_Y__SHIFT 16 1308a26ae754SRob Clark static inline uint32_t A5XX_VSC_BIN_SIZE_Y(uint32_t val) 1309a26ae754SRob Clark { 1310a26ae754SRob Clark return ((val) << A5XX_VSC_BIN_SIZE_Y__SHIFT) & A5XX_VSC_BIN_SIZE_Y__MASK; 1311a26ae754SRob Clark } 1312a26ae754SRob Clark 1313a26ae754SRob Clark #define REG_A5XX_GRAS_ADDR_MODE_CNTL 0x00000c81 1314a26ae754SRob Clark 1315a26ae754SRob Clark #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c90 1316a26ae754SRob Clark 1317a26ae754SRob Clark #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c91 1318a26ae754SRob Clark 1319a26ae754SRob Clark #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c92 1320a26ae754SRob Clark 1321a26ae754SRob Clark #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c93 1322a26ae754SRob Clark 1323a26ae754SRob Clark #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c94 1324a26ae754SRob Clark 1325a26ae754SRob Clark #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c95 1326a26ae754SRob Clark 1327a26ae754SRob Clark #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c96 1328a26ae754SRob Clark 1329a26ae754SRob Clark #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c97 1330a26ae754SRob Clark 1331a26ae754SRob Clark #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_0 0x00000c98 1332a26ae754SRob Clark 1333a26ae754SRob Clark #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_1 0x00000c99 1334a26ae754SRob Clark 1335a26ae754SRob Clark #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_2 0x00000c9a 1336a26ae754SRob Clark 1337a26ae754SRob Clark #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_3 0x00000c9b 1338a26ae754SRob Clark 1339a26ae754SRob Clark #define REG_A5XX_RB_DBG_ECO_CNTL 0x00000cc4 1340a26ae754SRob Clark 1341a26ae754SRob Clark #define REG_A5XX_RB_ADDR_MODE_CNTL 0x00000cc5 1342a26ae754SRob Clark 1343a26ae754SRob Clark #define REG_A5XX_RB_MODE_CNTL 0x00000cc6 1344a26ae754SRob Clark 1345a26ae754SRob Clark #define REG_A5XX_RB_CCU_CNTL 0x00000cc7 1346a26ae754SRob Clark 1347a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_RB_SEL_0 0x00000cd0 1348a26ae754SRob Clark 1349a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_RB_SEL_1 0x00000cd1 1350a26ae754SRob Clark 1351a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_RB_SEL_2 0x00000cd2 1352a26ae754SRob Clark 1353a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_RB_SEL_3 0x00000cd3 1354a26ae754SRob Clark 1355a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_RB_SEL_4 0x00000cd4 1356a26ae754SRob Clark 1357a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_RB_SEL_5 0x00000cd5 1358a26ae754SRob Clark 1359a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_RB_SEL_6 0x00000cd6 1360a26ae754SRob Clark 1361a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_RB_SEL_7 0x00000cd7 1362a26ae754SRob Clark 1363a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_CCU_SEL_0 0x00000cd8 1364a26ae754SRob Clark 1365a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_CCU_SEL_1 0x00000cd9 1366a26ae754SRob Clark 1367a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_CCU_SEL_2 0x00000cda 1368a26ae754SRob Clark 1369a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_CCU_SEL_3 0x00000cdb 1370a26ae754SRob Clark 1371a26ae754SRob Clark #define REG_A5XX_RB_POWERCTR_RB_SEL_0 0x00000ce0 1372a26ae754SRob Clark 1373a26ae754SRob Clark #define REG_A5XX_RB_POWERCTR_RB_SEL_1 0x00000ce1 1374a26ae754SRob Clark 1375a26ae754SRob Clark #define REG_A5XX_RB_POWERCTR_RB_SEL_2 0x00000ce2 1376a26ae754SRob Clark 1377a26ae754SRob Clark #define REG_A5XX_RB_POWERCTR_RB_SEL_3 0x00000ce3 1378a26ae754SRob Clark 1379a26ae754SRob Clark #define REG_A5XX_RB_POWERCTR_CCU_SEL_0 0x00000ce4 1380a26ae754SRob Clark 1381a26ae754SRob Clark #define REG_A5XX_RB_POWERCTR_CCU_SEL_1 0x00000ce5 1382a26ae754SRob Clark 1383a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_CMP_SEL_0 0x00000cec 1384a26ae754SRob Clark 1385a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_CMP_SEL_1 0x00000ced 1386a26ae754SRob Clark 1387a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_CMP_SEL_2 0x00000cee 1388a26ae754SRob Clark 1389a26ae754SRob Clark #define REG_A5XX_RB_PERFCTR_CMP_SEL_3 0x00000cef 1390a26ae754SRob Clark 1391a26ae754SRob Clark #define REG_A5XX_PC_DBG_ECO_CNTL 0x00000d00 1392a26ae754SRob Clark #define A5XX_PC_DBG_ECO_CNTL_TWOPASSUSEWFI 0x00000100 1393a26ae754SRob Clark 1394a26ae754SRob Clark #define REG_A5XX_PC_ADDR_MODE_CNTL 0x00000d01 1395a26ae754SRob Clark 1396a26ae754SRob Clark #define REG_A5XX_PC_MODE_CNTL 0x00000d02 1397a26ae754SRob Clark 1398a26ae754SRob Clark #define REG_A5XX_UNKNOWN_0D08 0x00000d08 1399a26ae754SRob Clark 1400a26ae754SRob Clark #define REG_A5XX_UNKNOWN_0D09 0x00000d09 1401a26ae754SRob Clark 1402a26ae754SRob Clark #define REG_A5XX_PC_PERFCTR_PC_SEL_0 0x00000d10 1403a26ae754SRob Clark 1404a26ae754SRob Clark #define REG_A5XX_PC_PERFCTR_PC_SEL_1 0x00000d11 1405a26ae754SRob Clark 1406a26ae754SRob Clark #define REG_A5XX_PC_PERFCTR_PC_SEL_2 0x00000d12 1407a26ae754SRob Clark 1408a26ae754SRob Clark #define REG_A5XX_PC_PERFCTR_PC_SEL_3 0x00000d13 1409a26ae754SRob Clark 1410a26ae754SRob Clark #define REG_A5XX_PC_PERFCTR_PC_SEL_4 0x00000d14 1411a26ae754SRob Clark 1412a26ae754SRob Clark #define REG_A5XX_PC_PERFCTR_PC_SEL_5 0x00000d15 1413a26ae754SRob Clark 1414a26ae754SRob Clark #define REG_A5XX_PC_PERFCTR_PC_SEL_6 0x00000d16 1415a26ae754SRob Clark 1416a26ae754SRob Clark #define REG_A5XX_PC_PERFCTR_PC_SEL_7 0x00000d17 1417a26ae754SRob Clark 1418a26ae754SRob Clark #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0 0x00000e00 1419a26ae754SRob Clark 1420a26ae754SRob Clark #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_1 0x00000e01 1421a26ae754SRob Clark 1422a26ae754SRob Clark #define REG_A5XX_HLSQ_ADDR_MODE_CNTL 0x00000e05 1423a26ae754SRob Clark 1424a26ae754SRob Clark #define REG_A5XX_HLSQ_MODE_CNTL 0x00000e06 1425a26ae754SRob Clark 1426a26ae754SRob Clark #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e10 1427a26ae754SRob Clark 1428a26ae754SRob Clark #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e11 1429a26ae754SRob Clark 1430a26ae754SRob Clark #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e12 1431a26ae754SRob Clark 1432a26ae754SRob Clark #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e13 1433a26ae754SRob Clark 1434a26ae754SRob Clark #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e14 1435a26ae754SRob Clark 1436a26ae754SRob Clark #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e15 1437a26ae754SRob Clark 1438a26ae754SRob Clark #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e16 1439a26ae754SRob Clark 1440a26ae754SRob Clark #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e17 1441a26ae754SRob Clark 1442a26ae754SRob Clark #define REG_A5XX_HLSQ_SPTP_RDSEL 0x00000f08 1443a26ae754SRob Clark 1444a26ae754SRob Clark #define REG_A5XX_HLSQ_DBG_READ_SEL 0x0000bc00 1445a26ae754SRob Clark 1446a26ae754SRob Clark #define REG_A5XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000a000 1447a26ae754SRob Clark 1448a26ae754SRob Clark #define REG_A5XX_VFD_ADDR_MODE_CNTL 0x00000e41 1449a26ae754SRob Clark 1450a26ae754SRob Clark #define REG_A5XX_VFD_MODE_CNTL 0x00000e42 1451a26ae754SRob Clark 1452a26ae754SRob Clark #define REG_A5XX_VFD_PERFCTR_VFD_SEL_0 0x00000e50 1453a26ae754SRob Clark 1454a26ae754SRob Clark #define REG_A5XX_VFD_PERFCTR_VFD_SEL_1 0x00000e51 1455a26ae754SRob Clark 1456a26ae754SRob Clark #define REG_A5XX_VFD_PERFCTR_VFD_SEL_2 0x00000e52 1457a26ae754SRob Clark 1458a26ae754SRob Clark #define REG_A5XX_VFD_PERFCTR_VFD_SEL_3 0x00000e53 1459a26ae754SRob Clark 1460a26ae754SRob Clark #define REG_A5XX_VFD_PERFCTR_VFD_SEL_4 0x00000e54 1461a26ae754SRob Clark 1462a26ae754SRob Clark #define REG_A5XX_VFD_PERFCTR_VFD_SEL_5 0x00000e55 1463a26ae754SRob Clark 1464a26ae754SRob Clark #define REG_A5XX_VFD_PERFCTR_VFD_SEL_6 0x00000e56 1465a26ae754SRob Clark 1466a26ae754SRob Clark #define REG_A5XX_VFD_PERFCTR_VFD_SEL_7 0x00000e57 1467a26ae754SRob Clark 1468a26ae754SRob Clark #define REG_A5XX_VPC_DBG_ECO_CNTL 0x00000e60 1469a26ae754SRob Clark 1470a26ae754SRob Clark #define REG_A5XX_VPC_ADDR_MODE_CNTL 0x00000e61 1471a26ae754SRob Clark 1472a26ae754SRob Clark #define REG_A5XX_VPC_MODE_CNTL 0x00000e62 1473a26ae754SRob Clark 1474a26ae754SRob Clark #define REG_A5XX_VPC_PERFCTR_VPC_SEL_0 0x00000e64 1475a26ae754SRob Clark 1476a26ae754SRob Clark #define REG_A5XX_VPC_PERFCTR_VPC_SEL_1 0x00000e65 1477a26ae754SRob Clark 1478a26ae754SRob Clark #define REG_A5XX_VPC_PERFCTR_VPC_SEL_2 0x00000e66 1479a26ae754SRob Clark 1480a26ae754SRob Clark #define REG_A5XX_VPC_PERFCTR_VPC_SEL_3 0x00000e67 1481a26ae754SRob Clark 1482a26ae754SRob Clark #define REG_A5XX_UCHE_ADDR_MODE_CNTL 0x00000e80 1483a26ae754SRob Clark 1484a26ae754SRob Clark #define REG_A5XX_UCHE_SVM_CNTL 0x00000e82 1485a26ae754SRob Clark 1486a26ae754SRob Clark #define REG_A5XX_UCHE_WRITE_THRU_BASE_LO 0x00000e87 1487a26ae754SRob Clark 1488a26ae754SRob Clark #define REG_A5XX_UCHE_WRITE_THRU_BASE_HI 0x00000e88 1489a26ae754SRob Clark 1490a26ae754SRob Clark #define REG_A5XX_UCHE_TRAP_BASE_LO 0x00000e89 1491a26ae754SRob Clark 1492a26ae754SRob Clark #define REG_A5XX_UCHE_TRAP_BASE_HI 0x00000e8a 1493a26ae754SRob Clark 1494a26ae754SRob Clark #define REG_A5XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e8b 1495a26ae754SRob Clark 1496a26ae754SRob Clark #define REG_A5XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e8c 1497a26ae754SRob Clark 1498a26ae754SRob Clark #define REG_A5XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e8d 1499a26ae754SRob Clark 1500a26ae754SRob Clark #define REG_A5XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e8e 1501a26ae754SRob Clark 1502a26ae754SRob Clark #define REG_A5XX_UCHE_DBG_ECO_CNTL_2 0x00000e8f 1503a26ae754SRob Clark 1504a26ae754SRob Clark #define REG_A5XX_UCHE_DBG_ECO_CNTL 0x00000e90 1505a26ae754SRob Clark 1506a26ae754SRob Clark #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO 0x00000e91 1507a26ae754SRob Clark 1508a26ae754SRob Clark #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_HI 0x00000e92 1509a26ae754SRob Clark 1510a26ae754SRob Clark #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_LO 0x00000e93 1511a26ae754SRob Clark 1512a26ae754SRob Clark #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_HI 0x00000e94 1513a26ae754SRob Clark 1514a26ae754SRob Clark #define REG_A5XX_UCHE_CACHE_INVALIDATE 0x00000e95 1515a26ae754SRob Clark 1516a26ae754SRob Clark #define REG_A5XX_UCHE_CACHE_WAYS 0x00000e96 1517a26ae754SRob Clark 1518a26ae754SRob Clark #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000ea0 1519a26ae754SRob Clark 1520a26ae754SRob Clark #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000ea1 1521a26ae754SRob Clark 1522a26ae754SRob Clark #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000ea2 1523a26ae754SRob Clark 1524a26ae754SRob Clark #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000ea3 1525a26ae754SRob Clark 1526a26ae754SRob Clark #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000ea4 1527a26ae754SRob Clark 1528a26ae754SRob Clark #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000ea5 1529a26ae754SRob Clark 1530a26ae754SRob Clark #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000ea6 1531a26ae754SRob Clark 1532a26ae754SRob Clark #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000ea7 1533a26ae754SRob Clark 1534a26ae754SRob Clark #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_0 0x00000ea8 1535a26ae754SRob Clark 1536a26ae754SRob Clark #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_1 0x00000ea9 1537a26ae754SRob Clark 1538a26ae754SRob Clark #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_2 0x00000eaa 1539a26ae754SRob Clark 1540a26ae754SRob Clark #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_3 0x00000eab 1541a26ae754SRob Clark 1542a26ae754SRob Clark #define REG_A5XX_UCHE_TRAP_LOG_LO 0x00000eb1 1543a26ae754SRob Clark 1544a26ae754SRob Clark #define REG_A5XX_UCHE_TRAP_LOG_HI 0x00000eb2 1545a26ae754SRob Clark 1546a26ae754SRob Clark #define REG_A5XX_SP_DBG_ECO_CNTL 0x00000ec0 1547a26ae754SRob Clark 1548a26ae754SRob Clark #define REG_A5XX_SP_ADDR_MODE_CNTL 0x00000ec1 1549a26ae754SRob Clark 1550a26ae754SRob Clark #define REG_A5XX_SP_MODE_CNTL 0x00000ec2 1551a26ae754SRob Clark 1552a26ae754SRob Clark #define REG_A5XX_SP_PERFCTR_SP_SEL_0 0x00000ed0 1553a26ae754SRob Clark 1554a26ae754SRob Clark #define REG_A5XX_SP_PERFCTR_SP_SEL_1 0x00000ed1 1555a26ae754SRob Clark 1556a26ae754SRob Clark #define REG_A5XX_SP_PERFCTR_SP_SEL_2 0x00000ed2 1557a26ae754SRob Clark 1558a26ae754SRob Clark #define REG_A5XX_SP_PERFCTR_SP_SEL_3 0x00000ed3 1559a26ae754SRob Clark 1560a26ae754SRob Clark #define REG_A5XX_SP_PERFCTR_SP_SEL_4 0x00000ed4 1561a26ae754SRob Clark 1562a26ae754SRob Clark #define REG_A5XX_SP_PERFCTR_SP_SEL_5 0x00000ed5 1563a26ae754SRob Clark 1564a26ae754SRob Clark #define REG_A5XX_SP_PERFCTR_SP_SEL_6 0x00000ed6 1565a26ae754SRob Clark 1566a26ae754SRob Clark #define REG_A5XX_SP_PERFCTR_SP_SEL_7 0x00000ed7 1567a26ae754SRob Clark 1568a26ae754SRob Clark #define REG_A5XX_SP_PERFCTR_SP_SEL_8 0x00000ed8 1569a26ae754SRob Clark 1570a26ae754SRob Clark #define REG_A5XX_SP_PERFCTR_SP_SEL_9 0x00000ed9 1571a26ae754SRob Clark 1572a26ae754SRob Clark #define REG_A5XX_SP_PERFCTR_SP_SEL_10 0x00000eda 1573a26ae754SRob Clark 1574a26ae754SRob Clark #define REG_A5XX_SP_PERFCTR_SP_SEL_11 0x00000edb 1575a26ae754SRob Clark 1576a26ae754SRob Clark #define REG_A5XX_SP_POWERCTR_SP_SEL_0 0x00000edc 1577a26ae754SRob Clark 1578a26ae754SRob Clark #define REG_A5XX_SP_POWERCTR_SP_SEL_1 0x00000edd 1579a26ae754SRob Clark 1580a26ae754SRob Clark #define REG_A5XX_SP_POWERCTR_SP_SEL_2 0x00000ede 1581a26ae754SRob Clark 1582a26ae754SRob Clark #define REG_A5XX_SP_POWERCTR_SP_SEL_3 0x00000edf 1583a26ae754SRob Clark 1584a26ae754SRob Clark #define REG_A5XX_TPL1_ADDR_MODE_CNTL 0x00000f01 1585a26ae754SRob Clark 1586a26ae754SRob Clark #define REG_A5XX_TPL1_MODE_CNTL 0x00000f02 1587a26ae754SRob Clark 1588a26ae754SRob Clark #define REG_A5XX_TPL1_PERFCTR_TP_SEL_0 0x00000f10 1589a26ae754SRob Clark 1590a26ae754SRob Clark #define REG_A5XX_TPL1_PERFCTR_TP_SEL_1 0x00000f11 1591a26ae754SRob Clark 1592a26ae754SRob Clark #define REG_A5XX_TPL1_PERFCTR_TP_SEL_2 0x00000f12 1593a26ae754SRob Clark 1594a26ae754SRob Clark #define REG_A5XX_TPL1_PERFCTR_TP_SEL_3 0x00000f13 1595a26ae754SRob Clark 1596a26ae754SRob Clark #define REG_A5XX_TPL1_PERFCTR_TP_SEL_4 0x00000f14 1597a26ae754SRob Clark 1598a26ae754SRob Clark #define REG_A5XX_TPL1_PERFCTR_TP_SEL_5 0x00000f15 1599a26ae754SRob Clark 1600a26ae754SRob Clark #define REG_A5XX_TPL1_PERFCTR_TP_SEL_6 0x00000f16 1601a26ae754SRob Clark 1602a26ae754SRob Clark #define REG_A5XX_TPL1_PERFCTR_TP_SEL_7 0x00000f17 1603a26ae754SRob Clark 1604a26ae754SRob Clark #define REG_A5XX_TPL1_POWERCTR_TP_SEL_0 0x00000f18 1605a26ae754SRob Clark 1606a26ae754SRob Clark #define REG_A5XX_TPL1_POWERCTR_TP_SEL_1 0x00000f19 1607a26ae754SRob Clark 1608a26ae754SRob Clark #define REG_A5XX_TPL1_POWERCTR_TP_SEL_2 0x00000f1a 1609a26ae754SRob Clark 1610a26ae754SRob Clark #define REG_A5XX_TPL1_POWERCTR_TP_SEL_3 0x00000f1b 1611a26ae754SRob Clark 1612a26ae754SRob Clark #define REG_A5XX_VBIF_VERSION 0x00003000 1613a26ae754SRob Clark 1614a26ae754SRob Clark #define REG_A5XX_VBIF_CLKON 0x00003001 1615a26ae754SRob Clark 1616a26ae754SRob Clark #define REG_A5XX_VBIF_ABIT_SORT 0x00003028 1617a26ae754SRob Clark 1618a26ae754SRob Clark #define REG_A5XX_VBIF_ABIT_SORT_CONF 0x00003029 1619a26ae754SRob Clark 1620a26ae754SRob Clark #define REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049 1621a26ae754SRob Clark 1622a26ae754SRob Clark #define REG_A5XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 1623a26ae754SRob Clark 1624a26ae754SRob Clark #define REG_A5XX_VBIF_IN_RD_LIM_CONF0 0x0000302c 1625a26ae754SRob Clark 1626a26ae754SRob Clark #define REG_A5XX_VBIF_IN_RD_LIM_CONF1 0x0000302d 1627a26ae754SRob Clark 1628a26ae754SRob Clark #define REG_A5XX_VBIF_XIN_HALT_CTRL0 0x00003080 1629a26ae754SRob Clark 1630a26ae754SRob Clark #define REG_A5XX_VBIF_XIN_HALT_CTRL1 0x00003081 1631a26ae754SRob Clark 1632a26ae754SRob Clark #define REG_A5XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084 1633a26ae754SRob Clark 1634a26ae754SRob Clark #define REG_A5XX_VBIF_TEST_BUS1_CTRL0 0x00003085 1635a26ae754SRob Clark 1636a26ae754SRob Clark #define REG_A5XX_VBIF_TEST_BUS1_CTRL1 0x00003086 1637a26ae754SRob Clark 1638a26ae754SRob Clark #define REG_A5XX_VBIF_TEST_BUS2_CTRL0 0x00003087 1639a26ae754SRob Clark 1640a26ae754SRob Clark #define REG_A5XX_VBIF_TEST_BUS2_CTRL1 0x00003088 1641a26ae754SRob Clark 1642a26ae754SRob Clark #define REG_A5XX_VBIF_TEST_BUS_OUT 0x0000308c 1643a26ae754SRob Clark 1644a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_CNT_SEL0 0x000030d0 1645a26ae754SRob Clark 1646a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_CNT_SEL1 0x000030d1 1647a26ae754SRob Clark 1648a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_CNT_SEL2 0x000030d2 1649a26ae754SRob Clark 1650a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_CNT_SEL3 0x000030d3 1651a26ae754SRob Clark 1652a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_CNT_LOW0 0x000030d8 1653a26ae754SRob Clark 1654a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_CNT_LOW1 0x000030d9 1655a26ae754SRob Clark 1656a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_CNT_LOW2 0x000030da 1657a26ae754SRob Clark 1658a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_CNT_LOW3 0x000030db 1659a26ae754SRob Clark 1660a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_CNT_HIGH0 0x000030e0 1661a26ae754SRob Clark 1662a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_CNT_HIGH1 0x000030e1 1663a26ae754SRob Clark 1664a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_CNT_HIGH2 0x000030e2 1665a26ae754SRob Clark 1666a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_CNT_HIGH3 0x000030e3 1667a26ae754SRob Clark 1668a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_PWR_CNT_EN0 0x00003100 1669a26ae754SRob Clark 1670a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_PWR_CNT_EN1 0x00003101 1671a26ae754SRob Clark 1672a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_PWR_CNT_EN2 0x00003102 1673a26ae754SRob Clark 1674a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110 1675a26ae754SRob Clark 1676a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111 1677a26ae754SRob Clark 1678a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112 1679a26ae754SRob Clark 1680a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118 1681a26ae754SRob Clark 1682a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119 1683a26ae754SRob Clark 1684a26ae754SRob Clark #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a 1685a26ae754SRob Clark 1686a26ae754SRob Clark #define REG_A5XX_GPMU_INST_RAM_BASE 0x00008800 1687a26ae754SRob Clark 1688a26ae754SRob Clark #define REG_A5XX_GPMU_DATA_RAM_BASE 0x00009800 1689a26ae754SRob Clark 1690a26ae754SRob Clark #define REG_A5XX_GPMU_SP_POWER_CNTL 0x0000a881 1691a26ae754SRob Clark 1692a26ae754SRob Clark #define REG_A5XX_GPMU_RBCCU_CLOCK_CNTL 0x0000a886 1693a26ae754SRob Clark 1694a26ae754SRob Clark #define REG_A5XX_GPMU_RBCCU_POWER_CNTL 0x0000a887 1695a26ae754SRob Clark 1696a26ae754SRob Clark #define REG_A5XX_GPMU_SP_PWR_CLK_STATUS 0x0000a88b 1697a26ae754SRob Clark #define A5XX_GPMU_SP_PWR_CLK_STATUS_PWR_ON 0x00100000 1698a26ae754SRob Clark 1699a26ae754SRob Clark #define REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS 0x0000a88d 1700a26ae754SRob Clark #define A5XX_GPMU_RBCCU_PWR_CLK_STATUS_PWR_ON 0x00100000 1701a26ae754SRob Clark 1702a26ae754SRob Clark #define REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY 0x0000a891 1703a26ae754SRob Clark 1704a26ae754SRob Clark #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL 0x0000a892 1705a26ae754SRob Clark 1706a26ae754SRob Clark #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST 0x0000a893 1707a26ae754SRob Clark 1708a26ae754SRob Clark #define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL 0x0000a894 1709a26ae754SRob Clark 1710a26ae754SRob Clark #define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3 1711a26ae754SRob Clark 1712a26ae754SRob Clark #define REG_A5XX_GPMU_WFI_CONFIG 0x0000a8c1 1713a26ae754SRob Clark 1714a26ae754SRob Clark #define REG_A5XX_GPMU_RBBM_INTR_INFO 0x0000a8d6 1715a26ae754SRob Clark 1716a26ae754SRob Clark #define REG_A5XX_GPMU_CM3_SYSRESET 0x0000a8d8 1717a26ae754SRob Clark 1718a26ae754SRob Clark #define REG_A5XX_GPMU_GENERAL_0 0x0000a8e0 1719a26ae754SRob Clark 1720a26ae754SRob Clark #define REG_A5XX_GPMU_GENERAL_1 0x0000a8e1 1721a26ae754SRob Clark 1722a26ae754SRob Clark #define REG_A5XX_SP_POWER_COUNTER_0_LO 0x0000a840 1723a26ae754SRob Clark 1724a26ae754SRob Clark #define REG_A5XX_SP_POWER_COUNTER_0_HI 0x0000a841 1725a26ae754SRob Clark 1726a26ae754SRob Clark #define REG_A5XX_SP_POWER_COUNTER_1_LO 0x0000a842 1727a26ae754SRob Clark 1728a26ae754SRob Clark #define REG_A5XX_SP_POWER_COUNTER_1_HI 0x0000a843 1729a26ae754SRob Clark 1730a26ae754SRob Clark #define REG_A5XX_SP_POWER_COUNTER_2_LO 0x0000a844 1731a26ae754SRob Clark 1732a26ae754SRob Clark #define REG_A5XX_SP_POWER_COUNTER_2_HI 0x0000a845 1733a26ae754SRob Clark 1734a26ae754SRob Clark #define REG_A5XX_SP_POWER_COUNTER_3_LO 0x0000a846 1735a26ae754SRob Clark 1736a26ae754SRob Clark #define REG_A5XX_SP_POWER_COUNTER_3_HI 0x0000a847 1737a26ae754SRob Clark 1738a26ae754SRob Clark #define REG_A5XX_TP_POWER_COUNTER_0_LO 0x0000a848 1739a26ae754SRob Clark 1740a26ae754SRob Clark #define REG_A5XX_TP_POWER_COUNTER_0_HI 0x0000a849 1741a26ae754SRob Clark 1742a26ae754SRob Clark #define REG_A5XX_TP_POWER_COUNTER_1_LO 0x0000a84a 1743a26ae754SRob Clark 1744a26ae754SRob Clark #define REG_A5XX_TP_POWER_COUNTER_1_HI 0x0000a84b 1745a26ae754SRob Clark 1746a26ae754SRob Clark #define REG_A5XX_TP_POWER_COUNTER_2_LO 0x0000a84c 1747a26ae754SRob Clark 1748a26ae754SRob Clark #define REG_A5XX_TP_POWER_COUNTER_2_HI 0x0000a84d 1749a26ae754SRob Clark 1750a26ae754SRob Clark #define REG_A5XX_TP_POWER_COUNTER_3_LO 0x0000a84e 1751a26ae754SRob Clark 1752a26ae754SRob Clark #define REG_A5XX_TP_POWER_COUNTER_3_HI 0x0000a84f 1753a26ae754SRob Clark 1754a26ae754SRob Clark #define REG_A5XX_RB_POWER_COUNTER_0_LO 0x0000a850 1755a26ae754SRob Clark 1756a26ae754SRob Clark #define REG_A5XX_RB_POWER_COUNTER_0_HI 0x0000a851 1757a26ae754SRob Clark 1758a26ae754SRob Clark #define REG_A5XX_RB_POWER_COUNTER_1_LO 0x0000a852 1759a26ae754SRob Clark 1760a26ae754SRob Clark #define REG_A5XX_RB_POWER_COUNTER_1_HI 0x0000a853 1761a26ae754SRob Clark 1762a26ae754SRob Clark #define REG_A5XX_RB_POWER_COUNTER_2_LO 0x0000a854 1763a26ae754SRob Clark 1764a26ae754SRob Clark #define REG_A5XX_RB_POWER_COUNTER_2_HI 0x0000a855 1765a26ae754SRob Clark 1766a26ae754SRob Clark #define REG_A5XX_RB_POWER_COUNTER_3_LO 0x0000a856 1767a26ae754SRob Clark 1768a26ae754SRob Clark #define REG_A5XX_RB_POWER_COUNTER_3_HI 0x0000a857 1769a26ae754SRob Clark 1770a26ae754SRob Clark #define REG_A5XX_CCU_POWER_COUNTER_0_LO 0x0000a858 1771a26ae754SRob Clark 1772a26ae754SRob Clark #define REG_A5XX_CCU_POWER_COUNTER_0_HI 0x0000a859 1773a26ae754SRob Clark 1774a26ae754SRob Clark #define REG_A5XX_CCU_POWER_COUNTER_1_LO 0x0000a85a 1775a26ae754SRob Clark 1776a26ae754SRob Clark #define REG_A5XX_CCU_POWER_COUNTER_1_HI 0x0000a85b 1777a26ae754SRob Clark 1778a26ae754SRob Clark #define REG_A5XX_UCHE_POWER_COUNTER_0_LO 0x0000a85c 1779a26ae754SRob Clark 1780a26ae754SRob Clark #define REG_A5XX_UCHE_POWER_COUNTER_0_HI 0x0000a85d 1781a26ae754SRob Clark 1782a26ae754SRob Clark #define REG_A5XX_UCHE_POWER_COUNTER_1_LO 0x0000a85e 1783a26ae754SRob Clark 1784a26ae754SRob Clark #define REG_A5XX_UCHE_POWER_COUNTER_1_HI 0x0000a85f 1785a26ae754SRob Clark 1786a26ae754SRob Clark #define REG_A5XX_UCHE_POWER_COUNTER_2_LO 0x0000a860 1787a26ae754SRob Clark 1788a26ae754SRob Clark #define REG_A5XX_UCHE_POWER_COUNTER_2_HI 0x0000a861 1789a26ae754SRob Clark 1790a26ae754SRob Clark #define REG_A5XX_UCHE_POWER_COUNTER_3_LO 0x0000a862 1791a26ae754SRob Clark 1792a26ae754SRob Clark #define REG_A5XX_UCHE_POWER_COUNTER_3_HI 0x0000a863 1793a26ae754SRob Clark 1794a26ae754SRob Clark #define REG_A5XX_CP_POWER_COUNTER_0_LO 0x0000a864 1795a26ae754SRob Clark 1796a26ae754SRob Clark #define REG_A5XX_CP_POWER_COUNTER_0_HI 0x0000a865 1797a26ae754SRob Clark 1798a26ae754SRob Clark #define REG_A5XX_CP_POWER_COUNTER_1_LO 0x0000a866 1799a26ae754SRob Clark 1800a26ae754SRob Clark #define REG_A5XX_CP_POWER_COUNTER_1_HI 0x0000a867 1801a26ae754SRob Clark 1802a26ae754SRob Clark #define REG_A5XX_CP_POWER_COUNTER_2_LO 0x0000a868 1803a26ae754SRob Clark 1804a26ae754SRob Clark #define REG_A5XX_CP_POWER_COUNTER_2_HI 0x0000a869 1805a26ae754SRob Clark 1806a26ae754SRob Clark #define REG_A5XX_CP_POWER_COUNTER_3_LO 0x0000a86a 1807a26ae754SRob Clark 1808a26ae754SRob Clark #define REG_A5XX_CP_POWER_COUNTER_3_HI 0x0000a86b 1809a26ae754SRob Clark 1810a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_0_LO 0x0000a86c 1811a26ae754SRob Clark 1812a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_0_HI 0x0000a86d 1813a26ae754SRob Clark 1814a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_1_LO 0x0000a86e 1815a26ae754SRob Clark 1816a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_1_HI 0x0000a86f 1817a26ae754SRob Clark 1818a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_2_LO 0x0000a870 1819a26ae754SRob Clark 1820a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_2_HI 0x0000a871 1821a26ae754SRob Clark 1822a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_3_LO 0x0000a872 1823a26ae754SRob Clark 1824a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_3_HI 0x0000a873 1825a26ae754SRob Clark 1826a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_4_LO 0x0000a874 1827a26ae754SRob Clark 1828a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_4_HI 0x0000a875 1829a26ae754SRob Clark 1830a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_5_LO 0x0000a876 1831a26ae754SRob Clark 1832a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_5_HI 0x0000a877 1833a26ae754SRob Clark 1834a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_ENABLE 0x0000a878 1835a26ae754SRob Clark 1836a26ae754SRob Clark #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_LO 0x0000a879 1837a26ae754SRob Clark 1838a26ae754SRob Clark #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_HI 0x0000a87a 1839a26ae754SRob Clark 1840a26ae754SRob Clark #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_RESET 0x0000a87b 1841a26ae754SRob Clark 1842a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_0 0x0000a87c 1843a26ae754SRob Clark 1844a26ae754SRob Clark #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_1 0x0000a87d 1845a26ae754SRob Clark 1846a26ae754SRob Clark #define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3 1847a26ae754SRob Clark 1848a26ae754SRob Clark #define REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL 0x0000a8a8 1849a26ae754SRob Clark 1850a26ae754SRob Clark #define REG_A5XX_GPMU_TEMP_SENSOR_ID 0x0000ac00 1851a26ae754SRob Clark 1852a26ae754SRob Clark #define REG_A5XX_GPMU_TEMP_SENSOR_CONFIG 0x0000ac01 1853a26ae754SRob Clark 1854a26ae754SRob Clark #define REG_A5XX_GPMU_TEMP_VAL 0x0000ac02 1855a26ae754SRob Clark 1856a26ae754SRob Clark #define REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD 0x0000ac03 1857a26ae754SRob Clark 1858a26ae754SRob Clark #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_STATUS 0x0000ac05 1859a26ae754SRob Clark 1860a26ae754SRob Clark #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK 0x0000ac06 1861a26ae754SRob Clark 1862a26ae754SRob Clark #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_0_1 0x0000ac40 1863a26ae754SRob Clark 1864a26ae754SRob Clark #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_2_3 0x0000ac41 1865a26ae754SRob Clark 1866a26ae754SRob Clark #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_0_1 0x0000ac42 1867a26ae754SRob Clark 1868a26ae754SRob Clark #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_2_3 0x0000ac43 1869a26ae754SRob Clark 1870a26ae754SRob Clark #define REG_A5XX_GPMU_BASE_LEAKAGE 0x0000ac46 1871a26ae754SRob Clark 1872a26ae754SRob Clark #define REG_A5XX_GPMU_GPMU_VOLTAGE 0x0000ac60 1873a26ae754SRob Clark 1874a26ae754SRob Clark #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_STATUS 0x0000ac61 1875a26ae754SRob Clark 1876a26ae754SRob Clark #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK 0x0000ac62 1877a26ae754SRob Clark 1878a26ae754SRob Clark #define REG_A5XX_GPMU_GPMU_PWR_THRESHOLD 0x0000ac80 1879a26ae754SRob Clark 1880a26ae754SRob Clark #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL 0x0000acc4 1881a26ae754SRob Clark 1882a26ae754SRob Clark #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_STATUS 0x0000acc5 1883a26ae754SRob Clark 1884a26ae754SRob Clark #define REG_A5XX_GDPM_CONFIG1 0x0000b80c 1885a26ae754SRob Clark 1886a26ae754SRob Clark #define REG_A5XX_GDPM_CONFIG2 0x0000b80d 1887a26ae754SRob Clark 1888a26ae754SRob Clark #define REG_A5XX_GDPM_INT_EN 0x0000b80f 1889a26ae754SRob Clark 1890a26ae754SRob Clark #define REG_A5XX_GDPM_INT_MASK 0x0000b811 1891a26ae754SRob Clark 1892a26ae754SRob Clark #define REG_A5XX_GPMU_BEC_ENABLE 0x0000b9a0 1893a26ae754SRob Clark 1894a26ae754SRob Clark #define REG_A5XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000c41a 1895a26ae754SRob Clark 1896a26ae754SRob Clark #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 0x0000c41d 1897a26ae754SRob Clark 1898a26ae754SRob Clark #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 0x0000c41f 1899a26ae754SRob Clark 1900a26ae754SRob Clark #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 0x0000c421 1901a26ae754SRob Clark 1902a26ae754SRob Clark #define REG_A5XX_GPU_CS_ENABLE_REG 0x0000c520 1903a26ae754SRob Clark 1904a26ae754SRob Clark #define REG_A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x0000c557 1905a26ae754SRob Clark 1906a26ae754SRob Clark #define REG_A5XX_GRAS_CL_CNTL 0x0000e000 1907a26ae754SRob Clark 1908a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E001 0x0000e001 1909a26ae754SRob Clark 1910a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E004 0x0000e004 1911a26ae754SRob Clark 1912a26ae754SRob Clark #define REG_A5XX_GRAS_CNTL 0x0000e005 1913a26ae754SRob Clark #define A5XX_GRAS_CNTL_VARYING 0x00000001 1914a26ae754SRob Clark 1915a26ae754SRob Clark #define REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x0000e006 1916a26ae754SRob Clark #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff 1917a26ae754SRob Clark #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0 1918a26ae754SRob Clark static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val) 1919a26ae754SRob Clark { 1920a26ae754SRob Clark return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK; 1921a26ae754SRob Clark } 1922a26ae754SRob Clark #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x000ffc00 1923a26ae754SRob Clark #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10 1924a26ae754SRob Clark static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) 1925a26ae754SRob Clark { 1926a26ae754SRob Clark return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK; 1927a26ae754SRob Clark } 1928a26ae754SRob Clark 1929a26ae754SRob Clark #define REG_A5XX_GRAS_CL_VPORT_XOFFSET_0 0x0000e010 1930a26ae754SRob Clark #define A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff 1931a26ae754SRob Clark #define A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0 1932a26ae754SRob Clark static inline uint32_t A5XX_GRAS_CL_VPORT_XOFFSET_0(float val) 1933a26ae754SRob Clark { 1934a26ae754SRob Clark return ((fui(val)) << A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK; 1935a26ae754SRob Clark } 1936a26ae754SRob Clark 1937a26ae754SRob Clark #define REG_A5XX_GRAS_CL_VPORT_XSCALE_0 0x0000e011 1938a26ae754SRob Clark #define A5XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff 1939a26ae754SRob Clark #define A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0 1940a26ae754SRob Clark static inline uint32_t A5XX_GRAS_CL_VPORT_XSCALE_0(float val) 1941a26ae754SRob Clark { 1942a26ae754SRob Clark return ((fui(val)) << A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_XSCALE_0__MASK; 1943a26ae754SRob Clark } 1944a26ae754SRob Clark 1945a26ae754SRob Clark #define REG_A5XX_GRAS_CL_VPORT_YOFFSET_0 0x0000e012 1946a26ae754SRob Clark #define A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff 1947a26ae754SRob Clark #define A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0 1948a26ae754SRob Clark static inline uint32_t A5XX_GRAS_CL_VPORT_YOFFSET_0(float val) 1949a26ae754SRob Clark { 1950a26ae754SRob Clark return ((fui(val)) << A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK; 1951a26ae754SRob Clark } 1952a26ae754SRob Clark 1953a26ae754SRob Clark #define REG_A5XX_GRAS_CL_VPORT_YSCALE_0 0x0000e013 1954a26ae754SRob Clark #define A5XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff 1955a26ae754SRob Clark #define A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0 1956a26ae754SRob Clark static inline uint32_t A5XX_GRAS_CL_VPORT_YSCALE_0(float val) 1957a26ae754SRob Clark { 1958a26ae754SRob Clark return ((fui(val)) << A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_YSCALE_0__MASK; 1959a26ae754SRob Clark } 1960a26ae754SRob Clark 1961a26ae754SRob Clark #define REG_A5XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000e014 1962a26ae754SRob Clark #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff 1963a26ae754SRob Clark #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0 1964a26ae754SRob Clark static inline uint32_t A5XX_GRAS_CL_VPORT_ZOFFSET_0(float val) 1965a26ae754SRob Clark { 1966a26ae754SRob Clark return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK; 1967a26ae754SRob Clark } 1968a26ae754SRob Clark 1969a26ae754SRob Clark #define REG_A5XX_GRAS_CL_VPORT_ZSCALE_0 0x0000e015 1970a26ae754SRob Clark #define A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff 1971a26ae754SRob Clark #define A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0 1972a26ae754SRob Clark static inline uint32_t A5XX_GRAS_CL_VPORT_ZSCALE_0(float val) 1973a26ae754SRob Clark { 1974a26ae754SRob Clark return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK; 1975a26ae754SRob Clark } 1976a26ae754SRob Clark 1977a26ae754SRob Clark #define REG_A5XX_GRAS_SU_CNTL 0x0000e090 1978a26ae754SRob Clark #define A5XX_GRAS_SU_CNTL_FRONT_CW 0x00000004 1979a26ae754SRob Clark #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8 1980a26ae754SRob Clark #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3 1981a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) 1982a26ae754SRob Clark { 1983a26ae754SRob Clark return ((((int32_t)(val * 4.0))) << A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK; 1984a26ae754SRob Clark } 1985a26ae754SRob Clark #define A5XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800 1986a26ae754SRob Clark #define A5XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000 1987a26ae754SRob Clark 1988a26ae754SRob Clark #define REG_A5XX_GRAS_SU_POINT_MINMAX 0x0000e091 1989a26ae754SRob Clark #define A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 1990a26ae754SRob Clark #define A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 1991a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MIN(float val) 1992a26ae754SRob Clark { 1993a26ae754SRob Clark return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 1994a26ae754SRob Clark } 1995a26ae754SRob Clark #define A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 1996a26ae754SRob Clark #define A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 1997a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MAX(float val) 1998a26ae754SRob Clark { 1999a26ae754SRob Clark return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 2000a26ae754SRob Clark } 2001a26ae754SRob Clark 2002a26ae754SRob Clark #define REG_A5XX_GRAS_SU_POINT_SIZE 0x0000e092 2003a26ae754SRob Clark #define A5XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff 2004a26ae754SRob Clark #define A5XX_GRAS_SU_POINT_SIZE__SHIFT 0 2005a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SU_POINT_SIZE(float val) 2006a26ae754SRob Clark { 2007a26ae754SRob Clark return ((((int32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_SIZE__SHIFT) & A5XX_GRAS_SU_POINT_SIZE__MASK; 2008a26ae754SRob Clark } 2009a26ae754SRob Clark 2010a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E093 0x0000e093 2011a26ae754SRob Clark 2012a26ae754SRob Clark #define REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL 0x0000e094 2013a26ae754SRob Clark #define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_ALPHA_TEST_ENABLE 0x00000001 2014a26ae754SRob Clark 2015a26ae754SRob Clark #define REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000e095 2016a26ae754SRob Clark #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff 2017a26ae754SRob Clark #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 2018a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_SCALE(float val) 2019a26ae754SRob Clark { 2020a26ae754SRob Clark return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; 2021a26ae754SRob Clark } 2022a26ae754SRob Clark 2023a26ae754SRob Clark #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000e096 2024a26ae754SRob Clark #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 2025a26ae754SRob Clark #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 2026a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 2027a26ae754SRob Clark { 2028a26ae754SRob Clark return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 2029a26ae754SRob Clark } 2030a26ae754SRob Clark 2031a26ae754SRob Clark #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x0000e097 2032a26ae754SRob Clark #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff 2033a26ae754SRob Clark #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0 2034a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val) 2035a26ae754SRob Clark { 2036a26ae754SRob Clark return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK; 2037a26ae754SRob Clark } 2038a26ae754SRob Clark 2039a26ae754SRob Clark #define REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO 0x0000e098 2040a26ae754SRob Clark #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 2041a26ae754SRob Clark #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 2042a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val) 2043a26ae754SRob Clark { 2044a26ae754SRob Clark return ((val) << A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; 2045a26ae754SRob Clark } 2046a26ae754SRob Clark 2047a26ae754SRob Clark #define REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x0000e099 2048a26ae754SRob Clark 2049a26ae754SRob Clark #define REG_A5XX_GRAS_SC_CNTL 0x0000e0a0 2050a26ae754SRob Clark #define A5XX_GRAS_SC_CNTL_SAMPLES_PASSED 0x00008000 2051a26ae754SRob Clark 2052a26ae754SRob Clark #define REG_A5XX_GRAS_SC_BIN_CNTL 0x0000e0a1 2053a26ae754SRob Clark 2054a26ae754SRob Clark #define REG_A5XX_GRAS_SC_RAS_MSAA_CNTL 0x0000e0a2 2055a26ae754SRob Clark #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 2056a26ae754SRob Clark #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 2057a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 2058a26ae754SRob Clark { 2059a26ae754SRob Clark return ((val) << A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK; 2060a26ae754SRob Clark } 2061a26ae754SRob Clark 2062a26ae754SRob Clark #define REG_A5XX_GRAS_SC_DEST_MSAA_CNTL 0x0000e0a3 2063a26ae754SRob Clark #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 2064a26ae754SRob Clark #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 2065a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 2066a26ae754SRob Clark { 2067a26ae754SRob Clark return ((val) << A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK; 2068a26ae754SRob Clark } 2069a26ae754SRob Clark #define A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 2070a26ae754SRob Clark 2071a26ae754SRob Clark #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL 0x0000e0a4 2072a26ae754SRob Clark 2073a26ae754SRob Clark #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0 0x0000e0aa 2074a26ae754SRob Clark #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000 2075a26ae754SRob Clark #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK 0x00007fff 2076a26ae754SRob Clark #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT 0 2077a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val) 2078a26ae754SRob Clark { 2079a26ae754SRob Clark return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK; 2080a26ae754SRob Clark } 2081a26ae754SRob Clark #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK 0x7fff0000 2082a26ae754SRob Clark #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT 16 2083a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val) 2084a26ae754SRob Clark { 2085a26ae754SRob Clark return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK; 2086a26ae754SRob Clark } 2087a26ae754SRob Clark 2088a26ae754SRob Clark #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0 0x0000e0ab 2089a26ae754SRob Clark #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000 2090a26ae754SRob Clark #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK 0x00007fff 2091a26ae754SRob Clark #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT 0 2092a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val) 2093a26ae754SRob Clark { 2094a26ae754SRob Clark return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK; 2095a26ae754SRob Clark } 2096a26ae754SRob Clark #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK 0x7fff0000 2097a26ae754SRob Clark #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT 16 2098a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val) 2099a26ae754SRob Clark { 2100a26ae754SRob Clark return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK; 2101a26ae754SRob Clark } 2102a26ae754SRob Clark 2103a26ae754SRob Clark #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0 0x0000e0ca 2104a26ae754SRob Clark #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000 2105a26ae754SRob Clark #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK 0x00007fff 2106a26ae754SRob Clark #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT 0 2107a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val) 2108a26ae754SRob Clark { 2109a26ae754SRob Clark return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK; 2110a26ae754SRob Clark } 2111a26ae754SRob Clark #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK 0x7fff0000 2112a26ae754SRob Clark #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT 16 2113a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val) 2114a26ae754SRob Clark { 2115a26ae754SRob Clark return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK; 2116a26ae754SRob Clark } 2117a26ae754SRob Clark 2118a26ae754SRob Clark #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0 0x0000e0cb 2119a26ae754SRob Clark #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000 2120a26ae754SRob Clark #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK 0x00007fff 2121a26ae754SRob Clark #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT 0 2122a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val) 2123a26ae754SRob Clark { 2124a26ae754SRob Clark return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK; 2125a26ae754SRob Clark } 2126a26ae754SRob Clark #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK 0x7fff0000 2127a26ae754SRob Clark #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT 16 2128a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val) 2129a26ae754SRob Clark { 2130a26ae754SRob Clark return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK; 2131a26ae754SRob Clark } 2132a26ae754SRob Clark 2133a26ae754SRob Clark #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000e0ea 2134a26ae754SRob Clark #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 2135a26ae754SRob Clark #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 2136a26ae754SRob Clark #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 2137a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 2138a26ae754SRob Clark { 2139a26ae754SRob Clark return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 2140a26ae754SRob Clark } 2141a26ae754SRob Clark #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 2142a26ae754SRob Clark #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 2143a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 2144a26ae754SRob Clark { 2145a26ae754SRob Clark return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 2146a26ae754SRob Clark } 2147a26ae754SRob Clark 2148a26ae754SRob Clark #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000e0eb 2149a26ae754SRob Clark #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 2150a26ae754SRob Clark #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 2151a26ae754SRob Clark #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 2152a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 2153a26ae754SRob Clark { 2154a26ae754SRob Clark return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 2155a26ae754SRob Clark } 2156a26ae754SRob Clark #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 2157a26ae754SRob Clark #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 2158a26ae754SRob Clark static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 2159a26ae754SRob Clark { 2160a26ae754SRob Clark return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 2161a26ae754SRob Clark } 2162a26ae754SRob Clark 2163a26ae754SRob Clark #define REG_A5XX_GRAS_LRZ_CNTL 0x0000e100 2164a26ae754SRob Clark 2165a26ae754SRob Clark #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO 0x0000e101 2166a26ae754SRob Clark 2167a26ae754SRob Clark #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_HI 0x0000e102 2168a26ae754SRob Clark 2169a26ae754SRob Clark #define REG_A5XX_GRAS_LRZ_BUFFER_PITCH 0x0000e103 2170a26ae754SRob Clark 2171a26ae754SRob Clark #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x0000e104 2172a26ae754SRob Clark 2173a26ae754SRob Clark #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x0000e105 2174a26ae754SRob Clark 2175a26ae754SRob Clark #define REG_A5XX_RB_CNTL 0x0000e140 2176a26ae754SRob Clark #define A5XX_RB_CNTL_WIDTH__MASK 0x000000ff 2177a26ae754SRob Clark #define A5XX_RB_CNTL_WIDTH__SHIFT 0 2178a26ae754SRob Clark static inline uint32_t A5XX_RB_CNTL_WIDTH(uint32_t val) 2179a26ae754SRob Clark { 2180a26ae754SRob Clark return ((val >> 5) << A5XX_RB_CNTL_WIDTH__SHIFT) & A5XX_RB_CNTL_WIDTH__MASK; 2181a26ae754SRob Clark } 2182a26ae754SRob Clark #define A5XX_RB_CNTL_HEIGHT__MASK 0x0001fe00 2183a26ae754SRob Clark #define A5XX_RB_CNTL_HEIGHT__SHIFT 9 2184a26ae754SRob Clark static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val) 2185a26ae754SRob Clark { 2186a26ae754SRob Clark return ((val >> 5) << A5XX_RB_CNTL_HEIGHT__SHIFT) & A5XX_RB_CNTL_HEIGHT__MASK; 2187a26ae754SRob Clark } 2188a26ae754SRob Clark #define A5XX_RB_CNTL_BYPASS 0x00020000 2189a26ae754SRob Clark 2190a26ae754SRob Clark #define REG_A5XX_RB_RENDER_CNTL 0x0000e141 2191a26ae754SRob Clark #define A5XX_RB_RENDER_CNTL_SAMPLES_PASSED 0x00000040 2192a26ae754SRob Clark #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000 2193a26ae754SRob Clark #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH2 0x00008000 2194a26ae754SRob Clark #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000 2195a26ae754SRob Clark #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16 2196a26ae754SRob Clark static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val) 2197a26ae754SRob Clark { 2198a26ae754SRob Clark return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK; 2199a26ae754SRob Clark } 2200a26ae754SRob Clark #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK 0xff000000 2201a26ae754SRob Clark #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT 24 2202a26ae754SRob Clark static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS2(uint32_t val) 2203a26ae754SRob Clark { 2204a26ae754SRob Clark return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK; 2205a26ae754SRob Clark } 2206a26ae754SRob Clark 2207a26ae754SRob Clark #define REG_A5XX_RB_RAS_MSAA_CNTL 0x0000e142 2208a26ae754SRob Clark #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 2209a26ae754SRob Clark #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 2210a26ae754SRob Clark static inline uint32_t A5XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 2211a26ae754SRob Clark { 2212a26ae754SRob Clark return ((val) << A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK; 2213a26ae754SRob Clark } 2214a26ae754SRob Clark 2215a26ae754SRob Clark #define REG_A5XX_RB_DEST_MSAA_CNTL 0x0000e143 2216a26ae754SRob Clark #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 2217a26ae754SRob Clark #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 2218a26ae754SRob Clark static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 2219a26ae754SRob Clark { 2220a26ae754SRob Clark return ((val) << A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK; 2221a26ae754SRob Clark } 2222a26ae754SRob Clark #define A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 2223a26ae754SRob Clark 2224a26ae754SRob Clark #define REG_A5XX_RB_RENDER_CONTROL0 0x0000e144 2225a26ae754SRob Clark #define A5XX_RB_RENDER_CONTROL0_VARYING 0x00000001 2226a26ae754SRob Clark #define A5XX_RB_RENDER_CONTROL0_XCOORD 0x00000040 2227a26ae754SRob Clark #define A5XX_RB_RENDER_CONTROL0_YCOORD 0x00000080 2228a26ae754SRob Clark #define A5XX_RB_RENDER_CONTROL0_ZCOORD 0x00000100 2229a26ae754SRob Clark #define A5XX_RB_RENDER_CONTROL0_WCOORD 0x00000200 2230a26ae754SRob Clark 2231a26ae754SRob Clark #define REG_A5XX_RB_RENDER_CONTROL1 0x0000e145 2232a26ae754SRob Clark #define A5XX_RB_RENDER_CONTROL1_FACENESS 0x00000002 2233a26ae754SRob Clark 2234a26ae754SRob Clark #define REG_A5XX_RB_FS_OUTPUT_CNTL 0x0000e146 2235a26ae754SRob Clark #define A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f 2236a26ae754SRob Clark #define A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT 0 2237a26ae754SRob Clark static inline uint32_t A5XX_RB_FS_OUTPUT_CNTL_MRT(uint32_t val) 2238a26ae754SRob Clark { 2239a26ae754SRob Clark return ((val) << A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK; 2240a26ae754SRob Clark } 2241a26ae754SRob Clark #define A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z 0x00000020 2242a26ae754SRob Clark 2243a26ae754SRob Clark #define REG_A5XX_RB_RENDER_COMPONENTS 0x0000e147 2244a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f 2245a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0 2246a26ae754SRob Clark static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) 2247a26ae754SRob Clark { 2248a26ae754SRob Clark return ((val) << A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT0__MASK; 2249a26ae754SRob Clark } 2250a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0 2251a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4 2252a26ae754SRob Clark static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) 2253a26ae754SRob Clark { 2254a26ae754SRob Clark return ((val) << A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT1__MASK; 2255a26ae754SRob Clark } 2256a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00 2257a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8 2258a26ae754SRob Clark static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) 2259a26ae754SRob Clark { 2260a26ae754SRob Clark return ((val) << A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT2__MASK; 2261a26ae754SRob Clark } 2262a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000 2263a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12 2264a26ae754SRob Clark static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) 2265a26ae754SRob Clark { 2266a26ae754SRob Clark return ((val) << A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT3__MASK; 2267a26ae754SRob Clark } 2268a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000 2269a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16 2270a26ae754SRob Clark static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) 2271a26ae754SRob Clark { 2272a26ae754SRob Clark return ((val) << A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT4__MASK; 2273a26ae754SRob Clark } 2274a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000 2275a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20 2276a26ae754SRob Clark static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) 2277a26ae754SRob Clark { 2278a26ae754SRob Clark return ((val) << A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT5__MASK; 2279a26ae754SRob Clark } 2280a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000 2281a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24 2282a26ae754SRob Clark static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) 2283a26ae754SRob Clark { 2284a26ae754SRob Clark return ((val) << A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT6__MASK; 2285a26ae754SRob Clark } 2286a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000 2287a26ae754SRob Clark #define A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28 2288a26ae754SRob Clark static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) 2289a26ae754SRob Clark { 2290a26ae754SRob Clark return ((val) << A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT7__MASK; 2291a26ae754SRob Clark } 2292a26ae754SRob Clark 2293a26ae754SRob Clark static inline uint32_t REG_A5XX_RB_MRT(uint32_t i0) { return 0x0000e150 + 0x7*i0; } 2294a26ae754SRob Clark 2295a26ae754SRob Clark static inline uint32_t REG_A5XX_RB_MRT_CONTROL(uint32_t i0) { return 0x0000e150 + 0x7*i0; } 2296a26ae754SRob Clark #define A5XX_RB_MRT_CONTROL_BLEND 0x00000001 2297a26ae754SRob Clark #define A5XX_RB_MRT_CONTROL_BLEND2 0x00000002 2298a26ae754SRob Clark #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780 2299a26ae754SRob Clark #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7 2300a26ae754SRob Clark static inline uint32_t A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 2301a26ae754SRob Clark { 2302a26ae754SRob Clark return ((val) << A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 2303a26ae754SRob Clark } 2304a26ae754SRob Clark 2305a26ae754SRob Clark static inline uint32_t REG_A5XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x0000e151 + 0x7*i0; } 2306a26ae754SRob Clark #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 2307a26ae754SRob Clark #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 2308a26ae754SRob Clark static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 2309a26ae754SRob Clark { 2310a26ae754SRob Clark return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 2311a26ae754SRob Clark } 2312a26ae754SRob Clark #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 2313a26ae754SRob Clark #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 2314a26ae754SRob Clark static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 2315a26ae754SRob Clark { 2316a26ae754SRob Clark return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 2317a26ae754SRob Clark } 2318a26ae754SRob Clark #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 2319a26ae754SRob Clark #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 2320a26ae754SRob Clark static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 2321a26ae754SRob Clark { 2322a26ae754SRob Clark return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 2323a26ae754SRob Clark } 2324a26ae754SRob Clark #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 2325a26ae754SRob Clark #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 2326a26ae754SRob Clark static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 2327a26ae754SRob Clark { 2328a26ae754SRob Clark return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 2329a26ae754SRob Clark } 2330a26ae754SRob Clark #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 2331a26ae754SRob Clark #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 2332a26ae754SRob Clark static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 2333a26ae754SRob Clark { 2334a26ae754SRob Clark return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 2335a26ae754SRob Clark } 2336a26ae754SRob Clark #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 2337a26ae754SRob Clark #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 2338a26ae754SRob Clark static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 2339a26ae754SRob Clark { 2340a26ae754SRob Clark return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 2341a26ae754SRob Clark } 2342a26ae754SRob Clark 2343a26ae754SRob Clark static inline uint32_t REG_A5XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x0000e152 + 0x7*i0; } 2344a26ae754SRob Clark #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff 2345a26ae754SRob Clark #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 2346a26ae754SRob Clark static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) 2347a26ae754SRob Clark { 2348a26ae754SRob Clark return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 2349a26ae754SRob Clark } 2350a26ae754SRob Clark #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300 2351a26ae754SRob Clark #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8 2352a26ae754SRob Clark static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a5xx_tile_mode val) 2353a26ae754SRob Clark { 2354a26ae754SRob Clark return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 2355a26ae754SRob Clark } 2356a26ae754SRob Clark #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000 2357a26ae754SRob Clark #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13 2358a26ae754SRob Clark static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 2359a26ae754SRob Clark { 2360a26ae754SRob Clark return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 2361a26ae754SRob Clark } 2362a26ae754SRob Clark #define A5XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00008000 2363a26ae754SRob Clark 2364a26ae754SRob Clark static inline uint32_t REG_A5XX_RB_MRT_PITCH(uint32_t i0) { return 0x0000e153 + 0x7*i0; } 2365a26ae754SRob Clark #define A5XX_RB_MRT_PITCH__MASK 0xffffffff 2366a26ae754SRob Clark #define A5XX_RB_MRT_PITCH__SHIFT 0 2367a26ae754SRob Clark static inline uint32_t A5XX_RB_MRT_PITCH(uint32_t val) 2368a26ae754SRob Clark { 2369a26ae754SRob Clark return ((val >> 6) << A5XX_RB_MRT_PITCH__SHIFT) & A5XX_RB_MRT_PITCH__MASK; 2370a26ae754SRob Clark } 2371a26ae754SRob Clark 2372a26ae754SRob Clark static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x0000e154 + 0x7*i0; } 2373a26ae754SRob Clark #define A5XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff 2374a26ae754SRob Clark #define A5XX_RB_MRT_ARRAY_PITCH__SHIFT 0 2375a26ae754SRob Clark static inline uint32_t A5XX_RB_MRT_ARRAY_PITCH(uint32_t val) 2376a26ae754SRob Clark { 2377a26ae754SRob Clark return ((val >> 6) << A5XX_RB_MRT_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_ARRAY_PITCH__MASK; 2378a26ae754SRob Clark } 2379a26ae754SRob Clark 2380a26ae754SRob Clark static inline uint32_t REG_A5XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x0000e155 + 0x7*i0; } 2381a26ae754SRob Clark 2382a26ae754SRob Clark static inline uint32_t REG_A5XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x0000e156 + 0x7*i0; } 2383a26ae754SRob Clark 2384a26ae754SRob Clark #define REG_A5XX_RB_BLEND_RED 0x0000e1a0 2385a26ae754SRob Clark #define A5XX_RB_BLEND_RED_UINT__MASK 0x000000ff 2386a26ae754SRob Clark #define A5XX_RB_BLEND_RED_UINT__SHIFT 0 2387a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_RED_UINT(uint32_t val) 2388a26ae754SRob Clark { 2389a26ae754SRob Clark return ((val) << A5XX_RB_BLEND_RED_UINT__SHIFT) & A5XX_RB_BLEND_RED_UINT__MASK; 2390a26ae754SRob Clark } 2391a26ae754SRob Clark #define A5XX_RB_BLEND_RED_SINT__MASK 0x0000ff00 2392a26ae754SRob Clark #define A5XX_RB_BLEND_RED_SINT__SHIFT 8 2393a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val) 2394a26ae754SRob Clark { 2395a26ae754SRob Clark return ((val) << A5XX_RB_BLEND_RED_SINT__SHIFT) & A5XX_RB_BLEND_RED_SINT__MASK; 2396a26ae754SRob Clark } 2397a26ae754SRob Clark #define A5XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 2398a26ae754SRob Clark #define A5XX_RB_BLEND_RED_FLOAT__SHIFT 16 2399a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val) 2400a26ae754SRob Clark { 2401a26ae754SRob Clark return ((util_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK; 2402a26ae754SRob Clark } 2403a26ae754SRob Clark 2404a26ae754SRob Clark #define REG_A5XX_RB_BLEND_RED_F32 0x0000e1a1 2405a26ae754SRob Clark #define A5XX_RB_BLEND_RED_F32__MASK 0xffffffff 2406a26ae754SRob Clark #define A5XX_RB_BLEND_RED_F32__SHIFT 0 2407a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_RED_F32(float val) 2408a26ae754SRob Clark { 2409a26ae754SRob Clark return ((fui(val)) << A5XX_RB_BLEND_RED_F32__SHIFT) & A5XX_RB_BLEND_RED_F32__MASK; 2410a26ae754SRob Clark } 2411a26ae754SRob Clark 2412a26ae754SRob Clark #define REG_A5XX_RB_BLEND_GREEN 0x0000e1a2 2413a26ae754SRob Clark #define A5XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff 2414a26ae754SRob Clark #define A5XX_RB_BLEND_GREEN_UINT__SHIFT 0 2415a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_GREEN_UINT(uint32_t val) 2416a26ae754SRob Clark { 2417a26ae754SRob Clark return ((val) << A5XX_RB_BLEND_GREEN_UINT__SHIFT) & A5XX_RB_BLEND_GREEN_UINT__MASK; 2418a26ae754SRob Clark } 2419a26ae754SRob Clark #define A5XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00 2420a26ae754SRob Clark #define A5XX_RB_BLEND_GREEN_SINT__SHIFT 8 2421a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val) 2422a26ae754SRob Clark { 2423a26ae754SRob Clark return ((val) << A5XX_RB_BLEND_GREEN_SINT__SHIFT) & A5XX_RB_BLEND_GREEN_SINT__MASK; 2424a26ae754SRob Clark } 2425a26ae754SRob Clark #define A5XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 2426a26ae754SRob Clark #define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 2427a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val) 2428a26ae754SRob Clark { 2429a26ae754SRob Clark return ((util_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK; 2430a26ae754SRob Clark } 2431a26ae754SRob Clark 2432a26ae754SRob Clark #define REG_A5XX_RB_BLEND_GREEN_F32 0x0000e1a3 2433a26ae754SRob Clark #define A5XX_RB_BLEND_GREEN_F32__MASK 0xffffffff 2434a26ae754SRob Clark #define A5XX_RB_BLEND_GREEN_F32__SHIFT 0 2435a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_GREEN_F32(float val) 2436a26ae754SRob Clark { 2437a26ae754SRob Clark return ((fui(val)) << A5XX_RB_BLEND_GREEN_F32__SHIFT) & A5XX_RB_BLEND_GREEN_F32__MASK; 2438a26ae754SRob Clark } 2439a26ae754SRob Clark 2440a26ae754SRob Clark #define REG_A5XX_RB_BLEND_BLUE 0x0000e1a4 2441a26ae754SRob Clark #define A5XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff 2442a26ae754SRob Clark #define A5XX_RB_BLEND_BLUE_UINT__SHIFT 0 2443a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_BLUE_UINT(uint32_t val) 2444a26ae754SRob Clark { 2445a26ae754SRob Clark return ((val) << A5XX_RB_BLEND_BLUE_UINT__SHIFT) & A5XX_RB_BLEND_BLUE_UINT__MASK; 2446a26ae754SRob Clark } 2447a26ae754SRob Clark #define A5XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00 2448a26ae754SRob Clark #define A5XX_RB_BLEND_BLUE_SINT__SHIFT 8 2449a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val) 2450a26ae754SRob Clark { 2451a26ae754SRob Clark return ((val) << A5XX_RB_BLEND_BLUE_SINT__SHIFT) & A5XX_RB_BLEND_BLUE_SINT__MASK; 2452a26ae754SRob Clark } 2453a26ae754SRob Clark #define A5XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 2454a26ae754SRob Clark #define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 2455a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val) 2456a26ae754SRob Clark { 2457a26ae754SRob Clark return ((util_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK; 2458a26ae754SRob Clark } 2459a26ae754SRob Clark 2460a26ae754SRob Clark #define REG_A5XX_RB_BLEND_BLUE_F32 0x0000e1a5 2461a26ae754SRob Clark #define A5XX_RB_BLEND_BLUE_F32__MASK 0xffffffff 2462a26ae754SRob Clark #define A5XX_RB_BLEND_BLUE_F32__SHIFT 0 2463a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_BLUE_F32(float val) 2464a26ae754SRob Clark { 2465a26ae754SRob Clark return ((fui(val)) << A5XX_RB_BLEND_BLUE_F32__SHIFT) & A5XX_RB_BLEND_BLUE_F32__MASK; 2466a26ae754SRob Clark } 2467a26ae754SRob Clark 2468a26ae754SRob Clark #define REG_A5XX_RB_BLEND_ALPHA 0x0000e1a6 2469a26ae754SRob Clark #define A5XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff 2470a26ae754SRob Clark #define A5XX_RB_BLEND_ALPHA_UINT__SHIFT 0 2471a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_ALPHA_UINT(uint32_t val) 2472a26ae754SRob Clark { 2473a26ae754SRob Clark return ((val) << A5XX_RB_BLEND_ALPHA_UINT__SHIFT) & A5XX_RB_BLEND_ALPHA_UINT__MASK; 2474a26ae754SRob Clark } 2475a26ae754SRob Clark #define A5XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00 2476a26ae754SRob Clark #define A5XX_RB_BLEND_ALPHA_SINT__SHIFT 8 2477a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val) 2478a26ae754SRob Clark { 2479a26ae754SRob Clark return ((val) << A5XX_RB_BLEND_ALPHA_SINT__SHIFT) & A5XX_RB_BLEND_ALPHA_SINT__MASK; 2480a26ae754SRob Clark } 2481a26ae754SRob Clark #define A5XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 2482a26ae754SRob Clark #define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 2483a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val) 2484a26ae754SRob Clark { 2485a26ae754SRob Clark return ((util_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK; 2486a26ae754SRob Clark } 2487a26ae754SRob Clark 2488a26ae754SRob Clark #define REG_A5XX_RB_BLEND_ALPHA_F32 0x0000e1a7 2489a26ae754SRob Clark #define A5XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff 2490a26ae754SRob Clark #define A5XX_RB_BLEND_ALPHA_F32__SHIFT 0 2491a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_ALPHA_F32(float val) 2492a26ae754SRob Clark { 2493a26ae754SRob Clark return ((fui(val)) << A5XX_RB_BLEND_ALPHA_F32__SHIFT) & A5XX_RB_BLEND_ALPHA_F32__MASK; 2494a26ae754SRob Clark } 2495a26ae754SRob Clark 2496a26ae754SRob Clark #define REG_A5XX_RB_ALPHA_CONTROL 0x0000e1a8 2497a26ae754SRob Clark #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff 2498a26ae754SRob Clark #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 2499a26ae754SRob Clark static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) 2500a26ae754SRob Clark { 2501a26ae754SRob Clark return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; 2502a26ae754SRob Clark } 2503a26ae754SRob Clark #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 2504a26ae754SRob Clark #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 2505a26ae754SRob Clark #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 2506a26ae754SRob Clark static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 2507a26ae754SRob Clark { 2508a26ae754SRob Clark return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; 2509a26ae754SRob Clark } 2510a26ae754SRob Clark 2511a26ae754SRob Clark #define REG_A5XX_RB_BLEND_CNTL 0x0000e1a9 2512a26ae754SRob Clark #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff 2513a26ae754SRob Clark #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 2514a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val) 2515a26ae754SRob Clark { 2516a26ae754SRob Clark return ((val) << A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK; 2517a26ae754SRob Clark } 2518a26ae754SRob Clark #define A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100 2519a26ae754SRob Clark #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000 2520a26ae754SRob Clark #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16 2521a26ae754SRob Clark static inline uint32_t A5XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val) 2522a26ae754SRob Clark { 2523a26ae754SRob Clark return ((val) << A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK; 2524a26ae754SRob Clark } 2525a26ae754SRob Clark 2526a26ae754SRob Clark #define REG_A5XX_RB_DEPTH_PLANE_CNTL 0x0000e1b0 2527a26ae754SRob Clark #define A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001 2528a26ae754SRob Clark 2529a26ae754SRob Clark #define REG_A5XX_RB_DEPTH_CNTL 0x0000e1b1 2530a26ae754SRob Clark #define A5XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001 2531a26ae754SRob Clark #define A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002 2532a26ae754SRob Clark #define A5XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c 2533a26ae754SRob Clark #define A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2 2534a26ae754SRob Clark static inline uint32_t A5XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) 2535a26ae754SRob Clark { 2536a26ae754SRob Clark return ((val) << A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A5XX_RB_DEPTH_CNTL_ZFUNC__MASK; 2537a26ae754SRob Clark } 2538a26ae754SRob Clark #define A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040 2539a26ae754SRob Clark 2540a26ae754SRob Clark #define REG_A5XX_RB_DEPTH_BUFFER_INFO 0x0000e1b2 2541a26ae754SRob Clark #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 2542a26ae754SRob Clark #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 2543a26ae754SRob Clark static inline uint32_t A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val) 2544a26ae754SRob Clark { 2545a26ae754SRob Clark return ((val) << A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; 2546a26ae754SRob Clark } 2547a26ae754SRob Clark 2548a26ae754SRob Clark #define REG_A5XX_RB_DEPTH_BUFFER_BASE_LO 0x0000e1b3 2549a26ae754SRob Clark 2550a26ae754SRob Clark #define REG_A5XX_RB_DEPTH_BUFFER_BASE_HI 0x0000e1b4 2551a26ae754SRob Clark 2552a26ae754SRob Clark #define REG_A5XX_RB_DEPTH_BUFFER_PITCH 0x0000e1b5 2553a26ae754SRob Clark #define A5XX_RB_DEPTH_BUFFER_PITCH__MASK 0xffffffff 2554a26ae754SRob Clark #define A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0 2555a26ae754SRob Clark static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) 2556a26ae754SRob Clark { 2557a26ae754SRob Clark return ((val >> 5) << A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_PITCH__MASK; 2558a26ae754SRob Clark } 2559a26ae754SRob Clark 2560a26ae754SRob Clark #define REG_A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x0000e1b6 2561a26ae754SRob Clark #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0xffffffff 2562a26ae754SRob Clark #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0 2563a26ae754SRob Clark static inline uint32_t A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) 2564a26ae754SRob Clark { 2565a26ae754SRob Clark return ((val >> 5) << A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; 2566a26ae754SRob Clark } 2567a26ae754SRob Clark 2568a26ae754SRob Clark #define REG_A5XX_RB_STENCIL_CONTROL 0x0000e1c0 2569a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 2570a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 2571a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 2572a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 2573a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 2574a26ae754SRob Clark static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 2575a26ae754SRob Clark { 2576a26ae754SRob Clark return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC__MASK; 2577a26ae754SRob Clark } 2578a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 2579a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 2580a26ae754SRob Clark static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 2581a26ae754SRob Clark { 2582a26ae754SRob Clark return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL__MASK; 2583a26ae754SRob Clark } 2584a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 2585a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 2586a26ae754SRob Clark static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 2587a26ae754SRob Clark { 2588a26ae754SRob Clark return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS__MASK; 2589a26ae754SRob Clark } 2590a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 2591a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 2592a26ae754SRob Clark static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 2593a26ae754SRob Clark { 2594a26ae754SRob Clark return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 2595a26ae754SRob Clark } 2596a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 2597a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 2598a26ae754SRob Clark static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 2599a26ae754SRob Clark { 2600a26ae754SRob Clark return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 2601a26ae754SRob Clark } 2602a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 2603a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 2604a26ae754SRob Clark static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 2605a26ae754SRob Clark { 2606a26ae754SRob Clark return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 2607a26ae754SRob Clark } 2608a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 2609a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 2610a26ae754SRob Clark static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 2611a26ae754SRob Clark { 2612a26ae754SRob Clark return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 2613a26ae754SRob Clark } 2614a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 2615a26ae754SRob Clark #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 2616a26ae754SRob Clark static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 2617a26ae754SRob Clark { 2618a26ae754SRob Clark return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 2619a26ae754SRob Clark } 2620a26ae754SRob Clark 2621a26ae754SRob Clark #define REG_A5XX_RB_STENCIL_INFO 0x0000e1c1 2622a26ae754SRob Clark #define A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 2623a26ae754SRob Clark 2624a26ae754SRob Clark #define REG_A5XX_RB_STENCIL_BASE_LO 0x0000e1c2 2625a26ae754SRob Clark 2626a26ae754SRob Clark #define REG_A5XX_RB_STENCIL_BASE_HI 0x0000e1c3 2627a26ae754SRob Clark 2628a26ae754SRob Clark #define REG_A5XX_RB_STENCIL_PITCH 0x0000e1c4 2629a26ae754SRob Clark #define A5XX_RB_STENCIL_PITCH__MASK 0xffffffff 2630a26ae754SRob Clark #define A5XX_RB_STENCIL_PITCH__SHIFT 0 2631a26ae754SRob Clark static inline uint32_t A5XX_RB_STENCIL_PITCH(uint32_t val) 2632a26ae754SRob Clark { 2633a26ae754SRob Clark return ((val >> 6) << A5XX_RB_STENCIL_PITCH__SHIFT) & A5XX_RB_STENCIL_PITCH__MASK; 2634a26ae754SRob Clark } 2635a26ae754SRob Clark 2636a26ae754SRob Clark #define REG_A5XX_RB_STENCIL_ARRAY_PITCH 0x0000e1c5 2637a26ae754SRob Clark #define A5XX_RB_STENCIL_ARRAY_PITCH__MASK 0xffffffff 2638a26ae754SRob Clark #define A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT 0 2639a26ae754SRob Clark static inline uint32_t A5XX_RB_STENCIL_ARRAY_PITCH(uint32_t val) 2640a26ae754SRob Clark { 2641a26ae754SRob Clark return ((val >> 6) << A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT) & A5XX_RB_STENCIL_ARRAY_PITCH__MASK; 2642a26ae754SRob Clark } 2643a26ae754SRob Clark 2644a26ae754SRob Clark #define REG_A5XX_RB_STENCILREFMASK 0x0000e1c6 2645a26ae754SRob Clark #define A5XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 2646a26ae754SRob Clark #define A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 2647a26ae754SRob Clark static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 2648a26ae754SRob Clark { 2649a26ae754SRob Clark return ((val) << A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILREF__MASK; 2650a26ae754SRob Clark } 2651a26ae754SRob Clark #define A5XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 2652a26ae754SRob Clark #define A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 2653a26ae754SRob Clark static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 2654a26ae754SRob Clark { 2655a26ae754SRob Clark return ((val) << A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILMASK__MASK; 2656a26ae754SRob Clark } 2657a26ae754SRob Clark #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 2658a26ae754SRob Clark #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 2659a26ae754SRob Clark static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 2660a26ae754SRob Clark { 2661a26ae754SRob Clark return ((val) << A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 2662a26ae754SRob Clark } 2663a26ae754SRob Clark 2664a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E1C7 0x0000e1c7 2665a26ae754SRob Clark 2666a26ae754SRob Clark #define REG_A5XX_RB_WINDOW_OFFSET 0x0000e1d0 2667a26ae754SRob Clark #define A5XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 2668a26ae754SRob Clark #define A5XX_RB_WINDOW_OFFSET_X__MASK 0x00007fff 2669a26ae754SRob Clark #define A5XX_RB_WINDOW_OFFSET_X__SHIFT 0 2670a26ae754SRob Clark static inline uint32_t A5XX_RB_WINDOW_OFFSET_X(uint32_t val) 2671a26ae754SRob Clark { 2672a26ae754SRob Clark return ((val) << A5XX_RB_WINDOW_OFFSET_X__SHIFT) & A5XX_RB_WINDOW_OFFSET_X__MASK; 2673a26ae754SRob Clark } 2674a26ae754SRob Clark #define A5XX_RB_WINDOW_OFFSET_Y__MASK 0x7fff0000 2675a26ae754SRob Clark #define A5XX_RB_WINDOW_OFFSET_Y__SHIFT 16 2676a26ae754SRob Clark static inline uint32_t A5XX_RB_WINDOW_OFFSET_Y(uint32_t val) 2677a26ae754SRob Clark { 2678a26ae754SRob Clark return ((val) << A5XX_RB_WINDOW_OFFSET_Y__SHIFT) & A5XX_RB_WINDOW_OFFSET_Y__MASK; 2679a26ae754SRob Clark } 2680a26ae754SRob Clark 2681a26ae754SRob Clark #define REG_A5XX_RB_BLIT_CNTL 0x0000e210 2682a26ae754SRob Clark #define A5XX_RB_BLIT_CNTL_BUF__MASK 0x0000003f 2683a26ae754SRob Clark #define A5XX_RB_BLIT_CNTL_BUF__SHIFT 0 2684a26ae754SRob Clark static inline uint32_t A5XX_RB_BLIT_CNTL_BUF(enum a5xx_blit_buf val) 2685a26ae754SRob Clark { 2686a26ae754SRob Clark return ((val) << A5XX_RB_BLIT_CNTL_BUF__SHIFT) & A5XX_RB_BLIT_CNTL_BUF__MASK; 2687a26ae754SRob Clark } 2688a26ae754SRob Clark 2689a26ae754SRob Clark #define REG_A5XX_RB_RESOLVE_CNTL_1 0x0000e211 2690a26ae754SRob Clark #define A5XX_RB_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE 0x80000000 2691a26ae754SRob Clark #define A5XX_RB_RESOLVE_CNTL_1_X__MASK 0x00007fff 2692a26ae754SRob Clark #define A5XX_RB_RESOLVE_CNTL_1_X__SHIFT 0 2693a26ae754SRob Clark static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_X(uint32_t val) 2694a26ae754SRob Clark { 2695a26ae754SRob Clark return ((val) << A5XX_RB_RESOLVE_CNTL_1_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_X__MASK; 2696a26ae754SRob Clark } 2697a26ae754SRob Clark #define A5XX_RB_RESOLVE_CNTL_1_Y__MASK 0x7fff0000 2698a26ae754SRob Clark #define A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT 16 2699a26ae754SRob Clark static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_Y(uint32_t val) 2700a26ae754SRob Clark { 2701a26ae754SRob Clark return ((val) << A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_Y__MASK; 2702a26ae754SRob Clark } 2703a26ae754SRob Clark 2704a26ae754SRob Clark #define REG_A5XX_RB_RESOLVE_CNTL_2 0x0000e212 2705a26ae754SRob Clark #define A5XX_RB_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE 0x80000000 2706a26ae754SRob Clark #define A5XX_RB_RESOLVE_CNTL_2_X__MASK 0x00007fff 2707a26ae754SRob Clark #define A5XX_RB_RESOLVE_CNTL_2_X__SHIFT 0 2708a26ae754SRob Clark static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_X(uint32_t val) 2709a26ae754SRob Clark { 2710a26ae754SRob Clark return ((val) << A5XX_RB_RESOLVE_CNTL_2_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_X__MASK; 2711a26ae754SRob Clark } 2712a26ae754SRob Clark #define A5XX_RB_RESOLVE_CNTL_2_Y__MASK 0x7fff0000 2713a26ae754SRob Clark #define A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT 16 2714a26ae754SRob Clark static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_Y(uint32_t val) 2715a26ae754SRob Clark { 2716a26ae754SRob Clark return ((val) << A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_Y__MASK; 2717a26ae754SRob Clark } 2718a26ae754SRob Clark 2719a26ae754SRob Clark #define REG_A5XX_RB_RESOLVE_CNTL_3 0x0000e213 2720a26ae754SRob Clark 2721a26ae754SRob Clark #define REG_A5XX_RB_BLIT_DST_LO 0x0000e214 2722a26ae754SRob Clark 2723a26ae754SRob Clark #define REG_A5XX_RB_BLIT_DST_HI 0x0000e215 2724a26ae754SRob Clark 2725a26ae754SRob Clark #define REG_A5XX_RB_BLIT_DST_PITCH 0x0000e216 2726a26ae754SRob Clark #define A5XX_RB_BLIT_DST_PITCH__MASK 0xffffffff 2727a26ae754SRob Clark #define A5XX_RB_BLIT_DST_PITCH__SHIFT 0 2728a26ae754SRob Clark static inline uint32_t A5XX_RB_BLIT_DST_PITCH(uint32_t val) 2729a26ae754SRob Clark { 2730a26ae754SRob Clark return ((val >> 6) << A5XX_RB_BLIT_DST_PITCH__SHIFT) & A5XX_RB_BLIT_DST_PITCH__MASK; 2731a26ae754SRob Clark } 2732a26ae754SRob Clark 2733a26ae754SRob Clark #define REG_A5XX_RB_BLIT_DST_ARRAY_PITCH 0x0000e217 2734a26ae754SRob Clark #define A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0xffffffff 2735a26ae754SRob Clark #define A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0 2736a26ae754SRob Clark static inline uint32_t A5XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) 2737a26ae754SRob Clark { 2738a26ae754SRob Clark return ((val >> 6) << A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK; 2739a26ae754SRob Clark } 2740a26ae754SRob Clark 2741a26ae754SRob Clark #define REG_A5XX_RB_CLEAR_COLOR_DW0 0x0000e218 2742a26ae754SRob Clark 2743a26ae754SRob Clark #define REG_A5XX_RB_CLEAR_COLOR_DW1 0x0000e219 2744a26ae754SRob Clark 2745a26ae754SRob Clark #define REG_A5XX_RB_CLEAR_COLOR_DW2 0x0000e21a 2746a26ae754SRob Clark 2747a26ae754SRob Clark #define REG_A5XX_RB_CLEAR_COLOR_DW3 0x0000e21b 2748a26ae754SRob Clark 2749a26ae754SRob Clark #define REG_A5XX_RB_CLEAR_CNTL 0x0000e21c 2750a26ae754SRob Clark #define A5XX_RB_CLEAR_CNTL_FAST_CLEAR 0x00000002 2751a26ae754SRob Clark #define A5XX_RB_CLEAR_CNTL_MASK__MASK 0x000000f0 2752a26ae754SRob Clark #define A5XX_RB_CLEAR_CNTL_MASK__SHIFT 4 2753a26ae754SRob Clark static inline uint32_t A5XX_RB_CLEAR_CNTL_MASK(uint32_t val) 2754a26ae754SRob Clark { 2755a26ae754SRob Clark return ((val) << A5XX_RB_CLEAR_CNTL_MASK__SHIFT) & A5XX_RB_CLEAR_CNTL_MASK__MASK; 2756a26ae754SRob Clark } 2757a26ae754SRob Clark 2758a26ae754SRob Clark #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x0000e240 2759a26ae754SRob Clark 2760a26ae754SRob Clark #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x0000e241 2761a26ae754SRob Clark 2762a26ae754SRob Clark #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x0000e242 2763a26ae754SRob Clark 2764a26ae754SRob Clark static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x0000e243 + 0x4*i0; } 2765a26ae754SRob Clark 2766a26ae754SRob Clark static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x0000e243 + 0x4*i0; } 2767a26ae754SRob Clark 2768a26ae754SRob Clark static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x0000e244 + 0x4*i0; } 2769a26ae754SRob Clark 2770a26ae754SRob Clark static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x0000e245 + 0x4*i0; } 2771a26ae754SRob Clark #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK 0xffffffff 2772a26ae754SRob Clark #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT 0 2773a26ae754SRob Clark static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t val) 2774a26ae754SRob Clark { 2775a26ae754SRob Clark return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK; 2776a26ae754SRob Clark } 2777a26ae754SRob Clark 2778a26ae754SRob Clark static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0) { return 0x0000e246 + 0x4*i0; } 2779a26ae754SRob Clark #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK 0xffffffff 2780a26ae754SRob Clark #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0 2781a26ae754SRob Clark static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) 2782a26ae754SRob Clark { 2783a26ae754SRob Clark return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK; 2784a26ae754SRob Clark } 2785a26ae754SRob Clark 2786a26ae754SRob Clark #define REG_A5XX_RB_BLIT_FLAG_DST_LO 0x0000e263 2787a26ae754SRob Clark 2788a26ae754SRob Clark #define REG_A5XX_RB_BLIT_FLAG_DST_HI 0x0000e264 2789a26ae754SRob Clark 2790a26ae754SRob Clark #define REG_A5XX_RB_BLIT_FLAG_DST_PITCH 0x0000e265 2791a26ae754SRob Clark #define A5XX_RB_BLIT_FLAG_DST_PITCH__MASK 0xffffffff 2792a26ae754SRob Clark #define A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT 0 2793a26ae754SRob Clark static inline uint32_t A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val) 2794a26ae754SRob Clark { 2795a26ae754SRob Clark return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_PITCH__MASK; 2796a26ae754SRob Clark } 2797a26ae754SRob Clark 2798a26ae754SRob Clark #define REG_A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH 0x0000e266 2799a26ae754SRob Clark #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK 0xffffffff 2800a26ae754SRob Clark #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT 0 2801a26ae754SRob Clark static inline uint32_t A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val) 2802a26ae754SRob Clark { 2803a26ae754SRob Clark return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK; 2804a26ae754SRob Clark } 2805a26ae754SRob Clark 2806a26ae754SRob Clark #define REG_A5XX_VPC_CNTL_0 0x0000e280 2807a26ae754SRob Clark #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK 0x0000007f 2808a26ae754SRob Clark #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT 0 2809a26ae754SRob Clark static inline uint32_t A5XX_VPC_CNTL_0_STRIDE_IN_VPC(uint32_t val) 2810a26ae754SRob Clark { 2811a26ae754SRob Clark return ((val) << A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT) & A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK; 2812a26ae754SRob Clark } 2813a26ae754SRob Clark #define A5XX_VPC_CNTL_0_VARYING 0x00000800 2814a26ae754SRob Clark 2815a26ae754SRob Clark static inline uint32_t REG_A5XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x0000e282 + 0x1*i0; } 2816a26ae754SRob Clark 2817a26ae754SRob Clark static inline uint32_t REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x0000e282 + 0x1*i0; } 2818a26ae754SRob Clark 2819a26ae754SRob Clark static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000e28a + 0x1*i0; } 2820a26ae754SRob Clark 2821a26ae754SRob Clark static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000e28a + 0x1*i0; } 2822a26ae754SRob Clark 2823a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E292 0x0000e292 2824a26ae754SRob Clark 2825a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E293 0x0000e293 2826a26ae754SRob Clark 2827a26ae754SRob Clark static inline uint32_t REG_A5XX_VPC_VAR(uint32_t i0) { return 0x0000e294 + 0x1*i0; } 2828a26ae754SRob Clark 2829a26ae754SRob Clark static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 + 0x1*i0; } 2830a26ae754SRob Clark 2831a26ae754SRob Clark #define REG_A5XX_VPC_GS_SIV_CNTL 0x0000e298 2832a26ae754SRob Clark 2833a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E29A 0x0000e29a 2834a26ae754SRob Clark 2835a26ae754SRob Clark #define REG_A5XX_VPC_PACK 0x0000e29d 2836a26ae754SRob Clark #define A5XX_VPC_PACK_NUMNONPOSVAR__MASK 0x000000ff 2837a26ae754SRob Clark #define A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT 0 2838a26ae754SRob Clark static inline uint32_t A5XX_VPC_PACK_NUMNONPOSVAR(uint32_t val) 2839a26ae754SRob Clark { 2840a26ae754SRob Clark return ((val) << A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A5XX_VPC_PACK_NUMNONPOSVAR__MASK; 2841a26ae754SRob Clark } 2842a26ae754SRob Clark 2843a26ae754SRob Clark #define REG_A5XX_VPC_FS_PRIMITIVEID_CNTL 0x0000e2a0 2844a26ae754SRob Clark 2845a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E2A1 0x0000e2a1 2846a26ae754SRob Clark 2847a26ae754SRob Clark #define REG_A5XX_VPC_SO_OVERRIDE 0x0000e2a2 2848a26ae754SRob Clark 2849a26ae754SRob Clark #define REG_A5XX_VPC_SO_BUFFER_BASE_LO_0 0x0000e2a7 2850a26ae754SRob Clark 2851a26ae754SRob Clark #define REG_A5XX_VPC_SO_BUFFER_BASE_HI_0 0x0000e2a8 2852a26ae754SRob Clark 2853a26ae754SRob Clark #define REG_A5XX_VPC_SO_BUFFER_SIZE_0 0x0000e2a9 2854a26ae754SRob Clark 2855a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E2AB 0x0000e2ab 2856a26ae754SRob Clark 2857a26ae754SRob Clark #define REG_A5XX_VPC_SO_FLUSH_BASE_LO_0 0x0000e2ac 2858a26ae754SRob Clark 2859a26ae754SRob Clark #define REG_A5XX_VPC_SO_FLUSH_BASE_HI_0 0x0000e2ad 2860a26ae754SRob Clark 2861a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E2AE 0x0000e2ae 2862a26ae754SRob Clark 2863a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E2B2 0x0000e2b2 2864a26ae754SRob Clark 2865a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E2B9 0x0000e2b9 2866a26ae754SRob Clark 2867a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E2C0 0x0000e2c0 2868a26ae754SRob Clark 2869a26ae754SRob Clark #define REG_A5XX_PC_PRIMITIVE_CNTL 0x0000e384 2870a26ae754SRob Clark #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK 0x0000007f 2871a26ae754SRob Clark #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT 0 2872a26ae754SRob Clark static inline uint32_t A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val) 2873a26ae754SRob Clark { 2874a26ae754SRob Clark return ((val) << A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT) & A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK; 2875a26ae754SRob Clark } 2876a26ae754SRob Clark 2877a26ae754SRob Clark #define REG_A5XX_PC_PRIM_VTX_CNTL 0x0000e385 2878a26ae754SRob Clark #define A5XX_PC_PRIM_VTX_CNTL_PSIZE 0x00000800 2879a26ae754SRob Clark 2880a26ae754SRob Clark #define REG_A5XX_PC_RASTER_CNTL 0x0000e388 2881a26ae754SRob Clark 2882a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E389 0x0000e389 2883a26ae754SRob Clark 2884a26ae754SRob Clark #define REG_A5XX_PC_RESTART_INDEX 0x0000e38c 2885a26ae754SRob Clark 2886a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E38D 0x0000e38d 2887a26ae754SRob Clark 2888a26ae754SRob Clark #define REG_A5XX_PC_GS_PARAM 0x0000e38e 2889a26ae754SRob Clark 2890a26ae754SRob Clark #define REG_A5XX_PC_HS_PARAM 0x0000e38f 2891a26ae754SRob Clark 2892a26ae754SRob Clark #define REG_A5XX_PC_POWER_CNTL 0x0000e3b0 2893a26ae754SRob Clark 2894a26ae754SRob Clark #define REG_A5XX_VFD_CONTROL_0 0x0000e400 2895a26ae754SRob Clark #define A5XX_VFD_CONTROL_0_VTXCNT__MASK 0x0000003f 2896a26ae754SRob Clark #define A5XX_VFD_CONTROL_0_VTXCNT__SHIFT 0 2897a26ae754SRob Clark static inline uint32_t A5XX_VFD_CONTROL_0_VTXCNT(uint32_t val) 2898a26ae754SRob Clark { 2899a26ae754SRob Clark return ((val) << A5XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A5XX_VFD_CONTROL_0_VTXCNT__MASK; 2900a26ae754SRob Clark } 2901a26ae754SRob Clark 2902a26ae754SRob Clark #define REG_A5XX_VFD_CONTROL_1 0x0000e401 2903a26ae754SRob Clark #define A5XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00 2904a26ae754SRob Clark #define A5XX_VFD_CONTROL_1_REGID4INST__SHIFT 8 2905a26ae754SRob Clark static inline uint32_t A5XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 2906a26ae754SRob Clark { 2907a26ae754SRob Clark return ((val) << A5XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A5XX_VFD_CONTROL_1_REGID4INST__MASK; 2908a26ae754SRob Clark } 2909a26ae754SRob Clark #define A5XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000 2910a26ae754SRob Clark #define A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16 2911a26ae754SRob Clark static inline uint32_t A5XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 2912a26ae754SRob Clark { 2913a26ae754SRob Clark return ((val) << A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A5XX_VFD_CONTROL_1_REGID4VTX__MASK; 2914a26ae754SRob Clark } 2915a26ae754SRob Clark 2916a26ae754SRob Clark #define REG_A5XX_VFD_CONTROL_2 0x0000e402 2917a26ae754SRob Clark 2918a26ae754SRob Clark #define REG_A5XX_VFD_CONTROL_3 0x0000e403 2919a26ae754SRob Clark 2920a26ae754SRob Clark #define REG_A5XX_VFD_CONTROL_4 0x0000e404 2921a26ae754SRob Clark 2922a26ae754SRob Clark #define REG_A5XX_VFD_CONTROL_5 0x0000e405 2923a26ae754SRob Clark 2924a26ae754SRob Clark #define REG_A5XX_VFD_INDEX_OFFSET 0x0000e408 2925a26ae754SRob Clark 2926a26ae754SRob Clark #define REG_A5XX_VFD_INSTANCE_START_OFFSET 0x0000e409 2927a26ae754SRob Clark 2928a26ae754SRob Clark static inline uint32_t REG_A5XX_VFD_FETCH(uint32_t i0) { return 0x0000e40a + 0x4*i0; } 2929a26ae754SRob Clark 2930a26ae754SRob Clark static inline uint32_t REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000e40a + 0x4*i0; } 2931a26ae754SRob Clark 2932a26ae754SRob Clark static inline uint32_t REG_A5XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000e40b + 0x4*i0; } 2933a26ae754SRob Clark 2934a26ae754SRob Clark static inline uint32_t REG_A5XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000e40c + 0x4*i0; } 2935a26ae754SRob Clark 2936a26ae754SRob Clark static inline uint32_t REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000e40d + 0x4*i0; } 2937a26ae754SRob Clark 2938a26ae754SRob Clark static inline uint32_t REG_A5XX_VFD_DECODE(uint32_t i0) { return 0x0000e48a + 0x2*i0; } 2939a26ae754SRob Clark 2940a26ae754SRob Clark static inline uint32_t REG_A5XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000e48a + 0x2*i0; } 2941a26ae754SRob Clark #define A5XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f 2942a26ae754SRob Clark #define A5XX_VFD_DECODE_INSTR_IDX__SHIFT 0 2943a26ae754SRob Clark static inline uint32_t A5XX_VFD_DECODE_INSTR_IDX(uint32_t val) 2944a26ae754SRob Clark { 2945a26ae754SRob Clark return ((val) << A5XX_VFD_DECODE_INSTR_IDX__SHIFT) & A5XX_VFD_DECODE_INSTR_IDX__MASK; 2946a26ae754SRob Clark } 2947a26ae754SRob Clark #define A5XX_VFD_DECODE_INSTR_FORMAT__MASK 0x3ff00000 2948a26ae754SRob Clark #define A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20 2949a26ae754SRob Clark static inline uint32_t A5XX_VFD_DECODE_INSTR_FORMAT(enum a5xx_vtx_fmt val) 2950a26ae754SRob Clark { 2951a26ae754SRob Clark return ((val) << A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A5XX_VFD_DECODE_INSTR_FORMAT__MASK; 2952a26ae754SRob Clark } 2953a26ae754SRob Clark #define A5XX_VFD_DECODE_INSTR_SWAP__MASK 0xc0000000 2954a26ae754SRob Clark #define A5XX_VFD_DECODE_INSTR_SWAP__SHIFT 30 2955a26ae754SRob Clark static inline uint32_t A5XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 2956a26ae754SRob Clark { 2957a26ae754SRob Clark return ((val) << A5XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A5XX_VFD_DECODE_INSTR_SWAP__MASK; 2958a26ae754SRob Clark } 2959a26ae754SRob Clark 2960a26ae754SRob Clark static inline uint32_t REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000e48b + 0x2*i0; } 2961a26ae754SRob Clark 2962a26ae754SRob Clark static inline uint32_t REG_A5XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000e4ca + 0x1*i0; } 2963a26ae754SRob Clark 2964a26ae754SRob Clark static inline uint32_t REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000e4ca + 0x1*i0; } 2965a26ae754SRob Clark #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f 2966a26ae754SRob Clark #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0 2967a26ae754SRob Clark static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val) 2968a26ae754SRob Clark { 2969a26ae754SRob Clark return ((val) << A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK; 2970a26ae754SRob Clark } 2971a26ae754SRob Clark #define A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0 2972a26ae754SRob Clark #define A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4 2973a26ae754SRob Clark static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) 2974a26ae754SRob Clark { 2975a26ae754SRob Clark return ((val) << A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK; 2976a26ae754SRob Clark } 2977a26ae754SRob Clark 2978a26ae754SRob Clark #define REG_A5XX_VFD_POWER_CNTL 0x0000e4f0 2979a26ae754SRob Clark 2980a26ae754SRob Clark #define REG_A5XX_SP_SP_CNTL 0x0000e580 2981a26ae754SRob Clark 2982a26ae754SRob Clark #define REG_A5XX_SP_VS_CONTROL_REG 0x0000e584 2983a26ae754SRob Clark #define A5XX_SP_VS_CONTROL_REG_ENABLED 0x00000001 2984a26ae754SRob Clark #define A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe 2985a26ae754SRob Clark #define A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 2986a26ae754SRob Clark static inline uint32_t A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 2987a26ae754SRob Clark { 2988a26ae754SRob Clark return ((val) << A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 2989a26ae754SRob Clark } 2990a26ae754SRob Clark #define A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 2991a26ae754SRob Clark #define A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 2992a26ae754SRob Clark static inline uint32_t A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 2993a26ae754SRob Clark { 2994a26ae754SRob Clark return ((val) << A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET__MASK; 2995a26ae754SRob Clark } 2996a26ae754SRob Clark 2997a26ae754SRob Clark #define REG_A5XX_SP_FS_CONTROL_REG 0x0000e585 2998a26ae754SRob Clark #define A5XX_SP_FS_CONTROL_REG_ENABLED 0x00000001 2999a26ae754SRob Clark #define A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe 3000a26ae754SRob Clark #define A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 3001a26ae754SRob Clark static inline uint32_t A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3002a26ae754SRob Clark { 3003a26ae754SRob Clark return ((val) << A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3004a26ae754SRob Clark } 3005a26ae754SRob Clark #define A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 3006a26ae754SRob Clark #define A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 3007a26ae754SRob Clark static inline uint32_t A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3008a26ae754SRob Clark { 3009a26ae754SRob Clark return ((val) << A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3010a26ae754SRob Clark } 3011a26ae754SRob Clark 3012a26ae754SRob Clark #define REG_A5XX_SP_HS_CONTROL_REG 0x0000e586 3013a26ae754SRob Clark #define A5XX_SP_HS_CONTROL_REG_ENABLED 0x00000001 3014a26ae754SRob Clark #define A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe 3015a26ae754SRob Clark #define A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 3016a26ae754SRob Clark static inline uint32_t A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3017a26ae754SRob Clark { 3018a26ae754SRob Clark return ((val) << A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3019a26ae754SRob Clark } 3020a26ae754SRob Clark #define A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 3021a26ae754SRob Clark #define A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 3022a26ae754SRob Clark static inline uint32_t A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3023a26ae754SRob Clark { 3024a26ae754SRob Clark return ((val) << A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3025a26ae754SRob Clark } 3026a26ae754SRob Clark 3027a26ae754SRob Clark #define REG_A5XX_SP_DS_CONTROL_REG 0x0000e587 3028a26ae754SRob Clark #define A5XX_SP_DS_CONTROL_REG_ENABLED 0x00000001 3029a26ae754SRob Clark #define A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe 3030a26ae754SRob Clark #define A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 3031a26ae754SRob Clark static inline uint32_t A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3032a26ae754SRob Clark { 3033a26ae754SRob Clark return ((val) << A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3034a26ae754SRob Clark } 3035a26ae754SRob Clark #define A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 3036a26ae754SRob Clark #define A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 3037a26ae754SRob Clark static inline uint32_t A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3038a26ae754SRob Clark { 3039a26ae754SRob Clark return ((val) << A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3040a26ae754SRob Clark } 3041a26ae754SRob Clark 3042a26ae754SRob Clark #define REG_A5XX_SP_GS_CONTROL_REG 0x0000e588 3043a26ae754SRob Clark #define A5XX_SP_GS_CONTROL_REG_ENABLED 0x00000001 3044a26ae754SRob Clark #define A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe 3045a26ae754SRob Clark #define A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 3046a26ae754SRob Clark static inline uint32_t A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3047a26ae754SRob Clark { 3048a26ae754SRob Clark return ((val) << A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3049a26ae754SRob Clark } 3050a26ae754SRob Clark #define A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 3051a26ae754SRob Clark #define A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 3052a26ae754SRob Clark static inline uint32_t A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3053a26ae754SRob Clark { 3054a26ae754SRob Clark return ((val) << A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3055a26ae754SRob Clark } 3056a26ae754SRob Clark 3057a26ae754SRob Clark #define REG_A5XX_SP_CS_CONFIG 0x0000e589 3058a26ae754SRob Clark 3059a26ae754SRob Clark #define REG_A5XX_SP_VS_CONFIG_MAX_CONST 0x0000e58a 3060a26ae754SRob Clark 3061a26ae754SRob Clark #define REG_A5XX_SP_FS_CONFIG_MAX_CONST 0x0000e58b 3062a26ae754SRob Clark 3063a26ae754SRob Clark #define REG_A5XX_SP_VS_CTRL_REG0 0x0000e590 3064a26ae754SRob Clark #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 3065a26ae754SRob Clark #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 3066a26ae754SRob Clark static inline uint32_t A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 3067a26ae754SRob Clark { 3068a26ae754SRob Clark return ((val) << A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 3069a26ae754SRob Clark } 3070a26ae754SRob Clark #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 3071a26ae754SRob Clark #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 3072a26ae754SRob Clark static inline uint32_t A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 3073a26ae754SRob Clark { 3074a26ae754SRob Clark return ((val) << A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 3075a26ae754SRob Clark } 3076a26ae754SRob Clark #define A5XX_SP_VS_CTRL_REG0_VARYING 0x00010000 3077a26ae754SRob Clark #define A5XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00100000 3078a26ae754SRob Clark 3079a26ae754SRob Clark #define REG_A5XX_SP_PRIMITIVE_CNTL 0x0000e592 3080a26ae754SRob Clark #define A5XX_SP_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK 0x0000001f 3081a26ae754SRob Clark #define A5XX_SP_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT 0 3082a26ae754SRob Clark static inline uint32_t A5XX_SP_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val) 3083a26ae754SRob Clark { 3084a26ae754SRob Clark return ((val >> 2) << A5XX_SP_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT) & A5XX_SP_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK; 3085a26ae754SRob Clark } 3086a26ae754SRob Clark 3087a26ae754SRob Clark static inline uint32_t REG_A5XX_SP_VS_OUT(uint32_t i0) { return 0x0000e593 + 0x1*i0; } 3088a26ae754SRob Clark 3089a26ae754SRob Clark static inline uint32_t REG_A5XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000e593 + 0x1*i0; } 3090a26ae754SRob Clark #define A5XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff 3091a26ae754SRob Clark #define A5XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 3092a26ae754SRob Clark static inline uint32_t A5XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 3093a26ae754SRob Clark { 3094a26ae754SRob Clark return ((val) << A5XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_A_REGID__MASK; 3095a26ae754SRob Clark } 3096a26ae754SRob Clark #define A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00 3097a26ae754SRob Clark #define A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8 3098a26ae754SRob Clark static inline uint32_t A5XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 3099a26ae754SRob Clark { 3100a26ae754SRob Clark return ((val) << A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 3101a26ae754SRob Clark } 3102a26ae754SRob Clark #define A5XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000 3103a26ae754SRob Clark #define A5XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 3104a26ae754SRob Clark static inline uint32_t A5XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 3105a26ae754SRob Clark { 3106a26ae754SRob Clark return ((val) << A5XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_B_REGID__MASK; 3107a26ae754SRob Clark } 3108a26ae754SRob Clark #define A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000 3109a26ae754SRob Clark #define A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24 3110a26ae754SRob Clark static inline uint32_t A5XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 3111a26ae754SRob Clark { 3112a26ae754SRob Clark return ((val) << A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 3113a26ae754SRob Clark } 3114a26ae754SRob Clark 3115a26ae754SRob Clark static inline uint32_t REG_A5XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; } 3116a26ae754SRob Clark 3117a26ae754SRob Clark static inline uint32_t REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; } 3118a26ae754SRob Clark #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 3119a26ae754SRob Clark #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 3120a26ae754SRob Clark static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 3121a26ae754SRob Clark { 3122a26ae754SRob Clark return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 3123a26ae754SRob Clark } 3124a26ae754SRob Clark #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 3125a26ae754SRob Clark #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 3126a26ae754SRob Clark static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 3127a26ae754SRob Clark { 3128a26ae754SRob Clark return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 3129a26ae754SRob Clark } 3130a26ae754SRob Clark #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 3131a26ae754SRob Clark #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 3132a26ae754SRob Clark static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 3133a26ae754SRob Clark { 3134a26ae754SRob Clark return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 3135a26ae754SRob Clark } 3136a26ae754SRob Clark #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 3137a26ae754SRob Clark #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 3138a26ae754SRob Clark static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 3139a26ae754SRob Clark { 3140a26ae754SRob Clark return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 3141a26ae754SRob Clark } 3142a26ae754SRob Clark 3143a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E5AB 0x0000e5ab 3144a26ae754SRob Clark 3145a26ae754SRob Clark #define REG_A5XX_SP_VS_OBJ_START_LO 0x0000e5ac 3146a26ae754SRob Clark 3147a26ae754SRob Clark #define REG_A5XX_SP_VS_OBJ_START_HI 0x0000e5ad 3148a26ae754SRob Clark 3149a26ae754SRob Clark #define REG_A5XX_SP_FS_CTRL_REG0 0x0000e5c0 3150a26ae754SRob Clark #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 3151a26ae754SRob Clark #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 3152a26ae754SRob Clark static inline uint32_t A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 3153a26ae754SRob Clark { 3154a26ae754SRob Clark return ((val) << A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 3155a26ae754SRob Clark } 3156a26ae754SRob Clark #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 3157a26ae754SRob Clark #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 3158a26ae754SRob Clark static inline uint32_t A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 3159a26ae754SRob Clark { 3160a26ae754SRob Clark return ((val) << A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 3161a26ae754SRob Clark } 3162a26ae754SRob Clark #define A5XX_SP_FS_CTRL_REG0_VARYING 0x00010000 3163a26ae754SRob Clark #define A5XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00100000 3164a26ae754SRob Clark 3165a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E5C2 0x0000e5c2 3166a26ae754SRob Clark 3167a26ae754SRob Clark #define REG_A5XX_SP_FS_OBJ_START_LO 0x0000e5c3 3168a26ae754SRob Clark 3169a26ae754SRob Clark #define REG_A5XX_SP_FS_OBJ_START_HI 0x0000e5c4 3170a26ae754SRob Clark 3171a26ae754SRob Clark #define REG_A5XX_SP_BLEND_CNTL 0x0000e5c9 3172a26ae754SRob Clark 3173a26ae754SRob Clark #define REG_A5XX_SP_FS_OUTPUT_CNTL 0x0000e5ca 3174a26ae754SRob Clark #define A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f 3175a26ae754SRob Clark #define A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT 0 3176a26ae754SRob Clark static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_MRT(uint32_t val) 3177a26ae754SRob Clark { 3178a26ae754SRob Clark return ((val) << A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK; 3179a26ae754SRob Clark } 3180a26ae754SRob Clark #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK 0x00001fe0 3181a26ae754SRob Clark #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT 5 3182a26ae754SRob Clark static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(uint32_t val) 3183a26ae754SRob Clark { 3184a26ae754SRob Clark return ((val) << A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK; 3185a26ae754SRob Clark } 3186a26ae754SRob Clark #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK 0x001fe000 3187a26ae754SRob Clark #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT 13 3188a26ae754SRob Clark static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(uint32_t val) 3189a26ae754SRob Clark { 3190a26ae754SRob Clark return ((val) << A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK; 3191a26ae754SRob Clark } 3192a26ae754SRob Clark 3193a26ae754SRob Clark static inline uint32_t REG_A5XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000e5cb + 0x1*i0; } 3194a26ae754SRob Clark 3195a26ae754SRob Clark static inline uint32_t REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000e5cb + 0x1*i0; } 3196a26ae754SRob Clark #define A5XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff 3197a26ae754SRob Clark #define A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0 3198a26ae754SRob Clark static inline uint32_t A5XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) 3199a26ae754SRob Clark { 3200a26ae754SRob Clark return ((val) << A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_REG_REGID__MASK; 3201a26ae754SRob Clark } 3202a26ae754SRob Clark #define A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100 3203a26ae754SRob Clark 3204a26ae754SRob Clark static inline uint32_t REG_A5XX_SP_FS_MRT(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; } 3205a26ae754SRob Clark 3206a26ae754SRob Clark static inline uint32_t REG_A5XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; } 3207a26ae754SRob Clark #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff 3208a26ae754SRob Clark #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0 3209a26ae754SRob Clark static inline uint32_t A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val) 3210a26ae754SRob Clark { 3211a26ae754SRob Clark return ((val) << A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK; 3212a26ae754SRob Clark } 3213a26ae754SRob Clark 3214a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E5DB 0x0000e5db 3215a26ae754SRob Clark 3216a26ae754SRob Clark #define REG_A5XX_SP_CS_CNTL_0 0x0000e5f0 3217a26ae754SRob Clark 3218a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E600 0x0000e600 3219a26ae754SRob Clark 3220a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E640 0x0000e640 3221a26ae754SRob Clark 3222a26ae754SRob Clark #define REG_A5XX_TPL1_TP_RAS_MSAA_CNTL 0x0000e704 3223a26ae754SRob Clark #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 3224a26ae754SRob Clark #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 3225a26ae754SRob Clark static inline uint32_t A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 3226a26ae754SRob Clark { 3227a26ae754SRob Clark return ((val) << A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK; 3228a26ae754SRob Clark } 3229a26ae754SRob Clark 3230a26ae754SRob Clark #define REG_A5XX_TPL1_TP_DEST_MSAA_CNTL 0x0000e705 3231a26ae754SRob Clark #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 3232a26ae754SRob Clark #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 3233a26ae754SRob Clark static inline uint32_t A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) 3234a26ae754SRob Clark { 3235a26ae754SRob Clark return ((val) << A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK; 3236a26ae754SRob Clark } 3237a26ae754SRob Clark #define A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 3238a26ae754SRob Clark 3239a26ae754SRob Clark #define REG_A5XX_TPL1_VS_TEX_COUNT 0x0000e700 3240a26ae754SRob Clark 3241a26ae754SRob Clark #define REG_A5XX_TPL1_VS_TEX_SAMP_LO 0x0000e722 3242a26ae754SRob Clark 3243a26ae754SRob Clark #define REG_A5XX_TPL1_VS_TEX_SAMP_HI 0x0000e723 3244a26ae754SRob Clark 3245a26ae754SRob Clark #define REG_A5XX_TPL1_VS_TEX_CONST_LO 0x0000e72a 3246a26ae754SRob Clark 3247a26ae754SRob Clark #define REG_A5XX_TPL1_VS_TEX_CONST_HI 0x0000e72b 3248a26ae754SRob Clark 3249a26ae754SRob Clark #define REG_A5XX_TPL1_FS_TEX_COUNT 0x0000e750 3250a26ae754SRob Clark 3251a26ae754SRob Clark #define REG_A5XX_TPL1_FS_TEX_SAMP_LO 0x0000e75a 3252a26ae754SRob Clark 3253a26ae754SRob Clark #define REG_A5XX_TPL1_FS_TEX_SAMP_HI 0x0000e75b 3254a26ae754SRob Clark 3255a26ae754SRob Clark #define REG_A5XX_TPL1_FS_TEX_CONST_LO 0x0000e75e 3256a26ae754SRob Clark 3257a26ae754SRob Clark #define REG_A5XX_TPL1_FS_TEX_CONST_HI 0x0000e75f 3258a26ae754SRob Clark 3259a26ae754SRob Clark #define REG_A5XX_TPL1_TP_FS_ROTATION_CNTL 0x0000e764 3260a26ae754SRob Clark 3261a26ae754SRob Clark #define REG_A5XX_HLSQ_CONTROL_0_REG 0x0000e784 3262a26ae754SRob Clark 3263a26ae754SRob Clark #define REG_A5XX_HLSQ_CONTROL_1_REG 0x0000e785 3264a26ae754SRob Clark #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x0000003f 3265a26ae754SRob Clark #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT 0 3266a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val) 3267a26ae754SRob Clark { 3268a26ae754SRob Clark return ((val) << A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK; 3269a26ae754SRob Clark } 3270a26ae754SRob Clark 3271a26ae754SRob Clark #define REG_A5XX_HLSQ_CONTROL_2_REG 0x0000e786 3272a26ae754SRob Clark #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff 3273a26ae754SRob Clark #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0 3274a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) 3275a26ae754SRob Clark { 3276a26ae754SRob Clark return ((val) << A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; 3277a26ae754SRob Clark } 3278a26ae754SRob Clark 3279a26ae754SRob Clark #define REG_A5XX_HLSQ_CONTROL_3_REG 0x0000e787 3280a26ae754SRob Clark #define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK 0x000000ff 3281a26ae754SRob Clark #define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT 0 3282a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val) 3283a26ae754SRob Clark { 3284a26ae754SRob Clark return ((val) << A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK; 3285a26ae754SRob Clark } 3286a26ae754SRob Clark 3287a26ae754SRob Clark #define REG_A5XX_HLSQ_CONTROL_4_REG 0x0000e788 3288a26ae754SRob Clark #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000 3289a26ae754SRob Clark #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16 3290a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) 3291a26ae754SRob Clark { 3292a26ae754SRob Clark return ((val) << A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK; 3293a26ae754SRob Clark } 3294a26ae754SRob Clark #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000 3295a26ae754SRob Clark #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24 3296a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) 3297a26ae754SRob Clark { 3298a26ae754SRob Clark return ((val) << A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; 3299a26ae754SRob Clark } 3300a26ae754SRob Clark 3301a26ae754SRob Clark #define REG_A5XX_HLSQ_UPDATE_CNTL 0x0000e78a 3302a26ae754SRob Clark 3303a26ae754SRob Clark #define REG_A5XX_HLSQ_VS_CONTROL_REG 0x0000e78b 3304a26ae754SRob Clark #define A5XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00000001 3305a26ae754SRob Clark #define A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe 3306a26ae754SRob Clark #define A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 3307a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3308a26ae754SRob Clark { 3309a26ae754SRob Clark return ((val) << A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3310a26ae754SRob Clark } 3311a26ae754SRob Clark #define A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 3312a26ae754SRob Clark #define A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 3313a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3314a26ae754SRob Clark { 3315a26ae754SRob Clark return ((val) << A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3316a26ae754SRob Clark } 3317a26ae754SRob Clark 3318a26ae754SRob Clark #define REG_A5XX_HLSQ_FS_CONTROL_REG 0x0000e78c 3319a26ae754SRob Clark #define A5XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00000001 3320a26ae754SRob Clark #define A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe 3321a26ae754SRob Clark #define A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 3322a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3323a26ae754SRob Clark { 3324a26ae754SRob Clark return ((val) << A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3325a26ae754SRob Clark } 3326a26ae754SRob Clark #define A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 3327a26ae754SRob Clark #define A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 3328a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3329a26ae754SRob Clark { 3330a26ae754SRob Clark return ((val) << A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3331a26ae754SRob Clark } 3332a26ae754SRob Clark 3333a26ae754SRob Clark #define REG_A5XX_HLSQ_HS_CONTROL_REG 0x0000e78d 3334a26ae754SRob Clark #define A5XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00000001 3335a26ae754SRob Clark #define A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe 3336a26ae754SRob Clark #define A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 3337a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3338a26ae754SRob Clark { 3339a26ae754SRob Clark return ((val) << A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3340a26ae754SRob Clark } 3341a26ae754SRob Clark #define A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 3342a26ae754SRob Clark #define A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 3343a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3344a26ae754SRob Clark { 3345a26ae754SRob Clark return ((val) << A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3346a26ae754SRob Clark } 3347a26ae754SRob Clark 3348a26ae754SRob Clark #define REG_A5XX_HLSQ_DS_CONTROL_REG 0x0000e78e 3349a26ae754SRob Clark #define A5XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00000001 3350a26ae754SRob Clark #define A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe 3351a26ae754SRob Clark #define A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 3352a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3353a26ae754SRob Clark { 3354a26ae754SRob Clark return ((val) << A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3355a26ae754SRob Clark } 3356a26ae754SRob Clark #define A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 3357a26ae754SRob Clark #define A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 3358a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3359a26ae754SRob Clark { 3360a26ae754SRob Clark return ((val) << A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3361a26ae754SRob Clark } 3362a26ae754SRob Clark 3363a26ae754SRob Clark #define REG_A5XX_HLSQ_GS_CONTROL_REG 0x0000e78f 3364a26ae754SRob Clark #define A5XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00000001 3365a26ae754SRob Clark #define A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe 3366a26ae754SRob Clark #define A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1 3367a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3368a26ae754SRob Clark { 3369a26ae754SRob Clark return ((val) << A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3370a26ae754SRob Clark } 3371a26ae754SRob Clark #define A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00 3372a26ae754SRob Clark #define A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8 3373a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3374a26ae754SRob Clark { 3375a26ae754SRob Clark return ((val) << A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3376a26ae754SRob Clark } 3377a26ae754SRob Clark 3378a26ae754SRob Clark #define REG_A5XX_HLSQ_CS_CONFIG 0x0000e790 3379a26ae754SRob Clark 3380a26ae754SRob Clark #define REG_A5XX_HLSQ_VS_CNTL 0x0000e791 3381a26ae754SRob Clark #define A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK 0xfffffffe 3382a26ae754SRob Clark #define A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT 1 3383a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_VS_CNTL_INSTRLEN(uint32_t val) 3384a26ae754SRob Clark { 3385a26ae754SRob Clark return ((val) << A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK; 3386a26ae754SRob Clark } 3387a26ae754SRob Clark 3388a26ae754SRob Clark #define REG_A5XX_HLSQ_FS_CNTL 0x0000e792 3389a26ae754SRob Clark #define A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK 0xfffffffe 3390a26ae754SRob Clark #define A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT 1 3391a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_FS_CNTL_INSTRLEN(uint32_t val) 3392a26ae754SRob Clark { 3393a26ae754SRob Clark return ((val) << A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK; 3394a26ae754SRob Clark } 3395a26ae754SRob Clark 3396a26ae754SRob Clark #define REG_A5XX_HLSQ_HS_CNTL 0x0000e793 3397a26ae754SRob Clark #define A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK 0xfffffffe 3398a26ae754SRob Clark #define A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT 1 3399a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_HS_CNTL_INSTRLEN(uint32_t val) 3400a26ae754SRob Clark { 3401a26ae754SRob Clark return ((val) << A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK; 3402a26ae754SRob Clark } 3403a26ae754SRob Clark 3404a26ae754SRob Clark #define REG_A5XX_HLSQ_DS_CNTL 0x0000e794 3405a26ae754SRob Clark #define A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK 0xfffffffe 3406a26ae754SRob Clark #define A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT 1 3407a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_DS_CNTL_INSTRLEN(uint32_t val) 3408a26ae754SRob Clark { 3409a26ae754SRob Clark return ((val) << A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK; 3410a26ae754SRob Clark } 3411a26ae754SRob Clark 3412a26ae754SRob Clark #define REG_A5XX_HLSQ_GS_CNTL 0x0000e795 3413a26ae754SRob Clark #define A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK 0xfffffffe 3414a26ae754SRob Clark #define A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT 1 3415a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_GS_CNTL_INSTRLEN(uint32_t val) 3416a26ae754SRob Clark { 3417a26ae754SRob Clark return ((val) << A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK; 3418a26ae754SRob Clark } 3419a26ae754SRob Clark 3420a26ae754SRob Clark #define REG_A5XX_HLSQ_CS_CNTL 0x0000e796 3421a26ae754SRob Clark #define A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK 0xfffffffe 3422a26ae754SRob Clark #define A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT 1 3423a26ae754SRob Clark static inline uint32_t A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val) 3424a26ae754SRob Clark { 3425a26ae754SRob Clark return ((val) << A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK; 3426a26ae754SRob Clark } 3427a26ae754SRob Clark 3428a26ae754SRob Clark #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_X 0x0000e7b9 3429a26ae754SRob Clark 3430a26ae754SRob Clark #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000e7ba 3431a26ae754SRob Clark 3432a26ae754SRob Clark #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000e7bb 3433a26ae754SRob Clark 3434a26ae754SRob Clark #define REG_A5XX_HLSQ_CS_NDRANGE_0 0x0000e7b0 3435a26ae754SRob Clark 3436a26ae754SRob Clark #define REG_A5XX_HLSQ_CS_NDRANGE_1 0x0000e7b1 3437a26ae754SRob Clark 3438a26ae754SRob Clark #define REG_A5XX_HLSQ_CS_NDRANGE_2 0x0000e7b2 3439a26ae754SRob Clark 3440a26ae754SRob Clark #define REG_A5XX_HLSQ_CS_NDRANGE_3 0x0000e7b3 3441a26ae754SRob Clark 3442a26ae754SRob Clark #define REG_A5XX_HLSQ_CS_NDRANGE_4 0x0000e7b4 3443a26ae754SRob Clark 3444a26ae754SRob Clark #define REG_A5XX_HLSQ_CS_NDRANGE_5 0x0000e7b5 3445a26ae754SRob Clark 3446a26ae754SRob Clark #define REG_A5XX_HLSQ_CS_NDRANGE_6 0x0000e7b6 3447a26ae754SRob Clark 3448a26ae754SRob Clark #define REG_A5XX_HLSQ_CS_CNTL_0 0x0000e7b7 3449a26ae754SRob Clark 3450a26ae754SRob Clark #define REG_A5XX_HLSQ_CS_CNTL_1 0x0000e7b8 3451a26ae754SRob Clark 3452a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E7C0 0x0000e7c0 3453a26ae754SRob Clark 3454a26ae754SRob Clark #define REG_A5XX_HLSQ_VS_CONSTLEN 0x0000e7c3 3455a26ae754SRob Clark 3456a26ae754SRob Clark #define REG_A5XX_HLSQ_VS_INSTRLEN 0x0000e7c4 3457a26ae754SRob Clark 3458a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E7C5 0x0000e7c5 3459a26ae754SRob Clark 3460a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E7CA 0x0000e7ca 3461a26ae754SRob Clark 3462a26ae754SRob Clark #define REG_A5XX_HLSQ_FS_CONSTLEN 0x0000e7d7 3463a26ae754SRob Clark 3464a26ae754SRob Clark #define REG_A5XX_HLSQ_FS_INSTRLEN 0x0000e7d8 3465a26ae754SRob Clark 3466a26ae754SRob Clark #define REG_A5XX_HLSQ_HS_CONSTLEN 0x0000e7c8 3467a26ae754SRob Clark 3468a26ae754SRob Clark #define REG_A5XX_HLSQ_HS_INSTRLEN 0x0000e7c9 3469a26ae754SRob Clark 3470a26ae754SRob Clark #define REG_A5XX_HLSQ_DS_CONSTLEN 0x0000e7cd 3471a26ae754SRob Clark 3472a26ae754SRob Clark #define REG_A5XX_HLSQ_DS_INSTRLEN 0x0000e7ce 3473a26ae754SRob Clark 3474a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E7CF 0x0000e7cf 3475a26ae754SRob Clark 3476a26ae754SRob Clark #define REG_A5XX_HLSQ_GS_CONSTLEN 0x0000e7d2 3477a26ae754SRob Clark 3478a26ae754SRob Clark #define REG_A5XX_HLSQ_GS_INSTRLEN 0x0000e7d3 3479a26ae754SRob Clark 3480a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E7D4 0x0000e7d4 3481a26ae754SRob Clark 3482a26ae754SRob Clark #define REG_A5XX_UNKNOWN_E7D9 0x0000e7d9 3483a26ae754SRob Clark 3484a26ae754SRob Clark #define REG_A5XX_HLSQ_CONTEXT_SWITCH_CS_SW_3 0x0000e7dc 3485a26ae754SRob Clark 3486a26ae754SRob Clark #define REG_A5XX_HLSQ_CONTEXT_SWITCH_CS_SW_4 0x0000e7dd 3487a26ae754SRob Clark 3488a26ae754SRob Clark #define REG_A5XX_RB_2D_DST_FILL 0x00002101 3489a26ae754SRob Clark 3490a26ae754SRob Clark #define REG_A5XX_RB_2D_SRC_INFO 0x00002107 3491a26ae754SRob Clark #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff 3492a26ae754SRob Clark #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 3493a26ae754SRob Clark static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) 3494a26ae754SRob Clark { 3495a26ae754SRob Clark return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK; 3496a26ae754SRob Clark } 3497a26ae754SRob Clark #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00 3498a26ae754SRob Clark #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT 10 3499a26ae754SRob Clark static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) 3500a26ae754SRob Clark { 3501a26ae754SRob Clark return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK; 3502a26ae754SRob Clark } 3503a26ae754SRob Clark 3504a26ae754SRob Clark #define REG_A5XX_RB_2D_SRC_LO 0x00002108 3505a26ae754SRob Clark 3506a26ae754SRob Clark #define REG_A5XX_RB_2D_SRC_HI 0x00002109 3507a26ae754SRob Clark 3508a26ae754SRob Clark #define REG_A5XX_RB_2D_DST_INFO 0x00002110 3509a26ae754SRob Clark #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff 3510a26ae754SRob Clark #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0 3511a26ae754SRob Clark static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) 3512a26ae754SRob Clark { 3513a26ae754SRob Clark return ((val) << A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK; 3514a26ae754SRob Clark } 3515a26ae754SRob Clark #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00 3516a26ae754SRob Clark #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10 3517a26ae754SRob Clark static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) 3518a26ae754SRob Clark { 3519a26ae754SRob Clark return ((val) << A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK; 3520a26ae754SRob Clark } 3521a26ae754SRob Clark 3522a26ae754SRob Clark #define REG_A5XX_RB_2D_SRC_FLAGS_LO 0x00002140 3523a26ae754SRob Clark 3524a26ae754SRob Clark #define REG_A5XX_RB_2D_SRC_FLAGS_HI 0x00002141 3525a26ae754SRob Clark 3526a26ae754SRob Clark #define REG_A5XX_RB_2D_DST_LO 0x00002111 3527a26ae754SRob Clark 3528a26ae754SRob Clark #define REG_A5XX_RB_2D_DST_HI 0x00002112 3529a26ae754SRob Clark 3530a26ae754SRob Clark #define REG_A5XX_RB_2D_DST_FLAGS_LO 0x00002143 3531a26ae754SRob Clark 3532a26ae754SRob Clark #define REG_A5XX_RB_2D_DST_FLAGS_HI 0x00002144 3533a26ae754SRob Clark 3534a26ae754SRob Clark #define REG_A5XX_GRAS_2D_SRC_INFO 0x00002181 3535a26ae754SRob Clark #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff 3536a26ae754SRob Clark #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 3537a26ae754SRob Clark static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) 3538a26ae754SRob Clark { 3539a26ae754SRob Clark return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK; 3540a26ae754SRob Clark } 3541a26ae754SRob Clark #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00 3542a26ae754SRob Clark #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10 3543a26ae754SRob Clark static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) 3544a26ae754SRob Clark { 3545a26ae754SRob Clark return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK; 3546a26ae754SRob Clark } 3547a26ae754SRob Clark 3548a26ae754SRob Clark #define REG_A5XX_GRAS_2D_DST_INFO 0x00002182 3549a26ae754SRob Clark #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff 3550a26ae754SRob Clark #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT 0 3551a26ae754SRob Clark static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val) 3552a26ae754SRob Clark { 3553a26ae754SRob Clark return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK; 3554a26ae754SRob Clark } 3555a26ae754SRob Clark #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00 3556a26ae754SRob Clark #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT 10 3557a26ae754SRob Clark static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) 3558a26ae754SRob Clark { 3559a26ae754SRob Clark return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK; 3560a26ae754SRob Clark } 3561a26ae754SRob Clark 3562a26ae754SRob Clark #define REG_A5XX_TEX_SAMP_0 0x00000000 3563a26ae754SRob Clark #define A5XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 3564a26ae754SRob Clark #define A5XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 3565a26ae754SRob Clark #define A5XX_TEX_SAMP_0_XY_MAG__SHIFT 1 3566a26ae754SRob Clark static inline uint32_t A5XX_TEX_SAMP_0_XY_MAG(enum a5xx_tex_filter val) 3567a26ae754SRob Clark { 3568a26ae754SRob Clark return ((val) << A5XX_TEX_SAMP_0_XY_MAG__SHIFT) & A5XX_TEX_SAMP_0_XY_MAG__MASK; 3569a26ae754SRob Clark } 3570a26ae754SRob Clark #define A5XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 3571a26ae754SRob Clark #define A5XX_TEX_SAMP_0_XY_MIN__SHIFT 3 3572a26ae754SRob Clark static inline uint32_t A5XX_TEX_SAMP_0_XY_MIN(enum a5xx_tex_filter val) 3573a26ae754SRob Clark { 3574a26ae754SRob Clark return ((val) << A5XX_TEX_SAMP_0_XY_MIN__SHIFT) & A5XX_TEX_SAMP_0_XY_MIN__MASK; 3575a26ae754SRob Clark } 3576a26ae754SRob Clark #define A5XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 3577a26ae754SRob Clark #define A5XX_TEX_SAMP_0_WRAP_S__SHIFT 5 3578a26ae754SRob Clark static inline uint32_t A5XX_TEX_SAMP_0_WRAP_S(enum a5xx_tex_clamp val) 3579a26ae754SRob Clark { 3580a26ae754SRob Clark return ((val) << A5XX_TEX_SAMP_0_WRAP_S__SHIFT) & A5XX_TEX_SAMP_0_WRAP_S__MASK; 3581a26ae754SRob Clark } 3582a26ae754SRob Clark #define A5XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 3583a26ae754SRob Clark #define A5XX_TEX_SAMP_0_WRAP_T__SHIFT 8 3584a26ae754SRob Clark static inline uint32_t A5XX_TEX_SAMP_0_WRAP_T(enum a5xx_tex_clamp val) 3585a26ae754SRob Clark { 3586a26ae754SRob Clark return ((val) << A5XX_TEX_SAMP_0_WRAP_T__SHIFT) & A5XX_TEX_SAMP_0_WRAP_T__MASK; 3587a26ae754SRob Clark } 3588a26ae754SRob Clark #define A5XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 3589a26ae754SRob Clark #define A5XX_TEX_SAMP_0_WRAP_R__SHIFT 11 3590a26ae754SRob Clark static inline uint32_t A5XX_TEX_SAMP_0_WRAP_R(enum a5xx_tex_clamp val) 3591a26ae754SRob Clark { 3592a26ae754SRob Clark return ((val) << A5XX_TEX_SAMP_0_WRAP_R__SHIFT) & A5XX_TEX_SAMP_0_WRAP_R__MASK; 3593a26ae754SRob Clark } 3594a26ae754SRob Clark #define A5XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 3595a26ae754SRob Clark #define A5XX_TEX_SAMP_0_ANISO__SHIFT 14 3596a26ae754SRob Clark static inline uint32_t A5XX_TEX_SAMP_0_ANISO(enum a5xx_tex_aniso val) 3597a26ae754SRob Clark { 3598a26ae754SRob Clark return ((val) << A5XX_TEX_SAMP_0_ANISO__SHIFT) & A5XX_TEX_SAMP_0_ANISO__MASK; 3599a26ae754SRob Clark } 3600a26ae754SRob Clark #define A5XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000 3601a26ae754SRob Clark #define A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19 3602a26ae754SRob Clark static inline uint32_t A5XX_TEX_SAMP_0_LOD_BIAS(float val) 3603a26ae754SRob Clark { 3604a26ae754SRob Clark return ((((int32_t)(val * 256.0))) << A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A5XX_TEX_SAMP_0_LOD_BIAS__MASK; 3605a26ae754SRob Clark } 3606a26ae754SRob Clark 3607a26ae754SRob Clark #define REG_A5XX_TEX_SAMP_1 0x00000001 3608a26ae754SRob Clark #define A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e 3609a26ae754SRob Clark #define A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 3610a26ae754SRob Clark static inline uint32_t A5XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) 3611a26ae754SRob Clark { 3612a26ae754SRob Clark return ((val) << A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK; 3613a26ae754SRob Clark } 3614a26ae754SRob Clark #define A5XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010 3615a26ae754SRob Clark #define A5XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 3616a26ae754SRob Clark #define A5XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 3617a26ae754SRob Clark #define A5XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 3618a26ae754SRob Clark #define A5XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 3619a26ae754SRob Clark static inline uint32_t A5XX_TEX_SAMP_1_MAX_LOD(float val) 3620a26ae754SRob Clark { 3621a26ae754SRob Clark return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A5XX_TEX_SAMP_1_MAX_LOD__MASK; 3622a26ae754SRob Clark } 3623a26ae754SRob Clark #define A5XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 3624a26ae754SRob Clark #define A5XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 3625a26ae754SRob Clark static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val) 3626a26ae754SRob Clark { 3627a26ae754SRob Clark return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A5XX_TEX_SAMP_1_MIN_LOD__MASK; 3628a26ae754SRob Clark } 3629a26ae754SRob Clark 3630a26ae754SRob Clark #define REG_A5XX_TEX_SAMP_2 0x00000002 3631a26ae754SRob Clark 3632a26ae754SRob Clark #define REG_A5XX_TEX_SAMP_3 0x00000003 3633a26ae754SRob Clark 3634a26ae754SRob Clark #define REG_A5XX_TEX_CONST_0 0x00000000 3635a26ae754SRob Clark #define A5XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003 3636a26ae754SRob Clark #define A5XX_TEX_CONST_0_TILE_MODE__SHIFT 0 3637a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_0_TILE_MODE(enum a5xx_tile_mode val) 3638a26ae754SRob Clark { 3639a26ae754SRob Clark return ((val) << A5XX_TEX_CONST_0_TILE_MODE__SHIFT) & A5XX_TEX_CONST_0_TILE_MODE__MASK; 3640a26ae754SRob Clark } 3641a26ae754SRob Clark #define A5XX_TEX_CONST_0_SRGB 0x00000004 3642a26ae754SRob Clark #define A5XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 3643a26ae754SRob Clark #define A5XX_TEX_CONST_0_SWIZ_X__SHIFT 4 3644a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_0_SWIZ_X(enum a5xx_tex_swiz val) 3645a26ae754SRob Clark { 3646a26ae754SRob Clark return ((val) << A5XX_TEX_CONST_0_SWIZ_X__SHIFT) & A5XX_TEX_CONST_0_SWIZ_X__MASK; 3647a26ae754SRob Clark } 3648a26ae754SRob Clark #define A5XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 3649a26ae754SRob Clark #define A5XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 3650a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Y(enum a5xx_tex_swiz val) 3651a26ae754SRob Clark { 3652a26ae754SRob Clark return ((val) << A5XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Y__MASK; 3653a26ae754SRob Clark } 3654a26ae754SRob Clark #define A5XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 3655a26ae754SRob Clark #define A5XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 3656a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Z(enum a5xx_tex_swiz val) 3657a26ae754SRob Clark { 3658a26ae754SRob Clark return ((val) << A5XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Z__MASK; 3659a26ae754SRob Clark } 3660a26ae754SRob Clark #define A5XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 3661a26ae754SRob Clark #define A5XX_TEX_CONST_0_SWIZ_W__SHIFT 13 3662a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_0_SWIZ_W(enum a5xx_tex_swiz val) 3663a26ae754SRob Clark { 3664a26ae754SRob Clark return ((val) << A5XX_TEX_CONST_0_SWIZ_W__SHIFT) & A5XX_TEX_CONST_0_SWIZ_W__MASK; 3665a26ae754SRob Clark } 3666a26ae754SRob Clark #define A5XX_TEX_CONST_0_FMT__MASK 0x3fc00000 3667a26ae754SRob Clark #define A5XX_TEX_CONST_0_FMT__SHIFT 22 3668a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_0_FMT(enum a5xx_tex_fmt val) 3669a26ae754SRob Clark { 3670a26ae754SRob Clark return ((val) << A5XX_TEX_CONST_0_FMT__SHIFT) & A5XX_TEX_CONST_0_FMT__MASK; 3671a26ae754SRob Clark } 3672a26ae754SRob Clark #define A5XX_TEX_CONST_0_SWAP__MASK 0xc0000000 3673a26ae754SRob Clark #define A5XX_TEX_CONST_0_SWAP__SHIFT 30 3674a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val) 3675a26ae754SRob Clark { 3676a26ae754SRob Clark return ((val) << A5XX_TEX_CONST_0_SWAP__SHIFT) & A5XX_TEX_CONST_0_SWAP__MASK; 3677a26ae754SRob Clark } 3678a26ae754SRob Clark 3679a26ae754SRob Clark #define REG_A5XX_TEX_CONST_1 0x00000001 3680a26ae754SRob Clark #define A5XX_TEX_CONST_1_WIDTH__MASK 0x00007fff 3681a26ae754SRob Clark #define A5XX_TEX_CONST_1_WIDTH__SHIFT 0 3682a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_1_WIDTH(uint32_t val) 3683a26ae754SRob Clark { 3684a26ae754SRob Clark return ((val) << A5XX_TEX_CONST_1_WIDTH__SHIFT) & A5XX_TEX_CONST_1_WIDTH__MASK; 3685a26ae754SRob Clark } 3686a26ae754SRob Clark #define A5XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000 3687a26ae754SRob Clark #define A5XX_TEX_CONST_1_HEIGHT__SHIFT 15 3688a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val) 3689a26ae754SRob Clark { 3690a26ae754SRob Clark return ((val) << A5XX_TEX_CONST_1_HEIGHT__SHIFT) & A5XX_TEX_CONST_1_HEIGHT__MASK; 3691a26ae754SRob Clark } 3692a26ae754SRob Clark 3693a26ae754SRob Clark #define REG_A5XX_TEX_CONST_2 0x00000002 3694a26ae754SRob Clark #define A5XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f 3695a26ae754SRob Clark #define A5XX_TEX_CONST_2_FETCHSIZE__SHIFT 0 3696a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_2_FETCHSIZE(enum a5xx_tex_fetchsize val) 3697a26ae754SRob Clark { 3698a26ae754SRob Clark return ((val) << A5XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A5XX_TEX_CONST_2_FETCHSIZE__MASK; 3699a26ae754SRob Clark } 3700a26ae754SRob Clark #define A5XX_TEX_CONST_2_PITCH__MASK 0x1fffff80 3701a26ae754SRob Clark #define A5XX_TEX_CONST_2_PITCH__SHIFT 7 3702a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_2_PITCH(uint32_t val) 3703a26ae754SRob Clark { 3704a26ae754SRob Clark return ((val) << A5XX_TEX_CONST_2_PITCH__SHIFT) & A5XX_TEX_CONST_2_PITCH__MASK; 3705a26ae754SRob Clark } 3706a26ae754SRob Clark #define A5XX_TEX_CONST_2_TYPE__MASK 0x60000000 3707a26ae754SRob Clark #define A5XX_TEX_CONST_2_TYPE__SHIFT 29 3708a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val) 3709a26ae754SRob Clark { 3710a26ae754SRob Clark return ((val) << A5XX_TEX_CONST_2_TYPE__SHIFT) & A5XX_TEX_CONST_2_TYPE__MASK; 3711a26ae754SRob Clark } 3712a26ae754SRob Clark 3713a26ae754SRob Clark #define REG_A5XX_TEX_CONST_3 0x00000003 3714a26ae754SRob Clark #define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff 3715a26ae754SRob Clark #define A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0 3716a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) 3717a26ae754SRob Clark { 3718a26ae754SRob Clark return ((val >> 12) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK; 3719a26ae754SRob Clark } 3720a26ae754SRob Clark #define A5XX_TEX_CONST_3_FLAG 0x10000000 3721a26ae754SRob Clark 3722a26ae754SRob Clark #define REG_A5XX_TEX_CONST_4 0x00000004 3723a26ae754SRob Clark #define A5XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0 3724a26ae754SRob Clark #define A5XX_TEX_CONST_4_BASE_LO__SHIFT 5 3725a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_4_BASE_LO(uint32_t val) 3726a26ae754SRob Clark { 3727a26ae754SRob Clark return ((val >> 5) << A5XX_TEX_CONST_4_BASE_LO__SHIFT) & A5XX_TEX_CONST_4_BASE_LO__MASK; 3728a26ae754SRob Clark } 3729a26ae754SRob Clark 3730a26ae754SRob Clark #define REG_A5XX_TEX_CONST_5 0x00000005 3731a26ae754SRob Clark #define A5XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff 3732a26ae754SRob Clark #define A5XX_TEX_CONST_5_BASE_HI__SHIFT 0 3733a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_5_BASE_HI(uint32_t val) 3734a26ae754SRob Clark { 3735a26ae754SRob Clark return ((val) << A5XX_TEX_CONST_5_BASE_HI__SHIFT) & A5XX_TEX_CONST_5_BASE_HI__MASK; 3736a26ae754SRob Clark } 3737a26ae754SRob Clark #define A5XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000 3738a26ae754SRob Clark #define A5XX_TEX_CONST_5_DEPTH__SHIFT 17 3739a26ae754SRob Clark static inline uint32_t A5XX_TEX_CONST_5_DEPTH(uint32_t val) 3740a26ae754SRob Clark { 3741a26ae754SRob Clark return ((val) << A5XX_TEX_CONST_5_DEPTH__SHIFT) & A5XX_TEX_CONST_5_DEPTH__MASK; 3742a26ae754SRob Clark } 3743a26ae754SRob Clark 3744a26ae754SRob Clark #define REG_A5XX_TEX_CONST_6 0x00000006 3745a26ae754SRob Clark 3746a26ae754SRob Clark #define REG_A5XX_TEX_CONST_7 0x00000007 3747a26ae754SRob Clark 3748a26ae754SRob Clark #define REG_A5XX_TEX_CONST_8 0x00000008 3749a26ae754SRob Clark 3750a26ae754SRob Clark #define REG_A5XX_TEX_CONST_9 0x00000009 3751a26ae754SRob Clark 3752a26ae754SRob Clark #define REG_A5XX_TEX_CONST_10 0x0000000a 3753a26ae754SRob Clark 3754a26ae754SRob Clark #define REG_A5XX_TEX_CONST_11 0x0000000b 3755a26ae754SRob Clark 3756a26ae754SRob Clark 3757a26ae754SRob Clark #endif /* A5XX_XML */ 3758