1 #ifndef A4XX_XML 2 #define A4XX_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2015-05-20 20:03:07) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) 13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2015-05-20 20:03:14) 15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27) 16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67120 bytes, from 2015-08-14 23:22:03) 17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63785 bytes, from 2015-08-14 18:27:06) 18 19 Copyright (C) 2013-2015 by the following authors: 20 - Rob Clark <robdclark@gmail.com> (robclark) 21 22 Permission is hereby granted, free of charge, to any person obtaining 23 a copy of this software and associated documentation files (the 24 "Software"), to deal in the Software without restriction, including 25 without limitation the rights to use, copy, modify, merge, publish, 26 distribute, sublicense, and/or sell copies of the Software, and to 27 permit persons to whom the Software is furnished to do so, subject to 28 the following conditions: 29 30 The above copyright notice and this permission notice (including the 31 next paragraph) shall be included in all copies or substantial 32 portions of the Software. 33 34 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 36 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 37 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 38 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 39 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 40 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43 44 enum a4xx_color_fmt { 45 RB4_A8_UNORM = 1, 46 RB4_R8_UNORM = 2, 47 RB4_R4G4B4A4_UNORM = 8, 48 RB4_R5G5B5A1_UNORM = 10, 49 RB4_R5G6R5_UNORM = 14, 50 RB4_R8G8_UNORM = 15, 51 RB4_R8G8_SNORM = 16, 52 RB4_R8G8_UINT = 17, 53 RB4_R8G8_SINT = 18, 54 RB4_R16_FLOAT = 21, 55 RB4_R16_UINT = 22, 56 RB4_R16_SINT = 23, 57 RB4_R8G8B8_UNORM = 25, 58 RB4_R8G8B8A8_UNORM = 26, 59 RB4_R8G8B8A8_SNORM = 28, 60 RB4_R8G8B8A8_UINT = 29, 61 RB4_R8G8B8A8_SINT = 30, 62 RB4_R10G10B10A2_UNORM = 31, 63 RB4_R10G10B10A2_UINT = 34, 64 RB4_R11G11B10_FLOAT = 39, 65 RB4_R16G16_FLOAT = 42, 66 RB4_R16G16_UINT = 43, 67 RB4_R16G16_SINT = 44, 68 RB4_R32_FLOAT = 45, 69 RB4_R32_UINT = 46, 70 RB4_R32_SINT = 47, 71 RB4_R16G16B16A16_FLOAT = 54, 72 RB4_R16G16B16A16_UINT = 55, 73 RB4_R16G16B16A16_SINT = 56, 74 RB4_R32G32_FLOAT = 57, 75 RB4_R32G32_UINT = 58, 76 RB4_R32G32_SINT = 59, 77 RB4_R32G32B32A32_FLOAT = 60, 78 RB4_R32G32B32A32_UINT = 61, 79 RB4_R32G32B32A32_SINT = 62, 80 }; 81 82 enum a4xx_tile_mode { 83 TILE4_LINEAR = 0, 84 TILE4_3 = 3, 85 }; 86 87 enum a4xx_rb_blend_opcode { 88 BLEND_DST_PLUS_SRC = 0, 89 BLEND_SRC_MINUS_DST = 1, 90 BLEND_DST_MINUS_SRC = 2, 91 BLEND_MIN_DST_SRC = 3, 92 BLEND_MAX_DST_SRC = 4, 93 }; 94 95 enum a4xx_vtx_fmt { 96 VFMT4_32_FLOAT = 1, 97 VFMT4_32_32_FLOAT = 2, 98 VFMT4_32_32_32_FLOAT = 3, 99 VFMT4_32_32_32_32_FLOAT = 4, 100 VFMT4_16_FLOAT = 5, 101 VFMT4_16_16_FLOAT = 6, 102 VFMT4_16_16_16_FLOAT = 7, 103 VFMT4_16_16_16_16_FLOAT = 8, 104 VFMT4_32_FIXED = 9, 105 VFMT4_32_32_FIXED = 10, 106 VFMT4_32_32_32_FIXED = 11, 107 VFMT4_32_32_32_32_FIXED = 12, 108 VFMT4_16_SINT = 16, 109 VFMT4_16_16_SINT = 17, 110 VFMT4_16_16_16_SINT = 18, 111 VFMT4_16_16_16_16_SINT = 19, 112 VFMT4_16_UINT = 20, 113 VFMT4_16_16_UINT = 21, 114 VFMT4_16_16_16_UINT = 22, 115 VFMT4_16_16_16_16_UINT = 23, 116 VFMT4_16_SNORM = 24, 117 VFMT4_16_16_SNORM = 25, 118 VFMT4_16_16_16_SNORM = 26, 119 VFMT4_16_16_16_16_SNORM = 27, 120 VFMT4_16_UNORM = 28, 121 VFMT4_16_16_UNORM = 29, 122 VFMT4_16_16_16_UNORM = 30, 123 VFMT4_16_16_16_16_UNORM = 31, 124 VFMT4_32_UINT = 32, 125 VFMT4_32_32_UINT = 33, 126 VFMT4_32_32_32_UINT = 34, 127 VFMT4_32_32_32_32_UINT = 35, 128 VFMT4_32_SINT = 36, 129 VFMT4_32_32_SINT = 37, 130 VFMT4_32_32_32_SINT = 38, 131 VFMT4_32_32_32_32_SINT = 39, 132 VFMT4_8_UINT = 40, 133 VFMT4_8_8_UINT = 41, 134 VFMT4_8_8_8_UINT = 42, 135 VFMT4_8_8_8_8_UINT = 43, 136 VFMT4_8_UNORM = 44, 137 VFMT4_8_8_UNORM = 45, 138 VFMT4_8_8_8_UNORM = 46, 139 VFMT4_8_8_8_8_UNORM = 47, 140 VFMT4_8_SINT = 48, 141 VFMT4_8_8_SINT = 49, 142 VFMT4_8_8_8_SINT = 50, 143 VFMT4_8_8_8_8_SINT = 51, 144 VFMT4_8_SNORM = 52, 145 VFMT4_8_8_SNORM = 53, 146 VFMT4_8_8_8_SNORM = 54, 147 VFMT4_8_8_8_8_SNORM = 55, 148 VFMT4_10_10_10_2_UINT = 60, 149 VFMT4_10_10_10_2_UNORM = 61, 150 VFMT4_10_10_10_2_SINT = 62, 151 VFMT4_10_10_10_2_SNORM = 63, 152 }; 153 154 enum a4xx_tex_fmt { 155 TFMT4_5_6_5_UNORM = 11, 156 TFMT4_5_5_5_1_UNORM = 10, 157 TFMT4_4_4_4_4_UNORM = 8, 158 TFMT4_X8Z24_UNORM = 71, 159 TFMT4_10_10_10_2_UNORM = 33, 160 TFMT4_A8_UNORM = 3, 161 TFMT4_L8_A8_UNORM = 13, 162 TFMT4_8_UNORM = 4, 163 TFMT4_8_8_UNORM = 14, 164 TFMT4_8_8_8_8_UNORM = 28, 165 TFMT4_8_8_SNORM = 15, 166 TFMT4_8_8_8_8_SNORM = 29, 167 TFMT4_8_8_UINT = 16, 168 TFMT4_8_8_8_8_UINT = 30, 169 TFMT4_8_8_SINT = 17, 170 TFMT4_8_8_8_8_SINT = 31, 171 TFMT4_16_UINT = 21, 172 TFMT4_16_16_UINT = 41, 173 TFMT4_16_16_16_16_UINT = 54, 174 TFMT4_16_SINT = 22, 175 TFMT4_16_16_SINT = 42, 176 TFMT4_16_16_16_16_SINT = 55, 177 TFMT4_32_UINT = 44, 178 TFMT4_32_32_UINT = 57, 179 TFMT4_32_32_32_32_UINT = 64, 180 TFMT4_32_SINT = 45, 181 TFMT4_32_32_SINT = 58, 182 TFMT4_32_32_32_32_SINT = 65, 183 TFMT4_16_FLOAT = 20, 184 TFMT4_16_16_FLOAT = 40, 185 TFMT4_16_16_16_16_FLOAT = 53, 186 TFMT4_32_FLOAT = 43, 187 TFMT4_32_32_FLOAT = 56, 188 TFMT4_32_32_32_32_FLOAT = 63, 189 TFMT4_9_9_9_E5_FLOAT = 32, 190 TFMT4_11_11_10_FLOAT = 37, 191 TFMT4_ATC_RGB = 100, 192 TFMT4_ATC_RGBA_EXPLICIT = 101, 193 TFMT4_ATC_RGBA_INTERPOLATED = 102, 194 TFMT4_ETC2_RG11_UNORM = 103, 195 TFMT4_ETC2_RG11_SNORM = 104, 196 TFMT4_ETC2_R11_UNORM = 105, 197 TFMT4_ETC2_R11_SNORM = 106, 198 TFMT4_ETC1 = 107, 199 TFMT4_ETC2_RGB8 = 108, 200 TFMT4_ETC2_RGBA8 = 109, 201 TFMT4_ETC2_RGB8A1 = 110, 202 TFMT4_ASTC_4x4 = 111, 203 TFMT4_ASTC_5x4 = 112, 204 TFMT4_ASTC_5x5 = 113, 205 TFMT4_ASTC_6x5 = 114, 206 TFMT4_ASTC_6x6 = 115, 207 TFMT4_ASTC_8x5 = 116, 208 TFMT4_ASTC_8x6 = 117, 209 TFMT4_ASTC_8x8 = 118, 210 TFMT4_ASTC_10x5 = 119, 211 TFMT4_ASTC_10x6 = 120, 212 TFMT4_ASTC_10x8 = 121, 213 TFMT4_ASTC_10x10 = 122, 214 TFMT4_ASTC_12x10 = 123, 215 TFMT4_ASTC_12x12 = 124, 216 }; 217 218 enum a4xx_tex_fetchsize { 219 TFETCH4_1_BYTE = 0, 220 TFETCH4_2_BYTE = 1, 221 TFETCH4_4_BYTE = 2, 222 TFETCH4_8_BYTE = 3, 223 TFETCH4_16_BYTE = 4, 224 }; 225 226 enum a4xx_depth_format { 227 DEPTH4_NONE = 0, 228 DEPTH4_16 = 1, 229 DEPTH4_24_8 = 2, 230 DEPTH4_32 = 3, 231 }; 232 233 enum a4xx_tess_spacing { 234 EQUAL_SPACING = 0, 235 ODD_SPACING = 2, 236 EVEN_SPACING = 3, 237 }; 238 239 enum a4xx_tex_filter { 240 A4XX_TEX_NEAREST = 0, 241 A4XX_TEX_LINEAR = 1, 242 A4XX_TEX_ANISO = 2, 243 }; 244 245 enum a4xx_tex_clamp { 246 A4XX_TEX_REPEAT = 0, 247 A4XX_TEX_CLAMP_TO_EDGE = 1, 248 A4XX_TEX_MIRROR_REPEAT = 2, 249 A4XX_TEX_CLAMP_NONE = 3, 250 }; 251 252 enum a4xx_tex_aniso { 253 A4XX_TEX_ANISO_1 = 0, 254 A4XX_TEX_ANISO_2 = 1, 255 A4XX_TEX_ANISO_4 = 2, 256 A4XX_TEX_ANISO_8 = 3, 257 A4XX_TEX_ANISO_16 = 4, 258 }; 259 260 enum a4xx_tex_swiz { 261 A4XX_TEX_X = 0, 262 A4XX_TEX_Y = 1, 263 A4XX_TEX_Z = 2, 264 A4XX_TEX_W = 3, 265 A4XX_TEX_ZERO = 4, 266 A4XX_TEX_ONE = 5, 267 }; 268 269 enum a4xx_tex_type { 270 A4XX_TEX_1D = 0, 271 A4XX_TEX_2D = 1, 272 A4XX_TEX_CUBE = 2, 273 A4XX_TEX_3D = 3, 274 }; 275 276 #define A4XX_CGC_HLSQ_EARLY_CYC__MASK 0x00700000 277 #define A4XX_CGC_HLSQ_EARLY_CYC__SHIFT 20 278 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) 279 { 280 return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK; 281 } 282 #define A4XX_INT0_RBBM_GPU_IDLE 0x00000001 283 #define A4XX_INT0_RBBM_AHB_ERROR 0x00000002 284 #define A4XX_INT0_RBBM_REG_TIMEOUT 0x00000004 285 #define A4XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 286 #define A4XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 287 #define A4XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020 288 #define A4XX_INT0_VFD_ERROR 0x00000040 289 #define A4XX_INT0_CP_SW_INT 0x00000080 290 #define A4XX_INT0_CP_T0_PACKET_IN_IB 0x00000100 291 #define A4XX_INT0_CP_OPCODE_ERROR 0x00000200 292 #define A4XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400 293 #define A4XX_INT0_CP_HW_FAULT 0x00000800 294 #define A4XX_INT0_CP_DMA 0x00001000 295 #define A4XX_INT0_CP_IB2_INT 0x00002000 296 #define A4XX_INT0_CP_IB1_INT 0x00004000 297 #define A4XX_INT0_CP_RB_INT 0x00008000 298 #define A4XX_INT0_CP_REG_PROTECT_FAULT 0x00010000 299 #define A4XX_INT0_CP_RB_DONE_TS 0x00020000 300 #define A4XX_INT0_CP_VS_DONE_TS 0x00040000 301 #define A4XX_INT0_CP_PS_DONE_TS 0x00080000 302 #define A4XX_INT0_CACHE_FLUSH_TS 0x00100000 303 #define A4XX_INT0_CP_AHB_ERROR_HALT 0x00200000 304 #define A4XX_INT0_MISC_HANG_DETECT 0x01000000 305 #define A4XX_INT0_UCHE_OOB_ACCESS 0x02000000 306 #define REG_A4XX_RB_GMEM_BASE_ADDR 0x00000cc0 307 308 #define REG_A4XX_RB_PERFCTR_RB_SEL_0 0x00000cc7 309 310 #define REG_A4XX_RB_PERFCTR_RB_SEL_1 0x00000cc8 311 312 #define REG_A4XX_RB_PERFCTR_RB_SEL_2 0x00000cc9 313 314 #define REG_A4XX_RB_PERFCTR_RB_SEL_3 0x00000cca 315 316 #define REG_A4XX_RB_PERFCTR_RB_SEL_4 0x00000ccb 317 318 #define REG_A4XX_RB_PERFCTR_RB_SEL_5 0x00000ccc 319 320 #define REG_A4XX_RB_PERFCTR_RB_SEL_6 0x00000ccd 321 322 #define REG_A4XX_RB_PERFCTR_RB_SEL_7 0x00000cce 323 324 #define REG_A4XX_RB_PERFCTR_CCU_SEL_3 0x00000cd2 325 326 #define REG_A4XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0 327 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff 328 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0 329 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) 330 { 331 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK; 332 } 333 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x3fff0000 334 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 16 335 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) 336 { 337 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK; 338 } 339 340 #define REG_A4XX_RB_CLEAR_COLOR_DW0 0x000020cc 341 342 #define REG_A4XX_RB_CLEAR_COLOR_DW1 0x000020cd 343 344 #define REG_A4XX_RB_CLEAR_COLOR_DW2 0x000020ce 345 346 #define REG_A4XX_RB_CLEAR_COLOR_DW3 0x000020cf 347 348 #define REG_A4XX_RB_MODE_CONTROL 0x000020a0 349 #define A4XX_RB_MODE_CONTROL_WIDTH__MASK 0x0000003f 350 #define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT 0 351 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) 352 { 353 return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK; 354 } 355 #define A4XX_RB_MODE_CONTROL_HEIGHT__MASK 0x00003f00 356 #define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT 8 357 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) 358 { 359 return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK; 360 } 361 362 #define REG_A4XX_RB_RENDER_CONTROL 0x000020a1 363 #define A4XX_RB_RENDER_CONTROL_BINNING_PASS 0x00000001 364 #define A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00000020 365 366 #define REG_A4XX_RB_MSAA_CONTROL 0x000020a2 367 #define A4XX_RB_MSAA_CONTROL_DISABLE 0x00001000 368 #define A4XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000e000 369 #define A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 13 370 static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val) 371 { 372 return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK; 373 } 374 375 #define REG_A4XX_RB_RENDER_CONTROL2 0x000020a3 376 #define A4XX_RB_RENDER_CONTROL2_XCOORD 0x00000001 377 #define A4XX_RB_RENDER_CONTROL2_YCOORD 0x00000002 378 #define A4XX_RB_RENDER_CONTROL2_ZCOORD 0x00000004 379 #define A4XX_RB_RENDER_CONTROL2_WCOORD 0x00000008 380 #define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK 0x00000010 381 #define A4XX_RB_RENDER_CONTROL2_FACENESS 0x00000020 382 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID 0x00000040 383 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK 0x00000380 384 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT 7 385 static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val) 386 { 387 return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK; 388 } 389 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR 0x00000800 390 #define A4XX_RB_RENDER_CONTROL2_VARYING 0x00001000 391 392 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; } 393 394 static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; } 395 #define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008 396 #define A4XX_RB_MRT_CONTROL_BLEND 0x00000010 397 #define A4XX_RB_MRT_CONTROL_BLEND2 0x00000020 398 #define A4XX_RB_MRT_CONTROL_FASTCLEAR 0x00000400 399 #define A4XX_RB_MRT_CONTROL_B11 0x00000800 400 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000 401 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24 402 static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 403 { 404 return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 405 } 406 407 static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; } 408 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f 409 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 410 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val) 411 { 412 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 413 } 414 #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0 415 #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6 416 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val) 417 { 418 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 419 } 420 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00000600 421 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 9 422 static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 423 { 424 return ((val) << A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK; 425 } 426 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00001800 427 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 11 428 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 429 { 430 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 431 } 432 #define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00002000 433 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xffffc000 434 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 14 435 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) 436 { 437 return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; 438 } 439 440 static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; } 441 442 static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; } 443 #define A4XX_RB_MRT_CONTROL3_STRIDE__MASK 0x03fffff8 444 #define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT 3 445 static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val) 446 { 447 return ((val) << A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT) & A4XX_RB_MRT_CONTROL3_STRIDE__MASK; 448 } 449 450 static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; } 451 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 452 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 453 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 454 { 455 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 456 } 457 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 458 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 459 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a4xx_rb_blend_opcode val) 460 { 461 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 462 } 463 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 464 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 465 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 466 { 467 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 468 } 469 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 470 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 471 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 472 { 473 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 474 } 475 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 476 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 477 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a4xx_rb_blend_opcode val) 478 { 479 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 480 } 481 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 482 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 483 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 484 { 485 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 486 } 487 488 #define REG_A4XX_RB_BLEND_RED 0x000020f3 489 #define A4XX_RB_BLEND_RED_UINT__MASK 0x00007fff 490 #define A4XX_RB_BLEND_RED_UINT__SHIFT 0 491 static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val) 492 { 493 return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK; 494 } 495 #define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 496 #define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16 497 static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val) 498 { 499 return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK; 500 } 501 502 #define REG_A4XX_RB_BLEND_GREEN 0x000020f4 503 #define A4XX_RB_BLEND_GREEN_UINT__MASK 0x00007fff 504 #define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0 505 static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val) 506 { 507 return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK; 508 } 509 #define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 510 #define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 511 static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val) 512 { 513 return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK; 514 } 515 516 #define REG_A4XX_RB_BLEND_BLUE 0x000020f5 517 #define A4XX_RB_BLEND_BLUE_UINT__MASK 0x00007fff 518 #define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0 519 static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val) 520 { 521 return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK; 522 } 523 #define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 524 #define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 525 static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val) 526 { 527 return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK; 528 } 529 530 #define REG_A4XX_RB_BLEND_ALPHA 0x000020f6 531 #define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x00007fff 532 #define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0 533 static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val) 534 { 535 return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK; 536 } 537 #define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 538 #define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 539 static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val) 540 { 541 return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK; 542 } 543 544 #define REG_A4XX_RB_ALPHA_CONTROL 0x000020f8 545 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff 546 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 547 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) 548 { 549 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; 550 } 551 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 552 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 553 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 554 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 555 { 556 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; 557 } 558 559 #define REG_A4XX_RB_FS_OUTPUT 0x000020f9 560 #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK 0x000000ff 561 #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT 0 562 static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val) 563 { 564 return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK; 565 } 566 #define A4XX_RB_FS_OUTPUT_FAST_CLEAR 0x00000100 567 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000 568 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT 16 569 static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val) 570 { 571 return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK; 572 } 573 574 #define REG_A4XX_RB_SAMPLE_COUNT_CONTROL 0x000020fa 575 #define A4XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 576 #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK 0xfffffffc 577 #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT 2 578 static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val) 579 { 580 return ((val >> 2) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK; 581 } 582 583 #define REG_A4XX_RB_RENDER_COMPONENTS 0x000020fb 584 #define A4XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f 585 #define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0 586 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) 587 { 588 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT0__MASK; 589 } 590 #define A4XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0 591 #define A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4 592 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) 593 { 594 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT1__MASK; 595 } 596 #define A4XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00 597 #define A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8 598 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) 599 { 600 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT2__MASK; 601 } 602 #define A4XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000 603 #define A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12 604 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) 605 { 606 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT3__MASK; 607 } 608 #define A4XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000 609 #define A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16 610 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) 611 { 612 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT4__MASK; 613 } 614 #define A4XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000 615 #define A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20 616 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) 617 { 618 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT5__MASK; 619 } 620 #define A4XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000 621 #define A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24 622 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) 623 { 624 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT6__MASK; 625 } 626 #define A4XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000 627 #define A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28 628 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) 629 { 630 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT7__MASK; 631 } 632 633 #define REG_A4XX_RB_COPY_CONTROL 0x000020fc 634 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003 635 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0 636 static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) 637 { 638 return ((val) << A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK; 639 } 640 #define A4XX_RB_COPY_CONTROL_MODE__MASK 0x00000070 641 #define A4XX_RB_COPY_CONTROL_MODE__SHIFT 4 642 static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) 643 { 644 return ((val) << A4XX_RB_COPY_CONTROL_MODE__SHIFT) & A4XX_RB_COPY_CONTROL_MODE__MASK; 645 } 646 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00 647 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8 648 static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) 649 { 650 return ((val) << A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK; 651 } 652 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000 653 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14 654 static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) 655 { 656 return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK; 657 } 658 659 #define REG_A4XX_RB_COPY_DEST_BASE 0x000020fd 660 #define A4XX_RB_COPY_DEST_BASE_BASE__MASK 0xffffffe0 661 #define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT 5 662 static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val) 663 { 664 return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK; 665 } 666 667 #define REG_A4XX_RB_COPY_DEST_PITCH 0x000020fe 668 #define A4XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff 669 #define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0 670 static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) 671 { 672 return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK; 673 } 674 675 #define REG_A4XX_RB_COPY_DEST_INFO 0x000020ff 676 #define A4XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc 677 #define A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2 678 static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val) 679 { 680 return ((val) << A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A4XX_RB_COPY_DEST_INFO_FORMAT__MASK; 681 } 682 #define A4XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 683 #define A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 684 static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) 685 { 686 return ((val) << A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A4XX_RB_COPY_DEST_INFO_SWAP__MASK; 687 } 688 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 689 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 690 static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 691 { 692 return ((val) << A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 693 } 694 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000 695 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14 696 static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) 697 { 698 return ((val) << A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK; 699 } 700 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000 701 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18 702 static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) 703 { 704 return ((val) << A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK; 705 } 706 #define A4XX_RB_COPY_DEST_INFO_TILE__MASK 0x03000000 707 #define A4XX_RB_COPY_DEST_INFO_TILE__SHIFT 24 708 static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val) 709 { 710 return ((val) << A4XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A4XX_RB_COPY_DEST_INFO_TILE__MASK; 711 } 712 713 #define REG_A4XX_RB_FS_OUTPUT_REG 0x00002100 714 #define A4XX_RB_FS_OUTPUT_REG_MRT__MASK 0x0000000f 715 #define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT 0 716 static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val) 717 { 718 return ((val) << A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_RB_FS_OUTPUT_REG_MRT__MASK; 719 } 720 #define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z 0x00000020 721 722 #define REG_A4XX_RB_DEPTH_CONTROL 0x00002101 723 #define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001 724 #define A4XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002 725 #define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004 726 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070 727 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4 728 static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) 729 { 730 return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK; 731 } 732 #define A4XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080 733 #define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000 734 #define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000 735 736 #define REG_A4XX_RB_DEPTH_CLEAR 0x00002102 737 738 #define REG_A4XX_RB_DEPTH_INFO 0x00002103 739 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003 740 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 741 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val) 742 { 743 return ((val) << A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 744 } 745 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 746 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 747 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 748 { 749 return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 750 } 751 752 #define REG_A4XX_RB_DEPTH_PITCH 0x00002104 753 #define A4XX_RB_DEPTH_PITCH__MASK 0xffffffff 754 #define A4XX_RB_DEPTH_PITCH__SHIFT 0 755 static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val) 756 { 757 return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK; 758 } 759 760 #define REG_A4XX_RB_DEPTH_PITCH2 0x00002105 761 #define A4XX_RB_DEPTH_PITCH2__MASK 0xffffffff 762 #define A4XX_RB_DEPTH_PITCH2__SHIFT 0 763 static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val) 764 { 765 return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK; 766 } 767 768 #define REG_A4XX_RB_STENCIL_CONTROL 0x00002106 769 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 770 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 771 #define A4XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 772 #define A4XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 773 #define A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 774 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 775 { 776 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC__MASK; 777 } 778 #define A4XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 779 #define A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 780 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 781 { 782 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL__MASK; 783 } 784 #define A4XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 785 #define A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 786 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 787 { 788 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS__MASK; 789 } 790 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 791 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 792 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 793 { 794 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 795 } 796 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 797 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 798 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 799 { 800 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 801 } 802 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 803 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 804 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 805 { 806 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 807 } 808 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 809 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 810 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 811 { 812 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 813 } 814 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 815 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 816 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 817 { 818 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 819 } 820 821 #define REG_A4XX_RB_STENCIL_CONTROL2 0x00002107 822 #define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER 0x00000001 823 824 #define REG_A4XX_RB_STENCIL_INFO 0x00002108 825 #define A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 826 #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff000 827 #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 12 828 static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) 829 { 830 return ((val >> 12) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK; 831 } 832 833 #define REG_A4XX_RB_STENCIL_PITCH 0x00002109 834 #define A4XX_RB_STENCIL_PITCH__MASK 0xffffffff 835 #define A4XX_RB_STENCIL_PITCH__SHIFT 0 836 static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val) 837 { 838 return ((val >> 5) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK; 839 } 840 841 #define REG_A4XX_RB_STENCILREFMASK 0x0000210b 842 #define A4XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 843 #define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 844 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 845 { 846 return ((val) << A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILREF__MASK; 847 } 848 #define A4XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 849 #define A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 850 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 851 { 852 return ((val) << A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILMASK__MASK; 853 } 854 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 855 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 856 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 857 { 858 return ((val) << A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 859 } 860 861 #define REG_A4XX_RB_STENCILREFMASK_BF 0x0000210c 862 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 863 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 864 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 865 { 866 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 867 } 868 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 869 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 870 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 871 { 872 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 873 } 874 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 875 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 876 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 877 { 878 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 879 } 880 881 #define REG_A4XX_RB_BIN_OFFSET 0x0000210d 882 #define A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 883 #define A4XX_RB_BIN_OFFSET_X__MASK 0x00007fff 884 #define A4XX_RB_BIN_OFFSET_X__SHIFT 0 885 static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val) 886 { 887 return ((val) << A4XX_RB_BIN_OFFSET_X__SHIFT) & A4XX_RB_BIN_OFFSET_X__MASK; 888 } 889 #define A4XX_RB_BIN_OFFSET_Y__MASK 0x7fff0000 890 #define A4XX_RB_BIN_OFFSET_Y__SHIFT 16 891 static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val) 892 { 893 return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK; 894 } 895 896 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; } 897 898 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; } 899 900 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; } 901 902 #define REG_A4XX_RBBM_HW_VERSION 0x00000000 903 904 #define REG_A4XX_RBBM_HW_CONFIGURATION 0x00000002 905 906 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; } 907 908 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; } 909 910 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; } 911 912 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; } 913 914 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; } 915 916 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; } 917 918 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; } 919 920 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; } 921 922 #define REG_A4XX_RBBM_CLOCK_CTL_UCHE 0x00000014 923 924 #define REG_A4XX_RBBM_CLOCK_CTL2_UCHE 0x00000015 925 926 #define REG_A4XX_RBBM_CLOCK_CTL3_UCHE 0x00000016 927 928 #define REG_A4XX_RBBM_CLOCK_CTL4_UCHE 0x00000017 929 930 #define REG_A4XX_RBBM_CLOCK_HYST_UCHE 0x00000018 931 932 #define REG_A4XX_RBBM_CLOCK_DELAY_UCHE 0x00000019 933 934 #define REG_A4XX_RBBM_CLOCK_MODE_GPC 0x0000001a 935 936 #define REG_A4XX_RBBM_CLOCK_DELAY_GPC 0x0000001b 937 938 #define REG_A4XX_RBBM_CLOCK_HYST_GPC 0x0000001c 939 940 #define REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM 0x0000001d 941 942 #define REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000001e 943 944 #define REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x0000001f 945 946 #define REG_A4XX_RBBM_CLOCK_CTL 0x00000020 947 948 #define REG_A4XX_RBBM_SP_HYST_CNT 0x00000021 949 950 #define REG_A4XX_RBBM_SW_RESET_CMD 0x00000022 951 952 #define REG_A4XX_RBBM_AHB_CTL0 0x00000023 953 954 #define REG_A4XX_RBBM_AHB_CTL1 0x00000024 955 956 #define REG_A4XX_RBBM_AHB_CMD 0x00000025 957 958 #define REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL 0x00000026 959 960 #define REG_A4XX_RBBM_RAM_ACC_63_32 0x00000028 961 962 #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x0000002b 963 964 #define REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL 0x0000002f 965 966 #define REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4 0x00000034 967 968 #define REG_A4XX_RBBM_INT_CLEAR_CMD 0x00000036 969 970 #define REG_A4XX_RBBM_INT_0_MASK 0x00000037 971 972 #define REG_A4XX_RBBM_RBBM_CTL 0x0000003e 973 974 #define REG_A4XX_RBBM_AHB_DEBUG_CTL 0x0000003f 975 976 #define REG_A4XX_RBBM_VBIF_DEBUG_CTL 0x00000041 977 978 #define REG_A4XX_RBBM_CLOCK_CTL2 0x00000042 979 980 #define REG_A4XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 981 982 #define REG_A4XX_RBBM_RESET_CYCLES 0x00000047 983 984 #define REG_A4XX_RBBM_EXT_TRACE_BUS_CTL 0x00000049 985 986 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A 0x0000004a 987 988 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B 0x0000004b 989 990 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C 0x0000004c 991 992 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D 0x0000004d 993 994 #define REG_A4XX_RBBM_PERFCTR_CP_0_LO 0x0000009c 995 996 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; } 997 998 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; } 999 1000 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; } 1001 1002 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; } 1003 1004 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; } 1005 1006 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; } 1007 1008 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; } 1009 1010 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; } 1011 1012 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; } 1013 1014 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; } 1015 1016 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; } 1017 1018 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; } 1019 1020 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; } 1021 1022 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; } 1023 1024 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; } 1025 1026 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; } 1027 1028 #define REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM 0x00000080 1029 1030 #define REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM 0x00000081 1031 1032 #define REG_A4XX_RBBM_CLOCK_CTL_HLSQ 0x0000008a 1033 1034 #define REG_A4XX_RBBM_CLOCK_HYST_HLSQ 0x0000008b 1035 1036 #define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ 0x0000008c 1037 1038 #define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM 0x0000008d 1039 1040 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; } 1041 1042 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; } 1043 1044 #define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168 1045 1046 #define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170 1047 1048 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0 0x00000171 1049 1050 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1 0x00000172 1051 1052 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2 0x00000173 1053 1054 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000174 1055 1056 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000175 1057 1058 #define REG_A4XX_RBBM_GPU_BUSY_MASKED 0x0000017a 1059 1060 #define REG_A4XX_RBBM_INT_0_STATUS 0x0000017d 1061 1062 #define REG_A4XX_RBBM_CLOCK_STATUS 0x00000182 1063 1064 #define REG_A4XX_RBBM_AHB_STATUS 0x00000189 1065 1066 #define REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS 0x0000018c 1067 1068 #define REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS 0x0000018d 1069 1070 #define REG_A4XX_RBBM_AHB_ERROR_STATUS 0x0000018f 1071 1072 #define REG_A4XX_RBBM_STATUS 0x00000191 1073 #define A4XX_RBBM_STATUS_HI_BUSY 0x00000001 1074 #define A4XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 1075 #define A4XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 1076 #define A4XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000 1077 #define A4XX_RBBM_STATUS_VBIF_BUSY 0x00008000 1078 #define A4XX_RBBM_STATUS_TSE_BUSY 0x00010000 1079 #define A4XX_RBBM_STATUS_RAS_BUSY 0x00020000 1080 #define A4XX_RBBM_STATUS_RB_BUSY 0x00040000 1081 #define A4XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 1082 #define A4XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 1083 #define A4XX_RBBM_STATUS_VFD_BUSY 0x00200000 1084 #define A4XX_RBBM_STATUS_VPC_BUSY 0x00400000 1085 #define A4XX_RBBM_STATUS_UCHE_BUSY 0x00800000 1086 #define A4XX_RBBM_STATUS_SP_BUSY 0x01000000 1087 #define A4XX_RBBM_STATUS_TPL1_BUSY 0x02000000 1088 #define A4XX_RBBM_STATUS_MARB_BUSY 0x04000000 1089 #define A4XX_RBBM_STATUS_VSC_BUSY 0x08000000 1090 #define A4XX_RBBM_STATUS_ARB_BUSY 0x10000000 1091 #define A4XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 1092 #define A4XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000 1093 #define A4XX_RBBM_STATUS_GPU_BUSY 0x80000000 1094 1095 #define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5 0x0000019f 1096 1097 #define REG_A4XX_CP_SCRATCH_UMASK 0x00000228 1098 1099 #define REG_A4XX_CP_SCRATCH_ADDR 0x00000229 1100 1101 #define REG_A4XX_CP_RB_BASE 0x00000200 1102 1103 #define REG_A4XX_CP_RB_CNTL 0x00000201 1104 1105 #define REG_A4XX_CP_RB_WPTR 0x00000205 1106 1107 #define REG_A4XX_CP_RB_RPTR_ADDR 0x00000203 1108 1109 #define REG_A4XX_CP_RB_RPTR 0x00000204 1110 1111 #define REG_A4XX_CP_IB1_BASE 0x00000206 1112 1113 #define REG_A4XX_CP_IB1_BUFSZ 0x00000207 1114 1115 #define REG_A4XX_CP_IB2_BASE 0x00000208 1116 1117 #define REG_A4XX_CP_IB2_BUFSZ 0x00000209 1118 1119 #define REG_A4XX_CP_ME_NRT_ADDR 0x0000020c 1120 1121 #define REG_A4XX_CP_ME_NRT_DATA 0x0000020d 1122 1123 #define REG_A4XX_CP_ME_RB_DONE_DATA 0x00000217 1124 1125 #define REG_A4XX_CP_QUEUE_THRESH2 0x00000219 1126 1127 #define REG_A4XX_CP_MERCIU_SIZE 0x0000021b 1128 1129 #define REG_A4XX_CP_ROQ_ADDR 0x0000021c 1130 1131 #define REG_A4XX_CP_ROQ_DATA 0x0000021d 1132 1133 #define REG_A4XX_CP_MEQ_ADDR 0x0000021e 1134 1135 #define REG_A4XX_CP_MEQ_DATA 0x0000021f 1136 1137 #define REG_A4XX_CP_MERCIU_ADDR 0x00000220 1138 1139 #define REG_A4XX_CP_MERCIU_DATA 0x00000221 1140 1141 #define REG_A4XX_CP_MERCIU_DATA2 0x00000222 1142 1143 #define REG_A4XX_CP_PFP_UCODE_ADDR 0x00000223 1144 1145 #define REG_A4XX_CP_PFP_UCODE_DATA 0x00000224 1146 1147 #define REG_A4XX_CP_ME_RAM_WADDR 0x00000225 1148 1149 #define REG_A4XX_CP_ME_RAM_RADDR 0x00000226 1150 1151 #define REG_A4XX_CP_ME_RAM_DATA 0x00000227 1152 1153 #define REG_A4XX_CP_PREEMPT 0x0000022a 1154 1155 #define REG_A4XX_CP_CNTL 0x0000022c 1156 1157 #define REG_A4XX_CP_ME_CNTL 0x0000022d 1158 1159 #define REG_A4XX_CP_DEBUG 0x0000022e 1160 1161 #define REG_A4XX_CP_DEBUG_ECO_CONTROL 0x00000231 1162 1163 #define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232 1164 1165 #define REG_A4XX_CP_PROTECT_REG_0 0x00000240 1166 1167 static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; } 1168 1169 static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; } 1170 1171 #define REG_A4XX_CP_PROTECT_CTRL 0x00000250 1172 1173 #define REG_A4XX_CP_ST_BASE 0x000004c0 1174 1175 #define REG_A4XX_CP_STQ_AVAIL 0x000004ce 1176 1177 #define REG_A4XX_CP_MERCIU_STAT 0x000004d0 1178 1179 #define REG_A4XX_CP_WFI_PEND_CTR 0x000004d2 1180 1181 #define REG_A4XX_CP_HW_FAULT 0x000004d8 1182 1183 #define REG_A4XX_CP_PROTECT_STATUS 0x000004da 1184 1185 #define REG_A4XX_CP_EVENTS_IN_FLIGHT 0x000004dd 1186 1187 #define REG_A4XX_CP_PERFCTR_CP_SEL_0 0x00000500 1188 1189 #define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b 1190 1191 static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; } 1192 1193 static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; } 1194 1195 #define REG_A4XX_SP_VS_STATUS 0x00000ec0 1196 1197 #define REG_A4XX_SP_MODE_CONTROL 0x00000ec3 1198 1199 #define REG_A4XX_SP_PERFCTR_SP_SEL_11 0x00000ecf 1200 1201 #define REG_A4XX_SP_SP_CTRL_REG 0x000022c0 1202 #define A4XX_SP_SP_CTRL_REG_BINNING_PASS 0x00080000 1203 1204 #define REG_A4XX_SP_INSTR_CACHE_CTRL 0x000022c1 1205 #define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER 0x00000080 1206 #define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER 0x00000100 1207 #define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER 0x00000400 1208 1209 #define REG_A4XX_SP_VS_CTRL_REG0 0x000022c4 1210 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 1211 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 1212 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 1213 { 1214 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK; 1215 } 1216 #define A4XX_SP_VS_CTRL_REG0_VARYING 0x00000002 1217 #define A4XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004 1218 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 1219 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 1220 static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 1221 { 1222 return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 1223 } 1224 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 1225 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 1226 static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 1227 { 1228 return ((val) << A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 1229 } 1230 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 1231 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 1232 static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 1233 { 1234 return ((val) << A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK; 1235 } 1236 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000 1237 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20 1238 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 1239 { 1240 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; 1241 } 1242 #define A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000 1243 #define A4XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000 1244 1245 #define REG_A4XX_SP_VS_CTRL_REG1 0x000022c5 1246 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff 1247 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0 1248 static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) 1249 { 1250 return ((val) << A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK; 1251 } 1252 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000 1253 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24 1254 static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) 1255 { 1256 return ((val) << A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK; 1257 } 1258 1259 #define REG_A4XX_SP_VS_PARAM_REG 0x000022c6 1260 #define A4XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff 1261 #define A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0 1262 static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) 1263 { 1264 return ((val) << A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_POSREGID__MASK; 1265 } 1266 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00 1267 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8 1268 static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) 1269 { 1270 return ((val) << A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK; 1271 } 1272 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000 1273 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20 1274 static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) 1275 { 1276 return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; 1277 } 1278 1279 static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 1280 1281 static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 1282 #define A4XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff 1283 #define A4XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 1284 static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 1285 { 1286 return ((val) << A4XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_A_REGID__MASK; 1287 } 1288 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00 1289 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9 1290 static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 1291 { 1292 return ((val) << A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 1293 } 1294 #define A4XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000 1295 #define A4XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 1296 static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 1297 { 1298 return ((val) << A4XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_B_REGID__MASK; 1299 } 1300 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000 1301 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25 1302 static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 1303 { 1304 return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 1305 } 1306 1307 static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; } 1308 1309 static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; } 1310 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 1311 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 1312 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 1313 { 1314 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 1315 } 1316 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 1317 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 1318 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 1319 { 1320 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 1321 } 1322 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 1323 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 1324 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 1325 { 1326 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 1327 } 1328 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 1329 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 1330 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 1331 { 1332 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 1333 } 1334 1335 #define REG_A4XX_SP_VS_OBJ_OFFSET_REG 0x000022e0 1336 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1337 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1338 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1339 { 1340 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1341 } 1342 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1343 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1344 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1345 { 1346 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1347 } 1348 1349 #define REG_A4XX_SP_VS_OBJ_START 0x000022e1 1350 1351 #define REG_A4XX_SP_VS_PVT_MEM_PARAM 0x000022e2 1352 1353 #define REG_A4XX_SP_VS_PVT_MEM_ADDR 0x000022e3 1354 1355 #define REG_A4XX_SP_VS_LENGTH_REG 0x000022e5 1356 1357 #define REG_A4XX_SP_FS_CTRL_REG0 0x000022e8 1358 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 1359 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 1360 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 1361 { 1362 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK; 1363 } 1364 #define A4XX_SP_FS_CTRL_REG0_VARYING 0x00000002 1365 #define A4XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004 1366 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 1367 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 1368 static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 1369 { 1370 return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 1371 } 1372 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 1373 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 1374 static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 1375 { 1376 return ((val) << A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 1377 } 1378 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 1379 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 1380 static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 1381 { 1382 return ((val) << A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK; 1383 } 1384 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 1385 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 1386 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 1387 { 1388 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 1389 } 1390 #define A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000 1391 #define A4XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000 1392 1393 #define REG_A4XX_SP_FS_CTRL_REG1 0x000022e9 1394 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff 1395 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0 1396 static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) 1397 { 1398 return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK; 1399 } 1400 #define A4XX_SP_FS_CTRL_REG1_FACENESS 0x00080000 1401 #define A4XX_SP_FS_CTRL_REG1_VARYING 0x00100000 1402 #define A4XX_SP_FS_CTRL_REG1_FRAGCOORD 0x00200000 1403 1404 #define REG_A4XX_SP_FS_OBJ_OFFSET_REG 0x000022ea 1405 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1406 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1407 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1408 { 1409 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1410 } 1411 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1412 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1413 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1414 { 1415 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1416 } 1417 1418 #define REG_A4XX_SP_FS_OBJ_START 0x000022eb 1419 1420 #define REG_A4XX_SP_FS_PVT_MEM_PARAM 0x000022ec 1421 1422 #define REG_A4XX_SP_FS_PVT_MEM_ADDR 0x000022ed 1423 1424 #define REG_A4XX_SP_FS_LENGTH_REG 0x000022ef 1425 1426 #define REG_A4XX_SP_FS_OUTPUT_REG 0x000022f0 1427 #define A4XX_SP_FS_OUTPUT_REG_MRT__MASK 0x0000000f 1428 #define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0 1429 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val) 1430 { 1431 return ((val) << A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_SP_FS_OUTPUT_REG_MRT__MASK; 1432 } 1433 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080 1434 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00 1435 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8 1436 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) 1437 { 1438 return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK; 1439 } 1440 #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK 0xff000000 1441 #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT 24 1442 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val) 1443 { 1444 return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK; 1445 } 1446 1447 static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; } 1448 1449 static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; } 1450 #define A4XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff 1451 #define A4XX_SP_FS_MRT_REG_REGID__SHIFT 0 1452 static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val) 1453 { 1454 return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK; 1455 } 1456 #define A4XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100 1457 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK 0x0003f000 1458 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT 12 1459 static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val) 1460 { 1461 return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK; 1462 } 1463 #define A4XX_SP_FS_MRT_REG_COLOR_SRGB 0x00040000 1464 1465 #define REG_A4XX_SP_CS_CTRL_REG0 0x00002300 1466 1467 #define REG_A4XX_SP_CS_OBJ_OFFSET_REG 0x00002301 1468 1469 #define REG_A4XX_SP_CS_OBJ_START 0x00002302 1470 1471 #define REG_A4XX_SP_CS_PVT_MEM_PARAM 0x00002303 1472 1473 #define REG_A4XX_SP_CS_PVT_MEM_ADDR 0x00002304 1474 1475 #define REG_A4XX_SP_CS_PVT_MEM_SIZE 0x00002305 1476 1477 #define REG_A4XX_SP_CS_LENGTH_REG 0x00002306 1478 1479 #define REG_A4XX_SP_HS_OBJ_OFFSET_REG 0x0000230d 1480 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1481 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1482 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1483 { 1484 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1485 } 1486 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1487 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1488 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1489 { 1490 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1491 } 1492 1493 #define REG_A4XX_SP_HS_OBJ_START 0x0000230e 1494 1495 #define REG_A4XX_SP_HS_PVT_MEM_PARAM 0x0000230f 1496 1497 #define REG_A4XX_SP_HS_PVT_MEM_ADDR 0x00002310 1498 1499 #define REG_A4XX_SP_HS_LENGTH_REG 0x00002312 1500 1501 #define REG_A4XX_SP_DS_PARAM_REG 0x0000231a 1502 #define A4XX_SP_DS_PARAM_REG_POSREGID__MASK 0x000000ff 1503 #define A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT 0 1504 static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val) 1505 { 1506 return ((val) << A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_DS_PARAM_REG_POSREGID__MASK; 1507 } 1508 #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000 1509 #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20 1510 static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) 1511 { 1512 return ((val) << A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK; 1513 } 1514 1515 static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; } 1516 1517 static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; } 1518 #define A4XX_SP_DS_OUT_REG_A_REGID__MASK 0x000001ff 1519 #define A4XX_SP_DS_OUT_REG_A_REGID__SHIFT 0 1520 static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val) 1521 { 1522 return ((val) << A4XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_A_REGID__MASK; 1523 } 1524 #define A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00001e00 1525 #define A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 9 1526 static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val) 1527 { 1528 return ((val) << A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK; 1529 } 1530 #define A4XX_SP_DS_OUT_REG_B_REGID__MASK 0x01ff0000 1531 #define A4XX_SP_DS_OUT_REG_B_REGID__SHIFT 16 1532 static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val) 1533 { 1534 return ((val) << A4XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_B_REGID__MASK; 1535 } 1536 #define A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x1e000000 1537 #define A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 25 1538 static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val) 1539 { 1540 return ((val) << A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK; 1541 } 1542 1543 static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; } 1544 1545 static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; } 1546 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 1547 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0 1548 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val) 1549 { 1550 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK; 1551 } 1552 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 1553 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8 1554 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val) 1555 { 1556 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK; 1557 } 1558 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 1559 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16 1560 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val) 1561 { 1562 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK; 1563 } 1564 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 1565 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24 1566 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) 1567 { 1568 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK; 1569 } 1570 1571 #define REG_A4XX_SP_DS_OBJ_OFFSET_REG 0x00002334 1572 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1573 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1574 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1575 { 1576 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1577 } 1578 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1579 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1580 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1581 { 1582 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1583 } 1584 1585 #define REG_A4XX_SP_DS_OBJ_START 0x00002335 1586 1587 #define REG_A4XX_SP_DS_PVT_MEM_PARAM 0x00002336 1588 1589 #define REG_A4XX_SP_DS_PVT_MEM_ADDR 0x00002337 1590 1591 #define REG_A4XX_SP_DS_LENGTH_REG 0x00002339 1592 1593 #define REG_A4XX_SP_GS_PARAM_REG 0x00002341 1594 #define A4XX_SP_GS_PARAM_REG_POSREGID__MASK 0x000000ff 1595 #define A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT 0 1596 static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val) 1597 { 1598 return ((val) << A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_POSREGID__MASK; 1599 } 1600 #define A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK 0x0000ff00 1601 #define A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT 8 1602 static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val) 1603 { 1604 return ((val) << A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK; 1605 } 1606 #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000 1607 #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20 1608 static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) 1609 { 1610 return ((val) << A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK; 1611 } 1612 1613 static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; } 1614 1615 static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; } 1616 #define A4XX_SP_GS_OUT_REG_A_REGID__MASK 0x000001ff 1617 #define A4XX_SP_GS_OUT_REG_A_REGID__SHIFT 0 1618 static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val) 1619 { 1620 return ((val) << A4XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_A_REGID__MASK; 1621 } 1622 #define A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00001e00 1623 #define A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 9 1624 static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val) 1625 { 1626 return ((val) << A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK; 1627 } 1628 #define A4XX_SP_GS_OUT_REG_B_REGID__MASK 0x01ff0000 1629 #define A4XX_SP_GS_OUT_REG_B_REGID__SHIFT 16 1630 static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val) 1631 { 1632 return ((val) << A4XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_B_REGID__MASK; 1633 } 1634 #define A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x1e000000 1635 #define A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 25 1636 static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val) 1637 { 1638 return ((val) << A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK; 1639 } 1640 1641 static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; } 1642 1643 static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; } 1644 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 1645 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0 1646 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val) 1647 { 1648 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK; 1649 } 1650 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 1651 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8 1652 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val) 1653 { 1654 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK; 1655 } 1656 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 1657 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16 1658 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val) 1659 { 1660 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK; 1661 } 1662 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 1663 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24 1664 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) 1665 { 1666 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK; 1667 } 1668 1669 #define REG_A4XX_SP_GS_OBJ_OFFSET_REG 0x0000235b 1670 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1671 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1672 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1673 { 1674 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1675 } 1676 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1677 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1678 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1679 { 1680 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1681 } 1682 1683 #define REG_A4XX_SP_GS_OBJ_START 0x0000235c 1684 1685 #define REG_A4XX_SP_GS_PVT_MEM_PARAM 0x0000235d 1686 1687 #define REG_A4XX_SP_GS_PVT_MEM_ADDR 0x0000235e 1688 1689 #define REG_A4XX_SP_GS_LENGTH_REG 0x00002360 1690 1691 #define REG_A4XX_VPC_DEBUG_RAM_SEL 0x00000e60 1692 1693 #define REG_A4XX_VPC_DEBUG_RAM_READ 0x00000e61 1694 1695 #define REG_A4XX_VPC_DEBUG_ECO_CONTROL 0x00000e64 1696 1697 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_3 0x00000e68 1698 1699 #define REG_A4XX_VPC_ATTR 0x00002140 1700 #define A4XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff 1701 #define A4XX_VPC_ATTR_TOTALATTR__SHIFT 0 1702 static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val) 1703 { 1704 return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK; 1705 } 1706 #define A4XX_VPC_ATTR_PSIZE 0x00000200 1707 #define A4XX_VPC_ATTR_THRDASSIGN__MASK 0x00003000 1708 #define A4XX_VPC_ATTR_THRDASSIGN__SHIFT 12 1709 static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val) 1710 { 1711 return ((val) << A4XX_VPC_ATTR_THRDASSIGN__SHIFT) & A4XX_VPC_ATTR_THRDASSIGN__MASK; 1712 } 1713 #define A4XX_VPC_ATTR_ENABLE 0x02000000 1714 1715 #define REG_A4XX_VPC_PACK 0x00002141 1716 #define A4XX_VPC_PACK_NUMBYPASSVAR__MASK 0x000000ff 1717 #define A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT 0 1718 static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val) 1719 { 1720 return ((val) << A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT) & A4XX_VPC_PACK_NUMBYPASSVAR__MASK; 1721 } 1722 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00 1723 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8 1724 static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) 1725 { 1726 return ((val) << A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK; 1727 } 1728 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000 1729 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16 1730 static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) 1731 { 1732 return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK; 1733 } 1734 1735 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; } 1736 1737 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; } 1738 1739 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; } 1740 1741 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; } 1742 1743 #define REG_A4XX_VPC_SO_FLUSH_WADDR_3 0x0000216e 1744 1745 #define REG_A4XX_VSC_BIN_SIZE 0x00000c00 1746 #define A4XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 1747 #define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 1748 static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 1749 { 1750 return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK; 1751 } 1752 #define A4XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 1753 #define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5 1754 static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 1755 { 1756 return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK; 1757 } 1758 1759 #define REG_A4XX_VSC_SIZE_ADDRESS 0x00000c01 1760 1761 #define REG_A4XX_VSC_SIZE_ADDRESS2 0x00000c02 1762 1763 #define REG_A4XX_VSC_DEBUG_ECO_CONTROL 0x00000c03 1764 1765 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } 1766 1767 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } 1768 #define A4XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff 1769 #define A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0 1770 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) 1771 { 1772 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_X__MASK; 1773 } 1774 #define A4XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00 1775 #define A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10 1776 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) 1777 { 1778 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_Y__MASK; 1779 } 1780 #define A4XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000 1781 #define A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20 1782 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) 1783 { 1784 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_W__MASK; 1785 } 1786 #define A4XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000 1787 #define A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24 1788 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) 1789 { 1790 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK; 1791 } 1792 1793 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 1794 1795 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 1796 1797 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; } 1798 1799 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; } 1800 1801 #define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1 0x00000c41 1802 1803 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_0 0x00000c50 1804 1805 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_1 0x00000c51 1806 1807 #define REG_A4XX_VFD_DEBUG_CONTROL 0x00000e40 1808 1809 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 0x00000e4a 1810 1811 #define REG_A4XX_VGT_CL_INITIATOR 0x000021d0 1812 1813 #define REG_A4XX_VGT_EVENT_INITIATOR 0x000021d9 1814 1815 #define REG_A4XX_VFD_CONTROL_0 0x00002200 1816 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x000000ff 1817 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0 1818 static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) 1819 { 1820 return ((val) << A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK; 1821 } 1822 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK 0x0001fe00 1823 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT 9 1824 static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val) 1825 { 1826 return ((val) << A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT) & A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK; 1827 } 1828 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x03f00000 1829 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 20 1830 static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) 1831 { 1832 return ((val) << A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK; 1833 } 1834 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xfc000000 1835 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 26 1836 static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) 1837 { 1838 return ((val) << A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK; 1839 } 1840 1841 #define REG_A4XX_VFD_CONTROL_1 0x00002201 1842 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff 1843 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0 1844 static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) 1845 { 1846 return ((val) << A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK; 1847 } 1848 #define A4XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000 1849 #define A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16 1850 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 1851 { 1852 return ((val) << A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A4XX_VFD_CONTROL_1_REGID4VTX__MASK; 1853 } 1854 #define A4XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000 1855 #define A4XX_VFD_CONTROL_1_REGID4INST__SHIFT 24 1856 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 1857 { 1858 return ((val) << A4XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A4XX_VFD_CONTROL_1_REGID4INST__MASK; 1859 } 1860 1861 #define REG_A4XX_VFD_CONTROL_2 0x00002202 1862 1863 #define REG_A4XX_VFD_CONTROL_3 0x00002203 1864 #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK 0x0000ff00 1865 #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT 8 1866 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val) 1867 { 1868 return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK; 1869 } 1870 #define A4XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000 1871 #define A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16 1872 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) 1873 { 1874 return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSX__MASK; 1875 } 1876 #define A4XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000 1877 #define A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24 1878 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) 1879 { 1880 return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSY__MASK; 1881 } 1882 1883 #define REG_A4XX_VFD_CONTROL_4 0x00002204 1884 1885 #define REG_A4XX_VFD_INDEX_OFFSET 0x00002208 1886 1887 static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; } 1888 1889 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; } 1890 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f 1891 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0 1892 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) 1893 { 1894 return ((val) << A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK; 1895 } 1896 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80 1897 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7 1898 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) 1899 { 1900 return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK; 1901 } 1902 #define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00080000 1903 #define A4XX_VFD_FETCH_INSTR_0_INSTANCED 0x00100000 1904 1905 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; } 1906 1907 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; } 1908 #define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xfffffff0 1909 #define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 4 1910 static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val) 1911 { 1912 return ((val >> 4) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK; 1913 } 1914 1915 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; } 1916 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK 0x000001ff 1917 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT 0 1918 static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val) 1919 { 1920 return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK; 1921 } 1922 1923 static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; } 1924 1925 static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; } 1926 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f 1927 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0 1928 static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) 1929 { 1930 return ((val) << A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK; 1931 } 1932 #define A4XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010 1933 #define A4XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0 1934 #define A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6 1935 static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val) 1936 { 1937 return ((val) << A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A4XX_VFD_DECODE_INSTR_FORMAT__MASK; 1938 } 1939 #define A4XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000 1940 #define A4XX_VFD_DECODE_INSTR_REGID__SHIFT 12 1941 static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val) 1942 { 1943 return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK; 1944 } 1945 #define A4XX_VFD_DECODE_INSTR_INT 0x00100000 1946 #define A4XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000 1947 #define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT 22 1948 static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 1949 { 1950 return ((val) << A4XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A4XX_VFD_DECODE_INSTR_SWAP__MASK; 1951 } 1952 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000 1953 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24 1954 static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) 1955 { 1956 return ((val) << A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK; 1957 } 1958 #define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000 1959 #define A4XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000 1960 1961 #define REG_A4XX_TPL1_DEBUG_ECO_CONTROL 0x00000f00 1962 1963 #define REG_A4XX_TPL1_TP_MODE_CONTROL 0x00000f03 1964 1965 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 0x00000f0b 1966 1967 #define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380 1968 1969 #define REG_A4XX_TPL1_TP_TEX_COUNT 0x00002381 1970 #define A4XX_TPL1_TP_TEX_COUNT_VS__MASK 0x000000ff 1971 #define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT 0 1972 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val) 1973 { 1974 return ((val) << A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_VS__MASK; 1975 } 1976 #define A4XX_TPL1_TP_TEX_COUNT_HS__MASK 0x0000ff00 1977 #define A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT 8 1978 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val) 1979 { 1980 return ((val) << A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_HS__MASK; 1981 } 1982 #define A4XX_TPL1_TP_TEX_COUNT_DS__MASK 0x00ff0000 1983 #define A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT 16 1984 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val) 1985 { 1986 return ((val) << A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_DS__MASK; 1987 } 1988 #define A4XX_TPL1_TP_TEX_COUNT_GS__MASK 0xff000000 1989 #define A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT 24 1990 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val) 1991 { 1992 return ((val) << A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_GS__MASK; 1993 } 1994 1995 #define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002384 1996 1997 #define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR 0x00002387 1998 1999 #define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR 0x0000238a 2000 2001 #define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR 0x0000238d 2002 2003 #define REG_A4XX_TPL1_TP_FS_TEX_COUNT 0x000023a0 2004 2005 #define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x000023a1 2006 2007 #define REG_A4XX_TPL1_TP_CS_BORDER_COLOR_BASE_ADDR 0x000023a4 2008 2009 #define REG_A4XX_TPL1_TP_CS_SAMPLER_BASE_ADDR 0x000023a5 2010 2011 #define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR 0x000023a6 2012 2013 #define REG_A4XX_GRAS_TSE_STATUS 0x00000c80 2014 2015 #define REG_A4XX_GRAS_DEBUG_ECO_CONTROL 0x00000c81 2016 2017 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c88 2018 2019 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c8b 2020 2021 #define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000 2022 2023 #define REG_A4XX_GRAS_CLEAR_CNTL 0x00002003 2024 #define A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR 0x00000001 2025 2026 #define REG_A4XX_GRAS_CL_GB_CLIP_ADJ 0x00002004 2027 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff 2028 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0 2029 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) 2030 { 2031 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; 2032 } 2033 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00 2034 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10 2035 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) 2036 { 2037 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; 2038 } 2039 2040 #define REG_A4XX_GRAS_CL_VPORT_XOFFSET_0 0x00002008 2041 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff 2042 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0 2043 static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val) 2044 { 2045 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK; 2046 } 2047 2048 #define REG_A4XX_GRAS_CL_VPORT_XSCALE_0 0x00002009 2049 #define A4XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff 2050 #define A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0 2051 static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val) 2052 { 2053 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_XSCALE_0__MASK; 2054 } 2055 2056 #define REG_A4XX_GRAS_CL_VPORT_YOFFSET_0 0x0000200a 2057 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff 2058 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0 2059 static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val) 2060 { 2061 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK; 2062 } 2063 2064 #define REG_A4XX_GRAS_CL_VPORT_YSCALE_0 0x0000200b 2065 #define A4XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff 2066 #define A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0 2067 static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val) 2068 { 2069 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_YSCALE_0__MASK; 2070 } 2071 2072 #define REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000200c 2073 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff 2074 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0 2075 static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val) 2076 { 2077 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK; 2078 } 2079 2080 #define REG_A4XX_GRAS_CL_VPORT_ZSCALE_0 0x0000200d 2081 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff 2082 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0 2083 static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val) 2084 { 2085 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK; 2086 } 2087 2088 #define REG_A4XX_GRAS_SU_POINT_MINMAX 0x00002070 2089 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 2090 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 2091 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val) 2092 { 2093 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 2094 } 2095 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 2096 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 2097 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val) 2098 { 2099 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 2100 } 2101 2102 #define REG_A4XX_GRAS_SU_POINT_SIZE 0x00002071 2103 #define A4XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff 2104 #define A4XX_GRAS_SU_POINT_SIZE__SHIFT 0 2105 static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val) 2106 { 2107 return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK; 2108 } 2109 2110 #define REG_A4XX_GRAS_ALPHA_CONTROL 0x00002073 2111 #define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE 0x00000004 2112 2113 #define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE 0x00002074 2114 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff 2115 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 2116 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val) 2117 { 2118 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; 2119 } 2120 2121 #define REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00002075 2122 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 2123 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 2124 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 2125 { 2126 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 2127 } 2128 2129 #define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP 0x00002076 2130 #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK 0xffffffff 2131 #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT 0 2132 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val) 2133 { 2134 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK; 2135 } 2136 2137 #define REG_A4XX_GRAS_DEPTH_CONTROL 0x00002077 2138 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK 0x00000003 2139 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT 0 2140 static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val) 2141 { 2142 return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK; 2143 } 2144 2145 #define REG_A4XX_GRAS_SU_MODE_CONTROL 0x00002078 2146 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001 2147 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002 2148 #define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004 2149 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8 2150 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3 2151 static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) 2152 { 2153 return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; 2154 } 2155 #define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800 2156 #define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS 0x00100000 2157 2158 #define REG_A4XX_GRAS_SC_CONTROL 0x0000207b 2159 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x0000000c 2160 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 2 2161 static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) 2162 { 2163 return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK; 2164 } 2165 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000380 2166 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 7 2167 static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val) 2168 { 2169 return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK; 2170 } 2171 #define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE 0x00000800 2172 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000 2173 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12 2174 static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) 2175 { 2176 return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK; 2177 } 2178 2179 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL 0x0000207c 2180 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 2181 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 2182 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 2183 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 2184 { 2185 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; 2186 } 2187 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 2188 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 2189 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 2190 { 2191 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; 2192 } 2193 2194 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR 0x0000207d 2195 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 2196 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 2197 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 2198 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 2199 { 2200 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; 2201 } 2202 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 2203 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 2204 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 2205 { 2206 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; 2207 } 2208 2209 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000209c 2210 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 2211 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 2212 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 2213 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 2214 { 2215 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 2216 } 2217 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 2218 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 2219 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 2220 { 2221 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 2222 } 2223 2224 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000209d 2225 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 2226 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 2227 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 2228 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 2229 { 2230 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 2231 } 2232 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 2233 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 2234 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 2235 { 2236 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 2237 } 2238 2239 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR 0x0000209e 2240 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE 0x80000000 2241 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK 0x00007fff 2242 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT 0 2243 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val) 2244 { 2245 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK; 2246 } 2247 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK 0x7fff0000 2248 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT 16 2249 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val) 2250 { 2251 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK; 2252 } 2253 2254 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL 0x0000209f 2255 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE 0x80000000 2256 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK 0x00007fff 2257 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT 0 2258 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val) 2259 { 2260 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK; 2261 } 2262 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK 0x7fff0000 2263 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT 16 2264 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val) 2265 { 2266 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK; 2267 } 2268 2269 #define REG_A4XX_UCHE_CACHE_MODE_CONTROL 0x00000e80 2270 2271 #define REG_A4XX_UCHE_TRAP_BASE_LO 0x00000e83 2272 2273 #define REG_A4XX_UCHE_TRAP_BASE_HI 0x00000e84 2274 2275 #define REG_A4XX_UCHE_CACHE_STATUS 0x00000e88 2276 2277 #define REG_A4XX_UCHE_INVALIDATE0 0x00000e8a 2278 2279 #define REG_A4XX_UCHE_INVALIDATE1 0x00000e8b 2280 2281 #define REG_A4XX_UCHE_CACHE_WAYS_VFD 0x00000e8c 2282 2283 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e95 2284 2285 #define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD 0x00000e00 2286 2287 #define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL 0x00000e04 2288 2289 #define REG_A4XX_HLSQ_MODE_CONTROL 0x00000e05 2290 2291 #define REG_A4XX_HLSQ_PERF_PIPE_MASK 0x00000e0e 2292 2293 #define REG_A4XX_HLSQ_CONTROL_0_REG 0x000023c0 2294 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010 2295 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4 2296 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) 2297 { 2298 return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; 2299 } 2300 #define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040 2301 #define A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200 2302 #define A4XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400 2303 #define A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000 2304 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000 2305 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27 2306 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) 2307 { 2308 return ((val) << A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK; 2309 } 2310 #define A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000 2311 #define A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000 2312 #define A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000 2313 #define A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000 2314 2315 #define REG_A4XX_HLSQ_CONTROL_1_REG 0x000023c1 2316 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040 2317 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6 2318 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) 2319 { 2320 return ((val) << A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK; 2321 } 2322 #define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100 2323 #define A4XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200 2324 #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK 0x00ff0000 2325 #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT 16 2326 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val) 2327 { 2328 return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK; 2329 } 2330 #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK 0xff000000 2331 #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT 24 2332 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val) 2333 { 2334 return ((val) << A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK; 2335 } 2336 2337 #define REG_A4XX_HLSQ_CONTROL_2_REG 0x000023c2 2338 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000 2339 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26 2340 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) 2341 { 2342 return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK; 2343 } 2344 #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000003fc 2345 #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 2 2346 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) 2347 { 2348 return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; 2349 } 2350 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK 0x0003fc00 2351 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT 10 2352 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val) 2353 { 2354 return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK; 2355 } 2356 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK 0x03fc0000 2357 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT 18 2358 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val) 2359 { 2360 return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK; 2361 } 2362 2363 #define REG_A4XX_HLSQ_CONTROL_3_REG 0x000023c3 2364 #define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff 2365 #define A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0 2366 static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val) 2367 { 2368 return ((val) << A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_REGID__MASK; 2369 } 2370 2371 #define REG_A4XX_HLSQ_CONTROL_4_REG 0x000023c4 2372 2373 #define REG_A4XX_HLSQ_VS_CONTROL_REG 0x000023c5 2374 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 2375 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0 2376 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) 2377 { 2378 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK; 2379 } 2380 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 2381 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 2382 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 2383 { 2384 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 2385 } 2386 #define A4XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00010000 2387 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 2388 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 2389 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 2390 { 2391 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK; 2392 } 2393 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 2394 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24 2395 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) 2396 { 2397 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK; 2398 } 2399 2400 #define REG_A4XX_HLSQ_FS_CONTROL_REG 0x000023c6 2401 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 2402 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0 2403 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) 2404 { 2405 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK; 2406 } 2407 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 2408 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 2409 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 2410 { 2411 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 2412 } 2413 #define A4XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00010000 2414 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 2415 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 2416 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 2417 { 2418 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK; 2419 } 2420 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 2421 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24 2422 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) 2423 { 2424 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK; 2425 } 2426 2427 #define REG_A4XX_HLSQ_HS_CONTROL_REG 0x000023c7 2428 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 2429 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT 0 2430 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val) 2431 { 2432 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK; 2433 } 2434 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 2435 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 2436 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 2437 { 2438 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 2439 } 2440 #define A4XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00010000 2441 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 2442 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 2443 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 2444 { 2445 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK; 2446 } 2447 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 2448 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT 24 2449 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val) 2450 { 2451 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK; 2452 } 2453 2454 #define REG_A4XX_HLSQ_DS_CONTROL_REG 0x000023c8 2455 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 2456 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT 0 2457 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val) 2458 { 2459 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK; 2460 } 2461 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 2462 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 2463 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 2464 { 2465 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 2466 } 2467 #define A4XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00010000 2468 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 2469 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 2470 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 2471 { 2472 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK; 2473 } 2474 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 2475 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT 24 2476 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val) 2477 { 2478 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK; 2479 } 2480 2481 #define REG_A4XX_HLSQ_GS_CONTROL_REG 0x000023c9 2482 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 2483 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT 0 2484 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val) 2485 { 2486 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK; 2487 } 2488 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 2489 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 2490 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 2491 { 2492 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 2493 } 2494 #define A4XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00010000 2495 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 2496 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 2497 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 2498 { 2499 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK; 2500 } 2501 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 2502 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT 24 2503 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val) 2504 { 2505 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK; 2506 } 2507 2508 #define REG_A4XX_HLSQ_CS_CONTROL 0x000023ca 2509 2510 #define REG_A4XX_HLSQ_CL_NDRANGE_0 0x000023cd 2511 2512 #define REG_A4XX_HLSQ_CL_NDRANGE_1 0x000023ce 2513 2514 #define REG_A4XX_HLSQ_CL_NDRANGE_2 0x000023cf 2515 2516 #define REG_A4XX_HLSQ_CL_NDRANGE_3 0x000023d0 2517 2518 #define REG_A4XX_HLSQ_CL_NDRANGE_4 0x000023d1 2519 2520 #define REG_A4XX_HLSQ_CL_NDRANGE_5 0x000023d2 2521 2522 #define REG_A4XX_HLSQ_CL_NDRANGE_6 0x000023d3 2523 2524 #define REG_A4XX_HLSQ_CL_CONTROL_0 0x000023d4 2525 2526 #define REG_A4XX_HLSQ_CL_CONTROL_1 0x000023d5 2527 2528 #define REG_A4XX_HLSQ_CL_KERNEL_CONST 0x000023d6 2529 2530 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_X 0x000023d7 2531 2532 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Y 0x000023d8 2533 2534 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z 0x000023d9 2535 2536 #define REG_A4XX_HLSQ_CL_WG_OFFSET 0x000023da 2537 2538 #define REG_A4XX_HLSQ_UPDATE_CONTROL 0x000023db 2539 2540 #define REG_A4XX_PC_BINNING_COMMAND 0x00000d00 2541 #define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001 2542 2543 #define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c 2544 2545 #define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10 2546 2547 #define REG_A4XX_PC_PERFCTR_PC_SEL_7 0x00000d17 2548 2549 #define REG_A4XX_PC_BIN_BASE 0x000021c0 2550 2551 #define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4 2552 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK 0x0000000f 2553 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT 0 2554 static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val) 2555 { 2556 return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK; 2557 } 2558 #define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000 2559 #define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000 2560 #define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000 2561 2562 #define REG_A4XX_UNKNOWN_21C5 0x000021c5 2563 2564 #define REG_A4XX_PC_RESTART_INDEX 0x000021c6 2565 2566 #define REG_A4XX_PC_GS_PARAM 0x000021e5 2567 #define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff 2568 #define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0 2569 static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val) 2570 { 2571 return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK; 2572 } 2573 #define A4XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800 2574 #define A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11 2575 static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val) 2576 { 2577 return ((val) << A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A4XX_PC_GS_PARAM_INVOCATIONS__MASK; 2578 } 2579 #define A4XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000 2580 #define A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23 2581 static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val) 2582 { 2583 return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK; 2584 } 2585 #define A4XX_PC_GS_PARAM_LAYER 0x80000000 2586 2587 #define REG_A4XX_PC_HS_PARAM 0x000021e7 2588 #define A4XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f 2589 #define A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0 2590 static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val) 2591 { 2592 return ((val) << A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A4XX_PC_HS_PARAM_VERTICES_OUT__MASK; 2593 } 2594 #define A4XX_PC_HS_PARAM_SPACING__MASK 0x00600000 2595 #define A4XX_PC_HS_PARAM_SPACING__SHIFT 21 2596 static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val) 2597 { 2598 return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK; 2599 } 2600 #define A4XX_PC_HS_PARAM_PRIMTYPE__MASK 0x01800000 2601 #define A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT 23 2602 static inline uint32_t A4XX_PC_HS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val) 2603 { 2604 return ((val) << A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_HS_PARAM_PRIMTYPE__MASK; 2605 } 2606 2607 #define REG_A4XX_VBIF_VERSION 0x00003000 2608 2609 #define REG_A4XX_VBIF_CLKON 0x00003001 2610 #define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000001 2611 2612 #define REG_A4XX_VBIF_ABIT_SORT 0x0000301c 2613 2614 #define REG_A4XX_VBIF_ABIT_SORT_CONF 0x0000301d 2615 2616 #define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 2617 2618 #define REG_A4XX_VBIF_IN_RD_LIM_CONF0 0x0000302c 2619 2620 #define REG_A4XX_VBIF_IN_RD_LIM_CONF1 0x0000302d 2621 2622 #define REG_A4XX_VBIF_IN_WR_LIM_CONF0 0x00003030 2623 2624 #define REG_A4XX_VBIF_IN_WR_LIM_CONF1 0x00003031 2625 2626 #define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049 2627 2628 #define REG_A4XX_UNKNOWN_0CC5 0x00000cc5 2629 2630 #define REG_A4XX_UNKNOWN_0CC6 0x00000cc6 2631 2632 #define REG_A4XX_UNKNOWN_0D01 0x00000d01 2633 2634 #define REG_A4XX_UNKNOWN_0E42 0x00000e42 2635 2636 #define REG_A4XX_UNKNOWN_0EC2 0x00000ec2 2637 2638 #define REG_A4XX_UNKNOWN_2001 0x00002001 2639 2640 #define REG_A4XX_UNKNOWN_209B 0x0000209b 2641 2642 #define REG_A4XX_UNKNOWN_20EF 0x000020ef 2643 2644 #define REG_A4XX_UNKNOWN_20F0 0x000020f0 2645 2646 #define REG_A4XX_UNKNOWN_20F1 0x000020f1 2647 2648 #define REG_A4XX_UNKNOWN_20F2 0x000020f2 2649 2650 #define REG_A4XX_UNKNOWN_20F7 0x000020f7 2651 #define A4XX_UNKNOWN_20F7__MASK 0xffffffff 2652 #define A4XX_UNKNOWN_20F7__SHIFT 0 2653 static inline uint32_t A4XX_UNKNOWN_20F7(float val) 2654 { 2655 return ((fui(val)) << A4XX_UNKNOWN_20F7__SHIFT) & A4XX_UNKNOWN_20F7__MASK; 2656 } 2657 2658 #define REG_A4XX_UNKNOWN_2152 0x00002152 2659 2660 #define REG_A4XX_UNKNOWN_2153 0x00002153 2661 2662 #define REG_A4XX_UNKNOWN_2154 0x00002154 2663 2664 #define REG_A4XX_UNKNOWN_2155 0x00002155 2665 2666 #define REG_A4XX_UNKNOWN_2156 0x00002156 2667 2668 #define REG_A4XX_UNKNOWN_2157 0x00002157 2669 2670 #define REG_A4XX_UNKNOWN_21C3 0x000021c3 2671 2672 #define REG_A4XX_UNKNOWN_21E6 0x000021e6 2673 2674 #define REG_A4XX_UNKNOWN_2209 0x00002209 2675 2676 #define REG_A4XX_UNKNOWN_22D7 0x000022d7 2677 2678 #define REG_A4XX_UNKNOWN_2352 0x00002352 2679 2680 #define REG_A4XX_TEX_SAMP_0 0x00000000 2681 #define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 2682 #define A4XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 2683 #define A4XX_TEX_SAMP_0_XY_MAG__SHIFT 1 2684 static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val) 2685 { 2686 return ((val) << A4XX_TEX_SAMP_0_XY_MAG__SHIFT) & A4XX_TEX_SAMP_0_XY_MAG__MASK; 2687 } 2688 #define A4XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 2689 #define A4XX_TEX_SAMP_0_XY_MIN__SHIFT 3 2690 static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val) 2691 { 2692 return ((val) << A4XX_TEX_SAMP_0_XY_MIN__SHIFT) & A4XX_TEX_SAMP_0_XY_MIN__MASK; 2693 } 2694 #define A4XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 2695 #define A4XX_TEX_SAMP_0_WRAP_S__SHIFT 5 2696 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val) 2697 { 2698 return ((val) << A4XX_TEX_SAMP_0_WRAP_S__SHIFT) & A4XX_TEX_SAMP_0_WRAP_S__MASK; 2699 } 2700 #define A4XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 2701 #define A4XX_TEX_SAMP_0_WRAP_T__SHIFT 8 2702 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val) 2703 { 2704 return ((val) << A4XX_TEX_SAMP_0_WRAP_T__SHIFT) & A4XX_TEX_SAMP_0_WRAP_T__MASK; 2705 } 2706 #define A4XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 2707 #define A4XX_TEX_SAMP_0_WRAP_R__SHIFT 11 2708 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val) 2709 { 2710 return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK; 2711 } 2712 #define A4XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 2713 #define A4XX_TEX_SAMP_0_ANISO__SHIFT 14 2714 static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val) 2715 { 2716 return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK; 2717 } 2718 2719 #define REG_A4XX_TEX_SAMP_1 0x00000001 2720 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e 2721 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 2722 static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) 2723 { 2724 return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK; 2725 } 2726 #define A4XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 2727 #define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 2728 #define A4XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 2729 #define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 2730 static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val) 2731 { 2732 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK; 2733 } 2734 #define A4XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 2735 #define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 2736 static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val) 2737 { 2738 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK; 2739 } 2740 2741 #define REG_A4XX_TEX_CONST_0 0x00000000 2742 #define A4XX_TEX_CONST_0_TILED 0x00000001 2743 #define A4XX_TEX_CONST_0_SRGB 0x00000004 2744 #define A4XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 2745 #define A4XX_TEX_CONST_0_SWIZ_X__SHIFT 4 2746 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val) 2747 { 2748 return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) & A4XX_TEX_CONST_0_SWIZ_X__MASK; 2749 } 2750 #define A4XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 2751 #define A4XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 2752 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val) 2753 { 2754 return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Y__MASK; 2755 } 2756 #define A4XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 2757 #define A4XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 2758 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val) 2759 { 2760 return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Z__MASK; 2761 } 2762 #define A4XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 2763 #define A4XX_TEX_CONST_0_SWIZ_W__SHIFT 13 2764 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val) 2765 { 2766 return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK; 2767 } 2768 #define A4XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 2769 #define A4XX_TEX_CONST_0_MIPLVLS__SHIFT 16 2770 static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val) 2771 { 2772 return ((val) << A4XX_TEX_CONST_0_MIPLVLS__SHIFT) & A4XX_TEX_CONST_0_MIPLVLS__MASK; 2773 } 2774 #define A4XX_TEX_CONST_0_FMT__MASK 0x1fc00000 2775 #define A4XX_TEX_CONST_0_FMT__SHIFT 22 2776 static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val) 2777 { 2778 return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK; 2779 } 2780 #define A4XX_TEX_CONST_0_TYPE__MASK 0x60000000 2781 #define A4XX_TEX_CONST_0_TYPE__SHIFT 29 2782 static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val) 2783 { 2784 return ((val) << A4XX_TEX_CONST_0_TYPE__SHIFT) & A4XX_TEX_CONST_0_TYPE__MASK; 2785 } 2786 2787 #define REG_A4XX_TEX_CONST_1 0x00000001 2788 #define A4XX_TEX_CONST_1_HEIGHT__MASK 0x00007fff 2789 #define A4XX_TEX_CONST_1_HEIGHT__SHIFT 0 2790 static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val) 2791 { 2792 return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK; 2793 } 2794 #define A4XX_TEX_CONST_1_WIDTH__MASK 0x1fff8000 2795 #define A4XX_TEX_CONST_1_WIDTH__SHIFT 15 2796 static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val) 2797 { 2798 return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK; 2799 } 2800 2801 #define REG_A4XX_TEX_CONST_2 0x00000002 2802 #define A4XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f 2803 #define A4XX_TEX_CONST_2_FETCHSIZE__SHIFT 0 2804 static inline uint32_t A4XX_TEX_CONST_2_FETCHSIZE(enum a4xx_tex_fetchsize val) 2805 { 2806 return ((val) << A4XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A4XX_TEX_CONST_2_FETCHSIZE__MASK; 2807 } 2808 #define A4XX_TEX_CONST_2_PITCH__MASK 0x3ffffe00 2809 #define A4XX_TEX_CONST_2_PITCH__SHIFT 9 2810 static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val) 2811 { 2812 return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) & A4XX_TEX_CONST_2_PITCH__MASK; 2813 } 2814 #define A4XX_TEX_CONST_2_SWAP__MASK 0xc0000000 2815 #define A4XX_TEX_CONST_2_SWAP__SHIFT 30 2816 static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) 2817 { 2818 return ((val) << A4XX_TEX_CONST_2_SWAP__SHIFT) & A4XX_TEX_CONST_2_SWAP__MASK; 2819 } 2820 2821 #define REG_A4XX_TEX_CONST_3 0x00000003 2822 #define A4XX_TEX_CONST_3_LAYERSZ__MASK 0x00003fff 2823 #define A4XX_TEX_CONST_3_LAYERSZ__SHIFT 0 2824 static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val) 2825 { 2826 return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK; 2827 } 2828 #define A4XX_TEX_CONST_3_DEPTH__MASK 0x7ffc0000 2829 #define A4XX_TEX_CONST_3_DEPTH__SHIFT 18 2830 static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val) 2831 { 2832 return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK; 2833 } 2834 2835 #define REG_A4XX_TEX_CONST_4 0x00000004 2836 #define A4XX_TEX_CONST_4_LAYERSZ__MASK 0x0000000f 2837 #define A4XX_TEX_CONST_4_LAYERSZ__SHIFT 0 2838 static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val) 2839 { 2840 return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK; 2841 } 2842 #define A4XX_TEX_CONST_4_BASE__MASK 0xffffffe0 2843 #define A4XX_TEX_CONST_4_BASE__SHIFT 5 2844 static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val) 2845 { 2846 return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK; 2847 } 2848 2849 #define REG_A4XX_TEX_CONST_5 0x00000005 2850 2851 #define REG_A4XX_TEX_CONST_6 0x00000006 2852 2853 #define REG_A4XX_TEX_CONST_7 0x00000007 2854 2855 2856 #endif /* A4XX_XML */ 2857