1 #ifndef A4XX_XML 2 #define A4XX_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-01-30 18:25:22) 12 - /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2020-12-31 19:26:32) 13 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-06-21 15:24:24) 14 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14609 bytes, from 2021-11-24 23:05:10) 15 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 69086 bytes, from 2022-03-03 16:41:33) 16 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2021-11-24 23:05:10) 17 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113358 bytes, from 2022-01-31 23:06:21) 18 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149512 bytes, from 2022-01-31 23:06:21) 19 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx.xml ( 184954 bytes, from 2022-03-03 16:41:33) 20 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-07-22 15:21:56) 21 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-01-30 18:25:22) 22 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-07-22 15:21:56) 23 - /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-07-22 15:21:56) 24 25 Copyright (C) 2013-2022 by the following authors: 26 - Rob Clark <robdclark@gmail.com> (robclark) 27 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 28 29 Permission is hereby granted, free of charge, to any person obtaining 30 a copy of this software and associated documentation files (the 31 "Software"), to deal in the Software without restriction, including 32 without limitation the rights to use, copy, modify, merge, publish, 33 distribute, sublicense, and/or sell copies of the Software, and to 34 permit persons to whom the Software is furnished to do so, subject to 35 the following conditions: 36 37 The above copyright notice and this permission notice (including the 38 next paragraph) shall be included in all copies or substantial 39 portions of the Software. 40 41 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 42 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 43 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 44 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 45 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 46 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 47 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 48 */ 49 50 51 enum a4xx_color_fmt { 52 RB4_A8_UNORM = 1, 53 RB4_R8_UNORM = 2, 54 RB4_R8_SNORM = 3, 55 RB4_R8_UINT = 4, 56 RB4_R8_SINT = 5, 57 RB4_R4G4B4A4_UNORM = 8, 58 RB4_R5G5B5A1_UNORM = 10, 59 RB4_R5G6B5_UNORM = 14, 60 RB4_R8G8_UNORM = 15, 61 RB4_R8G8_SNORM = 16, 62 RB4_R8G8_UINT = 17, 63 RB4_R8G8_SINT = 18, 64 RB4_R16_UNORM = 19, 65 RB4_R16_SNORM = 20, 66 RB4_R16_FLOAT = 21, 67 RB4_R16_UINT = 22, 68 RB4_R16_SINT = 23, 69 RB4_R8G8B8_UNORM = 25, 70 RB4_R8G8B8A8_UNORM = 26, 71 RB4_R8G8B8A8_SNORM = 28, 72 RB4_R8G8B8A8_UINT = 29, 73 RB4_R8G8B8A8_SINT = 30, 74 RB4_R10G10B10A2_UNORM = 31, 75 RB4_R10G10B10A2_UINT = 34, 76 RB4_R11G11B10_FLOAT = 39, 77 RB4_R16G16_UNORM = 40, 78 RB4_R16G16_SNORM = 41, 79 RB4_R16G16_FLOAT = 42, 80 RB4_R16G16_UINT = 43, 81 RB4_R16G16_SINT = 44, 82 RB4_R32_FLOAT = 45, 83 RB4_R32_UINT = 46, 84 RB4_R32_SINT = 47, 85 RB4_R16G16B16A16_UNORM = 52, 86 RB4_R16G16B16A16_SNORM = 53, 87 RB4_R16G16B16A16_FLOAT = 54, 88 RB4_R16G16B16A16_UINT = 55, 89 RB4_R16G16B16A16_SINT = 56, 90 RB4_R32G32_FLOAT = 57, 91 RB4_R32G32_UINT = 58, 92 RB4_R32G32_SINT = 59, 93 RB4_R32G32B32A32_FLOAT = 60, 94 RB4_R32G32B32A32_UINT = 61, 95 RB4_R32G32B32A32_SINT = 62, 96 RB4_NONE = 255, 97 }; 98 99 enum a4xx_tile_mode { 100 TILE4_LINEAR = 0, 101 TILE4_2 = 2, 102 TILE4_3 = 3, 103 }; 104 105 enum a4xx_vtx_fmt { 106 VFMT4_32_FLOAT = 1, 107 VFMT4_32_32_FLOAT = 2, 108 VFMT4_32_32_32_FLOAT = 3, 109 VFMT4_32_32_32_32_FLOAT = 4, 110 VFMT4_16_FLOAT = 5, 111 VFMT4_16_16_FLOAT = 6, 112 VFMT4_16_16_16_FLOAT = 7, 113 VFMT4_16_16_16_16_FLOAT = 8, 114 VFMT4_32_FIXED = 9, 115 VFMT4_32_32_FIXED = 10, 116 VFMT4_32_32_32_FIXED = 11, 117 VFMT4_32_32_32_32_FIXED = 12, 118 VFMT4_11_11_10_FLOAT = 13, 119 VFMT4_16_SINT = 16, 120 VFMT4_16_16_SINT = 17, 121 VFMT4_16_16_16_SINT = 18, 122 VFMT4_16_16_16_16_SINT = 19, 123 VFMT4_16_UINT = 20, 124 VFMT4_16_16_UINT = 21, 125 VFMT4_16_16_16_UINT = 22, 126 VFMT4_16_16_16_16_UINT = 23, 127 VFMT4_16_SNORM = 24, 128 VFMT4_16_16_SNORM = 25, 129 VFMT4_16_16_16_SNORM = 26, 130 VFMT4_16_16_16_16_SNORM = 27, 131 VFMT4_16_UNORM = 28, 132 VFMT4_16_16_UNORM = 29, 133 VFMT4_16_16_16_UNORM = 30, 134 VFMT4_16_16_16_16_UNORM = 31, 135 VFMT4_32_UINT = 32, 136 VFMT4_32_32_UINT = 33, 137 VFMT4_32_32_32_UINT = 34, 138 VFMT4_32_32_32_32_UINT = 35, 139 VFMT4_32_SINT = 36, 140 VFMT4_32_32_SINT = 37, 141 VFMT4_32_32_32_SINT = 38, 142 VFMT4_32_32_32_32_SINT = 39, 143 VFMT4_8_UINT = 40, 144 VFMT4_8_8_UINT = 41, 145 VFMT4_8_8_8_UINT = 42, 146 VFMT4_8_8_8_8_UINT = 43, 147 VFMT4_8_UNORM = 44, 148 VFMT4_8_8_UNORM = 45, 149 VFMT4_8_8_8_UNORM = 46, 150 VFMT4_8_8_8_8_UNORM = 47, 151 VFMT4_8_SINT = 48, 152 VFMT4_8_8_SINT = 49, 153 VFMT4_8_8_8_SINT = 50, 154 VFMT4_8_8_8_8_SINT = 51, 155 VFMT4_8_SNORM = 52, 156 VFMT4_8_8_SNORM = 53, 157 VFMT4_8_8_8_SNORM = 54, 158 VFMT4_8_8_8_8_SNORM = 55, 159 VFMT4_10_10_10_2_UINT = 56, 160 VFMT4_10_10_10_2_UNORM = 57, 161 VFMT4_10_10_10_2_SINT = 58, 162 VFMT4_10_10_10_2_SNORM = 59, 163 VFMT4_2_10_10_10_UINT = 60, 164 VFMT4_2_10_10_10_UNORM = 61, 165 VFMT4_2_10_10_10_SINT = 62, 166 VFMT4_2_10_10_10_SNORM = 63, 167 VFMT4_NONE = 255, 168 }; 169 170 enum a4xx_tex_fmt { 171 TFMT4_A8_UNORM = 3, 172 TFMT4_8_UNORM = 4, 173 TFMT4_8_SNORM = 5, 174 TFMT4_8_UINT = 6, 175 TFMT4_8_SINT = 7, 176 TFMT4_4_4_4_4_UNORM = 8, 177 TFMT4_5_5_5_1_UNORM = 9, 178 TFMT4_5_6_5_UNORM = 11, 179 TFMT4_L8_A8_UNORM = 13, 180 TFMT4_8_8_UNORM = 14, 181 TFMT4_8_8_SNORM = 15, 182 TFMT4_8_8_UINT = 16, 183 TFMT4_8_8_SINT = 17, 184 TFMT4_16_UNORM = 18, 185 TFMT4_16_SNORM = 19, 186 TFMT4_16_FLOAT = 20, 187 TFMT4_16_UINT = 21, 188 TFMT4_16_SINT = 22, 189 TFMT4_8_8_8_8_UNORM = 28, 190 TFMT4_8_8_8_8_SNORM = 29, 191 TFMT4_8_8_8_8_UINT = 30, 192 TFMT4_8_8_8_8_SINT = 31, 193 TFMT4_9_9_9_E5_FLOAT = 32, 194 TFMT4_10_10_10_2_UNORM = 33, 195 TFMT4_10_10_10_2_UINT = 34, 196 TFMT4_11_11_10_FLOAT = 37, 197 TFMT4_16_16_UNORM = 38, 198 TFMT4_16_16_SNORM = 39, 199 TFMT4_16_16_FLOAT = 40, 200 TFMT4_16_16_UINT = 41, 201 TFMT4_16_16_SINT = 42, 202 TFMT4_32_FLOAT = 43, 203 TFMT4_32_UINT = 44, 204 TFMT4_32_SINT = 45, 205 TFMT4_16_16_16_16_UNORM = 51, 206 TFMT4_16_16_16_16_SNORM = 52, 207 TFMT4_16_16_16_16_FLOAT = 53, 208 TFMT4_16_16_16_16_UINT = 54, 209 TFMT4_16_16_16_16_SINT = 55, 210 TFMT4_32_32_FLOAT = 56, 211 TFMT4_32_32_UINT = 57, 212 TFMT4_32_32_SINT = 58, 213 TFMT4_32_32_32_FLOAT = 59, 214 TFMT4_32_32_32_UINT = 60, 215 TFMT4_32_32_32_SINT = 61, 216 TFMT4_32_32_32_32_FLOAT = 63, 217 TFMT4_32_32_32_32_UINT = 64, 218 TFMT4_32_32_32_32_SINT = 65, 219 TFMT4_X8Z24_UNORM = 71, 220 TFMT4_DXT1 = 86, 221 TFMT4_DXT3 = 87, 222 TFMT4_DXT5 = 88, 223 TFMT4_RGTC1_UNORM = 90, 224 TFMT4_RGTC1_SNORM = 91, 225 TFMT4_RGTC2_UNORM = 94, 226 TFMT4_RGTC2_SNORM = 95, 227 TFMT4_BPTC_UFLOAT = 97, 228 TFMT4_BPTC_FLOAT = 98, 229 TFMT4_BPTC = 99, 230 TFMT4_ATC_RGB = 100, 231 TFMT4_ATC_RGBA_EXPLICIT = 101, 232 TFMT4_ATC_RGBA_INTERPOLATED = 102, 233 TFMT4_ETC2_RG11_UNORM = 103, 234 TFMT4_ETC2_RG11_SNORM = 104, 235 TFMT4_ETC2_R11_UNORM = 105, 236 TFMT4_ETC2_R11_SNORM = 106, 237 TFMT4_ETC1 = 107, 238 TFMT4_ETC2_RGB8 = 108, 239 TFMT4_ETC2_RGBA8 = 109, 240 TFMT4_ETC2_RGB8A1 = 110, 241 TFMT4_ASTC_4x4 = 111, 242 TFMT4_ASTC_5x4 = 112, 243 TFMT4_ASTC_5x5 = 113, 244 TFMT4_ASTC_6x5 = 114, 245 TFMT4_ASTC_6x6 = 115, 246 TFMT4_ASTC_8x5 = 116, 247 TFMT4_ASTC_8x6 = 117, 248 TFMT4_ASTC_8x8 = 118, 249 TFMT4_ASTC_10x5 = 119, 250 TFMT4_ASTC_10x6 = 120, 251 TFMT4_ASTC_10x8 = 121, 252 TFMT4_ASTC_10x10 = 122, 253 TFMT4_ASTC_12x10 = 123, 254 TFMT4_ASTC_12x12 = 124, 255 TFMT4_NONE = 255, 256 }; 257 258 enum a4xx_depth_format { 259 DEPTH4_NONE = 0, 260 DEPTH4_16 = 1, 261 DEPTH4_24_8 = 2, 262 DEPTH4_32 = 3, 263 }; 264 265 enum a4xx_ccu_perfcounter_select { 266 CCU_BUSY_CYCLES = 0, 267 CCU_RB_DEPTH_RETURN_STALL = 2, 268 CCU_RB_COLOR_RETURN_STALL = 3, 269 CCU_DEPTH_BLOCKS = 6, 270 CCU_COLOR_BLOCKS = 7, 271 CCU_DEPTH_BLOCK_HIT = 8, 272 CCU_COLOR_BLOCK_HIT = 9, 273 CCU_DEPTH_FLAG1_COUNT = 10, 274 CCU_DEPTH_FLAG2_COUNT = 11, 275 CCU_DEPTH_FLAG3_COUNT = 12, 276 CCU_DEPTH_FLAG4_COUNT = 13, 277 CCU_COLOR_FLAG1_COUNT = 14, 278 CCU_COLOR_FLAG2_COUNT = 15, 279 CCU_COLOR_FLAG3_COUNT = 16, 280 CCU_COLOR_FLAG4_COUNT = 17, 281 CCU_PARTIAL_BLOCK_READ = 18, 282 }; 283 284 enum a4xx_cp_perfcounter_select { 285 CP_ALWAYS_COUNT = 0, 286 CP_BUSY = 1, 287 CP_PFP_IDLE = 2, 288 CP_PFP_BUSY_WORKING = 3, 289 CP_PFP_STALL_CYCLES_ANY = 4, 290 CP_PFP_STARVE_CYCLES_ANY = 5, 291 CP_PFP_STARVED_PER_LOAD_ADDR = 6, 292 CP_PFP_STALLED_PER_STORE_ADDR = 7, 293 CP_PFP_PC_PROFILE = 8, 294 CP_PFP_MATCH_PM4_PKT_PROFILE = 9, 295 CP_PFP_COND_INDIRECT_DISCARDED = 10, 296 CP_LONG_RESUMPTIONS = 11, 297 CP_RESUME_CYCLES = 12, 298 CP_RESUME_TO_BOUNDARY_CYCLES = 13, 299 CP_LONG_PREEMPTIONS = 14, 300 CP_PREEMPT_CYCLES = 15, 301 CP_PREEMPT_TO_BOUNDARY_CYCLES = 16, 302 CP_ME_FIFO_EMPTY_PFP_IDLE = 17, 303 CP_ME_FIFO_EMPTY_PFP_BUSY = 18, 304 CP_ME_FIFO_NOT_EMPTY_NOT_FULL = 19, 305 CP_ME_FIFO_FULL_ME_BUSY = 20, 306 CP_ME_FIFO_FULL_ME_NON_WORKING = 21, 307 CP_ME_WAITING_FOR_PACKETS = 22, 308 CP_ME_BUSY_WORKING = 23, 309 CP_ME_STARVE_CYCLES_ANY = 24, 310 CP_ME_STARVE_CYCLES_PER_PROFILE = 25, 311 CP_ME_STALL_CYCLES_PER_PROFILE = 26, 312 CP_ME_PC_PROFILE = 27, 313 CP_RCIU_FIFO_EMPTY = 28, 314 CP_RCIU_FIFO_NOT_EMPTY_NOT_FULL = 29, 315 CP_RCIU_FIFO_FULL = 30, 316 CP_RCIU_FIFO_FULL_NO_CONTEXT = 31, 317 CP_RCIU_FIFO_FULL_AHB_MASTER = 32, 318 CP_RCIU_FIFO_FULL_OTHER = 33, 319 CP_AHB_IDLE = 34, 320 CP_AHB_STALL_ON_GRANT_NO_SPLIT = 35, 321 CP_AHB_STALL_ON_GRANT_SPLIT = 36, 322 CP_AHB_STALL_ON_GRANT_SPLIT_PROFILE = 37, 323 CP_AHB_BUSY_WORKING = 38, 324 CP_AHB_BUSY_STALL_ON_HRDY = 39, 325 CP_AHB_BUSY_STALL_ON_HRDY_PROFILE = 40, 326 }; 327 328 enum a4xx_gras_ras_perfcounter_select { 329 RAS_SUPER_TILES = 0, 330 RAS_8X8_TILES = 1, 331 RAS_4X4_TILES = 2, 332 RAS_BUSY_CYCLES = 3, 333 RAS_STALL_CYCLES_BY_RB = 4, 334 RAS_STALL_CYCLES_BY_VSC = 5, 335 RAS_STARVE_CYCLES_BY_TSE = 6, 336 RAS_SUPERTILE_CYCLES = 7, 337 RAS_TILE_CYCLES = 8, 338 RAS_FULLY_COVERED_SUPER_TILES = 9, 339 RAS_FULLY_COVERED_8X8_TILES = 10, 340 RAS_4X4_PRIM = 11, 341 RAS_8X4_4X8_PRIM = 12, 342 RAS_8X8_PRIM = 13, 343 }; 344 345 enum a4xx_gras_tse_perfcounter_select { 346 TSE_INPUT_PRIM = 0, 347 TSE_INPUT_NULL_PRIM = 1, 348 TSE_TRIVAL_REJ_PRIM = 2, 349 TSE_CLIPPED_PRIM = 3, 350 TSE_NEW_PRIM = 4, 351 TSE_ZERO_AREA_PRIM = 5, 352 TSE_FACENESS_CULLED_PRIM = 6, 353 TSE_ZERO_PIXEL_PRIM = 7, 354 TSE_OUTPUT_NULL_PRIM = 8, 355 TSE_OUTPUT_VISIBLE_PRIM = 9, 356 TSE_PRE_CLIP_PRIM = 10, 357 TSE_POST_CLIP_PRIM = 11, 358 TSE_BUSY_CYCLES = 12, 359 TSE_PC_STARVE = 13, 360 TSE_RAS_STALL = 14, 361 TSE_STALL_BARYPLANE_FIFO_FULL = 15, 362 TSE_STALL_ZPLANE_FIFO_FULL = 16, 363 }; 364 365 enum a4xx_hlsq_perfcounter_select { 366 HLSQ_SP_VS_STAGE_CONSTANT = 0, 367 HLSQ_SP_VS_STAGE_INSTRUCTIONS = 1, 368 HLSQ_SP_FS_STAGE_CONSTANT = 2, 369 HLSQ_SP_FS_STAGE_INSTRUCTIONS = 3, 370 HLSQ_TP_STATE = 4, 371 HLSQ_QUADS = 5, 372 HLSQ_PIXELS = 6, 373 HLSQ_VERTICES = 7, 374 HLSQ_SP_VS_STAGE_DATA_BYTES = 13, 375 HLSQ_SP_FS_STAGE_DATA_BYTES = 14, 376 HLSQ_BUSY_CYCLES = 15, 377 HLSQ_STALL_CYCLES_SP_STATE = 16, 378 HLSQ_STALL_CYCLES_SP_VS_STAGE = 17, 379 HLSQ_STALL_CYCLES_SP_FS_STAGE = 18, 380 HLSQ_STALL_CYCLES_UCHE = 19, 381 HLSQ_RBBM_LOAD_CYCLES = 20, 382 HLSQ_DI_TO_VS_START_SP = 21, 383 HLSQ_DI_TO_FS_START_SP = 22, 384 HLSQ_VS_STAGE_START_TO_DONE_SP = 23, 385 HLSQ_FS_STAGE_START_TO_DONE_SP = 24, 386 HLSQ_SP_STATE_COPY_CYCLES_VS_STAGE = 25, 387 HLSQ_SP_STATE_COPY_CYCLES_FS_STAGE = 26, 388 HLSQ_UCHE_LATENCY_CYCLES = 27, 389 HLSQ_UCHE_LATENCY_COUNT = 28, 390 HLSQ_STARVE_CYCLES_VFD = 29, 391 }; 392 393 enum a4xx_pc_perfcounter_select { 394 PC_VIS_STREAMS_LOADED = 0, 395 PC_VPC_PRIMITIVES = 2, 396 PC_DEAD_PRIM = 3, 397 PC_LIVE_PRIM = 4, 398 PC_DEAD_DRAWCALLS = 5, 399 PC_LIVE_DRAWCALLS = 6, 400 PC_VERTEX_MISSES = 7, 401 PC_STALL_CYCLES_VFD = 9, 402 PC_STALL_CYCLES_TSE = 10, 403 PC_STALL_CYCLES_UCHE = 11, 404 PC_WORKING_CYCLES = 12, 405 PC_IA_VERTICES = 13, 406 PC_GS_PRIMITIVES = 14, 407 PC_HS_INVOCATIONS = 15, 408 PC_DS_INVOCATIONS = 16, 409 PC_DS_PRIMITIVES = 17, 410 PC_STARVE_CYCLES_FOR_INDEX = 20, 411 PC_STARVE_CYCLES_FOR_TESS_FACTOR = 21, 412 PC_STARVE_CYCLES_FOR_VIZ_STREAM = 22, 413 PC_STALL_CYCLES_TESS = 23, 414 PC_STARVE_CYCLES_FOR_POSITION = 24, 415 PC_MODE0_DRAWCALL = 25, 416 PC_MODE1_DRAWCALL = 26, 417 PC_MODE2_DRAWCALL = 27, 418 PC_MODE3_DRAWCALL = 28, 419 PC_MODE4_DRAWCALL = 29, 420 PC_PREDICATED_DEAD_DRAWCALL = 30, 421 PC_STALL_CYCLES_BY_TSE_ONLY = 31, 422 PC_STALL_CYCLES_BY_VPC_ONLY = 32, 423 PC_VPC_POS_DATA_TRANSACTION = 33, 424 PC_BUSY_CYCLES = 34, 425 PC_STARVE_CYCLES_DI = 35, 426 PC_STALL_CYCLES_VPC = 36, 427 TESS_WORKING_CYCLES = 37, 428 TESS_NUM_CYCLES_SETUP_WORKING = 38, 429 TESS_NUM_CYCLES_PTGEN_WORKING = 39, 430 TESS_NUM_CYCLES_CONNGEN_WORKING = 40, 431 TESS_BUSY_CYCLES = 41, 432 TESS_STARVE_CYCLES_PC = 42, 433 TESS_STALL_CYCLES_PC = 43, 434 }; 435 436 enum a4xx_pwr_perfcounter_select { 437 PWR_CORE_CLOCK_CYCLES = 0, 438 PWR_BUSY_CLOCK_CYCLES = 1, 439 }; 440 441 enum a4xx_rb_perfcounter_select { 442 RB_BUSY_CYCLES = 0, 443 RB_BUSY_CYCLES_BINNING = 1, 444 RB_BUSY_CYCLES_RENDERING = 2, 445 RB_BUSY_CYCLES_RESOLVE = 3, 446 RB_STARVE_CYCLES_BY_SP = 4, 447 RB_STARVE_CYCLES_BY_RAS = 5, 448 RB_STARVE_CYCLES_BY_MARB = 6, 449 RB_STALL_CYCLES_BY_MARB = 7, 450 RB_STALL_CYCLES_BY_HLSQ = 8, 451 RB_RB_RB_MARB_DATA = 9, 452 RB_SP_RB_QUAD = 10, 453 RB_RAS_RB_Z_QUADS = 11, 454 RB_GMEM_CH0_READ = 12, 455 RB_GMEM_CH1_READ = 13, 456 RB_GMEM_CH0_WRITE = 14, 457 RB_GMEM_CH1_WRITE = 15, 458 RB_CP_CONTEXT_DONE = 16, 459 RB_CP_CACHE_FLUSH = 17, 460 RB_CP_ZPASS_DONE = 18, 461 RB_STALL_FIFO0_FULL = 19, 462 RB_STALL_FIFO1_FULL = 20, 463 RB_STALL_FIFO2_FULL = 21, 464 RB_STALL_FIFO3_FULL = 22, 465 RB_RB_HLSQ_TRANSACTIONS = 23, 466 RB_Z_READ = 24, 467 RB_Z_WRITE = 25, 468 RB_C_READ = 26, 469 RB_C_WRITE = 27, 470 RB_C_READ_LATENCY = 28, 471 RB_Z_READ_LATENCY = 29, 472 RB_STALL_BY_UCHE = 30, 473 RB_MARB_UCHE_TRANSACTIONS = 31, 474 RB_CACHE_STALL_MISS = 32, 475 RB_CACHE_STALL_FIFO_FULL = 33, 476 RB_8BIT_BLENDER_UNITS_ACTIVE = 34, 477 RB_16BIT_BLENDER_UNITS_ACTIVE = 35, 478 RB_SAMPLER_UNITS_ACTIVE = 36, 479 RB_TOTAL_PASS = 38, 480 RB_Z_PASS = 39, 481 RB_Z_FAIL = 40, 482 RB_S_FAIL = 41, 483 RB_POWER0 = 42, 484 RB_POWER1 = 43, 485 RB_POWER2 = 44, 486 RB_POWER3 = 45, 487 RB_POWER4 = 46, 488 RB_POWER5 = 47, 489 RB_POWER6 = 48, 490 RB_POWER7 = 49, 491 }; 492 493 enum a4xx_rbbm_perfcounter_select { 494 RBBM_ALWAYS_ON = 0, 495 RBBM_VBIF_BUSY = 1, 496 RBBM_TSE_BUSY = 2, 497 RBBM_RAS_BUSY = 3, 498 RBBM_PC_DCALL_BUSY = 4, 499 RBBM_PC_VSD_BUSY = 5, 500 RBBM_VFD_BUSY = 6, 501 RBBM_VPC_BUSY = 7, 502 RBBM_UCHE_BUSY = 8, 503 RBBM_VSC_BUSY = 9, 504 RBBM_HLSQ_BUSY = 10, 505 RBBM_ANY_RB_BUSY = 11, 506 RBBM_ANY_TPL1_BUSY = 12, 507 RBBM_ANY_SP_BUSY = 13, 508 RBBM_ANY_MARB_BUSY = 14, 509 RBBM_ANY_ARB_BUSY = 15, 510 RBBM_AHB_STATUS_BUSY = 16, 511 RBBM_AHB_STATUS_STALLED = 17, 512 RBBM_AHB_STATUS_TXFR = 18, 513 RBBM_AHB_STATUS_TXFR_SPLIT = 19, 514 RBBM_AHB_STATUS_TXFR_ERROR = 20, 515 RBBM_AHB_STATUS_LONG_STALL = 21, 516 RBBM_STATUS_MASKED = 22, 517 RBBM_CP_BUSY_GFX_CORE_IDLE = 23, 518 RBBM_TESS_BUSY = 24, 519 RBBM_COM_BUSY = 25, 520 RBBM_DCOM_BUSY = 32, 521 RBBM_ANY_CCU_BUSY = 33, 522 RBBM_DPM_BUSY = 34, 523 }; 524 525 enum a4xx_sp_perfcounter_select { 526 SP_LM_LOAD_INSTRUCTIONS = 0, 527 SP_LM_STORE_INSTRUCTIONS = 1, 528 SP_LM_ATOMICS = 2, 529 SP_GM_LOAD_INSTRUCTIONS = 3, 530 SP_GM_STORE_INSTRUCTIONS = 4, 531 SP_GM_ATOMICS = 5, 532 SP_VS_STAGE_TEX_INSTRUCTIONS = 6, 533 SP_VS_STAGE_CFLOW_INSTRUCTIONS = 7, 534 SP_VS_STAGE_EFU_INSTRUCTIONS = 8, 535 SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 9, 536 SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 10, 537 SP_FS_STAGE_TEX_INSTRUCTIONS = 11, 538 SP_FS_STAGE_CFLOW_INSTRUCTIONS = 12, 539 SP_FS_STAGE_EFU_INSTRUCTIONS = 13, 540 SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 14, 541 SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 15, 542 SP_VS_INSTRUCTIONS = 17, 543 SP_FS_INSTRUCTIONS = 18, 544 SP_ADDR_LOCK_COUNT = 19, 545 SP_UCHE_READ_TRANS = 20, 546 SP_UCHE_WRITE_TRANS = 21, 547 SP_EXPORT_VPC_TRANS = 22, 548 SP_EXPORT_RB_TRANS = 23, 549 SP_PIXELS_KILLED = 24, 550 SP_ICL1_REQUESTS = 25, 551 SP_ICL1_MISSES = 26, 552 SP_ICL0_REQUESTS = 27, 553 SP_ICL0_MISSES = 28, 554 SP_ALU_WORKING_CYCLES = 29, 555 SP_EFU_WORKING_CYCLES = 30, 556 SP_STALL_CYCLES_BY_VPC = 31, 557 SP_STALL_CYCLES_BY_TP = 32, 558 SP_STALL_CYCLES_BY_UCHE = 33, 559 SP_STALL_CYCLES_BY_RB = 34, 560 SP_BUSY_CYCLES = 35, 561 SP_HS_INSTRUCTIONS = 36, 562 SP_DS_INSTRUCTIONS = 37, 563 SP_GS_INSTRUCTIONS = 38, 564 SP_CS_INSTRUCTIONS = 39, 565 SP_SCHEDULER_NON_WORKING = 40, 566 SP_WAVE_CONTEXTS = 41, 567 SP_WAVE_CONTEXT_CYCLES = 42, 568 SP_POWER0 = 43, 569 SP_POWER1 = 44, 570 SP_POWER2 = 45, 571 SP_POWER3 = 46, 572 SP_POWER4 = 47, 573 SP_POWER5 = 48, 574 SP_POWER6 = 49, 575 SP_POWER7 = 50, 576 SP_POWER8 = 51, 577 SP_POWER9 = 52, 578 SP_POWER10 = 53, 579 SP_POWER11 = 54, 580 SP_POWER12 = 55, 581 SP_POWER13 = 56, 582 SP_POWER14 = 57, 583 SP_POWER15 = 58, 584 }; 585 586 enum a4xx_tp_perfcounter_select { 587 TP_L1_REQUESTS = 0, 588 TP_L1_MISSES = 1, 589 TP_QUADS_OFFSET = 8, 590 TP_QUAD_SHADOW = 9, 591 TP_QUADS_ARRAY = 10, 592 TP_QUADS_GRADIENT = 11, 593 TP_QUADS_1D2D = 12, 594 TP_QUADS_3DCUBE = 13, 595 TP_BUSY_CYCLES = 16, 596 TP_STALL_CYCLES_BY_ARB = 17, 597 TP_STATE_CACHE_REQUESTS = 20, 598 TP_STATE_CACHE_MISSES = 21, 599 TP_POWER0 = 22, 600 TP_POWER1 = 23, 601 TP_POWER2 = 24, 602 TP_POWER3 = 25, 603 TP_POWER4 = 26, 604 TP_POWER5 = 27, 605 TP_POWER6 = 28, 606 TP_POWER7 = 29, 607 }; 608 609 enum a4xx_uche_perfcounter_select { 610 UCHE_VBIF_READ_BEATS_TP = 0, 611 UCHE_VBIF_READ_BEATS_VFD = 1, 612 UCHE_VBIF_READ_BEATS_HLSQ = 2, 613 UCHE_VBIF_READ_BEATS_MARB = 3, 614 UCHE_VBIF_READ_BEATS_SP = 4, 615 UCHE_READ_REQUESTS_TP = 5, 616 UCHE_READ_REQUESTS_VFD = 6, 617 UCHE_READ_REQUESTS_HLSQ = 7, 618 UCHE_READ_REQUESTS_MARB = 8, 619 UCHE_READ_REQUESTS_SP = 9, 620 UCHE_WRITE_REQUESTS_MARB = 10, 621 UCHE_WRITE_REQUESTS_SP = 11, 622 UCHE_TAG_CHECK_FAILS = 12, 623 UCHE_EVICTS = 13, 624 UCHE_FLUSHES = 14, 625 UCHE_VBIF_LATENCY_CYCLES = 15, 626 UCHE_VBIF_LATENCY_SAMPLES = 16, 627 UCHE_BUSY_CYCLES = 17, 628 UCHE_VBIF_READ_BEATS_PC = 18, 629 UCHE_READ_REQUESTS_PC = 19, 630 UCHE_WRITE_REQUESTS_VPC = 20, 631 UCHE_STALL_BY_VBIF = 21, 632 UCHE_WRITE_REQUESTS_VSC = 22, 633 UCHE_POWER0 = 23, 634 UCHE_POWER1 = 24, 635 UCHE_POWER2 = 25, 636 UCHE_POWER3 = 26, 637 UCHE_POWER4 = 27, 638 UCHE_POWER5 = 28, 639 UCHE_POWER6 = 29, 640 UCHE_POWER7 = 30, 641 }; 642 643 enum a4xx_vbif_perfcounter_select { 644 AXI_READ_REQUESTS_ID_0 = 0, 645 AXI_READ_REQUESTS_ID_1 = 1, 646 AXI_READ_REQUESTS_ID_2 = 2, 647 AXI_READ_REQUESTS_ID_3 = 3, 648 AXI_READ_REQUESTS_ID_4 = 4, 649 AXI_READ_REQUESTS_ID_5 = 5, 650 AXI_READ_REQUESTS_ID_6 = 6, 651 AXI_READ_REQUESTS_ID_7 = 7, 652 AXI_READ_REQUESTS_ID_8 = 8, 653 AXI_READ_REQUESTS_ID_9 = 9, 654 AXI_READ_REQUESTS_ID_10 = 10, 655 AXI_READ_REQUESTS_ID_11 = 11, 656 AXI_READ_REQUESTS_ID_12 = 12, 657 AXI_READ_REQUESTS_ID_13 = 13, 658 AXI_READ_REQUESTS_ID_14 = 14, 659 AXI_READ_REQUESTS_ID_15 = 15, 660 AXI0_READ_REQUESTS_TOTAL = 16, 661 AXI1_READ_REQUESTS_TOTAL = 17, 662 AXI2_READ_REQUESTS_TOTAL = 18, 663 AXI3_READ_REQUESTS_TOTAL = 19, 664 AXI_READ_REQUESTS_TOTAL = 20, 665 AXI_WRITE_REQUESTS_ID_0 = 21, 666 AXI_WRITE_REQUESTS_ID_1 = 22, 667 AXI_WRITE_REQUESTS_ID_2 = 23, 668 AXI_WRITE_REQUESTS_ID_3 = 24, 669 AXI_WRITE_REQUESTS_ID_4 = 25, 670 AXI_WRITE_REQUESTS_ID_5 = 26, 671 AXI_WRITE_REQUESTS_ID_6 = 27, 672 AXI_WRITE_REQUESTS_ID_7 = 28, 673 AXI_WRITE_REQUESTS_ID_8 = 29, 674 AXI_WRITE_REQUESTS_ID_9 = 30, 675 AXI_WRITE_REQUESTS_ID_10 = 31, 676 AXI_WRITE_REQUESTS_ID_11 = 32, 677 AXI_WRITE_REQUESTS_ID_12 = 33, 678 AXI_WRITE_REQUESTS_ID_13 = 34, 679 AXI_WRITE_REQUESTS_ID_14 = 35, 680 AXI_WRITE_REQUESTS_ID_15 = 36, 681 AXI0_WRITE_REQUESTS_TOTAL = 37, 682 AXI1_WRITE_REQUESTS_TOTAL = 38, 683 AXI2_WRITE_REQUESTS_TOTAL = 39, 684 AXI3_WRITE_REQUESTS_TOTAL = 40, 685 AXI_WRITE_REQUESTS_TOTAL = 41, 686 AXI_TOTAL_REQUESTS = 42, 687 AXI_READ_DATA_BEATS_ID_0 = 43, 688 AXI_READ_DATA_BEATS_ID_1 = 44, 689 AXI_READ_DATA_BEATS_ID_2 = 45, 690 AXI_READ_DATA_BEATS_ID_3 = 46, 691 AXI_READ_DATA_BEATS_ID_4 = 47, 692 AXI_READ_DATA_BEATS_ID_5 = 48, 693 AXI_READ_DATA_BEATS_ID_6 = 49, 694 AXI_READ_DATA_BEATS_ID_7 = 50, 695 AXI_READ_DATA_BEATS_ID_8 = 51, 696 AXI_READ_DATA_BEATS_ID_9 = 52, 697 AXI_READ_DATA_BEATS_ID_10 = 53, 698 AXI_READ_DATA_BEATS_ID_11 = 54, 699 AXI_READ_DATA_BEATS_ID_12 = 55, 700 AXI_READ_DATA_BEATS_ID_13 = 56, 701 AXI_READ_DATA_BEATS_ID_14 = 57, 702 AXI_READ_DATA_BEATS_ID_15 = 58, 703 AXI0_READ_DATA_BEATS_TOTAL = 59, 704 AXI1_READ_DATA_BEATS_TOTAL = 60, 705 AXI2_READ_DATA_BEATS_TOTAL = 61, 706 AXI3_READ_DATA_BEATS_TOTAL = 62, 707 AXI_READ_DATA_BEATS_TOTAL = 63, 708 AXI_WRITE_DATA_BEATS_ID_0 = 64, 709 AXI_WRITE_DATA_BEATS_ID_1 = 65, 710 AXI_WRITE_DATA_BEATS_ID_2 = 66, 711 AXI_WRITE_DATA_BEATS_ID_3 = 67, 712 AXI_WRITE_DATA_BEATS_ID_4 = 68, 713 AXI_WRITE_DATA_BEATS_ID_5 = 69, 714 AXI_WRITE_DATA_BEATS_ID_6 = 70, 715 AXI_WRITE_DATA_BEATS_ID_7 = 71, 716 AXI_WRITE_DATA_BEATS_ID_8 = 72, 717 AXI_WRITE_DATA_BEATS_ID_9 = 73, 718 AXI_WRITE_DATA_BEATS_ID_10 = 74, 719 AXI_WRITE_DATA_BEATS_ID_11 = 75, 720 AXI_WRITE_DATA_BEATS_ID_12 = 76, 721 AXI_WRITE_DATA_BEATS_ID_13 = 77, 722 AXI_WRITE_DATA_BEATS_ID_14 = 78, 723 AXI_WRITE_DATA_BEATS_ID_15 = 79, 724 AXI0_WRITE_DATA_BEATS_TOTAL = 80, 725 AXI1_WRITE_DATA_BEATS_TOTAL = 81, 726 AXI2_WRITE_DATA_BEATS_TOTAL = 82, 727 AXI3_WRITE_DATA_BEATS_TOTAL = 83, 728 AXI_WRITE_DATA_BEATS_TOTAL = 84, 729 AXI_DATA_BEATS_TOTAL = 85, 730 CYCLES_HELD_OFF_ID_0 = 86, 731 CYCLES_HELD_OFF_ID_1 = 87, 732 CYCLES_HELD_OFF_ID_2 = 88, 733 CYCLES_HELD_OFF_ID_3 = 89, 734 CYCLES_HELD_OFF_ID_4 = 90, 735 CYCLES_HELD_OFF_ID_5 = 91, 736 CYCLES_HELD_OFF_ID_6 = 92, 737 CYCLES_HELD_OFF_ID_7 = 93, 738 CYCLES_HELD_OFF_ID_8 = 94, 739 CYCLES_HELD_OFF_ID_9 = 95, 740 CYCLES_HELD_OFF_ID_10 = 96, 741 CYCLES_HELD_OFF_ID_11 = 97, 742 CYCLES_HELD_OFF_ID_12 = 98, 743 CYCLES_HELD_OFF_ID_13 = 99, 744 CYCLES_HELD_OFF_ID_14 = 100, 745 CYCLES_HELD_OFF_ID_15 = 101, 746 AXI_READ_REQUEST_HELD_OFF = 102, 747 AXI_WRITE_REQUEST_HELD_OFF = 103, 748 AXI_REQUEST_HELD_OFF = 104, 749 AXI_WRITE_DATA_HELD_OFF = 105, 750 OCMEM_AXI_READ_REQUEST_HELD_OFF = 106, 751 OCMEM_AXI_WRITE_REQUEST_HELD_OFF = 107, 752 OCMEM_AXI_REQUEST_HELD_OFF = 108, 753 OCMEM_AXI_WRITE_DATA_HELD_OFF = 109, 754 ELAPSED_CYCLES_DDR = 110, 755 ELAPSED_CYCLES_OCMEM = 111, 756 }; 757 758 enum a4xx_vfd_perfcounter_select { 759 VFD_UCHE_BYTE_FETCHED = 0, 760 VFD_UCHE_TRANS = 1, 761 VFD_FETCH_INSTRUCTIONS = 3, 762 VFD_BUSY_CYCLES = 5, 763 VFD_STALL_CYCLES_UCHE = 6, 764 VFD_STALL_CYCLES_HLSQ = 7, 765 VFD_STALL_CYCLES_VPC_BYPASS = 8, 766 VFD_STALL_CYCLES_VPC_ALLOC = 9, 767 VFD_MODE_0_FIBERS = 13, 768 VFD_MODE_1_FIBERS = 14, 769 VFD_MODE_2_FIBERS = 15, 770 VFD_MODE_3_FIBERS = 16, 771 VFD_MODE_4_FIBERS = 17, 772 VFD_BFIFO_STALL = 18, 773 VFD_NUM_VERTICES_TOTAL = 19, 774 VFD_PACKER_FULL = 20, 775 VFD_UCHE_REQUEST_FIFO_FULL = 21, 776 VFD_STARVE_CYCLES_PC = 22, 777 VFD_STARVE_CYCLES_UCHE = 23, 778 }; 779 780 enum a4xx_vpc_perfcounter_select { 781 VPC_SP_LM_COMPONENTS = 2, 782 VPC_SP0_LM_BYTES = 3, 783 VPC_SP1_LM_BYTES = 4, 784 VPC_SP2_LM_BYTES = 5, 785 VPC_SP3_LM_BYTES = 6, 786 VPC_WORKING_CYCLES = 7, 787 VPC_STALL_CYCLES_LM = 8, 788 VPC_STARVE_CYCLES_RAS = 9, 789 VPC_STREAMOUT_CYCLES = 10, 790 VPC_UCHE_TRANSACTIONS = 12, 791 VPC_STALL_CYCLES_UCHE = 13, 792 VPC_BUSY_CYCLES = 14, 793 VPC_STARVE_CYCLES_SP = 15, 794 }; 795 796 enum a4xx_vsc_perfcounter_select { 797 VSC_BUSY_CYCLES = 0, 798 VSC_WORKING_CYCLES = 1, 799 VSC_STALL_CYCLES_UCHE = 2, 800 VSC_STARVE_CYCLES_RAS = 3, 801 VSC_EOT_NUM = 4, 802 }; 803 804 enum a4xx_tex_filter { 805 A4XX_TEX_NEAREST = 0, 806 A4XX_TEX_LINEAR = 1, 807 A4XX_TEX_ANISO = 2, 808 }; 809 810 enum a4xx_tex_clamp { 811 A4XX_TEX_REPEAT = 0, 812 A4XX_TEX_CLAMP_TO_EDGE = 1, 813 A4XX_TEX_MIRROR_REPEAT = 2, 814 A4XX_TEX_CLAMP_TO_BORDER = 3, 815 A4XX_TEX_MIRROR_CLAMP = 4, 816 }; 817 818 enum a4xx_tex_aniso { 819 A4XX_TEX_ANISO_1 = 0, 820 A4XX_TEX_ANISO_2 = 1, 821 A4XX_TEX_ANISO_4 = 2, 822 A4XX_TEX_ANISO_8 = 3, 823 A4XX_TEX_ANISO_16 = 4, 824 }; 825 826 enum a4xx_tex_swiz { 827 A4XX_TEX_X = 0, 828 A4XX_TEX_Y = 1, 829 A4XX_TEX_Z = 2, 830 A4XX_TEX_W = 3, 831 A4XX_TEX_ZERO = 4, 832 A4XX_TEX_ONE = 5, 833 }; 834 835 enum a4xx_tex_type { 836 A4XX_TEX_1D = 0, 837 A4XX_TEX_2D = 1, 838 A4XX_TEX_CUBE = 2, 839 A4XX_TEX_3D = 3, 840 A4XX_TEX_BUFFER = 4, 841 }; 842 843 #define A4XX_CGC_HLSQ_EARLY_CYC__MASK 0x00700000 844 #define A4XX_CGC_HLSQ_EARLY_CYC__SHIFT 20 845 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) 846 { 847 return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK; 848 } 849 #define A4XX_INT0_RBBM_GPU_IDLE 0x00000001 850 #define A4XX_INT0_RBBM_AHB_ERROR 0x00000002 851 #define A4XX_INT0_RBBM_REG_TIMEOUT 0x00000004 852 #define A4XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 853 #define A4XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 854 #define A4XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020 855 #define A4XX_INT0_VFD_ERROR 0x00000040 856 #define A4XX_INT0_CP_SW_INT 0x00000080 857 #define A4XX_INT0_CP_T0_PACKET_IN_IB 0x00000100 858 #define A4XX_INT0_CP_OPCODE_ERROR 0x00000200 859 #define A4XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400 860 #define A4XX_INT0_CP_HW_FAULT 0x00000800 861 #define A4XX_INT0_CP_DMA 0x00001000 862 #define A4XX_INT0_CP_IB2_INT 0x00002000 863 #define A4XX_INT0_CP_IB1_INT 0x00004000 864 #define A4XX_INT0_CP_RB_INT 0x00008000 865 #define A4XX_INT0_CP_REG_PROTECT_FAULT 0x00010000 866 #define A4XX_INT0_CP_RB_DONE_TS 0x00020000 867 #define A4XX_INT0_CP_VS_DONE_TS 0x00040000 868 #define A4XX_INT0_CP_PS_DONE_TS 0x00080000 869 #define A4XX_INT0_CACHE_FLUSH_TS 0x00100000 870 #define A4XX_INT0_CP_AHB_ERROR_HALT 0x00200000 871 #define A4XX_INT0_MISC_HANG_DETECT 0x01000000 872 #define A4XX_INT0_UCHE_OOB_ACCESS 0x02000000 873 #define REG_A4XX_RB_GMEM_BASE_ADDR 0x00000cc0 874 875 #define REG_A4XX_RB_PERFCTR_RB_SEL_0 0x00000cc7 876 877 #define REG_A4XX_RB_PERFCTR_RB_SEL_1 0x00000cc8 878 879 #define REG_A4XX_RB_PERFCTR_RB_SEL_2 0x00000cc9 880 881 #define REG_A4XX_RB_PERFCTR_RB_SEL_3 0x00000cca 882 883 #define REG_A4XX_RB_PERFCTR_RB_SEL_4 0x00000ccb 884 885 #define REG_A4XX_RB_PERFCTR_RB_SEL_5 0x00000ccc 886 887 #define REG_A4XX_RB_PERFCTR_RB_SEL_6 0x00000ccd 888 889 #define REG_A4XX_RB_PERFCTR_RB_SEL_7 0x00000cce 890 891 #define REG_A4XX_RB_PERFCTR_CCU_SEL_0 0x00000ccf 892 893 #define REG_A4XX_RB_PERFCTR_CCU_SEL_1 0x00000cd0 894 895 #define REG_A4XX_RB_PERFCTR_CCU_SEL_2 0x00000cd1 896 897 #define REG_A4XX_RB_PERFCTR_CCU_SEL_3 0x00000cd2 898 899 #define REG_A4XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0 900 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff 901 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0 902 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) 903 { 904 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK; 905 } 906 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x3fff0000 907 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 16 908 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) 909 { 910 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK; 911 } 912 913 #define REG_A4XX_RB_CLEAR_COLOR_DW0 0x000020cc 914 915 #define REG_A4XX_RB_CLEAR_COLOR_DW1 0x000020cd 916 917 #define REG_A4XX_RB_CLEAR_COLOR_DW2 0x000020ce 918 919 #define REG_A4XX_RB_CLEAR_COLOR_DW3 0x000020cf 920 921 #define REG_A4XX_RB_MODE_CONTROL 0x000020a0 922 #define A4XX_RB_MODE_CONTROL_WIDTH__MASK 0x0000003f 923 #define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT 0 924 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) 925 { 926 return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK; 927 } 928 #define A4XX_RB_MODE_CONTROL_HEIGHT__MASK 0x00003f00 929 #define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT 8 930 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) 931 { 932 return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK; 933 } 934 #define A4XX_RB_MODE_CONTROL_ENABLE_GMEM 0x00010000 935 936 #define REG_A4XX_RB_RENDER_CONTROL 0x000020a1 937 #define A4XX_RB_RENDER_CONTROL_BINNING_PASS 0x00000001 938 #define A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00000020 939 940 #define REG_A4XX_RB_MSAA_CONTROL 0x000020a2 941 #define A4XX_RB_MSAA_CONTROL_DISABLE 0x00001000 942 #define A4XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000e000 943 #define A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 13 944 static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val) 945 { 946 return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK; 947 } 948 949 #define REG_A4XX_RB_RENDER_CONTROL2 0x000020a3 950 #define A4XX_RB_RENDER_CONTROL2_COORD_MASK__MASK 0x0000000f 951 #define A4XX_RB_RENDER_CONTROL2_COORD_MASK__SHIFT 0 952 static inline uint32_t A4XX_RB_RENDER_CONTROL2_COORD_MASK(uint32_t val) 953 { 954 return ((val) << A4XX_RB_RENDER_CONTROL2_COORD_MASK__SHIFT) & A4XX_RB_RENDER_CONTROL2_COORD_MASK__MASK; 955 } 956 #define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK 0x00000010 957 #define A4XX_RB_RENDER_CONTROL2_FACENESS 0x00000020 958 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID 0x00000040 959 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK 0x00000380 960 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT 7 961 static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val) 962 { 963 return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK; 964 } 965 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR 0x00000800 966 #define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_PIXEL 0x00001000 967 #define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_CENTROID 0x00002000 968 #define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_SAMPLE 0x00004000 969 #define A4XX_RB_RENDER_CONTROL2_SIZE 0x00008000 970 971 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; } 972 973 static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; } 974 #define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008 975 #define A4XX_RB_MRT_CONTROL_BLEND 0x00000010 976 #define A4XX_RB_MRT_CONTROL_BLEND2 0x00000020 977 #define A4XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000040 978 #define A4XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00 979 #define A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8 980 static inline uint32_t A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) 981 { 982 return ((val) << A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A4XX_RB_MRT_CONTROL_ROP_CODE__MASK; 983 } 984 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000 985 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24 986 static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 987 { 988 return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 989 } 990 991 static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; } 992 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f 993 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 994 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val) 995 { 996 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 997 } 998 #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0 999 #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6 1000 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val) 1001 { 1002 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 1003 } 1004 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00000600 1005 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 9 1006 static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 1007 { 1008 return ((val) << A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK; 1009 } 1010 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00001800 1011 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 11 1012 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 1013 { 1014 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 1015 } 1016 #define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00002000 1017 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xffffc000 1018 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 14 1019 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) 1020 { 1021 return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; 1022 } 1023 1024 static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; } 1025 1026 static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; } 1027 #define A4XX_RB_MRT_CONTROL3_STRIDE__MASK 0x03fffff8 1028 #define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT 3 1029 static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val) 1030 { 1031 return ((val) << A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT) & A4XX_RB_MRT_CONTROL3_STRIDE__MASK; 1032 } 1033 1034 static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; } 1035 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 1036 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 1037 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 1038 { 1039 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 1040 } 1041 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 1042 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 1043 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 1044 { 1045 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 1046 } 1047 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 1048 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 1049 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 1050 { 1051 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 1052 } 1053 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 1054 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 1055 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 1056 { 1057 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 1058 } 1059 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 1060 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 1061 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 1062 { 1063 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 1064 } 1065 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 1066 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 1067 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 1068 { 1069 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 1070 } 1071 1072 #define REG_A4XX_RB_BLEND_RED 0x000020f0 1073 #define A4XX_RB_BLEND_RED_UINT__MASK 0x000000ff 1074 #define A4XX_RB_BLEND_RED_UINT__SHIFT 0 1075 static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val) 1076 { 1077 return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK; 1078 } 1079 #define A4XX_RB_BLEND_RED_SINT__MASK 0x0000ff00 1080 #define A4XX_RB_BLEND_RED_SINT__SHIFT 8 1081 static inline uint32_t A4XX_RB_BLEND_RED_SINT(uint32_t val) 1082 { 1083 return ((val) << A4XX_RB_BLEND_RED_SINT__SHIFT) & A4XX_RB_BLEND_RED_SINT__MASK; 1084 } 1085 #define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 1086 #define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16 1087 static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val) 1088 { 1089 return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK; 1090 } 1091 1092 #define REG_A4XX_RB_BLEND_RED_F32 0x000020f1 1093 #define A4XX_RB_BLEND_RED_F32__MASK 0xffffffff 1094 #define A4XX_RB_BLEND_RED_F32__SHIFT 0 1095 static inline uint32_t A4XX_RB_BLEND_RED_F32(float val) 1096 { 1097 return ((fui(val)) << A4XX_RB_BLEND_RED_F32__SHIFT) & A4XX_RB_BLEND_RED_F32__MASK; 1098 } 1099 1100 #define REG_A4XX_RB_BLEND_GREEN 0x000020f2 1101 #define A4XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff 1102 #define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0 1103 static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val) 1104 { 1105 return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK; 1106 } 1107 #define A4XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00 1108 #define A4XX_RB_BLEND_GREEN_SINT__SHIFT 8 1109 static inline uint32_t A4XX_RB_BLEND_GREEN_SINT(uint32_t val) 1110 { 1111 return ((val) << A4XX_RB_BLEND_GREEN_SINT__SHIFT) & A4XX_RB_BLEND_GREEN_SINT__MASK; 1112 } 1113 #define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 1114 #define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 1115 static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val) 1116 { 1117 return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK; 1118 } 1119 1120 #define REG_A4XX_RB_BLEND_GREEN_F32 0x000020f3 1121 #define A4XX_RB_BLEND_GREEN_F32__MASK 0xffffffff 1122 #define A4XX_RB_BLEND_GREEN_F32__SHIFT 0 1123 static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val) 1124 { 1125 return ((fui(val)) << A4XX_RB_BLEND_GREEN_F32__SHIFT) & A4XX_RB_BLEND_GREEN_F32__MASK; 1126 } 1127 1128 #define REG_A4XX_RB_BLEND_BLUE 0x000020f4 1129 #define A4XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff 1130 #define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0 1131 static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val) 1132 { 1133 return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK; 1134 } 1135 #define A4XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00 1136 #define A4XX_RB_BLEND_BLUE_SINT__SHIFT 8 1137 static inline uint32_t A4XX_RB_BLEND_BLUE_SINT(uint32_t val) 1138 { 1139 return ((val) << A4XX_RB_BLEND_BLUE_SINT__SHIFT) & A4XX_RB_BLEND_BLUE_SINT__MASK; 1140 } 1141 #define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 1142 #define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 1143 static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val) 1144 { 1145 return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK; 1146 } 1147 1148 #define REG_A4XX_RB_BLEND_BLUE_F32 0x000020f5 1149 #define A4XX_RB_BLEND_BLUE_F32__MASK 0xffffffff 1150 #define A4XX_RB_BLEND_BLUE_F32__SHIFT 0 1151 static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val) 1152 { 1153 return ((fui(val)) << A4XX_RB_BLEND_BLUE_F32__SHIFT) & A4XX_RB_BLEND_BLUE_F32__MASK; 1154 } 1155 1156 #define REG_A4XX_RB_BLEND_ALPHA 0x000020f6 1157 #define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff 1158 #define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0 1159 static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val) 1160 { 1161 return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK; 1162 } 1163 #define A4XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00 1164 #define A4XX_RB_BLEND_ALPHA_SINT__SHIFT 8 1165 static inline uint32_t A4XX_RB_BLEND_ALPHA_SINT(uint32_t val) 1166 { 1167 return ((val) << A4XX_RB_BLEND_ALPHA_SINT__SHIFT) & A4XX_RB_BLEND_ALPHA_SINT__MASK; 1168 } 1169 #define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 1170 #define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 1171 static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val) 1172 { 1173 return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK; 1174 } 1175 1176 #define REG_A4XX_RB_BLEND_ALPHA_F32 0x000020f7 1177 #define A4XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff 1178 #define A4XX_RB_BLEND_ALPHA_F32__SHIFT 0 1179 static inline uint32_t A4XX_RB_BLEND_ALPHA_F32(float val) 1180 { 1181 return ((fui(val)) << A4XX_RB_BLEND_ALPHA_F32__SHIFT) & A4XX_RB_BLEND_ALPHA_F32__MASK; 1182 } 1183 1184 #define REG_A4XX_RB_ALPHA_CONTROL 0x000020f8 1185 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff 1186 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 1187 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) 1188 { 1189 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; 1190 } 1191 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 1192 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 1193 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 1194 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 1195 { 1196 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; 1197 } 1198 1199 #define REG_A4XX_RB_FS_OUTPUT 0x000020f9 1200 #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK 0x000000ff 1201 #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT 0 1202 static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val) 1203 { 1204 return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK; 1205 } 1206 #define A4XX_RB_FS_OUTPUT_INDEPENDENT_BLEND 0x00000100 1207 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000 1208 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT 16 1209 static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val) 1210 { 1211 return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK; 1212 } 1213 1214 #define REG_A4XX_RB_SAMPLE_COUNT_CONTROL 0x000020fa 1215 #define A4XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 1216 #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK 0xfffffffc 1217 #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT 2 1218 static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val) 1219 { 1220 return ((val >> 2) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK; 1221 } 1222 1223 #define REG_A4XX_RB_RENDER_COMPONENTS 0x000020fb 1224 #define A4XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f 1225 #define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0 1226 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) 1227 { 1228 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT0__MASK; 1229 } 1230 #define A4XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0 1231 #define A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4 1232 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) 1233 { 1234 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT1__MASK; 1235 } 1236 #define A4XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00 1237 #define A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8 1238 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) 1239 { 1240 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT2__MASK; 1241 } 1242 #define A4XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000 1243 #define A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12 1244 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) 1245 { 1246 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT3__MASK; 1247 } 1248 #define A4XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000 1249 #define A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16 1250 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) 1251 { 1252 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT4__MASK; 1253 } 1254 #define A4XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000 1255 #define A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20 1256 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) 1257 { 1258 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT5__MASK; 1259 } 1260 #define A4XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000 1261 #define A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24 1262 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) 1263 { 1264 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT6__MASK; 1265 } 1266 #define A4XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000 1267 #define A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28 1268 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) 1269 { 1270 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT7__MASK; 1271 } 1272 1273 #define REG_A4XX_RB_COPY_CONTROL 0x000020fc 1274 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003 1275 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0 1276 static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) 1277 { 1278 return ((val) << A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK; 1279 } 1280 #define A4XX_RB_COPY_CONTROL_MODE__MASK 0x00000070 1281 #define A4XX_RB_COPY_CONTROL_MODE__SHIFT 4 1282 static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) 1283 { 1284 return ((val) << A4XX_RB_COPY_CONTROL_MODE__SHIFT) & A4XX_RB_COPY_CONTROL_MODE__MASK; 1285 } 1286 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00 1287 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8 1288 static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) 1289 { 1290 return ((val) << A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK; 1291 } 1292 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000 1293 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14 1294 static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) 1295 { 1296 return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK; 1297 } 1298 1299 #define REG_A4XX_RB_COPY_DEST_BASE 0x000020fd 1300 #define A4XX_RB_COPY_DEST_BASE_BASE__MASK 0xffffffe0 1301 #define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT 5 1302 static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val) 1303 { 1304 return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK; 1305 } 1306 1307 #define REG_A4XX_RB_COPY_DEST_PITCH 0x000020fe 1308 #define A4XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff 1309 #define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0 1310 static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) 1311 { 1312 return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK; 1313 } 1314 1315 #define REG_A4XX_RB_COPY_DEST_INFO 0x000020ff 1316 #define A4XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc 1317 #define A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2 1318 static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val) 1319 { 1320 return ((val) << A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A4XX_RB_COPY_DEST_INFO_FORMAT__MASK; 1321 } 1322 #define A4XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 1323 #define A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 1324 static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) 1325 { 1326 return ((val) << A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A4XX_RB_COPY_DEST_INFO_SWAP__MASK; 1327 } 1328 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 1329 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 1330 static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 1331 { 1332 return ((val) << A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 1333 } 1334 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000 1335 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14 1336 static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) 1337 { 1338 return ((val) << A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK; 1339 } 1340 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000 1341 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18 1342 static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) 1343 { 1344 return ((val) << A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK; 1345 } 1346 #define A4XX_RB_COPY_DEST_INFO_TILE__MASK 0x03000000 1347 #define A4XX_RB_COPY_DEST_INFO_TILE__SHIFT 24 1348 static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val) 1349 { 1350 return ((val) << A4XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A4XX_RB_COPY_DEST_INFO_TILE__MASK; 1351 } 1352 1353 #define REG_A4XX_RB_FS_OUTPUT_REG 0x00002100 1354 #define A4XX_RB_FS_OUTPUT_REG_MRT__MASK 0x0000000f 1355 #define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT 0 1356 static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val) 1357 { 1358 return ((val) << A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_RB_FS_OUTPUT_REG_MRT__MASK; 1359 } 1360 #define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z 0x00000020 1361 1362 #define REG_A4XX_RB_DEPTH_CONTROL 0x00002101 1363 #define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001 1364 #define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x00000002 1365 #define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004 1366 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070 1367 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4 1368 static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) 1369 { 1370 return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK; 1371 } 1372 #define A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE 0x00000080 1373 #define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000 1374 #define A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS 0x00020000 1375 #define A4XX_RB_DEPTH_CONTROL_Z_READ_ENABLE 0x80000000 1376 1377 #define REG_A4XX_RB_DEPTH_CLEAR 0x00002102 1378 1379 #define REG_A4XX_RB_DEPTH_INFO 0x00002103 1380 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003 1381 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 1382 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val) 1383 { 1384 return ((val) << A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 1385 } 1386 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 1387 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 1388 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 1389 { 1390 return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 1391 } 1392 1393 #define REG_A4XX_RB_DEPTH_PITCH 0x00002104 1394 #define A4XX_RB_DEPTH_PITCH__MASK 0xffffffff 1395 #define A4XX_RB_DEPTH_PITCH__SHIFT 0 1396 static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val) 1397 { 1398 return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK; 1399 } 1400 1401 #define REG_A4XX_RB_DEPTH_PITCH2 0x00002105 1402 #define A4XX_RB_DEPTH_PITCH2__MASK 0xffffffff 1403 #define A4XX_RB_DEPTH_PITCH2__SHIFT 0 1404 static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val) 1405 { 1406 return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK; 1407 } 1408 1409 #define REG_A4XX_RB_STENCIL_CONTROL 0x00002106 1410 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 1411 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 1412 #define A4XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 1413 #define A4XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 1414 #define A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 1415 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 1416 { 1417 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC__MASK; 1418 } 1419 #define A4XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 1420 #define A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 1421 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 1422 { 1423 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL__MASK; 1424 } 1425 #define A4XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 1426 #define A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 1427 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 1428 { 1429 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS__MASK; 1430 } 1431 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 1432 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 1433 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 1434 { 1435 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 1436 } 1437 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 1438 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 1439 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 1440 { 1441 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 1442 } 1443 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 1444 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 1445 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 1446 { 1447 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 1448 } 1449 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 1450 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 1451 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 1452 { 1453 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 1454 } 1455 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 1456 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 1457 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 1458 { 1459 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 1460 } 1461 1462 #define REG_A4XX_RB_STENCIL_CONTROL2 0x00002107 1463 #define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER 0x00000001 1464 1465 #define REG_A4XX_RB_STENCIL_INFO 0x00002108 1466 #define A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 1467 #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff000 1468 #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 12 1469 static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) 1470 { 1471 return ((val >> 12) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK; 1472 } 1473 1474 #define REG_A4XX_RB_STENCIL_PITCH 0x00002109 1475 #define A4XX_RB_STENCIL_PITCH__MASK 0xffffffff 1476 #define A4XX_RB_STENCIL_PITCH__SHIFT 0 1477 static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val) 1478 { 1479 return ((val >> 5) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK; 1480 } 1481 1482 #define REG_A4XX_RB_STENCILREFMASK 0x0000210b 1483 #define A4XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 1484 #define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 1485 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 1486 { 1487 return ((val) << A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILREF__MASK; 1488 } 1489 #define A4XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 1490 #define A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 1491 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 1492 { 1493 return ((val) << A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILMASK__MASK; 1494 } 1495 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 1496 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 1497 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 1498 { 1499 return ((val) << A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 1500 } 1501 1502 #define REG_A4XX_RB_STENCILREFMASK_BF 0x0000210c 1503 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 1504 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 1505 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 1506 { 1507 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 1508 } 1509 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 1510 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 1511 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 1512 { 1513 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 1514 } 1515 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 1516 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 1517 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 1518 { 1519 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 1520 } 1521 1522 #define REG_A4XX_RB_BIN_OFFSET 0x0000210d 1523 #define A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 1524 #define A4XX_RB_BIN_OFFSET_X__MASK 0x00007fff 1525 #define A4XX_RB_BIN_OFFSET_X__SHIFT 0 1526 static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val) 1527 { 1528 return ((val) << A4XX_RB_BIN_OFFSET_X__SHIFT) & A4XX_RB_BIN_OFFSET_X__MASK; 1529 } 1530 #define A4XX_RB_BIN_OFFSET_Y__MASK 0x7fff0000 1531 #define A4XX_RB_BIN_OFFSET_Y__SHIFT 16 1532 static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val) 1533 { 1534 return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK; 1535 } 1536 1537 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; } 1538 1539 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; } 1540 1541 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; } 1542 1543 #define REG_A4XX_RBBM_HW_VERSION 0x00000000 1544 1545 #define REG_A4XX_RBBM_HW_CONFIGURATION 0x00000002 1546 1547 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; } 1548 1549 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; } 1550 1551 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; } 1552 1553 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; } 1554 1555 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; } 1556 1557 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; } 1558 1559 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; } 1560 1561 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; } 1562 1563 #define REG_A4XX_RBBM_CLOCK_CTL_UCHE 0x00000014 1564 1565 #define REG_A4XX_RBBM_CLOCK_CTL2_UCHE 0x00000015 1566 1567 #define REG_A4XX_RBBM_CLOCK_CTL3_UCHE 0x00000016 1568 1569 #define REG_A4XX_RBBM_CLOCK_CTL4_UCHE 0x00000017 1570 1571 #define REG_A4XX_RBBM_CLOCK_HYST_UCHE 0x00000018 1572 1573 #define REG_A4XX_RBBM_CLOCK_DELAY_UCHE 0x00000019 1574 1575 #define REG_A4XX_RBBM_CLOCK_MODE_GPC 0x0000001a 1576 1577 #define REG_A4XX_RBBM_CLOCK_DELAY_GPC 0x0000001b 1578 1579 #define REG_A4XX_RBBM_CLOCK_HYST_GPC 0x0000001c 1580 1581 #define REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM 0x0000001d 1582 1583 #define REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000001e 1584 1585 #define REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x0000001f 1586 1587 #define REG_A4XX_RBBM_CLOCK_CTL 0x00000020 1588 1589 #define REG_A4XX_RBBM_SP_HYST_CNT 0x00000021 1590 1591 #define REG_A4XX_RBBM_SW_RESET_CMD 0x00000022 1592 1593 #define REG_A4XX_RBBM_AHB_CTL0 0x00000023 1594 1595 #define REG_A4XX_RBBM_AHB_CTL1 0x00000024 1596 1597 #define REG_A4XX_RBBM_AHB_CMD 0x00000025 1598 1599 #define REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL 0x00000026 1600 1601 #define REG_A4XX_RBBM_RAM_ACC_63_32 0x00000028 1602 1603 #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x0000002b 1604 1605 #define REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL 0x0000002f 1606 1607 #define REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4 0x00000034 1608 1609 #define REG_A4XX_RBBM_INT_CLEAR_CMD 0x00000036 1610 1611 #define REG_A4XX_RBBM_INT_0_MASK 0x00000037 1612 1613 #define REG_A4XX_RBBM_RBBM_CTL 0x0000003e 1614 1615 #define REG_A4XX_RBBM_AHB_DEBUG_CTL 0x0000003f 1616 1617 #define REG_A4XX_RBBM_VBIF_DEBUG_CTL 0x00000041 1618 1619 #define REG_A4XX_RBBM_CLOCK_CTL2 0x00000042 1620 1621 #define REG_A4XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 1622 1623 #define REG_A4XX_RBBM_RESET_CYCLES 0x00000047 1624 1625 #define REG_A4XX_RBBM_EXT_TRACE_BUS_CTL 0x00000049 1626 1627 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A 0x0000004a 1628 1629 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B 0x0000004b 1630 1631 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C 0x0000004c 1632 1633 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D 0x0000004d 1634 1635 #define REG_A4XX_RBBM_POWER_CNTL_IP 0x00000098 1636 #define A4XX_RBBM_POWER_CNTL_IP_SW_COLLAPSE 0x00000001 1637 #define A4XX_RBBM_POWER_CNTL_IP_SP_TP_PWR_ON 0x00100000 1638 1639 #define REG_A4XX_RBBM_PERFCTR_CP_0_LO 0x0000009c 1640 1641 #define REG_A4XX_RBBM_PERFCTR_CP_0_HI 0x0000009d 1642 1643 #define REG_A4XX_RBBM_PERFCTR_CP_1_LO 0x0000009e 1644 1645 #define REG_A4XX_RBBM_PERFCTR_CP_1_HI 0x0000009f 1646 1647 #define REG_A4XX_RBBM_PERFCTR_CP_2_LO 0x000000a0 1648 1649 #define REG_A4XX_RBBM_PERFCTR_CP_2_HI 0x000000a1 1650 1651 #define REG_A4XX_RBBM_PERFCTR_CP_3_LO 0x000000a2 1652 1653 #define REG_A4XX_RBBM_PERFCTR_CP_3_HI 0x000000a3 1654 1655 #define REG_A4XX_RBBM_PERFCTR_CP_4_LO 0x000000a4 1656 1657 #define REG_A4XX_RBBM_PERFCTR_CP_4_HI 0x000000a5 1658 1659 #define REG_A4XX_RBBM_PERFCTR_CP_5_LO 0x000000a6 1660 1661 #define REG_A4XX_RBBM_PERFCTR_CP_5_HI 0x000000a7 1662 1663 #define REG_A4XX_RBBM_PERFCTR_CP_6_LO 0x000000a8 1664 1665 #define REG_A4XX_RBBM_PERFCTR_CP_6_HI 0x000000a9 1666 1667 #define REG_A4XX_RBBM_PERFCTR_CP_7_LO 0x000000aa 1668 1669 #define REG_A4XX_RBBM_PERFCTR_CP_7_HI 0x000000ab 1670 1671 #define REG_A4XX_RBBM_PERFCTR_RBBM_0_LO 0x000000ac 1672 1673 #define REG_A4XX_RBBM_PERFCTR_RBBM_0_HI 0x000000ad 1674 1675 #define REG_A4XX_RBBM_PERFCTR_RBBM_1_LO 0x000000ae 1676 1677 #define REG_A4XX_RBBM_PERFCTR_RBBM_1_HI 0x000000af 1678 1679 #define REG_A4XX_RBBM_PERFCTR_RBBM_2_LO 0x000000b0 1680 1681 #define REG_A4XX_RBBM_PERFCTR_RBBM_2_HI 0x000000b1 1682 1683 #define REG_A4XX_RBBM_PERFCTR_RBBM_3_LO 0x000000b2 1684 1685 #define REG_A4XX_RBBM_PERFCTR_RBBM_3_HI 0x000000b3 1686 1687 #define REG_A4XX_RBBM_PERFCTR_PC_0_LO 0x000000b4 1688 1689 #define REG_A4XX_RBBM_PERFCTR_PC_0_HI 0x000000b5 1690 1691 #define REG_A4XX_RBBM_PERFCTR_PC_1_LO 0x000000b6 1692 1693 #define REG_A4XX_RBBM_PERFCTR_PC_1_HI 0x000000b7 1694 1695 #define REG_A4XX_RBBM_PERFCTR_PC_2_LO 0x000000b8 1696 1697 #define REG_A4XX_RBBM_PERFCTR_PC_2_HI 0x000000b9 1698 1699 #define REG_A4XX_RBBM_PERFCTR_PC_3_LO 0x000000ba 1700 1701 #define REG_A4XX_RBBM_PERFCTR_PC_3_HI 0x000000bb 1702 1703 #define REG_A4XX_RBBM_PERFCTR_PC_4_LO 0x000000bc 1704 1705 #define REG_A4XX_RBBM_PERFCTR_PC_4_HI 0x000000bd 1706 1707 #define REG_A4XX_RBBM_PERFCTR_PC_5_LO 0x000000be 1708 1709 #define REG_A4XX_RBBM_PERFCTR_PC_5_HI 0x000000bf 1710 1711 #define REG_A4XX_RBBM_PERFCTR_PC_6_LO 0x000000c0 1712 1713 #define REG_A4XX_RBBM_PERFCTR_PC_6_HI 0x000000c1 1714 1715 #define REG_A4XX_RBBM_PERFCTR_PC_7_LO 0x000000c2 1716 1717 #define REG_A4XX_RBBM_PERFCTR_PC_7_HI 0x000000c3 1718 1719 #define REG_A4XX_RBBM_PERFCTR_VFD_0_LO 0x000000c4 1720 1721 #define REG_A4XX_RBBM_PERFCTR_VFD_0_HI 0x000000c5 1722 1723 #define REG_A4XX_RBBM_PERFCTR_VFD_1_LO 0x000000c6 1724 1725 #define REG_A4XX_RBBM_PERFCTR_VFD_1_HI 0x000000c7 1726 1727 #define REG_A4XX_RBBM_PERFCTR_VFD_2_LO 0x000000c8 1728 1729 #define REG_A4XX_RBBM_PERFCTR_VFD_2_HI 0x000000c9 1730 1731 #define REG_A4XX_RBBM_PERFCTR_VFD_3_LO 0x000000ca 1732 1733 #define REG_A4XX_RBBM_PERFCTR_VFD_3_HI 0x000000cb 1734 1735 #define REG_A4XX_RBBM_PERFCTR_VFD_4_LO 0x000000cc 1736 1737 #define REG_A4XX_RBBM_PERFCTR_VFD_4_HI 0x000000cd 1738 1739 #define REG_A4XX_RBBM_PERFCTR_VFD_5_LO 0x000000ce 1740 1741 #define REG_A4XX_RBBM_PERFCTR_VFD_5_HI 0x000000cf 1742 1743 #define REG_A4XX_RBBM_PERFCTR_VFD_6_LO 0x000000d0 1744 1745 #define REG_A4XX_RBBM_PERFCTR_VFD_6_HI 0x000000d1 1746 1747 #define REG_A4XX_RBBM_PERFCTR_VFD_7_LO 0x000000d2 1748 1749 #define REG_A4XX_RBBM_PERFCTR_VFD_7_HI 0x000000d3 1750 1751 #define REG_A4XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000d4 1752 1753 #define REG_A4XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000d5 1754 1755 #define REG_A4XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000d6 1756 1757 #define REG_A4XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000d7 1758 1759 #define REG_A4XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000d8 1760 1761 #define REG_A4XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000d9 1762 1763 #define REG_A4XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000da 1764 1765 #define REG_A4XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000db 1766 1767 #define REG_A4XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000dc 1768 1769 #define REG_A4XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000dd 1770 1771 #define REG_A4XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000de 1772 1773 #define REG_A4XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000df 1774 1775 #define REG_A4XX_RBBM_PERFCTR_HLSQ_6_LO 0x000000e0 1776 1777 #define REG_A4XX_RBBM_PERFCTR_HLSQ_6_HI 0x000000e1 1778 1779 #define REG_A4XX_RBBM_PERFCTR_HLSQ_7_LO 0x000000e2 1780 1781 #define REG_A4XX_RBBM_PERFCTR_HLSQ_7_HI 0x000000e3 1782 1783 #define REG_A4XX_RBBM_PERFCTR_VPC_0_LO 0x000000e4 1784 1785 #define REG_A4XX_RBBM_PERFCTR_VPC_0_HI 0x000000e5 1786 1787 #define REG_A4XX_RBBM_PERFCTR_VPC_1_LO 0x000000e6 1788 1789 #define REG_A4XX_RBBM_PERFCTR_VPC_1_HI 0x000000e7 1790 1791 #define REG_A4XX_RBBM_PERFCTR_VPC_2_LO 0x000000e8 1792 1793 #define REG_A4XX_RBBM_PERFCTR_VPC_2_HI 0x000000e9 1794 1795 #define REG_A4XX_RBBM_PERFCTR_VPC_3_LO 0x000000ea 1796 1797 #define REG_A4XX_RBBM_PERFCTR_VPC_3_HI 0x000000eb 1798 1799 #define REG_A4XX_RBBM_PERFCTR_CCU_0_LO 0x000000ec 1800 1801 #define REG_A4XX_RBBM_PERFCTR_CCU_0_HI 0x000000ed 1802 1803 #define REG_A4XX_RBBM_PERFCTR_CCU_1_LO 0x000000ee 1804 1805 #define REG_A4XX_RBBM_PERFCTR_CCU_1_HI 0x000000ef 1806 1807 #define REG_A4XX_RBBM_PERFCTR_CCU_2_LO 0x000000f0 1808 1809 #define REG_A4XX_RBBM_PERFCTR_CCU_2_HI 0x000000f1 1810 1811 #define REG_A4XX_RBBM_PERFCTR_CCU_3_LO 0x000000f2 1812 1813 #define REG_A4XX_RBBM_PERFCTR_CCU_3_HI 0x000000f3 1814 1815 #define REG_A4XX_RBBM_PERFCTR_TSE_0_LO 0x000000f4 1816 1817 #define REG_A4XX_RBBM_PERFCTR_TSE_0_HI 0x000000f5 1818 1819 #define REG_A4XX_RBBM_PERFCTR_TSE_1_LO 0x000000f6 1820 1821 #define REG_A4XX_RBBM_PERFCTR_TSE_1_HI 0x000000f7 1822 1823 #define REG_A4XX_RBBM_PERFCTR_TSE_2_LO 0x000000f8 1824 1825 #define REG_A4XX_RBBM_PERFCTR_TSE_2_HI 0x000000f9 1826 1827 #define REG_A4XX_RBBM_PERFCTR_TSE_3_LO 0x000000fa 1828 1829 #define REG_A4XX_RBBM_PERFCTR_TSE_3_HI 0x000000fb 1830 1831 #define REG_A4XX_RBBM_PERFCTR_RAS_0_LO 0x000000fc 1832 1833 #define REG_A4XX_RBBM_PERFCTR_RAS_0_HI 0x000000fd 1834 1835 #define REG_A4XX_RBBM_PERFCTR_RAS_1_LO 0x000000fe 1836 1837 #define REG_A4XX_RBBM_PERFCTR_RAS_1_HI 0x000000ff 1838 1839 #define REG_A4XX_RBBM_PERFCTR_RAS_2_LO 0x00000100 1840 1841 #define REG_A4XX_RBBM_PERFCTR_RAS_2_HI 0x00000101 1842 1843 #define REG_A4XX_RBBM_PERFCTR_RAS_3_LO 0x00000102 1844 1845 #define REG_A4XX_RBBM_PERFCTR_RAS_3_HI 0x00000103 1846 1847 #define REG_A4XX_RBBM_PERFCTR_UCHE_0_LO 0x00000104 1848 1849 #define REG_A4XX_RBBM_PERFCTR_UCHE_0_HI 0x00000105 1850 1851 #define REG_A4XX_RBBM_PERFCTR_UCHE_1_LO 0x00000106 1852 1853 #define REG_A4XX_RBBM_PERFCTR_UCHE_1_HI 0x00000107 1854 1855 #define REG_A4XX_RBBM_PERFCTR_UCHE_2_LO 0x00000108 1856 1857 #define REG_A4XX_RBBM_PERFCTR_UCHE_2_HI 0x00000109 1858 1859 #define REG_A4XX_RBBM_PERFCTR_UCHE_3_LO 0x0000010a 1860 1861 #define REG_A4XX_RBBM_PERFCTR_UCHE_3_HI 0x0000010b 1862 1863 #define REG_A4XX_RBBM_PERFCTR_UCHE_4_LO 0x0000010c 1864 1865 #define REG_A4XX_RBBM_PERFCTR_UCHE_4_HI 0x0000010d 1866 1867 #define REG_A4XX_RBBM_PERFCTR_UCHE_5_LO 0x0000010e 1868 1869 #define REG_A4XX_RBBM_PERFCTR_UCHE_5_HI 0x0000010f 1870 1871 #define REG_A4XX_RBBM_PERFCTR_UCHE_6_LO 0x00000110 1872 1873 #define REG_A4XX_RBBM_PERFCTR_UCHE_6_HI 0x00000111 1874 1875 #define REG_A4XX_RBBM_PERFCTR_UCHE_7_LO 0x00000112 1876 1877 #define REG_A4XX_RBBM_PERFCTR_UCHE_7_HI 0x00000113 1878 1879 #define REG_A4XX_RBBM_PERFCTR_TP_0_LO 0x00000114 1880 1881 #define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115 1882 1883 #define REG_A4XX_RBBM_PERFCTR_TP_1_LO 0x00000116 1884 1885 #define REG_A4XX_RBBM_PERFCTR_TP_1_HI 0x00000117 1886 1887 #define REG_A4XX_RBBM_PERFCTR_TP_2_LO 0x00000118 1888 1889 #define REG_A4XX_RBBM_PERFCTR_TP_2_HI 0x00000119 1890 1891 #define REG_A4XX_RBBM_PERFCTR_TP_3_LO 0x0000011a 1892 1893 #define REG_A4XX_RBBM_PERFCTR_TP_3_HI 0x0000011b 1894 1895 #define REG_A4XX_RBBM_PERFCTR_TP_4_LO 0x0000011c 1896 1897 #define REG_A4XX_RBBM_PERFCTR_TP_4_HI 0x0000011d 1898 1899 #define REG_A4XX_RBBM_PERFCTR_TP_5_LO 0x0000011e 1900 1901 #define REG_A4XX_RBBM_PERFCTR_TP_5_HI 0x0000011f 1902 1903 #define REG_A4XX_RBBM_PERFCTR_TP_6_LO 0x00000120 1904 1905 #define REG_A4XX_RBBM_PERFCTR_TP_6_HI 0x00000121 1906 1907 #define REG_A4XX_RBBM_PERFCTR_TP_7_LO 0x00000122 1908 1909 #define REG_A4XX_RBBM_PERFCTR_TP_7_HI 0x00000123 1910 1911 #define REG_A4XX_RBBM_PERFCTR_SP_0_LO 0x00000124 1912 1913 #define REG_A4XX_RBBM_PERFCTR_SP_0_HI 0x00000125 1914 1915 #define REG_A4XX_RBBM_PERFCTR_SP_1_LO 0x00000126 1916 1917 #define REG_A4XX_RBBM_PERFCTR_SP_1_HI 0x00000127 1918 1919 #define REG_A4XX_RBBM_PERFCTR_SP_2_LO 0x00000128 1920 1921 #define REG_A4XX_RBBM_PERFCTR_SP_2_HI 0x00000129 1922 1923 #define REG_A4XX_RBBM_PERFCTR_SP_3_LO 0x0000012a 1924 1925 #define REG_A4XX_RBBM_PERFCTR_SP_3_HI 0x0000012b 1926 1927 #define REG_A4XX_RBBM_PERFCTR_SP_4_LO 0x0000012c 1928 1929 #define REG_A4XX_RBBM_PERFCTR_SP_4_HI 0x0000012d 1930 1931 #define REG_A4XX_RBBM_PERFCTR_SP_5_LO 0x0000012e 1932 1933 #define REG_A4XX_RBBM_PERFCTR_SP_5_HI 0x0000012f 1934 1935 #define REG_A4XX_RBBM_PERFCTR_SP_6_LO 0x00000130 1936 1937 #define REG_A4XX_RBBM_PERFCTR_SP_6_HI 0x00000131 1938 1939 #define REG_A4XX_RBBM_PERFCTR_SP_7_LO 0x00000132 1940 1941 #define REG_A4XX_RBBM_PERFCTR_SP_7_HI 0x00000133 1942 1943 #define REG_A4XX_RBBM_PERFCTR_SP_8_LO 0x00000134 1944 1945 #define REG_A4XX_RBBM_PERFCTR_SP_8_HI 0x00000135 1946 1947 #define REG_A4XX_RBBM_PERFCTR_SP_9_LO 0x00000136 1948 1949 #define REG_A4XX_RBBM_PERFCTR_SP_9_HI 0x00000137 1950 1951 #define REG_A4XX_RBBM_PERFCTR_SP_10_LO 0x00000138 1952 1953 #define REG_A4XX_RBBM_PERFCTR_SP_10_HI 0x00000139 1954 1955 #define REG_A4XX_RBBM_PERFCTR_SP_11_LO 0x0000013a 1956 1957 #define REG_A4XX_RBBM_PERFCTR_SP_11_HI 0x0000013b 1958 1959 #define REG_A4XX_RBBM_PERFCTR_RB_0_LO 0x0000013c 1960 1961 #define REG_A4XX_RBBM_PERFCTR_RB_0_HI 0x0000013d 1962 1963 #define REG_A4XX_RBBM_PERFCTR_RB_1_LO 0x0000013e 1964 1965 #define REG_A4XX_RBBM_PERFCTR_RB_1_HI 0x0000013f 1966 1967 #define REG_A4XX_RBBM_PERFCTR_RB_2_LO 0x00000140 1968 1969 #define REG_A4XX_RBBM_PERFCTR_RB_2_HI 0x00000141 1970 1971 #define REG_A4XX_RBBM_PERFCTR_RB_3_LO 0x00000142 1972 1973 #define REG_A4XX_RBBM_PERFCTR_RB_3_HI 0x00000143 1974 1975 #define REG_A4XX_RBBM_PERFCTR_RB_4_LO 0x00000144 1976 1977 #define REG_A4XX_RBBM_PERFCTR_RB_4_HI 0x00000145 1978 1979 #define REG_A4XX_RBBM_PERFCTR_RB_5_LO 0x00000146 1980 1981 #define REG_A4XX_RBBM_PERFCTR_RB_5_HI 0x00000147 1982 1983 #define REG_A4XX_RBBM_PERFCTR_RB_6_LO 0x00000148 1984 1985 #define REG_A4XX_RBBM_PERFCTR_RB_6_HI 0x00000149 1986 1987 #define REG_A4XX_RBBM_PERFCTR_RB_7_LO 0x0000014a 1988 1989 #define REG_A4XX_RBBM_PERFCTR_RB_7_HI 0x0000014b 1990 1991 #define REG_A4XX_RBBM_PERFCTR_VSC_0_LO 0x0000014c 1992 1993 #define REG_A4XX_RBBM_PERFCTR_VSC_0_HI 0x0000014d 1994 1995 #define REG_A4XX_RBBM_PERFCTR_VSC_1_LO 0x0000014e 1996 1997 #define REG_A4XX_RBBM_PERFCTR_VSC_1_HI 0x0000014f 1998 1999 #define REG_A4XX_RBBM_PERFCTR_PWR_0_LO 0x00000166 2000 2001 #define REG_A4XX_RBBM_PERFCTR_PWR_0_HI 0x00000167 2002 2003 #define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168 2004 2005 #define REG_A4XX_RBBM_PERFCTR_PWR_1_HI 0x00000169 2006 2007 #define REG_A4XX_RBBM_ALWAYSON_COUNTER_LO 0x0000016e 2008 2009 #define REG_A4XX_RBBM_ALWAYSON_COUNTER_HI 0x0000016f 2010 2011 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; } 2012 2013 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; } 2014 2015 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; } 2016 2017 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; } 2018 2019 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; } 2020 2021 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; } 2022 2023 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; } 2024 2025 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; } 2026 2027 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; } 2028 2029 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; } 2030 2031 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; } 2032 2033 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; } 2034 2035 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; } 2036 2037 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; } 2038 2039 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; } 2040 2041 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; } 2042 2043 #define REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM 0x00000080 2044 2045 #define REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM 0x00000081 2046 2047 #define REG_A4XX_RBBM_CLOCK_CTL_HLSQ 0x0000008a 2048 2049 #define REG_A4XX_RBBM_CLOCK_HYST_HLSQ 0x0000008b 2050 2051 #define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ 0x0000008c 2052 2053 #define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM 0x0000008d 2054 2055 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; } 2056 2057 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; } 2058 2059 #define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0 0x00000099 2060 2061 #define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1 0x0000009a 2062 2063 #define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170 2064 2065 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0 0x00000171 2066 2067 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1 0x00000172 2068 2069 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2 0x00000173 2070 2071 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000174 2072 2073 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000175 2074 2075 #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000176 2076 2077 #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000177 2078 2079 #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000178 2080 2081 #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_3 0x00000179 2082 2083 #define REG_A4XX_RBBM_GPU_BUSY_MASKED 0x0000017a 2084 2085 #define REG_A4XX_RBBM_INT_0_STATUS 0x0000017d 2086 2087 #define REG_A4XX_RBBM_CLOCK_STATUS 0x00000182 2088 2089 #define REG_A4XX_RBBM_AHB_STATUS 0x00000189 2090 2091 #define REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS 0x0000018c 2092 2093 #define REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS 0x0000018d 2094 2095 #define REG_A4XX_RBBM_AHB_ERROR_STATUS 0x0000018f 2096 2097 #define REG_A4XX_RBBM_STATUS 0x00000191 2098 #define A4XX_RBBM_STATUS_HI_BUSY 0x00000001 2099 #define A4XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 2100 #define A4XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 2101 #define A4XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000 2102 #define A4XX_RBBM_STATUS_VBIF_BUSY 0x00008000 2103 #define A4XX_RBBM_STATUS_TSE_BUSY 0x00010000 2104 #define A4XX_RBBM_STATUS_RAS_BUSY 0x00020000 2105 #define A4XX_RBBM_STATUS_RB_BUSY 0x00040000 2106 #define A4XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 2107 #define A4XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 2108 #define A4XX_RBBM_STATUS_VFD_BUSY 0x00200000 2109 #define A4XX_RBBM_STATUS_VPC_BUSY 0x00400000 2110 #define A4XX_RBBM_STATUS_UCHE_BUSY 0x00800000 2111 #define A4XX_RBBM_STATUS_SP_BUSY 0x01000000 2112 #define A4XX_RBBM_STATUS_TPL1_BUSY 0x02000000 2113 #define A4XX_RBBM_STATUS_MARB_BUSY 0x04000000 2114 #define A4XX_RBBM_STATUS_VSC_BUSY 0x08000000 2115 #define A4XX_RBBM_STATUS_ARB_BUSY 0x10000000 2116 #define A4XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 2117 #define A4XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000 2118 #define A4XX_RBBM_STATUS_GPU_BUSY 0x80000000 2119 2120 #define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5 0x0000019f 2121 2122 #define REG_A4XX_RBBM_POWER_STATUS 0x000001b0 2123 #define A4XX_RBBM_POWER_STATUS_SP_TP_PWR_ON 0x00100000 2124 2125 #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2 0x000001b8 2126 2127 #define REG_A4XX_CP_SCRATCH_UMASK 0x00000228 2128 2129 #define REG_A4XX_CP_SCRATCH_ADDR 0x00000229 2130 2131 #define REG_A4XX_CP_RB_BASE 0x00000200 2132 2133 #define REG_A4XX_CP_RB_CNTL 0x00000201 2134 2135 #define REG_A4XX_CP_RB_WPTR 0x00000205 2136 2137 #define REG_A4XX_CP_RB_RPTR_ADDR 0x00000203 2138 2139 #define REG_A4XX_CP_RB_RPTR 0x00000204 2140 2141 #define REG_A4XX_CP_IB1_BASE 0x00000206 2142 2143 #define REG_A4XX_CP_IB1_BUFSZ 0x00000207 2144 2145 #define REG_A4XX_CP_IB2_BASE 0x00000208 2146 2147 #define REG_A4XX_CP_IB2_BUFSZ 0x00000209 2148 2149 #define REG_A4XX_CP_ME_NRT_ADDR 0x0000020c 2150 2151 #define REG_A4XX_CP_ME_NRT_DATA 0x0000020d 2152 2153 #define REG_A4XX_CP_ME_RB_DONE_DATA 0x00000217 2154 2155 #define REG_A4XX_CP_QUEUE_THRESH2 0x00000219 2156 2157 #define REG_A4XX_CP_MERCIU_SIZE 0x0000021b 2158 2159 #define REG_A4XX_CP_ROQ_ADDR 0x0000021c 2160 2161 #define REG_A4XX_CP_ROQ_DATA 0x0000021d 2162 2163 #define REG_A4XX_CP_MEQ_ADDR 0x0000021e 2164 2165 #define REG_A4XX_CP_MEQ_DATA 0x0000021f 2166 2167 #define REG_A4XX_CP_MERCIU_ADDR 0x00000220 2168 2169 #define REG_A4XX_CP_MERCIU_DATA 0x00000221 2170 2171 #define REG_A4XX_CP_MERCIU_DATA2 0x00000222 2172 2173 #define REG_A4XX_CP_PFP_UCODE_ADDR 0x00000223 2174 2175 #define REG_A4XX_CP_PFP_UCODE_DATA 0x00000224 2176 2177 #define REG_A4XX_CP_ME_RAM_WADDR 0x00000225 2178 2179 #define REG_A4XX_CP_ME_RAM_RADDR 0x00000226 2180 2181 #define REG_A4XX_CP_ME_RAM_DATA 0x00000227 2182 2183 #define REG_A4XX_CP_PREEMPT 0x0000022a 2184 2185 #define REG_A4XX_CP_CNTL 0x0000022c 2186 2187 #define REG_A4XX_CP_ME_CNTL 0x0000022d 2188 2189 #define REG_A4XX_CP_DEBUG 0x0000022e 2190 2191 #define REG_A4XX_CP_DEBUG_ECO_CONTROL 0x00000231 2192 2193 #define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232 2194 2195 static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; } 2196 2197 static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; } 2198 #define A4XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff 2199 #define A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0 2200 static inline uint32_t A4XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) 2201 { 2202 return ((val) << A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A4XX_CP_PROTECT_REG_BASE_ADDR__MASK; 2203 } 2204 #define A4XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000 2205 #define A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24 2206 static inline uint32_t A4XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) 2207 { 2208 return ((val) << A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A4XX_CP_PROTECT_REG_MASK_LEN__MASK; 2209 } 2210 #define A4XX_CP_PROTECT_REG_TRAP_WRITE__MASK 0x20000000 2211 #define A4XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT 29 2212 static inline uint32_t A4XX_CP_PROTECT_REG_TRAP_WRITE(uint32_t val) 2213 { 2214 return ((val) << A4XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT) & A4XX_CP_PROTECT_REG_TRAP_WRITE__MASK; 2215 } 2216 #define A4XX_CP_PROTECT_REG_TRAP_READ__MASK 0x40000000 2217 #define A4XX_CP_PROTECT_REG_TRAP_READ__SHIFT 30 2218 static inline uint32_t A4XX_CP_PROTECT_REG_TRAP_READ(uint32_t val) 2219 { 2220 return ((val) << A4XX_CP_PROTECT_REG_TRAP_READ__SHIFT) & A4XX_CP_PROTECT_REG_TRAP_READ__MASK; 2221 } 2222 2223 #define REG_A4XX_CP_PROTECT_CTRL 0x00000250 2224 2225 #define REG_A4XX_CP_ST_BASE 0x000004c0 2226 2227 #define REG_A4XX_CP_STQ_AVAIL 0x000004ce 2228 2229 #define REG_A4XX_CP_MERCIU_STAT 0x000004d0 2230 2231 #define REG_A4XX_CP_WFI_PEND_CTR 0x000004d2 2232 2233 #define REG_A4XX_CP_HW_FAULT 0x000004d8 2234 2235 #define REG_A4XX_CP_PROTECT_STATUS 0x000004da 2236 2237 #define REG_A4XX_CP_EVENTS_IN_FLIGHT 0x000004dd 2238 2239 #define REG_A4XX_CP_PERFCTR_CP_SEL_0 0x00000500 2240 2241 #define REG_A4XX_CP_PERFCTR_CP_SEL_1 0x00000501 2242 2243 #define REG_A4XX_CP_PERFCTR_CP_SEL_2 0x00000502 2244 2245 #define REG_A4XX_CP_PERFCTR_CP_SEL_3 0x00000503 2246 2247 #define REG_A4XX_CP_PERFCTR_CP_SEL_4 0x00000504 2248 2249 #define REG_A4XX_CP_PERFCTR_CP_SEL_5 0x00000505 2250 2251 #define REG_A4XX_CP_PERFCTR_CP_SEL_6 0x00000506 2252 2253 #define REG_A4XX_CP_PERFCTR_CP_SEL_7 0x00000507 2254 2255 #define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b 2256 2257 static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; } 2258 2259 static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; } 2260 2261 #define REG_A4XX_SP_VS_STATUS 0x00000ec0 2262 2263 #define REG_A4XX_SP_MODE_CONTROL 0x00000ec3 2264 2265 #define REG_A4XX_SP_PERFCTR_SP_SEL_0 0x00000ec4 2266 2267 #define REG_A4XX_SP_PERFCTR_SP_SEL_1 0x00000ec5 2268 2269 #define REG_A4XX_SP_PERFCTR_SP_SEL_2 0x00000ec6 2270 2271 #define REG_A4XX_SP_PERFCTR_SP_SEL_3 0x00000ec7 2272 2273 #define REG_A4XX_SP_PERFCTR_SP_SEL_4 0x00000ec8 2274 2275 #define REG_A4XX_SP_PERFCTR_SP_SEL_5 0x00000ec9 2276 2277 #define REG_A4XX_SP_PERFCTR_SP_SEL_6 0x00000eca 2278 2279 #define REG_A4XX_SP_PERFCTR_SP_SEL_7 0x00000ecb 2280 2281 #define REG_A4XX_SP_PERFCTR_SP_SEL_8 0x00000ecc 2282 2283 #define REG_A4XX_SP_PERFCTR_SP_SEL_9 0x00000ecd 2284 2285 #define REG_A4XX_SP_PERFCTR_SP_SEL_10 0x00000ece 2286 2287 #define REG_A4XX_SP_PERFCTR_SP_SEL_11 0x00000ecf 2288 2289 #define REG_A4XX_SP_SP_CTRL_REG 0x000022c0 2290 #define A4XX_SP_SP_CTRL_REG_BINNING_PASS 0x00080000 2291 2292 #define REG_A4XX_SP_INSTR_CACHE_CTRL 0x000022c1 2293 #define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER 0x00000080 2294 #define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER 0x00000100 2295 #define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER 0x00000400 2296 2297 #define REG_A4XX_SP_VS_CTRL_REG0 0x000022c4 2298 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 2299 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 2300 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 2301 { 2302 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK; 2303 } 2304 #define A4XX_SP_VS_CTRL_REG0_VARYING 0x00000002 2305 #define A4XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004 2306 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 2307 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 2308 static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 2309 { 2310 return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 2311 } 2312 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 2313 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 2314 static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 2315 { 2316 return ((val) << A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 2317 } 2318 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 2319 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 2320 static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 2321 { 2322 return ((val) << A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK; 2323 } 2324 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000 2325 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20 2326 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 2327 { 2328 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; 2329 } 2330 #define A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000 2331 #define A4XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000 2332 2333 #define REG_A4XX_SP_VS_CTRL_REG1 0x000022c5 2334 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff 2335 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0 2336 static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) 2337 { 2338 return ((val) << A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK; 2339 } 2340 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000 2341 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24 2342 static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) 2343 { 2344 return ((val) << A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK; 2345 } 2346 2347 #define REG_A4XX_SP_VS_PARAM_REG 0x000022c6 2348 #define A4XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff 2349 #define A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0 2350 static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) 2351 { 2352 return ((val) << A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_POSREGID__MASK; 2353 } 2354 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00 2355 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8 2356 static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) 2357 { 2358 return ((val) << A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK; 2359 } 2360 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000 2361 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20 2362 static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) 2363 { 2364 return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; 2365 } 2366 2367 static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 2368 2369 static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 2370 #define A4XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff 2371 #define A4XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 2372 static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 2373 { 2374 return ((val) << A4XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_A_REGID__MASK; 2375 } 2376 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00 2377 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9 2378 static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 2379 { 2380 return ((val) << A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 2381 } 2382 #define A4XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000 2383 #define A4XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 2384 static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 2385 { 2386 return ((val) << A4XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_B_REGID__MASK; 2387 } 2388 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000 2389 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25 2390 static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 2391 { 2392 return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 2393 } 2394 2395 static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; } 2396 2397 static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; } 2398 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 2399 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 2400 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 2401 { 2402 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 2403 } 2404 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 2405 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 2406 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 2407 { 2408 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 2409 } 2410 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 2411 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 2412 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 2413 { 2414 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 2415 } 2416 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 2417 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 2418 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 2419 { 2420 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 2421 } 2422 2423 #define REG_A4XX_SP_VS_OBJ_OFFSET_REG 0x000022e0 2424 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2425 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2426 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2427 { 2428 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2429 } 2430 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2431 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2432 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2433 { 2434 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2435 } 2436 2437 #define REG_A4XX_SP_VS_OBJ_START 0x000022e1 2438 2439 #define REG_A4XX_SP_VS_PVT_MEM_PARAM 0x000022e2 2440 2441 #define REG_A4XX_SP_VS_PVT_MEM_ADDR 0x000022e3 2442 2443 #define REG_A4XX_SP_VS_LENGTH_REG 0x000022e5 2444 2445 #define REG_A4XX_SP_FS_CTRL_REG0 0x000022e8 2446 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 2447 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 2448 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 2449 { 2450 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK; 2451 } 2452 #define A4XX_SP_FS_CTRL_REG0_VARYING 0x00000002 2453 #define A4XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004 2454 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 2455 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 2456 static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 2457 { 2458 return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 2459 } 2460 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 2461 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 2462 static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 2463 { 2464 return ((val) << A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 2465 } 2466 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 2467 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 2468 static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 2469 { 2470 return ((val) << A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK; 2471 } 2472 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 2473 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 2474 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 2475 { 2476 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 2477 } 2478 #define A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000 2479 #define A4XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000 2480 2481 #define REG_A4XX_SP_FS_CTRL_REG1 0x000022e9 2482 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff 2483 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0 2484 static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) 2485 { 2486 return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK; 2487 } 2488 #define A4XX_SP_FS_CTRL_REG1_FACENESS 0x00080000 2489 #define A4XX_SP_FS_CTRL_REG1_VARYING 0x00100000 2490 #define A4XX_SP_FS_CTRL_REG1_FRAGCOORD 0x00200000 2491 2492 #define REG_A4XX_SP_FS_OBJ_OFFSET_REG 0x000022ea 2493 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2494 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2495 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2496 { 2497 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2498 } 2499 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2500 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2501 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2502 { 2503 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2504 } 2505 2506 #define REG_A4XX_SP_FS_OBJ_START 0x000022eb 2507 2508 #define REG_A4XX_SP_FS_PVT_MEM_PARAM 0x000022ec 2509 2510 #define REG_A4XX_SP_FS_PVT_MEM_ADDR 0x000022ed 2511 2512 #define REG_A4XX_SP_FS_LENGTH_REG 0x000022ef 2513 2514 #define REG_A4XX_SP_FS_OUTPUT_REG 0x000022f0 2515 #define A4XX_SP_FS_OUTPUT_REG_MRT__MASK 0x0000000f 2516 #define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0 2517 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val) 2518 { 2519 return ((val) << A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_SP_FS_OUTPUT_REG_MRT__MASK; 2520 } 2521 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080 2522 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00 2523 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8 2524 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) 2525 { 2526 return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK; 2527 } 2528 #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK 0xff000000 2529 #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT 24 2530 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val) 2531 { 2532 return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK; 2533 } 2534 2535 static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; } 2536 2537 static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; } 2538 #define A4XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff 2539 #define A4XX_SP_FS_MRT_REG_REGID__SHIFT 0 2540 static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val) 2541 { 2542 return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK; 2543 } 2544 #define A4XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100 2545 #define A4XX_SP_FS_MRT_REG_COLOR_SINT 0x00000400 2546 #define A4XX_SP_FS_MRT_REG_COLOR_UINT 0x00000800 2547 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK 0x0003f000 2548 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT 12 2549 static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val) 2550 { 2551 return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK; 2552 } 2553 #define A4XX_SP_FS_MRT_REG_COLOR_SRGB 0x00040000 2554 2555 #define REG_A4XX_SP_CS_CTRL_REG0 0x00002300 2556 #define A4XX_SP_CS_CTRL_REG0_THREADMODE__MASK 0x00000001 2557 #define A4XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT 0 2558 static inline uint32_t A4XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 2559 { 2560 return ((val) << A4XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_CS_CTRL_REG0_THREADMODE__MASK; 2561 } 2562 #define A4XX_SP_CS_CTRL_REG0_VARYING 0x00000002 2563 #define A4XX_SP_CS_CTRL_REG0_CACHEINVALID 0x00000004 2564 #define A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 2565 #define A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 2566 static inline uint32_t A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 2567 { 2568 return ((val) << A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 2569 } 2570 #define A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 2571 #define A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 2572 static inline uint32_t A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 2573 { 2574 return ((val) << A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 2575 } 2576 #define A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 2577 #define A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 2578 static inline uint32_t A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 2579 { 2580 return ((val) << A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP__MASK; 2581 } 2582 #define A4XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000 2583 #define A4XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20 2584 static inline uint32_t A4XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 2585 { 2586 return ((val) << A4XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_CS_CTRL_REG0_THREADSIZE__MASK; 2587 } 2588 #define A4XX_SP_CS_CTRL_REG0_SUPERTHREADMODE 0x00200000 2589 #define A4XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x00400000 2590 2591 #define REG_A4XX_SP_CS_OBJ_OFFSET_REG 0x00002301 2592 2593 #define REG_A4XX_SP_CS_OBJ_START 0x00002302 2594 2595 #define REG_A4XX_SP_CS_PVT_MEM_PARAM 0x00002303 2596 2597 #define REG_A4XX_SP_CS_PVT_MEM_ADDR 0x00002304 2598 2599 #define REG_A4XX_SP_CS_PVT_MEM_SIZE 0x00002305 2600 2601 #define REG_A4XX_SP_CS_LENGTH_REG 0x00002306 2602 2603 #define REG_A4XX_SP_HS_OBJ_OFFSET_REG 0x0000230d 2604 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2605 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2606 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2607 { 2608 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2609 } 2610 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2611 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2612 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2613 { 2614 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2615 } 2616 2617 #define REG_A4XX_SP_HS_OBJ_START 0x0000230e 2618 2619 #define REG_A4XX_SP_HS_PVT_MEM_PARAM 0x0000230f 2620 2621 #define REG_A4XX_SP_HS_PVT_MEM_ADDR 0x00002310 2622 2623 #define REG_A4XX_SP_HS_LENGTH_REG 0x00002312 2624 2625 #define REG_A4XX_SP_DS_PARAM_REG 0x0000231a 2626 #define A4XX_SP_DS_PARAM_REG_POSREGID__MASK 0x000000ff 2627 #define A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT 0 2628 static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val) 2629 { 2630 return ((val) << A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_DS_PARAM_REG_POSREGID__MASK; 2631 } 2632 #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000 2633 #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20 2634 static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) 2635 { 2636 return ((val) << A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK; 2637 } 2638 2639 static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; } 2640 2641 static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; } 2642 #define A4XX_SP_DS_OUT_REG_A_REGID__MASK 0x000001ff 2643 #define A4XX_SP_DS_OUT_REG_A_REGID__SHIFT 0 2644 static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val) 2645 { 2646 return ((val) << A4XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_A_REGID__MASK; 2647 } 2648 #define A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00001e00 2649 #define A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 9 2650 static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val) 2651 { 2652 return ((val) << A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK; 2653 } 2654 #define A4XX_SP_DS_OUT_REG_B_REGID__MASK 0x01ff0000 2655 #define A4XX_SP_DS_OUT_REG_B_REGID__SHIFT 16 2656 static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val) 2657 { 2658 return ((val) << A4XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_B_REGID__MASK; 2659 } 2660 #define A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x1e000000 2661 #define A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 25 2662 static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val) 2663 { 2664 return ((val) << A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK; 2665 } 2666 2667 static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; } 2668 2669 static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; } 2670 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 2671 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0 2672 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val) 2673 { 2674 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK; 2675 } 2676 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 2677 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8 2678 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val) 2679 { 2680 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK; 2681 } 2682 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 2683 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16 2684 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val) 2685 { 2686 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK; 2687 } 2688 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 2689 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24 2690 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) 2691 { 2692 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK; 2693 } 2694 2695 #define REG_A4XX_SP_DS_OBJ_OFFSET_REG 0x00002334 2696 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2697 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2698 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2699 { 2700 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2701 } 2702 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2703 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2704 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2705 { 2706 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2707 } 2708 2709 #define REG_A4XX_SP_DS_OBJ_START 0x00002335 2710 2711 #define REG_A4XX_SP_DS_PVT_MEM_PARAM 0x00002336 2712 2713 #define REG_A4XX_SP_DS_PVT_MEM_ADDR 0x00002337 2714 2715 #define REG_A4XX_SP_DS_LENGTH_REG 0x00002339 2716 2717 #define REG_A4XX_SP_GS_PARAM_REG 0x00002341 2718 #define A4XX_SP_GS_PARAM_REG_POSREGID__MASK 0x000000ff 2719 #define A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT 0 2720 static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val) 2721 { 2722 return ((val) << A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_POSREGID__MASK; 2723 } 2724 #define A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK 0x0000ff00 2725 #define A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT 8 2726 static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val) 2727 { 2728 return ((val) << A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK; 2729 } 2730 #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000 2731 #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20 2732 static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) 2733 { 2734 return ((val) << A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK; 2735 } 2736 2737 static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; } 2738 2739 static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; } 2740 #define A4XX_SP_GS_OUT_REG_A_REGID__MASK 0x000001ff 2741 #define A4XX_SP_GS_OUT_REG_A_REGID__SHIFT 0 2742 static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val) 2743 { 2744 return ((val) << A4XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_A_REGID__MASK; 2745 } 2746 #define A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00001e00 2747 #define A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 9 2748 static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val) 2749 { 2750 return ((val) << A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK; 2751 } 2752 #define A4XX_SP_GS_OUT_REG_B_REGID__MASK 0x01ff0000 2753 #define A4XX_SP_GS_OUT_REG_B_REGID__SHIFT 16 2754 static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val) 2755 { 2756 return ((val) << A4XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_B_REGID__MASK; 2757 } 2758 #define A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x1e000000 2759 #define A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 25 2760 static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val) 2761 { 2762 return ((val) << A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK; 2763 } 2764 2765 static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; } 2766 2767 static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; } 2768 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 2769 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0 2770 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val) 2771 { 2772 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK; 2773 } 2774 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 2775 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8 2776 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val) 2777 { 2778 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK; 2779 } 2780 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 2781 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16 2782 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val) 2783 { 2784 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK; 2785 } 2786 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 2787 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24 2788 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) 2789 { 2790 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK; 2791 } 2792 2793 #define REG_A4XX_SP_GS_OBJ_OFFSET_REG 0x0000235b 2794 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2795 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2796 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2797 { 2798 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2799 } 2800 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2801 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2802 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2803 { 2804 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2805 } 2806 2807 #define REG_A4XX_SP_GS_OBJ_START 0x0000235c 2808 2809 #define REG_A4XX_SP_GS_PVT_MEM_PARAM 0x0000235d 2810 2811 #define REG_A4XX_SP_GS_PVT_MEM_ADDR 0x0000235e 2812 2813 #define REG_A4XX_SP_GS_LENGTH_REG 0x00002360 2814 2815 #define REG_A4XX_VPC_DEBUG_RAM_SEL 0x00000e60 2816 2817 #define REG_A4XX_VPC_DEBUG_RAM_READ 0x00000e61 2818 2819 #define REG_A4XX_VPC_DEBUG_ECO_CONTROL 0x00000e64 2820 2821 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_0 0x00000e65 2822 2823 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_1 0x00000e66 2824 2825 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_2 0x00000e67 2826 2827 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_3 0x00000e68 2828 2829 #define REG_A4XX_VPC_ATTR 0x00002140 2830 #define A4XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff 2831 #define A4XX_VPC_ATTR_TOTALATTR__SHIFT 0 2832 static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val) 2833 { 2834 return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK; 2835 } 2836 #define A4XX_VPC_ATTR_PSIZE 0x00000200 2837 #define A4XX_VPC_ATTR_THRDASSIGN__MASK 0x00003000 2838 #define A4XX_VPC_ATTR_THRDASSIGN__SHIFT 12 2839 static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val) 2840 { 2841 return ((val) << A4XX_VPC_ATTR_THRDASSIGN__SHIFT) & A4XX_VPC_ATTR_THRDASSIGN__MASK; 2842 } 2843 #define A4XX_VPC_ATTR_ENABLE 0x02000000 2844 2845 #define REG_A4XX_VPC_PACK 0x00002141 2846 #define A4XX_VPC_PACK_NUMBYPASSVAR__MASK 0x000000ff 2847 #define A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT 0 2848 static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val) 2849 { 2850 return ((val) << A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT) & A4XX_VPC_PACK_NUMBYPASSVAR__MASK; 2851 } 2852 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00 2853 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8 2854 static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) 2855 { 2856 return ((val) << A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK; 2857 } 2858 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000 2859 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16 2860 static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) 2861 { 2862 return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK; 2863 } 2864 2865 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; } 2866 2867 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; } 2868 2869 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; } 2870 2871 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; } 2872 2873 #define REG_A4XX_VPC_SO_FLUSH_WADDR_3 0x0000216e 2874 2875 #define REG_A4XX_VSC_BIN_SIZE 0x00000c00 2876 #define A4XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 2877 #define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 2878 static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 2879 { 2880 return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK; 2881 } 2882 #define A4XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 2883 #define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5 2884 static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 2885 { 2886 return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK; 2887 } 2888 2889 #define REG_A4XX_VSC_SIZE_ADDRESS 0x00000c01 2890 2891 #define REG_A4XX_VSC_SIZE_ADDRESS2 0x00000c02 2892 2893 #define REG_A4XX_VSC_DEBUG_ECO_CONTROL 0x00000c03 2894 2895 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } 2896 2897 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } 2898 #define A4XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff 2899 #define A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0 2900 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) 2901 { 2902 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_X__MASK; 2903 } 2904 #define A4XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00 2905 #define A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10 2906 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) 2907 { 2908 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_Y__MASK; 2909 } 2910 #define A4XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000 2911 #define A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20 2912 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) 2913 { 2914 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_W__MASK; 2915 } 2916 #define A4XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000 2917 #define A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24 2918 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) 2919 { 2920 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK; 2921 } 2922 2923 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 2924 2925 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 2926 2927 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; } 2928 2929 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; } 2930 2931 #define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1 0x00000c41 2932 2933 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_0 0x00000c50 2934 2935 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_1 0x00000c51 2936 2937 #define REG_A4XX_VFD_DEBUG_CONTROL 0x00000e40 2938 2939 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_0 0x00000e43 2940 2941 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_1 0x00000e44 2942 2943 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_2 0x00000e45 2944 2945 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_3 0x00000e46 2946 2947 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_4 0x00000e47 2948 2949 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_5 0x00000e48 2950 2951 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_6 0x00000e49 2952 2953 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 0x00000e4a 2954 2955 #define REG_A4XX_VGT_CL_INITIATOR 0x000021d0 2956 2957 #define REG_A4XX_VGT_EVENT_INITIATOR 0x000021d9 2958 2959 #define REG_A4XX_VFD_CONTROL_0 0x00002200 2960 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x000000ff 2961 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0 2962 static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) 2963 { 2964 return ((val) << A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK; 2965 } 2966 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK 0x0001fe00 2967 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT 9 2968 static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val) 2969 { 2970 return ((val) << A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT) & A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK; 2971 } 2972 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x03f00000 2973 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 20 2974 static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) 2975 { 2976 return ((val) << A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK; 2977 } 2978 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xfc000000 2979 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 26 2980 static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) 2981 { 2982 return ((val) << A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK; 2983 } 2984 2985 #define REG_A4XX_VFD_CONTROL_1 0x00002201 2986 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff 2987 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0 2988 static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) 2989 { 2990 return ((val) << A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK; 2991 } 2992 #define A4XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000 2993 #define A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16 2994 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 2995 { 2996 return ((val) << A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A4XX_VFD_CONTROL_1_REGID4VTX__MASK; 2997 } 2998 #define A4XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000 2999 #define A4XX_VFD_CONTROL_1_REGID4INST__SHIFT 24 3000 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 3001 { 3002 return ((val) << A4XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A4XX_VFD_CONTROL_1_REGID4INST__MASK; 3003 } 3004 3005 #define REG_A4XX_VFD_CONTROL_2 0x00002202 3006 3007 #define REG_A4XX_VFD_CONTROL_3 0x00002203 3008 #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK 0x0000ff00 3009 #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT 8 3010 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val) 3011 { 3012 return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK; 3013 } 3014 #define A4XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000 3015 #define A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16 3016 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) 3017 { 3018 return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSX__MASK; 3019 } 3020 #define A4XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000 3021 #define A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24 3022 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) 3023 { 3024 return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSY__MASK; 3025 } 3026 3027 #define REG_A4XX_VFD_CONTROL_4 0x00002204 3028 3029 #define REG_A4XX_VFD_INDEX_OFFSET 0x00002208 3030 3031 static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; } 3032 3033 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; } 3034 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f 3035 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0 3036 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) 3037 { 3038 return ((val) << A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK; 3039 } 3040 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80 3041 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7 3042 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) 3043 { 3044 return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK; 3045 } 3046 #define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00080000 3047 #define A4XX_VFD_FETCH_INSTR_0_INSTANCED 0x00100000 3048 3049 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; } 3050 3051 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; } 3052 #define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xffffffff 3053 #define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 0 3054 static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val) 3055 { 3056 return ((val) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK; 3057 } 3058 3059 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; } 3060 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK 0x000001ff 3061 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT 0 3062 static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val) 3063 { 3064 return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK; 3065 } 3066 3067 static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; } 3068 3069 static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; } 3070 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f 3071 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0 3072 static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) 3073 { 3074 return ((val) << A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK; 3075 } 3076 #define A4XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010 3077 #define A4XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0 3078 #define A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6 3079 static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val) 3080 { 3081 return ((val) << A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A4XX_VFD_DECODE_INSTR_FORMAT__MASK; 3082 } 3083 #define A4XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000 3084 #define A4XX_VFD_DECODE_INSTR_REGID__SHIFT 12 3085 static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val) 3086 { 3087 return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK; 3088 } 3089 #define A4XX_VFD_DECODE_INSTR_INT 0x00100000 3090 #define A4XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000 3091 #define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT 22 3092 static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 3093 { 3094 return ((val) << A4XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A4XX_VFD_DECODE_INSTR_SWAP__MASK; 3095 } 3096 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000 3097 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24 3098 static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) 3099 { 3100 return ((val) << A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK; 3101 } 3102 #define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000 3103 #define A4XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000 3104 3105 #define REG_A4XX_TPL1_DEBUG_ECO_CONTROL 0x00000f00 3106 3107 #define REG_A4XX_TPL1_TP_MODE_CONTROL 0x00000f03 3108 3109 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_0 0x00000f04 3110 3111 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_1 0x00000f05 3112 3113 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_2 0x00000f06 3114 3115 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_3 0x00000f07 3116 3117 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_4 0x00000f08 3118 3119 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_5 0x00000f09 3120 3121 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_6 0x00000f0a 3122 3123 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 0x00000f0b 3124 3125 #define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380 3126 3127 #define REG_A4XX_TPL1_TP_TEX_COUNT 0x00002381 3128 #define A4XX_TPL1_TP_TEX_COUNT_VS__MASK 0x000000ff 3129 #define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT 0 3130 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val) 3131 { 3132 return ((val) << A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_VS__MASK; 3133 } 3134 #define A4XX_TPL1_TP_TEX_COUNT_HS__MASK 0x0000ff00 3135 #define A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT 8 3136 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val) 3137 { 3138 return ((val) << A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_HS__MASK; 3139 } 3140 #define A4XX_TPL1_TP_TEX_COUNT_DS__MASK 0x00ff0000 3141 #define A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT 16 3142 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val) 3143 { 3144 return ((val) << A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_DS__MASK; 3145 } 3146 #define A4XX_TPL1_TP_TEX_COUNT_GS__MASK 0xff000000 3147 #define A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT 24 3148 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val) 3149 { 3150 return ((val) << A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_GS__MASK; 3151 } 3152 3153 #define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002384 3154 3155 #define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR 0x00002387 3156 3157 #define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR 0x0000238a 3158 3159 #define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR 0x0000238d 3160 3161 #define REG_A4XX_TPL1_TP_FS_TEX_COUNT 0x000023a0 3162 3163 #define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x000023a1 3164 3165 #define REG_A4XX_TPL1_TP_CS_BORDER_COLOR_BASE_ADDR 0x000023a4 3166 3167 #define REG_A4XX_TPL1_TP_CS_SAMPLER_BASE_ADDR 0x000023a5 3168 3169 #define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR 0x000023a6 3170 3171 #define REG_A4XX_GRAS_TSE_STATUS 0x00000c80 3172 3173 #define REG_A4XX_GRAS_DEBUG_ECO_CONTROL 0x00000c81 3174 3175 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c88 3176 3177 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c89 3178 3179 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c8a 3180 3181 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c8b 3182 3183 #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c8c 3184 3185 #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c8d 3186 3187 #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c8e 3188 3189 #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c8f 3190 3191 #define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000 3192 #define A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00008000 3193 #define A4XX_GRAS_CL_CLIP_CNTL_ZNEAR_CLIP_DISABLE 0x00010000 3194 #define A4XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000 3195 #define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000 3196 3197 #define REG_A4XX_GRAS_CNTL 0x00002003 3198 #define A4XX_GRAS_CNTL_IJ_PERSP 0x00000001 3199 #define A4XX_GRAS_CNTL_IJ_LINEAR 0x00000002 3200 3201 #define REG_A4XX_GRAS_CL_GB_CLIP_ADJ 0x00002004 3202 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff 3203 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0 3204 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) 3205 { 3206 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; 3207 } 3208 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00 3209 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10 3210 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) 3211 { 3212 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; 3213 } 3214 3215 #define REG_A4XX_GRAS_CL_VPORT_XOFFSET_0 0x00002008 3216 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff 3217 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0 3218 static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val) 3219 { 3220 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK; 3221 } 3222 3223 #define REG_A4XX_GRAS_CL_VPORT_XSCALE_0 0x00002009 3224 #define A4XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff 3225 #define A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0 3226 static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val) 3227 { 3228 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_XSCALE_0__MASK; 3229 } 3230 3231 #define REG_A4XX_GRAS_CL_VPORT_YOFFSET_0 0x0000200a 3232 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff 3233 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0 3234 static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val) 3235 { 3236 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK; 3237 } 3238 3239 #define REG_A4XX_GRAS_CL_VPORT_YSCALE_0 0x0000200b 3240 #define A4XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff 3241 #define A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0 3242 static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val) 3243 { 3244 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_YSCALE_0__MASK; 3245 } 3246 3247 #define REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000200c 3248 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff 3249 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0 3250 static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val) 3251 { 3252 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK; 3253 } 3254 3255 #define REG_A4XX_GRAS_CL_VPORT_ZSCALE_0 0x0000200d 3256 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff 3257 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0 3258 static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val) 3259 { 3260 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK; 3261 } 3262 3263 #define REG_A4XX_GRAS_SU_POINT_MINMAX 0x00002070 3264 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 3265 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 3266 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val) 3267 { 3268 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 3269 } 3270 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 3271 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 3272 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val) 3273 { 3274 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 3275 } 3276 3277 #define REG_A4XX_GRAS_SU_POINT_SIZE 0x00002071 3278 #define A4XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff 3279 #define A4XX_GRAS_SU_POINT_SIZE__SHIFT 0 3280 static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val) 3281 { 3282 return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK; 3283 } 3284 3285 #define REG_A4XX_GRAS_ALPHA_CONTROL 0x00002073 3286 #define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE 0x00000004 3287 #define A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS 0x00000008 3288 3289 #define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE 0x00002074 3290 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff 3291 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 3292 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val) 3293 { 3294 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; 3295 } 3296 3297 #define REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00002075 3298 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 3299 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 3300 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 3301 { 3302 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 3303 } 3304 3305 #define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP 0x00002076 3306 #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK 0xffffffff 3307 #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT 0 3308 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val) 3309 { 3310 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK; 3311 } 3312 3313 #define REG_A4XX_GRAS_DEPTH_CONTROL 0x00002077 3314 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK 0x00000003 3315 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT 0 3316 static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val) 3317 { 3318 return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK; 3319 } 3320 3321 #define REG_A4XX_GRAS_SU_MODE_CONTROL 0x00002078 3322 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001 3323 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002 3324 #define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004 3325 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8 3326 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3 3327 static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) 3328 { 3329 return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; 3330 } 3331 #define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800 3332 #define A4XX_GRAS_SU_MODE_CONTROL_MSAA_ENABLE 0x00002000 3333 #define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS 0x00100000 3334 3335 #define REG_A4XX_GRAS_SC_CONTROL 0x0000207b 3336 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x0000000c 3337 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 2 3338 static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) 3339 { 3340 return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK; 3341 } 3342 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000380 3343 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 7 3344 static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val) 3345 { 3346 return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK; 3347 } 3348 #define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE 0x00000800 3349 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000 3350 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12 3351 static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) 3352 { 3353 return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK; 3354 } 3355 3356 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL 0x0000207c 3357 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 3358 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 3359 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 3360 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 3361 { 3362 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; 3363 } 3364 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 3365 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 3366 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 3367 { 3368 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; 3369 } 3370 3371 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR 0x0000207d 3372 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 3373 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 3374 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 3375 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 3376 { 3377 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; 3378 } 3379 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 3380 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 3381 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 3382 { 3383 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; 3384 } 3385 3386 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000209c 3387 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 3388 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 3389 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 3390 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 3391 { 3392 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 3393 } 3394 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 3395 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 3396 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 3397 { 3398 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 3399 } 3400 3401 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000209d 3402 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 3403 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 3404 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 3405 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 3406 { 3407 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 3408 } 3409 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 3410 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 3411 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 3412 { 3413 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 3414 } 3415 3416 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR 0x0000209e 3417 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE 0x80000000 3418 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK 0x00007fff 3419 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT 0 3420 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val) 3421 { 3422 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK; 3423 } 3424 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK 0x7fff0000 3425 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT 16 3426 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val) 3427 { 3428 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK; 3429 } 3430 3431 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL 0x0000209f 3432 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE 0x80000000 3433 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK 0x00007fff 3434 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT 0 3435 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val) 3436 { 3437 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK; 3438 } 3439 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK 0x7fff0000 3440 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT 16 3441 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val) 3442 { 3443 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK; 3444 } 3445 3446 #define REG_A4XX_UCHE_CACHE_MODE_CONTROL 0x00000e80 3447 3448 #define REG_A4XX_UCHE_TRAP_BASE_LO 0x00000e83 3449 3450 #define REG_A4XX_UCHE_TRAP_BASE_HI 0x00000e84 3451 3452 #define REG_A4XX_UCHE_CACHE_STATUS 0x00000e88 3453 3454 #define REG_A4XX_UCHE_INVALIDATE0 0x00000e8a 3455 3456 #define REG_A4XX_UCHE_INVALIDATE1 0x00000e8b 3457 3458 #define REG_A4XX_UCHE_CACHE_WAYS_VFD 0x00000e8c 3459 3460 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e8e 3461 3462 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e8f 3463 3464 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e90 3465 3466 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e91 3467 3468 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e92 3469 3470 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e93 3471 3472 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e94 3473 3474 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e95 3475 3476 #define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD 0x00000e00 3477 3478 #define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL 0x00000e04 3479 3480 #define REG_A4XX_HLSQ_MODE_CONTROL 0x00000e05 3481 3482 #define REG_A4XX_HLSQ_PERF_PIPE_MASK 0x00000e0e 3483 3484 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e06 3485 3486 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e07 3487 3488 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e08 3489 3490 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e09 3491 3492 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e0a 3493 3494 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e0b 3495 3496 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e0c 3497 3498 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e0d 3499 3500 #define REG_A4XX_HLSQ_CONTROL_0_REG 0x000023c0 3501 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010 3502 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4 3503 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) 3504 { 3505 return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; 3506 } 3507 #define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040 3508 #define A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200 3509 #define A4XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400 3510 #define A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000 3511 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000 3512 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27 3513 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) 3514 { 3515 return ((val) << A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK; 3516 } 3517 #define A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000 3518 #define A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000 3519 #define A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000 3520 #define A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000 3521 3522 #define REG_A4XX_HLSQ_CONTROL_1_REG 0x000023c1 3523 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040 3524 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6 3525 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) 3526 { 3527 return ((val) << A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK; 3528 } 3529 #define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100 3530 #define A4XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200 3531 #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK 0x00ff0000 3532 #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT 16 3533 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val) 3534 { 3535 return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK; 3536 } 3537 #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK 0xff000000 3538 #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT 24 3539 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val) 3540 { 3541 return ((val) << A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK; 3542 } 3543 3544 #define REG_A4XX_HLSQ_CONTROL_2_REG 0x000023c2 3545 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000 3546 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26 3547 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) 3548 { 3549 return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK; 3550 } 3551 #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000003fc 3552 #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 2 3553 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) 3554 { 3555 return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; 3556 } 3557 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK 0x0003fc00 3558 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT 10 3559 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val) 3560 { 3561 return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK; 3562 } 3563 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK 0x03fc0000 3564 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT 18 3565 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val) 3566 { 3567 return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK; 3568 } 3569 3570 #define REG_A4XX_HLSQ_CONTROL_3_REG 0x000023c3 3571 #define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff 3572 #define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0 3573 static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val) 3574 { 3575 return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK; 3576 } 3577 #define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00 3578 #define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8 3579 static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val) 3580 { 3581 return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK; 3582 } 3583 #define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000 3584 #define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16 3585 static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val) 3586 { 3587 return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK; 3588 } 3589 #define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000 3590 #define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24 3591 static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) 3592 { 3593 return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK; 3594 } 3595 3596 #define REG_A4XX_HLSQ_CONTROL_4_REG 0x000023c4 3597 #define A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff 3598 #define A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0 3599 static inline uint32_t A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val) 3600 { 3601 return ((val) << A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK; 3602 } 3603 #define A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00 3604 #define A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8 3605 static inline uint32_t A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val) 3606 { 3607 return ((val) << A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK; 3608 } 3609 3610 #define REG_A4XX_HLSQ_VS_CONTROL_REG 0x000023c5 3611 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 3612 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0 3613 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) 3614 { 3615 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK; 3616 } 3617 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00 3618 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 3619 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3620 { 3621 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3622 } 3623 #define A4XX_HLSQ_VS_CONTROL_REG_SSBO_ENABLE 0x00008000 3624 #define A4XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00010000 3625 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 3626 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 3627 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3628 { 3629 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3630 } 3631 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 3632 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24 3633 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) 3634 { 3635 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK; 3636 } 3637 3638 #define REG_A4XX_HLSQ_FS_CONTROL_REG 0x000023c6 3639 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 3640 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0 3641 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) 3642 { 3643 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK; 3644 } 3645 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00 3646 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 3647 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3648 { 3649 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3650 } 3651 #define A4XX_HLSQ_FS_CONTROL_REG_SSBO_ENABLE 0x00008000 3652 #define A4XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00010000 3653 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 3654 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 3655 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3656 { 3657 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3658 } 3659 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 3660 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24 3661 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) 3662 { 3663 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK; 3664 } 3665 3666 #define REG_A4XX_HLSQ_HS_CONTROL_REG 0x000023c7 3667 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 3668 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT 0 3669 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val) 3670 { 3671 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK; 3672 } 3673 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00 3674 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 3675 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3676 { 3677 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3678 } 3679 #define A4XX_HLSQ_HS_CONTROL_REG_SSBO_ENABLE 0x00008000 3680 #define A4XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00010000 3681 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 3682 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 3683 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3684 { 3685 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3686 } 3687 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 3688 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT 24 3689 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val) 3690 { 3691 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK; 3692 } 3693 3694 #define REG_A4XX_HLSQ_DS_CONTROL_REG 0x000023c8 3695 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 3696 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT 0 3697 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val) 3698 { 3699 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK; 3700 } 3701 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00 3702 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 3703 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3704 { 3705 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3706 } 3707 #define A4XX_HLSQ_DS_CONTROL_REG_SSBO_ENABLE 0x00008000 3708 #define A4XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00010000 3709 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 3710 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 3711 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3712 { 3713 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3714 } 3715 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 3716 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT 24 3717 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val) 3718 { 3719 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK; 3720 } 3721 3722 #define REG_A4XX_HLSQ_GS_CONTROL_REG 0x000023c9 3723 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 3724 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT 0 3725 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val) 3726 { 3727 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK; 3728 } 3729 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00 3730 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 3731 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3732 { 3733 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3734 } 3735 #define A4XX_HLSQ_GS_CONTROL_REG_SSBO_ENABLE 0x00008000 3736 #define A4XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00010000 3737 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 3738 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 3739 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3740 { 3741 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3742 } 3743 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 3744 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT 24 3745 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val) 3746 { 3747 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK; 3748 } 3749 3750 #define REG_A4XX_HLSQ_CS_CONTROL_REG 0x000023ca 3751 #define A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 3752 #define A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__SHIFT 0 3753 static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH(uint32_t val) 3754 { 3755 return ((val) << A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__MASK; 3756 } 3757 #define A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00 3758 #define A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 3759 static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3760 { 3761 return ((val) << A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3762 } 3763 #define A4XX_HLSQ_CS_CONTROL_REG_SSBO_ENABLE 0x00008000 3764 #define A4XX_HLSQ_CS_CONTROL_REG_ENABLED 0x00010000 3765 #define A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 3766 #define A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 3767 static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3768 { 3769 return ((val) << A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3770 } 3771 #define A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 3772 #define A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__SHIFT 24 3773 static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH(uint32_t val) 3774 { 3775 return ((val) << A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__MASK; 3776 } 3777 3778 #define REG_A4XX_HLSQ_CL_NDRANGE_0 0x000023cd 3779 #define A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__MASK 0x00000003 3780 #define A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__SHIFT 0 3781 static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM(uint32_t val) 3782 { 3783 return ((val) << A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__MASK; 3784 } 3785 #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc 3786 #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__SHIFT 2 3787 static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX(uint32_t val) 3788 { 3789 return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__MASK; 3790 } 3791 #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000 3792 #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__SHIFT 12 3793 static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY(uint32_t val) 3794 { 3795 return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__MASK; 3796 } 3797 #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000 3798 #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__SHIFT 22 3799 static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ(uint32_t val) 3800 { 3801 return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__MASK; 3802 } 3803 3804 #define REG_A4XX_HLSQ_CL_NDRANGE_1 0x000023ce 3805 #define A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__MASK 0xffffffff 3806 #define A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__SHIFT 0 3807 static inline uint32_t A4XX_HLSQ_CL_NDRANGE_1_SIZE_X(uint32_t val) 3808 { 3809 return ((val) << A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__SHIFT) & A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__MASK; 3810 } 3811 3812 #define REG_A4XX_HLSQ_CL_NDRANGE_2 0x000023cf 3813 3814 #define REG_A4XX_HLSQ_CL_NDRANGE_3 0x000023d0 3815 #define A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__MASK 0xffffffff 3816 #define A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__SHIFT 0 3817 static inline uint32_t A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y(uint32_t val) 3818 { 3819 return ((val) << A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__SHIFT) & A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__MASK; 3820 } 3821 3822 #define REG_A4XX_HLSQ_CL_NDRANGE_4 0x000023d1 3823 3824 #define REG_A4XX_HLSQ_CL_NDRANGE_5 0x000023d2 3825 #define A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__MASK 0xffffffff 3826 #define A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__SHIFT 0 3827 static inline uint32_t A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z(uint32_t val) 3828 { 3829 return ((val) << A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__SHIFT) & A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__MASK; 3830 } 3831 3832 #define REG_A4XX_HLSQ_CL_NDRANGE_6 0x000023d3 3833 3834 #define REG_A4XX_HLSQ_CL_CONTROL_0 0x000023d4 3835 #define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK 0x00000fff 3836 #define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__SHIFT 0 3837 static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID(uint32_t val) 3838 { 3839 return ((val) << A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__SHIFT) & A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK; 3840 } 3841 #define A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID__MASK 0x00fff000 3842 #define A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID__SHIFT 12 3843 static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID(uint32_t val) 3844 { 3845 return ((val) << A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID__SHIFT) & A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID__MASK; 3846 } 3847 #define A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__MASK 0xff000000 3848 #define A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__SHIFT 24 3849 static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID(uint32_t val) 3850 { 3851 return ((val) << A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__SHIFT) & A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__MASK; 3852 } 3853 3854 #define REG_A4XX_HLSQ_CL_CONTROL_1 0x000023d5 3855 #define A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID__MASK 0x00000fff 3856 #define A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID__SHIFT 0 3857 static inline uint32_t A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID(uint32_t val) 3858 { 3859 return ((val) << A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID__SHIFT) & A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID__MASK; 3860 } 3861 #define A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID__MASK 0x00fff000 3862 #define A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID__SHIFT 12 3863 static inline uint32_t A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID(uint32_t val) 3864 { 3865 return ((val) << A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID__SHIFT) & A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID__MASK; 3866 } 3867 3868 #define REG_A4XX_HLSQ_CL_KERNEL_CONST 0x000023d6 3869 #define A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID__MASK 0x00000fff 3870 #define A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID__SHIFT 0 3871 static inline uint32_t A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID(uint32_t val) 3872 { 3873 return ((val) << A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID__SHIFT) & A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID__MASK; 3874 } 3875 #define A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID__MASK 0x00fff000 3876 #define A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID__SHIFT 12 3877 static inline uint32_t A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID(uint32_t val) 3878 { 3879 return ((val) << A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID__SHIFT) & A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID__MASK; 3880 } 3881 3882 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_X 0x000023d7 3883 3884 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Y 0x000023d8 3885 3886 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z 0x000023d9 3887 3888 #define REG_A4XX_HLSQ_CL_WG_OFFSET 0x000023da 3889 #define A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID__MASK 0x00000fff 3890 #define A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID__SHIFT 0 3891 static inline uint32_t A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID(uint32_t val) 3892 { 3893 return ((val) << A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID__SHIFT) & A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID__MASK; 3894 } 3895 3896 #define REG_A4XX_HLSQ_UPDATE_CONTROL 0x000023db 3897 3898 #define REG_A4XX_PC_BINNING_COMMAND 0x00000d00 3899 #define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001 3900 3901 #define REG_A4XX_PC_TESSFACTOR_ADDR 0x00000d08 3902 3903 #define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c 3904 3905 #define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10 3906 3907 #define REG_A4XX_PC_PERFCTR_PC_SEL_1 0x00000d11 3908 3909 #define REG_A4XX_PC_PERFCTR_PC_SEL_2 0x00000d12 3910 3911 #define REG_A4XX_PC_PERFCTR_PC_SEL_3 0x00000d13 3912 3913 #define REG_A4XX_PC_PERFCTR_PC_SEL_4 0x00000d14 3914 3915 #define REG_A4XX_PC_PERFCTR_PC_SEL_5 0x00000d15 3916 3917 #define REG_A4XX_PC_PERFCTR_PC_SEL_6 0x00000d16 3918 3919 #define REG_A4XX_PC_PERFCTR_PC_SEL_7 0x00000d17 3920 3921 #define REG_A4XX_PC_BIN_BASE 0x000021c0 3922 3923 #define REG_A4XX_PC_VSTREAM_CONTROL 0x000021c2 3924 #define A4XX_PC_VSTREAM_CONTROL_SIZE__MASK 0x003f0000 3925 #define A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT 16 3926 static inline uint32_t A4XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val) 3927 { 3928 return ((val) << A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A4XX_PC_VSTREAM_CONTROL_SIZE__MASK; 3929 } 3930 #define A4XX_PC_VSTREAM_CONTROL_N__MASK 0x07c00000 3931 #define A4XX_PC_VSTREAM_CONTROL_N__SHIFT 22 3932 static inline uint32_t A4XX_PC_VSTREAM_CONTROL_N(uint32_t val) 3933 { 3934 return ((val) << A4XX_PC_VSTREAM_CONTROL_N__SHIFT) & A4XX_PC_VSTREAM_CONTROL_N__MASK; 3935 } 3936 3937 #define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4 3938 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK 0x0000000f 3939 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT 0 3940 static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val) 3941 { 3942 return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK; 3943 } 3944 #define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000 3945 #define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000 3946 #define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000 3947 3948 #define REG_A4XX_PC_PRIM_VTX_CNTL2 0x000021c5 3949 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK 0x00000007 3950 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT 0 3951 static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 3952 { 3953 return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK; 3954 } 3955 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK 0x00000038 3956 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT 3 3957 static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 3958 { 3959 return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK; 3960 } 3961 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_ENABLE 0x00000040 3962 3963 #define REG_A4XX_PC_RESTART_INDEX 0x000021c6 3964 3965 #define REG_A4XX_PC_GS_PARAM 0x000021e5 3966 #define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff 3967 #define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0 3968 static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val) 3969 { 3970 return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK; 3971 } 3972 #define A4XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800 3973 #define A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11 3974 static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val) 3975 { 3976 return ((val) << A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A4XX_PC_GS_PARAM_INVOCATIONS__MASK; 3977 } 3978 #define A4XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000 3979 #define A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23 3980 static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val) 3981 { 3982 return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK; 3983 } 3984 #define A4XX_PC_GS_PARAM_LAYER 0x80000000 3985 3986 #define REG_A4XX_PC_HS_PARAM 0x000021e7 3987 #define A4XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f 3988 #define A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0 3989 static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val) 3990 { 3991 return ((val) << A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A4XX_PC_HS_PARAM_VERTICES_OUT__MASK; 3992 } 3993 #define A4XX_PC_HS_PARAM_SPACING__MASK 0x00600000 3994 #define A4XX_PC_HS_PARAM_SPACING__SHIFT 21 3995 static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val) 3996 { 3997 return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK; 3998 } 3999 #define A4XX_PC_HS_PARAM_CW 0x00800000 4000 #define A4XX_PC_HS_PARAM_CONNECTED 0x01000000 4001 4002 #define REG_A4XX_VBIF_VERSION 0x00003000 4003 4004 #define REG_A4XX_VBIF_CLKON 0x00003001 4005 #define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000001 4006 4007 #define REG_A4XX_VBIF_ABIT_SORT 0x0000301c 4008 4009 #define REG_A4XX_VBIF_ABIT_SORT_CONF 0x0000301d 4010 4011 #define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 4012 4013 #define REG_A4XX_VBIF_IN_RD_LIM_CONF0 0x0000302c 4014 4015 #define REG_A4XX_VBIF_IN_RD_LIM_CONF1 0x0000302d 4016 4017 #define REG_A4XX_VBIF_IN_WR_LIM_CONF0 0x00003030 4018 4019 #define REG_A4XX_VBIF_IN_WR_LIM_CONF1 0x00003031 4020 4021 #define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049 4022 4023 #define REG_A4XX_VBIF_PERF_CNT_EN0 0x000030c0 4024 4025 #define REG_A4XX_VBIF_PERF_CNT_EN1 0x000030c1 4026 4027 #define REG_A4XX_VBIF_PERF_CNT_EN2 0x000030c2 4028 4029 #define REG_A4XX_VBIF_PERF_CNT_EN3 0x000030c3 4030 4031 #define REG_A4XX_VBIF_PERF_CNT_SEL0 0x000030d0 4032 4033 #define REG_A4XX_VBIF_PERF_CNT_SEL1 0x000030d1 4034 4035 #define REG_A4XX_VBIF_PERF_CNT_SEL2 0x000030d2 4036 4037 #define REG_A4XX_VBIF_PERF_CNT_SEL3 0x000030d3 4038 4039 #define REG_A4XX_VBIF_PERF_CNT_LOW0 0x000030d8 4040 4041 #define REG_A4XX_VBIF_PERF_CNT_LOW1 0x000030d9 4042 4043 #define REG_A4XX_VBIF_PERF_CNT_LOW2 0x000030da 4044 4045 #define REG_A4XX_VBIF_PERF_CNT_LOW3 0x000030db 4046 4047 #define REG_A4XX_VBIF_PERF_CNT_HIGH0 0x000030e0 4048 4049 #define REG_A4XX_VBIF_PERF_CNT_HIGH1 0x000030e1 4050 4051 #define REG_A4XX_VBIF_PERF_CNT_HIGH2 0x000030e2 4052 4053 #define REG_A4XX_VBIF_PERF_CNT_HIGH3 0x000030e3 4054 4055 #define REG_A4XX_VBIF_PERF_PWR_CNT_EN0 0x00003100 4056 4057 #define REG_A4XX_VBIF_PERF_PWR_CNT_EN1 0x00003101 4058 4059 #define REG_A4XX_VBIF_PERF_PWR_CNT_EN2 0x00003102 4060 4061 #define REG_A4XX_UNKNOWN_0CC5 0x00000cc5 4062 4063 #define REG_A4XX_UNKNOWN_0CC6 0x00000cc6 4064 4065 #define REG_A4XX_UNKNOWN_0D01 0x00000d01 4066 4067 #define REG_A4XX_UNKNOWN_0E42 0x00000e42 4068 4069 #define REG_A4XX_UNKNOWN_0EC2 0x00000ec2 4070 4071 #define REG_A4XX_UNKNOWN_2001 0x00002001 4072 4073 #define REG_A4XX_UNKNOWN_209B 0x0000209b 4074 4075 #define REG_A4XX_UNKNOWN_20EF 0x000020ef 4076 4077 #define REG_A4XX_UNKNOWN_2152 0x00002152 4078 4079 #define REG_A4XX_UNKNOWN_2153 0x00002153 4080 4081 #define REG_A4XX_UNKNOWN_2154 0x00002154 4082 4083 #define REG_A4XX_UNKNOWN_2155 0x00002155 4084 4085 #define REG_A4XX_UNKNOWN_2156 0x00002156 4086 4087 #define REG_A4XX_UNKNOWN_2157 0x00002157 4088 4089 #define REG_A4XX_UNKNOWN_21C3 0x000021c3 4090 4091 #define REG_A4XX_UNKNOWN_21E6 0x000021e6 4092 4093 #define REG_A4XX_UNKNOWN_2209 0x00002209 4094 4095 #define REG_A4XX_UNKNOWN_22D7 0x000022d7 4096 4097 #define REG_A4XX_UNKNOWN_2352 0x00002352 4098 4099 #define REG_A4XX_TEX_SAMP_0 0x00000000 4100 #define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 4101 #define A4XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 4102 #define A4XX_TEX_SAMP_0_XY_MAG__SHIFT 1 4103 static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val) 4104 { 4105 return ((val) << A4XX_TEX_SAMP_0_XY_MAG__SHIFT) & A4XX_TEX_SAMP_0_XY_MAG__MASK; 4106 } 4107 #define A4XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 4108 #define A4XX_TEX_SAMP_0_XY_MIN__SHIFT 3 4109 static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val) 4110 { 4111 return ((val) << A4XX_TEX_SAMP_0_XY_MIN__SHIFT) & A4XX_TEX_SAMP_0_XY_MIN__MASK; 4112 } 4113 #define A4XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 4114 #define A4XX_TEX_SAMP_0_WRAP_S__SHIFT 5 4115 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val) 4116 { 4117 return ((val) << A4XX_TEX_SAMP_0_WRAP_S__SHIFT) & A4XX_TEX_SAMP_0_WRAP_S__MASK; 4118 } 4119 #define A4XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 4120 #define A4XX_TEX_SAMP_0_WRAP_T__SHIFT 8 4121 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val) 4122 { 4123 return ((val) << A4XX_TEX_SAMP_0_WRAP_T__SHIFT) & A4XX_TEX_SAMP_0_WRAP_T__MASK; 4124 } 4125 #define A4XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 4126 #define A4XX_TEX_SAMP_0_WRAP_R__SHIFT 11 4127 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val) 4128 { 4129 return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK; 4130 } 4131 #define A4XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 4132 #define A4XX_TEX_SAMP_0_ANISO__SHIFT 14 4133 static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val) 4134 { 4135 return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK; 4136 } 4137 #define A4XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000 4138 #define A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19 4139 static inline uint32_t A4XX_TEX_SAMP_0_LOD_BIAS(float val) 4140 { 4141 return ((((int32_t)(val * 256.0))) << A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A4XX_TEX_SAMP_0_LOD_BIAS__MASK; 4142 } 4143 4144 #define REG_A4XX_TEX_SAMP_1 0x00000001 4145 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e 4146 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 4147 static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) 4148 { 4149 return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK; 4150 } 4151 #define A4XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010 4152 #define A4XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 4153 #define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 4154 #define A4XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 4155 #define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 4156 static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val) 4157 { 4158 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK; 4159 } 4160 #define A4XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 4161 #define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 4162 static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val) 4163 { 4164 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK; 4165 } 4166 4167 #define REG_A4XX_TEX_CONST_0 0x00000000 4168 #define A4XX_TEX_CONST_0_TILED 0x00000001 4169 #define A4XX_TEX_CONST_0_SRGB 0x00000004 4170 #define A4XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 4171 #define A4XX_TEX_CONST_0_SWIZ_X__SHIFT 4 4172 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val) 4173 { 4174 return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) & A4XX_TEX_CONST_0_SWIZ_X__MASK; 4175 } 4176 #define A4XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 4177 #define A4XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 4178 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val) 4179 { 4180 return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Y__MASK; 4181 } 4182 #define A4XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 4183 #define A4XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 4184 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val) 4185 { 4186 return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Z__MASK; 4187 } 4188 #define A4XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 4189 #define A4XX_TEX_CONST_0_SWIZ_W__SHIFT 13 4190 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val) 4191 { 4192 return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK; 4193 } 4194 #define A4XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 4195 #define A4XX_TEX_CONST_0_MIPLVLS__SHIFT 16 4196 static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val) 4197 { 4198 return ((val) << A4XX_TEX_CONST_0_MIPLVLS__SHIFT) & A4XX_TEX_CONST_0_MIPLVLS__MASK; 4199 } 4200 #define A4XX_TEX_CONST_0_FMT__MASK 0x1fc00000 4201 #define A4XX_TEX_CONST_0_FMT__SHIFT 22 4202 static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val) 4203 { 4204 return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK; 4205 } 4206 #define A4XX_TEX_CONST_0_TYPE__MASK 0xe0000000 4207 #define A4XX_TEX_CONST_0_TYPE__SHIFT 29 4208 static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val) 4209 { 4210 return ((val) << A4XX_TEX_CONST_0_TYPE__SHIFT) & A4XX_TEX_CONST_0_TYPE__MASK; 4211 } 4212 4213 #define REG_A4XX_TEX_CONST_1 0x00000001 4214 #define A4XX_TEX_CONST_1_HEIGHT__MASK 0x00007fff 4215 #define A4XX_TEX_CONST_1_HEIGHT__SHIFT 0 4216 static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val) 4217 { 4218 return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK; 4219 } 4220 #define A4XX_TEX_CONST_1_WIDTH__MASK 0x3fff8000 4221 #define A4XX_TEX_CONST_1_WIDTH__SHIFT 15 4222 static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val) 4223 { 4224 return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK; 4225 } 4226 4227 #define REG_A4XX_TEX_CONST_2 0x00000002 4228 #define A4XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f 4229 #define A4XX_TEX_CONST_2_PITCHALIGN__SHIFT 0 4230 static inline uint32_t A4XX_TEX_CONST_2_PITCHALIGN(uint32_t val) 4231 { 4232 return ((val) << A4XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A4XX_TEX_CONST_2_PITCHALIGN__MASK; 4233 } 4234 #define A4XX_TEX_CONST_2_BUFFER 0x00000040 4235 #define A4XX_TEX_CONST_2_PITCH__MASK 0x3ffffe00 4236 #define A4XX_TEX_CONST_2_PITCH__SHIFT 9 4237 static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val) 4238 { 4239 return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) & A4XX_TEX_CONST_2_PITCH__MASK; 4240 } 4241 #define A4XX_TEX_CONST_2_SWAP__MASK 0xc0000000 4242 #define A4XX_TEX_CONST_2_SWAP__SHIFT 30 4243 static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) 4244 { 4245 return ((val) << A4XX_TEX_CONST_2_SWAP__SHIFT) & A4XX_TEX_CONST_2_SWAP__MASK; 4246 } 4247 4248 #define REG_A4XX_TEX_CONST_3 0x00000003 4249 #define A4XX_TEX_CONST_3_LAYERSZ__MASK 0x00003fff 4250 #define A4XX_TEX_CONST_3_LAYERSZ__SHIFT 0 4251 static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val) 4252 { 4253 return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK; 4254 } 4255 #define A4XX_TEX_CONST_3_DEPTH__MASK 0x7ffc0000 4256 #define A4XX_TEX_CONST_3_DEPTH__SHIFT 18 4257 static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val) 4258 { 4259 return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK; 4260 } 4261 4262 #define REG_A4XX_TEX_CONST_4 0x00000004 4263 #define A4XX_TEX_CONST_4_LAYERSZ__MASK 0x0000000f 4264 #define A4XX_TEX_CONST_4_LAYERSZ__SHIFT 0 4265 static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val) 4266 { 4267 return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK; 4268 } 4269 #define A4XX_TEX_CONST_4_BASE__MASK 0xffffffe0 4270 #define A4XX_TEX_CONST_4_BASE__SHIFT 5 4271 static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val) 4272 { 4273 return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK; 4274 } 4275 4276 #define REG_A4XX_TEX_CONST_5 0x00000005 4277 4278 #define REG_A4XX_TEX_CONST_6 0x00000006 4279 4280 #define REG_A4XX_TEX_CONST_7 0x00000007 4281 4282 #define REG_A4XX_SSBO_0_0 0x00000000 4283 #define A4XX_SSBO_0_0_BASE__MASK 0xffffffe0 4284 #define A4XX_SSBO_0_0_BASE__SHIFT 5 4285 static inline uint32_t A4XX_SSBO_0_0_BASE(uint32_t val) 4286 { 4287 return ((val >> 5) << A4XX_SSBO_0_0_BASE__SHIFT) & A4XX_SSBO_0_0_BASE__MASK; 4288 } 4289 4290 #define REG_A4XX_SSBO_0_1 0x00000001 4291 #define A4XX_SSBO_0_1_PITCH__MASK 0x003fffff 4292 #define A4XX_SSBO_0_1_PITCH__SHIFT 0 4293 static inline uint32_t A4XX_SSBO_0_1_PITCH(uint32_t val) 4294 { 4295 return ((val) << A4XX_SSBO_0_1_PITCH__SHIFT) & A4XX_SSBO_0_1_PITCH__MASK; 4296 } 4297 4298 #define REG_A4XX_SSBO_0_2 0x00000002 4299 #define A4XX_SSBO_0_2_ARRAY_PITCH__MASK 0x03fff000 4300 #define A4XX_SSBO_0_2_ARRAY_PITCH__SHIFT 12 4301 static inline uint32_t A4XX_SSBO_0_2_ARRAY_PITCH(uint32_t val) 4302 { 4303 return ((val >> 12) << A4XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A4XX_SSBO_0_2_ARRAY_PITCH__MASK; 4304 } 4305 4306 #define REG_A4XX_SSBO_0_3 0x00000003 4307 #define A4XX_SSBO_0_3_CPP__MASK 0x0000003f 4308 #define A4XX_SSBO_0_3_CPP__SHIFT 0 4309 static inline uint32_t A4XX_SSBO_0_3_CPP(uint32_t val) 4310 { 4311 return ((val) << A4XX_SSBO_0_3_CPP__SHIFT) & A4XX_SSBO_0_3_CPP__MASK; 4312 } 4313 4314 #define REG_A4XX_SSBO_1_0 0x00000000 4315 #define A4XX_SSBO_1_0_CPP__MASK 0x0000001f 4316 #define A4XX_SSBO_1_0_CPP__SHIFT 0 4317 static inline uint32_t A4XX_SSBO_1_0_CPP(uint32_t val) 4318 { 4319 return ((val) << A4XX_SSBO_1_0_CPP__SHIFT) & A4XX_SSBO_1_0_CPP__MASK; 4320 } 4321 #define A4XX_SSBO_1_0_FMT__MASK 0x0000ff00 4322 #define A4XX_SSBO_1_0_FMT__SHIFT 8 4323 static inline uint32_t A4XX_SSBO_1_0_FMT(enum a4xx_color_fmt val) 4324 { 4325 return ((val) << A4XX_SSBO_1_0_FMT__SHIFT) & A4XX_SSBO_1_0_FMT__MASK; 4326 } 4327 #define A4XX_SSBO_1_0_WIDTH__MASK 0xffff0000 4328 #define A4XX_SSBO_1_0_WIDTH__SHIFT 16 4329 static inline uint32_t A4XX_SSBO_1_0_WIDTH(uint32_t val) 4330 { 4331 return ((val) << A4XX_SSBO_1_0_WIDTH__SHIFT) & A4XX_SSBO_1_0_WIDTH__MASK; 4332 } 4333 4334 #define REG_A4XX_SSBO_1_1 0x00000001 4335 #define A4XX_SSBO_1_1_HEIGHT__MASK 0x0000ffff 4336 #define A4XX_SSBO_1_1_HEIGHT__SHIFT 0 4337 static inline uint32_t A4XX_SSBO_1_1_HEIGHT(uint32_t val) 4338 { 4339 return ((val) << A4XX_SSBO_1_1_HEIGHT__SHIFT) & A4XX_SSBO_1_1_HEIGHT__MASK; 4340 } 4341 #define A4XX_SSBO_1_1_DEPTH__MASK 0xffff0000 4342 #define A4XX_SSBO_1_1_DEPTH__SHIFT 16 4343 static inline uint32_t A4XX_SSBO_1_1_DEPTH(uint32_t val) 4344 { 4345 return ((val) << A4XX_SSBO_1_1_DEPTH__SHIFT) & A4XX_SSBO_1_1_DEPTH__MASK; 4346 } 4347 4348 4349 #endif /* A4XX_XML */ 4350