1 #ifndef A4XX_XML 2 #define A4XX_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30) 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30) 15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 15085 bytes, from 2014-12-20 21:49:41) 16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 64344 bytes, from 2014-12-12 20:22:26) 17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 51069 bytes, from 2014-12-21 15:51:54) 18 19 Copyright (C) 2013-2014 by the following authors: 20 - Rob Clark <robdclark@gmail.com> (robclark) 21 22 Permission is hereby granted, free of charge, to any person obtaining 23 a copy of this software and associated documentation files (the 24 "Software"), to deal in the Software without restriction, including 25 without limitation the rights to use, copy, modify, merge, publish, 26 distribute, sublicense, and/or sell copies of the Software, and to 27 permit persons to whom the Software is furnished to do so, subject to 28 the following conditions: 29 30 The above copyright notice and this permission notice (including the 31 next paragraph) shall be included in all copies or substantial 32 portions of the Software. 33 34 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 36 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 37 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 38 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 39 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 40 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43 44 enum a4xx_color_fmt { 45 RB4_A8_UNORM = 1, 46 RB4_R5G6R5_UNORM = 14, 47 RB4_Z16_UNORM = 15, 48 RB4_R8G8B8_UNORM = 25, 49 RB4_R8G8B8A8_UNORM = 26, 50 }; 51 52 enum a4xx_tile_mode { 53 TILE4_LINEAR = 0, 54 TILE4_3 = 3, 55 }; 56 57 enum a4xx_rb_blend_opcode { 58 BLEND_DST_PLUS_SRC = 0, 59 BLEND_SRC_MINUS_DST = 1, 60 BLEND_DST_MINUS_SRC = 2, 61 BLEND_MIN_DST_SRC = 3, 62 BLEND_MAX_DST_SRC = 4, 63 }; 64 65 enum a4xx_vtx_fmt { 66 VFMT4_32_FLOAT = 1, 67 VFMT4_32_32_FLOAT = 2, 68 VFMT4_32_32_32_FLOAT = 3, 69 VFMT4_32_32_32_32_FLOAT = 4, 70 VFMT4_16_FLOAT = 5, 71 VFMT4_16_16_FLOAT = 6, 72 VFMT4_16_16_16_FLOAT = 7, 73 VFMT4_16_16_16_16_FLOAT = 8, 74 VFMT4_32_FIXED = 9, 75 VFMT4_32_32_FIXED = 10, 76 VFMT4_32_32_32_FIXED = 11, 77 VFMT4_32_32_32_32_FIXED = 12, 78 VFMT4_16_SINT = 16, 79 VFMT4_16_16_SINT = 17, 80 VFMT4_16_16_16_SINT = 18, 81 VFMT4_16_16_16_16_SINT = 19, 82 VFMT4_16_UINT = 20, 83 VFMT4_16_16_UINT = 21, 84 VFMT4_16_16_16_UINT = 22, 85 VFMT4_16_16_16_16_UINT = 23, 86 VFMT4_16_SNORM = 24, 87 VFMT4_16_16_SNORM = 25, 88 VFMT4_16_16_16_SNORM = 26, 89 VFMT4_16_16_16_16_SNORM = 27, 90 VFMT4_16_UNORM = 28, 91 VFMT4_16_16_UNORM = 29, 92 VFMT4_16_16_16_UNORM = 30, 93 VFMT4_16_16_16_16_UNORM = 31, 94 VFMT4_32_32_SINT = 37, 95 VFMT4_8_UINT = 40, 96 VFMT4_8_8_UINT = 41, 97 VFMT4_8_8_8_UINT = 42, 98 VFMT4_8_8_8_8_UINT = 43, 99 VFMT4_8_UNORM = 44, 100 VFMT4_8_8_UNORM = 45, 101 VFMT4_8_8_8_UNORM = 46, 102 VFMT4_8_8_8_8_UNORM = 47, 103 VFMT4_8_SINT = 48, 104 VFMT4_8_8_SINT = 49, 105 VFMT4_8_8_8_SINT = 50, 106 VFMT4_8_8_8_8_SINT = 51, 107 VFMT4_8_SNORM = 52, 108 VFMT4_8_8_SNORM = 53, 109 VFMT4_8_8_8_SNORM = 54, 110 VFMT4_8_8_8_8_SNORM = 55, 111 VFMT4_10_10_10_2_UINT = 60, 112 VFMT4_10_10_10_2_UNORM = 61, 113 VFMT4_10_10_10_2_SINT = 62, 114 VFMT4_10_10_10_2_SNORM = 63, 115 }; 116 117 enum a4xx_tex_fmt { 118 TFMT4_5_6_5_UNORM = 11, 119 TFMT4_5_5_5_1_UNORM = 10, 120 TFMT4_4_4_4_4_UNORM = 8, 121 TFMT4_X8Z24_UNORM = 71, 122 TFMT4_10_10_10_2_UNORM = 33, 123 TFMT4_A8_UNORM = 3, 124 TFMT4_L8_A8_UNORM = 13, 125 TFMT4_8_UNORM = 4, 126 TFMT4_8_8_UNORM = 14, 127 TFMT4_8_8_8_8_UNORM = 28, 128 TFMT4_16_FLOAT = 20, 129 TFMT4_16_16_FLOAT = 40, 130 TFMT4_16_16_16_16_FLOAT = 53, 131 TFMT4_32_FLOAT = 43, 132 TFMT4_32_32_FLOAT = 56, 133 TFMT4_32_32_32_32_FLOAT = 63, 134 }; 135 136 enum a4xx_tex_fetchsize { 137 TFETCH4_1_BYTE = 0, 138 TFETCH4_2_BYTE = 1, 139 TFETCH4_4_BYTE = 2, 140 TFETCH4_8_BYTE = 3, 141 TFETCH4_16_BYTE = 4, 142 }; 143 144 enum a4xx_depth_format { 145 DEPTH4_NONE = 0, 146 DEPTH4_16 = 1, 147 DEPTH4_24_8 = 2, 148 }; 149 150 enum a4xx_tex_filter { 151 A4XX_TEX_NEAREST = 0, 152 A4XX_TEX_LINEAR = 1, 153 }; 154 155 enum a4xx_tex_clamp { 156 A4XX_TEX_REPEAT = 0, 157 A4XX_TEX_CLAMP_TO_EDGE = 1, 158 A4XX_TEX_MIRROR_REPEAT = 2, 159 A4XX_TEX_CLAMP_NONE = 3, 160 }; 161 162 enum a4xx_tex_swiz { 163 A4XX_TEX_X = 0, 164 A4XX_TEX_Y = 1, 165 A4XX_TEX_Z = 2, 166 A4XX_TEX_W = 3, 167 A4XX_TEX_ZERO = 4, 168 A4XX_TEX_ONE = 5, 169 }; 170 171 enum a4xx_tex_type { 172 A4XX_TEX_1D = 0, 173 A4XX_TEX_2D = 1, 174 A4XX_TEX_CUBE = 2, 175 A4XX_TEX_3D = 3, 176 }; 177 178 #define A4XX_CGC_HLSQ_EARLY_CYC__MASK 0x00700000 179 #define A4XX_CGC_HLSQ_EARLY_CYC__SHIFT 20 180 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) 181 { 182 return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK; 183 } 184 #define A4XX_INT0_RBBM_GPU_IDLE 0x00000001 185 #define A4XX_INT0_RBBM_AHB_ERROR 0x00000002 186 #define A4XX_INT0_RBBM_REG_TIMEOUT 0x00000004 187 #define A4XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 188 #define A4XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 189 #define A4XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020 190 #define A4XX_INT0_VFD_ERROR 0x00000040 191 #define A4XX_INT0_CP_SW_INT 0x00000080 192 #define A4XX_INT0_CP_T0_PACKET_IN_IB 0x00000100 193 #define A4XX_INT0_CP_OPCODE_ERROR 0x00000200 194 #define A4XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400 195 #define A4XX_INT0_CP_HW_FAULT 0x00000800 196 #define A4XX_INT0_CP_DMA 0x00001000 197 #define A4XX_INT0_CP_IB2_INT 0x00002000 198 #define A4XX_INT0_CP_IB1_INT 0x00004000 199 #define A4XX_INT0_CP_RB_INT 0x00008000 200 #define A4XX_INT0_CP_REG_PROTECT_FAULT 0x00010000 201 #define A4XX_INT0_CP_RB_DONE_TS 0x00020000 202 #define A4XX_INT0_CP_VS_DONE_TS 0x00040000 203 #define A4XX_INT0_CP_PS_DONE_TS 0x00080000 204 #define A4XX_INT0_CACHE_FLUSH_TS 0x00100000 205 #define A4XX_INT0_CP_AHB_ERROR_HALT 0x00200000 206 #define A4XX_INT0_MISC_HANG_DETECT 0x01000000 207 #define A4XX_INT0_UCHE_OOB_ACCESS 0x02000000 208 #define REG_A4XX_RB_GMEM_BASE_ADDR 0x00000cc0 209 210 #define REG_A4XX_RB_PERFCTR_RB_SEL_0 0x00000cc7 211 212 #define REG_A4XX_RB_PERFCTR_RB_SEL_1 0x00000cc8 213 214 #define REG_A4XX_RB_PERFCTR_RB_SEL_2 0x00000cc9 215 216 #define REG_A4XX_RB_PERFCTR_RB_SEL_3 0x00000cca 217 218 #define REG_A4XX_RB_PERFCTR_RB_SEL_4 0x00000ccb 219 220 #define REG_A4XX_RB_PERFCTR_RB_SEL_5 0x00000ccc 221 222 #define REG_A4XX_RB_PERFCTR_RB_SEL_6 0x00000ccd 223 224 #define REG_A4XX_RB_PERFCTR_RB_SEL_7 0x00000cce 225 226 #define REG_A4XX_RB_PERFCTR_CCU_SEL_3 0x00000cd2 227 228 #define REG_A4XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0 229 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff 230 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0 231 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) 232 { 233 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK; 234 } 235 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x3fff0000 236 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 16 237 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) 238 { 239 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK; 240 } 241 242 #define REG_A4XX_RB_CLEAR_COLOR_DW0 0x000020cc 243 244 #define REG_A4XX_RB_CLEAR_COLOR_DW1 0x000020cd 245 246 #define REG_A4XX_RB_CLEAR_COLOR_DW2 0x000020ce 247 248 #define REG_A4XX_RB_CLEAR_COLOR_DW3 0x000020cf 249 250 #define REG_A4XX_RB_MODE_CONTROL 0x000020a0 251 #define A4XX_RB_MODE_CONTROL_WIDTH__MASK 0x0000003f 252 #define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT 0 253 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) 254 { 255 return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK; 256 } 257 #define A4XX_RB_MODE_CONTROL_HEIGHT__MASK 0x00003f00 258 #define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT 8 259 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) 260 { 261 return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK; 262 } 263 264 #define REG_A4XX_RB_RENDER_CONTROL 0x000020a1 265 #define A4XX_RB_RENDER_CONTROL_BINNING_PASS 0x00000001 266 #define A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00000020 267 268 #define REG_A4XX_RB_MSAA_CONTROL 0x000020a2 269 #define A4XX_RB_MSAA_CONTROL_DISABLE 0x00001000 270 #define A4XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000e000 271 #define A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 13 272 static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val) 273 { 274 return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK; 275 } 276 277 #define REG_A4XX_RB_RENDER_CONTROL2 0x000020a3 278 #define A4XX_RB_RENDER_CONTROL2_XCOORD 0x00000001 279 #define A4XX_RB_RENDER_CONTROL2_YCOORD 0x00000002 280 #define A4XX_RB_RENDER_CONTROL2_ZCOORD 0x00000004 281 #define A4XX_RB_RENDER_CONTROL2_WCOORD 0x00000008 282 #define A4XX_RB_RENDER_CONTROL2_FACENESS 0x00000020 283 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK 0x00000380 284 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT 7 285 static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val) 286 { 287 return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK; 288 } 289 #define A4XX_RB_RENDER_CONTROL2_VARYING 0x00001000 290 291 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; } 292 293 static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; } 294 #define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008 295 #define A4XX_RB_MRT_CONTROL_BLEND 0x00000010 296 #define A4XX_RB_MRT_CONTROL_BLEND2 0x00000020 297 #define A4XX_RB_MRT_CONTROL_FASTCLEAR 0x00000400 298 #define A4XX_RB_MRT_CONTROL_B11 0x00000800 299 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000 300 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24 301 static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 302 { 303 return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 304 } 305 306 static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; } 307 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f 308 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 309 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val) 310 { 311 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 312 } 313 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00000600 314 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 9 315 static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 316 { 317 return ((val) << A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK; 318 } 319 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00001800 320 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 11 321 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 322 { 323 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 324 } 325 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0x007fc000 326 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 14 327 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) 328 { 329 return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; 330 } 331 332 static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; } 333 334 static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; } 335 #define A4XX_RB_MRT_CONTROL3_STRIDE__MASK 0x0001fff8 336 #define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT 3 337 static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val) 338 { 339 return ((val) << A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT) & A4XX_RB_MRT_CONTROL3_STRIDE__MASK; 340 } 341 342 static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; } 343 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 344 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 345 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 346 { 347 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 348 } 349 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 350 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 351 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a4xx_rb_blend_opcode val) 352 { 353 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 354 } 355 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 356 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 357 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 358 { 359 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 360 } 361 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 362 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 363 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 364 { 365 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 366 } 367 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 368 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 369 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a4xx_rb_blend_opcode val) 370 { 371 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 372 } 373 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 374 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 375 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 376 { 377 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 378 } 379 380 #define REG_A4XX_RB_BLEND_RED 0x000020f3 381 #define A4XX_RB_BLEND_RED_UINT__MASK 0x00007fff 382 #define A4XX_RB_BLEND_RED_UINT__SHIFT 0 383 static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val) 384 { 385 return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK; 386 } 387 #define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 388 #define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16 389 static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val) 390 { 391 return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK; 392 } 393 394 #define REG_A4XX_RB_BLEND_GREEN 0x000020f4 395 #define A4XX_RB_BLEND_GREEN_UINT__MASK 0x00007fff 396 #define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0 397 static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val) 398 { 399 return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK; 400 } 401 #define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 402 #define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 403 static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val) 404 { 405 return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK; 406 } 407 408 #define REG_A4XX_RB_BLEND_BLUE 0x000020f5 409 #define A4XX_RB_BLEND_BLUE_UINT__MASK 0x00007fff 410 #define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0 411 static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val) 412 { 413 return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK; 414 } 415 #define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 416 #define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 417 static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val) 418 { 419 return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK; 420 } 421 422 #define REG_A4XX_RB_BLEND_ALPHA 0x000020f6 423 #define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x00007fff 424 #define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0 425 static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val) 426 { 427 return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK; 428 } 429 #define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 430 #define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 431 static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val) 432 { 433 return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK; 434 } 435 436 #define REG_A4XX_RB_ALPHA_CONTROL 0x000020f8 437 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff 438 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 439 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) 440 { 441 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; 442 } 443 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 444 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 445 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 446 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 447 { 448 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; 449 } 450 451 #define REG_A4XX_RB_FS_OUTPUT 0x000020f9 452 #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND 0x00000001 453 #define A4XX_RB_FS_OUTPUT_FAST_CLEAR 0x00000100 454 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000 455 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT 16 456 static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val) 457 { 458 return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK; 459 } 460 461 #define REG_A4XX_RB_RENDER_CONTROL3 0x000020fb 462 #define A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__MASK 0x0000001f 463 #define A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__SHIFT 0 464 static inline uint32_t A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE(uint32_t val) 465 { 466 return ((val) << A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__SHIFT) & A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__MASK; 467 } 468 469 #define REG_A4XX_RB_COPY_CONTROL 0x000020fc 470 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003 471 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0 472 static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) 473 { 474 return ((val) << A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK; 475 } 476 #define A4XX_RB_COPY_CONTROL_MODE__MASK 0x00000070 477 #define A4XX_RB_COPY_CONTROL_MODE__SHIFT 4 478 static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) 479 { 480 return ((val) << A4XX_RB_COPY_CONTROL_MODE__SHIFT) & A4XX_RB_COPY_CONTROL_MODE__MASK; 481 } 482 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00 483 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8 484 static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) 485 { 486 return ((val) << A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK; 487 } 488 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000 489 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14 490 static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) 491 { 492 return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK; 493 } 494 495 #define REG_A4XX_RB_COPY_DEST_BASE 0x000020fd 496 #define A4XX_RB_COPY_DEST_BASE_BASE__MASK 0xffffffe0 497 #define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT 5 498 static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val) 499 { 500 return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK; 501 } 502 503 #define REG_A4XX_RB_COPY_DEST_PITCH 0x000020fe 504 #define A4XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff 505 #define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0 506 static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) 507 { 508 return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK; 509 } 510 511 #define REG_A4XX_RB_COPY_DEST_INFO 0x000020ff 512 #define A4XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc 513 #define A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2 514 static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val) 515 { 516 return ((val) << A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A4XX_RB_COPY_DEST_INFO_FORMAT__MASK; 517 } 518 #define A4XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 519 #define A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 520 static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) 521 { 522 return ((val) << A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A4XX_RB_COPY_DEST_INFO_SWAP__MASK; 523 } 524 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 525 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 526 static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 527 { 528 return ((val) << A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 529 } 530 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000 531 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14 532 static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) 533 { 534 return ((val) << A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK; 535 } 536 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000 537 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18 538 static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) 539 { 540 return ((val) << A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK; 541 } 542 #define A4XX_RB_COPY_DEST_INFO_TILE__MASK 0x03000000 543 #define A4XX_RB_COPY_DEST_INFO_TILE__SHIFT 24 544 static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val) 545 { 546 return ((val) << A4XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A4XX_RB_COPY_DEST_INFO_TILE__MASK; 547 } 548 549 #define REG_A4XX_RB_FS_OUTPUT_REG 0x00002100 550 #define A4XX_RB_FS_OUTPUT_REG_COLOR_PIPE_ENABLE 0x00000001 551 #define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z 0x00000020 552 553 #define REG_A4XX_RB_DEPTH_CONTROL 0x00002101 554 #define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001 555 #define A4XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002 556 #define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004 557 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070 558 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4 559 static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) 560 { 561 return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK; 562 } 563 #define A4XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080 564 #define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000 565 #define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000 566 567 #define REG_A4XX_RB_DEPTH_CLEAR 0x00002102 568 569 #define REG_A4XX_RB_DEPTH_INFO 0x00002103 570 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003 571 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 572 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val) 573 { 574 return ((val) << A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 575 } 576 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 577 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 578 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 579 { 580 return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 581 } 582 583 #define REG_A4XX_RB_DEPTH_PITCH 0x00002104 584 #define A4XX_RB_DEPTH_PITCH__MASK 0xffffffff 585 #define A4XX_RB_DEPTH_PITCH__SHIFT 0 586 static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val) 587 { 588 return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK; 589 } 590 591 #define REG_A4XX_RB_DEPTH_PITCH2 0x00002105 592 #define A4XX_RB_DEPTH_PITCH2__MASK 0xffffffff 593 #define A4XX_RB_DEPTH_PITCH2__SHIFT 0 594 static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val) 595 { 596 return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK; 597 } 598 599 #define REG_A4XX_RB_STENCIL_CONTROL 0x00002106 600 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 601 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 602 #define A4XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 603 #define A4XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 604 #define A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 605 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 606 { 607 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC__MASK; 608 } 609 #define A4XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 610 #define A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 611 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 612 { 613 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL__MASK; 614 } 615 #define A4XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 616 #define A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 617 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 618 { 619 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS__MASK; 620 } 621 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 622 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 623 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 624 { 625 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 626 } 627 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 628 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 629 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 630 { 631 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 632 } 633 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 634 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 635 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 636 { 637 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 638 } 639 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 640 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 641 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 642 { 643 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 644 } 645 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 646 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 647 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 648 { 649 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 650 } 651 652 #define REG_A4XX_RB_STENCIL_CONTROL2 0x00002107 653 #define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER 0x00000001 654 655 #define REG_A4XX_RB_STENCILREFMASK 0x0000210b 656 #define A4XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 657 #define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 658 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 659 { 660 return ((val) << A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILREF__MASK; 661 } 662 #define A4XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 663 #define A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 664 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 665 { 666 return ((val) << A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILMASK__MASK; 667 } 668 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 669 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 670 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 671 { 672 return ((val) << A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 673 } 674 675 #define REG_A4XX_RB_STENCILREFMASK_BF 0x0000210c 676 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 677 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 678 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 679 { 680 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 681 } 682 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 683 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 684 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 685 { 686 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 687 } 688 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 689 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 690 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 691 { 692 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 693 } 694 695 #define REG_A4XX_RB_BIN_OFFSET 0x0000210d 696 #define A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 697 #define A4XX_RB_BIN_OFFSET_X__MASK 0x00007fff 698 #define A4XX_RB_BIN_OFFSET_X__SHIFT 0 699 static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val) 700 { 701 return ((val) << A4XX_RB_BIN_OFFSET_X__SHIFT) & A4XX_RB_BIN_OFFSET_X__MASK; 702 } 703 #define A4XX_RB_BIN_OFFSET_Y__MASK 0x7fff0000 704 #define A4XX_RB_BIN_OFFSET_Y__SHIFT 16 705 static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val) 706 { 707 return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK; 708 } 709 710 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; } 711 712 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; } 713 714 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; } 715 716 #define REG_A4XX_RBBM_HW_VERSION 0x00000000 717 718 #define REG_A4XX_RBBM_HW_CONFIGURATION 0x00000002 719 720 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; } 721 722 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; } 723 724 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; } 725 726 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; } 727 728 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; } 729 730 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; } 731 732 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; } 733 734 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; } 735 736 #define REG_A4XX_RBBM_CLOCK_CTL_UCHE 0x00000014 737 738 #define REG_A4XX_RBBM_CLOCK_CTL2_UCHE 0x00000015 739 740 #define REG_A4XX_RBBM_CLOCK_CTL3_UCHE 0x00000016 741 742 #define REG_A4XX_RBBM_CLOCK_CTL4_UCHE 0x00000017 743 744 #define REG_A4XX_RBBM_CLOCK_HYST_UCHE 0x00000018 745 746 #define REG_A4XX_RBBM_CLOCK_DELAY_UCHE 0x00000019 747 748 #define REG_A4XX_RBBM_CLOCK_MODE_GPC 0x0000001a 749 750 #define REG_A4XX_RBBM_CLOCK_DELAY_GPC 0x0000001b 751 752 #define REG_A4XX_RBBM_CLOCK_HYST_GPC 0x0000001c 753 754 #define REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM 0x0000001d 755 756 #define REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000001e 757 758 #define REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x0000001f 759 760 #define REG_A4XX_RBBM_CLOCK_CTL 0x00000020 761 762 #define REG_A4XX_RBBM_SP_HYST_CNT 0x00000021 763 764 #define REG_A4XX_RBBM_SW_RESET_CMD 0x00000022 765 766 #define REG_A4XX_RBBM_AHB_CTL0 0x00000023 767 768 #define REG_A4XX_RBBM_AHB_CTL1 0x00000024 769 770 #define REG_A4XX_RBBM_AHB_CMD 0x00000025 771 772 #define REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL 0x00000026 773 774 #define REG_A4XX_RBBM_RAM_ACC_63_32 0x00000028 775 776 #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x0000002b 777 778 #define REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL 0x0000002f 779 780 #define REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4 0x00000034 781 782 #define REG_A4XX_RBBM_INT_CLEAR_CMD 0x00000036 783 784 #define REG_A4XX_RBBM_INT_0_MASK 0x00000037 785 786 #define REG_A4XX_RBBM_RBBM_CTL 0x0000003e 787 788 #define REG_A4XX_RBBM_AHB_DEBUG_CTL 0x0000003f 789 790 #define REG_A4XX_RBBM_VBIF_DEBUG_CTL 0x00000041 791 792 #define REG_A4XX_RBBM_CLOCK_CTL2 0x00000042 793 794 #define REG_A4XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 795 796 #define REG_A4XX_RBBM_RESET_CYCLES 0x00000047 797 798 #define REG_A4XX_RBBM_EXT_TRACE_BUS_CTL 0x00000049 799 800 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A 0x0000004a 801 802 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B 0x0000004b 803 804 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C 0x0000004c 805 806 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D 0x0000004d 807 808 #define REG_A4XX_RBBM_PERFCTR_CP_0_LO 0x0000009c 809 810 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; } 811 812 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; } 813 814 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; } 815 816 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; } 817 818 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; } 819 820 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; } 821 822 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; } 823 824 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; } 825 826 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; } 827 828 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; } 829 830 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; } 831 832 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; } 833 834 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; } 835 836 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; } 837 838 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; } 839 840 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; } 841 842 #define REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM 0x00000080 843 844 #define REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM 0x00000081 845 846 #define REG_A4XX_RBBM_CLOCK_CTL_HLSQ 0x0000008a 847 848 #define REG_A4XX_RBBM_CLOCK_HYST_HLSQ 0x0000008b 849 850 #define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ 0x0000008c 851 852 #define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM 0x0000008d 853 854 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; } 855 856 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; } 857 858 #define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168 859 860 #define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170 861 862 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0 0x00000171 863 864 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1 0x00000172 865 866 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2 0x00000173 867 868 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000174 869 870 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000175 871 872 #define REG_A4XX_RBBM_GPU_BUSY_MASKED 0x0000017a 873 874 #define REG_A4XX_RBBM_INT_0_STATUS 0x0000017d 875 876 #define REG_A4XX_RBBM_CLOCK_STATUS 0x00000182 877 878 #define REG_A4XX_RBBM_AHB_STATUS 0x00000189 879 880 #define REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS 0x0000018c 881 882 #define REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS 0x0000018d 883 884 #define REG_A4XX_RBBM_AHB_ERROR_STATUS 0x0000018f 885 886 #define REG_A4XX_RBBM_STATUS 0x00000191 887 #define A4XX_RBBM_STATUS_HI_BUSY 0x00000001 888 #define A4XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 889 #define A4XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 890 #define A4XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000 891 #define A4XX_RBBM_STATUS_VBIF_BUSY 0x00008000 892 #define A4XX_RBBM_STATUS_TSE_BUSY 0x00010000 893 #define A4XX_RBBM_STATUS_RAS_BUSY 0x00020000 894 #define A4XX_RBBM_STATUS_RB_BUSY 0x00040000 895 #define A4XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 896 #define A4XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 897 #define A4XX_RBBM_STATUS_VFD_BUSY 0x00200000 898 #define A4XX_RBBM_STATUS_VPC_BUSY 0x00400000 899 #define A4XX_RBBM_STATUS_UCHE_BUSY 0x00800000 900 #define A4XX_RBBM_STATUS_SP_BUSY 0x01000000 901 #define A4XX_RBBM_STATUS_TPL1_BUSY 0x02000000 902 #define A4XX_RBBM_STATUS_MARB_BUSY 0x04000000 903 #define A4XX_RBBM_STATUS_VSC_BUSY 0x08000000 904 #define A4XX_RBBM_STATUS_ARB_BUSY 0x10000000 905 #define A4XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 906 #define A4XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000 907 #define A4XX_RBBM_STATUS_GPU_BUSY 0x80000000 908 909 #define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5 0x0000019f 910 911 #define REG_A4XX_CP_SCRATCH_UMASK 0x00000228 912 913 #define REG_A4XX_CP_SCRATCH_ADDR 0x00000229 914 915 #define REG_A4XX_CP_RB_BASE 0x00000200 916 917 #define REG_A4XX_CP_RB_CNTL 0x00000201 918 919 #define REG_A4XX_CP_RB_WPTR 0x00000205 920 921 #define REG_A4XX_CP_RB_RPTR_ADDR 0x00000203 922 923 #define REG_A4XX_CP_RB_RPTR 0x00000204 924 925 #define REG_A4XX_CP_IB1_BASE 0x00000206 926 927 #define REG_A4XX_CP_IB1_BUFSZ 0x00000207 928 929 #define REG_A4XX_CP_IB2_BASE 0x00000208 930 931 #define REG_A4XX_CP_IB2_BUFSZ 0x00000209 932 933 #define REG_A4XX_CP_ME_RB_DONE_DATA 0x00000217 934 935 #define REG_A4XX_CP_QUEUE_THRESH2 0x00000219 936 937 #define REG_A4XX_CP_MERCIU_SIZE 0x0000021b 938 939 #define REG_A4XX_CP_ROQ_ADDR 0x0000021c 940 941 #define REG_A4XX_CP_ROQ_DATA 0x0000021d 942 943 #define REG_A4XX_CP_MEQ_ADDR 0x0000021e 944 945 #define REG_A4XX_CP_MEQ_DATA 0x0000021f 946 947 #define REG_A4XX_CP_MERCIU_ADDR 0x00000220 948 949 #define REG_A4XX_CP_MERCIU_DATA 0x00000221 950 951 #define REG_A4XX_CP_MERCIU_DATA2 0x00000222 952 953 #define REG_A4XX_CP_PFP_UCODE_ADDR 0x00000223 954 955 #define REG_A4XX_CP_PFP_UCODE_DATA 0x00000224 956 957 #define REG_A4XX_CP_ME_RAM_WADDR 0x00000225 958 959 #define REG_A4XX_CP_ME_RAM_RADDR 0x00000226 960 961 #define REG_A4XX_CP_ME_RAM_DATA 0x00000227 962 963 #define REG_A4XX_CP_PREEMPT 0x0000022a 964 965 #define REG_A4XX_CP_CNTL 0x0000022c 966 967 #define REG_A4XX_CP_ME_CNTL 0x0000022d 968 969 #define REG_A4XX_CP_DEBUG 0x0000022e 970 971 #define REG_A4XX_CP_DEBUG_ECO_CONTROL 0x00000231 972 973 #define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232 974 975 #define REG_A4XX_CP_PROTECT_REG_0 0x00000240 976 977 static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; } 978 979 static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; } 980 981 #define REG_A4XX_CP_PROTECT_CTRL 0x00000250 982 983 #define REG_A4XX_CP_ST_BASE 0x000004c0 984 985 #define REG_A4XX_CP_STQ_AVAIL 0x000004ce 986 987 #define REG_A4XX_CP_MERCIU_STAT 0x000004d0 988 989 #define REG_A4XX_CP_WFI_PEND_CTR 0x000004d2 990 991 #define REG_A4XX_CP_HW_FAULT 0x000004d8 992 993 #define REG_A4XX_CP_PROTECT_STATUS 0x000004da 994 995 #define REG_A4XX_CP_EVENTS_IN_FLIGHT 0x000004dd 996 997 #define REG_A4XX_CP_PERFCTR_CP_SEL_0 0x00000500 998 999 #define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b 1000 1001 static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; } 1002 1003 static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; } 1004 1005 #define REG_A4XX_SP_VS_STATUS 0x00000ec0 1006 1007 #define REG_A4XX_SP_PERFCTR_SP_SEL_11 0x00000ecf 1008 1009 #define REG_A4XX_SP_SP_CTRL_REG 0x000022c0 1010 #define A4XX_SP_SP_CTRL_REG_BINNING_PASS 0x00080000 1011 1012 #define REG_A4XX_SP_INSTR_CACHE_CTRL 0x000022c1 1013 1014 #define REG_A4XX_SP_VS_CTRL_REG0 0x000022c4 1015 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 1016 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 1017 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 1018 { 1019 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK; 1020 } 1021 #define A4XX_SP_VS_CTRL_REG0_VARYING 0x00000002 1022 #define A4XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004 1023 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 1024 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 1025 static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 1026 { 1027 return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 1028 } 1029 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 1030 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 1031 static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 1032 { 1033 return ((val) << A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 1034 } 1035 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 1036 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 1037 static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 1038 { 1039 return ((val) << A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK; 1040 } 1041 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000 1042 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20 1043 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 1044 { 1045 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; 1046 } 1047 #define A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000 1048 #define A4XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000 1049 1050 #define REG_A4XX_SP_VS_CTRL_REG1 0x000022c5 1051 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff 1052 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0 1053 static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) 1054 { 1055 return ((val) << A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK; 1056 } 1057 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000 1058 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24 1059 static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) 1060 { 1061 return ((val) << A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK; 1062 } 1063 1064 #define REG_A4XX_SP_VS_PARAM_REG 0x000022c6 1065 #define A4XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff 1066 #define A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0 1067 static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) 1068 { 1069 return ((val) << A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_POSREGID__MASK; 1070 } 1071 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00 1072 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8 1073 static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) 1074 { 1075 return ((val) << A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK; 1076 } 1077 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000 1078 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20 1079 static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) 1080 { 1081 return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; 1082 } 1083 1084 static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 1085 1086 static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 1087 #define A4XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff 1088 #define A4XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 1089 static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 1090 { 1091 return ((val) << A4XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_A_REGID__MASK; 1092 } 1093 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00 1094 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9 1095 static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 1096 { 1097 return ((val) << A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 1098 } 1099 #define A4XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000 1100 #define A4XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 1101 static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 1102 { 1103 return ((val) << A4XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_B_REGID__MASK; 1104 } 1105 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000 1106 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25 1107 static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 1108 { 1109 return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 1110 } 1111 1112 static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; } 1113 1114 static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; } 1115 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 1116 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 1117 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 1118 { 1119 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 1120 } 1121 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 1122 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 1123 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 1124 { 1125 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 1126 } 1127 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 1128 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 1129 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 1130 { 1131 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 1132 } 1133 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 1134 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 1135 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 1136 { 1137 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 1138 } 1139 1140 #define REG_A4XX_SP_VS_OBJ_OFFSET_REG 0x000022e0 1141 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1142 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1143 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1144 { 1145 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1146 } 1147 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1148 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1149 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1150 { 1151 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1152 } 1153 1154 #define REG_A4XX_SP_VS_OBJ_START 0x000022e1 1155 1156 #define REG_A4XX_SP_VS_PVT_MEM_PARAM 0x000022e2 1157 1158 #define REG_A4XX_SP_VS_PVT_MEM_ADDR 0x000022e3 1159 1160 #define REG_A4XX_SP_VS_LENGTH_REG 0x000022e5 1161 1162 #define REG_A4XX_SP_FS_CTRL_REG0 0x000022e8 1163 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 1164 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 1165 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 1166 { 1167 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK; 1168 } 1169 #define A4XX_SP_FS_CTRL_REG0_VARYING 0x00000002 1170 #define A4XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004 1171 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 1172 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 1173 static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 1174 { 1175 return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 1176 } 1177 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 1178 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 1179 static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 1180 { 1181 return ((val) << A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 1182 } 1183 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 1184 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 1185 static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 1186 { 1187 return ((val) << A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK; 1188 } 1189 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 1190 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 1191 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 1192 { 1193 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 1194 } 1195 #define A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000 1196 #define A4XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000 1197 1198 #define REG_A4XX_SP_FS_CTRL_REG1 0x000022e9 1199 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff 1200 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0 1201 static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) 1202 { 1203 return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK; 1204 } 1205 #define A4XX_SP_FS_CTRL_REG1_FACENESS 0x00080000 1206 #define A4XX_SP_FS_CTRL_REG1_VARYING 0x00100000 1207 #define A4XX_SP_FS_CTRL_REG1_FRAGCOORD 0x00200000 1208 1209 #define REG_A4XX_SP_FS_OBJ_OFFSET_REG 0x000022ea 1210 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1211 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1212 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1213 { 1214 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1215 } 1216 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1217 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1218 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1219 { 1220 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1221 } 1222 1223 #define REG_A4XX_SP_FS_OBJ_START 0x000022eb 1224 1225 #define REG_A4XX_SP_FS_PVT_MEM_PARAM 0x000022ec 1226 1227 #define REG_A4XX_SP_FS_PVT_MEM_ADDR 0x000022ed 1228 1229 #define REG_A4XX_SP_FS_LENGTH_REG 0x000022ef 1230 1231 #define REG_A4XX_SP_FS_OUTPUT_REG 0x000022f0 1232 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080 1233 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00 1234 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8 1235 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) 1236 { 1237 return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK; 1238 } 1239 1240 static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; } 1241 1242 static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; } 1243 #define A4XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff 1244 #define A4XX_SP_FS_MRT_REG_REGID__SHIFT 0 1245 static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val) 1246 { 1247 return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK; 1248 } 1249 #define A4XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100 1250 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK 0x0003f000 1251 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT 12 1252 static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val) 1253 { 1254 return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK; 1255 } 1256 1257 #define REG_A4XX_SP_HS_OBJ_OFFSET_REG 0x0000230d 1258 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1259 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1260 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1261 { 1262 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1263 } 1264 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1265 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1266 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1267 { 1268 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1269 } 1270 1271 #define REG_A4XX_SP_DS_OBJ_OFFSET_REG 0x00002334 1272 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1273 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1274 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1275 { 1276 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1277 } 1278 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1279 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1280 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1281 { 1282 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1283 } 1284 1285 #define REG_A4XX_SP_GS_OBJ_OFFSET_REG 0x0000235b 1286 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1287 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1288 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1289 { 1290 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1291 } 1292 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1293 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1294 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1295 { 1296 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1297 } 1298 1299 #define REG_A4XX_SP_GS_LENGTH_REG 0x00002360 1300 1301 #define REG_A4XX_VPC_DEBUG_RAM_SEL 0x00000e60 1302 1303 #define REG_A4XX_VPC_DEBUG_RAM_READ 0x00000e61 1304 1305 #define REG_A4XX_VPC_DEBUG_ECO_CONTROL 0x00000e64 1306 1307 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_3 0x00000e68 1308 1309 #define REG_A4XX_VPC_ATTR 0x00002140 1310 #define A4XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff 1311 #define A4XX_VPC_ATTR_TOTALATTR__SHIFT 0 1312 static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val) 1313 { 1314 return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK; 1315 } 1316 #define A4XX_VPC_ATTR_PSIZE 0x00000200 1317 #define A4XX_VPC_ATTR_THRDASSIGN__MASK 0x00003000 1318 #define A4XX_VPC_ATTR_THRDASSIGN__SHIFT 12 1319 static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val) 1320 { 1321 return ((val) << A4XX_VPC_ATTR_THRDASSIGN__SHIFT) & A4XX_VPC_ATTR_THRDASSIGN__MASK; 1322 } 1323 #define A4XX_VPC_ATTR_ENABLE 0x02000000 1324 1325 #define REG_A4XX_VPC_PACK 0x00002141 1326 #define A4XX_VPC_PACK_NUMBYPASSVAR__MASK 0x000000ff 1327 #define A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT 0 1328 static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val) 1329 { 1330 return ((val) << A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT) & A4XX_VPC_PACK_NUMBYPASSVAR__MASK; 1331 } 1332 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00 1333 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8 1334 static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) 1335 { 1336 return ((val) << A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK; 1337 } 1338 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000 1339 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16 1340 static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) 1341 { 1342 return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK; 1343 } 1344 1345 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; } 1346 1347 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; } 1348 1349 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; } 1350 1351 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; } 1352 1353 #define REG_A4XX_VPC_SO_FLUSH_WADDR_3 0x0000216e 1354 1355 #define REG_A4XX_VSC_BIN_SIZE 0x00000c00 1356 #define A4XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 1357 #define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 1358 static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 1359 { 1360 return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK; 1361 } 1362 #define A4XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 1363 #define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5 1364 static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 1365 { 1366 return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK; 1367 } 1368 1369 #define REG_A4XX_VSC_SIZE_ADDRESS 0x00000c01 1370 1371 #define REG_A4XX_VSC_SIZE_ADDRESS2 0x00000c02 1372 1373 #define REG_A4XX_VSC_DEBUG_ECO_CONTROL 0x00000c03 1374 1375 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } 1376 1377 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } 1378 #define A4XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff 1379 #define A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0 1380 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) 1381 { 1382 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_X__MASK; 1383 } 1384 #define A4XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00 1385 #define A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10 1386 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) 1387 { 1388 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_Y__MASK; 1389 } 1390 #define A4XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000 1391 #define A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20 1392 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) 1393 { 1394 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_W__MASK; 1395 } 1396 #define A4XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000 1397 #define A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24 1398 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) 1399 { 1400 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK; 1401 } 1402 1403 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 1404 1405 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 1406 1407 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; } 1408 1409 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; } 1410 1411 #define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1 0x00000c41 1412 1413 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_0 0x00000c50 1414 1415 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_1 0x00000c51 1416 1417 #define REG_A4XX_VFD_DEBUG_CONTROL 0x00000e40 1418 1419 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 0x00000e4a 1420 1421 #define REG_A4XX_VFD_CONTROL_0 0x00002200 1422 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x000000ff 1423 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0 1424 static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) 1425 { 1426 return ((val) << A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK; 1427 } 1428 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK 0x0001fe00 1429 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT 9 1430 static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val) 1431 { 1432 return ((val) << A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT) & A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK; 1433 } 1434 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x03f00000 1435 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 20 1436 static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) 1437 { 1438 return ((val) << A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK; 1439 } 1440 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xfc000000 1441 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 26 1442 static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) 1443 { 1444 return ((val) << A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK; 1445 } 1446 1447 #define REG_A4XX_VFD_CONTROL_1 0x00002201 1448 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff 1449 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0 1450 static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) 1451 { 1452 return ((val) << A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK; 1453 } 1454 #define A4XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000 1455 #define A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16 1456 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 1457 { 1458 return ((val) << A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A4XX_VFD_CONTROL_1_REGID4VTX__MASK; 1459 } 1460 #define A4XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000 1461 #define A4XX_VFD_CONTROL_1_REGID4INST__SHIFT 24 1462 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 1463 { 1464 return ((val) << A4XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A4XX_VFD_CONTROL_1_REGID4INST__MASK; 1465 } 1466 1467 #define REG_A4XX_VFD_CONTROL_2 0x00002202 1468 1469 #define REG_A4XX_VFD_CONTROL_3 0x00002203 1470 #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK 0x0000ff00 1471 #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT 8 1472 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val) 1473 { 1474 return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK; 1475 } 1476 1477 #define REG_A4XX_VFD_CONTROL_4 0x00002204 1478 1479 #define REG_A4XX_VFD_INDEX_OFFSET 0x00002208 1480 1481 static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; } 1482 1483 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; } 1484 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f 1485 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0 1486 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) 1487 { 1488 return ((val) << A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK; 1489 } 1490 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80 1491 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7 1492 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) 1493 { 1494 return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK; 1495 } 1496 #define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00080000 1497 #define A4XX_VFD_FETCH_INSTR_0_INSTANCED 0x00100000 1498 1499 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; } 1500 1501 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; } 1502 #define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xfffffff0 1503 #define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 4 1504 static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val) 1505 { 1506 return ((val >> 4) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK; 1507 } 1508 1509 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; } 1510 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK 0x000001ff 1511 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT 0 1512 static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val) 1513 { 1514 return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK; 1515 } 1516 1517 static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; } 1518 1519 static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; } 1520 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f 1521 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0 1522 static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) 1523 { 1524 return ((val) << A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK; 1525 } 1526 #define A4XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010 1527 #define A4XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0 1528 #define A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6 1529 static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val) 1530 { 1531 return ((val) << A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A4XX_VFD_DECODE_INSTR_FORMAT__MASK; 1532 } 1533 #define A4XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000 1534 #define A4XX_VFD_DECODE_INSTR_REGID__SHIFT 12 1535 static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val) 1536 { 1537 return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK; 1538 } 1539 #define A4XX_VFD_DECODE_INSTR_INT 0x00100000 1540 #define A4XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000 1541 #define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT 22 1542 static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 1543 { 1544 return ((val) << A4XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A4XX_VFD_DECODE_INSTR_SWAP__MASK; 1545 } 1546 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000 1547 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24 1548 static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) 1549 { 1550 return ((val) << A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK; 1551 } 1552 #define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000 1553 #define A4XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000 1554 1555 #define REG_A4XX_TPL1_DEBUG_ECO_CONTROL 0x00000f00 1556 1557 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 0x00000f0b 1558 1559 #define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380 1560 1561 #define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR 0x000023a6 1562 1563 #define REG_A4XX_GRAS_TSE_STATUS 0x00000c80 1564 1565 #define REG_A4XX_GRAS_DEBUG_ECO_CONTROL 0x00000c81 1566 1567 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c88 1568 1569 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c8b 1570 1571 #define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000 1572 1573 #define REG_A4XX_GRAS_CLEAR_CNTL 0x00002003 1574 #define A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR 0x00000001 1575 1576 #define REG_A4XX_GRAS_CL_GB_CLIP_ADJ 0x00002004 1577 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff 1578 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0 1579 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) 1580 { 1581 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; 1582 } 1583 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00 1584 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10 1585 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) 1586 { 1587 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; 1588 } 1589 1590 #define REG_A4XX_GRAS_CL_VPORT_XOFFSET_0 0x00002008 1591 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff 1592 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0 1593 static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val) 1594 { 1595 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK; 1596 } 1597 1598 #define REG_A4XX_GRAS_CL_VPORT_XSCALE_0 0x00002009 1599 #define A4XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff 1600 #define A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0 1601 static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val) 1602 { 1603 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_XSCALE_0__MASK; 1604 } 1605 1606 #define REG_A4XX_GRAS_CL_VPORT_YOFFSET_0 0x0000200a 1607 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff 1608 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0 1609 static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val) 1610 { 1611 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK; 1612 } 1613 1614 #define REG_A4XX_GRAS_CL_VPORT_YSCALE_0 0x0000200b 1615 #define A4XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff 1616 #define A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0 1617 static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val) 1618 { 1619 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_YSCALE_0__MASK; 1620 } 1621 1622 #define REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000200c 1623 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff 1624 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0 1625 static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val) 1626 { 1627 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK; 1628 } 1629 1630 #define REG_A4XX_GRAS_CL_VPORT_ZSCALE_0 0x0000200d 1631 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff 1632 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0 1633 static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val) 1634 { 1635 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK; 1636 } 1637 1638 #define REG_A4XX_GRAS_SU_POINT_MINMAX 0x00002070 1639 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 1640 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 1641 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val) 1642 { 1643 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 1644 } 1645 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 1646 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 1647 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val) 1648 { 1649 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 1650 } 1651 1652 #define REG_A4XX_GRAS_SU_POINT_SIZE 0x00002071 1653 #define A4XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff 1654 #define A4XX_GRAS_SU_POINT_SIZE__SHIFT 0 1655 static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val) 1656 { 1657 return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK; 1658 } 1659 1660 #define REG_A4XX_GRAS_ALPHA_CONTROL 0x00002073 1661 #define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE 0x00000004 1662 1663 #define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE 0x00002074 1664 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff 1665 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 1666 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val) 1667 { 1668 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; 1669 } 1670 1671 #define REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00002075 1672 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 1673 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 1674 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 1675 { 1676 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 1677 } 1678 1679 #define REG_A4XX_GRAS_DEPTH_CONTROL 0x00002077 1680 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK 0x00000003 1681 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT 0 1682 static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val) 1683 { 1684 return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK; 1685 } 1686 1687 #define REG_A4XX_GRAS_SU_MODE_CONTROL 0x00002078 1688 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001 1689 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002 1690 #define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004 1691 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8 1692 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3 1693 static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) 1694 { 1695 return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; 1696 } 1697 #define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800 1698 #define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS 0x00100000 1699 1700 #define REG_A4XX_GRAS_SC_CONTROL 0x0000207b 1701 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x0000000c 1702 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 2 1703 static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) 1704 { 1705 return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK; 1706 } 1707 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000380 1708 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 7 1709 static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val) 1710 { 1711 return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK; 1712 } 1713 #define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE 0x00000800 1714 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000 1715 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12 1716 static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) 1717 { 1718 return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK; 1719 } 1720 1721 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL 0x0000207c 1722 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 1723 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 1724 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 1725 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 1726 { 1727 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; 1728 } 1729 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 1730 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 1731 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 1732 { 1733 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; 1734 } 1735 1736 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR 0x0000207d 1737 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 1738 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 1739 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 1740 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 1741 { 1742 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; 1743 } 1744 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 1745 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 1746 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 1747 { 1748 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; 1749 } 1750 1751 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000209c 1752 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 1753 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 1754 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 1755 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 1756 { 1757 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 1758 } 1759 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 1760 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 1761 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 1762 { 1763 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 1764 } 1765 1766 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000209d 1767 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 1768 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 1769 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 1770 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 1771 { 1772 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 1773 } 1774 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 1775 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 1776 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 1777 { 1778 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 1779 } 1780 1781 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR 0x0000209e 1782 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE 0x80000000 1783 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK 0x00007fff 1784 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT 0 1785 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val) 1786 { 1787 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK; 1788 } 1789 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK 0x7fff0000 1790 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT 16 1791 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val) 1792 { 1793 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK; 1794 } 1795 1796 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL 0x0000209f 1797 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE 0x80000000 1798 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK 0x00007fff 1799 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT 0 1800 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val) 1801 { 1802 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK; 1803 } 1804 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK 0x7fff0000 1805 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT 16 1806 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val) 1807 { 1808 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK; 1809 } 1810 1811 #define REG_A4XX_UCHE_CACHE_MODE_CONTROL 0x00000e80 1812 1813 #define REG_A4XX_UCHE_TRAP_BASE_LO 0x00000e83 1814 1815 #define REG_A4XX_UCHE_TRAP_BASE_HI 0x00000e84 1816 1817 #define REG_A4XX_UCHE_CACHE_STATUS 0x00000e88 1818 1819 #define REG_A4XX_UCHE_INVALIDATE0 0x00000e8a 1820 1821 #define REG_A4XX_UCHE_INVALIDATE1 0x00000e8b 1822 1823 #define REG_A4XX_UCHE_CACHE_WAYS_VFD 0x00000e8c 1824 1825 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e95 1826 1827 #define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD 0x00000e00 1828 1829 #define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL 0x00000e04 1830 1831 #define REG_A4XX_HLSQ_PERF_PIPE_MASK 0x00000e0e 1832 1833 #define REG_A4XX_HLSQ_CONTROL_0_REG 0x000023c0 1834 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010 1835 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4 1836 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) 1837 { 1838 return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; 1839 } 1840 #define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040 1841 #define A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200 1842 #define A4XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400 1843 #define A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000 1844 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000 1845 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27 1846 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) 1847 { 1848 return ((val) << A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK; 1849 } 1850 #define A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000 1851 #define A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000 1852 #define A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000 1853 #define A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000 1854 1855 #define REG_A4XX_HLSQ_CONTROL_1_REG 0x000023c1 1856 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040 1857 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6 1858 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) 1859 { 1860 return ((val) << A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK; 1861 } 1862 #define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100 1863 #define A4XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200 1864 #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK 0x00ff0000 1865 #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT 16 1866 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val) 1867 { 1868 return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK; 1869 } 1870 #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORD 0x02000000 1871 1872 #define REG_A4XX_HLSQ_CONTROL_2_REG 0x000023c2 1873 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000 1874 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26 1875 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) 1876 { 1877 return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK; 1878 } 1879 #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000003fc 1880 #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 2 1881 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) 1882 { 1883 return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; 1884 } 1885 1886 #define REG_A4XX_HLSQ_CONTROL_3_REG 0x000023c3 1887 #define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff 1888 #define A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0 1889 static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val) 1890 { 1891 return ((val) << A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_REGID__MASK; 1892 } 1893 1894 #define REG_A4XX_HLSQ_VS_CONTROL_REG 0x000023c5 1895 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 1896 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0 1897 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) 1898 { 1899 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK; 1900 } 1901 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 1902 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 1903 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 1904 { 1905 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 1906 } 1907 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 1908 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 1909 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 1910 { 1911 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK; 1912 } 1913 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 1914 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24 1915 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) 1916 { 1917 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK; 1918 } 1919 1920 #define REG_A4XX_HLSQ_FS_CONTROL_REG 0x000023c6 1921 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 1922 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0 1923 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) 1924 { 1925 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK; 1926 } 1927 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 1928 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 1929 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 1930 { 1931 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 1932 } 1933 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 1934 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 1935 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 1936 { 1937 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK; 1938 } 1939 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 1940 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24 1941 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) 1942 { 1943 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK; 1944 } 1945 1946 #define REG_A4XX_HLSQ_HS_CONTROL_REG 0x000023c7 1947 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 1948 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT 0 1949 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val) 1950 { 1951 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK; 1952 } 1953 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 1954 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 1955 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 1956 { 1957 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 1958 } 1959 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 1960 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 1961 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 1962 { 1963 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK; 1964 } 1965 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 1966 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT 24 1967 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val) 1968 { 1969 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK; 1970 } 1971 1972 #define REG_A4XX_HLSQ_DS_CONTROL_REG 0x000023c8 1973 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 1974 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT 0 1975 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val) 1976 { 1977 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK; 1978 } 1979 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 1980 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 1981 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 1982 { 1983 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 1984 } 1985 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 1986 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 1987 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 1988 { 1989 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK; 1990 } 1991 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 1992 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT 24 1993 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val) 1994 { 1995 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK; 1996 } 1997 1998 #define REG_A4XX_HLSQ_GS_CONTROL_REG 0x000023c9 1999 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 2000 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT 0 2001 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val) 2002 { 2003 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK; 2004 } 2005 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 2006 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 2007 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 2008 { 2009 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 2010 } 2011 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 2012 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 2013 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 2014 { 2015 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK; 2016 } 2017 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 2018 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT 24 2019 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val) 2020 { 2021 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK; 2022 } 2023 2024 #define REG_A4XX_HLSQ_UPDATE_CONTROL 0x000023db 2025 2026 #define REG_A4XX_PC_BINNING_COMMAND 0x00000d00 2027 #define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001 2028 2029 #define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c 2030 2031 #define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10 2032 2033 #define REG_A4XX_PC_PERFCTR_PC_SEL_7 0x00000d17 2034 2035 #define REG_A4XX_PC_BIN_BASE 0x000021c0 2036 2037 #define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4 2038 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT 0x00000001 2039 #define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000 2040 #define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000 2041 2042 #define REG_A4XX_UNKNOWN_21C5 0x000021c5 2043 2044 #define REG_A4XX_PC_RESTART_INDEX 0x000021c6 2045 2046 #define REG_A4XX_PC_GS_PARAM 0x000021e5 2047 2048 #define REG_A4XX_PC_HS_PARAM 0x000021e7 2049 2050 #define REG_A4XX_VBIF_VERSION 0x00003000 2051 2052 #define REG_A4XX_VBIF_CLKON 0x00003001 2053 #define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000001 2054 2055 #define REG_A4XX_VBIF_ABIT_SORT 0x0000301c 2056 2057 #define REG_A4XX_VBIF_ABIT_SORT_CONF 0x0000301d 2058 2059 #define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 2060 2061 #define REG_A4XX_VBIF_IN_RD_LIM_CONF0 0x0000302c 2062 2063 #define REG_A4XX_VBIF_IN_RD_LIM_CONF1 0x0000302d 2064 2065 #define REG_A4XX_VBIF_IN_WR_LIM_CONF0 0x00003030 2066 2067 #define REG_A4XX_VBIF_IN_WR_LIM_CONF1 0x00003031 2068 2069 #define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049 2070 2071 #define REG_A4XX_UNKNOWN_0CC5 0x00000cc5 2072 2073 #define REG_A4XX_UNKNOWN_0CC6 0x00000cc6 2074 2075 #define REG_A4XX_UNKNOWN_0D01 0x00000d01 2076 2077 #define REG_A4XX_UNKNOWN_0E05 0x00000e05 2078 2079 #define REG_A4XX_UNKNOWN_0E42 0x00000e42 2080 2081 #define REG_A4XX_UNKNOWN_0EC2 0x00000ec2 2082 2083 #define REG_A4XX_UNKNOWN_0EC3 0x00000ec3 2084 2085 #define REG_A4XX_UNKNOWN_0F03 0x00000f03 2086 2087 #define REG_A4XX_UNKNOWN_2001 0x00002001 2088 2089 #define REG_A4XX_UNKNOWN_209B 0x0000209b 2090 2091 #define REG_A4XX_UNKNOWN_20EF 0x000020ef 2092 2093 #define REG_A4XX_UNKNOWN_20F0 0x000020f0 2094 2095 #define REG_A4XX_UNKNOWN_20F1 0x000020f1 2096 2097 #define REG_A4XX_UNKNOWN_20F2 0x000020f2 2098 2099 #define REG_A4XX_UNKNOWN_20F7 0x000020f7 2100 #define A4XX_UNKNOWN_20F7__MASK 0xffffffff 2101 #define A4XX_UNKNOWN_20F7__SHIFT 0 2102 static inline uint32_t A4XX_UNKNOWN_20F7(float val) 2103 { 2104 return ((fui(val)) << A4XX_UNKNOWN_20F7__SHIFT) & A4XX_UNKNOWN_20F7__MASK; 2105 } 2106 2107 #define REG_A4XX_UNKNOWN_2152 0x00002152 2108 2109 #define REG_A4XX_UNKNOWN_2153 0x00002153 2110 2111 #define REG_A4XX_UNKNOWN_2154 0x00002154 2112 2113 #define REG_A4XX_UNKNOWN_2155 0x00002155 2114 2115 #define REG_A4XX_UNKNOWN_2156 0x00002156 2116 2117 #define REG_A4XX_UNKNOWN_2157 0x00002157 2118 2119 #define REG_A4XX_UNKNOWN_21C3 0x000021c3 2120 2121 #define REG_A4XX_UNKNOWN_21E6 0x000021e6 2122 2123 #define REG_A4XX_UNKNOWN_2209 0x00002209 2124 2125 #define REG_A4XX_UNKNOWN_22D7 0x000022d7 2126 2127 #define REG_A4XX_UNKNOWN_2381 0x00002381 2128 2129 #define REG_A4XX_UNKNOWN_23A0 0x000023a0 2130 2131 #define REG_A4XX_TEX_SAMP_0 0x00000000 2132 #define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 2133 #define A4XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 2134 #define A4XX_TEX_SAMP_0_XY_MAG__SHIFT 1 2135 static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val) 2136 { 2137 return ((val) << A4XX_TEX_SAMP_0_XY_MAG__SHIFT) & A4XX_TEX_SAMP_0_XY_MAG__MASK; 2138 } 2139 #define A4XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 2140 #define A4XX_TEX_SAMP_0_XY_MIN__SHIFT 3 2141 static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val) 2142 { 2143 return ((val) << A4XX_TEX_SAMP_0_XY_MIN__SHIFT) & A4XX_TEX_SAMP_0_XY_MIN__MASK; 2144 } 2145 #define A4XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 2146 #define A4XX_TEX_SAMP_0_WRAP_S__SHIFT 5 2147 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val) 2148 { 2149 return ((val) << A4XX_TEX_SAMP_0_WRAP_S__SHIFT) & A4XX_TEX_SAMP_0_WRAP_S__MASK; 2150 } 2151 #define A4XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 2152 #define A4XX_TEX_SAMP_0_WRAP_T__SHIFT 8 2153 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val) 2154 { 2155 return ((val) << A4XX_TEX_SAMP_0_WRAP_T__SHIFT) & A4XX_TEX_SAMP_0_WRAP_T__MASK; 2156 } 2157 #define A4XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 2158 #define A4XX_TEX_SAMP_0_WRAP_R__SHIFT 11 2159 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val) 2160 { 2161 return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK; 2162 } 2163 2164 #define REG_A4XX_TEX_SAMP_1 0x00000001 2165 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e 2166 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 2167 static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) 2168 { 2169 return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK; 2170 } 2171 #define A4XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 2172 #define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 2173 #define A4XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 2174 #define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 2175 static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val) 2176 { 2177 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK; 2178 } 2179 #define A4XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 2180 #define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 2181 static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val) 2182 { 2183 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK; 2184 } 2185 2186 #define REG_A4XX_TEX_CONST_0 0x00000000 2187 #define A4XX_TEX_CONST_0_TILED 0x00000001 2188 #define A4XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 2189 #define A4XX_TEX_CONST_0_SWIZ_X__SHIFT 4 2190 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val) 2191 { 2192 return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) & A4XX_TEX_CONST_0_SWIZ_X__MASK; 2193 } 2194 #define A4XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 2195 #define A4XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 2196 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val) 2197 { 2198 return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Y__MASK; 2199 } 2200 #define A4XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 2201 #define A4XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 2202 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val) 2203 { 2204 return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Z__MASK; 2205 } 2206 #define A4XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 2207 #define A4XX_TEX_CONST_0_SWIZ_W__SHIFT 13 2208 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val) 2209 { 2210 return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK; 2211 } 2212 #define A4XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 2213 #define A4XX_TEX_CONST_0_MIPLVLS__SHIFT 16 2214 static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val) 2215 { 2216 return ((val) << A4XX_TEX_CONST_0_MIPLVLS__SHIFT) & A4XX_TEX_CONST_0_MIPLVLS__MASK; 2217 } 2218 #define A4XX_TEX_CONST_0_FMT__MASK 0x1fc00000 2219 #define A4XX_TEX_CONST_0_FMT__SHIFT 22 2220 static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val) 2221 { 2222 return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK; 2223 } 2224 #define A4XX_TEX_CONST_0_TYPE__MASK 0x60000000 2225 #define A4XX_TEX_CONST_0_TYPE__SHIFT 29 2226 static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val) 2227 { 2228 return ((val) << A4XX_TEX_CONST_0_TYPE__SHIFT) & A4XX_TEX_CONST_0_TYPE__MASK; 2229 } 2230 2231 #define REG_A4XX_TEX_CONST_1 0x00000001 2232 #define A4XX_TEX_CONST_1_HEIGHT__MASK 0x00007fff 2233 #define A4XX_TEX_CONST_1_HEIGHT__SHIFT 0 2234 static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val) 2235 { 2236 return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK; 2237 } 2238 #define A4XX_TEX_CONST_1_WIDTH__MASK 0x1fff8000 2239 #define A4XX_TEX_CONST_1_WIDTH__SHIFT 15 2240 static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val) 2241 { 2242 return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK; 2243 } 2244 2245 #define REG_A4XX_TEX_CONST_2 0x00000002 2246 #define A4XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f 2247 #define A4XX_TEX_CONST_2_FETCHSIZE__SHIFT 0 2248 static inline uint32_t A4XX_TEX_CONST_2_FETCHSIZE(enum a4xx_tex_fetchsize val) 2249 { 2250 return ((val) << A4XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A4XX_TEX_CONST_2_FETCHSIZE__MASK; 2251 } 2252 #define A4XX_TEX_CONST_2_PITCH__MASK 0x3ffffe00 2253 #define A4XX_TEX_CONST_2_PITCH__SHIFT 9 2254 static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val) 2255 { 2256 return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) & A4XX_TEX_CONST_2_PITCH__MASK; 2257 } 2258 #define A4XX_TEX_CONST_2_SWAP__MASK 0xc0000000 2259 #define A4XX_TEX_CONST_2_SWAP__SHIFT 30 2260 static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) 2261 { 2262 return ((val) << A4XX_TEX_CONST_2_SWAP__SHIFT) & A4XX_TEX_CONST_2_SWAP__MASK; 2263 } 2264 2265 #define REG_A4XX_TEX_CONST_3 0x00000003 2266 #define A4XX_TEX_CONST_3_LAYERSZ__MASK 0x00003fff 2267 #define A4XX_TEX_CONST_3_LAYERSZ__SHIFT 0 2268 static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val) 2269 { 2270 return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK; 2271 } 2272 #define A4XX_TEX_CONST_3_DEPTH__MASK 0x7ffc0000 2273 #define A4XX_TEX_CONST_3_DEPTH__SHIFT 18 2274 static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val) 2275 { 2276 return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK; 2277 } 2278 2279 #define REG_A4XX_TEX_CONST_4 0x00000004 2280 #define A4XX_TEX_CONST_4_LAYERSZ__MASK 0x0000000f 2281 #define A4XX_TEX_CONST_4_LAYERSZ__SHIFT 0 2282 static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val) 2283 { 2284 return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK; 2285 } 2286 #define A4XX_TEX_CONST_4_BASE__MASK 0xffffffe0 2287 #define A4XX_TEX_CONST_4_BASE__SHIFT 5 2288 static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val) 2289 { 2290 return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK; 2291 } 2292 2293 #define REG_A4XX_TEX_CONST_5 0x00000005 2294 2295 #define REG_A4XX_TEX_CONST_6 0x00000006 2296 2297 #define REG_A4XX_TEX_CONST_7 0x00000007 2298 2299 2300 #endif /* A4XX_XML */ 2301