xref: /openbmc/linux/drivers/gpu/drm/msm/adreno/a4xx.xml.h (revision 791d3ef2)
1 #ifndef A4XX_XML
2 #define A4XX_XML
3 
4 /* Autogenerated file, DO NOT EDIT manually!
5 
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9 
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    431 bytes, from 2017-05-17 13:21:27)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2017-05-17 13:21:27)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  37162 bytes, from 2017-05-17 13:21:27)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  13324 bytes, from 2017-05-17 13:21:27)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  31866 bytes, from 2017-06-06 18:26:14)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2017-05-17 13:21:27)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 111898 bytes, from 2017-06-06 18:23:59)
18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          ( 139480 bytes, from 2017-06-16 12:44:39)
19 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2017-05-17 13:21:27)
20 
21 Copyright (C) 2013-2017 by the following authors:
22 - Rob Clark <robdclark@gmail.com> (robclark)
23 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
24 
25 Permission is hereby granted, free of charge, to any person obtaining
26 a copy of this software and associated documentation files (the
27 "Software"), to deal in the Software without restriction, including
28 without limitation the rights to use, copy, modify, merge, publish,
29 distribute, sublicense, and/or sell copies of the Software, and to
30 permit persons to whom the Software is furnished to do so, subject to
31 the following conditions:
32 
33 The above copyright notice and this permission notice (including the
34 next paragraph) shall be included in all copies or substantial
35 portions of the Software.
36 
37 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
39 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
40 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
41 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
42 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
43 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
44 */
45 
46 
47 enum a4xx_color_fmt {
48 	RB4_A8_UNORM = 1,
49 	RB4_R8_UNORM = 2,
50 	RB4_R8_SNORM = 3,
51 	RB4_R8_UINT = 4,
52 	RB4_R8_SINT = 5,
53 	RB4_R4G4B4A4_UNORM = 8,
54 	RB4_R5G5B5A1_UNORM = 10,
55 	RB4_R5G6B5_UNORM = 14,
56 	RB4_R8G8_UNORM = 15,
57 	RB4_R8G8_SNORM = 16,
58 	RB4_R8G8_UINT = 17,
59 	RB4_R8G8_SINT = 18,
60 	RB4_R16_UNORM = 19,
61 	RB4_R16_SNORM = 20,
62 	RB4_R16_FLOAT = 21,
63 	RB4_R16_UINT = 22,
64 	RB4_R16_SINT = 23,
65 	RB4_R8G8B8_UNORM = 25,
66 	RB4_R8G8B8A8_UNORM = 26,
67 	RB4_R8G8B8A8_SNORM = 28,
68 	RB4_R8G8B8A8_UINT = 29,
69 	RB4_R8G8B8A8_SINT = 30,
70 	RB4_R10G10B10A2_UNORM = 31,
71 	RB4_R10G10B10A2_UINT = 34,
72 	RB4_R11G11B10_FLOAT = 39,
73 	RB4_R16G16_UNORM = 40,
74 	RB4_R16G16_SNORM = 41,
75 	RB4_R16G16_FLOAT = 42,
76 	RB4_R16G16_UINT = 43,
77 	RB4_R16G16_SINT = 44,
78 	RB4_R32_FLOAT = 45,
79 	RB4_R32_UINT = 46,
80 	RB4_R32_SINT = 47,
81 	RB4_R16G16B16A16_UNORM = 52,
82 	RB4_R16G16B16A16_SNORM = 53,
83 	RB4_R16G16B16A16_FLOAT = 54,
84 	RB4_R16G16B16A16_UINT = 55,
85 	RB4_R16G16B16A16_SINT = 56,
86 	RB4_R32G32_FLOAT = 57,
87 	RB4_R32G32_UINT = 58,
88 	RB4_R32G32_SINT = 59,
89 	RB4_R32G32B32A32_FLOAT = 60,
90 	RB4_R32G32B32A32_UINT = 61,
91 	RB4_R32G32B32A32_SINT = 62,
92 };
93 
94 enum a4xx_tile_mode {
95 	TILE4_LINEAR = 0,
96 	TILE4_2 = 2,
97 	TILE4_3 = 3,
98 };
99 
100 enum a4xx_vtx_fmt {
101 	VFMT4_32_FLOAT = 1,
102 	VFMT4_32_32_FLOAT = 2,
103 	VFMT4_32_32_32_FLOAT = 3,
104 	VFMT4_32_32_32_32_FLOAT = 4,
105 	VFMT4_16_FLOAT = 5,
106 	VFMT4_16_16_FLOAT = 6,
107 	VFMT4_16_16_16_FLOAT = 7,
108 	VFMT4_16_16_16_16_FLOAT = 8,
109 	VFMT4_32_FIXED = 9,
110 	VFMT4_32_32_FIXED = 10,
111 	VFMT4_32_32_32_FIXED = 11,
112 	VFMT4_32_32_32_32_FIXED = 12,
113 	VFMT4_11_11_10_FLOAT = 13,
114 	VFMT4_16_SINT = 16,
115 	VFMT4_16_16_SINT = 17,
116 	VFMT4_16_16_16_SINT = 18,
117 	VFMT4_16_16_16_16_SINT = 19,
118 	VFMT4_16_UINT = 20,
119 	VFMT4_16_16_UINT = 21,
120 	VFMT4_16_16_16_UINT = 22,
121 	VFMT4_16_16_16_16_UINT = 23,
122 	VFMT4_16_SNORM = 24,
123 	VFMT4_16_16_SNORM = 25,
124 	VFMT4_16_16_16_SNORM = 26,
125 	VFMT4_16_16_16_16_SNORM = 27,
126 	VFMT4_16_UNORM = 28,
127 	VFMT4_16_16_UNORM = 29,
128 	VFMT4_16_16_16_UNORM = 30,
129 	VFMT4_16_16_16_16_UNORM = 31,
130 	VFMT4_32_UINT = 32,
131 	VFMT4_32_32_UINT = 33,
132 	VFMT4_32_32_32_UINT = 34,
133 	VFMT4_32_32_32_32_UINT = 35,
134 	VFMT4_32_SINT = 36,
135 	VFMT4_32_32_SINT = 37,
136 	VFMT4_32_32_32_SINT = 38,
137 	VFMT4_32_32_32_32_SINT = 39,
138 	VFMT4_8_UINT = 40,
139 	VFMT4_8_8_UINT = 41,
140 	VFMT4_8_8_8_UINT = 42,
141 	VFMT4_8_8_8_8_UINT = 43,
142 	VFMT4_8_UNORM = 44,
143 	VFMT4_8_8_UNORM = 45,
144 	VFMT4_8_8_8_UNORM = 46,
145 	VFMT4_8_8_8_8_UNORM = 47,
146 	VFMT4_8_SINT = 48,
147 	VFMT4_8_8_SINT = 49,
148 	VFMT4_8_8_8_SINT = 50,
149 	VFMT4_8_8_8_8_SINT = 51,
150 	VFMT4_8_SNORM = 52,
151 	VFMT4_8_8_SNORM = 53,
152 	VFMT4_8_8_8_SNORM = 54,
153 	VFMT4_8_8_8_8_SNORM = 55,
154 	VFMT4_10_10_10_2_UINT = 56,
155 	VFMT4_10_10_10_2_UNORM = 57,
156 	VFMT4_10_10_10_2_SINT = 58,
157 	VFMT4_10_10_10_2_SNORM = 59,
158 	VFMT4_2_10_10_10_UINT = 60,
159 	VFMT4_2_10_10_10_UNORM = 61,
160 	VFMT4_2_10_10_10_SINT = 62,
161 	VFMT4_2_10_10_10_SNORM = 63,
162 };
163 
164 enum a4xx_tex_fmt {
165 	TFMT4_A8_UNORM = 3,
166 	TFMT4_8_UNORM = 4,
167 	TFMT4_8_SNORM = 5,
168 	TFMT4_8_UINT = 6,
169 	TFMT4_8_SINT = 7,
170 	TFMT4_4_4_4_4_UNORM = 8,
171 	TFMT4_5_5_5_1_UNORM = 9,
172 	TFMT4_5_6_5_UNORM = 11,
173 	TFMT4_L8_A8_UNORM = 13,
174 	TFMT4_8_8_UNORM = 14,
175 	TFMT4_8_8_SNORM = 15,
176 	TFMT4_8_8_UINT = 16,
177 	TFMT4_8_8_SINT = 17,
178 	TFMT4_16_UNORM = 18,
179 	TFMT4_16_SNORM = 19,
180 	TFMT4_16_FLOAT = 20,
181 	TFMT4_16_UINT = 21,
182 	TFMT4_16_SINT = 22,
183 	TFMT4_8_8_8_8_UNORM = 28,
184 	TFMT4_8_8_8_8_SNORM = 29,
185 	TFMT4_8_8_8_8_UINT = 30,
186 	TFMT4_8_8_8_8_SINT = 31,
187 	TFMT4_9_9_9_E5_FLOAT = 32,
188 	TFMT4_10_10_10_2_UNORM = 33,
189 	TFMT4_10_10_10_2_UINT = 34,
190 	TFMT4_11_11_10_FLOAT = 37,
191 	TFMT4_16_16_UNORM = 38,
192 	TFMT4_16_16_SNORM = 39,
193 	TFMT4_16_16_FLOAT = 40,
194 	TFMT4_16_16_UINT = 41,
195 	TFMT4_16_16_SINT = 42,
196 	TFMT4_32_FLOAT = 43,
197 	TFMT4_32_UINT = 44,
198 	TFMT4_32_SINT = 45,
199 	TFMT4_16_16_16_16_UNORM = 51,
200 	TFMT4_16_16_16_16_SNORM = 52,
201 	TFMT4_16_16_16_16_FLOAT = 53,
202 	TFMT4_16_16_16_16_UINT = 54,
203 	TFMT4_16_16_16_16_SINT = 55,
204 	TFMT4_32_32_FLOAT = 56,
205 	TFMT4_32_32_UINT = 57,
206 	TFMT4_32_32_SINT = 58,
207 	TFMT4_32_32_32_FLOAT = 59,
208 	TFMT4_32_32_32_UINT = 60,
209 	TFMT4_32_32_32_SINT = 61,
210 	TFMT4_32_32_32_32_FLOAT = 63,
211 	TFMT4_32_32_32_32_UINT = 64,
212 	TFMT4_32_32_32_32_SINT = 65,
213 	TFMT4_X8Z24_UNORM = 71,
214 	TFMT4_DXT1 = 86,
215 	TFMT4_DXT3 = 87,
216 	TFMT4_DXT5 = 88,
217 	TFMT4_RGTC1_UNORM = 90,
218 	TFMT4_RGTC1_SNORM = 91,
219 	TFMT4_RGTC2_UNORM = 94,
220 	TFMT4_RGTC2_SNORM = 95,
221 	TFMT4_BPTC_UFLOAT = 97,
222 	TFMT4_BPTC_FLOAT = 98,
223 	TFMT4_BPTC = 99,
224 	TFMT4_ATC_RGB = 100,
225 	TFMT4_ATC_RGBA_EXPLICIT = 101,
226 	TFMT4_ATC_RGBA_INTERPOLATED = 102,
227 	TFMT4_ETC2_RG11_UNORM = 103,
228 	TFMT4_ETC2_RG11_SNORM = 104,
229 	TFMT4_ETC2_R11_UNORM = 105,
230 	TFMT4_ETC2_R11_SNORM = 106,
231 	TFMT4_ETC1 = 107,
232 	TFMT4_ETC2_RGB8 = 108,
233 	TFMT4_ETC2_RGBA8 = 109,
234 	TFMT4_ETC2_RGB8A1 = 110,
235 	TFMT4_ASTC_4x4 = 111,
236 	TFMT4_ASTC_5x4 = 112,
237 	TFMT4_ASTC_5x5 = 113,
238 	TFMT4_ASTC_6x5 = 114,
239 	TFMT4_ASTC_6x6 = 115,
240 	TFMT4_ASTC_8x5 = 116,
241 	TFMT4_ASTC_8x6 = 117,
242 	TFMT4_ASTC_8x8 = 118,
243 	TFMT4_ASTC_10x5 = 119,
244 	TFMT4_ASTC_10x6 = 120,
245 	TFMT4_ASTC_10x8 = 121,
246 	TFMT4_ASTC_10x10 = 122,
247 	TFMT4_ASTC_12x10 = 123,
248 	TFMT4_ASTC_12x12 = 124,
249 };
250 
251 enum a4xx_tex_fetchsize {
252 	TFETCH4_1_BYTE = 0,
253 	TFETCH4_2_BYTE = 1,
254 	TFETCH4_4_BYTE = 2,
255 	TFETCH4_8_BYTE = 3,
256 	TFETCH4_16_BYTE = 4,
257 };
258 
259 enum a4xx_depth_format {
260 	DEPTH4_NONE = 0,
261 	DEPTH4_16 = 1,
262 	DEPTH4_24_8 = 2,
263 	DEPTH4_32 = 3,
264 };
265 
266 enum a4xx_tess_spacing {
267 	EQUAL_SPACING = 0,
268 	ODD_SPACING = 2,
269 	EVEN_SPACING = 3,
270 };
271 
272 enum a4xx_ccu_perfcounter_select {
273 	CCU_BUSY_CYCLES = 0,
274 	CCU_RB_DEPTH_RETURN_STALL = 2,
275 	CCU_RB_COLOR_RETURN_STALL = 3,
276 	CCU_DEPTH_BLOCKS = 6,
277 	CCU_COLOR_BLOCKS = 7,
278 	CCU_DEPTH_BLOCK_HIT = 8,
279 	CCU_COLOR_BLOCK_HIT = 9,
280 	CCU_DEPTH_FLAG1_COUNT = 10,
281 	CCU_DEPTH_FLAG2_COUNT = 11,
282 	CCU_DEPTH_FLAG3_COUNT = 12,
283 	CCU_DEPTH_FLAG4_COUNT = 13,
284 	CCU_COLOR_FLAG1_COUNT = 14,
285 	CCU_COLOR_FLAG2_COUNT = 15,
286 	CCU_COLOR_FLAG3_COUNT = 16,
287 	CCU_COLOR_FLAG4_COUNT = 17,
288 	CCU_PARTIAL_BLOCK_READ = 18,
289 };
290 
291 enum a4xx_cp_perfcounter_select {
292 	CP_ALWAYS_COUNT = 0,
293 	CP_BUSY = 1,
294 	CP_PFP_IDLE = 2,
295 	CP_PFP_BUSY_WORKING = 3,
296 	CP_PFP_STALL_CYCLES_ANY = 4,
297 	CP_PFP_STARVE_CYCLES_ANY = 5,
298 	CP_PFP_STARVED_PER_LOAD_ADDR = 6,
299 	CP_PFP_STALLED_PER_STORE_ADDR = 7,
300 	CP_PFP_PC_PROFILE = 8,
301 	CP_PFP_MATCH_PM4_PKT_PROFILE = 9,
302 	CP_PFP_COND_INDIRECT_DISCARDED = 10,
303 	CP_LONG_RESUMPTIONS = 11,
304 	CP_RESUME_CYCLES = 12,
305 	CP_RESUME_TO_BOUNDARY_CYCLES = 13,
306 	CP_LONG_PREEMPTIONS = 14,
307 	CP_PREEMPT_CYCLES = 15,
308 	CP_PREEMPT_TO_BOUNDARY_CYCLES = 16,
309 	CP_ME_FIFO_EMPTY_PFP_IDLE = 17,
310 	CP_ME_FIFO_EMPTY_PFP_BUSY = 18,
311 	CP_ME_FIFO_NOT_EMPTY_NOT_FULL = 19,
312 	CP_ME_FIFO_FULL_ME_BUSY = 20,
313 	CP_ME_FIFO_FULL_ME_NON_WORKING = 21,
314 	CP_ME_WAITING_FOR_PACKETS = 22,
315 	CP_ME_BUSY_WORKING = 23,
316 	CP_ME_STARVE_CYCLES_ANY = 24,
317 	CP_ME_STARVE_CYCLES_PER_PROFILE = 25,
318 	CP_ME_STALL_CYCLES_PER_PROFILE = 26,
319 	CP_ME_PC_PROFILE = 27,
320 	CP_RCIU_FIFO_EMPTY = 28,
321 	CP_RCIU_FIFO_NOT_EMPTY_NOT_FULL = 29,
322 	CP_RCIU_FIFO_FULL = 30,
323 	CP_RCIU_FIFO_FULL_NO_CONTEXT = 31,
324 	CP_RCIU_FIFO_FULL_AHB_MASTER = 32,
325 	CP_RCIU_FIFO_FULL_OTHER = 33,
326 	CP_AHB_IDLE = 34,
327 	CP_AHB_STALL_ON_GRANT_NO_SPLIT = 35,
328 	CP_AHB_STALL_ON_GRANT_SPLIT = 36,
329 	CP_AHB_STALL_ON_GRANT_SPLIT_PROFILE = 37,
330 	CP_AHB_BUSY_WORKING = 38,
331 	CP_AHB_BUSY_STALL_ON_HRDY = 39,
332 	CP_AHB_BUSY_STALL_ON_HRDY_PROFILE = 40,
333 };
334 
335 enum a4xx_gras_ras_perfcounter_select {
336 	RAS_SUPER_TILES = 0,
337 	RAS_8X8_TILES = 1,
338 	RAS_4X4_TILES = 2,
339 	RAS_BUSY_CYCLES = 3,
340 	RAS_STALL_CYCLES_BY_RB = 4,
341 	RAS_STALL_CYCLES_BY_VSC = 5,
342 	RAS_STARVE_CYCLES_BY_TSE = 6,
343 	RAS_SUPERTILE_CYCLES = 7,
344 	RAS_TILE_CYCLES = 8,
345 	RAS_FULLY_COVERED_SUPER_TILES = 9,
346 	RAS_FULLY_COVERED_8X8_TILES = 10,
347 	RAS_4X4_PRIM = 11,
348 	RAS_8X4_4X8_PRIM = 12,
349 	RAS_8X8_PRIM = 13,
350 };
351 
352 enum a4xx_gras_tse_perfcounter_select {
353 	TSE_INPUT_PRIM = 0,
354 	TSE_INPUT_NULL_PRIM = 1,
355 	TSE_TRIVAL_REJ_PRIM = 2,
356 	TSE_CLIPPED_PRIM = 3,
357 	TSE_NEW_PRIM = 4,
358 	TSE_ZERO_AREA_PRIM = 5,
359 	TSE_FACENESS_CULLED_PRIM = 6,
360 	TSE_ZERO_PIXEL_PRIM = 7,
361 	TSE_OUTPUT_NULL_PRIM = 8,
362 	TSE_OUTPUT_VISIBLE_PRIM = 9,
363 	TSE_PRE_CLIP_PRIM = 10,
364 	TSE_POST_CLIP_PRIM = 11,
365 	TSE_BUSY_CYCLES = 12,
366 	TSE_PC_STARVE = 13,
367 	TSE_RAS_STALL = 14,
368 	TSE_STALL_BARYPLANE_FIFO_FULL = 15,
369 	TSE_STALL_ZPLANE_FIFO_FULL = 16,
370 };
371 
372 enum a4xx_hlsq_perfcounter_select {
373 	HLSQ_SP_VS_STAGE_CONSTANT = 0,
374 	HLSQ_SP_VS_STAGE_INSTRUCTIONS = 1,
375 	HLSQ_SP_FS_STAGE_CONSTANT = 2,
376 	HLSQ_SP_FS_STAGE_INSTRUCTIONS = 3,
377 	HLSQ_TP_STATE = 4,
378 	HLSQ_QUADS = 5,
379 	HLSQ_PIXELS = 6,
380 	HLSQ_VERTICES = 7,
381 	HLSQ_SP_VS_STAGE_DATA_BYTES = 13,
382 	HLSQ_SP_FS_STAGE_DATA_BYTES = 14,
383 	HLSQ_BUSY_CYCLES = 15,
384 	HLSQ_STALL_CYCLES_SP_STATE = 16,
385 	HLSQ_STALL_CYCLES_SP_VS_STAGE = 17,
386 	HLSQ_STALL_CYCLES_SP_FS_STAGE = 18,
387 	HLSQ_STALL_CYCLES_UCHE = 19,
388 	HLSQ_RBBM_LOAD_CYCLES = 20,
389 	HLSQ_DI_TO_VS_START_SP = 21,
390 	HLSQ_DI_TO_FS_START_SP = 22,
391 	HLSQ_VS_STAGE_START_TO_DONE_SP = 23,
392 	HLSQ_FS_STAGE_START_TO_DONE_SP = 24,
393 	HLSQ_SP_STATE_COPY_CYCLES_VS_STAGE = 25,
394 	HLSQ_SP_STATE_COPY_CYCLES_FS_STAGE = 26,
395 	HLSQ_UCHE_LATENCY_CYCLES = 27,
396 	HLSQ_UCHE_LATENCY_COUNT = 28,
397 	HLSQ_STARVE_CYCLES_VFD = 29,
398 };
399 
400 enum a4xx_pc_perfcounter_select {
401 	PC_VIS_STREAMS_LOADED = 0,
402 	PC_VPC_PRIMITIVES = 2,
403 	PC_DEAD_PRIM = 3,
404 	PC_LIVE_PRIM = 4,
405 	PC_DEAD_DRAWCALLS = 5,
406 	PC_LIVE_DRAWCALLS = 6,
407 	PC_VERTEX_MISSES = 7,
408 	PC_STALL_CYCLES_VFD = 9,
409 	PC_STALL_CYCLES_TSE = 10,
410 	PC_STALL_CYCLES_UCHE = 11,
411 	PC_WORKING_CYCLES = 12,
412 	PC_IA_VERTICES = 13,
413 	PC_GS_PRIMITIVES = 14,
414 	PC_HS_INVOCATIONS = 15,
415 	PC_DS_INVOCATIONS = 16,
416 	PC_DS_PRIMITIVES = 17,
417 	PC_STARVE_CYCLES_FOR_INDEX = 20,
418 	PC_STARVE_CYCLES_FOR_TESS_FACTOR = 21,
419 	PC_STARVE_CYCLES_FOR_VIZ_STREAM = 22,
420 	PC_STALL_CYCLES_TESS = 23,
421 	PC_STARVE_CYCLES_FOR_POSITION = 24,
422 	PC_MODE0_DRAWCALL = 25,
423 	PC_MODE1_DRAWCALL = 26,
424 	PC_MODE2_DRAWCALL = 27,
425 	PC_MODE3_DRAWCALL = 28,
426 	PC_MODE4_DRAWCALL = 29,
427 	PC_PREDICATED_DEAD_DRAWCALL = 30,
428 	PC_STALL_CYCLES_BY_TSE_ONLY = 31,
429 	PC_STALL_CYCLES_BY_VPC_ONLY = 32,
430 	PC_VPC_POS_DATA_TRANSACTION = 33,
431 	PC_BUSY_CYCLES = 34,
432 	PC_STARVE_CYCLES_DI = 35,
433 	PC_STALL_CYCLES_VPC = 36,
434 	TESS_WORKING_CYCLES = 37,
435 	TESS_NUM_CYCLES_SETUP_WORKING = 38,
436 	TESS_NUM_CYCLES_PTGEN_WORKING = 39,
437 	TESS_NUM_CYCLES_CONNGEN_WORKING = 40,
438 	TESS_BUSY_CYCLES = 41,
439 	TESS_STARVE_CYCLES_PC = 42,
440 	TESS_STALL_CYCLES_PC = 43,
441 };
442 
443 enum a4xx_pwr_perfcounter_select {
444 	PWR_CORE_CLOCK_CYCLES = 0,
445 	PWR_BUSY_CLOCK_CYCLES = 1,
446 };
447 
448 enum a4xx_rb_perfcounter_select {
449 	RB_BUSY_CYCLES = 0,
450 	RB_BUSY_CYCLES_BINNING = 1,
451 	RB_BUSY_CYCLES_RENDERING = 2,
452 	RB_BUSY_CYCLES_RESOLVE = 3,
453 	RB_STARVE_CYCLES_BY_SP = 4,
454 	RB_STARVE_CYCLES_BY_RAS = 5,
455 	RB_STARVE_CYCLES_BY_MARB = 6,
456 	RB_STALL_CYCLES_BY_MARB = 7,
457 	RB_STALL_CYCLES_BY_HLSQ = 8,
458 	RB_RB_RB_MARB_DATA = 9,
459 	RB_SP_RB_QUAD = 10,
460 	RB_RAS_RB_Z_QUADS = 11,
461 	RB_GMEM_CH0_READ = 12,
462 	RB_GMEM_CH1_READ = 13,
463 	RB_GMEM_CH0_WRITE = 14,
464 	RB_GMEM_CH1_WRITE = 15,
465 	RB_CP_CONTEXT_DONE = 16,
466 	RB_CP_CACHE_FLUSH = 17,
467 	RB_CP_ZPASS_DONE = 18,
468 	RB_STALL_FIFO0_FULL = 19,
469 	RB_STALL_FIFO1_FULL = 20,
470 	RB_STALL_FIFO2_FULL = 21,
471 	RB_STALL_FIFO3_FULL = 22,
472 	RB_RB_HLSQ_TRANSACTIONS = 23,
473 	RB_Z_READ = 24,
474 	RB_Z_WRITE = 25,
475 	RB_C_READ = 26,
476 	RB_C_WRITE = 27,
477 	RB_C_READ_LATENCY = 28,
478 	RB_Z_READ_LATENCY = 29,
479 	RB_STALL_BY_UCHE = 30,
480 	RB_MARB_UCHE_TRANSACTIONS = 31,
481 	RB_CACHE_STALL_MISS = 32,
482 	RB_CACHE_STALL_FIFO_FULL = 33,
483 	RB_8BIT_BLENDER_UNITS_ACTIVE = 34,
484 	RB_16BIT_BLENDER_UNITS_ACTIVE = 35,
485 	RB_SAMPLER_UNITS_ACTIVE = 36,
486 	RB_TOTAL_PASS = 38,
487 	RB_Z_PASS = 39,
488 	RB_Z_FAIL = 40,
489 	RB_S_FAIL = 41,
490 	RB_POWER0 = 42,
491 	RB_POWER1 = 43,
492 	RB_POWER2 = 44,
493 	RB_POWER3 = 45,
494 	RB_POWER4 = 46,
495 	RB_POWER5 = 47,
496 	RB_POWER6 = 48,
497 	RB_POWER7 = 49,
498 };
499 
500 enum a4xx_rbbm_perfcounter_select {
501 	RBBM_ALWAYS_ON = 0,
502 	RBBM_VBIF_BUSY = 1,
503 	RBBM_TSE_BUSY = 2,
504 	RBBM_RAS_BUSY = 3,
505 	RBBM_PC_DCALL_BUSY = 4,
506 	RBBM_PC_VSD_BUSY = 5,
507 	RBBM_VFD_BUSY = 6,
508 	RBBM_VPC_BUSY = 7,
509 	RBBM_UCHE_BUSY = 8,
510 	RBBM_VSC_BUSY = 9,
511 	RBBM_HLSQ_BUSY = 10,
512 	RBBM_ANY_RB_BUSY = 11,
513 	RBBM_ANY_TPL1_BUSY = 12,
514 	RBBM_ANY_SP_BUSY = 13,
515 	RBBM_ANY_MARB_BUSY = 14,
516 	RBBM_ANY_ARB_BUSY = 15,
517 	RBBM_AHB_STATUS_BUSY = 16,
518 	RBBM_AHB_STATUS_STALLED = 17,
519 	RBBM_AHB_STATUS_TXFR = 18,
520 	RBBM_AHB_STATUS_TXFR_SPLIT = 19,
521 	RBBM_AHB_STATUS_TXFR_ERROR = 20,
522 	RBBM_AHB_STATUS_LONG_STALL = 21,
523 	RBBM_STATUS_MASKED = 22,
524 	RBBM_CP_BUSY_GFX_CORE_IDLE = 23,
525 	RBBM_TESS_BUSY = 24,
526 	RBBM_COM_BUSY = 25,
527 	RBBM_DCOM_BUSY = 32,
528 	RBBM_ANY_CCU_BUSY = 33,
529 	RBBM_DPM_BUSY = 34,
530 };
531 
532 enum a4xx_sp_perfcounter_select {
533 	SP_LM_LOAD_INSTRUCTIONS = 0,
534 	SP_LM_STORE_INSTRUCTIONS = 1,
535 	SP_LM_ATOMICS = 2,
536 	SP_GM_LOAD_INSTRUCTIONS = 3,
537 	SP_GM_STORE_INSTRUCTIONS = 4,
538 	SP_GM_ATOMICS = 5,
539 	SP_VS_STAGE_TEX_INSTRUCTIONS = 6,
540 	SP_VS_STAGE_CFLOW_INSTRUCTIONS = 7,
541 	SP_VS_STAGE_EFU_INSTRUCTIONS = 8,
542 	SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 9,
543 	SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 10,
544 	SP_FS_STAGE_TEX_INSTRUCTIONS = 11,
545 	SP_FS_STAGE_CFLOW_INSTRUCTIONS = 12,
546 	SP_FS_STAGE_EFU_INSTRUCTIONS = 13,
547 	SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 14,
548 	SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 15,
549 	SP_VS_INSTRUCTIONS = 17,
550 	SP_FS_INSTRUCTIONS = 18,
551 	SP_ADDR_LOCK_COUNT = 19,
552 	SP_UCHE_READ_TRANS = 20,
553 	SP_UCHE_WRITE_TRANS = 21,
554 	SP_EXPORT_VPC_TRANS = 22,
555 	SP_EXPORT_RB_TRANS = 23,
556 	SP_PIXELS_KILLED = 24,
557 	SP_ICL1_REQUESTS = 25,
558 	SP_ICL1_MISSES = 26,
559 	SP_ICL0_REQUESTS = 27,
560 	SP_ICL0_MISSES = 28,
561 	SP_ALU_WORKING_CYCLES = 29,
562 	SP_EFU_WORKING_CYCLES = 30,
563 	SP_STALL_CYCLES_BY_VPC = 31,
564 	SP_STALL_CYCLES_BY_TP = 32,
565 	SP_STALL_CYCLES_BY_UCHE = 33,
566 	SP_STALL_CYCLES_BY_RB = 34,
567 	SP_BUSY_CYCLES = 35,
568 	SP_HS_INSTRUCTIONS = 36,
569 	SP_DS_INSTRUCTIONS = 37,
570 	SP_GS_INSTRUCTIONS = 38,
571 	SP_CS_INSTRUCTIONS = 39,
572 	SP_SCHEDULER_NON_WORKING = 40,
573 	SP_WAVE_CONTEXTS = 41,
574 	SP_WAVE_CONTEXT_CYCLES = 42,
575 	SP_POWER0 = 43,
576 	SP_POWER1 = 44,
577 	SP_POWER2 = 45,
578 	SP_POWER3 = 46,
579 	SP_POWER4 = 47,
580 	SP_POWER5 = 48,
581 	SP_POWER6 = 49,
582 	SP_POWER7 = 50,
583 	SP_POWER8 = 51,
584 	SP_POWER9 = 52,
585 	SP_POWER10 = 53,
586 	SP_POWER11 = 54,
587 	SP_POWER12 = 55,
588 	SP_POWER13 = 56,
589 	SP_POWER14 = 57,
590 	SP_POWER15 = 58,
591 };
592 
593 enum a4xx_tp_perfcounter_select {
594 	TP_L1_REQUESTS = 0,
595 	TP_L1_MISSES = 1,
596 	TP_QUADS_OFFSET = 8,
597 	TP_QUAD_SHADOW = 9,
598 	TP_QUADS_ARRAY = 10,
599 	TP_QUADS_GRADIENT = 11,
600 	TP_QUADS_1D2D = 12,
601 	TP_QUADS_3DCUBE = 13,
602 	TP_BUSY_CYCLES = 16,
603 	TP_STALL_CYCLES_BY_ARB = 17,
604 	TP_STATE_CACHE_REQUESTS = 20,
605 	TP_STATE_CACHE_MISSES = 21,
606 	TP_POWER0 = 22,
607 	TP_POWER1 = 23,
608 	TP_POWER2 = 24,
609 	TP_POWER3 = 25,
610 	TP_POWER4 = 26,
611 	TP_POWER5 = 27,
612 	TP_POWER6 = 28,
613 	TP_POWER7 = 29,
614 };
615 
616 enum a4xx_uche_perfcounter_select {
617 	UCHE_VBIF_READ_BEATS_TP = 0,
618 	UCHE_VBIF_READ_BEATS_VFD = 1,
619 	UCHE_VBIF_READ_BEATS_HLSQ = 2,
620 	UCHE_VBIF_READ_BEATS_MARB = 3,
621 	UCHE_VBIF_READ_BEATS_SP = 4,
622 	UCHE_READ_REQUESTS_TP = 5,
623 	UCHE_READ_REQUESTS_VFD = 6,
624 	UCHE_READ_REQUESTS_HLSQ = 7,
625 	UCHE_READ_REQUESTS_MARB = 8,
626 	UCHE_READ_REQUESTS_SP = 9,
627 	UCHE_WRITE_REQUESTS_MARB = 10,
628 	UCHE_WRITE_REQUESTS_SP = 11,
629 	UCHE_TAG_CHECK_FAILS = 12,
630 	UCHE_EVICTS = 13,
631 	UCHE_FLUSHES = 14,
632 	UCHE_VBIF_LATENCY_CYCLES = 15,
633 	UCHE_VBIF_LATENCY_SAMPLES = 16,
634 	UCHE_BUSY_CYCLES = 17,
635 	UCHE_VBIF_READ_BEATS_PC = 18,
636 	UCHE_READ_REQUESTS_PC = 19,
637 	UCHE_WRITE_REQUESTS_VPC = 20,
638 	UCHE_STALL_BY_VBIF = 21,
639 	UCHE_WRITE_REQUESTS_VSC = 22,
640 	UCHE_POWER0 = 23,
641 	UCHE_POWER1 = 24,
642 	UCHE_POWER2 = 25,
643 	UCHE_POWER3 = 26,
644 	UCHE_POWER4 = 27,
645 	UCHE_POWER5 = 28,
646 	UCHE_POWER6 = 29,
647 	UCHE_POWER7 = 30,
648 };
649 
650 enum a4xx_vbif_perfcounter_select {
651 	AXI_READ_REQUESTS_ID_0 = 0,
652 	AXI_READ_REQUESTS_ID_1 = 1,
653 	AXI_READ_REQUESTS_ID_2 = 2,
654 	AXI_READ_REQUESTS_ID_3 = 3,
655 	AXI_READ_REQUESTS_ID_4 = 4,
656 	AXI_READ_REQUESTS_ID_5 = 5,
657 	AXI_READ_REQUESTS_ID_6 = 6,
658 	AXI_READ_REQUESTS_ID_7 = 7,
659 	AXI_READ_REQUESTS_ID_8 = 8,
660 	AXI_READ_REQUESTS_ID_9 = 9,
661 	AXI_READ_REQUESTS_ID_10 = 10,
662 	AXI_READ_REQUESTS_ID_11 = 11,
663 	AXI_READ_REQUESTS_ID_12 = 12,
664 	AXI_READ_REQUESTS_ID_13 = 13,
665 	AXI_READ_REQUESTS_ID_14 = 14,
666 	AXI_READ_REQUESTS_ID_15 = 15,
667 	AXI0_READ_REQUESTS_TOTAL = 16,
668 	AXI1_READ_REQUESTS_TOTAL = 17,
669 	AXI2_READ_REQUESTS_TOTAL = 18,
670 	AXI3_READ_REQUESTS_TOTAL = 19,
671 	AXI_READ_REQUESTS_TOTAL = 20,
672 	AXI_WRITE_REQUESTS_ID_0 = 21,
673 	AXI_WRITE_REQUESTS_ID_1 = 22,
674 	AXI_WRITE_REQUESTS_ID_2 = 23,
675 	AXI_WRITE_REQUESTS_ID_3 = 24,
676 	AXI_WRITE_REQUESTS_ID_4 = 25,
677 	AXI_WRITE_REQUESTS_ID_5 = 26,
678 	AXI_WRITE_REQUESTS_ID_6 = 27,
679 	AXI_WRITE_REQUESTS_ID_7 = 28,
680 	AXI_WRITE_REQUESTS_ID_8 = 29,
681 	AXI_WRITE_REQUESTS_ID_9 = 30,
682 	AXI_WRITE_REQUESTS_ID_10 = 31,
683 	AXI_WRITE_REQUESTS_ID_11 = 32,
684 	AXI_WRITE_REQUESTS_ID_12 = 33,
685 	AXI_WRITE_REQUESTS_ID_13 = 34,
686 	AXI_WRITE_REQUESTS_ID_14 = 35,
687 	AXI_WRITE_REQUESTS_ID_15 = 36,
688 	AXI0_WRITE_REQUESTS_TOTAL = 37,
689 	AXI1_WRITE_REQUESTS_TOTAL = 38,
690 	AXI2_WRITE_REQUESTS_TOTAL = 39,
691 	AXI3_WRITE_REQUESTS_TOTAL = 40,
692 	AXI_WRITE_REQUESTS_TOTAL = 41,
693 	AXI_TOTAL_REQUESTS = 42,
694 	AXI_READ_DATA_BEATS_ID_0 = 43,
695 	AXI_READ_DATA_BEATS_ID_1 = 44,
696 	AXI_READ_DATA_BEATS_ID_2 = 45,
697 	AXI_READ_DATA_BEATS_ID_3 = 46,
698 	AXI_READ_DATA_BEATS_ID_4 = 47,
699 	AXI_READ_DATA_BEATS_ID_5 = 48,
700 	AXI_READ_DATA_BEATS_ID_6 = 49,
701 	AXI_READ_DATA_BEATS_ID_7 = 50,
702 	AXI_READ_DATA_BEATS_ID_8 = 51,
703 	AXI_READ_DATA_BEATS_ID_9 = 52,
704 	AXI_READ_DATA_BEATS_ID_10 = 53,
705 	AXI_READ_DATA_BEATS_ID_11 = 54,
706 	AXI_READ_DATA_BEATS_ID_12 = 55,
707 	AXI_READ_DATA_BEATS_ID_13 = 56,
708 	AXI_READ_DATA_BEATS_ID_14 = 57,
709 	AXI_READ_DATA_BEATS_ID_15 = 58,
710 	AXI0_READ_DATA_BEATS_TOTAL = 59,
711 	AXI1_READ_DATA_BEATS_TOTAL = 60,
712 	AXI2_READ_DATA_BEATS_TOTAL = 61,
713 	AXI3_READ_DATA_BEATS_TOTAL = 62,
714 	AXI_READ_DATA_BEATS_TOTAL = 63,
715 	AXI_WRITE_DATA_BEATS_ID_0 = 64,
716 	AXI_WRITE_DATA_BEATS_ID_1 = 65,
717 	AXI_WRITE_DATA_BEATS_ID_2 = 66,
718 	AXI_WRITE_DATA_BEATS_ID_3 = 67,
719 	AXI_WRITE_DATA_BEATS_ID_4 = 68,
720 	AXI_WRITE_DATA_BEATS_ID_5 = 69,
721 	AXI_WRITE_DATA_BEATS_ID_6 = 70,
722 	AXI_WRITE_DATA_BEATS_ID_7 = 71,
723 	AXI_WRITE_DATA_BEATS_ID_8 = 72,
724 	AXI_WRITE_DATA_BEATS_ID_9 = 73,
725 	AXI_WRITE_DATA_BEATS_ID_10 = 74,
726 	AXI_WRITE_DATA_BEATS_ID_11 = 75,
727 	AXI_WRITE_DATA_BEATS_ID_12 = 76,
728 	AXI_WRITE_DATA_BEATS_ID_13 = 77,
729 	AXI_WRITE_DATA_BEATS_ID_14 = 78,
730 	AXI_WRITE_DATA_BEATS_ID_15 = 79,
731 	AXI0_WRITE_DATA_BEATS_TOTAL = 80,
732 	AXI1_WRITE_DATA_BEATS_TOTAL = 81,
733 	AXI2_WRITE_DATA_BEATS_TOTAL = 82,
734 	AXI3_WRITE_DATA_BEATS_TOTAL = 83,
735 	AXI_WRITE_DATA_BEATS_TOTAL = 84,
736 	AXI_DATA_BEATS_TOTAL = 85,
737 	CYCLES_HELD_OFF_ID_0 = 86,
738 	CYCLES_HELD_OFF_ID_1 = 87,
739 	CYCLES_HELD_OFF_ID_2 = 88,
740 	CYCLES_HELD_OFF_ID_3 = 89,
741 	CYCLES_HELD_OFF_ID_4 = 90,
742 	CYCLES_HELD_OFF_ID_5 = 91,
743 	CYCLES_HELD_OFF_ID_6 = 92,
744 	CYCLES_HELD_OFF_ID_7 = 93,
745 	CYCLES_HELD_OFF_ID_8 = 94,
746 	CYCLES_HELD_OFF_ID_9 = 95,
747 	CYCLES_HELD_OFF_ID_10 = 96,
748 	CYCLES_HELD_OFF_ID_11 = 97,
749 	CYCLES_HELD_OFF_ID_12 = 98,
750 	CYCLES_HELD_OFF_ID_13 = 99,
751 	CYCLES_HELD_OFF_ID_14 = 100,
752 	CYCLES_HELD_OFF_ID_15 = 101,
753 	AXI_READ_REQUEST_HELD_OFF = 102,
754 	AXI_WRITE_REQUEST_HELD_OFF = 103,
755 	AXI_REQUEST_HELD_OFF = 104,
756 	AXI_WRITE_DATA_HELD_OFF = 105,
757 	OCMEM_AXI_READ_REQUEST_HELD_OFF = 106,
758 	OCMEM_AXI_WRITE_REQUEST_HELD_OFF = 107,
759 	OCMEM_AXI_REQUEST_HELD_OFF = 108,
760 	OCMEM_AXI_WRITE_DATA_HELD_OFF = 109,
761 	ELAPSED_CYCLES_DDR = 110,
762 	ELAPSED_CYCLES_OCMEM = 111,
763 };
764 
765 enum a4xx_vfd_perfcounter_select {
766 	VFD_UCHE_BYTE_FETCHED = 0,
767 	VFD_UCHE_TRANS = 1,
768 	VFD_FETCH_INSTRUCTIONS = 3,
769 	VFD_BUSY_CYCLES = 5,
770 	VFD_STALL_CYCLES_UCHE = 6,
771 	VFD_STALL_CYCLES_HLSQ = 7,
772 	VFD_STALL_CYCLES_VPC_BYPASS = 8,
773 	VFD_STALL_CYCLES_VPC_ALLOC = 9,
774 	VFD_MODE_0_FIBERS = 13,
775 	VFD_MODE_1_FIBERS = 14,
776 	VFD_MODE_2_FIBERS = 15,
777 	VFD_MODE_3_FIBERS = 16,
778 	VFD_MODE_4_FIBERS = 17,
779 	VFD_BFIFO_STALL = 18,
780 	VFD_NUM_VERTICES_TOTAL = 19,
781 	VFD_PACKER_FULL = 20,
782 	VFD_UCHE_REQUEST_FIFO_FULL = 21,
783 	VFD_STARVE_CYCLES_PC = 22,
784 	VFD_STARVE_CYCLES_UCHE = 23,
785 };
786 
787 enum a4xx_vpc_perfcounter_select {
788 	VPC_SP_LM_COMPONENTS = 2,
789 	VPC_SP0_LM_BYTES = 3,
790 	VPC_SP1_LM_BYTES = 4,
791 	VPC_SP2_LM_BYTES = 5,
792 	VPC_SP3_LM_BYTES = 6,
793 	VPC_WORKING_CYCLES = 7,
794 	VPC_STALL_CYCLES_LM = 8,
795 	VPC_STARVE_CYCLES_RAS = 9,
796 	VPC_STREAMOUT_CYCLES = 10,
797 	VPC_UCHE_TRANSACTIONS = 12,
798 	VPC_STALL_CYCLES_UCHE = 13,
799 	VPC_BUSY_CYCLES = 14,
800 	VPC_STARVE_CYCLES_SP = 15,
801 };
802 
803 enum a4xx_vsc_perfcounter_select {
804 	VSC_BUSY_CYCLES = 0,
805 	VSC_WORKING_CYCLES = 1,
806 	VSC_STALL_CYCLES_UCHE = 2,
807 	VSC_STARVE_CYCLES_RAS = 3,
808 	VSC_EOT_NUM = 4,
809 };
810 
811 enum a4xx_tex_filter {
812 	A4XX_TEX_NEAREST = 0,
813 	A4XX_TEX_LINEAR = 1,
814 	A4XX_TEX_ANISO = 2,
815 };
816 
817 enum a4xx_tex_clamp {
818 	A4XX_TEX_REPEAT = 0,
819 	A4XX_TEX_CLAMP_TO_EDGE = 1,
820 	A4XX_TEX_MIRROR_REPEAT = 2,
821 	A4XX_TEX_CLAMP_TO_BORDER = 3,
822 	A4XX_TEX_MIRROR_CLAMP = 4,
823 };
824 
825 enum a4xx_tex_aniso {
826 	A4XX_TEX_ANISO_1 = 0,
827 	A4XX_TEX_ANISO_2 = 1,
828 	A4XX_TEX_ANISO_4 = 2,
829 	A4XX_TEX_ANISO_8 = 3,
830 	A4XX_TEX_ANISO_16 = 4,
831 };
832 
833 enum a4xx_tex_swiz {
834 	A4XX_TEX_X = 0,
835 	A4XX_TEX_Y = 1,
836 	A4XX_TEX_Z = 2,
837 	A4XX_TEX_W = 3,
838 	A4XX_TEX_ZERO = 4,
839 	A4XX_TEX_ONE = 5,
840 };
841 
842 enum a4xx_tex_type {
843 	A4XX_TEX_1D = 0,
844 	A4XX_TEX_2D = 1,
845 	A4XX_TEX_CUBE = 2,
846 	A4XX_TEX_3D = 3,
847 };
848 
849 #define A4XX_CGC_HLSQ_EARLY_CYC__MASK				0x00700000
850 #define A4XX_CGC_HLSQ_EARLY_CYC__SHIFT				20
851 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val)
852 {
853 	return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK;
854 }
855 #define A4XX_INT0_RBBM_GPU_IDLE					0x00000001
856 #define A4XX_INT0_RBBM_AHB_ERROR				0x00000002
857 #define A4XX_INT0_RBBM_REG_TIMEOUT				0x00000004
858 #define A4XX_INT0_RBBM_ME_MS_TIMEOUT				0x00000008
859 #define A4XX_INT0_RBBM_PFP_MS_TIMEOUT				0x00000010
860 #define A4XX_INT0_RBBM_ATB_BUS_OVERFLOW				0x00000020
861 #define A4XX_INT0_VFD_ERROR					0x00000040
862 #define A4XX_INT0_CP_SW_INT					0x00000080
863 #define A4XX_INT0_CP_T0_PACKET_IN_IB				0x00000100
864 #define A4XX_INT0_CP_OPCODE_ERROR				0x00000200
865 #define A4XX_INT0_CP_RESERVED_BIT_ERROR				0x00000400
866 #define A4XX_INT0_CP_HW_FAULT					0x00000800
867 #define A4XX_INT0_CP_DMA					0x00001000
868 #define A4XX_INT0_CP_IB2_INT					0x00002000
869 #define A4XX_INT0_CP_IB1_INT					0x00004000
870 #define A4XX_INT0_CP_RB_INT					0x00008000
871 #define A4XX_INT0_CP_REG_PROTECT_FAULT				0x00010000
872 #define A4XX_INT0_CP_RB_DONE_TS					0x00020000
873 #define A4XX_INT0_CP_VS_DONE_TS					0x00040000
874 #define A4XX_INT0_CP_PS_DONE_TS					0x00080000
875 #define A4XX_INT0_CACHE_FLUSH_TS				0x00100000
876 #define A4XX_INT0_CP_AHB_ERROR_HALT				0x00200000
877 #define A4XX_INT0_MISC_HANG_DETECT				0x01000000
878 #define A4XX_INT0_UCHE_OOB_ACCESS				0x02000000
879 #define REG_A4XX_RB_GMEM_BASE_ADDR				0x00000cc0
880 
881 #define REG_A4XX_RB_PERFCTR_RB_SEL_0				0x00000cc7
882 
883 #define REG_A4XX_RB_PERFCTR_RB_SEL_1				0x00000cc8
884 
885 #define REG_A4XX_RB_PERFCTR_RB_SEL_2				0x00000cc9
886 
887 #define REG_A4XX_RB_PERFCTR_RB_SEL_3				0x00000cca
888 
889 #define REG_A4XX_RB_PERFCTR_RB_SEL_4				0x00000ccb
890 
891 #define REG_A4XX_RB_PERFCTR_RB_SEL_5				0x00000ccc
892 
893 #define REG_A4XX_RB_PERFCTR_RB_SEL_6				0x00000ccd
894 
895 #define REG_A4XX_RB_PERFCTR_RB_SEL_7				0x00000cce
896 
897 #define REG_A4XX_RB_PERFCTR_CCU_SEL_0				0x00000ccf
898 
899 #define REG_A4XX_RB_PERFCTR_CCU_SEL_1				0x00000cd0
900 
901 #define REG_A4XX_RB_PERFCTR_CCU_SEL_2				0x00000cd1
902 
903 #define REG_A4XX_RB_PERFCTR_CCU_SEL_3				0x00000cd2
904 
905 #define REG_A4XX_RB_FRAME_BUFFER_DIMENSION			0x00000ce0
906 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK		0x00003fff
907 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT		0
908 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val)
909 {
910 	return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK;
911 }
912 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK		0x3fff0000
913 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT		16
914 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val)
915 {
916 	return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK;
917 }
918 
919 #define REG_A4XX_RB_CLEAR_COLOR_DW0				0x000020cc
920 
921 #define REG_A4XX_RB_CLEAR_COLOR_DW1				0x000020cd
922 
923 #define REG_A4XX_RB_CLEAR_COLOR_DW2				0x000020ce
924 
925 #define REG_A4XX_RB_CLEAR_COLOR_DW3				0x000020cf
926 
927 #define REG_A4XX_RB_MODE_CONTROL				0x000020a0
928 #define A4XX_RB_MODE_CONTROL_WIDTH__MASK			0x0000003f
929 #define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT			0
930 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val)
931 {
932 	return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK;
933 }
934 #define A4XX_RB_MODE_CONTROL_HEIGHT__MASK			0x00003f00
935 #define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT			8
936 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val)
937 {
938 	return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK;
939 }
940 #define A4XX_RB_MODE_CONTROL_ENABLE_GMEM			0x00010000
941 
942 #define REG_A4XX_RB_RENDER_CONTROL				0x000020a1
943 #define A4XX_RB_RENDER_CONTROL_BINNING_PASS			0x00000001
944 #define A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE		0x00000020
945 
946 #define REG_A4XX_RB_MSAA_CONTROL				0x000020a2
947 #define A4XX_RB_MSAA_CONTROL_DISABLE				0x00001000
948 #define A4XX_RB_MSAA_CONTROL_SAMPLES__MASK			0x0000e000
949 #define A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT			13
950 static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val)
951 {
952 	return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK;
953 }
954 
955 #define REG_A4XX_RB_RENDER_CONTROL2				0x000020a3
956 #define A4XX_RB_RENDER_CONTROL2_XCOORD				0x00000001
957 #define A4XX_RB_RENDER_CONTROL2_YCOORD				0x00000002
958 #define A4XX_RB_RENDER_CONTROL2_ZCOORD				0x00000004
959 #define A4XX_RB_RENDER_CONTROL2_WCOORD				0x00000008
960 #define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK			0x00000010
961 #define A4XX_RB_RENDER_CONTROL2_FACENESS			0x00000020
962 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID			0x00000040
963 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK		0x00000380
964 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT		7
965 static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val)
966 {
967 	return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK;
968 }
969 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR			0x00000800
970 #define A4XX_RB_RENDER_CONTROL2_VARYING				0x00001000
971 
972 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
973 
974 static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
975 #define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE			0x00000008
976 #define A4XX_RB_MRT_CONTROL_BLEND				0x00000010
977 #define A4XX_RB_MRT_CONTROL_BLEND2				0x00000020
978 #define A4XX_RB_MRT_CONTROL_ROP_ENABLE				0x00000040
979 #define A4XX_RB_MRT_CONTROL_ROP_CODE__MASK			0x00000f00
980 #define A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT			8
981 static inline uint32_t A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
982 {
983 	return ((val) << A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A4XX_RB_MRT_CONTROL_ROP_CODE__MASK;
984 }
985 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK		0x0f000000
986 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT		24
987 static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
988 {
989 	return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
990 }
991 
992 static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; }
993 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK			0x0000003f
994 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT		0
995 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val)
996 {
997 	return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
998 }
999 #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK		0x000000c0
1000 #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT		6
1001 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val)
1002 {
1003 	return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
1004 }
1005 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK			0x00000600
1006 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT			9
1007 static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
1008 {
1009 	return ((val) << A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK;
1010 }
1011 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK			0x00001800
1012 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT			11
1013 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
1014 {
1015 	return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
1016 }
1017 #define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB				0x00002000
1018 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK		0xffffc000
1019 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT		14
1020 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
1021 {
1022 	return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;
1023 }
1024 
1025 static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; }
1026 
1027 static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; }
1028 #define A4XX_RB_MRT_CONTROL3_STRIDE__MASK			0x03fffff8
1029 #define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT			3
1030 static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val)
1031 {
1032 	return ((val) << A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT) & A4XX_RB_MRT_CONTROL3_STRIDE__MASK;
1033 }
1034 
1035 static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; }
1036 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK		0x0000001f
1037 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT		0
1038 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
1039 {
1040 	return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
1041 }
1042 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK	0x000000e0
1043 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT	5
1044 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
1045 {
1046 	return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
1047 }
1048 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK		0x00001f00
1049 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT	8
1050 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
1051 {
1052 	return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
1053 }
1054 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK	0x001f0000
1055 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT	16
1056 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
1057 {
1058 	return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
1059 }
1060 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK	0x00e00000
1061 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT	21
1062 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
1063 {
1064 	return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
1065 }
1066 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK	0x1f000000
1067 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT	24
1068 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
1069 {
1070 	return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
1071 }
1072 
1073 #define REG_A4XX_RB_BLEND_RED					0x000020f0
1074 #define A4XX_RB_BLEND_RED_UINT__MASK				0x000000ff
1075 #define A4XX_RB_BLEND_RED_UINT__SHIFT				0
1076 static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val)
1077 {
1078 	return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK;
1079 }
1080 #define A4XX_RB_BLEND_RED_SINT__MASK				0x0000ff00
1081 #define A4XX_RB_BLEND_RED_SINT__SHIFT				8
1082 static inline uint32_t A4XX_RB_BLEND_RED_SINT(uint32_t val)
1083 {
1084 	return ((val) << A4XX_RB_BLEND_RED_SINT__SHIFT) & A4XX_RB_BLEND_RED_SINT__MASK;
1085 }
1086 #define A4XX_RB_BLEND_RED_FLOAT__MASK				0xffff0000
1087 #define A4XX_RB_BLEND_RED_FLOAT__SHIFT				16
1088 static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)
1089 {
1090 	return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;
1091 }
1092 
1093 #define REG_A4XX_RB_BLEND_RED_F32				0x000020f1
1094 #define A4XX_RB_BLEND_RED_F32__MASK				0xffffffff
1095 #define A4XX_RB_BLEND_RED_F32__SHIFT				0
1096 static inline uint32_t A4XX_RB_BLEND_RED_F32(float val)
1097 {
1098 	return ((fui(val)) << A4XX_RB_BLEND_RED_F32__SHIFT) & A4XX_RB_BLEND_RED_F32__MASK;
1099 }
1100 
1101 #define REG_A4XX_RB_BLEND_GREEN					0x000020f2
1102 #define A4XX_RB_BLEND_GREEN_UINT__MASK				0x000000ff
1103 #define A4XX_RB_BLEND_GREEN_UINT__SHIFT				0
1104 static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val)
1105 {
1106 	return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK;
1107 }
1108 #define A4XX_RB_BLEND_GREEN_SINT__MASK				0x0000ff00
1109 #define A4XX_RB_BLEND_GREEN_SINT__SHIFT				8
1110 static inline uint32_t A4XX_RB_BLEND_GREEN_SINT(uint32_t val)
1111 {
1112 	return ((val) << A4XX_RB_BLEND_GREEN_SINT__SHIFT) & A4XX_RB_BLEND_GREEN_SINT__MASK;
1113 }
1114 #define A4XX_RB_BLEND_GREEN_FLOAT__MASK				0xffff0000
1115 #define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT			16
1116 static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)
1117 {
1118 	return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;
1119 }
1120 
1121 #define REG_A4XX_RB_BLEND_GREEN_F32				0x000020f3
1122 #define A4XX_RB_BLEND_GREEN_F32__MASK				0xffffffff
1123 #define A4XX_RB_BLEND_GREEN_F32__SHIFT				0
1124 static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val)
1125 {
1126 	return ((fui(val)) << A4XX_RB_BLEND_GREEN_F32__SHIFT) & A4XX_RB_BLEND_GREEN_F32__MASK;
1127 }
1128 
1129 #define REG_A4XX_RB_BLEND_BLUE					0x000020f4
1130 #define A4XX_RB_BLEND_BLUE_UINT__MASK				0x000000ff
1131 #define A4XX_RB_BLEND_BLUE_UINT__SHIFT				0
1132 static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val)
1133 {
1134 	return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK;
1135 }
1136 #define A4XX_RB_BLEND_BLUE_SINT__MASK				0x0000ff00
1137 #define A4XX_RB_BLEND_BLUE_SINT__SHIFT				8
1138 static inline uint32_t A4XX_RB_BLEND_BLUE_SINT(uint32_t val)
1139 {
1140 	return ((val) << A4XX_RB_BLEND_BLUE_SINT__SHIFT) & A4XX_RB_BLEND_BLUE_SINT__MASK;
1141 }
1142 #define A4XX_RB_BLEND_BLUE_FLOAT__MASK				0xffff0000
1143 #define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT				16
1144 static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)
1145 {
1146 	return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;
1147 }
1148 
1149 #define REG_A4XX_RB_BLEND_BLUE_F32				0x000020f5
1150 #define A4XX_RB_BLEND_BLUE_F32__MASK				0xffffffff
1151 #define A4XX_RB_BLEND_BLUE_F32__SHIFT				0
1152 static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val)
1153 {
1154 	return ((fui(val)) << A4XX_RB_BLEND_BLUE_F32__SHIFT) & A4XX_RB_BLEND_BLUE_F32__MASK;
1155 }
1156 
1157 #define REG_A4XX_RB_BLEND_ALPHA					0x000020f6
1158 #define A4XX_RB_BLEND_ALPHA_UINT__MASK				0x000000ff
1159 #define A4XX_RB_BLEND_ALPHA_UINT__SHIFT				0
1160 static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val)
1161 {
1162 	return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK;
1163 }
1164 #define A4XX_RB_BLEND_ALPHA_SINT__MASK				0x0000ff00
1165 #define A4XX_RB_BLEND_ALPHA_SINT__SHIFT				8
1166 static inline uint32_t A4XX_RB_BLEND_ALPHA_SINT(uint32_t val)
1167 {
1168 	return ((val) << A4XX_RB_BLEND_ALPHA_SINT__SHIFT) & A4XX_RB_BLEND_ALPHA_SINT__MASK;
1169 }
1170 #define A4XX_RB_BLEND_ALPHA_FLOAT__MASK				0xffff0000
1171 #define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT			16
1172 static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)
1173 {
1174 	return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;
1175 }
1176 
1177 #define REG_A4XX_RB_BLEND_ALPHA_F32				0x000020f7
1178 #define A4XX_RB_BLEND_ALPHA_F32__MASK				0xffffffff
1179 #define A4XX_RB_BLEND_ALPHA_F32__SHIFT				0
1180 static inline uint32_t A4XX_RB_BLEND_ALPHA_F32(float val)
1181 {
1182 	return ((fui(val)) << A4XX_RB_BLEND_ALPHA_F32__SHIFT) & A4XX_RB_BLEND_ALPHA_F32__MASK;
1183 }
1184 
1185 #define REG_A4XX_RB_ALPHA_CONTROL				0x000020f8
1186 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK			0x000000ff
1187 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT			0
1188 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
1189 {
1190 	return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
1191 }
1192 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST			0x00000100
1193 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK		0x00000e00
1194 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT		9
1195 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
1196 {
1197 	return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
1198 }
1199 
1200 #define REG_A4XX_RB_FS_OUTPUT					0x000020f9
1201 #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK			0x000000ff
1202 #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT			0
1203 static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val)
1204 {
1205 	return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK;
1206 }
1207 #define A4XX_RB_FS_OUTPUT_INDEPENDENT_BLEND			0x00000100
1208 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK			0xffff0000
1209 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT			16
1210 static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val)
1211 {
1212 	return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK;
1213 }
1214 
1215 #define REG_A4XX_RB_SAMPLE_COUNT_CONTROL			0x000020fa
1216 #define A4XX_RB_SAMPLE_COUNT_CONTROL_COPY			0x00000002
1217 #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK			0xfffffffc
1218 #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT		2
1219 static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val)
1220 {
1221 	return ((val >> 2) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK;
1222 }
1223 
1224 #define REG_A4XX_RB_RENDER_COMPONENTS				0x000020fb
1225 #define A4XX_RB_RENDER_COMPONENTS_RT0__MASK			0x0000000f
1226 #define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT			0
1227 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
1228 {
1229 	return ((val) << A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT0__MASK;
1230 }
1231 #define A4XX_RB_RENDER_COMPONENTS_RT1__MASK			0x000000f0
1232 #define A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT			4
1233 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
1234 {
1235 	return ((val) << A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT1__MASK;
1236 }
1237 #define A4XX_RB_RENDER_COMPONENTS_RT2__MASK			0x00000f00
1238 #define A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT			8
1239 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
1240 {
1241 	return ((val) << A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT2__MASK;
1242 }
1243 #define A4XX_RB_RENDER_COMPONENTS_RT3__MASK			0x0000f000
1244 #define A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT			12
1245 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
1246 {
1247 	return ((val) << A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT3__MASK;
1248 }
1249 #define A4XX_RB_RENDER_COMPONENTS_RT4__MASK			0x000f0000
1250 #define A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT			16
1251 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
1252 {
1253 	return ((val) << A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT4__MASK;
1254 }
1255 #define A4XX_RB_RENDER_COMPONENTS_RT5__MASK			0x00f00000
1256 #define A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT			20
1257 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
1258 {
1259 	return ((val) << A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT5__MASK;
1260 }
1261 #define A4XX_RB_RENDER_COMPONENTS_RT6__MASK			0x0f000000
1262 #define A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT			24
1263 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
1264 {
1265 	return ((val) << A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT6__MASK;
1266 }
1267 #define A4XX_RB_RENDER_COMPONENTS_RT7__MASK			0xf0000000
1268 #define A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT			28
1269 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
1270 {
1271 	return ((val) << A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT7__MASK;
1272 }
1273 
1274 #define REG_A4XX_RB_COPY_CONTROL				0x000020fc
1275 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK			0x00000003
1276 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT		0
1277 static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val)
1278 {
1279 	return ((val) << A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK;
1280 }
1281 #define A4XX_RB_COPY_CONTROL_MODE__MASK				0x00000070
1282 #define A4XX_RB_COPY_CONTROL_MODE__SHIFT			4
1283 static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val)
1284 {
1285 	return ((val) << A4XX_RB_COPY_CONTROL_MODE__SHIFT) & A4XX_RB_COPY_CONTROL_MODE__MASK;
1286 }
1287 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK			0x00000f00
1288 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT			8
1289 static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)
1290 {
1291 	return ((val) << A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK;
1292 }
1293 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK			0xffffc000
1294 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT			14
1295 static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
1296 {
1297 	return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK;
1298 }
1299 
1300 #define REG_A4XX_RB_COPY_DEST_BASE				0x000020fd
1301 #define A4XX_RB_COPY_DEST_BASE_BASE__MASK			0xffffffe0
1302 #define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT			5
1303 static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val)
1304 {
1305 	return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK;
1306 }
1307 
1308 #define REG_A4XX_RB_COPY_DEST_PITCH				0x000020fe
1309 #define A4XX_RB_COPY_DEST_PITCH_PITCH__MASK			0xffffffff
1310 #define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT			0
1311 static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val)
1312 {
1313 	return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK;
1314 }
1315 
1316 #define REG_A4XX_RB_COPY_DEST_INFO				0x000020ff
1317 #define A4XX_RB_COPY_DEST_INFO_FORMAT__MASK			0x000000fc
1318 #define A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT			2
1319 static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val)
1320 {
1321 	return ((val) << A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A4XX_RB_COPY_DEST_INFO_FORMAT__MASK;
1322 }
1323 #define A4XX_RB_COPY_DEST_INFO_SWAP__MASK			0x00000300
1324 #define A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT			8
1325 static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val)
1326 {
1327 	return ((val) << A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A4XX_RB_COPY_DEST_INFO_SWAP__MASK;
1328 }
1329 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK		0x00000c00
1330 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT		10
1331 static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
1332 {
1333 	return ((val) << A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
1334 }
1335 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK		0x0003c000
1336 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT		14
1337 static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val)
1338 {
1339 	return ((val) << A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK;
1340 }
1341 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK			0x001c0000
1342 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT			18
1343 static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val)
1344 {
1345 	return ((val) << A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK;
1346 }
1347 #define A4XX_RB_COPY_DEST_INFO_TILE__MASK			0x03000000
1348 #define A4XX_RB_COPY_DEST_INFO_TILE__SHIFT			24
1349 static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val)
1350 {
1351 	return ((val) << A4XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A4XX_RB_COPY_DEST_INFO_TILE__MASK;
1352 }
1353 
1354 #define REG_A4XX_RB_FS_OUTPUT_REG				0x00002100
1355 #define A4XX_RB_FS_OUTPUT_REG_MRT__MASK				0x0000000f
1356 #define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT			0
1357 static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val)
1358 {
1359 	return ((val) << A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_RB_FS_OUTPUT_REG_MRT__MASK;
1360 }
1361 #define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z			0x00000020
1362 
1363 #define REG_A4XX_RB_DEPTH_CONTROL				0x00002101
1364 #define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z			0x00000001
1365 #define A4XX_RB_DEPTH_CONTROL_Z_ENABLE				0x00000002
1366 #define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE			0x00000004
1367 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK			0x00000070
1368 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT			4
1369 static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
1370 {
1371 	return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK;
1372 }
1373 #define A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE			0x00000080
1374 #define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE			0x00010000
1375 #define A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS			0x00020000
1376 #define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE			0x80000000
1377 
1378 #define REG_A4XX_RB_DEPTH_CLEAR					0x00002102
1379 
1380 #define REG_A4XX_RB_DEPTH_INFO					0x00002103
1381 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK			0x00000003
1382 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT			0
1383 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val)
1384 {
1385 	return ((val) << A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
1386 }
1387 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK			0xfffff000
1388 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT			12
1389 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
1390 {
1391 	return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
1392 }
1393 
1394 #define REG_A4XX_RB_DEPTH_PITCH					0x00002104
1395 #define A4XX_RB_DEPTH_PITCH__MASK				0xffffffff
1396 #define A4XX_RB_DEPTH_PITCH__SHIFT				0
1397 static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val)
1398 {
1399 	return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK;
1400 }
1401 
1402 #define REG_A4XX_RB_DEPTH_PITCH2				0x00002105
1403 #define A4XX_RB_DEPTH_PITCH2__MASK				0xffffffff
1404 #define A4XX_RB_DEPTH_PITCH2__SHIFT				0
1405 static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val)
1406 {
1407 	return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK;
1408 }
1409 
1410 #define REG_A4XX_RB_STENCIL_CONTROL				0x00002106
1411 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE			0x00000001
1412 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF		0x00000002
1413 #define A4XX_RB_STENCIL_CONTROL_STENCIL_READ			0x00000004
1414 #define A4XX_RB_STENCIL_CONTROL_FUNC__MASK			0x00000700
1415 #define A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT			8
1416 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
1417 {
1418 	return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC__MASK;
1419 }
1420 #define A4XX_RB_STENCIL_CONTROL_FAIL__MASK			0x00003800
1421 #define A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT			11
1422 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
1423 {
1424 	return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL__MASK;
1425 }
1426 #define A4XX_RB_STENCIL_CONTROL_ZPASS__MASK			0x0001c000
1427 #define A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT			14
1428 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
1429 {
1430 	return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS__MASK;
1431 }
1432 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK			0x000e0000
1433 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT			17
1434 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
1435 {
1436 	return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
1437 }
1438 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK			0x00700000
1439 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT			20
1440 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
1441 {
1442 	return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
1443 }
1444 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK			0x03800000
1445 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT			23
1446 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
1447 {
1448 	return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
1449 }
1450 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK			0x1c000000
1451 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT			26
1452 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
1453 {
1454 	return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
1455 }
1456 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK			0xe0000000
1457 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT			29
1458 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
1459 {
1460 	return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
1461 }
1462 
1463 #define REG_A4XX_RB_STENCIL_CONTROL2				0x00002107
1464 #define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER			0x00000001
1465 
1466 #define REG_A4XX_RB_STENCIL_INFO				0x00002108
1467 #define A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL			0x00000001
1468 #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK			0xfffff000
1469 #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT		12
1470 static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
1471 {
1472 	return ((val >> 12) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;
1473 }
1474 
1475 #define REG_A4XX_RB_STENCIL_PITCH				0x00002109
1476 #define A4XX_RB_STENCIL_PITCH__MASK				0xffffffff
1477 #define A4XX_RB_STENCIL_PITCH__SHIFT				0
1478 static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val)
1479 {
1480 	return ((val >> 5) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK;
1481 }
1482 
1483 #define REG_A4XX_RB_STENCILREFMASK				0x0000210b
1484 #define A4XX_RB_STENCILREFMASK_STENCILREF__MASK			0x000000ff
1485 #define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT		0
1486 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
1487 {
1488 	return ((val) << A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILREF__MASK;
1489 }
1490 #define A4XX_RB_STENCILREFMASK_STENCILMASK__MASK		0x0000ff00
1491 #define A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT		8
1492 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
1493 {
1494 	return ((val) << A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILMASK__MASK;
1495 }
1496 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK		0x00ff0000
1497 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT		16
1498 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
1499 {
1500 	return ((val) << A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
1501 }
1502 
1503 #define REG_A4XX_RB_STENCILREFMASK_BF				0x0000210c
1504 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK		0x000000ff
1505 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT		0
1506 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
1507 {
1508 	return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
1509 }
1510 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK		0x0000ff00
1511 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT		8
1512 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
1513 {
1514 	return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
1515 }
1516 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK	0x00ff0000
1517 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT	16
1518 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
1519 {
1520 	return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
1521 }
1522 
1523 #define REG_A4XX_RB_BIN_OFFSET					0x0000210d
1524 #define A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE		0x80000000
1525 #define A4XX_RB_BIN_OFFSET_X__MASK				0x00007fff
1526 #define A4XX_RB_BIN_OFFSET_X__SHIFT				0
1527 static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val)
1528 {
1529 	return ((val) << A4XX_RB_BIN_OFFSET_X__SHIFT) & A4XX_RB_BIN_OFFSET_X__MASK;
1530 }
1531 #define A4XX_RB_BIN_OFFSET_Y__MASK				0x7fff0000
1532 #define A4XX_RB_BIN_OFFSET_Y__SHIFT				16
1533 static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val)
1534 {
1535 	return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK;
1536 }
1537 
1538 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; }
1539 
1540 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; }
1541 
1542 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; }
1543 
1544 #define REG_A4XX_RBBM_HW_VERSION				0x00000000
1545 
1546 #define REG_A4XX_RBBM_HW_CONFIGURATION				0x00000002
1547 
1548 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; }
1549 
1550 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; }
1551 
1552 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; }
1553 
1554 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; }
1555 
1556 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; }
1557 
1558 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; }
1559 
1560 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; }
1561 
1562 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; }
1563 
1564 #define REG_A4XX_RBBM_CLOCK_CTL_UCHE 				0x00000014
1565 
1566 #define REG_A4XX_RBBM_CLOCK_CTL2_UCHE				0x00000015
1567 
1568 #define REG_A4XX_RBBM_CLOCK_CTL3_UCHE				0x00000016
1569 
1570 #define REG_A4XX_RBBM_CLOCK_CTL4_UCHE				0x00000017
1571 
1572 #define REG_A4XX_RBBM_CLOCK_HYST_UCHE				0x00000018
1573 
1574 #define REG_A4XX_RBBM_CLOCK_DELAY_UCHE				0x00000019
1575 
1576 #define REG_A4XX_RBBM_CLOCK_MODE_GPC				0x0000001a
1577 
1578 #define REG_A4XX_RBBM_CLOCK_DELAY_GPC				0x0000001b
1579 
1580 #define REG_A4XX_RBBM_CLOCK_HYST_GPC				0x0000001c
1581 
1582 #define REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM			0x0000001d
1583 
1584 #define REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM			0x0000001e
1585 
1586 #define REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM			0x0000001f
1587 
1588 #define REG_A4XX_RBBM_CLOCK_CTL					0x00000020
1589 
1590 #define REG_A4XX_RBBM_SP_HYST_CNT				0x00000021
1591 
1592 #define REG_A4XX_RBBM_SW_RESET_CMD				0x00000022
1593 
1594 #define REG_A4XX_RBBM_AHB_CTL0					0x00000023
1595 
1596 #define REG_A4XX_RBBM_AHB_CTL1					0x00000024
1597 
1598 #define REG_A4XX_RBBM_AHB_CMD					0x00000025
1599 
1600 #define REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL			0x00000026
1601 
1602 #define REG_A4XX_RBBM_RAM_ACC_63_32				0x00000028
1603 
1604 #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL			0x0000002b
1605 
1606 #define REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL			0x0000002f
1607 
1608 #define REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4			0x00000034
1609 
1610 #define REG_A4XX_RBBM_INT_CLEAR_CMD				0x00000036
1611 
1612 #define REG_A4XX_RBBM_INT_0_MASK				0x00000037
1613 
1614 #define REG_A4XX_RBBM_RBBM_CTL					0x0000003e
1615 
1616 #define REG_A4XX_RBBM_AHB_DEBUG_CTL				0x0000003f
1617 
1618 #define REG_A4XX_RBBM_VBIF_DEBUG_CTL				0x00000041
1619 
1620 #define REG_A4XX_RBBM_CLOCK_CTL2				0x00000042
1621 
1622 #define REG_A4XX_RBBM_BLOCK_SW_RESET_CMD			0x00000045
1623 
1624 #define REG_A4XX_RBBM_RESET_CYCLES				0x00000047
1625 
1626 #define REG_A4XX_RBBM_EXT_TRACE_BUS_CTL				0x00000049
1627 
1628 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A				0x0000004a
1629 
1630 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B				0x0000004b
1631 
1632 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C				0x0000004c
1633 
1634 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D				0x0000004d
1635 
1636 #define REG_A4XX_RBBM_POWER_CNTL_IP				0x00000098
1637 #define A4XX_RBBM_POWER_CNTL_IP_SW_COLLAPSE			0x00000001
1638 #define A4XX_RBBM_POWER_CNTL_IP_SP_TP_PWR_ON			0x00100000
1639 
1640 #define REG_A4XX_RBBM_PERFCTR_CP_0_LO				0x0000009c
1641 
1642 #define REG_A4XX_RBBM_PERFCTR_CP_0_HI				0x0000009d
1643 
1644 #define REG_A4XX_RBBM_PERFCTR_CP_1_LO				0x0000009e
1645 
1646 #define REG_A4XX_RBBM_PERFCTR_CP_1_HI				0x0000009f
1647 
1648 #define REG_A4XX_RBBM_PERFCTR_CP_2_LO				0x000000a0
1649 
1650 #define REG_A4XX_RBBM_PERFCTR_CP_2_HI				0x000000a1
1651 
1652 #define REG_A4XX_RBBM_PERFCTR_CP_3_LO				0x000000a2
1653 
1654 #define REG_A4XX_RBBM_PERFCTR_CP_3_HI				0x000000a3
1655 
1656 #define REG_A4XX_RBBM_PERFCTR_CP_4_LO				0x000000a4
1657 
1658 #define REG_A4XX_RBBM_PERFCTR_CP_4_HI				0x000000a5
1659 
1660 #define REG_A4XX_RBBM_PERFCTR_CP_5_LO				0x000000a6
1661 
1662 #define REG_A4XX_RBBM_PERFCTR_CP_5_HI				0x000000a7
1663 
1664 #define REG_A4XX_RBBM_PERFCTR_CP_6_LO				0x000000a8
1665 
1666 #define REG_A4XX_RBBM_PERFCTR_CP_6_HI				0x000000a9
1667 
1668 #define REG_A4XX_RBBM_PERFCTR_CP_7_LO				0x000000aa
1669 
1670 #define REG_A4XX_RBBM_PERFCTR_CP_7_HI				0x000000ab
1671 
1672 #define REG_A4XX_RBBM_PERFCTR_RBBM_0_LO				0x000000ac
1673 
1674 #define REG_A4XX_RBBM_PERFCTR_RBBM_0_HI				0x000000ad
1675 
1676 #define REG_A4XX_RBBM_PERFCTR_RBBM_1_LO				0x000000ae
1677 
1678 #define REG_A4XX_RBBM_PERFCTR_RBBM_1_HI				0x000000af
1679 
1680 #define REG_A4XX_RBBM_PERFCTR_RBBM_2_LO				0x000000b0
1681 
1682 #define REG_A4XX_RBBM_PERFCTR_RBBM_2_HI				0x000000b1
1683 
1684 #define REG_A4XX_RBBM_PERFCTR_RBBM_3_LO				0x000000b2
1685 
1686 #define REG_A4XX_RBBM_PERFCTR_RBBM_3_HI				0x000000b3
1687 
1688 #define REG_A4XX_RBBM_PERFCTR_PC_0_LO				0x000000b4
1689 
1690 #define REG_A4XX_RBBM_PERFCTR_PC_0_HI				0x000000b5
1691 
1692 #define REG_A4XX_RBBM_PERFCTR_PC_1_LO				0x000000b6
1693 
1694 #define REG_A4XX_RBBM_PERFCTR_PC_1_HI				0x000000b7
1695 
1696 #define REG_A4XX_RBBM_PERFCTR_PC_2_LO				0x000000b8
1697 
1698 #define REG_A4XX_RBBM_PERFCTR_PC_2_HI				0x000000b9
1699 
1700 #define REG_A4XX_RBBM_PERFCTR_PC_3_LO				0x000000ba
1701 
1702 #define REG_A4XX_RBBM_PERFCTR_PC_3_HI				0x000000bb
1703 
1704 #define REG_A4XX_RBBM_PERFCTR_PC_4_LO				0x000000bc
1705 
1706 #define REG_A4XX_RBBM_PERFCTR_PC_4_HI				0x000000bd
1707 
1708 #define REG_A4XX_RBBM_PERFCTR_PC_5_LO				0x000000be
1709 
1710 #define REG_A4XX_RBBM_PERFCTR_PC_5_HI				0x000000bf
1711 
1712 #define REG_A4XX_RBBM_PERFCTR_PC_6_LO				0x000000c0
1713 
1714 #define REG_A4XX_RBBM_PERFCTR_PC_6_HI				0x000000c1
1715 
1716 #define REG_A4XX_RBBM_PERFCTR_PC_7_LO				0x000000c2
1717 
1718 #define REG_A4XX_RBBM_PERFCTR_PC_7_HI				0x000000c3
1719 
1720 #define REG_A4XX_RBBM_PERFCTR_VFD_0_LO				0x000000c4
1721 
1722 #define REG_A4XX_RBBM_PERFCTR_VFD_0_HI				0x000000c5
1723 
1724 #define REG_A4XX_RBBM_PERFCTR_VFD_1_LO				0x000000c6
1725 
1726 #define REG_A4XX_RBBM_PERFCTR_VFD_1_HI				0x000000c7
1727 
1728 #define REG_A4XX_RBBM_PERFCTR_VFD_2_LO				0x000000c8
1729 
1730 #define REG_A4XX_RBBM_PERFCTR_VFD_2_HI				0x000000c9
1731 
1732 #define REG_A4XX_RBBM_PERFCTR_VFD_3_LO				0x000000ca
1733 
1734 #define REG_A4XX_RBBM_PERFCTR_VFD_3_HI				0x000000cb
1735 
1736 #define REG_A4XX_RBBM_PERFCTR_VFD_4_LO				0x000000cc
1737 
1738 #define REG_A4XX_RBBM_PERFCTR_VFD_4_HI				0x000000cd
1739 
1740 #define REG_A4XX_RBBM_PERFCTR_VFD_5_LO				0x000000ce
1741 
1742 #define REG_A4XX_RBBM_PERFCTR_VFD_5_HI				0x000000cf
1743 
1744 #define REG_A4XX_RBBM_PERFCTR_VFD_6_LO				0x000000d0
1745 
1746 #define REG_A4XX_RBBM_PERFCTR_VFD_6_HI				0x000000d1
1747 
1748 #define REG_A4XX_RBBM_PERFCTR_VFD_7_LO				0x000000d2
1749 
1750 #define REG_A4XX_RBBM_PERFCTR_VFD_7_HI				0x000000d3
1751 
1752 #define REG_A4XX_RBBM_PERFCTR_HLSQ_0_LO				0x000000d4
1753 
1754 #define REG_A4XX_RBBM_PERFCTR_HLSQ_0_HI				0x000000d5
1755 
1756 #define REG_A4XX_RBBM_PERFCTR_HLSQ_1_LO				0x000000d6
1757 
1758 #define REG_A4XX_RBBM_PERFCTR_HLSQ_1_HI				0x000000d7
1759 
1760 #define REG_A4XX_RBBM_PERFCTR_HLSQ_2_LO				0x000000d8
1761 
1762 #define REG_A4XX_RBBM_PERFCTR_HLSQ_2_HI				0x000000d9
1763 
1764 #define REG_A4XX_RBBM_PERFCTR_HLSQ_3_LO				0x000000da
1765 
1766 #define REG_A4XX_RBBM_PERFCTR_HLSQ_3_HI				0x000000db
1767 
1768 #define REG_A4XX_RBBM_PERFCTR_HLSQ_4_LO				0x000000dc
1769 
1770 #define REG_A4XX_RBBM_PERFCTR_HLSQ_4_HI				0x000000dd
1771 
1772 #define REG_A4XX_RBBM_PERFCTR_HLSQ_5_LO				0x000000de
1773 
1774 #define REG_A4XX_RBBM_PERFCTR_HLSQ_5_HI				0x000000df
1775 
1776 #define REG_A4XX_RBBM_PERFCTR_HLSQ_6_LO				0x000000e0
1777 
1778 #define REG_A4XX_RBBM_PERFCTR_HLSQ_6_HI				0x000000e1
1779 
1780 #define REG_A4XX_RBBM_PERFCTR_HLSQ_7_LO				0x000000e2
1781 
1782 #define REG_A4XX_RBBM_PERFCTR_HLSQ_7_HI				0x000000e3
1783 
1784 #define REG_A4XX_RBBM_PERFCTR_VPC_0_LO				0x000000e4
1785 
1786 #define REG_A4XX_RBBM_PERFCTR_VPC_0_HI				0x000000e5
1787 
1788 #define REG_A4XX_RBBM_PERFCTR_VPC_1_LO				0x000000e6
1789 
1790 #define REG_A4XX_RBBM_PERFCTR_VPC_1_HI				0x000000e7
1791 
1792 #define REG_A4XX_RBBM_PERFCTR_VPC_2_LO				0x000000e8
1793 
1794 #define REG_A4XX_RBBM_PERFCTR_VPC_2_HI				0x000000e9
1795 
1796 #define REG_A4XX_RBBM_PERFCTR_VPC_3_LO				0x000000ea
1797 
1798 #define REG_A4XX_RBBM_PERFCTR_VPC_3_HI				0x000000eb
1799 
1800 #define REG_A4XX_RBBM_PERFCTR_CCU_0_LO				0x000000ec
1801 
1802 #define REG_A4XX_RBBM_PERFCTR_CCU_0_HI				0x000000ed
1803 
1804 #define REG_A4XX_RBBM_PERFCTR_CCU_1_LO				0x000000ee
1805 
1806 #define REG_A4XX_RBBM_PERFCTR_CCU_1_HI				0x000000ef
1807 
1808 #define REG_A4XX_RBBM_PERFCTR_CCU_2_LO				0x000000f0
1809 
1810 #define REG_A4XX_RBBM_PERFCTR_CCU_2_HI				0x000000f1
1811 
1812 #define REG_A4XX_RBBM_PERFCTR_CCU_3_LO				0x000000f2
1813 
1814 #define REG_A4XX_RBBM_PERFCTR_CCU_3_HI				0x000000f3
1815 
1816 #define REG_A4XX_RBBM_PERFCTR_TSE_0_LO				0x000000f4
1817 
1818 #define REG_A4XX_RBBM_PERFCTR_TSE_0_HI				0x000000f5
1819 
1820 #define REG_A4XX_RBBM_PERFCTR_TSE_1_LO				0x000000f6
1821 
1822 #define REG_A4XX_RBBM_PERFCTR_TSE_1_HI				0x000000f7
1823 
1824 #define REG_A4XX_RBBM_PERFCTR_TSE_2_LO				0x000000f8
1825 
1826 #define REG_A4XX_RBBM_PERFCTR_TSE_2_HI				0x000000f9
1827 
1828 #define REG_A4XX_RBBM_PERFCTR_TSE_3_LO				0x000000fa
1829 
1830 #define REG_A4XX_RBBM_PERFCTR_TSE_3_HI				0x000000fb
1831 
1832 #define REG_A4XX_RBBM_PERFCTR_RAS_0_LO				0x000000fc
1833 
1834 #define REG_A4XX_RBBM_PERFCTR_RAS_0_HI				0x000000fd
1835 
1836 #define REG_A4XX_RBBM_PERFCTR_RAS_1_LO				0x000000fe
1837 
1838 #define REG_A4XX_RBBM_PERFCTR_RAS_1_HI				0x000000ff
1839 
1840 #define REG_A4XX_RBBM_PERFCTR_RAS_2_LO				0x00000100
1841 
1842 #define REG_A4XX_RBBM_PERFCTR_RAS_2_HI				0x00000101
1843 
1844 #define REG_A4XX_RBBM_PERFCTR_RAS_3_LO				0x00000102
1845 
1846 #define REG_A4XX_RBBM_PERFCTR_RAS_3_HI				0x00000103
1847 
1848 #define REG_A4XX_RBBM_PERFCTR_UCHE_0_LO				0x00000104
1849 
1850 #define REG_A4XX_RBBM_PERFCTR_UCHE_0_HI				0x00000105
1851 
1852 #define REG_A4XX_RBBM_PERFCTR_UCHE_1_LO				0x00000106
1853 
1854 #define REG_A4XX_RBBM_PERFCTR_UCHE_1_HI				0x00000107
1855 
1856 #define REG_A4XX_RBBM_PERFCTR_UCHE_2_LO				0x00000108
1857 
1858 #define REG_A4XX_RBBM_PERFCTR_UCHE_2_HI				0x00000109
1859 
1860 #define REG_A4XX_RBBM_PERFCTR_UCHE_3_LO				0x0000010a
1861 
1862 #define REG_A4XX_RBBM_PERFCTR_UCHE_3_HI				0x0000010b
1863 
1864 #define REG_A4XX_RBBM_PERFCTR_UCHE_4_LO				0x0000010c
1865 
1866 #define REG_A4XX_RBBM_PERFCTR_UCHE_4_HI				0x0000010d
1867 
1868 #define REG_A4XX_RBBM_PERFCTR_UCHE_5_LO				0x0000010e
1869 
1870 #define REG_A4XX_RBBM_PERFCTR_UCHE_5_HI				0x0000010f
1871 
1872 #define REG_A4XX_RBBM_PERFCTR_UCHE_6_LO				0x00000110
1873 
1874 #define REG_A4XX_RBBM_PERFCTR_UCHE_6_HI				0x00000111
1875 
1876 #define REG_A4XX_RBBM_PERFCTR_UCHE_7_LO				0x00000112
1877 
1878 #define REG_A4XX_RBBM_PERFCTR_UCHE_7_HI				0x00000113
1879 
1880 #define REG_A4XX_RBBM_PERFCTR_TP_0_LO				0x00000114
1881 
1882 #define REG_A4XX_RBBM_PERFCTR_TP_0_HI				0x00000115
1883 
1884 #define REG_A4XX_RBBM_PERFCTR_TP_0_LO				0x00000114
1885 
1886 #define REG_A4XX_RBBM_PERFCTR_TP_0_HI				0x00000115
1887 
1888 #define REG_A4XX_RBBM_PERFCTR_TP_1_LO				0x00000116
1889 
1890 #define REG_A4XX_RBBM_PERFCTR_TP_1_HI				0x00000117
1891 
1892 #define REG_A4XX_RBBM_PERFCTR_TP_2_LO				0x00000118
1893 
1894 #define REG_A4XX_RBBM_PERFCTR_TP_2_HI				0x00000119
1895 
1896 #define REG_A4XX_RBBM_PERFCTR_TP_3_LO				0x0000011a
1897 
1898 #define REG_A4XX_RBBM_PERFCTR_TP_3_HI				0x0000011b
1899 
1900 #define REG_A4XX_RBBM_PERFCTR_TP_4_LO				0x0000011c
1901 
1902 #define REG_A4XX_RBBM_PERFCTR_TP_4_HI				0x0000011d
1903 
1904 #define REG_A4XX_RBBM_PERFCTR_TP_5_LO				0x0000011e
1905 
1906 #define REG_A4XX_RBBM_PERFCTR_TP_5_HI				0x0000011f
1907 
1908 #define REG_A4XX_RBBM_PERFCTR_TP_6_LO				0x00000120
1909 
1910 #define REG_A4XX_RBBM_PERFCTR_TP_6_HI				0x00000121
1911 
1912 #define REG_A4XX_RBBM_PERFCTR_TP_7_LO				0x00000122
1913 
1914 #define REG_A4XX_RBBM_PERFCTR_TP_7_HI				0x00000123
1915 
1916 #define REG_A4XX_RBBM_PERFCTR_SP_0_LO				0x00000124
1917 
1918 #define REG_A4XX_RBBM_PERFCTR_SP_0_HI				0x00000125
1919 
1920 #define REG_A4XX_RBBM_PERFCTR_SP_1_LO				0x00000126
1921 
1922 #define REG_A4XX_RBBM_PERFCTR_SP_1_HI				0x00000127
1923 
1924 #define REG_A4XX_RBBM_PERFCTR_SP_2_LO				0x00000128
1925 
1926 #define REG_A4XX_RBBM_PERFCTR_SP_2_HI				0x00000129
1927 
1928 #define REG_A4XX_RBBM_PERFCTR_SP_3_LO				0x0000012a
1929 
1930 #define REG_A4XX_RBBM_PERFCTR_SP_3_HI				0x0000012b
1931 
1932 #define REG_A4XX_RBBM_PERFCTR_SP_4_LO				0x0000012c
1933 
1934 #define REG_A4XX_RBBM_PERFCTR_SP_4_HI				0x0000012d
1935 
1936 #define REG_A4XX_RBBM_PERFCTR_SP_5_LO				0x0000012e
1937 
1938 #define REG_A4XX_RBBM_PERFCTR_SP_5_HI				0x0000012f
1939 
1940 #define REG_A4XX_RBBM_PERFCTR_SP_6_LO				0x00000130
1941 
1942 #define REG_A4XX_RBBM_PERFCTR_SP_6_HI				0x00000131
1943 
1944 #define REG_A4XX_RBBM_PERFCTR_SP_7_LO				0x00000132
1945 
1946 #define REG_A4XX_RBBM_PERFCTR_SP_7_HI				0x00000133
1947 
1948 #define REG_A4XX_RBBM_PERFCTR_SP_8_LO				0x00000134
1949 
1950 #define REG_A4XX_RBBM_PERFCTR_SP_8_HI				0x00000135
1951 
1952 #define REG_A4XX_RBBM_PERFCTR_SP_9_LO				0x00000136
1953 
1954 #define REG_A4XX_RBBM_PERFCTR_SP_9_HI				0x00000137
1955 
1956 #define REG_A4XX_RBBM_PERFCTR_SP_10_LO				0x00000138
1957 
1958 #define REG_A4XX_RBBM_PERFCTR_SP_10_HI				0x00000139
1959 
1960 #define REG_A4XX_RBBM_PERFCTR_SP_11_LO				0x0000013a
1961 
1962 #define REG_A4XX_RBBM_PERFCTR_SP_11_HI				0x0000013b
1963 
1964 #define REG_A4XX_RBBM_PERFCTR_RB_0_LO				0x0000013c
1965 
1966 #define REG_A4XX_RBBM_PERFCTR_RB_0_HI				0x0000013d
1967 
1968 #define REG_A4XX_RBBM_PERFCTR_RB_1_LO				0x0000013e
1969 
1970 #define REG_A4XX_RBBM_PERFCTR_RB_1_HI				0x0000013f
1971 
1972 #define REG_A4XX_RBBM_PERFCTR_RB_2_LO				0x00000140
1973 
1974 #define REG_A4XX_RBBM_PERFCTR_RB_2_HI				0x00000141
1975 
1976 #define REG_A4XX_RBBM_PERFCTR_RB_3_LO				0x00000142
1977 
1978 #define REG_A4XX_RBBM_PERFCTR_RB_3_HI				0x00000143
1979 
1980 #define REG_A4XX_RBBM_PERFCTR_RB_4_LO				0x00000144
1981 
1982 #define REG_A4XX_RBBM_PERFCTR_RB_4_HI				0x00000145
1983 
1984 #define REG_A4XX_RBBM_PERFCTR_RB_5_LO				0x00000146
1985 
1986 #define REG_A4XX_RBBM_PERFCTR_RB_5_HI				0x00000147
1987 
1988 #define REG_A4XX_RBBM_PERFCTR_RB_6_LO				0x00000148
1989 
1990 #define REG_A4XX_RBBM_PERFCTR_RB_6_HI				0x00000149
1991 
1992 #define REG_A4XX_RBBM_PERFCTR_RB_7_LO				0x0000014a
1993 
1994 #define REG_A4XX_RBBM_PERFCTR_RB_7_HI				0x0000014b
1995 
1996 #define REG_A4XX_RBBM_PERFCTR_VSC_0_LO				0x0000014c
1997 
1998 #define REG_A4XX_RBBM_PERFCTR_VSC_0_HI				0x0000014d
1999 
2000 #define REG_A4XX_RBBM_PERFCTR_VSC_1_LO				0x0000014e
2001 
2002 #define REG_A4XX_RBBM_PERFCTR_VSC_1_HI				0x0000014f
2003 
2004 #define REG_A4XX_RBBM_PERFCTR_PWR_0_LO				0x00000166
2005 
2006 #define REG_A4XX_RBBM_PERFCTR_PWR_0_HI				0x00000167
2007 
2008 #define REG_A4XX_RBBM_PERFCTR_PWR_1_LO				0x00000168
2009 
2010 #define REG_A4XX_RBBM_PERFCTR_PWR_1_HI				0x00000169
2011 
2012 #define REG_A4XX_RBBM_ALWAYSON_COUNTER_LO			0x0000016e
2013 
2014 #define REG_A4XX_RBBM_ALWAYSON_COUNTER_HI			0x0000016f
2015 
2016 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; }
2017 
2018 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; }
2019 
2020 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; }
2021 
2022 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; }
2023 
2024 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; }
2025 
2026 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; }
2027 
2028 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; }
2029 
2030 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; }
2031 
2032 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; }
2033 
2034 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; }
2035 
2036 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; }
2037 
2038 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; }
2039 
2040 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; }
2041 
2042 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; }
2043 
2044 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; }
2045 
2046 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; }
2047 
2048 #define REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM			0x00000080
2049 
2050 #define REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM			0x00000081
2051 
2052 #define REG_A4XX_RBBM_CLOCK_CTL_HLSQ				0x0000008a
2053 
2054 #define REG_A4XX_RBBM_CLOCK_HYST_HLSQ				0x0000008b
2055 
2056 #define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ				0x0000008c
2057 
2058 #define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM			0x0000008d
2059 
2060 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; }
2061 
2062 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; }
2063 
2064 #define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0			0x00000099
2065 
2066 #define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1			0x0000009a
2067 
2068 #define REG_A4XX_RBBM_PERFCTR_PWR_1_LO				0x00000168
2069 
2070 #define REG_A4XX_RBBM_PERFCTR_CTL				0x00000170
2071 
2072 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0				0x00000171
2073 
2074 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1				0x00000172
2075 
2076 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2				0x00000173
2077 
2078 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO			0x00000174
2079 
2080 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI			0x00000175
2081 
2082 #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_0			0x00000176
2083 
2084 #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_1			0x00000177
2085 
2086 #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_2			0x00000178
2087 
2088 #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_3			0x00000179
2089 
2090 #define REG_A4XX_RBBM_GPU_BUSY_MASKED				0x0000017a
2091 
2092 #define REG_A4XX_RBBM_INT_0_STATUS				0x0000017d
2093 
2094 #define REG_A4XX_RBBM_CLOCK_STATUS				0x00000182
2095 
2096 #define REG_A4XX_RBBM_AHB_STATUS				0x00000189
2097 
2098 #define REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS			0x0000018c
2099 
2100 #define REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS			0x0000018d
2101 
2102 #define REG_A4XX_RBBM_AHB_ERROR_STATUS				0x0000018f
2103 
2104 #define REG_A4XX_RBBM_STATUS					0x00000191
2105 #define A4XX_RBBM_STATUS_HI_BUSY				0x00000001
2106 #define A4XX_RBBM_STATUS_CP_ME_BUSY				0x00000002
2107 #define A4XX_RBBM_STATUS_CP_PFP_BUSY				0x00000004
2108 #define A4XX_RBBM_STATUS_CP_NRT_BUSY				0x00004000
2109 #define A4XX_RBBM_STATUS_VBIF_BUSY				0x00008000
2110 #define A4XX_RBBM_STATUS_TSE_BUSY				0x00010000
2111 #define A4XX_RBBM_STATUS_RAS_BUSY				0x00020000
2112 #define A4XX_RBBM_STATUS_RB_BUSY				0x00040000
2113 #define A4XX_RBBM_STATUS_PC_DCALL_BUSY				0x00080000
2114 #define A4XX_RBBM_STATUS_PC_VSD_BUSY				0x00100000
2115 #define A4XX_RBBM_STATUS_VFD_BUSY				0x00200000
2116 #define A4XX_RBBM_STATUS_VPC_BUSY				0x00400000
2117 #define A4XX_RBBM_STATUS_UCHE_BUSY				0x00800000
2118 #define A4XX_RBBM_STATUS_SP_BUSY				0x01000000
2119 #define A4XX_RBBM_STATUS_TPL1_BUSY				0x02000000
2120 #define A4XX_RBBM_STATUS_MARB_BUSY				0x04000000
2121 #define A4XX_RBBM_STATUS_VSC_BUSY				0x08000000
2122 #define A4XX_RBBM_STATUS_ARB_BUSY				0x10000000
2123 #define A4XX_RBBM_STATUS_HLSQ_BUSY				0x20000000
2124 #define A4XX_RBBM_STATUS_GPU_BUSY_NOHC				0x40000000
2125 #define A4XX_RBBM_STATUS_GPU_BUSY				0x80000000
2126 
2127 #define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5			0x0000019f
2128 
2129 #define REG_A4XX_RBBM_POWER_STATUS				0x000001b0
2130 #define A4XX_RBBM_POWER_STATUS_SP_TP_PWR_ON			0x00100000
2131 
2132 #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2			0x000001b8
2133 
2134 #define REG_A4XX_CP_SCRATCH_UMASK				0x00000228
2135 
2136 #define REG_A4XX_CP_SCRATCH_ADDR				0x00000229
2137 
2138 #define REG_A4XX_CP_RB_BASE					0x00000200
2139 
2140 #define REG_A4XX_CP_RB_CNTL					0x00000201
2141 
2142 #define REG_A4XX_CP_RB_WPTR					0x00000205
2143 
2144 #define REG_A4XX_CP_RB_RPTR_ADDR				0x00000203
2145 
2146 #define REG_A4XX_CP_RB_RPTR					0x00000204
2147 
2148 #define REG_A4XX_CP_IB1_BASE					0x00000206
2149 
2150 #define REG_A4XX_CP_IB1_BUFSZ					0x00000207
2151 
2152 #define REG_A4XX_CP_IB2_BASE					0x00000208
2153 
2154 #define REG_A4XX_CP_IB2_BUFSZ					0x00000209
2155 
2156 #define REG_A4XX_CP_ME_NRT_ADDR					0x0000020c
2157 
2158 #define REG_A4XX_CP_ME_NRT_DATA					0x0000020d
2159 
2160 #define REG_A4XX_CP_ME_RB_DONE_DATA				0x00000217
2161 
2162 #define REG_A4XX_CP_QUEUE_THRESH2				0x00000219
2163 
2164 #define REG_A4XX_CP_MERCIU_SIZE					0x0000021b
2165 
2166 #define REG_A4XX_CP_ROQ_ADDR					0x0000021c
2167 
2168 #define REG_A4XX_CP_ROQ_DATA					0x0000021d
2169 
2170 #define REG_A4XX_CP_MEQ_ADDR					0x0000021e
2171 
2172 #define REG_A4XX_CP_MEQ_DATA					0x0000021f
2173 
2174 #define REG_A4XX_CP_MERCIU_ADDR					0x00000220
2175 
2176 #define REG_A4XX_CP_MERCIU_DATA					0x00000221
2177 
2178 #define REG_A4XX_CP_MERCIU_DATA2				0x00000222
2179 
2180 #define REG_A4XX_CP_PFP_UCODE_ADDR				0x00000223
2181 
2182 #define REG_A4XX_CP_PFP_UCODE_DATA				0x00000224
2183 
2184 #define REG_A4XX_CP_ME_RAM_WADDR				0x00000225
2185 
2186 #define REG_A4XX_CP_ME_RAM_RADDR				0x00000226
2187 
2188 #define REG_A4XX_CP_ME_RAM_DATA					0x00000227
2189 
2190 #define REG_A4XX_CP_PREEMPT					0x0000022a
2191 
2192 #define REG_A4XX_CP_CNTL					0x0000022c
2193 
2194 #define REG_A4XX_CP_ME_CNTL					0x0000022d
2195 
2196 #define REG_A4XX_CP_DEBUG					0x0000022e
2197 
2198 #define REG_A4XX_CP_DEBUG_ECO_CONTROL				0x00000231
2199 
2200 #define REG_A4XX_CP_DRAW_STATE_ADDR				0x00000232
2201 
2202 static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; }
2203 
2204 static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; }
2205 #define A4XX_CP_PROTECT_REG_BASE_ADDR__MASK			0x0001ffff
2206 #define A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT			0
2207 static inline uint32_t A4XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
2208 {
2209 	return ((val) << A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A4XX_CP_PROTECT_REG_BASE_ADDR__MASK;
2210 }
2211 #define A4XX_CP_PROTECT_REG_MASK_LEN__MASK			0x1f000000
2212 #define A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT			24
2213 static inline uint32_t A4XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
2214 {
2215 	return ((val) << A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A4XX_CP_PROTECT_REG_MASK_LEN__MASK;
2216 }
2217 #define A4XX_CP_PROTECT_REG_TRAP_WRITE				0x20000000
2218 #define A4XX_CP_PROTECT_REG_TRAP_READ				0x40000000
2219 
2220 #define REG_A4XX_CP_PROTECT_CTRL				0x00000250
2221 
2222 #define REG_A4XX_CP_ST_BASE					0x000004c0
2223 
2224 #define REG_A4XX_CP_STQ_AVAIL					0x000004ce
2225 
2226 #define REG_A4XX_CP_MERCIU_STAT					0x000004d0
2227 
2228 #define REG_A4XX_CP_WFI_PEND_CTR				0x000004d2
2229 
2230 #define REG_A4XX_CP_HW_FAULT					0x000004d8
2231 
2232 #define REG_A4XX_CP_PROTECT_STATUS				0x000004da
2233 
2234 #define REG_A4XX_CP_EVENTS_IN_FLIGHT				0x000004dd
2235 
2236 #define REG_A4XX_CP_PERFCTR_CP_SEL_0				0x00000500
2237 
2238 #define REG_A4XX_CP_PERFCTR_CP_SEL_1				0x00000501
2239 
2240 #define REG_A4XX_CP_PERFCTR_CP_SEL_2				0x00000502
2241 
2242 #define REG_A4XX_CP_PERFCTR_CP_SEL_3				0x00000503
2243 
2244 #define REG_A4XX_CP_PERFCTR_CP_SEL_4				0x00000504
2245 
2246 #define REG_A4XX_CP_PERFCTR_CP_SEL_5				0x00000505
2247 
2248 #define REG_A4XX_CP_PERFCTR_CP_SEL_6				0x00000506
2249 
2250 #define REG_A4XX_CP_PERFCTR_CP_SEL_7				0x00000507
2251 
2252 #define REG_A4XX_CP_PERFCOMBINER_SELECT				0x0000050b
2253 
2254 static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; }
2255 
2256 static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; }
2257 
2258 #define REG_A4XX_SP_VS_STATUS					0x00000ec0
2259 
2260 #define REG_A4XX_SP_MODE_CONTROL				0x00000ec3
2261 
2262 #define REG_A4XX_SP_PERFCTR_SP_SEL_0				0x00000ec4
2263 
2264 #define REG_A4XX_SP_PERFCTR_SP_SEL_1				0x00000ec5
2265 
2266 #define REG_A4XX_SP_PERFCTR_SP_SEL_2				0x00000ec6
2267 
2268 #define REG_A4XX_SP_PERFCTR_SP_SEL_3				0x00000ec7
2269 
2270 #define REG_A4XX_SP_PERFCTR_SP_SEL_4				0x00000ec8
2271 
2272 #define REG_A4XX_SP_PERFCTR_SP_SEL_5				0x00000ec9
2273 
2274 #define REG_A4XX_SP_PERFCTR_SP_SEL_6				0x00000eca
2275 
2276 #define REG_A4XX_SP_PERFCTR_SP_SEL_7				0x00000ecb
2277 
2278 #define REG_A4XX_SP_PERFCTR_SP_SEL_8				0x00000ecc
2279 
2280 #define REG_A4XX_SP_PERFCTR_SP_SEL_9				0x00000ecd
2281 
2282 #define REG_A4XX_SP_PERFCTR_SP_SEL_10				0x00000ece
2283 
2284 #define REG_A4XX_SP_PERFCTR_SP_SEL_11				0x00000ecf
2285 
2286 #define REG_A4XX_SP_SP_CTRL_REG					0x000022c0
2287 #define A4XX_SP_SP_CTRL_REG_BINNING_PASS			0x00080000
2288 
2289 #define REG_A4XX_SP_INSTR_CACHE_CTRL				0x000022c1
2290 #define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER			0x00000080
2291 #define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER			0x00000100
2292 #define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER			0x00000400
2293 
2294 #define REG_A4XX_SP_VS_CTRL_REG0				0x000022c4
2295 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK			0x00000001
2296 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT			0
2297 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
2298 {
2299 	return ((val) << A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
2300 }
2301 #define A4XX_SP_VS_CTRL_REG0_VARYING				0x00000002
2302 #define A4XX_SP_VS_CTRL_REG0_CACHEINVALID			0x00000004
2303 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x000003f0
2304 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT		4
2305 static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
2306 {
2307 	return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
2308 }
2309 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x0000fc00
2310 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT		10
2311 static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
2312 {
2313 	return ((val) << A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
2314 }
2315 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK		0x000c0000
2316 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT		18
2317 static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
2318 {
2319 	return ((val) << A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK;
2320 }
2321 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK			0x00100000
2322 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT			20
2323 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
2324 {
2325 	return ((val) << A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
2326 }
2327 #define A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE			0x00200000
2328 #define A4XX_SP_VS_CTRL_REG0_PIXLODENABLE			0x00400000
2329 
2330 #define REG_A4XX_SP_VS_CTRL_REG1				0x000022c5
2331 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK			0x000000ff
2332 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT			0
2333 static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val)
2334 {
2335 	return ((val) << A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK;
2336 }
2337 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK		0x7f000000
2338 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT		24
2339 static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
2340 {
2341 	return ((val) << A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK;
2342 }
2343 
2344 #define REG_A4XX_SP_VS_PARAM_REG				0x000022c6
2345 #define A4XX_SP_VS_PARAM_REG_POSREGID__MASK			0x000000ff
2346 #define A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT			0
2347 static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val)
2348 {
2349 	return ((val) << A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_POSREGID__MASK;
2350 }
2351 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK			0x0000ff00
2352 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT			8
2353 static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val)
2354 {
2355 	return ((val) << A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK;
2356 }
2357 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK		0xfff00000
2358 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT		20
2359 static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
2360 {
2361 	return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK;
2362 }
2363 
2364 static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
2365 
2366 static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
2367 #define A4XX_SP_VS_OUT_REG_A_REGID__MASK			0x000001ff
2368 #define A4XX_SP_VS_OUT_REG_A_REGID__SHIFT			0
2369 static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
2370 {
2371 	return ((val) << A4XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_A_REGID__MASK;
2372 }
2373 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK			0x00001e00
2374 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT			9
2375 static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
2376 {
2377 	return ((val) << A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
2378 }
2379 #define A4XX_SP_VS_OUT_REG_B_REGID__MASK			0x01ff0000
2380 #define A4XX_SP_VS_OUT_REG_B_REGID__SHIFT			16
2381 static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
2382 {
2383 	return ((val) << A4XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_B_REGID__MASK;
2384 }
2385 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK			0x1e000000
2386 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT			25
2387 static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
2388 {
2389 	return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
2390 }
2391 
2392 static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
2393 
2394 static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
2395 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK			0x000000ff
2396 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT			0
2397 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
2398 {
2399 	return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
2400 }
2401 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK			0x0000ff00
2402 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT			8
2403 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
2404 {
2405 	return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
2406 }
2407 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK			0x00ff0000
2408 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT			16
2409 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
2410 {
2411 	return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
2412 }
2413 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK			0xff000000
2414 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT			24
2415 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
2416 {
2417 	return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
2418 }
2419 
2420 #define REG_A4XX_SP_VS_OBJ_OFFSET_REG				0x000022e0
2421 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK	0x01ff0000
2422 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT	16
2423 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2424 {
2425 	return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2426 }
2427 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK		0xfe000000
2428 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT	25
2429 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2430 {
2431 	return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2432 }
2433 
2434 #define REG_A4XX_SP_VS_OBJ_START				0x000022e1
2435 
2436 #define REG_A4XX_SP_VS_PVT_MEM_PARAM				0x000022e2
2437 
2438 #define REG_A4XX_SP_VS_PVT_MEM_ADDR				0x000022e3
2439 
2440 #define REG_A4XX_SP_VS_LENGTH_REG				0x000022e5
2441 
2442 #define REG_A4XX_SP_FS_CTRL_REG0				0x000022e8
2443 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK			0x00000001
2444 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT			0
2445 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
2446 {
2447 	return ((val) << A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
2448 }
2449 #define A4XX_SP_FS_CTRL_REG0_VARYING				0x00000002
2450 #define A4XX_SP_FS_CTRL_REG0_CACHEINVALID			0x00000004
2451 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x000003f0
2452 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT		4
2453 static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
2454 {
2455 	return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
2456 }
2457 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x0000fc00
2458 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT		10
2459 static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
2460 {
2461 	return ((val) << A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
2462 }
2463 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK		0x000c0000
2464 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT		18
2465 static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
2466 {
2467 	return ((val) << A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK;
2468 }
2469 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK			0x00100000
2470 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT			20
2471 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
2472 {
2473 	return ((val) << A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
2474 }
2475 #define A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE			0x00200000
2476 #define A4XX_SP_FS_CTRL_REG0_PIXLODENABLE			0x00400000
2477 
2478 #define REG_A4XX_SP_FS_CTRL_REG1				0x000022e9
2479 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK			0x000000ff
2480 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT			0
2481 static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val)
2482 {
2483 	return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK;
2484 }
2485 #define A4XX_SP_FS_CTRL_REG1_FACENESS				0x00080000
2486 #define A4XX_SP_FS_CTRL_REG1_VARYING				0x00100000
2487 #define A4XX_SP_FS_CTRL_REG1_FRAGCOORD				0x00200000
2488 
2489 #define REG_A4XX_SP_FS_OBJ_OFFSET_REG				0x000022ea
2490 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK	0x01ff0000
2491 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT	16
2492 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2493 {
2494 	return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2495 }
2496 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK		0xfe000000
2497 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT	25
2498 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2499 {
2500 	return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2501 }
2502 
2503 #define REG_A4XX_SP_FS_OBJ_START				0x000022eb
2504 
2505 #define REG_A4XX_SP_FS_PVT_MEM_PARAM				0x000022ec
2506 
2507 #define REG_A4XX_SP_FS_PVT_MEM_ADDR				0x000022ed
2508 
2509 #define REG_A4XX_SP_FS_LENGTH_REG				0x000022ef
2510 
2511 #define REG_A4XX_SP_FS_OUTPUT_REG				0x000022f0
2512 #define A4XX_SP_FS_OUTPUT_REG_MRT__MASK				0x0000000f
2513 #define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT			0
2514 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val)
2515 {
2516 	return ((val) << A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_SP_FS_OUTPUT_REG_MRT__MASK;
2517 }
2518 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE			0x00000080
2519 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK			0x0000ff00
2520 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT		8
2521 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val)
2522 {
2523 	return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK;
2524 }
2525 #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK		0xff000000
2526 #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT		24
2527 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val)
2528 {
2529 	return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK;
2530 }
2531 
2532 static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
2533 
2534 static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
2535 #define A4XX_SP_FS_MRT_REG_REGID__MASK				0x000000ff
2536 #define A4XX_SP_FS_MRT_REG_REGID__SHIFT				0
2537 static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val)
2538 {
2539 	return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK;
2540 }
2541 #define A4XX_SP_FS_MRT_REG_HALF_PRECISION			0x00000100
2542 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK			0x0003f000
2543 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT			12
2544 static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val)
2545 {
2546 	return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK;
2547 }
2548 #define A4XX_SP_FS_MRT_REG_COLOR_SRGB				0x00040000
2549 
2550 #define REG_A4XX_SP_CS_CTRL_REG0				0x00002300
2551 
2552 #define REG_A4XX_SP_CS_OBJ_OFFSET_REG				0x00002301
2553 
2554 #define REG_A4XX_SP_CS_OBJ_START				0x00002302
2555 
2556 #define REG_A4XX_SP_CS_PVT_MEM_PARAM				0x00002303
2557 
2558 #define REG_A4XX_SP_CS_PVT_MEM_ADDR				0x00002304
2559 
2560 #define REG_A4XX_SP_CS_PVT_MEM_SIZE				0x00002305
2561 
2562 #define REG_A4XX_SP_CS_LENGTH_REG				0x00002306
2563 
2564 #define REG_A4XX_SP_HS_OBJ_OFFSET_REG				0x0000230d
2565 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK	0x01ff0000
2566 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT	16
2567 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2568 {
2569 	return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2570 }
2571 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK		0xfe000000
2572 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT	25
2573 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2574 {
2575 	return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2576 }
2577 
2578 #define REG_A4XX_SP_HS_OBJ_START				0x0000230e
2579 
2580 #define REG_A4XX_SP_HS_PVT_MEM_PARAM				0x0000230f
2581 
2582 #define REG_A4XX_SP_HS_PVT_MEM_ADDR				0x00002310
2583 
2584 #define REG_A4XX_SP_HS_LENGTH_REG				0x00002312
2585 
2586 #define REG_A4XX_SP_DS_PARAM_REG				0x0000231a
2587 #define A4XX_SP_DS_PARAM_REG_POSREGID__MASK			0x000000ff
2588 #define A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT			0
2589 static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val)
2590 {
2591 	return ((val) << A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_DS_PARAM_REG_POSREGID__MASK;
2592 }
2593 #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK		0xfff00000
2594 #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT		20
2595 static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
2596 {
2597 	return ((val) << A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK;
2598 }
2599 
2600 static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; }
2601 
2602 static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; }
2603 #define A4XX_SP_DS_OUT_REG_A_REGID__MASK			0x000001ff
2604 #define A4XX_SP_DS_OUT_REG_A_REGID__SHIFT			0
2605 static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
2606 {
2607 	return ((val) << A4XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_A_REGID__MASK;
2608 }
2609 #define A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK			0x00001e00
2610 #define A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT			9
2611 static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)
2612 {
2613 	return ((val) << A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK;
2614 }
2615 #define A4XX_SP_DS_OUT_REG_B_REGID__MASK			0x01ff0000
2616 #define A4XX_SP_DS_OUT_REG_B_REGID__SHIFT			16
2617 static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val)
2618 {
2619 	return ((val) << A4XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_B_REGID__MASK;
2620 }
2621 #define A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK			0x1e000000
2622 #define A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT			25
2623 static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)
2624 {
2625 	return ((val) << A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK;
2626 }
2627 
2628 static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; }
2629 
2630 static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; }
2631 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK			0x000000ff
2632 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT			0
2633 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)
2634 {
2635 	return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK;
2636 }
2637 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK			0x0000ff00
2638 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT			8
2639 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)
2640 {
2641 	return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK;
2642 }
2643 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK			0x00ff0000
2644 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT			16
2645 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)
2646 {
2647 	return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK;
2648 }
2649 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK			0xff000000
2650 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT			24
2651 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
2652 {
2653 	return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
2654 }
2655 
2656 #define REG_A4XX_SP_DS_OBJ_OFFSET_REG				0x00002334
2657 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK	0x01ff0000
2658 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT	16
2659 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2660 {
2661 	return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2662 }
2663 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK		0xfe000000
2664 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT	25
2665 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2666 {
2667 	return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2668 }
2669 
2670 #define REG_A4XX_SP_DS_OBJ_START				0x00002335
2671 
2672 #define REG_A4XX_SP_DS_PVT_MEM_PARAM				0x00002336
2673 
2674 #define REG_A4XX_SP_DS_PVT_MEM_ADDR				0x00002337
2675 
2676 #define REG_A4XX_SP_DS_LENGTH_REG				0x00002339
2677 
2678 #define REG_A4XX_SP_GS_PARAM_REG				0x00002341
2679 #define A4XX_SP_GS_PARAM_REG_POSREGID__MASK			0x000000ff
2680 #define A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT			0
2681 static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val)
2682 {
2683 	return ((val) << A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_POSREGID__MASK;
2684 }
2685 #define A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK			0x0000ff00
2686 #define A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT			8
2687 static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val)
2688 {
2689 	return ((val) << A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK;
2690 }
2691 #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK		0xfff00000
2692 #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT		20
2693 static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
2694 {
2695 	return ((val) << A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK;
2696 }
2697 
2698 static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; }
2699 
2700 static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; }
2701 #define A4XX_SP_GS_OUT_REG_A_REGID__MASK			0x000001ff
2702 #define A4XX_SP_GS_OUT_REG_A_REGID__SHIFT			0
2703 static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val)
2704 {
2705 	return ((val) << A4XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_A_REGID__MASK;
2706 }
2707 #define A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK			0x00001e00
2708 #define A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT			9
2709 static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)
2710 {
2711 	return ((val) << A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK;
2712 }
2713 #define A4XX_SP_GS_OUT_REG_B_REGID__MASK			0x01ff0000
2714 #define A4XX_SP_GS_OUT_REG_B_REGID__SHIFT			16
2715 static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val)
2716 {
2717 	return ((val) << A4XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_B_REGID__MASK;
2718 }
2719 #define A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK			0x1e000000
2720 #define A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT			25
2721 static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)
2722 {
2723 	return ((val) << A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK;
2724 }
2725 
2726 static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; }
2727 
2728 static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; }
2729 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK			0x000000ff
2730 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT			0
2731 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)
2732 {
2733 	return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK;
2734 }
2735 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK			0x0000ff00
2736 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT			8
2737 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)
2738 {
2739 	return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK;
2740 }
2741 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK			0x00ff0000
2742 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT			16
2743 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)
2744 {
2745 	return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK;
2746 }
2747 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK			0xff000000
2748 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT			24
2749 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)
2750 {
2751 	return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;
2752 }
2753 
2754 #define REG_A4XX_SP_GS_OBJ_OFFSET_REG				0x0000235b
2755 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK	0x01ff0000
2756 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT	16
2757 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2758 {
2759 	return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2760 }
2761 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK		0xfe000000
2762 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT	25
2763 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2764 {
2765 	return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2766 }
2767 
2768 #define REG_A4XX_SP_GS_OBJ_START				0x0000235c
2769 
2770 #define REG_A4XX_SP_GS_PVT_MEM_PARAM				0x0000235d
2771 
2772 #define REG_A4XX_SP_GS_PVT_MEM_ADDR				0x0000235e
2773 
2774 #define REG_A4XX_SP_GS_LENGTH_REG				0x00002360
2775 
2776 #define REG_A4XX_VPC_DEBUG_RAM_SEL				0x00000e60
2777 
2778 #define REG_A4XX_VPC_DEBUG_RAM_READ				0x00000e61
2779 
2780 #define REG_A4XX_VPC_DEBUG_ECO_CONTROL				0x00000e64
2781 
2782 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_0				0x00000e65
2783 
2784 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_1				0x00000e66
2785 
2786 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_2				0x00000e67
2787 
2788 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_3				0x00000e68
2789 
2790 #define REG_A4XX_VPC_ATTR					0x00002140
2791 #define A4XX_VPC_ATTR_TOTALATTR__MASK				0x000001ff
2792 #define A4XX_VPC_ATTR_TOTALATTR__SHIFT				0
2793 static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val)
2794 {
2795 	return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK;
2796 }
2797 #define A4XX_VPC_ATTR_PSIZE					0x00000200
2798 #define A4XX_VPC_ATTR_THRDASSIGN__MASK				0x00003000
2799 #define A4XX_VPC_ATTR_THRDASSIGN__SHIFT				12
2800 static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val)
2801 {
2802 	return ((val) << A4XX_VPC_ATTR_THRDASSIGN__SHIFT) & A4XX_VPC_ATTR_THRDASSIGN__MASK;
2803 }
2804 #define A4XX_VPC_ATTR_ENABLE					0x02000000
2805 
2806 #define REG_A4XX_VPC_PACK					0x00002141
2807 #define A4XX_VPC_PACK_NUMBYPASSVAR__MASK			0x000000ff
2808 #define A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT			0
2809 static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val)
2810 {
2811 	return ((val) << A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT) & A4XX_VPC_PACK_NUMBYPASSVAR__MASK;
2812 }
2813 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK			0x0000ff00
2814 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT			8
2815 static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val)
2816 {
2817 	return ((val) << A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK;
2818 }
2819 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK			0x00ff0000
2820 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT			16
2821 static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val)
2822 {
2823 	return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK;
2824 }
2825 
2826 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; }
2827 
2828 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; }
2829 
2830 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; }
2831 
2832 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; }
2833 
2834 #define REG_A4XX_VPC_SO_FLUSH_WADDR_3				0x0000216e
2835 
2836 #define REG_A4XX_VSC_BIN_SIZE					0x00000c00
2837 #define A4XX_VSC_BIN_SIZE_WIDTH__MASK				0x0000001f
2838 #define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT				0
2839 static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
2840 {
2841 	return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK;
2842 }
2843 #define A4XX_VSC_BIN_SIZE_HEIGHT__MASK				0x000003e0
2844 #define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT				5
2845 static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
2846 {
2847 	return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK;
2848 }
2849 
2850 #define REG_A4XX_VSC_SIZE_ADDRESS				0x00000c01
2851 
2852 #define REG_A4XX_VSC_SIZE_ADDRESS2				0x00000c02
2853 
2854 #define REG_A4XX_VSC_DEBUG_ECO_CONTROL				0x00000c03
2855 
2856 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
2857 
2858 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
2859 #define A4XX_VSC_PIPE_CONFIG_REG_X__MASK			0x000003ff
2860 #define A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT			0
2861 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
2862 {
2863 	return ((val) << A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_X__MASK;
2864 }
2865 #define A4XX_VSC_PIPE_CONFIG_REG_Y__MASK			0x000ffc00
2866 #define A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT			10
2867 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
2868 {
2869 	return ((val) << A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_Y__MASK;
2870 }
2871 #define A4XX_VSC_PIPE_CONFIG_REG_W__MASK			0x00f00000
2872 #define A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT			20
2873 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
2874 {
2875 	return ((val) << A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_W__MASK;
2876 }
2877 #define A4XX_VSC_PIPE_CONFIG_REG_H__MASK			0x0f000000
2878 #define A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT			24
2879 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
2880 {
2881 	return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK;
2882 }
2883 
2884 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
2885 
2886 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
2887 
2888 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
2889 
2890 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
2891 
2892 #define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1			0x00000c41
2893 
2894 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_0				0x00000c50
2895 
2896 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_1				0x00000c51
2897 
2898 #define REG_A4XX_VFD_DEBUG_CONTROL				0x00000e40
2899 
2900 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_0				0x00000e43
2901 
2902 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_1				0x00000e44
2903 
2904 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_2				0x00000e45
2905 
2906 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_3				0x00000e46
2907 
2908 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_4				0x00000e47
2909 
2910 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_5				0x00000e48
2911 
2912 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_6				0x00000e49
2913 
2914 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_7				0x00000e4a
2915 
2916 #define REG_A4XX_VGT_CL_INITIATOR				0x000021d0
2917 
2918 #define REG_A4XX_VGT_EVENT_INITIATOR				0x000021d9
2919 
2920 #define REG_A4XX_VFD_CONTROL_0					0x00002200
2921 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK			0x000000ff
2922 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT			0
2923 static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val)
2924 {
2925 	return ((val) << A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK;
2926 }
2927 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK			0x0001fe00
2928 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT			9
2929 static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val)
2930 {
2931 	return ((val) << A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT) & A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK;
2932 }
2933 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK		0x03f00000
2934 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT		20
2935 static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val)
2936 {
2937 	return ((val) << A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK;
2938 }
2939 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK		0xfc000000
2940 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT		26
2941 static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val)
2942 {
2943 	return ((val) << A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK;
2944 }
2945 
2946 #define REG_A4XX_VFD_CONTROL_1					0x00002201
2947 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK			0x0000ffff
2948 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT			0
2949 static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val)
2950 {
2951 	return ((val) << A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK;
2952 }
2953 #define A4XX_VFD_CONTROL_1_REGID4VTX__MASK			0x00ff0000
2954 #define A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT			16
2955 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
2956 {
2957 	return ((val) << A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A4XX_VFD_CONTROL_1_REGID4VTX__MASK;
2958 }
2959 #define A4XX_VFD_CONTROL_1_REGID4INST__MASK			0xff000000
2960 #define A4XX_VFD_CONTROL_1_REGID4INST__SHIFT			24
2961 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
2962 {
2963 	return ((val) << A4XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A4XX_VFD_CONTROL_1_REGID4INST__MASK;
2964 }
2965 
2966 #define REG_A4XX_VFD_CONTROL_2					0x00002202
2967 
2968 #define REG_A4XX_VFD_CONTROL_3					0x00002203
2969 #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK			0x0000ff00
2970 #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT			8
2971 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val)
2972 {
2973 	return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK;
2974 }
2975 #define A4XX_VFD_CONTROL_3_REGID_TESSX__MASK			0x00ff0000
2976 #define A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT			16
2977 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
2978 {
2979 	return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSX__MASK;
2980 }
2981 #define A4XX_VFD_CONTROL_3_REGID_TESSY__MASK			0xff000000
2982 #define A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT			24
2983 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
2984 {
2985 	return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSY__MASK;
2986 }
2987 
2988 #define REG_A4XX_VFD_CONTROL_4					0x00002204
2989 
2990 #define REG_A4XX_VFD_INDEX_OFFSET				0x00002208
2991 
2992 static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; }
2993 
2994 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; }
2995 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK			0x0000007f
2996 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT			0
2997 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val)
2998 {
2999 	return ((val) << A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK;
3000 }
3001 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK			0x0001ff80
3002 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT			7
3003 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)
3004 {
3005 	return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK;
3006 }
3007 #define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT			0x00080000
3008 #define A4XX_VFD_FETCH_INSTR_0_INSTANCED			0x00100000
3009 
3010 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; }
3011 
3012 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; }
3013 #define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK			0xffffffff
3014 #define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT			0
3015 static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val)
3016 {
3017 	return ((val) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK;
3018 }
3019 
3020 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; }
3021 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK			0x000001ff
3022 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT			0
3023 static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val)
3024 {
3025 	return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK;
3026 }
3027 
3028 static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; }
3029 
3030 static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; }
3031 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK			0x0000000f
3032 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT			0
3033 static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val)
3034 {
3035 	return ((val) << A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK;
3036 }
3037 #define A4XX_VFD_DECODE_INSTR_CONSTFILL				0x00000010
3038 #define A4XX_VFD_DECODE_INSTR_FORMAT__MASK			0x00000fc0
3039 #define A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT			6
3040 static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val)
3041 {
3042 	return ((val) << A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A4XX_VFD_DECODE_INSTR_FORMAT__MASK;
3043 }
3044 #define A4XX_VFD_DECODE_INSTR_REGID__MASK			0x000ff000
3045 #define A4XX_VFD_DECODE_INSTR_REGID__SHIFT			12
3046 static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val)
3047 {
3048 	return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK;
3049 }
3050 #define A4XX_VFD_DECODE_INSTR_INT				0x00100000
3051 #define A4XX_VFD_DECODE_INSTR_SWAP__MASK			0x00c00000
3052 #define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT			22
3053 static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
3054 {
3055 	return ((val) << A4XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A4XX_VFD_DECODE_INSTR_SWAP__MASK;
3056 }
3057 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK			0x1f000000
3058 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT			24
3059 static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
3060 {
3061 	return ((val) << A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK;
3062 }
3063 #define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID			0x20000000
3064 #define A4XX_VFD_DECODE_INSTR_SWITCHNEXT			0x40000000
3065 
3066 #define REG_A4XX_TPL1_DEBUG_ECO_CONTROL				0x00000f00
3067 
3068 #define REG_A4XX_TPL1_TP_MODE_CONTROL				0x00000f03
3069 
3070 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_0				0x00000f04
3071 
3072 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_1				0x00000f05
3073 
3074 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_2				0x00000f06
3075 
3076 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_3				0x00000f07
3077 
3078 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_4				0x00000f08
3079 
3080 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_5				0x00000f09
3081 
3082 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_6				0x00000f0a
3083 
3084 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_7				0x00000f0b
3085 
3086 #define REG_A4XX_TPL1_TP_TEX_OFFSET				0x00002380
3087 
3088 #define REG_A4XX_TPL1_TP_TEX_COUNT				0x00002381
3089 #define A4XX_TPL1_TP_TEX_COUNT_VS__MASK				0x000000ff
3090 #define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT			0
3091 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val)
3092 {
3093 	return ((val) << A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_VS__MASK;
3094 }
3095 #define A4XX_TPL1_TP_TEX_COUNT_HS__MASK				0x0000ff00
3096 #define A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT			8
3097 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val)
3098 {
3099 	return ((val) << A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_HS__MASK;
3100 }
3101 #define A4XX_TPL1_TP_TEX_COUNT_DS__MASK				0x00ff0000
3102 #define A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT			16
3103 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val)
3104 {
3105 	return ((val) << A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_DS__MASK;
3106 }
3107 #define A4XX_TPL1_TP_TEX_COUNT_GS__MASK				0xff000000
3108 #define A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT			24
3109 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val)
3110 {
3111 	return ((val) << A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_GS__MASK;
3112 }
3113 
3114 #define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR		0x00002384
3115 
3116 #define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR		0x00002387
3117 
3118 #define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR		0x0000238a
3119 
3120 #define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR		0x0000238d
3121 
3122 #define REG_A4XX_TPL1_TP_FS_TEX_COUNT				0x000023a0
3123 
3124 #define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR		0x000023a1
3125 
3126 #define REG_A4XX_TPL1_TP_CS_BORDER_COLOR_BASE_ADDR		0x000023a4
3127 
3128 #define REG_A4XX_TPL1_TP_CS_SAMPLER_BASE_ADDR			0x000023a5
3129 
3130 #define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR			0x000023a6
3131 
3132 #define REG_A4XX_GRAS_TSE_STATUS				0x00000c80
3133 
3134 #define REG_A4XX_GRAS_DEBUG_ECO_CONTROL				0x00000c81
3135 
3136 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0				0x00000c88
3137 
3138 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_1				0x00000c89
3139 
3140 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_2				0x00000c8a
3141 
3142 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3				0x00000c8b
3143 
3144 #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_0				0x00000c8c
3145 
3146 #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_1				0x00000c8d
3147 
3148 #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_2				0x00000c8e
3149 
3150 #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_3				0x00000c8f
3151 
3152 #define REG_A4XX_GRAS_CL_CLIP_CNTL				0x00002000
3153 #define A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE			0x00008000
3154 #define A4XX_GRAS_CL_CLIP_CNTL_ZNEAR_CLIP_DISABLE		0x00010000
3155 #define A4XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE		0x00020000
3156 #define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z			0x00400000
3157 
3158 #define REG_A4XX_GRAS_CLEAR_CNTL				0x00002003
3159 #define A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR			0x00000001
3160 
3161 #define REG_A4XX_GRAS_CL_GB_CLIP_ADJ				0x00002004
3162 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK			0x000003ff
3163 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT			0
3164 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val)
3165 {
3166 	return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK;
3167 }
3168 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK			0x000ffc00
3169 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT			10
3170 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val)
3171 {
3172 	return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK;
3173 }
3174 
3175 #define REG_A4XX_GRAS_CL_VPORT_XOFFSET_0			0x00002008
3176 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK			0xffffffff
3177 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT			0
3178 static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val)
3179 {
3180 	return ((fui(val)) << A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
3181 }
3182 
3183 #define REG_A4XX_GRAS_CL_VPORT_XSCALE_0				0x00002009
3184 #define A4XX_GRAS_CL_VPORT_XSCALE_0__MASK			0xffffffff
3185 #define A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT			0
3186 static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val)
3187 {
3188 	return ((fui(val)) << A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_XSCALE_0__MASK;
3189 }
3190 
3191 #define REG_A4XX_GRAS_CL_VPORT_YOFFSET_0			0x0000200a
3192 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK			0xffffffff
3193 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT			0
3194 static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val)
3195 {
3196 	return ((fui(val)) << A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
3197 }
3198 
3199 #define REG_A4XX_GRAS_CL_VPORT_YSCALE_0				0x0000200b
3200 #define A4XX_GRAS_CL_VPORT_YSCALE_0__MASK			0xffffffff
3201 #define A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT			0
3202 static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val)
3203 {
3204 	return ((fui(val)) << A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_YSCALE_0__MASK;
3205 }
3206 
3207 #define REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0			0x0000200c
3208 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK			0xffffffff
3209 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT			0
3210 static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
3211 {
3212 	return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
3213 }
3214 
3215 #define REG_A4XX_GRAS_CL_VPORT_ZSCALE_0				0x0000200d
3216 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK			0xffffffff
3217 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT			0
3218 static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val)
3219 {
3220 	return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
3221 }
3222 
3223 #define REG_A4XX_GRAS_SU_POINT_MINMAX				0x00002070
3224 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK			0x0000ffff
3225 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT			0
3226 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val)
3227 {
3228 	return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
3229 }
3230 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK			0xffff0000
3231 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT			16
3232 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val)
3233 {
3234 	return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
3235 }
3236 
3237 #define REG_A4XX_GRAS_SU_POINT_SIZE				0x00002071
3238 #define A4XX_GRAS_SU_POINT_SIZE__MASK				0xffffffff
3239 #define A4XX_GRAS_SU_POINT_SIZE__SHIFT				0
3240 static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val)
3241 {
3242 	return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK;
3243 }
3244 
3245 #define REG_A4XX_GRAS_ALPHA_CONTROL				0x00002073
3246 #define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE		0x00000004
3247 #define A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS		0x00000008
3248 
3249 #define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE			0x00002074
3250 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK			0xffffffff
3251 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT			0
3252 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
3253 {
3254 	return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
3255 }
3256 
3257 #define REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET			0x00002075
3258 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK			0xffffffff
3259 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT			0
3260 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
3261 {
3262 	return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
3263 }
3264 
3265 #define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP			0x00002076
3266 #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK			0xffffffff
3267 #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT			0
3268 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val)
3269 {
3270 	return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK;
3271 }
3272 
3273 #define REG_A4XX_GRAS_DEPTH_CONTROL				0x00002077
3274 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK			0x00000003
3275 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT			0
3276 static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val)
3277 {
3278 	return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK;
3279 }
3280 
3281 #define REG_A4XX_GRAS_SU_MODE_CONTROL				0x00002078
3282 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT			0x00000001
3283 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK			0x00000002
3284 #define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW			0x00000004
3285 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK		0x000007f8
3286 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT		3
3287 static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val)
3288 {
3289 	return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;
3290 }
3291 #define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET			0x00000800
3292 #define A4XX_GRAS_SU_MODE_CONTROL_MSAA_ENABLE			0x00002000
3293 #define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS		0x00100000
3294 
3295 #define REG_A4XX_GRAS_SC_CONTROL				0x0000207b
3296 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK			0x0000000c
3297 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT			2
3298 static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
3299 {
3300 	return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK;
3301 }
3302 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK			0x00000380
3303 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT		7
3304 static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val)
3305 {
3306 	return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK;
3307 }
3308 #define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE			0x00000800
3309 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK			0x0000f000
3310 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT			12
3311 static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val)
3312 {
3313 	return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK;
3314 }
3315 
3316 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL			0x0000207c
3317 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE	0x80000000
3318 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK			0x00007fff
3319 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT			0
3320 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
3321 {
3322 	return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
3323 }
3324 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK			0x7fff0000
3325 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT			16
3326 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
3327 {
3328 	return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
3329 }
3330 
3331 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR			0x0000207d
3332 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE	0x80000000
3333 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK			0x00007fff
3334 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT			0
3335 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
3336 {
3337 	return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
3338 }
3339 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK			0x7fff0000
3340 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT			16
3341 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
3342 {
3343 	return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
3344 }
3345 
3346 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR			0x0000209c
3347 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE	0x80000000
3348 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK			0x00007fff
3349 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT			0
3350 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
3351 {
3352 	return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
3353 }
3354 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK			0x7fff0000
3355 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT			16
3356 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
3357 {
3358 	return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
3359 }
3360 
3361 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL			0x0000209d
3362 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE	0x80000000
3363 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK			0x00007fff
3364 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT			0
3365 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
3366 {
3367 	return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
3368 }
3369 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK			0x7fff0000
3370 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT			16
3371 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
3372 {
3373 	return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
3374 }
3375 
3376 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR			0x0000209e
3377 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE	0x80000000
3378 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK			0x00007fff
3379 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT			0
3380 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val)
3381 {
3382 	return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK;
3383 }
3384 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK			0x7fff0000
3385 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT			16
3386 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val)
3387 {
3388 	return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK;
3389 }
3390 
3391 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL			0x0000209f
3392 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE	0x80000000
3393 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK			0x00007fff
3394 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT			0
3395 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val)
3396 {
3397 	return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK;
3398 }
3399 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK			0x7fff0000
3400 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT			16
3401 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val)
3402 {
3403 	return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK;
3404 }
3405 
3406 #define REG_A4XX_UCHE_CACHE_MODE_CONTROL			0x00000e80
3407 
3408 #define REG_A4XX_UCHE_TRAP_BASE_LO				0x00000e83
3409 
3410 #define REG_A4XX_UCHE_TRAP_BASE_HI				0x00000e84
3411 
3412 #define REG_A4XX_UCHE_CACHE_STATUS				0x00000e88
3413 
3414 #define REG_A4XX_UCHE_INVALIDATE0				0x00000e8a
3415 
3416 #define REG_A4XX_UCHE_INVALIDATE1				0x00000e8b
3417 
3418 #define REG_A4XX_UCHE_CACHE_WAYS_VFD				0x00000e8c
3419 
3420 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_0			0x00000e8e
3421 
3422 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_1			0x00000e8f
3423 
3424 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_2			0x00000e90
3425 
3426 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_3			0x00000e91
3427 
3428 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_4			0x00000e92
3429 
3430 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_5			0x00000e93
3431 
3432 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_6			0x00000e94
3433 
3434 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7			0x00000e95
3435 
3436 #define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD				0x00000e00
3437 
3438 #define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL				0x00000e04
3439 
3440 #define REG_A4XX_HLSQ_MODE_CONTROL				0x00000e05
3441 
3442 #define REG_A4XX_HLSQ_PERF_PIPE_MASK				0x00000e0e
3443 
3444 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_0			0x00000e06
3445 
3446 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_1			0x00000e07
3447 
3448 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_2			0x00000e08
3449 
3450 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_3			0x00000e09
3451 
3452 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_4			0x00000e0a
3453 
3454 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_5			0x00000e0b
3455 
3456 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_6			0x00000e0c
3457 
3458 #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_7			0x00000e0d
3459 
3460 #define REG_A4XX_HLSQ_CONTROL_0_REG				0x000023c0
3461 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK		0x00000010
3462 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT		4
3463 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
3464 {
3465 	return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
3466 }
3467 #define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE		0x00000040
3468 #define A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART			0x00000200
3469 #define A4XX_HLSQ_CONTROL_0_REG_RESERVED2			0x00000400
3470 #define A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE			0x04000000
3471 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK			0x08000000
3472 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT		27
3473 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val)
3474 {
3475 	return ((val) << A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK;
3476 }
3477 #define A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE		0x10000000
3478 #define A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE		0x20000000
3479 #define A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE			0x40000000
3480 #define A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT			0x80000000
3481 
3482 #define REG_A4XX_HLSQ_CONTROL_1_REG				0x000023c1
3483 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK		0x00000040
3484 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT		6
3485 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val)
3486 {
3487 	return ((val) << A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK;
3488 }
3489 #define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE		0x00000100
3490 #define A4XX_HLSQ_CONTROL_1_REG_RESERVED1			0x00000200
3491 #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK		0x00ff0000
3492 #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT		16
3493 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val)
3494 {
3495 	return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK;
3496 }
3497 #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK		0xff000000
3498 #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT		24
3499 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val)
3500 {
3501 	return ((val) << A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK;
3502 }
3503 
3504 #define REG_A4XX_HLSQ_CONTROL_2_REG				0x000023c2
3505 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK	0xfc000000
3506 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT	26
3507 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
3508 {
3509 	return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK;
3510 }
3511 #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK			0x000003fc
3512 #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT		2
3513 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
3514 {
3515 	return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
3516 }
3517 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK		0x0003fc00
3518 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT		10
3519 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val)
3520 {
3521 	return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK;
3522 }
3523 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK		0x03fc0000
3524 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT		18
3525 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val)
3526 {
3527 	return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK;
3528 }
3529 
3530 #define REG_A4XX_HLSQ_CONTROL_3_REG				0x000023c3
3531 #define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK			0x000000ff
3532 #define A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT			0
3533 static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val)
3534 {
3535 	return ((val) << A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_REGID__MASK;
3536 }
3537 
3538 #define REG_A4XX_HLSQ_CONTROL_4_REG				0x000023c4
3539 
3540 #define REG_A4XX_HLSQ_VS_CONTROL_REG				0x000023c5
3541 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK		0x000000ff
3542 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT		0
3543 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3544 {
3545 	return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK;
3546 }
3547 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK	0x0000ff00
3548 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT	8
3549 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3550 {
3551 	return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3552 }
3553 #define A4XX_HLSQ_VS_CONTROL_REG_ENABLED			0x00010000
3554 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK		0x00fe0000
3555 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT		17
3556 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3557 {
3558 	return ((val) << A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3559 }
3560 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK		0xff000000
3561 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT		24
3562 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3563 {
3564 	return ((val) << A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK;
3565 }
3566 
3567 #define REG_A4XX_HLSQ_FS_CONTROL_REG				0x000023c6
3568 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK		0x000000ff
3569 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT		0
3570 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3571 {
3572 	return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK;
3573 }
3574 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK	0x0000ff00
3575 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT	8
3576 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3577 {
3578 	return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3579 }
3580 #define A4XX_HLSQ_FS_CONTROL_REG_ENABLED			0x00010000
3581 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK		0x00fe0000
3582 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT		17
3583 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3584 {
3585 	return ((val) << A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3586 }
3587 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK		0xff000000
3588 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT		24
3589 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3590 {
3591 	return ((val) << A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK;
3592 }
3593 
3594 #define REG_A4XX_HLSQ_HS_CONTROL_REG				0x000023c7
3595 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK		0x000000ff
3596 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT		0
3597 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3598 {
3599 	return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK;
3600 }
3601 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK	0x0000ff00
3602 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT	8
3603 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3604 {
3605 	return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3606 }
3607 #define A4XX_HLSQ_HS_CONTROL_REG_ENABLED			0x00010000
3608 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK		0x00fe0000
3609 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT		17
3610 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3611 {
3612 	return ((val) << A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3613 }
3614 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK		0xff000000
3615 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT		24
3616 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3617 {
3618 	return ((val) << A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK;
3619 }
3620 
3621 #define REG_A4XX_HLSQ_DS_CONTROL_REG				0x000023c8
3622 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK		0x000000ff
3623 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT		0
3624 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3625 {
3626 	return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK;
3627 }
3628 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK	0x0000ff00
3629 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT	8
3630 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3631 {
3632 	return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3633 }
3634 #define A4XX_HLSQ_DS_CONTROL_REG_ENABLED			0x00010000
3635 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK		0x00fe0000
3636 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT		17
3637 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3638 {
3639 	return ((val) << A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3640 }
3641 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK		0xff000000
3642 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT		24
3643 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3644 {
3645 	return ((val) << A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK;
3646 }
3647 
3648 #define REG_A4XX_HLSQ_GS_CONTROL_REG				0x000023c9
3649 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK		0x000000ff
3650 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT		0
3651 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3652 {
3653 	return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK;
3654 }
3655 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK	0x0000ff00
3656 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT	8
3657 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3658 {
3659 	return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3660 }
3661 #define A4XX_HLSQ_GS_CONTROL_REG_ENABLED			0x00010000
3662 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK		0x00fe0000
3663 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT		17
3664 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3665 {
3666 	return ((val) << A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3667 }
3668 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK		0xff000000
3669 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT		24
3670 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3671 {
3672 	return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK;
3673 }
3674 
3675 #define REG_A4XX_HLSQ_CS_CONTROL				0x000023ca
3676 
3677 #define REG_A4XX_HLSQ_CL_NDRANGE_0				0x000023cd
3678 
3679 #define REG_A4XX_HLSQ_CL_NDRANGE_1				0x000023ce
3680 
3681 #define REG_A4XX_HLSQ_CL_NDRANGE_2				0x000023cf
3682 
3683 #define REG_A4XX_HLSQ_CL_NDRANGE_3				0x000023d0
3684 
3685 #define REG_A4XX_HLSQ_CL_NDRANGE_4				0x000023d1
3686 
3687 #define REG_A4XX_HLSQ_CL_NDRANGE_5				0x000023d2
3688 
3689 #define REG_A4XX_HLSQ_CL_NDRANGE_6				0x000023d3
3690 
3691 #define REG_A4XX_HLSQ_CL_CONTROL_0				0x000023d4
3692 
3693 #define REG_A4XX_HLSQ_CL_CONTROL_1				0x000023d5
3694 
3695 #define REG_A4XX_HLSQ_CL_KERNEL_CONST				0x000023d6
3696 
3697 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_X				0x000023d7
3698 
3699 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Y				0x000023d8
3700 
3701 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z				0x000023d9
3702 
3703 #define REG_A4XX_HLSQ_CL_WG_OFFSET				0x000023da
3704 
3705 #define REG_A4XX_HLSQ_UPDATE_CONTROL				0x000023db
3706 
3707 #define REG_A4XX_PC_BINNING_COMMAND				0x00000d00
3708 #define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE			0x00000001
3709 
3710 #define REG_A4XX_PC_TESSFACTOR_ADDR				0x00000d08
3711 
3712 #define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE			0x00000d0c
3713 
3714 #define REG_A4XX_PC_PERFCTR_PC_SEL_0				0x00000d10
3715 
3716 #define REG_A4XX_PC_PERFCTR_PC_SEL_1				0x00000d11
3717 
3718 #define REG_A4XX_PC_PERFCTR_PC_SEL_2				0x00000d12
3719 
3720 #define REG_A4XX_PC_PERFCTR_PC_SEL_3				0x00000d13
3721 
3722 #define REG_A4XX_PC_PERFCTR_PC_SEL_4				0x00000d14
3723 
3724 #define REG_A4XX_PC_PERFCTR_PC_SEL_5				0x00000d15
3725 
3726 #define REG_A4XX_PC_PERFCTR_PC_SEL_6				0x00000d16
3727 
3728 #define REG_A4XX_PC_PERFCTR_PC_SEL_7				0x00000d17
3729 
3730 #define REG_A4XX_PC_BIN_BASE					0x000021c0
3731 
3732 #define REG_A4XX_PC_VSTREAM_CONTROL				0x000021c2
3733 #define A4XX_PC_VSTREAM_CONTROL_SIZE__MASK			0x003f0000
3734 #define A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT			16
3735 static inline uint32_t A4XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val)
3736 {
3737 	return ((val) << A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A4XX_PC_VSTREAM_CONTROL_SIZE__MASK;
3738 }
3739 #define A4XX_PC_VSTREAM_CONTROL_N__MASK				0x07c00000
3740 #define A4XX_PC_VSTREAM_CONTROL_N__SHIFT			22
3741 static inline uint32_t A4XX_PC_VSTREAM_CONTROL_N(uint32_t val)
3742 {
3743 	return ((val) << A4XX_PC_VSTREAM_CONTROL_N__SHIFT) & A4XX_PC_VSTREAM_CONTROL_N__MASK;
3744 }
3745 
3746 #define REG_A4XX_PC_PRIM_VTX_CNTL				0x000021c4
3747 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK			0x0000000f
3748 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT			0
3749 static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val)
3750 {
3751 	return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK;
3752 }
3753 #define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART			0x00100000
3754 #define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST		0x02000000
3755 #define A4XX_PC_PRIM_VTX_CNTL_PSIZE				0x04000000
3756 
3757 #define REG_A4XX_PC_PRIM_VTX_CNTL2				0x000021c5
3758 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK	0x00000007
3759 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT	0
3760 static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
3761 {
3762 	return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK;
3763 }
3764 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK	0x00000038
3765 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT	3
3766 static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
3767 {
3768 	return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK;
3769 }
3770 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_ENABLE			0x00000040
3771 
3772 #define REG_A4XX_PC_RESTART_INDEX				0x000021c6
3773 
3774 #define REG_A4XX_PC_GS_PARAM					0x000021e5
3775 #define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK			0x000003ff
3776 #define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT			0
3777 static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
3778 {
3779 	return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK;
3780 }
3781 #define A4XX_PC_GS_PARAM_INVOCATIONS__MASK			0x0000f800
3782 #define A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT			11
3783 static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val)
3784 {
3785 	return ((val) << A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A4XX_PC_GS_PARAM_INVOCATIONS__MASK;
3786 }
3787 #define A4XX_PC_GS_PARAM_PRIMTYPE__MASK				0x01800000
3788 #define A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT			23
3789 static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
3790 {
3791 	return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK;
3792 }
3793 #define A4XX_PC_GS_PARAM_LAYER					0x80000000
3794 
3795 #define REG_A4XX_PC_HS_PARAM					0x000021e7
3796 #define A4XX_PC_HS_PARAM_VERTICES_OUT__MASK			0x0000003f
3797 #define A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT			0
3798 static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val)
3799 {
3800 	return ((val) << A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A4XX_PC_HS_PARAM_VERTICES_OUT__MASK;
3801 }
3802 #define A4XX_PC_HS_PARAM_SPACING__MASK				0x00600000
3803 #define A4XX_PC_HS_PARAM_SPACING__SHIFT				21
3804 static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
3805 {
3806 	return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK;
3807 }
3808 #define A4XX_PC_HS_PARAM_CW					0x00800000
3809 #define A4XX_PC_HS_PARAM_CONNECTED				0x01000000
3810 
3811 #define REG_A4XX_VBIF_VERSION					0x00003000
3812 
3813 #define REG_A4XX_VBIF_CLKON					0x00003001
3814 #define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS			0x00000001
3815 
3816 #define REG_A4XX_VBIF_ABIT_SORT					0x0000301c
3817 
3818 #define REG_A4XX_VBIF_ABIT_SORT_CONF				0x0000301d
3819 
3820 #define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN				0x0000302a
3821 
3822 #define REG_A4XX_VBIF_IN_RD_LIM_CONF0				0x0000302c
3823 
3824 #define REG_A4XX_VBIF_IN_RD_LIM_CONF1				0x0000302d
3825 
3826 #define REG_A4XX_VBIF_IN_WR_LIM_CONF0				0x00003030
3827 
3828 #define REG_A4XX_VBIF_IN_WR_LIM_CONF1				0x00003031
3829 
3830 #define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB			0x00003049
3831 
3832 #define REG_A4XX_VBIF_PERF_CNT_EN0				0x000030c0
3833 
3834 #define REG_A4XX_VBIF_PERF_CNT_EN1				0x000030c1
3835 
3836 #define REG_A4XX_VBIF_PERF_CNT_EN2				0x000030c2
3837 
3838 #define REG_A4XX_VBIF_PERF_CNT_EN3				0x000030c3
3839 
3840 #define REG_A4XX_VBIF_PERF_CNT_SEL0				0x000030d0
3841 
3842 #define REG_A4XX_VBIF_PERF_CNT_SEL1				0x000030d1
3843 
3844 #define REG_A4XX_VBIF_PERF_CNT_SEL2				0x000030d2
3845 
3846 #define REG_A4XX_VBIF_PERF_CNT_SEL3				0x000030d3
3847 
3848 #define REG_A4XX_VBIF_PERF_CNT_LOW0				0x000030d8
3849 
3850 #define REG_A4XX_VBIF_PERF_CNT_LOW1				0x000030d9
3851 
3852 #define REG_A4XX_VBIF_PERF_CNT_LOW2				0x000030da
3853 
3854 #define REG_A4XX_VBIF_PERF_CNT_LOW3				0x000030db
3855 
3856 #define REG_A4XX_VBIF_PERF_CNT_HIGH0				0x000030e0
3857 
3858 #define REG_A4XX_VBIF_PERF_CNT_HIGH1				0x000030e1
3859 
3860 #define REG_A4XX_VBIF_PERF_CNT_HIGH2				0x000030e2
3861 
3862 #define REG_A4XX_VBIF_PERF_CNT_HIGH3				0x000030e3
3863 
3864 #define REG_A4XX_VBIF_PERF_PWR_CNT_EN0				0x00003100
3865 
3866 #define REG_A4XX_VBIF_PERF_PWR_CNT_EN1				0x00003101
3867 
3868 #define REG_A4XX_VBIF_PERF_PWR_CNT_EN2				0x00003102
3869 
3870 #define REG_A4XX_UNKNOWN_0CC5					0x00000cc5
3871 
3872 #define REG_A4XX_UNKNOWN_0CC6					0x00000cc6
3873 
3874 #define REG_A4XX_UNKNOWN_0D01					0x00000d01
3875 
3876 #define REG_A4XX_UNKNOWN_0E42					0x00000e42
3877 
3878 #define REG_A4XX_UNKNOWN_0EC2					0x00000ec2
3879 
3880 #define REG_A4XX_UNKNOWN_2001					0x00002001
3881 
3882 #define REG_A4XX_UNKNOWN_209B					0x0000209b
3883 
3884 #define REG_A4XX_UNKNOWN_20EF					0x000020ef
3885 
3886 #define REG_A4XX_UNKNOWN_2152					0x00002152
3887 
3888 #define REG_A4XX_UNKNOWN_2153					0x00002153
3889 
3890 #define REG_A4XX_UNKNOWN_2154					0x00002154
3891 
3892 #define REG_A4XX_UNKNOWN_2155					0x00002155
3893 
3894 #define REG_A4XX_UNKNOWN_2156					0x00002156
3895 
3896 #define REG_A4XX_UNKNOWN_2157					0x00002157
3897 
3898 #define REG_A4XX_UNKNOWN_21C3					0x000021c3
3899 
3900 #define REG_A4XX_UNKNOWN_21E6					0x000021e6
3901 
3902 #define REG_A4XX_UNKNOWN_2209					0x00002209
3903 
3904 #define REG_A4XX_UNKNOWN_22D7					0x000022d7
3905 
3906 #define REG_A4XX_UNKNOWN_2352					0x00002352
3907 
3908 #define REG_A4XX_TEX_SAMP_0					0x00000000
3909 #define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR			0x00000001
3910 #define A4XX_TEX_SAMP_0_XY_MAG__MASK				0x00000006
3911 #define A4XX_TEX_SAMP_0_XY_MAG__SHIFT				1
3912 static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val)
3913 {
3914 	return ((val) << A4XX_TEX_SAMP_0_XY_MAG__SHIFT) & A4XX_TEX_SAMP_0_XY_MAG__MASK;
3915 }
3916 #define A4XX_TEX_SAMP_0_XY_MIN__MASK				0x00000018
3917 #define A4XX_TEX_SAMP_0_XY_MIN__SHIFT				3
3918 static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val)
3919 {
3920 	return ((val) << A4XX_TEX_SAMP_0_XY_MIN__SHIFT) & A4XX_TEX_SAMP_0_XY_MIN__MASK;
3921 }
3922 #define A4XX_TEX_SAMP_0_WRAP_S__MASK				0x000000e0
3923 #define A4XX_TEX_SAMP_0_WRAP_S__SHIFT				5
3924 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val)
3925 {
3926 	return ((val) << A4XX_TEX_SAMP_0_WRAP_S__SHIFT) & A4XX_TEX_SAMP_0_WRAP_S__MASK;
3927 }
3928 #define A4XX_TEX_SAMP_0_WRAP_T__MASK				0x00000700
3929 #define A4XX_TEX_SAMP_0_WRAP_T__SHIFT				8
3930 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val)
3931 {
3932 	return ((val) << A4XX_TEX_SAMP_0_WRAP_T__SHIFT) & A4XX_TEX_SAMP_0_WRAP_T__MASK;
3933 }
3934 #define A4XX_TEX_SAMP_0_WRAP_R__MASK				0x00003800
3935 #define A4XX_TEX_SAMP_0_WRAP_R__SHIFT				11
3936 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val)
3937 {
3938 	return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK;
3939 }
3940 #define A4XX_TEX_SAMP_0_ANISO__MASK				0x0001c000
3941 #define A4XX_TEX_SAMP_0_ANISO__SHIFT				14
3942 static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val)
3943 {
3944 	return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK;
3945 }
3946 #define A4XX_TEX_SAMP_0_LOD_BIAS__MASK				0xfff80000
3947 #define A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT				19
3948 static inline uint32_t A4XX_TEX_SAMP_0_LOD_BIAS(float val)
3949 {
3950 	return ((((int32_t)(val * 256.0))) << A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A4XX_TEX_SAMP_0_LOD_BIAS__MASK;
3951 }
3952 
3953 #define REG_A4XX_TEX_SAMP_1					0x00000001
3954 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK			0x0000000e
3955 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT			1
3956 static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
3957 {
3958 	return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
3959 }
3960 #define A4XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF			0x00000010
3961 #define A4XX_TEX_SAMP_1_UNNORM_COORDS				0x00000020
3962 #define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR			0x00000040
3963 #define A4XX_TEX_SAMP_1_MAX_LOD__MASK				0x000fff00
3964 #define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT				8
3965 static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val)
3966 {
3967 	return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK;
3968 }
3969 #define A4XX_TEX_SAMP_1_MIN_LOD__MASK				0xfff00000
3970 #define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT				20
3971 static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val)
3972 {
3973 	return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK;
3974 }
3975 
3976 #define REG_A4XX_TEX_CONST_0					0x00000000
3977 #define A4XX_TEX_CONST_0_TILED					0x00000001
3978 #define A4XX_TEX_CONST_0_SRGB					0x00000004
3979 #define A4XX_TEX_CONST_0_SWIZ_X__MASK				0x00000070
3980 #define A4XX_TEX_CONST_0_SWIZ_X__SHIFT				4
3981 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val)
3982 {
3983 	return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) & A4XX_TEX_CONST_0_SWIZ_X__MASK;
3984 }
3985 #define A4XX_TEX_CONST_0_SWIZ_Y__MASK				0x00000380
3986 #define A4XX_TEX_CONST_0_SWIZ_Y__SHIFT				7
3987 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val)
3988 {
3989 	return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Y__MASK;
3990 }
3991 #define A4XX_TEX_CONST_0_SWIZ_Z__MASK				0x00001c00
3992 #define A4XX_TEX_CONST_0_SWIZ_Z__SHIFT				10
3993 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val)
3994 {
3995 	return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Z__MASK;
3996 }
3997 #define A4XX_TEX_CONST_0_SWIZ_W__MASK				0x0000e000
3998 #define A4XX_TEX_CONST_0_SWIZ_W__SHIFT				13
3999 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val)
4000 {
4001 	return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK;
4002 }
4003 #define A4XX_TEX_CONST_0_MIPLVLS__MASK				0x000f0000
4004 #define A4XX_TEX_CONST_0_MIPLVLS__SHIFT				16
4005 static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val)
4006 {
4007 	return ((val) << A4XX_TEX_CONST_0_MIPLVLS__SHIFT) & A4XX_TEX_CONST_0_MIPLVLS__MASK;
4008 }
4009 #define A4XX_TEX_CONST_0_FMT__MASK				0x1fc00000
4010 #define A4XX_TEX_CONST_0_FMT__SHIFT				22
4011 static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val)
4012 {
4013 	return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK;
4014 }
4015 #define A4XX_TEX_CONST_0_TYPE__MASK				0x60000000
4016 #define A4XX_TEX_CONST_0_TYPE__SHIFT				29
4017 static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val)
4018 {
4019 	return ((val) << A4XX_TEX_CONST_0_TYPE__SHIFT) & A4XX_TEX_CONST_0_TYPE__MASK;
4020 }
4021 
4022 #define REG_A4XX_TEX_CONST_1					0x00000001
4023 #define A4XX_TEX_CONST_1_HEIGHT__MASK				0x00007fff
4024 #define A4XX_TEX_CONST_1_HEIGHT__SHIFT				0
4025 static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val)
4026 {
4027 	return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK;
4028 }
4029 #define A4XX_TEX_CONST_1_WIDTH__MASK				0x3fff8000
4030 #define A4XX_TEX_CONST_1_WIDTH__SHIFT				15
4031 static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val)
4032 {
4033 	return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK;
4034 }
4035 
4036 #define REG_A4XX_TEX_CONST_2					0x00000002
4037 #define A4XX_TEX_CONST_2_FETCHSIZE__MASK			0x0000000f
4038 #define A4XX_TEX_CONST_2_FETCHSIZE__SHIFT			0
4039 static inline uint32_t A4XX_TEX_CONST_2_FETCHSIZE(enum a4xx_tex_fetchsize val)
4040 {
4041 	return ((val) << A4XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A4XX_TEX_CONST_2_FETCHSIZE__MASK;
4042 }
4043 #define A4XX_TEX_CONST_2_PITCH__MASK				0x3ffffe00
4044 #define A4XX_TEX_CONST_2_PITCH__SHIFT				9
4045 static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val)
4046 {
4047 	return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) & A4XX_TEX_CONST_2_PITCH__MASK;
4048 }
4049 #define A4XX_TEX_CONST_2_SWAP__MASK				0xc0000000
4050 #define A4XX_TEX_CONST_2_SWAP__SHIFT				30
4051 static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
4052 {
4053 	return ((val) << A4XX_TEX_CONST_2_SWAP__SHIFT) & A4XX_TEX_CONST_2_SWAP__MASK;
4054 }
4055 
4056 #define REG_A4XX_TEX_CONST_3					0x00000003
4057 #define A4XX_TEX_CONST_3_LAYERSZ__MASK				0x00003fff
4058 #define A4XX_TEX_CONST_3_LAYERSZ__SHIFT				0
4059 static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val)
4060 {
4061 	return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK;
4062 }
4063 #define A4XX_TEX_CONST_3_DEPTH__MASK				0x7ffc0000
4064 #define A4XX_TEX_CONST_3_DEPTH__SHIFT				18
4065 static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val)
4066 {
4067 	return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK;
4068 }
4069 
4070 #define REG_A4XX_TEX_CONST_4					0x00000004
4071 #define A4XX_TEX_CONST_4_LAYERSZ__MASK				0x0000000f
4072 #define A4XX_TEX_CONST_4_LAYERSZ__SHIFT				0
4073 static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val)
4074 {
4075 	return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK;
4076 }
4077 #define A4XX_TEX_CONST_4_BASE__MASK				0xffffffe0
4078 #define A4XX_TEX_CONST_4_BASE__SHIFT				5
4079 static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val)
4080 {
4081 	return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK;
4082 }
4083 
4084 #define REG_A4XX_TEX_CONST_5					0x00000005
4085 
4086 #define REG_A4XX_TEX_CONST_6					0x00000006
4087 
4088 #define REG_A4XX_TEX_CONST_7					0x00000007
4089 
4090 
4091 #endif /* A4XX_XML */
4092