1bc00ae02SRob Clark #ifndef A4XX_XML 2bc00ae02SRob Clark #define A4XX_XML 3bc00ae02SRob Clark 4bc00ae02SRob Clark /* Autogenerated file, DO NOT EDIT manually! 5bc00ae02SRob Clark 6bc00ae02SRob Clark This file was generated by the rules-ng-ng headergen tool in this git repository: 7bc00ae02SRob Clark http://github.com/freedreno/envytools/ 8bc00ae02SRob Clark git clone https://github.com/freedreno/envytools.git 9bc00ae02SRob Clark 10bc00ae02SRob Clark The rules-ng-ng source files this header was generated from are: 11c28c82e9SRob Clark - /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14) 12c28c82e9SRob Clark - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14) 13c28c82e9SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14) 14c28c82e9SRob Clark - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14) 15c28c82e9SRob Clark - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14) 16c28c82e9SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14) 17c28c82e9SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14) 18c28c82e9SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14) 19c28c82e9SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14) 20c28c82e9SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14) 21c28c82e9SRob Clark - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14) 22c28c82e9SRob Clark - /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14) 23c28c82e9SRob Clark - /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14) 24bc00ae02SRob Clark 25c28c82e9SRob Clark Copyright (C) 2013-2020 by the following authors: 26bc00ae02SRob Clark - Rob Clark <robdclark@gmail.com> (robclark) 27a2272e48SRob Clark - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 28bc00ae02SRob Clark 29bc00ae02SRob Clark Permission is hereby granted, free of charge, to any person obtaining 30bc00ae02SRob Clark a copy of this software and associated documentation files (the 31bc00ae02SRob Clark "Software"), to deal in the Software without restriction, including 32bc00ae02SRob Clark without limitation the rights to use, copy, modify, merge, publish, 33bc00ae02SRob Clark distribute, sublicense, and/or sell copies of the Software, and to 34bc00ae02SRob Clark permit persons to whom the Software is furnished to do so, subject to 35bc00ae02SRob Clark the following conditions: 36bc00ae02SRob Clark 37bc00ae02SRob Clark The above copyright notice and this permission notice (including the 38bc00ae02SRob Clark next paragraph) shall be included in all copies or substantial 39bc00ae02SRob Clark portions of the Software. 40bc00ae02SRob Clark 41bc00ae02SRob Clark THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 42bc00ae02SRob Clark EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 43bc00ae02SRob Clark MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 44bc00ae02SRob Clark IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 45bc00ae02SRob Clark LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 46bc00ae02SRob Clark OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 47bc00ae02SRob Clark WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 48bc00ae02SRob Clark */ 49bc00ae02SRob Clark 50bc00ae02SRob Clark 51bc00ae02SRob Clark enum a4xx_color_fmt { 52bc00ae02SRob Clark RB4_A8_UNORM = 1, 53af6cb4c1SRob Clark RB4_R8_UNORM = 2, 54a26ae754SRob Clark RB4_R8_SNORM = 3, 55a26ae754SRob Clark RB4_R8_UINT = 4, 56a26ae754SRob Clark RB4_R8_SINT = 5, 57af6cb4c1SRob Clark RB4_R4G4B4A4_UNORM = 8, 58af6cb4c1SRob Clark RB4_R5G5B5A1_UNORM = 10, 59a2272e48SRob Clark RB4_R5G6B5_UNORM = 14, 60af6cb4c1SRob Clark RB4_R8G8_UNORM = 15, 61af6cb4c1SRob Clark RB4_R8G8_SNORM = 16, 62af6cb4c1SRob Clark RB4_R8G8_UINT = 17, 63af6cb4c1SRob Clark RB4_R8G8_SINT = 18, 64a2272e48SRob Clark RB4_R16_UNORM = 19, 65a2272e48SRob Clark RB4_R16_SNORM = 20, 66af6cb4c1SRob Clark RB4_R16_FLOAT = 21, 67af6cb4c1SRob Clark RB4_R16_UINT = 22, 68af6cb4c1SRob Clark RB4_R16_SINT = 23, 69bc00ae02SRob Clark RB4_R8G8B8_UNORM = 25, 70bc00ae02SRob Clark RB4_R8G8B8A8_UNORM = 26, 71af6cb4c1SRob Clark RB4_R8G8B8A8_SNORM = 28, 72af6cb4c1SRob Clark RB4_R8G8B8A8_UINT = 29, 73af6cb4c1SRob Clark RB4_R8G8B8A8_SINT = 30, 74af6cb4c1SRob Clark RB4_R10G10B10A2_UNORM = 31, 75af6cb4c1SRob Clark RB4_R10G10B10A2_UINT = 34, 76af6cb4c1SRob Clark RB4_R11G11B10_FLOAT = 39, 77a2272e48SRob Clark RB4_R16G16_UNORM = 40, 78a2272e48SRob Clark RB4_R16G16_SNORM = 41, 79af6cb4c1SRob Clark RB4_R16G16_FLOAT = 42, 80af6cb4c1SRob Clark RB4_R16G16_UINT = 43, 81af6cb4c1SRob Clark RB4_R16G16_SINT = 44, 82af6cb4c1SRob Clark RB4_R32_FLOAT = 45, 83af6cb4c1SRob Clark RB4_R32_UINT = 46, 84af6cb4c1SRob Clark RB4_R32_SINT = 47, 85a2272e48SRob Clark RB4_R16G16B16A16_UNORM = 52, 86a2272e48SRob Clark RB4_R16G16B16A16_SNORM = 53, 87af6cb4c1SRob Clark RB4_R16G16B16A16_FLOAT = 54, 88af6cb4c1SRob Clark RB4_R16G16B16A16_UINT = 55, 89af6cb4c1SRob Clark RB4_R16G16B16A16_SINT = 56, 90af6cb4c1SRob Clark RB4_R32G32_FLOAT = 57, 91af6cb4c1SRob Clark RB4_R32G32_UINT = 58, 92af6cb4c1SRob Clark RB4_R32G32_SINT = 59, 93af6cb4c1SRob Clark RB4_R32G32B32A32_FLOAT = 60, 94af6cb4c1SRob Clark RB4_R32G32B32A32_UINT = 61, 95af6cb4c1SRob Clark RB4_R32G32B32A32_SINT = 62, 96c28c82e9SRob Clark RB4_NONE = 255, 97bc00ae02SRob Clark }; 98bc00ae02SRob Clark 99bc00ae02SRob Clark enum a4xx_tile_mode { 100bc00ae02SRob Clark TILE4_LINEAR = 0, 101a26ae754SRob Clark TILE4_2 = 2, 102bc00ae02SRob Clark TILE4_3 = 3, 103bc00ae02SRob Clark }; 104bc00ae02SRob Clark 105bc00ae02SRob Clark enum a4xx_vtx_fmt { 1068a264743SRob Clark VFMT4_32_FLOAT = 1, 1078a264743SRob Clark VFMT4_32_32_FLOAT = 2, 1088a264743SRob Clark VFMT4_32_32_32_FLOAT = 3, 1098a264743SRob Clark VFMT4_32_32_32_32_FLOAT = 4, 1108a264743SRob Clark VFMT4_16_FLOAT = 5, 1118a264743SRob Clark VFMT4_16_16_FLOAT = 6, 1128a264743SRob Clark VFMT4_16_16_16_FLOAT = 7, 1138a264743SRob Clark VFMT4_16_16_16_16_FLOAT = 8, 1148a264743SRob Clark VFMT4_32_FIXED = 9, 1158a264743SRob Clark VFMT4_32_32_FIXED = 10, 1168a264743SRob Clark VFMT4_32_32_32_FIXED = 11, 1178a264743SRob Clark VFMT4_32_32_32_32_FIXED = 12, 118a2272e48SRob Clark VFMT4_11_11_10_FLOAT = 13, 1198a264743SRob Clark VFMT4_16_SINT = 16, 1208a264743SRob Clark VFMT4_16_16_SINT = 17, 1218a264743SRob Clark VFMT4_16_16_16_SINT = 18, 1228a264743SRob Clark VFMT4_16_16_16_16_SINT = 19, 1238a264743SRob Clark VFMT4_16_UINT = 20, 1248a264743SRob Clark VFMT4_16_16_UINT = 21, 1258a264743SRob Clark VFMT4_16_16_16_UINT = 22, 1268a264743SRob Clark VFMT4_16_16_16_16_UINT = 23, 1278a264743SRob Clark VFMT4_16_SNORM = 24, 1288a264743SRob Clark VFMT4_16_16_SNORM = 25, 1298a264743SRob Clark VFMT4_16_16_16_SNORM = 26, 1308a264743SRob Clark VFMT4_16_16_16_16_SNORM = 27, 1318a264743SRob Clark VFMT4_16_UNORM = 28, 1328a264743SRob Clark VFMT4_16_16_UNORM = 29, 1338a264743SRob Clark VFMT4_16_16_16_UNORM = 30, 1348a264743SRob Clark VFMT4_16_16_16_16_UNORM = 31, 135af6cb4c1SRob Clark VFMT4_32_UINT = 32, 136af6cb4c1SRob Clark VFMT4_32_32_UINT = 33, 137af6cb4c1SRob Clark VFMT4_32_32_32_UINT = 34, 138af6cb4c1SRob Clark VFMT4_32_32_32_32_UINT = 35, 139af6cb4c1SRob Clark VFMT4_32_SINT = 36, 1408a264743SRob Clark VFMT4_32_32_SINT = 37, 141af6cb4c1SRob Clark VFMT4_32_32_32_SINT = 38, 142af6cb4c1SRob Clark VFMT4_32_32_32_32_SINT = 39, 1438a264743SRob Clark VFMT4_8_UINT = 40, 1448a264743SRob Clark VFMT4_8_8_UINT = 41, 1458a264743SRob Clark VFMT4_8_8_8_UINT = 42, 1468a264743SRob Clark VFMT4_8_8_8_8_UINT = 43, 1478a264743SRob Clark VFMT4_8_UNORM = 44, 1488a264743SRob Clark VFMT4_8_8_UNORM = 45, 1498a264743SRob Clark VFMT4_8_8_8_UNORM = 46, 1508a264743SRob Clark VFMT4_8_8_8_8_UNORM = 47, 1518a264743SRob Clark VFMT4_8_SINT = 48, 1528a264743SRob Clark VFMT4_8_8_SINT = 49, 1538a264743SRob Clark VFMT4_8_8_8_SINT = 50, 1548a264743SRob Clark VFMT4_8_8_8_8_SINT = 51, 1558a264743SRob Clark VFMT4_8_SNORM = 52, 1568a264743SRob Clark VFMT4_8_8_SNORM = 53, 1578a264743SRob Clark VFMT4_8_8_8_SNORM = 54, 1588a264743SRob Clark VFMT4_8_8_8_8_SNORM = 55, 159a2272e48SRob Clark VFMT4_10_10_10_2_UINT = 56, 160a2272e48SRob Clark VFMT4_10_10_10_2_UNORM = 57, 161a2272e48SRob Clark VFMT4_10_10_10_2_SINT = 58, 162a2272e48SRob Clark VFMT4_10_10_10_2_SNORM = 59, 163a2272e48SRob Clark VFMT4_2_10_10_10_UINT = 60, 164a2272e48SRob Clark VFMT4_2_10_10_10_UNORM = 61, 165a2272e48SRob Clark VFMT4_2_10_10_10_SINT = 62, 166a2272e48SRob Clark VFMT4_2_10_10_10_SNORM = 63, 167c28c82e9SRob Clark VFMT4_NONE = 255, 168bc00ae02SRob Clark }; 169bc00ae02SRob Clark 170bc00ae02SRob Clark enum a4xx_tex_fmt { 1718a264743SRob Clark TFMT4_A8_UNORM = 3, 1728a264743SRob Clark TFMT4_8_UNORM = 4, 1738217e97aSRob Clark TFMT4_8_SNORM = 5, 1748217e97aSRob Clark TFMT4_8_UINT = 6, 1758217e97aSRob Clark TFMT4_8_SINT = 7, 176a2272e48SRob Clark TFMT4_4_4_4_4_UNORM = 8, 177a2272e48SRob Clark TFMT4_5_5_5_1_UNORM = 9, 178a2272e48SRob Clark TFMT4_5_6_5_UNORM = 11, 179a2272e48SRob Clark TFMT4_L8_A8_UNORM = 13, 180a2272e48SRob Clark TFMT4_8_8_UNORM = 14, 181a2272e48SRob Clark TFMT4_8_8_SNORM = 15, 182a2272e48SRob Clark TFMT4_8_8_UINT = 16, 183af6cb4c1SRob Clark TFMT4_8_8_SINT = 17, 184a2272e48SRob Clark TFMT4_16_UNORM = 18, 185a2272e48SRob Clark TFMT4_16_SNORM = 19, 1868a264743SRob Clark TFMT4_16_FLOAT = 20, 187a2272e48SRob Clark TFMT4_16_UINT = 21, 188a2272e48SRob Clark TFMT4_16_SINT = 22, 189a2272e48SRob Clark TFMT4_8_8_8_8_UNORM = 28, 190a2272e48SRob Clark TFMT4_8_8_8_8_SNORM = 29, 191a2272e48SRob Clark TFMT4_8_8_8_8_UINT = 30, 192a2272e48SRob Clark TFMT4_8_8_8_8_SINT = 31, 193af6cb4c1SRob Clark TFMT4_9_9_9_E5_FLOAT = 32, 194a2272e48SRob Clark TFMT4_10_10_10_2_UNORM = 33, 195a2272e48SRob Clark TFMT4_10_10_10_2_UINT = 34, 196af6cb4c1SRob Clark TFMT4_11_11_10_FLOAT = 37, 197a2272e48SRob Clark TFMT4_16_16_UNORM = 38, 198a2272e48SRob Clark TFMT4_16_16_SNORM = 39, 199a2272e48SRob Clark TFMT4_16_16_FLOAT = 40, 200a2272e48SRob Clark TFMT4_16_16_UINT = 41, 201a2272e48SRob Clark TFMT4_16_16_SINT = 42, 202a2272e48SRob Clark TFMT4_32_FLOAT = 43, 203a2272e48SRob Clark TFMT4_32_UINT = 44, 204a2272e48SRob Clark TFMT4_32_SINT = 45, 205a2272e48SRob Clark TFMT4_16_16_16_16_UNORM = 51, 206a2272e48SRob Clark TFMT4_16_16_16_16_SNORM = 52, 207a2272e48SRob Clark TFMT4_16_16_16_16_FLOAT = 53, 208a2272e48SRob Clark TFMT4_16_16_16_16_UINT = 54, 209a2272e48SRob Clark TFMT4_16_16_16_16_SINT = 55, 210a2272e48SRob Clark TFMT4_32_32_FLOAT = 56, 211a2272e48SRob Clark TFMT4_32_32_UINT = 57, 212a2272e48SRob Clark TFMT4_32_32_SINT = 58, 213a2272e48SRob Clark TFMT4_32_32_32_FLOAT = 59, 214a2272e48SRob Clark TFMT4_32_32_32_UINT = 60, 215a2272e48SRob Clark TFMT4_32_32_32_SINT = 61, 216a2272e48SRob Clark TFMT4_32_32_32_32_FLOAT = 63, 217a2272e48SRob Clark TFMT4_32_32_32_32_UINT = 64, 218a2272e48SRob Clark TFMT4_32_32_32_32_SINT = 65, 219a2272e48SRob Clark TFMT4_X8Z24_UNORM = 71, 220a2272e48SRob Clark TFMT4_DXT1 = 86, 221a2272e48SRob Clark TFMT4_DXT3 = 87, 222a2272e48SRob Clark TFMT4_DXT5 = 88, 223a2272e48SRob Clark TFMT4_RGTC1_UNORM = 90, 224a2272e48SRob Clark TFMT4_RGTC1_SNORM = 91, 225a2272e48SRob Clark TFMT4_RGTC2_UNORM = 94, 226a2272e48SRob Clark TFMT4_RGTC2_SNORM = 95, 227a2272e48SRob Clark TFMT4_BPTC_UFLOAT = 97, 228a2272e48SRob Clark TFMT4_BPTC_FLOAT = 98, 229a2272e48SRob Clark TFMT4_BPTC = 99, 230af6cb4c1SRob Clark TFMT4_ATC_RGB = 100, 231af6cb4c1SRob Clark TFMT4_ATC_RGBA_EXPLICIT = 101, 232af6cb4c1SRob Clark TFMT4_ATC_RGBA_INTERPOLATED = 102, 233af6cb4c1SRob Clark TFMT4_ETC2_RG11_UNORM = 103, 234af6cb4c1SRob Clark TFMT4_ETC2_RG11_SNORM = 104, 235af6cb4c1SRob Clark TFMT4_ETC2_R11_UNORM = 105, 236af6cb4c1SRob Clark TFMT4_ETC2_R11_SNORM = 106, 237af6cb4c1SRob Clark TFMT4_ETC1 = 107, 238af6cb4c1SRob Clark TFMT4_ETC2_RGB8 = 108, 239af6cb4c1SRob Clark TFMT4_ETC2_RGBA8 = 109, 240af6cb4c1SRob Clark TFMT4_ETC2_RGB8A1 = 110, 241af6cb4c1SRob Clark TFMT4_ASTC_4x4 = 111, 242af6cb4c1SRob Clark TFMT4_ASTC_5x4 = 112, 243af6cb4c1SRob Clark TFMT4_ASTC_5x5 = 113, 244af6cb4c1SRob Clark TFMT4_ASTC_6x5 = 114, 245af6cb4c1SRob Clark TFMT4_ASTC_6x6 = 115, 246af6cb4c1SRob Clark TFMT4_ASTC_8x5 = 116, 247af6cb4c1SRob Clark TFMT4_ASTC_8x6 = 117, 248af6cb4c1SRob Clark TFMT4_ASTC_8x8 = 118, 249af6cb4c1SRob Clark TFMT4_ASTC_10x5 = 119, 250af6cb4c1SRob Clark TFMT4_ASTC_10x6 = 120, 251af6cb4c1SRob Clark TFMT4_ASTC_10x8 = 121, 252af6cb4c1SRob Clark TFMT4_ASTC_10x10 = 122, 253af6cb4c1SRob Clark TFMT4_ASTC_12x10 = 123, 254af6cb4c1SRob Clark TFMT4_ASTC_12x12 = 124, 255c28c82e9SRob Clark TFMT4_NONE = 255, 256bc00ae02SRob Clark }; 257bc00ae02SRob Clark 258bc00ae02SRob Clark enum a4xx_depth_format { 259bc00ae02SRob Clark DEPTH4_NONE = 0, 260bc00ae02SRob Clark DEPTH4_16 = 1, 261bc00ae02SRob Clark DEPTH4_24_8 = 2, 2622d3584ebSRob Clark DEPTH4_32 = 3, 263bc00ae02SRob Clark }; 264bc00ae02SRob Clark 265a2272e48SRob Clark enum a4xx_ccu_perfcounter_select { 266a2272e48SRob Clark CCU_BUSY_CYCLES = 0, 267a2272e48SRob Clark CCU_RB_DEPTH_RETURN_STALL = 2, 268a2272e48SRob Clark CCU_RB_COLOR_RETURN_STALL = 3, 269a2272e48SRob Clark CCU_DEPTH_BLOCKS = 6, 270a2272e48SRob Clark CCU_COLOR_BLOCKS = 7, 271a2272e48SRob Clark CCU_DEPTH_BLOCK_HIT = 8, 272a2272e48SRob Clark CCU_COLOR_BLOCK_HIT = 9, 273a2272e48SRob Clark CCU_DEPTH_FLAG1_COUNT = 10, 274a2272e48SRob Clark CCU_DEPTH_FLAG2_COUNT = 11, 275a2272e48SRob Clark CCU_DEPTH_FLAG3_COUNT = 12, 276a2272e48SRob Clark CCU_DEPTH_FLAG4_COUNT = 13, 277a2272e48SRob Clark CCU_COLOR_FLAG1_COUNT = 14, 278a2272e48SRob Clark CCU_COLOR_FLAG2_COUNT = 15, 279a2272e48SRob Clark CCU_COLOR_FLAG3_COUNT = 16, 280a2272e48SRob Clark CCU_COLOR_FLAG4_COUNT = 17, 281a2272e48SRob Clark CCU_PARTIAL_BLOCK_READ = 18, 282a2272e48SRob Clark }; 283a2272e48SRob Clark 284a2272e48SRob Clark enum a4xx_cp_perfcounter_select { 285a2272e48SRob Clark CP_ALWAYS_COUNT = 0, 286a2272e48SRob Clark CP_BUSY = 1, 287a2272e48SRob Clark CP_PFP_IDLE = 2, 288a2272e48SRob Clark CP_PFP_BUSY_WORKING = 3, 289a2272e48SRob Clark CP_PFP_STALL_CYCLES_ANY = 4, 290a2272e48SRob Clark CP_PFP_STARVE_CYCLES_ANY = 5, 291a2272e48SRob Clark CP_PFP_STARVED_PER_LOAD_ADDR = 6, 292a2272e48SRob Clark CP_PFP_STALLED_PER_STORE_ADDR = 7, 293a2272e48SRob Clark CP_PFP_PC_PROFILE = 8, 294a2272e48SRob Clark CP_PFP_MATCH_PM4_PKT_PROFILE = 9, 295a2272e48SRob Clark CP_PFP_COND_INDIRECT_DISCARDED = 10, 296a2272e48SRob Clark CP_LONG_RESUMPTIONS = 11, 297a2272e48SRob Clark CP_RESUME_CYCLES = 12, 298a2272e48SRob Clark CP_RESUME_TO_BOUNDARY_CYCLES = 13, 299a2272e48SRob Clark CP_LONG_PREEMPTIONS = 14, 300a2272e48SRob Clark CP_PREEMPT_CYCLES = 15, 301a2272e48SRob Clark CP_PREEMPT_TO_BOUNDARY_CYCLES = 16, 302a2272e48SRob Clark CP_ME_FIFO_EMPTY_PFP_IDLE = 17, 303a2272e48SRob Clark CP_ME_FIFO_EMPTY_PFP_BUSY = 18, 304a2272e48SRob Clark CP_ME_FIFO_NOT_EMPTY_NOT_FULL = 19, 305a2272e48SRob Clark CP_ME_FIFO_FULL_ME_BUSY = 20, 306a2272e48SRob Clark CP_ME_FIFO_FULL_ME_NON_WORKING = 21, 307a2272e48SRob Clark CP_ME_WAITING_FOR_PACKETS = 22, 308a2272e48SRob Clark CP_ME_BUSY_WORKING = 23, 309a2272e48SRob Clark CP_ME_STARVE_CYCLES_ANY = 24, 310a2272e48SRob Clark CP_ME_STARVE_CYCLES_PER_PROFILE = 25, 311a2272e48SRob Clark CP_ME_STALL_CYCLES_PER_PROFILE = 26, 312a2272e48SRob Clark CP_ME_PC_PROFILE = 27, 313a2272e48SRob Clark CP_RCIU_FIFO_EMPTY = 28, 314a2272e48SRob Clark CP_RCIU_FIFO_NOT_EMPTY_NOT_FULL = 29, 315a2272e48SRob Clark CP_RCIU_FIFO_FULL = 30, 316a2272e48SRob Clark CP_RCIU_FIFO_FULL_NO_CONTEXT = 31, 317a2272e48SRob Clark CP_RCIU_FIFO_FULL_AHB_MASTER = 32, 318a2272e48SRob Clark CP_RCIU_FIFO_FULL_OTHER = 33, 319a2272e48SRob Clark CP_AHB_IDLE = 34, 320a2272e48SRob Clark CP_AHB_STALL_ON_GRANT_NO_SPLIT = 35, 321a2272e48SRob Clark CP_AHB_STALL_ON_GRANT_SPLIT = 36, 322a2272e48SRob Clark CP_AHB_STALL_ON_GRANT_SPLIT_PROFILE = 37, 323a2272e48SRob Clark CP_AHB_BUSY_WORKING = 38, 324a2272e48SRob Clark CP_AHB_BUSY_STALL_ON_HRDY = 39, 325a2272e48SRob Clark CP_AHB_BUSY_STALL_ON_HRDY_PROFILE = 40, 326a2272e48SRob Clark }; 327a2272e48SRob Clark 328a2272e48SRob Clark enum a4xx_gras_ras_perfcounter_select { 329a2272e48SRob Clark RAS_SUPER_TILES = 0, 330a2272e48SRob Clark RAS_8X8_TILES = 1, 331a2272e48SRob Clark RAS_4X4_TILES = 2, 332a2272e48SRob Clark RAS_BUSY_CYCLES = 3, 333a2272e48SRob Clark RAS_STALL_CYCLES_BY_RB = 4, 334a2272e48SRob Clark RAS_STALL_CYCLES_BY_VSC = 5, 335a2272e48SRob Clark RAS_STARVE_CYCLES_BY_TSE = 6, 336a2272e48SRob Clark RAS_SUPERTILE_CYCLES = 7, 337a2272e48SRob Clark RAS_TILE_CYCLES = 8, 338a2272e48SRob Clark RAS_FULLY_COVERED_SUPER_TILES = 9, 339a2272e48SRob Clark RAS_FULLY_COVERED_8X8_TILES = 10, 340a2272e48SRob Clark RAS_4X4_PRIM = 11, 341a2272e48SRob Clark RAS_8X4_4X8_PRIM = 12, 342a2272e48SRob Clark RAS_8X8_PRIM = 13, 343a2272e48SRob Clark }; 344a2272e48SRob Clark 345a2272e48SRob Clark enum a4xx_gras_tse_perfcounter_select { 346a2272e48SRob Clark TSE_INPUT_PRIM = 0, 347a2272e48SRob Clark TSE_INPUT_NULL_PRIM = 1, 348a2272e48SRob Clark TSE_TRIVAL_REJ_PRIM = 2, 349a2272e48SRob Clark TSE_CLIPPED_PRIM = 3, 350a2272e48SRob Clark TSE_NEW_PRIM = 4, 351a2272e48SRob Clark TSE_ZERO_AREA_PRIM = 5, 352a2272e48SRob Clark TSE_FACENESS_CULLED_PRIM = 6, 353a2272e48SRob Clark TSE_ZERO_PIXEL_PRIM = 7, 354a2272e48SRob Clark TSE_OUTPUT_NULL_PRIM = 8, 355a2272e48SRob Clark TSE_OUTPUT_VISIBLE_PRIM = 9, 356a2272e48SRob Clark TSE_PRE_CLIP_PRIM = 10, 357a2272e48SRob Clark TSE_POST_CLIP_PRIM = 11, 358a2272e48SRob Clark TSE_BUSY_CYCLES = 12, 359a2272e48SRob Clark TSE_PC_STARVE = 13, 360a2272e48SRob Clark TSE_RAS_STALL = 14, 361a2272e48SRob Clark TSE_STALL_BARYPLANE_FIFO_FULL = 15, 362a2272e48SRob Clark TSE_STALL_ZPLANE_FIFO_FULL = 16, 363a2272e48SRob Clark }; 364a2272e48SRob Clark 365a2272e48SRob Clark enum a4xx_hlsq_perfcounter_select { 366a2272e48SRob Clark HLSQ_SP_VS_STAGE_CONSTANT = 0, 367a2272e48SRob Clark HLSQ_SP_VS_STAGE_INSTRUCTIONS = 1, 368a2272e48SRob Clark HLSQ_SP_FS_STAGE_CONSTANT = 2, 369a2272e48SRob Clark HLSQ_SP_FS_STAGE_INSTRUCTIONS = 3, 370a2272e48SRob Clark HLSQ_TP_STATE = 4, 371a2272e48SRob Clark HLSQ_QUADS = 5, 372a2272e48SRob Clark HLSQ_PIXELS = 6, 373a2272e48SRob Clark HLSQ_VERTICES = 7, 374a2272e48SRob Clark HLSQ_SP_VS_STAGE_DATA_BYTES = 13, 375a2272e48SRob Clark HLSQ_SP_FS_STAGE_DATA_BYTES = 14, 376a2272e48SRob Clark HLSQ_BUSY_CYCLES = 15, 377a2272e48SRob Clark HLSQ_STALL_CYCLES_SP_STATE = 16, 378a2272e48SRob Clark HLSQ_STALL_CYCLES_SP_VS_STAGE = 17, 379a2272e48SRob Clark HLSQ_STALL_CYCLES_SP_FS_STAGE = 18, 380a2272e48SRob Clark HLSQ_STALL_CYCLES_UCHE = 19, 381a2272e48SRob Clark HLSQ_RBBM_LOAD_CYCLES = 20, 382a2272e48SRob Clark HLSQ_DI_TO_VS_START_SP = 21, 383a2272e48SRob Clark HLSQ_DI_TO_FS_START_SP = 22, 384a2272e48SRob Clark HLSQ_VS_STAGE_START_TO_DONE_SP = 23, 385a2272e48SRob Clark HLSQ_FS_STAGE_START_TO_DONE_SP = 24, 386a2272e48SRob Clark HLSQ_SP_STATE_COPY_CYCLES_VS_STAGE = 25, 387a2272e48SRob Clark HLSQ_SP_STATE_COPY_CYCLES_FS_STAGE = 26, 388a2272e48SRob Clark HLSQ_UCHE_LATENCY_CYCLES = 27, 389a2272e48SRob Clark HLSQ_UCHE_LATENCY_COUNT = 28, 390a2272e48SRob Clark HLSQ_STARVE_CYCLES_VFD = 29, 391a2272e48SRob Clark }; 392a2272e48SRob Clark 393a2272e48SRob Clark enum a4xx_pc_perfcounter_select { 394a2272e48SRob Clark PC_VIS_STREAMS_LOADED = 0, 395a2272e48SRob Clark PC_VPC_PRIMITIVES = 2, 396a2272e48SRob Clark PC_DEAD_PRIM = 3, 397a2272e48SRob Clark PC_LIVE_PRIM = 4, 398a2272e48SRob Clark PC_DEAD_DRAWCALLS = 5, 399a2272e48SRob Clark PC_LIVE_DRAWCALLS = 6, 400a2272e48SRob Clark PC_VERTEX_MISSES = 7, 401a2272e48SRob Clark PC_STALL_CYCLES_VFD = 9, 402a2272e48SRob Clark PC_STALL_CYCLES_TSE = 10, 403a2272e48SRob Clark PC_STALL_CYCLES_UCHE = 11, 404a2272e48SRob Clark PC_WORKING_CYCLES = 12, 405a2272e48SRob Clark PC_IA_VERTICES = 13, 406a2272e48SRob Clark PC_GS_PRIMITIVES = 14, 407a2272e48SRob Clark PC_HS_INVOCATIONS = 15, 408a2272e48SRob Clark PC_DS_INVOCATIONS = 16, 409a2272e48SRob Clark PC_DS_PRIMITIVES = 17, 410a2272e48SRob Clark PC_STARVE_CYCLES_FOR_INDEX = 20, 411a2272e48SRob Clark PC_STARVE_CYCLES_FOR_TESS_FACTOR = 21, 412a2272e48SRob Clark PC_STARVE_CYCLES_FOR_VIZ_STREAM = 22, 413a2272e48SRob Clark PC_STALL_CYCLES_TESS = 23, 414a2272e48SRob Clark PC_STARVE_CYCLES_FOR_POSITION = 24, 415a2272e48SRob Clark PC_MODE0_DRAWCALL = 25, 416a2272e48SRob Clark PC_MODE1_DRAWCALL = 26, 417a2272e48SRob Clark PC_MODE2_DRAWCALL = 27, 418a2272e48SRob Clark PC_MODE3_DRAWCALL = 28, 419a2272e48SRob Clark PC_MODE4_DRAWCALL = 29, 420a2272e48SRob Clark PC_PREDICATED_DEAD_DRAWCALL = 30, 421a2272e48SRob Clark PC_STALL_CYCLES_BY_TSE_ONLY = 31, 422a2272e48SRob Clark PC_STALL_CYCLES_BY_VPC_ONLY = 32, 423a2272e48SRob Clark PC_VPC_POS_DATA_TRANSACTION = 33, 424a2272e48SRob Clark PC_BUSY_CYCLES = 34, 425a2272e48SRob Clark PC_STARVE_CYCLES_DI = 35, 426a2272e48SRob Clark PC_STALL_CYCLES_VPC = 36, 427a2272e48SRob Clark TESS_WORKING_CYCLES = 37, 428a2272e48SRob Clark TESS_NUM_CYCLES_SETUP_WORKING = 38, 429a2272e48SRob Clark TESS_NUM_CYCLES_PTGEN_WORKING = 39, 430a2272e48SRob Clark TESS_NUM_CYCLES_CONNGEN_WORKING = 40, 431a2272e48SRob Clark TESS_BUSY_CYCLES = 41, 432a2272e48SRob Clark TESS_STARVE_CYCLES_PC = 42, 433a2272e48SRob Clark TESS_STALL_CYCLES_PC = 43, 434a2272e48SRob Clark }; 435a2272e48SRob Clark 436a2272e48SRob Clark enum a4xx_pwr_perfcounter_select { 437a2272e48SRob Clark PWR_CORE_CLOCK_CYCLES = 0, 438a2272e48SRob Clark PWR_BUSY_CLOCK_CYCLES = 1, 439a2272e48SRob Clark }; 440a2272e48SRob Clark 441a2272e48SRob Clark enum a4xx_rb_perfcounter_select { 442a2272e48SRob Clark RB_BUSY_CYCLES = 0, 443a2272e48SRob Clark RB_BUSY_CYCLES_BINNING = 1, 444a2272e48SRob Clark RB_BUSY_CYCLES_RENDERING = 2, 445a2272e48SRob Clark RB_BUSY_CYCLES_RESOLVE = 3, 446a2272e48SRob Clark RB_STARVE_CYCLES_BY_SP = 4, 447a2272e48SRob Clark RB_STARVE_CYCLES_BY_RAS = 5, 448a2272e48SRob Clark RB_STARVE_CYCLES_BY_MARB = 6, 449a2272e48SRob Clark RB_STALL_CYCLES_BY_MARB = 7, 450a2272e48SRob Clark RB_STALL_CYCLES_BY_HLSQ = 8, 451a2272e48SRob Clark RB_RB_RB_MARB_DATA = 9, 452a2272e48SRob Clark RB_SP_RB_QUAD = 10, 453a2272e48SRob Clark RB_RAS_RB_Z_QUADS = 11, 454a2272e48SRob Clark RB_GMEM_CH0_READ = 12, 455a2272e48SRob Clark RB_GMEM_CH1_READ = 13, 456a2272e48SRob Clark RB_GMEM_CH0_WRITE = 14, 457a2272e48SRob Clark RB_GMEM_CH1_WRITE = 15, 458a2272e48SRob Clark RB_CP_CONTEXT_DONE = 16, 459a2272e48SRob Clark RB_CP_CACHE_FLUSH = 17, 460a2272e48SRob Clark RB_CP_ZPASS_DONE = 18, 461a2272e48SRob Clark RB_STALL_FIFO0_FULL = 19, 462a2272e48SRob Clark RB_STALL_FIFO1_FULL = 20, 463a2272e48SRob Clark RB_STALL_FIFO2_FULL = 21, 464a2272e48SRob Clark RB_STALL_FIFO3_FULL = 22, 465a2272e48SRob Clark RB_RB_HLSQ_TRANSACTIONS = 23, 466a2272e48SRob Clark RB_Z_READ = 24, 467a2272e48SRob Clark RB_Z_WRITE = 25, 468a2272e48SRob Clark RB_C_READ = 26, 469a2272e48SRob Clark RB_C_WRITE = 27, 470a2272e48SRob Clark RB_C_READ_LATENCY = 28, 471a2272e48SRob Clark RB_Z_READ_LATENCY = 29, 472a2272e48SRob Clark RB_STALL_BY_UCHE = 30, 473a2272e48SRob Clark RB_MARB_UCHE_TRANSACTIONS = 31, 474a2272e48SRob Clark RB_CACHE_STALL_MISS = 32, 475a2272e48SRob Clark RB_CACHE_STALL_FIFO_FULL = 33, 476a2272e48SRob Clark RB_8BIT_BLENDER_UNITS_ACTIVE = 34, 477a2272e48SRob Clark RB_16BIT_BLENDER_UNITS_ACTIVE = 35, 478a2272e48SRob Clark RB_SAMPLER_UNITS_ACTIVE = 36, 479a2272e48SRob Clark RB_TOTAL_PASS = 38, 480a2272e48SRob Clark RB_Z_PASS = 39, 481a2272e48SRob Clark RB_Z_FAIL = 40, 482a2272e48SRob Clark RB_S_FAIL = 41, 483a2272e48SRob Clark RB_POWER0 = 42, 484a2272e48SRob Clark RB_POWER1 = 43, 485a2272e48SRob Clark RB_POWER2 = 44, 486a2272e48SRob Clark RB_POWER3 = 45, 487a2272e48SRob Clark RB_POWER4 = 46, 488a2272e48SRob Clark RB_POWER5 = 47, 489a2272e48SRob Clark RB_POWER6 = 48, 490a2272e48SRob Clark RB_POWER7 = 49, 491a2272e48SRob Clark }; 492a2272e48SRob Clark 493a2272e48SRob Clark enum a4xx_rbbm_perfcounter_select { 494a2272e48SRob Clark RBBM_ALWAYS_ON = 0, 495a2272e48SRob Clark RBBM_VBIF_BUSY = 1, 496a2272e48SRob Clark RBBM_TSE_BUSY = 2, 497a2272e48SRob Clark RBBM_RAS_BUSY = 3, 498a2272e48SRob Clark RBBM_PC_DCALL_BUSY = 4, 499a2272e48SRob Clark RBBM_PC_VSD_BUSY = 5, 500a2272e48SRob Clark RBBM_VFD_BUSY = 6, 501a2272e48SRob Clark RBBM_VPC_BUSY = 7, 502a2272e48SRob Clark RBBM_UCHE_BUSY = 8, 503a2272e48SRob Clark RBBM_VSC_BUSY = 9, 504a2272e48SRob Clark RBBM_HLSQ_BUSY = 10, 505a2272e48SRob Clark RBBM_ANY_RB_BUSY = 11, 506a2272e48SRob Clark RBBM_ANY_TPL1_BUSY = 12, 507a2272e48SRob Clark RBBM_ANY_SP_BUSY = 13, 508a2272e48SRob Clark RBBM_ANY_MARB_BUSY = 14, 509a2272e48SRob Clark RBBM_ANY_ARB_BUSY = 15, 510a2272e48SRob Clark RBBM_AHB_STATUS_BUSY = 16, 511a2272e48SRob Clark RBBM_AHB_STATUS_STALLED = 17, 512a2272e48SRob Clark RBBM_AHB_STATUS_TXFR = 18, 513a2272e48SRob Clark RBBM_AHB_STATUS_TXFR_SPLIT = 19, 514a2272e48SRob Clark RBBM_AHB_STATUS_TXFR_ERROR = 20, 515a2272e48SRob Clark RBBM_AHB_STATUS_LONG_STALL = 21, 516a2272e48SRob Clark RBBM_STATUS_MASKED = 22, 517a2272e48SRob Clark RBBM_CP_BUSY_GFX_CORE_IDLE = 23, 518a2272e48SRob Clark RBBM_TESS_BUSY = 24, 519a2272e48SRob Clark RBBM_COM_BUSY = 25, 520a2272e48SRob Clark RBBM_DCOM_BUSY = 32, 521a2272e48SRob Clark RBBM_ANY_CCU_BUSY = 33, 522a2272e48SRob Clark RBBM_DPM_BUSY = 34, 523a2272e48SRob Clark }; 524a2272e48SRob Clark 525a2272e48SRob Clark enum a4xx_sp_perfcounter_select { 526a2272e48SRob Clark SP_LM_LOAD_INSTRUCTIONS = 0, 527a2272e48SRob Clark SP_LM_STORE_INSTRUCTIONS = 1, 528a2272e48SRob Clark SP_LM_ATOMICS = 2, 529a2272e48SRob Clark SP_GM_LOAD_INSTRUCTIONS = 3, 530a2272e48SRob Clark SP_GM_STORE_INSTRUCTIONS = 4, 531a2272e48SRob Clark SP_GM_ATOMICS = 5, 532a2272e48SRob Clark SP_VS_STAGE_TEX_INSTRUCTIONS = 6, 533a2272e48SRob Clark SP_VS_STAGE_CFLOW_INSTRUCTIONS = 7, 534a2272e48SRob Clark SP_VS_STAGE_EFU_INSTRUCTIONS = 8, 535a2272e48SRob Clark SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 9, 536a2272e48SRob Clark SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 10, 537a2272e48SRob Clark SP_FS_STAGE_TEX_INSTRUCTIONS = 11, 538a2272e48SRob Clark SP_FS_STAGE_CFLOW_INSTRUCTIONS = 12, 539a2272e48SRob Clark SP_FS_STAGE_EFU_INSTRUCTIONS = 13, 540a2272e48SRob Clark SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 14, 541a2272e48SRob Clark SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 15, 542a2272e48SRob Clark SP_VS_INSTRUCTIONS = 17, 543a2272e48SRob Clark SP_FS_INSTRUCTIONS = 18, 544a2272e48SRob Clark SP_ADDR_LOCK_COUNT = 19, 545a2272e48SRob Clark SP_UCHE_READ_TRANS = 20, 546a2272e48SRob Clark SP_UCHE_WRITE_TRANS = 21, 547a2272e48SRob Clark SP_EXPORT_VPC_TRANS = 22, 548a2272e48SRob Clark SP_EXPORT_RB_TRANS = 23, 549a2272e48SRob Clark SP_PIXELS_KILLED = 24, 550a2272e48SRob Clark SP_ICL1_REQUESTS = 25, 551a2272e48SRob Clark SP_ICL1_MISSES = 26, 552a2272e48SRob Clark SP_ICL0_REQUESTS = 27, 553a2272e48SRob Clark SP_ICL0_MISSES = 28, 554a2272e48SRob Clark SP_ALU_WORKING_CYCLES = 29, 555a2272e48SRob Clark SP_EFU_WORKING_CYCLES = 30, 556a2272e48SRob Clark SP_STALL_CYCLES_BY_VPC = 31, 557a2272e48SRob Clark SP_STALL_CYCLES_BY_TP = 32, 558a2272e48SRob Clark SP_STALL_CYCLES_BY_UCHE = 33, 559a2272e48SRob Clark SP_STALL_CYCLES_BY_RB = 34, 560a2272e48SRob Clark SP_BUSY_CYCLES = 35, 561a2272e48SRob Clark SP_HS_INSTRUCTIONS = 36, 562a2272e48SRob Clark SP_DS_INSTRUCTIONS = 37, 563a2272e48SRob Clark SP_GS_INSTRUCTIONS = 38, 564a2272e48SRob Clark SP_CS_INSTRUCTIONS = 39, 565a2272e48SRob Clark SP_SCHEDULER_NON_WORKING = 40, 566a2272e48SRob Clark SP_WAVE_CONTEXTS = 41, 567a2272e48SRob Clark SP_WAVE_CONTEXT_CYCLES = 42, 568a2272e48SRob Clark SP_POWER0 = 43, 569a2272e48SRob Clark SP_POWER1 = 44, 570a2272e48SRob Clark SP_POWER2 = 45, 571a2272e48SRob Clark SP_POWER3 = 46, 572a2272e48SRob Clark SP_POWER4 = 47, 573a2272e48SRob Clark SP_POWER5 = 48, 574a2272e48SRob Clark SP_POWER6 = 49, 575a2272e48SRob Clark SP_POWER7 = 50, 576a2272e48SRob Clark SP_POWER8 = 51, 577a2272e48SRob Clark SP_POWER9 = 52, 578a2272e48SRob Clark SP_POWER10 = 53, 579a2272e48SRob Clark SP_POWER11 = 54, 580a2272e48SRob Clark SP_POWER12 = 55, 581a2272e48SRob Clark SP_POWER13 = 56, 582a2272e48SRob Clark SP_POWER14 = 57, 583a2272e48SRob Clark SP_POWER15 = 58, 584a2272e48SRob Clark }; 585a2272e48SRob Clark 586a2272e48SRob Clark enum a4xx_tp_perfcounter_select { 587a2272e48SRob Clark TP_L1_REQUESTS = 0, 588a2272e48SRob Clark TP_L1_MISSES = 1, 589a2272e48SRob Clark TP_QUADS_OFFSET = 8, 590a2272e48SRob Clark TP_QUAD_SHADOW = 9, 591a2272e48SRob Clark TP_QUADS_ARRAY = 10, 592a2272e48SRob Clark TP_QUADS_GRADIENT = 11, 593a2272e48SRob Clark TP_QUADS_1D2D = 12, 594a2272e48SRob Clark TP_QUADS_3DCUBE = 13, 595a2272e48SRob Clark TP_BUSY_CYCLES = 16, 596a2272e48SRob Clark TP_STALL_CYCLES_BY_ARB = 17, 597a2272e48SRob Clark TP_STATE_CACHE_REQUESTS = 20, 598a2272e48SRob Clark TP_STATE_CACHE_MISSES = 21, 599a2272e48SRob Clark TP_POWER0 = 22, 600a2272e48SRob Clark TP_POWER1 = 23, 601a2272e48SRob Clark TP_POWER2 = 24, 602a2272e48SRob Clark TP_POWER3 = 25, 603a2272e48SRob Clark TP_POWER4 = 26, 604a2272e48SRob Clark TP_POWER5 = 27, 605a2272e48SRob Clark TP_POWER6 = 28, 606a2272e48SRob Clark TP_POWER7 = 29, 607a2272e48SRob Clark }; 608a2272e48SRob Clark 609a2272e48SRob Clark enum a4xx_uche_perfcounter_select { 610a2272e48SRob Clark UCHE_VBIF_READ_BEATS_TP = 0, 611a2272e48SRob Clark UCHE_VBIF_READ_BEATS_VFD = 1, 612a2272e48SRob Clark UCHE_VBIF_READ_BEATS_HLSQ = 2, 613a2272e48SRob Clark UCHE_VBIF_READ_BEATS_MARB = 3, 614a2272e48SRob Clark UCHE_VBIF_READ_BEATS_SP = 4, 615a2272e48SRob Clark UCHE_READ_REQUESTS_TP = 5, 616a2272e48SRob Clark UCHE_READ_REQUESTS_VFD = 6, 617a2272e48SRob Clark UCHE_READ_REQUESTS_HLSQ = 7, 618a2272e48SRob Clark UCHE_READ_REQUESTS_MARB = 8, 619a2272e48SRob Clark UCHE_READ_REQUESTS_SP = 9, 620a2272e48SRob Clark UCHE_WRITE_REQUESTS_MARB = 10, 621a2272e48SRob Clark UCHE_WRITE_REQUESTS_SP = 11, 622a2272e48SRob Clark UCHE_TAG_CHECK_FAILS = 12, 623a2272e48SRob Clark UCHE_EVICTS = 13, 624a2272e48SRob Clark UCHE_FLUSHES = 14, 625a2272e48SRob Clark UCHE_VBIF_LATENCY_CYCLES = 15, 626a2272e48SRob Clark UCHE_VBIF_LATENCY_SAMPLES = 16, 627a2272e48SRob Clark UCHE_BUSY_CYCLES = 17, 628a2272e48SRob Clark UCHE_VBIF_READ_BEATS_PC = 18, 629a2272e48SRob Clark UCHE_READ_REQUESTS_PC = 19, 630a2272e48SRob Clark UCHE_WRITE_REQUESTS_VPC = 20, 631a2272e48SRob Clark UCHE_STALL_BY_VBIF = 21, 632a2272e48SRob Clark UCHE_WRITE_REQUESTS_VSC = 22, 633a2272e48SRob Clark UCHE_POWER0 = 23, 634a2272e48SRob Clark UCHE_POWER1 = 24, 635a2272e48SRob Clark UCHE_POWER2 = 25, 636a2272e48SRob Clark UCHE_POWER3 = 26, 637a2272e48SRob Clark UCHE_POWER4 = 27, 638a2272e48SRob Clark UCHE_POWER5 = 28, 639a2272e48SRob Clark UCHE_POWER6 = 29, 640a2272e48SRob Clark UCHE_POWER7 = 30, 641a2272e48SRob Clark }; 642a2272e48SRob Clark 643a2272e48SRob Clark enum a4xx_vbif_perfcounter_select { 644a2272e48SRob Clark AXI_READ_REQUESTS_ID_0 = 0, 645a2272e48SRob Clark AXI_READ_REQUESTS_ID_1 = 1, 646a2272e48SRob Clark AXI_READ_REQUESTS_ID_2 = 2, 647a2272e48SRob Clark AXI_READ_REQUESTS_ID_3 = 3, 648a2272e48SRob Clark AXI_READ_REQUESTS_ID_4 = 4, 649a2272e48SRob Clark AXI_READ_REQUESTS_ID_5 = 5, 650a2272e48SRob Clark AXI_READ_REQUESTS_ID_6 = 6, 651a2272e48SRob Clark AXI_READ_REQUESTS_ID_7 = 7, 652a2272e48SRob Clark AXI_READ_REQUESTS_ID_8 = 8, 653a2272e48SRob Clark AXI_READ_REQUESTS_ID_9 = 9, 654a2272e48SRob Clark AXI_READ_REQUESTS_ID_10 = 10, 655a2272e48SRob Clark AXI_READ_REQUESTS_ID_11 = 11, 656a2272e48SRob Clark AXI_READ_REQUESTS_ID_12 = 12, 657a2272e48SRob Clark AXI_READ_REQUESTS_ID_13 = 13, 658a2272e48SRob Clark AXI_READ_REQUESTS_ID_14 = 14, 659a2272e48SRob Clark AXI_READ_REQUESTS_ID_15 = 15, 660a2272e48SRob Clark AXI0_READ_REQUESTS_TOTAL = 16, 661a2272e48SRob Clark AXI1_READ_REQUESTS_TOTAL = 17, 662a2272e48SRob Clark AXI2_READ_REQUESTS_TOTAL = 18, 663a2272e48SRob Clark AXI3_READ_REQUESTS_TOTAL = 19, 664a2272e48SRob Clark AXI_READ_REQUESTS_TOTAL = 20, 665a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_0 = 21, 666a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_1 = 22, 667a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_2 = 23, 668a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_3 = 24, 669a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_4 = 25, 670a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_5 = 26, 671a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_6 = 27, 672a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_7 = 28, 673a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_8 = 29, 674a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_9 = 30, 675a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_10 = 31, 676a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_11 = 32, 677a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_12 = 33, 678a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_13 = 34, 679a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_14 = 35, 680a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_15 = 36, 681a2272e48SRob Clark AXI0_WRITE_REQUESTS_TOTAL = 37, 682a2272e48SRob Clark AXI1_WRITE_REQUESTS_TOTAL = 38, 683a2272e48SRob Clark AXI2_WRITE_REQUESTS_TOTAL = 39, 684a2272e48SRob Clark AXI3_WRITE_REQUESTS_TOTAL = 40, 685a2272e48SRob Clark AXI_WRITE_REQUESTS_TOTAL = 41, 686a2272e48SRob Clark AXI_TOTAL_REQUESTS = 42, 687a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_0 = 43, 688a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_1 = 44, 689a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_2 = 45, 690a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_3 = 46, 691a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_4 = 47, 692a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_5 = 48, 693a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_6 = 49, 694a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_7 = 50, 695a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_8 = 51, 696a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_9 = 52, 697a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_10 = 53, 698a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_11 = 54, 699a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_12 = 55, 700a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_13 = 56, 701a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_14 = 57, 702a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_15 = 58, 703a2272e48SRob Clark AXI0_READ_DATA_BEATS_TOTAL = 59, 704a2272e48SRob Clark AXI1_READ_DATA_BEATS_TOTAL = 60, 705a2272e48SRob Clark AXI2_READ_DATA_BEATS_TOTAL = 61, 706a2272e48SRob Clark AXI3_READ_DATA_BEATS_TOTAL = 62, 707a2272e48SRob Clark AXI_READ_DATA_BEATS_TOTAL = 63, 708a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_0 = 64, 709a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_1 = 65, 710a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_2 = 66, 711a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_3 = 67, 712a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_4 = 68, 713a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_5 = 69, 714a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_6 = 70, 715a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_7 = 71, 716a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_8 = 72, 717a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_9 = 73, 718a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_10 = 74, 719a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_11 = 75, 720a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_12 = 76, 721a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_13 = 77, 722a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_14 = 78, 723a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_15 = 79, 724a2272e48SRob Clark AXI0_WRITE_DATA_BEATS_TOTAL = 80, 725a2272e48SRob Clark AXI1_WRITE_DATA_BEATS_TOTAL = 81, 726a2272e48SRob Clark AXI2_WRITE_DATA_BEATS_TOTAL = 82, 727a2272e48SRob Clark AXI3_WRITE_DATA_BEATS_TOTAL = 83, 728a2272e48SRob Clark AXI_WRITE_DATA_BEATS_TOTAL = 84, 729a2272e48SRob Clark AXI_DATA_BEATS_TOTAL = 85, 730a2272e48SRob Clark CYCLES_HELD_OFF_ID_0 = 86, 731a2272e48SRob Clark CYCLES_HELD_OFF_ID_1 = 87, 732a2272e48SRob Clark CYCLES_HELD_OFF_ID_2 = 88, 733a2272e48SRob Clark CYCLES_HELD_OFF_ID_3 = 89, 734a2272e48SRob Clark CYCLES_HELD_OFF_ID_4 = 90, 735a2272e48SRob Clark CYCLES_HELD_OFF_ID_5 = 91, 736a2272e48SRob Clark CYCLES_HELD_OFF_ID_6 = 92, 737a2272e48SRob Clark CYCLES_HELD_OFF_ID_7 = 93, 738a2272e48SRob Clark CYCLES_HELD_OFF_ID_8 = 94, 739a2272e48SRob Clark CYCLES_HELD_OFF_ID_9 = 95, 740a2272e48SRob Clark CYCLES_HELD_OFF_ID_10 = 96, 741a2272e48SRob Clark CYCLES_HELD_OFF_ID_11 = 97, 742a2272e48SRob Clark CYCLES_HELD_OFF_ID_12 = 98, 743a2272e48SRob Clark CYCLES_HELD_OFF_ID_13 = 99, 744a2272e48SRob Clark CYCLES_HELD_OFF_ID_14 = 100, 745a2272e48SRob Clark CYCLES_HELD_OFF_ID_15 = 101, 746a2272e48SRob Clark AXI_READ_REQUEST_HELD_OFF = 102, 747a2272e48SRob Clark AXI_WRITE_REQUEST_HELD_OFF = 103, 748a2272e48SRob Clark AXI_REQUEST_HELD_OFF = 104, 749a2272e48SRob Clark AXI_WRITE_DATA_HELD_OFF = 105, 750a2272e48SRob Clark OCMEM_AXI_READ_REQUEST_HELD_OFF = 106, 751a2272e48SRob Clark OCMEM_AXI_WRITE_REQUEST_HELD_OFF = 107, 752a2272e48SRob Clark OCMEM_AXI_REQUEST_HELD_OFF = 108, 753a2272e48SRob Clark OCMEM_AXI_WRITE_DATA_HELD_OFF = 109, 754a2272e48SRob Clark ELAPSED_CYCLES_DDR = 110, 755a2272e48SRob Clark ELAPSED_CYCLES_OCMEM = 111, 756a2272e48SRob Clark }; 757a2272e48SRob Clark 758a2272e48SRob Clark enum a4xx_vfd_perfcounter_select { 759a2272e48SRob Clark VFD_UCHE_BYTE_FETCHED = 0, 760a2272e48SRob Clark VFD_UCHE_TRANS = 1, 761a2272e48SRob Clark VFD_FETCH_INSTRUCTIONS = 3, 762a2272e48SRob Clark VFD_BUSY_CYCLES = 5, 763a2272e48SRob Clark VFD_STALL_CYCLES_UCHE = 6, 764a2272e48SRob Clark VFD_STALL_CYCLES_HLSQ = 7, 765a2272e48SRob Clark VFD_STALL_CYCLES_VPC_BYPASS = 8, 766a2272e48SRob Clark VFD_STALL_CYCLES_VPC_ALLOC = 9, 767a2272e48SRob Clark VFD_MODE_0_FIBERS = 13, 768a2272e48SRob Clark VFD_MODE_1_FIBERS = 14, 769a2272e48SRob Clark VFD_MODE_2_FIBERS = 15, 770a2272e48SRob Clark VFD_MODE_3_FIBERS = 16, 771a2272e48SRob Clark VFD_MODE_4_FIBERS = 17, 772a2272e48SRob Clark VFD_BFIFO_STALL = 18, 773a2272e48SRob Clark VFD_NUM_VERTICES_TOTAL = 19, 774a2272e48SRob Clark VFD_PACKER_FULL = 20, 775a2272e48SRob Clark VFD_UCHE_REQUEST_FIFO_FULL = 21, 776a2272e48SRob Clark VFD_STARVE_CYCLES_PC = 22, 777a2272e48SRob Clark VFD_STARVE_CYCLES_UCHE = 23, 778a2272e48SRob Clark }; 779a2272e48SRob Clark 780a2272e48SRob Clark enum a4xx_vpc_perfcounter_select { 781a2272e48SRob Clark VPC_SP_LM_COMPONENTS = 2, 782a2272e48SRob Clark VPC_SP0_LM_BYTES = 3, 783a2272e48SRob Clark VPC_SP1_LM_BYTES = 4, 784a2272e48SRob Clark VPC_SP2_LM_BYTES = 5, 785a2272e48SRob Clark VPC_SP3_LM_BYTES = 6, 786a2272e48SRob Clark VPC_WORKING_CYCLES = 7, 787a2272e48SRob Clark VPC_STALL_CYCLES_LM = 8, 788a2272e48SRob Clark VPC_STARVE_CYCLES_RAS = 9, 789a2272e48SRob Clark VPC_STREAMOUT_CYCLES = 10, 790a2272e48SRob Clark VPC_UCHE_TRANSACTIONS = 12, 791a2272e48SRob Clark VPC_STALL_CYCLES_UCHE = 13, 792a2272e48SRob Clark VPC_BUSY_CYCLES = 14, 793a2272e48SRob Clark VPC_STARVE_CYCLES_SP = 15, 794a2272e48SRob Clark }; 795a2272e48SRob Clark 796a2272e48SRob Clark enum a4xx_vsc_perfcounter_select { 797a2272e48SRob Clark VSC_BUSY_CYCLES = 0, 798a2272e48SRob Clark VSC_WORKING_CYCLES = 1, 799a2272e48SRob Clark VSC_STALL_CYCLES_UCHE = 2, 800a2272e48SRob Clark VSC_STARVE_CYCLES_RAS = 3, 801a2272e48SRob Clark VSC_EOT_NUM = 4, 802a2272e48SRob Clark }; 803a2272e48SRob Clark 804bc00ae02SRob Clark enum a4xx_tex_filter { 805bc00ae02SRob Clark A4XX_TEX_NEAREST = 0, 806bc00ae02SRob Clark A4XX_TEX_LINEAR = 1, 807af6cb4c1SRob Clark A4XX_TEX_ANISO = 2, 808bc00ae02SRob Clark }; 809bc00ae02SRob Clark 810bc00ae02SRob Clark enum a4xx_tex_clamp { 811bc00ae02SRob Clark A4XX_TEX_REPEAT = 0, 812bc00ae02SRob Clark A4XX_TEX_CLAMP_TO_EDGE = 1, 813bc00ae02SRob Clark A4XX_TEX_MIRROR_REPEAT = 2, 8148217e97aSRob Clark A4XX_TEX_CLAMP_TO_BORDER = 3, 8158217e97aSRob Clark A4XX_TEX_MIRROR_CLAMP = 4, 816bc00ae02SRob Clark }; 817bc00ae02SRob Clark 818af6cb4c1SRob Clark enum a4xx_tex_aniso { 819af6cb4c1SRob Clark A4XX_TEX_ANISO_1 = 0, 820af6cb4c1SRob Clark A4XX_TEX_ANISO_2 = 1, 821af6cb4c1SRob Clark A4XX_TEX_ANISO_4 = 2, 822af6cb4c1SRob Clark A4XX_TEX_ANISO_8 = 3, 823af6cb4c1SRob Clark A4XX_TEX_ANISO_16 = 4, 824af6cb4c1SRob Clark }; 825af6cb4c1SRob Clark 826bc00ae02SRob Clark enum a4xx_tex_swiz { 827bc00ae02SRob Clark A4XX_TEX_X = 0, 828bc00ae02SRob Clark A4XX_TEX_Y = 1, 829bc00ae02SRob Clark A4XX_TEX_Z = 2, 830bc00ae02SRob Clark A4XX_TEX_W = 3, 831bc00ae02SRob Clark A4XX_TEX_ZERO = 4, 832bc00ae02SRob Clark A4XX_TEX_ONE = 5, 833bc00ae02SRob Clark }; 834bc00ae02SRob Clark 835bc00ae02SRob Clark enum a4xx_tex_type { 836bc00ae02SRob Clark A4XX_TEX_1D = 0, 837bc00ae02SRob Clark A4XX_TEX_2D = 1, 838bc00ae02SRob Clark A4XX_TEX_CUBE = 2, 839bc00ae02SRob Clark A4XX_TEX_3D = 3, 840bc00ae02SRob Clark }; 841bc00ae02SRob Clark 842bc00ae02SRob Clark #define A4XX_CGC_HLSQ_EARLY_CYC__MASK 0x00700000 843bc00ae02SRob Clark #define A4XX_CGC_HLSQ_EARLY_CYC__SHIFT 20 844bc00ae02SRob Clark static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) 845bc00ae02SRob Clark { 846bc00ae02SRob Clark return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK; 847bc00ae02SRob Clark } 848bc00ae02SRob Clark #define A4XX_INT0_RBBM_GPU_IDLE 0x00000001 849bc00ae02SRob Clark #define A4XX_INT0_RBBM_AHB_ERROR 0x00000002 850bc00ae02SRob Clark #define A4XX_INT0_RBBM_REG_TIMEOUT 0x00000004 851bc00ae02SRob Clark #define A4XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 852bc00ae02SRob Clark #define A4XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 853bc00ae02SRob Clark #define A4XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020 854bc00ae02SRob Clark #define A4XX_INT0_VFD_ERROR 0x00000040 855bc00ae02SRob Clark #define A4XX_INT0_CP_SW_INT 0x00000080 856bc00ae02SRob Clark #define A4XX_INT0_CP_T0_PACKET_IN_IB 0x00000100 857bc00ae02SRob Clark #define A4XX_INT0_CP_OPCODE_ERROR 0x00000200 858bc00ae02SRob Clark #define A4XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400 859bc00ae02SRob Clark #define A4XX_INT0_CP_HW_FAULT 0x00000800 860bc00ae02SRob Clark #define A4XX_INT0_CP_DMA 0x00001000 861bc00ae02SRob Clark #define A4XX_INT0_CP_IB2_INT 0x00002000 862bc00ae02SRob Clark #define A4XX_INT0_CP_IB1_INT 0x00004000 863bc00ae02SRob Clark #define A4XX_INT0_CP_RB_INT 0x00008000 864bc00ae02SRob Clark #define A4XX_INT0_CP_REG_PROTECT_FAULT 0x00010000 865bc00ae02SRob Clark #define A4XX_INT0_CP_RB_DONE_TS 0x00020000 866bc00ae02SRob Clark #define A4XX_INT0_CP_VS_DONE_TS 0x00040000 867bc00ae02SRob Clark #define A4XX_INT0_CP_PS_DONE_TS 0x00080000 868bc00ae02SRob Clark #define A4XX_INT0_CACHE_FLUSH_TS 0x00100000 869bc00ae02SRob Clark #define A4XX_INT0_CP_AHB_ERROR_HALT 0x00200000 870bc00ae02SRob Clark #define A4XX_INT0_MISC_HANG_DETECT 0x01000000 871bc00ae02SRob Clark #define A4XX_INT0_UCHE_OOB_ACCESS 0x02000000 872bc00ae02SRob Clark #define REG_A4XX_RB_GMEM_BASE_ADDR 0x00000cc0 873bc00ae02SRob Clark 874bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_0 0x00000cc7 875bc00ae02SRob Clark 876bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_1 0x00000cc8 877bc00ae02SRob Clark 878bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_2 0x00000cc9 879bc00ae02SRob Clark 880bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_3 0x00000cca 881bc00ae02SRob Clark 882bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_4 0x00000ccb 883bc00ae02SRob Clark 884bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_5 0x00000ccc 885bc00ae02SRob Clark 886bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_6 0x00000ccd 887bc00ae02SRob Clark 888bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_7 0x00000cce 889bc00ae02SRob Clark 890a2272e48SRob Clark #define REG_A4XX_RB_PERFCTR_CCU_SEL_0 0x00000ccf 891a2272e48SRob Clark 892a2272e48SRob Clark #define REG_A4XX_RB_PERFCTR_CCU_SEL_1 0x00000cd0 893a2272e48SRob Clark 894a2272e48SRob Clark #define REG_A4XX_RB_PERFCTR_CCU_SEL_2 0x00000cd1 895a2272e48SRob Clark 896bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_CCU_SEL_3 0x00000cd2 897bc00ae02SRob Clark 898bc00ae02SRob Clark #define REG_A4XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0 899bc00ae02SRob Clark #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff 900bc00ae02SRob Clark #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0 901bc00ae02SRob Clark static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) 902bc00ae02SRob Clark { 903bc00ae02SRob Clark return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK; 904bc00ae02SRob Clark } 905bc00ae02SRob Clark #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x3fff0000 906bc00ae02SRob Clark #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 16 907bc00ae02SRob Clark static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) 908bc00ae02SRob Clark { 909bc00ae02SRob Clark return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK; 910bc00ae02SRob Clark } 911bc00ae02SRob Clark 912bc00ae02SRob Clark #define REG_A4XX_RB_CLEAR_COLOR_DW0 0x000020cc 913bc00ae02SRob Clark 914bc00ae02SRob Clark #define REG_A4XX_RB_CLEAR_COLOR_DW1 0x000020cd 915bc00ae02SRob Clark 916bc00ae02SRob Clark #define REG_A4XX_RB_CLEAR_COLOR_DW2 0x000020ce 917bc00ae02SRob Clark 918bc00ae02SRob Clark #define REG_A4XX_RB_CLEAR_COLOR_DW3 0x000020cf 919bc00ae02SRob Clark 920bc00ae02SRob Clark #define REG_A4XX_RB_MODE_CONTROL 0x000020a0 921bc00ae02SRob Clark #define A4XX_RB_MODE_CONTROL_WIDTH__MASK 0x0000003f 922bc00ae02SRob Clark #define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT 0 923bc00ae02SRob Clark static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) 924bc00ae02SRob Clark { 925bc00ae02SRob Clark return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK; 926bc00ae02SRob Clark } 927bc00ae02SRob Clark #define A4XX_RB_MODE_CONTROL_HEIGHT__MASK 0x00003f00 928bc00ae02SRob Clark #define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT 8 929bc00ae02SRob Clark static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) 930bc00ae02SRob Clark { 931bc00ae02SRob Clark return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK; 932bc00ae02SRob Clark } 933a26ae754SRob Clark #define A4XX_RB_MODE_CONTROL_ENABLE_GMEM 0x00010000 934bc00ae02SRob Clark 935bc00ae02SRob Clark #define REG_A4XX_RB_RENDER_CONTROL 0x000020a1 936bc00ae02SRob Clark #define A4XX_RB_RENDER_CONTROL_BINNING_PASS 0x00000001 937bc00ae02SRob Clark #define A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00000020 938bc00ae02SRob Clark 939bc00ae02SRob Clark #define REG_A4XX_RB_MSAA_CONTROL 0x000020a2 940bc00ae02SRob Clark #define A4XX_RB_MSAA_CONTROL_DISABLE 0x00001000 941bc00ae02SRob Clark #define A4XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000e000 942bc00ae02SRob Clark #define A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 13 943bc00ae02SRob Clark static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val) 944bc00ae02SRob Clark { 945bc00ae02SRob Clark return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK; 946bc00ae02SRob Clark } 947bc00ae02SRob Clark 9488a264743SRob Clark #define REG_A4XX_RB_RENDER_CONTROL2 0x000020a3 949c28c82e9SRob Clark #define A4XX_RB_RENDER_CONTROL2_COORD_MASK__MASK 0x0000000f 950c28c82e9SRob Clark #define A4XX_RB_RENDER_CONTROL2_COORD_MASK__SHIFT 0 951c28c82e9SRob Clark static inline uint32_t A4XX_RB_RENDER_CONTROL2_COORD_MASK(uint32_t val) 952c28c82e9SRob Clark { 953c28c82e9SRob Clark return ((val) << A4XX_RB_RENDER_CONTROL2_COORD_MASK__SHIFT) & A4XX_RB_RENDER_CONTROL2_COORD_MASK__MASK; 954c28c82e9SRob Clark } 955af6cb4c1SRob Clark #define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK 0x00000010 9568a264743SRob Clark #define A4XX_RB_RENDER_CONTROL2_FACENESS 0x00000020 957af6cb4c1SRob Clark #define A4XX_RB_RENDER_CONTROL2_SAMPLEID 0x00000040 9588a264743SRob Clark #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK 0x00000380 9598a264743SRob Clark #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT 7 9608a264743SRob Clark static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val) 961bc00ae02SRob Clark { 9628a264743SRob Clark return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK; 963bc00ae02SRob Clark } 964af6cb4c1SRob Clark #define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR 0x00000800 965c28c82e9SRob Clark #define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_PIXEL 0x00001000 966c28c82e9SRob Clark #define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_CENTROID 0x00002000 967c28c82e9SRob Clark #define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_SAMPLE 0x00004000 968c28c82e9SRob Clark #define A4XX_RB_RENDER_CONTROL2_SIZE 0x00008000 969bc00ae02SRob Clark 970bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; } 971bc00ae02SRob Clark 972bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; } 973bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008 974bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL_BLEND 0x00000010 975bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL_BLEND2 0x00000020 976a2272e48SRob Clark #define A4XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000040 977a2272e48SRob Clark #define A4XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00 978a2272e48SRob Clark #define A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8 979a2272e48SRob Clark static inline uint32_t A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) 980a2272e48SRob Clark { 981a2272e48SRob Clark return ((val) << A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A4XX_RB_MRT_CONTROL_ROP_CODE__MASK; 982a2272e48SRob Clark } 983bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000 984bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24 985bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 986bc00ae02SRob Clark { 987bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 988bc00ae02SRob Clark } 989bc00ae02SRob Clark 990bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; } 991bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f 992bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 993bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val) 994bc00ae02SRob Clark { 995bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 996bc00ae02SRob Clark } 997af6cb4c1SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0 998af6cb4c1SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6 999af6cb4c1SRob Clark static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val) 1000af6cb4c1SRob Clark { 1001af6cb4c1SRob Clark return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 1002af6cb4c1SRob Clark } 1003bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00000600 1004bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 9 1005bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 1006bc00ae02SRob Clark { 1007bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK; 1008bc00ae02SRob Clark } 1009bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00001800 1010bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 11 1011bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 1012bc00ae02SRob Clark { 1013bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 1014bc00ae02SRob Clark } 1015af6cb4c1SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00002000 10162d3584ebSRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xffffc000 1017bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 14 1018bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) 1019bc00ae02SRob Clark { 1020bc00ae02SRob Clark return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; 1021bc00ae02SRob Clark } 1022bc00ae02SRob Clark 1023bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; } 1024bc00ae02SRob Clark 1025bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; } 10262d3584ebSRob Clark #define A4XX_RB_MRT_CONTROL3_STRIDE__MASK 0x03fffff8 1027bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT 3 1028bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val) 1029bc00ae02SRob Clark { 1030bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT) & A4XX_RB_MRT_CONTROL3_STRIDE__MASK; 1031bc00ae02SRob Clark } 1032bc00ae02SRob Clark 1033bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; } 1034bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 1035bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 1036bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 1037bc00ae02SRob Clark { 1038bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 1039bc00ae02SRob Clark } 1040bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 1041bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 1042a26ae754SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 1043bc00ae02SRob Clark { 1044bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 1045bc00ae02SRob Clark } 1046bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 1047bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 1048bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 1049bc00ae02SRob Clark { 1050bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 1051bc00ae02SRob Clark } 1052bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 1053bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 1054bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 1055bc00ae02SRob Clark { 1056bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 1057bc00ae02SRob Clark } 1058bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 1059bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 1060a26ae754SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 1061bc00ae02SRob Clark { 1062bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 1063bc00ae02SRob Clark } 1064bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 1065bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 1066bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 1067bc00ae02SRob Clark { 1068bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 1069bc00ae02SRob Clark } 1070bc00ae02SRob Clark 1071a2272e48SRob Clark #define REG_A4XX_RB_BLEND_RED 0x000020f0 1072a26ae754SRob Clark #define A4XX_RB_BLEND_RED_UINT__MASK 0x000000ff 10738a264743SRob Clark #define A4XX_RB_BLEND_RED_UINT__SHIFT 0 10748a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val) 10758a264743SRob Clark { 10768a264743SRob Clark return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK; 10778a264743SRob Clark } 1078a26ae754SRob Clark #define A4XX_RB_BLEND_RED_SINT__MASK 0x0000ff00 1079a26ae754SRob Clark #define A4XX_RB_BLEND_RED_SINT__SHIFT 8 1080a26ae754SRob Clark static inline uint32_t A4XX_RB_BLEND_RED_SINT(uint32_t val) 1081a26ae754SRob Clark { 1082a26ae754SRob Clark return ((val) << A4XX_RB_BLEND_RED_SINT__SHIFT) & A4XX_RB_BLEND_RED_SINT__MASK; 1083a26ae754SRob Clark } 10848a264743SRob Clark #define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 10858a264743SRob Clark #define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16 10868a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val) 10878a264743SRob Clark { 10888a264743SRob Clark return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK; 10898a264743SRob Clark } 10908a264743SRob Clark 1091a2272e48SRob Clark #define REG_A4XX_RB_BLEND_RED_F32 0x000020f1 1092a2272e48SRob Clark #define A4XX_RB_BLEND_RED_F32__MASK 0xffffffff 1093a2272e48SRob Clark #define A4XX_RB_BLEND_RED_F32__SHIFT 0 1094a2272e48SRob Clark static inline uint32_t A4XX_RB_BLEND_RED_F32(float val) 1095a2272e48SRob Clark { 1096a2272e48SRob Clark return ((fui(val)) << A4XX_RB_BLEND_RED_F32__SHIFT) & A4XX_RB_BLEND_RED_F32__MASK; 1097a2272e48SRob Clark } 1098a2272e48SRob Clark 1099a2272e48SRob Clark #define REG_A4XX_RB_BLEND_GREEN 0x000020f2 1100a26ae754SRob Clark #define A4XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff 11018a264743SRob Clark #define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0 11028a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val) 11038a264743SRob Clark { 11048a264743SRob Clark return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK; 11058a264743SRob Clark } 1106a26ae754SRob Clark #define A4XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00 1107a26ae754SRob Clark #define A4XX_RB_BLEND_GREEN_SINT__SHIFT 8 1108a26ae754SRob Clark static inline uint32_t A4XX_RB_BLEND_GREEN_SINT(uint32_t val) 1109a26ae754SRob Clark { 1110a26ae754SRob Clark return ((val) << A4XX_RB_BLEND_GREEN_SINT__SHIFT) & A4XX_RB_BLEND_GREEN_SINT__MASK; 1111a26ae754SRob Clark } 11128a264743SRob Clark #define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 11138a264743SRob Clark #define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 11148a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val) 11158a264743SRob Clark { 11168a264743SRob Clark return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK; 11178a264743SRob Clark } 11188a264743SRob Clark 1119a2272e48SRob Clark #define REG_A4XX_RB_BLEND_GREEN_F32 0x000020f3 1120a2272e48SRob Clark #define A4XX_RB_BLEND_GREEN_F32__MASK 0xffffffff 1121a2272e48SRob Clark #define A4XX_RB_BLEND_GREEN_F32__SHIFT 0 1122a2272e48SRob Clark static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val) 1123a2272e48SRob Clark { 1124a2272e48SRob Clark return ((fui(val)) << A4XX_RB_BLEND_GREEN_F32__SHIFT) & A4XX_RB_BLEND_GREEN_F32__MASK; 1125a2272e48SRob Clark } 1126a2272e48SRob Clark 1127a2272e48SRob Clark #define REG_A4XX_RB_BLEND_BLUE 0x000020f4 1128a26ae754SRob Clark #define A4XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff 11298a264743SRob Clark #define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0 11308a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val) 11318a264743SRob Clark { 11328a264743SRob Clark return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK; 11338a264743SRob Clark } 1134a26ae754SRob Clark #define A4XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00 1135a26ae754SRob Clark #define A4XX_RB_BLEND_BLUE_SINT__SHIFT 8 1136a26ae754SRob Clark static inline uint32_t A4XX_RB_BLEND_BLUE_SINT(uint32_t val) 1137a26ae754SRob Clark { 1138a26ae754SRob Clark return ((val) << A4XX_RB_BLEND_BLUE_SINT__SHIFT) & A4XX_RB_BLEND_BLUE_SINT__MASK; 1139a26ae754SRob Clark } 11408a264743SRob Clark #define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 11418a264743SRob Clark #define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 11428a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val) 11438a264743SRob Clark { 11448a264743SRob Clark return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK; 11458a264743SRob Clark } 11468a264743SRob Clark 1147a2272e48SRob Clark #define REG_A4XX_RB_BLEND_BLUE_F32 0x000020f5 1148a2272e48SRob Clark #define A4XX_RB_BLEND_BLUE_F32__MASK 0xffffffff 1149a2272e48SRob Clark #define A4XX_RB_BLEND_BLUE_F32__SHIFT 0 1150a2272e48SRob Clark static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val) 1151a2272e48SRob Clark { 1152a2272e48SRob Clark return ((fui(val)) << A4XX_RB_BLEND_BLUE_F32__SHIFT) & A4XX_RB_BLEND_BLUE_F32__MASK; 1153a2272e48SRob Clark } 1154a2272e48SRob Clark 11558a264743SRob Clark #define REG_A4XX_RB_BLEND_ALPHA 0x000020f6 1156a26ae754SRob Clark #define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff 11578a264743SRob Clark #define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0 11588a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val) 11598a264743SRob Clark { 11608a264743SRob Clark return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK; 11618a264743SRob Clark } 1162a26ae754SRob Clark #define A4XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00 1163a26ae754SRob Clark #define A4XX_RB_BLEND_ALPHA_SINT__SHIFT 8 1164a26ae754SRob Clark static inline uint32_t A4XX_RB_BLEND_ALPHA_SINT(uint32_t val) 1165a26ae754SRob Clark { 1166a26ae754SRob Clark return ((val) << A4XX_RB_BLEND_ALPHA_SINT__SHIFT) & A4XX_RB_BLEND_ALPHA_SINT__MASK; 1167a26ae754SRob Clark } 11688a264743SRob Clark #define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 11698a264743SRob Clark #define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 11708a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val) 11718a264743SRob Clark { 11728a264743SRob Clark return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK; 11738a264743SRob Clark } 11748a264743SRob Clark 1175a2272e48SRob Clark #define REG_A4XX_RB_BLEND_ALPHA_F32 0x000020f7 1176a2272e48SRob Clark #define A4XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff 1177a2272e48SRob Clark #define A4XX_RB_BLEND_ALPHA_F32__SHIFT 0 1178a2272e48SRob Clark static inline uint32_t A4XX_RB_BLEND_ALPHA_F32(float val) 1179a2272e48SRob Clark { 1180a2272e48SRob Clark return ((fui(val)) << A4XX_RB_BLEND_ALPHA_F32__SHIFT) & A4XX_RB_BLEND_ALPHA_F32__MASK; 1181a2272e48SRob Clark } 1182a2272e48SRob Clark 1183bc00ae02SRob Clark #define REG_A4XX_RB_ALPHA_CONTROL 0x000020f8 11848a264743SRob Clark #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff 11858a264743SRob Clark #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 11868a264743SRob Clark static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) 11878a264743SRob Clark { 11888a264743SRob Clark return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; 11898a264743SRob Clark } 1190bc00ae02SRob Clark #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 1191bc00ae02SRob Clark #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 1192bc00ae02SRob Clark #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 1193bc00ae02SRob Clark static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 1194bc00ae02SRob Clark { 1195bc00ae02SRob Clark return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; 1196bc00ae02SRob Clark } 1197bc00ae02SRob Clark 1198bc00ae02SRob Clark #define REG_A4XX_RB_FS_OUTPUT 0x000020f9 1199af6cb4c1SRob Clark #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK 0x000000ff 1200af6cb4c1SRob Clark #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT 0 1201af6cb4c1SRob Clark static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val) 1202af6cb4c1SRob Clark { 1203af6cb4c1SRob Clark return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK; 1204af6cb4c1SRob Clark } 1205a2272e48SRob Clark #define A4XX_RB_FS_OUTPUT_INDEPENDENT_BLEND 0x00000100 1206bc00ae02SRob Clark #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000 1207bc00ae02SRob Clark #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT 16 1208bc00ae02SRob Clark static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val) 1209bc00ae02SRob Clark { 1210bc00ae02SRob Clark return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK; 1211bc00ae02SRob Clark } 1212bc00ae02SRob Clark 12132d3584ebSRob Clark #define REG_A4XX_RB_SAMPLE_COUNT_CONTROL 0x000020fa 12142d3584ebSRob Clark #define A4XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 12152d3584ebSRob Clark #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK 0xfffffffc 12162d3584ebSRob Clark #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT 2 12172d3584ebSRob Clark static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val) 12182d3584ebSRob Clark { 12192d3584ebSRob Clark return ((val >> 2) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK; 12202d3584ebSRob Clark } 12212d3584ebSRob Clark 1222af6cb4c1SRob Clark #define REG_A4XX_RB_RENDER_COMPONENTS 0x000020fb 1223af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f 1224af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0 1225af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) 1226bc00ae02SRob Clark { 1227af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT0__MASK; 1228af6cb4c1SRob Clark } 1229af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0 1230af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4 1231af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) 1232af6cb4c1SRob Clark { 1233af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT1__MASK; 1234af6cb4c1SRob Clark } 1235af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00 1236af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8 1237af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) 1238af6cb4c1SRob Clark { 1239af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT2__MASK; 1240af6cb4c1SRob Clark } 1241af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000 1242af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12 1243af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) 1244af6cb4c1SRob Clark { 1245af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT3__MASK; 1246af6cb4c1SRob Clark } 1247af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000 1248af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16 1249af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) 1250af6cb4c1SRob Clark { 1251af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT4__MASK; 1252af6cb4c1SRob Clark } 1253af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000 1254af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20 1255af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) 1256af6cb4c1SRob Clark { 1257af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT5__MASK; 1258af6cb4c1SRob Clark } 1259af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000 1260af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24 1261af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) 1262af6cb4c1SRob Clark { 1263af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT6__MASK; 1264af6cb4c1SRob Clark } 1265af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000 1266af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28 1267af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) 1268af6cb4c1SRob Clark { 1269af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT7__MASK; 1270bc00ae02SRob Clark } 1271bc00ae02SRob Clark 1272bc00ae02SRob Clark #define REG_A4XX_RB_COPY_CONTROL 0x000020fc 1273bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003 1274bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0 1275bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) 1276bc00ae02SRob Clark { 1277bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK; 1278bc00ae02SRob Clark } 1279bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_MODE__MASK 0x00000070 1280bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_MODE__SHIFT 4 1281bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) 1282bc00ae02SRob Clark { 1283bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_CONTROL_MODE__SHIFT) & A4XX_RB_COPY_CONTROL_MODE__MASK; 1284bc00ae02SRob Clark } 1285bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00 1286bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8 1287bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) 1288bc00ae02SRob Clark { 1289bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK; 1290bc00ae02SRob Clark } 1291bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000 1292bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14 1293bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) 1294bc00ae02SRob Clark { 1295bc00ae02SRob Clark return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK; 1296bc00ae02SRob Clark } 1297bc00ae02SRob Clark 1298bc00ae02SRob Clark #define REG_A4XX_RB_COPY_DEST_BASE 0x000020fd 12998a264743SRob Clark #define A4XX_RB_COPY_DEST_BASE_BASE__MASK 0xffffffe0 13008a264743SRob Clark #define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT 5 1301bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val) 1302bc00ae02SRob Clark { 13038a264743SRob Clark return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK; 1304bc00ae02SRob Clark } 1305bc00ae02SRob Clark 1306bc00ae02SRob Clark #define REG_A4XX_RB_COPY_DEST_PITCH 0x000020fe 1307bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff 1308bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0 1309bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) 1310bc00ae02SRob Clark { 1311bc00ae02SRob Clark return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK; 1312bc00ae02SRob Clark } 1313bc00ae02SRob Clark 1314bc00ae02SRob Clark #define REG_A4XX_RB_COPY_DEST_INFO 0x000020ff 1315bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc 1316bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2 1317bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val) 1318bc00ae02SRob Clark { 1319bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A4XX_RB_COPY_DEST_INFO_FORMAT__MASK; 1320bc00ae02SRob Clark } 1321bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 1322bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 1323bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) 1324bc00ae02SRob Clark { 1325bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A4XX_RB_COPY_DEST_INFO_SWAP__MASK; 1326bc00ae02SRob Clark } 1327bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 1328bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 1329bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 1330bc00ae02SRob Clark { 1331bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 1332bc00ae02SRob Clark } 1333bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000 1334bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14 1335bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) 1336bc00ae02SRob Clark { 1337bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK; 1338bc00ae02SRob Clark } 1339bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000 1340bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18 1341bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) 1342bc00ae02SRob Clark { 1343bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK; 1344bc00ae02SRob Clark } 1345bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_TILE__MASK 0x03000000 1346bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_TILE__SHIFT 24 1347bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val) 1348bc00ae02SRob Clark { 1349bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A4XX_RB_COPY_DEST_INFO_TILE__MASK; 1350bc00ae02SRob Clark } 1351bc00ae02SRob Clark 1352bc00ae02SRob Clark #define REG_A4XX_RB_FS_OUTPUT_REG 0x00002100 1353af6cb4c1SRob Clark #define A4XX_RB_FS_OUTPUT_REG_MRT__MASK 0x0000000f 1354af6cb4c1SRob Clark #define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT 0 1355af6cb4c1SRob Clark static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val) 1356af6cb4c1SRob Clark { 1357af6cb4c1SRob Clark return ((val) << A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_RB_FS_OUTPUT_REG_MRT__MASK; 1358af6cb4c1SRob Clark } 1359bc00ae02SRob Clark #define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z 0x00000020 1360bc00ae02SRob Clark 1361bc00ae02SRob Clark #define REG_A4XX_RB_DEPTH_CONTROL 0x00002101 1362bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001 1363bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002 1364bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004 1365bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070 1366bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4 1367bc00ae02SRob Clark static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) 1368bc00ae02SRob Clark { 1369bc00ae02SRob Clark return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK; 1370bc00ae02SRob Clark } 1371a26ae754SRob Clark #define A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE 0x00000080 1372bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000 1373a2272e48SRob Clark #define A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS 0x00020000 1374bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000 1375bc00ae02SRob Clark 1376bc00ae02SRob Clark #define REG_A4XX_RB_DEPTH_CLEAR 0x00002102 1377bc00ae02SRob Clark 1378bc00ae02SRob Clark #define REG_A4XX_RB_DEPTH_INFO 0x00002103 1379bc00ae02SRob Clark #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003 1380bc00ae02SRob Clark #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 1381bc00ae02SRob Clark static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val) 1382bc00ae02SRob Clark { 1383bc00ae02SRob Clark return ((val) << A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 1384bc00ae02SRob Clark } 1385bc00ae02SRob Clark #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 1386bc00ae02SRob Clark #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 1387bc00ae02SRob Clark static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 1388bc00ae02SRob Clark { 1389bc00ae02SRob Clark return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 1390bc00ae02SRob Clark } 1391bc00ae02SRob Clark 1392bc00ae02SRob Clark #define REG_A4XX_RB_DEPTH_PITCH 0x00002104 1393bc00ae02SRob Clark #define A4XX_RB_DEPTH_PITCH__MASK 0xffffffff 1394bc00ae02SRob Clark #define A4XX_RB_DEPTH_PITCH__SHIFT 0 1395bc00ae02SRob Clark static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val) 1396bc00ae02SRob Clark { 13978a264743SRob Clark return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK; 1398bc00ae02SRob Clark } 1399bc00ae02SRob Clark 1400bc00ae02SRob Clark #define REG_A4XX_RB_DEPTH_PITCH2 0x00002105 1401bc00ae02SRob Clark #define A4XX_RB_DEPTH_PITCH2__MASK 0xffffffff 1402bc00ae02SRob Clark #define A4XX_RB_DEPTH_PITCH2__SHIFT 0 1403bc00ae02SRob Clark static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val) 1404bc00ae02SRob Clark { 14058a264743SRob Clark return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK; 1406bc00ae02SRob Clark } 1407bc00ae02SRob Clark 1408bc00ae02SRob Clark #define REG_A4XX_RB_STENCIL_CONTROL 0x00002106 1409bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 1410bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 1411bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 1412bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 1413bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 1414bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 1415bc00ae02SRob Clark { 1416bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC__MASK; 1417bc00ae02SRob Clark } 1418bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 1419bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 1420bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 1421bc00ae02SRob Clark { 1422bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL__MASK; 1423bc00ae02SRob Clark } 1424bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 1425bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 1426bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 1427bc00ae02SRob Clark { 1428bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS__MASK; 1429bc00ae02SRob Clark } 1430bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 1431bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 1432bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 1433bc00ae02SRob Clark { 1434bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 1435bc00ae02SRob Clark } 1436bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 1437bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 1438bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 1439bc00ae02SRob Clark { 1440bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 1441bc00ae02SRob Clark } 1442bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 1443bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 1444bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 1445bc00ae02SRob Clark { 1446bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 1447bc00ae02SRob Clark } 1448bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 1449bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 1450bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 1451bc00ae02SRob Clark { 1452bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 1453bc00ae02SRob Clark } 1454bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 1455bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 1456bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 1457bc00ae02SRob Clark { 1458bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 1459bc00ae02SRob Clark } 1460bc00ae02SRob Clark 1461bc00ae02SRob Clark #define REG_A4XX_RB_STENCIL_CONTROL2 0x00002107 1462bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER 0x00000001 1463bc00ae02SRob Clark 14642d3584ebSRob Clark #define REG_A4XX_RB_STENCIL_INFO 0x00002108 14652d3584ebSRob Clark #define A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 14662d3584ebSRob Clark #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff000 14672d3584ebSRob Clark #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 12 14682d3584ebSRob Clark static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) 14692d3584ebSRob Clark { 14702d3584ebSRob Clark return ((val >> 12) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK; 14712d3584ebSRob Clark } 14722d3584ebSRob Clark 14732d3584ebSRob Clark #define REG_A4XX_RB_STENCIL_PITCH 0x00002109 14742d3584ebSRob Clark #define A4XX_RB_STENCIL_PITCH__MASK 0xffffffff 14752d3584ebSRob Clark #define A4XX_RB_STENCIL_PITCH__SHIFT 0 14762d3584ebSRob Clark static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val) 14772d3584ebSRob Clark { 14782d3584ebSRob Clark return ((val >> 5) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK; 14792d3584ebSRob Clark } 14802d3584ebSRob Clark 1481bc00ae02SRob Clark #define REG_A4XX_RB_STENCILREFMASK 0x0000210b 1482bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 1483bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 1484bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 1485bc00ae02SRob Clark { 1486bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILREF__MASK; 1487bc00ae02SRob Clark } 1488bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 1489bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 1490bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 1491bc00ae02SRob Clark { 1492bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILMASK__MASK; 1493bc00ae02SRob Clark } 1494bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 1495bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 1496bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 1497bc00ae02SRob Clark { 1498bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 1499bc00ae02SRob Clark } 1500bc00ae02SRob Clark 1501bc00ae02SRob Clark #define REG_A4XX_RB_STENCILREFMASK_BF 0x0000210c 1502bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 1503bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 1504bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 1505bc00ae02SRob Clark { 1506bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 1507bc00ae02SRob Clark } 1508bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 1509bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 1510bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 1511bc00ae02SRob Clark { 1512bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 1513bc00ae02SRob Clark } 1514bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 1515bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 1516bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 1517bc00ae02SRob Clark { 1518bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 1519bc00ae02SRob Clark } 1520bc00ae02SRob Clark 1521bc00ae02SRob Clark #define REG_A4XX_RB_BIN_OFFSET 0x0000210d 1522bc00ae02SRob Clark #define A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 1523bc00ae02SRob Clark #define A4XX_RB_BIN_OFFSET_X__MASK 0x00007fff 1524bc00ae02SRob Clark #define A4XX_RB_BIN_OFFSET_X__SHIFT 0 1525bc00ae02SRob Clark static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val) 1526bc00ae02SRob Clark { 1527bc00ae02SRob Clark return ((val) << A4XX_RB_BIN_OFFSET_X__SHIFT) & A4XX_RB_BIN_OFFSET_X__MASK; 1528bc00ae02SRob Clark } 1529bc00ae02SRob Clark #define A4XX_RB_BIN_OFFSET_Y__MASK 0x7fff0000 1530bc00ae02SRob Clark #define A4XX_RB_BIN_OFFSET_Y__SHIFT 16 1531bc00ae02SRob Clark static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val) 1532bc00ae02SRob Clark { 1533bc00ae02SRob Clark return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK; 1534bc00ae02SRob Clark } 1535bc00ae02SRob Clark 15368a264743SRob Clark static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; } 15378a264743SRob Clark 15388a264743SRob Clark static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; } 15398a264743SRob Clark 15408a264743SRob Clark static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; } 1541bc00ae02SRob Clark 1542bc00ae02SRob Clark #define REG_A4XX_RBBM_HW_VERSION 0x00000000 1543bc00ae02SRob Clark 1544bc00ae02SRob Clark #define REG_A4XX_RBBM_HW_CONFIGURATION 0x00000002 1545bc00ae02SRob Clark 1546bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; } 1547bc00ae02SRob Clark 1548bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; } 1549bc00ae02SRob Clark 1550bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; } 1551bc00ae02SRob Clark 1552bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; } 1553bc00ae02SRob Clark 1554bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; } 1555bc00ae02SRob Clark 1556bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; } 1557bc00ae02SRob Clark 1558bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; } 1559bc00ae02SRob Clark 1560bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; } 1561bc00ae02SRob Clark 1562bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL_UCHE 0x00000014 1563bc00ae02SRob Clark 1564bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL2_UCHE 0x00000015 1565bc00ae02SRob Clark 1566bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL3_UCHE 0x00000016 1567bc00ae02SRob Clark 1568bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL4_UCHE 0x00000017 1569bc00ae02SRob Clark 1570bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_HYST_UCHE 0x00000018 1571bc00ae02SRob Clark 1572bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_DELAY_UCHE 0x00000019 1573bc00ae02SRob Clark 1574bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_MODE_GPC 0x0000001a 1575bc00ae02SRob Clark 1576bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_DELAY_GPC 0x0000001b 1577bc00ae02SRob Clark 1578bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_HYST_GPC 0x0000001c 1579bc00ae02SRob Clark 1580bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM 0x0000001d 1581bc00ae02SRob Clark 1582bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000001e 1583bc00ae02SRob Clark 1584bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x0000001f 1585bc00ae02SRob Clark 1586bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL 0x00000020 1587bc00ae02SRob Clark 1588bc00ae02SRob Clark #define REG_A4XX_RBBM_SP_HYST_CNT 0x00000021 1589bc00ae02SRob Clark 1590bc00ae02SRob Clark #define REG_A4XX_RBBM_SW_RESET_CMD 0x00000022 1591bc00ae02SRob Clark 1592bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_CTL0 0x00000023 1593bc00ae02SRob Clark 1594bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_CTL1 0x00000024 1595bc00ae02SRob Clark 1596bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_CMD 0x00000025 1597bc00ae02SRob Clark 1598bc00ae02SRob Clark #define REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL 0x00000026 1599bc00ae02SRob Clark 1600bc00ae02SRob Clark #define REG_A4XX_RBBM_RAM_ACC_63_32 0x00000028 1601bc00ae02SRob Clark 1602bc00ae02SRob Clark #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x0000002b 1603bc00ae02SRob Clark 1604bc00ae02SRob Clark #define REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL 0x0000002f 1605bc00ae02SRob Clark 1606bc00ae02SRob Clark #define REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4 0x00000034 1607bc00ae02SRob Clark 1608bc00ae02SRob Clark #define REG_A4XX_RBBM_INT_CLEAR_CMD 0x00000036 1609bc00ae02SRob Clark 1610bc00ae02SRob Clark #define REG_A4XX_RBBM_INT_0_MASK 0x00000037 1611bc00ae02SRob Clark 1612bc00ae02SRob Clark #define REG_A4XX_RBBM_RBBM_CTL 0x0000003e 1613bc00ae02SRob Clark 1614bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_DEBUG_CTL 0x0000003f 1615bc00ae02SRob Clark 1616bc00ae02SRob Clark #define REG_A4XX_RBBM_VBIF_DEBUG_CTL 0x00000041 1617bc00ae02SRob Clark 1618bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL2 0x00000042 1619bc00ae02SRob Clark 1620bc00ae02SRob Clark #define REG_A4XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 1621bc00ae02SRob Clark 1622bc00ae02SRob Clark #define REG_A4XX_RBBM_RESET_CYCLES 0x00000047 1623bc00ae02SRob Clark 1624bc00ae02SRob Clark #define REG_A4XX_RBBM_EXT_TRACE_BUS_CTL 0x00000049 1625bc00ae02SRob Clark 1626bc00ae02SRob Clark #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A 0x0000004a 1627bc00ae02SRob Clark 1628bc00ae02SRob Clark #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B 0x0000004b 1629bc00ae02SRob Clark 1630bc00ae02SRob Clark #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C 0x0000004c 1631bc00ae02SRob Clark 1632bc00ae02SRob Clark #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D 0x0000004d 1633bc00ae02SRob Clark 1634a2272e48SRob Clark #define REG_A4XX_RBBM_POWER_CNTL_IP 0x00000098 1635a2272e48SRob Clark #define A4XX_RBBM_POWER_CNTL_IP_SW_COLLAPSE 0x00000001 1636a2272e48SRob Clark #define A4XX_RBBM_POWER_CNTL_IP_SP_TP_PWR_ON 0x00100000 1637a2272e48SRob Clark 1638bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_0_LO 0x0000009c 1639bc00ae02SRob Clark 1640a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_0_HI 0x0000009d 1641a2272e48SRob Clark 1642a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_1_LO 0x0000009e 1643a2272e48SRob Clark 1644a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_1_HI 0x0000009f 1645a2272e48SRob Clark 1646a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_2_LO 0x000000a0 1647a2272e48SRob Clark 1648a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_2_HI 0x000000a1 1649a2272e48SRob Clark 1650a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_3_LO 0x000000a2 1651a2272e48SRob Clark 1652a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_3_HI 0x000000a3 1653a2272e48SRob Clark 1654a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_4_LO 0x000000a4 1655a2272e48SRob Clark 1656a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_4_HI 0x000000a5 1657a2272e48SRob Clark 1658a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_5_LO 0x000000a6 1659a2272e48SRob Clark 1660a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_5_HI 0x000000a7 1661a2272e48SRob Clark 1662a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_6_LO 0x000000a8 1663a2272e48SRob Clark 1664a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_6_HI 0x000000a9 1665a2272e48SRob Clark 1666a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_7_LO 0x000000aa 1667a2272e48SRob Clark 1668a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_7_HI 0x000000ab 1669a2272e48SRob Clark 1670a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_0_LO 0x000000ac 1671a2272e48SRob Clark 1672a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_0_HI 0x000000ad 1673a2272e48SRob Clark 1674a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_1_LO 0x000000ae 1675a2272e48SRob Clark 1676a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_1_HI 0x000000af 1677a2272e48SRob Clark 1678a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_2_LO 0x000000b0 1679a2272e48SRob Clark 1680a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_2_HI 0x000000b1 1681a2272e48SRob Clark 1682a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_3_LO 0x000000b2 1683a2272e48SRob Clark 1684a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_3_HI 0x000000b3 1685a2272e48SRob Clark 1686a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_0_LO 0x000000b4 1687a2272e48SRob Clark 1688a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_0_HI 0x000000b5 1689a2272e48SRob Clark 1690a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_1_LO 0x000000b6 1691a2272e48SRob Clark 1692a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_1_HI 0x000000b7 1693a2272e48SRob Clark 1694a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_2_LO 0x000000b8 1695a2272e48SRob Clark 1696a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_2_HI 0x000000b9 1697a2272e48SRob Clark 1698a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_3_LO 0x000000ba 1699a2272e48SRob Clark 1700a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_3_HI 0x000000bb 1701a2272e48SRob Clark 1702a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_4_LO 0x000000bc 1703a2272e48SRob Clark 1704a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_4_HI 0x000000bd 1705a2272e48SRob Clark 1706a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_5_LO 0x000000be 1707a2272e48SRob Clark 1708a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_5_HI 0x000000bf 1709a2272e48SRob Clark 1710a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_6_LO 0x000000c0 1711a2272e48SRob Clark 1712a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_6_HI 0x000000c1 1713a2272e48SRob Clark 1714a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_7_LO 0x000000c2 1715a2272e48SRob Clark 1716a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_7_HI 0x000000c3 1717a2272e48SRob Clark 1718a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_0_LO 0x000000c4 1719a2272e48SRob Clark 1720a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_0_HI 0x000000c5 1721a2272e48SRob Clark 1722a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_1_LO 0x000000c6 1723a2272e48SRob Clark 1724a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_1_HI 0x000000c7 1725a2272e48SRob Clark 1726a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_2_LO 0x000000c8 1727a2272e48SRob Clark 1728a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_2_HI 0x000000c9 1729a2272e48SRob Clark 1730a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_3_LO 0x000000ca 1731a2272e48SRob Clark 1732a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_3_HI 0x000000cb 1733a2272e48SRob Clark 1734a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_4_LO 0x000000cc 1735a2272e48SRob Clark 1736a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_4_HI 0x000000cd 1737a2272e48SRob Clark 1738a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_5_LO 0x000000ce 1739a2272e48SRob Clark 1740a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_5_HI 0x000000cf 1741a2272e48SRob Clark 1742a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_6_LO 0x000000d0 1743a2272e48SRob Clark 1744a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_6_HI 0x000000d1 1745a2272e48SRob Clark 1746a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_7_LO 0x000000d2 1747a2272e48SRob Clark 1748a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_7_HI 0x000000d3 1749a2272e48SRob Clark 1750a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000d4 1751a2272e48SRob Clark 1752a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000d5 1753a2272e48SRob Clark 1754a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000d6 1755a2272e48SRob Clark 1756a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000d7 1757a2272e48SRob Clark 1758a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000d8 1759a2272e48SRob Clark 1760a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000d9 1761a2272e48SRob Clark 1762a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000da 1763a2272e48SRob Clark 1764a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000db 1765a2272e48SRob Clark 1766a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000dc 1767a2272e48SRob Clark 1768a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000dd 1769a2272e48SRob Clark 1770a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000de 1771a2272e48SRob Clark 1772a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000df 1773a2272e48SRob Clark 1774a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_6_LO 0x000000e0 1775a2272e48SRob Clark 1776a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_6_HI 0x000000e1 1777a2272e48SRob Clark 1778a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_7_LO 0x000000e2 1779a2272e48SRob Clark 1780a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_7_HI 0x000000e3 1781a2272e48SRob Clark 1782a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VPC_0_LO 0x000000e4 1783a2272e48SRob Clark 1784a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VPC_0_HI 0x000000e5 1785a2272e48SRob Clark 1786a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VPC_1_LO 0x000000e6 1787a2272e48SRob Clark 1788a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VPC_1_HI 0x000000e7 1789a2272e48SRob Clark 1790a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VPC_2_LO 0x000000e8 1791a2272e48SRob Clark 1792a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VPC_2_HI 0x000000e9 1793a2272e48SRob Clark 1794a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VPC_3_LO 0x000000ea 1795a2272e48SRob Clark 1796a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VPC_3_HI 0x000000eb 1797a2272e48SRob Clark 1798a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CCU_0_LO 0x000000ec 1799a2272e48SRob Clark 1800a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CCU_0_HI 0x000000ed 1801a2272e48SRob Clark 1802a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CCU_1_LO 0x000000ee 1803a2272e48SRob Clark 1804a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CCU_1_HI 0x000000ef 1805a2272e48SRob Clark 1806a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CCU_2_LO 0x000000f0 1807a2272e48SRob Clark 1808a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CCU_2_HI 0x000000f1 1809a2272e48SRob Clark 1810a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CCU_3_LO 0x000000f2 1811a2272e48SRob Clark 1812a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CCU_3_HI 0x000000f3 1813a2272e48SRob Clark 1814a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TSE_0_LO 0x000000f4 1815a2272e48SRob Clark 1816a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TSE_0_HI 0x000000f5 1817a2272e48SRob Clark 1818a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TSE_1_LO 0x000000f6 1819a2272e48SRob Clark 1820a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TSE_1_HI 0x000000f7 1821a2272e48SRob Clark 1822a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TSE_2_LO 0x000000f8 1823a2272e48SRob Clark 1824a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TSE_2_HI 0x000000f9 1825a2272e48SRob Clark 1826a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TSE_3_LO 0x000000fa 1827a2272e48SRob Clark 1828a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TSE_3_HI 0x000000fb 1829a2272e48SRob Clark 1830a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RAS_0_LO 0x000000fc 1831a2272e48SRob Clark 1832a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RAS_0_HI 0x000000fd 1833a2272e48SRob Clark 1834a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RAS_1_LO 0x000000fe 1835a2272e48SRob Clark 1836a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RAS_1_HI 0x000000ff 1837a2272e48SRob Clark 1838a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RAS_2_LO 0x00000100 1839a2272e48SRob Clark 1840a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RAS_2_HI 0x00000101 1841a2272e48SRob Clark 1842a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RAS_3_LO 0x00000102 1843a2272e48SRob Clark 1844a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RAS_3_HI 0x00000103 1845a2272e48SRob Clark 1846a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_0_LO 0x00000104 1847a2272e48SRob Clark 1848a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_0_HI 0x00000105 1849a2272e48SRob Clark 1850a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_1_LO 0x00000106 1851a2272e48SRob Clark 1852a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_1_HI 0x00000107 1853a2272e48SRob Clark 1854a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_2_LO 0x00000108 1855a2272e48SRob Clark 1856a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_2_HI 0x00000109 1857a2272e48SRob Clark 1858a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_3_LO 0x0000010a 1859a2272e48SRob Clark 1860a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_3_HI 0x0000010b 1861a2272e48SRob Clark 1862a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_4_LO 0x0000010c 1863a2272e48SRob Clark 1864a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_4_HI 0x0000010d 1865a2272e48SRob Clark 1866a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_5_LO 0x0000010e 1867a2272e48SRob Clark 1868a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_5_HI 0x0000010f 1869a2272e48SRob Clark 1870a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_6_LO 0x00000110 1871a2272e48SRob Clark 1872a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_6_HI 0x00000111 1873a2272e48SRob Clark 1874a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_7_LO 0x00000112 1875a2272e48SRob Clark 1876a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_7_HI 0x00000113 1877a2272e48SRob Clark 1878a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_0_LO 0x00000114 1879a2272e48SRob Clark 1880a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115 1881a2272e48SRob Clark 1882a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_1_LO 0x00000116 1883a2272e48SRob Clark 1884a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_1_HI 0x00000117 1885a2272e48SRob Clark 1886a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_2_LO 0x00000118 1887a2272e48SRob Clark 1888a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_2_HI 0x00000119 1889a2272e48SRob Clark 1890a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_3_LO 0x0000011a 1891a2272e48SRob Clark 1892a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_3_HI 0x0000011b 1893a2272e48SRob Clark 1894a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_4_LO 0x0000011c 1895a2272e48SRob Clark 1896a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_4_HI 0x0000011d 1897a2272e48SRob Clark 1898a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_5_LO 0x0000011e 1899a2272e48SRob Clark 1900a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_5_HI 0x0000011f 1901a2272e48SRob Clark 1902a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_6_LO 0x00000120 1903a2272e48SRob Clark 1904a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_6_HI 0x00000121 1905a2272e48SRob Clark 1906a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_7_LO 0x00000122 1907a2272e48SRob Clark 1908a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_7_HI 0x00000123 1909a2272e48SRob Clark 1910a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_0_LO 0x00000124 1911a2272e48SRob Clark 1912a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_0_HI 0x00000125 1913a2272e48SRob Clark 1914a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_1_LO 0x00000126 1915a2272e48SRob Clark 1916a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_1_HI 0x00000127 1917a2272e48SRob Clark 1918a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_2_LO 0x00000128 1919a2272e48SRob Clark 1920a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_2_HI 0x00000129 1921a2272e48SRob Clark 1922a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_3_LO 0x0000012a 1923a2272e48SRob Clark 1924a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_3_HI 0x0000012b 1925a2272e48SRob Clark 1926a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_4_LO 0x0000012c 1927a2272e48SRob Clark 1928a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_4_HI 0x0000012d 1929a2272e48SRob Clark 1930a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_5_LO 0x0000012e 1931a2272e48SRob Clark 1932a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_5_HI 0x0000012f 1933a2272e48SRob Clark 1934a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_6_LO 0x00000130 1935a2272e48SRob Clark 1936a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_6_HI 0x00000131 1937a2272e48SRob Clark 1938a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_7_LO 0x00000132 1939a2272e48SRob Clark 1940a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_7_HI 0x00000133 1941a2272e48SRob Clark 1942a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_8_LO 0x00000134 1943a2272e48SRob Clark 1944a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_8_HI 0x00000135 1945a2272e48SRob Clark 1946a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_9_LO 0x00000136 1947a2272e48SRob Clark 1948a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_9_HI 0x00000137 1949a2272e48SRob Clark 1950a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_10_LO 0x00000138 1951a2272e48SRob Clark 1952a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_10_HI 0x00000139 1953a2272e48SRob Clark 1954a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_11_LO 0x0000013a 1955a2272e48SRob Clark 1956a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_11_HI 0x0000013b 1957a2272e48SRob Clark 1958a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_0_LO 0x0000013c 1959a2272e48SRob Clark 1960a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_0_HI 0x0000013d 1961a2272e48SRob Clark 1962a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_1_LO 0x0000013e 1963a2272e48SRob Clark 1964a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_1_HI 0x0000013f 1965a2272e48SRob Clark 1966a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_2_LO 0x00000140 1967a2272e48SRob Clark 1968a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_2_HI 0x00000141 1969a2272e48SRob Clark 1970a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_3_LO 0x00000142 1971a2272e48SRob Clark 1972a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_3_HI 0x00000143 1973a2272e48SRob Clark 1974a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_4_LO 0x00000144 1975a2272e48SRob Clark 1976a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_4_HI 0x00000145 1977a2272e48SRob Clark 1978a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_5_LO 0x00000146 1979a2272e48SRob Clark 1980a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_5_HI 0x00000147 1981a2272e48SRob Clark 1982a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_6_LO 0x00000148 1983a2272e48SRob Clark 1984a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_6_HI 0x00000149 1985a2272e48SRob Clark 1986a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_7_LO 0x0000014a 1987a2272e48SRob Clark 1988a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_7_HI 0x0000014b 1989a2272e48SRob Clark 1990a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VSC_0_LO 0x0000014c 1991a2272e48SRob Clark 1992a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VSC_0_HI 0x0000014d 1993a2272e48SRob Clark 1994a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VSC_1_LO 0x0000014e 1995a2272e48SRob Clark 1996a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VSC_1_HI 0x0000014f 1997a2272e48SRob Clark 1998a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PWR_0_LO 0x00000166 1999a2272e48SRob Clark 2000a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PWR_0_HI 0x00000167 2001a2272e48SRob Clark 2002a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168 2003a2272e48SRob Clark 2004a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PWR_1_HI 0x00000169 2005a2272e48SRob Clark 2006a2272e48SRob Clark #define REG_A4XX_RBBM_ALWAYSON_COUNTER_LO 0x0000016e 2007a2272e48SRob Clark 2008a2272e48SRob Clark #define REG_A4XX_RBBM_ALWAYSON_COUNTER_HI 0x0000016f 2009a2272e48SRob Clark 2010bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; } 2011bc00ae02SRob Clark 2012bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; } 2013bc00ae02SRob Clark 2014bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; } 2015bc00ae02SRob Clark 2016bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; } 2017bc00ae02SRob Clark 2018bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; } 2019bc00ae02SRob Clark 2020bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; } 2021bc00ae02SRob Clark 2022bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; } 2023bc00ae02SRob Clark 2024bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; } 2025bc00ae02SRob Clark 2026bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; } 2027bc00ae02SRob Clark 2028bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; } 2029bc00ae02SRob Clark 2030bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; } 2031bc00ae02SRob Clark 2032bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; } 2033bc00ae02SRob Clark 2034bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; } 2035bc00ae02SRob Clark 2036bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; } 2037bc00ae02SRob Clark 2038bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; } 2039bc00ae02SRob Clark 2040bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; } 2041bc00ae02SRob Clark 2042bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM 0x00000080 2043bc00ae02SRob Clark 2044bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM 0x00000081 2045bc00ae02SRob Clark 2046bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL_HLSQ 0x0000008a 2047bc00ae02SRob Clark 2048bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_HYST_HLSQ 0x0000008b 2049bc00ae02SRob Clark 2050bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ 0x0000008c 2051bc00ae02SRob Clark 2052bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM 0x0000008d 2053bc00ae02SRob Clark 2054bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; } 2055bc00ae02SRob Clark 2056bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; } 2057bc00ae02SRob Clark 2058a2272e48SRob Clark #define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0 0x00000099 2059a2272e48SRob Clark 2060a2272e48SRob Clark #define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1 0x0000009a 2061a2272e48SRob Clark 2062bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170 2063bc00ae02SRob Clark 2064bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0 0x00000171 2065bc00ae02SRob Clark 2066bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1 0x00000172 2067bc00ae02SRob Clark 2068bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2 0x00000173 2069bc00ae02SRob Clark 2070bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000174 2071bc00ae02SRob Clark 2072bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000175 2073bc00ae02SRob Clark 2074a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000176 2075a2272e48SRob Clark 2076a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000177 2077a2272e48SRob Clark 2078a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000178 2079a2272e48SRob Clark 2080a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_3 0x00000179 2081a2272e48SRob Clark 2082bc00ae02SRob Clark #define REG_A4XX_RBBM_GPU_BUSY_MASKED 0x0000017a 2083bc00ae02SRob Clark 2084bc00ae02SRob Clark #define REG_A4XX_RBBM_INT_0_STATUS 0x0000017d 2085bc00ae02SRob Clark 2086bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_STATUS 0x00000182 2087bc00ae02SRob Clark 2088bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_STATUS 0x00000189 2089bc00ae02SRob Clark 2090bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS 0x0000018c 2091bc00ae02SRob Clark 2092bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS 0x0000018d 2093bc00ae02SRob Clark 2094bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_ERROR_STATUS 0x0000018f 2095bc00ae02SRob Clark 2096bc00ae02SRob Clark #define REG_A4XX_RBBM_STATUS 0x00000191 2097bc00ae02SRob Clark #define A4XX_RBBM_STATUS_HI_BUSY 0x00000001 2098bc00ae02SRob Clark #define A4XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 2099bc00ae02SRob Clark #define A4XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 2100bc00ae02SRob Clark #define A4XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000 2101bc00ae02SRob Clark #define A4XX_RBBM_STATUS_VBIF_BUSY 0x00008000 2102bc00ae02SRob Clark #define A4XX_RBBM_STATUS_TSE_BUSY 0x00010000 2103bc00ae02SRob Clark #define A4XX_RBBM_STATUS_RAS_BUSY 0x00020000 2104bc00ae02SRob Clark #define A4XX_RBBM_STATUS_RB_BUSY 0x00040000 2105bc00ae02SRob Clark #define A4XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 2106bc00ae02SRob Clark #define A4XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 2107bc00ae02SRob Clark #define A4XX_RBBM_STATUS_VFD_BUSY 0x00200000 2108bc00ae02SRob Clark #define A4XX_RBBM_STATUS_VPC_BUSY 0x00400000 2109bc00ae02SRob Clark #define A4XX_RBBM_STATUS_UCHE_BUSY 0x00800000 2110bc00ae02SRob Clark #define A4XX_RBBM_STATUS_SP_BUSY 0x01000000 2111bc00ae02SRob Clark #define A4XX_RBBM_STATUS_TPL1_BUSY 0x02000000 2112bc00ae02SRob Clark #define A4XX_RBBM_STATUS_MARB_BUSY 0x04000000 2113bc00ae02SRob Clark #define A4XX_RBBM_STATUS_VSC_BUSY 0x08000000 2114bc00ae02SRob Clark #define A4XX_RBBM_STATUS_ARB_BUSY 0x10000000 2115bc00ae02SRob Clark #define A4XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 2116bc00ae02SRob Clark #define A4XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000 2117bc00ae02SRob Clark #define A4XX_RBBM_STATUS_GPU_BUSY 0x80000000 2118bc00ae02SRob Clark 2119bc00ae02SRob Clark #define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5 0x0000019f 2120bc00ae02SRob Clark 2121a2272e48SRob Clark #define REG_A4XX_RBBM_POWER_STATUS 0x000001b0 2122a2272e48SRob Clark #define A4XX_RBBM_POWER_STATUS_SP_TP_PWR_ON 0x00100000 2123a2272e48SRob Clark 2124a2272e48SRob Clark #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2 0x000001b8 2125a2272e48SRob Clark 2126bc00ae02SRob Clark #define REG_A4XX_CP_SCRATCH_UMASK 0x00000228 2127bc00ae02SRob Clark 2128bc00ae02SRob Clark #define REG_A4XX_CP_SCRATCH_ADDR 0x00000229 2129bc00ae02SRob Clark 2130bc00ae02SRob Clark #define REG_A4XX_CP_RB_BASE 0x00000200 2131bc00ae02SRob Clark 2132bc00ae02SRob Clark #define REG_A4XX_CP_RB_CNTL 0x00000201 2133bc00ae02SRob Clark 2134bc00ae02SRob Clark #define REG_A4XX_CP_RB_WPTR 0x00000205 2135bc00ae02SRob Clark 2136bc00ae02SRob Clark #define REG_A4XX_CP_RB_RPTR_ADDR 0x00000203 2137bc00ae02SRob Clark 2138bc00ae02SRob Clark #define REG_A4XX_CP_RB_RPTR 0x00000204 2139bc00ae02SRob Clark 2140bc00ae02SRob Clark #define REG_A4XX_CP_IB1_BASE 0x00000206 2141bc00ae02SRob Clark 2142bc00ae02SRob Clark #define REG_A4XX_CP_IB1_BUFSZ 0x00000207 2143bc00ae02SRob Clark 2144bc00ae02SRob Clark #define REG_A4XX_CP_IB2_BASE 0x00000208 2145bc00ae02SRob Clark 2146bc00ae02SRob Clark #define REG_A4XX_CP_IB2_BUFSZ 0x00000209 2147bc00ae02SRob Clark 2148af6cb4c1SRob Clark #define REG_A4XX_CP_ME_NRT_ADDR 0x0000020c 2149af6cb4c1SRob Clark 2150af6cb4c1SRob Clark #define REG_A4XX_CP_ME_NRT_DATA 0x0000020d 2151af6cb4c1SRob Clark 2152bc00ae02SRob Clark #define REG_A4XX_CP_ME_RB_DONE_DATA 0x00000217 2153bc00ae02SRob Clark 2154bc00ae02SRob Clark #define REG_A4XX_CP_QUEUE_THRESH2 0x00000219 2155bc00ae02SRob Clark 2156bc00ae02SRob Clark #define REG_A4XX_CP_MERCIU_SIZE 0x0000021b 2157bc00ae02SRob Clark 2158bc00ae02SRob Clark #define REG_A4XX_CP_ROQ_ADDR 0x0000021c 2159bc00ae02SRob Clark 2160bc00ae02SRob Clark #define REG_A4XX_CP_ROQ_DATA 0x0000021d 2161bc00ae02SRob Clark 2162bc00ae02SRob Clark #define REG_A4XX_CP_MEQ_ADDR 0x0000021e 2163bc00ae02SRob Clark 2164bc00ae02SRob Clark #define REG_A4XX_CP_MEQ_DATA 0x0000021f 2165bc00ae02SRob Clark 2166bc00ae02SRob Clark #define REG_A4XX_CP_MERCIU_ADDR 0x00000220 2167bc00ae02SRob Clark 2168bc00ae02SRob Clark #define REG_A4XX_CP_MERCIU_DATA 0x00000221 2169bc00ae02SRob Clark 2170bc00ae02SRob Clark #define REG_A4XX_CP_MERCIU_DATA2 0x00000222 2171bc00ae02SRob Clark 2172bc00ae02SRob Clark #define REG_A4XX_CP_PFP_UCODE_ADDR 0x00000223 2173bc00ae02SRob Clark 2174bc00ae02SRob Clark #define REG_A4XX_CP_PFP_UCODE_DATA 0x00000224 2175bc00ae02SRob Clark 2176bc00ae02SRob Clark #define REG_A4XX_CP_ME_RAM_WADDR 0x00000225 2177bc00ae02SRob Clark 2178bc00ae02SRob Clark #define REG_A4XX_CP_ME_RAM_RADDR 0x00000226 2179bc00ae02SRob Clark 2180bc00ae02SRob Clark #define REG_A4XX_CP_ME_RAM_DATA 0x00000227 2181bc00ae02SRob Clark 2182bc00ae02SRob Clark #define REG_A4XX_CP_PREEMPT 0x0000022a 2183bc00ae02SRob Clark 2184bc00ae02SRob Clark #define REG_A4XX_CP_CNTL 0x0000022c 2185bc00ae02SRob Clark 2186bc00ae02SRob Clark #define REG_A4XX_CP_ME_CNTL 0x0000022d 2187bc00ae02SRob Clark 2188bc00ae02SRob Clark #define REG_A4XX_CP_DEBUG 0x0000022e 2189bc00ae02SRob Clark 2190bc00ae02SRob Clark #define REG_A4XX_CP_DEBUG_ECO_CONTROL 0x00000231 2191bc00ae02SRob Clark 2192bc00ae02SRob Clark #define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232 2193bc00ae02SRob Clark 2194bc00ae02SRob Clark static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; } 2195bc00ae02SRob Clark 2196bc00ae02SRob Clark static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; } 2197a26ae754SRob Clark #define A4XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff 2198a26ae754SRob Clark #define A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0 2199a26ae754SRob Clark static inline uint32_t A4XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) 2200a26ae754SRob Clark { 2201a26ae754SRob Clark return ((val) << A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A4XX_CP_PROTECT_REG_BASE_ADDR__MASK; 2202a26ae754SRob Clark } 2203a26ae754SRob Clark #define A4XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000 2204a26ae754SRob Clark #define A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24 2205a26ae754SRob Clark static inline uint32_t A4XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) 2206a26ae754SRob Clark { 2207a26ae754SRob Clark return ((val) << A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A4XX_CP_PROTECT_REG_MASK_LEN__MASK; 2208a26ae754SRob Clark } 2209c28c82e9SRob Clark #define A4XX_CP_PROTECT_REG_TRAP_WRITE__MASK 0x20000000 2210c28c82e9SRob Clark #define A4XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT 29 2211c28c82e9SRob Clark static inline uint32_t A4XX_CP_PROTECT_REG_TRAP_WRITE(uint32_t val) 2212c28c82e9SRob Clark { 2213c28c82e9SRob Clark return ((val) << A4XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT) & A4XX_CP_PROTECT_REG_TRAP_WRITE__MASK; 2214c28c82e9SRob Clark } 2215c28c82e9SRob Clark #define A4XX_CP_PROTECT_REG_TRAP_READ__MASK 0x40000000 2216c28c82e9SRob Clark #define A4XX_CP_PROTECT_REG_TRAP_READ__SHIFT 30 2217c28c82e9SRob Clark static inline uint32_t A4XX_CP_PROTECT_REG_TRAP_READ(uint32_t val) 2218c28c82e9SRob Clark { 2219c28c82e9SRob Clark return ((val) << A4XX_CP_PROTECT_REG_TRAP_READ__SHIFT) & A4XX_CP_PROTECT_REG_TRAP_READ__MASK; 2220c28c82e9SRob Clark } 2221bc00ae02SRob Clark 2222bc00ae02SRob Clark #define REG_A4XX_CP_PROTECT_CTRL 0x00000250 2223bc00ae02SRob Clark 2224bc00ae02SRob Clark #define REG_A4XX_CP_ST_BASE 0x000004c0 2225bc00ae02SRob Clark 2226bc00ae02SRob Clark #define REG_A4XX_CP_STQ_AVAIL 0x000004ce 2227bc00ae02SRob Clark 2228bc00ae02SRob Clark #define REG_A4XX_CP_MERCIU_STAT 0x000004d0 2229bc00ae02SRob Clark 2230bc00ae02SRob Clark #define REG_A4XX_CP_WFI_PEND_CTR 0x000004d2 2231bc00ae02SRob Clark 2232bc00ae02SRob Clark #define REG_A4XX_CP_HW_FAULT 0x000004d8 2233bc00ae02SRob Clark 2234bc00ae02SRob Clark #define REG_A4XX_CP_PROTECT_STATUS 0x000004da 2235bc00ae02SRob Clark 2236bc00ae02SRob Clark #define REG_A4XX_CP_EVENTS_IN_FLIGHT 0x000004dd 2237bc00ae02SRob Clark 2238bc00ae02SRob Clark #define REG_A4XX_CP_PERFCTR_CP_SEL_0 0x00000500 2239bc00ae02SRob Clark 2240a2272e48SRob Clark #define REG_A4XX_CP_PERFCTR_CP_SEL_1 0x00000501 2241a2272e48SRob Clark 2242a2272e48SRob Clark #define REG_A4XX_CP_PERFCTR_CP_SEL_2 0x00000502 2243a2272e48SRob Clark 2244a2272e48SRob Clark #define REG_A4XX_CP_PERFCTR_CP_SEL_3 0x00000503 2245a2272e48SRob Clark 2246a2272e48SRob Clark #define REG_A4XX_CP_PERFCTR_CP_SEL_4 0x00000504 2247a2272e48SRob Clark 2248a2272e48SRob Clark #define REG_A4XX_CP_PERFCTR_CP_SEL_5 0x00000505 2249a2272e48SRob Clark 2250a2272e48SRob Clark #define REG_A4XX_CP_PERFCTR_CP_SEL_6 0x00000506 2251a2272e48SRob Clark 2252a2272e48SRob Clark #define REG_A4XX_CP_PERFCTR_CP_SEL_7 0x00000507 2253a2272e48SRob Clark 2254bc00ae02SRob Clark #define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b 2255bc00ae02SRob Clark 2256bc00ae02SRob Clark static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; } 2257bc00ae02SRob Clark 2258bc00ae02SRob Clark static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; } 2259bc00ae02SRob Clark 2260bc00ae02SRob Clark #define REG_A4XX_SP_VS_STATUS 0x00000ec0 2261bc00ae02SRob Clark 2262af6cb4c1SRob Clark #define REG_A4XX_SP_MODE_CONTROL 0x00000ec3 2263af6cb4c1SRob Clark 2264a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_0 0x00000ec4 2265a2272e48SRob Clark 2266a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_1 0x00000ec5 2267a2272e48SRob Clark 2268a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_2 0x00000ec6 2269a2272e48SRob Clark 2270a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_3 0x00000ec7 2271a2272e48SRob Clark 2272a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_4 0x00000ec8 2273a2272e48SRob Clark 2274a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_5 0x00000ec9 2275a2272e48SRob Clark 2276a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_6 0x00000eca 2277a2272e48SRob Clark 2278a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_7 0x00000ecb 2279a2272e48SRob Clark 2280a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_8 0x00000ecc 2281a2272e48SRob Clark 2282a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_9 0x00000ecd 2283a2272e48SRob Clark 2284a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_10 0x00000ece 2285a2272e48SRob Clark 2286bc00ae02SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_11 0x00000ecf 2287bc00ae02SRob Clark 2288bc00ae02SRob Clark #define REG_A4XX_SP_SP_CTRL_REG 0x000022c0 2289bc00ae02SRob Clark #define A4XX_SP_SP_CTRL_REG_BINNING_PASS 0x00080000 2290bc00ae02SRob Clark 2291bc00ae02SRob Clark #define REG_A4XX_SP_INSTR_CACHE_CTRL 0x000022c1 2292af6cb4c1SRob Clark #define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER 0x00000080 2293af6cb4c1SRob Clark #define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER 0x00000100 2294af6cb4c1SRob Clark #define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER 0x00000400 2295bc00ae02SRob Clark 2296bc00ae02SRob Clark #define REG_A4XX_SP_VS_CTRL_REG0 0x000022c4 2297bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 2298bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 2299bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 2300bc00ae02SRob Clark { 2301bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK; 2302bc00ae02SRob Clark } 2303bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_VARYING 0x00000002 2304bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004 2305bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 2306bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 2307bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 2308bc00ae02SRob Clark { 2309bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 2310bc00ae02SRob Clark } 2311a26ae754SRob Clark #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 2312bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 2313bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 2314bc00ae02SRob Clark { 2315bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 2316bc00ae02SRob Clark } 2317bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 2318bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 2319bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 2320bc00ae02SRob Clark { 2321bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK; 2322bc00ae02SRob Clark } 2323bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000 2324bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20 2325bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 2326bc00ae02SRob Clark { 2327bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; 2328bc00ae02SRob Clark } 2329bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000 2330bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000 2331bc00ae02SRob Clark 2332bc00ae02SRob Clark #define REG_A4XX_SP_VS_CTRL_REG1 0x000022c5 2333bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff 2334bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0 2335bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) 2336bc00ae02SRob Clark { 2337bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK; 2338bc00ae02SRob Clark } 2339bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000 2340bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24 2341bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) 2342bc00ae02SRob Clark { 2343bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK; 2344bc00ae02SRob Clark } 2345bc00ae02SRob Clark 2346bc00ae02SRob Clark #define REG_A4XX_SP_VS_PARAM_REG 0x000022c6 2347bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff 2348bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0 2349bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) 2350bc00ae02SRob Clark { 2351bc00ae02SRob Clark return ((val) << A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_POSREGID__MASK; 2352bc00ae02SRob Clark } 2353bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00 2354bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8 2355bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) 2356bc00ae02SRob Clark { 2357bc00ae02SRob Clark return ((val) << A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK; 2358bc00ae02SRob Clark } 2359bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000 2360bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20 2361bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) 2362bc00ae02SRob Clark { 2363bc00ae02SRob Clark return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; 2364bc00ae02SRob Clark } 2365bc00ae02SRob Clark 2366bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 2367bc00ae02SRob Clark 2368bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 2369bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff 2370bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 2371bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 2372bc00ae02SRob Clark { 2373bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_A_REGID__MASK; 2374bc00ae02SRob Clark } 2375bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00 2376bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9 2377bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 2378bc00ae02SRob Clark { 2379bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 2380bc00ae02SRob Clark } 2381bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000 2382bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 2383bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 2384bc00ae02SRob Clark { 2385bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_B_REGID__MASK; 2386bc00ae02SRob Clark } 2387bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000 2388bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25 2389bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 2390bc00ae02SRob Clark { 2391bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 2392bc00ae02SRob Clark } 2393bc00ae02SRob Clark 2394bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; } 2395bc00ae02SRob Clark 2396bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; } 2397bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 2398bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 2399bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 2400bc00ae02SRob Clark { 2401bc00ae02SRob Clark return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 2402bc00ae02SRob Clark } 2403bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 2404bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 2405bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 2406bc00ae02SRob Clark { 2407bc00ae02SRob Clark return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 2408bc00ae02SRob Clark } 2409bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 2410bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 2411bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 2412bc00ae02SRob Clark { 2413bc00ae02SRob Clark return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 2414bc00ae02SRob Clark } 2415bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 2416bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 2417bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 2418bc00ae02SRob Clark { 2419bc00ae02SRob Clark return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 2420bc00ae02SRob Clark } 2421bc00ae02SRob Clark 2422bc00ae02SRob Clark #define REG_A4XX_SP_VS_OBJ_OFFSET_REG 0x000022e0 2423bc00ae02SRob Clark #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2424bc00ae02SRob Clark #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2425bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2426bc00ae02SRob Clark { 2427bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2428bc00ae02SRob Clark } 2429bc00ae02SRob Clark #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2430bc00ae02SRob Clark #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2431bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2432bc00ae02SRob Clark { 2433bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2434bc00ae02SRob Clark } 2435bc00ae02SRob Clark 2436bc00ae02SRob Clark #define REG_A4XX_SP_VS_OBJ_START 0x000022e1 2437bc00ae02SRob Clark 2438bc00ae02SRob Clark #define REG_A4XX_SP_VS_PVT_MEM_PARAM 0x000022e2 2439bc00ae02SRob Clark 2440bc00ae02SRob Clark #define REG_A4XX_SP_VS_PVT_MEM_ADDR 0x000022e3 2441bc00ae02SRob Clark 2442bc00ae02SRob Clark #define REG_A4XX_SP_VS_LENGTH_REG 0x000022e5 2443bc00ae02SRob Clark 2444bc00ae02SRob Clark #define REG_A4XX_SP_FS_CTRL_REG0 0x000022e8 2445bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 2446bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 2447bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 2448bc00ae02SRob Clark { 2449bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK; 2450bc00ae02SRob Clark } 2451bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_VARYING 0x00000002 2452bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004 2453bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 2454bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 2455bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 2456bc00ae02SRob Clark { 2457bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 2458bc00ae02SRob Clark } 2459a26ae754SRob Clark #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 2460bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 2461bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 2462bc00ae02SRob Clark { 2463bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 2464bc00ae02SRob Clark } 2465bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 2466bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 2467bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 2468bc00ae02SRob Clark { 2469bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK; 2470bc00ae02SRob Clark } 2471bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 2472bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 2473bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 2474bc00ae02SRob Clark { 2475bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 2476bc00ae02SRob Clark } 2477bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000 2478bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000 2479bc00ae02SRob Clark 2480bc00ae02SRob Clark #define REG_A4XX_SP_FS_CTRL_REG1 0x000022e9 2481bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff 2482bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0 2483bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) 2484bc00ae02SRob Clark { 2485bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK; 2486bc00ae02SRob Clark } 24878a264743SRob Clark #define A4XX_SP_FS_CTRL_REG1_FACENESS 0x00080000 2488bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG1_VARYING 0x00100000 24898a264743SRob Clark #define A4XX_SP_FS_CTRL_REG1_FRAGCOORD 0x00200000 2490bc00ae02SRob Clark 2491bc00ae02SRob Clark #define REG_A4XX_SP_FS_OBJ_OFFSET_REG 0x000022ea 2492bc00ae02SRob Clark #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2493bc00ae02SRob Clark #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2494bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2495bc00ae02SRob Clark { 2496bc00ae02SRob Clark return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2497bc00ae02SRob Clark } 2498bc00ae02SRob Clark #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2499bc00ae02SRob Clark #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2500bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2501bc00ae02SRob Clark { 2502bc00ae02SRob Clark return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2503bc00ae02SRob Clark } 2504bc00ae02SRob Clark 2505bc00ae02SRob Clark #define REG_A4XX_SP_FS_OBJ_START 0x000022eb 2506bc00ae02SRob Clark 2507bc00ae02SRob Clark #define REG_A4XX_SP_FS_PVT_MEM_PARAM 0x000022ec 2508bc00ae02SRob Clark 2509bc00ae02SRob Clark #define REG_A4XX_SP_FS_PVT_MEM_ADDR 0x000022ed 2510bc00ae02SRob Clark 2511bc00ae02SRob Clark #define REG_A4XX_SP_FS_LENGTH_REG 0x000022ef 2512bc00ae02SRob Clark 2513bc00ae02SRob Clark #define REG_A4XX_SP_FS_OUTPUT_REG 0x000022f0 2514af6cb4c1SRob Clark #define A4XX_SP_FS_OUTPUT_REG_MRT__MASK 0x0000000f 2515af6cb4c1SRob Clark #define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0 2516af6cb4c1SRob Clark static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val) 2517af6cb4c1SRob Clark { 2518af6cb4c1SRob Clark return ((val) << A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_SP_FS_OUTPUT_REG_MRT__MASK; 2519af6cb4c1SRob Clark } 2520bc00ae02SRob Clark #define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080 2521bc00ae02SRob Clark #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00 2522bc00ae02SRob Clark #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8 2523bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) 2524bc00ae02SRob Clark { 2525bc00ae02SRob Clark return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK; 2526bc00ae02SRob Clark } 2527af6cb4c1SRob Clark #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK 0xff000000 2528af6cb4c1SRob Clark #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT 24 2529af6cb4c1SRob Clark static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val) 2530af6cb4c1SRob Clark { 2531af6cb4c1SRob Clark return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK; 2532af6cb4c1SRob Clark } 2533bc00ae02SRob Clark 2534bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; } 2535bc00ae02SRob Clark 2536bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; } 2537bc00ae02SRob Clark #define A4XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff 2538bc00ae02SRob Clark #define A4XX_SP_FS_MRT_REG_REGID__SHIFT 0 2539bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val) 2540bc00ae02SRob Clark { 2541bc00ae02SRob Clark return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK; 2542bc00ae02SRob Clark } 2543bc00ae02SRob Clark #define A4XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100 2544bc00ae02SRob Clark #define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK 0x0003f000 2545bc00ae02SRob Clark #define A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT 12 2546bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val) 2547bc00ae02SRob Clark { 2548bc00ae02SRob Clark return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK; 2549bc00ae02SRob Clark } 25502d3584ebSRob Clark #define A4XX_SP_FS_MRT_REG_COLOR_SRGB 0x00040000 2551bc00ae02SRob Clark 2552af6cb4c1SRob Clark #define REG_A4XX_SP_CS_CTRL_REG0 0x00002300 2553af6cb4c1SRob Clark 2554af6cb4c1SRob Clark #define REG_A4XX_SP_CS_OBJ_OFFSET_REG 0x00002301 2555af6cb4c1SRob Clark 2556af6cb4c1SRob Clark #define REG_A4XX_SP_CS_OBJ_START 0x00002302 2557af6cb4c1SRob Clark 2558af6cb4c1SRob Clark #define REG_A4XX_SP_CS_PVT_MEM_PARAM 0x00002303 2559af6cb4c1SRob Clark 2560af6cb4c1SRob Clark #define REG_A4XX_SP_CS_PVT_MEM_ADDR 0x00002304 2561af6cb4c1SRob Clark 2562af6cb4c1SRob Clark #define REG_A4XX_SP_CS_PVT_MEM_SIZE 0x00002305 2563af6cb4c1SRob Clark 2564af6cb4c1SRob Clark #define REG_A4XX_SP_CS_LENGTH_REG 0x00002306 2565af6cb4c1SRob Clark 2566bc00ae02SRob Clark #define REG_A4XX_SP_HS_OBJ_OFFSET_REG 0x0000230d 2567bc00ae02SRob Clark #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2568bc00ae02SRob Clark #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2569bc00ae02SRob Clark static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2570bc00ae02SRob Clark { 2571bc00ae02SRob Clark return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2572bc00ae02SRob Clark } 2573bc00ae02SRob Clark #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2574bc00ae02SRob Clark #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2575bc00ae02SRob Clark static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2576bc00ae02SRob Clark { 2577bc00ae02SRob Clark return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2578bc00ae02SRob Clark } 2579bc00ae02SRob Clark 2580af6cb4c1SRob Clark #define REG_A4XX_SP_HS_OBJ_START 0x0000230e 2581af6cb4c1SRob Clark 2582af6cb4c1SRob Clark #define REG_A4XX_SP_HS_PVT_MEM_PARAM 0x0000230f 2583af6cb4c1SRob Clark 2584af6cb4c1SRob Clark #define REG_A4XX_SP_HS_PVT_MEM_ADDR 0x00002310 2585af6cb4c1SRob Clark 2586af6cb4c1SRob Clark #define REG_A4XX_SP_HS_LENGTH_REG 0x00002312 2587af6cb4c1SRob Clark 25882d3584ebSRob Clark #define REG_A4XX_SP_DS_PARAM_REG 0x0000231a 25892d3584ebSRob Clark #define A4XX_SP_DS_PARAM_REG_POSREGID__MASK 0x000000ff 25902d3584ebSRob Clark #define A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT 0 25912d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val) 25922d3584ebSRob Clark { 25932d3584ebSRob Clark return ((val) << A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_DS_PARAM_REG_POSREGID__MASK; 25942d3584ebSRob Clark } 25952d3584ebSRob Clark #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000 25962d3584ebSRob Clark #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20 25972d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) 25982d3584ebSRob Clark { 25992d3584ebSRob Clark return ((val) << A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK; 26002d3584ebSRob Clark } 26012d3584ebSRob Clark 26022d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; } 26032d3584ebSRob Clark 26042d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; } 26052d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_A_REGID__MASK 0x000001ff 26062d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_A_REGID__SHIFT 0 26072d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val) 26082d3584ebSRob Clark { 26092d3584ebSRob Clark return ((val) << A4XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_A_REGID__MASK; 26102d3584ebSRob Clark } 26112d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00001e00 26122d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 9 26132d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val) 26142d3584ebSRob Clark { 26152d3584ebSRob Clark return ((val) << A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK; 26162d3584ebSRob Clark } 26172d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_B_REGID__MASK 0x01ff0000 26182d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_B_REGID__SHIFT 16 26192d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val) 26202d3584ebSRob Clark { 26212d3584ebSRob Clark return ((val) << A4XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_B_REGID__MASK; 26222d3584ebSRob Clark } 26232d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x1e000000 26242d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 25 26252d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val) 26262d3584ebSRob Clark { 26272d3584ebSRob Clark return ((val) << A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK; 26282d3584ebSRob Clark } 26292d3584ebSRob Clark 26302d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; } 26312d3584ebSRob Clark 26322d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; } 26332d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 26342d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0 26352d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val) 26362d3584ebSRob Clark { 26372d3584ebSRob Clark return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK; 26382d3584ebSRob Clark } 26392d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 26402d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8 26412d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val) 26422d3584ebSRob Clark { 26432d3584ebSRob Clark return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK; 26442d3584ebSRob Clark } 26452d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 26462d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16 26472d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val) 26482d3584ebSRob Clark { 26492d3584ebSRob Clark return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK; 26502d3584ebSRob Clark } 26512d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 26522d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24 26532d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) 26542d3584ebSRob Clark { 26552d3584ebSRob Clark return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK; 26562d3584ebSRob Clark } 26572d3584ebSRob Clark 2658bc00ae02SRob Clark #define REG_A4XX_SP_DS_OBJ_OFFSET_REG 0x00002334 2659bc00ae02SRob Clark #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2660bc00ae02SRob Clark #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2661bc00ae02SRob Clark static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2662bc00ae02SRob Clark { 2663bc00ae02SRob Clark return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2664bc00ae02SRob Clark } 2665bc00ae02SRob Clark #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2666bc00ae02SRob Clark #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2667bc00ae02SRob Clark static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2668bc00ae02SRob Clark { 2669bc00ae02SRob Clark return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2670bc00ae02SRob Clark } 2671bc00ae02SRob Clark 2672af6cb4c1SRob Clark #define REG_A4XX_SP_DS_OBJ_START 0x00002335 2673af6cb4c1SRob Clark 2674af6cb4c1SRob Clark #define REG_A4XX_SP_DS_PVT_MEM_PARAM 0x00002336 2675af6cb4c1SRob Clark 2676af6cb4c1SRob Clark #define REG_A4XX_SP_DS_PVT_MEM_ADDR 0x00002337 2677af6cb4c1SRob Clark 2678af6cb4c1SRob Clark #define REG_A4XX_SP_DS_LENGTH_REG 0x00002339 2679af6cb4c1SRob Clark 26802d3584ebSRob Clark #define REG_A4XX_SP_GS_PARAM_REG 0x00002341 26812d3584ebSRob Clark #define A4XX_SP_GS_PARAM_REG_POSREGID__MASK 0x000000ff 26822d3584ebSRob Clark #define A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT 0 26832d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val) 26842d3584ebSRob Clark { 26852d3584ebSRob Clark return ((val) << A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_POSREGID__MASK; 26862d3584ebSRob Clark } 26872d3584ebSRob Clark #define A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK 0x0000ff00 26882d3584ebSRob Clark #define A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT 8 26892d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val) 26902d3584ebSRob Clark { 26912d3584ebSRob Clark return ((val) << A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK; 26922d3584ebSRob Clark } 26932d3584ebSRob Clark #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000 26942d3584ebSRob Clark #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20 26952d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) 26962d3584ebSRob Clark { 26972d3584ebSRob Clark return ((val) << A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK; 26982d3584ebSRob Clark } 26992d3584ebSRob Clark 27002d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; } 27012d3584ebSRob Clark 27022d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; } 27032d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_A_REGID__MASK 0x000001ff 27042d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_A_REGID__SHIFT 0 27052d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val) 27062d3584ebSRob Clark { 27072d3584ebSRob Clark return ((val) << A4XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_A_REGID__MASK; 27082d3584ebSRob Clark } 27092d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00001e00 27102d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 9 27112d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val) 27122d3584ebSRob Clark { 27132d3584ebSRob Clark return ((val) << A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK; 27142d3584ebSRob Clark } 27152d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_B_REGID__MASK 0x01ff0000 27162d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_B_REGID__SHIFT 16 27172d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val) 27182d3584ebSRob Clark { 27192d3584ebSRob Clark return ((val) << A4XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_B_REGID__MASK; 27202d3584ebSRob Clark } 27212d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x1e000000 27222d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 25 27232d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val) 27242d3584ebSRob Clark { 27252d3584ebSRob Clark return ((val) << A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK; 27262d3584ebSRob Clark } 27272d3584ebSRob Clark 27282d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; } 27292d3584ebSRob Clark 27302d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; } 27312d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 27322d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0 27332d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val) 27342d3584ebSRob Clark { 27352d3584ebSRob Clark return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK; 27362d3584ebSRob Clark } 27372d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 27382d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8 27392d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val) 27402d3584ebSRob Clark { 27412d3584ebSRob Clark return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK; 27422d3584ebSRob Clark } 27432d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 27442d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16 27452d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val) 27462d3584ebSRob Clark { 27472d3584ebSRob Clark return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK; 27482d3584ebSRob Clark } 27492d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 27502d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24 27512d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) 27522d3584ebSRob Clark { 27532d3584ebSRob Clark return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK; 27542d3584ebSRob Clark } 27552d3584ebSRob Clark 2756bc00ae02SRob Clark #define REG_A4XX_SP_GS_OBJ_OFFSET_REG 0x0000235b 2757bc00ae02SRob Clark #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2758bc00ae02SRob Clark #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2759bc00ae02SRob Clark static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2760bc00ae02SRob Clark { 2761bc00ae02SRob Clark return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2762bc00ae02SRob Clark } 2763bc00ae02SRob Clark #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2764bc00ae02SRob Clark #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2765bc00ae02SRob Clark static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2766bc00ae02SRob Clark { 2767bc00ae02SRob Clark return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2768bc00ae02SRob Clark } 2769bc00ae02SRob Clark 2770af6cb4c1SRob Clark #define REG_A4XX_SP_GS_OBJ_START 0x0000235c 2771af6cb4c1SRob Clark 2772af6cb4c1SRob Clark #define REG_A4XX_SP_GS_PVT_MEM_PARAM 0x0000235d 2773af6cb4c1SRob Clark 2774af6cb4c1SRob Clark #define REG_A4XX_SP_GS_PVT_MEM_ADDR 0x0000235e 2775af6cb4c1SRob Clark 2776bc00ae02SRob Clark #define REG_A4XX_SP_GS_LENGTH_REG 0x00002360 2777bc00ae02SRob Clark 2778bc00ae02SRob Clark #define REG_A4XX_VPC_DEBUG_RAM_SEL 0x00000e60 2779bc00ae02SRob Clark 2780bc00ae02SRob Clark #define REG_A4XX_VPC_DEBUG_RAM_READ 0x00000e61 2781bc00ae02SRob Clark 2782bc00ae02SRob Clark #define REG_A4XX_VPC_DEBUG_ECO_CONTROL 0x00000e64 2783bc00ae02SRob Clark 2784a2272e48SRob Clark #define REG_A4XX_VPC_PERFCTR_VPC_SEL_0 0x00000e65 2785a2272e48SRob Clark 2786a2272e48SRob Clark #define REG_A4XX_VPC_PERFCTR_VPC_SEL_1 0x00000e66 2787a2272e48SRob Clark 2788a2272e48SRob Clark #define REG_A4XX_VPC_PERFCTR_VPC_SEL_2 0x00000e67 2789a2272e48SRob Clark 2790bc00ae02SRob Clark #define REG_A4XX_VPC_PERFCTR_VPC_SEL_3 0x00000e68 2791bc00ae02SRob Clark 2792bc00ae02SRob Clark #define REG_A4XX_VPC_ATTR 0x00002140 2793bc00ae02SRob Clark #define A4XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff 2794bc00ae02SRob Clark #define A4XX_VPC_ATTR_TOTALATTR__SHIFT 0 2795bc00ae02SRob Clark static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val) 2796bc00ae02SRob Clark { 2797bc00ae02SRob Clark return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK; 2798bc00ae02SRob Clark } 2799bc00ae02SRob Clark #define A4XX_VPC_ATTR_PSIZE 0x00000200 2800bc00ae02SRob Clark #define A4XX_VPC_ATTR_THRDASSIGN__MASK 0x00003000 2801bc00ae02SRob Clark #define A4XX_VPC_ATTR_THRDASSIGN__SHIFT 12 2802bc00ae02SRob Clark static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val) 2803bc00ae02SRob Clark { 2804bc00ae02SRob Clark return ((val) << A4XX_VPC_ATTR_THRDASSIGN__SHIFT) & A4XX_VPC_ATTR_THRDASSIGN__MASK; 2805bc00ae02SRob Clark } 2806bc00ae02SRob Clark #define A4XX_VPC_ATTR_ENABLE 0x02000000 2807bc00ae02SRob Clark 2808bc00ae02SRob Clark #define REG_A4XX_VPC_PACK 0x00002141 2809bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMBYPASSVAR__MASK 0x000000ff 2810bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT 0 2811bc00ae02SRob Clark static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val) 2812bc00ae02SRob Clark { 2813bc00ae02SRob Clark return ((val) << A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT) & A4XX_VPC_PACK_NUMBYPASSVAR__MASK; 2814bc00ae02SRob Clark } 2815bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00 2816bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8 2817bc00ae02SRob Clark static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) 2818bc00ae02SRob Clark { 2819bc00ae02SRob Clark return ((val) << A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK; 2820bc00ae02SRob Clark } 2821bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000 2822bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16 2823bc00ae02SRob Clark static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) 2824bc00ae02SRob Clark { 2825bc00ae02SRob Clark return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK; 2826bc00ae02SRob Clark } 2827bc00ae02SRob Clark 2828bc00ae02SRob Clark static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; } 2829bc00ae02SRob Clark 2830bc00ae02SRob Clark static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; } 2831bc00ae02SRob Clark 2832bc00ae02SRob Clark static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; } 2833bc00ae02SRob Clark 2834bc00ae02SRob Clark static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; } 2835bc00ae02SRob Clark 2836bc00ae02SRob Clark #define REG_A4XX_VPC_SO_FLUSH_WADDR_3 0x0000216e 2837bc00ae02SRob Clark 2838bc00ae02SRob Clark #define REG_A4XX_VSC_BIN_SIZE 0x00000c00 2839bc00ae02SRob Clark #define A4XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 2840bc00ae02SRob Clark #define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 2841bc00ae02SRob Clark static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 2842bc00ae02SRob Clark { 2843bc00ae02SRob Clark return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK; 2844bc00ae02SRob Clark } 2845bc00ae02SRob Clark #define A4XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 2846bc00ae02SRob Clark #define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5 2847bc00ae02SRob Clark static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 2848bc00ae02SRob Clark { 2849bc00ae02SRob Clark return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK; 2850bc00ae02SRob Clark } 2851bc00ae02SRob Clark 2852bc00ae02SRob Clark #define REG_A4XX_VSC_SIZE_ADDRESS 0x00000c01 2853bc00ae02SRob Clark 2854bc00ae02SRob Clark #define REG_A4XX_VSC_SIZE_ADDRESS2 0x00000c02 2855bc00ae02SRob Clark 2856bc00ae02SRob Clark #define REG_A4XX_VSC_DEBUG_ECO_CONTROL 0x00000c03 2857bc00ae02SRob Clark 2858bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } 2859bc00ae02SRob Clark 2860bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } 2861bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff 2862bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0 2863bc00ae02SRob Clark static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) 2864bc00ae02SRob Clark { 2865bc00ae02SRob Clark return ((val) << A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_X__MASK; 2866bc00ae02SRob Clark } 2867bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00 2868bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10 2869bc00ae02SRob Clark static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) 2870bc00ae02SRob Clark { 2871bc00ae02SRob Clark return ((val) << A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_Y__MASK; 2872bc00ae02SRob Clark } 2873bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000 2874bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20 2875bc00ae02SRob Clark static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) 2876bc00ae02SRob Clark { 2877bc00ae02SRob Clark return ((val) << A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_W__MASK; 2878bc00ae02SRob Clark } 2879bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000 2880bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24 2881bc00ae02SRob Clark static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) 2882bc00ae02SRob Clark { 2883bc00ae02SRob Clark return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK; 2884bc00ae02SRob Clark } 2885bc00ae02SRob Clark 2886bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 2887bc00ae02SRob Clark 2888bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 2889bc00ae02SRob Clark 2890bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; } 2891bc00ae02SRob Clark 2892bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; } 2893bc00ae02SRob Clark 2894bc00ae02SRob Clark #define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1 0x00000c41 2895bc00ae02SRob Clark 2896bc00ae02SRob Clark #define REG_A4XX_VSC_PERFCTR_VSC_SEL_0 0x00000c50 2897bc00ae02SRob Clark 2898bc00ae02SRob Clark #define REG_A4XX_VSC_PERFCTR_VSC_SEL_1 0x00000c51 2899bc00ae02SRob Clark 2900bc00ae02SRob Clark #define REG_A4XX_VFD_DEBUG_CONTROL 0x00000e40 2901bc00ae02SRob Clark 2902a2272e48SRob Clark #define REG_A4XX_VFD_PERFCTR_VFD_SEL_0 0x00000e43 2903a2272e48SRob Clark 2904a2272e48SRob Clark #define REG_A4XX_VFD_PERFCTR_VFD_SEL_1 0x00000e44 2905a2272e48SRob Clark 2906a2272e48SRob Clark #define REG_A4XX_VFD_PERFCTR_VFD_SEL_2 0x00000e45 2907a2272e48SRob Clark 2908a2272e48SRob Clark #define REG_A4XX_VFD_PERFCTR_VFD_SEL_3 0x00000e46 2909a2272e48SRob Clark 2910a2272e48SRob Clark #define REG_A4XX_VFD_PERFCTR_VFD_SEL_4 0x00000e47 2911a2272e48SRob Clark 2912a2272e48SRob Clark #define REG_A4XX_VFD_PERFCTR_VFD_SEL_5 0x00000e48 2913a2272e48SRob Clark 2914a2272e48SRob Clark #define REG_A4XX_VFD_PERFCTR_VFD_SEL_6 0x00000e49 2915a2272e48SRob Clark 2916bc00ae02SRob Clark #define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 0x00000e4a 2917bc00ae02SRob Clark 2918af6cb4c1SRob Clark #define REG_A4XX_VGT_CL_INITIATOR 0x000021d0 2919af6cb4c1SRob Clark 2920af6cb4c1SRob Clark #define REG_A4XX_VGT_EVENT_INITIATOR 0x000021d9 2921af6cb4c1SRob Clark 2922bc00ae02SRob Clark #define REG_A4XX_VFD_CONTROL_0 0x00002200 2923bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x000000ff 2924bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0 2925bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) 2926bc00ae02SRob Clark { 2927bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK; 2928bc00ae02SRob Clark } 2929bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK 0x0001fe00 2930bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT 9 2931bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val) 2932bc00ae02SRob Clark { 2933bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT) & A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK; 2934bc00ae02SRob Clark } 2935bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x03f00000 2936bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 20 2937bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) 2938bc00ae02SRob Clark { 2939bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK; 2940bc00ae02SRob Clark } 2941bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xfc000000 2942bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 26 2943bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) 2944bc00ae02SRob Clark { 2945bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK; 2946bc00ae02SRob Clark } 2947bc00ae02SRob Clark 2948bc00ae02SRob Clark #define REG_A4XX_VFD_CONTROL_1 0x00002201 2949bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff 2950bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0 2951bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) 2952bc00ae02SRob Clark { 2953bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK; 2954bc00ae02SRob Clark } 2955bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000 2956bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16 2957bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 2958bc00ae02SRob Clark { 2959bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A4XX_VFD_CONTROL_1_REGID4VTX__MASK; 2960bc00ae02SRob Clark } 2961bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000 2962bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_REGID4INST__SHIFT 24 2963bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 2964bc00ae02SRob Clark { 2965bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A4XX_VFD_CONTROL_1_REGID4INST__MASK; 2966bc00ae02SRob Clark } 2967bc00ae02SRob Clark 2968bc00ae02SRob Clark #define REG_A4XX_VFD_CONTROL_2 0x00002202 2969bc00ae02SRob Clark 2970bc00ae02SRob Clark #define REG_A4XX_VFD_CONTROL_3 0x00002203 29718a264743SRob Clark #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK 0x0000ff00 29728a264743SRob Clark #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT 8 29738a264743SRob Clark static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val) 29748a264743SRob Clark { 29758a264743SRob Clark return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK; 29768a264743SRob Clark } 29772d3584ebSRob Clark #define A4XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000 29782d3584ebSRob Clark #define A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16 29792d3584ebSRob Clark static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) 29802d3584ebSRob Clark { 29812d3584ebSRob Clark return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSX__MASK; 29822d3584ebSRob Clark } 29832d3584ebSRob Clark #define A4XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000 29842d3584ebSRob Clark #define A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24 29852d3584ebSRob Clark static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) 29862d3584ebSRob Clark { 29872d3584ebSRob Clark return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSY__MASK; 29882d3584ebSRob Clark } 2989bc00ae02SRob Clark 2990bc00ae02SRob Clark #define REG_A4XX_VFD_CONTROL_4 0x00002204 2991bc00ae02SRob Clark 2992bc00ae02SRob Clark #define REG_A4XX_VFD_INDEX_OFFSET 0x00002208 2993bc00ae02SRob Clark 2994bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; } 2995bc00ae02SRob Clark 2996bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; } 2997bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f 2998bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0 2999bc00ae02SRob Clark static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) 3000bc00ae02SRob Clark { 3001bc00ae02SRob Clark return ((val) << A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK; 3002bc00ae02SRob Clark } 3003bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80 3004bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7 3005bc00ae02SRob Clark static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) 3006bc00ae02SRob Clark { 3007bc00ae02SRob Clark return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK; 3008bc00ae02SRob Clark } 3009bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00080000 30108a264743SRob Clark #define A4XX_VFD_FETCH_INSTR_0_INSTANCED 0x00100000 3011bc00ae02SRob Clark 3012bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; } 3013bc00ae02SRob Clark 3014bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; } 301552260ae4SRob Clark #define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xffffffff 301652260ae4SRob Clark #define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 0 3017bc00ae02SRob Clark static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val) 3018bc00ae02SRob Clark { 301952260ae4SRob Clark return ((val) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK; 3020bc00ae02SRob Clark } 3021bc00ae02SRob Clark 3022bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; } 30238a264743SRob Clark #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK 0x000001ff 30248a264743SRob Clark #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT 0 30258a264743SRob Clark static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val) 30268a264743SRob Clark { 30278a264743SRob Clark return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK; 30288a264743SRob Clark } 3029bc00ae02SRob Clark 3030bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; } 3031bc00ae02SRob Clark 3032bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; } 3033bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f 3034bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0 3035bc00ae02SRob Clark static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) 3036bc00ae02SRob Clark { 3037bc00ae02SRob Clark return ((val) << A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK; 3038bc00ae02SRob Clark } 3039bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010 3040bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0 3041bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6 3042bc00ae02SRob Clark static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val) 3043bc00ae02SRob Clark { 3044bc00ae02SRob Clark return ((val) << A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A4XX_VFD_DECODE_INSTR_FORMAT__MASK; 3045bc00ae02SRob Clark } 3046bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000 3047bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_REGID__SHIFT 12 3048bc00ae02SRob Clark static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val) 3049bc00ae02SRob Clark { 3050bc00ae02SRob Clark return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK; 3051bc00ae02SRob Clark } 30528a264743SRob Clark #define A4XX_VFD_DECODE_INSTR_INT 0x00100000 3053bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000 3054bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT 22 3055bc00ae02SRob Clark static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 3056bc00ae02SRob Clark { 3057bc00ae02SRob Clark return ((val) << A4XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A4XX_VFD_DECODE_INSTR_SWAP__MASK; 3058bc00ae02SRob Clark } 3059bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000 3060bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24 3061bc00ae02SRob Clark static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) 3062bc00ae02SRob Clark { 3063bc00ae02SRob Clark return ((val) << A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK; 3064bc00ae02SRob Clark } 3065bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000 3066bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000 3067bc00ae02SRob Clark 3068bc00ae02SRob Clark #define REG_A4XX_TPL1_DEBUG_ECO_CONTROL 0x00000f00 3069bc00ae02SRob Clark 3070af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_MODE_CONTROL 0x00000f03 3071af6cb4c1SRob Clark 3072a2272e48SRob Clark #define REG_A4XX_TPL1_PERFCTR_TP_SEL_0 0x00000f04 3073a2272e48SRob Clark 3074a2272e48SRob Clark #define REG_A4XX_TPL1_PERFCTR_TP_SEL_1 0x00000f05 3075a2272e48SRob Clark 3076a2272e48SRob Clark #define REG_A4XX_TPL1_PERFCTR_TP_SEL_2 0x00000f06 3077a2272e48SRob Clark 3078a2272e48SRob Clark #define REG_A4XX_TPL1_PERFCTR_TP_SEL_3 0x00000f07 3079a2272e48SRob Clark 3080a2272e48SRob Clark #define REG_A4XX_TPL1_PERFCTR_TP_SEL_4 0x00000f08 3081a2272e48SRob Clark 3082a2272e48SRob Clark #define REG_A4XX_TPL1_PERFCTR_TP_SEL_5 0x00000f09 3083a2272e48SRob Clark 3084a2272e48SRob Clark #define REG_A4XX_TPL1_PERFCTR_TP_SEL_6 0x00000f0a 3085a2272e48SRob Clark 3086bc00ae02SRob Clark #define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 0x00000f0b 3087bc00ae02SRob Clark 3088bc00ae02SRob Clark #define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380 3089bc00ae02SRob Clark 3090af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_TEX_COUNT 0x00002381 3091af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_VS__MASK 0x000000ff 3092af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT 0 3093af6cb4c1SRob Clark static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val) 3094af6cb4c1SRob Clark { 3095af6cb4c1SRob Clark return ((val) << A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_VS__MASK; 3096af6cb4c1SRob Clark } 3097af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_HS__MASK 0x0000ff00 3098af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT 8 3099af6cb4c1SRob Clark static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val) 3100af6cb4c1SRob Clark { 3101af6cb4c1SRob Clark return ((val) << A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_HS__MASK; 3102af6cb4c1SRob Clark } 3103af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_DS__MASK 0x00ff0000 3104af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT 16 3105af6cb4c1SRob Clark static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val) 3106af6cb4c1SRob Clark { 3107af6cb4c1SRob Clark return ((val) << A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_DS__MASK; 3108af6cb4c1SRob Clark } 3109af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_GS__MASK 0xff000000 3110af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT 24 3111af6cb4c1SRob Clark static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val) 3112af6cb4c1SRob Clark { 3113af6cb4c1SRob Clark return ((val) << A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_GS__MASK; 3114af6cb4c1SRob Clark } 3115af6cb4c1SRob Clark 3116af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002384 3117af6cb4c1SRob Clark 3118af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR 0x00002387 3119af6cb4c1SRob Clark 3120af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR 0x0000238a 3121af6cb4c1SRob Clark 3122af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR 0x0000238d 3123af6cb4c1SRob Clark 3124af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_FS_TEX_COUNT 0x000023a0 3125af6cb4c1SRob Clark 3126af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x000023a1 3127af6cb4c1SRob Clark 3128af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_CS_BORDER_COLOR_BASE_ADDR 0x000023a4 3129af6cb4c1SRob Clark 3130af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_CS_SAMPLER_BASE_ADDR 0x000023a5 3131af6cb4c1SRob Clark 3132bc00ae02SRob Clark #define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR 0x000023a6 3133bc00ae02SRob Clark 3134bc00ae02SRob Clark #define REG_A4XX_GRAS_TSE_STATUS 0x00000c80 3135bc00ae02SRob Clark 3136bc00ae02SRob Clark #define REG_A4XX_GRAS_DEBUG_ECO_CONTROL 0x00000c81 3137bc00ae02SRob Clark 3138bc00ae02SRob Clark #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c88 3139bc00ae02SRob Clark 3140a2272e48SRob Clark #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c89 3141a2272e48SRob Clark 3142a2272e48SRob Clark #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c8a 3143a2272e48SRob Clark 3144bc00ae02SRob Clark #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c8b 3145bc00ae02SRob Clark 3146a2272e48SRob Clark #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c8c 3147a2272e48SRob Clark 3148a2272e48SRob Clark #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c8d 3149a2272e48SRob Clark 3150a2272e48SRob Clark #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c8e 3151a2272e48SRob Clark 3152a2272e48SRob Clark #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c8f 3153a2272e48SRob Clark 3154bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000 3155a2272e48SRob Clark #define A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00008000 3156a26ae754SRob Clark #define A4XX_GRAS_CL_CLIP_CNTL_ZNEAR_CLIP_DISABLE 0x00010000 3157a26ae754SRob Clark #define A4XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000 3158a2272e48SRob Clark #define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000 3159bc00ae02SRob Clark 3160c28c82e9SRob Clark #define REG_A4XX_GRAS_CNTL 0x00002003 3161c28c82e9SRob Clark #define A4XX_GRAS_CNTL_IJ_PERSP 0x00000001 3162c28c82e9SRob Clark #define A4XX_GRAS_CNTL_IJ_LINEAR 0x00000002 3163bc00ae02SRob Clark 3164bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_GB_CLIP_ADJ 0x00002004 3165bc00ae02SRob Clark #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff 3166bc00ae02SRob Clark #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0 3167bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) 3168bc00ae02SRob Clark { 3169bc00ae02SRob Clark return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; 3170bc00ae02SRob Clark } 3171bc00ae02SRob Clark #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00 3172bc00ae02SRob Clark #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10 3173bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) 3174bc00ae02SRob Clark { 3175bc00ae02SRob Clark return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; 3176bc00ae02SRob Clark } 3177bc00ae02SRob Clark 3178bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_XOFFSET_0 0x00002008 3179bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff 3180bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0 3181bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val) 3182bc00ae02SRob Clark { 3183bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK; 3184bc00ae02SRob Clark } 3185bc00ae02SRob Clark 3186bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_XSCALE_0 0x00002009 3187bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff 3188bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0 3189bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val) 3190bc00ae02SRob Clark { 3191bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_XSCALE_0__MASK; 3192bc00ae02SRob Clark } 3193bc00ae02SRob Clark 3194bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_YOFFSET_0 0x0000200a 3195bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff 3196bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0 3197bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val) 3198bc00ae02SRob Clark { 3199bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK; 3200bc00ae02SRob Clark } 3201bc00ae02SRob Clark 3202bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_YSCALE_0 0x0000200b 3203bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff 3204bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0 3205bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val) 3206bc00ae02SRob Clark { 3207bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_YSCALE_0__MASK; 3208bc00ae02SRob Clark } 3209bc00ae02SRob Clark 3210bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000200c 3211bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff 3212bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0 3213bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val) 3214bc00ae02SRob Clark { 3215bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK; 3216bc00ae02SRob Clark } 3217bc00ae02SRob Clark 3218bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_ZSCALE_0 0x0000200d 3219bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff 3220bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0 3221bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val) 3222bc00ae02SRob Clark { 3223bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK; 3224bc00ae02SRob Clark } 3225bc00ae02SRob Clark 3226bc00ae02SRob Clark #define REG_A4XX_GRAS_SU_POINT_MINMAX 0x00002070 3227bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 3228bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 3229bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val) 3230bc00ae02SRob Clark { 3231bc00ae02SRob Clark return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 3232bc00ae02SRob Clark } 3233bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 3234bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 3235bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val) 3236bc00ae02SRob Clark { 3237bc00ae02SRob Clark return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 3238bc00ae02SRob Clark } 3239bc00ae02SRob Clark 3240bc00ae02SRob Clark #define REG_A4XX_GRAS_SU_POINT_SIZE 0x00002071 3241bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff 3242bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_SIZE__SHIFT 0 3243bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val) 3244bc00ae02SRob Clark { 3245bc00ae02SRob Clark return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK; 3246bc00ae02SRob Clark } 3247bc00ae02SRob Clark 3248bc00ae02SRob Clark #define REG_A4XX_GRAS_ALPHA_CONTROL 0x00002073 3249bc00ae02SRob Clark #define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE 0x00000004 3250a2272e48SRob Clark #define A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS 0x00000008 3251bc00ae02SRob Clark 3252bc00ae02SRob Clark #define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE 0x00002074 3253bc00ae02SRob Clark #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff 3254bc00ae02SRob Clark #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 3255bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val) 3256bc00ae02SRob Clark { 3257bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; 3258bc00ae02SRob Clark } 3259bc00ae02SRob Clark 3260bc00ae02SRob Clark #define REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00002075 3261bc00ae02SRob Clark #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 3262bc00ae02SRob Clark #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 3263bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 3264bc00ae02SRob Clark { 3265bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 3266bc00ae02SRob Clark } 3267bc00ae02SRob Clark 3268af6cb4c1SRob Clark #define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP 0x00002076 3269af6cb4c1SRob Clark #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK 0xffffffff 3270af6cb4c1SRob Clark #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT 0 3271af6cb4c1SRob Clark static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val) 3272af6cb4c1SRob Clark { 3273af6cb4c1SRob Clark return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK; 3274af6cb4c1SRob Clark } 3275af6cb4c1SRob Clark 32768a264743SRob Clark #define REG_A4XX_GRAS_DEPTH_CONTROL 0x00002077 32778a264743SRob Clark #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK 0x00000003 32788a264743SRob Clark #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT 0 32798a264743SRob Clark static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val) 32808a264743SRob Clark { 32818a264743SRob Clark return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK; 32828a264743SRob Clark } 32838a264743SRob Clark 32848a264743SRob Clark #define REG_A4XX_GRAS_SU_MODE_CONTROL 0x00002078 32858a264743SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001 32868a264743SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002 32878a264743SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004 32888a264743SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8 32898a264743SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3 32908a264743SRob Clark static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) 32918a264743SRob Clark { 32928a264743SRob Clark return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; 32938a264743SRob Clark } 32948a264743SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800 3295a26ae754SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_MSAA_ENABLE 0x00002000 32968a264743SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS 0x00100000 32978a264743SRob Clark 32988a264743SRob Clark #define REG_A4XX_GRAS_SC_CONTROL 0x0000207b 32998a264743SRob Clark #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x0000000c 33008a264743SRob Clark #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 2 33018a264743SRob Clark static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) 33028a264743SRob Clark { 33038a264743SRob Clark return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK; 33048a264743SRob Clark } 33058a264743SRob Clark #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000380 33068a264743SRob Clark #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 7 33078a264743SRob Clark static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val) 33088a264743SRob Clark { 33098a264743SRob Clark return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK; 33108a264743SRob Clark } 33118a264743SRob Clark #define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE 0x00000800 33128a264743SRob Clark #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000 33138a264743SRob Clark #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12 33148a264743SRob Clark static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) 33158a264743SRob Clark { 33168a264743SRob Clark return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK; 33178a264743SRob Clark } 3318bc00ae02SRob Clark 3319bc00ae02SRob Clark #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL 0x0000207c 3320bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 3321bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 3322bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 3323bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 3324bc00ae02SRob Clark { 3325bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; 3326bc00ae02SRob Clark } 3327bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 3328bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 3329bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 3330bc00ae02SRob Clark { 3331bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; 3332bc00ae02SRob Clark } 3333bc00ae02SRob Clark 3334bc00ae02SRob Clark #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR 0x0000207d 3335bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 3336bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 3337bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 3338bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 3339bc00ae02SRob Clark { 3340bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; 3341bc00ae02SRob Clark } 3342bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 3343bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 3344bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 3345bc00ae02SRob Clark { 3346bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; 3347bc00ae02SRob Clark } 3348bc00ae02SRob Clark 3349bc00ae02SRob Clark #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000209c 3350bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 3351bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 3352bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 3353bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 3354bc00ae02SRob Clark { 3355bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 3356bc00ae02SRob Clark } 3357bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 3358bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 3359bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 3360bc00ae02SRob Clark { 3361bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 3362bc00ae02SRob Clark } 3363bc00ae02SRob Clark 3364bc00ae02SRob Clark #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000209d 3365bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 3366bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 3367bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 3368bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 3369bc00ae02SRob Clark { 3370bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 3371bc00ae02SRob Clark } 3372bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 3373bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 3374bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 3375bc00ae02SRob Clark { 3376bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 3377bc00ae02SRob Clark } 3378bc00ae02SRob Clark 33798a264743SRob Clark #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR 0x0000209e 33808a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE 0x80000000 33818a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK 0x00007fff 33828a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT 0 33838a264743SRob Clark static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val) 3384bc00ae02SRob Clark { 33858a264743SRob Clark return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK; 33868a264743SRob Clark } 33878a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK 0x7fff0000 33888a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT 16 33898a264743SRob Clark static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val) 33908a264743SRob Clark { 33918a264743SRob Clark return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK; 3392bc00ae02SRob Clark } 3393bc00ae02SRob Clark 33948a264743SRob Clark #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL 0x0000209f 33958a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE 0x80000000 33968a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK 0x00007fff 33978a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT 0 33988a264743SRob Clark static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val) 3399bc00ae02SRob Clark { 34008a264743SRob Clark return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK; 3401bc00ae02SRob Clark } 34028a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK 0x7fff0000 34038a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT 16 34048a264743SRob Clark static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val) 3405bc00ae02SRob Clark { 34068a264743SRob Clark return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK; 3407bc00ae02SRob Clark } 3408bc00ae02SRob Clark 3409bc00ae02SRob Clark #define REG_A4XX_UCHE_CACHE_MODE_CONTROL 0x00000e80 3410bc00ae02SRob Clark 3411bc00ae02SRob Clark #define REG_A4XX_UCHE_TRAP_BASE_LO 0x00000e83 3412bc00ae02SRob Clark 3413bc00ae02SRob Clark #define REG_A4XX_UCHE_TRAP_BASE_HI 0x00000e84 3414bc00ae02SRob Clark 3415bc00ae02SRob Clark #define REG_A4XX_UCHE_CACHE_STATUS 0x00000e88 3416bc00ae02SRob Clark 3417bc00ae02SRob Clark #define REG_A4XX_UCHE_INVALIDATE0 0x00000e8a 3418bc00ae02SRob Clark 3419bc00ae02SRob Clark #define REG_A4XX_UCHE_INVALIDATE1 0x00000e8b 3420bc00ae02SRob Clark 3421bc00ae02SRob Clark #define REG_A4XX_UCHE_CACHE_WAYS_VFD 0x00000e8c 3422bc00ae02SRob Clark 3423a2272e48SRob Clark #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e8e 3424a2272e48SRob Clark 3425a2272e48SRob Clark #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e8f 3426a2272e48SRob Clark 3427a2272e48SRob Clark #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e90 3428a2272e48SRob Clark 3429a2272e48SRob Clark #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e91 3430a2272e48SRob Clark 3431a2272e48SRob Clark #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e92 3432a2272e48SRob Clark 3433a2272e48SRob Clark #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e93 3434a2272e48SRob Clark 3435a2272e48SRob Clark #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e94 3436a2272e48SRob Clark 3437bc00ae02SRob Clark #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e95 3438bc00ae02SRob Clark 3439bc00ae02SRob Clark #define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD 0x00000e00 3440bc00ae02SRob Clark 3441bc00ae02SRob Clark #define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL 0x00000e04 3442bc00ae02SRob Clark 3443af6cb4c1SRob Clark #define REG_A4XX_HLSQ_MODE_CONTROL 0x00000e05 3444af6cb4c1SRob Clark 3445bc00ae02SRob Clark #define REG_A4XX_HLSQ_PERF_PIPE_MASK 0x00000e0e 3446bc00ae02SRob Clark 3447a2272e48SRob Clark #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e06 3448a2272e48SRob Clark 3449a2272e48SRob Clark #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e07 3450a2272e48SRob Clark 3451a2272e48SRob Clark #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e08 3452a2272e48SRob Clark 3453a2272e48SRob Clark #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e09 3454a2272e48SRob Clark 3455a2272e48SRob Clark #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e0a 3456a2272e48SRob Clark 3457a2272e48SRob Clark #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e0b 3458a2272e48SRob Clark 3459a2272e48SRob Clark #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e0c 3460a2272e48SRob Clark 3461a2272e48SRob Clark #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e0d 3462a2272e48SRob Clark 3463bc00ae02SRob Clark #define REG_A4XX_HLSQ_CONTROL_0_REG 0x000023c0 3464bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010 3465bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4 3466bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) 3467bc00ae02SRob Clark { 3468bc00ae02SRob Clark return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; 3469bc00ae02SRob Clark } 3470bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040 3471bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200 3472bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400 3473bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000 3474bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000 3475bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27 3476bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) 3477bc00ae02SRob Clark { 3478bc00ae02SRob Clark return ((val) << A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK; 3479bc00ae02SRob Clark } 3480bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000 3481bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000 3482bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000 3483bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000 3484bc00ae02SRob Clark 3485bc00ae02SRob Clark #define REG_A4XX_HLSQ_CONTROL_1_REG 0x000023c1 3486bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040 3487bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6 3488bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) 3489bc00ae02SRob Clark { 3490bc00ae02SRob Clark return ((val) << A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK; 3491bc00ae02SRob Clark } 3492bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100 3493bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200 34948a264743SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK 0x00ff0000 34958a264743SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT 16 34968a264743SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val) 34978a264743SRob Clark { 34988a264743SRob Clark return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK; 34998a264743SRob Clark } 3500af6cb4c1SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK 0xff000000 3501af6cb4c1SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT 24 3502af6cb4c1SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val) 3503af6cb4c1SRob Clark { 3504af6cb4c1SRob Clark return ((val) << A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK; 3505af6cb4c1SRob Clark } 3506bc00ae02SRob Clark 3507bc00ae02SRob Clark #define REG_A4XX_HLSQ_CONTROL_2_REG 0x000023c2 3508bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000 3509bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26 3510bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) 3511bc00ae02SRob Clark { 3512bc00ae02SRob Clark return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK; 3513bc00ae02SRob Clark } 35148a264743SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000003fc 35158a264743SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 2 35168a264743SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) 35178a264743SRob Clark { 35188a264743SRob Clark return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; 35198a264743SRob Clark } 3520af6cb4c1SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK 0x0003fc00 3521af6cb4c1SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT 10 3522af6cb4c1SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val) 3523af6cb4c1SRob Clark { 3524af6cb4c1SRob Clark return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK; 3525af6cb4c1SRob Clark } 3526af6cb4c1SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK 0x03fc0000 3527af6cb4c1SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT 18 3528af6cb4c1SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val) 3529af6cb4c1SRob Clark { 3530af6cb4c1SRob Clark return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK; 3531af6cb4c1SRob Clark } 3532bc00ae02SRob Clark 3533bc00ae02SRob Clark #define REG_A4XX_HLSQ_CONTROL_3_REG 0x000023c3 3534c28c82e9SRob Clark #define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff 3535c28c82e9SRob Clark #define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0 3536c28c82e9SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val) 3537bc00ae02SRob Clark { 3538c28c82e9SRob Clark return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK; 3539c28c82e9SRob Clark } 3540c28c82e9SRob Clark #define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00 3541c28c82e9SRob Clark #define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8 3542c28c82e9SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val) 3543c28c82e9SRob Clark { 3544c28c82e9SRob Clark return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK; 3545c28c82e9SRob Clark } 3546c28c82e9SRob Clark #define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000 3547c28c82e9SRob Clark #define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16 3548c28c82e9SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val) 3549c28c82e9SRob Clark { 3550c28c82e9SRob Clark return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK; 3551c28c82e9SRob Clark } 3552c28c82e9SRob Clark #define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000 3553c28c82e9SRob Clark #define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24 3554c28c82e9SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) 3555c28c82e9SRob Clark { 3556c28c82e9SRob Clark return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK; 3557bc00ae02SRob Clark } 3558bc00ae02SRob Clark 3559af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CONTROL_4_REG 0x000023c4 3560c28c82e9SRob Clark #define A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff 3561c28c82e9SRob Clark #define A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0 3562c28c82e9SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val) 3563c28c82e9SRob Clark { 3564c28c82e9SRob Clark return ((val) << A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK; 3565c28c82e9SRob Clark } 3566c28c82e9SRob Clark #define A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00 3567c28c82e9SRob Clark #define A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8 3568c28c82e9SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val) 3569c28c82e9SRob Clark { 3570c28c82e9SRob Clark return ((val) << A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK; 3571c28c82e9SRob Clark } 3572af6cb4c1SRob Clark 3573bc00ae02SRob Clark #define REG_A4XX_HLSQ_VS_CONTROL_REG 0x000023c5 3574bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 3575bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0 3576bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) 3577bc00ae02SRob Clark { 3578bc00ae02SRob Clark return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK; 3579bc00ae02SRob Clark } 35802d756322SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00 3581bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 3582bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3583bc00ae02SRob Clark { 3584bc00ae02SRob Clark return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3585bc00ae02SRob Clark } 35862d756322SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_SSBO_ENABLE 0x00008000 3587af6cb4c1SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00010000 3588bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 3589bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 3590bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3591bc00ae02SRob Clark { 3592bc00ae02SRob Clark return ((val) << A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3593bc00ae02SRob Clark } 3594bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 3595bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24 3596bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) 3597bc00ae02SRob Clark { 3598bc00ae02SRob Clark return ((val) << A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK; 3599bc00ae02SRob Clark } 3600bc00ae02SRob Clark 3601bc00ae02SRob Clark #define REG_A4XX_HLSQ_FS_CONTROL_REG 0x000023c6 3602bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 3603bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0 3604bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) 3605bc00ae02SRob Clark { 3606bc00ae02SRob Clark return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK; 3607bc00ae02SRob Clark } 36082d756322SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00 3609bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 3610bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3611bc00ae02SRob Clark { 3612bc00ae02SRob Clark return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3613bc00ae02SRob Clark } 36142d756322SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_SSBO_ENABLE 0x00008000 3615af6cb4c1SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00010000 3616bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 3617bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 3618bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3619bc00ae02SRob Clark { 3620bc00ae02SRob Clark return ((val) << A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3621bc00ae02SRob Clark } 3622bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 3623bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24 3624bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) 3625bc00ae02SRob Clark { 3626bc00ae02SRob Clark return ((val) << A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK; 3627bc00ae02SRob Clark } 3628bc00ae02SRob Clark 3629bc00ae02SRob Clark #define REG_A4XX_HLSQ_HS_CONTROL_REG 0x000023c7 3630bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 3631bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT 0 3632bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val) 3633bc00ae02SRob Clark { 3634bc00ae02SRob Clark return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK; 3635bc00ae02SRob Clark } 36362d756322SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00 3637bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 3638bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3639bc00ae02SRob Clark { 3640bc00ae02SRob Clark return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3641bc00ae02SRob Clark } 36422d756322SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_SSBO_ENABLE 0x00008000 3643af6cb4c1SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00010000 3644bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 3645bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 3646bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3647bc00ae02SRob Clark { 3648bc00ae02SRob Clark return ((val) << A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3649bc00ae02SRob Clark } 3650bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 3651bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT 24 3652bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val) 3653bc00ae02SRob Clark { 3654bc00ae02SRob Clark return ((val) << A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK; 3655bc00ae02SRob Clark } 3656bc00ae02SRob Clark 3657bc00ae02SRob Clark #define REG_A4XX_HLSQ_DS_CONTROL_REG 0x000023c8 3658bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 3659bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT 0 3660bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val) 3661bc00ae02SRob Clark { 3662bc00ae02SRob Clark return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK; 3663bc00ae02SRob Clark } 36642d756322SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00 3665bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 3666bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3667bc00ae02SRob Clark { 3668bc00ae02SRob Clark return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3669bc00ae02SRob Clark } 36702d756322SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_SSBO_ENABLE 0x00008000 3671af6cb4c1SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00010000 3672bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 3673bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 3674bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3675bc00ae02SRob Clark { 3676bc00ae02SRob Clark return ((val) << A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3677bc00ae02SRob Clark } 3678bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 3679bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT 24 3680bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val) 3681bc00ae02SRob Clark { 3682bc00ae02SRob Clark return ((val) << A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK; 3683bc00ae02SRob Clark } 3684bc00ae02SRob Clark 3685bc00ae02SRob Clark #define REG_A4XX_HLSQ_GS_CONTROL_REG 0x000023c9 3686bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 3687bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT 0 3688bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val) 3689bc00ae02SRob Clark { 3690bc00ae02SRob Clark return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK; 3691bc00ae02SRob Clark } 36922d756322SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00 3693bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 3694bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3695bc00ae02SRob Clark { 3696bc00ae02SRob Clark return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3697bc00ae02SRob Clark } 36982d756322SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_SSBO_ENABLE 0x00008000 3699af6cb4c1SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00010000 3700bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 3701bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 3702bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3703bc00ae02SRob Clark { 3704bc00ae02SRob Clark return ((val) << A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3705bc00ae02SRob Clark } 3706bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 3707bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT 24 3708bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val) 3709bc00ae02SRob Clark { 3710bc00ae02SRob Clark return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK; 3711bc00ae02SRob Clark } 3712bc00ae02SRob Clark 37132d756322SRob Clark #define REG_A4XX_HLSQ_CS_CONTROL_REG 0x000023ca 37142d756322SRob Clark #define A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 37152d756322SRob Clark #define A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__SHIFT 0 37162d756322SRob Clark static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH(uint32_t val) 37172d756322SRob Clark { 37182d756322SRob Clark return ((val) << A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__MASK; 37192d756322SRob Clark } 37202d756322SRob Clark #define A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00 37212d756322SRob Clark #define A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 37222d756322SRob Clark static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 37232d756322SRob Clark { 37242d756322SRob Clark return ((val) << A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 37252d756322SRob Clark } 37262d756322SRob Clark #define A4XX_HLSQ_CS_CONTROL_REG_SSBO_ENABLE 0x00008000 37272d756322SRob Clark #define A4XX_HLSQ_CS_CONTROL_REG_ENABLED 0x00010000 37282d756322SRob Clark #define A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 37292d756322SRob Clark #define A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 37302d756322SRob Clark static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 37312d756322SRob Clark { 37322d756322SRob Clark return ((val) << A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__MASK; 37332d756322SRob Clark } 37342d756322SRob Clark #define A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 37352d756322SRob Clark #define A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__SHIFT 24 37362d756322SRob Clark static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH(uint32_t val) 37372d756322SRob Clark { 37382d756322SRob Clark return ((val) << A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__MASK; 37392d756322SRob Clark } 3740af6cb4c1SRob Clark 3741af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_NDRANGE_0 0x000023cd 37422d756322SRob Clark #define A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__MASK 0x00000003 37432d756322SRob Clark #define A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__SHIFT 0 37442d756322SRob Clark static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM(uint32_t val) 37452d756322SRob Clark { 37462d756322SRob Clark return ((val) << A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__MASK; 37472d756322SRob Clark } 37482d756322SRob Clark #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc 37492d756322SRob Clark #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__SHIFT 2 37502d756322SRob Clark static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX(uint32_t val) 37512d756322SRob Clark { 37522d756322SRob Clark return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__MASK; 37532d756322SRob Clark } 37542d756322SRob Clark #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000 37552d756322SRob Clark #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__SHIFT 12 37562d756322SRob Clark static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY(uint32_t val) 37572d756322SRob Clark { 37582d756322SRob Clark return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__MASK; 37592d756322SRob Clark } 37602d756322SRob Clark #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000 37612d756322SRob Clark #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__SHIFT 22 37622d756322SRob Clark static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ(uint32_t val) 37632d756322SRob Clark { 37642d756322SRob Clark return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__MASK; 37652d756322SRob Clark } 3766af6cb4c1SRob Clark 3767af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_NDRANGE_1 0x000023ce 37682d756322SRob Clark #define A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__MASK 0xffffffff 37692d756322SRob Clark #define A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__SHIFT 0 37702d756322SRob Clark static inline uint32_t A4XX_HLSQ_CL_NDRANGE_1_SIZE_X(uint32_t val) 37712d756322SRob Clark { 37722d756322SRob Clark return ((val) << A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__SHIFT) & A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__MASK; 37732d756322SRob Clark } 3774af6cb4c1SRob Clark 3775af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_NDRANGE_2 0x000023cf 3776af6cb4c1SRob Clark 3777af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_NDRANGE_3 0x000023d0 37782d756322SRob Clark #define A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__MASK 0xffffffff 37792d756322SRob Clark #define A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__SHIFT 0 37802d756322SRob Clark static inline uint32_t A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y(uint32_t val) 37812d756322SRob Clark { 37822d756322SRob Clark return ((val) << A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__SHIFT) & A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__MASK; 37832d756322SRob Clark } 3784af6cb4c1SRob Clark 3785af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_NDRANGE_4 0x000023d1 3786af6cb4c1SRob Clark 3787af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_NDRANGE_5 0x000023d2 37882d756322SRob Clark #define A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__MASK 0xffffffff 37892d756322SRob Clark #define A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__SHIFT 0 37902d756322SRob Clark static inline uint32_t A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z(uint32_t val) 37912d756322SRob Clark { 37922d756322SRob Clark return ((val) << A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__SHIFT) & A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__MASK; 37932d756322SRob Clark } 3794af6cb4c1SRob Clark 3795af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_NDRANGE_6 0x000023d3 3796af6cb4c1SRob Clark 3797af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_CONTROL_0 0x000023d4 37982d756322SRob Clark #define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK 0x000000ff 37992d756322SRob Clark #define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__SHIFT 0 38002d756322SRob Clark static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID(uint32_t val) 38012d756322SRob Clark { 38022d756322SRob Clark return ((val) << A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__SHIFT) & A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK; 38032d756322SRob Clark } 38042d756322SRob Clark #define A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__MASK 0xff000000 38052d756322SRob Clark #define A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__SHIFT 24 38062d756322SRob Clark static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID(uint32_t val) 38072d756322SRob Clark { 38082d756322SRob Clark return ((val) << A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__SHIFT) & A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__MASK; 38092d756322SRob Clark } 3810af6cb4c1SRob Clark 3811af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_CONTROL_1 0x000023d5 3812af6cb4c1SRob Clark 3813af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_KERNEL_CONST 0x000023d6 3814af6cb4c1SRob Clark 3815af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_X 0x000023d7 3816af6cb4c1SRob Clark 3817af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Y 0x000023d8 3818af6cb4c1SRob Clark 3819af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z 0x000023d9 3820af6cb4c1SRob Clark 3821af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_WG_OFFSET 0x000023da 3822af6cb4c1SRob Clark 3823bc00ae02SRob Clark #define REG_A4XX_HLSQ_UPDATE_CONTROL 0x000023db 3824bc00ae02SRob Clark 3825bc00ae02SRob Clark #define REG_A4XX_PC_BINNING_COMMAND 0x00000d00 3826bc00ae02SRob Clark #define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001 3827bc00ae02SRob Clark 3828a26ae754SRob Clark #define REG_A4XX_PC_TESSFACTOR_ADDR 0x00000d08 3829a26ae754SRob Clark 3830bc00ae02SRob Clark #define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c 3831bc00ae02SRob Clark 3832bc00ae02SRob Clark #define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10 3833bc00ae02SRob Clark 3834a2272e48SRob Clark #define REG_A4XX_PC_PERFCTR_PC_SEL_1 0x00000d11 3835a2272e48SRob Clark 3836a2272e48SRob Clark #define REG_A4XX_PC_PERFCTR_PC_SEL_2 0x00000d12 3837a2272e48SRob Clark 3838a2272e48SRob Clark #define REG_A4XX_PC_PERFCTR_PC_SEL_3 0x00000d13 3839a2272e48SRob Clark 3840a2272e48SRob Clark #define REG_A4XX_PC_PERFCTR_PC_SEL_4 0x00000d14 3841a2272e48SRob Clark 3842a2272e48SRob Clark #define REG_A4XX_PC_PERFCTR_PC_SEL_5 0x00000d15 3843a2272e48SRob Clark 3844a2272e48SRob Clark #define REG_A4XX_PC_PERFCTR_PC_SEL_6 0x00000d16 3845a2272e48SRob Clark 3846bc00ae02SRob Clark #define REG_A4XX_PC_PERFCTR_PC_SEL_7 0x00000d17 3847bc00ae02SRob Clark 3848bc00ae02SRob Clark #define REG_A4XX_PC_BIN_BASE 0x000021c0 3849bc00ae02SRob Clark 3850a26ae754SRob Clark #define REG_A4XX_PC_VSTREAM_CONTROL 0x000021c2 3851a26ae754SRob Clark #define A4XX_PC_VSTREAM_CONTROL_SIZE__MASK 0x003f0000 3852a26ae754SRob Clark #define A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT 16 3853a26ae754SRob Clark static inline uint32_t A4XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val) 3854a26ae754SRob Clark { 3855a26ae754SRob Clark return ((val) << A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A4XX_PC_VSTREAM_CONTROL_SIZE__MASK; 3856a26ae754SRob Clark } 3857a26ae754SRob Clark #define A4XX_PC_VSTREAM_CONTROL_N__MASK 0x07c00000 3858a26ae754SRob Clark #define A4XX_PC_VSTREAM_CONTROL_N__SHIFT 22 3859a26ae754SRob Clark static inline uint32_t A4XX_PC_VSTREAM_CONTROL_N(uint32_t val) 3860a26ae754SRob Clark { 3861a26ae754SRob Clark return ((val) << A4XX_PC_VSTREAM_CONTROL_N__SHIFT) & A4XX_PC_VSTREAM_CONTROL_N__MASK; 3862a26ae754SRob Clark } 3863a26ae754SRob Clark 3864bc00ae02SRob Clark #define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4 3865af6cb4c1SRob Clark #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK 0x0000000f 3866af6cb4c1SRob Clark #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT 0 3867af6cb4c1SRob Clark static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val) 3868af6cb4c1SRob Clark { 3869af6cb4c1SRob Clark return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK; 3870af6cb4c1SRob Clark } 3871af6cb4c1SRob Clark #define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000 3872bc00ae02SRob Clark #define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000 3873bc00ae02SRob Clark #define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000 3874bc00ae02SRob Clark 3875a2272e48SRob Clark #define REG_A4XX_PC_PRIM_VTX_CNTL2 0x000021c5 3876a2272e48SRob Clark #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK 0x00000007 3877a2272e48SRob Clark #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT 0 3878a2272e48SRob Clark static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 3879a2272e48SRob Clark { 3880a2272e48SRob Clark return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK; 3881a2272e48SRob Clark } 3882a2272e48SRob Clark #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK 0x00000038 3883a2272e48SRob Clark #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT 3 3884a2272e48SRob Clark static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 3885a2272e48SRob Clark { 3886a2272e48SRob Clark return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK; 3887a2272e48SRob Clark } 3888a2272e48SRob Clark #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_ENABLE 0x00000040 3889bc00ae02SRob Clark 3890bc00ae02SRob Clark #define REG_A4XX_PC_RESTART_INDEX 0x000021c6 3891bc00ae02SRob Clark 3892bc00ae02SRob Clark #define REG_A4XX_PC_GS_PARAM 0x000021e5 3893af6cb4c1SRob Clark #define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff 3894af6cb4c1SRob Clark #define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0 3895af6cb4c1SRob Clark static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val) 3896af6cb4c1SRob Clark { 3897af6cb4c1SRob Clark return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK; 3898af6cb4c1SRob Clark } 3899af6cb4c1SRob Clark #define A4XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800 3900af6cb4c1SRob Clark #define A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11 3901af6cb4c1SRob Clark static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val) 3902af6cb4c1SRob Clark { 3903af6cb4c1SRob Clark return ((val) << A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A4XX_PC_GS_PARAM_INVOCATIONS__MASK; 3904af6cb4c1SRob Clark } 3905af6cb4c1SRob Clark #define A4XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000 3906af6cb4c1SRob Clark #define A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23 3907af6cb4c1SRob Clark static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val) 3908af6cb4c1SRob Clark { 3909af6cb4c1SRob Clark return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK; 3910af6cb4c1SRob Clark } 3911af6cb4c1SRob Clark #define A4XX_PC_GS_PARAM_LAYER 0x80000000 3912bc00ae02SRob Clark 3913bc00ae02SRob Clark #define REG_A4XX_PC_HS_PARAM 0x000021e7 3914af6cb4c1SRob Clark #define A4XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f 3915af6cb4c1SRob Clark #define A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0 3916af6cb4c1SRob Clark static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val) 3917af6cb4c1SRob Clark { 3918af6cb4c1SRob Clark return ((val) << A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A4XX_PC_HS_PARAM_VERTICES_OUT__MASK; 3919af6cb4c1SRob Clark } 3920af6cb4c1SRob Clark #define A4XX_PC_HS_PARAM_SPACING__MASK 0x00600000 3921af6cb4c1SRob Clark #define A4XX_PC_HS_PARAM_SPACING__SHIFT 21 3922af6cb4c1SRob Clark static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val) 3923af6cb4c1SRob Clark { 3924af6cb4c1SRob Clark return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK; 3925af6cb4c1SRob Clark } 3926a26ae754SRob Clark #define A4XX_PC_HS_PARAM_CW 0x00800000 3927a26ae754SRob Clark #define A4XX_PC_HS_PARAM_CONNECTED 0x01000000 3928bc00ae02SRob Clark 3929bc00ae02SRob Clark #define REG_A4XX_VBIF_VERSION 0x00003000 3930bc00ae02SRob Clark 3931bc00ae02SRob Clark #define REG_A4XX_VBIF_CLKON 0x00003001 3932bc00ae02SRob Clark #define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000001 3933bc00ae02SRob Clark 3934bc00ae02SRob Clark #define REG_A4XX_VBIF_ABIT_SORT 0x0000301c 3935bc00ae02SRob Clark 3936bc00ae02SRob Clark #define REG_A4XX_VBIF_ABIT_SORT_CONF 0x0000301d 3937bc00ae02SRob Clark 3938bc00ae02SRob Clark #define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 3939bc00ae02SRob Clark 3940bc00ae02SRob Clark #define REG_A4XX_VBIF_IN_RD_LIM_CONF0 0x0000302c 3941bc00ae02SRob Clark 3942bc00ae02SRob Clark #define REG_A4XX_VBIF_IN_RD_LIM_CONF1 0x0000302d 3943bc00ae02SRob Clark 3944bc00ae02SRob Clark #define REG_A4XX_VBIF_IN_WR_LIM_CONF0 0x00003030 3945bc00ae02SRob Clark 3946bc00ae02SRob Clark #define REG_A4XX_VBIF_IN_WR_LIM_CONF1 0x00003031 3947bc00ae02SRob Clark 3948bc00ae02SRob Clark #define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049 3949bc00ae02SRob Clark 395052260ae4SRob Clark #define REG_A4XX_VBIF_PERF_CNT_EN0 0x000030c0 395152260ae4SRob Clark 395252260ae4SRob Clark #define REG_A4XX_VBIF_PERF_CNT_EN1 0x000030c1 395352260ae4SRob Clark 395452260ae4SRob Clark #define REG_A4XX_VBIF_PERF_CNT_EN2 0x000030c2 395552260ae4SRob Clark 395652260ae4SRob Clark #define REG_A4XX_VBIF_PERF_CNT_EN3 0x000030c3 395752260ae4SRob Clark 395852260ae4SRob Clark #define REG_A4XX_VBIF_PERF_CNT_SEL0 0x000030d0 395952260ae4SRob Clark 396052260ae4SRob Clark #define REG_A4XX_VBIF_PERF_CNT_SEL1 0x000030d1 396152260ae4SRob Clark 396252260ae4SRob Clark #define REG_A4XX_VBIF_PERF_CNT_SEL2 0x000030d2 396352260ae4SRob Clark 396452260ae4SRob Clark #define REG_A4XX_VBIF_PERF_CNT_SEL3 0x000030d3 396552260ae4SRob Clark 396652260ae4SRob Clark #define REG_A4XX_VBIF_PERF_CNT_LOW0 0x000030d8 396752260ae4SRob Clark 396852260ae4SRob Clark #define REG_A4XX_VBIF_PERF_CNT_LOW1 0x000030d9 396952260ae4SRob Clark 397052260ae4SRob Clark #define REG_A4XX_VBIF_PERF_CNT_LOW2 0x000030da 397152260ae4SRob Clark 397252260ae4SRob Clark #define REG_A4XX_VBIF_PERF_CNT_LOW3 0x000030db 397352260ae4SRob Clark 397452260ae4SRob Clark #define REG_A4XX_VBIF_PERF_CNT_HIGH0 0x000030e0 397552260ae4SRob Clark 397652260ae4SRob Clark #define REG_A4XX_VBIF_PERF_CNT_HIGH1 0x000030e1 397752260ae4SRob Clark 397852260ae4SRob Clark #define REG_A4XX_VBIF_PERF_CNT_HIGH2 0x000030e2 397952260ae4SRob Clark 398052260ae4SRob Clark #define REG_A4XX_VBIF_PERF_CNT_HIGH3 0x000030e3 398152260ae4SRob Clark 398252260ae4SRob Clark #define REG_A4XX_VBIF_PERF_PWR_CNT_EN0 0x00003100 398352260ae4SRob Clark 398452260ae4SRob Clark #define REG_A4XX_VBIF_PERF_PWR_CNT_EN1 0x00003101 398552260ae4SRob Clark 398652260ae4SRob Clark #define REG_A4XX_VBIF_PERF_PWR_CNT_EN2 0x00003102 398752260ae4SRob Clark 3988bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_0CC5 0x00000cc5 3989bc00ae02SRob Clark 3990bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_0CC6 0x00000cc6 3991bc00ae02SRob Clark 3992bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_0D01 0x00000d01 3993bc00ae02SRob Clark 3994bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_0E42 0x00000e42 3995bc00ae02SRob Clark 3996bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_0EC2 0x00000ec2 3997bc00ae02SRob Clark 3998bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2001 0x00002001 3999bc00ae02SRob Clark 4000bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_209B 0x0000209b 4001bc00ae02SRob Clark 4002bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_20EF 0x000020ef 4003bc00ae02SRob Clark 4004bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2152 0x00002152 4005bc00ae02SRob Clark 4006bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2153 0x00002153 4007bc00ae02SRob Clark 4008bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2154 0x00002154 4009bc00ae02SRob Clark 4010bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2155 0x00002155 4011bc00ae02SRob Clark 4012bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2156 0x00002156 4013bc00ae02SRob Clark 4014bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2157 0x00002157 4015bc00ae02SRob Clark 4016bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_21C3 0x000021c3 4017bc00ae02SRob Clark 4018bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_21E6 0x000021e6 4019bc00ae02SRob Clark 4020bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2209 0x00002209 4021bc00ae02SRob Clark 4022bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_22D7 0x000022d7 4023bc00ae02SRob Clark 40242d3584ebSRob Clark #define REG_A4XX_UNKNOWN_2352 0x00002352 40252d3584ebSRob Clark 4026bc00ae02SRob Clark #define REG_A4XX_TEX_SAMP_0 0x00000000 40278a264743SRob Clark #define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 4028bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 4029bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_XY_MAG__SHIFT 1 4030bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val) 4031bc00ae02SRob Clark { 4032bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_0_XY_MAG__SHIFT) & A4XX_TEX_SAMP_0_XY_MAG__MASK; 4033bc00ae02SRob Clark } 4034bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 4035bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_XY_MIN__SHIFT 3 4036bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val) 4037bc00ae02SRob Clark { 4038bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_0_XY_MIN__SHIFT) & A4XX_TEX_SAMP_0_XY_MIN__MASK; 4039bc00ae02SRob Clark } 4040bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 4041bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_S__SHIFT 5 4042bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val) 4043bc00ae02SRob Clark { 4044bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_0_WRAP_S__SHIFT) & A4XX_TEX_SAMP_0_WRAP_S__MASK; 4045bc00ae02SRob Clark } 4046bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 4047bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_T__SHIFT 8 4048bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val) 4049bc00ae02SRob Clark { 4050bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_0_WRAP_T__SHIFT) & A4XX_TEX_SAMP_0_WRAP_T__MASK; 4051bc00ae02SRob Clark } 4052bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 4053bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_R__SHIFT 11 4054bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val) 4055bc00ae02SRob Clark { 4056bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK; 4057bc00ae02SRob Clark } 4058af6cb4c1SRob Clark #define A4XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 4059af6cb4c1SRob Clark #define A4XX_TEX_SAMP_0_ANISO__SHIFT 14 4060af6cb4c1SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val) 4061af6cb4c1SRob Clark { 4062af6cb4c1SRob Clark return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK; 4063af6cb4c1SRob Clark } 4064a2272e48SRob Clark #define A4XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000 4065a2272e48SRob Clark #define A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19 4066a2272e48SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_LOD_BIAS(float val) 4067a2272e48SRob Clark { 4068a2272e48SRob Clark return ((((int32_t)(val * 256.0))) << A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A4XX_TEX_SAMP_0_LOD_BIAS__MASK; 4069a2272e48SRob Clark } 4070bc00ae02SRob Clark 4071bc00ae02SRob Clark #define REG_A4XX_TEX_SAMP_1 0x00000001 4072bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e 4073bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 4074bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) 4075bc00ae02SRob Clark { 4076bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK; 4077bc00ae02SRob Clark } 4078a2272e48SRob Clark #define A4XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010 40798a264743SRob Clark #define A4XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 40808a264743SRob Clark #define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 4081bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 4082bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 4083bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val) 4084bc00ae02SRob Clark { 40858a264743SRob Clark return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK; 4086bc00ae02SRob Clark } 4087bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 4088bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 4089bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val) 4090bc00ae02SRob Clark { 40918a264743SRob Clark return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK; 4092bc00ae02SRob Clark } 4093bc00ae02SRob Clark 4094bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_0 0x00000000 4095bc00ae02SRob Clark #define A4XX_TEX_CONST_0_TILED 0x00000001 4096af6cb4c1SRob Clark #define A4XX_TEX_CONST_0_SRGB 0x00000004 4097bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 4098bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_X__SHIFT 4 4099bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val) 4100bc00ae02SRob Clark { 4101bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) & A4XX_TEX_CONST_0_SWIZ_X__MASK; 4102bc00ae02SRob Clark } 4103bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 4104bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 4105bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val) 4106bc00ae02SRob Clark { 4107bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Y__MASK; 4108bc00ae02SRob Clark } 4109bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 4110bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 4111bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val) 4112bc00ae02SRob Clark { 4113bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Z__MASK; 4114bc00ae02SRob Clark } 4115bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 4116bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_W__SHIFT 13 4117bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val) 4118bc00ae02SRob Clark { 4119bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK; 4120bc00ae02SRob Clark } 41218a264743SRob Clark #define A4XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 41228a264743SRob Clark #define A4XX_TEX_CONST_0_MIPLVLS__SHIFT 16 41238a264743SRob Clark static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val) 41248a264743SRob Clark { 41258a264743SRob Clark return ((val) << A4XX_TEX_CONST_0_MIPLVLS__SHIFT) & A4XX_TEX_CONST_0_MIPLVLS__MASK; 41268a264743SRob Clark } 4127bc00ae02SRob Clark #define A4XX_TEX_CONST_0_FMT__MASK 0x1fc00000 4128bc00ae02SRob Clark #define A4XX_TEX_CONST_0_FMT__SHIFT 22 4129bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val) 4130bc00ae02SRob Clark { 4131bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK; 4132bc00ae02SRob Clark } 4133bc00ae02SRob Clark #define A4XX_TEX_CONST_0_TYPE__MASK 0x60000000 4134bc00ae02SRob Clark #define A4XX_TEX_CONST_0_TYPE__SHIFT 29 4135bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val) 4136bc00ae02SRob Clark { 4137bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_TYPE__SHIFT) & A4XX_TEX_CONST_0_TYPE__MASK; 4138bc00ae02SRob Clark } 4139bc00ae02SRob Clark 4140bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_1 0x00000001 4141bc00ae02SRob Clark #define A4XX_TEX_CONST_1_HEIGHT__MASK 0x00007fff 4142bc00ae02SRob Clark #define A4XX_TEX_CONST_1_HEIGHT__SHIFT 0 4143bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val) 4144bc00ae02SRob Clark { 4145bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK; 4146bc00ae02SRob Clark } 4147a2272e48SRob Clark #define A4XX_TEX_CONST_1_WIDTH__MASK 0x3fff8000 4148bc00ae02SRob Clark #define A4XX_TEX_CONST_1_WIDTH__SHIFT 15 4149bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val) 4150bc00ae02SRob Clark { 4151bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK; 4152bc00ae02SRob Clark } 4153bc00ae02SRob Clark 4154bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_2 0x00000002 4155c28c82e9SRob Clark #define A4XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f 4156c28c82e9SRob Clark #define A4XX_TEX_CONST_2_PITCHALIGN__SHIFT 0 4157c28c82e9SRob Clark static inline uint32_t A4XX_TEX_CONST_2_PITCHALIGN(uint32_t val) 41588a264743SRob Clark { 4159c28c82e9SRob Clark return ((val) << A4XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A4XX_TEX_CONST_2_PITCHALIGN__MASK; 41608a264743SRob Clark } 4161bc00ae02SRob Clark #define A4XX_TEX_CONST_2_PITCH__MASK 0x3ffffe00 4162bc00ae02SRob Clark #define A4XX_TEX_CONST_2_PITCH__SHIFT 9 4163bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val) 4164bc00ae02SRob Clark { 4165bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) & A4XX_TEX_CONST_2_PITCH__MASK; 4166bc00ae02SRob Clark } 4167bc00ae02SRob Clark #define A4XX_TEX_CONST_2_SWAP__MASK 0xc0000000 4168bc00ae02SRob Clark #define A4XX_TEX_CONST_2_SWAP__SHIFT 30 4169bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) 4170bc00ae02SRob Clark { 4171bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_2_SWAP__SHIFT) & A4XX_TEX_CONST_2_SWAP__MASK; 4172bc00ae02SRob Clark } 4173bc00ae02SRob Clark 4174bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_3 0x00000003 41758a264743SRob Clark #define A4XX_TEX_CONST_3_LAYERSZ__MASK 0x00003fff 4176bc00ae02SRob Clark #define A4XX_TEX_CONST_3_LAYERSZ__SHIFT 0 4177bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val) 4178bc00ae02SRob Clark { 4179bc00ae02SRob Clark return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK; 4180bc00ae02SRob Clark } 41818a264743SRob Clark #define A4XX_TEX_CONST_3_DEPTH__MASK 0x7ffc0000 41828a264743SRob Clark #define A4XX_TEX_CONST_3_DEPTH__SHIFT 18 41838a264743SRob Clark static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val) 41848a264743SRob Clark { 41858a264743SRob Clark return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK; 41868a264743SRob Clark } 4187bc00ae02SRob Clark 4188bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_4 0x00000004 41898a264743SRob Clark #define A4XX_TEX_CONST_4_LAYERSZ__MASK 0x0000000f 41908a264743SRob Clark #define A4XX_TEX_CONST_4_LAYERSZ__SHIFT 0 41918a264743SRob Clark static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val) 41928a264743SRob Clark { 41938a264743SRob Clark return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK; 41948a264743SRob Clark } 41958a264743SRob Clark #define A4XX_TEX_CONST_4_BASE__MASK 0xffffffe0 41968a264743SRob Clark #define A4XX_TEX_CONST_4_BASE__SHIFT 5 4197bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val) 4198bc00ae02SRob Clark { 41998a264743SRob Clark return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK; 4200bc00ae02SRob Clark } 4201bc00ae02SRob Clark 4202bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_5 0x00000005 4203bc00ae02SRob Clark 4204bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_6 0x00000006 4205bc00ae02SRob Clark 4206bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_7 0x00000007 4207bc00ae02SRob Clark 42082d756322SRob Clark #define REG_A4XX_SSBO_0_0 0x00000000 42092d756322SRob Clark #define A4XX_SSBO_0_0_BASE__MASK 0xffffffe0 42102d756322SRob Clark #define A4XX_SSBO_0_0_BASE__SHIFT 5 42112d756322SRob Clark static inline uint32_t A4XX_SSBO_0_0_BASE(uint32_t val) 42122d756322SRob Clark { 42132d756322SRob Clark return ((val >> 5) << A4XX_SSBO_0_0_BASE__SHIFT) & A4XX_SSBO_0_0_BASE__MASK; 42142d756322SRob Clark } 42152d756322SRob Clark 42162d756322SRob Clark #define REG_A4XX_SSBO_0_1 0x00000001 42172d756322SRob Clark #define A4XX_SSBO_0_1_PITCH__MASK 0x003fffff 42182d756322SRob Clark #define A4XX_SSBO_0_1_PITCH__SHIFT 0 42192d756322SRob Clark static inline uint32_t A4XX_SSBO_0_1_PITCH(uint32_t val) 42202d756322SRob Clark { 42212d756322SRob Clark return ((val) << A4XX_SSBO_0_1_PITCH__SHIFT) & A4XX_SSBO_0_1_PITCH__MASK; 42222d756322SRob Clark } 42232d756322SRob Clark 42242d756322SRob Clark #define REG_A4XX_SSBO_0_2 0x00000002 42252d756322SRob Clark #define A4XX_SSBO_0_2_ARRAY_PITCH__MASK 0x03fff000 42262d756322SRob Clark #define A4XX_SSBO_0_2_ARRAY_PITCH__SHIFT 12 42272d756322SRob Clark static inline uint32_t A4XX_SSBO_0_2_ARRAY_PITCH(uint32_t val) 42282d756322SRob Clark { 42292d756322SRob Clark return ((val >> 12) << A4XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A4XX_SSBO_0_2_ARRAY_PITCH__MASK; 42302d756322SRob Clark } 42312d756322SRob Clark 42322d756322SRob Clark #define REG_A4XX_SSBO_0_3 0x00000003 42332d756322SRob Clark #define A4XX_SSBO_0_3_CPP__MASK 0x0000003f 42342d756322SRob Clark #define A4XX_SSBO_0_3_CPP__SHIFT 0 42352d756322SRob Clark static inline uint32_t A4XX_SSBO_0_3_CPP(uint32_t val) 42362d756322SRob Clark { 42372d756322SRob Clark return ((val) << A4XX_SSBO_0_3_CPP__SHIFT) & A4XX_SSBO_0_3_CPP__MASK; 42382d756322SRob Clark } 42392d756322SRob Clark 42402d756322SRob Clark #define REG_A4XX_SSBO_1_0 0x00000000 42412d756322SRob Clark #define A4XX_SSBO_1_0_CPP__MASK 0x0000001f 42422d756322SRob Clark #define A4XX_SSBO_1_0_CPP__SHIFT 0 42432d756322SRob Clark static inline uint32_t A4XX_SSBO_1_0_CPP(uint32_t val) 42442d756322SRob Clark { 42452d756322SRob Clark return ((val) << A4XX_SSBO_1_0_CPP__SHIFT) & A4XX_SSBO_1_0_CPP__MASK; 42462d756322SRob Clark } 42472d756322SRob Clark #define A4XX_SSBO_1_0_FMT__MASK 0x0000ff00 42482d756322SRob Clark #define A4XX_SSBO_1_0_FMT__SHIFT 8 42492d756322SRob Clark static inline uint32_t A4XX_SSBO_1_0_FMT(enum a4xx_color_fmt val) 42502d756322SRob Clark { 42512d756322SRob Clark return ((val) << A4XX_SSBO_1_0_FMT__SHIFT) & A4XX_SSBO_1_0_FMT__MASK; 42522d756322SRob Clark } 42532d756322SRob Clark #define A4XX_SSBO_1_0_WIDTH__MASK 0xffff0000 42542d756322SRob Clark #define A4XX_SSBO_1_0_WIDTH__SHIFT 16 42552d756322SRob Clark static inline uint32_t A4XX_SSBO_1_0_WIDTH(uint32_t val) 42562d756322SRob Clark { 42572d756322SRob Clark return ((val) << A4XX_SSBO_1_0_WIDTH__SHIFT) & A4XX_SSBO_1_0_WIDTH__MASK; 42582d756322SRob Clark } 42592d756322SRob Clark 42602d756322SRob Clark #define REG_A4XX_SSBO_1_1 0x00000001 42612d756322SRob Clark #define A4XX_SSBO_1_1_HEIGHT__MASK 0x0000ffff 42622d756322SRob Clark #define A4XX_SSBO_1_1_HEIGHT__SHIFT 0 42632d756322SRob Clark static inline uint32_t A4XX_SSBO_1_1_HEIGHT(uint32_t val) 42642d756322SRob Clark { 42652d756322SRob Clark return ((val) << A4XX_SSBO_1_1_HEIGHT__SHIFT) & A4XX_SSBO_1_1_HEIGHT__MASK; 42662d756322SRob Clark } 42672d756322SRob Clark #define A4XX_SSBO_1_1_DEPTH__MASK 0xffff0000 42682d756322SRob Clark #define A4XX_SSBO_1_1_DEPTH__SHIFT 16 42692d756322SRob Clark static inline uint32_t A4XX_SSBO_1_1_DEPTH(uint32_t val) 42702d756322SRob Clark { 42712d756322SRob Clark return ((val) << A4XX_SSBO_1_1_DEPTH__SHIFT) & A4XX_SSBO_1_1_DEPTH__MASK; 42722d756322SRob Clark } 42732d756322SRob Clark 4274bc00ae02SRob Clark 4275bc00ae02SRob Clark #endif /* A4XX_XML */ 4276