1bc00ae02SRob Clark #ifndef A4XX_XML 2bc00ae02SRob Clark #define A4XX_XML 3bc00ae02SRob Clark 4bc00ae02SRob Clark /* Autogenerated file, DO NOT EDIT manually! 5bc00ae02SRob Clark 6bc00ae02SRob Clark This file was generated by the rules-ng-ng headergen tool in this git repository: 7bc00ae02SRob Clark http://github.com/freedreno/envytools/ 8bc00ae02SRob Clark git clone https://github.com/freedreno/envytools.git 9bc00ae02SRob Clark 10bc00ae02SRob Clark The rules-ng-ng source files this header was generated from are: 11bc00ae02SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15) 12bc00ae02SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13bc00ae02SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30) 14bc00ae02SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30) 15bc00ae02SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 15053 bytes, from 2014-11-09 15:45:47) 16bc00ae02SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 63169 bytes, from 2014-11-13 22:44:18) 17bc00ae02SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 49097 bytes, from 2014-11-14 15:38:00) 18bc00ae02SRob Clark 19bc00ae02SRob Clark Copyright (C) 2013-2014 by the following authors: 20bc00ae02SRob Clark - Rob Clark <robdclark@gmail.com> (robclark) 21bc00ae02SRob Clark 22bc00ae02SRob Clark Permission is hereby granted, free of charge, to any person obtaining 23bc00ae02SRob Clark a copy of this software and associated documentation files (the 24bc00ae02SRob Clark "Software"), to deal in the Software without restriction, including 25bc00ae02SRob Clark without limitation the rights to use, copy, modify, merge, publish, 26bc00ae02SRob Clark distribute, sublicense, and/or sell copies of the Software, and to 27bc00ae02SRob Clark permit persons to whom the Software is furnished to do so, subject to 28bc00ae02SRob Clark the following conditions: 29bc00ae02SRob Clark 30bc00ae02SRob Clark The above copyright notice and this permission notice (including the 31bc00ae02SRob Clark next paragraph) shall be included in all copies or substantial 32bc00ae02SRob Clark portions of the Software. 33bc00ae02SRob Clark 34bc00ae02SRob Clark THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35bc00ae02SRob Clark EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 36bc00ae02SRob Clark MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 37bc00ae02SRob Clark IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 38bc00ae02SRob Clark LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 39bc00ae02SRob Clark OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 40bc00ae02SRob Clark WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 41bc00ae02SRob Clark */ 42bc00ae02SRob Clark 43bc00ae02SRob Clark 44bc00ae02SRob Clark enum a4xx_color_fmt { 45bc00ae02SRob Clark RB4_A8_UNORM = 1, 46bc00ae02SRob Clark RB4_R5G6R5_UNORM = 14, 47bc00ae02SRob Clark RB4_Z16_UNORM = 15, 48bc00ae02SRob Clark RB4_R8G8B8_UNORM = 25, 49bc00ae02SRob Clark RB4_R8G8B8A8_UNORM = 26, 50bc00ae02SRob Clark }; 51bc00ae02SRob Clark 52bc00ae02SRob Clark enum a4xx_tile_mode { 53bc00ae02SRob Clark TILE4_LINEAR = 0, 54bc00ae02SRob Clark TILE4_3 = 3, 55bc00ae02SRob Clark }; 56bc00ae02SRob Clark 57bc00ae02SRob Clark enum a4xx_rb_blend_opcode { 58bc00ae02SRob Clark BLEND_DST_PLUS_SRC = 0, 59bc00ae02SRob Clark BLEND_SRC_MINUS_DST = 1, 60bc00ae02SRob Clark BLEND_DST_MINUS_SRC = 2, 61bc00ae02SRob Clark BLEND_MIN_DST_SRC = 3, 62bc00ae02SRob Clark BLEND_MAX_DST_SRC = 4, 63bc00ae02SRob Clark }; 64bc00ae02SRob Clark 65bc00ae02SRob Clark enum a4xx_vtx_fmt { 66bc00ae02SRob Clark VFMT4_FLOAT_32 = 1, 67bc00ae02SRob Clark VFMT4_FLOAT_32_32 = 2, 68bc00ae02SRob Clark VFMT4_FLOAT_32_32_32 = 3, 69bc00ae02SRob Clark VFMT4_FLOAT_32_32_32_32 = 4, 70bc00ae02SRob Clark VFMT4_FLOAT_16 = 5, 71bc00ae02SRob Clark VFMT4_FLOAT_16_16 = 6, 72bc00ae02SRob Clark VFMT4_FLOAT_16_16_16 = 7, 73bc00ae02SRob Clark VFMT4_FLOAT_16_16_16_16 = 8, 74bc00ae02SRob Clark VFMT4_FIXED_32 = 9, 75bc00ae02SRob Clark VFMT4_FIXED_32_32 = 10, 76bc00ae02SRob Clark VFMT4_FIXED_32_32_32 = 11, 77bc00ae02SRob Clark VFMT4_FIXED_32_32_32_32 = 12, 78bc00ae02SRob Clark VFMT4_SHORT_16 = 16, 79bc00ae02SRob Clark VFMT4_SHORT_16_16 = 17, 80bc00ae02SRob Clark VFMT4_SHORT_16_16_16 = 18, 81bc00ae02SRob Clark VFMT4_SHORT_16_16_16_16 = 19, 82bc00ae02SRob Clark VFMT4_USHORT_16 = 20, 83bc00ae02SRob Clark VFMT4_USHORT_16_16 = 21, 84bc00ae02SRob Clark VFMT4_USHORT_16_16_16 = 22, 85bc00ae02SRob Clark VFMT4_USHORT_16_16_16_16 = 23, 86bc00ae02SRob Clark VFMT4_NORM_SHORT_16 = 24, 87bc00ae02SRob Clark VFMT4_NORM_SHORT_16_16 = 25, 88bc00ae02SRob Clark VFMT4_NORM_SHORT_16_16_16 = 26, 89bc00ae02SRob Clark VFMT4_NORM_SHORT_16_16_16_16 = 27, 90bc00ae02SRob Clark VFMT4_NORM_USHORT_16 = 28, 91bc00ae02SRob Clark VFMT4_NORM_USHORT_16_16 = 29, 92bc00ae02SRob Clark VFMT4_NORM_USHORT_16_16_16 = 30, 93bc00ae02SRob Clark VFMT4_NORM_USHORT_16_16_16_16 = 31, 94bc00ae02SRob Clark VFMT4_UBYTE_8 = 40, 95bc00ae02SRob Clark VFMT4_UBYTE_8_8 = 41, 96bc00ae02SRob Clark VFMT4_UBYTE_8_8_8 = 42, 97bc00ae02SRob Clark VFMT4_UBYTE_8_8_8_8 = 43, 98bc00ae02SRob Clark VFMT4_NORM_UBYTE_8 = 44, 99bc00ae02SRob Clark VFMT4_NORM_UBYTE_8_8 = 45, 100bc00ae02SRob Clark VFMT4_NORM_UBYTE_8_8_8 = 46, 101bc00ae02SRob Clark VFMT4_NORM_UBYTE_8_8_8_8 = 47, 102bc00ae02SRob Clark VFMT4_BYTE_8 = 48, 103bc00ae02SRob Clark VFMT4_BYTE_8_8 = 49, 104bc00ae02SRob Clark VFMT4_BYTE_8_8_8 = 50, 105bc00ae02SRob Clark VFMT4_BYTE_8_8_8_8 = 51, 106bc00ae02SRob Clark VFMT4_NORM_BYTE_8 = 52, 107bc00ae02SRob Clark VFMT4_NORM_BYTE_8_8 = 53, 108bc00ae02SRob Clark VFMT4_NORM_BYTE_8_8_8 = 54, 109bc00ae02SRob Clark VFMT4_NORM_BYTE_8_8_8_8 = 55, 110bc00ae02SRob Clark VFMT4_UINT_10_10_10_2 = 60, 111bc00ae02SRob Clark VFMT4_NORM_UINT_10_10_10_2 = 61, 112bc00ae02SRob Clark VFMT4_INT_10_10_10_2 = 62, 113bc00ae02SRob Clark VFMT4_NORM_INT_10_10_10_2 = 63, 114bc00ae02SRob Clark }; 115bc00ae02SRob Clark 116bc00ae02SRob Clark enum a4xx_tex_fmt { 117bc00ae02SRob Clark TFMT4_NORM_USHORT_565 = 11, 118bc00ae02SRob Clark TFMT4_NORM_USHORT_5551 = 10, 119bc00ae02SRob Clark TFMT4_NORM_USHORT_4444 = 8, 120bc00ae02SRob Clark TFMT4_NORM_UINT_X8Z24 = 71, 121bc00ae02SRob Clark TFMT4_NORM_UINT_2_10_10_10 = 33, 122bc00ae02SRob Clark TFMT4_NORM_UINT_A8 = 3, 123bc00ae02SRob Clark TFMT4_NORM_UINT_L8_A8 = 13, 124bc00ae02SRob Clark TFMT4_NORM_UINT_8 = 4, 125bc00ae02SRob Clark TFMT4_NORM_UINT_8_8_8_8 = 28, 126bc00ae02SRob Clark TFMT4_FLOAT_16 = 20, 127bc00ae02SRob Clark TFMT4_FLOAT_16_16 = 40, 128bc00ae02SRob Clark TFMT4_FLOAT_16_16_16_16 = 53, 129bc00ae02SRob Clark TFMT4_FLOAT_32 = 43, 130bc00ae02SRob Clark TFMT4_FLOAT_32_32 = 56, 131bc00ae02SRob Clark TFMT4_FLOAT_32_32_32_32 = 63, 132bc00ae02SRob Clark }; 133bc00ae02SRob Clark 134bc00ae02SRob Clark enum a4xx_depth_format { 135bc00ae02SRob Clark DEPTH4_NONE = 0, 136bc00ae02SRob Clark DEPTH4_16 = 1, 137bc00ae02SRob Clark DEPTH4_24_8 = 2, 138bc00ae02SRob Clark }; 139bc00ae02SRob Clark 140bc00ae02SRob Clark enum a4xx_tex_filter { 141bc00ae02SRob Clark A4XX_TEX_NEAREST = 0, 142bc00ae02SRob Clark A4XX_TEX_LINEAR = 1, 143bc00ae02SRob Clark }; 144bc00ae02SRob Clark 145bc00ae02SRob Clark enum a4xx_tex_clamp { 146bc00ae02SRob Clark A4XX_TEX_REPEAT = 0, 147bc00ae02SRob Clark A4XX_TEX_CLAMP_TO_EDGE = 1, 148bc00ae02SRob Clark A4XX_TEX_MIRROR_REPEAT = 2, 149bc00ae02SRob Clark A4XX_TEX_CLAMP_NONE = 3, 150bc00ae02SRob Clark }; 151bc00ae02SRob Clark 152bc00ae02SRob Clark enum a4xx_tex_swiz { 153bc00ae02SRob Clark A4XX_TEX_X = 0, 154bc00ae02SRob Clark A4XX_TEX_Y = 1, 155bc00ae02SRob Clark A4XX_TEX_Z = 2, 156bc00ae02SRob Clark A4XX_TEX_W = 3, 157bc00ae02SRob Clark A4XX_TEX_ZERO = 4, 158bc00ae02SRob Clark A4XX_TEX_ONE = 5, 159bc00ae02SRob Clark }; 160bc00ae02SRob Clark 161bc00ae02SRob Clark enum a4xx_tex_type { 162bc00ae02SRob Clark A4XX_TEX_1D = 0, 163bc00ae02SRob Clark A4XX_TEX_2D = 1, 164bc00ae02SRob Clark A4XX_TEX_CUBE = 2, 165bc00ae02SRob Clark A4XX_TEX_3D = 3, 166bc00ae02SRob Clark }; 167bc00ae02SRob Clark 168bc00ae02SRob Clark #define A4XX_CGC_HLSQ_EARLY_CYC__MASK 0x00700000 169bc00ae02SRob Clark #define A4XX_CGC_HLSQ_EARLY_CYC__SHIFT 20 170bc00ae02SRob Clark static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) 171bc00ae02SRob Clark { 172bc00ae02SRob Clark return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK; 173bc00ae02SRob Clark } 174bc00ae02SRob Clark #define A4XX_INT0_RBBM_GPU_IDLE 0x00000001 175bc00ae02SRob Clark #define A4XX_INT0_RBBM_AHB_ERROR 0x00000002 176bc00ae02SRob Clark #define A4XX_INT0_RBBM_REG_TIMEOUT 0x00000004 177bc00ae02SRob Clark #define A4XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 178bc00ae02SRob Clark #define A4XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 179bc00ae02SRob Clark #define A4XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020 180bc00ae02SRob Clark #define A4XX_INT0_VFD_ERROR 0x00000040 181bc00ae02SRob Clark #define A4XX_INT0_CP_SW_INT 0x00000080 182bc00ae02SRob Clark #define A4XX_INT0_CP_T0_PACKET_IN_IB 0x00000100 183bc00ae02SRob Clark #define A4XX_INT0_CP_OPCODE_ERROR 0x00000200 184bc00ae02SRob Clark #define A4XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400 185bc00ae02SRob Clark #define A4XX_INT0_CP_HW_FAULT 0x00000800 186bc00ae02SRob Clark #define A4XX_INT0_CP_DMA 0x00001000 187bc00ae02SRob Clark #define A4XX_INT0_CP_IB2_INT 0x00002000 188bc00ae02SRob Clark #define A4XX_INT0_CP_IB1_INT 0x00004000 189bc00ae02SRob Clark #define A4XX_INT0_CP_RB_INT 0x00008000 190bc00ae02SRob Clark #define A4XX_INT0_CP_REG_PROTECT_FAULT 0x00010000 191bc00ae02SRob Clark #define A4XX_INT0_CP_RB_DONE_TS 0x00020000 192bc00ae02SRob Clark #define A4XX_INT0_CP_VS_DONE_TS 0x00040000 193bc00ae02SRob Clark #define A4XX_INT0_CP_PS_DONE_TS 0x00080000 194bc00ae02SRob Clark #define A4XX_INT0_CACHE_FLUSH_TS 0x00100000 195bc00ae02SRob Clark #define A4XX_INT0_CP_AHB_ERROR_HALT 0x00200000 196bc00ae02SRob Clark #define A4XX_INT0_MISC_HANG_DETECT 0x01000000 197bc00ae02SRob Clark #define A4XX_INT0_UCHE_OOB_ACCESS 0x02000000 198bc00ae02SRob Clark #define REG_A4XX_RB_GMEM_BASE_ADDR 0x00000cc0 199bc00ae02SRob Clark 200bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_0 0x00000cc7 201bc00ae02SRob Clark 202bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_1 0x00000cc8 203bc00ae02SRob Clark 204bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_2 0x00000cc9 205bc00ae02SRob Clark 206bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_3 0x00000cca 207bc00ae02SRob Clark 208bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_4 0x00000ccb 209bc00ae02SRob Clark 210bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_5 0x00000ccc 211bc00ae02SRob Clark 212bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_6 0x00000ccd 213bc00ae02SRob Clark 214bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_7 0x00000cce 215bc00ae02SRob Clark 216bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_CCU_SEL_3 0x00000cd2 217bc00ae02SRob Clark 218bc00ae02SRob Clark #define REG_A4XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0 219bc00ae02SRob Clark #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff 220bc00ae02SRob Clark #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0 221bc00ae02SRob Clark static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) 222bc00ae02SRob Clark { 223bc00ae02SRob Clark return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK; 224bc00ae02SRob Clark } 225bc00ae02SRob Clark #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x3fff0000 226bc00ae02SRob Clark #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 16 227bc00ae02SRob Clark static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) 228bc00ae02SRob Clark { 229bc00ae02SRob Clark return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK; 230bc00ae02SRob Clark } 231bc00ae02SRob Clark 232bc00ae02SRob Clark #define REG_A4XX_RB_CLEAR_COLOR_DW0 0x000020cc 233bc00ae02SRob Clark 234bc00ae02SRob Clark #define REG_A4XX_RB_CLEAR_COLOR_DW1 0x000020cd 235bc00ae02SRob Clark 236bc00ae02SRob Clark #define REG_A4XX_RB_CLEAR_COLOR_DW2 0x000020ce 237bc00ae02SRob Clark 238bc00ae02SRob Clark #define REG_A4XX_RB_CLEAR_COLOR_DW3 0x000020cf 239bc00ae02SRob Clark 240bc00ae02SRob Clark #define REG_A4XX_RB_MODE_CONTROL 0x000020a0 241bc00ae02SRob Clark #define A4XX_RB_MODE_CONTROL_WIDTH__MASK 0x0000003f 242bc00ae02SRob Clark #define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT 0 243bc00ae02SRob Clark static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) 244bc00ae02SRob Clark { 245bc00ae02SRob Clark return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK; 246bc00ae02SRob Clark } 247bc00ae02SRob Clark #define A4XX_RB_MODE_CONTROL_HEIGHT__MASK 0x00003f00 248bc00ae02SRob Clark #define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT 8 249bc00ae02SRob Clark static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) 250bc00ae02SRob Clark { 251bc00ae02SRob Clark return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK; 252bc00ae02SRob Clark } 253bc00ae02SRob Clark 254bc00ae02SRob Clark #define REG_A4XX_RB_RENDER_CONTROL 0x000020a1 255bc00ae02SRob Clark #define A4XX_RB_RENDER_CONTROL_BINNING_PASS 0x00000001 256bc00ae02SRob Clark #define A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00000020 257bc00ae02SRob Clark 258bc00ae02SRob Clark #define REG_A4XX_RB_MSAA_CONTROL 0x000020a2 259bc00ae02SRob Clark #define A4XX_RB_MSAA_CONTROL_DISABLE 0x00001000 260bc00ae02SRob Clark #define A4XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000e000 261bc00ae02SRob Clark #define A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 13 262bc00ae02SRob Clark static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val) 263bc00ae02SRob Clark { 264bc00ae02SRob Clark return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK; 265bc00ae02SRob Clark } 266bc00ae02SRob Clark 267bc00ae02SRob Clark #define REG_A4XX_RB_MSAA_CONTROL2 0x000020a3 268bc00ae02SRob Clark #define A4XX_RB_MSAA_CONTROL2_MSAA_SAMPLES__MASK 0x00000380 269bc00ae02SRob Clark #define A4XX_RB_MSAA_CONTROL2_MSAA_SAMPLES__SHIFT 7 270bc00ae02SRob Clark static inline uint32_t A4XX_RB_MSAA_CONTROL2_MSAA_SAMPLES(uint32_t val) 271bc00ae02SRob Clark { 272bc00ae02SRob Clark return ((val) << A4XX_RB_MSAA_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL2_MSAA_SAMPLES__MASK; 273bc00ae02SRob Clark } 274bc00ae02SRob Clark #define A4XX_RB_MSAA_CONTROL2_VARYING 0x00001000 275bc00ae02SRob Clark 276bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; } 277bc00ae02SRob Clark 278bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; } 279bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008 280bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL_BLEND 0x00000010 281bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL_BLEND2 0x00000020 282bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL_FASTCLEAR 0x00000400 283bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL_B11 0x00000800 284bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000 285bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24 286bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 287bc00ae02SRob Clark { 288bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 289bc00ae02SRob Clark } 290bc00ae02SRob Clark 291bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; } 292bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f 293bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 294bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val) 295bc00ae02SRob Clark { 296bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 297bc00ae02SRob Clark } 298bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00000600 299bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 9 300bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 301bc00ae02SRob Clark { 302bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK; 303bc00ae02SRob Clark } 304bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00001800 305bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 11 306bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 307bc00ae02SRob Clark { 308bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 309bc00ae02SRob Clark } 310bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0x007fc000 311bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 14 312bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) 313bc00ae02SRob Clark { 314bc00ae02SRob Clark return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; 315bc00ae02SRob Clark } 316bc00ae02SRob Clark 317bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; } 318bc00ae02SRob Clark 319bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; } 320bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL3_STRIDE__MASK 0x0001fff8 321bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT 3 322bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val) 323bc00ae02SRob Clark { 324bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT) & A4XX_RB_MRT_CONTROL3_STRIDE__MASK; 325bc00ae02SRob Clark } 326bc00ae02SRob Clark 327bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; } 328bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 329bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 330bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 331bc00ae02SRob Clark { 332bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 333bc00ae02SRob Clark } 334bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 335bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 336bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a4xx_rb_blend_opcode val) 337bc00ae02SRob Clark { 338bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 339bc00ae02SRob Clark } 340bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 341bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 342bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 343bc00ae02SRob Clark { 344bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 345bc00ae02SRob Clark } 346bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 347bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 348bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 349bc00ae02SRob Clark { 350bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 351bc00ae02SRob Clark } 352bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 353bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 354bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a4xx_rb_blend_opcode val) 355bc00ae02SRob Clark { 356bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 357bc00ae02SRob Clark } 358bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 359bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 360bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 361bc00ae02SRob Clark { 362bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 363bc00ae02SRob Clark } 364bc00ae02SRob Clark 365bc00ae02SRob Clark #define REG_A4XX_RB_ALPHA_CONTROL 0x000020f8 366bc00ae02SRob Clark #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 367bc00ae02SRob Clark #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 368bc00ae02SRob Clark #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 369bc00ae02SRob Clark static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 370bc00ae02SRob Clark { 371bc00ae02SRob Clark return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; 372bc00ae02SRob Clark } 373bc00ae02SRob Clark 374bc00ae02SRob Clark #define REG_A4XX_RB_FS_OUTPUT 0x000020f9 375bc00ae02SRob Clark #define A4XX_RB_FS_OUTPUT_ENABLE_COLOR_PIPE 0x00000001 376bc00ae02SRob Clark #define A4XX_RB_FS_OUTPUT_FAST_CLEAR 0x00000100 377bc00ae02SRob Clark #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000 378bc00ae02SRob Clark #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT 16 379bc00ae02SRob Clark static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val) 380bc00ae02SRob Clark { 381bc00ae02SRob Clark return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK; 382bc00ae02SRob Clark } 383bc00ae02SRob Clark 384bc00ae02SRob Clark #define REG_A4XX_RB_RENDER_CONTROL3 0x000020fb 385bc00ae02SRob Clark #define A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__MASK 0x0000001f 386bc00ae02SRob Clark #define A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__SHIFT 0 387bc00ae02SRob Clark static inline uint32_t A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE(uint32_t val) 388bc00ae02SRob Clark { 389bc00ae02SRob Clark return ((val) << A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__SHIFT) & A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE__MASK; 390bc00ae02SRob Clark } 391bc00ae02SRob Clark 392bc00ae02SRob Clark #define REG_A4XX_RB_COPY_CONTROL 0x000020fc 393bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003 394bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0 395bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) 396bc00ae02SRob Clark { 397bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK; 398bc00ae02SRob Clark } 399bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_MODE__MASK 0x00000070 400bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_MODE__SHIFT 4 401bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) 402bc00ae02SRob Clark { 403bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_CONTROL_MODE__SHIFT) & A4XX_RB_COPY_CONTROL_MODE__MASK; 404bc00ae02SRob Clark } 405bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00 406bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8 407bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) 408bc00ae02SRob Clark { 409bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK; 410bc00ae02SRob Clark } 411bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000 412bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14 413bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) 414bc00ae02SRob Clark { 415bc00ae02SRob Clark return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK; 416bc00ae02SRob Clark } 417bc00ae02SRob Clark 418bc00ae02SRob Clark #define REG_A4XX_RB_COPY_DEST_BASE 0x000020fd 419bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_BASE_BASE__MASK 0xfffffff0 420bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT 4 421bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val) 422bc00ae02SRob Clark { 423bc00ae02SRob Clark return ((val >> 4) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK; 424bc00ae02SRob Clark } 425bc00ae02SRob Clark 426bc00ae02SRob Clark #define REG_A4XX_RB_COPY_DEST_PITCH 0x000020fe 427bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff 428bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0 429bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) 430bc00ae02SRob Clark { 431bc00ae02SRob Clark return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK; 432bc00ae02SRob Clark } 433bc00ae02SRob Clark 434bc00ae02SRob Clark #define REG_A4XX_RB_COPY_DEST_INFO 0x000020ff 435bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc 436bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2 437bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val) 438bc00ae02SRob Clark { 439bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A4XX_RB_COPY_DEST_INFO_FORMAT__MASK; 440bc00ae02SRob Clark } 441bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 442bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 443bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) 444bc00ae02SRob Clark { 445bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A4XX_RB_COPY_DEST_INFO_SWAP__MASK; 446bc00ae02SRob Clark } 447bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 448bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 449bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 450bc00ae02SRob Clark { 451bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 452bc00ae02SRob Clark } 453bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000 454bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14 455bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) 456bc00ae02SRob Clark { 457bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK; 458bc00ae02SRob Clark } 459bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000 460bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18 461bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) 462bc00ae02SRob Clark { 463bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK; 464bc00ae02SRob Clark } 465bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_TILE__MASK 0x03000000 466bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_TILE__SHIFT 24 467bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val) 468bc00ae02SRob Clark { 469bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A4XX_RB_COPY_DEST_INFO_TILE__MASK; 470bc00ae02SRob Clark } 471bc00ae02SRob Clark 472bc00ae02SRob Clark #define REG_A4XX_RB_FS_OUTPUT_REG 0x00002100 473bc00ae02SRob Clark #define A4XX_RB_FS_OUTPUT_REG_COLOR_PIPE_ENABLE 0x00000001 474bc00ae02SRob Clark #define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z 0x00000020 475bc00ae02SRob Clark 476bc00ae02SRob Clark #define REG_A4XX_RB_DEPTH_CONTROL 0x00002101 477bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001 478bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002 479bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004 480bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070 481bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4 482bc00ae02SRob Clark static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) 483bc00ae02SRob Clark { 484bc00ae02SRob Clark return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK; 485bc00ae02SRob Clark } 486bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080 487bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000 488bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000 489bc00ae02SRob Clark 490bc00ae02SRob Clark #define REG_A4XX_RB_DEPTH_CLEAR 0x00002102 491bc00ae02SRob Clark 492bc00ae02SRob Clark #define REG_A4XX_RB_DEPTH_INFO 0x00002103 493bc00ae02SRob Clark #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003 494bc00ae02SRob Clark #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 495bc00ae02SRob Clark static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val) 496bc00ae02SRob Clark { 497bc00ae02SRob Clark return ((val) << A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 498bc00ae02SRob Clark } 499bc00ae02SRob Clark #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 500bc00ae02SRob Clark #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 501bc00ae02SRob Clark static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 502bc00ae02SRob Clark { 503bc00ae02SRob Clark return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 504bc00ae02SRob Clark } 505bc00ae02SRob Clark 506bc00ae02SRob Clark #define REG_A4XX_RB_DEPTH_PITCH 0x00002104 507bc00ae02SRob Clark #define A4XX_RB_DEPTH_PITCH__MASK 0xffffffff 508bc00ae02SRob Clark #define A4XX_RB_DEPTH_PITCH__SHIFT 0 509bc00ae02SRob Clark static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val) 510bc00ae02SRob Clark { 511bc00ae02SRob Clark return ((val >> 4) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK; 512bc00ae02SRob Clark } 513bc00ae02SRob Clark 514bc00ae02SRob Clark #define REG_A4XX_RB_DEPTH_PITCH2 0x00002105 515bc00ae02SRob Clark #define A4XX_RB_DEPTH_PITCH2__MASK 0xffffffff 516bc00ae02SRob Clark #define A4XX_RB_DEPTH_PITCH2__SHIFT 0 517bc00ae02SRob Clark static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val) 518bc00ae02SRob Clark { 519bc00ae02SRob Clark return ((val >> 4) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK; 520bc00ae02SRob Clark } 521bc00ae02SRob Clark 522bc00ae02SRob Clark #define REG_A4XX_RB_STENCIL_CONTROL 0x00002106 523bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 524bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 525bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 526bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 527bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 528bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 529bc00ae02SRob Clark { 530bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC__MASK; 531bc00ae02SRob Clark } 532bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 533bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 534bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 535bc00ae02SRob Clark { 536bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL__MASK; 537bc00ae02SRob Clark } 538bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 539bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 540bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 541bc00ae02SRob Clark { 542bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS__MASK; 543bc00ae02SRob Clark } 544bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 545bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 546bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 547bc00ae02SRob Clark { 548bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 549bc00ae02SRob Clark } 550bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 551bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 552bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 553bc00ae02SRob Clark { 554bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 555bc00ae02SRob Clark } 556bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 557bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 558bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 559bc00ae02SRob Clark { 560bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 561bc00ae02SRob Clark } 562bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 563bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 564bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 565bc00ae02SRob Clark { 566bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 567bc00ae02SRob Clark } 568bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 569bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 570bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 571bc00ae02SRob Clark { 572bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 573bc00ae02SRob Clark } 574bc00ae02SRob Clark 575bc00ae02SRob Clark #define REG_A4XX_RB_STENCIL_CONTROL2 0x00002107 576bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER 0x00000001 577bc00ae02SRob Clark 578bc00ae02SRob Clark #define REG_A4XX_RB_STENCILREFMASK 0x0000210b 579bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 580bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 581bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 582bc00ae02SRob Clark { 583bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILREF__MASK; 584bc00ae02SRob Clark } 585bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 586bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 587bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 588bc00ae02SRob Clark { 589bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILMASK__MASK; 590bc00ae02SRob Clark } 591bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 592bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 593bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 594bc00ae02SRob Clark { 595bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 596bc00ae02SRob Clark } 597bc00ae02SRob Clark 598bc00ae02SRob Clark #define REG_A4XX_RB_STENCILREFMASK_BF 0x0000210c 599bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 600bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 601bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 602bc00ae02SRob Clark { 603bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 604bc00ae02SRob Clark } 605bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 606bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 607bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 608bc00ae02SRob Clark { 609bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 610bc00ae02SRob Clark } 611bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 612bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 613bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 614bc00ae02SRob Clark { 615bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 616bc00ae02SRob Clark } 617bc00ae02SRob Clark 618bc00ae02SRob Clark #define REG_A4XX_RB_BIN_OFFSET 0x0000210d 619bc00ae02SRob Clark #define A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 620bc00ae02SRob Clark #define A4XX_RB_BIN_OFFSET_X__MASK 0x00007fff 621bc00ae02SRob Clark #define A4XX_RB_BIN_OFFSET_X__SHIFT 0 622bc00ae02SRob Clark static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val) 623bc00ae02SRob Clark { 624bc00ae02SRob Clark return ((val) << A4XX_RB_BIN_OFFSET_X__SHIFT) & A4XX_RB_BIN_OFFSET_X__MASK; 625bc00ae02SRob Clark } 626bc00ae02SRob Clark #define A4XX_RB_BIN_OFFSET_Y__MASK 0x7fff0000 627bc00ae02SRob Clark #define A4XX_RB_BIN_OFFSET_Y__SHIFT 16 628bc00ae02SRob Clark static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val) 629bc00ae02SRob Clark { 630bc00ae02SRob Clark return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK; 631bc00ae02SRob Clark } 632bc00ae02SRob Clark 633bc00ae02SRob Clark #define REG_A4XX_RB_VPORT_Z_CLAMP_MAX_15 0x0000213f 634bc00ae02SRob Clark 635bc00ae02SRob Clark #define REG_A4XX_RBBM_HW_VERSION 0x00000000 636bc00ae02SRob Clark 637bc00ae02SRob Clark #define REG_A4XX_RBBM_HW_CONFIGURATION 0x00000002 638bc00ae02SRob Clark 639bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; } 640bc00ae02SRob Clark 641bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; } 642bc00ae02SRob Clark 643bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; } 644bc00ae02SRob Clark 645bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; } 646bc00ae02SRob Clark 647bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; } 648bc00ae02SRob Clark 649bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; } 650bc00ae02SRob Clark 651bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; } 652bc00ae02SRob Clark 653bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; } 654bc00ae02SRob Clark 655bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL_UCHE 0x00000014 656bc00ae02SRob Clark 657bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL2_UCHE 0x00000015 658bc00ae02SRob Clark 659bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL3_UCHE 0x00000016 660bc00ae02SRob Clark 661bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL4_UCHE 0x00000017 662bc00ae02SRob Clark 663bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_HYST_UCHE 0x00000018 664bc00ae02SRob Clark 665bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_DELAY_UCHE 0x00000019 666bc00ae02SRob Clark 667bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_MODE_GPC 0x0000001a 668bc00ae02SRob Clark 669bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_DELAY_GPC 0x0000001b 670bc00ae02SRob Clark 671bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_HYST_GPC 0x0000001c 672bc00ae02SRob Clark 673bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM 0x0000001d 674bc00ae02SRob Clark 675bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000001e 676bc00ae02SRob Clark 677bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x0000001f 678bc00ae02SRob Clark 679bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL 0x00000020 680bc00ae02SRob Clark 681bc00ae02SRob Clark #define REG_A4XX_RBBM_SP_HYST_CNT 0x00000021 682bc00ae02SRob Clark 683bc00ae02SRob Clark #define REG_A4XX_RBBM_SW_RESET_CMD 0x00000022 684bc00ae02SRob Clark 685bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_CTL0 0x00000023 686bc00ae02SRob Clark 687bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_CTL1 0x00000024 688bc00ae02SRob Clark 689bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_CMD 0x00000025 690bc00ae02SRob Clark 691bc00ae02SRob Clark #define REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL 0x00000026 692bc00ae02SRob Clark 693bc00ae02SRob Clark #define REG_A4XX_RBBM_RAM_ACC_63_32 0x00000028 694bc00ae02SRob Clark 695bc00ae02SRob Clark #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x0000002b 696bc00ae02SRob Clark 697bc00ae02SRob Clark #define REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL 0x0000002f 698bc00ae02SRob Clark 699bc00ae02SRob Clark #define REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4 0x00000034 700bc00ae02SRob Clark 701bc00ae02SRob Clark #define REG_A4XX_RBBM_INT_CLEAR_CMD 0x00000036 702bc00ae02SRob Clark 703bc00ae02SRob Clark #define REG_A4XX_RBBM_INT_0_MASK 0x00000037 704bc00ae02SRob Clark 705bc00ae02SRob Clark #define REG_A4XX_RBBM_RBBM_CTL 0x0000003e 706bc00ae02SRob Clark 707bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_DEBUG_CTL 0x0000003f 708bc00ae02SRob Clark 709bc00ae02SRob Clark #define REG_A4XX_RBBM_VBIF_DEBUG_CTL 0x00000041 710bc00ae02SRob Clark 711bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL2 0x00000042 712bc00ae02SRob Clark 713bc00ae02SRob Clark #define REG_A4XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 714bc00ae02SRob Clark 715bc00ae02SRob Clark #define REG_A4XX_RBBM_RESET_CYCLES 0x00000047 716bc00ae02SRob Clark 717bc00ae02SRob Clark #define REG_A4XX_RBBM_EXT_TRACE_BUS_CTL 0x00000049 718bc00ae02SRob Clark 719bc00ae02SRob Clark #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A 0x0000004a 720bc00ae02SRob Clark 721bc00ae02SRob Clark #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B 0x0000004b 722bc00ae02SRob Clark 723bc00ae02SRob Clark #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C 0x0000004c 724bc00ae02SRob Clark 725bc00ae02SRob Clark #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D 0x0000004d 726bc00ae02SRob Clark 727bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_0_LO 0x0000009c 728bc00ae02SRob Clark 729bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; } 730bc00ae02SRob Clark 731bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; } 732bc00ae02SRob Clark 733bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; } 734bc00ae02SRob Clark 735bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; } 736bc00ae02SRob Clark 737bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; } 738bc00ae02SRob Clark 739bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; } 740bc00ae02SRob Clark 741bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; } 742bc00ae02SRob Clark 743bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; } 744bc00ae02SRob Clark 745bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; } 746bc00ae02SRob Clark 747bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; } 748bc00ae02SRob Clark 749bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; } 750bc00ae02SRob Clark 751bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; } 752bc00ae02SRob Clark 753bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; } 754bc00ae02SRob Clark 755bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; } 756bc00ae02SRob Clark 757bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; } 758bc00ae02SRob Clark 759bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; } 760bc00ae02SRob Clark 761bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM 0x00000080 762bc00ae02SRob Clark 763bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM 0x00000081 764bc00ae02SRob Clark 765bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL_HLSQ 0x0000008a 766bc00ae02SRob Clark 767bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_HYST_HLSQ 0x0000008b 768bc00ae02SRob Clark 769bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ 0x0000008c 770bc00ae02SRob Clark 771bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM 0x0000008d 772bc00ae02SRob Clark 773bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; } 774bc00ae02SRob Clark 775bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; } 776bc00ae02SRob Clark 777bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168 778bc00ae02SRob Clark 779bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170 780bc00ae02SRob Clark 781bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0 0x00000171 782bc00ae02SRob Clark 783bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1 0x00000172 784bc00ae02SRob Clark 785bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2 0x00000173 786bc00ae02SRob Clark 787bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000174 788bc00ae02SRob Clark 789bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000175 790bc00ae02SRob Clark 791bc00ae02SRob Clark #define REG_A4XX_RBBM_GPU_BUSY_MASKED 0x0000017a 792bc00ae02SRob Clark 793bc00ae02SRob Clark #define REG_A4XX_RBBM_INT_0_STATUS 0x0000017d 794bc00ae02SRob Clark 795bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_STATUS 0x00000182 796bc00ae02SRob Clark 797bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_STATUS 0x00000189 798bc00ae02SRob Clark 799bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS 0x0000018c 800bc00ae02SRob Clark 801bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS 0x0000018d 802bc00ae02SRob Clark 803bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_ERROR_STATUS 0x0000018f 804bc00ae02SRob Clark 805bc00ae02SRob Clark #define REG_A4XX_RBBM_STATUS 0x00000191 806bc00ae02SRob Clark #define A4XX_RBBM_STATUS_HI_BUSY 0x00000001 807bc00ae02SRob Clark #define A4XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 808bc00ae02SRob Clark #define A4XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 809bc00ae02SRob Clark #define A4XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000 810bc00ae02SRob Clark #define A4XX_RBBM_STATUS_VBIF_BUSY 0x00008000 811bc00ae02SRob Clark #define A4XX_RBBM_STATUS_TSE_BUSY 0x00010000 812bc00ae02SRob Clark #define A4XX_RBBM_STATUS_RAS_BUSY 0x00020000 813bc00ae02SRob Clark #define A4XX_RBBM_STATUS_RB_BUSY 0x00040000 814bc00ae02SRob Clark #define A4XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 815bc00ae02SRob Clark #define A4XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 816bc00ae02SRob Clark #define A4XX_RBBM_STATUS_VFD_BUSY 0x00200000 817bc00ae02SRob Clark #define A4XX_RBBM_STATUS_VPC_BUSY 0x00400000 818bc00ae02SRob Clark #define A4XX_RBBM_STATUS_UCHE_BUSY 0x00800000 819bc00ae02SRob Clark #define A4XX_RBBM_STATUS_SP_BUSY 0x01000000 820bc00ae02SRob Clark #define A4XX_RBBM_STATUS_TPL1_BUSY 0x02000000 821bc00ae02SRob Clark #define A4XX_RBBM_STATUS_MARB_BUSY 0x04000000 822bc00ae02SRob Clark #define A4XX_RBBM_STATUS_VSC_BUSY 0x08000000 823bc00ae02SRob Clark #define A4XX_RBBM_STATUS_ARB_BUSY 0x10000000 824bc00ae02SRob Clark #define A4XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 825bc00ae02SRob Clark #define A4XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000 826bc00ae02SRob Clark #define A4XX_RBBM_STATUS_GPU_BUSY 0x80000000 827bc00ae02SRob Clark 828bc00ae02SRob Clark #define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5 0x0000019f 829bc00ae02SRob Clark 830bc00ae02SRob Clark #define REG_A4XX_CP_SCRATCH_UMASK 0x00000228 831bc00ae02SRob Clark 832bc00ae02SRob Clark #define REG_A4XX_CP_SCRATCH_ADDR 0x00000229 833bc00ae02SRob Clark 834bc00ae02SRob Clark #define REG_A4XX_CP_RB_BASE 0x00000200 835bc00ae02SRob Clark 836bc00ae02SRob Clark #define REG_A4XX_CP_RB_CNTL 0x00000201 837bc00ae02SRob Clark 838bc00ae02SRob Clark #define REG_A4XX_CP_RB_WPTR 0x00000205 839bc00ae02SRob Clark 840bc00ae02SRob Clark #define REG_A4XX_CP_RB_RPTR_ADDR 0x00000203 841bc00ae02SRob Clark 842bc00ae02SRob Clark #define REG_A4XX_CP_RB_RPTR 0x00000204 843bc00ae02SRob Clark 844bc00ae02SRob Clark #define REG_A4XX_CP_IB1_BASE 0x00000206 845bc00ae02SRob Clark 846bc00ae02SRob Clark #define REG_A4XX_CP_IB1_BUFSZ 0x00000207 847bc00ae02SRob Clark 848bc00ae02SRob Clark #define REG_A4XX_CP_IB2_BASE 0x00000208 849bc00ae02SRob Clark 850bc00ae02SRob Clark #define REG_A4XX_CP_IB2_BUFSZ 0x00000209 851bc00ae02SRob Clark 852bc00ae02SRob Clark #define REG_A4XX_CP_ME_RB_DONE_DATA 0x00000217 853bc00ae02SRob Clark 854bc00ae02SRob Clark #define REG_A4XX_CP_QUEUE_THRESH2 0x00000219 855bc00ae02SRob Clark 856bc00ae02SRob Clark #define REG_A4XX_CP_MERCIU_SIZE 0x0000021b 857bc00ae02SRob Clark 858bc00ae02SRob Clark #define REG_A4XX_CP_ROQ_ADDR 0x0000021c 859bc00ae02SRob Clark 860bc00ae02SRob Clark #define REG_A4XX_CP_ROQ_DATA 0x0000021d 861bc00ae02SRob Clark 862bc00ae02SRob Clark #define REG_A4XX_CP_MEQ_ADDR 0x0000021e 863bc00ae02SRob Clark 864bc00ae02SRob Clark #define REG_A4XX_CP_MEQ_DATA 0x0000021f 865bc00ae02SRob Clark 866bc00ae02SRob Clark #define REG_A4XX_CP_MERCIU_ADDR 0x00000220 867bc00ae02SRob Clark 868bc00ae02SRob Clark #define REG_A4XX_CP_MERCIU_DATA 0x00000221 869bc00ae02SRob Clark 870bc00ae02SRob Clark #define REG_A4XX_CP_MERCIU_DATA2 0x00000222 871bc00ae02SRob Clark 872bc00ae02SRob Clark #define REG_A4XX_CP_PFP_UCODE_ADDR 0x00000223 873bc00ae02SRob Clark 874bc00ae02SRob Clark #define REG_A4XX_CP_PFP_UCODE_DATA 0x00000224 875bc00ae02SRob Clark 876bc00ae02SRob Clark #define REG_A4XX_CP_ME_RAM_WADDR 0x00000225 877bc00ae02SRob Clark 878bc00ae02SRob Clark #define REG_A4XX_CP_ME_RAM_RADDR 0x00000226 879bc00ae02SRob Clark 880bc00ae02SRob Clark #define REG_A4XX_CP_ME_RAM_DATA 0x00000227 881bc00ae02SRob Clark 882bc00ae02SRob Clark #define REG_A4XX_CP_PREEMPT 0x0000022a 883bc00ae02SRob Clark 884bc00ae02SRob Clark #define REG_A4XX_CP_CNTL 0x0000022c 885bc00ae02SRob Clark 886bc00ae02SRob Clark #define REG_A4XX_CP_ME_CNTL 0x0000022d 887bc00ae02SRob Clark 888bc00ae02SRob Clark #define REG_A4XX_CP_DEBUG 0x0000022e 889bc00ae02SRob Clark 890bc00ae02SRob Clark #define REG_A4XX_CP_DEBUG_ECO_CONTROL 0x00000231 891bc00ae02SRob Clark 892bc00ae02SRob Clark #define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232 893bc00ae02SRob Clark 894bc00ae02SRob Clark #define REG_A4XX_CP_PROTECT_REG_0 0x00000240 895bc00ae02SRob Clark 896bc00ae02SRob Clark static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; } 897bc00ae02SRob Clark 898bc00ae02SRob Clark static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; } 899bc00ae02SRob Clark 900bc00ae02SRob Clark #define REG_A4XX_CP_PROTECT_CTRL 0x00000250 901bc00ae02SRob Clark 902bc00ae02SRob Clark #define REG_A4XX_CP_ST_BASE 0x000004c0 903bc00ae02SRob Clark 904bc00ae02SRob Clark #define REG_A4XX_CP_STQ_AVAIL 0x000004ce 905bc00ae02SRob Clark 906bc00ae02SRob Clark #define REG_A4XX_CP_MERCIU_STAT 0x000004d0 907bc00ae02SRob Clark 908bc00ae02SRob Clark #define REG_A4XX_CP_WFI_PEND_CTR 0x000004d2 909bc00ae02SRob Clark 910bc00ae02SRob Clark #define REG_A4XX_CP_HW_FAULT 0x000004d8 911bc00ae02SRob Clark 912bc00ae02SRob Clark #define REG_A4XX_CP_PROTECT_STATUS 0x000004da 913bc00ae02SRob Clark 914bc00ae02SRob Clark #define REG_A4XX_CP_EVENTS_IN_FLIGHT 0x000004dd 915bc00ae02SRob Clark 916bc00ae02SRob Clark #define REG_A4XX_CP_PERFCTR_CP_SEL_0 0x00000500 917bc00ae02SRob Clark 918bc00ae02SRob Clark #define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b 919bc00ae02SRob Clark 920bc00ae02SRob Clark static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; } 921bc00ae02SRob Clark 922bc00ae02SRob Clark static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; } 923bc00ae02SRob Clark 924bc00ae02SRob Clark #define REG_A4XX_SP_VS_STATUS 0x00000ec0 925bc00ae02SRob Clark 926bc00ae02SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_11 0x00000ecf 927bc00ae02SRob Clark 928bc00ae02SRob Clark #define REG_A4XX_SP_SP_CTRL_REG 0x000022c0 929bc00ae02SRob Clark #define A4XX_SP_SP_CTRL_REG_BINNING_PASS 0x00080000 930bc00ae02SRob Clark 931bc00ae02SRob Clark #define REG_A4XX_SP_INSTR_CACHE_CTRL 0x000022c1 932bc00ae02SRob Clark 933bc00ae02SRob Clark #define REG_A4XX_SP_VS_CTRL_REG0 0x000022c4 934bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 935bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 936bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 937bc00ae02SRob Clark { 938bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK; 939bc00ae02SRob Clark } 940bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_VARYING 0x00000002 941bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004 942bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 943bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 944bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 945bc00ae02SRob Clark { 946bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 947bc00ae02SRob Clark } 948bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 949bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 950bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 951bc00ae02SRob Clark { 952bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 953bc00ae02SRob Clark } 954bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 955bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 956bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 957bc00ae02SRob Clark { 958bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK; 959bc00ae02SRob Clark } 960bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000 961bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20 962bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 963bc00ae02SRob Clark { 964bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; 965bc00ae02SRob Clark } 966bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000 967bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000 968bc00ae02SRob Clark 969bc00ae02SRob Clark #define REG_A4XX_SP_VS_CTRL_REG1 0x000022c5 970bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff 971bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0 972bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) 973bc00ae02SRob Clark { 974bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK; 975bc00ae02SRob Clark } 976bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000 977bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24 978bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) 979bc00ae02SRob Clark { 980bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK; 981bc00ae02SRob Clark } 982bc00ae02SRob Clark 983bc00ae02SRob Clark #define REG_A4XX_SP_VS_PARAM_REG 0x000022c6 984bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff 985bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0 986bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) 987bc00ae02SRob Clark { 988bc00ae02SRob Clark return ((val) << A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_POSREGID__MASK; 989bc00ae02SRob Clark } 990bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00 991bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8 992bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) 993bc00ae02SRob Clark { 994bc00ae02SRob Clark return ((val) << A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK; 995bc00ae02SRob Clark } 996bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000 997bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20 998bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) 999bc00ae02SRob Clark { 1000bc00ae02SRob Clark return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; 1001bc00ae02SRob Clark } 1002bc00ae02SRob Clark 1003bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 1004bc00ae02SRob Clark 1005bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 1006bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff 1007bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 1008bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 1009bc00ae02SRob Clark { 1010bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_A_REGID__MASK; 1011bc00ae02SRob Clark } 1012bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00 1013bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9 1014bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 1015bc00ae02SRob Clark { 1016bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 1017bc00ae02SRob Clark } 1018bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000 1019bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 1020bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 1021bc00ae02SRob Clark { 1022bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_B_REGID__MASK; 1023bc00ae02SRob Clark } 1024bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000 1025bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25 1026bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 1027bc00ae02SRob Clark { 1028bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 1029bc00ae02SRob Clark } 1030bc00ae02SRob Clark 1031bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; } 1032bc00ae02SRob Clark 1033bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; } 1034bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 1035bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 1036bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 1037bc00ae02SRob Clark { 1038bc00ae02SRob Clark return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 1039bc00ae02SRob Clark } 1040bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 1041bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 1042bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 1043bc00ae02SRob Clark { 1044bc00ae02SRob Clark return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 1045bc00ae02SRob Clark } 1046bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 1047bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 1048bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 1049bc00ae02SRob Clark { 1050bc00ae02SRob Clark return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 1051bc00ae02SRob Clark } 1052bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 1053bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 1054bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 1055bc00ae02SRob Clark { 1056bc00ae02SRob Clark return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 1057bc00ae02SRob Clark } 1058bc00ae02SRob Clark 1059bc00ae02SRob Clark #define REG_A4XX_SP_VS_OBJ_OFFSET_REG 0x000022e0 1060bc00ae02SRob Clark #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1061bc00ae02SRob Clark #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1062bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1063bc00ae02SRob Clark { 1064bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1065bc00ae02SRob Clark } 1066bc00ae02SRob Clark #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1067bc00ae02SRob Clark #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1068bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1069bc00ae02SRob Clark { 1070bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1071bc00ae02SRob Clark } 1072bc00ae02SRob Clark 1073bc00ae02SRob Clark #define REG_A4XX_SP_VS_OBJ_START 0x000022e1 1074bc00ae02SRob Clark 1075bc00ae02SRob Clark #define REG_A4XX_SP_VS_PVT_MEM_PARAM 0x000022e2 1076bc00ae02SRob Clark 1077bc00ae02SRob Clark #define REG_A4XX_SP_VS_PVT_MEM_ADDR 0x000022e3 1078bc00ae02SRob Clark 1079bc00ae02SRob Clark #define REG_A4XX_SP_VS_LENGTH_REG 0x000022e5 1080bc00ae02SRob Clark 1081bc00ae02SRob Clark #define REG_A4XX_SP_FS_CTRL_REG0 0x000022e8 1082bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 1083bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 1084bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 1085bc00ae02SRob Clark { 1086bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK; 1087bc00ae02SRob Clark } 1088bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_VARYING 0x00000002 1089bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004 1090bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 1091bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 1092bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 1093bc00ae02SRob Clark { 1094bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 1095bc00ae02SRob Clark } 1096bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 1097bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 1098bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 1099bc00ae02SRob Clark { 1100bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 1101bc00ae02SRob Clark } 1102bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 1103bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 1104bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 1105bc00ae02SRob Clark { 1106bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK; 1107bc00ae02SRob Clark } 1108bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 1109bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 1110bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 1111bc00ae02SRob Clark { 1112bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 1113bc00ae02SRob Clark } 1114bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000 1115bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000 1116bc00ae02SRob Clark 1117bc00ae02SRob Clark #define REG_A4XX_SP_FS_CTRL_REG1 0x000022e9 1118bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff 1119bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0 1120bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) 1121bc00ae02SRob Clark { 1122bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK; 1123bc00ae02SRob Clark } 1124bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG1_VARYING 0x00100000 1125bc00ae02SRob Clark 1126bc00ae02SRob Clark #define REG_A4XX_SP_FS_OBJ_OFFSET_REG 0x000022ea 1127bc00ae02SRob Clark #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1128bc00ae02SRob Clark #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1129bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1130bc00ae02SRob Clark { 1131bc00ae02SRob Clark return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1132bc00ae02SRob Clark } 1133bc00ae02SRob Clark #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1134bc00ae02SRob Clark #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1135bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1136bc00ae02SRob Clark { 1137bc00ae02SRob Clark return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1138bc00ae02SRob Clark } 1139bc00ae02SRob Clark 1140bc00ae02SRob Clark #define REG_A4XX_SP_FS_OBJ_START 0x000022eb 1141bc00ae02SRob Clark 1142bc00ae02SRob Clark #define REG_A4XX_SP_FS_PVT_MEM_PARAM 0x000022ec 1143bc00ae02SRob Clark 1144bc00ae02SRob Clark #define REG_A4XX_SP_FS_PVT_MEM_ADDR 0x000022ed 1145bc00ae02SRob Clark 1146bc00ae02SRob Clark #define REG_A4XX_SP_FS_LENGTH_REG 0x000022ef 1147bc00ae02SRob Clark 1148bc00ae02SRob Clark #define REG_A4XX_SP_FS_OUTPUT_REG 0x000022f0 1149bc00ae02SRob Clark #define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080 1150bc00ae02SRob Clark #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00 1151bc00ae02SRob Clark #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8 1152bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) 1153bc00ae02SRob Clark { 1154bc00ae02SRob Clark return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK; 1155bc00ae02SRob Clark } 1156bc00ae02SRob Clark 1157bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; } 1158bc00ae02SRob Clark 1159bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; } 1160bc00ae02SRob Clark #define A4XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff 1161bc00ae02SRob Clark #define A4XX_SP_FS_MRT_REG_REGID__SHIFT 0 1162bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val) 1163bc00ae02SRob Clark { 1164bc00ae02SRob Clark return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK; 1165bc00ae02SRob Clark } 1166bc00ae02SRob Clark #define A4XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100 1167bc00ae02SRob Clark #define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK 0x0003f000 1168bc00ae02SRob Clark #define A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT 12 1169bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val) 1170bc00ae02SRob Clark { 1171bc00ae02SRob Clark return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK; 1172bc00ae02SRob Clark } 1173bc00ae02SRob Clark 1174bc00ae02SRob Clark #define REG_A4XX_SP_HS_OBJ_OFFSET_REG 0x0000230d 1175bc00ae02SRob Clark #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1176bc00ae02SRob Clark #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1177bc00ae02SRob Clark static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1178bc00ae02SRob Clark { 1179bc00ae02SRob Clark return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1180bc00ae02SRob Clark } 1181bc00ae02SRob Clark #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1182bc00ae02SRob Clark #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1183bc00ae02SRob Clark static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1184bc00ae02SRob Clark { 1185bc00ae02SRob Clark return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1186bc00ae02SRob Clark } 1187bc00ae02SRob Clark 1188bc00ae02SRob Clark #define REG_A4XX_SP_DS_OBJ_OFFSET_REG 0x00002334 1189bc00ae02SRob Clark #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1190bc00ae02SRob Clark #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1191bc00ae02SRob Clark static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1192bc00ae02SRob Clark { 1193bc00ae02SRob Clark return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1194bc00ae02SRob Clark } 1195bc00ae02SRob Clark #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1196bc00ae02SRob Clark #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1197bc00ae02SRob Clark static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1198bc00ae02SRob Clark { 1199bc00ae02SRob Clark return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1200bc00ae02SRob Clark } 1201bc00ae02SRob Clark 1202bc00ae02SRob Clark #define REG_A4XX_SP_GS_OBJ_OFFSET_REG 0x0000235b 1203bc00ae02SRob Clark #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1204bc00ae02SRob Clark #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1205bc00ae02SRob Clark static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1206bc00ae02SRob Clark { 1207bc00ae02SRob Clark return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1208bc00ae02SRob Clark } 1209bc00ae02SRob Clark #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1210bc00ae02SRob Clark #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1211bc00ae02SRob Clark static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1212bc00ae02SRob Clark { 1213bc00ae02SRob Clark return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1214bc00ae02SRob Clark } 1215bc00ae02SRob Clark 1216bc00ae02SRob Clark #define REG_A4XX_SP_GS_LENGTH_REG 0x00002360 1217bc00ae02SRob Clark 1218bc00ae02SRob Clark #define REG_A4XX_VPC_DEBUG_RAM_SEL 0x00000e60 1219bc00ae02SRob Clark 1220bc00ae02SRob Clark #define REG_A4XX_VPC_DEBUG_RAM_READ 0x00000e61 1221bc00ae02SRob Clark 1222bc00ae02SRob Clark #define REG_A4XX_VPC_DEBUG_ECO_CONTROL 0x00000e64 1223bc00ae02SRob Clark 1224bc00ae02SRob Clark #define REG_A4XX_VPC_PERFCTR_VPC_SEL_3 0x00000e68 1225bc00ae02SRob Clark 1226bc00ae02SRob Clark #define REG_A4XX_VPC_ATTR 0x00002140 1227bc00ae02SRob Clark #define A4XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff 1228bc00ae02SRob Clark #define A4XX_VPC_ATTR_TOTALATTR__SHIFT 0 1229bc00ae02SRob Clark static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val) 1230bc00ae02SRob Clark { 1231bc00ae02SRob Clark return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK; 1232bc00ae02SRob Clark } 1233bc00ae02SRob Clark #define A4XX_VPC_ATTR_PSIZE 0x00000200 1234bc00ae02SRob Clark #define A4XX_VPC_ATTR_THRDASSIGN__MASK 0x00003000 1235bc00ae02SRob Clark #define A4XX_VPC_ATTR_THRDASSIGN__SHIFT 12 1236bc00ae02SRob Clark static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val) 1237bc00ae02SRob Clark { 1238bc00ae02SRob Clark return ((val) << A4XX_VPC_ATTR_THRDASSIGN__SHIFT) & A4XX_VPC_ATTR_THRDASSIGN__MASK; 1239bc00ae02SRob Clark } 1240bc00ae02SRob Clark #define A4XX_VPC_ATTR_ENABLE 0x02000000 1241bc00ae02SRob Clark 1242bc00ae02SRob Clark #define REG_A4XX_VPC_PACK 0x00002141 1243bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMBYPASSVAR__MASK 0x000000ff 1244bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT 0 1245bc00ae02SRob Clark static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val) 1246bc00ae02SRob Clark { 1247bc00ae02SRob Clark return ((val) << A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT) & A4XX_VPC_PACK_NUMBYPASSVAR__MASK; 1248bc00ae02SRob Clark } 1249bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00 1250bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8 1251bc00ae02SRob Clark static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) 1252bc00ae02SRob Clark { 1253bc00ae02SRob Clark return ((val) << A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK; 1254bc00ae02SRob Clark } 1255bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000 1256bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16 1257bc00ae02SRob Clark static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) 1258bc00ae02SRob Clark { 1259bc00ae02SRob Clark return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK; 1260bc00ae02SRob Clark } 1261bc00ae02SRob Clark 1262bc00ae02SRob Clark static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; } 1263bc00ae02SRob Clark 1264bc00ae02SRob Clark static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; } 1265bc00ae02SRob Clark 1266bc00ae02SRob Clark static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; } 1267bc00ae02SRob Clark 1268bc00ae02SRob Clark static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; } 1269bc00ae02SRob Clark 1270bc00ae02SRob Clark #define REG_A4XX_VPC_SO_FLUSH_WADDR_3 0x0000216e 1271bc00ae02SRob Clark 1272bc00ae02SRob Clark #define REG_A4XX_VSC_BIN_SIZE 0x00000c00 1273bc00ae02SRob Clark #define A4XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 1274bc00ae02SRob Clark #define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 1275bc00ae02SRob Clark static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 1276bc00ae02SRob Clark { 1277bc00ae02SRob Clark return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK; 1278bc00ae02SRob Clark } 1279bc00ae02SRob Clark #define A4XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 1280bc00ae02SRob Clark #define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5 1281bc00ae02SRob Clark static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 1282bc00ae02SRob Clark { 1283bc00ae02SRob Clark return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK; 1284bc00ae02SRob Clark } 1285bc00ae02SRob Clark 1286bc00ae02SRob Clark #define REG_A4XX_VSC_SIZE_ADDRESS 0x00000c01 1287bc00ae02SRob Clark 1288bc00ae02SRob Clark #define REG_A4XX_VSC_SIZE_ADDRESS2 0x00000c02 1289bc00ae02SRob Clark 1290bc00ae02SRob Clark #define REG_A4XX_VSC_DEBUG_ECO_CONTROL 0x00000c03 1291bc00ae02SRob Clark 1292bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } 1293bc00ae02SRob Clark 1294bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } 1295bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff 1296bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0 1297bc00ae02SRob Clark static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) 1298bc00ae02SRob Clark { 1299bc00ae02SRob Clark return ((val) << A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_X__MASK; 1300bc00ae02SRob Clark } 1301bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00 1302bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10 1303bc00ae02SRob Clark static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) 1304bc00ae02SRob Clark { 1305bc00ae02SRob Clark return ((val) << A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_Y__MASK; 1306bc00ae02SRob Clark } 1307bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000 1308bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20 1309bc00ae02SRob Clark static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) 1310bc00ae02SRob Clark { 1311bc00ae02SRob Clark return ((val) << A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_W__MASK; 1312bc00ae02SRob Clark } 1313bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000 1314bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24 1315bc00ae02SRob Clark static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) 1316bc00ae02SRob Clark { 1317bc00ae02SRob Clark return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK; 1318bc00ae02SRob Clark } 1319bc00ae02SRob Clark 1320bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 1321bc00ae02SRob Clark 1322bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 1323bc00ae02SRob Clark 1324bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; } 1325bc00ae02SRob Clark 1326bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; } 1327bc00ae02SRob Clark 1328bc00ae02SRob Clark #define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1 0x00000c41 1329bc00ae02SRob Clark 1330bc00ae02SRob Clark #define REG_A4XX_VSC_PERFCTR_VSC_SEL_0 0x00000c50 1331bc00ae02SRob Clark 1332bc00ae02SRob Clark #define REG_A4XX_VSC_PERFCTR_VSC_SEL_1 0x00000c51 1333bc00ae02SRob Clark 1334bc00ae02SRob Clark #define REG_A4XX_VFD_DEBUG_CONTROL 0x00000e40 1335bc00ae02SRob Clark 1336bc00ae02SRob Clark #define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 0x00000e4a 1337bc00ae02SRob Clark 1338bc00ae02SRob Clark #define REG_A4XX_VFD_CONTROL_0 0x00002200 1339bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x000000ff 1340bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0 1341bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) 1342bc00ae02SRob Clark { 1343bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK; 1344bc00ae02SRob Clark } 1345bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK 0x0001fe00 1346bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT 9 1347bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val) 1348bc00ae02SRob Clark { 1349bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT) & A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK; 1350bc00ae02SRob Clark } 1351bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x03f00000 1352bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 20 1353bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) 1354bc00ae02SRob Clark { 1355bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK; 1356bc00ae02SRob Clark } 1357bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xfc000000 1358bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 26 1359bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) 1360bc00ae02SRob Clark { 1361bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK; 1362bc00ae02SRob Clark } 1363bc00ae02SRob Clark 1364bc00ae02SRob Clark #define REG_A4XX_VFD_CONTROL_1 0x00002201 1365bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff 1366bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0 1367bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) 1368bc00ae02SRob Clark { 1369bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK; 1370bc00ae02SRob Clark } 1371bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000 1372bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16 1373bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 1374bc00ae02SRob Clark { 1375bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A4XX_VFD_CONTROL_1_REGID4VTX__MASK; 1376bc00ae02SRob Clark } 1377bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000 1378bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_REGID4INST__SHIFT 24 1379bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 1380bc00ae02SRob Clark { 1381bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A4XX_VFD_CONTROL_1_REGID4INST__MASK; 1382bc00ae02SRob Clark } 1383bc00ae02SRob Clark 1384bc00ae02SRob Clark #define REG_A4XX_VFD_CONTROL_2 0x00002202 1385bc00ae02SRob Clark 1386bc00ae02SRob Clark #define REG_A4XX_VFD_CONTROL_3 0x00002203 1387bc00ae02SRob Clark 1388bc00ae02SRob Clark #define REG_A4XX_VFD_CONTROL_4 0x00002204 1389bc00ae02SRob Clark 1390bc00ae02SRob Clark #define REG_A4XX_VFD_INDEX_OFFSET 0x00002208 1391bc00ae02SRob Clark 1392bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; } 1393bc00ae02SRob Clark 1394bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; } 1395bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f 1396bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0 1397bc00ae02SRob Clark static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) 1398bc00ae02SRob Clark { 1399bc00ae02SRob Clark return ((val) << A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK; 1400bc00ae02SRob Clark } 1401bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80 1402bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7 1403bc00ae02SRob Clark static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) 1404bc00ae02SRob Clark { 1405bc00ae02SRob Clark return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK; 1406bc00ae02SRob Clark } 1407bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00080000 1408bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_0_STEPRATE__MASK 0xff000000 1409bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT 24 1410bc00ae02SRob Clark static inline uint32_t A4XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val) 1411bc00ae02SRob Clark { 1412bc00ae02SRob Clark return ((val) << A4XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_STEPRATE__MASK; 1413bc00ae02SRob Clark } 1414bc00ae02SRob Clark 1415bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; } 1416bc00ae02SRob Clark 1417bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; } 1418bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xfffffff0 1419bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 4 1420bc00ae02SRob Clark static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val) 1421bc00ae02SRob Clark { 1422bc00ae02SRob Clark return ((val >> 4) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK; 1423bc00ae02SRob Clark } 1424bc00ae02SRob Clark 1425bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; } 1426bc00ae02SRob Clark 1427bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; } 1428bc00ae02SRob Clark 1429bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; } 1430bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f 1431bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0 1432bc00ae02SRob Clark static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) 1433bc00ae02SRob Clark { 1434bc00ae02SRob Clark return ((val) << A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK; 1435bc00ae02SRob Clark } 1436bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010 1437bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0 1438bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6 1439bc00ae02SRob Clark static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val) 1440bc00ae02SRob Clark { 1441bc00ae02SRob Clark return ((val) << A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A4XX_VFD_DECODE_INSTR_FORMAT__MASK; 1442bc00ae02SRob Clark } 1443bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000 1444bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_REGID__SHIFT 12 1445bc00ae02SRob Clark static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val) 1446bc00ae02SRob Clark { 1447bc00ae02SRob Clark return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK; 1448bc00ae02SRob Clark } 1449bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000 1450bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT 22 1451bc00ae02SRob Clark static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 1452bc00ae02SRob Clark { 1453bc00ae02SRob Clark return ((val) << A4XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A4XX_VFD_DECODE_INSTR_SWAP__MASK; 1454bc00ae02SRob Clark } 1455bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000 1456bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24 1457bc00ae02SRob Clark static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) 1458bc00ae02SRob Clark { 1459bc00ae02SRob Clark return ((val) << A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK; 1460bc00ae02SRob Clark } 1461bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000 1462bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000 1463bc00ae02SRob Clark 1464bc00ae02SRob Clark #define REG_A4XX_TPL1_DEBUG_ECO_CONTROL 0x00000f00 1465bc00ae02SRob Clark 1466bc00ae02SRob Clark #define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 0x00000f0b 1467bc00ae02SRob Clark 1468bc00ae02SRob Clark #define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380 1469bc00ae02SRob Clark 1470bc00ae02SRob Clark #define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR 0x000023a6 1471bc00ae02SRob Clark 1472bc00ae02SRob Clark #define REG_A4XX_GRAS_TSE_STATUS 0x00000c80 1473bc00ae02SRob Clark 1474bc00ae02SRob Clark #define REG_A4XX_GRAS_DEBUG_ECO_CONTROL 0x00000c81 1475bc00ae02SRob Clark 1476bc00ae02SRob Clark #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c88 1477bc00ae02SRob Clark 1478bc00ae02SRob Clark #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c8b 1479bc00ae02SRob Clark 1480bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000 1481bc00ae02SRob Clark 1482bc00ae02SRob Clark #define REG_A4XX_GRAS_CLEAR_CNTL 0x00002003 1483bc00ae02SRob Clark #define A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR 0x00000001 1484bc00ae02SRob Clark 1485bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_GB_CLIP_ADJ 0x00002004 1486bc00ae02SRob Clark #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff 1487bc00ae02SRob Clark #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0 1488bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) 1489bc00ae02SRob Clark { 1490bc00ae02SRob Clark return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; 1491bc00ae02SRob Clark } 1492bc00ae02SRob Clark #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00 1493bc00ae02SRob Clark #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10 1494bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) 1495bc00ae02SRob Clark { 1496bc00ae02SRob Clark return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; 1497bc00ae02SRob Clark } 1498bc00ae02SRob Clark 1499bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_XOFFSET_0 0x00002008 1500bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff 1501bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0 1502bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val) 1503bc00ae02SRob Clark { 1504bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK; 1505bc00ae02SRob Clark } 1506bc00ae02SRob Clark 1507bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_XSCALE_0 0x00002009 1508bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff 1509bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0 1510bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val) 1511bc00ae02SRob Clark { 1512bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_XSCALE_0__MASK; 1513bc00ae02SRob Clark } 1514bc00ae02SRob Clark 1515bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_YOFFSET_0 0x0000200a 1516bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff 1517bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0 1518bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val) 1519bc00ae02SRob Clark { 1520bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK; 1521bc00ae02SRob Clark } 1522bc00ae02SRob Clark 1523bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_YSCALE_0 0x0000200b 1524bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff 1525bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0 1526bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val) 1527bc00ae02SRob Clark { 1528bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_YSCALE_0__MASK; 1529bc00ae02SRob Clark } 1530bc00ae02SRob Clark 1531bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000200c 1532bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff 1533bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0 1534bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val) 1535bc00ae02SRob Clark { 1536bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK; 1537bc00ae02SRob Clark } 1538bc00ae02SRob Clark 1539bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_ZSCALE_0 0x0000200d 1540bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff 1541bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0 1542bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val) 1543bc00ae02SRob Clark { 1544bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK; 1545bc00ae02SRob Clark } 1546bc00ae02SRob Clark 1547bc00ae02SRob Clark #define REG_A4XX_GRAS_SU_POINT_MINMAX 0x00002070 1548bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 1549bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 1550bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val) 1551bc00ae02SRob Clark { 1552bc00ae02SRob Clark return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 1553bc00ae02SRob Clark } 1554bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 1555bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 1556bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val) 1557bc00ae02SRob Clark { 1558bc00ae02SRob Clark return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 1559bc00ae02SRob Clark } 1560bc00ae02SRob Clark 1561bc00ae02SRob Clark #define REG_A4XX_GRAS_SU_POINT_SIZE 0x00002071 1562bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff 1563bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_SIZE__SHIFT 0 1564bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val) 1565bc00ae02SRob Clark { 1566bc00ae02SRob Clark return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK; 1567bc00ae02SRob Clark } 1568bc00ae02SRob Clark 1569bc00ae02SRob Clark #define REG_A4XX_GRAS_ALPHA_CONTROL 0x00002073 1570bc00ae02SRob Clark #define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE 0x00000004 1571bc00ae02SRob Clark 1572bc00ae02SRob Clark #define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE 0x00002074 1573bc00ae02SRob Clark #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff 1574bc00ae02SRob Clark #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 1575bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val) 1576bc00ae02SRob Clark { 1577bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; 1578bc00ae02SRob Clark } 1579bc00ae02SRob Clark 1580bc00ae02SRob Clark #define REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00002075 1581bc00ae02SRob Clark #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 1582bc00ae02SRob Clark #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 1583bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 1584bc00ae02SRob Clark { 1585bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 1586bc00ae02SRob Clark } 1587bc00ae02SRob Clark 1588bc00ae02SRob Clark #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL 0x0000209f 1589bc00ae02SRob Clark 1590bc00ae02SRob Clark #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL 0x0000207c 1591bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 1592bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 1593bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 1594bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 1595bc00ae02SRob Clark { 1596bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; 1597bc00ae02SRob Clark } 1598bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 1599bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 1600bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 1601bc00ae02SRob Clark { 1602bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; 1603bc00ae02SRob Clark } 1604bc00ae02SRob Clark 1605bc00ae02SRob Clark #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR 0x0000207d 1606bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 1607bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 1608bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 1609bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 1610bc00ae02SRob Clark { 1611bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; 1612bc00ae02SRob Clark } 1613bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 1614bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 1615bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 1616bc00ae02SRob Clark { 1617bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; 1618bc00ae02SRob Clark } 1619bc00ae02SRob Clark 1620bc00ae02SRob Clark #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000209c 1621bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 1622bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 1623bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 1624bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 1625bc00ae02SRob Clark { 1626bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 1627bc00ae02SRob Clark } 1628bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 1629bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 1630bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 1631bc00ae02SRob Clark { 1632bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 1633bc00ae02SRob Clark } 1634bc00ae02SRob Clark 1635bc00ae02SRob Clark #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000209d 1636bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 1637bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 1638bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 1639bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 1640bc00ae02SRob Clark { 1641bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 1642bc00ae02SRob Clark } 1643bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 1644bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 1645bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 1646bc00ae02SRob Clark { 1647bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 1648bc00ae02SRob Clark } 1649bc00ae02SRob Clark 1650bc00ae02SRob Clark #define REG_A4XX_GRAS_DEPTH_CONTROL 0x00002077 1651bc00ae02SRob Clark #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK 0x00000003 1652bc00ae02SRob Clark #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT 0 1653bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val) 1654bc00ae02SRob Clark { 1655bc00ae02SRob Clark return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK; 1656bc00ae02SRob Clark } 1657bc00ae02SRob Clark 1658bc00ae02SRob Clark #define REG_A4XX_GRAS_SU_MODE_CONTROL 0x00002078 1659bc00ae02SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001 1660bc00ae02SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002 1661bc00ae02SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004 1662bc00ae02SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8 1663bc00ae02SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3 1664bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) 1665bc00ae02SRob Clark { 1666bc00ae02SRob Clark return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; 1667bc00ae02SRob Clark } 1668bc00ae02SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800 1669bc00ae02SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS 0x00100000 1670bc00ae02SRob Clark 1671bc00ae02SRob Clark #define REG_A4XX_GRAS_SC_CONTROL 0x0000207b 1672bc00ae02SRob Clark #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x0000000c 1673bc00ae02SRob Clark #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 2 1674bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) 1675bc00ae02SRob Clark { 1676bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK; 1677bc00ae02SRob Clark } 1678bc00ae02SRob Clark #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000380 1679bc00ae02SRob Clark #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 7 1680bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val) 1681bc00ae02SRob Clark { 1682bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK; 1683bc00ae02SRob Clark } 1684bc00ae02SRob Clark #define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE 0x00000800 1685bc00ae02SRob Clark #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000 1686bc00ae02SRob Clark #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12 1687bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) 1688bc00ae02SRob Clark { 1689bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK; 1690bc00ae02SRob Clark } 1691bc00ae02SRob Clark 1692bc00ae02SRob Clark #define REG_A4XX_UCHE_CACHE_MODE_CONTROL 0x00000e80 1693bc00ae02SRob Clark 1694bc00ae02SRob Clark #define REG_A4XX_UCHE_TRAP_BASE_LO 0x00000e83 1695bc00ae02SRob Clark 1696bc00ae02SRob Clark #define REG_A4XX_UCHE_TRAP_BASE_HI 0x00000e84 1697bc00ae02SRob Clark 1698bc00ae02SRob Clark #define REG_A4XX_UCHE_CACHE_STATUS 0x00000e88 1699bc00ae02SRob Clark 1700bc00ae02SRob Clark #define REG_A4XX_UCHE_INVALIDATE0 0x00000e8a 1701bc00ae02SRob Clark 1702bc00ae02SRob Clark #define REG_A4XX_UCHE_INVALIDATE1 0x00000e8b 1703bc00ae02SRob Clark 1704bc00ae02SRob Clark #define REG_A4XX_UCHE_CACHE_WAYS_VFD 0x00000e8c 1705bc00ae02SRob Clark 1706bc00ae02SRob Clark #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e95 1707bc00ae02SRob Clark 1708bc00ae02SRob Clark #define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD 0x00000e00 1709bc00ae02SRob Clark 1710bc00ae02SRob Clark #define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL 0x00000e04 1711bc00ae02SRob Clark 1712bc00ae02SRob Clark #define REG_A4XX_HLSQ_PERF_PIPE_MASK 0x00000e0e 1713bc00ae02SRob Clark 1714bc00ae02SRob Clark #define REG_A4XX_HLSQ_CONTROL_0_REG 0x000023c0 1715bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010 1716bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4 1717bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) 1718bc00ae02SRob Clark { 1719bc00ae02SRob Clark return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; 1720bc00ae02SRob Clark } 1721bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040 1722bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200 1723bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400 1724bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000 1725bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000 1726bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27 1727bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) 1728bc00ae02SRob Clark { 1729bc00ae02SRob Clark return ((val) << A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK; 1730bc00ae02SRob Clark } 1731bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000 1732bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000 1733bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000 1734bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000 1735bc00ae02SRob Clark 1736bc00ae02SRob Clark #define REG_A4XX_HLSQ_CONTROL_1_REG 0x000023c1 1737bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040 1738bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6 1739bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) 1740bc00ae02SRob Clark { 1741bc00ae02SRob Clark return ((val) << A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK; 1742bc00ae02SRob Clark } 1743bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100 1744bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200 1745bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORD 0x02000000 1746bc00ae02SRob Clark 1747bc00ae02SRob Clark #define REG_A4XX_HLSQ_CONTROL_2_REG 0x000023c2 1748bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000 1749bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26 1750bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) 1751bc00ae02SRob Clark { 1752bc00ae02SRob Clark return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK; 1753bc00ae02SRob Clark } 1754bc00ae02SRob Clark 1755bc00ae02SRob Clark #define REG_A4XX_HLSQ_CONTROL_3_REG 0x000023c3 1756bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff 1757bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0 1758bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val) 1759bc00ae02SRob Clark { 1760bc00ae02SRob Clark return ((val) << A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_REGID__MASK; 1761bc00ae02SRob Clark } 1762bc00ae02SRob Clark 1763bc00ae02SRob Clark #define REG_A4XX_HLSQ_VS_CONTROL_REG 0x000023c5 1764bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 1765bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0 1766bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) 1767bc00ae02SRob Clark { 1768bc00ae02SRob Clark return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK; 1769bc00ae02SRob Clark } 1770bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 1771bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 1772bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 1773bc00ae02SRob Clark { 1774bc00ae02SRob Clark return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 1775bc00ae02SRob Clark } 1776bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 1777bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 1778bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 1779bc00ae02SRob Clark { 1780bc00ae02SRob Clark return ((val) << A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK; 1781bc00ae02SRob Clark } 1782bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 1783bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24 1784bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) 1785bc00ae02SRob Clark { 1786bc00ae02SRob Clark return ((val) << A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK; 1787bc00ae02SRob Clark } 1788bc00ae02SRob Clark 1789bc00ae02SRob Clark #define REG_A4XX_HLSQ_FS_CONTROL_REG 0x000023c6 1790bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 1791bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0 1792bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) 1793bc00ae02SRob Clark { 1794bc00ae02SRob Clark return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK; 1795bc00ae02SRob Clark } 1796bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 1797bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 1798bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 1799bc00ae02SRob Clark { 1800bc00ae02SRob Clark return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 1801bc00ae02SRob Clark } 1802bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 1803bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 1804bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 1805bc00ae02SRob Clark { 1806bc00ae02SRob Clark return ((val) << A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK; 1807bc00ae02SRob Clark } 1808bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 1809bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24 1810bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) 1811bc00ae02SRob Clark { 1812bc00ae02SRob Clark return ((val) << A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK; 1813bc00ae02SRob Clark } 1814bc00ae02SRob Clark 1815bc00ae02SRob Clark #define REG_A4XX_HLSQ_HS_CONTROL_REG 0x000023c7 1816bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 1817bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT 0 1818bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val) 1819bc00ae02SRob Clark { 1820bc00ae02SRob Clark return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK; 1821bc00ae02SRob Clark } 1822bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 1823bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 1824bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 1825bc00ae02SRob Clark { 1826bc00ae02SRob Clark return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 1827bc00ae02SRob Clark } 1828bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 1829bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 1830bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 1831bc00ae02SRob Clark { 1832bc00ae02SRob Clark return ((val) << A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK; 1833bc00ae02SRob Clark } 1834bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 1835bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT 24 1836bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val) 1837bc00ae02SRob Clark { 1838bc00ae02SRob Clark return ((val) << A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK; 1839bc00ae02SRob Clark } 1840bc00ae02SRob Clark 1841bc00ae02SRob Clark #define REG_A4XX_HLSQ_DS_CONTROL_REG 0x000023c8 1842bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 1843bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT 0 1844bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val) 1845bc00ae02SRob Clark { 1846bc00ae02SRob Clark return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK; 1847bc00ae02SRob Clark } 1848bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 1849bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 1850bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 1851bc00ae02SRob Clark { 1852bc00ae02SRob Clark return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 1853bc00ae02SRob Clark } 1854bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 1855bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 1856bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 1857bc00ae02SRob Clark { 1858bc00ae02SRob Clark return ((val) << A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK; 1859bc00ae02SRob Clark } 1860bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 1861bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT 24 1862bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val) 1863bc00ae02SRob Clark { 1864bc00ae02SRob Clark return ((val) << A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK; 1865bc00ae02SRob Clark } 1866bc00ae02SRob Clark 1867bc00ae02SRob Clark #define REG_A4XX_HLSQ_GS_CONTROL_REG 0x000023c9 1868bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 1869bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT 0 1870bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val) 1871bc00ae02SRob Clark { 1872bc00ae02SRob Clark return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK; 1873bc00ae02SRob Clark } 1874bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 1875bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 1876bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 1877bc00ae02SRob Clark { 1878bc00ae02SRob Clark return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 1879bc00ae02SRob Clark } 1880bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 1881bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 1882bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 1883bc00ae02SRob Clark { 1884bc00ae02SRob Clark return ((val) << A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK; 1885bc00ae02SRob Clark } 1886bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 1887bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT 24 1888bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val) 1889bc00ae02SRob Clark { 1890bc00ae02SRob Clark return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK; 1891bc00ae02SRob Clark } 1892bc00ae02SRob Clark 1893bc00ae02SRob Clark #define REG_A4XX_HLSQ_UPDATE_CONTROL 0x000023db 1894bc00ae02SRob Clark 1895bc00ae02SRob Clark #define REG_A4XX_PC_BINNING_COMMAND 0x00000d00 1896bc00ae02SRob Clark #define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001 1897bc00ae02SRob Clark 1898bc00ae02SRob Clark #define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c 1899bc00ae02SRob Clark 1900bc00ae02SRob Clark #define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10 1901bc00ae02SRob Clark 1902bc00ae02SRob Clark #define REG_A4XX_PC_PERFCTR_PC_SEL_7 0x00000d17 1903bc00ae02SRob Clark 1904bc00ae02SRob Clark #define REG_A4XX_PC_BIN_BASE 0x000021c0 1905bc00ae02SRob Clark 1906bc00ae02SRob Clark #define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4 1907bc00ae02SRob Clark #define A4XX_PC_PRIM_VTX_CNTL_VAROUT 0x00000001 1908bc00ae02SRob Clark #define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000 1909bc00ae02SRob Clark #define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000 1910bc00ae02SRob Clark 1911bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_21C5 0x000021c5 1912bc00ae02SRob Clark 1913bc00ae02SRob Clark #define REG_A4XX_PC_RESTART_INDEX 0x000021c6 1914bc00ae02SRob Clark 1915bc00ae02SRob Clark #define REG_A4XX_PC_GS_PARAM 0x000021e5 1916bc00ae02SRob Clark 1917bc00ae02SRob Clark #define REG_A4XX_PC_HS_PARAM 0x000021e7 1918bc00ae02SRob Clark 1919bc00ae02SRob Clark #define REG_A4XX_VBIF_VERSION 0x00003000 1920bc00ae02SRob Clark 1921bc00ae02SRob Clark #define REG_A4XX_VBIF_CLKON 0x00003001 1922bc00ae02SRob Clark #define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000001 1923bc00ae02SRob Clark 1924bc00ae02SRob Clark #define REG_A4XX_VBIF_ABIT_SORT 0x0000301c 1925bc00ae02SRob Clark 1926bc00ae02SRob Clark #define REG_A4XX_VBIF_ABIT_SORT_CONF 0x0000301d 1927bc00ae02SRob Clark 1928bc00ae02SRob Clark #define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 1929bc00ae02SRob Clark 1930bc00ae02SRob Clark #define REG_A4XX_VBIF_IN_RD_LIM_CONF0 0x0000302c 1931bc00ae02SRob Clark 1932bc00ae02SRob Clark #define REG_A4XX_VBIF_IN_RD_LIM_CONF1 0x0000302d 1933bc00ae02SRob Clark 1934bc00ae02SRob Clark #define REG_A4XX_VBIF_IN_WR_LIM_CONF0 0x00003030 1935bc00ae02SRob Clark 1936bc00ae02SRob Clark #define REG_A4XX_VBIF_IN_WR_LIM_CONF1 0x00003031 1937bc00ae02SRob Clark 1938bc00ae02SRob Clark #define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049 1939bc00ae02SRob Clark 1940bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_0CC5 0x00000cc5 1941bc00ae02SRob Clark 1942bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_0CC6 0x00000cc6 1943bc00ae02SRob Clark 1944bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_0D01 0x00000d01 1945bc00ae02SRob Clark 1946bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_0E05 0x00000e05 1947bc00ae02SRob Clark 1948bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_0E42 0x00000e42 1949bc00ae02SRob Clark 1950bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_0EC2 0x00000ec2 1951bc00ae02SRob Clark 1952bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_0EC3 0x00000ec3 1953bc00ae02SRob Clark 1954bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_0F03 0x00000f03 1955bc00ae02SRob Clark 1956bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2001 0x00002001 1957bc00ae02SRob Clark 1958bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_209B 0x0000209b 1959bc00ae02SRob Clark 1960bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_20EF 0x000020ef 1961bc00ae02SRob Clark 1962bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_20F0 0x000020f0 1963bc00ae02SRob Clark 1964bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_20F1 0x000020f1 1965bc00ae02SRob Clark 1966bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_20F2 0x000020f2 1967bc00ae02SRob Clark 1968bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_20F3 0x000020f3 1969bc00ae02SRob Clark 1970bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_20F4 0x000020f4 1971bc00ae02SRob Clark 1972bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_20F5 0x000020f5 1973bc00ae02SRob Clark 1974bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_20F6 0x000020f6 1975bc00ae02SRob Clark 1976bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_20F7 0x000020f7 1977bc00ae02SRob Clark 1978bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2152 0x00002152 1979bc00ae02SRob Clark 1980bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2153 0x00002153 1981bc00ae02SRob Clark 1982bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2154 0x00002154 1983bc00ae02SRob Clark 1984bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2155 0x00002155 1985bc00ae02SRob Clark 1986bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2156 0x00002156 1987bc00ae02SRob Clark 1988bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2157 0x00002157 1989bc00ae02SRob Clark 1990bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_21C3 0x000021c3 1991bc00ae02SRob Clark 1992bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_21E6 0x000021e6 1993bc00ae02SRob Clark 1994bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2209 0x00002209 1995bc00ae02SRob Clark 1996bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_22D7 0x000022d7 1997bc00ae02SRob Clark 1998bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2381 0x00002381 1999bc00ae02SRob Clark 2000bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_23A0 0x000023a0 2001bc00ae02SRob Clark 2002bc00ae02SRob Clark #define REG_A4XX_TEX_SAMP_0 0x00000000 2003bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 2004bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_XY_MAG__SHIFT 1 2005bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val) 2006bc00ae02SRob Clark { 2007bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_0_XY_MAG__SHIFT) & A4XX_TEX_SAMP_0_XY_MAG__MASK; 2008bc00ae02SRob Clark } 2009bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 2010bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_XY_MIN__SHIFT 3 2011bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val) 2012bc00ae02SRob Clark { 2013bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_0_XY_MIN__SHIFT) & A4XX_TEX_SAMP_0_XY_MIN__MASK; 2014bc00ae02SRob Clark } 2015bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 2016bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_S__SHIFT 5 2017bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val) 2018bc00ae02SRob Clark { 2019bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_0_WRAP_S__SHIFT) & A4XX_TEX_SAMP_0_WRAP_S__MASK; 2020bc00ae02SRob Clark } 2021bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 2022bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_T__SHIFT 8 2023bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val) 2024bc00ae02SRob Clark { 2025bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_0_WRAP_T__SHIFT) & A4XX_TEX_SAMP_0_WRAP_T__MASK; 2026bc00ae02SRob Clark } 2027bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 2028bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_R__SHIFT 11 2029bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val) 2030bc00ae02SRob Clark { 2031bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK; 2032bc00ae02SRob Clark } 2033bc00ae02SRob Clark 2034bc00ae02SRob Clark #define REG_A4XX_TEX_SAMP_1 0x00000001 2035bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e 2036bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 2037bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) 2038bc00ae02SRob Clark { 2039bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK; 2040bc00ae02SRob Clark } 2041bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 2042bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 2043bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val) 2044bc00ae02SRob Clark { 2045bc00ae02SRob Clark return ((((uint32_t)(val * 64.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK; 2046bc00ae02SRob Clark } 2047bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 2048bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 2049bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val) 2050bc00ae02SRob Clark { 2051bc00ae02SRob Clark return ((((uint32_t)(val * 64.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK; 2052bc00ae02SRob Clark } 2053bc00ae02SRob Clark 2054bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_0 0x00000000 2055bc00ae02SRob Clark #define A4XX_TEX_CONST_0_TILED 0x00000001 2056bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 2057bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_X__SHIFT 4 2058bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val) 2059bc00ae02SRob Clark { 2060bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) & A4XX_TEX_CONST_0_SWIZ_X__MASK; 2061bc00ae02SRob Clark } 2062bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 2063bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 2064bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val) 2065bc00ae02SRob Clark { 2066bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Y__MASK; 2067bc00ae02SRob Clark } 2068bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 2069bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 2070bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val) 2071bc00ae02SRob Clark { 2072bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Z__MASK; 2073bc00ae02SRob Clark } 2074bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 2075bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_W__SHIFT 13 2076bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val) 2077bc00ae02SRob Clark { 2078bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK; 2079bc00ae02SRob Clark } 2080bc00ae02SRob Clark #define A4XX_TEX_CONST_0_FMT__MASK 0x1fc00000 2081bc00ae02SRob Clark #define A4XX_TEX_CONST_0_FMT__SHIFT 22 2082bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val) 2083bc00ae02SRob Clark { 2084bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK; 2085bc00ae02SRob Clark } 2086bc00ae02SRob Clark #define A4XX_TEX_CONST_0_TYPE__MASK 0x60000000 2087bc00ae02SRob Clark #define A4XX_TEX_CONST_0_TYPE__SHIFT 29 2088bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val) 2089bc00ae02SRob Clark { 2090bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_TYPE__SHIFT) & A4XX_TEX_CONST_0_TYPE__MASK; 2091bc00ae02SRob Clark } 2092bc00ae02SRob Clark 2093bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_1 0x00000001 2094bc00ae02SRob Clark #define A4XX_TEX_CONST_1_HEIGHT__MASK 0x00007fff 2095bc00ae02SRob Clark #define A4XX_TEX_CONST_1_HEIGHT__SHIFT 0 2096bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val) 2097bc00ae02SRob Clark { 2098bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK; 2099bc00ae02SRob Clark } 2100bc00ae02SRob Clark #define A4XX_TEX_CONST_1_WIDTH__MASK 0x1fff8000 2101bc00ae02SRob Clark #define A4XX_TEX_CONST_1_WIDTH__SHIFT 15 2102bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val) 2103bc00ae02SRob Clark { 2104bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK; 2105bc00ae02SRob Clark } 2106bc00ae02SRob Clark 2107bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_2 0x00000002 2108bc00ae02SRob Clark #define A4XX_TEX_CONST_2_PITCH__MASK 0x3ffffe00 2109bc00ae02SRob Clark #define A4XX_TEX_CONST_2_PITCH__SHIFT 9 2110bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val) 2111bc00ae02SRob Clark { 2112bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) & A4XX_TEX_CONST_2_PITCH__MASK; 2113bc00ae02SRob Clark } 2114bc00ae02SRob Clark #define A4XX_TEX_CONST_2_SWAP__MASK 0xc0000000 2115bc00ae02SRob Clark #define A4XX_TEX_CONST_2_SWAP__SHIFT 30 2116bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) 2117bc00ae02SRob Clark { 2118bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_2_SWAP__SHIFT) & A4XX_TEX_CONST_2_SWAP__MASK; 2119bc00ae02SRob Clark } 2120bc00ae02SRob Clark 2121bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_3 0x00000003 2122bc00ae02SRob Clark #define A4XX_TEX_CONST_3_LAYERSZ__MASK 0x0000000f 2123bc00ae02SRob Clark #define A4XX_TEX_CONST_3_LAYERSZ__SHIFT 0 2124bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val) 2125bc00ae02SRob Clark { 2126bc00ae02SRob Clark return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK; 2127bc00ae02SRob Clark } 2128bc00ae02SRob Clark 2129bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_4 0x00000004 2130bc00ae02SRob Clark #define A4XX_TEX_CONST_4_BASE__MASK 0xffffffff 2131bc00ae02SRob Clark #define A4XX_TEX_CONST_4_BASE__SHIFT 0 2132bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val) 2133bc00ae02SRob Clark { 2134bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK; 2135bc00ae02SRob Clark } 2136bc00ae02SRob Clark 2137bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_5 0x00000005 2138bc00ae02SRob Clark 2139bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_6 0x00000006 2140bc00ae02SRob Clark 2141bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_7 0x00000007 2142bc00ae02SRob Clark 2143bc00ae02SRob Clark 2144bc00ae02SRob Clark #endif /* A4XX_XML */ 2145