1bc00ae02SRob Clark #ifndef A4XX_XML 2bc00ae02SRob Clark #define A4XX_XML 3bc00ae02SRob Clark 4bc00ae02SRob Clark /* Autogenerated file, DO NOT EDIT manually! 5bc00ae02SRob Clark 6bc00ae02SRob Clark This file was generated by the rules-ng-ng headergen tool in this git repository: 7bc00ae02SRob Clark http://github.com/freedreno/envytools/ 8bc00ae02SRob Clark git clone https://github.com/freedreno/envytools.git 9bc00ae02SRob Clark 10bc00ae02SRob Clark The rules-ng-ng source files this header was generated from are: 11a26ae754SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44) 12a2272e48SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) 13a26ae754SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08) 14a26ae754SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08) 15a26ae754SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08) 16a26ae754SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08) 17a26ae754SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48) 18a26ae754SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05) 198217e97aSRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) 20bc00ae02SRob Clark 21a2272e48SRob Clark Copyright (C) 2013-2016 by the following authors: 22bc00ae02SRob Clark - Rob Clark <robdclark@gmail.com> (robclark) 23a2272e48SRob Clark - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 24bc00ae02SRob Clark 25bc00ae02SRob Clark Permission is hereby granted, free of charge, to any person obtaining 26bc00ae02SRob Clark a copy of this software and associated documentation files (the 27bc00ae02SRob Clark "Software"), to deal in the Software without restriction, including 28bc00ae02SRob Clark without limitation the rights to use, copy, modify, merge, publish, 29bc00ae02SRob Clark distribute, sublicense, and/or sell copies of the Software, and to 30bc00ae02SRob Clark permit persons to whom the Software is furnished to do so, subject to 31bc00ae02SRob Clark the following conditions: 32bc00ae02SRob Clark 33bc00ae02SRob Clark The above copyright notice and this permission notice (including the 34bc00ae02SRob Clark next paragraph) shall be included in all copies or substantial 35bc00ae02SRob Clark portions of the Software. 36bc00ae02SRob Clark 37bc00ae02SRob Clark THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 38bc00ae02SRob Clark EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 39bc00ae02SRob Clark MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 40bc00ae02SRob Clark IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 41bc00ae02SRob Clark LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 42bc00ae02SRob Clark OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 43bc00ae02SRob Clark WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 44bc00ae02SRob Clark */ 45bc00ae02SRob Clark 46bc00ae02SRob Clark 47bc00ae02SRob Clark enum a4xx_color_fmt { 48bc00ae02SRob Clark RB4_A8_UNORM = 1, 49af6cb4c1SRob Clark RB4_R8_UNORM = 2, 50a26ae754SRob Clark RB4_R8_SNORM = 3, 51a26ae754SRob Clark RB4_R8_UINT = 4, 52a26ae754SRob Clark RB4_R8_SINT = 5, 53af6cb4c1SRob Clark RB4_R4G4B4A4_UNORM = 8, 54af6cb4c1SRob Clark RB4_R5G5B5A1_UNORM = 10, 55a2272e48SRob Clark RB4_R5G6B5_UNORM = 14, 56af6cb4c1SRob Clark RB4_R8G8_UNORM = 15, 57af6cb4c1SRob Clark RB4_R8G8_SNORM = 16, 58af6cb4c1SRob Clark RB4_R8G8_UINT = 17, 59af6cb4c1SRob Clark RB4_R8G8_SINT = 18, 60a2272e48SRob Clark RB4_R16_UNORM = 19, 61a2272e48SRob Clark RB4_R16_SNORM = 20, 62af6cb4c1SRob Clark RB4_R16_FLOAT = 21, 63af6cb4c1SRob Clark RB4_R16_UINT = 22, 64af6cb4c1SRob Clark RB4_R16_SINT = 23, 65bc00ae02SRob Clark RB4_R8G8B8_UNORM = 25, 66bc00ae02SRob Clark RB4_R8G8B8A8_UNORM = 26, 67af6cb4c1SRob Clark RB4_R8G8B8A8_SNORM = 28, 68af6cb4c1SRob Clark RB4_R8G8B8A8_UINT = 29, 69af6cb4c1SRob Clark RB4_R8G8B8A8_SINT = 30, 70af6cb4c1SRob Clark RB4_R10G10B10A2_UNORM = 31, 71af6cb4c1SRob Clark RB4_R10G10B10A2_UINT = 34, 72af6cb4c1SRob Clark RB4_R11G11B10_FLOAT = 39, 73a2272e48SRob Clark RB4_R16G16_UNORM = 40, 74a2272e48SRob Clark RB4_R16G16_SNORM = 41, 75af6cb4c1SRob Clark RB4_R16G16_FLOAT = 42, 76af6cb4c1SRob Clark RB4_R16G16_UINT = 43, 77af6cb4c1SRob Clark RB4_R16G16_SINT = 44, 78af6cb4c1SRob Clark RB4_R32_FLOAT = 45, 79af6cb4c1SRob Clark RB4_R32_UINT = 46, 80af6cb4c1SRob Clark RB4_R32_SINT = 47, 81a2272e48SRob Clark RB4_R16G16B16A16_UNORM = 52, 82a2272e48SRob Clark RB4_R16G16B16A16_SNORM = 53, 83af6cb4c1SRob Clark RB4_R16G16B16A16_FLOAT = 54, 84af6cb4c1SRob Clark RB4_R16G16B16A16_UINT = 55, 85af6cb4c1SRob Clark RB4_R16G16B16A16_SINT = 56, 86af6cb4c1SRob Clark RB4_R32G32_FLOAT = 57, 87af6cb4c1SRob Clark RB4_R32G32_UINT = 58, 88af6cb4c1SRob Clark RB4_R32G32_SINT = 59, 89af6cb4c1SRob Clark RB4_R32G32B32A32_FLOAT = 60, 90af6cb4c1SRob Clark RB4_R32G32B32A32_UINT = 61, 91af6cb4c1SRob Clark RB4_R32G32B32A32_SINT = 62, 92bc00ae02SRob Clark }; 93bc00ae02SRob Clark 94bc00ae02SRob Clark enum a4xx_tile_mode { 95bc00ae02SRob Clark TILE4_LINEAR = 0, 96a26ae754SRob Clark TILE4_2 = 2, 97bc00ae02SRob Clark TILE4_3 = 3, 98bc00ae02SRob Clark }; 99bc00ae02SRob Clark 100bc00ae02SRob Clark enum a4xx_vtx_fmt { 1018a264743SRob Clark VFMT4_32_FLOAT = 1, 1028a264743SRob Clark VFMT4_32_32_FLOAT = 2, 1038a264743SRob Clark VFMT4_32_32_32_FLOAT = 3, 1048a264743SRob Clark VFMT4_32_32_32_32_FLOAT = 4, 1058a264743SRob Clark VFMT4_16_FLOAT = 5, 1068a264743SRob Clark VFMT4_16_16_FLOAT = 6, 1078a264743SRob Clark VFMT4_16_16_16_FLOAT = 7, 1088a264743SRob Clark VFMT4_16_16_16_16_FLOAT = 8, 1098a264743SRob Clark VFMT4_32_FIXED = 9, 1108a264743SRob Clark VFMT4_32_32_FIXED = 10, 1118a264743SRob Clark VFMT4_32_32_32_FIXED = 11, 1128a264743SRob Clark VFMT4_32_32_32_32_FIXED = 12, 113a2272e48SRob Clark VFMT4_11_11_10_FLOAT = 13, 1148a264743SRob Clark VFMT4_16_SINT = 16, 1158a264743SRob Clark VFMT4_16_16_SINT = 17, 1168a264743SRob Clark VFMT4_16_16_16_SINT = 18, 1178a264743SRob Clark VFMT4_16_16_16_16_SINT = 19, 1188a264743SRob Clark VFMT4_16_UINT = 20, 1198a264743SRob Clark VFMT4_16_16_UINT = 21, 1208a264743SRob Clark VFMT4_16_16_16_UINT = 22, 1218a264743SRob Clark VFMT4_16_16_16_16_UINT = 23, 1228a264743SRob Clark VFMT4_16_SNORM = 24, 1238a264743SRob Clark VFMT4_16_16_SNORM = 25, 1248a264743SRob Clark VFMT4_16_16_16_SNORM = 26, 1258a264743SRob Clark VFMT4_16_16_16_16_SNORM = 27, 1268a264743SRob Clark VFMT4_16_UNORM = 28, 1278a264743SRob Clark VFMT4_16_16_UNORM = 29, 1288a264743SRob Clark VFMT4_16_16_16_UNORM = 30, 1298a264743SRob Clark VFMT4_16_16_16_16_UNORM = 31, 130af6cb4c1SRob Clark VFMT4_32_UINT = 32, 131af6cb4c1SRob Clark VFMT4_32_32_UINT = 33, 132af6cb4c1SRob Clark VFMT4_32_32_32_UINT = 34, 133af6cb4c1SRob Clark VFMT4_32_32_32_32_UINT = 35, 134af6cb4c1SRob Clark VFMT4_32_SINT = 36, 1358a264743SRob Clark VFMT4_32_32_SINT = 37, 136af6cb4c1SRob Clark VFMT4_32_32_32_SINT = 38, 137af6cb4c1SRob Clark VFMT4_32_32_32_32_SINT = 39, 1388a264743SRob Clark VFMT4_8_UINT = 40, 1398a264743SRob Clark VFMT4_8_8_UINT = 41, 1408a264743SRob Clark VFMT4_8_8_8_UINT = 42, 1418a264743SRob Clark VFMT4_8_8_8_8_UINT = 43, 1428a264743SRob Clark VFMT4_8_UNORM = 44, 1438a264743SRob Clark VFMT4_8_8_UNORM = 45, 1448a264743SRob Clark VFMT4_8_8_8_UNORM = 46, 1458a264743SRob Clark VFMT4_8_8_8_8_UNORM = 47, 1468a264743SRob Clark VFMT4_8_SINT = 48, 1478a264743SRob Clark VFMT4_8_8_SINT = 49, 1488a264743SRob Clark VFMT4_8_8_8_SINT = 50, 1498a264743SRob Clark VFMT4_8_8_8_8_SINT = 51, 1508a264743SRob Clark VFMT4_8_SNORM = 52, 1518a264743SRob Clark VFMT4_8_8_SNORM = 53, 1528a264743SRob Clark VFMT4_8_8_8_SNORM = 54, 1538a264743SRob Clark VFMT4_8_8_8_8_SNORM = 55, 154a2272e48SRob Clark VFMT4_10_10_10_2_UINT = 56, 155a2272e48SRob Clark VFMT4_10_10_10_2_UNORM = 57, 156a2272e48SRob Clark VFMT4_10_10_10_2_SINT = 58, 157a2272e48SRob Clark VFMT4_10_10_10_2_SNORM = 59, 158a2272e48SRob Clark VFMT4_2_10_10_10_UINT = 60, 159a2272e48SRob Clark VFMT4_2_10_10_10_UNORM = 61, 160a2272e48SRob Clark VFMT4_2_10_10_10_SINT = 62, 161a2272e48SRob Clark VFMT4_2_10_10_10_SNORM = 63, 162bc00ae02SRob Clark }; 163bc00ae02SRob Clark 164bc00ae02SRob Clark enum a4xx_tex_fmt { 1658a264743SRob Clark TFMT4_A8_UNORM = 3, 1668a264743SRob Clark TFMT4_8_UNORM = 4, 1678217e97aSRob Clark TFMT4_8_SNORM = 5, 1688217e97aSRob Clark TFMT4_8_UINT = 6, 1698217e97aSRob Clark TFMT4_8_SINT = 7, 170a2272e48SRob Clark TFMT4_4_4_4_4_UNORM = 8, 171a2272e48SRob Clark TFMT4_5_5_5_1_UNORM = 9, 172a2272e48SRob Clark TFMT4_5_6_5_UNORM = 11, 173a2272e48SRob Clark TFMT4_L8_A8_UNORM = 13, 174a2272e48SRob Clark TFMT4_8_8_UNORM = 14, 175a2272e48SRob Clark TFMT4_8_8_SNORM = 15, 176a2272e48SRob Clark TFMT4_8_8_UINT = 16, 177af6cb4c1SRob Clark TFMT4_8_8_SINT = 17, 178a2272e48SRob Clark TFMT4_16_UNORM = 18, 179a2272e48SRob Clark TFMT4_16_SNORM = 19, 1808a264743SRob Clark TFMT4_16_FLOAT = 20, 181a2272e48SRob Clark TFMT4_16_UINT = 21, 182a2272e48SRob Clark TFMT4_16_SINT = 22, 183a2272e48SRob Clark TFMT4_8_8_8_8_UNORM = 28, 184a2272e48SRob Clark TFMT4_8_8_8_8_SNORM = 29, 185a2272e48SRob Clark TFMT4_8_8_8_8_UINT = 30, 186a2272e48SRob Clark TFMT4_8_8_8_8_SINT = 31, 187af6cb4c1SRob Clark TFMT4_9_9_9_E5_FLOAT = 32, 188a2272e48SRob Clark TFMT4_10_10_10_2_UNORM = 33, 189a2272e48SRob Clark TFMT4_10_10_10_2_UINT = 34, 190af6cb4c1SRob Clark TFMT4_11_11_10_FLOAT = 37, 191a2272e48SRob Clark TFMT4_16_16_UNORM = 38, 192a2272e48SRob Clark TFMT4_16_16_SNORM = 39, 193a2272e48SRob Clark TFMT4_16_16_FLOAT = 40, 194a2272e48SRob Clark TFMT4_16_16_UINT = 41, 195a2272e48SRob Clark TFMT4_16_16_SINT = 42, 196a2272e48SRob Clark TFMT4_32_FLOAT = 43, 197a2272e48SRob Clark TFMT4_32_UINT = 44, 198a2272e48SRob Clark TFMT4_32_SINT = 45, 199a2272e48SRob Clark TFMT4_16_16_16_16_UNORM = 51, 200a2272e48SRob Clark TFMT4_16_16_16_16_SNORM = 52, 201a2272e48SRob Clark TFMT4_16_16_16_16_FLOAT = 53, 202a2272e48SRob Clark TFMT4_16_16_16_16_UINT = 54, 203a2272e48SRob Clark TFMT4_16_16_16_16_SINT = 55, 204a2272e48SRob Clark TFMT4_32_32_FLOAT = 56, 205a2272e48SRob Clark TFMT4_32_32_UINT = 57, 206a2272e48SRob Clark TFMT4_32_32_SINT = 58, 207a2272e48SRob Clark TFMT4_32_32_32_FLOAT = 59, 208a2272e48SRob Clark TFMT4_32_32_32_UINT = 60, 209a2272e48SRob Clark TFMT4_32_32_32_SINT = 61, 210a2272e48SRob Clark TFMT4_32_32_32_32_FLOAT = 63, 211a2272e48SRob Clark TFMT4_32_32_32_32_UINT = 64, 212a2272e48SRob Clark TFMT4_32_32_32_32_SINT = 65, 213a2272e48SRob Clark TFMT4_X8Z24_UNORM = 71, 214a2272e48SRob Clark TFMT4_DXT1 = 86, 215a2272e48SRob Clark TFMT4_DXT3 = 87, 216a2272e48SRob Clark TFMT4_DXT5 = 88, 217a2272e48SRob Clark TFMT4_RGTC1_UNORM = 90, 218a2272e48SRob Clark TFMT4_RGTC1_SNORM = 91, 219a2272e48SRob Clark TFMT4_RGTC2_UNORM = 94, 220a2272e48SRob Clark TFMT4_RGTC2_SNORM = 95, 221a2272e48SRob Clark TFMT4_BPTC_UFLOAT = 97, 222a2272e48SRob Clark TFMT4_BPTC_FLOAT = 98, 223a2272e48SRob Clark TFMT4_BPTC = 99, 224af6cb4c1SRob Clark TFMT4_ATC_RGB = 100, 225af6cb4c1SRob Clark TFMT4_ATC_RGBA_EXPLICIT = 101, 226af6cb4c1SRob Clark TFMT4_ATC_RGBA_INTERPOLATED = 102, 227af6cb4c1SRob Clark TFMT4_ETC2_RG11_UNORM = 103, 228af6cb4c1SRob Clark TFMT4_ETC2_RG11_SNORM = 104, 229af6cb4c1SRob Clark TFMT4_ETC2_R11_UNORM = 105, 230af6cb4c1SRob Clark TFMT4_ETC2_R11_SNORM = 106, 231af6cb4c1SRob Clark TFMT4_ETC1 = 107, 232af6cb4c1SRob Clark TFMT4_ETC2_RGB8 = 108, 233af6cb4c1SRob Clark TFMT4_ETC2_RGBA8 = 109, 234af6cb4c1SRob Clark TFMT4_ETC2_RGB8A1 = 110, 235af6cb4c1SRob Clark TFMT4_ASTC_4x4 = 111, 236af6cb4c1SRob Clark TFMT4_ASTC_5x4 = 112, 237af6cb4c1SRob Clark TFMT4_ASTC_5x5 = 113, 238af6cb4c1SRob Clark TFMT4_ASTC_6x5 = 114, 239af6cb4c1SRob Clark TFMT4_ASTC_6x6 = 115, 240af6cb4c1SRob Clark TFMT4_ASTC_8x5 = 116, 241af6cb4c1SRob Clark TFMT4_ASTC_8x6 = 117, 242af6cb4c1SRob Clark TFMT4_ASTC_8x8 = 118, 243af6cb4c1SRob Clark TFMT4_ASTC_10x5 = 119, 244af6cb4c1SRob Clark TFMT4_ASTC_10x6 = 120, 245af6cb4c1SRob Clark TFMT4_ASTC_10x8 = 121, 246af6cb4c1SRob Clark TFMT4_ASTC_10x10 = 122, 247af6cb4c1SRob Clark TFMT4_ASTC_12x10 = 123, 248af6cb4c1SRob Clark TFMT4_ASTC_12x12 = 124, 2498a264743SRob Clark }; 2508a264743SRob Clark 2518a264743SRob Clark enum a4xx_tex_fetchsize { 2528a264743SRob Clark TFETCH4_1_BYTE = 0, 2538a264743SRob Clark TFETCH4_2_BYTE = 1, 2548a264743SRob Clark TFETCH4_4_BYTE = 2, 2558a264743SRob Clark TFETCH4_8_BYTE = 3, 2568a264743SRob Clark TFETCH4_16_BYTE = 4, 257bc00ae02SRob Clark }; 258bc00ae02SRob Clark 259bc00ae02SRob Clark enum a4xx_depth_format { 260bc00ae02SRob Clark DEPTH4_NONE = 0, 261bc00ae02SRob Clark DEPTH4_16 = 1, 262bc00ae02SRob Clark DEPTH4_24_8 = 2, 2632d3584ebSRob Clark DEPTH4_32 = 3, 264bc00ae02SRob Clark }; 265bc00ae02SRob Clark 266af6cb4c1SRob Clark enum a4xx_tess_spacing { 267af6cb4c1SRob Clark EQUAL_SPACING = 0, 268af6cb4c1SRob Clark ODD_SPACING = 2, 269af6cb4c1SRob Clark EVEN_SPACING = 3, 270af6cb4c1SRob Clark }; 271af6cb4c1SRob Clark 272a2272e48SRob Clark enum a4xx_ccu_perfcounter_select { 273a2272e48SRob Clark CCU_BUSY_CYCLES = 0, 274a2272e48SRob Clark CCU_RB_DEPTH_RETURN_STALL = 2, 275a2272e48SRob Clark CCU_RB_COLOR_RETURN_STALL = 3, 276a2272e48SRob Clark CCU_DEPTH_BLOCKS = 6, 277a2272e48SRob Clark CCU_COLOR_BLOCKS = 7, 278a2272e48SRob Clark CCU_DEPTH_BLOCK_HIT = 8, 279a2272e48SRob Clark CCU_COLOR_BLOCK_HIT = 9, 280a2272e48SRob Clark CCU_DEPTH_FLAG1_COUNT = 10, 281a2272e48SRob Clark CCU_DEPTH_FLAG2_COUNT = 11, 282a2272e48SRob Clark CCU_DEPTH_FLAG3_COUNT = 12, 283a2272e48SRob Clark CCU_DEPTH_FLAG4_COUNT = 13, 284a2272e48SRob Clark CCU_COLOR_FLAG1_COUNT = 14, 285a2272e48SRob Clark CCU_COLOR_FLAG2_COUNT = 15, 286a2272e48SRob Clark CCU_COLOR_FLAG3_COUNT = 16, 287a2272e48SRob Clark CCU_COLOR_FLAG4_COUNT = 17, 288a2272e48SRob Clark CCU_PARTIAL_BLOCK_READ = 18, 289a2272e48SRob Clark }; 290a2272e48SRob Clark 291a2272e48SRob Clark enum a4xx_cp_perfcounter_select { 292a2272e48SRob Clark CP_ALWAYS_COUNT = 0, 293a2272e48SRob Clark CP_BUSY = 1, 294a2272e48SRob Clark CP_PFP_IDLE = 2, 295a2272e48SRob Clark CP_PFP_BUSY_WORKING = 3, 296a2272e48SRob Clark CP_PFP_STALL_CYCLES_ANY = 4, 297a2272e48SRob Clark CP_PFP_STARVE_CYCLES_ANY = 5, 298a2272e48SRob Clark CP_PFP_STARVED_PER_LOAD_ADDR = 6, 299a2272e48SRob Clark CP_PFP_STALLED_PER_STORE_ADDR = 7, 300a2272e48SRob Clark CP_PFP_PC_PROFILE = 8, 301a2272e48SRob Clark CP_PFP_MATCH_PM4_PKT_PROFILE = 9, 302a2272e48SRob Clark CP_PFP_COND_INDIRECT_DISCARDED = 10, 303a2272e48SRob Clark CP_LONG_RESUMPTIONS = 11, 304a2272e48SRob Clark CP_RESUME_CYCLES = 12, 305a2272e48SRob Clark CP_RESUME_TO_BOUNDARY_CYCLES = 13, 306a2272e48SRob Clark CP_LONG_PREEMPTIONS = 14, 307a2272e48SRob Clark CP_PREEMPT_CYCLES = 15, 308a2272e48SRob Clark CP_PREEMPT_TO_BOUNDARY_CYCLES = 16, 309a2272e48SRob Clark CP_ME_FIFO_EMPTY_PFP_IDLE = 17, 310a2272e48SRob Clark CP_ME_FIFO_EMPTY_PFP_BUSY = 18, 311a2272e48SRob Clark CP_ME_FIFO_NOT_EMPTY_NOT_FULL = 19, 312a2272e48SRob Clark CP_ME_FIFO_FULL_ME_BUSY = 20, 313a2272e48SRob Clark CP_ME_FIFO_FULL_ME_NON_WORKING = 21, 314a2272e48SRob Clark CP_ME_WAITING_FOR_PACKETS = 22, 315a2272e48SRob Clark CP_ME_BUSY_WORKING = 23, 316a2272e48SRob Clark CP_ME_STARVE_CYCLES_ANY = 24, 317a2272e48SRob Clark CP_ME_STARVE_CYCLES_PER_PROFILE = 25, 318a2272e48SRob Clark CP_ME_STALL_CYCLES_PER_PROFILE = 26, 319a2272e48SRob Clark CP_ME_PC_PROFILE = 27, 320a2272e48SRob Clark CP_RCIU_FIFO_EMPTY = 28, 321a2272e48SRob Clark CP_RCIU_FIFO_NOT_EMPTY_NOT_FULL = 29, 322a2272e48SRob Clark CP_RCIU_FIFO_FULL = 30, 323a2272e48SRob Clark CP_RCIU_FIFO_FULL_NO_CONTEXT = 31, 324a2272e48SRob Clark CP_RCIU_FIFO_FULL_AHB_MASTER = 32, 325a2272e48SRob Clark CP_RCIU_FIFO_FULL_OTHER = 33, 326a2272e48SRob Clark CP_AHB_IDLE = 34, 327a2272e48SRob Clark CP_AHB_STALL_ON_GRANT_NO_SPLIT = 35, 328a2272e48SRob Clark CP_AHB_STALL_ON_GRANT_SPLIT = 36, 329a2272e48SRob Clark CP_AHB_STALL_ON_GRANT_SPLIT_PROFILE = 37, 330a2272e48SRob Clark CP_AHB_BUSY_WORKING = 38, 331a2272e48SRob Clark CP_AHB_BUSY_STALL_ON_HRDY = 39, 332a2272e48SRob Clark CP_AHB_BUSY_STALL_ON_HRDY_PROFILE = 40, 333a2272e48SRob Clark }; 334a2272e48SRob Clark 335a2272e48SRob Clark enum a4xx_gras_ras_perfcounter_select { 336a2272e48SRob Clark RAS_SUPER_TILES = 0, 337a2272e48SRob Clark RAS_8X8_TILES = 1, 338a2272e48SRob Clark RAS_4X4_TILES = 2, 339a2272e48SRob Clark RAS_BUSY_CYCLES = 3, 340a2272e48SRob Clark RAS_STALL_CYCLES_BY_RB = 4, 341a2272e48SRob Clark RAS_STALL_CYCLES_BY_VSC = 5, 342a2272e48SRob Clark RAS_STARVE_CYCLES_BY_TSE = 6, 343a2272e48SRob Clark RAS_SUPERTILE_CYCLES = 7, 344a2272e48SRob Clark RAS_TILE_CYCLES = 8, 345a2272e48SRob Clark RAS_FULLY_COVERED_SUPER_TILES = 9, 346a2272e48SRob Clark RAS_FULLY_COVERED_8X8_TILES = 10, 347a2272e48SRob Clark RAS_4X4_PRIM = 11, 348a2272e48SRob Clark RAS_8X4_4X8_PRIM = 12, 349a2272e48SRob Clark RAS_8X8_PRIM = 13, 350a2272e48SRob Clark }; 351a2272e48SRob Clark 352a2272e48SRob Clark enum a4xx_gras_tse_perfcounter_select { 353a2272e48SRob Clark TSE_INPUT_PRIM = 0, 354a2272e48SRob Clark TSE_INPUT_NULL_PRIM = 1, 355a2272e48SRob Clark TSE_TRIVAL_REJ_PRIM = 2, 356a2272e48SRob Clark TSE_CLIPPED_PRIM = 3, 357a2272e48SRob Clark TSE_NEW_PRIM = 4, 358a2272e48SRob Clark TSE_ZERO_AREA_PRIM = 5, 359a2272e48SRob Clark TSE_FACENESS_CULLED_PRIM = 6, 360a2272e48SRob Clark TSE_ZERO_PIXEL_PRIM = 7, 361a2272e48SRob Clark TSE_OUTPUT_NULL_PRIM = 8, 362a2272e48SRob Clark TSE_OUTPUT_VISIBLE_PRIM = 9, 363a2272e48SRob Clark TSE_PRE_CLIP_PRIM = 10, 364a2272e48SRob Clark TSE_POST_CLIP_PRIM = 11, 365a2272e48SRob Clark TSE_BUSY_CYCLES = 12, 366a2272e48SRob Clark TSE_PC_STARVE = 13, 367a2272e48SRob Clark TSE_RAS_STALL = 14, 368a2272e48SRob Clark TSE_STALL_BARYPLANE_FIFO_FULL = 15, 369a2272e48SRob Clark TSE_STALL_ZPLANE_FIFO_FULL = 16, 370a2272e48SRob Clark }; 371a2272e48SRob Clark 372a2272e48SRob Clark enum a4xx_hlsq_perfcounter_select { 373a2272e48SRob Clark HLSQ_SP_VS_STAGE_CONSTANT = 0, 374a2272e48SRob Clark HLSQ_SP_VS_STAGE_INSTRUCTIONS = 1, 375a2272e48SRob Clark HLSQ_SP_FS_STAGE_CONSTANT = 2, 376a2272e48SRob Clark HLSQ_SP_FS_STAGE_INSTRUCTIONS = 3, 377a2272e48SRob Clark HLSQ_TP_STATE = 4, 378a2272e48SRob Clark HLSQ_QUADS = 5, 379a2272e48SRob Clark HLSQ_PIXELS = 6, 380a2272e48SRob Clark HLSQ_VERTICES = 7, 381a2272e48SRob Clark HLSQ_SP_VS_STAGE_DATA_BYTES = 13, 382a2272e48SRob Clark HLSQ_SP_FS_STAGE_DATA_BYTES = 14, 383a2272e48SRob Clark HLSQ_BUSY_CYCLES = 15, 384a2272e48SRob Clark HLSQ_STALL_CYCLES_SP_STATE = 16, 385a2272e48SRob Clark HLSQ_STALL_CYCLES_SP_VS_STAGE = 17, 386a2272e48SRob Clark HLSQ_STALL_CYCLES_SP_FS_STAGE = 18, 387a2272e48SRob Clark HLSQ_STALL_CYCLES_UCHE = 19, 388a2272e48SRob Clark HLSQ_RBBM_LOAD_CYCLES = 20, 389a2272e48SRob Clark HLSQ_DI_TO_VS_START_SP = 21, 390a2272e48SRob Clark HLSQ_DI_TO_FS_START_SP = 22, 391a2272e48SRob Clark HLSQ_VS_STAGE_START_TO_DONE_SP = 23, 392a2272e48SRob Clark HLSQ_FS_STAGE_START_TO_DONE_SP = 24, 393a2272e48SRob Clark HLSQ_SP_STATE_COPY_CYCLES_VS_STAGE = 25, 394a2272e48SRob Clark HLSQ_SP_STATE_COPY_CYCLES_FS_STAGE = 26, 395a2272e48SRob Clark HLSQ_UCHE_LATENCY_CYCLES = 27, 396a2272e48SRob Clark HLSQ_UCHE_LATENCY_COUNT = 28, 397a2272e48SRob Clark HLSQ_STARVE_CYCLES_VFD = 29, 398a2272e48SRob Clark }; 399a2272e48SRob Clark 400a2272e48SRob Clark enum a4xx_pc_perfcounter_select { 401a2272e48SRob Clark PC_VIS_STREAMS_LOADED = 0, 402a2272e48SRob Clark PC_VPC_PRIMITIVES = 2, 403a2272e48SRob Clark PC_DEAD_PRIM = 3, 404a2272e48SRob Clark PC_LIVE_PRIM = 4, 405a2272e48SRob Clark PC_DEAD_DRAWCALLS = 5, 406a2272e48SRob Clark PC_LIVE_DRAWCALLS = 6, 407a2272e48SRob Clark PC_VERTEX_MISSES = 7, 408a2272e48SRob Clark PC_STALL_CYCLES_VFD = 9, 409a2272e48SRob Clark PC_STALL_CYCLES_TSE = 10, 410a2272e48SRob Clark PC_STALL_CYCLES_UCHE = 11, 411a2272e48SRob Clark PC_WORKING_CYCLES = 12, 412a2272e48SRob Clark PC_IA_VERTICES = 13, 413a2272e48SRob Clark PC_GS_PRIMITIVES = 14, 414a2272e48SRob Clark PC_HS_INVOCATIONS = 15, 415a2272e48SRob Clark PC_DS_INVOCATIONS = 16, 416a2272e48SRob Clark PC_DS_PRIMITIVES = 17, 417a2272e48SRob Clark PC_STARVE_CYCLES_FOR_INDEX = 20, 418a2272e48SRob Clark PC_STARVE_CYCLES_FOR_TESS_FACTOR = 21, 419a2272e48SRob Clark PC_STARVE_CYCLES_FOR_VIZ_STREAM = 22, 420a2272e48SRob Clark PC_STALL_CYCLES_TESS = 23, 421a2272e48SRob Clark PC_STARVE_CYCLES_FOR_POSITION = 24, 422a2272e48SRob Clark PC_MODE0_DRAWCALL = 25, 423a2272e48SRob Clark PC_MODE1_DRAWCALL = 26, 424a2272e48SRob Clark PC_MODE2_DRAWCALL = 27, 425a2272e48SRob Clark PC_MODE3_DRAWCALL = 28, 426a2272e48SRob Clark PC_MODE4_DRAWCALL = 29, 427a2272e48SRob Clark PC_PREDICATED_DEAD_DRAWCALL = 30, 428a2272e48SRob Clark PC_STALL_CYCLES_BY_TSE_ONLY = 31, 429a2272e48SRob Clark PC_STALL_CYCLES_BY_VPC_ONLY = 32, 430a2272e48SRob Clark PC_VPC_POS_DATA_TRANSACTION = 33, 431a2272e48SRob Clark PC_BUSY_CYCLES = 34, 432a2272e48SRob Clark PC_STARVE_CYCLES_DI = 35, 433a2272e48SRob Clark PC_STALL_CYCLES_VPC = 36, 434a2272e48SRob Clark TESS_WORKING_CYCLES = 37, 435a2272e48SRob Clark TESS_NUM_CYCLES_SETUP_WORKING = 38, 436a2272e48SRob Clark TESS_NUM_CYCLES_PTGEN_WORKING = 39, 437a2272e48SRob Clark TESS_NUM_CYCLES_CONNGEN_WORKING = 40, 438a2272e48SRob Clark TESS_BUSY_CYCLES = 41, 439a2272e48SRob Clark TESS_STARVE_CYCLES_PC = 42, 440a2272e48SRob Clark TESS_STALL_CYCLES_PC = 43, 441a2272e48SRob Clark }; 442a2272e48SRob Clark 443a2272e48SRob Clark enum a4xx_pwr_perfcounter_select { 444a2272e48SRob Clark PWR_CORE_CLOCK_CYCLES = 0, 445a2272e48SRob Clark PWR_BUSY_CLOCK_CYCLES = 1, 446a2272e48SRob Clark }; 447a2272e48SRob Clark 448a2272e48SRob Clark enum a4xx_rb_perfcounter_select { 449a2272e48SRob Clark RB_BUSY_CYCLES = 0, 450a2272e48SRob Clark RB_BUSY_CYCLES_BINNING = 1, 451a2272e48SRob Clark RB_BUSY_CYCLES_RENDERING = 2, 452a2272e48SRob Clark RB_BUSY_CYCLES_RESOLVE = 3, 453a2272e48SRob Clark RB_STARVE_CYCLES_BY_SP = 4, 454a2272e48SRob Clark RB_STARVE_CYCLES_BY_RAS = 5, 455a2272e48SRob Clark RB_STARVE_CYCLES_BY_MARB = 6, 456a2272e48SRob Clark RB_STALL_CYCLES_BY_MARB = 7, 457a2272e48SRob Clark RB_STALL_CYCLES_BY_HLSQ = 8, 458a2272e48SRob Clark RB_RB_RB_MARB_DATA = 9, 459a2272e48SRob Clark RB_SP_RB_QUAD = 10, 460a2272e48SRob Clark RB_RAS_RB_Z_QUADS = 11, 461a2272e48SRob Clark RB_GMEM_CH0_READ = 12, 462a2272e48SRob Clark RB_GMEM_CH1_READ = 13, 463a2272e48SRob Clark RB_GMEM_CH0_WRITE = 14, 464a2272e48SRob Clark RB_GMEM_CH1_WRITE = 15, 465a2272e48SRob Clark RB_CP_CONTEXT_DONE = 16, 466a2272e48SRob Clark RB_CP_CACHE_FLUSH = 17, 467a2272e48SRob Clark RB_CP_ZPASS_DONE = 18, 468a2272e48SRob Clark RB_STALL_FIFO0_FULL = 19, 469a2272e48SRob Clark RB_STALL_FIFO1_FULL = 20, 470a2272e48SRob Clark RB_STALL_FIFO2_FULL = 21, 471a2272e48SRob Clark RB_STALL_FIFO3_FULL = 22, 472a2272e48SRob Clark RB_RB_HLSQ_TRANSACTIONS = 23, 473a2272e48SRob Clark RB_Z_READ = 24, 474a2272e48SRob Clark RB_Z_WRITE = 25, 475a2272e48SRob Clark RB_C_READ = 26, 476a2272e48SRob Clark RB_C_WRITE = 27, 477a2272e48SRob Clark RB_C_READ_LATENCY = 28, 478a2272e48SRob Clark RB_Z_READ_LATENCY = 29, 479a2272e48SRob Clark RB_STALL_BY_UCHE = 30, 480a2272e48SRob Clark RB_MARB_UCHE_TRANSACTIONS = 31, 481a2272e48SRob Clark RB_CACHE_STALL_MISS = 32, 482a2272e48SRob Clark RB_CACHE_STALL_FIFO_FULL = 33, 483a2272e48SRob Clark RB_8BIT_BLENDER_UNITS_ACTIVE = 34, 484a2272e48SRob Clark RB_16BIT_BLENDER_UNITS_ACTIVE = 35, 485a2272e48SRob Clark RB_SAMPLER_UNITS_ACTIVE = 36, 486a2272e48SRob Clark RB_TOTAL_PASS = 38, 487a2272e48SRob Clark RB_Z_PASS = 39, 488a2272e48SRob Clark RB_Z_FAIL = 40, 489a2272e48SRob Clark RB_S_FAIL = 41, 490a2272e48SRob Clark RB_POWER0 = 42, 491a2272e48SRob Clark RB_POWER1 = 43, 492a2272e48SRob Clark RB_POWER2 = 44, 493a2272e48SRob Clark RB_POWER3 = 45, 494a2272e48SRob Clark RB_POWER4 = 46, 495a2272e48SRob Clark RB_POWER5 = 47, 496a2272e48SRob Clark RB_POWER6 = 48, 497a2272e48SRob Clark RB_POWER7 = 49, 498a2272e48SRob Clark }; 499a2272e48SRob Clark 500a2272e48SRob Clark enum a4xx_rbbm_perfcounter_select { 501a2272e48SRob Clark RBBM_ALWAYS_ON = 0, 502a2272e48SRob Clark RBBM_VBIF_BUSY = 1, 503a2272e48SRob Clark RBBM_TSE_BUSY = 2, 504a2272e48SRob Clark RBBM_RAS_BUSY = 3, 505a2272e48SRob Clark RBBM_PC_DCALL_BUSY = 4, 506a2272e48SRob Clark RBBM_PC_VSD_BUSY = 5, 507a2272e48SRob Clark RBBM_VFD_BUSY = 6, 508a2272e48SRob Clark RBBM_VPC_BUSY = 7, 509a2272e48SRob Clark RBBM_UCHE_BUSY = 8, 510a2272e48SRob Clark RBBM_VSC_BUSY = 9, 511a2272e48SRob Clark RBBM_HLSQ_BUSY = 10, 512a2272e48SRob Clark RBBM_ANY_RB_BUSY = 11, 513a2272e48SRob Clark RBBM_ANY_TPL1_BUSY = 12, 514a2272e48SRob Clark RBBM_ANY_SP_BUSY = 13, 515a2272e48SRob Clark RBBM_ANY_MARB_BUSY = 14, 516a2272e48SRob Clark RBBM_ANY_ARB_BUSY = 15, 517a2272e48SRob Clark RBBM_AHB_STATUS_BUSY = 16, 518a2272e48SRob Clark RBBM_AHB_STATUS_STALLED = 17, 519a2272e48SRob Clark RBBM_AHB_STATUS_TXFR = 18, 520a2272e48SRob Clark RBBM_AHB_STATUS_TXFR_SPLIT = 19, 521a2272e48SRob Clark RBBM_AHB_STATUS_TXFR_ERROR = 20, 522a2272e48SRob Clark RBBM_AHB_STATUS_LONG_STALL = 21, 523a2272e48SRob Clark RBBM_STATUS_MASKED = 22, 524a2272e48SRob Clark RBBM_CP_BUSY_GFX_CORE_IDLE = 23, 525a2272e48SRob Clark RBBM_TESS_BUSY = 24, 526a2272e48SRob Clark RBBM_COM_BUSY = 25, 527a2272e48SRob Clark RBBM_DCOM_BUSY = 32, 528a2272e48SRob Clark RBBM_ANY_CCU_BUSY = 33, 529a2272e48SRob Clark RBBM_DPM_BUSY = 34, 530a2272e48SRob Clark }; 531a2272e48SRob Clark 532a2272e48SRob Clark enum a4xx_sp_perfcounter_select { 533a2272e48SRob Clark SP_LM_LOAD_INSTRUCTIONS = 0, 534a2272e48SRob Clark SP_LM_STORE_INSTRUCTIONS = 1, 535a2272e48SRob Clark SP_LM_ATOMICS = 2, 536a2272e48SRob Clark SP_GM_LOAD_INSTRUCTIONS = 3, 537a2272e48SRob Clark SP_GM_STORE_INSTRUCTIONS = 4, 538a2272e48SRob Clark SP_GM_ATOMICS = 5, 539a2272e48SRob Clark SP_VS_STAGE_TEX_INSTRUCTIONS = 6, 540a2272e48SRob Clark SP_VS_STAGE_CFLOW_INSTRUCTIONS = 7, 541a2272e48SRob Clark SP_VS_STAGE_EFU_INSTRUCTIONS = 8, 542a2272e48SRob Clark SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 9, 543a2272e48SRob Clark SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 10, 544a2272e48SRob Clark SP_FS_STAGE_TEX_INSTRUCTIONS = 11, 545a2272e48SRob Clark SP_FS_STAGE_CFLOW_INSTRUCTIONS = 12, 546a2272e48SRob Clark SP_FS_STAGE_EFU_INSTRUCTIONS = 13, 547a2272e48SRob Clark SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 14, 548a2272e48SRob Clark SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 15, 549a2272e48SRob Clark SP_VS_INSTRUCTIONS = 17, 550a2272e48SRob Clark SP_FS_INSTRUCTIONS = 18, 551a2272e48SRob Clark SP_ADDR_LOCK_COUNT = 19, 552a2272e48SRob Clark SP_UCHE_READ_TRANS = 20, 553a2272e48SRob Clark SP_UCHE_WRITE_TRANS = 21, 554a2272e48SRob Clark SP_EXPORT_VPC_TRANS = 22, 555a2272e48SRob Clark SP_EXPORT_RB_TRANS = 23, 556a2272e48SRob Clark SP_PIXELS_KILLED = 24, 557a2272e48SRob Clark SP_ICL1_REQUESTS = 25, 558a2272e48SRob Clark SP_ICL1_MISSES = 26, 559a2272e48SRob Clark SP_ICL0_REQUESTS = 27, 560a2272e48SRob Clark SP_ICL0_MISSES = 28, 561a2272e48SRob Clark SP_ALU_WORKING_CYCLES = 29, 562a2272e48SRob Clark SP_EFU_WORKING_CYCLES = 30, 563a2272e48SRob Clark SP_STALL_CYCLES_BY_VPC = 31, 564a2272e48SRob Clark SP_STALL_CYCLES_BY_TP = 32, 565a2272e48SRob Clark SP_STALL_CYCLES_BY_UCHE = 33, 566a2272e48SRob Clark SP_STALL_CYCLES_BY_RB = 34, 567a2272e48SRob Clark SP_BUSY_CYCLES = 35, 568a2272e48SRob Clark SP_HS_INSTRUCTIONS = 36, 569a2272e48SRob Clark SP_DS_INSTRUCTIONS = 37, 570a2272e48SRob Clark SP_GS_INSTRUCTIONS = 38, 571a2272e48SRob Clark SP_CS_INSTRUCTIONS = 39, 572a2272e48SRob Clark SP_SCHEDULER_NON_WORKING = 40, 573a2272e48SRob Clark SP_WAVE_CONTEXTS = 41, 574a2272e48SRob Clark SP_WAVE_CONTEXT_CYCLES = 42, 575a2272e48SRob Clark SP_POWER0 = 43, 576a2272e48SRob Clark SP_POWER1 = 44, 577a2272e48SRob Clark SP_POWER2 = 45, 578a2272e48SRob Clark SP_POWER3 = 46, 579a2272e48SRob Clark SP_POWER4 = 47, 580a2272e48SRob Clark SP_POWER5 = 48, 581a2272e48SRob Clark SP_POWER6 = 49, 582a2272e48SRob Clark SP_POWER7 = 50, 583a2272e48SRob Clark SP_POWER8 = 51, 584a2272e48SRob Clark SP_POWER9 = 52, 585a2272e48SRob Clark SP_POWER10 = 53, 586a2272e48SRob Clark SP_POWER11 = 54, 587a2272e48SRob Clark SP_POWER12 = 55, 588a2272e48SRob Clark SP_POWER13 = 56, 589a2272e48SRob Clark SP_POWER14 = 57, 590a2272e48SRob Clark SP_POWER15 = 58, 591a2272e48SRob Clark }; 592a2272e48SRob Clark 593a2272e48SRob Clark enum a4xx_tp_perfcounter_select { 594a2272e48SRob Clark TP_L1_REQUESTS = 0, 595a2272e48SRob Clark TP_L1_MISSES = 1, 596a2272e48SRob Clark TP_QUADS_OFFSET = 8, 597a2272e48SRob Clark TP_QUAD_SHADOW = 9, 598a2272e48SRob Clark TP_QUADS_ARRAY = 10, 599a2272e48SRob Clark TP_QUADS_GRADIENT = 11, 600a2272e48SRob Clark TP_QUADS_1D2D = 12, 601a2272e48SRob Clark TP_QUADS_3DCUBE = 13, 602a2272e48SRob Clark TP_BUSY_CYCLES = 16, 603a2272e48SRob Clark TP_STALL_CYCLES_BY_ARB = 17, 604a2272e48SRob Clark TP_STATE_CACHE_REQUESTS = 20, 605a2272e48SRob Clark TP_STATE_CACHE_MISSES = 21, 606a2272e48SRob Clark TP_POWER0 = 22, 607a2272e48SRob Clark TP_POWER1 = 23, 608a2272e48SRob Clark TP_POWER2 = 24, 609a2272e48SRob Clark TP_POWER3 = 25, 610a2272e48SRob Clark TP_POWER4 = 26, 611a2272e48SRob Clark TP_POWER5 = 27, 612a2272e48SRob Clark TP_POWER6 = 28, 613a2272e48SRob Clark TP_POWER7 = 29, 614a2272e48SRob Clark }; 615a2272e48SRob Clark 616a2272e48SRob Clark enum a4xx_uche_perfcounter_select { 617a2272e48SRob Clark UCHE_VBIF_READ_BEATS_TP = 0, 618a2272e48SRob Clark UCHE_VBIF_READ_BEATS_VFD = 1, 619a2272e48SRob Clark UCHE_VBIF_READ_BEATS_HLSQ = 2, 620a2272e48SRob Clark UCHE_VBIF_READ_BEATS_MARB = 3, 621a2272e48SRob Clark UCHE_VBIF_READ_BEATS_SP = 4, 622a2272e48SRob Clark UCHE_READ_REQUESTS_TP = 5, 623a2272e48SRob Clark UCHE_READ_REQUESTS_VFD = 6, 624a2272e48SRob Clark UCHE_READ_REQUESTS_HLSQ = 7, 625a2272e48SRob Clark UCHE_READ_REQUESTS_MARB = 8, 626a2272e48SRob Clark UCHE_READ_REQUESTS_SP = 9, 627a2272e48SRob Clark UCHE_WRITE_REQUESTS_MARB = 10, 628a2272e48SRob Clark UCHE_WRITE_REQUESTS_SP = 11, 629a2272e48SRob Clark UCHE_TAG_CHECK_FAILS = 12, 630a2272e48SRob Clark UCHE_EVICTS = 13, 631a2272e48SRob Clark UCHE_FLUSHES = 14, 632a2272e48SRob Clark UCHE_VBIF_LATENCY_CYCLES = 15, 633a2272e48SRob Clark UCHE_VBIF_LATENCY_SAMPLES = 16, 634a2272e48SRob Clark UCHE_BUSY_CYCLES = 17, 635a2272e48SRob Clark UCHE_VBIF_READ_BEATS_PC = 18, 636a2272e48SRob Clark UCHE_READ_REQUESTS_PC = 19, 637a2272e48SRob Clark UCHE_WRITE_REQUESTS_VPC = 20, 638a2272e48SRob Clark UCHE_STALL_BY_VBIF = 21, 639a2272e48SRob Clark UCHE_WRITE_REQUESTS_VSC = 22, 640a2272e48SRob Clark UCHE_POWER0 = 23, 641a2272e48SRob Clark UCHE_POWER1 = 24, 642a2272e48SRob Clark UCHE_POWER2 = 25, 643a2272e48SRob Clark UCHE_POWER3 = 26, 644a2272e48SRob Clark UCHE_POWER4 = 27, 645a2272e48SRob Clark UCHE_POWER5 = 28, 646a2272e48SRob Clark UCHE_POWER6 = 29, 647a2272e48SRob Clark UCHE_POWER7 = 30, 648a2272e48SRob Clark }; 649a2272e48SRob Clark 650a2272e48SRob Clark enum a4xx_vbif_perfcounter_select { 651a2272e48SRob Clark AXI_READ_REQUESTS_ID_0 = 0, 652a2272e48SRob Clark AXI_READ_REQUESTS_ID_1 = 1, 653a2272e48SRob Clark AXI_READ_REQUESTS_ID_2 = 2, 654a2272e48SRob Clark AXI_READ_REQUESTS_ID_3 = 3, 655a2272e48SRob Clark AXI_READ_REQUESTS_ID_4 = 4, 656a2272e48SRob Clark AXI_READ_REQUESTS_ID_5 = 5, 657a2272e48SRob Clark AXI_READ_REQUESTS_ID_6 = 6, 658a2272e48SRob Clark AXI_READ_REQUESTS_ID_7 = 7, 659a2272e48SRob Clark AXI_READ_REQUESTS_ID_8 = 8, 660a2272e48SRob Clark AXI_READ_REQUESTS_ID_9 = 9, 661a2272e48SRob Clark AXI_READ_REQUESTS_ID_10 = 10, 662a2272e48SRob Clark AXI_READ_REQUESTS_ID_11 = 11, 663a2272e48SRob Clark AXI_READ_REQUESTS_ID_12 = 12, 664a2272e48SRob Clark AXI_READ_REQUESTS_ID_13 = 13, 665a2272e48SRob Clark AXI_READ_REQUESTS_ID_14 = 14, 666a2272e48SRob Clark AXI_READ_REQUESTS_ID_15 = 15, 667a2272e48SRob Clark AXI0_READ_REQUESTS_TOTAL = 16, 668a2272e48SRob Clark AXI1_READ_REQUESTS_TOTAL = 17, 669a2272e48SRob Clark AXI2_READ_REQUESTS_TOTAL = 18, 670a2272e48SRob Clark AXI3_READ_REQUESTS_TOTAL = 19, 671a2272e48SRob Clark AXI_READ_REQUESTS_TOTAL = 20, 672a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_0 = 21, 673a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_1 = 22, 674a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_2 = 23, 675a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_3 = 24, 676a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_4 = 25, 677a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_5 = 26, 678a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_6 = 27, 679a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_7 = 28, 680a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_8 = 29, 681a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_9 = 30, 682a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_10 = 31, 683a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_11 = 32, 684a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_12 = 33, 685a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_13 = 34, 686a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_14 = 35, 687a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_15 = 36, 688a2272e48SRob Clark AXI0_WRITE_REQUESTS_TOTAL = 37, 689a2272e48SRob Clark AXI1_WRITE_REQUESTS_TOTAL = 38, 690a2272e48SRob Clark AXI2_WRITE_REQUESTS_TOTAL = 39, 691a2272e48SRob Clark AXI3_WRITE_REQUESTS_TOTAL = 40, 692a2272e48SRob Clark AXI_WRITE_REQUESTS_TOTAL = 41, 693a2272e48SRob Clark AXI_TOTAL_REQUESTS = 42, 694a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_0 = 43, 695a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_1 = 44, 696a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_2 = 45, 697a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_3 = 46, 698a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_4 = 47, 699a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_5 = 48, 700a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_6 = 49, 701a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_7 = 50, 702a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_8 = 51, 703a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_9 = 52, 704a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_10 = 53, 705a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_11 = 54, 706a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_12 = 55, 707a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_13 = 56, 708a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_14 = 57, 709a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_15 = 58, 710a2272e48SRob Clark AXI0_READ_DATA_BEATS_TOTAL = 59, 711a2272e48SRob Clark AXI1_READ_DATA_BEATS_TOTAL = 60, 712a2272e48SRob Clark AXI2_READ_DATA_BEATS_TOTAL = 61, 713a2272e48SRob Clark AXI3_READ_DATA_BEATS_TOTAL = 62, 714a2272e48SRob Clark AXI_READ_DATA_BEATS_TOTAL = 63, 715a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_0 = 64, 716a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_1 = 65, 717a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_2 = 66, 718a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_3 = 67, 719a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_4 = 68, 720a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_5 = 69, 721a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_6 = 70, 722a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_7 = 71, 723a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_8 = 72, 724a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_9 = 73, 725a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_10 = 74, 726a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_11 = 75, 727a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_12 = 76, 728a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_13 = 77, 729a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_14 = 78, 730a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_15 = 79, 731a2272e48SRob Clark AXI0_WRITE_DATA_BEATS_TOTAL = 80, 732a2272e48SRob Clark AXI1_WRITE_DATA_BEATS_TOTAL = 81, 733a2272e48SRob Clark AXI2_WRITE_DATA_BEATS_TOTAL = 82, 734a2272e48SRob Clark AXI3_WRITE_DATA_BEATS_TOTAL = 83, 735a2272e48SRob Clark AXI_WRITE_DATA_BEATS_TOTAL = 84, 736a2272e48SRob Clark AXI_DATA_BEATS_TOTAL = 85, 737a2272e48SRob Clark CYCLES_HELD_OFF_ID_0 = 86, 738a2272e48SRob Clark CYCLES_HELD_OFF_ID_1 = 87, 739a2272e48SRob Clark CYCLES_HELD_OFF_ID_2 = 88, 740a2272e48SRob Clark CYCLES_HELD_OFF_ID_3 = 89, 741a2272e48SRob Clark CYCLES_HELD_OFF_ID_4 = 90, 742a2272e48SRob Clark CYCLES_HELD_OFF_ID_5 = 91, 743a2272e48SRob Clark CYCLES_HELD_OFF_ID_6 = 92, 744a2272e48SRob Clark CYCLES_HELD_OFF_ID_7 = 93, 745a2272e48SRob Clark CYCLES_HELD_OFF_ID_8 = 94, 746a2272e48SRob Clark CYCLES_HELD_OFF_ID_9 = 95, 747a2272e48SRob Clark CYCLES_HELD_OFF_ID_10 = 96, 748a2272e48SRob Clark CYCLES_HELD_OFF_ID_11 = 97, 749a2272e48SRob Clark CYCLES_HELD_OFF_ID_12 = 98, 750a2272e48SRob Clark CYCLES_HELD_OFF_ID_13 = 99, 751a2272e48SRob Clark CYCLES_HELD_OFF_ID_14 = 100, 752a2272e48SRob Clark CYCLES_HELD_OFF_ID_15 = 101, 753a2272e48SRob Clark AXI_READ_REQUEST_HELD_OFF = 102, 754a2272e48SRob Clark AXI_WRITE_REQUEST_HELD_OFF = 103, 755a2272e48SRob Clark AXI_REQUEST_HELD_OFF = 104, 756a2272e48SRob Clark AXI_WRITE_DATA_HELD_OFF = 105, 757a2272e48SRob Clark OCMEM_AXI_READ_REQUEST_HELD_OFF = 106, 758a2272e48SRob Clark OCMEM_AXI_WRITE_REQUEST_HELD_OFF = 107, 759a2272e48SRob Clark OCMEM_AXI_REQUEST_HELD_OFF = 108, 760a2272e48SRob Clark OCMEM_AXI_WRITE_DATA_HELD_OFF = 109, 761a2272e48SRob Clark ELAPSED_CYCLES_DDR = 110, 762a2272e48SRob Clark ELAPSED_CYCLES_OCMEM = 111, 763a2272e48SRob Clark }; 764a2272e48SRob Clark 765a2272e48SRob Clark enum a4xx_vfd_perfcounter_select { 766a2272e48SRob Clark VFD_UCHE_BYTE_FETCHED = 0, 767a2272e48SRob Clark VFD_UCHE_TRANS = 1, 768a2272e48SRob Clark VFD_FETCH_INSTRUCTIONS = 3, 769a2272e48SRob Clark VFD_BUSY_CYCLES = 5, 770a2272e48SRob Clark VFD_STALL_CYCLES_UCHE = 6, 771a2272e48SRob Clark VFD_STALL_CYCLES_HLSQ = 7, 772a2272e48SRob Clark VFD_STALL_CYCLES_VPC_BYPASS = 8, 773a2272e48SRob Clark VFD_STALL_CYCLES_VPC_ALLOC = 9, 774a2272e48SRob Clark VFD_MODE_0_FIBERS = 13, 775a2272e48SRob Clark VFD_MODE_1_FIBERS = 14, 776a2272e48SRob Clark VFD_MODE_2_FIBERS = 15, 777a2272e48SRob Clark VFD_MODE_3_FIBERS = 16, 778a2272e48SRob Clark VFD_MODE_4_FIBERS = 17, 779a2272e48SRob Clark VFD_BFIFO_STALL = 18, 780a2272e48SRob Clark VFD_NUM_VERTICES_TOTAL = 19, 781a2272e48SRob Clark VFD_PACKER_FULL = 20, 782a2272e48SRob Clark VFD_UCHE_REQUEST_FIFO_FULL = 21, 783a2272e48SRob Clark VFD_STARVE_CYCLES_PC = 22, 784a2272e48SRob Clark VFD_STARVE_CYCLES_UCHE = 23, 785a2272e48SRob Clark }; 786a2272e48SRob Clark 787a2272e48SRob Clark enum a4xx_vpc_perfcounter_select { 788a2272e48SRob Clark VPC_SP_LM_COMPONENTS = 2, 789a2272e48SRob Clark VPC_SP0_LM_BYTES = 3, 790a2272e48SRob Clark VPC_SP1_LM_BYTES = 4, 791a2272e48SRob Clark VPC_SP2_LM_BYTES = 5, 792a2272e48SRob Clark VPC_SP3_LM_BYTES = 6, 793a2272e48SRob Clark VPC_WORKING_CYCLES = 7, 794a2272e48SRob Clark VPC_STALL_CYCLES_LM = 8, 795a2272e48SRob Clark VPC_STARVE_CYCLES_RAS = 9, 796a2272e48SRob Clark VPC_STREAMOUT_CYCLES = 10, 797a2272e48SRob Clark VPC_UCHE_TRANSACTIONS = 12, 798a2272e48SRob Clark VPC_STALL_CYCLES_UCHE = 13, 799a2272e48SRob Clark VPC_BUSY_CYCLES = 14, 800a2272e48SRob Clark VPC_STARVE_CYCLES_SP = 15, 801a2272e48SRob Clark }; 802a2272e48SRob Clark 803a2272e48SRob Clark enum a4xx_vsc_perfcounter_select { 804a2272e48SRob Clark VSC_BUSY_CYCLES = 0, 805a2272e48SRob Clark VSC_WORKING_CYCLES = 1, 806a2272e48SRob Clark VSC_STALL_CYCLES_UCHE = 2, 807a2272e48SRob Clark VSC_STARVE_CYCLES_RAS = 3, 808a2272e48SRob Clark VSC_EOT_NUM = 4, 809a2272e48SRob Clark }; 810a2272e48SRob Clark 811bc00ae02SRob Clark enum a4xx_tex_filter { 812bc00ae02SRob Clark A4XX_TEX_NEAREST = 0, 813bc00ae02SRob Clark A4XX_TEX_LINEAR = 1, 814af6cb4c1SRob Clark A4XX_TEX_ANISO = 2, 815bc00ae02SRob Clark }; 816bc00ae02SRob Clark 817bc00ae02SRob Clark enum a4xx_tex_clamp { 818bc00ae02SRob Clark A4XX_TEX_REPEAT = 0, 819bc00ae02SRob Clark A4XX_TEX_CLAMP_TO_EDGE = 1, 820bc00ae02SRob Clark A4XX_TEX_MIRROR_REPEAT = 2, 8218217e97aSRob Clark A4XX_TEX_CLAMP_TO_BORDER = 3, 8228217e97aSRob Clark A4XX_TEX_MIRROR_CLAMP = 4, 823bc00ae02SRob Clark }; 824bc00ae02SRob Clark 825af6cb4c1SRob Clark enum a4xx_tex_aniso { 826af6cb4c1SRob Clark A4XX_TEX_ANISO_1 = 0, 827af6cb4c1SRob Clark A4XX_TEX_ANISO_2 = 1, 828af6cb4c1SRob Clark A4XX_TEX_ANISO_4 = 2, 829af6cb4c1SRob Clark A4XX_TEX_ANISO_8 = 3, 830af6cb4c1SRob Clark A4XX_TEX_ANISO_16 = 4, 831af6cb4c1SRob Clark }; 832af6cb4c1SRob Clark 833bc00ae02SRob Clark enum a4xx_tex_swiz { 834bc00ae02SRob Clark A4XX_TEX_X = 0, 835bc00ae02SRob Clark A4XX_TEX_Y = 1, 836bc00ae02SRob Clark A4XX_TEX_Z = 2, 837bc00ae02SRob Clark A4XX_TEX_W = 3, 838bc00ae02SRob Clark A4XX_TEX_ZERO = 4, 839bc00ae02SRob Clark A4XX_TEX_ONE = 5, 840bc00ae02SRob Clark }; 841bc00ae02SRob Clark 842bc00ae02SRob Clark enum a4xx_tex_type { 843bc00ae02SRob Clark A4XX_TEX_1D = 0, 844bc00ae02SRob Clark A4XX_TEX_2D = 1, 845bc00ae02SRob Clark A4XX_TEX_CUBE = 2, 846bc00ae02SRob Clark A4XX_TEX_3D = 3, 847bc00ae02SRob Clark }; 848bc00ae02SRob Clark 849bc00ae02SRob Clark #define A4XX_CGC_HLSQ_EARLY_CYC__MASK 0x00700000 850bc00ae02SRob Clark #define A4XX_CGC_HLSQ_EARLY_CYC__SHIFT 20 851bc00ae02SRob Clark static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) 852bc00ae02SRob Clark { 853bc00ae02SRob Clark return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK; 854bc00ae02SRob Clark } 855bc00ae02SRob Clark #define A4XX_INT0_RBBM_GPU_IDLE 0x00000001 856bc00ae02SRob Clark #define A4XX_INT0_RBBM_AHB_ERROR 0x00000002 857bc00ae02SRob Clark #define A4XX_INT0_RBBM_REG_TIMEOUT 0x00000004 858bc00ae02SRob Clark #define A4XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 859bc00ae02SRob Clark #define A4XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 860bc00ae02SRob Clark #define A4XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020 861bc00ae02SRob Clark #define A4XX_INT0_VFD_ERROR 0x00000040 862bc00ae02SRob Clark #define A4XX_INT0_CP_SW_INT 0x00000080 863bc00ae02SRob Clark #define A4XX_INT0_CP_T0_PACKET_IN_IB 0x00000100 864bc00ae02SRob Clark #define A4XX_INT0_CP_OPCODE_ERROR 0x00000200 865bc00ae02SRob Clark #define A4XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400 866bc00ae02SRob Clark #define A4XX_INT0_CP_HW_FAULT 0x00000800 867bc00ae02SRob Clark #define A4XX_INT0_CP_DMA 0x00001000 868bc00ae02SRob Clark #define A4XX_INT0_CP_IB2_INT 0x00002000 869bc00ae02SRob Clark #define A4XX_INT0_CP_IB1_INT 0x00004000 870bc00ae02SRob Clark #define A4XX_INT0_CP_RB_INT 0x00008000 871bc00ae02SRob Clark #define A4XX_INT0_CP_REG_PROTECT_FAULT 0x00010000 872bc00ae02SRob Clark #define A4XX_INT0_CP_RB_DONE_TS 0x00020000 873bc00ae02SRob Clark #define A4XX_INT0_CP_VS_DONE_TS 0x00040000 874bc00ae02SRob Clark #define A4XX_INT0_CP_PS_DONE_TS 0x00080000 875bc00ae02SRob Clark #define A4XX_INT0_CACHE_FLUSH_TS 0x00100000 876bc00ae02SRob Clark #define A4XX_INT0_CP_AHB_ERROR_HALT 0x00200000 877bc00ae02SRob Clark #define A4XX_INT0_MISC_HANG_DETECT 0x01000000 878bc00ae02SRob Clark #define A4XX_INT0_UCHE_OOB_ACCESS 0x02000000 879bc00ae02SRob Clark #define REG_A4XX_RB_GMEM_BASE_ADDR 0x00000cc0 880bc00ae02SRob Clark 881bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_0 0x00000cc7 882bc00ae02SRob Clark 883bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_1 0x00000cc8 884bc00ae02SRob Clark 885bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_2 0x00000cc9 886bc00ae02SRob Clark 887bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_3 0x00000cca 888bc00ae02SRob Clark 889bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_4 0x00000ccb 890bc00ae02SRob Clark 891bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_5 0x00000ccc 892bc00ae02SRob Clark 893bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_6 0x00000ccd 894bc00ae02SRob Clark 895bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_7 0x00000cce 896bc00ae02SRob Clark 897a2272e48SRob Clark #define REG_A4XX_RB_PERFCTR_CCU_SEL_0 0x00000ccf 898a2272e48SRob Clark 899a2272e48SRob Clark #define REG_A4XX_RB_PERFCTR_CCU_SEL_1 0x00000cd0 900a2272e48SRob Clark 901a2272e48SRob Clark #define REG_A4XX_RB_PERFCTR_CCU_SEL_2 0x00000cd1 902a2272e48SRob Clark 903bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_CCU_SEL_3 0x00000cd2 904bc00ae02SRob Clark 905bc00ae02SRob Clark #define REG_A4XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0 906bc00ae02SRob Clark #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff 907bc00ae02SRob Clark #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0 908bc00ae02SRob Clark static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) 909bc00ae02SRob Clark { 910bc00ae02SRob Clark return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK; 911bc00ae02SRob Clark } 912bc00ae02SRob Clark #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x3fff0000 913bc00ae02SRob Clark #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 16 914bc00ae02SRob Clark static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) 915bc00ae02SRob Clark { 916bc00ae02SRob Clark return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK; 917bc00ae02SRob Clark } 918bc00ae02SRob Clark 919bc00ae02SRob Clark #define REG_A4XX_RB_CLEAR_COLOR_DW0 0x000020cc 920bc00ae02SRob Clark 921bc00ae02SRob Clark #define REG_A4XX_RB_CLEAR_COLOR_DW1 0x000020cd 922bc00ae02SRob Clark 923bc00ae02SRob Clark #define REG_A4XX_RB_CLEAR_COLOR_DW2 0x000020ce 924bc00ae02SRob Clark 925bc00ae02SRob Clark #define REG_A4XX_RB_CLEAR_COLOR_DW3 0x000020cf 926bc00ae02SRob Clark 927bc00ae02SRob Clark #define REG_A4XX_RB_MODE_CONTROL 0x000020a0 928bc00ae02SRob Clark #define A4XX_RB_MODE_CONTROL_WIDTH__MASK 0x0000003f 929bc00ae02SRob Clark #define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT 0 930bc00ae02SRob Clark static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) 931bc00ae02SRob Clark { 932bc00ae02SRob Clark return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK; 933bc00ae02SRob Clark } 934bc00ae02SRob Clark #define A4XX_RB_MODE_CONTROL_HEIGHT__MASK 0x00003f00 935bc00ae02SRob Clark #define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT 8 936bc00ae02SRob Clark static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) 937bc00ae02SRob Clark { 938bc00ae02SRob Clark return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK; 939bc00ae02SRob Clark } 940a26ae754SRob Clark #define A4XX_RB_MODE_CONTROL_ENABLE_GMEM 0x00010000 941bc00ae02SRob Clark 942bc00ae02SRob Clark #define REG_A4XX_RB_RENDER_CONTROL 0x000020a1 943bc00ae02SRob Clark #define A4XX_RB_RENDER_CONTROL_BINNING_PASS 0x00000001 944bc00ae02SRob Clark #define A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00000020 945bc00ae02SRob Clark 946bc00ae02SRob Clark #define REG_A4XX_RB_MSAA_CONTROL 0x000020a2 947bc00ae02SRob Clark #define A4XX_RB_MSAA_CONTROL_DISABLE 0x00001000 948bc00ae02SRob Clark #define A4XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000e000 949bc00ae02SRob Clark #define A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 13 950bc00ae02SRob Clark static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val) 951bc00ae02SRob Clark { 952bc00ae02SRob Clark return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK; 953bc00ae02SRob Clark } 954bc00ae02SRob Clark 9558a264743SRob Clark #define REG_A4XX_RB_RENDER_CONTROL2 0x000020a3 9568a264743SRob Clark #define A4XX_RB_RENDER_CONTROL2_XCOORD 0x00000001 9578a264743SRob Clark #define A4XX_RB_RENDER_CONTROL2_YCOORD 0x00000002 9588a264743SRob Clark #define A4XX_RB_RENDER_CONTROL2_ZCOORD 0x00000004 9598a264743SRob Clark #define A4XX_RB_RENDER_CONTROL2_WCOORD 0x00000008 960af6cb4c1SRob Clark #define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK 0x00000010 9618a264743SRob Clark #define A4XX_RB_RENDER_CONTROL2_FACENESS 0x00000020 962af6cb4c1SRob Clark #define A4XX_RB_RENDER_CONTROL2_SAMPLEID 0x00000040 9638a264743SRob Clark #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK 0x00000380 9648a264743SRob Clark #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT 7 9658a264743SRob Clark static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val) 966bc00ae02SRob Clark { 9678a264743SRob Clark return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK; 968bc00ae02SRob Clark } 969af6cb4c1SRob Clark #define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR 0x00000800 9708a264743SRob Clark #define A4XX_RB_RENDER_CONTROL2_VARYING 0x00001000 971bc00ae02SRob Clark 972bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; } 973bc00ae02SRob Clark 974bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; } 975bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008 976bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL_BLEND 0x00000010 977bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL_BLEND2 0x00000020 978a2272e48SRob Clark #define A4XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000040 979a2272e48SRob Clark #define A4XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00 980a2272e48SRob Clark #define A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8 981a2272e48SRob Clark static inline uint32_t A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) 982a2272e48SRob Clark { 983a2272e48SRob Clark return ((val) << A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A4XX_RB_MRT_CONTROL_ROP_CODE__MASK; 984a2272e48SRob Clark } 985bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000 986bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24 987bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 988bc00ae02SRob Clark { 989bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 990bc00ae02SRob Clark } 991bc00ae02SRob Clark 992bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; } 993bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f 994bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 995bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val) 996bc00ae02SRob Clark { 997bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 998bc00ae02SRob Clark } 999af6cb4c1SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0 1000af6cb4c1SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6 1001af6cb4c1SRob Clark static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val) 1002af6cb4c1SRob Clark { 1003af6cb4c1SRob Clark return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 1004af6cb4c1SRob Clark } 1005bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00000600 1006bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 9 1007bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 1008bc00ae02SRob Clark { 1009bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK; 1010bc00ae02SRob Clark } 1011bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00001800 1012bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 11 1013bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 1014bc00ae02SRob Clark { 1015bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 1016bc00ae02SRob Clark } 1017af6cb4c1SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00002000 10182d3584ebSRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xffffc000 1019bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 14 1020bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) 1021bc00ae02SRob Clark { 1022bc00ae02SRob Clark return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; 1023bc00ae02SRob Clark } 1024bc00ae02SRob Clark 1025bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; } 1026bc00ae02SRob Clark 1027bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; } 10282d3584ebSRob Clark #define A4XX_RB_MRT_CONTROL3_STRIDE__MASK 0x03fffff8 1029bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT 3 1030bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val) 1031bc00ae02SRob Clark { 1032bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT) & A4XX_RB_MRT_CONTROL3_STRIDE__MASK; 1033bc00ae02SRob Clark } 1034bc00ae02SRob Clark 1035bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; } 1036bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 1037bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 1038bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 1039bc00ae02SRob Clark { 1040bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 1041bc00ae02SRob Clark } 1042bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 1043bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 1044a26ae754SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 1045bc00ae02SRob Clark { 1046bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 1047bc00ae02SRob Clark } 1048bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 1049bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 1050bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 1051bc00ae02SRob Clark { 1052bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 1053bc00ae02SRob Clark } 1054bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 1055bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 1056bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 1057bc00ae02SRob Clark { 1058bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 1059bc00ae02SRob Clark } 1060bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 1061bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 1062a26ae754SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 1063bc00ae02SRob Clark { 1064bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 1065bc00ae02SRob Clark } 1066bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 1067bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 1068bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 1069bc00ae02SRob Clark { 1070bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 1071bc00ae02SRob Clark } 1072bc00ae02SRob Clark 1073a2272e48SRob Clark #define REG_A4XX_RB_BLEND_RED 0x000020f0 1074a26ae754SRob Clark #define A4XX_RB_BLEND_RED_UINT__MASK 0x000000ff 10758a264743SRob Clark #define A4XX_RB_BLEND_RED_UINT__SHIFT 0 10768a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val) 10778a264743SRob Clark { 10788a264743SRob Clark return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK; 10798a264743SRob Clark } 1080a26ae754SRob Clark #define A4XX_RB_BLEND_RED_SINT__MASK 0x0000ff00 1081a26ae754SRob Clark #define A4XX_RB_BLEND_RED_SINT__SHIFT 8 1082a26ae754SRob Clark static inline uint32_t A4XX_RB_BLEND_RED_SINT(uint32_t val) 1083a26ae754SRob Clark { 1084a26ae754SRob Clark return ((val) << A4XX_RB_BLEND_RED_SINT__SHIFT) & A4XX_RB_BLEND_RED_SINT__MASK; 1085a26ae754SRob Clark } 10868a264743SRob Clark #define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 10878a264743SRob Clark #define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16 10888a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val) 10898a264743SRob Clark { 10908a264743SRob Clark return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK; 10918a264743SRob Clark } 10928a264743SRob Clark 1093a2272e48SRob Clark #define REG_A4XX_RB_BLEND_RED_F32 0x000020f1 1094a2272e48SRob Clark #define A4XX_RB_BLEND_RED_F32__MASK 0xffffffff 1095a2272e48SRob Clark #define A4XX_RB_BLEND_RED_F32__SHIFT 0 1096a2272e48SRob Clark static inline uint32_t A4XX_RB_BLEND_RED_F32(float val) 1097a2272e48SRob Clark { 1098a2272e48SRob Clark return ((fui(val)) << A4XX_RB_BLEND_RED_F32__SHIFT) & A4XX_RB_BLEND_RED_F32__MASK; 1099a2272e48SRob Clark } 1100a2272e48SRob Clark 1101a2272e48SRob Clark #define REG_A4XX_RB_BLEND_GREEN 0x000020f2 1102a26ae754SRob Clark #define A4XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff 11038a264743SRob Clark #define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0 11048a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val) 11058a264743SRob Clark { 11068a264743SRob Clark return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK; 11078a264743SRob Clark } 1108a26ae754SRob Clark #define A4XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00 1109a26ae754SRob Clark #define A4XX_RB_BLEND_GREEN_SINT__SHIFT 8 1110a26ae754SRob Clark static inline uint32_t A4XX_RB_BLEND_GREEN_SINT(uint32_t val) 1111a26ae754SRob Clark { 1112a26ae754SRob Clark return ((val) << A4XX_RB_BLEND_GREEN_SINT__SHIFT) & A4XX_RB_BLEND_GREEN_SINT__MASK; 1113a26ae754SRob Clark } 11148a264743SRob Clark #define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 11158a264743SRob Clark #define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 11168a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val) 11178a264743SRob Clark { 11188a264743SRob Clark return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK; 11198a264743SRob Clark } 11208a264743SRob Clark 1121a2272e48SRob Clark #define REG_A4XX_RB_BLEND_GREEN_F32 0x000020f3 1122a2272e48SRob Clark #define A4XX_RB_BLEND_GREEN_F32__MASK 0xffffffff 1123a2272e48SRob Clark #define A4XX_RB_BLEND_GREEN_F32__SHIFT 0 1124a2272e48SRob Clark static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val) 1125a2272e48SRob Clark { 1126a2272e48SRob Clark return ((fui(val)) << A4XX_RB_BLEND_GREEN_F32__SHIFT) & A4XX_RB_BLEND_GREEN_F32__MASK; 1127a2272e48SRob Clark } 1128a2272e48SRob Clark 1129a2272e48SRob Clark #define REG_A4XX_RB_BLEND_BLUE 0x000020f4 1130a26ae754SRob Clark #define A4XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff 11318a264743SRob Clark #define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0 11328a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val) 11338a264743SRob Clark { 11348a264743SRob Clark return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK; 11358a264743SRob Clark } 1136a26ae754SRob Clark #define A4XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00 1137a26ae754SRob Clark #define A4XX_RB_BLEND_BLUE_SINT__SHIFT 8 1138a26ae754SRob Clark static inline uint32_t A4XX_RB_BLEND_BLUE_SINT(uint32_t val) 1139a26ae754SRob Clark { 1140a26ae754SRob Clark return ((val) << A4XX_RB_BLEND_BLUE_SINT__SHIFT) & A4XX_RB_BLEND_BLUE_SINT__MASK; 1141a26ae754SRob Clark } 11428a264743SRob Clark #define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 11438a264743SRob Clark #define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 11448a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val) 11458a264743SRob Clark { 11468a264743SRob Clark return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK; 11478a264743SRob Clark } 11488a264743SRob Clark 1149a2272e48SRob Clark #define REG_A4XX_RB_BLEND_BLUE_F32 0x000020f5 1150a2272e48SRob Clark #define A4XX_RB_BLEND_BLUE_F32__MASK 0xffffffff 1151a2272e48SRob Clark #define A4XX_RB_BLEND_BLUE_F32__SHIFT 0 1152a2272e48SRob Clark static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val) 1153a2272e48SRob Clark { 1154a2272e48SRob Clark return ((fui(val)) << A4XX_RB_BLEND_BLUE_F32__SHIFT) & A4XX_RB_BLEND_BLUE_F32__MASK; 1155a2272e48SRob Clark } 1156a2272e48SRob Clark 11578a264743SRob Clark #define REG_A4XX_RB_BLEND_ALPHA 0x000020f6 1158a26ae754SRob Clark #define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff 11598a264743SRob Clark #define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0 11608a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val) 11618a264743SRob Clark { 11628a264743SRob Clark return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK; 11638a264743SRob Clark } 1164a26ae754SRob Clark #define A4XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00 1165a26ae754SRob Clark #define A4XX_RB_BLEND_ALPHA_SINT__SHIFT 8 1166a26ae754SRob Clark static inline uint32_t A4XX_RB_BLEND_ALPHA_SINT(uint32_t val) 1167a26ae754SRob Clark { 1168a26ae754SRob Clark return ((val) << A4XX_RB_BLEND_ALPHA_SINT__SHIFT) & A4XX_RB_BLEND_ALPHA_SINT__MASK; 1169a26ae754SRob Clark } 11708a264743SRob Clark #define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 11718a264743SRob Clark #define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 11728a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val) 11738a264743SRob Clark { 11748a264743SRob Clark return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK; 11758a264743SRob Clark } 11768a264743SRob Clark 1177a2272e48SRob Clark #define REG_A4XX_RB_BLEND_ALPHA_F32 0x000020f7 1178a2272e48SRob Clark #define A4XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff 1179a2272e48SRob Clark #define A4XX_RB_BLEND_ALPHA_F32__SHIFT 0 1180a2272e48SRob Clark static inline uint32_t A4XX_RB_BLEND_ALPHA_F32(float val) 1181a2272e48SRob Clark { 1182a2272e48SRob Clark return ((fui(val)) << A4XX_RB_BLEND_ALPHA_F32__SHIFT) & A4XX_RB_BLEND_ALPHA_F32__MASK; 1183a2272e48SRob Clark } 1184a2272e48SRob Clark 1185bc00ae02SRob Clark #define REG_A4XX_RB_ALPHA_CONTROL 0x000020f8 11868a264743SRob Clark #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff 11878a264743SRob Clark #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 11888a264743SRob Clark static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) 11898a264743SRob Clark { 11908a264743SRob Clark return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; 11918a264743SRob Clark } 1192bc00ae02SRob Clark #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 1193bc00ae02SRob Clark #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 1194bc00ae02SRob Clark #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 1195bc00ae02SRob Clark static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 1196bc00ae02SRob Clark { 1197bc00ae02SRob Clark return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; 1198bc00ae02SRob Clark } 1199bc00ae02SRob Clark 1200bc00ae02SRob Clark #define REG_A4XX_RB_FS_OUTPUT 0x000020f9 1201af6cb4c1SRob Clark #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK 0x000000ff 1202af6cb4c1SRob Clark #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT 0 1203af6cb4c1SRob Clark static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val) 1204af6cb4c1SRob Clark { 1205af6cb4c1SRob Clark return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK; 1206af6cb4c1SRob Clark } 1207a2272e48SRob Clark #define A4XX_RB_FS_OUTPUT_INDEPENDENT_BLEND 0x00000100 1208bc00ae02SRob Clark #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000 1209bc00ae02SRob Clark #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT 16 1210bc00ae02SRob Clark static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val) 1211bc00ae02SRob Clark { 1212bc00ae02SRob Clark return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK; 1213bc00ae02SRob Clark } 1214bc00ae02SRob Clark 12152d3584ebSRob Clark #define REG_A4XX_RB_SAMPLE_COUNT_CONTROL 0x000020fa 12162d3584ebSRob Clark #define A4XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 12172d3584ebSRob Clark #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK 0xfffffffc 12182d3584ebSRob Clark #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT 2 12192d3584ebSRob Clark static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val) 12202d3584ebSRob Clark { 12212d3584ebSRob Clark return ((val >> 2) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK; 12222d3584ebSRob Clark } 12232d3584ebSRob Clark 1224af6cb4c1SRob Clark #define REG_A4XX_RB_RENDER_COMPONENTS 0x000020fb 1225af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f 1226af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0 1227af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) 1228bc00ae02SRob Clark { 1229af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT0__MASK; 1230af6cb4c1SRob Clark } 1231af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0 1232af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4 1233af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) 1234af6cb4c1SRob Clark { 1235af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT1__MASK; 1236af6cb4c1SRob Clark } 1237af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00 1238af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8 1239af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) 1240af6cb4c1SRob Clark { 1241af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT2__MASK; 1242af6cb4c1SRob Clark } 1243af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000 1244af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12 1245af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) 1246af6cb4c1SRob Clark { 1247af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT3__MASK; 1248af6cb4c1SRob Clark } 1249af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000 1250af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16 1251af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) 1252af6cb4c1SRob Clark { 1253af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT4__MASK; 1254af6cb4c1SRob Clark } 1255af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000 1256af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20 1257af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) 1258af6cb4c1SRob Clark { 1259af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT5__MASK; 1260af6cb4c1SRob Clark } 1261af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000 1262af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24 1263af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) 1264af6cb4c1SRob Clark { 1265af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT6__MASK; 1266af6cb4c1SRob Clark } 1267af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000 1268af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28 1269af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) 1270af6cb4c1SRob Clark { 1271af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT7__MASK; 1272bc00ae02SRob Clark } 1273bc00ae02SRob Clark 1274bc00ae02SRob Clark #define REG_A4XX_RB_COPY_CONTROL 0x000020fc 1275bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003 1276bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0 1277bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) 1278bc00ae02SRob Clark { 1279bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK; 1280bc00ae02SRob Clark } 1281bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_MODE__MASK 0x00000070 1282bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_MODE__SHIFT 4 1283bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) 1284bc00ae02SRob Clark { 1285bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_CONTROL_MODE__SHIFT) & A4XX_RB_COPY_CONTROL_MODE__MASK; 1286bc00ae02SRob Clark } 1287bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00 1288bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8 1289bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) 1290bc00ae02SRob Clark { 1291bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK; 1292bc00ae02SRob Clark } 1293bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000 1294bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14 1295bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) 1296bc00ae02SRob Clark { 1297bc00ae02SRob Clark return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK; 1298bc00ae02SRob Clark } 1299bc00ae02SRob Clark 1300bc00ae02SRob Clark #define REG_A4XX_RB_COPY_DEST_BASE 0x000020fd 13018a264743SRob Clark #define A4XX_RB_COPY_DEST_BASE_BASE__MASK 0xffffffe0 13028a264743SRob Clark #define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT 5 1303bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val) 1304bc00ae02SRob Clark { 13058a264743SRob Clark return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK; 1306bc00ae02SRob Clark } 1307bc00ae02SRob Clark 1308bc00ae02SRob Clark #define REG_A4XX_RB_COPY_DEST_PITCH 0x000020fe 1309bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff 1310bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0 1311bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) 1312bc00ae02SRob Clark { 1313bc00ae02SRob Clark return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK; 1314bc00ae02SRob Clark } 1315bc00ae02SRob Clark 1316bc00ae02SRob Clark #define REG_A4XX_RB_COPY_DEST_INFO 0x000020ff 1317bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc 1318bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2 1319bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val) 1320bc00ae02SRob Clark { 1321bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A4XX_RB_COPY_DEST_INFO_FORMAT__MASK; 1322bc00ae02SRob Clark } 1323bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 1324bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 1325bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) 1326bc00ae02SRob Clark { 1327bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A4XX_RB_COPY_DEST_INFO_SWAP__MASK; 1328bc00ae02SRob Clark } 1329bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 1330bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 1331bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 1332bc00ae02SRob Clark { 1333bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 1334bc00ae02SRob Clark } 1335bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000 1336bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14 1337bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) 1338bc00ae02SRob Clark { 1339bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK; 1340bc00ae02SRob Clark } 1341bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000 1342bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18 1343bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) 1344bc00ae02SRob Clark { 1345bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK; 1346bc00ae02SRob Clark } 1347bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_TILE__MASK 0x03000000 1348bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_TILE__SHIFT 24 1349bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val) 1350bc00ae02SRob Clark { 1351bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A4XX_RB_COPY_DEST_INFO_TILE__MASK; 1352bc00ae02SRob Clark } 1353bc00ae02SRob Clark 1354bc00ae02SRob Clark #define REG_A4XX_RB_FS_OUTPUT_REG 0x00002100 1355af6cb4c1SRob Clark #define A4XX_RB_FS_OUTPUT_REG_MRT__MASK 0x0000000f 1356af6cb4c1SRob Clark #define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT 0 1357af6cb4c1SRob Clark static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val) 1358af6cb4c1SRob Clark { 1359af6cb4c1SRob Clark return ((val) << A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_RB_FS_OUTPUT_REG_MRT__MASK; 1360af6cb4c1SRob Clark } 1361bc00ae02SRob Clark #define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z 0x00000020 1362bc00ae02SRob Clark 1363bc00ae02SRob Clark #define REG_A4XX_RB_DEPTH_CONTROL 0x00002101 1364bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001 1365bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002 1366bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004 1367bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070 1368bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4 1369bc00ae02SRob Clark static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) 1370bc00ae02SRob Clark { 1371bc00ae02SRob Clark return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK; 1372bc00ae02SRob Clark } 1373a26ae754SRob Clark #define A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE 0x00000080 1374bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000 1375a2272e48SRob Clark #define A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS 0x00020000 1376bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000 1377bc00ae02SRob Clark 1378bc00ae02SRob Clark #define REG_A4XX_RB_DEPTH_CLEAR 0x00002102 1379bc00ae02SRob Clark 1380bc00ae02SRob Clark #define REG_A4XX_RB_DEPTH_INFO 0x00002103 1381bc00ae02SRob Clark #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003 1382bc00ae02SRob Clark #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 1383bc00ae02SRob Clark static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val) 1384bc00ae02SRob Clark { 1385bc00ae02SRob Clark return ((val) << A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 1386bc00ae02SRob Clark } 1387bc00ae02SRob Clark #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 1388bc00ae02SRob Clark #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 1389bc00ae02SRob Clark static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 1390bc00ae02SRob Clark { 1391bc00ae02SRob Clark return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 1392bc00ae02SRob Clark } 1393bc00ae02SRob Clark 1394bc00ae02SRob Clark #define REG_A4XX_RB_DEPTH_PITCH 0x00002104 1395bc00ae02SRob Clark #define A4XX_RB_DEPTH_PITCH__MASK 0xffffffff 1396bc00ae02SRob Clark #define A4XX_RB_DEPTH_PITCH__SHIFT 0 1397bc00ae02SRob Clark static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val) 1398bc00ae02SRob Clark { 13998a264743SRob Clark return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK; 1400bc00ae02SRob Clark } 1401bc00ae02SRob Clark 1402bc00ae02SRob Clark #define REG_A4XX_RB_DEPTH_PITCH2 0x00002105 1403bc00ae02SRob Clark #define A4XX_RB_DEPTH_PITCH2__MASK 0xffffffff 1404bc00ae02SRob Clark #define A4XX_RB_DEPTH_PITCH2__SHIFT 0 1405bc00ae02SRob Clark static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val) 1406bc00ae02SRob Clark { 14078a264743SRob Clark return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK; 1408bc00ae02SRob Clark } 1409bc00ae02SRob Clark 1410bc00ae02SRob Clark #define REG_A4XX_RB_STENCIL_CONTROL 0x00002106 1411bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 1412bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 1413bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 1414bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 1415bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 1416bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 1417bc00ae02SRob Clark { 1418bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC__MASK; 1419bc00ae02SRob Clark } 1420bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 1421bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 1422bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 1423bc00ae02SRob Clark { 1424bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL__MASK; 1425bc00ae02SRob Clark } 1426bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 1427bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 1428bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 1429bc00ae02SRob Clark { 1430bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS__MASK; 1431bc00ae02SRob Clark } 1432bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 1433bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 1434bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 1435bc00ae02SRob Clark { 1436bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 1437bc00ae02SRob Clark } 1438bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 1439bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 1440bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 1441bc00ae02SRob Clark { 1442bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 1443bc00ae02SRob Clark } 1444bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 1445bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 1446bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 1447bc00ae02SRob Clark { 1448bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 1449bc00ae02SRob Clark } 1450bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 1451bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 1452bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 1453bc00ae02SRob Clark { 1454bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 1455bc00ae02SRob Clark } 1456bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 1457bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 1458bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 1459bc00ae02SRob Clark { 1460bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 1461bc00ae02SRob Clark } 1462bc00ae02SRob Clark 1463bc00ae02SRob Clark #define REG_A4XX_RB_STENCIL_CONTROL2 0x00002107 1464bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER 0x00000001 1465bc00ae02SRob Clark 14662d3584ebSRob Clark #define REG_A4XX_RB_STENCIL_INFO 0x00002108 14672d3584ebSRob Clark #define A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 14682d3584ebSRob Clark #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff000 14692d3584ebSRob Clark #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 12 14702d3584ebSRob Clark static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) 14712d3584ebSRob Clark { 14722d3584ebSRob Clark return ((val >> 12) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK; 14732d3584ebSRob Clark } 14742d3584ebSRob Clark 14752d3584ebSRob Clark #define REG_A4XX_RB_STENCIL_PITCH 0x00002109 14762d3584ebSRob Clark #define A4XX_RB_STENCIL_PITCH__MASK 0xffffffff 14772d3584ebSRob Clark #define A4XX_RB_STENCIL_PITCH__SHIFT 0 14782d3584ebSRob Clark static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val) 14792d3584ebSRob Clark { 14802d3584ebSRob Clark return ((val >> 5) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK; 14812d3584ebSRob Clark } 14822d3584ebSRob Clark 1483bc00ae02SRob Clark #define REG_A4XX_RB_STENCILREFMASK 0x0000210b 1484bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 1485bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 1486bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 1487bc00ae02SRob Clark { 1488bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILREF__MASK; 1489bc00ae02SRob Clark } 1490bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 1491bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 1492bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 1493bc00ae02SRob Clark { 1494bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILMASK__MASK; 1495bc00ae02SRob Clark } 1496bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 1497bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 1498bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 1499bc00ae02SRob Clark { 1500bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 1501bc00ae02SRob Clark } 1502bc00ae02SRob Clark 1503bc00ae02SRob Clark #define REG_A4XX_RB_STENCILREFMASK_BF 0x0000210c 1504bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 1505bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 1506bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 1507bc00ae02SRob Clark { 1508bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 1509bc00ae02SRob Clark } 1510bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 1511bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 1512bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 1513bc00ae02SRob Clark { 1514bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 1515bc00ae02SRob Clark } 1516bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 1517bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 1518bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 1519bc00ae02SRob Clark { 1520bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 1521bc00ae02SRob Clark } 1522bc00ae02SRob Clark 1523bc00ae02SRob Clark #define REG_A4XX_RB_BIN_OFFSET 0x0000210d 1524bc00ae02SRob Clark #define A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 1525bc00ae02SRob Clark #define A4XX_RB_BIN_OFFSET_X__MASK 0x00007fff 1526bc00ae02SRob Clark #define A4XX_RB_BIN_OFFSET_X__SHIFT 0 1527bc00ae02SRob Clark static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val) 1528bc00ae02SRob Clark { 1529bc00ae02SRob Clark return ((val) << A4XX_RB_BIN_OFFSET_X__SHIFT) & A4XX_RB_BIN_OFFSET_X__MASK; 1530bc00ae02SRob Clark } 1531bc00ae02SRob Clark #define A4XX_RB_BIN_OFFSET_Y__MASK 0x7fff0000 1532bc00ae02SRob Clark #define A4XX_RB_BIN_OFFSET_Y__SHIFT 16 1533bc00ae02SRob Clark static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val) 1534bc00ae02SRob Clark { 1535bc00ae02SRob Clark return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK; 1536bc00ae02SRob Clark } 1537bc00ae02SRob Clark 15388a264743SRob Clark static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; } 15398a264743SRob Clark 15408a264743SRob Clark static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; } 15418a264743SRob Clark 15428a264743SRob Clark static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; } 1543bc00ae02SRob Clark 1544bc00ae02SRob Clark #define REG_A4XX_RBBM_HW_VERSION 0x00000000 1545bc00ae02SRob Clark 1546bc00ae02SRob Clark #define REG_A4XX_RBBM_HW_CONFIGURATION 0x00000002 1547bc00ae02SRob Clark 1548bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; } 1549bc00ae02SRob Clark 1550bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; } 1551bc00ae02SRob Clark 1552bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; } 1553bc00ae02SRob Clark 1554bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; } 1555bc00ae02SRob Clark 1556bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; } 1557bc00ae02SRob Clark 1558bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; } 1559bc00ae02SRob Clark 1560bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; } 1561bc00ae02SRob Clark 1562bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; } 1563bc00ae02SRob Clark 1564bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL_UCHE 0x00000014 1565bc00ae02SRob Clark 1566bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL2_UCHE 0x00000015 1567bc00ae02SRob Clark 1568bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL3_UCHE 0x00000016 1569bc00ae02SRob Clark 1570bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL4_UCHE 0x00000017 1571bc00ae02SRob Clark 1572bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_HYST_UCHE 0x00000018 1573bc00ae02SRob Clark 1574bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_DELAY_UCHE 0x00000019 1575bc00ae02SRob Clark 1576bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_MODE_GPC 0x0000001a 1577bc00ae02SRob Clark 1578bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_DELAY_GPC 0x0000001b 1579bc00ae02SRob Clark 1580bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_HYST_GPC 0x0000001c 1581bc00ae02SRob Clark 1582bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM 0x0000001d 1583bc00ae02SRob Clark 1584bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000001e 1585bc00ae02SRob Clark 1586bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x0000001f 1587bc00ae02SRob Clark 1588bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL 0x00000020 1589bc00ae02SRob Clark 1590bc00ae02SRob Clark #define REG_A4XX_RBBM_SP_HYST_CNT 0x00000021 1591bc00ae02SRob Clark 1592bc00ae02SRob Clark #define REG_A4XX_RBBM_SW_RESET_CMD 0x00000022 1593bc00ae02SRob Clark 1594bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_CTL0 0x00000023 1595bc00ae02SRob Clark 1596bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_CTL1 0x00000024 1597bc00ae02SRob Clark 1598bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_CMD 0x00000025 1599bc00ae02SRob Clark 1600bc00ae02SRob Clark #define REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL 0x00000026 1601bc00ae02SRob Clark 1602bc00ae02SRob Clark #define REG_A4XX_RBBM_RAM_ACC_63_32 0x00000028 1603bc00ae02SRob Clark 1604bc00ae02SRob Clark #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x0000002b 1605bc00ae02SRob Clark 1606bc00ae02SRob Clark #define REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL 0x0000002f 1607bc00ae02SRob Clark 1608bc00ae02SRob Clark #define REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4 0x00000034 1609bc00ae02SRob Clark 1610bc00ae02SRob Clark #define REG_A4XX_RBBM_INT_CLEAR_CMD 0x00000036 1611bc00ae02SRob Clark 1612bc00ae02SRob Clark #define REG_A4XX_RBBM_INT_0_MASK 0x00000037 1613bc00ae02SRob Clark 1614bc00ae02SRob Clark #define REG_A4XX_RBBM_RBBM_CTL 0x0000003e 1615bc00ae02SRob Clark 1616bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_DEBUG_CTL 0x0000003f 1617bc00ae02SRob Clark 1618bc00ae02SRob Clark #define REG_A4XX_RBBM_VBIF_DEBUG_CTL 0x00000041 1619bc00ae02SRob Clark 1620bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL2 0x00000042 1621bc00ae02SRob Clark 1622bc00ae02SRob Clark #define REG_A4XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 1623bc00ae02SRob Clark 1624bc00ae02SRob Clark #define REG_A4XX_RBBM_RESET_CYCLES 0x00000047 1625bc00ae02SRob Clark 1626bc00ae02SRob Clark #define REG_A4XX_RBBM_EXT_TRACE_BUS_CTL 0x00000049 1627bc00ae02SRob Clark 1628bc00ae02SRob Clark #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A 0x0000004a 1629bc00ae02SRob Clark 1630bc00ae02SRob Clark #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B 0x0000004b 1631bc00ae02SRob Clark 1632bc00ae02SRob Clark #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C 0x0000004c 1633bc00ae02SRob Clark 1634bc00ae02SRob Clark #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D 0x0000004d 1635bc00ae02SRob Clark 1636a2272e48SRob Clark #define REG_A4XX_RBBM_POWER_CNTL_IP 0x00000098 1637a2272e48SRob Clark #define A4XX_RBBM_POWER_CNTL_IP_SW_COLLAPSE 0x00000001 1638a2272e48SRob Clark #define A4XX_RBBM_POWER_CNTL_IP_SP_TP_PWR_ON 0x00100000 1639a2272e48SRob Clark 1640bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_0_LO 0x0000009c 1641bc00ae02SRob Clark 1642a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_0_HI 0x0000009d 1643a2272e48SRob Clark 1644a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_1_LO 0x0000009e 1645a2272e48SRob Clark 1646a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_1_HI 0x0000009f 1647a2272e48SRob Clark 1648a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_2_LO 0x000000a0 1649a2272e48SRob Clark 1650a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_2_HI 0x000000a1 1651a2272e48SRob Clark 1652a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_3_LO 0x000000a2 1653a2272e48SRob Clark 1654a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_3_HI 0x000000a3 1655a2272e48SRob Clark 1656a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_4_LO 0x000000a4 1657a2272e48SRob Clark 1658a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_4_HI 0x000000a5 1659a2272e48SRob Clark 1660a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_5_LO 0x000000a6 1661a2272e48SRob Clark 1662a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_5_HI 0x000000a7 1663a2272e48SRob Clark 1664a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_6_LO 0x000000a8 1665a2272e48SRob Clark 1666a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_6_HI 0x000000a9 1667a2272e48SRob Clark 1668a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_7_LO 0x000000aa 1669a2272e48SRob Clark 1670a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_7_HI 0x000000ab 1671a2272e48SRob Clark 1672a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_0_LO 0x000000ac 1673a2272e48SRob Clark 1674a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_0_HI 0x000000ad 1675a2272e48SRob Clark 1676a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_1_LO 0x000000ae 1677a2272e48SRob Clark 1678a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_1_HI 0x000000af 1679a2272e48SRob Clark 1680a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_2_LO 0x000000b0 1681a2272e48SRob Clark 1682a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_2_HI 0x000000b1 1683a2272e48SRob Clark 1684a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_3_LO 0x000000b2 1685a2272e48SRob Clark 1686a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_3_HI 0x000000b3 1687a2272e48SRob Clark 1688a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_0_LO 0x000000b4 1689a2272e48SRob Clark 1690a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_0_HI 0x000000b5 1691a2272e48SRob Clark 1692a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_1_LO 0x000000b6 1693a2272e48SRob Clark 1694a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_1_HI 0x000000b7 1695a2272e48SRob Clark 1696a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_2_LO 0x000000b8 1697a2272e48SRob Clark 1698a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_2_HI 0x000000b9 1699a2272e48SRob Clark 1700a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_3_LO 0x000000ba 1701a2272e48SRob Clark 1702a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_3_HI 0x000000bb 1703a2272e48SRob Clark 1704a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_4_LO 0x000000bc 1705a2272e48SRob Clark 1706a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_4_HI 0x000000bd 1707a2272e48SRob Clark 1708a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_5_LO 0x000000be 1709a2272e48SRob Clark 1710a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_5_HI 0x000000bf 1711a2272e48SRob Clark 1712a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_6_LO 0x000000c0 1713a2272e48SRob Clark 1714a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_6_HI 0x000000c1 1715a2272e48SRob Clark 1716a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_7_LO 0x000000c2 1717a2272e48SRob Clark 1718a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_7_HI 0x000000c3 1719a2272e48SRob Clark 1720a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_0_LO 0x000000c4 1721a2272e48SRob Clark 1722a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_0_HI 0x000000c5 1723a2272e48SRob Clark 1724a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_1_LO 0x000000c6 1725a2272e48SRob Clark 1726a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_1_HI 0x000000c7 1727a2272e48SRob Clark 1728a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_2_LO 0x000000c8 1729a2272e48SRob Clark 1730a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_2_HI 0x000000c9 1731a2272e48SRob Clark 1732a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_3_LO 0x000000ca 1733a2272e48SRob Clark 1734a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_3_HI 0x000000cb 1735a2272e48SRob Clark 1736a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_4_LO 0x000000cc 1737a2272e48SRob Clark 1738a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_4_HI 0x000000cd 1739a2272e48SRob Clark 1740a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_5_LO 0x000000ce 1741a2272e48SRob Clark 1742a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_5_HI 0x000000cf 1743a2272e48SRob Clark 1744a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_6_LO 0x000000d0 1745a2272e48SRob Clark 1746a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_6_HI 0x000000d1 1747a2272e48SRob Clark 1748a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_7_LO 0x000000d2 1749a2272e48SRob Clark 1750a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_7_HI 0x000000d3 1751a2272e48SRob Clark 1752a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000d4 1753a2272e48SRob Clark 1754a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000d5 1755a2272e48SRob Clark 1756a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000d6 1757a2272e48SRob Clark 1758a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000d7 1759a2272e48SRob Clark 1760a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000d8 1761a2272e48SRob Clark 1762a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000d9 1763a2272e48SRob Clark 1764a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000da 1765a2272e48SRob Clark 1766a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000db 1767a2272e48SRob Clark 1768a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000dc 1769a2272e48SRob Clark 1770a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000dd 1771a2272e48SRob Clark 1772a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000de 1773a2272e48SRob Clark 1774a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000df 1775a2272e48SRob Clark 1776a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_6_LO 0x000000e0 1777a2272e48SRob Clark 1778a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_6_HI 0x000000e1 1779a2272e48SRob Clark 1780a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_7_LO 0x000000e2 1781a2272e48SRob Clark 1782a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_7_HI 0x000000e3 1783a2272e48SRob Clark 1784a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VPC_0_LO 0x000000e4 1785a2272e48SRob Clark 1786a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VPC_0_HI 0x000000e5 1787a2272e48SRob Clark 1788a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VPC_1_LO 0x000000e6 1789a2272e48SRob Clark 1790a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VPC_1_HI 0x000000e7 1791a2272e48SRob Clark 1792a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VPC_2_LO 0x000000e8 1793a2272e48SRob Clark 1794a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VPC_2_HI 0x000000e9 1795a2272e48SRob Clark 1796a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VPC_3_LO 0x000000ea 1797a2272e48SRob Clark 1798a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VPC_3_HI 0x000000eb 1799a2272e48SRob Clark 1800a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CCU_0_LO 0x000000ec 1801a2272e48SRob Clark 1802a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CCU_0_HI 0x000000ed 1803a2272e48SRob Clark 1804a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CCU_1_LO 0x000000ee 1805a2272e48SRob Clark 1806a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CCU_1_HI 0x000000ef 1807a2272e48SRob Clark 1808a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CCU_2_LO 0x000000f0 1809a2272e48SRob Clark 1810a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CCU_2_HI 0x000000f1 1811a2272e48SRob Clark 1812a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CCU_3_LO 0x000000f2 1813a2272e48SRob Clark 1814a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CCU_3_HI 0x000000f3 1815a2272e48SRob Clark 1816a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TSE_0_LO 0x000000f4 1817a2272e48SRob Clark 1818a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TSE_0_HI 0x000000f5 1819a2272e48SRob Clark 1820a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TSE_1_LO 0x000000f6 1821a2272e48SRob Clark 1822a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TSE_1_HI 0x000000f7 1823a2272e48SRob Clark 1824a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TSE_2_LO 0x000000f8 1825a2272e48SRob Clark 1826a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TSE_2_HI 0x000000f9 1827a2272e48SRob Clark 1828a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TSE_3_LO 0x000000fa 1829a2272e48SRob Clark 1830a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TSE_3_HI 0x000000fb 1831a2272e48SRob Clark 1832a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RAS_0_LO 0x000000fc 1833a2272e48SRob Clark 1834a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RAS_0_HI 0x000000fd 1835a2272e48SRob Clark 1836a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RAS_1_LO 0x000000fe 1837a2272e48SRob Clark 1838a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RAS_1_HI 0x000000ff 1839a2272e48SRob Clark 1840a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RAS_2_LO 0x00000100 1841a2272e48SRob Clark 1842a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RAS_2_HI 0x00000101 1843a2272e48SRob Clark 1844a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RAS_3_LO 0x00000102 1845a2272e48SRob Clark 1846a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RAS_3_HI 0x00000103 1847a2272e48SRob Clark 1848a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_0_LO 0x00000104 1849a2272e48SRob Clark 1850a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_0_HI 0x00000105 1851a2272e48SRob Clark 1852a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_1_LO 0x00000106 1853a2272e48SRob Clark 1854a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_1_HI 0x00000107 1855a2272e48SRob Clark 1856a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_2_LO 0x00000108 1857a2272e48SRob Clark 1858a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_2_HI 0x00000109 1859a2272e48SRob Clark 1860a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_3_LO 0x0000010a 1861a2272e48SRob Clark 1862a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_3_HI 0x0000010b 1863a2272e48SRob Clark 1864a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_4_LO 0x0000010c 1865a2272e48SRob Clark 1866a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_4_HI 0x0000010d 1867a2272e48SRob Clark 1868a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_5_LO 0x0000010e 1869a2272e48SRob Clark 1870a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_5_HI 0x0000010f 1871a2272e48SRob Clark 1872a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_6_LO 0x00000110 1873a2272e48SRob Clark 1874a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_6_HI 0x00000111 1875a2272e48SRob Clark 1876a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_7_LO 0x00000112 1877a2272e48SRob Clark 1878a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_7_HI 0x00000113 1879a2272e48SRob Clark 1880a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_0_LO 0x00000114 1881a2272e48SRob Clark 1882a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115 1883a2272e48SRob Clark 1884a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_0_LO 0x00000114 1885a2272e48SRob Clark 1886a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115 1887a2272e48SRob Clark 1888a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_1_LO 0x00000116 1889a2272e48SRob Clark 1890a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_1_HI 0x00000117 1891a2272e48SRob Clark 1892a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_2_LO 0x00000118 1893a2272e48SRob Clark 1894a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_2_HI 0x00000119 1895a2272e48SRob Clark 1896a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_3_LO 0x0000011a 1897a2272e48SRob Clark 1898a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_3_HI 0x0000011b 1899a2272e48SRob Clark 1900a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_4_LO 0x0000011c 1901a2272e48SRob Clark 1902a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_4_HI 0x0000011d 1903a2272e48SRob Clark 1904a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_5_LO 0x0000011e 1905a2272e48SRob Clark 1906a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_5_HI 0x0000011f 1907a2272e48SRob Clark 1908a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_6_LO 0x00000120 1909a2272e48SRob Clark 1910a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_6_HI 0x00000121 1911a2272e48SRob Clark 1912a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_7_LO 0x00000122 1913a2272e48SRob Clark 1914a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_7_HI 0x00000123 1915a2272e48SRob Clark 1916a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_0_LO 0x00000124 1917a2272e48SRob Clark 1918a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_0_HI 0x00000125 1919a2272e48SRob Clark 1920a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_1_LO 0x00000126 1921a2272e48SRob Clark 1922a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_1_HI 0x00000127 1923a2272e48SRob Clark 1924a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_2_LO 0x00000128 1925a2272e48SRob Clark 1926a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_2_HI 0x00000129 1927a2272e48SRob Clark 1928a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_3_LO 0x0000012a 1929a2272e48SRob Clark 1930a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_3_HI 0x0000012b 1931a2272e48SRob Clark 1932a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_4_LO 0x0000012c 1933a2272e48SRob Clark 1934a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_4_HI 0x0000012d 1935a2272e48SRob Clark 1936a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_5_LO 0x0000012e 1937a2272e48SRob Clark 1938a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_5_HI 0x0000012f 1939a2272e48SRob Clark 1940a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_6_LO 0x00000130 1941a2272e48SRob Clark 1942a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_6_HI 0x00000131 1943a2272e48SRob Clark 1944a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_7_LO 0x00000132 1945a2272e48SRob Clark 1946a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_7_HI 0x00000133 1947a2272e48SRob Clark 1948a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_8_LO 0x00000134 1949a2272e48SRob Clark 1950a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_8_HI 0x00000135 1951a2272e48SRob Clark 1952a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_9_LO 0x00000136 1953a2272e48SRob Clark 1954a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_9_HI 0x00000137 1955a2272e48SRob Clark 1956a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_10_LO 0x00000138 1957a2272e48SRob Clark 1958a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_10_HI 0x00000139 1959a2272e48SRob Clark 1960a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_11_LO 0x0000013a 1961a2272e48SRob Clark 1962a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_11_HI 0x0000013b 1963a2272e48SRob Clark 1964a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_0_LO 0x0000013c 1965a2272e48SRob Clark 1966a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_0_HI 0x0000013d 1967a2272e48SRob Clark 1968a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_1_LO 0x0000013e 1969a2272e48SRob Clark 1970a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_1_HI 0x0000013f 1971a2272e48SRob Clark 1972a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_2_LO 0x00000140 1973a2272e48SRob Clark 1974a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_2_HI 0x00000141 1975a2272e48SRob Clark 1976a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_3_LO 0x00000142 1977a2272e48SRob Clark 1978a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_3_HI 0x00000143 1979a2272e48SRob Clark 1980a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_4_LO 0x00000144 1981a2272e48SRob Clark 1982a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_4_HI 0x00000145 1983a2272e48SRob Clark 1984a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_5_LO 0x00000146 1985a2272e48SRob Clark 1986a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_5_HI 0x00000147 1987a2272e48SRob Clark 1988a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_6_LO 0x00000148 1989a2272e48SRob Clark 1990a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_6_HI 0x00000149 1991a2272e48SRob Clark 1992a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_7_LO 0x0000014a 1993a2272e48SRob Clark 1994a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_7_HI 0x0000014b 1995a2272e48SRob Clark 1996a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VSC_0_LO 0x0000014c 1997a2272e48SRob Clark 1998a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VSC_0_HI 0x0000014d 1999a2272e48SRob Clark 2000a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VSC_1_LO 0x0000014e 2001a2272e48SRob Clark 2002a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VSC_1_HI 0x0000014f 2003a2272e48SRob Clark 2004a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PWR_0_LO 0x00000166 2005a2272e48SRob Clark 2006a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PWR_0_HI 0x00000167 2007a2272e48SRob Clark 2008a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168 2009a2272e48SRob Clark 2010a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PWR_1_HI 0x00000169 2011a2272e48SRob Clark 2012a2272e48SRob Clark #define REG_A4XX_RBBM_ALWAYSON_COUNTER_LO 0x0000016e 2013a2272e48SRob Clark 2014a2272e48SRob Clark #define REG_A4XX_RBBM_ALWAYSON_COUNTER_HI 0x0000016f 2015a2272e48SRob Clark 2016bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; } 2017bc00ae02SRob Clark 2018bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; } 2019bc00ae02SRob Clark 2020bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; } 2021bc00ae02SRob Clark 2022bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; } 2023bc00ae02SRob Clark 2024bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; } 2025bc00ae02SRob Clark 2026bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; } 2027bc00ae02SRob Clark 2028bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; } 2029bc00ae02SRob Clark 2030bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; } 2031bc00ae02SRob Clark 2032bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; } 2033bc00ae02SRob Clark 2034bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; } 2035bc00ae02SRob Clark 2036bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; } 2037bc00ae02SRob Clark 2038bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; } 2039bc00ae02SRob Clark 2040bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; } 2041bc00ae02SRob Clark 2042bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; } 2043bc00ae02SRob Clark 2044bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; } 2045bc00ae02SRob Clark 2046bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; } 2047bc00ae02SRob Clark 2048bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM 0x00000080 2049bc00ae02SRob Clark 2050bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM 0x00000081 2051bc00ae02SRob Clark 2052bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL_HLSQ 0x0000008a 2053bc00ae02SRob Clark 2054bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_HYST_HLSQ 0x0000008b 2055bc00ae02SRob Clark 2056bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ 0x0000008c 2057bc00ae02SRob Clark 2058bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM 0x0000008d 2059bc00ae02SRob Clark 2060bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; } 2061bc00ae02SRob Clark 2062bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; } 2063bc00ae02SRob Clark 2064a2272e48SRob Clark #define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0 0x00000099 2065a2272e48SRob Clark 2066a2272e48SRob Clark #define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1 0x0000009a 2067a2272e48SRob Clark 2068bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168 2069bc00ae02SRob Clark 2070bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170 2071bc00ae02SRob Clark 2072bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0 0x00000171 2073bc00ae02SRob Clark 2074bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1 0x00000172 2075bc00ae02SRob Clark 2076bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2 0x00000173 2077bc00ae02SRob Clark 2078bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000174 2079bc00ae02SRob Clark 2080bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000175 2081bc00ae02SRob Clark 2082a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000176 2083a2272e48SRob Clark 2084a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000177 2085a2272e48SRob Clark 2086a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000178 2087a2272e48SRob Clark 2088a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_3 0x00000179 2089a2272e48SRob Clark 2090bc00ae02SRob Clark #define REG_A4XX_RBBM_GPU_BUSY_MASKED 0x0000017a 2091bc00ae02SRob Clark 2092bc00ae02SRob Clark #define REG_A4XX_RBBM_INT_0_STATUS 0x0000017d 2093bc00ae02SRob Clark 2094bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_STATUS 0x00000182 2095bc00ae02SRob Clark 2096bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_STATUS 0x00000189 2097bc00ae02SRob Clark 2098bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS 0x0000018c 2099bc00ae02SRob Clark 2100bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS 0x0000018d 2101bc00ae02SRob Clark 2102bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_ERROR_STATUS 0x0000018f 2103bc00ae02SRob Clark 2104bc00ae02SRob Clark #define REG_A4XX_RBBM_STATUS 0x00000191 2105bc00ae02SRob Clark #define A4XX_RBBM_STATUS_HI_BUSY 0x00000001 2106bc00ae02SRob Clark #define A4XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 2107bc00ae02SRob Clark #define A4XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 2108bc00ae02SRob Clark #define A4XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000 2109bc00ae02SRob Clark #define A4XX_RBBM_STATUS_VBIF_BUSY 0x00008000 2110bc00ae02SRob Clark #define A4XX_RBBM_STATUS_TSE_BUSY 0x00010000 2111bc00ae02SRob Clark #define A4XX_RBBM_STATUS_RAS_BUSY 0x00020000 2112bc00ae02SRob Clark #define A4XX_RBBM_STATUS_RB_BUSY 0x00040000 2113bc00ae02SRob Clark #define A4XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 2114bc00ae02SRob Clark #define A4XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 2115bc00ae02SRob Clark #define A4XX_RBBM_STATUS_VFD_BUSY 0x00200000 2116bc00ae02SRob Clark #define A4XX_RBBM_STATUS_VPC_BUSY 0x00400000 2117bc00ae02SRob Clark #define A4XX_RBBM_STATUS_UCHE_BUSY 0x00800000 2118bc00ae02SRob Clark #define A4XX_RBBM_STATUS_SP_BUSY 0x01000000 2119bc00ae02SRob Clark #define A4XX_RBBM_STATUS_TPL1_BUSY 0x02000000 2120bc00ae02SRob Clark #define A4XX_RBBM_STATUS_MARB_BUSY 0x04000000 2121bc00ae02SRob Clark #define A4XX_RBBM_STATUS_VSC_BUSY 0x08000000 2122bc00ae02SRob Clark #define A4XX_RBBM_STATUS_ARB_BUSY 0x10000000 2123bc00ae02SRob Clark #define A4XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 2124bc00ae02SRob Clark #define A4XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000 2125bc00ae02SRob Clark #define A4XX_RBBM_STATUS_GPU_BUSY 0x80000000 2126bc00ae02SRob Clark 2127bc00ae02SRob Clark #define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5 0x0000019f 2128bc00ae02SRob Clark 2129a2272e48SRob Clark #define REG_A4XX_RBBM_POWER_STATUS 0x000001b0 2130a2272e48SRob Clark #define A4XX_RBBM_POWER_STATUS_SP_TP_PWR_ON 0x00100000 2131a2272e48SRob Clark 2132a2272e48SRob Clark #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2 0x000001b8 2133a2272e48SRob Clark 2134bc00ae02SRob Clark #define REG_A4XX_CP_SCRATCH_UMASK 0x00000228 2135bc00ae02SRob Clark 2136bc00ae02SRob Clark #define REG_A4XX_CP_SCRATCH_ADDR 0x00000229 2137bc00ae02SRob Clark 2138bc00ae02SRob Clark #define REG_A4XX_CP_RB_BASE 0x00000200 2139bc00ae02SRob Clark 2140bc00ae02SRob Clark #define REG_A4XX_CP_RB_CNTL 0x00000201 2141bc00ae02SRob Clark 2142bc00ae02SRob Clark #define REG_A4XX_CP_RB_WPTR 0x00000205 2143bc00ae02SRob Clark 2144bc00ae02SRob Clark #define REG_A4XX_CP_RB_RPTR_ADDR 0x00000203 2145bc00ae02SRob Clark 2146bc00ae02SRob Clark #define REG_A4XX_CP_RB_RPTR 0x00000204 2147bc00ae02SRob Clark 2148bc00ae02SRob Clark #define REG_A4XX_CP_IB1_BASE 0x00000206 2149bc00ae02SRob Clark 2150bc00ae02SRob Clark #define REG_A4XX_CP_IB1_BUFSZ 0x00000207 2151bc00ae02SRob Clark 2152bc00ae02SRob Clark #define REG_A4XX_CP_IB2_BASE 0x00000208 2153bc00ae02SRob Clark 2154bc00ae02SRob Clark #define REG_A4XX_CP_IB2_BUFSZ 0x00000209 2155bc00ae02SRob Clark 2156af6cb4c1SRob Clark #define REG_A4XX_CP_ME_NRT_ADDR 0x0000020c 2157af6cb4c1SRob Clark 2158af6cb4c1SRob Clark #define REG_A4XX_CP_ME_NRT_DATA 0x0000020d 2159af6cb4c1SRob Clark 2160bc00ae02SRob Clark #define REG_A4XX_CP_ME_RB_DONE_DATA 0x00000217 2161bc00ae02SRob Clark 2162bc00ae02SRob Clark #define REG_A4XX_CP_QUEUE_THRESH2 0x00000219 2163bc00ae02SRob Clark 2164bc00ae02SRob Clark #define REG_A4XX_CP_MERCIU_SIZE 0x0000021b 2165bc00ae02SRob Clark 2166bc00ae02SRob Clark #define REG_A4XX_CP_ROQ_ADDR 0x0000021c 2167bc00ae02SRob Clark 2168bc00ae02SRob Clark #define REG_A4XX_CP_ROQ_DATA 0x0000021d 2169bc00ae02SRob Clark 2170bc00ae02SRob Clark #define REG_A4XX_CP_MEQ_ADDR 0x0000021e 2171bc00ae02SRob Clark 2172bc00ae02SRob Clark #define REG_A4XX_CP_MEQ_DATA 0x0000021f 2173bc00ae02SRob Clark 2174bc00ae02SRob Clark #define REG_A4XX_CP_MERCIU_ADDR 0x00000220 2175bc00ae02SRob Clark 2176bc00ae02SRob Clark #define REG_A4XX_CP_MERCIU_DATA 0x00000221 2177bc00ae02SRob Clark 2178bc00ae02SRob Clark #define REG_A4XX_CP_MERCIU_DATA2 0x00000222 2179bc00ae02SRob Clark 2180bc00ae02SRob Clark #define REG_A4XX_CP_PFP_UCODE_ADDR 0x00000223 2181bc00ae02SRob Clark 2182bc00ae02SRob Clark #define REG_A4XX_CP_PFP_UCODE_DATA 0x00000224 2183bc00ae02SRob Clark 2184bc00ae02SRob Clark #define REG_A4XX_CP_ME_RAM_WADDR 0x00000225 2185bc00ae02SRob Clark 2186bc00ae02SRob Clark #define REG_A4XX_CP_ME_RAM_RADDR 0x00000226 2187bc00ae02SRob Clark 2188bc00ae02SRob Clark #define REG_A4XX_CP_ME_RAM_DATA 0x00000227 2189bc00ae02SRob Clark 2190bc00ae02SRob Clark #define REG_A4XX_CP_PREEMPT 0x0000022a 2191bc00ae02SRob Clark 2192bc00ae02SRob Clark #define REG_A4XX_CP_CNTL 0x0000022c 2193bc00ae02SRob Clark 2194bc00ae02SRob Clark #define REG_A4XX_CP_ME_CNTL 0x0000022d 2195bc00ae02SRob Clark 2196bc00ae02SRob Clark #define REG_A4XX_CP_DEBUG 0x0000022e 2197bc00ae02SRob Clark 2198bc00ae02SRob Clark #define REG_A4XX_CP_DEBUG_ECO_CONTROL 0x00000231 2199bc00ae02SRob Clark 2200bc00ae02SRob Clark #define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232 2201bc00ae02SRob Clark 2202bc00ae02SRob Clark static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; } 2203bc00ae02SRob Clark 2204bc00ae02SRob Clark static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; } 2205a26ae754SRob Clark #define A4XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff 2206a26ae754SRob Clark #define A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0 2207a26ae754SRob Clark static inline uint32_t A4XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) 2208a26ae754SRob Clark { 2209a26ae754SRob Clark return ((val) << A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A4XX_CP_PROTECT_REG_BASE_ADDR__MASK; 2210a26ae754SRob Clark } 2211a26ae754SRob Clark #define A4XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000 2212a26ae754SRob Clark #define A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24 2213a26ae754SRob Clark static inline uint32_t A4XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) 2214a26ae754SRob Clark { 2215a26ae754SRob Clark return ((val) << A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A4XX_CP_PROTECT_REG_MASK_LEN__MASK; 2216a26ae754SRob Clark } 2217a26ae754SRob Clark #define A4XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000 2218a26ae754SRob Clark #define A4XX_CP_PROTECT_REG_TRAP_READ 0x40000000 2219bc00ae02SRob Clark 2220bc00ae02SRob Clark #define REG_A4XX_CP_PROTECT_CTRL 0x00000250 2221bc00ae02SRob Clark 2222bc00ae02SRob Clark #define REG_A4XX_CP_ST_BASE 0x000004c0 2223bc00ae02SRob Clark 2224bc00ae02SRob Clark #define REG_A4XX_CP_STQ_AVAIL 0x000004ce 2225bc00ae02SRob Clark 2226bc00ae02SRob Clark #define REG_A4XX_CP_MERCIU_STAT 0x000004d0 2227bc00ae02SRob Clark 2228bc00ae02SRob Clark #define REG_A4XX_CP_WFI_PEND_CTR 0x000004d2 2229bc00ae02SRob Clark 2230bc00ae02SRob Clark #define REG_A4XX_CP_HW_FAULT 0x000004d8 2231bc00ae02SRob Clark 2232bc00ae02SRob Clark #define REG_A4XX_CP_PROTECT_STATUS 0x000004da 2233bc00ae02SRob Clark 2234bc00ae02SRob Clark #define REG_A4XX_CP_EVENTS_IN_FLIGHT 0x000004dd 2235bc00ae02SRob Clark 2236bc00ae02SRob Clark #define REG_A4XX_CP_PERFCTR_CP_SEL_0 0x00000500 2237bc00ae02SRob Clark 2238a2272e48SRob Clark #define REG_A4XX_CP_PERFCTR_CP_SEL_1 0x00000501 2239a2272e48SRob Clark 2240a2272e48SRob Clark #define REG_A4XX_CP_PERFCTR_CP_SEL_2 0x00000502 2241a2272e48SRob Clark 2242a2272e48SRob Clark #define REG_A4XX_CP_PERFCTR_CP_SEL_3 0x00000503 2243a2272e48SRob Clark 2244a2272e48SRob Clark #define REG_A4XX_CP_PERFCTR_CP_SEL_4 0x00000504 2245a2272e48SRob Clark 2246a2272e48SRob Clark #define REG_A4XX_CP_PERFCTR_CP_SEL_5 0x00000505 2247a2272e48SRob Clark 2248a2272e48SRob Clark #define REG_A4XX_CP_PERFCTR_CP_SEL_6 0x00000506 2249a2272e48SRob Clark 2250a2272e48SRob Clark #define REG_A4XX_CP_PERFCTR_CP_SEL_7 0x00000507 2251a2272e48SRob Clark 2252bc00ae02SRob Clark #define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b 2253bc00ae02SRob Clark 2254bc00ae02SRob Clark static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; } 2255bc00ae02SRob Clark 2256bc00ae02SRob Clark static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; } 2257bc00ae02SRob Clark 2258bc00ae02SRob Clark #define REG_A4XX_SP_VS_STATUS 0x00000ec0 2259bc00ae02SRob Clark 2260af6cb4c1SRob Clark #define REG_A4XX_SP_MODE_CONTROL 0x00000ec3 2261af6cb4c1SRob Clark 2262a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_0 0x00000ec4 2263a2272e48SRob Clark 2264a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_1 0x00000ec5 2265a2272e48SRob Clark 2266a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_2 0x00000ec6 2267a2272e48SRob Clark 2268a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_3 0x00000ec7 2269a2272e48SRob Clark 2270a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_4 0x00000ec8 2271a2272e48SRob Clark 2272a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_5 0x00000ec9 2273a2272e48SRob Clark 2274a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_6 0x00000eca 2275a2272e48SRob Clark 2276a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_7 0x00000ecb 2277a2272e48SRob Clark 2278a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_8 0x00000ecc 2279a2272e48SRob Clark 2280a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_9 0x00000ecd 2281a2272e48SRob Clark 2282a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_10 0x00000ece 2283a2272e48SRob Clark 2284bc00ae02SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_11 0x00000ecf 2285bc00ae02SRob Clark 2286bc00ae02SRob Clark #define REG_A4XX_SP_SP_CTRL_REG 0x000022c0 2287bc00ae02SRob Clark #define A4XX_SP_SP_CTRL_REG_BINNING_PASS 0x00080000 2288bc00ae02SRob Clark 2289bc00ae02SRob Clark #define REG_A4XX_SP_INSTR_CACHE_CTRL 0x000022c1 2290af6cb4c1SRob Clark #define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER 0x00000080 2291af6cb4c1SRob Clark #define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER 0x00000100 2292af6cb4c1SRob Clark #define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER 0x00000400 2293bc00ae02SRob Clark 2294bc00ae02SRob Clark #define REG_A4XX_SP_VS_CTRL_REG0 0x000022c4 2295bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 2296bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 2297bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 2298bc00ae02SRob Clark { 2299bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK; 2300bc00ae02SRob Clark } 2301bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_VARYING 0x00000002 2302bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004 2303bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 2304bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 2305bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 2306bc00ae02SRob Clark { 2307bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 2308bc00ae02SRob Clark } 2309a26ae754SRob Clark #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 2310bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 2311bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 2312bc00ae02SRob Clark { 2313bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 2314bc00ae02SRob Clark } 2315bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 2316bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 2317bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 2318bc00ae02SRob Clark { 2319bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK; 2320bc00ae02SRob Clark } 2321bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000 2322bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20 2323bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 2324bc00ae02SRob Clark { 2325bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; 2326bc00ae02SRob Clark } 2327bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000 2328bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000 2329bc00ae02SRob Clark 2330bc00ae02SRob Clark #define REG_A4XX_SP_VS_CTRL_REG1 0x000022c5 2331bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff 2332bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0 2333bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) 2334bc00ae02SRob Clark { 2335bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK; 2336bc00ae02SRob Clark } 2337bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000 2338bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24 2339bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) 2340bc00ae02SRob Clark { 2341bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK; 2342bc00ae02SRob Clark } 2343bc00ae02SRob Clark 2344bc00ae02SRob Clark #define REG_A4XX_SP_VS_PARAM_REG 0x000022c6 2345bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff 2346bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0 2347bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) 2348bc00ae02SRob Clark { 2349bc00ae02SRob Clark return ((val) << A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_POSREGID__MASK; 2350bc00ae02SRob Clark } 2351bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00 2352bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8 2353bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) 2354bc00ae02SRob Clark { 2355bc00ae02SRob Clark return ((val) << A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK; 2356bc00ae02SRob Clark } 2357bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000 2358bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20 2359bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) 2360bc00ae02SRob Clark { 2361bc00ae02SRob Clark return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; 2362bc00ae02SRob Clark } 2363bc00ae02SRob Clark 2364bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 2365bc00ae02SRob Clark 2366bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 2367bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff 2368bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 2369bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 2370bc00ae02SRob Clark { 2371bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_A_REGID__MASK; 2372bc00ae02SRob Clark } 2373bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00 2374bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9 2375bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 2376bc00ae02SRob Clark { 2377bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 2378bc00ae02SRob Clark } 2379bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000 2380bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 2381bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 2382bc00ae02SRob Clark { 2383bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_B_REGID__MASK; 2384bc00ae02SRob Clark } 2385bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000 2386bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25 2387bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 2388bc00ae02SRob Clark { 2389bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 2390bc00ae02SRob Clark } 2391bc00ae02SRob Clark 2392bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; } 2393bc00ae02SRob Clark 2394bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; } 2395bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 2396bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 2397bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 2398bc00ae02SRob Clark { 2399bc00ae02SRob Clark return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 2400bc00ae02SRob Clark } 2401bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 2402bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 2403bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 2404bc00ae02SRob Clark { 2405bc00ae02SRob Clark return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 2406bc00ae02SRob Clark } 2407bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 2408bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 2409bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 2410bc00ae02SRob Clark { 2411bc00ae02SRob Clark return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 2412bc00ae02SRob Clark } 2413bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 2414bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 2415bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 2416bc00ae02SRob Clark { 2417bc00ae02SRob Clark return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 2418bc00ae02SRob Clark } 2419bc00ae02SRob Clark 2420bc00ae02SRob Clark #define REG_A4XX_SP_VS_OBJ_OFFSET_REG 0x000022e0 2421bc00ae02SRob Clark #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2422bc00ae02SRob Clark #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2423bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2424bc00ae02SRob Clark { 2425bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2426bc00ae02SRob Clark } 2427bc00ae02SRob Clark #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2428bc00ae02SRob Clark #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2429bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2430bc00ae02SRob Clark { 2431bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2432bc00ae02SRob Clark } 2433bc00ae02SRob Clark 2434bc00ae02SRob Clark #define REG_A4XX_SP_VS_OBJ_START 0x000022e1 2435bc00ae02SRob Clark 2436bc00ae02SRob Clark #define REG_A4XX_SP_VS_PVT_MEM_PARAM 0x000022e2 2437bc00ae02SRob Clark 2438bc00ae02SRob Clark #define REG_A4XX_SP_VS_PVT_MEM_ADDR 0x000022e3 2439bc00ae02SRob Clark 2440bc00ae02SRob Clark #define REG_A4XX_SP_VS_LENGTH_REG 0x000022e5 2441bc00ae02SRob Clark 2442bc00ae02SRob Clark #define REG_A4XX_SP_FS_CTRL_REG0 0x000022e8 2443bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 2444bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 2445bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 2446bc00ae02SRob Clark { 2447bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK; 2448bc00ae02SRob Clark } 2449bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_VARYING 0x00000002 2450bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004 2451bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 2452bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 2453bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 2454bc00ae02SRob Clark { 2455bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 2456bc00ae02SRob Clark } 2457a26ae754SRob Clark #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 2458bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 2459bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 2460bc00ae02SRob Clark { 2461bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 2462bc00ae02SRob Clark } 2463bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 2464bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 2465bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 2466bc00ae02SRob Clark { 2467bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK; 2468bc00ae02SRob Clark } 2469bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 2470bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 2471bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 2472bc00ae02SRob Clark { 2473bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 2474bc00ae02SRob Clark } 2475bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000 2476bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000 2477bc00ae02SRob Clark 2478bc00ae02SRob Clark #define REG_A4XX_SP_FS_CTRL_REG1 0x000022e9 2479bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff 2480bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0 2481bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) 2482bc00ae02SRob Clark { 2483bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK; 2484bc00ae02SRob Clark } 24858a264743SRob Clark #define A4XX_SP_FS_CTRL_REG1_FACENESS 0x00080000 2486bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG1_VARYING 0x00100000 24878a264743SRob Clark #define A4XX_SP_FS_CTRL_REG1_FRAGCOORD 0x00200000 2488bc00ae02SRob Clark 2489bc00ae02SRob Clark #define REG_A4XX_SP_FS_OBJ_OFFSET_REG 0x000022ea 2490bc00ae02SRob Clark #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2491bc00ae02SRob Clark #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2492bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2493bc00ae02SRob Clark { 2494bc00ae02SRob Clark return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2495bc00ae02SRob Clark } 2496bc00ae02SRob Clark #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2497bc00ae02SRob Clark #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2498bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2499bc00ae02SRob Clark { 2500bc00ae02SRob Clark return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2501bc00ae02SRob Clark } 2502bc00ae02SRob Clark 2503bc00ae02SRob Clark #define REG_A4XX_SP_FS_OBJ_START 0x000022eb 2504bc00ae02SRob Clark 2505bc00ae02SRob Clark #define REG_A4XX_SP_FS_PVT_MEM_PARAM 0x000022ec 2506bc00ae02SRob Clark 2507bc00ae02SRob Clark #define REG_A4XX_SP_FS_PVT_MEM_ADDR 0x000022ed 2508bc00ae02SRob Clark 2509bc00ae02SRob Clark #define REG_A4XX_SP_FS_LENGTH_REG 0x000022ef 2510bc00ae02SRob Clark 2511bc00ae02SRob Clark #define REG_A4XX_SP_FS_OUTPUT_REG 0x000022f0 2512af6cb4c1SRob Clark #define A4XX_SP_FS_OUTPUT_REG_MRT__MASK 0x0000000f 2513af6cb4c1SRob Clark #define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0 2514af6cb4c1SRob Clark static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val) 2515af6cb4c1SRob Clark { 2516af6cb4c1SRob Clark return ((val) << A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_SP_FS_OUTPUT_REG_MRT__MASK; 2517af6cb4c1SRob Clark } 2518bc00ae02SRob Clark #define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080 2519bc00ae02SRob Clark #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00 2520bc00ae02SRob Clark #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8 2521bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) 2522bc00ae02SRob Clark { 2523bc00ae02SRob Clark return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK; 2524bc00ae02SRob Clark } 2525af6cb4c1SRob Clark #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK 0xff000000 2526af6cb4c1SRob Clark #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT 24 2527af6cb4c1SRob Clark static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val) 2528af6cb4c1SRob Clark { 2529af6cb4c1SRob Clark return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK; 2530af6cb4c1SRob Clark } 2531bc00ae02SRob Clark 2532bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; } 2533bc00ae02SRob Clark 2534bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; } 2535bc00ae02SRob Clark #define A4XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff 2536bc00ae02SRob Clark #define A4XX_SP_FS_MRT_REG_REGID__SHIFT 0 2537bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val) 2538bc00ae02SRob Clark { 2539bc00ae02SRob Clark return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK; 2540bc00ae02SRob Clark } 2541bc00ae02SRob Clark #define A4XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100 2542bc00ae02SRob Clark #define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK 0x0003f000 2543bc00ae02SRob Clark #define A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT 12 2544bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val) 2545bc00ae02SRob Clark { 2546bc00ae02SRob Clark return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK; 2547bc00ae02SRob Clark } 25482d3584ebSRob Clark #define A4XX_SP_FS_MRT_REG_COLOR_SRGB 0x00040000 2549bc00ae02SRob Clark 2550af6cb4c1SRob Clark #define REG_A4XX_SP_CS_CTRL_REG0 0x00002300 2551af6cb4c1SRob Clark 2552af6cb4c1SRob Clark #define REG_A4XX_SP_CS_OBJ_OFFSET_REG 0x00002301 2553af6cb4c1SRob Clark 2554af6cb4c1SRob Clark #define REG_A4XX_SP_CS_OBJ_START 0x00002302 2555af6cb4c1SRob Clark 2556af6cb4c1SRob Clark #define REG_A4XX_SP_CS_PVT_MEM_PARAM 0x00002303 2557af6cb4c1SRob Clark 2558af6cb4c1SRob Clark #define REG_A4XX_SP_CS_PVT_MEM_ADDR 0x00002304 2559af6cb4c1SRob Clark 2560af6cb4c1SRob Clark #define REG_A4XX_SP_CS_PVT_MEM_SIZE 0x00002305 2561af6cb4c1SRob Clark 2562af6cb4c1SRob Clark #define REG_A4XX_SP_CS_LENGTH_REG 0x00002306 2563af6cb4c1SRob Clark 2564bc00ae02SRob Clark #define REG_A4XX_SP_HS_OBJ_OFFSET_REG 0x0000230d 2565bc00ae02SRob Clark #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2566bc00ae02SRob Clark #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2567bc00ae02SRob Clark static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2568bc00ae02SRob Clark { 2569bc00ae02SRob Clark return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2570bc00ae02SRob Clark } 2571bc00ae02SRob Clark #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2572bc00ae02SRob Clark #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2573bc00ae02SRob Clark static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2574bc00ae02SRob Clark { 2575bc00ae02SRob Clark return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2576bc00ae02SRob Clark } 2577bc00ae02SRob Clark 2578af6cb4c1SRob Clark #define REG_A4XX_SP_HS_OBJ_START 0x0000230e 2579af6cb4c1SRob Clark 2580af6cb4c1SRob Clark #define REG_A4XX_SP_HS_PVT_MEM_PARAM 0x0000230f 2581af6cb4c1SRob Clark 2582af6cb4c1SRob Clark #define REG_A4XX_SP_HS_PVT_MEM_ADDR 0x00002310 2583af6cb4c1SRob Clark 2584af6cb4c1SRob Clark #define REG_A4XX_SP_HS_LENGTH_REG 0x00002312 2585af6cb4c1SRob Clark 25862d3584ebSRob Clark #define REG_A4XX_SP_DS_PARAM_REG 0x0000231a 25872d3584ebSRob Clark #define A4XX_SP_DS_PARAM_REG_POSREGID__MASK 0x000000ff 25882d3584ebSRob Clark #define A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT 0 25892d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val) 25902d3584ebSRob Clark { 25912d3584ebSRob Clark return ((val) << A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_DS_PARAM_REG_POSREGID__MASK; 25922d3584ebSRob Clark } 25932d3584ebSRob Clark #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000 25942d3584ebSRob Clark #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20 25952d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) 25962d3584ebSRob Clark { 25972d3584ebSRob Clark return ((val) << A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK; 25982d3584ebSRob Clark } 25992d3584ebSRob Clark 26002d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; } 26012d3584ebSRob Clark 26022d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; } 26032d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_A_REGID__MASK 0x000001ff 26042d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_A_REGID__SHIFT 0 26052d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val) 26062d3584ebSRob Clark { 26072d3584ebSRob Clark return ((val) << A4XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_A_REGID__MASK; 26082d3584ebSRob Clark } 26092d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00001e00 26102d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 9 26112d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val) 26122d3584ebSRob Clark { 26132d3584ebSRob Clark return ((val) << A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK; 26142d3584ebSRob Clark } 26152d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_B_REGID__MASK 0x01ff0000 26162d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_B_REGID__SHIFT 16 26172d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val) 26182d3584ebSRob Clark { 26192d3584ebSRob Clark return ((val) << A4XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_B_REGID__MASK; 26202d3584ebSRob Clark } 26212d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x1e000000 26222d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 25 26232d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val) 26242d3584ebSRob Clark { 26252d3584ebSRob Clark return ((val) << A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK; 26262d3584ebSRob Clark } 26272d3584ebSRob Clark 26282d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; } 26292d3584ebSRob Clark 26302d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; } 26312d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 26322d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0 26332d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val) 26342d3584ebSRob Clark { 26352d3584ebSRob Clark return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK; 26362d3584ebSRob Clark } 26372d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 26382d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8 26392d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val) 26402d3584ebSRob Clark { 26412d3584ebSRob Clark return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK; 26422d3584ebSRob Clark } 26432d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 26442d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16 26452d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val) 26462d3584ebSRob Clark { 26472d3584ebSRob Clark return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK; 26482d3584ebSRob Clark } 26492d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 26502d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24 26512d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) 26522d3584ebSRob Clark { 26532d3584ebSRob Clark return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK; 26542d3584ebSRob Clark } 26552d3584ebSRob Clark 2656bc00ae02SRob Clark #define REG_A4XX_SP_DS_OBJ_OFFSET_REG 0x00002334 2657bc00ae02SRob Clark #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2658bc00ae02SRob Clark #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2659bc00ae02SRob Clark static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2660bc00ae02SRob Clark { 2661bc00ae02SRob Clark return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2662bc00ae02SRob Clark } 2663bc00ae02SRob Clark #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2664bc00ae02SRob Clark #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2665bc00ae02SRob Clark static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2666bc00ae02SRob Clark { 2667bc00ae02SRob Clark return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2668bc00ae02SRob Clark } 2669bc00ae02SRob Clark 2670af6cb4c1SRob Clark #define REG_A4XX_SP_DS_OBJ_START 0x00002335 2671af6cb4c1SRob Clark 2672af6cb4c1SRob Clark #define REG_A4XX_SP_DS_PVT_MEM_PARAM 0x00002336 2673af6cb4c1SRob Clark 2674af6cb4c1SRob Clark #define REG_A4XX_SP_DS_PVT_MEM_ADDR 0x00002337 2675af6cb4c1SRob Clark 2676af6cb4c1SRob Clark #define REG_A4XX_SP_DS_LENGTH_REG 0x00002339 2677af6cb4c1SRob Clark 26782d3584ebSRob Clark #define REG_A4XX_SP_GS_PARAM_REG 0x00002341 26792d3584ebSRob Clark #define A4XX_SP_GS_PARAM_REG_POSREGID__MASK 0x000000ff 26802d3584ebSRob Clark #define A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT 0 26812d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val) 26822d3584ebSRob Clark { 26832d3584ebSRob Clark return ((val) << A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_POSREGID__MASK; 26842d3584ebSRob Clark } 26852d3584ebSRob Clark #define A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK 0x0000ff00 26862d3584ebSRob Clark #define A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT 8 26872d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val) 26882d3584ebSRob Clark { 26892d3584ebSRob Clark return ((val) << A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK; 26902d3584ebSRob Clark } 26912d3584ebSRob Clark #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000 26922d3584ebSRob Clark #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20 26932d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) 26942d3584ebSRob Clark { 26952d3584ebSRob Clark return ((val) << A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK; 26962d3584ebSRob Clark } 26972d3584ebSRob Clark 26982d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; } 26992d3584ebSRob Clark 27002d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; } 27012d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_A_REGID__MASK 0x000001ff 27022d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_A_REGID__SHIFT 0 27032d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val) 27042d3584ebSRob Clark { 27052d3584ebSRob Clark return ((val) << A4XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_A_REGID__MASK; 27062d3584ebSRob Clark } 27072d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00001e00 27082d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 9 27092d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val) 27102d3584ebSRob Clark { 27112d3584ebSRob Clark return ((val) << A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK; 27122d3584ebSRob Clark } 27132d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_B_REGID__MASK 0x01ff0000 27142d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_B_REGID__SHIFT 16 27152d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val) 27162d3584ebSRob Clark { 27172d3584ebSRob Clark return ((val) << A4XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_B_REGID__MASK; 27182d3584ebSRob Clark } 27192d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x1e000000 27202d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 25 27212d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val) 27222d3584ebSRob Clark { 27232d3584ebSRob Clark return ((val) << A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK; 27242d3584ebSRob Clark } 27252d3584ebSRob Clark 27262d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; } 27272d3584ebSRob Clark 27282d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; } 27292d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 27302d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0 27312d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val) 27322d3584ebSRob Clark { 27332d3584ebSRob Clark return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK; 27342d3584ebSRob Clark } 27352d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 27362d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8 27372d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val) 27382d3584ebSRob Clark { 27392d3584ebSRob Clark return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK; 27402d3584ebSRob Clark } 27412d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 27422d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16 27432d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val) 27442d3584ebSRob Clark { 27452d3584ebSRob Clark return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK; 27462d3584ebSRob Clark } 27472d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 27482d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24 27492d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) 27502d3584ebSRob Clark { 27512d3584ebSRob Clark return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK; 27522d3584ebSRob Clark } 27532d3584ebSRob Clark 2754bc00ae02SRob Clark #define REG_A4XX_SP_GS_OBJ_OFFSET_REG 0x0000235b 2755bc00ae02SRob Clark #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2756bc00ae02SRob Clark #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2757bc00ae02SRob Clark static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2758bc00ae02SRob Clark { 2759bc00ae02SRob Clark return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2760bc00ae02SRob Clark } 2761bc00ae02SRob Clark #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2762bc00ae02SRob Clark #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2763bc00ae02SRob Clark static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2764bc00ae02SRob Clark { 2765bc00ae02SRob Clark return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2766bc00ae02SRob Clark } 2767bc00ae02SRob Clark 2768af6cb4c1SRob Clark #define REG_A4XX_SP_GS_OBJ_START 0x0000235c 2769af6cb4c1SRob Clark 2770af6cb4c1SRob Clark #define REG_A4XX_SP_GS_PVT_MEM_PARAM 0x0000235d 2771af6cb4c1SRob Clark 2772af6cb4c1SRob Clark #define REG_A4XX_SP_GS_PVT_MEM_ADDR 0x0000235e 2773af6cb4c1SRob Clark 2774bc00ae02SRob Clark #define REG_A4XX_SP_GS_LENGTH_REG 0x00002360 2775bc00ae02SRob Clark 2776bc00ae02SRob Clark #define REG_A4XX_VPC_DEBUG_RAM_SEL 0x00000e60 2777bc00ae02SRob Clark 2778bc00ae02SRob Clark #define REG_A4XX_VPC_DEBUG_RAM_READ 0x00000e61 2779bc00ae02SRob Clark 2780bc00ae02SRob Clark #define REG_A4XX_VPC_DEBUG_ECO_CONTROL 0x00000e64 2781bc00ae02SRob Clark 2782a2272e48SRob Clark #define REG_A4XX_VPC_PERFCTR_VPC_SEL_0 0x00000e65 2783a2272e48SRob Clark 2784a2272e48SRob Clark #define REG_A4XX_VPC_PERFCTR_VPC_SEL_1 0x00000e66 2785a2272e48SRob Clark 2786a2272e48SRob Clark #define REG_A4XX_VPC_PERFCTR_VPC_SEL_2 0x00000e67 2787a2272e48SRob Clark 2788bc00ae02SRob Clark #define REG_A4XX_VPC_PERFCTR_VPC_SEL_3 0x00000e68 2789bc00ae02SRob Clark 2790bc00ae02SRob Clark #define REG_A4XX_VPC_ATTR 0x00002140 2791bc00ae02SRob Clark #define A4XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff 2792bc00ae02SRob Clark #define A4XX_VPC_ATTR_TOTALATTR__SHIFT 0 2793bc00ae02SRob Clark static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val) 2794bc00ae02SRob Clark { 2795bc00ae02SRob Clark return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK; 2796bc00ae02SRob Clark } 2797bc00ae02SRob Clark #define A4XX_VPC_ATTR_PSIZE 0x00000200 2798bc00ae02SRob Clark #define A4XX_VPC_ATTR_THRDASSIGN__MASK 0x00003000 2799bc00ae02SRob Clark #define A4XX_VPC_ATTR_THRDASSIGN__SHIFT 12 2800bc00ae02SRob Clark static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val) 2801bc00ae02SRob Clark { 2802bc00ae02SRob Clark return ((val) << A4XX_VPC_ATTR_THRDASSIGN__SHIFT) & A4XX_VPC_ATTR_THRDASSIGN__MASK; 2803bc00ae02SRob Clark } 2804bc00ae02SRob Clark #define A4XX_VPC_ATTR_ENABLE 0x02000000 2805bc00ae02SRob Clark 2806bc00ae02SRob Clark #define REG_A4XX_VPC_PACK 0x00002141 2807bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMBYPASSVAR__MASK 0x000000ff 2808bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT 0 2809bc00ae02SRob Clark static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val) 2810bc00ae02SRob Clark { 2811bc00ae02SRob Clark return ((val) << A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT) & A4XX_VPC_PACK_NUMBYPASSVAR__MASK; 2812bc00ae02SRob Clark } 2813bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00 2814bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8 2815bc00ae02SRob Clark static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) 2816bc00ae02SRob Clark { 2817bc00ae02SRob Clark return ((val) << A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK; 2818bc00ae02SRob Clark } 2819bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000 2820bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16 2821bc00ae02SRob Clark static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) 2822bc00ae02SRob Clark { 2823bc00ae02SRob Clark return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK; 2824bc00ae02SRob Clark } 2825bc00ae02SRob Clark 2826bc00ae02SRob Clark static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; } 2827bc00ae02SRob Clark 2828bc00ae02SRob Clark static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; } 2829bc00ae02SRob Clark 2830bc00ae02SRob Clark static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; } 2831bc00ae02SRob Clark 2832bc00ae02SRob Clark static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; } 2833bc00ae02SRob Clark 2834bc00ae02SRob Clark #define REG_A4XX_VPC_SO_FLUSH_WADDR_3 0x0000216e 2835bc00ae02SRob Clark 2836bc00ae02SRob Clark #define REG_A4XX_VSC_BIN_SIZE 0x00000c00 2837bc00ae02SRob Clark #define A4XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 2838bc00ae02SRob Clark #define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 2839bc00ae02SRob Clark static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 2840bc00ae02SRob Clark { 2841bc00ae02SRob Clark return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK; 2842bc00ae02SRob Clark } 2843bc00ae02SRob Clark #define A4XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 2844bc00ae02SRob Clark #define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5 2845bc00ae02SRob Clark static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 2846bc00ae02SRob Clark { 2847bc00ae02SRob Clark return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK; 2848bc00ae02SRob Clark } 2849bc00ae02SRob Clark 2850bc00ae02SRob Clark #define REG_A4XX_VSC_SIZE_ADDRESS 0x00000c01 2851bc00ae02SRob Clark 2852bc00ae02SRob Clark #define REG_A4XX_VSC_SIZE_ADDRESS2 0x00000c02 2853bc00ae02SRob Clark 2854bc00ae02SRob Clark #define REG_A4XX_VSC_DEBUG_ECO_CONTROL 0x00000c03 2855bc00ae02SRob Clark 2856bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } 2857bc00ae02SRob Clark 2858bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } 2859bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff 2860bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0 2861bc00ae02SRob Clark static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) 2862bc00ae02SRob Clark { 2863bc00ae02SRob Clark return ((val) << A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_X__MASK; 2864bc00ae02SRob Clark } 2865bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00 2866bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10 2867bc00ae02SRob Clark static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) 2868bc00ae02SRob Clark { 2869bc00ae02SRob Clark return ((val) << A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_Y__MASK; 2870bc00ae02SRob Clark } 2871bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000 2872bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20 2873bc00ae02SRob Clark static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) 2874bc00ae02SRob Clark { 2875bc00ae02SRob Clark return ((val) << A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_W__MASK; 2876bc00ae02SRob Clark } 2877bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000 2878bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24 2879bc00ae02SRob Clark static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) 2880bc00ae02SRob Clark { 2881bc00ae02SRob Clark return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK; 2882bc00ae02SRob Clark } 2883bc00ae02SRob Clark 2884bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 2885bc00ae02SRob Clark 2886bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 2887bc00ae02SRob Clark 2888bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; } 2889bc00ae02SRob Clark 2890bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; } 2891bc00ae02SRob Clark 2892bc00ae02SRob Clark #define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1 0x00000c41 2893bc00ae02SRob Clark 2894bc00ae02SRob Clark #define REG_A4XX_VSC_PERFCTR_VSC_SEL_0 0x00000c50 2895bc00ae02SRob Clark 2896bc00ae02SRob Clark #define REG_A4XX_VSC_PERFCTR_VSC_SEL_1 0x00000c51 2897bc00ae02SRob Clark 2898bc00ae02SRob Clark #define REG_A4XX_VFD_DEBUG_CONTROL 0x00000e40 2899bc00ae02SRob Clark 2900a2272e48SRob Clark #define REG_A4XX_VFD_PERFCTR_VFD_SEL_0 0x00000e43 2901a2272e48SRob Clark 2902a2272e48SRob Clark #define REG_A4XX_VFD_PERFCTR_VFD_SEL_1 0x00000e44 2903a2272e48SRob Clark 2904a2272e48SRob Clark #define REG_A4XX_VFD_PERFCTR_VFD_SEL_2 0x00000e45 2905a2272e48SRob Clark 2906a2272e48SRob Clark #define REG_A4XX_VFD_PERFCTR_VFD_SEL_3 0x00000e46 2907a2272e48SRob Clark 2908a2272e48SRob Clark #define REG_A4XX_VFD_PERFCTR_VFD_SEL_4 0x00000e47 2909a2272e48SRob Clark 2910a2272e48SRob Clark #define REG_A4XX_VFD_PERFCTR_VFD_SEL_5 0x00000e48 2911a2272e48SRob Clark 2912a2272e48SRob Clark #define REG_A4XX_VFD_PERFCTR_VFD_SEL_6 0x00000e49 2913a2272e48SRob Clark 2914bc00ae02SRob Clark #define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 0x00000e4a 2915bc00ae02SRob Clark 2916af6cb4c1SRob Clark #define REG_A4XX_VGT_CL_INITIATOR 0x000021d0 2917af6cb4c1SRob Clark 2918af6cb4c1SRob Clark #define REG_A4XX_VGT_EVENT_INITIATOR 0x000021d9 2919af6cb4c1SRob Clark 2920bc00ae02SRob Clark #define REG_A4XX_VFD_CONTROL_0 0x00002200 2921bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x000000ff 2922bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0 2923bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) 2924bc00ae02SRob Clark { 2925bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK; 2926bc00ae02SRob Clark } 2927bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK 0x0001fe00 2928bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT 9 2929bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val) 2930bc00ae02SRob Clark { 2931bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT) & A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK; 2932bc00ae02SRob Clark } 2933bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x03f00000 2934bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 20 2935bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) 2936bc00ae02SRob Clark { 2937bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK; 2938bc00ae02SRob Clark } 2939bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xfc000000 2940bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 26 2941bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) 2942bc00ae02SRob Clark { 2943bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK; 2944bc00ae02SRob Clark } 2945bc00ae02SRob Clark 2946bc00ae02SRob Clark #define REG_A4XX_VFD_CONTROL_1 0x00002201 2947bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff 2948bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0 2949bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) 2950bc00ae02SRob Clark { 2951bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK; 2952bc00ae02SRob Clark } 2953bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000 2954bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16 2955bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 2956bc00ae02SRob Clark { 2957bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A4XX_VFD_CONTROL_1_REGID4VTX__MASK; 2958bc00ae02SRob Clark } 2959bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000 2960bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_REGID4INST__SHIFT 24 2961bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 2962bc00ae02SRob Clark { 2963bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A4XX_VFD_CONTROL_1_REGID4INST__MASK; 2964bc00ae02SRob Clark } 2965bc00ae02SRob Clark 2966bc00ae02SRob Clark #define REG_A4XX_VFD_CONTROL_2 0x00002202 2967bc00ae02SRob Clark 2968bc00ae02SRob Clark #define REG_A4XX_VFD_CONTROL_3 0x00002203 29698a264743SRob Clark #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK 0x0000ff00 29708a264743SRob Clark #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT 8 29718a264743SRob Clark static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val) 29728a264743SRob Clark { 29738a264743SRob Clark return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK; 29748a264743SRob Clark } 29752d3584ebSRob Clark #define A4XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000 29762d3584ebSRob Clark #define A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16 29772d3584ebSRob Clark static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) 29782d3584ebSRob Clark { 29792d3584ebSRob Clark return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSX__MASK; 29802d3584ebSRob Clark } 29812d3584ebSRob Clark #define A4XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000 29822d3584ebSRob Clark #define A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24 29832d3584ebSRob Clark static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) 29842d3584ebSRob Clark { 29852d3584ebSRob Clark return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSY__MASK; 29862d3584ebSRob Clark } 2987bc00ae02SRob Clark 2988bc00ae02SRob Clark #define REG_A4XX_VFD_CONTROL_4 0x00002204 2989bc00ae02SRob Clark 2990bc00ae02SRob Clark #define REG_A4XX_VFD_INDEX_OFFSET 0x00002208 2991bc00ae02SRob Clark 2992bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; } 2993bc00ae02SRob Clark 2994bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; } 2995bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f 2996bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0 2997bc00ae02SRob Clark static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) 2998bc00ae02SRob Clark { 2999bc00ae02SRob Clark return ((val) << A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK; 3000bc00ae02SRob Clark } 3001bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80 3002bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7 3003bc00ae02SRob Clark static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) 3004bc00ae02SRob Clark { 3005bc00ae02SRob Clark return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK; 3006bc00ae02SRob Clark } 3007bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00080000 30088a264743SRob Clark #define A4XX_VFD_FETCH_INSTR_0_INSTANCED 0x00100000 3009bc00ae02SRob Clark 3010bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; } 3011bc00ae02SRob Clark 3012bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; } 3013bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xfffffff0 3014bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 4 3015bc00ae02SRob Clark static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val) 3016bc00ae02SRob Clark { 3017bc00ae02SRob Clark return ((val >> 4) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK; 3018bc00ae02SRob Clark } 3019bc00ae02SRob Clark 3020bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; } 30218a264743SRob Clark #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK 0x000001ff 30228a264743SRob Clark #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT 0 30238a264743SRob Clark static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val) 30248a264743SRob Clark { 30258a264743SRob Clark return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK; 30268a264743SRob Clark } 3027bc00ae02SRob Clark 3028bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; } 3029bc00ae02SRob Clark 3030bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; } 3031bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f 3032bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0 3033bc00ae02SRob Clark static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) 3034bc00ae02SRob Clark { 3035bc00ae02SRob Clark return ((val) << A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK; 3036bc00ae02SRob Clark } 3037bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010 3038bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0 3039bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6 3040bc00ae02SRob Clark static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val) 3041bc00ae02SRob Clark { 3042bc00ae02SRob Clark return ((val) << A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A4XX_VFD_DECODE_INSTR_FORMAT__MASK; 3043bc00ae02SRob Clark } 3044bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000 3045bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_REGID__SHIFT 12 3046bc00ae02SRob Clark static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val) 3047bc00ae02SRob Clark { 3048bc00ae02SRob Clark return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK; 3049bc00ae02SRob Clark } 30508a264743SRob Clark #define A4XX_VFD_DECODE_INSTR_INT 0x00100000 3051bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000 3052bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT 22 3053bc00ae02SRob Clark static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 3054bc00ae02SRob Clark { 3055bc00ae02SRob Clark return ((val) << A4XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A4XX_VFD_DECODE_INSTR_SWAP__MASK; 3056bc00ae02SRob Clark } 3057bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000 3058bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24 3059bc00ae02SRob Clark static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) 3060bc00ae02SRob Clark { 3061bc00ae02SRob Clark return ((val) << A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK; 3062bc00ae02SRob Clark } 3063bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000 3064bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000 3065bc00ae02SRob Clark 3066bc00ae02SRob Clark #define REG_A4XX_TPL1_DEBUG_ECO_CONTROL 0x00000f00 3067bc00ae02SRob Clark 3068af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_MODE_CONTROL 0x00000f03 3069af6cb4c1SRob Clark 3070a2272e48SRob Clark #define REG_A4XX_TPL1_PERFCTR_TP_SEL_0 0x00000f04 3071a2272e48SRob Clark 3072a2272e48SRob Clark #define REG_A4XX_TPL1_PERFCTR_TP_SEL_1 0x00000f05 3073a2272e48SRob Clark 3074a2272e48SRob Clark #define REG_A4XX_TPL1_PERFCTR_TP_SEL_2 0x00000f06 3075a2272e48SRob Clark 3076a2272e48SRob Clark #define REG_A4XX_TPL1_PERFCTR_TP_SEL_3 0x00000f07 3077a2272e48SRob Clark 3078a2272e48SRob Clark #define REG_A4XX_TPL1_PERFCTR_TP_SEL_4 0x00000f08 3079a2272e48SRob Clark 3080a2272e48SRob Clark #define REG_A4XX_TPL1_PERFCTR_TP_SEL_5 0x00000f09 3081a2272e48SRob Clark 3082a2272e48SRob Clark #define REG_A4XX_TPL1_PERFCTR_TP_SEL_6 0x00000f0a 3083a2272e48SRob Clark 3084bc00ae02SRob Clark #define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 0x00000f0b 3085bc00ae02SRob Clark 3086bc00ae02SRob Clark #define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380 3087bc00ae02SRob Clark 3088af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_TEX_COUNT 0x00002381 3089af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_VS__MASK 0x000000ff 3090af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT 0 3091af6cb4c1SRob Clark static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val) 3092af6cb4c1SRob Clark { 3093af6cb4c1SRob Clark return ((val) << A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_VS__MASK; 3094af6cb4c1SRob Clark } 3095af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_HS__MASK 0x0000ff00 3096af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT 8 3097af6cb4c1SRob Clark static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val) 3098af6cb4c1SRob Clark { 3099af6cb4c1SRob Clark return ((val) << A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_HS__MASK; 3100af6cb4c1SRob Clark } 3101af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_DS__MASK 0x00ff0000 3102af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT 16 3103af6cb4c1SRob Clark static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val) 3104af6cb4c1SRob Clark { 3105af6cb4c1SRob Clark return ((val) << A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_DS__MASK; 3106af6cb4c1SRob Clark } 3107af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_GS__MASK 0xff000000 3108af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT 24 3109af6cb4c1SRob Clark static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val) 3110af6cb4c1SRob Clark { 3111af6cb4c1SRob Clark return ((val) << A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_GS__MASK; 3112af6cb4c1SRob Clark } 3113af6cb4c1SRob Clark 3114af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002384 3115af6cb4c1SRob Clark 3116af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR 0x00002387 3117af6cb4c1SRob Clark 3118af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR 0x0000238a 3119af6cb4c1SRob Clark 3120af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR 0x0000238d 3121af6cb4c1SRob Clark 3122af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_FS_TEX_COUNT 0x000023a0 3123af6cb4c1SRob Clark 3124af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x000023a1 3125af6cb4c1SRob Clark 3126af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_CS_BORDER_COLOR_BASE_ADDR 0x000023a4 3127af6cb4c1SRob Clark 3128af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_CS_SAMPLER_BASE_ADDR 0x000023a5 3129af6cb4c1SRob Clark 3130bc00ae02SRob Clark #define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR 0x000023a6 3131bc00ae02SRob Clark 3132bc00ae02SRob Clark #define REG_A4XX_GRAS_TSE_STATUS 0x00000c80 3133bc00ae02SRob Clark 3134bc00ae02SRob Clark #define REG_A4XX_GRAS_DEBUG_ECO_CONTROL 0x00000c81 3135bc00ae02SRob Clark 3136bc00ae02SRob Clark #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c88 3137bc00ae02SRob Clark 3138a2272e48SRob Clark #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c89 3139a2272e48SRob Clark 3140a2272e48SRob Clark #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c8a 3141a2272e48SRob Clark 3142bc00ae02SRob Clark #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c8b 3143bc00ae02SRob Clark 3144a2272e48SRob Clark #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c8c 3145a2272e48SRob Clark 3146a2272e48SRob Clark #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c8d 3147a2272e48SRob Clark 3148a2272e48SRob Clark #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c8e 3149a2272e48SRob Clark 3150a2272e48SRob Clark #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c8f 3151a2272e48SRob Clark 3152bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000 3153a2272e48SRob Clark #define A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00008000 3154a26ae754SRob Clark #define A4XX_GRAS_CL_CLIP_CNTL_ZNEAR_CLIP_DISABLE 0x00010000 3155a26ae754SRob Clark #define A4XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000 3156a2272e48SRob Clark #define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000 3157bc00ae02SRob Clark 3158bc00ae02SRob Clark #define REG_A4XX_GRAS_CLEAR_CNTL 0x00002003 3159bc00ae02SRob Clark #define A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR 0x00000001 3160bc00ae02SRob Clark 3161bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_GB_CLIP_ADJ 0x00002004 3162bc00ae02SRob Clark #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff 3163bc00ae02SRob Clark #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0 3164bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) 3165bc00ae02SRob Clark { 3166bc00ae02SRob Clark return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; 3167bc00ae02SRob Clark } 3168bc00ae02SRob Clark #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00 3169bc00ae02SRob Clark #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10 3170bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) 3171bc00ae02SRob Clark { 3172bc00ae02SRob Clark return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; 3173bc00ae02SRob Clark } 3174bc00ae02SRob Clark 3175bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_XOFFSET_0 0x00002008 3176bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff 3177bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0 3178bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val) 3179bc00ae02SRob Clark { 3180bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK; 3181bc00ae02SRob Clark } 3182bc00ae02SRob Clark 3183bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_XSCALE_0 0x00002009 3184bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff 3185bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0 3186bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val) 3187bc00ae02SRob Clark { 3188bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_XSCALE_0__MASK; 3189bc00ae02SRob Clark } 3190bc00ae02SRob Clark 3191bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_YOFFSET_0 0x0000200a 3192bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff 3193bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0 3194bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val) 3195bc00ae02SRob Clark { 3196bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK; 3197bc00ae02SRob Clark } 3198bc00ae02SRob Clark 3199bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_YSCALE_0 0x0000200b 3200bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff 3201bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0 3202bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val) 3203bc00ae02SRob Clark { 3204bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_YSCALE_0__MASK; 3205bc00ae02SRob Clark } 3206bc00ae02SRob Clark 3207bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000200c 3208bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff 3209bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0 3210bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val) 3211bc00ae02SRob Clark { 3212bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK; 3213bc00ae02SRob Clark } 3214bc00ae02SRob Clark 3215bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_ZSCALE_0 0x0000200d 3216bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff 3217bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0 3218bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val) 3219bc00ae02SRob Clark { 3220bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK; 3221bc00ae02SRob Clark } 3222bc00ae02SRob Clark 3223bc00ae02SRob Clark #define REG_A4XX_GRAS_SU_POINT_MINMAX 0x00002070 3224bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 3225bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 3226bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val) 3227bc00ae02SRob Clark { 3228bc00ae02SRob Clark return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 3229bc00ae02SRob Clark } 3230bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 3231bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 3232bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val) 3233bc00ae02SRob Clark { 3234bc00ae02SRob Clark return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 3235bc00ae02SRob Clark } 3236bc00ae02SRob Clark 3237bc00ae02SRob Clark #define REG_A4XX_GRAS_SU_POINT_SIZE 0x00002071 3238bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff 3239bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_SIZE__SHIFT 0 3240bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val) 3241bc00ae02SRob Clark { 3242bc00ae02SRob Clark return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK; 3243bc00ae02SRob Clark } 3244bc00ae02SRob Clark 3245bc00ae02SRob Clark #define REG_A4XX_GRAS_ALPHA_CONTROL 0x00002073 3246bc00ae02SRob Clark #define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE 0x00000004 3247a2272e48SRob Clark #define A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS 0x00000008 3248bc00ae02SRob Clark 3249bc00ae02SRob Clark #define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE 0x00002074 3250bc00ae02SRob Clark #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff 3251bc00ae02SRob Clark #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 3252bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val) 3253bc00ae02SRob Clark { 3254bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; 3255bc00ae02SRob Clark } 3256bc00ae02SRob Clark 3257bc00ae02SRob Clark #define REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00002075 3258bc00ae02SRob Clark #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 3259bc00ae02SRob Clark #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 3260bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 3261bc00ae02SRob Clark { 3262bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 3263bc00ae02SRob Clark } 3264bc00ae02SRob Clark 3265af6cb4c1SRob Clark #define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP 0x00002076 3266af6cb4c1SRob Clark #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK 0xffffffff 3267af6cb4c1SRob Clark #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT 0 3268af6cb4c1SRob Clark static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val) 3269af6cb4c1SRob Clark { 3270af6cb4c1SRob Clark return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK; 3271af6cb4c1SRob Clark } 3272af6cb4c1SRob Clark 32738a264743SRob Clark #define REG_A4XX_GRAS_DEPTH_CONTROL 0x00002077 32748a264743SRob Clark #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK 0x00000003 32758a264743SRob Clark #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT 0 32768a264743SRob Clark static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val) 32778a264743SRob Clark { 32788a264743SRob Clark return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK; 32798a264743SRob Clark } 32808a264743SRob Clark 32818a264743SRob Clark #define REG_A4XX_GRAS_SU_MODE_CONTROL 0x00002078 32828a264743SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001 32838a264743SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002 32848a264743SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004 32858a264743SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8 32868a264743SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3 32878a264743SRob Clark static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) 32888a264743SRob Clark { 32898a264743SRob Clark return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; 32908a264743SRob Clark } 32918a264743SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800 3292a26ae754SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_MSAA_ENABLE 0x00002000 32938a264743SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS 0x00100000 32948a264743SRob Clark 32958a264743SRob Clark #define REG_A4XX_GRAS_SC_CONTROL 0x0000207b 32968a264743SRob Clark #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x0000000c 32978a264743SRob Clark #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 2 32988a264743SRob Clark static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) 32998a264743SRob Clark { 33008a264743SRob Clark return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK; 33018a264743SRob Clark } 33028a264743SRob Clark #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000380 33038a264743SRob Clark #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 7 33048a264743SRob Clark static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val) 33058a264743SRob Clark { 33068a264743SRob Clark return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK; 33078a264743SRob Clark } 33088a264743SRob Clark #define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE 0x00000800 33098a264743SRob Clark #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000 33108a264743SRob Clark #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12 33118a264743SRob Clark static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) 33128a264743SRob Clark { 33138a264743SRob Clark return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK; 33148a264743SRob Clark } 3315bc00ae02SRob Clark 3316bc00ae02SRob Clark #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL 0x0000207c 3317bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 3318bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 3319bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 3320bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 3321bc00ae02SRob Clark { 3322bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; 3323bc00ae02SRob Clark } 3324bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 3325bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 3326bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 3327bc00ae02SRob Clark { 3328bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; 3329bc00ae02SRob Clark } 3330bc00ae02SRob Clark 3331bc00ae02SRob Clark #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR 0x0000207d 3332bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 3333bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 3334bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 3335bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 3336bc00ae02SRob Clark { 3337bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; 3338bc00ae02SRob Clark } 3339bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 3340bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 3341bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 3342bc00ae02SRob Clark { 3343bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; 3344bc00ae02SRob Clark } 3345bc00ae02SRob Clark 3346bc00ae02SRob Clark #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000209c 3347bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 3348bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 3349bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 3350bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 3351bc00ae02SRob Clark { 3352bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 3353bc00ae02SRob Clark } 3354bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 3355bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 3356bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 3357bc00ae02SRob Clark { 3358bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 3359bc00ae02SRob Clark } 3360bc00ae02SRob Clark 3361bc00ae02SRob Clark #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000209d 3362bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 3363bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 3364bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 3365bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 3366bc00ae02SRob Clark { 3367bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 3368bc00ae02SRob Clark } 3369bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 3370bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 3371bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 3372bc00ae02SRob Clark { 3373bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 3374bc00ae02SRob Clark } 3375bc00ae02SRob Clark 33768a264743SRob Clark #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR 0x0000209e 33778a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE 0x80000000 33788a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK 0x00007fff 33798a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT 0 33808a264743SRob Clark static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val) 3381bc00ae02SRob Clark { 33828a264743SRob Clark return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK; 33838a264743SRob Clark } 33848a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK 0x7fff0000 33858a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT 16 33868a264743SRob Clark static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val) 33878a264743SRob Clark { 33888a264743SRob Clark return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK; 3389bc00ae02SRob Clark } 3390bc00ae02SRob Clark 33918a264743SRob Clark #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL 0x0000209f 33928a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE 0x80000000 33938a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK 0x00007fff 33948a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT 0 33958a264743SRob Clark static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val) 3396bc00ae02SRob Clark { 33978a264743SRob Clark return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK; 3398bc00ae02SRob Clark } 33998a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK 0x7fff0000 34008a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT 16 34018a264743SRob Clark static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val) 3402bc00ae02SRob Clark { 34038a264743SRob Clark return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK; 3404bc00ae02SRob Clark } 3405bc00ae02SRob Clark 3406bc00ae02SRob Clark #define REG_A4XX_UCHE_CACHE_MODE_CONTROL 0x00000e80 3407bc00ae02SRob Clark 3408bc00ae02SRob Clark #define REG_A4XX_UCHE_TRAP_BASE_LO 0x00000e83 3409bc00ae02SRob Clark 3410bc00ae02SRob Clark #define REG_A4XX_UCHE_TRAP_BASE_HI 0x00000e84 3411bc00ae02SRob Clark 3412bc00ae02SRob Clark #define REG_A4XX_UCHE_CACHE_STATUS 0x00000e88 3413bc00ae02SRob Clark 3414bc00ae02SRob Clark #define REG_A4XX_UCHE_INVALIDATE0 0x00000e8a 3415bc00ae02SRob Clark 3416bc00ae02SRob Clark #define REG_A4XX_UCHE_INVALIDATE1 0x00000e8b 3417bc00ae02SRob Clark 3418bc00ae02SRob Clark #define REG_A4XX_UCHE_CACHE_WAYS_VFD 0x00000e8c 3419bc00ae02SRob Clark 3420a2272e48SRob Clark #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e8e 3421a2272e48SRob Clark 3422a2272e48SRob Clark #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e8f 3423a2272e48SRob Clark 3424a2272e48SRob Clark #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e90 3425a2272e48SRob Clark 3426a2272e48SRob Clark #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e91 3427a2272e48SRob Clark 3428a2272e48SRob Clark #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e92 3429a2272e48SRob Clark 3430a2272e48SRob Clark #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e93 3431a2272e48SRob Clark 3432a2272e48SRob Clark #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e94 3433a2272e48SRob Clark 3434bc00ae02SRob Clark #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e95 3435bc00ae02SRob Clark 3436bc00ae02SRob Clark #define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD 0x00000e00 3437bc00ae02SRob Clark 3438bc00ae02SRob Clark #define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL 0x00000e04 3439bc00ae02SRob Clark 3440af6cb4c1SRob Clark #define REG_A4XX_HLSQ_MODE_CONTROL 0x00000e05 3441af6cb4c1SRob Clark 3442bc00ae02SRob Clark #define REG_A4XX_HLSQ_PERF_PIPE_MASK 0x00000e0e 3443bc00ae02SRob Clark 3444a2272e48SRob Clark #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e06 3445a2272e48SRob Clark 3446a2272e48SRob Clark #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e07 3447a2272e48SRob Clark 3448a2272e48SRob Clark #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e08 3449a2272e48SRob Clark 3450a2272e48SRob Clark #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e09 3451a2272e48SRob Clark 3452a2272e48SRob Clark #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e0a 3453a2272e48SRob Clark 3454a2272e48SRob Clark #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e0b 3455a2272e48SRob Clark 3456a2272e48SRob Clark #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e0c 3457a2272e48SRob Clark 3458a2272e48SRob Clark #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e0d 3459a2272e48SRob Clark 3460bc00ae02SRob Clark #define REG_A4XX_HLSQ_CONTROL_0_REG 0x000023c0 3461bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010 3462bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4 3463bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) 3464bc00ae02SRob Clark { 3465bc00ae02SRob Clark return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; 3466bc00ae02SRob Clark } 3467bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040 3468bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200 3469bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400 3470bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000 3471bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000 3472bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27 3473bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) 3474bc00ae02SRob Clark { 3475bc00ae02SRob Clark return ((val) << A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK; 3476bc00ae02SRob Clark } 3477bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000 3478bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000 3479bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000 3480bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000 3481bc00ae02SRob Clark 3482bc00ae02SRob Clark #define REG_A4XX_HLSQ_CONTROL_1_REG 0x000023c1 3483bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040 3484bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6 3485bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) 3486bc00ae02SRob Clark { 3487bc00ae02SRob Clark return ((val) << A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK; 3488bc00ae02SRob Clark } 3489bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100 3490bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200 34918a264743SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK 0x00ff0000 34928a264743SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT 16 34938a264743SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val) 34948a264743SRob Clark { 34958a264743SRob Clark return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK; 34968a264743SRob Clark } 3497af6cb4c1SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK 0xff000000 3498af6cb4c1SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT 24 3499af6cb4c1SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val) 3500af6cb4c1SRob Clark { 3501af6cb4c1SRob Clark return ((val) << A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK; 3502af6cb4c1SRob Clark } 3503bc00ae02SRob Clark 3504bc00ae02SRob Clark #define REG_A4XX_HLSQ_CONTROL_2_REG 0x000023c2 3505bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000 3506bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26 3507bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) 3508bc00ae02SRob Clark { 3509bc00ae02SRob Clark return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK; 3510bc00ae02SRob Clark } 35118a264743SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000003fc 35128a264743SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 2 35138a264743SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) 35148a264743SRob Clark { 35158a264743SRob Clark return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; 35168a264743SRob Clark } 3517af6cb4c1SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK 0x0003fc00 3518af6cb4c1SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT 10 3519af6cb4c1SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val) 3520af6cb4c1SRob Clark { 3521af6cb4c1SRob Clark return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK; 3522af6cb4c1SRob Clark } 3523af6cb4c1SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK 0x03fc0000 3524af6cb4c1SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT 18 3525af6cb4c1SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val) 3526af6cb4c1SRob Clark { 3527af6cb4c1SRob Clark return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK; 3528af6cb4c1SRob Clark } 3529bc00ae02SRob Clark 3530bc00ae02SRob Clark #define REG_A4XX_HLSQ_CONTROL_3_REG 0x000023c3 3531bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff 3532bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0 3533bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val) 3534bc00ae02SRob Clark { 3535bc00ae02SRob Clark return ((val) << A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_REGID__MASK; 3536bc00ae02SRob Clark } 3537bc00ae02SRob Clark 3538af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CONTROL_4_REG 0x000023c4 3539af6cb4c1SRob Clark 3540bc00ae02SRob Clark #define REG_A4XX_HLSQ_VS_CONTROL_REG 0x000023c5 3541bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 3542bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0 3543bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) 3544bc00ae02SRob Clark { 3545bc00ae02SRob Clark return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK; 3546bc00ae02SRob Clark } 3547bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 3548bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 3549bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3550bc00ae02SRob Clark { 3551bc00ae02SRob Clark return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3552bc00ae02SRob Clark } 3553af6cb4c1SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00010000 3554bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 3555bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 3556bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3557bc00ae02SRob Clark { 3558bc00ae02SRob Clark return ((val) << A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3559bc00ae02SRob Clark } 3560bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 3561bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24 3562bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) 3563bc00ae02SRob Clark { 3564bc00ae02SRob Clark return ((val) << A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK; 3565bc00ae02SRob Clark } 3566bc00ae02SRob Clark 3567bc00ae02SRob Clark #define REG_A4XX_HLSQ_FS_CONTROL_REG 0x000023c6 3568bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 3569bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0 3570bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) 3571bc00ae02SRob Clark { 3572bc00ae02SRob Clark return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK; 3573bc00ae02SRob Clark } 3574bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 3575bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 3576bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3577bc00ae02SRob Clark { 3578bc00ae02SRob Clark return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3579bc00ae02SRob Clark } 3580af6cb4c1SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00010000 3581bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 3582bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 3583bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3584bc00ae02SRob Clark { 3585bc00ae02SRob Clark return ((val) << A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3586bc00ae02SRob Clark } 3587bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 3588bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24 3589bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) 3590bc00ae02SRob Clark { 3591bc00ae02SRob Clark return ((val) << A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK; 3592bc00ae02SRob Clark } 3593bc00ae02SRob Clark 3594bc00ae02SRob Clark #define REG_A4XX_HLSQ_HS_CONTROL_REG 0x000023c7 3595bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 3596bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT 0 3597bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val) 3598bc00ae02SRob Clark { 3599bc00ae02SRob Clark return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK; 3600bc00ae02SRob Clark } 3601bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 3602bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 3603bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3604bc00ae02SRob Clark { 3605bc00ae02SRob Clark return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3606bc00ae02SRob Clark } 3607af6cb4c1SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00010000 3608bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 3609bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 3610bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3611bc00ae02SRob Clark { 3612bc00ae02SRob Clark return ((val) << A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3613bc00ae02SRob Clark } 3614bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 3615bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT 24 3616bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val) 3617bc00ae02SRob Clark { 3618bc00ae02SRob Clark return ((val) << A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK; 3619bc00ae02SRob Clark } 3620bc00ae02SRob Clark 3621bc00ae02SRob Clark #define REG_A4XX_HLSQ_DS_CONTROL_REG 0x000023c8 3622bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 3623bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT 0 3624bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val) 3625bc00ae02SRob Clark { 3626bc00ae02SRob Clark return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK; 3627bc00ae02SRob Clark } 3628bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 3629bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 3630bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3631bc00ae02SRob Clark { 3632bc00ae02SRob Clark return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3633bc00ae02SRob Clark } 3634af6cb4c1SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00010000 3635bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 3636bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 3637bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3638bc00ae02SRob Clark { 3639bc00ae02SRob Clark return ((val) << A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3640bc00ae02SRob Clark } 3641bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 3642bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT 24 3643bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val) 3644bc00ae02SRob Clark { 3645bc00ae02SRob Clark return ((val) << A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK; 3646bc00ae02SRob Clark } 3647bc00ae02SRob Clark 3648bc00ae02SRob Clark #define REG_A4XX_HLSQ_GS_CONTROL_REG 0x000023c9 3649bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 3650bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT 0 3651bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val) 3652bc00ae02SRob Clark { 3653bc00ae02SRob Clark return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK; 3654bc00ae02SRob Clark } 3655bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 3656bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 3657bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3658bc00ae02SRob Clark { 3659bc00ae02SRob Clark return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3660bc00ae02SRob Clark } 3661af6cb4c1SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00010000 3662bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 3663bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 3664bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3665bc00ae02SRob Clark { 3666bc00ae02SRob Clark return ((val) << A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3667bc00ae02SRob Clark } 3668bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 3669bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT 24 3670bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val) 3671bc00ae02SRob Clark { 3672bc00ae02SRob Clark return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK; 3673bc00ae02SRob Clark } 3674bc00ae02SRob Clark 3675af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CS_CONTROL 0x000023ca 3676af6cb4c1SRob Clark 3677af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_NDRANGE_0 0x000023cd 3678af6cb4c1SRob Clark 3679af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_NDRANGE_1 0x000023ce 3680af6cb4c1SRob Clark 3681af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_NDRANGE_2 0x000023cf 3682af6cb4c1SRob Clark 3683af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_NDRANGE_3 0x000023d0 3684af6cb4c1SRob Clark 3685af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_NDRANGE_4 0x000023d1 3686af6cb4c1SRob Clark 3687af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_NDRANGE_5 0x000023d2 3688af6cb4c1SRob Clark 3689af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_NDRANGE_6 0x000023d3 3690af6cb4c1SRob Clark 3691af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_CONTROL_0 0x000023d4 3692af6cb4c1SRob Clark 3693af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_CONTROL_1 0x000023d5 3694af6cb4c1SRob Clark 3695af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_KERNEL_CONST 0x000023d6 3696af6cb4c1SRob Clark 3697af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_X 0x000023d7 3698af6cb4c1SRob Clark 3699af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Y 0x000023d8 3700af6cb4c1SRob Clark 3701af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z 0x000023d9 3702af6cb4c1SRob Clark 3703af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_WG_OFFSET 0x000023da 3704af6cb4c1SRob Clark 3705bc00ae02SRob Clark #define REG_A4XX_HLSQ_UPDATE_CONTROL 0x000023db 3706bc00ae02SRob Clark 3707bc00ae02SRob Clark #define REG_A4XX_PC_BINNING_COMMAND 0x00000d00 3708bc00ae02SRob Clark #define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001 3709bc00ae02SRob Clark 3710a26ae754SRob Clark #define REG_A4XX_PC_TESSFACTOR_ADDR 0x00000d08 3711a26ae754SRob Clark 3712bc00ae02SRob Clark #define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c 3713bc00ae02SRob Clark 3714bc00ae02SRob Clark #define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10 3715bc00ae02SRob Clark 3716a2272e48SRob Clark #define REG_A4XX_PC_PERFCTR_PC_SEL_1 0x00000d11 3717a2272e48SRob Clark 3718a2272e48SRob Clark #define REG_A4XX_PC_PERFCTR_PC_SEL_2 0x00000d12 3719a2272e48SRob Clark 3720a2272e48SRob Clark #define REG_A4XX_PC_PERFCTR_PC_SEL_3 0x00000d13 3721a2272e48SRob Clark 3722a2272e48SRob Clark #define REG_A4XX_PC_PERFCTR_PC_SEL_4 0x00000d14 3723a2272e48SRob Clark 3724a2272e48SRob Clark #define REG_A4XX_PC_PERFCTR_PC_SEL_5 0x00000d15 3725a2272e48SRob Clark 3726a2272e48SRob Clark #define REG_A4XX_PC_PERFCTR_PC_SEL_6 0x00000d16 3727a2272e48SRob Clark 3728bc00ae02SRob Clark #define REG_A4XX_PC_PERFCTR_PC_SEL_7 0x00000d17 3729bc00ae02SRob Clark 3730bc00ae02SRob Clark #define REG_A4XX_PC_BIN_BASE 0x000021c0 3731bc00ae02SRob Clark 3732a26ae754SRob Clark #define REG_A4XX_PC_VSTREAM_CONTROL 0x000021c2 3733a26ae754SRob Clark #define A4XX_PC_VSTREAM_CONTROL_SIZE__MASK 0x003f0000 3734a26ae754SRob Clark #define A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT 16 3735a26ae754SRob Clark static inline uint32_t A4XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val) 3736a26ae754SRob Clark { 3737a26ae754SRob Clark return ((val) << A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A4XX_PC_VSTREAM_CONTROL_SIZE__MASK; 3738a26ae754SRob Clark } 3739a26ae754SRob Clark #define A4XX_PC_VSTREAM_CONTROL_N__MASK 0x07c00000 3740a26ae754SRob Clark #define A4XX_PC_VSTREAM_CONTROL_N__SHIFT 22 3741a26ae754SRob Clark static inline uint32_t A4XX_PC_VSTREAM_CONTROL_N(uint32_t val) 3742a26ae754SRob Clark { 3743a26ae754SRob Clark return ((val) << A4XX_PC_VSTREAM_CONTROL_N__SHIFT) & A4XX_PC_VSTREAM_CONTROL_N__MASK; 3744a26ae754SRob Clark } 3745a26ae754SRob Clark 3746bc00ae02SRob Clark #define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4 3747af6cb4c1SRob Clark #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK 0x0000000f 3748af6cb4c1SRob Clark #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT 0 3749af6cb4c1SRob Clark static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val) 3750af6cb4c1SRob Clark { 3751af6cb4c1SRob Clark return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK; 3752af6cb4c1SRob Clark } 3753af6cb4c1SRob Clark #define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000 3754bc00ae02SRob Clark #define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000 3755bc00ae02SRob Clark #define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000 3756bc00ae02SRob Clark 3757a2272e48SRob Clark #define REG_A4XX_PC_PRIM_VTX_CNTL2 0x000021c5 3758a2272e48SRob Clark #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK 0x00000007 3759a2272e48SRob Clark #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT 0 3760a2272e48SRob Clark static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 3761a2272e48SRob Clark { 3762a2272e48SRob Clark return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK; 3763a2272e48SRob Clark } 3764a2272e48SRob Clark #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK 0x00000038 3765a2272e48SRob Clark #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT 3 3766a2272e48SRob Clark static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 3767a2272e48SRob Clark { 3768a2272e48SRob Clark return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK; 3769a2272e48SRob Clark } 3770a2272e48SRob Clark #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_ENABLE 0x00000040 3771bc00ae02SRob Clark 3772bc00ae02SRob Clark #define REG_A4XX_PC_RESTART_INDEX 0x000021c6 3773bc00ae02SRob Clark 3774bc00ae02SRob Clark #define REG_A4XX_PC_GS_PARAM 0x000021e5 3775af6cb4c1SRob Clark #define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff 3776af6cb4c1SRob Clark #define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0 3777af6cb4c1SRob Clark static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val) 3778af6cb4c1SRob Clark { 3779af6cb4c1SRob Clark return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK; 3780af6cb4c1SRob Clark } 3781af6cb4c1SRob Clark #define A4XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800 3782af6cb4c1SRob Clark #define A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11 3783af6cb4c1SRob Clark static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val) 3784af6cb4c1SRob Clark { 3785af6cb4c1SRob Clark return ((val) << A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A4XX_PC_GS_PARAM_INVOCATIONS__MASK; 3786af6cb4c1SRob Clark } 3787af6cb4c1SRob Clark #define A4XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000 3788af6cb4c1SRob Clark #define A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23 3789af6cb4c1SRob Clark static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val) 3790af6cb4c1SRob Clark { 3791af6cb4c1SRob Clark return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK; 3792af6cb4c1SRob Clark } 3793af6cb4c1SRob Clark #define A4XX_PC_GS_PARAM_LAYER 0x80000000 3794bc00ae02SRob Clark 3795bc00ae02SRob Clark #define REG_A4XX_PC_HS_PARAM 0x000021e7 3796af6cb4c1SRob Clark #define A4XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f 3797af6cb4c1SRob Clark #define A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0 3798af6cb4c1SRob Clark static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val) 3799af6cb4c1SRob Clark { 3800af6cb4c1SRob Clark return ((val) << A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A4XX_PC_HS_PARAM_VERTICES_OUT__MASK; 3801af6cb4c1SRob Clark } 3802af6cb4c1SRob Clark #define A4XX_PC_HS_PARAM_SPACING__MASK 0x00600000 3803af6cb4c1SRob Clark #define A4XX_PC_HS_PARAM_SPACING__SHIFT 21 3804af6cb4c1SRob Clark static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val) 3805af6cb4c1SRob Clark { 3806af6cb4c1SRob Clark return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK; 3807af6cb4c1SRob Clark } 3808a26ae754SRob Clark #define A4XX_PC_HS_PARAM_CW 0x00800000 3809a26ae754SRob Clark #define A4XX_PC_HS_PARAM_CONNECTED 0x01000000 3810bc00ae02SRob Clark 3811bc00ae02SRob Clark #define REG_A4XX_VBIF_VERSION 0x00003000 3812bc00ae02SRob Clark 3813bc00ae02SRob Clark #define REG_A4XX_VBIF_CLKON 0x00003001 3814bc00ae02SRob Clark #define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000001 3815bc00ae02SRob Clark 3816bc00ae02SRob Clark #define REG_A4XX_VBIF_ABIT_SORT 0x0000301c 3817bc00ae02SRob Clark 3818bc00ae02SRob Clark #define REG_A4XX_VBIF_ABIT_SORT_CONF 0x0000301d 3819bc00ae02SRob Clark 3820bc00ae02SRob Clark #define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 3821bc00ae02SRob Clark 3822bc00ae02SRob Clark #define REG_A4XX_VBIF_IN_RD_LIM_CONF0 0x0000302c 3823bc00ae02SRob Clark 3824bc00ae02SRob Clark #define REG_A4XX_VBIF_IN_RD_LIM_CONF1 0x0000302d 3825bc00ae02SRob Clark 3826bc00ae02SRob Clark #define REG_A4XX_VBIF_IN_WR_LIM_CONF0 0x00003030 3827bc00ae02SRob Clark 3828bc00ae02SRob Clark #define REG_A4XX_VBIF_IN_WR_LIM_CONF1 0x00003031 3829bc00ae02SRob Clark 3830bc00ae02SRob Clark #define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049 3831bc00ae02SRob Clark 3832bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_0CC5 0x00000cc5 3833bc00ae02SRob Clark 3834bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_0CC6 0x00000cc6 3835bc00ae02SRob Clark 3836bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_0D01 0x00000d01 3837bc00ae02SRob Clark 3838bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_0E42 0x00000e42 3839bc00ae02SRob Clark 3840bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_0EC2 0x00000ec2 3841bc00ae02SRob Clark 3842bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2001 0x00002001 3843bc00ae02SRob Clark 3844bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_209B 0x0000209b 3845bc00ae02SRob Clark 3846bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_20EF 0x000020ef 3847bc00ae02SRob Clark 3848bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2152 0x00002152 3849bc00ae02SRob Clark 3850bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2153 0x00002153 3851bc00ae02SRob Clark 3852bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2154 0x00002154 3853bc00ae02SRob Clark 3854bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2155 0x00002155 3855bc00ae02SRob Clark 3856bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2156 0x00002156 3857bc00ae02SRob Clark 3858bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2157 0x00002157 3859bc00ae02SRob Clark 3860bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_21C3 0x000021c3 3861bc00ae02SRob Clark 3862bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_21E6 0x000021e6 3863bc00ae02SRob Clark 3864bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2209 0x00002209 3865bc00ae02SRob Clark 3866bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_22D7 0x000022d7 3867bc00ae02SRob Clark 38682d3584ebSRob Clark #define REG_A4XX_UNKNOWN_2352 0x00002352 38692d3584ebSRob Clark 3870bc00ae02SRob Clark #define REG_A4XX_TEX_SAMP_0 0x00000000 38718a264743SRob Clark #define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 3872bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 3873bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_XY_MAG__SHIFT 1 3874bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val) 3875bc00ae02SRob Clark { 3876bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_0_XY_MAG__SHIFT) & A4XX_TEX_SAMP_0_XY_MAG__MASK; 3877bc00ae02SRob Clark } 3878bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 3879bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_XY_MIN__SHIFT 3 3880bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val) 3881bc00ae02SRob Clark { 3882bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_0_XY_MIN__SHIFT) & A4XX_TEX_SAMP_0_XY_MIN__MASK; 3883bc00ae02SRob Clark } 3884bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 3885bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_S__SHIFT 5 3886bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val) 3887bc00ae02SRob Clark { 3888bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_0_WRAP_S__SHIFT) & A4XX_TEX_SAMP_0_WRAP_S__MASK; 3889bc00ae02SRob Clark } 3890bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 3891bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_T__SHIFT 8 3892bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val) 3893bc00ae02SRob Clark { 3894bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_0_WRAP_T__SHIFT) & A4XX_TEX_SAMP_0_WRAP_T__MASK; 3895bc00ae02SRob Clark } 3896bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 3897bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_R__SHIFT 11 3898bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val) 3899bc00ae02SRob Clark { 3900bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK; 3901bc00ae02SRob Clark } 3902af6cb4c1SRob Clark #define A4XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 3903af6cb4c1SRob Clark #define A4XX_TEX_SAMP_0_ANISO__SHIFT 14 3904af6cb4c1SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val) 3905af6cb4c1SRob Clark { 3906af6cb4c1SRob Clark return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK; 3907af6cb4c1SRob Clark } 3908a2272e48SRob Clark #define A4XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000 3909a2272e48SRob Clark #define A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19 3910a2272e48SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_LOD_BIAS(float val) 3911a2272e48SRob Clark { 3912a2272e48SRob Clark return ((((int32_t)(val * 256.0))) << A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A4XX_TEX_SAMP_0_LOD_BIAS__MASK; 3913a2272e48SRob Clark } 3914bc00ae02SRob Clark 3915bc00ae02SRob Clark #define REG_A4XX_TEX_SAMP_1 0x00000001 3916bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e 3917bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 3918bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) 3919bc00ae02SRob Clark { 3920bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK; 3921bc00ae02SRob Clark } 3922a2272e48SRob Clark #define A4XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010 39238a264743SRob Clark #define A4XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 39248a264743SRob Clark #define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 3925bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 3926bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 3927bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val) 3928bc00ae02SRob Clark { 39298a264743SRob Clark return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK; 3930bc00ae02SRob Clark } 3931bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 3932bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 3933bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val) 3934bc00ae02SRob Clark { 39358a264743SRob Clark return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK; 3936bc00ae02SRob Clark } 3937bc00ae02SRob Clark 3938bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_0 0x00000000 3939bc00ae02SRob Clark #define A4XX_TEX_CONST_0_TILED 0x00000001 3940af6cb4c1SRob Clark #define A4XX_TEX_CONST_0_SRGB 0x00000004 3941bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 3942bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_X__SHIFT 4 3943bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val) 3944bc00ae02SRob Clark { 3945bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) & A4XX_TEX_CONST_0_SWIZ_X__MASK; 3946bc00ae02SRob Clark } 3947bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 3948bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 3949bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val) 3950bc00ae02SRob Clark { 3951bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Y__MASK; 3952bc00ae02SRob Clark } 3953bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 3954bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 3955bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val) 3956bc00ae02SRob Clark { 3957bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Z__MASK; 3958bc00ae02SRob Clark } 3959bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 3960bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_W__SHIFT 13 3961bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val) 3962bc00ae02SRob Clark { 3963bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK; 3964bc00ae02SRob Clark } 39658a264743SRob Clark #define A4XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 39668a264743SRob Clark #define A4XX_TEX_CONST_0_MIPLVLS__SHIFT 16 39678a264743SRob Clark static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val) 39688a264743SRob Clark { 39698a264743SRob Clark return ((val) << A4XX_TEX_CONST_0_MIPLVLS__SHIFT) & A4XX_TEX_CONST_0_MIPLVLS__MASK; 39708a264743SRob Clark } 3971bc00ae02SRob Clark #define A4XX_TEX_CONST_0_FMT__MASK 0x1fc00000 3972bc00ae02SRob Clark #define A4XX_TEX_CONST_0_FMT__SHIFT 22 3973bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val) 3974bc00ae02SRob Clark { 3975bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK; 3976bc00ae02SRob Clark } 3977bc00ae02SRob Clark #define A4XX_TEX_CONST_0_TYPE__MASK 0x60000000 3978bc00ae02SRob Clark #define A4XX_TEX_CONST_0_TYPE__SHIFT 29 3979bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val) 3980bc00ae02SRob Clark { 3981bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_TYPE__SHIFT) & A4XX_TEX_CONST_0_TYPE__MASK; 3982bc00ae02SRob Clark } 3983bc00ae02SRob Clark 3984bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_1 0x00000001 3985bc00ae02SRob Clark #define A4XX_TEX_CONST_1_HEIGHT__MASK 0x00007fff 3986bc00ae02SRob Clark #define A4XX_TEX_CONST_1_HEIGHT__SHIFT 0 3987bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val) 3988bc00ae02SRob Clark { 3989bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK; 3990bc00ae02SRob Clark } 3991a2272e48SRob Clark #define A4XX_TEX_CONST_1_WIDTH__MASK 0x3fff8000 3992bc00ae02SRob Clark #define A4XX_TEX_CONST_1_WIDTH__SHIFT 15 3993bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val) 3994bc00ae02SRob Clark { 3995bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK; 3996bc00ae02SRob Clark } 3997bc00ae02SRob Clark 3998bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_2 0x00000002 39998a264743SRob Clark #define A4XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f 40008a264743SRob Clark #define A4XX_TEX_CONST_2_FETCHSIZE__SHIFT 0 40018a264743SRob Clark static inline uint32_t A4XX_TEX_CONST_2_FETCHSIZE(enum a4xx_tex_fetchsize val) 40028a264743SRob Clark { 40038a264743SRob Clark return ((val) << A4XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A4XX_TEX_CONST_2_FETCHSIZE__MASK; 40048a264743SRob Clark } 4005bc00ae02SRob Clark #define A4XX_TEX_CONST_2_PITCH__MASK 0x3ffffe00 4006bc00ae02SRob Clark #define A4XX_TEX_CONST_2_PITCH__SHIFT 9 4007bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val) 4008bc00ae02SRob Clark { 4009bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) & A4XX_TEX_CONST_2_PITCH__MASK; 4010bc00ae02SRob Clark } 4011bc00ae02SRob Clark #define A4XX_TEX_CONST_2_SWAP__MASK 0xc0000000 4012bc00ae02SRob Clark #define A4XX_TEX_CONST_2_SWAP__SHIFT 30 4013bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) 4014bc00ae02SRob Clark { 4015bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_2_SWAP__SHIFT) & A4XX_TEX_CONST_2_SWAP__MASK; 4016bc00ae02SRob Clark } 4017bc00ae02SRob Clark 4018bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_3 0x00000003 40198a264743SRob Clark #define A4XX_TEX_CONST_3_LAYERSZ__MASK 0x00003fff 4020bc00ae02SRob Clark #define A4XX_TEX_CONST_3_LAYERSZ__SHIFT 0 4021bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val) 4022bc00ae02SRob Clark { 4023bc00ae02SRob Clark return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK; 4024bc00ae02SRob Clark } 40258a264743SRob Clark #define A4XX_TEX_CONST_3_DEPTH__MASK 0x7ffc0000 40268a264743SRob Clark #define A4XX_TEX_CONST_3_DEPTH__SHIFT 18 40278a264743SRob Clark static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val) 40288a264743SRob Clark { 40298a264743SRob Clark return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK; 40308a264743SRob Clark } 4031bc00ae02SRob Clark 4032bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_4 0x00000004 40338a264743SRob Clark #define A4XX_TEX_CONST_4_LAYERSZ__MASK 0x0000000f 40348a264743SRob Clark #define A4XX_TEX_CONST_4_LAYERSZ__SHIFT 0 40358a264743SRob Clark static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val) 40368a264743SRob Clark { 40378a264743SRob Clark return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK; 40388a264743SRob Clark } 40398a264743SRob Clark #define A4XX_TEX_CONST_4_BASE__MASK 0xffffffe0 40408a264743SRob Clark #define A4XX_TEX_CONST_4_BASE__SHIFT 5 4041bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val) 4042bc00ae02SRob Clark { 40438a264743SRob Clark return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK; 4044bc00ae02SRob Clark } 4045bc00ae02SRob Clark 4046bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_5 0x00000005 4047bc00ae02SRob Clark 4048bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_6 0x00000006 4049bc00ae02SRob Clark 4050bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_7 0x00000007 4051bc00ae02SRob Clark 4052bc00ae02SRob Clark 4053bc00ae02SRob Clark #endif /* A4XX_XML */ 4054