1bc00ae02SRob Clark #ifndef A4XX_XML 2bc00ae02SRob Clark #define A4XX_XML 3bc00ae02SRob Clark 4bc00ae02SRob Clark /* Autogenerated file, DO NOT EDIT manually! 5bc00ae02SRob Clark 6bc00ae02SRob Clark This file was generated by the rules-ng-ng headergen tool in this git repository: 7bc00ae02SRob Clark http://github.com/freedreno/envytools/ 8bc00ae02SRob Clark git clone https://github.com/freedreno/envytools.git 9bc00ae02SRob Clark 10bc00ae02SRob Clark The rules-ng-ng source files this header was generated from are: 118217e97aSRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31) 12a2272e48SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) 132d3584ebSRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) 14a2272e48SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25) 15a2272e48SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31) 16a2272e48SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21) 17a2272e48SRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109916 bytes, from 2016-02-20 18:44:48) 188217e97aSRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) 19bc00ae02SRob Clark 20a2272e48SRob Clark Copyright (C) 2013-2016 by the following authors: 21bc00ae02SRob Clark - Rob Clark <robdclark@gmail.com> (robclark) 22a2272e48SRob Clark - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 23bc00ae02SRob Clark 24bc00ae02SRob Clark Permission is hereby granted, free of charge, to any person obtaining 25bc00ae02SRob Clark a copy of this software and associated documentation files (the 26bc00ae02SRob Clark "Software"), to deal in the Software without restriction, including 27bc00ae02SRob Clark without limitation the rights to use, copy, modify, merge, publish, 28bc00ae02SRob Clark distribute, sublicense, and/or sell copies of the Software, and to 29bc00ae02SRob Clark permit persons to whom the Software is furnished to do so, subject to 30bc00ae02SRob Clark the following conditions: 31bc00ae02SRob Clark 32bc00ae02SRob Clark The above copyright notice and this permission notice (including the 33bc00ae02SRob Clark next paragraph) shall be included in all copies or substantial 34bc00ae02SRob Clark portions of the Software. 35bc00ae02SRob Clark 36bc00ae02SRob Clark THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 37bc00ae02SRob Clark EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 38bc00ae02SRob Clark MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 39bc00ae02SRob Clark IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 40bc00ae02SRob Clark LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 41bc00ae02SRob Clark OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 42bc00ae02SRob Clark WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 43bc00ae02SRob Clark */ 44bc00ae02SRob Clark 45bc00ae02SRob Clark 46bc00ae02SRob Clark enum a4xx_color_fmt { 47bc00ae02SRob Clark RB4_A8_UNORM = 1, 48af6cb4c1SRob Clark RB4_R8_UNORM = 2, 49af6cb4c1SRob Clark RB4_R4G4B4A4_UNORM = 8, 50af6cb4c1SRob Clark RB4_R5G5B5A1_UNORM = 10, 51a2272e48SRob Clark RB4_R5G6B5_UNORM = 14, 52af6cb4c1SRob Clark RB4_R8G8_UNORM = 15, 53af6cb4c1SRob Clark RB4_R8G8_SNORM = 16, 54af6cb4c1SRob Clark RB4_R8G8_UINT = 17, 55af6cb4c1SRob Clark RB4_R8G8_SINT = 18, 56a2272e48SRob Clark RB4_R16_UNORM = 19, 57a2272e48SRob Clark RB4_R16_SNORM = 20, 58af6cb4c1SRob Clark RB4_R16_FLOAT = 21, 59af6cb4c1SRob Clark RB4_R16_UINT = 22, 60af6cb4c1SRob Clark RB4_R16_SINT = 23, 61bc00ae02SRob Clark RB4_R8G8B8_UNORM = 25, 62bc00ae02SRob Clark RB4_R8G8B8A8_UNORM = 26, 63af6cb4c1SRob Clark RB4_R8G8B8A8_SNORM = 28, 64af6cb4c1SRob Clark RB4_R8G8B8A8_UINT = 29, 65af6cb4c1SRob Clark RB4_R8G8B8A8_SINT = 30, 66af6cb4c1SRob Clark RB4_R10G10B10A2_UNORM = 31, 67af6cb4c1SRob Clark RB4_R10G10B10A2_UINT = 34, 68af6cb4c1SRob Clark RB4_R11G11B10_FLOAT = 39, 69a2272e48SRob Clark RB4_R16G16_UNORM = 40, 70a2272e48SRob Clark RB4_R16G16_SNORM = 41, 71af6cb4c1SRob Clark RB4_R16G16_FLOAT = 42, 72af6cb4c1SRob Clark RB4_R16G16_UINT = 43, 73af6cb4c1SRob Clark RB4_R16G16_SINT = 44, 74af6cb4c1SRob Clark RB4_R32_FLOAT = 45, 75af6cb4c1SRob Clark RB4_R32_UINT = 46, 76af6cb4c1SRob Clark RB4_R32_SINT = 47, 77a2272e48SRob Clark RB4_R16G16B16A16_UNORM = 52, 78a2272e48SRob Clark RB4_R16G16B16A16_SNORM = 53, 79af6cb4c1SRob Clark RB4_R16G16B16A16_FLOAT = 54, 80af6cb4c1SRob Clark RB4_R16G16B16A16_UINT = 55, 81af6cb4c1SRob Clark RB4_R16G16B16A16_SINT = 56, 82af6cb4c1SRob Clark RB4_R32G32_FLOAT = 57, 83af6cb4c1SRob Clark RB4_R32G32_UINT = 58, 84af6cb4c1SRob Clark RB4_R32G32_SINT = 59, 85af6cb4c1SRob Clark RB4_R32G32B32A32_FLOAT = 60, 86af6cb4c1SRob Clark RB4_R32G32B32A32_UINT = 61, 87af6cb4c1SRob Clark RB4_R32G32B32A32_SINT = 62, 88bc00ae02SRob Clark }; 89bc00ae02SRob Clark 90bc00ae02SRob Clark enum a4xx_tile_mode { 91bc00ae02SRob Clark TILE4_LINEAR = 0, 92bc00ae02SRob Clark TILE4_3 = 3, 93bc00ae02SRob Clark }; 94bc00ae02SRob Clark 95bc00ae02SRob Clark enum a4xx_rb_blend_opcode { 96bc00ae02SRob Clark BLEND_DST_PLUS_SRC = 0, 97bc00ae02SRob Clark BLEND_SRC_MINUS_DST = 1, 98bc00ae02SRob Clark BLEND_DST_MINUS_SRC = 2, 99bc00ae02SRob Clark BLEND_MIN_DST_SRC = 3, 100bc00ae02SRob Clark BLEND_MAX_DST_SRC = 4, 101bc00ae02SRob Clark }; 102bc00ae02SRob Clark 103bc00ae02SRob Clark enum a4xx_vtx_fmt { 1048a264743SRob Clark VFMT4_32_FLOAT = 1, 1058a264743SRob Clark VFMT4_32_32_FLOAT = 2, 1068a264743SRob Clark VFMT4_32_32_32_FLOAT = 3, 1078a264743SRob Clark VFMT4_32_32_32_32_FLOAT = 4, 1088a264743SRob Clark VFMT4_16_FLOAT = 5, 1098a264743SRob Clark VFMT4_16_16_FLOAT = 6, 1108a264743SRob Clark VFMT4_16_16_16_FLOAT = 7, 1118a264743SRob Clark VFMT4_16_16_16_16_FLOAT = 8, 1128a264743SRob Clark VFMT4_32_FIXED = 9, 1138a264743SRob Clark VFMT4_32_32_FIXED = 10, 1148a264743SRob Clark VFMT4_32_32_32_FIXED = 11, 1158a264743SRob Clark VFMT4_32_32_32_32_FIXED = 12, 116a2272e48SRob Clark VFMT4_11_11_10_FLOAT = 13, 1178a264743SRob Clark VFMT4_16_SINT = 16, 1188a264743SRob Clark VFMT4_16_16_SINT = 17, 1198a264743SRob Clark VFMT4_16_16_16_SINT = 18, 1208a264743SRob Clark VFMT4_16_16_16_16_SINT = 19, 1218a264743SRob Clark VFMT4_16_UINT = 20, 1228a264743SRob Clark VFMT4_16_16_UINT = 21, 1238a264743SRob Clark VFMT4_16_16_16_UINT = 22, 1248a264743SRob Clark VFMT4_16_16_16_16_UINT = 23, 1258a264743SRob Clark VFMT4_16_SNORM = 24, 1268a264743SRob Clark VFMT4_16_16_SNORM = 25, 1278a264743SRob Clark VFMT4_16_16_16_SNORM = 26, 1288a264743SRob Clark VFMT4_16_16_16_16_SNORM = 27, 1298a264743SRob Clark VFMT4_16_UNORM = 28, 1308a264743SRob Clark VFMT4_16_16_UNORM = 29, 1318a264743SRob Clark VFMT4_16_16_16_UNORM = 30, 1328a264743SRob Clark VFMT4_16_16_16_16_UNORM = 31, 133af6cb4c1SRob Clark VFMT4_32_UINT = 32, 134af6cb4c1SRob Clark VFMT4_32_32_UINT = 33, 135af6cb4c1SRob Clark VFMT4_32_32_32_UINT = 34, 136af6cb4c1SRob Clark VFMT4_32_32_32_32_UINT = 35, 137af6cb4c1SRob Clark VFMT4_32_SINT = 36, 1388a264743SRob Clark VFMT4_32_32_SINT = 37, 139af6cb4c1SRob Clark VFMT4_32_32_32_SINT = 38, 140af6cb4c1SRob Clark VFMT4_32_32_32_32_SINT = 39, 1418a264743SRob Clark VFMT4_8_UINT = 40, 1428a264743SRob Clark VFMT4_8_8_UINT = 41, 1438a264743SRob Clark VFMT4_8_8_8_UINT = 42, 1448a264743SRob Clark VFMT4_8_8_8_8_UINT = 43, 1458a264743SRob Clark VFMT4_8_UNORM = 44, 1468a264743SRob Clark VFMT4_8_8_UNORM = 45, 1478a264743SRob Clark VFMT4_8_8_8_UNORM = 46, 1488a264743SRob Clark VFMT4_8_8_8_8_UNORM = 47, 1498a264743SRob Clark VFMT4_8_SINT = 48, 1508a264743SRob Clark VFMT4_8_8_SINT = 49, 1518a264743SRob Clark VFMT4_8_8_8_SINT = 50, 1528a264743SRob Clark VFMT4_8_8_8_8_SINT = 51, 1538a264743SRob Clark VFMT4_8_SNORM = 52, 1548a264743SRob Clark VFMT4_8_8_SNORM = 53, 1558a264743SRob Clark VFMT4_8_8_8_SNORM = 54, 1568a264743SRob Clark VFMT4_8_8_8_8_SNORM = 55, 157a2272e48SRob Clark VFMT4_10_10_10_2_UINT = 56, 158a2272e48SRob Clark VFMT4_10_10_10_2_UNORM = 57, 159a2272e48SRob Clark VFMT4_10_10_10_2_SINT = 58, 160a2272e48SRob Clark VFMT4_10_10_10_2_SNORM = 59, 161a2272e48SRob Clark VFMT4_2_10_10_10_UINT = 60, 162a2272e48SRob Clark VFMT4_2_10_10_10_UNORM = 61, 163a2272e48SRob Clark VFMT4_2_10_10_10_SINT = 62, 164a2272e48SRob Clark VFMT4_2_10_10_10_SNORM = 63, 165bc00ae02SRob Clark }; 166bc00ae02SRob Clark 167bc00ae02SRob Clark enum a4xx_tex_fmt { 1688a264743SRob Clark TFMT4_A8_UNORM = 3, 1698a264743SRob Clark TFMT4_8_UNORM = 4, 1708217e97aSRob Clark TFMT4_8_SNORM = 5, 1718217e97aSRob Clark TFMT4_8_UINT = 6, 1728217e97aSRob Clark TFMT4_8_SINT = 7, 173a2272e48SRob Clark TFMT4_4_4_4_4_UNORM = 8, 174a2272e48SRob Clark TFMT4_5_5_5_1_UNORM = 9, 175a2272e48SRob Clark TFMT4_5_6_5_UNORM = 11, 176a2272e48SRob Clark TFMT4_L8_A8_UNORM = 13, 177a2272e48SRob Clark TFMT4_8_8_UNORM = 14, 178a2272e48SRob Clark TFMT4_8_8_SNORM = 15, 179a2272e48SRob Clark TFMT4_8_8_UINT = 16, 180af6cb4c1SRob Clark TFMT4_8_8_SINT = 17, 181a2272e48SRob Clark TFMT4_16_UNORM = 18, 182a2272e48SRob Clark TFMT4_16_SNORM = 19, 1838a264743SRob Clark TFMT4_16_FLOAT = 20, 184a2272e48SRob Clark TFMT4_16_UINT = 21, 185a2272e48SRob Clark TFMT4_16_SINT = 22, 186a2272e48SRob Clark TFMT4_8_8_8_8_UNORM = 28, 187a2272e48SRob Clark TFMT4_8_8_8_8_SNORM = 29, 188a2272e48SRob Clark TFMT4_8_8_8_8_UINT = 30, 189a2272e48SRob Clark TFMT4_8_8_8_8_SINT = 31, 190af6cb4c1SRob Clark TFMT4_9_9_9_E5_FLOAT = 32, 191a2272e48SRob Clark TFMT4_10_10_10_2_UNORM = 33, 192a2272e48SRob Clark TFMT4_10_10_10_2_UINT = 34, 193af6cb4c1SRob Clark TFMT4_11_11_10_FLOAT = 37, 194a2272e48SRob Clark TFMT4_16_16_UNORM = 38, 195a2272e48SRob Clark TFMT4_16_16_SNORM = 39, 196a2272e48SRob Clark TFMT4_16_16_FLOAT = 40, 197a2272e48SRob Clark TFMT4_16_16_UINT = 41, 198a2272e48SRob Clark TFMT4_16_16_SINT = 42, 199a2272e48SRob Clark TFMT4_32_FLOAT = 43, 200a2272e48SRob Clark TFMT4_32_UINT = 44, 201a2272e48SRob Clark TFMT4_32_SINT = 45, 202a2272e48SRob Clark TFMT4_16_16_16_16_UNORM = 51, 203a2272e48SRob Clark TFMT4_16_16_16_16_SNORM = 52, 204a2272e48SRob Clark TFMT4_16_16_16_16_FLOAT = 53, 205a2272e48SRob Clark TFMT4_16_16_16_16_UINT = 54, 206a2272e48SRob Clark TFMT4_16_16_16_16_SINT = 55, 207a2272e48SRob Clark TFMT4_32_32_FLOAT = 56, 208a2272e48SRob Clark TFMT4_32_32_UINT = 57, 209a2272e48SRob Clark TFMT4_32_32_SINT = 58, 210a2272e48SRob Clark TFMT4_32_32_32_FLOAT = 59, 211a2272e48SRob Clark TFMT4_32_32_32_UINT = 60, 212a2272e48SRob Clark TFMT4_32_32_32_SINT = 61, 213a2272e48SRob Clark TFMT4_32_32_32_32_FLOAT = 63, 214a2272e48SRob Clark TFMT4_32_32_32_32_UINT = 64, 215a2272e48SRob Clark TFMT4_32_32_32_32_SINT = 65, 216a2272e48SRob Clark TFMT4_X8Z24_UNORM = 71, 217a2272e48SRob Clark TFMT4_DXT1 = 86, 218a2272e48SRob Clark TFMT4_DXT3 = 87, 219a2272e48SRob Clark TFMT4_DXT5 = 88, 220a2272e48SRob Clark TFMT4_RGTC1_UNORM = 90, 221a2272e48SRob Clark TFMT4_RGTC1_SNORM = 91, 222a2272e48SRob Clark TFMT4_RGTC2_UNORM = 94, 223a2272e48SRob Clark TFMT4_RGTC2_SNORM = 95, 224a2272e48SRob Clark TFMT4_BPTC_UFLOAT = 97, 225a2272e48SRob Clark TFMT4_BPTC_FLOAT = 98, 226a2272e48SRob Clark TFMT4_BPTC = 99, 227af6cb4c1SRob Clark TFMT4_ATC_RGB = 100, 228af6cb4c1SRob Clark TFMT4_ATC_RGBA_EXPLICIT = 101, 229af6cb4c1SRob Clark TFMT4_ATC_RGBA_INTERPOLATED = 102, 230af6cb4c1SRob Clark TFMT4_ETC2_RG11_UNORM = 103, 231af6cb4c1SRob Clark TFMT4_ETC2_RG11_SNORM = 104, 232af6cb4c1SRob Clark TFMT4_ETC2_R11_UNORM = 105, 233af6cb4c1SRob Clark TFMT4_ETC2_R11_SNORM = 106, 234af6cb4c1SRob Clark TFMT4_ETC1 = 107, 235af6cb4c1SRob Clark TFMT4_ETC2_RGB8 = 108, 236af6cb4c1SRob Clark TFMT4_ETC2_RGBA8 = 109, 237af6cb4c1SRob Clark TFMT4_ETC2_RGB8A1 = 110, 238af6cb4c1SRob Clark TFMT4_ASTC_4x4 = 111, 239af6cb4c1SRob Clark TFMT4_ASTC_5x4 = 112, 240af6cb4c1SRob Clark TFMT4_ASTC_5x5 = 113, 241af6cb4c1SRob Clark TFMT4_ASTC_6x5 = 114, 242af6cb4c1SRob Clark TFMT4_ASTC_6x6 = 115, 243af6cb4c1SRob Clark TFMT4_ASTC_8x5 = 116, 244af6cb4c1SRob Clark TFMT4_ASTC_8x6 = 117, 245af6cb4c1SRob Clark TFMT4_ASTC_8x8 = 118, 246af6cb4c1SRob Clark TFMT4_ASTC_10x5 = 119, 247af6cb4c1SRob Clark TFMT4_ASTC_10x6 = 120, 248af6cb4c1SRob Clark TFMT4_ASTC_10x8 = 121, 249af6cb4c1SRob Clark TFMT4_ASTC_10x10 = 122, 250af6cb4c1SRob Clark TFMT4_ASTC_12x10 = 123, 251af6cb4c1SRob Clark TFMT4_ASTC_12x12 = 124, 2528a264743SRob Clark }; 2538a264743SRob Clark 2548a264743SRob Clark enum a4xx_tex_fetchsize { 2558a264743SRob Clark TFETCH4_1_BYTE = 0, 2568a264743SRob Clark TFETCH4_2_BYTE = 1, 2578a264743SRob Clark TFETCH4_4_BYTE = 2, 2588a264743SRob Clark TFETCH4_8_BYTE = 3, 2598a264743SRob Clark TFETCH4_16_BYTE = 4, 260bc00ae02SRob Clark }; 261bc00ae02SRob Clark 262bc00ae02SRob Clark enum a4xx_depth_format { 263bc00ae02SRob Clark DEPTH4_NONE = 0, 264bc00ae02SRob Clark DEPTH4_16 = 1, 265bc00ae02SRob Clark DEPTH4_24_8 = 2, 2662d3584ebSRob Clark DEPTH4_32 = 3, 267bc00ae02SRob Clark }; 268bc00ae02SRob Clark 269af6cb4c1SRob Clark enum a4xx_tess_spacing { 270af6cb4c1SRob Clark EQUAL_SPACING = 0, 271af6cb4c1SRob Clark ODD_SPACING = 2, 272af6cb4c1SRob Clark EVEN_SPACING = 3, 273af6cb4c1SRob Clark }; 274af6cb4c1SRob Clark 275a2272e48SRob Clark enum a4xx_ccu_perfcounter_select { 276a2272e48SRob Clark CCU_BUSY_CYCLES = 0, 277a2272e48SRob Clark CCU_RB_DEPTH_RETURN_STALL = 2, 278a2272e48SRob Clark CCU_RB_COLOR_RETURN_STALL = 3, 279a2272e48SRob Clark CCU_DEPTH_BLOCKS = 6, 280a2272e48SRob Clark CCU_COLOR_BLOCKS = 7, 281a2272e48SRob Clark CCU_DEPTH_BLOCK_HIT = 8, 282a2272e48SRob Clark CCU_COLOR_BLOCK_HIT = 9, 283a2272e48SRob Clark CCU_DEPTH_FLAG1_COUNT = 10, 284a2272e48SRob Clark CCU_DEPTH_FLAG2_COUNT = 11, 285a2272e48SRob Clark CCU_DEPTH_FLAG3_COUNT = 12, 286a2272e48SRob Clark CCU_DEPTH_FLAG4_COUNT = 13, 287a2272e48SRob Clark CCU_COLOR_FLAG1_COUNT = 14, 288a2272e48SRob Clark CCU_COLOR_FLAG2_COUNT = 15, 289a2272e48SRob Clark CCU_COLOR_FLAG3_COUNT = 16, 290a2272e48SRob Clark CCU_COLOR_FLAG4_COUNT = 17, 291a2272e48SRob Clark CCU_PARTIAL_BLOCK_READ = 18, 292a2272e48SRob Clark }; 293a2272e48SRob Clark 294a2272e48SRob Clark enum a4xx_cp_perfcounter_select { 295a2272e48SRob Clark CP_ALWAYS_COUNT = 0, 296a2272e48SRob Clark CP_BUSY = 1, 297a2272e48SRob Clark CP_PFP_IDLE = 2, 298a2272e48SRob Clark CP_PFP_BUSY_WORKING = 3, 299a2272e48SRob Clark CP_PFP_STALL_CYCLES_ANY = 4, 300a2272e48SRob Clark CP_PFP_STARVE_CYCLES_ANY = 5, 301a2272e48SRob Clark CP_PFP_STARVED_PER_LOAD_ADDR = 6, 302a2272e48SRob Clark CP_PFP_STALLED_PER_STORE_ADDR = 7, 303a2272e48SRob Clark CP_PFP_PC_PROFILE = 8, 304a2272e48SRob Clark CP_PFP_MATCH_PM4_PKT_PROFILE = 9, 305a2272e48SRob Clark CP_PFP_COND_INDIRECT_DISCARDED = 10, 306a2272e48SRob Clark CP_LONG_RESUMPTIONS = 11, 307a2272e48SRob Clark CP_RESUME_CYCLES = 12, 308a2272e48SRob Clark CP_RESUME_TO_BOUNDARY_CYCLES = 13, 309a2272e48SRob Clark CP_LONG_PREEMPTIONS = 14, 310a2272e48SRob Clark CP_PREEMPT_CYCLES = 15, 311a2272e48SRob Clark CP_PREEMPT_TO_BOUNDARY_CYCLES = 16, 312a2272e48SRob Clark CP_ME_FIFO_EMPTY_PFP_IDLE = 17, 313a2272e48SRob Clark CP_ME_FIFO_EMPTY_PFP_BUSY = 18, 314a2272e48SRob Clark CP_ME_FIFO_NOT_EMPTY_NOT_FULL = 19, 315a2272e48SRob Clark CP_ME_FIFO_FULL_ME_BUSY = 20, 316a2272e48SRob Clark CP_ME_FIFO_FULL_ME_NON_WORKING = 21, 317a2272e48SRob Clark CP_ME_WAITING_FOR_PACKETS = 22, 318a2272e48SRob Clark CP_ME_BUSY_WORKING = 23, 319a2272e48SRob Clark CP_ME_STARVE_CYCLES_ANY = 24, 320a2272e48SRob Clark CP_ME_STARVE_CYCLES_PER_PROFILE = 25, 321a2272e48SRob Clark CP_ME_STALL_CYCLES_PER_PROFILE = 26, 322a2272e48SRob Clark CP_ME_PC_PROFILE = 27, 323a2272e48SRob Clark CP_RCIU_FIFO_EMPTY = 28, 324a2272e48SRob Clark CP_RCIU_FIFO_NOT_EMPTY_NOT_FULL = 29, 325a2272e48SRob Clark CP_RCIU_FIFO_FULL = 30, 326a2272e48SRob Clark CP_RCIU_FIFO_FULL_NO_CONTEXT = 31, 327a2272e48SRob Clark CP_RCIU_FIFO_FULL_AHB_MASTER = 32, 328a2272e48SRob Clark CP_RCIU_FIFO_FULL_OTHER = 33, 329a2272e48SRob Clark CP_AHB_IDLE = 34, 330a2272e48SRob Clark CP_AHB_STALL_ON_GRANT_NO_SPLIT = 35, 331a2272e48SRob Clark CP_AHB_STALL_ON_GRANT_SPLIT = 36, 332a2272e48SRob Clark CP_AHB_STALL_ON_GRANT_SPLIT_PROFILE = 37, 333a2272e48SRob Clark CP_AHB_BUSY_WORKING = 38, 334a2272e48SRob Clark CP_AHB_BUSY_STALL_ON_HRDY = 39, 335a2272e48SRob Clark CP_AHB_BUSY_STALL_ON_HRDY_PROFILE = 40, 336a2272e48SRob Clark }; 337a2272e48SRob Clark 338a2272e48SRob Clark enum a4xx_gras_ras_perfcounter_select { 339a2272e48SRob Clark RAS_SUPER_TILES = 0, 340a2272e48SRob Clark RAS_8X8_TILES = 1, 341a2272e48SRob Clark RAS_4X4_TILES = 2, 342a2272e48SRob Clark RAS_BUSY_CYCLES = 3, 343a2272e48SRob Clark RAS_STALL_CYCLES_BY_RB = 4, 344a2272e48SRob Clark RAS_STALL_CYCLES_BY_VSC = 5, 345a2272e48SRob Clark RAS_STARVE_CYCLES_BY_TSE = 6, 346a2272e48SRob Clark RAS_SUPERTILE_CYCLES = 7, 347a2272e48SRob Clark RAS_TILE_CYCLES = 8, 348a2272e48SRob Clark RAS_FULLY_COVERED_SUPER_TILES = 9, 349a2272e48SRob Clark RAS_FULLY_COVERED_8X8_TILES = 10, 350a2272e48SRob Clark RAS_4X4_PRIM = 11, 351a2272e48SRob Clark RAS_8X4_4X8_PRIM = 12, 352a2272e48SRob Clark RAS_8X8_PRIM = 13, 353a2272e48SRob Clark }; 354a2272e48SRob Clark 355a2272e48SRob Clark enum a4xx_gras_tse_perfcounter_select { 356a2272e48SRob Clark TSE_INPUT_PRIM = 0, 357a2272e48SRob Clark TSE_INPUT_NULL_PRIM = 1, 358a2272e48SRob Clark TSE_TRIVAL_REJ_PRIM = 2, 359a2272e48SRob Clark TSE_CLIPPED_PRIM = 3, 360a2272e48SRob Clark TSE_NEW_PRIM = 4, 361a2272e48SRob Clark TSE_ZERO_AREA_PRIM = 5, 362a2272e48SRob Clark TSE_FACENESS_CULLED_PRIM = 6, 363a2272e48SRob Clark TSE_ZERO_PIXEL_PRIM = 7, 364a2272e48SRob Clark TSE_OUTPUT_NULL_PRIM = 8, 365a2272e48SRob Clark TSE_OUTPUT_VISIBLE_PRIM = 9, 366a2272e48SRob Clark TSE_PRE_CLIP_PRIM = 10, 367a2272e48SRob Clark TSE_POST_CLIP_PRIM = 11, 368a2272e48SRob Clark TSE_BUSY_CYCLES = 12, 369a2272e48SRob Clark TSE_PC_STARVE = 13, 370a2272e48SRob Clark TSE_RAS_STALL = 14, 371a2272e48SRob Clark TSE_STALL_BARYPLANE_FIFO_FULL = 15, 372a2272e48SRob Clark TSE_STALL_ZPLANE_FIFO_FULL = 16, 373a2272e48SRob Clark }; 374a2272e48SRob Clark 375a2272e48SRob Clark enum a4xx_hlsq_perfcounter_select { 376a2272e48SRob Clark HLSQ_SP_VS_STAGE_CONSTANT = 0, 377a2272e48SRob Clark HLSQ_SP_VS_STAGE_INSTRUCTIONS = 1, 378a2272e48SRob Clark HLSQ_SP_FS_STAGE_CONSTANT = 2, 379a2272e48SRob Clark HLSQ_SP_FS_STAGE_INSTRUCTIONS = 3, 380a2272e48SRob Clark HLSQ_TP_STATE = 4, 381a2272e48SRob Clark HLSQ_QUADS = 5, 382a2272e48SRob Clark HLSQ_PIXELS = 6, 383a2272e48SRob Clark HLSQ_VERTICES = 7, 384a2272e48SRob Clark HLSQ_SP_VS_STAGE_DATA_BYTES = 13, 385a2272e48SRob Clark HLSQ_SP_FS_STAGE_DATA_BYTES = 14, 386a2272e48SRob Clark HLSQ_BUSY_CYCLES = 15, 387a2272e48SRob Clark HLSQ_STALL_CYCLES_SP_STATE = 16, 388a2272e48SRob Clark HLSQ_STALL_CYCLES_SP_VS_STAGE = 17, 389a2272e48SRob Clark HLSQ_STALL_CYCLES_SP_FS_STAGE = 18, 390a2272e48SRob Clark HLSQ_STALL_CYCLES_UCHE = 19, 391a2272e48SRob Clark HLSQ_RBBM_LOAD_CYCLES = 20, 392a2272e48SRob Clark HLSQ_DI_TO_VS_START_SP = 21, 393a2272e48SRob Clark HLSQ_DI_TO_FS_START_SP = 22, 394a2272e48SRob Clark HLSQ_VS_STAGE_START_TO_DONE_SP = 23, 395a2272e48SRob Clark HLSQ_FS_STAGE_START_TO_DONE_SP = 24, 396a2272e48SRob Clark HLSQ_SP_STATE_COPY_CYCLES_VS_STAGE = 25, 397a2272e48SRob Clark HLSQ_SP_STATE_COPY_CYCLES_FS_STAGE = 26, 398a2272e48SRob Clark HLSQ_UCHE_LATENCY_CYCLES = 27, 399a2272e48SRob Clark HLSQ_UCHE_LATENCY_COUNT = 28, 400a2272e48SRob Clark HLSQ_STARVE_CYCLES_VFD = 29, 401a2272e48SRob Clark }; 402a2272e48SRob Clark 403a2272e48SRob Clark enum a4xx_pc_perfcounter_select { 404a2272e48SRob Clark PC_VIS_STREAMS_LOADED = 0, 405a2272e48SRob Clark PC_VPC_PRIMITIVES = 2, 406a2272e48SRob Clark PC_DEAD_PRIM = 3, 407a2272e48SRob Clark PC_LIVE_PRIM = 4, 408a2272e48SRob Clark PC_DEAD_DRAWCALLS = 5, 409a2272e48SRob Clark PC_LIVE_DRAWCALLS = 6, 410a2272e48SRob Clark PC_VERTEX_MISSES = 7, 411a2272e48SRob Clark PC_STALL_CYCLES_VFD = 9, 412a2272e48SRob Clark PC_STALL_CYCLES_TSE = 10, 413a2272e48SRob Clark PC_STALL_CYCLES_UCHE = 11, 414a2272e48SRob Clark PC_WORKING_CYCLES = 12, 415a2272e48SRob Clark PC_IA_VERTICES = 13, 416a2272e48SRob Clark PC_GS_PRIMITIVES = 14, 417a2272e48SRob Clark PC_HS_INVOCATIONS = 15, 418a2272e48SRob Clark PC_DS_INVOCATIONS = 16, 419a2272e48SRob Clark PC_DS_PRIMITIVES = 17, 420a2272e48SRob Clark PC_STARVE_CYCLES_FOR_INDEX = 20, 421a2272e48SRob Clark PC_STARVE_CYCLES_FOR_TESS_FACTOR = 21, 422a2272e48SRob Clark PC_STARVE_CYCLES_FOR_VIZ_STREAM = 22, 423a2272e48SRob Clark PC_STALL_CYCLES_TESS = 23, 424a2272e48SRob Clark PC_STARVE_CYCLES_FOR_POSITION = 24, 425a2272e48SRob Clark PC_MODE0_DRAWCALL = 25, 426a2272e48SRob Clark PC_MODE1_DRAWCALL = 26, 427a2272e48SRob Clark PC_MODE2_DRAWCALL = 27, 428a2272e48SRob Clark PC_MODE3_DRAWCALL = 28, 429a2272e48SRob Clark PC_MODE4_DRAWCALL = 29, 430a2272e48SRob Clark PC_PREDICATED_DEAD_DRAWCALL = 30, 431a2272e48SRob Clark PC_STALL_CYCLES_BY_TSE_ONLY = 31, 432a2272e48SRob Clark PC_STALL_CYCLES_BY_VPC_ONLY = 32, 433a2272e48SRob Clark PC_VPC_POS_DATA_TRANSACTION = 33, 434a2272e48SRob Clark PC_BUSY_CYCLES = 34, 435a2272e48SRob Clark PC_STARVE_CYCLES_DI = 35, 436a2272e48SRob Clark PC_STALL_CYCLES_VPC = 36, 437a2272e48SRob Clark TESS_WORKING_CYCLES = 37, 438a2272e48SRob Clark TESS_NUM_CYCLES_SETUP_WORKING = 38, 439a2272e48SRob Clark TESS_NUM_CYCLES_PTGEN_WORKING = 39, 440a2272e48SRob Clark TESS_NUM_CYCLES_CONNGEN_WORKING = 40, 441a2272e48SRob Clark TESS_BUSY_CYCLES = 41, 442a2272e48SRob Clark TESS_STARVE_CYCLES_PC = 42, 443a2272e48SRob Clark TESS_STALL_CYCLES_PC = 43, 444a2272e48SRob Clark }; 445a2272e48SRob Clark 446a2272e48SRob Clark enum a4xx_pwr_perfcounter_select { 447a2272e48SRob Clark PWR_CORE_CLOCK_CYCLES = 0, 448a2272e48SRob Clark PWR_BUSY_CLOCK_CYCLES = 1, 449a2272e48SRob Clark }; 450a2272e48SRob Clark 451a2272e48SRob Clark enum a4xx_rb_perfcounter_select { 452a2272e48SRob Clark RB_BUSY_CYCLES = 0, 453a2272e48SRob Clark RB_BUSY_CYCLES_BINNING = 1, 454a2272e48SRob Clark RB_BUSY_CYCLES_RENDERING = 2, 455a2272e48SRob Clark RB_BUSY_CYCLES_RESOLVE = 3, 456a2272e48SRob Clark RB_STARVE_CYCLES_BY_SP = 4, 457a2272e48SRob Clark RB_STARVE_CYCLES_BY_RAS = 5, 458a2272e48SRob Clark RB_STARVE_CYCLES_BY_MARB = 6, 459a2272e48SRob Clark RB_STALL_CYCLES_BY_MARB = 7, 460a2272e48SRob Clark RB_STALL_CYCLES_BY_HLSQ = 8, 461a2272e48SRob Clark RB_RB_RB_MARB_DATA = 9, 462a2272e48SRob Clark RB_SP_RB_QUAD = 10, 463a2272e48SRob Clark RB_RAS_RB_Z_QUADS = 11, 464a2272e48SRob Clark RB_GMEM_CH0_READ = 12, 465a2272e48SRob Clark RB_GMEM_CH1_READ = 13, 466a2272e48SRob Clark RB_GMEM_CH0_WRITE = 14, 467a2272e48SRob Clark RB_GMEM_CH1_WRITE = 15, 468a2272e48SRob Clark RB_CP_CONTEXT_DONE = 16, 469a2272e48SRob Clark RB_CP_CACHE_FLUSH = 17, 470a2272e48SRob Clark RB_CP_ZPASS_DONE = 18, 471a2272e48SRob Clark RB_STALL_FIFO0_FULL = 19, 472a2272e48SRob Clark RB_STALL_FIFO1_FULL = 20, 473a2272e48SRob Clark RB_STALL_FIFO2_FULL = 21, 474a2272e48SRob Clark RB_STALL_FIFO3_FULL = 22, 475a2272e48SRob Clark RB_RB_HLSQ_TRANSACTIONS = 23, 476a2272e48SRob Clark RB_Z_READ = 24, 477a2272e48SRob Clark RB_Z_WRITE = 25, 478a2272e48SRob Clark RB_C_READ = 26, 479a2272e48SRob Clark RB_C_WRITE = 27, 480a2272e48SRob Clark RB_C_READ_LATENCY = 28, 481a2272e48SRob Clark RB_Z_READ_LATENCY = 29, 482a2272e48SRob Clark RB_STALL_BY_UCHE = 30, 483a2272e48SRob Clark RB_MARB_UCHE_TRANSACTIONS = 31, 484a2272e48SRob Clark RB_CACHE_STALL_MISS = 32, 485a2272e48SRob Clark RB_CACHE_STALL_FIFO_FULL = 33, 486a2272e48SRob Clark RB_8BIT_BLENDER_UNITS_ACTIVE = 34, 487a2272e48SRob Clark RB_16BIT_BLENDER_UNITS_ACTIVE = 35, 488a2272e48SRob Clark RB_SAMPLER_UNITS_ACTIVE = 36, 489a2272e48SRob Clark RB_TOTAL_PASS = 38, 490a2272e48SRob Clark RB_Z_PASS = 39, 491a2272e48SRob Clark RB_Z_FAIL = 40, 492a2272e48SRob Clark RB_S_FAIL = 41, 493a2272e48SRob Clark RB_POWER0 = 42, 494a2272e48SRob Clark RB_POWER1 = 43, 495a2272e48SRob Clark RB_POWER2 = 44, 496a2272e48SRob Clark RB_POWER3 = 45, 497a2272e48SRob Clark RB_POWER4 = 46, 498a2272e48SRob Clark RB_POWER5 = 47, 499a2272e48SRob Clark RB_POWER6 = 48, 500a2272e48SRob Clark RB_POWER7 = 49, 501a2272e48SRob Clark }; 502a2272e48SRob Clark 503a2272e48SRob Clark enum a4xx_rbbm_perfcounter_select { 504a2272e48SRob Clark RBBM_ALWAYS_ON = 0, 505a2272e48SRob Clark RBBM_VBIF_BUSY = 1, 506a2272e48SRob Clark RBBM_TSE_BUSY = 2, 507a2272e48SRob Clark RBBM_RAS_BUSY = 3, 508a2272e48SRob Clark RBBM_PC_DCALL_BUSY = 4, 509a2272e48SRob Clark RBBM_PC_VSD_BUSY = 5, 510a2272e48SRob Clark RBBM_VFD_BUSY = 6, 511a2272e48SRob Clark RBBM_VPC_BUSY = 7, 512a2272e48SRob Clark RBBM_UCHE_BUSY = 8, 513a2272e48SRob Clark RBBM_VSC_BUSY = 9, 514a2272e48SRob Clark RBBM_HLSQ_BUSY = 10, 515a2272e48SRob Clark RBBM_ANY_RB_BUSY = 11, 516a2272e48SRob Clark RBBM_ANY_TPL1_BUSY = 12, 517a2272e48SRob Clark RBBM_ANY_SP_BUSY = 13, 518a2272e48SRob Clark RBBM_ANY_MARB_BUSY = 14, 519a2272e48SRob Clark RBBM_ANY_ARB_BUSY = 15, 520a2272e48SRob Clark RBBM_AHB_STATUS_BUSY = 16, 521a2272e48SRob Clark RBBM_AHB_STATUS_STALLED = 17, 522a2272e48SRob Clark RBBM_AHB_STATUS_TXFR = 18, 523a2272e48SRob Clark RBBM_AHB_STATUS_TXFR_SPLIT = 19, 524a2272e48SRob Clark RBBM_AHB_STATUS_TXFR_ERROR = 20, 525a2272e48SRob Clark RBBM_AHB_STATUS_LONG_STALL = 21, 526a2272e48SRob Clark RBBM_STATUS_MASKED = 22, 527a2272e48SRob Clark RBBM_CP_BUSY_GFX_CORE_IDLE = 23, 528a2272e48SRob Clark RBBM_TESS_BUSY = 24, 529a2272e48SRob Clark RBBM_COM_BUSY = 25, 530a2272e48SRob Clark RBBM_DCOM_BUSY = 32, 531a2272e48SRob Clark RBBM_ANY_CCU_BUSY = 33, 532a2272e48SRob Clark RBBM_DPM_BUSY = 34, 533a2272e48SRob Clark }; 534a2272e48SRob Clark 535a2272e48SRob Clark enum a4xx_sp_perfcounter_select { 536a2272e48SRob Clark SP_LM_LOAD_INSTRUCTIONS = 0, 537a2272e48SRob Clark SP_LM_STORE_INSTRUCTIONS = 1, 538a2272e48SRob Clark SP_LM_ATOMICS = 2, 539a2272e48SRob Clark SP_GM_LOAD_INSTRUCTIONS = 3, 540a2272e48SRob Clark SP_GM_STORE_INSTRUCTIONS = 4, 541a2272e48SRob Clark SP_GM_ATOMICS = 5, 542a2272e48SRob Clark SP_VS_STAGE_TEX_INSTRUCTIONS = 6, 543a2272e48SRob Clark SP_VS_STAGE_CFLOW_INSTRUCTIONS = 7, 544a2272e48SRob Clark SP_VS_STAGE_EFU_INSTRUCTIONS = 8, 545a2272e48SRob Clark SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 9, 546a2272e48SRob Clark SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 10, 547a2272e48SRob Clark SP_FS_STAGE_TEX_INSTRUCTIONS = 11, 548a2272e48SRob Clark SP_FS_STAGE_CFLOW_INSTRUCTIONS = 12, 549a2272e48SRob Clark SP_FS_STAGE_EFU_INSTRUCTIONS = 13, 550a2272e48SRob Clark SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 14, 551a2272e48SRob Clark SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 15, 552a2272e48SRob Clark SP_VS_INSTRUCTIONS = 17, 553a2272e48SRob Clark SP_FS_INSTRUCTIONS = 18, 554a2272e48SRob Clark SP_ADDR_LOCK_COUNT = 19, 555a2272e48SRob Clark SP_UCHE_READ_TRANS = 20, 556a2272e48SRob Clark SP_UCHE_WRITE_TRANS = 21, 557a2272e48SRob Clark SP_EXPORT_VPC_TRANS = 22, 558a2272e48SRob Clark SP_EXPORT_RB_TRANS = 23, 559a2272e48SRob Clark SP_PIXELS_KILLED = 24, 560a2272e48SRob Clark SP_ICL1_REQUESTS = 25, 561a2272e48SRob Clark SP_ICL1_MISSES = 26, 562a2272e48SRob Clark SP_ICL0_REQUESTS = 27, 563a2272e48SRob Clark SP_ICL0_MISSES = 28, 564a2272e48SRob Clark SP_ALU_WORKING_CYCLES = 29, 565a2272e48SRob Clark SP_EFU_WORKING_CYCLES = 30, 566a2272e48SRob Clark SP_STALL_CYCLES_BY_VPC = 31, 567a2272e48SRob Clark SP_STALL_CYCLES_BY_TP = 32, 568a2272e48SRob Clark SP_STALL_CYCLES_BY_UCHE = 33, 569a2272e48SRob Clark SP_STALL_CYCLES_BY_RB = 34, 570a2272e48SRob Clark SP_BUSY_CYCLES = 35, 571a2272e48SRob Clark SP_HS_INSTRUCTIONS = 36, 572a2272e48SRob Clark SP_DS_INSTRUCTIONS = 37, 573a2272e48SRob Clark SP_GS_INSTRUCTIONS = 38, 574a2272e48SRob Clark SP_CS_INSTRUCTIONS = 39, 575a2272e48SRob Clark SP_SCHEDULER_NON_WORKING = 40, 576a2272e48SRob Clark SP_WAVE_CONTEXTS = 41, 577a2272e48SRob Clark SP_WAVE_CONTEXT_CYCLES = 42, 578a2272e48SRob Clark SP_POWER0 = 43, 579a2272e48SRob Clark SP_POWER1 = 44, 580a2272e48SRob Clark SP_POWER2 = 45, 581a2272e48SRob Clark SP_POWER3 = 46, 582a2272e48SRob Clark SP_POWER4 = 47, 583a2272e48SRob Clark SP_POWER5 = 48, 584a2272e48SRob Clark SP_POWER6 = 49, 585a2272e48SRob Clark SP_POWER7 = 50, 586a2272e48SRob Clark SP_POWER8 = 51, 587a2272e48SRob Clark SP_POWER9 = 52, 588a2272e48SRob Clark SP_POWER10 = 53, 589a2272e48SRob Clark SP_POWER11 = 54, 590a2272e48SRob Clark SP_POWER12 = 55, 591a2272e48SRob Clark SP_POWER13 = 56, 592a2272e48SRob Clark SP_POWER14 = 57, 593a2272e48SRob Clark SP_POWER15 = 58, 594a2272e48SRob Clark }; 595a2272e48SRob Clark 596a2272e48SRob Clark enum a4xx_tp_perfcounter_select { 597a2272e48SRob Clark TP_L1_REQUESTS = 0, 598a2272e48SRob Clark TP_L1_MISSES = 1, 599a2272e48SRob Clark TP_QUADS_OFFSET = 8, 600a2272e48SRob Clark TP_QUAD_SHADOW = 9, 601a2272e48SRob Clark TP_QUADS_ARRAY = 10, 602a2272e48SRob Clark TP_QUADS_GRADIENT = 11, 603a2272e48SRob Clark TP_QUADS_1D2D = 12, 604a2272e48SRob Clark TP_QUADS_3DCUBE = 13, 605a2272e48SRob Clark TP_BUSY_CYCLES = 16, 606a2272e48SRob Clark TP_STALL_CYCLES_BY_ARB = 17, 607a2272e48SRob Clark TP_STATE_CACHE_REQUESTS = 20, 608a2272e48SRob Clark TP_STATE_CACHE_MISSES = 21, 609a2272e48SRob Clark TP_POWER0 = 22, 610a2272e48SRob Clark TP_POWER1 = 23, 611a2272e48SRob Clark TP_POWER2 = 24, 612a2272e48SRob Clark TP_POWER3 = 25, 613a2272e48SRob Clark TP_POWER4 = 26, 614a2272e48SRob Clark TP_POWER5 = 27, 615a2272e48SRob Clark TP_POWER6 = 28, 616a2272e48SRob Clark TP_POWER7 = 29, 617a2272e48SRob Clark }; 618a2272e48SRob Clark 619a2272e48SRob Clark enum a4xx_uche_perfcounter_select { 620a2272e48SRob Clark UCHE_VBIF_READ_BEATS_TP = 0, 621a2272e48SRob Clark UCHE_VBIF_READ_BEATS_VFD = 1, 622a2272e48SRob Clark UCHE_VBIF_READ_BEATS_HLSQ = 2, 623a2272e48SRob Clark UCHE_VBIF_READ_BEATS_MARB = 3, 624a2272e48SRob Clark UCHE_VBIF_READ_BEATS_SP = 4, 625a2272e48SRob Clark UCHE_READ_REQUESTS_TP = 5, 626a2272e48SRob Clark UCHE_READ_REQUESTS_VFD = 6, 627a2272e48SRob Clark UCHE_READ_REQUESTS_HLSQ = 7, 628a2272e48SRob Clark UCHE_READ_REQUESTS_MARB = 8, 629a2272e48SRob Clark UCHE_READ_REQUESTS_SP = 9, 630a2272e48SRob Clark UCHE_WRITE_REQUESTS_MARB = 10, 631a2272e48SRob Clark UCHE_WRITE_REQUESTS_SP = 11, 632a2272e48SRob Clark UCHE_TAG_CHECK_FAILS = 12, 633a2272e48SRob Clark UCHE_EVICTS = 13, 634a2272e48SRob Clark UCHE_FLUSHES = 14, 635a2272e48SRob Clark UCHE_VBIF_LATENCY_CYCLES = 15, 636a2272e48SRob Clark UCHE_VBIF_LATENCY_SAMPLES = 16, 637a2272e48SRob Clark UCHE_BUSY_CYCLES = 17, 638a2272e48SRob Clark UCHE_VBIF_READ_BEATS_PC = 18, 639a2272e48SRob Clark UCHE_READ_REQUESTS_PC = 19, 640a2272e48SRob Clark UCHE_WRITE_REQUESTS_VPC = 20, 641a2272e48SRob Clark UCHE_STALL_BY_VBIF = 21, 642a2272e48SRob Clark UCHE_WRITE_REQUESTS_VSC = 22, 643a2272e48SRob Clark UCHE_POWER0 = 23, 644a2272e48SRob Clark UCHE_POWER1 = 24, 645a2272e48SRob Clark UCHE_POWER2 = 25, 646a2272e48SRob Clark UCHE_POWER3 = 26, 647a2272e48SRob Clark UCHE_POWER4 = 27, 648a2272e48SRob Clark UCHE_POWER5 = 28, 649a2272e48SRob Clark UCHE_POWER6 = 29, 650a2272e48SRob Clark UCHE_POWER7 = 30, 651a2272e48SRob Clark }; 652a2272e48SRob Clark 653a2272e48SRob Clark enum a4xx_vbif_perfcounter_select { 654a2272e48SRob Clark AXI_READ_REQUESTS_ID_0 = 0, 655a2272e48SRob Clark AXI_READ_REQUESTS_ID_1 = 1, 656a2272e48SRob Clark AXI_READ_REQUESTS_ID_2 = 2, 657a2272e48SRob Clark AXI_READ_REQUESTS_ID_3 = 3, 658a2272e48SRob Clark AXI_READ_REQUESTS_ID_4 = 4, 659a2272e48SRob Clark AXI_READ_REQUESTS_ID_5 = 5, 660a2272e48SRob Clark AXI_READ_REQUESTS_ID_6 = 6, 661a2272e48SRob Clark AXI_READ_REQUESTS_ID_7 = 7, 662a2272e48SRob Clark AXI_READ_REQUESTS_ID_8 = 8, 663a2272e48SRob Clark AXI_READ_REQUESTS_ID_9 = 9, 664a2272e48SRob Clark AXI_READ_REQUESTS_ID_10 = 10, 665a2272e48SRob Clark AXI_READ_REQUESTS_ID_11 = 11, 666a2272e48SRob Clark AXI_READ_REQUESTS_ID_12 = 12, 667a2272e48SRob Clark AXI_READ_REQUESTS_ID_13 = 13, 668a2272e48SRob Clark AXI_READ_REQUESTS_ID_14 = 14, 669a2272e48SRob Clark AXI_READ_REQUESTS_ID_15 = 15, 670a2272e48SRob Clark AXI0_READ_REQUESTS_TOTAL = 16, 671a2272e48SRob Clark AXI1_READ_REQUESTS_TOTAL = 17, 672a2272e48SRob Clark AXI2_READ_REQUESTS_TOTAL = 18, 673a2272e48SRob Clark AXI3_READ_REQUESTS_TOTAL = 19, 674a2272e48SRob Clark AXI_READ_REQUESTS_TOTAL = 20, 675a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_0 = 21, 676a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_1 = 22, 677a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_2 = 23, 678a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_3 = 24, 679a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_4 = 25, 680a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_5 = 26, 681a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_6 = 27, 682a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_7 = 28, 683a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_8 = 29, 684a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_9 = 30, 685a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_10 = 31, 686a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_11 = 32, 687a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_12 = 33, 688a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_13 = 34, 689a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_14 = 35, 690a2272e48SRob Clark AXI_WRITE_REQUESTS_ID_15 = 36, 691a2272e48SRob Clark AXI0_WRITE_REQUESTS_TOTAL = 37, 692a2272e48SRob Clark AXI1_WRITE_REQUESTS_TOTAL = 38, 693a2272e48SRob Clark AXI2_WRITE_REQUESTS_TOTAL = 39, 694a2272e48SRob Clark AXI3_WRITE_REQUESTS_TOTAL = 40, 695a2272e48SRob Clark AXI_WRITE_REQUESTS_TOTAL = 41, 696a2272e48SRob Clark AXI_TOTAL_REQUESTS = 42, 697a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_0 = 43, 698a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_1 = 44, 699a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_2 = 45, 700a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_3 = 46, 701a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_4 = 47, 702a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_5 = 48, 703a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_6 = 49, 704a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_7 = 50, 705a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_8 = 51, 706a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_9 = 52, 707a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_10 = 53, 708a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_11 = 54, 709a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_12 = 55, 710a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_13 = 56, 711a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_14 = 57, 712a2272e48SRob Clark AXI_READ_DATA_BEATS_ID_15 = 58, 713a2272e48SRob Clark AXI0_READ_DATA_BEATS_TOTAL = 59, 714a2272e48SRob Clark AXI1_READ_DATA_BEATS_TOTAL = 60, 715a2272e48SRob Clark AXI2_READ_DATA_BEATS_TOTAL = 61, 716a2272e48SRob Clark AXI3_READ_DATA_BEATS_TOTAL = 62, 717a2272e48SRob Clark AXI_READ_DATA_BEATS_TOTAL = 63, 718a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_0 = 64, 719a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_1 = 65, 720a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_2 = 66, 721a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_3 = 67, 722a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_4 = 68, 723a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_5 = 69, 724a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_6 = 70, 725a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_7 = 71, 726a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_8 = 72, 727a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_9 = 73, 728a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_10 = 74, 729a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_11 = 75, 730a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_12 = 76, 731a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_13 = 77, 732a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_14 = 78, 733a2272e48SRob Clark AXI_WRITE_DATA_BEATS_ID_15 = 79, 734a2272e48SRob Clark AXI0_WRITE_DATA_BEATS_TOTAL = 80, 735a2272e48SRob Clark AXI1_WRITE_DATA_BEATS_TOTAL = 81, 736a2272e48SRob Clark AXI2_WRITE_DATA_BEATS_TOTAL = 82, 737a2272e48SRob Clark AXI3_WRITE_DATA_BEATS_TOTAL = 83, 738a2272e48SRob Clark AXI_WRITE_DATA_BEATS_TOTAL = 84, 739a2272e48SRob Clark AXI_DATA_BEATS_TOTAL = 85, 740a2272e48SRob Clark CYCLES_HELD_OFF_ID_0 = 86, 741a2272e48SRob Clark CYCLES_HELD_OFF_ID_1 = 87, 742a2272e48SRob Clark CYCLES_HELD_OFF_ID_2 = 88, 743a2272e48SRob Clark CYCLES_HELD_OFF_ID_3 = 89, 744a2272e48SRob Clark CYCLES_HELD_OFF_ID_4 = 90, 745a2272e48SRob Clark CYCLES_HELD_OFF_ID_5 = 91, 746a2272e48SRob Clark CYCLES_HELD_OFF_ID_6 = 92, 747a2272e48SRob Clark CYCLES_HELD_OFF_ID_7 = 93, 748a2272e48SRob Clark CYCLES_HELD_OFF_ID_8 = 94, 749a2272e48SRob Clark CYCLES_HELD_OFF_ID_9 = 95, 750a2272e48SRob Clark CYCLES_HELD_OFF_ID_10 = 96, 751a2272e48SRob Clark CYCLES_HELD_OFF_ID_11 = 97, 752a2272e48SRob Clark CYCLES_HELD_OFF_ID_12 = 98, 753a2272e48SRob Clark CYCLES_HELD_OFF_ID_13 = 99, 754a2272e48SRob Clark CYCLES_HELD_OFF_ID_14 = 100, 755a2272e48SRob Clark CYCLES_HELD_OFF_ID_15 = 101, 756a2272e48SRob Clark AXI_READ_REQUEST_HELD_OFF = 102, 757a2272e48SRob Clark AXI_WRITE_REQUEST_HELD_OFF = 103, 758a2272e48SRob Clark AXI_REQUEST_HELD_OFF = 104, 759a2272e48SRob Clark AXI_WRITE_DATA_HELD_OFF = 105, 760a2272e48SRob Clark OCMEM_AXI_READ_REQUEST_HELD_OFF = 106, 761a2272e48SRob Clark OCMEM_AXI_WRITE_REQUEST_HELD_OFF = 107, 762a2272e48SRob Clark OCMEM_AXI_REQUEST_HELD_OFF = 108, 763a2272e48SRob Clark OCMEM_AXI_WRITE_DATA_HELD_OFF = 109, 764a2272e48SRob Clark ELAPSED_CYCLES_DDR = 110, 765a2272e48SRob Clark ELAPSED_CYCLES_OCMEM = 111, 766a2272e48SRob Clark }; 767a2272e48SRob Clark 768a2272e48SRob Clark enum a4xx_vfd_perfcounter_select { 769a2272e48SRob Clark VFD_UCHE_BYTE_FETCHED = 0, 770a2272e48SRob Clark VFD_UCHE_TRANS = 1, 771a2272e48SRob Clark VFD_FETCH_INSTRUCTIONS = 3, 772a2272e48SRob Clark VFD_BUSY_CYCLES = 5, 773a2272e48SRob Clark VFD_STALL_CYCLES_UCHE = 6, 774a2272e48SRob Clark VFD_STALL_CYCLES_HLSQ = 7, 775a2272e48SRob Clark VFD_STALL_CYCLES_VPC_BYPASS = 8, 776a2272e48SRob Clark VFD_STALL_CYCLES_VPC_ALLOC = 9, 777a2272e48SRob Clark VFD_MODE_0_FIBERS = 13, 778a2272e48SRob Clark VFD_MODE_1_FIBERS = 14, 779a2272e48SRob Clark VFD_MODE_2_FIBERS = 15, 780a2272e48SRob Clark VFD_MODE_3_FIBERS = 16, 781a2272e48SRob Clark VFD_MODE_4_FIBERS = 17, 782a2272e48SRob Clark VFD_BFIFO_STALL = 18, 783a2272e48SRob Clark VFD_NUM_VERTICES_TOTAL = 19, 784a2272e48SRob Clark VFD_PACKER_FULL = 20, 785a2272e48SRob Clark VFD_UCHE_REQUEST_FIFO_FULL = 21, 786a2272e48SRob Clark VFD_STARVE_CYCLES_PC = 22, 787a2272e48SRob Clark VFD_STARVE_CYCLES_UCHE = 23, 788a2272e48SRob Clark }; 789a2272e48SRob Clark 790a2272e48SRob Clark enum a4xx_vpc_perfcounter_select { 791a2272e48SRob Clark VPC_SP_LM_COMPONENTS = 2, 792a2272e48SRob Clark VPC_SP0_LM_BYTES = 3, 793a2272e48SRob Clark VPC_SP1_LM_BYTES = 4, 794a2272e48SRob Clark VPC_SP2_LM_BYTES = 5, 795a2272e48SRob Clark VPC_SP3_LM_BYTES = 6, 796a2272e48SRob Clark VPC_WORKING_CYCLES = 7, 797a2272e48SRob Clark VPC_STALL_CYCLES_LM = 8, 798a2272e48SRob Clark VPC_STARVE_CYCLES_RAS = 9, 799a2272e48SRob Clark VPC_STREAMOUT_CYCLES = 10, 800a2272e48SRob Clark VPC_UCHE_TRANSACTIONS = 12, 801a2272e48SRob Clark VPC_STALL_CYCLES_UCHE = 13, 802a2272e48SRob Clark VPC_BUSY_CYCLES = 14, 803a2272e48SRob Clark VPC_STARVE_CYCLES_SP = 15, 804a2272e48SRob Clark }; 805a2272e48SRob Clark 806a2272e48SRob Clark enum a4xx_vsc_perfcounter_select { 807a2272e48SRob Clark VSC_BUSY_CYCLES = 0, 808a2272e48SRob Clark VSC_WORKING_CYCLES = 1, 809a2272e48SRob Clark VSC_STALL_CYCLES_UCHE = 2, 810a2272e48SRob Clark VSC_STARVE_CYCLES_RAS = 3, 811a2272e48SRob Clark VSC_EOT_NUM = 4, 812a2272e48SRob Clark }; 813a2272e48SRob Clark 814bc00ae02SRob Clark enum a4xx_tex_filter { 815bc00ae02SRob Clark A4XX_TEX_NEAREST = 0, 816bc00ae02SRob Clark A4XX_TEX_LINEAR = 1, 817af6cb4c1SRob Clark A4XX_TEX_ANISO = 2, 818bc00ae02SRob Clark }; 819bc00ae02SRob Clark 820bc00ae02SRob Clark enum a4xx_tex_clamp { 821bc00ae02SRob Clark A4XX_TEX_REPEAT = 0, 822bc00ae02SRob Clark A4XX_TEX_CLAMP_TO_EDGE = 1, 823bc00ae02SRob Clark A4XX_TEX_MIRROR_REPEAT = 2, 8248217e97aSRob Clark A4XX_TEX_CLAMP_TO_BORDER = 3, 8258217e97aSRob Clark A4XX_TEX_MIRROR_CLAMP = 4, 826bc00ae02SRob Clark }; 827bc00ae02SRob Clark 828af6cb4c1SRob Clark enum a4xx_tex_aniso { 829af6cb4c1SRob Clark A4XX_TEX_ANISO_1 = 0, 830af6cb4c1SRob Clark A4XX_TEX_ANISO_2 = 1, 831af6cb4c1SRob Clark A4XX_TEX_ANISO_4 = 2, 832af6cb4c1SRob Clark A4XX_TEX_ANISO_8 = 3, 833af6cb4c1SRob Clark A4XX_TEX_ANISO_16 = 4, 834af6cb4c1SRob Clark }; 835af6cb4c1SRob Clark 836bc00ae02SRob Clark enum a4xx_tex_swiz { 837bc00ae02SRob Clark A4XX_TEX_X = 0, 838bc00ae02SRob Clark A4XX_TEX_Y = 1, 839bc00ae02SRob Clark A4XX_TEX_Z = 2, 840bc00ae02SRob Clark A4XX_TEX_W = 3, 841bc00ae02SRob Clark A4XX_TEX_ZERO = 4, 842bc00ae02SRob Clark A4XX_TEX_ONE = 5, 843bc00ae02SRob Clark }; 844bc00ae02SRob Clark 845bc00ae02SRob Clark enum a4xx_tex_type { 846bc00ae02SRob Clark A4XX_TEX_1D = 0, 847bc00ae02SRob Clark A4XX_TEX_2D = 1, 848bc00ae02SRob Clark A4XX_TEX_CUBE = 2, 849bc00ae02SRob Clark A4XX_TEX_3D = 3, 850bc00ae02SRob Clark }; 851bc00ae02SRob Clark 852bc00ae02SRob Clark #define A4XX_CGC_HLSQ_EARLY_CYC__MASK 0x00700000 853bc00ae02SRob Clark #define A4XX_CGC_HLSQ_EARLY_CYC__SHIFT 20 854bc00ae02SRob Clark static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) 855bc00ae02SRob Clark { 856bc00ae02SRob Clark return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK; 857bc00ae02SRob Clark } 858bc00ae02SRob Clark #define A4XX_INT0_RBBM_GPU_IDLE 0x00000001 859bc00ae02SRob Clark #define A4XX_INT0_RBBM_AHB_ERROR 0x00000002 860bc00ae02SRob Clark #define A4XX_INT0_RBBM_REG_TIMEOUT 0x00000004 861bc00ae02SRob Clark #define A4XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 862bc00ae02SRob Clark #define A4XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 863bc00ae02SRob Clark #define A4XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020 864bc00ae02SRob Clark #define A4XX_INT0_VFD_ERROR 0x00000040 865bc00ae02SRob Clark #define A4XX_INT0_CP_SW_INT 0x00000080 866bc00ae02SRob Clark #define A4XX_INT0_CP_T0_PACKET_IN_IB 0x00000100 867bc00ae02SRob Clark #define A4XX_INT0_CP_OPCODE_ERROR 0x00000200 868bc00ae02SRob Clark #define A4XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400 869bc00ae02SRob Clark #define A4XX_INT0_CP_HW_FAULT 0x00000800 870bc00ae02SRob Clark #define A4XX_INT0_CP_DMA 0x00001000 871bc00ae02SRob Clark #define A4XX_INT0_CP_IB2_INT 0x00002000 872bc00ae02SRob Clark #define A4XX_INT0_CP_IB1_INT 0x00004000 873bc00ae02SRob Clark #define A4XX_INT0_CP_RB_INT 0x00008000 874bc00ae02SRob Clark #define A4XX_INT0_CP_REG_PROTECT_FAULT 0x00010000 875bc00ae02SRob Clark #define A4XX_INT0_CP_RB_DONE_TS 0x00020000 876bc00ae02SRob Clark #define A4XX_INT0_CP_VS_DONE_TS 0x00040000 877bc00ae02SRob Clark #define A4XX_INT0_CP_PS_DONE_TS 0x00080000 878bc00ae02SRob Clark #define A4XX_INT0_CACHE_FLUSH_TS 0x00100000 879bc00ae02SRob Clark #define A4XX_INT0_CP_AHB_ERROR_HALT 0x00200000 880bc00ae02SRob Clark #define A4XX_INT0_MISC_HANG_DETECT 0x01000000 881bc00ae02SRob Clark #define A4XX_INT0_UCHE_OOB_ACCESS 0x02000000 882bc00ae02SRob Clark #define REG_A4XX_RB_GMEM_BASE_ADDR 0x00000cc0 883bc00ae02SRob Clark 884bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_0 0x00000cc7 885bc00ae02SRob Clark 886bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_1 0x00000cc8 887bc00ae02SRob Clark 888bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_2 0x00000cc9 889bc00ae02SRob Clark 890bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_3 0x00000cca 891bc00ae02SRob Clark 892bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_4 0x00000ccb 893bc00ae02SRob Clark 894bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_5 0x00000ccc 895bc00ae02SRob Clark 896bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_6 0x00000ccd 897bc00ae02SRob Clark 898bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_7 0x00000cce 899bc00ae02SRob Clark 900a2272e48SRob Clark #define REG_A4XX_RB_PERFCTR_CCU_SEL_0 0x00000ccf 901a2272e48SRob Clark 902a2272e48SRob Clark #define REG_A4XX_RB_PERFCTR_CCU_SEL_1 0x00000cd0 903a2272e48SRob Clark 904a2272e48SRob Clark #define REG_A4XX_RB_PERFCTR_CCU_SEL_2 0x00000cd1 905a2272e48SRob Clark 906bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_CCU_SEL_3 0x00000cd2 907bc00ae02SRob Clark 908bc00ae02SRob Clark #define REG_A4XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0 909bc00ae02SRob Clark #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff 910bc00ae02SRob Clark #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0 911bc00ae02SRob Clark static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) 912bc00ae02SRob Clark { 913bc00ae02SRob Clark return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK; 914bc00ae02SRob Clark } 915bc00ae02SRob Clark #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x3fff0000 916bc00ae02SRob Clark #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 16 917bc00ae02SRob Clark static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) 918bc00ae02SRob Clark { 919bc00ae02SRob Clark return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK; 920bc00ae02SRob Clark } 921bc00ae02SRob Clark 922bc00ae02SRob Clark #define REG_A4XX_RB_CLEAR_COLOR_DW0 0x000020cc 923bc00ae02SRob Clark 924bc00ae02SRob Clark #define REG_A4XX_RB_CLEAR_COLOR_DW1 0x000020cd 925bc00ae02SRob Clark 926bc00ae02SRob Clark #define REG_A4XX_RB_CLEAR_COLOR_DW2 0x000020ce 927bc00ae02SRob Clark 928bc00ae02SRob Clark #define REG_A4XX_RB_CLEAR_COLOR_DW3 0x000020cf 929bc00ae02SRob Clark 930bc00ae02SRob Clark #define REG_A4XX_RB_MODE_CONTROL 0x000020a0 931bc00ae02SRob Clark #define A4XX_RB_MODE_CONTROL_WIDTH__MASK 0x0000003f 932bc00ae02SRob Clark #define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT 0 933bc00ae02SRob Clark static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) 934bc00ae02SRob Clark { 935bc00ae02SRob Clark return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK; 936bc00ae02SRob Clark } 937bc00ae02SRob Clark #define A4XX_RB_MODE_CONTROL_HEIGHT__MASK 0x00003f00 938bc00ae02SRob Clark #define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT 8 939bc00ae02SRob Clark static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) 940bc00ae02SRob Clark { 941bc00ae02SRob Clark return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK; 942bc00ae02SRob Clark } 943bc00ae02SRob Clark 944bc00ae02SRob Clark #define REG_A4XX_RB_RENDER_CONTROL 0x000020a1 945bc00ae02SRob Clark #define A4XX_RB_RENDER_CONTROL_BINNING_PASS 0x00000001 946bc00ae02SRob Clark #define A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00000020 947bc00ae02SRob Clark 948bc00ae02SRob Clark #define REG_A4XX_RB_MSAA_CONTROL 0x000020a2 949bc00ae02SRob Clark #define A4XX_RB_MSAA_CONTROL_DISABLE 0x00001000 950bc00ae02SRob Clark #define A4XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000e000 951bc00ae02SRob Clark #define A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 13 952bc00ae02SRob Clark static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val) 953bc00ae02SRob Clark { 954bc00ae02SRob Clark return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK; 955bc00ae02SRob Clark } 956bc00ae02SRob Clark 9578a264743SRob Clark #define REG_A4XX_RB_RENDER_CONTROL2 0x000020a3 9588a264743SRob Clark #define A4XX_RB_RENDER_CONTROL2_XCOORD 0x00000001 9598a264743SRob Clark #define A4XX_RB_RENDER_CONTROL2_YCOORD 0x00000002 9608a264743SRob Clark #define A4XX_RB_RENDER_CONTROL2_ZCOORD 0x00000004 9618a264743SRob Clark #define A4XX_RB_RENDER_CONTROL2_WCOORD 0x00000008 962af6cb4c1SRob Clark #define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK 0x00000010 9638a264743SRob Clark #define A4XX_RB_RENDER_CONTROL2_FACENESS 0x00000020 964af6cb4c1SRob Clark #define A4XX_RB_RENDER_CONTROL2_SAMPLEID 0x00000040 9658a264743SRob Clark #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK 0x00000380 9668a264743SRob Clark #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT 7 9678a264743SRob Clark static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val) 968bc00ae02SRob Clark { 9698a264743SRob Clark return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK; 970bc00ae02SRob Clark } 971af6cb4c1SRob Clark #define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR 0x00000800 9728a264743SRob Clark #define A4XX_RB_RENDER_CONTROL2_VARYING 0x00001000 973bc00ae02SRob Clark 974bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; } 975bc00ae02SRob Clark 976bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; } 977bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008 978bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL_BLEND 0x00000010 979bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL_BLEND2 0x00000020 980a2272e48SRob Clark #define A4XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000040 981a2272e48SRob Clark #define A4XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00 982a2272e48SRob Clark #define A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8 983a2272e48SRob Clark static inline uint32_t A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) 984a2272e48SRob Clark { 985a2272e48SRob Clark return ((val) << A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A4XX_RB_MRT_CONTROL_ROP_CODE__MASK; 986a2272e48SRob Clark } 987bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000 988bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24 989bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 990bc00ae02SRob Clark { 991bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 992bc00ae02SRob Clark } 993bc00ae02SRob Clark 994bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; } 995bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f 996bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 997bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val) 998bc00ae02SRob Clark { 999bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 1000bc00ae02SRob Clark } 1001af6cb4c1SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0 1002af6cb4c1SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6 1003af6cb4c1SRob Clark static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val) 1004af6cb4c1SRob Clark { 1005af6cb4c1SRob Clark return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 1006af6cb4c1SRob Clark } 1007bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00000600 1008bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 9 1009bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 1010bc00ae02SRob Clark { 1011bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK; 1012bc00ae02SRob Clark } 1013bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00001800 1014bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 11 1015bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 1016bc00ae02SRob Clark { 1017bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 1018bc00ae02SRob Clark } 1019af6cb4c1SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00002000 10202d3584ebSRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xffffc000 1021bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 14 1022bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) 1023bc00ae02SRob Clark { 1024bc00ae02SRob Clark return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; 1025bc00ae02SRob Clark } 1026bc00ae02SRob Clark 1027bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; } 1028bc00ae02SRob Clark 1029bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; } 10302d3584ebSRob Clark #define A4XX_RB_MRT_CONTROL3_STRIDE__MASK 0x03fffff8 1031bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT 3 1032bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val) 1033bc00ae02SRob Clark { 1034bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT) & A4XX_RB_MRT_CONTROL3_STRIDE__MASK; 1035bc00ae02SRob Clark } 1036bc00ae02SRob Clark 1037bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; } 1038bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 1039bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 1040bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 1041bc00ae02SRob Clark { 1042bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 1043bc00ae02SRob Clark } 1044bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 1045bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 1046bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a4xx_rb_blend_opcode val) 1047bc00ae02SRob Clark { 1048bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 1049bc00ae02SRob Clark } 1050bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 1051bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 1052bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 1053bc00ae02SRob Clark { 1054bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 1055bc00ae02SRob Clark } 1056bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 1057bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 1058bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 1059bc00ae02SRob Clark { 1060bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 1061bc00ae02SRob Clark } 1062bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 1063bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 1064bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a4xx_rb_blend_opcode val) 1065bc00ae02SRob Clark { 1066bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 1067bc00ae02SRob Clark } 1068bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 1069bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 1070bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 1071bc00ae02SRob Clark { 1072bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 1073bc00ae02SRob Clark } 1074bc00ae02SRob Clark 1075a2272e48SRob Clark #define REG_A4XX_RB_BLEND_RED 0x000020f0 1076a2272e48SRob Clark #define A4XX_RB_BLEND_RED_UINT__MASK 0x0000ffff 10778a264743SRob Clark #define A4XX_RB_BLEND_RED_UINT__SHIFT 0 10788a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val) 10798a264743SRob Clark { 10808a264743SRob Clark return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK; 10818a264743SRob Clark } 10828a264743SRob Clark #define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 10838a264743SRob Clark #define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16 10848a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val) 10858a264743SRob Clark { 10868a264743SRob Clark return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK; 10878a264743SRob Clark } 10888a264743SRob Clark 1089a2272e48SRob Clark #define REG_A4XX_RB_BLEND_RED_F32 0x000020f1 1090a2272e48SRob Clark #define A4XX_RB_BLEND_RED_F32__MASK 0xffffffff 1091a2272e48SRob Clark #define A4XX_RB_BLEND_RED_F32__SHIFT 0 1092a2272e48SRob Clark static inline uint32_t A4XX_RB_BLEND_RED_F32(float val) 1093a2272e48SRob Clark { 1094a2272e48SRob Clark return ((fui(val)) << A4XX_RB_BLEND_RED_F32__SHIFT) & A4XX_RB_BLEND_RED_F32__MASK; 1095a2272e48SRob Clark } 1096a2272e48SRob Clark 1097a2272e48SRob Clark #define REG_A4XX_RB_BLEND_GREEN 0x000020f2 1098a2272e48SRob Clark #define A4XX_RB_BLEND_GREEN_UINT__MASK 0x0000ffff 10998a264743SRob Clark #define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0 11008a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val) 11018a264743SRob Clark { 11028a264743SRob Clark return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK; 11038a264743SRob Clark } 11048a264743SRob Clark #define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 11058a264743SRob Clark #define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 11068a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val) 11078a264743SRob Clark { 11088a264743SRob Clark return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK; 11098a264743SRob Clark } 11108a264743SRob Clark 1111a2272e48SRob Clark #define REG_A4XX_RB_BLEND_GREEN_F32 0x000020f3 1112a2272e48SRob Clark #define A4XX_RB_BLEND_GREEN_F32__MASK 0xffffffff 1113a2272e48SRob Clark #define A4XX_RB_BLEND_GREEN_F32__SHIFT 0 1114a2272e48SRob Clark static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val) 1115a2272e48SRob Clark { 1116a2272e48SRob Clark return ((fui(val)) << A4XX_RB_BLEND_GREEN_F32__SHIFT) & A4XX_RB_BLEND_GREEN_F32__MASK; 1117a2272e48SRob Clark } 1118a2272e48SRob Clark 1119a2272e48SRob Clark #define REG_A4XX_RB_BLEND_BLUE 0x000020f4 1120a2272e48SRob Clark #define A4XX_RB_BLEND_BLUE_UINT__MASK 0x0000ffff 11218a264743SRob Clark #define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0 11228a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val) 11238a264743SRob Clark { 11248a264743SRob Clark return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK; 11258a264743SRob Clark } 11268a264743SRob Clark #define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 11278a264743SRob Clark #define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 11288a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val) 11298a264743SRob Clark { 11308a264743SRob Clark return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK; 11318a264743SRob Clark } 11328a264743SRob Clark 1133a2272e48SRob Clark #define REG_A4XX_RB_BLEND_BLUE_F32 0x000020f5 1134a2272e48SRob Clark #define A4XX_RB_BLEND_BLUE_F32__MASK 0xffffffff 1135a2272e48SRob Clark #define A4XX_RB_BLEND_BLUE_F32__SHIFT 0 1136a2272e48SRob Clark static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val) 1137a2272e48SRob Clark { 1138a2272e48SRob Clark return ((fui(val)) << A4XX_RB_BLEND_BLUE_F32__SHIFT) & A4XX_RB_BLEND_BLUE_F32__MASK; 1139a2272e48SRob Clark } 1140a2272e48SRob Clark 11418a264743SRob Clark #define REG_A4XX_RB_BLEND_ALPHA 0x000020f6 1142a2272e48SRob Clark #define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x0000ffff 11438a264743SRob Clark #define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0 11448a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val) 11458a264743SRob Clark { 11468a264743SRob Clark return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK; 11478a264743SRob Clark } 11488a264743SRob Clark #define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 11498a264743SRob Clark #define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 11508a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val) 11518a264743SRob Clark { 11528a264743SRob Clark return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK; 11538a264743SRob Clark } 11548a264743SRob Clark 1155a2272e48SRob Clark #define REG_A4XX_RB_BLEND_ALPHA_F32 0x000020f7 1156a2272e48SRob Clark #define A4XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff 1157a2272e48SRob Clark #define A4XX_RB_BLEND_ALPHA_F32__SHIFT 0 1158a2272e48SRob Clark static inline uint32_t A4XX_RB_BLEND_ALPHA_F32(float val) 1159a2272e48SRob Clark { 1160a2272e48SRob Clark return ((fui(val)) << A4XX_RB_BLEND_ALPHA_F32__SHIFT) & A4XX_RB_BLEND_ALPHA_F32__MASK; 1161a2272e48SRob Clark } 1162a2272e48SRob Clark 1163bc00ae02SRob Clark #define REG_A4XX_RB_ALPHA_CONTROL 0x000020f8 11648a264743SRob Clark #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff 11658a264743SRob Clark #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 11668a264743SRob Clark static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) 11678a264743SRob Clark { 11688a264743SRob Clark return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; 11698a264743SRob Clark } 1170bc00ae02SRob Clark #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 1171bc00ae02SRob Clark #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 1172bc00ae02SRob Clark #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 1173bc00ae02SRob Clark static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 1174bc00ae02SRob Clark { 1175bc00ae02SRob Clark return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; 1176bc00ae02SRob Clark } 1177bc00ae02SRob Clark 1178bc00ae02SRob Clark #define REG_A4XX_RB_FS_OUTPUT 0x000020f9 1179af6cb4c1SRob Clark #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK 0x000000ff 1180af6cb4c1SRob Clark #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT 0 1181af6cb4c1SRob Clark static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val) 1182af6cb4c1SRob Clark { 1183af6cb4c1SRob Clark return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK; 1184af6cb4c1SRob Clark } 1185a2272e48SRob Clark #define A4XX_RB_FS_OUTPUT_INDEPENDENT_BLEND 0x00000100 1186bc00ae02SRob Clark #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000 1187bc00ae02SRob Clark #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT 16 1188bc00ae02SRob Clark static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val) 1189bc00ae02SRob Clark { 1190bc00ae02SRob Clark return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK; 1191bc00ae02SRob Clark } 1192bc00ae02SRob Clark 11932d3584ebSRob Clark #define REG_A4XX_RB_SAMPLE_COUNT_CONTROL 0x000020fa 11942d3584ebSRob Clark #define A4XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 11952d3584ebSRob Clark #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK 0xfffffffc 11962d3584ebSRob Clark #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT 2 11972d3584ebSRob Clark static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val) 11982d3584ebSRob Clark { 11992d3584ebSRob Clark return ((val >> 2) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK; 12002d3584ebSRob Clark } 12012d3584ebSRob Clark 1202af6cb4c1SRob Clark #define REG_A4XX_RB_RENDER_COMPONENTS 0x000020fb 1203af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f 1204af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0 1205af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) 1206bc00ae02SRob Clark { 1207af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT0__MASK; 1208af6cb4c1SRob Clark } 1209af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0 1210af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4 1211af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) 1212af6cb4c1SRob Clark { 1213af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT1__MASK; 1214af6cb4c1SRob Clark } 1215af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00 1216af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8 1217af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) 1218af6cb4c1SRob Clark { 1219af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT2__MASK; 1220af6cb4c1SRob Clark } 1221af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000 1222af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12 1223af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) 1224af6cb4c1SRob Clark { 1225af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT3__MASK; 1226af6cb4c1SRob Clark } 1227af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000 1228af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16 1229af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) 1230af6cb4c1SRob Clark { 1231af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT4__MASK; 1232af6cb4c1SRob Clark } 1233af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000 1234af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20 1235af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) 1236af6cb4c1SRob Clark { 1237af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT5__MASK; 1238af6cb4c1SRob Clark } 1239af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000 1240af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24 1241af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) 1242af6cb4c1SRob Clark { 1243af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT6__MASK; 1244af6cb4c1SRob Clark } 1245af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000 1246af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28 1247af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) 1248af6cb4c1SRob Clark { 1249af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT7__MASK; 1250bc00ae02SRob Clark } 1251bc00ae02SRob Clark 1252bc00ae02SRob Clark #define REG_A4XX_RB_COPY_CONTROL 0x000020fc 1253bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003 1254bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0 1255bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) 1256bc00ae02SRob Clark { 1257bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK; 1258bc00ae02SRob Clark } 1259bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_MODE__MASK 0x00000070 1260bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_MODE__SHIFT 4 1261bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) 1262bc00ae02SRob Clark { 1263bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_CONTROL_MODE__SHIFT) & A4XX_RB_COPY_CONTROL_MODE__MASK; 1264bc00ae02SRob Clark } 1265bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00 1266bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8 1267bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) 1268bc00ae02SRob Clark { 1269bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK; 1270bc00ae02SRob Clark } 1271bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000 1272bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14 1273bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) 1274bc00ae02SRob Clark { 1275bc00ae02SRob Clark return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK; 1276bc00ae02SRob Clark } 1277bc00ae02SRob Clark 1278bc00ae02SRob Clark #define REG_A4XX_RB_COPY_DEST_BASE 0x000020fd 12798a264743SRob Clark #define A4XX_RB_COPY_DEST_BASE_BASE__MASK 0xffffffe0 12808a264743SRob Clark #define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT 5 1281bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val) 1282bc00ae02SRob Clark { 12838a264743SRob Clark return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK; 1284bc00ae02SRob Clark } 1285bc00ae02SRob Clark 1286bc00ae02SRob Clark #define REG_A4XX_RB_COPY_DEST_PITCH 0x000020fe 1287bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff 1288bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0 1289bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) 1290bc00ae02SRob Clark { 1291bc00ae02SRob Clark return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK; 1292bc00ae02SRob Clark } 1293bc00ae02SRob Clark 1294bc00ae02SRob Clark #define REG_A4XX_RB_COPY_DEST_INFO 0x000020ff 1295bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc 1296bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2 1297bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val) 1298bc00ae02SRob Clark { 1299bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A4XX_RB_COPY_DEST_INFO_FORMAT__MASK; 1300bc00ae02SRob Clark } 1301bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 1302bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 1303bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) 1304bc00ae02SRob Clark { 1305bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A4XX_RB_COPY_DEST_INFO_SWAP__MASK; 1306bc00ae02SRob Clark } 1307bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 1308bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 1309bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 1310bc00ae02SRob Clark { 1311bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 1312bc00ae02SRob Clark } 1313bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000 1314bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14 1315bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) 1316bc00ae02SRob Clark { 1317bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK; 1318bc00ae02SRob Clark } 1319bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000 1320bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18 1321bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) 1322bc00ae02SRob Clark { 1323bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK; 1324bc00ae02SRob Clark } 1325bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_TILE__MASK 0x03000000 1326bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_TILE__SHIFT 24 1327bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val) 1328bc00ae02SRob Clark { 1329bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A4XX_RB_COPY_DEST_INFO_TILE__MASK; 1330bc00ae02SRob Clark } 1331bc00ae02SRob Clark 1332bc00ae02SRob Clark #define REG_A4XX_RB_FS_OUTPUT_REG 0x00002100 1333af6cb4c1SRob Clark #define A4XX_RB_FS_OUTPUT_REG_MRT__MASK 0x0000000f 1334af6cb4c1SRob Clark #define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT 0 1335af6cb4c1SRob Clark static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val) 1336af6cb4c1SRob Clark { 1337af6cb4c1SRob Clark return ((val) << A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_RB_FS_OUTPUT_REG_MRT__MASK; 1338af6cb4c1SRob Clark } 1339bc00ae02SRob Clark #define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z 0x00000020 1340bc00ae02SRob Clark 1341bc00ae02SRob Clark #define REG_A4XX_RB_DEPTH_CONTROL 0x00002101 1342bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001 1343bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002 1344bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004 1345bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070 1346bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4 1347bc00ae02SRob Clark static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) 1348bc00ae02SRob Clark { 1349bc00ae02SRob Clark return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK; 1350bc00ae02SRob Clark } 1351bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080 1352bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000 1353a2272e48SRob Clark #define A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS 0x00020000 1354bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000 1355bc00ae02SRob Clark 1356bc00ae02SRob Clark #define REG_A4XX_RB_DEPTH_CLEAR 0x00002102 1357bc00ae02SRob Clark 1358bc00ae02SRob Clark #define REG_A4XX_RB_DEPTH_INFO 0x00002103 1359bc00ae02SRob Clark #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003 1360bc00ae02SRob Clark #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 1361bc00ae02SRob Clark static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val) 1362bc00ae02SRob Clark { 1363bc00ae02SRob Clark return ((val) << A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 1364bc00ae02SRob Clark } 1365bc00ae02SRob Clark #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 1366bc00ae02SRob Clark #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 1367bc00ae02SRob Clark static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 1368bc00ae02SRob Clark { 1369bc00ae02SRob Clark return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 1370bc00ae02SRob Clark } 1371bc00ae02SRob Clark 1372bc00ae02SRob Clark #define REG_A4XX_RB_DEPTH_PITCH 0x00002104 1373bc00ae02SRob Clark #define A4XX_RB_DEPTH_PITCH__MASK 0xffffffff 1374bc00ae02SRob Clark #define A4XX_RB_DEPTH_PITCH__SHIFT 0 1375bc00ae02SRob Clark static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val) 1376bc00ae02SRob Clark { 13778a264743SRob Clark return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK; 1378bc00ae02SRob Clark } 1379bc00ae02SRob Clark 1380bc00ae02SRob Clark #define REG_A4XX_RB_DEPTH_PITCH2 0x00002105 1381bc00ae02SRob Clark #define A4XX_RB_DEPTH_PITCH2__MASK 0xffffffff 1382bc00ae02SRob Clark #define A4XX_RB_DEPTH_PITCH2__SHIFT 0 1383bc00ae02SRob Clark static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val) 1384bc00ae02SRob Clark { 13858a264743SRob Clark return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK; 1386bc00ae02SRob Clark } 1387bc00ae02SRob Clark 1388bc00ae02SRob Clark #define REG_A4XX_RB_STENCIL_CONTROL 0x00002106 1389bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 1390bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 1391bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 1392bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 1393bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 1394bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 1395bc00ae02SRob Clark { 1396bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC__MASK; 1397bc00ae02SRob Clark } 1398bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 1399bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 1400bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 1401bc00ae02SRob Clark { 1402bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL__MASK; 1403bc00ae02SRob Clark } 1404bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 1405bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 1406bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 1407bc00ae02SRob Clark { 1408bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS__MASK; 1409bc00ae02SRob Clark } 1410bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 1411bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 1412bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 1413bc00ae02SRob Clark { 1414bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 1415bc00ae02SRob Clark } 1416bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 1417bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 1418bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 1419bc00ae02SRob Clark { 1420bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 1421bc00ae02SRob Clark } 1422bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 1423bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 1424bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 1425bc00ae02SRob Clark { 1426bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 1427bc00ae02SRob Clark } 1428bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 1429bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 1430bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 1431bc00ae02SRob Clark { 1432bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 1433bc00ae02SRob Clark } 1434bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 1435bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 1436bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 1437bc00ae02SRob Clark { 1438bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 1439bc00ae02SRob Clark } 1440bc00ae02SRob Clark 1441bc00ae02SRob Clark #define REG_A4XX_RB_STENCIL_CONTROL2 0x00002107 1442bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER 0x00000001 1443bc00ae02SRob Clark 14442d3584ebSRob Clark #define REG_A4XX_RB_STENCIL_INFO 0x00002108 14452d3584ebSRob Clark #define A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 14462d3584ebSRob Clark #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff000 14472d3584ebSRob Clark #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 12 14482d3584ebSRob Clark static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) 14492d3584ebSRob Clark { 14502d3584ebSRob Clark return ((val >> 12) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK; 14512d3584ebSRob Clark } 14522d3584ebSRob Clark 14532d3584ebSRob Clark #define REG_A4XX_RB_STENCIL_PITCH 0x00002109 14542d3584ebSRob Clark #define A4XX_RB_STENCIL_PITCH__MASK 0xffffffff 14552d3584ebSRob Clark #define A4XX_RB_STENCIL_PITCH__SHIFT 0 14562d3584ebSRob Clark static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val) 14572d3584ebSRob Clark { 14582d3584ebSRob Clark return ((val >> 5) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK; 14592d3584ebSRob Clark } 14602d3584ebSRob Clark 1461bc00ae02SRob Clark #define REG_A4XX_RB_STENCILREFMASK 0x0000210b 1462bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 1463bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 1464bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 1465bc00ae02SRob Clark { 1466bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILREF__MASK; 1467bc00ae02SRob Clark } 1468bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 1469bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 1470bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 1471bc00ae02SRob Clark { 1472bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILMASK__MASK; 1473bc00ae02SRob Clark } 1474bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 1475bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 1476bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 1477bc00ae02SRob Clark { 1478bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 1479bc00ae02SRob Clark } 1480bc00ae02SRob Clark 1481bc00ae02SRob Clark #define REG_A4XX_RB_STENCILREFMASK_BF 0x0000210c 1482bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 1483bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 1484bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 1485bc00ae02SRob Clark { 1486bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 1487bc00ae02SRob Clark } 1488bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 1489bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 1490bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 1491bc00ae02SRob Clark { 1492bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 1493bc00ae02SRob Clark } 1494bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 1495bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 1496bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 1497bc00ae02SRob Clark { 1498bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 1499bc00ae02SRob Clark } 1500bc00ae02SRob Clark 1501bc00ae02SRob Clark #define REG_A4XX_RB_BIN_OFFSET 0x0000210d 1502bc00ae02SRob Clark #define A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 1503bc00ae02SRob Clark #define A4XX_RB_BIN_OFFSET_X__MASK 0x00007fff 1504bc00ae02SRob Clark #define A4XX_RB_BIN_OFFSET_X__SHIFT 0 1505bc00ae02SRob Clark static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val) 1506bc00ae02SRob Clark { 1507bc00ae02SRob Clark return ((val) << A4XX_RB_BIN_OFFSET_X__SHIFT) & A4XX_RB_BIN_OFFSET_X__MASK; 1508bc00ae02SRob Clark } 1509bc00ae02SRob Clark #define A4XX_RB_BIN_OFFSET_Y__MASK 0x7fff0000 1510bc00ae02SRob Clark #define A4XX_RB_BIN_OFFSET_Y__SHIFT 16 1511bc00ae02SRob Clark static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val) 1512bc00ae02SRob Clark { 1513bc00ae02SRob Clark return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK; 1514bc00ae02SRob Clark } 1515bc00ae02SRob Clark 15168a264743SRob Clark static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; } 15178a264743SRob Clark 15188a264743SRob Clark static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; } 15198a264743SRob Clark 15208a264743SRob Clark static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; } 1521bc00ae02SRob Clark 1522bc00ae02SRob Clark #define REG_A4XX_RBBM_HW_VERSION 0x00000000 1523bc00ae02SRob Clark 1524bc00ae02SRob Clark #define REG_A4XX_RBBM_HW_CONFIGURATION 0x00000002 1525bc00ae02SRob Clark 1526bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; } 1527bc00ae02SRob Clark 1528bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; } 1529bc00ae02SRob Clark 1530bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; } 1531bc00ae02SRob Clark 1532bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; } 1533bc00ae02SRob Clark 1534bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; } 1535bc00ae02SRob Clark 1536bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; } 1537bc00ae02SRob Clark 1538bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; } 1539bc00ae02SRob Clark 1540bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; } 1541bc00ae02SRob Clark 1542bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL_UCHE 0x00000014 1543bc00ae02SRob Clark 1544bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL2_UCHE 0x00000015 1545bc00ae02SRob Clark 1546bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL3_UCHE 0x00000016 1547bc00ae02SRob Clark 1548bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL4_UCHE 0x00000017 1549bc00ae02SRob Clark 1550bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_HYST_UCHE 0x00000018 1551bc00ae02SRob Clark 1552bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_DELAY_UCHE 0x00000019 1553bc00ae02SRob Clark 1554bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_MODE_GPC 0x0000001a 1555bc00ae02SRob Clark 1556bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_DELAY_GPC 0x0000001b 1557bc00ae02SRob Clark 1558bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_HYST_GPC 0x0000001c 1559bc00ae02SRob Clark 1560bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM 0x0000001d 1561bc00ae02SRob Clark 1562bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000001e 1563bc00ae02SRob Clark 1564bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x0000001f 1565bc00ae02SRob Clark 1566bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL 0x00000020 1567bc00ae02SRob Clark 1568bc00ae02SRob Clark #define REG_A4XX_RBBM_SP_HYST_CNT 0x00000021 1569bc00ae02SRob Clark 1570bc00ae02SRob Clark #define REG_A4XX_RBBM_SW_RESET_CMD 0x00000022 1571bc00ae02SRob Clark 1572bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_CTL0 0x00000023 1573bc00ae02SRob Clark 1574bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_CTL1 0x00000024 1575bc00ae02SRob Clark 1576bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_CMD 0x00000025 1577bc00ae02SRob Clark 1578bc00ae02SRob Clark #define REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL 0x00000026 1579bc00ae02SRob Clark 1580bc00ae02SRob Clark #define REG_A4XX_RBBM_RAM_ACC_63_32 0x00000028 1581bc00ae02SRob Clark 1582bc00ae02SRob Clark #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x0000002b 1583bc00ae02SRob Clark 1584bc00ae02SRob Clark #define REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL 0x0000002f 1585bc00ae02SRob Clark 1586bc00ae02SRob Clark #define REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4 0x00000034 1587bc00ae02SRob Clark 1588bc00ae02SRob Clark #define REG_A4XX_RBBM_INT_CLEAR_CMD 0x00000036 1589bc00ae02SRob Clark 1590bc00ae02SRob Clark #define REG_A4XX_RBBM_INT_0_MASK 0x00000037 1591bc00ae02SRob Clark 1592bc00ae02SRob Clark #define REG_A4XX_RBBM_RBBM_CTL 0x0000003e 1593bc00ae02SRob Clark 1594bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_DEBUG_CTL 0x0000003f 1595bc00ae02SRob Clark 1596bc00ae02SRob Clark #define REG_A4XX_RBBM_VBIF_DEBUG_CTL 0x00000041 1597bc00ae02SRob Clark 1598bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL2 0x00000042 1599bc00ae02SRob Clark 1600bc00ae02SRob Clark #define REG_A4XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 1601bc00ae02SRob Clark 1602bc00ae02SRob Clark #define REG_A4XX_RBBM_RESET_CYCLES 0x00000047 1603bc00ae02SRob Clark 1604bc00ae02SRob Clark #define REG_A4XX_RBBM_EXT_TRACE_BUS_CTL 0x00000049 1605bc00ae02SRob Clark 1606bc00ae02SRob Clark #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A 0x0000004a 1607bc00ae02SRob Clark 1608bc00ae02SRob Clark #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B 0x0000004b 1609bc00ae02SRob Clark 1610bc00ae02SRob Clark #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C 0x0000004c 1611bc00ae02SRob Clark 1612bc00ae02SRob Clark #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D 0x0000004d 1613bc00ae02SRob Clark 1614a2272e48SRob Clark #define REG_A4XX_RBBM_POWER_CNTL_IP 0x00000098 1615a2272e48SRob Clark #define A4XX_RBBM_POWER_CNTL_IP_SW_COLLAPSE 0x00000001 1616a2272e48SRob Clark #define A4XX_RBBM_POWER_CNTL_IP_SP_TP_PWR_ON 0x00100000 1617a2272e48SRob Clark 1618bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_0_LO 0x0000009c 1619bc00ae02SRob Clark 1620a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_0_HI 0x0000009d 1621a2272e48SRob Clark 1622a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_1_LO 0x0000009e 1623a2272e48SRob Clark 1624a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_1_HI 0x0000009f 1625a2272e48SRob Clark 1626a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_2_LO 0x000000a0 1627a2272e48SRob Clark 1628a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_2_HI 0x000000a1 1629a2272e48SRob Clark 1630a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_3_LO 0x000000a2 1631a2272e48SRob Clark 1632a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_3_HI 0x000000a3 1633a2272e48SRob Clark 1634a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_4_LO 0x000000a4 1635a2272e48SRob Clark 1636a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_4_HI 0x000000a5 1637a2272e48SRob Clark 1638a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_5_LO 0x000000a6 1639a2272e48SRob Clark 1640a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_5_HI 0x000000a7 1641a2272e48SRob Clark 1642a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_6_LO 0x000000a8 1643a2272e48SRob Clark 1644a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_6_HI 0x000000a9 1645a2272e48SRob Clark 1646a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_7_LO 0x000000aa 1647a2272e48SRob Clark 1648a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_7_HI 0x000000ab 1649a2272e48SRob Clark 1650a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_0_LO 0x000000ac 1651a2272e48SRob Clark 1652a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_0_HI 0x000000ad 1653a2272e48SRob Clark 1654a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_1_LO 0x000000ae 1655a2272e48SRob Clark 1656a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_1_HI 0x000000af 1657a2272e48SRob Clark 1658a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_2_LO 0x000000b0 1659a2272e48SRob Clark 1660a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_2_HI 0x000000b1 1661a2272e48SRob Clark 1662a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_3_LO 0x000000b2 1663a2272e48SRob Clark 1664a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_3_HI 0x000000b3 1665a2272e48SRob Clark 1666a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_0_LO 0x000000b4 1667a2272e48SRob Clark 1668a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_0_HI 0x000000b5 1669a2272e48SRob Clark 1670a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_1_LO 0x000000b6 1671a2272e48SRob Clark 1672a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_1_HI 0x000000b7 1673a2272e48SRob Clark 1674a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_2_LO 0x000000b8 1675a2272e48SRob Clark 1676a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_2_HI 0x000000b9 1677a2272e48SRob Clark 1678a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_3_LO 0x000000ba 1679a2272e48SRob Clark 1680a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_3_HI 0x000000bb 1681a2272e48SRob Clark 1682a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_4_LO 0x000000bc 1683a2272e48SRob Clark 1684a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_4_HI 0x000000bd 1685a2272e48SRob Clark 1686a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_5_LO 0x000000be 1687a2272e48SRob Clark 1688a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_5_HI 0x000000bf 1689a2272e48SRob Clark 1690a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_6_LO 0x000000c0 1691a2272e48SRob Clark 1692a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_6_HI 0x000000c1 1693a2272e48SRob Clark 1694a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_7_LO 0x000000c2 1695a2272e48SRob Clark 1696a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PC_7_HI 0x000000c3 1697a2272e48SRob Clark 1698a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_0_LO 0x000000c4 1699a2272e48SRob Clark 1700a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_0_HI 0x000000c5 1701a2272e48SRob Clark 1702a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_1_LO 0x000000c6 1703a2272e48SRob Clark 1704a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_1_HI 0x000000c7 1705a2272e48SRob Clark 1706a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_2_LO 0x000000c8 1707a2272e48SRob Clark 1708a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_2_HI 0x000000c9 1709a2272e48SRob Clark 1710a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_3_LO 0x000000ca 1711a2272e48SRob Clark 1712a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_3_HI 0x000000cb 1713a2272e48SRob Clark 1714a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_4_LO 0x000000cc 1715a2272e48SRob Clark 1716a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_4_HI 0x000000cd 1717a2272e48SRob Clark 1718a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_5_LO 0x000000ce 1719a2272e48SRob Clark 1720a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_5_HI 0x000000cf 1721a2272e48SRob Clark 1722a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_6_LO 0x000000d0 1723a2272e48SRob Clark 1724a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_6_HI 0x000000d1 1725a2272e48SRob Clark 1726a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_7_LO 0x000000d2 1727a2272e48SRob Clark 1728a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VFD_7_HI 0x000000d3 1729a2272e48SRob Clark 1730a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000d4 1731a2272e48SRob Clark 1732a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000d5 1733a2272e48SRob Clark 1734a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000d6 1735a2272e48SRob Clark 1736a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000d7 1737a2272e48SRob Clark 1738a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000d8 1739a2272e48SRob Clark 1740a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000d9 1741a2272e48SRob Clark 1742a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000da 1743a2272e48SRob Clark 1744a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000db 1745a2272e48SRob Clark 1746a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000dc 1747a2272e48SRob Clark 1748a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000dd 1749a2272e48SRob Clark 1750a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000de 1751a2272e48SRob Clark 1752a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000df 1753a2272e48SRob Clark 1754a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_6_LO 0x000000e0 1755a2272e48SRob Clark 1756a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_6_HI 0x000000e1 1757a2272e48SRob Clark 1758a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_7_LO 0x000000e2 1759a2272e48SRob Clark 1760a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_HLSQ_7_HI 0x000000e3 1761a2272e48SRob Clark 1762a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VPC_0_LO 0x000000e4 1763a2272e48SRob Clark 1764a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VPC_0_HI 0x000000e5 1765a2272e48SRob Clark 1766a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VPC_1_LO 0x000000e6 1767a2272e48SRob Clark 1768a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VPC_1_HI 0x000000e7 1769a2272e48SRob Clark 1770a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VPC_2_LO 0x000000e8 1771a2272e48SRob Clark 1772a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VPC_2_HI 0x000000e9 1773a2272e48SRob Clark 1774a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VPC_3_LO 0x000000ea 1775a2272e48SRob Clark 1776a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VPC_3_HI 0x000000eb 1777a2272e48SRob Clark 1778a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CCU_0_LO 0x000000ec 1779a2272e48SRob Clark 1780a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CCU_0_HI 0x000000ed 1781a2272e48SRob Clark 1782a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CCU_1_LO 0x000000ee 1783a2272e48SRob Clark 1784a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CCU_1_HI 0x000000ef 1785a2272e48SRob Clark 1786a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CCU_2_LO 0x000000f0 1787a2272e48SRob Clark 1788a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CCU_2_HI 0x000000f1 1789a2272e48SRob Clark 1790a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CCU_3_LO 0x000000f2 1791a2272e48SRob Clark 1792a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_CCU_3_HI 0x000000f3 1793a2272e48SRob Clark 1794a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TSE_0_LO 0x000000f4 1795a2272e48SRob Clark 1796a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TSE_0_HI 0x000000f5 1797a2272e48SRob Clark 1798a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TSE_1_LO 0x000000f6 1799a2272e48SRob Clark 1800a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TSE_1_HI 0x000000f7 1801a2272e48SRob Clark 1802a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TSE_2_LO 0x000000f8 1803a2272e48SRob Clark 1804a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TSE_2_HI 0x000000f9 1805a2272e48SRob Clark 1806a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TSE_3_LO 0x000000fa 1807a2272e48SRob Clark 1808a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TSE_3_HI 0x000000fb 1809a2272e48SRob Clark 1810a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RAS_0_LO 0x000000fc 1811a2272e48SRob Clark 1812a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RAS_0_HI 0x000000fd 1813a2272e48SRob Clark 1814a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RAS_1_LO 0x000000fe 1815a2272e48SRob Clark 1816a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RAS_1_HI 0x000000ff 1817a2272e48SRob Clark 1818a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RAS_2_LO 0x00000100 1819a2272e48SRob Clark 1820a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RAS_2_HI 0x00000101 1821a2272e48SRob Clark 1822a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RAS_3_LO 0x00000102 1823a2272e48SRob Clark 1824a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RAS_3_HI 0x00000103 1825a2272e48SRob Clark 1826a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_0_LO 0x00000104 1827a2272e48SRob Clark 1828a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_0_HI 0x00000105 1829a2272e48SRob Clark 1830a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_1_LO 0x00000106 1831a2272e48SRob Clark 1832a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_1_HI 0x00000107 1833a2272e48SRob Clark 1834a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_2_LO 0x00000108 1835a2272e48SRob Clark 1836a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_2_HI 0x00000109 1837a2272e48SRob Clark 1838a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_3_LO 0x0000010a 1839a2272e48SRob Clark 1840a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_3_HI 0x0000010b 1841a2272e48SRob Clark 1842a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_4_LO 0x0000010c 1843a2272e48SRob Clark 1844a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_4_HI 0x0000010d 1845a2272e48SRob Clark 1846a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_5_LO 0x0000010e 1847a2272e48SRob Clark 1848a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_5_HI 0x0000010f 1849a2272e48SRob Clark 1850a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_6_LO 0x00000110 1851a2272e48SRob Clark 1852a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_6_HI 0x00000111 1853a2272e48SRob Clark 1854a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_7_LO 0x00000112 1855a2272e48SRob Clark 1856a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_UCHE_7_HI 0x00000113 1857a2272e48SRob Clark 1858a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_0_LO 0x00000114 1859a2272e48SRob Clark 1860a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115 1861a2272e48SRob Clark 1862a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_0_LO 0x00000114 1863a2272e48SRob Clark 1864a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115 1865a2272e48SRob Clark 1866a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_1_LO 0x00000116 1867a2272e48SRob Clark 1868a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_1_HI 0x00000117 1869a2272e48SRob Clark 1870a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_2_LO 0x00000118 1871a2272e48SRob Clark 1872a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_2_HI 0x00000119 1873a2272e48SRob Clark 1874a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_3_LO 0x0000011a 1875a2272e48SRob Clark 1876a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_3_HI 0x0000011b 1877a2272e48SRob Clark 1878a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_4_LO 0x0000011c 1879a2272e48SRob Clark 1880a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_4_HI 0x0000011d 1881a2272e48SRob Clark 1882a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_5_LO 0x0000011e 1883a2272e48SRob Clark 1884a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_5_HI 0x0000011f 1885a2272e48SRob Clark 1886a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_6_LO 0x00000120 1887a2272e48SRob Clark 1888a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_6_HI 0x00000121 1889a2272e48SRob Clark 1890a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_7_LO 0x00000122 1891a2272e48SRob Clark 1892a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_TP_7_HI 0x00000123 1893a2272e48SRob Clark 1894a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_0_LO 0x00000124 1895a2272e48SRob Clark 1896a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_0_HI 0x00000125 1897a2272e48SRob Clark 1898a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_1_LO 0x00000126 1899a2272e48SRob Clark 1900a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_1_HI 0x00000127 1901a2272e48SRob Clark 1902a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_2_LO 0x00000128 1903a2272e48SRob Clark 1904a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_2_HI 0x00000129 1905a2272e48SRob Clark 1906a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_3_LO 0x0000012a 1907a2272e48SRob Clark 1908a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_3_HI 0x0000012b 1909a2272e48SRob Clark 1910a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_4_LO 0x0000012c 1911a2272e48SRob Clark 1912a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_4_HI 0x0000012d 1913a2272e48SRob Clark 1914a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_5_LO 0x0000012e 1915a2272e48SRob Clark 1916a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_5_HI 0x0000012f 1917a2272e48SRob Clark 1918a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_6_LO 0x00000130 1919a2272e48SRob Clark 1920a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_6_HI 0x00000131 1921a2272e48SRob Clark 1922a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_7_LO 0x00000132 1923a2272e48SRob Clark 1924a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_7_HI 0x00000133 1925a2272e48SRob Clark 1926a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_8_LO 0x00000134 1927a2272e48SRob Clark 1928a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_8_HI 0x00000135 1929a2272e48SRob Clark 1930a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_9_LO 0x00000136 1931a2272e48SRob Clark 1932a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_9_HI 0x00000137 1933a2272e48SRob Clark 1934a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_10_LO 0x00000138 1935a2272e48SRob Clark 1936a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_10_HI 0x00000139 1937a2272e48SRob Clark 1938a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_11_LO 0x0000013a 1939a2272e48SRob Clark 1940a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_SP_11_HI 0x0000013b 1941a2272e48SRob Clark 1942a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_0_LO 0x0000013c 1943a2272e48SRob Clark 1944a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_0_HI 0x0000013d 1945a2272e48SRob Clark 1946a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_1_LO 0x0000013e 1947a2272e48SRob Clark 1948a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_1_HI 0x0000013f 1949a2272e48SRob Clark 1950a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_2_LO 0x00000140 1951a2272e48SRob Clark 1952a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_2_HI 0x00000141 1953a2272e48SRob Clark 1954a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_3_LO 0x00000142 1955a2272e48SRob Clark 1956a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_3_HI 0x00000143 1957a2272e48SRob Clark 1958a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_4_LO 0x00000144 1959a2272e48SRob Clark 1960a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_4_HI 0x00000145 1961a2272e48SRob Clark 1962a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_5_LO 0x00000146 1963a2272e48SRob Clark 1964a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_5_HI 0x00000147 1965a2272e48SRob Clark 1966a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_6_LO 0x00000148 1967a2272e48SRob Clark 1968a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_6_HI 0x00000149 1969a2272e48SRob Clark 1970a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_7_LO 0x0000014a 1971a2272e48SRob Clark 1972a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RB_7_HI 0x0000014b 1973a2272e48SRob Clark 1974a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VSC_0_LO 0x0000014c 1975a2272e48SRob Clark 1976a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VSC_0_HI 0x0000014d 1977a2272e48SRob Clark 1978a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VSC_1_LO 0x0000014e 1979a2272e48SRob Clark 1980a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_VSC_1_HI 0x0000014f 1981a2272e48SRob Clark 1982a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PWR_0_LO 0x00000166 1983a2272e48SRob Clark 1984a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PWR_0_HI 0x00000167 1985a2272e48SRob Clark 1986a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168 1987a2272e48SRob Clark 1988a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_PWR_1_HI 0x00000169 1989a2272e48SRob Clark 1990a2272e48SRob Clark #define REG_A4XX_RBBM_ALWAYSON_COUNTER_LO 0x0000016e 1991a2272e48SRob Clark 1992a2272e48SRob Clark #define REG_A4XX_RBBM_ALWAYSON_COUNTER_HI 0x0000016f 1993a2272e48SRob Clark 1994bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; } 1995bc00ae02SRob Clark 1996bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; } 1997bc00ae02SRob Clark 1998bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; } 1999bc00ae02SRob Clark 2000bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; } 2001bc00ae02SRob Clark 2002bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; } 2003bc00ae02SRob Clark 2004bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; } 2005bc00ae02SRob Clark 2006bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; } 2007bc00ae02SRob Clark 2008bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; } 2009bc00ae02SRob Clark 2010bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; } 2011bc00ae02SRob Clark 2012bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; } 2013bc00ae02SRob Clark 2014bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; } 2015bc00ae02SRob Clark 2016bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; } 2017bc00ae02SRob Clark 2018bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; } 2019bc00ae02SRob Clark 2020bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; } 2021bc00ae02SRob Clark 2022bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; } 2023bc00ae02SRob Clark 2024bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; } 2025bc00ae02SRob Clark 2026bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM 0x00000080 2027bc00ae02SRob Clark 2028bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM 0x00000081 2029bc00ae02SRob Clark 2030bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL_HLSQ 0x0000008a 2031bc00ae02SRob Clark 2032bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_HYST_HLSQ 0x0000008b 2033bc00ae02SRob Clark 2034bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ 0x0000008c 2035bc00ae02SRob Clark 2036bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM 0x0000008d 2037bc00ae02SRob Clark 2038bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; } 2039bc00ae02SRob Clark 2040bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; } 2041bc00ae02SRob Clark 2042a2272e48SRob Clark #define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0 0x00000099 2043a2272e48SRob Clark 2044a2272e48SRob Clark #define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1 0x0000009a 2045a2272e48SRob Clark 2046bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168 2047bc00ae02SRob Clark 2048bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170 2049bc00ae02SRob Clark 2050bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0 0x00000171 2051bc00ae02SRob Clark 2052bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1 0x00000172 2053bc00ae02SRob Clark 2054bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2 0x00000173 2055bc00ae02SRob Clark 2056bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000174 2057bc00ae02SRob Clark 2058bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000175 2059bc00ae02SRob Clark 2060a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000176 2061a2272e48SRob Clark 2062a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000177 2063a2272e48SRob Clark 2064a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000178 2065a2272e48SRob Clark 2066a2272e48SRob Clark #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_3 0x00000179 2067a2272e48SRob Clark 2068bc00ae02SRob Clark #define REG_A4XX_RBBM_GPU_BUSY_MASKED 0x0000017a 2069bc00ae02SRob Clark 2070bc00ae02SRob Clark #define REG_A4XX_RBBM_INT_0_STATUS 0x0000017d 2071bc00ae02SRob Clark 2072bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_STATUS 0x00000182 2073bc00ae02SRob Clark 2074bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_STATUS 0x00000189 2075bc00ae02SRob Clark 2076bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS 0x0000018c 2077bc00ae02SRob Clark 2078bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS 0x0000018d 2079bc00ae02SRob Clark 2080bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_ERROR_STATUS 0x0000018f 2081bc00ae02SRob Clark 2082bc00ae02SRob Clark #define REG_A4XX_RBBM_STATUS 0x00000191 2083bc00ae02SRob Clark #define A4XX_RBBM_STATUS_HI_BUSY 0x00000001 2084bc00ae02SRob Clark #define A4XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 2085bc00ae02SRob Clark #define A4XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 2086bc00ae02SRob Clark #define A4XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000 2087bc00ae02SRob Clark #define A4XX_RBBM_STATUS_VBIF_BUSY 0x00008000 2088bc00ae02SRob Clark #define A4XX_RBBM_STATUS_TSE_BUSY 0x00010000 2089bc00ae02SRob Clark #define A4XX_RBBM_STATUS_RAS_BUSY 0x00020000 2090bc00ae02SRob Clark #define A4XX_RBBM_STATUS_RB_BUSY 0x00040000 2091bc00ae02SRob Clark #define A4XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 2092bc00ae02SRob Clark #define A4XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 2093bc00ae02SRob Clark #define A4XX_RBBM_STATUS_VFD_BUSY 0x00200000 2094bc00ae02SRob Clark #define A4XX_RBBM_STATUS_VPC_BUSY 0x00400000 2095bc00ae02SRob Clark #define A4XX_RBBM_STATUS_UCHE_BUSY 0x00800000 2096bc00ae02SRob Clark #define A4XX_RBBM_STATUS_SP_BUSY 0x01000000 2097bc00ae02SRob Clark #define A4XX_RBBM_STATUS_TPL1_BUSY 0x02000000 2098bc00ae02SRob Clark #define A4XX_RBBM_STATUS_MARB_BUSY 0x04000000 2099bc00ae02SRob Clark #define A4XX_RBBM_STATUS_VSC_BUSY 0x08000000 2100bc00ae02SRob Clark #define A4XX_RBBM_STATUS_ARB_BUSY 0x10000000 2101bc00ae02SRob Clark #define A4XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 2102bc00ae02SRob Clark #define A4XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000 2103bc00ae02SRob Clark #define A4XX_RBBM_STATUS_GPU_BUSY 0x80000000 2104bc00ae02SRob Clark 2105bc00ae02SRob Clark #define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5 0x0000019f 2106bc00ae02SRob Clark 2107a2272e48SRob Clark #define REG_A4XX_RBBM_POWER_STATUS 0x000001b0 2108a2272e48SRob Clark #define A4XX_RBBM_POWER_STATUS_SP_TP_PWR_ON 0x00100000 2109a2272e48SRob Clark 2110a2272e48SRob Clark #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2 0x000001b8 2111a2272e48SRob Clark 2112bc00ae02SRob Clark #define REG_A4XX_CP_SCRATCH_UMASK 0x00000228 2113bc00ae02SRob Clark 2114bc00ae02SRob Clark #define REG_A4XX_CP_SCRATCH_ADDR 0x00000229 2115bc00ae02SRob Clark 2116bc00ae02SRob Clark #define REG_A4XX_CP_RB_BASE 0x00000200 2117bc00ae02SRob Clark 2118bc00ae02SRob Clark #define REG_A4XX_CP_RB_CNTL 0x00000201 2119bc00ae02SRob Clark 2120bc00ae02SRob Clark #define REG_A4XX_CP_RB_WPTR 0x00000205 2121bc00ae02SRob Clark 2122bc00ae02SRob Clark #define REG_A4XX_CP_RB_RPTR_ADDR 0x00000203 2123bc00ae02SRob Clark 2124bc00ae02SRob Clark #define REG_A4XX_CP_RB_RPTR 0x00000204 2125bc00ae02SRob Clark 2126bc00ae02SRob Clark #define REG_A4XX_CP_IB1_BASE 0x00000206 2127bc00ae02SRob Clark 2128bc00ae02SRob Clark #define REG_A4XX_CP_IB1_BUFSZ 0x00000207 2129bc00ae02SRob Clark 2130bc00ae02SRob Clark #define REG_A4XX_CP_IB2_BASE 0x00000208 2131bc00ae02SRob Clark 2132bc00ae02SRob Clark #define REG_A4XX_CP_IB2_BUFSZ 0x00000209 2133bc00ae02SRob Clark 2134af6cb4c1SRob Clark #define REG_A4XX_CP_ME_NRT_ADDR 0x0000020c 2135af6cb4c1SRob Clark 2136af6cb4c1SRob Clark #define REG_A4XX_CP_ME_NRT_DATA 0x0000020d 2137af6cb4c1SRob Clark 2138bc00ae02SRob Clark #define REG_A4XX_CP_ME_RB_DONE_DATA 0x00000217 2139bc00ae02SRob Clark 2140bc00ae02SRob Clark #define REG_A4XX_CP_QUEUE_THRESH2 0x00000219 2141bc00ae02SRob Clark 2142bc00ae02SRob Clark #define REG_A4XX_CP_MERCIU_SIZE 0x0000021b 2143bc00ae02SRob Clark 2144bc00ae02SRob Clark #define REG_A4XX_CP_ROQ_ADDR 0x0000021c 2145bc00ae02SRob Clark 2146bc00ae02SRob Clark #define REG_A4XX_CP_ROQ_DATA 0x0000021d 2147bc00ae02SRob Clark 2148bc00ae02SRob Clark #define REG_A4XX_CP_MEQ_ADDR 0x0000021e 2149bc00ae02SRob Clark 2150bc00ae02SRob Clark #define REG_A4XX_CP_MEQ_DATA 0x0000021f 2151bc00ae02SRob Clark 2152bc00ae02SRob Clark #define REG_A4XX_CP_MERCIU_ADDR 0x00000220 2153bc00ae02SRob Clark 2154bc00ae02SRob Clark #define REG_A4XX_CP_MERCIU_DATA 0x00000221 2155bc00ae02SRob Clark 2156bc00ae02SRob Clark #define REG_A4XX_CP_MERCIU_DATA2 0x00000222 2157bc00ae02SRob Clark 2158bc00ae02SRob Clark #define REG_A4XX_CP_PFP_UCODE_ADDR 0x00000223 2159bc00ae02SRob Clark 2160bc00ae02SRob Clark #define REG_A4XX_CP_PFP_UCODE_DATA 0x00000224 2161bc00ae02SRob Clark 2162bc00ae02SRob Clark #define REG_A4XX_CP_ME_RAM_WADDR 0x00000225 2163bc00ae02SRob Clark 2164bc00ae02SRob Clark #define REG_A4XX_CP_ME_RAM_RADDR 0x00000226 2165bc00ae02SRob Clark 2166bc00ae02SRob Clark #define REG_A4XX_CP_ME_RAM_DATA 0x00000227 2167bc00ae02SRob Clark 2168bc00ae02SRob Clark #define REG_A4XX_CP_PREEMPT 0x0000022a 2169bc00ae02SRob Clark 2170bc00ae02SRob Clark #define REG_A4XX_CP_CNTL 0x0000022c 2171bc00ae02SRob Clark 2172bc00ae02SRob Clark #define REG_A4XX_CP_ME_CNTL 0x0000022d 2173bc00ae02SRob Clark 2174bc00ae02SRob Clark #define REG_A4XX_CP_DEBUG 0x0000022e 2175bc00ae02SRob Clark 2176bc00ae02SRob Clark #define REG_A4XX_CP_DEBUG_ECO_CONTROL 0x00000231 2177bc00ae02SRob Clark 2178bc00ae02SRob Clark #define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232 2179bc00ae02SRob Clark 2180bc00ae02SRob Clark #define REG_A4XX_CP_PROTECT_REG_0 0x00000240 2181bc00ae02SRob Clark 2182bc00ae02SRob Clark static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; } 2183bc00ae02SRob Clark 2184bc00ae02SRob Clark static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; } 2185bc00ae02SRob Clark 2186bc00ae02SRob Clark #define REG_A4XX_CP_PROTECT_CTRL 0x00000250 2187bc00ae02SRob Clark 2188bc00ae02SRob Clark #define REG_A4XX_CP_ST_BASE 0x000004c0 2189bc00ae02SRob Clark 2190bc00ae02SRob Clark #define REG_A4XX_CP_STQ_AVAIL 0x000004ce 2191bc00ae02SRob Clark 2192bc00ae02SRob Clark #define REG_A4XX_CP_MERCIU_STAT 0x000004d0 2193bc00ae02SRob Clark 2194bc00ae02SRob Clark #define REG_A4XX_CP_WFI_PEND_CTR 0x000004d2 2195bc00ae02SRob Clark 2196bc00ae02SRob Clark #define REG_A4XX_CP_HW_FAULT 0x000004d8 2197bc00ae02SRob Clark 2198bc00ae02SRob Clark #define REG_A4XX_CP_PROTECT_STATUS 0x000004da 2199bc00ae02SRob Clark 2200bc00ae02SRob Clark #define REG_A4XX_CP_EVENTS_IN_FLIGHT 0x000004dd 2201bc00ae02SRob Clark 2202bc00ae02SRob Clark #define REG_A4XX_CP_PERFCTR_CP_SEL_0 0x00000500 2203bc00ae02SRob Clark 2204a2272e48SRob Clark #define REG_A4XX_CP_PERFCTR_CP_SEL_1 0x00000501 2205a2272e48SRob Clark 2206a2272e48SRob Clark #define REG_A4XX_CP_PERFCTR_CP_SEL_2 0x00000502 2207a2272e48SRob Clark 2208a2272e48SRob Clark #define REG_A4XX_CP_PERFCTR_CP_SEL_3 0x00000503 2209a2272e48SRob Clark 2210a2272e48SRob Clark #define REG_A4XX_CP_PERFCTR_CP_SEL_4 0x00000504 2211a2272e48SRob Clark 2212a2272e48SRob Clark #define REG_A4XX_CP_PERFCTR_CP_SEL_5 0x00000505 2213a2272e48SRob Clark 2214a2272e48SRob Clark #define REG_A4XX_CP_PERFCTR_CP_SEL_6 0x00000506 2215a2272e48SRob Clark 2216a2272e48SRob Clark #define REG_A4XX_CP_PERFCTR_CP_SEL_7 0x00000507 2217a2272e48SRob Clark 2218bc00ae02SRob Clark #define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b 2219bc00ae02SRob Clark 2220bc00ae02SRob Clark static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; } 2221bc00ae02SRob Clark 2222bc00ae02SRob Clark static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; } 2223bc00ae02SRob Clark 2224bc00ae02SRob Clark #define REG_A4XX_SP_VS_STATUS 0x00000ec0 2225bc00ae02SRob Clark 2226af6cb4c1SRob Clark #define REG_A4XX_SP_MODE_CONTROL 0x00000ec3 2227af6cb4c1SRob Clark 2228a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_0 0x00000ec4 2229a2272e48SRob Clark 2230a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_1 0x00000ec5 2231a2272e48SRob Clark 2232a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_2 0x00000ec6 2233a2272e48SRob Clark 2234a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_3 0x00000ec7 2235a2272e48SRob Clark 2236a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_4 0x00000ec8 2237a2272e48SRob Clark 2238a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_5 0x00000ec9 2239a2272e48SRob Clark 2240a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_6 0x00000eca 2241a2272e48SRob Clark 2242a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_7 0x00000ecb 2243a2272e48SRob Clark 2244a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_8 0x00000ecc 2245a2272e48SRob Clark 2246a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_9 0x00000ecd 2247a2272e48SRob Clark 2248a2272e48SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_10 0x00000ece 2249a2272e48SRob Clark 2250bc00ae02SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_11 0x00000ecf 2251bc00ae02SRob Clark 2252bc00ae02SRob Clark #define REG_A4XX_SP_SP_CTRL_REG 0x000022c0 2253bc00ae02SRob Clark #define A4XX_SP_SP_CTRL_REG_BINNING_PASS 0x00080000 2254bc00ae02SRob Clark 2255bc00ae02SRob Clark #define REG_A4XX_SP_INSTR_CACHE_CTRL 0x000022c1 2256af6cb4c1SRob Clark #define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER 0x00000080 2257af6cb4c1SRob Clark #define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER 0x00000100 2258af6cb4c1SRob Clark #define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER 0x00000400 2259bc00ae02SRob Clark 2260bc00ae02SRob Clark #define REG_A4XX_SP_VS_CTRL_REG0 0x000022c4 2261bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 2262bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 2263bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 2264bc00ae02SRob Clark { 2265bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK; 2266bc00ae02SRob Clark } 2267bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_VARYING 0x00000002 2268bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004 2269bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 2270bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 2271bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 2272bc00ae02SRob Clark { 2273bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 2274bc00ae02SRob Clark } 2275bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 2276bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 2277bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 2278bc00ae02SRob Clark { 2279bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 2280bc00ae02SRob Clark } 2281bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 2282bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 2283bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 2284bc00ae02SRob Clark { 2285bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK; 2286bc00ae02SRob Clark } 2287bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000 2288bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20 2289bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 2290bc00ae02SRob Clark { 2291bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; 2292bc00ae02SRob Clark } 2293bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000 2294bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000 2295bc00ae02SRob Clark 2296bc00ae02SRob Clark #define REG_A4XX_SP_VS_CTRL_REG1 0x000022c5 2297bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff 2298bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0 2299bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) 2300bc00ae02SRob Clark { 2301bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK; 2302bc00ae02SRob Clark } 2303bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000 2304bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24 2305bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) 2306bc00ae02SRob Clark { 2307bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK; 2308bc00ae02SRob Clark } 2309bc00ae02SRob Clark 2310bc00ae02SRob Clark #define REG_A4XX_SP_VS_PARAM_REG 0x000022c6 2311bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff 2312bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0 2313bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) 2314bc00ae02SRob Clark { 2315bc00ae02SRob Clark return ((val) << A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_POSREGID__MASK; 2316bc00ae02SRob Clark } 2317bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00 2318bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8 2319bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) 2320bc00ae02SRob Clark { 2321bc00ae02SRob Clark return ((val) << A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK; 2322bc00ae02SRob Clark } 2323bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000 2324bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20 2325bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) 2326bc00ae02SRob Clark { 2327bc00ae02SRob Clark return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; 2328bc00ae02SRob Clark } 2329bc00ae02SRob Clark 2330bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 2331bc00ae02SRob Clark 2332bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 2333bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff 2334bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 2335bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 2336bc00ae02SRob Clark { 2337bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_A_REGID__MASK; 2338bc00ae02SRob Clark } 2339bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00 2340bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9 2341bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 2342bc00ae02SRob Clark { 2343bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 2344bc00ae02SRob Clark } 2345bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000 2346bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 2347bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 2348bc00ae02SRob Clark { 2349bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_B_REGID__MASK; 2350bc00ae02SRob Clark } 2351bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000 2352bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25 2353bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 2354bc00ae02SRob Clark { 2355bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 2356bc00ae02SRob Clark } 2357bc00ae02SRob Clark 2358bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; } 2359bc00ae02SRob Clark 2360bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; } 2361bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 2362bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 2363bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 2364bc00ae02SRob Clark { 2365bc00ae02SRob Clark return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 2366bc00ae02SRob Clark } 2367bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 2368bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 2369bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 2370bc00ae02SRob Clark { 2371bc00ae02SRob Clark return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 2372bc00ae02SRob Clark } 2373bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 2374bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 2375bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 2376bc00ae02SRob Clark { 2377bc00ae02SRob Clark return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 2378bc00ae02SRob Clark } 2379bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 2380bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 2381bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 2382bc00ae02SRob Clark { 2383bc00ae02SRob Clark return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 2384bc00ae02SRob Clark } 2385bc00ae02SRob Clark 2386bc00ae02SRob Clark #define REG_A4XX_SP_VS_OBJ_OFFSET_REG 0x000022e0 2387bc00ae02SRob Clark #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2388bc00ae02SRob Clark #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2389bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2390bc00ae02SRob Clark { 2391bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2392bc00ae02SRob Clark } 2393bc00ae02SRob Clark #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2394bc00ae02SRob Clark #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2395bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2396bc00ae02SRob Clark { 2397bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2398bc00ae02SRob Clark } 2399bc00ae02SRob Clark 2400bc00ae02SRob Clark #define REG_A4XX_SP_VS_OBJ_START 0x000022e1 2401bc00ae02SRob Clark 2402bc00ae02SRob Clark #define REG_A4XX_SP_VS_PVT_MEM_PARAM 0x000022e2 2403bc00ae02SRob Clark 2404bc00ae02SRob Clark #define REG_A4XX_SP_VS_PVT_MEM_ADDR 0x000022e3 2405bc00ae02SRob Clark 2406bc00ae02SRob Clark #define REG_A4XX_SP_VS_LENGTH_REG 0x000022e5 2407bc00ae02SRob Clark 2408bc00ae02SRob Clark #define REG_A4XX_SP_FS_CTRL_REG0 0x000022e8 2409bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 2410bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 2411bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 2412bc00ae02SRob Clark { 2413bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK; 2414bc00ae02SRob Clark } 2415bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_VARYING 0x00000002 2416bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004 2417bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 2418bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 2419bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 2420bc00ae02SRob Clark { 2421bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 2422bc00ae02SRob Clark } 2423bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 2424bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 2425bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 2426bc00ae02SRob Clark { 2427bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 2428bc00ae02SRob Clark } 2429bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 2430bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 2431bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 2432bc00ae02SRob Clark { 2433bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK; 2434bc00ae02SRob Clark } 2435bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 2436bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 2437bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 2438bc00ae02SRob Clark { 2439bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 2440bc00ae02SRob Clark } 2441bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000 2442bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000 2443bc00ae02SRob Clark 2444bc00ae02SRob Clark #define REG_A4XX_SP_FS_CTRL_REG1 0x000022e9 2445bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff 2446bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0 2447bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) 2448bc00ae02SRob Clark { 2449bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK; 2450bc00ae02SRob Clark } 24518a264743SRob Clark #define A4XX_SP_FS_CTRL_REG1_FACENESS 0x00080000 2452bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG1_VARYING 0x00100000 24538a264743SRob Clark #define A4XX_SP_FS_CTRL_REG1_FRAGCOORD 0x00200000 2454bc00ae02SRob Clark 2455bc00ae02SRob Clark #define REG_A4XX_SP_FS_OBJ_OFFSET_REG 0x000022ea 2456bc00ae02SRob Clark #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2457bc00ae02SRob Clark #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2458bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2459bc00ae02SRob Clark { 2460bc00ae02SRob Clark return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2461bc00ae02SRob Clark } 2462bc00ae02SRob Clark #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2463bc00ae02SRob Clark #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2464bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2465bc00ae02SRob Clark { 2466bc00ae02SRob Clark return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2467bc00ae02SRob Clark } 2468bc00ae02SRob Clark 2469bc00ae02SRob Clark #define REG_A4XX_SP_FS_OBJ_START 0x000022eb 2470bc00ae02SRob Clark 2471bc00ae02SRob Clark #define REG_A4XX_SP_FS_PVT_MEM_PARAM 0x000022ec 2472bc00ae02SRob Clark 2473bc00ae02SRob Clark #define REG_A4XX_SP_FS_PVT_MEM_ADDR 0x000022ed 2474bc00ae02SRob Clark 2475bc00ae02SRob Clark #define REG_A4XX_SP_FS_LENGTH_REG 0x000022ef 2476bc00ae02SRob Clark 2477bc00ae02SRob Clark #define REG_A4XX_SP_FS_OUTPUT_REG 0x000022f0 2478af6cb4c1SRob Clark #define A4XX_SP_FS_OUTPUT_REG_MRT__MASK 0x0000000f 2479af6cb4c1SRob Clark #define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0 2480af6cb4c1SRob Clark static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val) 2481af6cb4c1SRob Clark { 2482af6cb4c1SRob Clark return ((val) << A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_SP_FS_OUTPUT_REG_MRT__MASK; 2483af6cb4c1SRob Clark } 2484bc00ae02SRob Clark #define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080 2485bc00ae02SRob Clark #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00 2486bc00ae02SRob Clark #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8 2487bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) 2488bc00ae02SRob Clark { 2489bc00ae02SRob Clark return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK; 2490bc00ae02SRob Clark } 2491af6cb4c1SRob Clark #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK 0xff000000 2492af6cb4c1SRob Clark #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT 24 2493af6cb4c1SRob Clark static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val) 2494af6cb4c1SRob Clark { 2495af6cb4c1SRob Clark return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK; 2496af6cb4c1SRob Clark } 2497bc00ae02SRob Clark 2498bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; } 2499bc00ae02SRob Clark 2500bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; } 2501bc00ae02SRob Clark #define A4XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff 2502bc00ae02SRob Clark #define A4XX_SP_FS_MRT_REG_REGID__SHIFT 0 2503bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val) 2504bc00ae02SRob Clark { 2505bc00ae02SRob Clark return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK; 2506bc00ae02SRob Clark } 2507bc00ae02SRob Clark #define A4XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100 2508bc00ae02SRob Clark #define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK 0x0003f000 2509bc00ae02SRob Clark #define A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT 12 2510bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val) 2511bc00ae02SRob Clark { 2512bc00ae02SRob Clark return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK; 2513bc00ae02SRob Clark } 25142d3584ebSRob Clark #define A4XX_SP_FS_MRT_REG_COLOR_SRGB 0x00040000 2515bc00ae02SRob Clark 2516af6cb4c1SRob Clark #define REG_A4XX_SP_CS_CTRL_REG0 0x00002300 2517af6cb4c1SRob Clark 2518af6cb4c1SRob Clark #define REG_A4XX_SP_CS_OBJ_OFFSET_REG 0x00002301 2519af6cb4c1SRob Clark 2520af6cb4c1SRob Clark #define REG_A4XX_SP_CS_OBJ_START 0x00002302 2521af6cb4c1SRob Clark 2522af6cb4c1SRob Clark #define REG_A4XX_SP_CS_PVT_MEM_PARAM 0x00002303 2523af6cb4c1SRob Clark 2524af6cb4c1SRob Clark #define REG_A4XX_SP_CS_PVT_MEM_ADDR 0x00002304 2525af6cb4c1SRob Clark 2526af6cb4c1SRob Clark #define REG_A4XX_SP_CS_PVT_MEM_SIZE 0x00002305 2527af6cb4c1SRob Clark 2528af6cb4c1SRob Clark #define REG_A4XX_SP_CS_LENGTH_REG 0x00002306 2529af6cb4c1SRob Clark 2530bc00ae02SRob Clark #define REG_A4XX_SP_HS_OBJ_OFFSET_REG 0x0000230d 2531bc00ae02SRob Clark #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2532bc00ae02SRob Clark #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2533bc00ae02SRob Clark static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2534bc00ae02SRob Clark { 2535bc00ae02SRob Clark return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2536bc00ae02SRob Clark } 2537bc00ae02SRob Clark #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2538bc00ae02SRob Clark #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2539bc00ae02SRob Clark static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2540bc00ae02SRob Clark { 2541bc00ae02SRob Clark return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2542bc00ae02SRob Clark } 2543bc00ae02SRob Clark 2544af6cb4c1SRob Clark #define REG_A4XX_SP_HS_OBJ_START 0x0000230e 2545af6cb4c1SRob Clark 2546af6cb4c1SRob Clark #define REG_A4XX_SP_HS_PVT_MEM_PARAM 0x0000230f 2547af6cb4c1SRob Clark 2548af6cb4c1SRob Clark #define REG_A4XX_SP_HS_PVT_MEM_ADDR 0x00002310 2549af6cb4c1SRob Clark 2550af6cb4c1SRob Clark #define REG_A4XX_SP_HS_LENGTH_REG 0x00002312 2551af6cb4c1SRob Clark 25522d3584ebSRob Clark #define REG_A4XX_SP_DS_PARAM_REG 0x0000231a 25532d3584ebSRob Clark #define A4XX_SP_DS_PARAM_REG_POSREGID__MASK 0x000000ff 25542d3584ebSRob Clark #define A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT 0 25552d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val) 25562d3584ebSRob Clark { 25572d3584ebSRob Clark return ((val) << A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_DS_PARAM_REG_POSREGID__MASK; 25582d3584ebSRob Clark } 25592d3584ebSRob Clark #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000 25602d3584ebSRob Clark #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20 25612d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) 25622d3584ebSRob Clark { 25632d3584ebSRob Clark return ((val) << A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK; 25642d3584ebSRob Clark } 25652d3584ebSRob Clark 25662d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; } 25672d3584ebSRob Clark 25682d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; } 25692d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_A_REGID__MASK 0x000001ff 25702d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_A_REGID__SHIFT 0 25712d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val) 25722d3584ebSRob Clark { 25732d3584ebSRob Clark return ((val) << A4XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_A_REGID__MASK; 25742d3584ebSRob Clark } 25752d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00001e00 25762d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 9 25772d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val) 25782d3584ebSRob Clark { 25792d3584ebSRob Clark return ((val) << A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK; 25802d3584ebSRob Clark } 25812d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_B_REGID__MASK 0x01ff0000 25822d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_B_REGID__SHIFT 16 25832d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val) 25842d3584ebSRob Clark { 25852d3584ebSRob Clark return ((val) << A4XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_B_REGID__MASK; 25862d3584ebSRob Clark } 25872d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x1e000000 25882d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 25 25892d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val) 25902d3584ebSRob Clark { 25912d3584ebSRob Clark return ((val) << A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK; 25922d3584ebSRob Clark } 25932d3584ebSRob Clark 25942d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; } 25952d3584ebSRob Clark 25962d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; } 25972d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 25982d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0 25992d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val) 26002d3584ebSRob Clark { 26012d3584ebSRob Clark return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK; 26022d3584ebSRob Clark } 26032d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 26042d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8 26052d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val) 26062d3584ebSRob Clark { 26072d3584ebSRob Clark return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK; 26082d3584ebSRob Clark } 26092d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 26102d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16 26112d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val) 26122d3584ebSRob Clark { 26132d3584ebSRob Clark return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK; 26142d3584ebSRob Clark } 26152d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 26162d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24 26172d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) 26182d3584ebSRob Clark { 26192d3584ebSRob Clark return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK; 26202d3584ebSRob Clark } 26212d3584ebSRob Clark 2622bc00ae02SRob Clark #define REG_A4XX_SP_DS_OBJ_OFFSET_REG 0x00002334 2623bc00ae02SRob Clark #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2624bc00ae02SRob Clark #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2625bc00ae02SRob Clark static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2626bc00ae02SRob Clark { 2627bc00ae02SRob Clark return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2628bc00ae02SRob Clark } 2629bc00ae02SRob Clark #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2630bc00ae02SRob Clark #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2631bc00ae02SRob Clark static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2632bc00ae02SRob Clark { 2633bc00ae02SRob Clark return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2634bc00ae02SRob Clark } 2635bc00ae02SRob Clark 2636af6cb4c1SRob Clark #define REG_A4XX_SP_DS_OBJ_START 0x00002335 2637af6cb4c1SRob Clark 2638af6cb4c1SRob Clark #define REG_A4XX_SP_DS_PVT_MEM_PARAM 0x00002336 2639af6cb4c1SRob Clark 2640af6cb4c1SRob Clark #define REG_A4XX_SP_DS_PVT_MEM_ADDR 0x00002337 2641af6cb4c1SRob Clark 2642af6cb4c1SRob Clark #define REG_A4XX_SP_DS_LENGTH_REG 0x00002339 2643af6cb4c1SRob Clark 26442d3584ebSRob Clark #define REG_A4XX_SP_GS_PARAM_REG 0x00002341 26452d3584ebSRob Clark #define A4XX_SP_GS_PARAM_REG_POSREGID__MASK 0x000000ff 26462d3584ebSRob Clark #define A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT 0 26472d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val) 26482d3584ebSRob Clark { 26492d3584ebSRob Clark return ((val) << A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_POSREGID__MASK; 26502d3584ebSRob Clark } 26512d3584ebSRob Clark #define A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK 0x0000ff00 26522d3584ebSRob Clark #define A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT 8 26532d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val) 26542d3584ebSRob Clark { 26552d3584ebSRob Clark return ((val) << A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK; 26562d3584ebSRob Clark } 26572d3584ebSRob Clark #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000 26582d3584ebSRob Clark #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20 26592d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) 26602d3584ebSRob Clark { 26612d3584ebSRob Clark return ((val) << A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK; 26622d3584ebSRob Clark } 26632d3584ebSRob Clark 26642d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; } 26652d3584ebSRob Clark 26662d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; } 26672d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_A_REGID__MASK 0x000001ff 26682d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_A_REGID__SHIFT 0 26692d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val) 26702d3584ebSRob Clark { 26712d3584ebSRob Clark return ((val) << A4XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_A_REGID__MASK; 26722d3584ebSRob Clark } 26732d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00001e00 26742d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 9 26752d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val) 26762d3584ebSRob Clark { 26772d3584ebSRob Clark return ((val) << A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK; 26782d3584ebSRob Clark } 26792d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_B_REGID__MASK 0x01ff0000 26802d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_B_REGID__SHIFT 16 26812d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val) 26822d3584ebSRob Clark { 26832d3584ebSRob Clark return ((val) << A4XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_B_REGID__MASK; 26842d3584ebSRob Clark } 26852d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x1e000000 26862d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 25 26872d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val) 26882d3584ebSRob Clark { 26892d3584ebSRob Clark return ((val) << A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK; 26902d3584ebSRob Clark } 26912d3584ebSRob Clark 26922d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; } 26932d3584ebSRob Clark 26942d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; } 26952d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 26962d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0 26972d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val) 26982d3584ebSRob Clark { 26992d3584ebSRob Clark return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK; 27002d3584ebSRob Clark } 27012d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 27022d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8 27032d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val) 27042d3584ebSRob Clark { 27052d3584ebSRob Clark return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK; 27062d3584ebSRob Clark } 27072d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 27082d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16 27092d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val) 27102d3584ebSRob Clark { 27112d3584ebSRob Clark return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK; 27122d3584ebSRob Clark } 27132d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 27142d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24 27152d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) 27162d3584ebSRob Clark { 27172d3584ebSRob Clark return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK; 27182d3584ebSRob Clark } 27192d3584ebSRob Clark 2720bc00ae02SRob Clark #define REG_A4XX_SP_GS_OBJ_OFFSET_REG 0x0000235b 2721bc00ae02SRob Clark #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2722bc00ae02SRob Clark #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2723bc00ae02SRob Clark static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2724bc00ae02SRob Clark { 2725bc00ae02SRob Clark return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2726bc00ae02SRob Clark } 2727bc00ae02SRob Clark #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2728bc00ae02SRob Clark #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2729bc00ae02SRob Clark static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2730bc00ae02SRob Clark { 2731bc00ae02SRob Clark return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2732bc00ae02SRob Clark } 2733bc00ae02SRob Clark 2734af6cb4c1SRob Clark #define REG_A4XX_SP_GS_OBJ_START 0x0000235c 2735af6cb4c1SRob Clark 2736af6cb4c1SRob Clark #define REG_A4XX_SP_GS_PVT_MEM_PARAM 0x0000235d 2737af6cb4c1SRob Clark 2738af6cb4c1SRob Clark #define REG_A4XX_SP_GS_PVT_MEM_ADDR 0x0000235e 2739af6cb4c1SRob Clark 2740bc00ae02SRob Clark #define REG_A4XX_SP_GS_LENGTH_REG 0x00002360 2741bc00ae02SRob Clark 2742bc00ae02SRob Clark #define REG_A4XX_VPC_DEBUG_RAM_SEL 0x00000e60 2743bc00ae02SRob Clark 2744bc00ae02SRob Clark #define REG_A4XX_VPC_DEBUG_RAM_READ 0x00000e61 2745bc00ae02SRob Clark 2746bc00ae02SRob Clark #define REG_A4XX_VPC_DEBUG_ECO_CONTROL 0x00000e64 2747bc00ae02SRob Clark 2748a2272e48SRob Clark #define REG_A4XX_VPC_PERFCTR_VPC_SEL_0 0x00000e65 2749a2272e48SRob Clark 2750a2272e48SRob Clark #define REG_A4XX_VPC_PERFCTR_VPC_SEL_1 0x00000e66 2751a2272e48SRob Clark 2752a2272e48SRob Clark #define REG_A4XX_VPC_PERFCTR_VPC_SEL_2 0x00000e67 2753a2272e48SRob Clark 2754bc00ae02SRob Clark #define REG_A4XX_VPC_PERFCTR_VPC_SEL_3 0x00000e68 2755bc00ae02SRob Clark 2756bc00ae02SRob Clark #define REG_A4XX_VPC_ATTR 0x00002140 2757bc00ae02SRob Clark #define A4XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff 2758bc00ae02SRob Clark #define A4XX_VPC_ATTR_TOTALATTR__SHIFT 0 2759bc00ae02SRob Clark static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val) 2760bc00ae02SRob Clark { 2761bc00ae02SRob Clark return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK; 2762bc00ae02SRob Clark } 2763bc00ae02SRob Clark #define A4XX_VPC_ATTR_PSIZE 0x00000200 2764bc00ae02SRob Clark #define A4XX_VPC_ATTR_THRDASSIGN__MASK 0x00003000 2765bc00ae02SRob Clark #define A4XX_VPC_ATTR_THRDASSIGN__SHIFT 12 2766bc00ae02SRob Clark static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val) 2767bc00ae02SRob Clark { 2768bc00ae02SRob Clark return ((val) << A4XX_VPC_ATTR_THRDASSIGN__SHIFT) & A4XX_VPC_ATTR_THRDASSIGN__MASK; 2769bc00ae02SRob Clark } 2770bc00ae02SRob Clark #define A4XX_VPC_ATTR_ENABLE 0x02000000 2771bc00ae02SRob Clark 2772bc00ae02SRob Clark #define REG_A4XX_VPC_PACK 0x00002141 2773bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMBYPASSVAR__MASK 0x000000ff 2774bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT 0 2775bc00ae02SRob Clark static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val) 2776bc00ae02SRob Clark { 2777bc00ae02SRob Clark return ((val) << A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT) & A4XX_VPC_PACK_NUMBYPASSVAR__MASK; 2778bc00ae02SRob Clark } 2779bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00 2780bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8 2781bc00ae02SRob Clark static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) 2782bc00ae02SRob Clark { 2783bc00ae02SRob Clark return ((val) << A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK; 2784bc00ae02SRob Clark } 2785bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000 2786bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16 2787bc00ae02SRob Clark static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) 2788bc00ae02SRob Clark { 2789bc00ae02SRob Clark return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK; 2790bc00ae02SRob Clark } 2791bc00ae02SRob Clark 2792bc00ae02SRob Clark static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; } 2793bc00ae02SRob Clark 2794bc00ae02SRob Clark static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; } 2795bc00ae02SRob Clark 2796bc00ae02SRob Clark static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; } 2797bc00ae02SRob Clark 2798bc00ae02SRob Clark static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; } 2799bc00ae02SRob Clark 2800bc00ae02SRob Clark #define REG_A4XX_VPC_SO_FLUSH_WADDR_3 0x0000216e 2801bc00ae02SRob Clark 2802bc00ae02SRob Clark #define REG_A4XX_VSC_BIN_SIZE 0x00000c00 2803bc00ae02SRob Clark #define A4XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 2804bc00ae02SRob Clark #define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 2805bc00ae02SRob Clark static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 2806bc00ae02SRob Clark { 2807bc00ae02SRob Clark return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK; 2808bc00ae02SRob Clark } 2809bc00ae02SRob Clark #define A4XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 2810bc00ae02SRob Clark #define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5 2811bc00ae02SRob Clark static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 2812bc00ae02SRob Clark { 2813bc00ae02SRob Clark return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK; 2814bc00ae02SRob Clark } 2815bc00ae02SRob Clark 2816bc00ae02SRob Clark #define REG_A4XX_VSC_SIZE_ADDRESS 0x00000c01 2817bc00ae02SRob Clark 2818bc00ae02SRob Clark #define REG_A4XX_VSC_SIZE_ADDRESS2 0x00000c02 2819bc00ae02SRob Clark 2820bc00ae02SRob Clark #define REG_A4XX_VSC_DEBUG_ECO_CONTROL 0x00000c03 2821bc00ae02SRob Clark 2822bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } 2823bc00ae02SRob Clark 2824bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } 2825bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff 2826bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0 2827bc00ae02SRob Clark static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) 2828bc00ae02SRob Clark { 2829bc00ae02SRob Clark return ((val) << A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_X__MASK; 2830bc00ae02SRob Clark } 2831bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00 2832bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10 2833bc00ae02SRob Clark static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) 2834bc00ae02SRob Clark { 2835bc00ae02SRob Clark return ((val) << A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_Y__MASK; 2836bc00ae02SRob Clark } 2837bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000 2838bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20 2839bc00ae02SRob Clark static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) 2840bc00ae02SRob Clark { 2841bc00ae02SRob Clark return ((val) << A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_W__MASK; 2842bc00ae02SRob Clark } 2843bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000 2844bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24 2845bc00ae02SRob Clark static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) 2846bc00ae02SRob Clark { 2847bc00ae02SRob Clark return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK; 2848bc00ae02SRob Clark } 2849bc00ae02SRob Clark 2850bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 2851bc00ae02SRob Clark 2852bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 2853bc00ae02SRob Clark 2854bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; } 2855bc00ae02SRob Clark 2856bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; } 2857bc00ae02SRob Clark 2858bc00ae02SRob Clark #define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1 0x00000c41 2859bc00ae02SRob Clark 2860bc00ae02SRob Clark #define REG_A4XX_VSC_PERFCTR_VSC_SEL_0 0x00000c50 2861bc00ae02SRob Clark 2862bc00ae02SRob Clark #define REG_A4XX_VSC_PERFCTR_VSC_SEL_1 0x00000c51 2863bc00ae02SRob Clark 2864bc00ae02SRob Clark #define REG_A4XX_VFD_DEBUG_CONTROL 0x00000e40 2865bc00ae02SRob Clark 2866a2272e48SRob Clark #define REG_A4XX_VFD_PERFCTR_VFD_SEL_0 0x00000e43 2867a2272e48SRob Clark 2868a2272e48SRob Clark #define REG_A4XX_VFD_PERFCTR_VFD_SEL_1 0x00000e44 2869a2272e48SRob Clark 2870a2272e48SRob Clark #define REG_A4XX_VFD_PERFCTR_VFD_SEL_2 0x00000e45 2871a2272e48SRob Clark 2872a2272e48SRob Clark #define REG_A4XX_VFD_PERFCTR_VFD_SEL_3 0x00000e46 2873a2272e48SRob Clark 2874a2272e48SRob Clark #define REG_A4XX_VFD_PERFCTR_VFD_SEL_4 0x00000e47 2875a2272e48SRob Clark 2876a2272e48SRob Clark #define REG_A4XX_VFD_PERFCTR_VFD_SEL_5 0x00000e48 2877a2272e48SRob Clark 2878a2272e48SRob Clark #define REG_A4XX_VFD_PERFCTR_VFD_SEL_6 0x00000e49 2879a2272e48SRob Clark 2880bc00ae02SRob Clark #define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 0x00000e4a 2881bc00ae02SRob Clark 2882af6cb4c1SRob Clark #define REG_A4XX_VGT_CL_INITIATOR 0x000021d0 2883af6cb4c1SRob Clark 2884af6cb4c1SRob Clark #define REG_A4XX_VGT_EVENT_INITIATOR 0x000021d9 2885af6cb4c1SRob Clark 2886bc00ae02SRob Clark #define REG_A4XX_VFD_CONTROL_0 0x00002200 2887bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x000000ff 2888bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0 2889bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) 2890bc00ae02SRob Clark { 2891bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK; 2892bc00ae02SRob Clark } 2893bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK 0x0001fe00 2894bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT 9 2895bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val) 2896bc00ae02SRob Clark { 2897bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT) & A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK; 2898bc00ae02SRob Clark } 2899bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x03f00000 2900bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 20 2901bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) 2902bc00ae02SRob Clark { 2903bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK; 2904bc00ae02SRob Clark } 2905bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xfc000000 2906bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 26 2907bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) 2908bc00ae02SRob Clark { 2909bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK; 2910bc00ae02SRob Clark } 2911bc00ae02SRob Clark 2912bc00ae02SRob Clark #define REG_A4XX_VFD_CONTROL_1 0x00002201 2913bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff 2914bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0 2915bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) 2916bc00ae02SRob Clark { 2917bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK; 2918bc00ae02SRob Clark } 2919bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000 2920bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16 2921bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 2922bc00ae02SRob Clark { 2923bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A4XX_VFD_CONTROL_1_REGID4VTX__MASK; 2924bc00ae02SRob Clark } 2925bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000 2926bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_REGID4INST__SHIFT 24 2927bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 2928bc00ae02SRob Clark { 2929bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A4XX_VFD_CONTROL_1_REGID4INST__MASK; 2930bc00ae02SRob Clark } 2931bc00ae02SRob Clark 2932bc00ae02SRob Clark #define REG_A4XX_VFD_CONTROL_2 0x00002202 2933bc00ae02SRob Clark 2934bc00ae02SRob Clark #define REG_A4XX_VFD_CONTROL_3 0x00002203 29358a264743SRob Clark #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK 0x0000ff00 29368a264743SRob Clark #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT 8 29378a264743SRob Clark static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val) 29388a264743SRob Clark { 29398a264743SRob Clark return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK; 29408a264743SRob Clark } 29412d3584ebSRob Clark #define A4XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000 29422d3584ebSRob Clark #define A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16 29432d3584ebSRob Clark static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) 29442d3584ebSRob Clark { 29452d3584ebSRob Clark return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSX__MASK; 29462d3584ebSRob Clark } 29472d3584ebSRob Clark #define A4XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000 29482d3584ebSRob Clark #define A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24 29492d3584ebSRob Clark static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) 29502d3584ebSRob Clark { 29512d3584ebSRob Clark return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSY__MASK; 29522d3584ebSRob Clark } 2953bc00ae02SRob Clark 2954bc00ae02SRob Clark #define REG_A4XX_VFD_CONTROL_4 0x00002204 2955bc00ae02SRob Clark 2956bc00ae02SRob Clark #define REG_A4XX_VFD_INDEX_OFFSET 0x00002208 2957bc00ae02SRob Clark 2958bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; } 2959bc00ae02SRob Clark 2960bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; } 2961bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f 2962bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0 2963bc00ae02SRob Clark static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) 2964bc00ae02SRob Clark { 2965bc00ae02SRob Clark return ((val) << A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK; 2966bc00ae02SRob Clark } 2967bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80 2968bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7 2969bc00ae02SRob Clark static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) 2970bc00ae02SRob Clark { 2971bc00ae02SRob Clark return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK; 2972bc00ae02SRob Clark } 2973bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00080000 29748a264743SRob Clark #define A4XX_VFD_FETCH_INSTR_0_INSTANCED 0x00100000 2975bc00ae02SRob Clark 2976bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; } 2977bc00ae02SRob Clark 2978bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; } 2979bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xfffffff0 2980bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 4 2981bc00ae02SRob Clark static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val) 2982bc00ae02SRob Clark { 2983bc00ae02SRob Clark return ((val >> 4) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK; 2984bc00ae02SRob Clark } 2985bc00ae02SRob Clark 2986bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; } 29878a264743SRob Clark #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK 0x000001ff 29888a264743SRob Clark #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT 0 29898a264743SRob Clark static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val) 29908a264743SRob Clark { 29918a264743SRob Clark return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK; 29928a264743SRob Clark } 2993bc00ae02SRob Clark 2994bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; } 2995bc00ae02SRob Clark 2996bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; } 2997bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f 2998bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0 2999bc00ae02SRob Clark static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) 3000bc00ae02SRob Clark { 3001bc00ae02SRob Clark return ((val) << A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK; 3002bc00ae02SRob Clark } 3003bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010 3004bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0 3005bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6 3006bc00ae02SRob Clark static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val) 3007bc00ae02SRob Clark { 3008bc00ae02SRob Clark return ((val) << A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A4XX_VFD_DECODE_INSTR_FORMAT__MASK; 3009bc00ae02SRob Clark } 3010bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000 3011bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_REGID__SHIFT 12 3012bc00ae02SRob Clark static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val) 3013bc00ae02SRob Clark { 3014bc00ae02SRob Clark return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK; 3015bc00ae02SRob Clark } 30168a264743SRob Clark #define A4XX_VFD_DECODE_INSTR_INT 0x00100000 3017bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000 3018bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT 22 3019bc00ae02SRob Clark static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 3020bc00ae02SRob Clark { 3021bc00ae02SRob Clark return ((val) << A4XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A4XX_VFD_DECODE_INSTR_SWAP__MASK; 3022bc00ae02SRob Clark } 3023bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000 3024bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24 3025bc00ae02SRob Clark static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) 3026bc00ae02SRob Clark { 3027bc00ae02SRob Clark return ((val) << A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK; 3028bc00ae02SRob Clark } 3029bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000 3030bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000 3031bc00ae02SRob Clark 3032bc00ae02SRob Clark #define REG_A4XX_TPL1_DEBUG_ECO_CONTROL 0x00000f00 3033bc00ae02SRob Clark 3034af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_MODE_CONTROL 0x00000f03 3035af6cb4c1SRob Clark 3036a2272e48SRob Clark #define REG_A4XX_TPL1_PERFCTR_TP_SEL_0 0x00000f04 3037a2272e48SRob Clark 3038a2272e48SRob Clark #define REG_A4XX_TPL1_PERFCTR_TP_SEL_1 0x00000f05 3039a2272e48SRob Clark 3040a2272e48SRob Clark #define REG_A4XX_TPL1_PERFCTR_TP_SEL_2 0x00000f06 3041a2272e48SRob Clark 3042a2272e48SRob Clark #define REG_A4XX_TPL1_PERFCTR_TP_SEL_3 0x00000f07 3043a2272e48SRob Clark 3044a2272e48SRob Clark #define REG_A4XX_TPL1_PERFCTR_TP_SEL_4 0x00000f08 3045a2272e48SRob Clark 3046a2272e48SRob Clark #define REG_A4XX_TPL1_PERFCTR_TP_SEL_5 0x00000f09 3047a2272e48SRob Clark 3048a2272e48SRob Clark #define REG_A4XX_TPL1_PERFCTR_TP_SEL_6 0x00000f0a 3049a2272e48SRob Clark 3050bc00ae02SRob Clark #define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 0x00000f0b 3051bc00ae02SRob Clark 3052bc00ae02SRob Clark #define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380 3053bc00ae02SRob Clark 3054af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_TEX_COUNT 0x00002381 3055af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_VS__MASK 0x000000ff 3056af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT 0 3057af6cb4c1SRob Clark static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val) 3058af6cb4c1SRob Clark { 3059af6cb4c1SRob Clark return ((val) << A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_VS__MASK; 3060af6cb4c1SRob Clark } 3061af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_HS__MASK 0x0000ff00 3062af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT 8 3063af6cb4c1SRob Clark static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val) 3064af6cb4c1SRob Clark { 3065af6cb4c1SRob Clark return ((val) << A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_HS__MASK; 3066af6cb4c1SRob Clark } 3067af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_DS__MASK 0x00ff0000 3068af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT 16 3069af6cb4c1SRob Clark static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val) 3070af6cb4c1SRob Clark { 3071af6cb4c1SRob Clark return ((val) << A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_DS__MASK; 3072af6cb4c1SRob Clark } 3073af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_GS__MASK 0xff000000 3074af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT 24 3075af6cb4c1SRob Clark static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val) 3076af6cb4c1SRob Clark { 3077af6cb4c1SRob Clark return ((val) << A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_GS__MASK; 3078af6cb4c1SRob Clark } 3079af6cb4c1SRob Clark 3080af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002384 3081af6cb4c1SRob Clark 3082af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR 0x00002387 3083af6cb4c1SRob Clark 3084af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR 0x0000238a 3085af6cb4c1SRob Clark 3086af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR 0x0000238d 3087af6cb4c1SRob Clark 3088af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_FS_TEX_COUNT 0x000023a0 3089af6cb4c1SRob Clark 3090af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x000023a1 3091af6cb4c1SRob Clark 3092af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_CS_BORDER_COLOR_BASE_ADDR 0x000023a4 3093af6cb4c1SRob Clark 3094af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_CS_SAMPLER_BASE_ADDR 0x000023a5 3095af6cb4c1SRob Clark 3096bc00ae02SRob Clark #define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR 0x000023a6 3097bc00ae02SRob Clark 3098bc00ae02SRob Clark #define REG_A4XX_GRAS_TSE_STATUS 0x00000c80 3099bc00ae02SRob Clark 3100bc00ae02SRob Clark #define REG_A4XX_GRAS_DEBUG_ECO_CONTROL 0x00000c81 3101bc00ae02SRob Clark 3102bc00ae02SRob Clark #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c88 3103bc00ae02SRob Clark 3104a2272e48SRob Clark #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c89 3105a2272e48SRob Clark 3106a2272e48SRob Clark #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c8a 3107a2272e48SRob Clark 3108bc00ae02SRob Clark #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c8b 3109bc00ae02SRob Clark 3110a2272e48SRob Clark #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c8c 3111a2272e48SRob Clark 3112a2272e48SRob Clark #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c8d 3113a2272e48SRob Clark 3114a2272e48SRob Clark #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c8e 3115a2272e48SRob Clark 3116a2272e48SRob Clark #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c8f 3117a2272e48SRob Clark 3118bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000 3119a2272e48SRob Clark #define A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00008000 3120a2272e48SRob Clark #define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000 3121bc00ae02SRob Clark 3122bc00ae02SRob Clark #define REG_A4XX_GRAS_CLEAR_CNTL 0x00002003 3123bc00ae02SRob Clark #define A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR 0x00000001 3124bc00ae02SRob Clark 3125bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_GB_CLIP_ADJ 0x00002004 3126bc00ae02SRob Clark #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff 3127bc00ae02SRob Clark #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0 3128bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) 3129bc00ae02SRob Clark { 3130bc00ae02SRob Clark return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; 3131bc00ae02SRob Clark } 3132bc00ae02SRob Clark #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00 3133bc00ae02SRob Clark #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10 3134bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) 3135bc00ae02SRob Clark { 3136bc00ae02SRob Clark return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; 3137bc00ae02SRob Clark } 3138bc00ae02SRob Clark 3139bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_XOFFSET_0 0x00002008 3140bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff 3141bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0 3142bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val) 3143bc00ae02SRob Clark { 3144bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK; 3145bc00ae02SRob Clark } 3146bc00ae02SRob Clark 3147bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_XSCALE_0 0x00002009 3148bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff 3149bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0 3150bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val) 3151bc00ae02SRob Clark { 3152bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_XSCALE_0__MASK; 3153bc00ae02SRob Clark } 3154bc00ae02SRob Clark 3155bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_YOFFSET_0 0x0000200a 3156bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff 3157bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0 3158bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val) 3159bc00ae02SRob Clark { 3160bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK; 3161bc00ae02SRob Clark } 3162bc00ae02SRob Clark 3163bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_YSCALE_0 0x0000200b 3164bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff 3165bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0 3166bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val) 3167bc00ae02SRob Clark { 3168bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_YSCALE_0__MASK; 3169bc00ae02SRob Clark } 3170bc00ae02SRob Clark 3171bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000200c 3172bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff 3173bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0 3174bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val) 3175bc00ae02SRob Clark { 3176bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK; 3177bc00ae02SRob Clark } 3178bc00ae02SRob Clark 3179bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_ZSCALE_0 0x0000200d 3180bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff 3181bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0 3182bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val) 3183bc00ae02SRob Clark { 3184bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK; 3185bc00ae02SRob Clark } 3186bc00ae02SRob Clark 3187bc00ae02SRob Clark #define REG_A4XX_GRAS_SU_POINT_MINMAX 0x00002070 3188bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 3189bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 3190bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val) 3191bc00ae02SRob Clark { 3192bc00ae02SRob Clark return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 3193bc00ae02SRob Clark } 3194bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 3195bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 3196bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val) 3197bc00ae02SRob Clark { 3198bc00ae02SRob Clark return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 3199bc00ae02SRob Clark } 3200bc00ae02SRob Clark 3201bc00ae02SRob Clark #define REG_A4XX_GRAS_SU_POINT_SIZE 0x00002071 3202bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff 3203bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_SIZE__SHIFT 0 3204bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val) 3205bc00ae02SRob Clark { 3206bc00ae02SRob Clark return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK; 3207bc00ae02SRob Clark } 3208bc00ae02SRob Clark 3209bc00ae02SRob Clark #define REG_A4XX_GRAS_ALPHA_CONTROL 0x00002073 3210bc00ae02SRob Clark #define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE 0x00000004 3211a2272e48SRob Clark #define A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS 0x00000008 3212bc00ae02SRob Clark 3213bc00ae02SRob Clark #define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE 0x00002074 3214bc00ae02SRob Clark #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff 3215bc00ae02SRob Clark #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 3216bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val) 3217bc00ae02SRob Clark { 3218bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; 3219bc00ae02SRob Clark } 3220bc00ae02SRob Clark 3221bc00ae02SRob Clark #define REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00002075 3222bc00ae02SRob Clark #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 3223bc00ae02SRob Clark #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 3224bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 3225bc00ae02SRob Clark { 3226bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 3227bc00ae02SRob Clark } 3228bc00ae02SRob Clark 3229af6cb4c1SRob Clark #define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP 0x00002076 3230af6cb4c1SRob Clark #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK 0xffffffff 3231af6cb4c1SRob Clark #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT 0 3232af6cb4c1SRob Clark static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val) 3233af6cb4c1SRob Clark { 3234af6cb4c1SRob Clark return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK; 3235af6cb4c1SRob Clark } 3236af6cb4c1SRob Clark 32378a264743SRob Clark #define REG_A4XX_GRAS_DEPTH_CONTROL 0x00002077 32388a264743SRob Clark #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK 0x00000003 32398a264743SRob Clark #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT 0 32408a264743SRob Clark static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val) 32418a264743SRob Clark { 32428a264743SRob Clark return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK; 32438a264743SRob Clark } 32448a264743SRob Clark 32458a264743SRob Clark #define REG_A4XX_GRAS_SU_MODE_CONTROL 0x00002078 32468a264743SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001 32478a264743SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002 32488a264743SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004 32498a264743SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8 32508a264743SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3 32518a264743SRob Clark static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) 32528a264743SRob Clark { 32538a264743SRob Clark return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; 32548a264743SRob Clark } 32558a264743SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800 32568a264743SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS 0x00100000 32578a264743SRob Clark 32588a264743SRob Clark #define REG_A4XX_GRAS_SC_CONTROL 0x0000207b 32598a264743SRob Clark #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x0000000c 32608a264743SRob Clark #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 2 32618a264743SRob Clark static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) 32628a264743SRob Clark { 32638a264743SRob Clark return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK; 32648a264743SRob Clark } 32658a264743SRob Clark #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000380 32668a264743SRob Clark #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 7 32678a264743SRob Clark static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val) 32688a264743SRob Clark { 32698a264743SRob Clark return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK; 32708a264743SRob Clark } 32718a264743SRob Clark #define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE 0x00000800 32728a264743SRob Clark #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000 32738a264743SRob Clark #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12 32748a264743SRob Clark static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) 32758a264743SRob Clark { 32768a264743SRob Clark return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK; 32778a264743SRob Clark } 3278bc00ae02SRob Clark 3279bc00ae02SRob Clark #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL 0x0000207c 3280bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 3281bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 3282bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 3283bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 3284bc00ae02SRob Clark { 3285bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; 3286bc00ae02SRob Clark } 3287bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 3288bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 3289bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 3290bc00ae02SRob Clark { 3291bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; 3292bc00ae02SRob Clark } 3293bc00ae02SRob Clark 3294bc00ae02SRob Clark #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR 0x0000207d 3295bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 3296bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 3297bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 3298bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 3299bc00ae02SRob Clark { 3300bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; 3301bc00ae02SRob Clark } 3302bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 3303bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 3304bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 3305bc00ae02SRob Clark { 3306bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; 3307bc00ae02SRob Clark } 3308bc00ae02SRob Clark 3309bc00ae02SRob Clark #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000209c 3310bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 3311bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 3312bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 3313bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 3314bc00ae02SRob Clark { 3315bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 3316bc00ae02SRob Clark } 3317bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 3318bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 3319bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 3320bc00ae02SRob Clark { 3321bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 3322bc00ae02SRob Clark } 3323bc00ae02SRob Clark 3324bc00ae02SRob Clark #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000209d 3325bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 3326bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 3327bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 3328bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 3329bc00ae02SRob Clark { 3330bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 3331bc00ae02SRob Clark } 3332bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 3333bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 3334bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 3335bc00ae02SRob Clark { 3336bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 3337bc00ae02SRob Clark } 3338bc00ae02SRob Clark 33398a264743SRob Clark #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR 0x0000209e 33408a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE 0x80000000 33418a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK 0x00007fff 33428a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT 0 33438a264743SRob Clark static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val) 3344bc00ae02SRob Clark { 33458a264743SRob Clark return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK; 33468a264743SRob Clark } 33478a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK 0x7fff0000 33488a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT 16 33498a264743SRob Clark static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val) 33508a264743SRob Clark { 33518a264743SRob Clark return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK; 3352bc00ae02SRob Clark } 3353bc00ae02SRob Clark 33548a264743SRob Clark #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL 0x0000209f 33558a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE 0x80000000 33568a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK 0x00007fff 33578a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT 0 33588a264743SRob Clark static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val) 3359bc00ae02SRob Clark { 33608a264743SRob Clark return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK; 3361bc00ae02SRob Clark } 33628a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK 0x7fff0000 33638a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT 16 33648a264743SRob Clark static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val) 3365bc00ae02SRob Clark { 33668a264743SRob Clark return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK; 3367bc00ae02SRob Clark } 3368bc00ae02SRob Clark 3369bc00ae02SRob Clark #define REG_A4XX_UCHE_CACHE_MODE_CONTROL 0x00000e80 3370bc00ae02SRob Clark 3371bc00ae02SRob Clark #define REG_A4XX_UCHE_TRAP_BASE_LO 0x00000e83 3372bc00ae02SRob Clark 3373bc00ae02SRob Clark #define REG_A4XX_UCHE_TRAP_BASE_HI 0x00000e84 3374bc00ae02SRob Clark 3375bc00ae02SRob Clark #define REG_A4XX_UCHE_CACHE_STATUS 0x00000e88 3376bc00ae02SRob Clark 3377bc00ae02SRob Clark #define REG_A4XX_UCHE_INVALIDATE0 0x00000e8a 3378bc00ae02SRob Clark 3379bc00ae02SRob Clark #define REG_A4XX_UCHE_INVALIDATE1 0x00000e8b 3380bc00ae02SRob Clark 3381bc00ae02SRob Clark #define REG_A4XX_UCHE_CACHE_WAYS_VFD 0x00000e8c 3382bc00ae02SRob Clark 3383a2272e48SRob Clark #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e8e 3384a2272e48SRob Clark 3385a2272e48SRob Clark #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e8f 3386a2272e48SRob Clark 3387a2272e48SRob Clark #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e90 3388a2272e48SRob Clark 3389a2272e48SRob Clark #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e91 3390a2272e48SRob Clark 3391a2272e48SRob Clark #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e92 3392a2272e48SRob Clark 3393a2272e48SRob Clark #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e93 3394a2272e48SRob Clark 3395a2272e48SRob Clark #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e94 3396a2272e48SRob Clark 3397bc00ae02SRob Clark #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e95 3398bc00ae02SRob Clark 3399bc00ae02SRob Clark #define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD 0x00000e00 3400bc00ae02SRob Clark 3401bc00ae02SRob Clark #define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL 0x00000e04 3402bc00ae02SRob Clark 3403af6cb4c1SRob Clark #define REG_A4XX_HLSQ_MODE_CONTROL 0x00000e05 3404af6cb4c1SRob Clark 3405bc00ae02SRob Clark #define REG_A4XX_HLSQ_PERF_PIPE_MASK 0x00000e0e 3406bc00ae02SRob Clark 3407a2272e48SRob Clark #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e06 3408a2272e48SRob Clark 3409a2272e48SRob Clark #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e07 3410a2272e48SRob Clark 3411a2272e48SRob Clark #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e08 3412a2272e48SRob Clark 3413a2272e48SRob Clark #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e09 3414a2272e48SRob Clark 3415a2272e48SRob Clark #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e0a 3416a2272e48SRob Clark 3417a2272e48SRob Clark #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e0b 3418a2272e48SRob Clark 3419a2272e48SRob Clark #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e0c 3420a2272e48SRob Clark 3421a2272e48SRob Clark #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e0d 3422a2272e48SRob Clark 3423bc00ae02SRob Clark #define REG_A4XX_HLSQ_CONTROL_0_REG 0x000023c0 3424bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010 3425bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4 3426bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) 3427bc00ae02SRob Clark { 3428bc00ae02SRob Clark return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; 3429bc00ae02SRob Clark } 3430bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040 3431bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200 3432bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400 3433bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000 3434bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000 3435bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27 3436bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) 3437bc00ae02SRob Clark { 3438bc00ae02SRob Clark return ((val) << A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK; 3439bc00ae02SRob Clark } 3440bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000 3441bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000 3442bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000 3443bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000 3444bc00ae02SRob Clark 3445bc00ae02SRob Clark #define REG_A4XX_HLSQ_CONTROL_1_REG 0x000023c1 3446bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040 3447bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6 3448bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) 3449bc00ae02SRob Clark { 3450bc00ae02SRob Clark return ((val) << A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK; 3451bc00ae02SRob Clark } 3452bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100 3453bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200 34548a264743SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK 0x00ff0000 34558a264743SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT 16 34568a264743SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val) 34578a264743SRob Clark { 34588a264743SRob Clark return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK; 34598a264743SRob Clark } 3460af6cb4c1SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK 0xff000000 3461af6cb4c1SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT 24 3462af6cb4c1SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val) 3463af6cb4c1SRob Clark { 3464af6cb4c1SRob Clark return ((val) << A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK; 3465af6cb4c1SRob Clark } 3466bc00ae02SRob Clark 3467bc00ae02SRob Clark #define REG_A4XX_HLSQ_CONTROL_2_REG 0x000023c2 3468bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000 3469bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26 3470bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) 3471bc00ae02SRob Clark { 3472bc00ae02SRob Clark return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK; 3473bc00ae02SRob Clark } 34748a264743SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000003fc 34758a264743SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 2 34768a264743SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) 34778a264743SRob Clark { 34788a264743SRob Clark return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; 34798a264743SRob Clark } 3480af6cb4c1SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK 0x0003fc00 3481af6cb4c1SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT 10 3482af6cb4c1SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val) 3483af6cb4c1SRob Clark { 3484af6cb4c1SRob Clark return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK; 3485af6cb4c1SRob Clark } 3486af6cb4c1SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK 0x03fc0000 3487af6cb4c1SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT 18 3488af6cb4c1SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val) 3489af6cb4c1SRob Clark { 3490af6cb4c1SRob Clark return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK; 3491af6cb4c1SRob Clark } 3492bc00ae02SRob Clark 3493bc00ae02SRob Clark #define REG_A4XX_HLSQ_CONTROL_3_REG 0x000023c3 3494bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff 3495bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0 3496bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val) 3497bc00ae02SRob Clark { 3498bc00ae02SRob Clark return ((val) << A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_REGID__MASK; 3499bc00ae02SRob Clark } 3500bc00ae02SRob Clark 3501af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CONTROL_4_REG 0x000023c4 3502af6cb4c1SRob Clark 3503bc00ae02SRob Clark #define REG_A4XX_HLSQ_VS_CONTROL_REG 0x000023c5 3504bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 3505bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0 3506bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) 3507bc00ae02SRob Clark { 3508bc00ae02SRob Clark return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK; 3509bc00ae02SRob Clark } 3510bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 3511bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 3512bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3513bc00ae02SRob Clark { 3514bc00ae02SRob Clark return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3515bc00ae02SRob Clark } 3516af6cb4c1SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00010000 3517bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 3518bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 3519bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3520bc00ae02SRob Clark { 3521bc00ae02SRob Clark return ((val) << A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3522bc00ae02SRob Clark } 3523bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 3524bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24 3525bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) 3526bc00ae02SRob Clark { 3527bc00ae02SRob Clark return ((val) << A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK; 3528bc00ae02SRob Clark } 3529bc00ae02SRob Clark 3530bc00ae02SRob Clark #define REG_A4XX_HLSQ_FS_CONTROL_REG 0x000023c6 3531bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 3532bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0 3533bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) 3534bc00ae02SRob Clark { 3535bc00ae02SRob Clark return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK; 3536bc00ae02SRob Clark } 3537bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 3538bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 3539bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3540bc00ae02SRob Clark { 3541bc00ae02SRob Clark return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3542bc00ae02SRob Clark } 3543af6cb4c1SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00010000 3544bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 3545bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 3546bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3547bc00ae02SRob Clark { 3548bc00ae02SRob Clark return ((val) << A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3549bc00ae02SRob Clark } 3550bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 3551bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24 3552bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) 3553bc00ae02SRob Clark { 3554bc00ae02SRob Clark return ((val) << A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK; 3555bc00ae02SRob Clark } 3556bc00ae02SRob Clark 3557bc00ae02SRob Clark #define REG_A4XX_HLSQ_HS_CONTROL_REG 0x000023c7 3558bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 3559bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT 0 3560bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val) 3561bc00ae02SRob Clark { 3562bc00ae02SRob Clark return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK; 3563bc00ae02SRob Clark } 3564bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 3565bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 3566bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3567bc00ae02SRob Clark { 3568bc00ae02SRob Clark return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3569bc00ae02SRob Clark } 3570af6cb4c1SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00010000 3571bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 3572bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 3573bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3574bc00ae02SRob Clark { 3575bc00ae02SRob Clark return ((val) << A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3576bc00ae02SRob Clark } 3577bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 3578bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT 24 3579bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val) 3580bc00ae02SRob Clark { 3581bc00ae02SRob Clark return ((val) << A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK; 3582bc00ae02SRob Clark } 3583bc00ae02SRob Clark 3584bc00ae02SRob Clark #define REG_A4XX_HLSQ_DS_CONTROL_REG 0x000023c8 3585bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 3586bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT 0 3587bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val) 3588bc00ae02SRob Clark { 3589bc00ae02SRob Clark return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK; 3590bc00ae02SRob Clark } 3591bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 3592bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 3593bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3594bc00ae02SRob Clark { 3595bc00ae02SRob Clark return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3596bc00ae02SRob Clark } 3597af6cb4c1SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00010000 3598bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 3599bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 3600bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3601bc00ae02SRob Clark { 3602bc00ae02SRob Clark return ((val) << A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3603bc00ae02SRob Clark } 3604bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 3605bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT 24 3606bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val) 3607bc00ae02SRob Clark { 3608bc00ae02SRob Clark return ((val) << A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK; 3609bc00ae02SRob Clark } 3610bc00ae02SRob Clark 3611bc00ae02SRob Clark #define REG_A4XX_HLSQ_GS_CONTROL_REG 0x000023c9 3612bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 3613bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT 0 3614bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val) 3615bc00ae02SRob Clark { 3616bc00ae02SRob Clark return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK; 3617bc00ae02SRob Clark } 3618bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 3619bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 3620bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 3621bc00ae02SRob Clark { 3622bc00ae02SRob Clark return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 3623bc00ae02SRob Clark } 3624af6cb4c1SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00010000 3625bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 3626bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 3627bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 3628bc00ae02SRob Clark { 3629bc00ae02SRob Clark return ((val) << A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK; 3630bc00ae02SRob Clark } 3631bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 3632bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT 24 3633bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val) 3634bc00ae02SRob Clark { 3635bc00ae02SRob Clark return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK; 3636bc00ae02SRob Clark } 3637bc00ae02SRob Clark 3638af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CS_CONTROL 0x000023ca 3639af6cb4c1SRob Clark 3640af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_NDRANGE_0 0x000023cd 3641af6cb4c1SRob Clark 3642af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_NDRANGE_1 0x000023ce 3643af6cb4c1SRob Clark 3644af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_NDRANGE_2 0x000023cf 3645af6cb4c1SRob Clark 3646af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_NDRANGE_3 0x000023d0 3647af6cb4c1SRob Clark 3648af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_NDRANGE_4 0x000023d1 3649af6cb4c1SRob Clark 3650af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_NDRANGE_5 0x000023d2 3651af6cb4c1SRob Clark 3652af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_NDRANGE_6 0x000023d3 3653af6cb4c1SRob Clark 3654af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_CONTROL_0 0x000023d4 3655af6cb4c1SRob Clark 3656af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_CONTROL_1 0x000023d5 3657af6cb4c1SRob Clark 3658af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_KERNEL_CONST 0x000023d6 3659af6cb4c1SRob Clark 3660af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_X 0x000023d7 3661af6cb4c1SRob Clark 3662af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Y 0x000023d8 3663af6cb4c1SRob Clark 3664af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z 0x000023d9 3665af6cb4c1SRob Clark 3666af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_WG_OFFSET 0x000023da 3667af6cb4c1SRob Clark 3668bc00ae02SRob Clark #define REG_A4XX_HLSQ_UPDATE_CONTROL 0x000023db 3669bc00ae02SRob Clark 3670bc00ae02SRob Clark #define REG_A4XX_PC_BINNING_COMMAND 0x00000d00 3671bc00ae02SRob Clark #define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001 3672bc00ae02SRob Clark 3673bc00ae02SRob Clark #define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c 3674bc00ae02SRob Clark 3675bc00ae02SRob Clark #define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10 3676bc00ae02SRob Clark 3677a2272e48SRob Clark #define REG_A4XX_PC_PERFCTR_PC_SEL_1 0x00000d11 3678a2272e48SRob Clark 3679a2272e48SRob Clark #define REG_A4XX_PC_PERFCTR_PC_SEL_2 0x00000d12 3680a2272e48SRob Clark 3681a2272e48SRob Clark #define REG_A4XX_PC_PERFCTR_PC_SEL_3 0x00000d13 3682a2272e48SRob Clark 3683a2272e48SRob Clark #define REG_A4XX_PC_PERFCTR_PC_SEL_4 0x00000d14 3684a2272e48SRob Clark 3685a2272e48SRob Clark #define REG_A4XX_PC_PERFCTR_PC_SEL_5 0x00000d15 3686a2272e48SRob Clark 3687a2272e48SRob Clark #define REG_A4XX_PC_PERFCTR_PC_SEL_6 0x00000d16 3688a2272e48SRob Clark 3689bc00ae02SRob Clark #define REG_A4XX_PC_PERFCTR_PC_SEL_7 0x00000d17 3690bc00ae02SRob Clark 3691bc00ae02SRob Clark #define REG_A4XX_PC_BIN_BASE 0x000021c0 3692bc00ae02SRob Clark 3693bc00ae02SRob Clark #define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4 3694af6cb4c1SRob Clark #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK 0x0000000f 3695af6cb4c1SRob Clark #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT 0 3696af6cb4c1SRob Clark static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val) 3697af6cb4c1SRob Clark { 3698af6cb4c1SRob Clark return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK; 3699af6cb4c1SRob Clark } 3700af6cb4c1SRob Clark #define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000 3701bc00ae02SRob Clark #define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000 3702bc00ae02SRob Clark #define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000 3703bc00ae02SRob Clark 3704a2272e48SRob Clark #define REG_A4XX_PC_PRIM_VTX_CNTL2 0x000021c5 3705a2272e48SRob Clark #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK 0x00000007 3706a2272e48SRob Clark #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT 0 3707a2272e48SRob Clark static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 3708a2272e48SRob Clark { 3709a2272e48SRob Clark return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK; 3710a2272e48SRob Clark } 3711a2272e48SRob Clark #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK 0x00000038 3712a2272e48SRob Clark #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT 3 3713a2272e48SRob Clark static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 3714a2272e48SRob Clark { 3715a2272e48SRob Clark return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK; 3716a2272e48SRob Clark } 3717a2272e48SRob Clark #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_ENABLE 0x00000040 3718bc00ae02SRob Clark 3719bc00ae02SRob Clark #define REG_A4XX_PC_RESTART_INDEX 0x000021c6 3720bc00ae02SRob Clark 3721bc00ae02SRob Clark #define REG_A4XX_PC_GS_PARAM 0x000021e5 3722af6cb4c1SRob Clark #define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff 3723af6cb4c1SRob Clark #define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0 3724af6cb4c1SRob Clark static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val) 3725af6cb4c1SRob Clark { 3726af6cb4c1SRob Clark return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK; 3727af6cb4c1SRob Clark } 3728af6cb4c1SRob Clark #define A4XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800 3729af6cb4c1SRob Clark #define A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11 3730af6cb4c1SRob Clark static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val) 3731af6cb4c1SRob Clark { 3732af6cb4c1SRob Clark return ((val) << A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A4XX_PC_GS_PARAM_INVOCATIONS__MASK; 3733af6cb4c1SRob Clark } 3734af6cb4c1SRob Clark #define A4XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000 3735af6cb4c1SRob Clark #define A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23 3736af6cb4c1SRob Clark static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val) 3737af6cb4c1SRob Clark { 3738af6cb4c1SRob Clark return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK; 3739af6cb4c1SRob Clark } 3740af6cb4c1SRob Clark #define A4XX_PC_GS_PARAM_LAYER 0x80000000 3741bc00ae02SRob Clark 3742bc00ae02SRob Clark #define REG_A4XX_PC_HS_PARAM 0x000021e7 3743af6cb4c1SRob Clark #define A4XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f 3744af6cb4c1SRob Clark #define A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0 3745af6cb4c1SRob Clark static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val) 3746af6cb4c1SRob Clark { 3747af6cb4c1SRob Clark return ((val) << A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A4XX_PC_HS_PARAM_VERTICES_OUT__MASK; 3748af6cb4c1SRob Clark } 3749af6cb4c1SRob Clark #define A4XX_PC_HS_PARAM_SPACING__MASK 0x00600000 3750af6cb4c1SRob Clark #define A4XX_PC_HS_PARAM_SPACING__SHIFT 21 3751af6cb4c1SRob Clark static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val) 3752af6cb4c1SRob Clark { 3753af6cb4c1SRob Clark return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK; 3754af6cb4c1SRob Clark } 3755af6cb4c1SRob Clark #define A4XX_PC_HS_PARAM_PRIMTYPE__MASK 0x01800000 3756af6cb4c1SRob Clark #define A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT 23 3757af6cb4c1SRob Clark static inline uint32_t A4XX_PC_HS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val) 3758af6cb4c1SRob Clark { 3759af6cb4c1SRob Clark return ((val) << A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_HS_PARAM_PRIMTYPE__MASK; 3760af6cb4c1SRob Clark } 3761bc00ae02SRob Clark 3762bc00ae02SRob Clark #define REG_A4XX_VBIF_VERSION 0x00003000 3763bc00ae02SRob Clark 3764bc00ae02SRob Clark #define REG_A4XX_VBIF_CLKON 0x00003001 3765bc00ae02SRob Clark #define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000001 3766bc00ae02SRob Clark 3767bc00ae02SRob Clark #define REG_A4XX_VBIF_ABIT_SORT 0x0000301c 3768bc00ae02SRob Clark 3769bc00ae02SRob Clark #define REG_A4XX_VBIF_ABIT_SORT_CONF 0x0000301d 3770bc00ae02SRob Clark 3771bc00ae02SRob Clark #define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 3772bc00ae02SRob Clark 3773bc00ae02SRob Clark #define REG_A4XX_VBIF_IN_RD_LIM_CONF0 0x0000302c 3774bc00ae02SRob Clark 3775bc00ae02SRob Clark #define REG_A4XX_VBIF_IN_RD_LIM_CONF1 0x0000302d 3776bc00ae02SRob Clark 3777bc00ae02SRob Clark #define REG_A4XX_VBIF_IN_WR_LIM_CONF0 0x00003030 3778bc00ae02SRob Clark 3779bc00ae02SRob Clark #define REG_A4XX_VBIF_IN_WR_LIM_CONF1 0x00003031 3780bc00ae02SRob Clark 3781bc00ae02SRob Clark #define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049 3782bc00ae02SRob Clark 3783bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_0CC5 0x00000cc5 3784bc00ae02SRob Clark 3785bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_0CC6 0x00000cc6 3786bc00ae02SRob Clark 3787bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_0D01 0x00000d01 3788bc00ae02SRob Clark 3789bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_0E42 0x00000e42 3790bc00ae02SRob Clark 3791bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_0EC2 0x00000ec2 3792bc00ae02SRob Clark 3793bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2001 0x00002001 3794bc00ae02SRob Clark 3795bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_209B 0x0000209b 3796bc00ae02SRob Clark 3797bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_20EF 0x000020ef 3798bc00ae02SRob Clark 3799bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2152 0x00002152 3800bc00ae02SRob Clark 3801bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2153 0x00002153 3802bc00ae02SRob Clark 3803bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2154 0x00002154 3804bc00ae02SRob Clark 3805bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2155 0x00002155 3806bc00ae02SRob Clark 3807bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2156 0x00002156 3808bc00ae02SRob Clark 3809bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2157 0x00002157 3810bc00ae02SRob Clark 3811bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_21C3 0x000021c3 3812bc00ae02SRob Clark 3813bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_21E6 0x000021e6 3814bc00ae02SRob Clark 3815bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2209 0x00002209 3816bc00ae02SRob Clark 3817bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_22D7 0x000022d7 3818bc00ae02SRob Clark 38192d3584ebSRob Clark #define REG_A4XX_UNKNOWN_2352 0x00002352 38202d3584ebSRob Clark 3821bc00ae02SRob Clark #define REG_A4XX_TEX_SAMP_0 0x00000000 38228a264743SRob Clark #define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 3823bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 3824bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_XY_MAG__SHIFT 1 3825bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val) 3826bc00ae02SRob Clark { 3827bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_0_XY_MAG__SHIFT) & A4XX_TEX_SAMP_0_XY_MAG__MASK; 3828bc00ae02SRob Clark } 3829bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 3830bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_XY_MIN__SHIFT 3 3831bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val) 3832bc00ae02SRob Clark { 3833bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_0_XY_MIN__SHIFT) & A4XX_TEX_SAMP_0_XY_MIN__MASK; 3834bc00ae02SRob Clark } 3835bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 3836bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_S__SHIFT 5 3837bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val) 3838bc00ae02SRob Clark { 3839bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_0_WRAP_S__SHIFT) & A4XX_TEX_SAMP_0_WRAP_S__MASK; 3840bc00ae02SRob Clark } 3841bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 3842bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_T__SHIFT 8 3843bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val) 3844bc00ae02SRob Clark { 3845bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_0_WRAP_T__SHIFT) & A4XX_TEX_SAMP_0_WRAP_T__MASK; 3846bc00ae02SRob Clark } 3847bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 3848bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_R__SHIFT 11 3849bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val) 3850bc00ae02SRob Clark { 3851bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK; 3852bc00ae02SRob Clark } 3853af6cb4c1SRob Clark #define A4XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 3854af6cb4c1SRob Clark #define A4XX_TEX_SAMP_0_ANISO__SHIFT 14 3855af6cb4c1SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val) 3856af6cb4c1SRob Clark { 3857af6cb4c1SRob Clark return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK; 3858af6cb4c1SRob Clark } 3859a2272e48SRob Clark #define A4XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000 3860a2272e48SRob Clark #define A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19 3861a2272e48SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_LOD_BIAS(float val) 3862a2272e48SRob Clark { 3863a2272e48SRob Clark return ((((int32_t)(val * 256.0))) << A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A4XX_TEX_SAMP_0_LOD_BIAS__MASK; 3864a2272e48SRob Clark } 3865bc00ae02SRob Clark 3866bc00ae02SRob Clark #define REG_A4XX_TEX_SAMP_1 0x00000001 3867bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e 3868bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 3869bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) 3870bc00ae02SRob Clark { 3871bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK; 3872bc00ae02SRob Clark } 3873a2272e48SRob Clark #define A4XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010 38748a264743SRob Clark #define A4XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 38758a264743SRob Clark #define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 3876bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 3877bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 3878bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val) 3879bc00ae02SRob Clark { 38808a264743SRob Clark return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK; 3881bc00ae02SRob Clark } 3882bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 3883bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 3884bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val) 3885bc00ae02SRob Clark { 38868a264743SRob Clark return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK; 3887bc00ae02SRob Clark } 3888bc00ae02SRob Clark 3889bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_0 0x00000000 3890bc00ae02SRob Clark #define A4XX_TEX_CONST_0_TILED 0x00000001 3891af6cb4c1SRob Clark #define A4XX_TEX_CONST_0_SRGB 0x00000004 3892bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 3893bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_X__SHIFT 4 3894bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val) 3895bc00ae02SRob Clark { 3896bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) & A4XX_TEX_CONST_0_SWIZ_X__MASK; 3897bc00ae02SRob Clark } 3898bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 3899bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 3900bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val) 3901bc00ae02SRob Clark { 3902bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Y__MASK; 3903bc00ae02SRob Clark } 3904bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 3905bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 3906bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val) 3907bc00ae02SRob Clark { 3908bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Z__MASK; 3909bc00ae02SRob Clark } 3910bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 3911bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_W__SHIFT 13 3912bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val) 3913bc00ae02SRob Clark { 3914bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK; 3915bc00ae02SRob Clark } 39168a264743SRob Clark #define A4XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 39178a264743SRob Clark #define A4XX_TEX_CONST_0_MIPLVLS__SHIFT 16 39188a264743SRob Clark static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val) 39198a264743SRob Clark { 39208a264743SRob Clark return ((val) << A4XX_TEX_CONST_0_MIPLVLS__SHIFT) & A4XX_TEX_CONST_0_MIPLVLS__MASK; 39218a264743SRob Clark } 3922bc00ae02SRob Clark #define A4XX_TEX_CONST_0_FMT__MASK 0x1fc00000 3923bc00ae02SRob Clark #define A4XX_TEX_CONST_0_FMT__SHIFT 22 3924bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val) 3925bc00ae02SRob Clark { 3926bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK; 3927bc00ae02SRob Clark } 3928bc00ae02SRob Clark #define A4XX_TEX_CONST_0_TYPE__MASK 0x60000000 3929bc00ae02SRob Clark #define A4XX_TEX_CONST_0_TYPE__SHIFT 29 3930bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val) 3931bc00ae02SRob Clark { 3932bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_TYPE__SHIFT) & A4XX_TEX_CONST_0_TYPE__MASK; 3933bc00ae02SRob Clark } 3934bc00ae02SRob Clark 3935bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_1 0x00000001 3936bc00ae02SRob Clark #define A4XX_TEX_CONST_1_HEIGHT__MASK 0x00007fff 3937bc00ae02SRob Clark #define A4XX_TEX_CONST_1_HEIGHT__SHIFT 0 3938bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val) 3939bc00ae02SRob Clark { 3940bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK; 3941bc00ae02SRob Clark } 3942a2272e48SRob Clark #define A4XX_TEX_CONST_1_WIDTH__MASK 0x3fff8000 3943bc00ae02SRob Clark #define A4XX_TEX_CONST_1_WIDTH__SHIFT 15 3944bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val) 3945bc00ae02SRob Clark { 3946bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK; 3947bc00ae02SRob Clark } 3948bc00ae02SRob Clark 3949bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_2 0x00000002 39508a264743SRob Clark #define A4XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f 39518a264743SRob Clark #define A4XX_TEX_CONST_2_FETCHSIZE__SHIFT 0 39528a264743SRob Clark static inline uint32_t A4XX_TEX_CONST_2_FETCHSIZE(enum a4xx_tex_fetchsize val) 39538a264743SRob Clark { 39548a264743SRob Clark return ((val) << A4XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A4XX_TEX_CONST_2_FETCHSIZE__MASK; 39558a264743SRob Clark } 3956bc00ae02SRob Clark #define A4XX_TEX_CONST_2_PITCH__MASK 0x3ffffe00 3957bc00ae02SRob Clark #define A4XX_TEX_CONST_2_PITCH__SHIFT 9 3958bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val) 3959bc00ae02SRob Clark { 3960bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) & A4XX_TEX_CONST_2_PITCH__MASK; 3961bc00ae02SRob Clark } 3962bc00ae02SRob Clark #define A4XX_TEX_CONST_2_SWAP__MASK 0xc0000000 3963bc00ae02SRob Clark #define A4XX_TEX_CONST_2_SWAP__SHIFT 30 3964bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) 3965bc00ae02SRob Clark { 3966bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_2_SWAP__SHIFT) & A4XX_TEX_CONST_2_SWAP__MASK; 3967bc00ae02SRob Clark } 3968bc00ae02SRob Clark 3969bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_3 0x00000003 39708a264743SRob Clark #define A4XX_TEX_CONST_3_LAYERSZ__MASK 0x00003fff 3971bc00ae02SRob Clark #define A4XX_TEX_CONST_3_LAYERSZ__SHIFT 0 3972bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val) 3973bc00ae02SRob Clark { 3974bc00ae02SRob Clark return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK; 3975bc00ae02SRob Clark } 39768a264743SRob Clark #define A4XX_TEX_CONST_3_DEPTH__MASK 0x7ffc0000 39778a264743SRob Clark #define A4XX_TEX_CONST_3_DEPTH__SHIFT 18 39788a264743SRob Clark static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val) 39798a264743SRob Clark { 39808a264743SRob Clark return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK; 39818a264743SRob Clark } 3982bc00ae02SRob Clark 3983bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_4 0x00000004 39848a264743SRob Clark #define A4XX_TEX_CONST_4_LAYERSZ__MASK 0x0000000f 39858a264743SRob Clark #define A4XX_TEX_CONST_4_LAYERSZ__SHIFT 0 39868a264743SRob Clark static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val) 39878a264743SRob Clark { 39888a264743SRob Clark return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK; 39898a264743SRob Clark } 39908a264743SRob Clark #define A4XX_TEX_CONST_4_BASE__MASK 0xffffffe0 39918a264743SRob Clark #define A4XX_TEX_CONST_4_BASE__SHIFT 5 3992bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val) 3993bc00ae02SRob Clark { 39948a264743SRob Clark return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK; 3995bc00ae02SRob Clark } 3996bc00ae02SRob Clark 3997bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_5 0x00000005 3998bc00ae02SRob Clark 3999bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_6 0x00000006 4000bc00ae02SRob Clark 4001bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_7 0x00000007 4002bc00ae02SRob Clark 4003bc00ae02SRob Clark 4004bc00ae02SRob Clark #endif /* A4XX_XML */ 4005