1bc00ae02SRob Clark #ifndef A4XX_XML 2bc00ae02SRob Clark #define A4XX_XML 3bc00ae02SRob Clark 4bc00ae02SRob Clark /* Autogenerated file, DO NOT EDIT manually! 5bc00ae02SRob Clark 6bc00ae02SRob Clark This file was generated by the rules-ng-ng headergen tool in this git repository: 7bc00ae02SRob Clark http://github.com/freedreno/envytools/ 8bc00ae02SRob Clark git clone https://github.com/freedreno/envytools.git 9bc00ae02SRob Clark 10bc00ae02SRob Clark The rules-ng-ng source files this header was generated from are: 118217e97aSRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31) 122d3584ebSRob Clark - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) 132d3584ebSRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) 148217e97aSRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55) 152d3584ebSRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27) 168217e97aSRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55) 178217e97aSRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12) 188217e97aSRob Clark - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) 19bc00ae02SRob Clark 20af6cb4c1SRob Clark Copyright (C) 2013-2015 by the following authors: 21bc00ae02SRob Clark - Rob Clark <robdclark@gmail.com> (robclark) 22bc00ae02SRob Clark 23bc00ae02SRob Clark Permission is hereby granted, free of charge, to any person obtaining 24bc00ae02SRob Clark a copy of this software and associated documentation files (the 25bc00ae02SRob Clark "Software"), to deal in the Software without restriction, including 26bc00ae02SRob Clark without limitation the rights to use, copy, modify, merge, publish, 27bc00ae02SRob Clark distribute, sublicense, and/or sell copies of the Software, and to 28bc00ae02SRob Clark permit persons to whom the Software is furnished to do so, subject to 29bc00ae02SRob Clark the following conditions: 30bc00ae02SRob Clark 31bc00ae02SRob Clark The above copyright notice and this permission notice (including the 32bc00ae02SRob Clark next paragraph) shall be included in all copies or substantial 33bc00ae02SRob Clark portions of the Software. 34bc00ae02SRob Clark 35bc00ae02SRob Clark THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36bc00ae02SRob Clark EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 37bc00ae02SRob Clark MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 38bc00ae02SRob Clark IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 39bc00ae02SRob Clark LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 40bc00ae02SRob Clark OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 41bc00ae02SRob Clark WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 42bc00ae02SRob Clark */ 43bc00ae02SRob Clark 44bc00ae02SRob Clark 45bc00ae02SRob Clark enum a4xx_color_fmt { 46bc00ae02SRob Clark RB4_A8_UNORM = 1, 47af6cb4c1SRob Clark RB4_R8_UNORM = 2, 48af6cb4c1SRob Clark RB4_R4G4B4A4_UNORM = 8, 49af6cb4c1SRob Clark RB4_R5G5B5A1_UNORM = 10, 50bc00ae02SRob Clark RB4_R5G6R5_UNORM = 14, 51af6cb4c1SRob Clark RB4_R8G8_UNORM = 15, 52af6cb4c1SRob Clark RB4_R8G8_SNORM = 16, 53af6cb4c1SRob Clark RB4_R8G8_UINT = 17, 54af6cb4c1SRob Clark RB4_R8G8_SINT = 18, 55af6cb4c1SRob Clark RB4_R16_FLOAT = 21, 56af6cb4c1SRob Clark RB4_R16_UINT = 22, 57af6cb4c1SRob Clark RB4_R16_SINT = 23, 58bc00ae02SRob Clark RB4_R8G8B8_UNORM = 25, 59bc00ae02SRob Clark RB4_R8G8B8A8_UNORM = 26, 60af6cb4c1SRob Clark RB4_R8G8B8A8_SNORM = 28, 61af6cb4c1SRob Clark RB4_R8G8B8A8_UINT = 29, 62af6cb4c1SRob Clark RB4_R8G8B8A8_SINT = 30, 63af6cb4c1SRob Clark RB4_R10G10B10A2_UNORM = 31, 64af6cb4c1SRob Clark RB4_R10G10B10A2_UINT = 34, 65af6cb4c1SRob Clark RB4_R11G11B10_FLOAT = 39, 66af6cb4c1SRob Clark RB4_R16G16_FLOAT = 42, 67af6cb4c1SRob Clark RB4_R16G16_UINT = 43, 68af6cb4c1SRob Clark RB4_R16G16_SINT = 44, 69af6cb4c1SRob Clark RB4_R32_FLOAT = 45, 70af6cb4c1SRob Clark RB4_R32_UINT = 46, 71af6cb4c1SRob Clark RB4_R32_SINT = 47, 72af6cb4c1SRob Clark RB4_R16G16B16A16_FLOAT = 54, 73af6cb4c1SRob Clark RB4_R16G16B16A16_UINT = 55, 74af6cb4c1SRob Clark RB4_R16G16B16A16_SINT = 56, 75af6cb4c1SRob Clark RB4_R32G32_FLOAT = 57, 76af6cb4c1SRob Clark RB4_R32G32_UINT = 58, 77af6cb4c1SRob Clark RB4_R32G32_SINT = 59, 78af6cb4c1SRob Clark RB4_R32G32B32A32_FLOAT = 60, 79af6cb4c1SRob Clark RB4_R32G32B32A32_UINT = 61, 80af6cb4c1SRob Clark RB4_R32G32B32A32_SINT = 62, 81bc00ae02SRob Clark }; 82bc00ae02SRob Clark 83bc00ae02SRob Clark enum a4xx_tile_mode { 84bc00ae02SRob Clark TILE4_LINEAR = 0, 85bc00ae02SRob Clark TILE4_3 = 3, 86bc00ae02SRob Clark }; 87bc00ae02SRob Clark 88bc00ae02SRob Clark enum a4xx_rb_blend_opcode { 89bc00ae02SRob Clark BLEND_DST_PLUS_SRC = 0, 90bc00ae02SRob Clark BLEND_SRC_MINUS_DST = 1, 91bc00ae02SRob Clark BLEND_DST_MINUS_SRC = 2, 92bc00ae02SRob Clark BLEND_MIN_DST_SRC = 3, 93bc00ae02SRob Clark BLEND_MAX_DST_SRC = 4, 94bc00ae02SRob Clark }; 95bc00ae02SRob Clark 96bc00ae02SRob Clark enum a4xx_vtx_fmt { 978a264743SRob Clark VFMT4_32_FLOAT = 1, 988a264743SRob Clark VFMT4_32_32_FLOAT = 2, 998a264743SRob Clark VFMT4_32_32_32_FLOAT = 3, 1008a264743SRob Clark VFMT4_32_32_32_32_FLOAT = 4, 1018a264743SRob Clark VFMT4_16_FLOAT = 5, 1028a264743SRob Clark VFMT4_16_16_FLOAT = 6, 1038a264743SRob Clark VFMT4_16_16_16_FLOAT = 7, 1048a264743SRob Clark VFMT4_16_16_16_16_FLOAT = 8, 1058a264743SRob Clark VFMT4_32_FIXED = 9, 1068a264743SRob Clark VFMT4_32_32_FIXED = 10, 1078a264743SRob Clark VFMT4_32_32_32_FIXED = 11, 1088a264743SRob Clark VFMT4_32_32_32_32_FIXED = 12, 1098a264743SRob Clark VFMT4_16_SINT = 16, 1108a264743SRob Clark VFMT4_16_16_SINT = 17, 1118a264743SRob Clark VFMT4_16_16_16_SINT = 18, 1128a264743SRob Clark VFMT4_16_16_16_16_SINT = 19, 1138a264743SRob Clark VFMT4_16_UINT = 20, 1148a264743SRob Clark VFMT4_16_16_UINT = 21, 1158a264743SRob Clark VFMT4_16_16_16_UINT = 22, 1168a264743SRob Clark VFMT4_16_16_16_16_UINT = 23, 1178a264743SRob Clark VFMT4_16_SNORM = 24, 1188a264743SRob Clark VFMT4_16_16_SNORM = 25, 1198a264743SRob Clark VFMT4_16_16_16_SNORM = 26, 1208a264743SRob Clark VFMT4_16_16_16_16_SNORM = 27, 1218a264743SRob Clark VFMT4_16_UNORM = 28, 1228a264743SRob Clark VFMT4_16_16_UNORM = 29, 1238a264743SRob Clark VFMT4_16_16_16_UNORM = 30, 1248a264743SRob Clark VFMT4_16_16_16_16_UNORM = 31, 125af6cb4c1SRob Clark VFMT4_32_UINT = 32, 126af6cb4c1SRob Clark VFMT4_32_32_UINT = 33, 127af6cb4c1SRob Clark VFMT4_32_32_32_UINT = 34, 128af6cb4c1SRob Clark VFMT4_32_32_32_32_UINT = 35, 129af6cb4c1SRob Clark VFMT4_32_SINT = 36, 1308a264743SRob Clark VFMT4_32_32_SINT = 37, 131af6cb4c1SRob Clark VFMT4_32_32_32_SINT = 38, 132af6cb4c1SRob Clark VFMT4_32_32_32_32_SINT = 39, 1338a264743SRob Clark VFMT4_8_UINT = 40, 1348a264743SRob Clark VFMT4_8_8_UINT = 41, 1358a264743SRob Clark VFMT4_8_8_8_UINT = 42, 1368a264743SRob Clark VFMT4_8_8_8_8_UINT = 43, 1378a264743SRob Clark VFMT4_8_UNORM = 44, 1388a264743SRob Clark VFMT4_8_8_UNORM = 45, 1398a264743SRob Clark VFMT4_8_8_8_UNORM = 46, 1408a264743SRob Clark VFMT4_8_8_8_8_UNORM = 47, 1418a264743SRob Clark VFMT4_8_SINT = 48, 1428a264743SRob Clark VFMT4_8_8_SINT = 49, 1438a264743SRob Clark VFMT4_8_8_8_SINT = 50, 1448a264743SRob Clark VFMT4_8_8_8_8_SINT = 51, 1458a264743SRob Clark VFMT4_8_SNORM = 52, 1468a264743SRob Clark VFMT4_8_8_SNORM = 53, 1478a264743SRob Clark VFMT4_8_8_8_SNORM = 54, 1488a264743SRob Clark VFMT4_8_8_8_8_SNORM = 55, 1498a264743SRob Clark VFMT4_10_10_10_2_UINT = 60, 1508a264743SRob Clark VFMT4_10_10_10_2_UNORM = 61, 1518a264743SRob Clark VFMT4_10_10_10_2_SINT = 62, 1528a264743SRob Clark VFMT4_10_10_10_2_SNORM = 63, 153bc00ae02SRob Clark }; 154bc00ae02SRob Clark 155bc00ae02SRob Clark enum a4xx_tex_fmt { 1568a264743SRob Clark TFMT4_5_6_5_UNORM = 11, 1578a264743SRob Clark TFMT4_5_5_5_1_UNORM = 10, 1588a264743SRob Clark TFMT4_4_4_4_4_UNORM = 8, 1598a264743SRob Clark TFMT4_X8Z24_UNORM = 71, 1608a264743SRob Clark TFMT4_10_10_10_2_UNORM = 33, 1618a264743SRob Clark TFMT4_A8_UNORM = 3, 1628a264743SRob Clark TFMT4_L8_A8_UNORM = 13, 1638a264743SRob Clark TFMT4_8_UNORM = 4, 1648a264743SRob Clark TFMT4_8_8_UNORM = 14, 1658a264743SRob Clark TFMT4_8_8_8_8_UNORM = 28, 1668217e97aSRob Clark TFMT4_8_SNORM = 5, 167af6cb4c1SRob Clark TFMT4_8_8_SNORM = 15, 168af6cb4c1SRob Clark TFMT4_8_8_8_8_SNORM = 29, 1698217e97aSRob Clark TFMT4_8_UINT = 6, 170af6cb4c1SRob Clark TFMT4_8_8_UINT = 16, 171af6cb4c1SRob Clark TFMT4_8_8_8_8_UINT = 30, 1728217e97aSRob Clark TFMT4_8_SINT = 7, 173af6cb4c1SRob Clark TFMT4_8_8_SINT = 17, 174af6cb4c1SRob Clark TFMT4_8_8_8_8_SINT = 31, 175af6cb4c1SRob Clark TFMT4_16_UINT = 21, 176af6cb4c1SRob Clark TFMT4_16_16_UINT = 41, 177af6cb4c1SRob Clark TFMT4_16_16_16_16_UINT = 54, 178af6cb4c1SRob Clark TFMT4_16_SINT = 22, 179af6cb4c1SRob Clark TFMT4_16_16_SINT = 42, 180af6cb4c1SRob Clark TFMT4_16_16_16_16_SINT = 55, 181af6cb4c1SRob Clark TFMT4_32_UINT = 44, 182af6cb4c1SRob Clark TFMT4_32_32_UINT = 57, 183af6cb4c1SRob Clark TFMT4_32_32_32_32_UINT = 64, 184af6cb4c1SRob Clark TFMT4_32_SINT = 45, 185af6cb4c1SRob Clark TFMT4_32_32_SINT = 58, 186af6cb4c1SRob Clark TFMT4_32_32_32_32_SINT = 65, 1878a264743SRob Clark TFMT4_16_FLOAT = 20, 1888a264743SRob Clark TFMT4_16_16_FLOAT = 40, 1898a264743SRob Clark TFMT4_16_16_16_16_FLOAT = 53, 1908a264743SRob Clark TFMT4_32_FLOAT = 43, 1918a264743SRob Clark TFMT4_32_32_FLOAT = 56, 1928a264743SRob Clark TFMT4_32_32_32_32_FLOAT = 63, 193af6cb4c1SRob Clark TFMT4_9_9_9_E5_FLOAT = 32, 194af6cb4c1SRob Clark TFMT4_11_11_10_FLOAT = 37, 195af6cb4c1SRob Clark TFMT4_ATC_RGB = 100, 196af6cb4c1SRob Clark TFMT4_ATC_RGBA_EXPLICIT = 101, 197af6cb4c1SRob Clark TFMT4_ATC_RGBA_INTERPOLATED = 102, 198af6cb4c1SRob Clark TFMT4_ETC2_RG11_UNORM = 103, 199af6cb4c1SRob Clark TFMT4_ETC2_RG11_SNORM = 104, 200af6cb4c1SRob Clark TFMT4_ETC2_R11_UNORM = 105, 201af6cb4c1SRob Clark TFMT4_ETC2_R11_SNORM = 106, 202af6cb4c1SRob Clark TFMT4_ETC1 = 107, 203af6cb4c1SRob Clark TFMT4_ETC2_RGB8 = 108, 204af6cb4c1SRob Clark TFMT4_ETC2_RGBA8 = 109, 205af6cb4c1SRob Clark TFMT4_ETC2_RGB8A1 = 110, 206af6cb4c1SRob Clark TFMT4_ASTC_4x4 = 111, 207af6cb4c1SRob Clark TFMT4_ASTC_5x4 = 112, 208af6cb4c1SRob Clark TFMT4_ASTC_5x5 = 113, 209af6cb4c1SRob Clark TFMT4_ASTC_6x5 = 114, 210af6cb4c1SRob Clark TFMT4_ASTC_6x6 = 115, 211af6cb4c1SRob Clark TFMT4_ASTC_8x5 = 116, 212af6cb4c1SRob Clark TFMT4_ASTC_8x6 = 117, 213af6cb4c1SRob Clark TFMT4_ASTC_8x8 = 118, 214af6cb4c1SRob Clark TFMT4_ASTC_10x5 = 119, 215af6cb4c1SRob Clark TFMT4_ASTC_10x6 = 120, 216af6cb4c1SRob Clark TFMT4_ASTC_10x8 = 121, 217af6cb4c1SRob Clark TFMT4_ASTC_10x10 = 122, 218af6cb4c1SRob Clark TFMT4_ASTC_12x10 = 123, 219af6cb4c1SRob Clark TFMT4_ASTC_12x12 = 124, 2208a264743SRob Clark }; 2218a264743SRob Clark 2228a264743SRob Clark enum a4xx_tex_fetchsize { 2238a264743SRob Clark TFETCH4_1_BYTE = 0, 2248a264743SRob Clark TFETCH4_2_BYTE = 1, 2258a264743SRob Clark TFETCH4_4_BYTE = 2, 2268a264743SRob Clark TFETCH4_8_BYTE = 3, 2278a264743SRob Clark TFETCH4_16_BYTE = 4, 228bc00ae02SRob Clark }; 229bc00ae02SRob Clark 230bc00ae02SRob Clark enum a4xx_depth_format { 231bc00ae02SRob Clark DEPTH4_NONE = 0, 232bc00ae02SRob Clark DEPTH4_16 = 1, 233bc00ae02SRob Clark DEPTH4_24_8 = 2, 2342d3584ebSRob Clark DEPTH4_32 = 3, 235bc00ae02SRob Clark }; 236bc00ae02SRob Clark 237af6cb4c1SRob Clark enum a4xx_tess_spacing { 238af6cb4c1SRob Clark EQUAL_SPACING = 0, 239af6cb4c1SRob Clark ODD_SPACING = 2, 240af6cb4c1SRob Clark EVEN_SPACING = 3, 241af6cb4c1SRob Clark }; 242af6cb4c1SRob Clark 243bc00ae02SRob Clark enum a4xx_tex_filter { 244bc00ae02SRob Clark A4XX_TEX_NEAREST = 0, 245bc00ae02SRob Clark A4XX_TEX_LINEAR = 1, 246af6cb4c1SRob Clark A4XX_TEX_ANISO = 2, 247bc00ae02SRob Clark }; 248bc00ae02SRob Clark 249bc00ae02SRob Clark enum a4xx_tex_clamp { 250bc00ae02SRob Clark A4XX_TEX_REPEAT = 0, 251bc00ae02SRob Clark A4XX_TEX_CLAMP_TO_EDGE = 1, 252bc00ae02SRob Clark A4XX_TEX_MIRROR_REPEAT = 2, 2538217e97aSRob Clark A4XX_TEX_CLAMP_TO_BORDER = 3, 2548217e97aSRob Clark A4XX_TEX_MIRROR_CLAMP = 4, 255bc00ae02SRob Clark }; 256bc00ae02SRob Clark 257af6cb4c1SRob Clark enum a4xx_tex_aniso { 258af6cb4c1SRob Clark A4XX_TEX_ANISO_1 = 0, 259af6cb4c1SRob Clark A4XX_TEX_ANISO_2 = 1, 260af6cb4c1SRob Clark A4XX_TEX_ANISO_4 = 2, 261af6cb4c1SRob Clark A4XX_TEX_ANISO_8 = 3, 262af6cb4c1SRob Clark A4XX_TEX_ANISO_16 = 4, 263af6cb4c1SRob Clark }; 264af6cb4c1SRob Clark 265bc00ae02SRob Clark enum a4xx_tex_swiz { 266bc00ae02SRob Clark A4XX_TEX_X = 0, 267bc00ae02SRob Clark A4XX_TEX_Y = 1, 268bc00ae02SRob Clark A4XX_TEX_Z = 2, 269bc00ae02SRob Clark A4XX_TEX_W = 3, 270bc00ae02SRob Clark A4XX_TEX_ZERO = 4, 271bc00ae02SRob Clark A4XX_TEX_ONE = 5, 272bc00ae02SRob Clark }; 273bc00ae02SRob Clark 274bc00ae02SRob Clark enum a4xx_tex_type { 275bc00ae02SRob Clark A4XX_TEX_1D = 0, 276bc00ae02SRob Clark A4XX_TEX_2D = 1, 277bc00ae02SRob Clark A4XX_TEX_CUBE = 2, 278bc00ae02SRob Clark A4XX_TEX_3D = 3, 279bc00ae02SRob Clark }; 280bc00ae02SRob Clark 281bc00ae02SRob Clark #define A4XX_CGC_HLSQ_EARLY_CYC__MASK 0x00700000 282bc00ae02SRob Clark #define A4XX_CGC_HLSQ_EARLY_CYC__SHIFT 20 283bc00ae02SRob Clark static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) 284bc00ae02SRob Clark { 285bc00ae02SRob Clark return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK; 286bc00ae02SRob Clark } 287bc00ae02SRob Clark #define A4XX_INT0_RBBM_GPU_IDLE 0x00000001 288bc00ae02SRob Clark #define A4XX_INT0_RBBM_AHB_ERROR 0x00000002 289bc00ae02SRob Clark #define A4XX_INT0_RBBM_REG_TIMEOUT 0x00000004 290bc00ae02SRob Clark #define A4XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 291bc00ae02SRob Clark #define A4XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 292bc00ae02SRob Clark #define A4XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020 293bc00ae02SRob Clark #define A4XX_INT0_VFD_ERROR 0x00000040 294bc00ae02SRob Clark #define A4XX_INT0_CP_SW_INT 0x00000080 295bc00ae02SRob Clark #define A4XX_INT0_CP_T0_PACKET_IN_IB 0x00000100 296bc00ae02SRob Clark #define A4XX_INT0_CP_OPCODE_ERROR 0x00000200 297bc00ae02SRob Clark #define A4XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400 298bc00ae02SRob Clark #define A4XX_INT0_CP_HW_FAULT 0x00000800 299bc00ae02SRob Clark #define A4XX_INT0_CP_DMA 0x00001000 300bc00ae02SRob Clark #define A4XX_INT0_CP_IB2_INT 0x00002000 301bc00ae02SRob Clark #define A4XX_INT0_CP_IB1_INT 0x00004000 302bc00ae02SRob Clark #define A4XX_INT0_CP_RB_INT 0x00008000 303bc00ae02SRob Clark #define A4XX_INT0_CP_REG_PROTECT_FAULT 0x00010000 304bc00ae02SRob Clark #define A4XX_INT0_CP_RB_DONE_TS 0x00020000 305bc00ae02SRob Clark #define A4XX_INT0_CP_VS_DONE_TS 0x00040000 306bc00ae02SRob Clark #define A4XX_INT0_CP_PS_DONE_TS 0x00080000 307bc00ae02SRob Clark #define A4XX_INT0_CACHE_FLUSH_TS 0x00100000 308bc00ae02SRob Clark #define A4XX_INT0_CP_AHB_ERROR_HALT 0x00200000 309bc00ae02SRob Clark #define A4XX_INT0_MISC_HANG_DETECT 0x01000000 310bc00ae02SRob Clark #define A4XX_INT0_UCHE_OOB_ACCESS 0x02000000 311bc00ae02SRob Clark #define REG_A4XX_RB_GMEM_BASE_ADDR 0x00000cc0 312bc00ae02SRob Clark 313bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_0 0x00000cc7 314bc00ae02SRob Clark 315bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_1 0x00000cc8 316bc00ae02SRob Clark 317bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_2 0x00000cc9 318bc00ae02SRob Clark 319bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_3 0x00000cca 320bc00ae02SRob Clark 321bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_4 0x00000ccb 322bc00ae02SRob Clark 323bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_5 0x00000ccc 324bc00ae02SRob Clark 325bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_6 0x00000ccd 326bc00ae02SRob Clark 327bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_RB_SEL_7 0x00000cce 328bc00ae02SRob Clark 329bc00ae02SRob Clark #define REG_A4XX_RB_PERFCTR_CCU_SEL_3 0x00000cd2 330bc00ae02SRob Clark 331bc00ae02SRob Clark #define REG_A4XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0 332bc00ae02SRob Clark #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff 333bc00ae02SRob Clark #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0 334bc00ae02SRob Clark static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) 335bc00ae02SRob Clark { 336bc00ae02SRob Clark return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK; 337bc00ae02SRob Clark } 338bc00ae02SRob Clark #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x3fff0000 339bc00ae02SRob Clark #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 16 340bc00ae02SRob Clark static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) 341bc00ae02SRob Clark { 342bc00ae02SRob Clark return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK; 343bc00ae02SRob Clark } 344bc00ae02SRob Clark 345bc00ae02SRob Clark #define REG_A4XX_RB_CLEAR_COLOR_DW0 0x000020cc 346bc00ae02SRob Clark 347bc00ae02SRob Clark #define REG_A4XX_RB_CLEAR_COLOR_DW1 0x000020cd 348bc00ae02SRob Clark 349bc00ae02SRob Clark #define REG_A4XX_RB_CLEAR_COLOR_DW2 0x000020ce 350bc00ae02SRob Clark 351bc00ae02SRob Clark #define REG_A4XX_RB_CLEAR_COLOR_DW3 0x000020cf 352bc00ae02SRob Clark 353bc00ae02SRob Clark #define REG_A4XX_RB_MODE_CONTROL 0x000020a0 354bc00ae02SRob Clark #define A4XX_RB_MODE_CONTROL_WIDTH__MASK 0x0000003f 355bc00ae02SRob Clark #define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT 0 356bc00ae02SRob Clark static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) 357bc00ae02SRob Clark { 358bc00ae02SRob Clark return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK; 359bc00ae02SRob Clark } 360bc00ae02SRob Clark #define A4XX_RB_MODE_CONTROL_HEIGHT__MASK 0x00003f00 361bc00ae02SRob Clark #define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT 8 362bc00ae02SRob Clark static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) 363bc00ae02SRob Clark { 364bc00ae02SRob Clark return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK; 365bc00ae02SRob Clark } 366bc00ae02SRob Clark 367bc00ae02SRob Clark #define REG_A4XX_RB_RENDER_CONTROL 0x000020a1 368bc00ae02SRob Clark #define A4XX_RB_RENDER_CONTROL_BINNING_PASS 0x00000001 369bc00ae02SRob Clark #define A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00000020 370bc00ae02SRob Clark 371bc00ae02SRob Clark #define REG_A4XX_RB_MSAA_CONTROL 0x000020a2 372bc00ae02SRob Clark #define A4XX_RB_MSAA_CONTROL_DISABLE 0x00001000 373bc00ae02SRob Clark #define A4XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000e000 374bc00ae02SRob Clark #define A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 13 375bc00ae02SRob Clark static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val) 376bc00ae02SRob Clark { 377bc00ae02SRob Clark return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK; 378bc00ae02SRob Clark } 379bc00ae02SRob Clark 3808a264743SRob Clark #define REG_A4XX_RB_RENDER_CONTROL2 0x000020a3 3818a264743SRob Clark #define A4XX_RB_RENDER_CONTROL2_XCOORD 0x00000001 3828a264743SRob Clark #define A4XX_RB_RENDER_CONTROL2_YCOORD 0x00000002 3838a264743SRob Clark #define A4XX_RB_RENDER_CONTROL2_ZCOORD 0x00000004 3848a264743SRob Clark #define A4XX_RB_RENDER_CONTROL2_WCOORD 0x00000008 385af6cb4c1SRob Clark #define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK 0x00000010 3868a264743SRob Clark #define A4XX_RB_RENDER_CONTROL2_FACENESS 0x00000020 387af6cb4c1SRob Clark #define A4XX_RB_RENDER_CONTROL2_SAMPLEID 0x00000040 3888a264743SRob Clark #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK 0x00000380 3898a264743SRob Clark #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT 7 3908a264743SRob Clark static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val) 391bc00ae02SRob Clark { 3928a264743SRob Clark return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK; 393bc00ae02SRob Clark } 394af6cb4c1SRob Clark #define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR 0x00000800 3958a264743SRob Clark #define A4XX_RB_RENDER_CONTROL2_VARYING 0x00001000 396bc00ae02SRob Clark 397bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; } 398bc00ae02SRob Clark 399bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; } 400bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008 401bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL_BLEND 0x00000010 402bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL_BLEND2 0x00000020 403bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL_FASTCLEAR 0x00000400 404bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL_B11 0x00000800 405bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000 406bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24 407bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 408bc00ae02SRob Clark { 409bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 410bc00ae02SRob Clark } 411bc00ae02SRob Clark 412bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; } 413bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f 414bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 415bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val) 416bc00ae02SRob Clark { 417bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 418bc00ae02SRob Clark } 419af6cb4c1SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0 420af6cb4c1SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6 421af6cb4c1SRob Clark static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val) 422af6cb4c1SRob Clark { 423af6cb4c1SRob Clark return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 424af6cb4c1SRob Clark } 425bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00000600 426bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 9 427bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 428bc00ae02SRob Clark { 429bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK; 430bc00ae02SRob Clark } 431bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00001800 432bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 11 433bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 434bc00ae02SRob Clark { 435bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 436bc00ae02SRob Clark } 437af6cb4c1SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00002000 4382d3584ebSRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xffffc000 439bc00ae02SRob Clark #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 14 440bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) 441bc00ae02SRob Clark { 442bc00ae02SRob Clark return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; 443bc00ae02SRob Clark } 444bc00ae02SRob Clark 445bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; } 446bc00ae02SRob Clark 447bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; } 4482d3584ebSRob Clark #define A4XX_RB_MRT_CONTROL3_STRIDE__MASK 0x03fffff8 449bc00ae02SRob Clark #define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT 3 450bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val) 451bc00ae02SRob Clark { 452bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT) & A4XX_RB_MRT_CONTROL3_STRIDE__MASK; 453bc00ae02SRob Clark } 454bc00ae02SRob Clark 455bc00ae02SRob Clark static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; } 456bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 457bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 458bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 459bc00ae02SRob Clark { 460bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 461bc00ae02SRob Clark } 462bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 463bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 464bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a4xx_rb_blend_opcode val) 465bc00ae02SRob Clark { 466bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 467bc00ae02SRob Clark } 468bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 469bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 470bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 471bc00ae02SRob Clark { 472bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 473bc00ae02SRob Clark } 474bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 475bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 476bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 477bc00ae02SRob Clark { 478bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 479bc00ae02SRob Clark } 480bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 481bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 482bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a4xx_rb_blend_opcode val) 483bc00ae02SRob Clark { 484bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 485bc00ae02SRob Clark } 486bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 487bc00ae02SRob Clark #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 488bc00ae02SRob Clark static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 489bc00ae02SRob Clark { 490bc00ae02SRob Clark return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 491bc00ae02SRob Clark } 492bc00ae02SRob Clark 4938a264743SRob Clark #define REG_A4XX_RB_BLEND_RED 0x000020f3 4948a264743SRob Clark #define A4XX_RB_BLEND_RED_UINT__MASK 0x00007fff 4958a264743SRob Clark #define A4XX_RB_BLEND_RED_UINT__SHIFT 0 4968a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val) 4978a264743SRob Clark { 4988a264743SRob Clark return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK; 4998a264743SRob Clark } 5008a264743SRob Clark #define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 5018a264743SRob Clark #define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16 5028a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val) 5038a264743SRob Clark { 5048a264743SRob Clark return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK; 5058a264743SRob Clark } 5068a264743SRob Clark 5078a264743SRob Clark #define REG_A4XX_RB_BLEND_GREEN 0x000020f4 5088a264743SRob Clark #define A4XX_RB_BLEND_GREEN_UINT__MASK 0x00007fff 5098a264743SRob Clark #define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0 5108a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val) 5118a264743SRob Clark { 5128a264743SRob Clark return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK; 5138a264743SRob Clark } 5148a264743SRob Clark #define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 5158a264743SRob Clark #define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 5168a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val) 5178a264743SRob Clark { 5188a264743SRob Clark return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK; 5198a264743SRob Clark } 5208a264743SRob Clark 5218a264743SRob Clark #define REG_A4XX_RB_BLEND_BLUE 0x000020f5 5228a264743SRob Clark #define A4XX_RB_BLEND_BLUE_UINT__MASK 0x00007fff 5238a264743SRob Clark #define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0 5248a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val) 5258a264743SRob Clark { 5268a264743SRob Clark return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK; 5278a264743SRob Clark } 5288a264743SRob Clark #define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 5298a264743SRob Clark #define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 5308a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val) 5318a264743SRob Clark { 5328a264743SRob Clark return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK; 5338a264743SRob Clark } 5348a264743SRob Clark 5358a264743SRob Clark #define REG_A4XX_RB_BLEND_ALPHA 0x000020f6 5368a264743SRob Clark #define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x00007fff 5378a264743SRob Clark #define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0 5388a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val) 5398a264743SRob Clark { 5408a264743SRob Clark return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK; 5418a264743SRob Clark } 5428a264743SRob Clark #define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 5438a264743SRob Clark #define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 5448a264743SRob Clark static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val) 5458a264743SRob Clark { 5468a264743SRob Clark return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK; 5478a264743SRob Clark } 5488a264743SRob Clark 549bc00ae02SRob Clark #define REG_A4XX_RB_ALPHA_CONTROL 0x000020f8 5508a264743SRob Clark #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff 5518a264743SRob Clark #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 5528a264743SRob Clark static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) 5538a264743SRob Clark { 5548a264743SRob Clark return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; 5558a264743SRob Clark } 556bc00ae02SRob Clark #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 557bc00ae02SRob Clark #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 558bc00ae02SRob Clark #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 559bc00ae02SRob Clark static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 560bc00ae02SRob Clark { 561bc00ae02SRob Clark return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; 562bc00ae02SRob Clark } 563bc00ae02SRob Clark 564bc00ae02SRob Clark #define REG_A4XX_RB_FS_OUTPUT 0x000020f9 565af6cb4c1SRob Clark #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK 0x000000ff 566af6cb4c1SRob Clark #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT 0 567af6cb4c1SRob Clark static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val) 568af6cb4c1SRob Clark { 569af6cb4c1SRob Clark return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK; 570af6cb4c1SRob Clark } 571bc00ae02SRob Clark #define A4XX_RB_FS_OUTPUT_FAST_CLEAR 0x00000100 572bc00ae02SRob Clark #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000 573bc00ae02SRob Clark #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT 16 574bc00ae02SRob Clark static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val) 575bc00ae02SRob Clark { 576bc00ae02SRob Clark return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK; 577bc00ae02SRob Clark } 578bc00ae02SRob Clark 5792d3584ebSRob Clark #define REG_A4XX_RB_SAMPLE_COUNT_CONTROL 0x000020fa 5802d3584ebSRob Clark #define A4XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 5812d3584ebSRob Clark #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK 0xfffffffc 5822d3584ebSRob Clark #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT 2 5832d3584ebSRob Clark static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val) 5842d3584ebSRob Clark { 5852d3584ebSRob Clark return ((val >> 2) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK; 5862d3584ebSRob Clark } 5872d3584ebSRob Clark 588af6cb4c1SRob Clark #define REG_A4XX_RB_RENDER_COMPONENTS 0x000020fb 589af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f 590af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0 591af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) 592bc00ae02SRob Clark { 593af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT0__MASK; 594af6cb4c1SRob Clark } 595af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0 596af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4 597af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) 598af6cb4c1SRob Clark { 599af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT1__MASK; 600af6cb4c1SRob Clark } 601af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00 602af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8 603af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) 604af6cb4c1SRob Clark { 605af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT2__MASK; 606af6cb4c1SRob Clark } 607af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000 608af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12 609af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) 610af6cb4c1SRob Clark { 611af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT3__MASK; 612af6cb4c1SRob Clark } 613af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000 614af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16 615af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) 616af6cb4c1SRob Clark { 617af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT4__MASK; 618af6cb4c1SRob Clark } 619af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000 620af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20 621af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) 622af6cb4c1SRob Clark { 623af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT5__MASK; 624af6cb4c1SRob Clark } 625af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000 626af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24 627af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) 628af6cb4c1SRob Clark { 629af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT6__MASK; 630af6cb4c1SRob Clark } 631af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000 632af6cb4c1SRob Clark #define A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28 633af6cb4c1SRob Clark static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) 634af6cb4c1SRob Clark { 635af6cb4c1SRob Clark return ((val) << A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT7__MASK; 636bc00ae02SRob Clark } 637bc00ae02SRob Clark 638bc00ae02SRob Clark #define REG_A4XX_RB_COPY_CONTROL 0x000020fc 639bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003 640bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0 641bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) 642bc00ae02SRob Clark { 643bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK; 644bc00ae02SRob Clark } 645bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_MODE__MASK 0x00000070 646bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_MODE__SHIFT 4 647bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) 648bc00ae02SRob Clark { 649bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_CONTROL_MODE__SHIFT) & A4XX_RB_COPY_CONTROL_MODE__MASK; 650bc00ae02SRob Clark } 651bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00 652bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8 653bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) 654bc00ae02SRob Clark { 655bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK; 656bc00ae02SRob Clark } 657bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000 658bc00ae02SRob Clark #define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14 659bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) 660bc00ae02SRob Clark { 661bc00ae02SRob Clark return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK; 662bc00ae02SRob Clark } 663bc00ae02SRob Clark 664bc00ae02SRob Clark #define REG_A4XX_RB_COPY_DEST_BASE 0x000020fd 6658a264743SRob Clark #define A4XX_RB_COPY_DEST_BASE_BASE__MASK 0xffffffe0 6668a264743SRob Clark #define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT 5 667bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val) 668bc00ae02SRob Clark { 6698a264743SRob Clark return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK; 670bc00ae02SRob Clark } 671bc00ae02SRob Clark 672bc00ae02SRob Clark #define REG_A4XX_RB_COPY_DEST_PITCH 0x000020fe 673bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff 674bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0 675bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) 676bc00ae02SRob Clark { 677bc00ae02SRob Clark return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK; 678bc00ae02SRob Clark } 679bc00ae02SRob Clark 680bc00ae02SRob Clark #define REG_A4XX_RB_COPY_DEST_INFO 0x000020ff 681bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc 682bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2 683bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val) 684bc00ae02SRob Clark { 685bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A4XX_RB_COPY_DEST_INFO_FORMAT__MASK; 686bc00ae02SRob Clark } 687bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 688bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 689bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) 690bc00ae02SRob Clark { 691bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A4XX_RB_COPY_DEST_INFO_SWAP__MASK; 692bc00ae02SRob Clark } 693bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 694bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 695bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 696bc00ae02SRob Clark { 697bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 698bc00ae02SRob Clark } 699bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000 700bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14 701bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) 702bc00ae02SRob Clark { 703bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK; 704bc00ae02SRob Clark } 705bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000 706bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18 707bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) 708bc00ae02SRob Clark { 709bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK; 710bc00ae02SRob Clark } 711bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_TILE__MASK 0x03000000 712bc00ae02SRob Clark #define A4XX_RB_COPY_DEST_INFO_TILE__SHIFT 24 713bc00ae02SRob Clark static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val) 714bc00ae02SRob Clark { 715bc00ae02SRob Clark return ((val) << A4XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A4XX_RB_COPY_DEST_INFO_TILE__MASK; 716bc00ae02SRob Clark } 717bc00ae02SRob Clark 718bc00ae02SRob Clark #define REG_A4XX_RB_FS_OUTPUT_REG 0x00002100 719af6cb4c1SRob Clark #define A4XX_RB_FS_OUTPUT_REG_MRT__MASK 0x0000000f 720af6cb4c1SRob Clark #define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT 0 721af6cb4c1SRob Clark static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val) 722af6cb4c1SRob Clark { 723af6cb4c1SRob Clark return ((val) << A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_RB_FS_OUTPUT_REG_MRT__MASK; 724af6cb4c1SRob Clark } 725bc00ae02SRob Clark #define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z 0x00000020 726bc00ae02SRob Clark 727bc00ae02SRob Clark #define REG_A4XX_RB_DEPTH_CONTROL 0x00002101 728bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001 729bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002 730bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004 731bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070 732bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4 733bc00ae02SRob Clark static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) 734bc00ae02SRob Clark { 735bc00ae02SRob Clark return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK; 736bc00ae02SRob Clark } 737bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080 738bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000 739bc00ae02SRob Clark #define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000 740bc00ae02SRob Clark 741bc00ae02SRob Clark #define REG_A4XX_RB_DEPTH_CLEAR 0x00002102 742bc00ae02SRob Clark 743bc00ae02SRob Clark #define REG_A4XX_RB_DEPTH_INFO 0x00002103 744bc00ae02SRob Clark #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003 745bc00ae02SRob Clark #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 746bc00ae02SRob Clark static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val) 747bc00ae02SRob Clark { 748bc00ae02SRob Clark return ((val) << A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 749bc00ae02SRob Clark } 750bc00ae02SRob Clark #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 751bc00ae02SRob Clark #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 752bc00ae02SRob Clark static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 753bc00ae02SRob Clark { 754bc00ae02SRob Clark return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 755bc00ae02SRob Clark } 756bc00ae02SRob Clark 757bc00ae02SRob Clark #define REG_A4XX_RB_DEPTH_PITCH 0x00002104 758bc00ae02SRob Clark #define A4XX_RB_DEPTH_PITCH__MASK 0xffffffff 759bc00ae02SRob Clark #define A4XX_RB_DEPTH_PITCH__SHIFT 0 760bc00ae02SRob Clark static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val) 761bc00ae02SRob Clark { 7628a264743SRob Clark return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK; 763bc00ae02SRob Clark } 764bc00ae02SRob Clark 765bc00ae02SRob Clark #define REG_A4XX_RB_DEPTH_PITCH2 0x00002105 766bc00ae02SRob Clark #define A4XX_RB_DEPTH_PITCH2__MASK 0xffffffff 767bc00ae02SRob Clark #define A4XX_RB_DEPTH_PITCH2__SHIFT 0 768bc00ae02SRob Clark static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val) 769bc00ae02SRob Clark { 7708a264743SRob Clark return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK; 771bc00ae02SRob Clark } 772bc00ae02SRob Clark 773bc00ae02SRob Clark #define REG_A4XX_RB_STENCIL_CONTROL 0x00002106 774bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 775bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 776bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 777bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 778bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 779bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 780bc00ae02SRob Clark { 781bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC__MASK; 782bc00ae02SRob Clark } 783bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 784bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 785bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 786bc00ae02SRob Clark { 787bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL__MASK; 788bc00ae02SRob Clark } 789bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 790bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 791bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 792bc00ae02SRob Clark { 793bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS__MASK; 794bc00ae02SRob Clark } 795bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 796bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 797bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 798bc00ae02SRob Clark { 799bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 800bc00ae02SRob Clark } 801bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 802bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 803bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 804bc00ae02SRob Clark { 805bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 806bc00ae02SRob Clark } 807bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 808bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 809bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 810bc00ae02SRob Clark { 811bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 812bc00ae02SRob Clark } 813bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 814bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 815bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 816bc00ae02SRob Clark { 817bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 818bc00ae02SRob Clark } 819bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 820bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 821bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 822bc00ae02SRob Clark { 823bc00ae02SRob Clark return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 824bc00ae02SRob Clark } 825bc00ae02SRob Clark 826bc00ae02SRob Clark #define REG_A4XX_RB_STENCIL_CONTROL2 0x00002107 827bc00ae02SRob Clark #define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER 0x00000001 828bc00ae02SRob Clark 8292d3584ebSRob Clark #define REG_A4XX_RB_STENCIL_INFO 0x00002108 8302d3584ebSRob Clark #define A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 8312d3584ebSRob Clark #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff000 8322d3584ebSRob Clark #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 12 8332d3584ebSRob Clark static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) 8342d3584ebSRob Clark { 8352d3584ebSRob Clark return ((val >> 12) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK; 8362d3584ebSRob Clark } 8372d3584ebSRob Clark 8382d3584ebSRob Clark #define REG_A4XX_RB_STENCIL_PITCH 0x00002109 8392d3584ebSRob Clark #define A4XX_RB_STENCIL_PITCH__MASK 0xffffffff 8402d3584ebSRob Clark #define A4XX_RB_STENCIL_PITCH__SHIFT 0 8412d3584ebSRob Clark static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val) 8422d3584ebSRob Clark { 8432d3584ebSRob Clark return ((val >> 5) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK; 8442d3584ebSRob Clark } 8452d3584ebSRob Clark 846bc00ae02SRob Clark #define REG_A4XX_RB_STENCILREFMASK 0x0000210b 847bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 848bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 849bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 850bc00ae02SRob Clark { 851bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILREF__MASK; 852bc00ae02SRob Clark } 853bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 854bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 855bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 856bc00ae02SRob Clark { 857bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILMASK__MASK; 858bc00ae02SRob Clark } 859bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 860bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 861bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 862bc00ae02SRob Clark { 863bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 864bc00ae02SRob Clark } 865bc00ae02SRob Clark 866bc00ae02SRob Clark #define REG_A4XX_RB_STENCILREFMASK_BF 0x0000210c 867bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 868bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 869bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 870bc00ae02SRob Clark { 871bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 872bc00ae02SRob Clark } 873bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 874bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 875bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 876bc00ae02SRob Clark { 877bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 878bc00ae02SRob Clark } 879bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 880bc00ae02SRob Clark #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 881bc00ae02SRob Clark static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 882bc00ae02SRob Clark { 883bc00ae02SRob Clark return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 884bc00ae02SRob Clark } 885bc00ae02SRob Clark 886bc00ae02SRob Clark #define REG_A4XX_RB_BIN_OFFSET 0x0000210d 887bc00ae02SRob Clark #define A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 888bc00ae02SRob Clark #define A4XX_RB_BIN_OFFSET_X__MASK 0x00007fff 889bc00ae02SRob Clark #define A4XX_RB_BIN_OFFSET_X__SHIFT 0 890bc00ae02SRob Clark static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val) 891bc00ae02SRob Clark { 892bc00ae02SRob Clark return ((val) << A4XX_RB_BIN_OFFSET_X__SHIFT) & A4XX_RB_BIN_OFFSET_X__MASK; 893bc00ae02SRob Clark } 894bc00ae02SRob Clark #define A4XX_RB_BIN_OFFSET_Y__MASK 0x7fff0000 895bc00ae02SRob Clark #define A4XX_RB_BIN_OFFSET_Y__SHIFT 16 896bc00ae02SRob Clark static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val) 897bc00ae02SRob Clark { 898bc00ae02SRob Clark return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK; 899bc00ae02SRob Clark } 900bc00ae02SRob Clark 9018a264743SRob Clark static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; } 9028a264743SRob Clark 9038a264743SRob Clark static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; } 9048a264743SRob Clark 9058a264743SRob Clark static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; } 906bc00ae02SRob Clark 907bc00ae02SRob Clark #define REG_A4XX_RBBM_HW_VERSION 0x00000000 908bc00ae02SRob Clark 909bc00ae02SRob Clark #define REG_A4XX_RBBM_HW_CONFIGURATION 0x00000002 910bc00ae02SRob Clark 911bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; } 912bc00ae02SRob Clark 913bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; } 914bc00ae02SRob Clark 915bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; } 916bc00ae02SRob Clark 917bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; } 918bc00ae02SRob Clark 919bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; } 920bc00ae02SRob Clark 921bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; } 922bc00ae02SRob Clark 923bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; } 924bc00ae02SRob Clark 925bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; } 926bc00ae02SRob Clark 927bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL_UCHE 0x00000014 928bc00ae02SRob Clark 929bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL2_UCHE 0x00000015 930bc00ae02SRob Clark 931bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL3_UCHE 0x00000016 932bc00ae02SRob Clark 933bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL4_UCHE 0x00000017 934bc00ae02SRob Clark 935bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_HYST_UCHE 0x00000018 936bc00ae02SRob Clark 937bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_DELAY_UCHE 0x00000019 938bc00ae02SRob Clark 939bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_MODE_GPC 0x0000001a 940bc00ae02SRob Clark 941bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_DELAY_GPC 0x0000001b 942bc00ae02SRob Clark 943bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_HYST_GPC 0x0000001c 944bc00ae02SRob Clark 945bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM 0x0000001d 946bc00ae02SRob Clark 947bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000001e 948bc00ae02SRob Clark 949bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x0000001f 950bc00ae02SRob Clark 951bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL 0x00000020 952bc00ae02SRob Clark 953bc00ae02SRob Clark #define REG_A4XX_RBBM_SP_HYST_CNT 0x00000021 954bc00ae02SRob Clark 955bc00ae02SRob Clark #define REG_A4XX_RBBM_SW_RESET_CMD 0x00000022 956bc00ae02SRob Clark 957bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_CTL0 0x00000023 958bc00ae02SRob Clark 959bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_CTL1 0x00000024 960bc00ae02SRob Clark 961bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_CMD 0x00000025 962bc00ae02SRob Clark 963bc00ae02SRob Clark #define REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL 0x00000026 964bc00ae02SRob Clark 965bc00ae02SRob Clark #define REG_A4XX_RBBM_RAM_ACC_63_32 0x00000028 966bc00ae02SRob Clark 967bc00ae02SRob Clark #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x0000002b 968bc00ae02SRob Clark 969bc00ae02SRob Clark #define REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL 0x0000002f 970bc00ae02SRob Clark 971bc00ae02SRob Clark #define REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4 0x00000034 972bc00ae02SRob Clark 973bc00ae02SRob Clark #define REG_A4XX_RBBM_INT_CLEAR_CMD 0x00000036 974bc00ae02SRob Clark 975bc00ae02SRob Clark #define REG_A4XX_RBBM_INT_0_MASK 0x00000037 976bc00ae02SRob Clark 977bc00ae02SRob Clark #define REG_A4XX_RBBM_RBBM_CTL 0x0000003e 978bc00ae02SRob Clark 979bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_DEBUG_CTL 0x0000003f 980bc00ae02SRob Clark 981bc00ae02SRob Clark #define REG_A4XX_RBBM_VBIF_DEBUG_CTL 0x00000041 982bc00ae02SRob Clark 983bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL2 0x00000042 984bc00ae02SRob Clark 985bc00ae02SRob Clark #define REG_A4XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 986bc00ae02SRob Clark 987bc00ae02SRob Clark #define REG_A4XX_RBBM_RESET_CYCLES 0x00000047 988bc00ae02SRob Clark 989bc00ae02SRob Clark #define REG_A4XX_RBBM_EXT_TRACE_BUS_CTL 0x00000049 990bc00ae02SRob Clark 991bc00ae02SRob Clark #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A 0x0000004a 992bc00ae02SRob Clark 993bc00ae02SRob Clark #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B 0x0000004b 994bc00ae02SRob Clark 995bc00ae02SRob Clark #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C 0x0000004c 996bc00ae02SRob Clark 997bc00ae02SRob Clark #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D 0x0000004d 998bc00ae02SRob Clark 999bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_CP_0_LO 0x0000009c 1000bc00ae02SRob Clark 1001bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; } 1002bc00ae02SRob Clark 1003bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; } 1004bc00ae02SRob Clark 1005bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; } 1006bc00ae02SRob Clark 1007bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; } 1008bc00ae02SRob Clark 1009bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; } 1010bc00ae02SRob Clark 1011bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; } 1012bc00ae02SRob Clark 1013bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; } 1014bc00ae02SRob Clark 1015bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; } 1016bc00ae02SRob Clark 1017bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; } 1018bc00ae02SRob Clark 1019bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; } 1020bc00ae02SRob Clark 1021bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; } 1022bc00ae02SRob Clark 1023bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; } 1024bc00ae02SRob Clark 1025bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; } 1026bc00ae02SRob Clark 1027bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; } 1028bc00ae02SRob Clark 1029bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; } 1030bc00ae02SRob Clark 1031bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; } 1032bc00ae02SRob Clark 1033bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM 0x00000080 1034bc00ae02SRob Clark 1035bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM 0x00000081 1036bc00ae02SRob Clark 1037bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_CTL_HLSQ 0x0000008a 1038bc00ae02SRob Clark 1039bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_HYST_HLSQ 0x0000008b 1040bc00ae02SRob Clark 1041bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ 0x0000008c 1042bc00ae02SRob Clark 1043bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM 0x0000008d 1044bc00ae02SRob Clark 1045bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; } 1046bc00ae02SRob Clark 1047bc00ae02SRob Clark static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; } 1048bc00ae02SRob Clark 1049bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168 1050bc00ae02SRob Clark 1051bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170 1052bc00ae02SRob Clark 1053bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0 0x00000171 1054bc00ae02SRob Clark 1055bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1 0x00000172 1056bc00ae02SRob Clark 1057bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2 0x00000173 1058bc00ae02SRob Clark 1059bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000174 1060bc00ae02SRob Clark 1061bc00ae02SRob Clark #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000175 1062bc00ae02SRob Clark 1063bc00ae02SRob Clark #define REG_A4XX_RBBM_GPU_BUSY_MASKED 0x0000017a 1064bc00ae02SRob Clark 1065bc00ae02SRob Clark #define REG_A4XX_RBBM_INT_0_STATUS 0x0000017d 1066bc00ae02SRob Clark 1067bc00ae02SRob Clark #define REG_A4XX_RBBM_CLOCK_STATUS 0x00000182 1068bc00ae02SRob Clark 1069bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_STATUS 0x00000189 1070bc00ae02SRob Clark 1071bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS 0x0000018c 1072bc00ae02SRob Clark 1073bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS 0x0000018d 1074bc00ae02SRob Clark 1075bc00ae02SRob Clark #define REG_A4XX_RBBM_AHB_ERROR_STATUS 0x0000018f 1076bc00ae02SRob Clark 1077bc00ae02SRob Clark #define REG_A4XX_RBBM_STATUS 0x00000191 1078bc00ae02SRob Clark #define A4XX_RBBM_STATUS_HI_BUSY 0x00000001 1079bc00ae02SRob Clark #define A4XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 1080bc00ae02SRob Clark #define A4XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 1081bc00ae02SRob Clark #define A4XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000 1082bc00ae02SRob Clark #define A4XX_RBBM_STATUS_VBIF_BUSY 0x00008000 1083bc00ae02SRob Clark #define A4XX_RBBM_STATUS_TSE_BUSY 0x00010000 1084bc00ae02SRob Clark #define A4XX_RBBM_STATUS_RAS_BUSY 0x00020000 1085bc00ae02SRob Clark #define A4XX_RBBM_STATUS_RB_BUSY 0x00040000 1086bc00ae02SRob Clark #define A4XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 1087bc00ae02SRob Clark #define A4XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 1088bc00ae02SRob Clark #define A4XX_RBBM_STATUS_VFD_BUSY 0x00200000 1089bc00ae02SRob Clark #define A4XX_RBBM_STATUS_VPC_BUSY 0x00400000 1090bc00ae02SRob Clark #define A4XX_RBBM_STATUS_UCHE_BUSY 0x00800000 1091bc00ae02SRob Clark #define A4XX_RBBM_STATUS_SP_BUSY 0x01000000 1092bc00ae02SRob Clark #define A4XX_RBBM_STATUS_TPL1_BUSY 0x02000000 1093bc00ae02SRob Clark #define A4XX_RBBM_STATUS_MARB_BUSY 0x04000000 1094bc00ae02SRob Clark #define A4XX_RBBM_STATUS_VSC_BUSY 0x08000000 1095bc00ae02SRob Clark #define A4XX_RBBM_STATUS_ARB_BUSY 0x10000000 1096bc00ae02SRob Clark #define A4XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 1097bc00ae02SRob Clark #define A4XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000 1098bc00ae02SRob Clark #define A4XX_RBBM_STATUS_GPU_BUSY 0x80000000 1099bc00ae02SRob Clark 1100bc00ae02SRob Clark #define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5 0x0000019f 1101bc00ae02SRob Clark 1102bc00ae02SRob Clark #define REG_A4XX_CP_SCRATCH_UMASK 0x00000228 1103bc00ae02SRob Clark 1104bc00ae02SRob Clark #define REG_A4XX_CP_SCRATCH_ADDR 0x00000229 1105bc00ae02SRob Clark 1106bc00ae02SRob Clark #define REG_A4XX_CP_RB_BASE 0x00000200 1107bc00ae02SRob Clark 1108bc00ae02SRob Clark #define REG_A4XX_CP_RB_CNTL 0x00000201 1109bc00ae02SRob Clark 1110bc00ae02SRob Clark #define REG_A4XX_CP_RB_WPTR 0x00000205 1111bc00ae02SRob Clark 1112bc00ae02SRob Clark #define REG_A4XX_CP_RB_RPTR_ADDR 0x00000203 1113bc00ae02SRob Clark 1114bc00ae02SRob Clark #define REG_A4XX_CP_RB_RPTR 0x00000204 1115bc00ae02SRob Clark 1116bc00ae02SRob Clark #define REG_A4XX_CP_IB1_BASE 0x00000206 1117bc00ae02SRob Clark 1118bc00ae02SRob Clark #define REG_A4XX_CP_IB1_BUFSZ 0x00000207 1119bc00ae02SRob Clark 1120bc00ae02SRob Clark #define REG_A4XX_CP_IB2_BASE 0x00000208 1121bc00ae02SRob Clark 1122bc00ae02SRob Clark #define REG_A4XX_CP_IB2_BUFSZ 0x00000209 1123bc00ae02SRob Clark 1124af6cb4c1SRob Clark #define REG_A4XX_CP_ME_NRT_ADDR 0x0000020c 1125af6cb4c1SRob Clark 1126af6cb4c1SRob Clark #define REG_A4XX_CP_ME_NRT_DATA 0x0000020d 1127af6cb4c1SRob Clark 1128bc00ae02SRob Clark #define REG_A4XX_CP_ME_RB_DONE_DATA 0x00000217 1129bc00ae02SRob Clark 1130bc00ae02SRob Clark #define REG_A4XX_CP_QUEUE_THRESH2 0x00000219 1131bc00ae02SRob Clark 1132bc00ae02SRob Clark #define REG_A4XX_CP_MERCIU_SIZE 0x0000021b 1133bc00ae02SRob Clark 1134bc00ae02SRob Clark #define REG_A4XX_CP_ROQ_ADDR 0x0000021c 1135bc00ae02SRob Clark 1136bc00ae02SRob Clark #define REG_A4XX_CP_ROQ_DATA 0x0000021d 1137bc00ae02SRob Clark 1138bc00ae02SRob Clark #define REG_A4XX_CP_MEQ_ADDR 0x0000021e 1139bc00ae02SRob Clark 1140bc00ae02SRob Clark #define REG_A4XX_CP_MEQ_DATA 0x0000021f 1141bc00ae02SRob Clark 1142bc00ae02SRob Clark #define REG_A4XX_CP_MERCIU_ADDR 0x00000220 1143bc00ae02SRob Clark 1144bc00ae02SRob Clark #define REG_A4XX_CP_MERCIU_DATA 0x00000221 1145bc00ae02SRob Clark 1146bc00ae02SRob Clark #define REG_A4XX_CP_MERCIU_DATA2 0x00000222 1147bc00ae02SRob Clark 1148bc00ae02SRob Clark #define REG_A4XX_CP_PFP_UCODE_ADDR 0x00000223 1149bc00ae02SRob Clark 1150bc00ae02SRob Clark #define REG_A4XX_CP_PFP_UCODE_DATA 0x00000224 1151bc00ae02SRob Clark 1152bc00ae02SRob Clark #define REG_A4XX_CP_ME_RAM_WADDR 0x00000225 1153bc00ae02SRob Clark 1154bc00ae02SRob Clark #define REG_A4XX_CP_ME_RAM_RADDR 0x00000226 1155bc00ae02SRob Clark 1156bc00ae02SRob Clark #define REG_A4XX_CP_ME_RAM_DATA 0x00000227 1157bc00ae02SRob Clark 1158bc00ae02SRob Clark #define REG_A4XX_CP_PREEMPT 0x0000022a 1159bc00ae02SRob Clark 1160bc00ae02SRob Clark #define REG_A4XX_CP_CNTL 0x0000022c 1161bc00ae02SRob Clark 1162bc00ae02SRob Clark #define REG_A4XX_CP_ME_CNTL 0x0000022d 1163bc00ae02SRob Clark 1164bc00ae02SRob Clark #define REG_A4XX_CP_DEBUG 0x0000022e 1165bc00ae02SRob Clark 1166bc00ae02SRob Clark #define REG_A4XX_CP_DEBUG_ECO_CONTROL 0x00000231 1167bc00ae02SRob Clark 1168bc00ae02SRob Clark #define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232 1169bc00ae02SRob Clark 1170bc00ae02SRob Clark #define REG_A4XX_CP_PROTECT_REG_0 0x00000240 1171bc00ae02SRob Clark 1172bc00ae02SRob Clark static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; } 1173bc00ae02SRob Clark 1174bc00ae02SRob Clark static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; } 1175bc00ae02SRob Clark 1176bc00ae02SRob Clark #define REG_A4XX_CP_PROTECT_CTRL 0x00000250 1177bc00ae02SRob Clark 1178bc00ae02SRob Clark #define REG_A4XX_CP_ST_BASE 0x000004c0 1179bc00ae02SRob Clark 1180bc00ae02SRob Clark #define REG_A4XX_CP_STQ_AVAIL 0x000004ce 1181bc00ae02SRob Clark 1182bc00ae02SRob Clark #define REG_A4XX_CP_MERCIU_STAT 0x000004d0 1183bc00ae02SRob Clark 1184bc00ae02SRob Clark #define REG_A4XX_CP_WFI_PEND_CTR 0x000004d2 1185bc00ae02SRob Clark 1186bc00ae02SRob Clark #define REG_A4XX_CP_HW_FAULT 0x000004d8 1187bc00ae02SRob Clark 1188bc00ae02SRob Clark #define REG_A4XX_CP_PROTECT_STATUS 0x000004da 1189bc00ae02SRob Clark 1190bc00ae02SRob Clark #define REG_A4XX_CP_EVENTS_IN_FLIGHT 0x000004dd 1191bc00ae02SRob Clark 1192bc00ae02SRob Clark #define REG_A4XX_CP_PERFCTR_CP_SEL_0 0x00000500 1193bc00ae02SRob Clark 1194bc00ae02SRob Clark #define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b 1195bc00ae02SRob Clark 1196bc00ae02SRob Clark static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; } 1197bc00ae02SRob Clark 1198bc00ae02SRob Clark static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; } 1199bc00ae02SRob Clark 1200bc00ae02SRob Clark #define REG_A4XX_SP_VS_STATUS 0x00000ec0 1201bc00ae02SRob Clark 1202af6cb4c1SRob Clark #define REG_A4XX_SP_MODE_CONTROL 0x00000ec3 1203af6cb4c1SRob Clark 1204bc00ae02SRob Clark #define REG_A4XX_SP_PERFCTR_SP_SEL_11 0x00000ecf 1205bc00ae02SRob Clark 1206bc00ae02SRob Clark #define REG_A4XX_SP_SP_CTRL_REG 0x000022c0 1207bc00ae02SRob Clark #define A4XX_SP_SP_CTRL_REG_BINNING_PASS 0x00080000 1208bc00ae02SRob Clark 1209bc00ae02SRob Clark #define REG_A4XX_SP_INSTR_CACHE_CTRL 0x000022c1 1210af6cb4c1SRob Clark #define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER 0x00000080 1211af6cb4c1SRob Clark #define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER 0x00000100 1212af6cb4c1SRob Clark #define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER 0x00000400 1213bc00ae02SRob Clark 1214bc00ae02SRob Clark #define REG_A4XX_SP_VS_CTRL_REG0 0x000022c4 1215bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 1216bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 1217bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 1218bc00ae02SRob Clark { 1219bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK; 1220bc00ae02SRob Clark } 1221bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_VARYING 0x00000002 1222bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004 1223bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 1224bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 1225bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 1226bc00ae02SRob Clark { 1227bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 1228bc00ae02SRob Clark } 1229bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 1230bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 1231bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 1232bc00ae02SRob Clark { 1233bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 1234bc00ae02SRob Clark } 1235bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 1236bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 1237bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 1238bc00ae02SRob Clark { 1239bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK; 1240bc00ae02SRob Clark } 1241bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000 1242bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20 1243bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 1244bc00ae02SRob Clark { 1245bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; 1246bc00ae02SRob Clark } 1247bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000 1248bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000 1249bc00ae02SRob Clark 1250bc00ae02SRob Clark #define REG_A4XX_SP_VS_CTRL_REG1 0x000022c5 1251bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff 1252bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0 1253bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) 1254bc00ae02SRob Clark { 1255bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK; 1256bc00ae02SRob Clark } 1257bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000 1258bc00ae02SRob Clark #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24 1259bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) 1260bc00ae02SRob Clark { 1261bc00ae02SRob Clark return ((val) << A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK; 1262bc00ae02SRob Clark } 1263bc00ae02SRob Clark 1264bc00ae02SRob Clark #define REG_A4XX_SP_VS_PARAM_REG 0x000022c6 1265bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff 1266bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0 1267bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) 1268bc00ae02SRob Clark { 1269bc00ae02SRob Clark return ((val) << A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_POSREGID__MASK; 1270bc00ae02SRob Clark } 1271bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00 1272bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8 1273bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) 1274bc00ae02SRob Clark { 1275bc00ae02SRob Clark return ((val) << A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK; 1276bc00ae02SRob Clark } 1277bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000 1278bc00ae02SRob Clark #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20 1279bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) 1280bc00ae02SRob Clark { 1281bc00ae02SRob Clark return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; 1282bc00ae02SRob Clark } 1283bc00ae02SRob Clark 1284bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 1285bc00ae02SRob Clark 1286bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 1287bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff 1288bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 1289bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 1290bc00ae02SRob Clark { 1291bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_A_REGID__MASK; 1292bc00ae02SRob Clark } 1293bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00 1294bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9 1295bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 1296bc00ae02SRob Clark { 1297bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 1298bc00ae02SRob Clark } 1299bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000 1300bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 1301bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 1302bc00ae02SRob Clark { 1303bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_B_REGID__MASK; 1304bc00ae02SRob Clark } 1305bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000 1306bc00ae02SRob Clark #define A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25 1307bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 1308bc00ae02SRob Clark { 1309bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 1310bc00ae02SRob Clark } 1311bc00ae02SRob Clark 1312bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; } 1313bc00ae02SRob Clark 1314bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; } 1315bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 1316bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 1317bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 1318bc00ae02SRob Clark { 1319bc00ae02SRob Clark return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 1320bc00ae02SRob Clark } 1321bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 1322bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 1323bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 1324bc00ae02SRob Clark { 1325bc00ae02SRob Clark return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 1326bc00ae02SRob Clark } 1327bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 1328bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 1329bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 1330bc00ae02SRob Clark { 1331bc00ae02SRob Clark return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 1332bc00ae02SRob Clark } 1333bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 1334bc00ae02SRob Clark #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 1335bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 1336bc00ae02SRob Clark { 1337bc00ae02SRob Clark return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 1338bc00ae02SRob Clark } 1339bc00ae02SRob Clark 1340bc00ae02SRob Clark #define REG_A4XX_SP_VS_OBJ_OFFSET_REG 0x000022e0 1341bc00ae02SRob Clark #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1342bc00ae02SRob Clark #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1343bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1344bc00ae02SRob Clark { 1345bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1346bc00ae02SRob Clark } 1347bc00ae02SRob Clark #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1348bc00ae02SRob Clark #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1349bc00ae02SRob Clark static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1350bc00ae02SRob Clark { 1351bc00ae02SRob Clark return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1352bc00ae02SRob Clark } 1353bc00ae02SRob Clark 1354bc00ae02SRob Clark #define REG_A4XX_SP_VS_OBJ_START 0x000022e1 1355bc00ae02SRob Clark 1356bc00ae02SRob Clark #define REG_A4XX_SP_VS_PVT_MEM_PARAM 0x000022e2 1357bc00ae02SRob Clark 1358bc00ae02SRob Clark #define REG_A4XX_SP_VS_PVT_MEM_ADDR 0x000022e3 1359bc00ae02SRob Clark 1360bc00ae02SRob Clark #define REG_A4XX_SP_VS_LENGTH_REG 0x000022e5 1361bc00ae02SRob Clark 1362bc00ae02SRob Clark #define REG_A4XX_SP_FS_CTRL_REG0 0x000022e8 1363bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 1364bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 1365bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 1366bc00ae02SRob Clark { 1367bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK; 1368bc00ae02SRob Clark } 1369bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_VARYING 0x00000002 1370bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004 1371bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 1372bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 1373bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 1374bc00ae02SRob Clark { 1375bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 1376bc00ae02SRob Clark } 1377bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 1378bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 1379bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 1380bc00ae02SRob Clark { 1381bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 1382bc00ae02SRob Clark } 1383bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 1384bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 1385bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 1386bc00ae02SRob Clark { 1387bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK; 1388bc00ae02SRob Clark } 1389bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 1390bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 1391bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 1392bc00ae02SRob Clark { 1393bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 1394bc00ae02SRob Clark } 1395bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000 1396bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000 1397bc00ae02SRob Clark 1398bc00ae02SRob Clark #define REG_A4XX_SP_FS_CTRL_REG1 0x000022e9 1399bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff 1400bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0 1401bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) 1402bc00ae02SRob Clark { 1403bc00ae02SRob Clark return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK; 1404bc00ae02SRob Clark } 14058a264743SRob Clark #define A4XX_SP_FS_CTRL_REG1_FACENESS 0x00080000 1406bc00ae02SRob Clark #define A4XX_SP_FS_CTRL_REG1_VARYING 0x00100000 14078a264743SRob Clark #define A4XX_SP_FS_CTRL_REG1_FRAGCOORD 0x00200000 1408bc00ae02SRob Clark 1409bc00ae02SRob Clark #define REG_A4XX_SP_FS_OBJ_OFFSET_REG 0x000022ea 1410bc00ae02SRob Clark #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1411bc00ae02SRob Clark #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1412bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1413bc00ae02SRob Clark { 1414bc00ae02SRob Clark return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1415bc00ae02SRob Clark } 1416bc00ae02SRob Clark #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1417bc00ae02SRob Clark #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1418bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1419bc00ae02SRob Clark { 1420bc00ae02SRob Clark return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1421bc00ae02SRob Clark } 1422bc00ae02SRob Clark 1423bc00ae02SRob Clark #define REG_A4XX_SP_FS_OBJ_START 0x000022eb 1424bc00ae02SRob Clark 1425bc00ae02SRob Clark #define REG_A4XX_SP_FS_PVT_MEM_PARAM 0x000022ec 1426bc00ae02SRob Clark 1427bc00ae02SRob Clark #define REG_A4XX_SP_FS_PVT_MEM_ADDR 0x000022ed 1428bc00ae02SRob Clark 1429bc00ae02SRob Clark #define REG_A4XX_SP_FS_LENGTH_REG 0x000022ef 1430bc00ae02SRob Clark 1431bc00ae02SRob Clark #define REG_A4XX_SP_FS_OUTPUT_REG 0x000022f0 1432af6cb4c1SRob Clark #define A4XX_SP_FS_OUTPUT_REG_MRT__MASK 0x0000000f 1433af6cb4c1SRob Clark #define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0 1434af6cb4c1SRob Clark static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val) 1435af6cb4c1SRob Clark { 1436af6cb4c1SRob Clark return ((val) << A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_SP_FS_OUTPUT_REG_MRT__MASK; 1437af6cb4c1SRob Clark } 1438bc00ae02SRob Clark #define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080 1439bc00ae02SRob Clark #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00 1440bc00ae02SRob Clark #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8 1441bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) 1442bc00ae02SRob Clark { 1443bc00ae02SRob Clark return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK; 1444bc00ae02SRob Clark } 1445af6cb4c1SRob Clark #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK 0xff000000 1446af6cb4c1SRob Clark #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT 24 1447af6cb4c1SRob Clark static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val) 1448af6cb4c1SRob Clark { 1449af6cb4c1SRob Clark return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK; 1450af6cb4c1SRob Clark } 1451bc00ae02SRob Clark 1452bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; } 1453bc00ae02SRob Clark 1454bc00ae02SRob Clark static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; } 1455bc00ae02SRob Clark #define A4XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff 1456bc00ae02SRob Clark #define A4XX_SP_FS_MRT_REG_REGID__SHIFT 0 1457bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val) 1458bc00ae02SRob Clark { 1459bc00ae02SRob Clark return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK; 1460bc00ae02SRob Clark } 1461bc00ae02SRob Clark #define A4XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100 1462bc00ae02SRob Clark #define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK 0x0003f000 1463bc00ae02SRob Clark #define A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT 12 1464bc00ae02SRob Clark static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val) 1465bc00ae02SRob Clark { 1466bc00ae02SRob Clark return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK; 1467bc00ae02SRob Clark } 14682d3584ebSRob Clark #define A4XX_SP_FS_MRT_REG_COLOR_SRGB 0x00040000 1469bc00ae02SRob Clark 1470af6cb4c1SRob Clark #define REG_A4XX_SP_CS_CTRL_REG0 0x00002300 1471af6cb4c1SRob Clark 1472af6cb4c1SRob Clark #define REG_A4XX_SP_CS_OBJ_OFFSET_REG 0x00002301 1473af6cb4c1SRob Clark 1474af6cb4c1SRob Clark #define REG_A4XX_SP_CS_OBJ_START 0x00002302 1475af6cb4c1SRob Clark 1476af6cb4c1SRob Clark #define REG_A4XX_SP_CS_PVT_MEM_PARAM 0x00002303 1477af6cb4c1SRob Clark 1478af6cb4c1SRob Clark #define REG_A4XX_SP_CS_PVT_MEM_ADDR 0x00002304 1479af6cb4c1SRob Clark 1480af6cb4c1SRob Clark #define REG_A4XX_SP_CS_PVT_MEM_SIZE 0x00002305 1481af6cb4c1SRob Clark 1482af6cb4c1SRob Clark #define REG_A4XX_SP_CS_LENGTH_REG 0x00002306 1483af6cb4c1SRob Clark 1484bc00ae02SRob Clark #define REG_A4XX_SP_HS_OBJ_OFFSET_REG 0x0000230d 1485bc00ae02SRob Clark #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1486bc00ae02SRob Clark #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1487bc00ae02SRob Clark static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1488bc00ae02SRob Clark { 1489bc00ae02SRob Clark return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1490bc00ae02SRob Clark } 1491bc00ae02SRob Clark #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1492bc00ae02SRob Clark #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1493bc00ae02SRob Clark static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1494bc00ae02SRob Clark { 1495bc00ae02SRob Clark return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1496bc00ae02SRob Clark } 1497bc00ae02SRob Clark 1498af6cb4c1SRob Clark #define REG_A4XX_SP_HS_OBJ_START 0x0000230e 1499af6cb4c1SRob Clark 1500af6cb4c1SRob Clark #define REG_A4XX_SP_HS_PVT_MEM_PARAM 0x0000230f 1501af6cb4c1SRob Clark 1502af6cb4c1SRob Clark #define REG_A4XX_SP_HS_PVT_MEM_ADDR 0x00002310 1503af6cb4c1SRob Clark 1504af6cb4c1SRob Clark #define REG_A4XX_SP_HS_LENGTH_REG 0x00002312 1505af6cb4c1SRob Clark 15062d3584ebSRob Clark #define REG_A4XX_SP_DS_PARAM_REG 0x0000231a 15072d3584ebSRob Clark #define A4XX_SP_DS_PARAM_REG_POSREGID__MASK 0x000000ff 15082d3584ebSRob Clark #define A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT 0 15092d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val) 15102d3584ebSRob Clark { 15112d3584ebSRob Clark return ((val) << A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_DS_PARAM_REG_POSREGID__MASK; 15122d3584ebSRob Clark } 15132d3584ebSRob Clark #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000 15142d3584ebSRob Clark #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20 15152d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) 15162d3584ebSRob Clark { 15172d3584ebSRob Clark return ((val) << A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK; 15182d3584ebSRob Clark } 15192d3584ebSRob Clark 15202d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; } 15212d3584ebSRob Clark 15222d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; } 15232d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_A_REGID__MASK 0x000001ff 15242d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_A_REGID__SHIFT 0 15252d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val) 15262d3584ebSRob Clark { 15272d3584ebSRob Clark return ((val) << A4XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_A_REGID__MASK; 15282d3584ebSRob Clark } 15292d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00001e00 15302d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 9 15312d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val) 15322d3584ebSRob Clark { 15332d3584ebSRob Clark return ((val) << A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK; 15342d3584ebSRob Clark } 15352d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_B_REGID__MASK 0x01ff0000 15362d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_B_REGID__SHIFT 16 15372d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val) 15382d3584ebSRob Clark { 15392d3584ebSRob Clark return ((val) << A4XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_B_REGID__MASK; 15402d3584ebSRob Clark } 15412d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x1e000000 15422d3584ebSRob Clark #define A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 25 15432d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val) 15442d3584ebSRob Clark { 15452d3584ebSRob Clark return ((val) << A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK; 15462d3584ebSRob Clark } 15472d3584ebSRob Clark 15482d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; } 15492d3584ebSRob Clark 15502d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; } 15512d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 15522d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0 15532d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val) 15542d3584ebSRob Clark { 15552d3584ebSRob Clark return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK; 15562d3584ebSRob Clark } 15572d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 15582d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8 15592d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val) 15602d3584ebSRob Clark { 15612d3584ebSRob Clark return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK; 15622d3584ebSRob Clark } 15632d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 15642d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16 15652d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val) 15662d3584ebSRob Clark { 15672d3584ebSRob Clark return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK; 15682d3584ebSRob Clark } 15692d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 15702d3584ebSRob Clark #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24 15712d3584ebSRob Clark static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) 15722d3584ebSRob Clark { 15732d3584ebSRob Clark return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK; 15742d3584ebSRob Clark } 15752d3584ebSRob Clark 1576bc00ae02SRob Clark #define REG_A4XX_SP_DS_OBJ_OFFSET_REG 0x00002334 1577bc00ae02SRob Clark #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1578bc00ae02SRob Clark #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1579bc00ae02SRob Clark static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1580bc00ae02SRob Clark { 1581bc00ae02SRob Clark return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1582bc00ae02SRob Clark } 1583bc00ae02SRob Clark #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1584bc00ae02SRob Clark #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1585bc00ae02SRob Clark static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1586bc00ae02SRob Clark { 1587bc00ae02SRob Clark return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1588bc00ae02SRob Clark } 1589bc00ae02SRob Clark 1590af6cb4c1SRob Clark #define REG_A4XX_SP_DS_OBJ_START 0x00002335 1591af6cb4c1SRob Clark 1592af6cb4c1SRob Clark #define REG_A4XX_SP_DS_PVT_MEM_PARAM 0x00002336 1593af6cb4c1SRob Clark 1594af6cb4c1SRob Clark #define REG_A4XX_SP_DS_PVT_MEM_ADDR 0x00002337 1595af6cb4c1SRob Clark 1596af6cb4c1SRob Clark #define REG_A4XX_SP_DS_LENGTH_REG 0x00002339 1597af6cb4c1SRob Clark 15982d3584ebSRob Clark #define REG_A4XX_SP_GS_PARAM_REG 0x00002341 15992d3584ebSRob Clark #define A4XX_SP_GS_PARAM_REG_POSREGID__MASK 0x000000ff 16002d3584ebSRob Clark #define A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT 0 16012d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val) 16022d3584ebSRob Clark { 16032d3584ebSRob Clark return ((val) << A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_POSREGID__MASK; 16042d3584ebSRob Clark } 16052d3584ebSRob Clark #define A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK 0x0000ff00 16062d3584ebSRob Clark #define A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT 8 16072d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val) 16082d3584ebSRob Clark { 16092d3584ebSRob Clark return ((val) << A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK; 16102d3584ebSRob Clark } 16112d3584ebSRob Clark #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000 16122d3584ebSRob Clark #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20 16132d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) 16142d3584ebSRob Clark { 16152d3584ebSRob Clark return ((val) << A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK; 16162d3584ebSRob Clark } 16172d3584ebSRob Clark 16182d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; } 16192d3584ebSRob Clark 16202d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; } 16212d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_A_REGID__MASK 0x000001ff 16222d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_A_REGID__SHIFT 0 16232d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val) 16242d3584ebSRob Clark { 16252d3584ebSRob Clark return ((val) << A4XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_A_REGID__MASK; 16262d3584ebSRob Clark } 16272d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00001e00 16282d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 9 16292d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val) 16302d3584ebSRob Clark { 16312d3584ebSRob Clark return ((val) << A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK; 16322d3584ebSRob Clark } 16332d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_B_REGID__MASK 0x01ff0000 16342d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_B_REGID__SHIFT 16 16352d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val) 16362d3584ebSRob Clark { 16372d3584ebSRob Clark return ((val) << A4XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_B_REGID__MASK; 16382d3584ebSRob Clark } 16392d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x1e000000 16402d3584ebSRob Clark #define A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 25 16412d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val) 16422d3584ebSRob Clark { 16432d3584ebSRob Clark return ((val) << A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK; 16442d3584ebSRob Clark } 16452d3584ebSRob Clark 16462d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; } 16472d3584ebSRob Clark 16482d3584ebSRob Clark static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; } 16492d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 16502d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0 16512d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val) 16522d3584ebSRob Clark { 16532d3584ebSRob Clark return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK; 16542d3584ebSRob Clark } 16552d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 16562d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8 16572d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val) 16582d3584ebSRob Clark { 16592d3584ebSRob Clark return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK; 16602d3584ebSRob Clark } 16612d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 16622d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16 16632d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val) 16642d3584ebSRob Clark { 16652d3584ebSRob Clark return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK; 16662d3584ebSRob Clark } 16672d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 16682d3584ebSRob Clark #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24 16692d3584ebSRob Clark static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) 16702d3584ebSRob Clark { 16712d3584ebSRob Clark return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK; 16722d3584ebSRob Clark } 16732d3584ebSRob Clark 1674bc00ae02SRob Clark #define REG_A4XX_SP_GS_OBJ_OFFSET_REG 0x0000235b 1675bc00ae02SRob Clark #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1676bc00ae02SRob Clark #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1677bc00ae02SRob Clark static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1678bc00ae02SRob Clark { 1679bc00ae02SRob Clark return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1680bc00ae02SRob Clark } 1681bc00ae02SRob Clark #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1682bc00ae02SRob Clark #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1683bc00ae02SRob Clark static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1684bc00ae02SRob Clark { 1685bc00ae02SRob Clark return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1686bc00ae02SRob Clark } 1687bc00ae02SRob Clark 1688af6cb4c1SRob Clark #define REG_A4XX_SP_GS_OBJ_START 0x0000235c 1689af6cb4c1SRob Clark 1690af6cb4c1SRob Clark #define REG_A4XX_SP_GS_PVT_MEM_PARAM 0x0000235d 1691af6cb4c1SRob Clark 1692af6cb4c1SRob Clark #define REG_A4XX_SP_GS_PVT_MEM_ADDR 0x0000235e 1693af6cb4c1SRob Clark 1694bc00ae02SRob Clark #define REG_A4XX_SP_GS_LENGTH_REG 0x00002360 1695bc00ae02SRob Clark 1696bc00ae02SRob Clark #define REG_A4XX_VPC_DEBUG_RAM_SEL 0x00000e60 1697bc00ae02SRob Clark 1698bc00ae02SRob Clark #define REG_A4XX_VPC_DEBUG_RAM_READ 0x00000e61 1699bc00ae02SRob Clark 1700bc00ae02SRob Clark #define REG_A4XX_VPC_DEBUG_ECO_CONTROL 0x00000e64 1701bc00ae02SRob Clark 1702bc00ae02SRob Clark #define REG_A4XX_VPC_PERFCTR_VPC_SEL_3 0x00000e68 1703bc00ae02SRob Clark 1704bc00ae02SRob Clark #define REG_A4XX_VPC_ATTR 0x00002140 1705bc00ae02SRob Clark #define A4XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff 1706bc00ae02SRob Clark #define A4XX_VPC_ATTR_TOTALATTR__SHIFT 0 1707bc00ae02SRob Clark static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val) 1708bc00ae02SRob Clark { 1709bc00ae02SRob Clark return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK; 1710bc00ae02SRob Clark } 1711bc00ae02SRob Clark #define A4XX_VPC_ATTR_PSIZE 0x00000200 1712bc00ae02SRob Clark #define A4XX_VPC_ATTR_THRDASSIGN__MASK 0x00003000 1713bc00ae02SRob Clark #define A4XX_VPC_ATTR_THRDASSIGN__SHIFT 12 1714bc00ae02SRob Clark static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val) 1715bc00ae02SRob Clark { 1716bc00ae02SRob Clark return ((val) << A4XX_VPC_ATTR_THRDASSIGN__SHIFT) & A4XX_VPC_ATTR_THRDASSIGN__MASK; 1717bc00ae02SRob Clark } 1718bc00ae02SRob Clark #define A4XX_VPC_ATTR_ENABLE 0x02000000 1719bc00ae02SRob Clark 1720bc00ae02SRob Clark #define REG_A4XX_VPC_PACK 0x00002141 1721bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMBYPASSVAR__MASK 0x000000ff 1722bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT 0 1723bc00ae02SRob Clark static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val) 1724bc00ae02SRob Clark { 1725bc00ae02SRob Clark return ((val) << A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT) & A4XX_VPC_PACK_NUMBYPASSVAR__MASK; 1726bc00ae02SRob Clark } 1727bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00 1728bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8 1729bc00ae02SRob Clark static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) 1730bc00ae02SRob Clark { 1731bc00ae02SRob Clark return ((val) << A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK; 1732bc00ae02SRob Clark } 1733bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000 1734bc00ae02SRob Clark #define A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16 1735bc00ae02SRob Clark static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) 1736bc00ae02SRob Clark { 1737bc00ae02SRob Clark return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK; 1738bc00ae02SRob Clark } 1739bc00ae02SRob Clark 1740bc00ae02SRob Clark static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; } 1741bc00ae02SRob Clark 1742bc00ae02SRob Clark static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; } 1743bc00ae02SRob Clark 1744bc00ae02SRob Clark static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; } 1745bc00ae02SRob Clark 1746bc00ae02SRob Clark static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; } 1747bc00ae02SRob Clark 1748bc00ae02SRob Clark #define REG_A4XX_VPC_SO_FLUSH_WADDR_3 0x0000216e 1749bc00ae02SRob Clark 1750bc00ae02SRob Clark #define REG_A4XX_VSC_BIN_SIZE 0x00000c00 1751bc00ae02SRob Clark #define A4XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 1752bc00ae02SRob Clark #define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 1753bc00ae02SRob Clark static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 1754bc00ae02SRob Clark { 1755bc00ae02SRob Clark return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK; 1756bc00ae02SRob Clark } 1757bc00ae02SRob Clark #define A4XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 1758bc00ae02SRob Clark #define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5 1759bc00ae02SRob Clark static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 1760bc00ae02SRob Clark { 1761bc00ae02SRob Clark return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK; 1762bc00ae02SRob Clark } 1763bc00ae02SRob Clark 1764bc00ae02SRob Clark #define REG_A4XX_VSC_SIZE_ADDRESS 0x00000c01 1765bc00ae02SRob Clark 1766bc00ae02SRob Clark #define REG_A4XX_VSC_SIZE_ADDRESS2 0x00000c02 1767bc00ae02SRob Clark 1768bc00ae02SRob Clark #define REG_A4XX_VSC_DEBUG_ECO_CONTROL 0x00000c03 1769bc00ae02SRob Clark 1770bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } 1771bc00ae02SRob Clark 1772bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } 1773bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff 1774bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0 1775bc00ae02SRob Clark static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) 1776bc00ae02SRob Clark { 1777bc00ae02SRob Clark return ((val) << A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_X__MASK; 1778bc00ae02SRob Clark } 1779bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00 1780bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10 1781bc00ae02SRob Clark static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) 1782bc00ae02SRob Clark { 1783bc00ae02SRob Clark return ((val) << A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_Y__MASK; 1784bc00ae02SRob Clark } 1785bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000 1786bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20 1787bc00ae02SRob Clark static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) 1788bc00ae02SRob Clark { 1789bc00ae02SRob Clark return ((val) << A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_W__MASK; 1790bc00ae02SRob Clark } 1791bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000 1792bc00ae02SRob Clark #define A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24 1793bc00ae02SRob Clark static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) 1794bc00ae02SRob Clark { 1795bc00ae02SRob Clark return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK; 1796bc00ae02SRob Clark } 1797bc00ae02SRob Clark 1798bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 1799bc00ae02SRob Clark 1800bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 1801bc00ae02SRob Clark 1802bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; } 1803bc00ae02SRob Clark 1804bc00ae02SRob Clark static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; } 1805bc00ae02SRob Clark 1806bc00ae02SRob Clark #define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1 0x00000c41 1807bc00ae02SRob Clark 1808bc00ae02SRob Clark #define REG_A4XX_VSC_PERFCTR_VSC_SEL_0 0x00000c50 1809bc00ae02SRob Clark 1810bc00ae02SRob Clark #define REG_A4XX_VSC_PERFCTR_VSC_SEL_1 0x00000c51 1811bc00ae02SRob Clark 1812bc00ae02SRob Clark #define REG_A4XX_VFD_DEBUG_CONTROL 0x00000e40 1813bc00ae02SRob Clark 1814bc00ae02SRob Clark #define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 0x00000e4a 1815bc00ae02SRob Clark 1816af6cb4c1SRob Clark #define REG_A4XX_VGT_CL_INITIATOR 0x000021d0 1817af6cb4c1SRob Clark 1818af6cb4c1SRob Clark #define REG_A4XX_VGT_EVENT_INITIATOR 0x000021d9 1819af6cb4c1SRob Clark 1820bc00ae02SRob Clark #define REG_A4XX_VFD_CONTROL_0 0x00002200 1821bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x000000ff 1822bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0 1823bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) 1824bc00ae02SRob Clark { 1825bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK; 1826bc00ae02SRob Clark } 1827bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK 0x0001fe00 1828bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT 9 1829bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val) 1830bc00ae02SRob Clark { 1831bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT) & A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK; 1832bc00ae02SRob Clark } 1833bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x03f00000 1834bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 20 1835bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) 1836bc00ae02SRob Clark { 1837bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK; 1838bc00ae02SRob Clark } 1839bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xfc000000 1840bc00ae02SRob Clark #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 26 1841bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) 1842bc00ae02SRob Clark { 1843bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK; 1844bc00ae02SRob Clark } 1845bc00ae02SRob Clark 1846bc00ae02SRob Clark #define REG_A4XX_VFD_CONTROL_1 0x00002201 1847bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff 1848bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0 1849bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) 1850bc00ae02SRob Clark { 1851bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK; 1852bc00ae02SRob Clark } 1853bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000 1854bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16 1855bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 1856bc00ae02SRob Clark { 1857bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A4XX_VFD_CONTROL_1_REGID4VTX__MASK; 1858bc00ae02SRob Clark } 1859bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000 1860bc00ae02SRob Clark #define A4XX_VFD_CONTROL_1_REGID4INST__SHIFT 24 1861bc00ae02SRob Clark static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 1862bc00ae02SRob Clark { 1863bc00ae02SRob Clark return ((val) << A4XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A4XX_VFD_CONTROL_1_REGID4INST__MASK; 1864bc00ae02SRob Clark } 1865bc00ae02SRob Clark 1866bc00ae02SRob Clark #define REG_A4XX_VFD_CONTROL_2 0x00002202 1867bc00ae02SRob Clark 1868bc00ae02SRob Clark #define REG_A4XX_VFD_CONTROL_3 0x00002203 18698a264743SRob Clark #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK 0x0000ff00 18708a264743SRob Clark #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT 8 18718a264743SRob Clark static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val) 18728a264743SRob Clark { 18738a264743SRob Clark return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK; 18748a264743SRob Clark } 18752d3584ebSRob Clark #define A4XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000 18762d3584ebSRob Clark #define A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16 18772d3584ebSRob Clark static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) 18782d3584ebSRob Clark { 18792d3584ebSRob Clark return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSX__MASK; 18802d3584ebSRob Clark } 18812d3584ebSRob Clark #define A4XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000 18822d3584ebSRob Clark #define A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24 18832d3584ebSRob Clark static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) 18842d3584ebSRob Clark { 18852d3584ebSRob Clark return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSY__MASK; 18862d3584ebSRob Clark } 1887bc00ae02SRob Clark 1888bc00ae02SRob Clark #define REG_A4XX_VFD_CONTROL_4 0x00002204 1889bc00ae02SRob Clark 1890bc00ae02SRob Clark #define REG_A4XX_VFD_INDEX_OFFSET 0x00002208 1891bc00ae02SRob Clark 1892bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; } 1893bc00ae02SRob Clark 1894bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; } 1895bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f 1896bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0 1897bc00ae02SRob Clark static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) 1898bc00ae02SRob Clark { 1899bc00ae02SRob Clark return ((val) << A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK; 1900bc00ae02SRob Clark } 1901bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80 1902bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7 1903bc00ae02SRob Clark static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) 1904bc00ae02SRob Clark { 1905bc00ae02SRob Clark return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK; 1906bc00ae02SRob Clark } 1907bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00080000 19088a264743SRob Clark #define A4XX_VFD_FETCH_INSTR_0_INSTANCED 0x00100000 1909bc00ae02SRob Clark 1910bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; } 1911bc00ae02SRob Clark 1912bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; } 1913bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xfffffff0 1914bc00ae02SRob Clark #define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 4 1915bc00ae02SRob Clark static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val) 1916bc00ae02SRob Clark { 1917bc00ae02SRob Clark return ((val >> 4) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK; 1918bc00ae02SRob Clark } 1919bc00ae02SRob Clark 1920bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; } 19218a264743SRob Clark #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK 0x000001ff 19228a264743SRob Clark #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT 0 19238a264743SRob Clark static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val) 19248a264743SRob Clark { 19258a264743SRob Clark return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK; 19268a264743SRob Clark } 1927bc00ae02SRob Clark 1928bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; } 1929bc00ae02SRob Clark 1930bc00ae02SRob Clark static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; } 1931bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f 1932bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0 1933bc00ae02SRob Clark static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) 1934bc00ae02SRob Clark { 1935bc00ae02SRob Clark return ((val) << A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK; 1936bc00ae02SRob Clark } 1937bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010 1938bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0 1939bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6 1940bc00ae02SRob Clark static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val) 1941bc00ae02SRob Clark { 1942bc00ae02SRob Clark return ((val) << A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A4XX_VFD_DECODE_INSTR_FORMAT__MASK; 1943bc00ae02SRob Clark } 1944bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000 1945bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_REGID__SHIFT 12 1946bc00ae02SRob Clark static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val) 1947bc00ae02SRob Clark { 1948bc00ae02SRob Clark return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK; 1949bc00ae02SRob Clark } 19508a264743SRob Clark #define A4XX_VFD_DECODE_INSTR_INT 0x00100000 1951bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000 1952bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT 22 1953bc00ae02SRob Clark static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 1954bc00ae02SRob Clark { 1955bc00ae02SRob Clark return ((val) << A4XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A4XX_VFD_DECODE_INSTR_SWAP__MASK; 1956bc00ae02SRob Clark } 1957bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000 1958bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24 1959bc00ae02SRob Clark static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) 1960bc00ae02SRob Clark { 1961bc00ae02SRob Clark return ((val) << A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK; 1962bc00ae02SRob Clark } 1963bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000 1964bc00ae02SRob Clark #define A4XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000 1965bc00ae02SRob Clark 1966bc00ae02SRob Clark #define REG_A4XX_TPL1_DEBUG_ECO_CONTROL 0x00000f00 1967bc00ae02SRob Clark 1968af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_MODE_CONTROL 0x00000f03 1969af6cb4c1SRob Clark 1970bc00ae02SRob Clark #define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 0x00000f0b 1971bc00ae02SRob Clark 1972bc00ae02SRob Clark #define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380 1973bc00ae02SRob Clark 1974af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_TEX_COUNT 0x00002381 1975af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_VS__MASK 0x000000ff 1976af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT 0 1977af6cb4c1SRob Clark static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val) 1978af6cb4c1SRob Clark { 1979af6cb4c1SRob Clark return ((val) << A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_VS__MASK; 1980af6cb4c1SRob Clark } 1981af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_HS__MASK 0x0000ff00 1982af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT 8 1983af6cb4c1SRob Clark static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val) 1984af6cb4c1SRob Clark { 1985af6cb4c1SRob Clark return ((val) << A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_HS__MASK; 1986af6cb4c1SRob Clark } 1987af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_DS__MASK 0x00ff0000 1988af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT 16 1989af6cb4c1SRob Clark static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val) 1990af6cb4c1SRob Clark { 1991af6cb4c1SRob Clark return ((val) << A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_DS__MASK; 1992af6cb4c1SRob Clark } 1993af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_GS__MASK 0xff000000 1994af6cb4c1SRob Clark #define A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT 24 1995af6cb4c1SRob Clark static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val) 1996af6cb4c1SRob Clark { 1997af6cb4c1SRob Clark return ((val) << A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_GS__MASK; 1998af6cb4c1SRob Clark } 1999af6cb4c1SRob Clark 2000af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002384 2001af6cb4c1SRob Clark 2002af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR 0x00002387 2003af6cb4c1SRob Clark 2004af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR 0x0000238a 2005af6cb4c1SRob Clark 2006af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR 0x0000238d 2007af6cb4c1SRob Clark 2008af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_FS_TEX_COUNT 0x000023a0 2009af6cb4c1SRob Clark 2010af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x000023a1 2011af6cb4c1SRob Clark 2012af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_CS_BORDER_COLOR_BASE_ADDR 0x000023a4 2013af6cb4c1SRob Clark 2014af6cb4c1SRob Clark #define REG_A4XX_TPL1_TP_CS_SAMPLER_BASE_ADDR 0x000023a5 2015af6cb4c1SRob Clark 2016bc00ae02SRob Clark #define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR 0x000023a6 2017bc00ae02SRob Clark 2018bc00ae02SRob Clark #define REG_A4XX_GRAS_TSE_STATUS 0x00000c80 2019bc00ae02SRob Clark 2020bc00ae02SRob Clark #define REG_A4XX_GRAS_DEBUG_ECO_CONTROL 0x00000c81 2021bc00ae02SRob Clark 2022bc00ae02SRob Clark #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c88 2023bc00ae02SRob Clark 2024bc00ae02SRob Clark #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c8b 2025bc00ae02SRob Clark 2026bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000 2027bc00ae02SRob Clark 2028bc00ae02SRob Clark #define REG_A4XX_GRAS_CLEAR_CNTL 0x00002003 2029bc00ae02SRob Clark #define A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR 0x00000001 2030bc00ae02SRob Clark 2031bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_GB_CLIP_ADJ 0x00002004 2032bc00ae02SRob Clark #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff 2033bc00ae02SRob Clark #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0 2034bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) 2035bc00ae02SRob Clark { 2036bc00ae02SRob Clark return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; 2037bc00ae02SRob Clark } 2038bc00ae02SRob Clark #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00 2039bc00ae02SRob Clark #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10 2040bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) 2041bc00ae02SRob Clark { 2042bc00ae02SRob Clark return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; 2043bc00ae02SRob Clark } 2044bc00ae02SRob Clark 2045bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_XOFFSET_0 0x00002008 2046bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff 2047bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0 2048bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val) 2049bc00ae02SRob Clark { 2050bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK; 2051bc00ae02SRob Clark } 2052bc00ae02SRob Clark 2053bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_XSCALE_0 0x00002009 2054bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff 2055bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0 2056bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val) 2057bc00ae02SRob Clark { 2058bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_XSCALE_0__MASK; 2059bc00ae02SRob Clark } 2060bc00ae02SRob Clark 2061bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_YOFFSET_0 0x0000200a 2062bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff 2063bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0 2064bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val) 2065bc00ae02SRob Clark { 2066bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK; 2067bc00ae02SRob Clark } 2068bc00ae02SRob Clark 2069bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_YSCALE_0 0x0000200b 2070bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff 2071bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0 2072bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val) 2073bc00ae02SRob Clark { 2074bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_YSCALE_0__MASK; 2075bc00ae02SRob Clark } 2076bc00ae02SRob Clark 2077bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000200c 2078bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff 2079bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0 2080bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val) 2081bc00ae02SRob Clark { 2082bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK; 2083bc00ae02SRob Clark } 2084bc00ae02SRob Clark 2085bc00ae02SRob Clark #define REG_A4XX_GRAS_CL_VPORT_ZSCALE_0 0x0000200d 2086bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff 2087bc00ae02SRob Clark #define A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0 2088bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val) 2089bc00ae02SRob Clark { 2090bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK; 2091bc00ae02SRob Clark } 2092bc00ae02SRob Clark 2093bc00ae02SRob Clark #define REG_A4XX_GRAS_SU_POINT_MINMAX 0x00002070 2094bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 2095bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 2096bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val) 2097bc00ae02SRob Clark { 2098bc00ae02SRob Clark return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 2099bc00ae02SRob Clark } 2100bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 2101bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 2102bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val) 2103bc00ae02SRob Clark { 2104bc00ae02SRob Clark return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 2105bc00ae02SRob Clark } 2106bc00ae02SRob Clark 2107bc00ae02SRob Clark #define REG_A4XX_GRAS_SU_POINT_SIZE 0x00002071 2108bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff 2109bc00ae02SRob Clark #define A4XX_GRAS_SU_POINT_SIZE__SHIFT 0 2110bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val) 2111bc00ae02SRob Clark { 2112bc00ae02SRob Clark return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK; 2113bc00ae02SRob Clark } 2114bc00ae02SRob Clark 2115bc00ae02SRob Clark #define REG_A4XX_GRAS_ALPHA_CONTROL 0x00002073 2116bc00ae02SRob Clark #define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE 0x00000004 2117bc00ae02SRob Clark 2118bc00ae02SRob Clark #define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE 0x00002074 2119bc00ae02SRob Clark #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff 2120bc00ae02SRob Clark #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 2121bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val) 2122bc00ae02SRob Clark { 2123bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; 2124bc00ae02SRob Clark } 2125bc00ae02SRob Clark 2126bc00ae02SRob Clark #define REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00002075 2127bc00ae02SRob Clark #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 2128bc00ae02SRob Clark #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 2129bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 2130bc00ae02SRob Clark { 2131bc00ae02SRob Clark return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 2132bc00ae02SRob Clark } 2133bc00ae02SRob Clark 2134af6cb4c1SRob Clark #define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP 0x00002076 2135af6cb4c1SRob Clark #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK 0xffffffff 2136af6cb4c1SRob Clark #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT 0 2137af6cb4c1SRob Clark static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val) 2138af6cb4c1SRob Clark { 2139af6cb4c1SRob Clark return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK; 2140af6cb4c1SRob Clark } 2141af6cb4c1SRob Clark 21428a264743SRob Clark #define REG_A4XX_GRAS_DEPTH_CONTROL 0x00002077 21438a264743SRob Clark #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK 0x00000003 21448a264743SRob Clark #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT 0 21458a264743SRob Clark static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val) 21468a264743SRob Clark { 21478a264743SRob Clark return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK; 21488a264743SRob Clark } 21498a264743SRob Clark 21508a264743SRob Clark #define REG_A4XX_GRAS_SU_MODE_CONTROL 0x00002078 21518a264743SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001 21528a264743SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002 21538a264743SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004 21548a264743SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8 21558a264743SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3 21568a264743SRob Clark static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) 21578a264743SRob Clark { 21588a264743SRob Clark return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; 21598a264743SRob Clark } 21608a264743SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800 21618a264743SRob Clark #define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS 0x00100000 21628a264743SRob Clark 21638a264743SRob Clark #define REG_A4XX_GRAS_SC_CONTROL 0x0000207b 21648a264743SRob Clark #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x0000000c 21658a264743SRob Clark #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 2 21668a264743SRob Clark static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) 21678a264743SRob Clark { 21688a264743SRob Clark return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK; 21698a264743SRob Clark } 21708a264743SRob Clark #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000380 21718a264743SRob Clark #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 7 21728a264743SRob Clark static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val) 21738a264743SRob Clark { 21748a264743SRob Clark return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK; 21758a264743SRob Clark } 21768a264743SRob Clark #define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE 0x00000800 21778a264743SRob Clark #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000 21788a264743SRob Clark #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12 21798a264743SRob Clark static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) 21808a264743SRob Clark { 21818a264743SRob Clark return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK; 21828a264743SRob Clark } 2183bc00ae02SRob Clark 2184bc00ae02SRob Clark #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL 0x0000207c 2185bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 2186bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 2187bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 2188bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 2189bc00ae02SRob Clark { 2190bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; 2191bc00ae02SRob Clark } 2192bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 2193bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 2194bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 2195bc00ae02SRob Clark { 2196bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; 2197bc00ae02SRob Clark } 2198bc00ae02SRob Clark 2199bc00ae02SRob Clark #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR 0x0000207d 2200bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 2201bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 2202bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 2203bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 2204bc00ae02SRob Clark { 2205bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; 2206bc00ae02SRob Clark } 2207bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 2208bc00ae02SRob Clark #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 2209bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 2210bc00ae02SRob Clark { 2211bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; 2212bc00ae02SRob Clark } 2213bc00ae02SRob Clark 2214bc00ae02SRob Clark #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000209c 2215bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 2216bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 2217bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 2218bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 2219bc00ae02SRob Clark { 2220bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 2221bc00ae02SRob Clark } 2222bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 2223bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 2224bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 2225bc00ae02SRob Clark { 2226bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 2227bc00ae02SRob Clark } 2228bc00ae02SRob Clark 2229bc00ae02SRob Clark #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000209d 2230bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 2231bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 2232bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 2233bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 2234bc00ae02SRob Clark { 2235bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 2236bc00ae02SRob Clark } 2237bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 2238bc00ae02SRob Clark #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 2239bc00ae02SRob Clark static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 2240bc00ae02SRob Clark { 2241bc00ae02SRob Clark return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 2242bc00ae02SRob Clark } 2243bc00ae02SRob Clark 22448a264743SRob Clark #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR 0x0000209e 22458a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE 0x80000000 22468a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK 0x00007fff 22478a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT 0 22488a264743SRob Clark static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val) 2249bc00ae02SRob Clark { 22508a264743SRob Clark return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK; 22518a264743SRob Clark } 22528a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK 0x7fff0000 22538a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT 16 22548a264743SRob Clark static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val) 22558a264743SRob Clark { 22568a264743SRob Clark return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK; 2257bc00ae02SRob Clark } 2258bc00ae02SRob Clark 22598a264743SRob Clark #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL 0x0000209f 22608a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE 0x80000000 22618a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK 0x00007fff 22628a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT 0 22638a264743SRob Clark static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val) 2264bc00ae02SRob Clark { 22658a264743SRob Clark return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK; 2266bc00ae02SRob Clark } 22678a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK 0x7fff0000 22688a264743SRob Clark #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT 16 22698a264743SRob Clark static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val) 2270bc00ae02SRob Clark { 22718a264743SRob Clark return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK; 2272bc00ae02SRob Clark } 2273bc00ae02SRob Clark 2274bc00ae02SRob Clark #define REG_A4XX_UCHE_CACHE_MODE_CONTROL 0x00000e80 2275bc00ae02SRob Clark 2276bc00ae02SRob Clark #define REG_A4XX_UCHE_TRAP_BASE_LO 0x00000e83 2277bc00ae02SRob Clark 2278bc00ae02SRob Clark #define REG_A4XX_UCHE_TRAP_BASE_HI 0x00000e84 2279bc00ae02SRob Clark 2280bc00ae02SRob Clark #define REG_A4XX_UCHE_CACHE_STATUS 0x00000e88 2281bc00ae02SRob Clark 2282bc00ae02SRob Clark #define REG_A4XX_UCHE_INVALIDATE0 0x00000e8a 2283bc00ae02SRob Clark 2284bc00ae02SRob Clark #define REG_A4XX_UCHE_INVALIDATE1 0x00000e8b 2285bc00ae02SRob Clark 2286bc00ae02SRob Clark #define REG_A4XX_UCHE_CACHE_WAYS_VFD 0x00000e8c 2287bc00ae02SRob Clark 2288bc00ae02SRob Clark #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e95 2289bc00ae02SRob Clark 2290bc00ae02SRob Clark #define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD 0x00000e00 2291bc00ae02SRob Clark 2292bc00ae02SRob Clark #define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL 0x00000e04 2293bc00ae02SRob Clark 2294af6cb4c1SRob Clark #define REG_A4XX_HLSQ_MODE_CONTROL 0x00000e05 2295af6cb4c1SRob Clark 2296bc00ae02SRob Clark #define REG_A4XX_HLSQ_PERF_PIPE_MASK 0x00000e0e 2297bc00ae02SRob Clark 2298bc00ae02SRob Clark #define REG_A4XX_HLSQ_CONTROL_0_REG 0x000023c0 2299bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010 2300bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4 2301bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) 2302bc00ae02SRob Clark { 2303bc00ae02SRob Clark return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; 2304bc00ae02SRob Clark } 2305bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040 2306bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200 2307bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400 2308bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000 2309bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000 2310bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27 2311bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) 2312bc00ae02SRob Clark { 2313bc00ae02SRob Clark return ((val) << A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK; 2314bc00ae02SRob Clark } 2315bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000 2316bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000 2317bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000 2318bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000 2319bc00ae02SRob Clark 2320bc00ae02SRob Clark #define REG_A4XX_HLSQ_CONTROL_1_REG 0x000023c1 2321bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040 2322bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6 2323bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) 2324bc00ae02SRob Clark { 2325bc00ae02SRob Clark return ((val) << A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK; 2326bc00ae02SRob Clark } 2327bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100 2328bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200 23298a264743SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK 0x00ff0000 23308a264743SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT 16 23318a264743SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val) 23328a264743SRob Clark { 23338a264743SRob Clark return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK; 23348a264743SRob Clark } 2335af6cb4c1SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK 0xff000000 2336af6cb4c1SRob Clark #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT 24 2337af6cb4c1SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val) 2338af6cb4c1SRob Clark { 2339af6cb4c1SRob Clark return ((val) << A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK; 2340af6cb4c1SRob Clark } 2341bc00ae02SRob Clark 2342bc00ae02SRob Clark #define REG_A4XX_HLSQ_CONTROL_2_REG 0x000023c2 2343bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000 2344bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26 2345bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) 2346bc00ae02SRob Clark { 2347bc00ae02SRob Clark return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK; 2348bc00ae02SRob Clark } 23498a264743SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000003fc 23508a264743SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 2 23518a264743SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) 23528a264743SRob Clark { 23538a264743SRob Clark return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; 23548a264743SRob Clark } 2355af6cb4c1SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK 0x0003fc00 2356af6cb4c1SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT 10 2357af6cb4c1SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val) 2358af6cb4c1SRob Clark { 2359af6cb4c1SRob Clark return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK; 2360af6cb4c1SRob Clark } 2361af6cb4c1SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK 0x03fc0000 2362af6cb4c1SRob Clark #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT 18 2363af6cb4c1SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val) 2364af6cb4c1SRob Clark { 2365af6cb4c1SRob Clark return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK; 2366af6cb4c1SRob Clark } 2367bc00ae02SRob Clark 2368bc00ae02SRob Clark #define REG_A4XX_HLSQ_CONTROL_3_REG 0x000023c3 2369bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff 2370bc00ae02SRob Clark #define A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0 2371bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val) 2372bc00ae02SRob Clark { 2373bc00ae02SRob Clark return ((val) << A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_REGID__MASK; 2374bc00ae02SRob Clark } 2375bc00ae02SRob Clark 2376af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CONTROL_4_REG 0x000023c4 2377af6cb4c1SRob Clark 2378bc00ae02SRob Clark #define REG_A4XX_HLSQ_VS_CONTROL_REG 0x000023c5 2379bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 2380bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0 2381bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) 2382bc00ae02SRob Clark { 2383bc00ae02SRob Clark return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK; 2384bc00ae02SRob Clark } 2385bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 2386bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 2387bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 2388bc00ae02SRob Clark { 2389bc00ae02SRob Clark return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 2390bc00ae02SRob Clark } 2391af6cb4c1SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00010000 2392bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 2393bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 2394bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 2395bc00ae02SRob Clark { 2396bc00ae02SRob Clark return ((val) << A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK; 2397bc00ae02SRob Clark } 2398bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 2399bc00ae02SRob Clark #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24 2400bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) 2401bc00ae02SRob Clark { 2402bc00ae02SRob Clark return ((val) << A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK; 2403bc00ae02SRob Clark } 2404bc00ae02SRob Clark 2405bc00ae02SRob Clark #define REG_A4XX_HLSQ_FS_CONTROL_REG 0x000023c6 2406bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 2407bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0 2408bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) 2409bc00ae02SRob Clark { 2410bc00ae02SRob Clark return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK; 2411bc00ae02SRob Clark } 2412bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 2413bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 2414bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 2415bc00ae02SRob Clark { 2416bc00ae02SRob Clark return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 2417bc00ae02SRob Clark } 2418af6cb4c1SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00010000 2419bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 2420bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 2421bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 2422bc00ae02SRob Clark { 2423bc00ae02SRob Clark return ((val) << A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK; 2424bc00ae02SRob Clark } 2425bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 2426bc00ae02SRob Clark #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24 2427bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) 2428bc00ae02SRob Clark { 2429bc00ae02SRob Clark return ((val) << A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK; 2430bc00ae02SRob Clark } 2431bc00ae02SRob Clark 2432bc00ae02SRob Clark #define REG_A4XX_HLSQ_HS_CONTROL_REG 0x000023c7 2433bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 2434bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT 0 2435bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val) 2436bc00ae02SRob Clark { 2437bc00ae02SRob Clark return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK; 2438bc00ae02SRob Clark } 2439bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 2440bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 2441bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 2442bc00ae02SRob Clark { 2443bc00ae02SRob Clark return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 2444bc00ae02SRob Clark } 2445af6cb4c1SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00010000 2446bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 2447bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 2448bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 2449bc00ae02SRob Clark { 2450bc00ae02SRob Clark return ((val) << A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK; 2451bc00ae02SRob Clark } 2452bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 2453bc00ae02SRob Clark #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT 24 2454bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val) 2455bc00ae02SRob Clark { 2456bc00ae02SRob Clark return ((val) << A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK; 2457bc00ae02SRob Clark } 2458bc00ae02SRob Clark 2459bc00ae02SRob Clark #define REG_A4XX_HLSQ_DS_CONTROL_REG 0x000023c8 2460bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 2461bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT 0 2462bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val) 2463bc00ae02SRob Clark { 2464bc00ae02SRob Clark return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK; 2465bc00ae02SRob Clark } 2466bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 2467bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 2468bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 2469bc00ae02SRob Clark { 2470bc00ae02SRob Clark return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 2471bc00ae02SRob Clark } 2472af6cb4c1SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00010000 2473bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 2474bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 2475bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 2476bc00ae02SRob Clark { 2477bc00ae02SRob Clark return ((val) << A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK; 2478bc00ae02SRob Clark } 2479bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 2480bc00ae02SRob Clark #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT 24 2481bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val) 2482bc00ae02SRob Clark { 2483bc00ae02SRob Clark return ((val) << A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK; 2484bc00ae02SRob Clark } 2485bc00ae02SRob Clark 2486bc00ae02SRob Clark #define REG_A4XX_HLSQ_GS_CONTROL_REG 0x000023c9 2487bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 2488bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT 0 2489bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val) 2490bc00ae02SRob Clark { 2491bc00ae02SRob Clark return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK; 2492bc00ae02SRob Clark } 2493bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 2494bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 2495bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 2496bc00ae02SRob Clark { 2497bc00ae02SRob Clark return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 2498bc00ae02SRob Clark } 2499af6cb4c1SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00010000 2500bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 2501bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 2502bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 2503bc00ae02SRob Clark { 2504bc00ae02SRob Clark return ((val) << A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK; 2505bc00ae02SRob Clark } 2506bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 2507bc00ae02SRob Clark #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT 24 2508bc00ae02SRob Clark static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val) 2509bc00ae02SRob Clark { 2510bc00ae02SRob Clark return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK; 2511bc00ae02SRob Clark } 2512bc00ae02SRob Clark 2513af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CS_CONTROL 0x000023ca 2514af6cb4c1SRob Clark 2515af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_NDRANGE_0 0x000023cd 2516af6cb4c1SRob Clark 2517af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_NDRANGE_1 0x000023ce 2518af6cb4c1SRob Clark 2519af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_NDRANGE_2 0x000023cf 2520af6cb4c1SRob Clark 2521af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_NDRANGE_3 0x000023d0 2522af6cb4c1SRob Clark 2523af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_NDRANGE_4 0x000023d1 2524af6cb4c1SRob Clark 2525af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_NDRANGE_5 0x000023d2 2526af6cb4c1SRob Clark 2527af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_NDRANGE_6 0x000023d3 2528af6cb4c1SRob Clark 2529af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_CONTROL_0 0x000023d4 2530af6cb4c1SRob Clark 2531af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_CONTROL_1 0x000023d5 2532af6cb4c1SRob Clark 2533af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_KERNEL_CONST 0x000023d6 2534af6cb4c1SRob Clark 2535af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_X 0x000023d7 2536af6cb4c1SRob Clark 2537af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Y 0x000023d8 2538af6cb4c1SRob Clark 2539af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z 0x000023d9 2540af6cb4c1SRob Clark 2541af6cb4c1SRob Clark #define REG_A4XX_HLSQ_CL_WG_OFFSET 0x000023da 2542af6cb4c1SRob Clark 2543bc00ae02SRob Clark #define REG_A4XX_HLSQ_UPDATE_CONTROL 0x000023db 2544bc00ae02SRob Clark 2545bc00ae02SRob Clark #define REG_A4XX_PC_BINNING_COMMAND 0x00000d00 2546bc00ae02SRob Clark #define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001 2547bc00ae02SRob Clark 2548bc00ae02SRob Clark #define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c 2549bc00ae02SRob Clark 2550bc00ae02SRob Clark #define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10 2551bc00ae02SRob Clark 2552bc00ae02SRob Clark #define REG_A4XX_PC_PERFCTR_PC_SEL_7 0x00000d17 2553bc00ae02SRob Clark 2554bc00ae02SRob Clark #define REG_A4XX_PC_BIN_BASE 0x000021c0 2555bc00ae02SRob Clark 2556bc00ae02SRob Clark #define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4 2557af6cb4c1SRob Clark #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK 0x0000000f 2558af6cb4c1SRob Clark #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT 0 2559af6cb4c1SRob Clark static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val) 2560af6cb4c1SRob Clark { 2561af6cb4c1SRob Clark return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK; 2562af6cb4c1SRob Clark } 2563af6cb4c1SRob Clark #define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000 2564bc00ae02SRob Clark #define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000 2565bc00ae02SRob Clark #define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000 2566bc00ae02SRob Clark 2567bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_21C5 0x000021c5 2568bc00ae02SRob Clark 2569bc00ae02SRob Clark #define REG_A4XX_PC_RESTART_INDEX 0x000021c6 2570bc00ae02SRob Clark 2571bc00ae02SRob Clark #define REG_A4XX_PC_GS_PARAM 0x000021e5 2572af6cb4c1SRob Clark #define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff 2573af6cb4c1SRob Clark #define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0 2574af6cb4c1SRob Clark static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val) 2575af6cb4c1SRob Clark { 2576af6cb4c1SRob Clark return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK; 2577af6cb4c1SRob Clark } 2578af6cb4c1SRob Clark #define A4XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800 2579af6cb4c1SRob Clark #define A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11 2580af6cb4c1SRob Clark static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val) 2581af6cb4c1SRob Clark { 2582af6cb4c1SRob Clark return ((val) << A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A4XX_PC_GS_PARAM_INVOCATIONS__MASK; 2583af6cb4c1SRob Clark } 2584af6cb4c1SRob Clark #define A4XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000 2585af6cb4c1SRob Clark #define A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23 2586af6cb4c1SRob Clark static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val) 2587af6cb4c1SRob Clark { 2588af6cb4c1SRob Clark return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK; 2589af6cb4c1SRob Clark } 2590af6cb4c1SRob Clark #define A4XX_PC_GS_PARAM_LAYER 0x80000000 2591bc00ae02SRob Clark 2592bc00ae02SRob Clark #define REG_A4XX_PC_HS_PARAM 0x000021e7 2593af6cb4c1SRob Clark #define A4XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f 2594af6cb4c1SRob Clark #define A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0 2595af6cb4c1SRob Clark static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val) 2596af6cb4c1SRob Clark { 2597af6cb4c1SRob Clark return ((val) << A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A4XX_PC_HS_PARAM_VERTICES_OUT__MASK; 2598af6cb4c1SRob Clark } 2599af6cb4c1SRob Clark #define A4XX_PC_HS_PARAM_SPACING__MASK 0x00600000 2600af6cb4c1SRob Clark #define A4XX_PC_HS_PARAM_SPACING__SHIFT 21 2601af6cb4c1SRob Clark static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val) 2602af6cb4c1SRob Clark { 2603af6cb4c1SRob Clark return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK; 2604af6cb4c1SRob Clark } 2605af6cb4c1SRob Clark #define A4XX_PC_HS_PARAM_PRIMTYPE__MASK 0x01800000 2606af6cb4c1SRob Clark #define A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT 23 2607af6cb4c1SRob Clark static inline uint32_t A4XX_PC_HS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val) 2608af6cb4c1SRob Clark { 2609af6cb4c1SRob Clark return ((val) << A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_HS_PARAM_PRIMTYPE__MASK; 2610af6cb4c1SRob Clark } 2611bc00ae02SRob Clark 2612bc00ae02SRob Clark #define REG_A4XX_VBIF_VERSION 0x00003000 2613bc00ae02SRob Clark 2614bc00ae02SRob Clark #define REG_A4XX_VBIF_CLKON 0x00003001 2615bc00ae02SRob Clark #define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000001 2616bc00ae02SRob Clark 2617bc00ae02SRob Clark #define REG_A4XX_VBIF_ABIT_SORT 0x0000301c 2618bc00ae02SRob Clark 2619bc00ae02SRob Clark #define REG_A4XX_VBIF_ABIT_SORT_CONF 0x0000301d 2620bc00ae02SRob Clark 2621bc00ae02SRob Clark #define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 2622bc00ae02SRob Clark 2623bc00ae02SRob Clark #define REG_A4XX_VBIF_IN_RD_LIM_CONF0 0x0000302c 2624bc00ae02SRob Clark 2625bc00ae02SRob Clark #define REG_A4XX_VBIF_IN_RD_LIM_CONF1 0x0000302d 2626bc00ae02SRob Clark 2627bc00ae02SRob Clark #define REG_A4XX_VBIF_IN_WR_LIM_CONF0 0x00003030 2628bc00ae02SRob Clark 2629bc00ae02SRob Clark #define REG_A4XX_VBIF_IN_WR_LIM_CONF1 0x00003031 2630bc00ae02SRob Clark 2631bc00ae02SRob Clark #define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049 2632bc00ae02SRob Clark 2633bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_0CC5 0x00000cc5 2634bc00ae02SRob Clark 2635bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_0CC6 0x00000cc6 2636bc00ae02SRob Clark 2637bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_0D01 0x00000d01 2638bc00ae02SRob Clark 2639bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_0E42 0x00000e42 2640bc00ae02SRob Clark 2641bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_0EC2 0x00000ec2 2642bc00ae02SRob Clark 2643bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2001 0x00002001 2644bc00ae02SRob Clark 2645bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_209B 0x0000209b 2646bc00ae02SRob Clark 2647bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_20EF 0x000020ef 2648bc00ae02SRob Clark 2649bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_20F0 0x000020f0 2650bc00ae02SRob Clark 2651bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_20F1 0x000020f1 2652bc00ae02SRob Clark 2653bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_20F2 0x000020f2 2654bc00ae02SRob Clark 2655bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_20F7 0x000020f7 26568a264743SRob Clark #define A4XX_UNKNOWN_20F7__MASK 0xffffffff 26578a264743SRob Clark #define A4XX_UNKNOWN_20F7__SHIFT 0 26588a264743SRob Clark static inline uint32_t A4XX_UNKNOWN_20F7(float val) 26598a264743SRob Clark { 26608a264743SRob Clark return ((fui(val)) << A4XX_UNKNOWN_20F7__SHIFT) & A4XX_UNKNOWN_20F7__MASK; 26618a264743SRob Clark } 2662bc00ae02SRob Clark 2663bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2152 0x00002152 2664bc00ae02SRob Clark 2665bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2153 0x00002153 2666bc00ae02SRob Clark 2667bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2154 0x00002154 2668bc00ae02SRob Clark 2669bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2155 0x00002155 2670bc00ae02SRob Clark 2671bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2156 0x00002156 2672bc00ae02SRob Clark 2673bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2157 0x00002157 2674bc00ae02SRob Clark 2675bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_21C3 0x000021c3 2676bc00ae02SRob Clark 2677bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_21E6 0x000021e6 2678bc00ae02SRob Clark 2679bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_2209 0x00002209 2680bc00ae02SRob Clark 2681bc00ae02SRob Clark #define REG_A4XX_UNKNOWN_22D7 0x000022d7 2682bc00ae02SRob Clark 26832d3584ebSRob Clark #define REG_A4XX_UNKNOWN_2352 0x00002352 26842d3584ebSRob Clark 2685bc00ae02SRob Clark #define REG_A4XX_TEX_SAMP_0 0x00000000 26868a264743SRob Clark #define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 2687bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 2688bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_XY_MAG__SHIFT 1 2689bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val) 2690bc00ae02SRob Clark { 2691bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_0_XY_MAG__SHIFT) & A4XX_TEX_SAMP_0_XY_MAG__MASK; 2692bc00ae02SRob Clark } 2693bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 2694bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_XY_MIN__SHIFT 3 2695bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val) 2696bc00ae02SRob Clark { 2697bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_0_XY_MIN__SHIFT) & A4XX_TEX_SAMP_0_XY_MIN__MASK; 2698bc00ae02SRob Clark } 2699bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 2700bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_S__SHIFT 5 2701bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val) 2702bc00ae02SRob Clark { 2703bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_0_WRAP_S__SHIFT) & A4XX_TEX_SAMP_0_WRAP_S__MASK; 2704bc00ae02SRob Clark } 2705bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 2706bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_T__SHIFT 8 2707bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val) 2708bc00ae02SRob Clark { 2709bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_0_WRAP_T__SHIFT) & A4XX_TEX_SAMP_0_WRAP_T__MASK; 2710bc00ae02SRob Clark } 2711bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 2712bc00ae02SRob Clark #define A4XX_TEX_SAMP_0_WRAP_R__SHIFT 11 2713bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val) 2714bc00ae02SRob Clark { 2715bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK; 2716bc00ae02SRob Clark } 2717af6cb4c1SRob Clark #define A4XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 2718af6cb4c1SRob Clark #define A4XX_TEX_SAMP_0_ANISO__SHIFT 14 2719af6cb4c1SRob Clark static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val) 2720af6cb4c1SRob Clark { 2721af6cb4c1SRob Clark return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK; 2722af6cb4c1SRob Clark } 2723bc00ae02SRob Clark 2724bc00ae02SRob Clark #define REG_A4XX_TEX_SAMP_1 0x00000001 2725bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e 2726bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 2727bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) 2728bc00ae02SRob Clark { 2729bc00ae02SRob Clark return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK; 2730bc00ae02SRob Clark } 27318a264743SRob Clark #define A4XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 27328a264743SRob Clark #define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 2733bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 2734bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 2735bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val) 2736bc00ae02SRob Clark { 27378a264743SRob Clark return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK; 2738bc00ae02SRob Clark } 2739bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 2740bc00ae02SRob Clark #define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 2741bc00ae02SRob Clark static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val) 2742bc00ae02SRob Clark { 27438a264743SRob Clark return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK; 2744bc00ae02SRob Clark } 2745bc00ae02SRob Clark 2746bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_0 0x00000000 2747bc00ae02SRob Clark #define A4XX_TEX_CONST_0_TILED 0x00000001 2748af6cb4c1SRob Clark #define A4XX_TEX_CONST_0_SRGB 0x00000004 2749bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 2750bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_X__SHIFT 4 2751bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val) 2752bc00ae02SRob Clark { 2753bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) & A4XX_TEX_CONST_0_SWIZ_X__MASK; 2754bc00ae02SRob Clark } 2755bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 2756bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 2757bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val) 2758bc00ae02SRob Clark { 2759bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Y__MASK; 2760bc00ae02SRob Clark } 2761bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 2762bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 2763bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val) 2764bc00ae02SRob Clark { 2765bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Z__MASK; 2766bc00ae02SRob Clark } 2767bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 2768bc00ae02SRob Clark #define A4XX_TEX_CONST_0_SWIZ_W__SHIFT 13 2769bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val) 2770bc00ae02SRob Clark { 2771bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK; 2772bc00ae02SRob Clark } 27738a264743SRob Clark #define A4XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 27748a264743SRob Clark #define A4XX_TEX_CONST_0_MIPLVLS__SHIFT 16 27758a264743SRob Clark static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val) 27768a264743SRob Clark { 27778a264743SRob Clark return ((val) << A4XX_TEX_CONST_0_MIPLVLS__SHIFT) & A4XX_TEX_CONST_0_MIPLVLS__MASK; 27788a264743SRob Clark } 2779bc00ae02SRob Clark #define A4XX_TEX_CONST_0_FMT__MASK 0x1fc00000 2780bc00ae02SRob Clark #define A4XX_TEX_CONST_0_FMT__SHIFT 22 2781bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val) 2782bc00ae02SRob Clark { 2783bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK; 2784bc00ae02SRob Clark } 2785bc00ae02SRob Clark #define A4XX_TEX_CONST_0_TYPE__MASK 0x60000000 2786bc00ae02SRob Clark #define A4XX_TEX_CONST_0_TYPE__SHIFT 29 2787bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val) 2788bc00ae02SRob Clark { 2789bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_0_TYPE__SHIFT) & A4XX_TEX_CONST_0_TYPE__MASK; 2790bc00ae02SRob Clark } 2791bc00ae02SRob Clark 2792bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_1 0x00000001 2793bc00ae02SRob Clark #define A4XX_TEX_CONST_1_HEIGHT__MASK 0x00007fff 2794bc00ae02SRob Clark #define A4XX_TEX_CONST_1_HEIGHT__SHIFT 0 2795bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val) 2796bc00ae02SRob Clark { 2797bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK; 2798bc00ae02SRob Clark } 2799bc00ae02SRob Clark #define A4XX_TEX_CONST_1_WIDTH__MASK 0x1fff8000 2800bc00ae02SRob Clark #define A4XX_TEX_CONST_1_WIDTH__SHIFT 15 2801bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val) 2802bc00ae02SRob Clark { 2803bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK; 2804bc00ae02SRob Clark } 2805bc00ae02SRob Clark 2806bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_2 0x00000002 28078a264743SRob Clark #define A4XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f 28088a264743SRob Clark #define A4XX_TEX_CONST_2_FETCHSIZE__SHIFT 0 28098a264743SRob Clark static inline uint32_t A4XX_TEX_CONST_2_FETCHSIZE(enum a4xx_tex_fetchsize val) 28108a264743SRob Clark { 28118a264743SRob Clark return ((val) << A4XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A4XX_TEX_CONST_2_FETCHSIZE__MASK; 28128a264743SRob Clark } 2813bc00ae02SRob Clark #define A4XX_TEX_CONST_2_PITCH__MASK 0x3ffffe00 2814bc00ae02SRob Clark #define A4XX_TEX_CONST_2_PITCH__SHIFT 9 2815bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val) 2816bc00ae02SRob Clark { 2817bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) & A4XX_TEX_CONST_2_PITCH__MASK; 2818bc00ae02SRob Clark } 2819bc00ae02SRob Clark #define A4XX_TEX_CONST_2_SWAP__MASK 0xc0000000 2820bc00ae02SRob Clark #define A4XX_TEX_CONST_2_SWAP__SHIFT 30 2821bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) 2822bc00ae02SRob Clark { 2823bc00ae02SRob Clark return ((val) << A4XX_TEX_CONST_2_SWAP__SHIFT) & A4XX_TEX_CONST_2_SWAP__MASK; 2824bc00ae02SRob Clark } 2825bc00ae02SRob Clark 2826bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_3 0x00000003 28278a264743SRob Clark #define A4XX_TEX_CONST_3_LAYERSZ__MASK 0x00003fff 2828bc00ae02SRob Clark #define A4XX_TEX_CONST_3_LAYERSZ__SHIFT 0 2829bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val) 2830bc00ae02SRob Clark { 2831bc00ae02SRob Clark return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK; 2832bc00ae02SRob Clark } 28338a264743SRob Clark #define A4XX_TEX_CONST_3_DEPTH__MASK 0x7ffc0000 28348a264743SRob Clark #define A4XX_TEX_CONST_3_DEPTH__SHIFT 18 28358a264743SRob Clark static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val) 28368a264743SRob Clark { 28378a264743SRob Clark return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK; 28388a264743SRob Clark } 2839bc00ae02SRob Clark 2840bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_4 0x00000004 28418a264743SRob Clark #define A4XX_TEX_CONST_4_LAYERSZ__MASK 0x0000000f 28428a264743SRob Clark #define A4XX_TEX_CONST_4_LAYERSZ__SHIFT 0 28438a264743SRob Clark static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val) 28448a264743SRob Clark { 28458a264743SRob Clark return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK; 28468a264743SRob Clark } 28478a264743SRob Clark #define A4XX_TEX_CONST_4_BASE__MASK 0xffffffe0 28488a264743SRob Clark #define A4XX_TEX_CONST_4_BASE__SHIFT 5 2849bc00ae02SRob Clark static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val) 2850bc00ae02SRob Clark { 28518a264743SRob Clark return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK; 2852bc00ae02SRob Clark } 2853bc00ae02SRob Clark 2854bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_5 0x00000005 2855bc00ae02SRob Clark 2856bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_6 0x00000006 2857bc00ae02SRob Clark 2858bc00ae02SRob Clark #define REG_A4XX_TEX_CONST_7 0x00000007 2859bc00ae02SRob Clark 2860bc00ae02SRob Clark 2861bc00ae02SRob Clark #endif /* A4XX_XML */ 2862