1 #ifndef A3XX_XML 2 #define A3XX_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2023-03-10 18:32:52) 12 - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46) 13 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 91929 bytes, from 2023-02-28 23:52:27) 14 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from 2023-03-10 18:32:53) 15 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 74995 bytes, from 2023-03-20 18:06:23) 16 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2022-08-02 16:38:43) 17 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113474 bytes, from 2022-08-02 16:38:43) 18 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149590 bytes, from 2023-02-14 19:37:12) 19 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 198949 bytes, from 2023-03-20 18:06:23) 20 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11404 bytes, from 2023-03-10 18:32:53) 21 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2022-08-02 16:38:43) 22 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 9055 bytes, from 2023-03-10 18:32:52) 23 - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2976 bytes, from 2023-03-10 18:32:52) 24 25 Copyright (C) 2013-2022 by the following authors: 26 - Rob Clark <robdclark@gmail.com> (robclark) 27 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 28 29 Permission is hereby granted, free of charge, to any person obtaining 30 a copy of this software and associated documentation files (the 31 "Software"), to deal in the Software without restriction, including 32 without limitation the rights to use, copy, modify, merge, publish, 33 distribute, sublicense, and/or sell copies of the Software, and to 34 permit persons to whom the Software is furnished to do so, subject to 35 the following conditions: 36 37 The above copyright notice and this permission notice (including the 38 next paragraph) shall be included in all copies or substantial 39 portions of the Software. 40 41 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 42 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 43 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 44 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 45 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 46 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 47 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 48 */ 49 50 51 enum a3xx_tile_mode { 52 LINEAR = 0, 53 TILE_4X4 = 1, 54 TILE_32X32 = 2, 55 TILE_4X2 = 3, 56 }; 57 58 enum a3xx_state_block_id { 59 HLSQ_BLOCK_ID_TP_TEX = 2, 60 HLSQ_BLOCK_ID_TP_MIPMAP = 3, 61 HLSQ_BLOCK_ID_SP_VS = 4, 62 HLSQ_BLOCK_ID_SP_FS = 6, 63 }; 64 65 enum a3xx_cache_opcode { 66 INVALIDATE = 1, 67 }; 68 69 enum a3xx_vtx_fmt { 70 VFMT_32_FLOAT = 0, 71 VFMT_32_32_FLOAT = 1, 72 VFMT_32_32_32_FLOAT = 2, 73 VFMT_32_32_32_32_FLOAT = 3, 74 VFMT_16_FLOAT = 4, 75 VFMT_16_16_FLOAT = 5, 76 VFMT_16_16_16_FLOAT = 6, 77 VFMT_16_16_16_16_FLOAT = 7, 78 VFMT_32_FIXED = 8, 79 VFMT_32_32_FIXED = 9, 80 VFMT_32_32_32_FIXED = 10, 81 VFMT_32_32_32_32_FIXED = 11, 82 VFMT_16_SINT = 16, 83 VFMT_16_16_SINT = 17, 84 VFMT_16_16_16_SINT = 18, 85 VFMT_16_16_16_16_SINT = 19, 86 VFMT_16_UINT = 20, 87 VFMT_16_16_UINT = 21, 88 VFMT_16_16_16_UINT = 22, 89 VFMT_16_16_16_16_UINT = 23, 90 VFMT_16_SNORM = 24, 91 VFMT_16_16_SNORM = 25, 92 VFMT_16_16_16_SNORM = 26, 93 VFMT_16_16_16_16_SNORM = 27, 94 VFMT_16_UNORM = 28, 95 VFMT_16_16_UNORM = 29, 96 VFMT_16_16_16_UNORM = 30, 97 VFMT_16_16_16_16_UNORM = 31, 98 VFMT_32_UINT = 32, 99 VFMT_32_32_UINT = 33, 100 VFMT_32_32_32_UINT = 34, 101 VFMT_32_32_32_32_UINT = 35, 102 VFMT_32_SINT = 36, 103 VFMT_32_32_SINT = 37, 104 VFMT_32_32_32_SINT = 38, 105 VFMT_32_32_32_32_SINT = 39, 106 VFMT_8_UINT = 40, 107 VFMT_8_8_UINT = 41, 108 VFMT_8_8_8_UINT = 42, 109 VFMT_8_8_8_8_UINT = 43, 110 VFMT_8_UNORM = 44, 111 VFMT_8_8_UNORM = 45, 112 VFMT_8_8_8_UNORM = 46, 113 VFMT_8_8_8_8_UNORM = 47, 114 VFMT_8_SINT = 48, 115 VFMT_8_8_SINT = 49, 116 VFMT_8_8_8_SINT = 50, 117 VFMT_8_8_8_8_SINT = 51, 118 VFMT_8_SNORM = 52, 119 VFMT_8_8_SNORM = 53, 120 VFMT_8_8_8_SNORM = 54, 121 VFMT_8_8_8_8_SNORM = 55, 122 VFMT_10_10_10_2_UINT = 56, 123 VFMT_10_10_10_2_UNORM = 57, 124 VFMT_10_10_10_2_SINT = 58, 125 VFMT_10_10_10_2_SNORM = 59, 126 VFMT_2_10_10_10_UINT = 60, 127 VFMT_2_10_10_10_UNORM = 61, 128 VFMT_2_10_10_10_SINT = 62, 129 VFMT_2_10_10_10_SNORM = 63, 130 VFMT_NONE = 255, 131 }; 132 133 enum a3xx_tex_fmt { 134 TFMT_5_6_5_UNORM = 4, 135 TFMT_5_5_5_1_UNORM = 5, 136 TFMT_4_4_4_4_UNORM = 7, 137 TFMT_Z16_UNORM = 9, 138 TFMT_X8Z24_UNORM = 10, 139 TFMT_Z32_FLOAT = 11, 140 TFMT_UV_64X32 = 16, 141 TFMT_VU_64X32 = 17, 142 TFMT_Y_64X32 = 18, 143 TFMT_NV12_64X32 = 19, 144 TFMT_UV_LINEAR = 20, 145 TFMT_VU_LINEAR = 21, 146 TFMT_Y_LINEAR = 22, 147 TFMT_NV12_LINEAR = 23, 148 TFMT_I420_Y = 24, 149 TFMT_I420_U = 26, 150 TFMT_I420_V = 27, 151 TFMT_ATC_RGB = 32, 152 TFMT_ATC_RGBA_EXPLICIT = 33, 153 TFMT_ETC1 = 34, 154 TFMT_ATC_RGBA_INTERPOLATED = 35, 155 TFMT_DXT1 = 36, 156 TFMT_DXT3 = 37, 157 TFMT_DXT5 = 38, 158 TFMT_2_10_10_10_UNORM = 40, 159 TFMT_10_10_10_2_UNORM = 41, 160 TFMT_9_9_9_E5_FLOAT = 42, 161 TFMT_11_11_10_FLOAT = 43, 162 TFMT_A8_UNORM = 44, 163 TFMT_L8_UNORM = 45, 164 TFMT_L8_A8_UNORM = 47, 165 TFMT_8_UNORM = 48, 166 TFMT_8_8_UNORM = 49, 167 TFMT_8_8_8_UNORM = 50, 168 TFMT_8_8_8_8_UNORM = 51, 169 TFMT_8_SNORM = 52, 170 TFMT_8_8_SNORM = 53, 171 TFMT_8_8_8_SNORM = 54, 172 TFMT_8_8_8_8_SNORM = 55, 173 TFMT_8_UINT = 56, 174 TFMT_8_8_UINT = 57, 175 TFMT_8_8_8_UINT = 58, 176 TFMT_8_8_8_8_UINT = 59, 177 TFMT_8_SINT = 60, 178 TFMT_8_8_SINT = 61, 179 TFMT_8_8_8_SINT = 62, 180 TFMT_8_8_8_8_SINT = 63, 181 TFMT_16_FLOAT = 64, 182 TFMT_16_16_FLOAT = 65, 183 TFMT_16_16_16_16_FLOAT = 67, 184 TFMT_16_UINT = 68, 185 TFMT_16_16_UINT = 69, 186 TFMT_16_16_16_16_UINT = 71, 187 TFMT_16_SINT = 72, 188 TFMT_16_16_SINT = 73, 189 TFMT_16_16_16_16_SINT = 75, 190 TFMT_16_UNORM = 76, 191 TFMT_16_16_UNORM = 77, 192 TFMT_16_16_16_16_UNORM = 79, 193 TFMT_16_SNORM = 80, 194 TFMT_16_16_SNORM = 81, 195 TFMT_16_16_16_16_SNORM = 83, 196 TFMT_32_FLOAT = 84, 197 TFMT_32_32_FLOAT = 85, 198 TFMT_32_32_32_32_FLOAT = 87, 199 TFMT_32_UINT = 88, 200 TFMT_32_32_UINT = 89, 201 TFMT_32_32_32_32_UINT = 91, 202 TFMT_32_SINT = 92, 203 TFMT_32_32_SINT = 93, 204 TFMT_32_32_32_32_SINT = 95, 205 TFMT_2_10_10_10_UINT = 96, 206 TFMT_10_10_10_2_UINT = 97, 207 TFMT_ETC2_RG11_SNORM = 112, 208 TFMT_ETC2_RG11_UNORM = 113, 209 TFMT_ETC2_R11_SNORM = 114, 210 TFMT_ETC2_R11_UNORM = 115, 211 TFMT_ETC2_RGBA8 = 116, 212 TFMT_ETC2_RGB8A1 = 117, 213 TFMT_ETC2_RGB8 = 118, 214 TFMT_NONE = 255, 215 }; 216 217 enum a3xx_color_fmt { 218 RB_R5G6B5_UNORM = 0, 219 RB_R5G5B5A1_UNORM = 1, 220 RB_R4G4B4A4_UNORM = 3, 221 RB_R8G8B8_UNORM = 4, 222 RB_R8G8B8A8_UNORM = 8, 223 RB_R8G8B8A8_SNORM = 9, 224 RB_R8G8B8A8_UINT = 10, 225 RB_R8G8B8A8_SINT = 11, 226 RB_R8G8_UNORM = 12, 227 RB_R8G8_SNORM = 13, 228 RB_R8G8_UINT = 14, 229 RB_R8G8_SINT = 15, 230 RB_R10G10B10A2_UNORM = 16, 231 RB_A2R10G10B10_UNORM = 17, 232 RB_R10G10B10A2_UINT = 18, 233 RB_A2R10G10B10_UINT = 19, 234 RB_A8_UNORM = 20, 235 RB_R8_UNORM = 21, 236 RB_R16_FLOAT = 24, 237 RB_R16G16_FLOAT = 25, 238 RB_R16G16B16A16_FLOAT = 27, 239 RB_R11G11B10_FLOAT = 28, 240 RB_R16_SNORM = 32, 241 RB_R16G16_SNORM = 33, 242 RB_R16G16B16A16_SNORM = 35, 243 RB_R16_UNORM = 36, 244 RB_R16G16_UNORM = 37, 245 RB_R16G16B16A16_UNORM = 39, 246 RB_R16_SINT = 40, 247 RB_R16G16_SINT = 41, 248 RB_R16G16B16A16_SINT = 43, 249 RB_R16_UINT = 44, 250 RB_R16G16_UINT = 45, 251 RB_R16G16B16A16_UINT = 47, 252 RB_R32_FLOAT = 48, 253 RB_R32G32_FLOAT = 49, 254 RB_R32G32B32A32_FLOAT = 51, 255 RB_R32_SINT = 52, 256 RB_R32G32_SINT = 53, 257 RB_R32G32B32A32_SINT = 55, 258 RB_R32_UINT = 56, 259 RB_R32G32_UINT = 57, 260 RB_R32G32B32A32_UINT = 59, 261 RB_NONE = 255, 262 }; 263 264 enum a3xx_cp_perfcounter_select { 265 CP_ALWAYS_COUNT = 0, 266 CP_AHB_PFPTRANS_WAIT = 3, 267 CP_AHB_NRTTRANS_WAIT = 6, 268 CP_CSF_NRT_READ_WAIT = 8, 269 CP_CSF_I1_FIFO_FULL = 9, 270 CP_CSF_I2_FIFO_FULL = 10, 271 CP_CSF_ST_FIFO_FULL = 11, 272 CP_RESERVED_12 = 12, 273 CP_CSF_RING_ROQ_FULL = 13, 274 CP_CSF_I1_ROQ_FULL = 14, 275 CP_CSF_I2_ROQ_FULL = 15, 276 CP_CSF_ST_ROQ_FULL = 16, 277 CP_RESERVED_17 = 17, 278 CP_MIU_TAG_MEM_FULL = 18, 279 CP_MIU_NRT_WRITE_STALLED = 22, 280 CP_MIU_NRT_READ_STALLED = 23, 281 CP_ME_REGS_RB_DONE_FIFO_FULL = 26, 282 CP_ME_REGS_VS_EVENT_FIFO_FULL = 27, 283 CP_ME_REGS_PS_EVENT_FIFO_FULL = 28, 284 CP_ME_REGS_CF_EVENT_FIFO_FULL = 29, 285 CP_ME_MICRO_RB_STARVED = 30, 286 CP_AHB_RBBM_DWORD_SENT = 40, 287 CP_ME_BUSY_CLOCKS = 41, 288 CP_ME_WAIT_CONTEXT_AVAIL = 42, 289 CP_PFP_TYPE0_PACKET = 43, 290 CP_PFP_TYPE3_PACKET = 44, 291 CP_CSF_RB_WPTR_NEQ_RPTR = 45, 292 CP_CSF_I1_SIZE_NEQ_ZERO = 46, 293 CP_CSF_I2_SIZE_NEQ_ZERO = 47, 294 CP_CSF_RBI1I2_FETCHING = 48, 295 }; 296 297 enum a3xx_gras_tse_perfcounter_select { 298 GRAS_TSEPERF_INPUT_PRIM = 0, 299 GRAS_TSEPERF_INPUT_NULL_PRIM = 1, 300 GRAS_TSEPERF_TRIVAL_REJ_PRIM = 2, 301 GRAS_TSEPERF_CLIPPED_PRIM = 3, 302 GRAS_TSEPERF_NEW_PRIM = 4, 303 GRAS_TSEPERF_ZERO_AREA_PRIM = 5, 304 GRAS_TSEPERF_FACENESS_CULLED_PRIM = 6, 305 GRAS_TSEPERF_ZERO_PIXEL_PRIM = 7, 306 GRAS_TSEPERF_OUTPUT_NULL_PRIM = 8, 307 GRAS_TSEPERF_OUTPUT_VISIBLE_PRIM = 9, 308 GRAS_TSEPERF_PRE_CLIP_PRIM = 10, 309 GRAS_TSEPERF_POST_CLIP_PRIM = 11, 310 GRAS_TSEPERF_WORKING_CYCLES = 12, 311 GRAS_TSEPERF_PC_STARVE = 13, 312 GRAS_TSERASPERF_STALL = 14, 313 }; 314 315 enum a3xx_gras_ras_perfcounter_select { 316 GRAS_RASPERF_16X16_TILES = 0, 317 GRAS_RASPERF_8X8_TILES = 1, 318 GRAS_RASPERF_4X4_TILES = 2, 319 GRAS_RASPERF_WORKING_CYCLES = 3, 320 GRAS_RASPERF_STALL_CYCLES_BY_RB = 4, 321 GRAS_RASPERF_STALL_CYCLES_BY_VSC = 5, 322 GRAS_RASPERF_STARVE_CYCLES_BY_TSE = 6, 323 }; 324 325 enum a3xx_hlsq_perfcounter_select { 326 HLSQ_PERF_SP_VS_CONSTANT = 0, 327 HLSQ_PERF_SP_VS_INSTRUCTIONS = 1, 328 HLSQ_PERF_SP_FS_CONSTANT = 2, 329 HLSQ_PERF_SP_FS_INSTRUCTIONS = 3, 330 HLSQ_PERF_TP_STATE = 4, 331 HLSQ_PERF_QUADS = 5, 332 HLSQ_PERF_PIXELS = 6, 333 HLSQ_PERF_VERTICES = 7, 334 HLSQ_PERF_FS8_THREADS = 8, 335 HLSQ_PERF_FS16_THREADS = 9, 336 HLSQ_PERF_FS32_THREADS = 10, 337 HLSQ_PERF_VS8_THREADS = 11, 338 HLSQ_PERF_VS16_THREADS = 12, 339 HLSQ_PERF_SP_VS_DATA_BYTES = 13, 340 HLSQ_PERF_SP_FS_DATA_BYTES = 14, 341 HLSQ_PERF_ACTIVE_CYCLES = 15, 342 HLSQ_PERF_STALL_CYCLES_SP_STATE = 16, 343 HLSQ_PERF_STALL_CYCLES_SP_VS = 17, 344 HLSQ_PERF_STALL_CYCLES_SP_FS = 18, 345 HLSQ_PERF_STALL_CYCLES_UCHE = 19, 346 HLSQ_PERF_RBBM_LOAD_CYCLES = 20, 347 HLSQ_PERF_DI_TO_VS_START_SP0 = 21, 348 HLSQ_PERF_DI_TO_FS_START_SP0 = 22, 349 HLSQ_PERF_VS_START_TO_DONE_SP0 = 23, 350 HLSQ_PERF_FS_START_TO_DONE_SP0 = 24, 351 HLSQ_PERF_SP_STATE_COPY_CYCLES_VS = 25, 352 HLSQ_PERF_SP_STATE_COPY_CYCLES_FS = 26, 353 HLSQ_PERF_UCHE_LATENCY_CYCLES = 27, 354 HLSQ_PERF_UCHE_LATENCY_COUNT = 28, 355 }; 356 357 enum a3xx_pc_perfcounter_select { 358 PC_PCPERF_VISIBILITY_STREAMS = 0, 359 PC_PCPERF_TOTAL_INSTANCES = 1, 360 PC_PCPERF_PRIMITIVES_PC_VPC = 2, 361 PC_PCPERF_PRIMITIVES_KILLED_BY_VS = 3, 362 PC_PCPERF_PRIMITIVES_VISIBLE_BY_VS = 4, 363 PC_PCPERF_DRAWCALLS_KILLED_BY_VS = 5, 364 PC_PCPERF_DRAWCALLS_VISIBLE_BY_VS = 6, 365 PC_PCPERF_VERTICES_TO_VFD = 7, 366 PC_PCPERF_REUSED_VERTICES = 8, 367 PC_PCPERF_CYCLES_STALLED_BY_VFD = 9, 368 PC_PCPERF_CYCLES_STALLED_BY_TSE = 10, 369 PC_PCPERF_CYCLES_STALLED_BY_VBIF = 11, 370 PC_PCPERF_CYCLES_IS_WORKING = 12, 371 }; 372 373 enum a3xx_rb_perfcounter_select { 374 RB_RBPERF_ACTIVE_CYCLES_ANY = 0, 375 RB_RBPERF_ACTIVE_CYCLES_ALL = 1, 376 RB_RBPERF_STARVE_CYCLES_BY_SP = 2, 377 RB_RBPERF_STARVE_CYCLES_BY_RAS = 3, 378 RB_RBPERF_STARVE_CYCLES_BY_MARB = 4, 379 RB_RBPERF_STALL_CYCLES_BY_MARB = 5, 380 RB_RBPERF_STALL_CYCLES_BY_HLSQ = 6, 381 RB_RBPERF_RB_MARB_DATA = 7, 382 RB_RBPERF_SP_RB_QUAD = 8, 383 RB_RBPERF_RAS_EARLY_Z_QUADS = 9, 384 RB_RBPERF_GMEM_CH0_READ = 10, 385 RB_RBPERF_GMEM_CH1_READ = 11, 386 RB_RBPERF_GMEM_CH0_WRITE = 12, 387 RB_RBPERF_GMEM_CH1_WRITE = 13, 388 RB_RBPERF_CP_CONTEXT_DONE = 14, 389 RB_RBPERF_CP_CACHE_FLUSH = 15, 390 RB_RBPERF_CP_ZPASS_DONE = 16, 391 }; 392 393 enum a3xx_rbbm_perfcounter_select { 394 RBBM_ALAWYS_ON = 0, 395 RBBM_VBIF_BUSY = 1, 396 RBBM_TSE_BUSY = 2, 397 RBBM_RAS_BUSY = 3, 398 RBBM_PC_DCALL_BUSY = 4, 399 RBBM_PC_VSD_BUSY = 5, 400 RBBM_VFD_BUSY = 6, 401 RBBM_VPC_BUSY = 7, 402 RBBM_UCHE_BUSY = 8, 403 RBBM_VSC_BUSY = 9, 404 RBBM_HLSQ_BUSY = 10, 405 RBBM_ANY_RB_BUSY = 11, 406 RBBM_ANY_TEX_BUSY = 12, 407 RBBM_ANY_USP_BUSY = 13, 408 RBBM_ANY_MARB_BUSY = 14, 409 RBBM_ANY_ARB_BUSY = 15, 410 RBBM_AHB_STATUS_BUSY = 16, 411 RBBM_AHB_STATUS_STALLED = 17, 412 RBBM_AHB_STATUS_TXFR = 18, 413 RBBM_AHB_STATUS_TXFR_SPLIT = 19, 414 RBBM_AHB_STATUS_TXFR_ERROR = 20, 415 RBBM_AHB_STATUS_LONG_STALL = 21, 416 RBBM_RBBM_STATUS_MASKED = 22, 417 }; 418 419 enum a3xx_sp_perfcounter_select { 420 SP_LM_LOAD_INSTRUCTIONS = 0, 421 SP_LM_STORE_INSTRUCTIONS = 1, 422 SP_LM_ATOMICS = 2, 423 SP_UCHE_LOAD_INSTRUCTIONS = 3, 424 SP_UCHE_STORE_INSTRUCTIONS = 4, 425 SP_UCHE_ATOMICS = 5, 426 SP_VS_TEX_INSTRUCTIONS = 6, 427 SP_VS_CFLOW_INSTRUCTIONS = 7, 428 SP_VS_EFU_INSTRUCTIONS = 8, 429 SP_VS_FULL_ALU_INSTRUCTIONS = 9, 430 SP_VS_HALF_ALU_INSTRUCTIONS = 10, 431 SP_FS_TEX_INSTRUCTIONS = 11, 432 SP_FS_CFLOW_INSTRUCTIONS = 12, 433 SP_FS_EFU_INSTRUCTIONS = 13, 434 SP_FS_FULL_ALU_INSTRUCTIONS = 14, 435 SP_FS_HALF_ALU_INSTRUCTIONS = 15, 436 SP_FS_BARY_INSTRUCTIONS = 16, 437 SP_VS_INSTRUCTIONS = 17, 438 SP_FS_INSTRUCTIONS = 18, 439 SP_ADDR_LOCK_COUNT = 19, 440 SP_UCHE_READ_TRANS = 20, 441 SP_UCHE_WRITE_TRANS = 21, 442 SP_EXPORT_VPC_TRANS = 22, 443 SP_EXPORT_RB_TRANS = 23, 444 SP_PIXELS_KILLED = 24, 445 SP_ICL1_REQUESTS = 25, 446 SP_ICL1_MISSES = 26, 447 SP_ICL0_REQUESTS = 27, 448 SP_ICL0_MISSES = 28, 449 SP_ALU_ACTIVE_CYCLES = 29, 450 SP_EFU_ACTIVE_CYCLES = 30, 451 SP_STALL_CYCLES_BY_VPC = 31, 452 SP_STALL_CYCLES_BY_TP = 32, 453 SP_STALL_CYCLES_BY_UCHE = 33, 454 SP_STALL_CYCLES_BY_RB = 34, 455 SP_ACTIVE_CYCLES_ANY = 35, 456 SP_ACTIVE_CYCLES_ALL = 36, 457 }; 458 459 enum a3xx_tp_perfcounter_select { 460 TPL1_TPPERF_L1_REQUESTS = 0, 461 TPL1_TPPERF_TP0_L1_REQUESTS = 1, 462 TPL1_TPPERF_TP0_L1_MISSES = 2, 463 TPL1_TPPERF_TP1_L1_REQUESTS = 3, 464 TPL1_TPPERF_TP1_L1_MISSES = 4, 465 TPL1_TPPERF_TP2_L1_REQUESTS = 5, 466 TPL1_TPPERF_TP2_L1_MISSES = 6, 467 TPL1_TPPERF_TP3_L1_REQUESTS = 7, 468 TPL1_TPPERF_TP3_L1_MISSES = 8, 469 TPL1_TPPERF_OUTPUT_TEXELS_POINT = 9, 470 TPL1_TPPERF_OUTPUT_TEXELS_BILINEAR = 10, 471 TPL1_TPPERF_OUTPUT_TEXELS_MIP = 11, 472 TPL1_TPPERF_OUTPUT_TEXELS_ANISO = 12, 473 TPL1_TPPERF_BILINEAR_OPS = 13, 474 TPL1_TPPERF_QUADSQUADS_OFFSET = 14, 475 TPL1_TPPERF_QUADQUADS_SHADOW = 15, 476 TPL1_TPPERF_QUADS_ARRAY = 16, 477 TPL1_TPPERF_QUADS_PROJECTION = 17, 478 TPL1_TPPERF_QUADS_GRADIENT = 18, 479 TPL1_TPPERF_QUADS_1D2D = 19, 480 TPL1_TPPERF_QUADS_3DCUBE = 20, 481 TPL1_TPPERF_ZERO_LOD = 21, 482 TPL1_TPPERF_OUTPUT_TEXELS = 22, 483 TPL1_TPPERF_ACTIVE_CYCLES_ANY = 23, 484 TPL1_TPPERF_ACTIVE_CYCLES_ALL = 24, 485 TPL1_TPPERF_STALL_CYCLES_BY_ARB = 25, 486 TPL1_TPPERF_LATENCY = 26, 487 TPL1_TPPERF_LATENCY_TRANS = 27, 488 }; 489 490 enum a3xx_vfd_perfcounter_select { 491 VFD_PERF_UCHE_BYTE_FETCHED = 0, 492 VFD_PERF_UCHE_TRANS = 1, 493 VFD_PERF_VPC_BYPASS_COMPONENTS = 2, 494 VFD_PERF_FETCH_INSTRUCTIONS = 3, 495 VFD_PERF_DECODE_INSTRUCTIONS = 4, 496 VFD_PERF_ACTIVE_CYCLES = 5, 497 VFD_PERF_STALL_CYCLES_UCHE = 6, 498 VFD_PERF_STALL_CYCLES_HLSQ = 7, 499 VFD_PERF_STALL_CYCLES_VPC_BYPASS = 8, 500 VFD_PERF_STALL_CYCLES_VPC_ALLOC = 9, 501 }; 502 503 enum a3xx_vpc_perfcounter_select { 504 VPC_PERF_SP_LM_PRIMITIVES = 0, 505 VPC_PERF_COMPONENTS_FROM_SP = 1, 506 VPC_PERF_SP_LM_COMPONENTS = 2, 507 VPC_PERF_ACTIVE_CYCLES = 3, 508 VPC_PERF_STALL_CYCLES_LM = 4, 509 VPC_PERF_STALL_CYCLES_RAS = 5, 510 }; 511 512 enum a3xx_uche_perfcounter_select { 513 UCHE_UCHEPERF_VBIF_READ_BEATS_TP = 0, 514 UCHE_UCHEPERF_VBIF_READ_BEATS_VFD = 1, 515 UCHE_UCHEPERF_VBIF_READ_BEATS_HLSQ = 2, 516 UCHE_UCHEPERF_VBIF_READ_BEATS_MARB = 3, 517 UCHE_UCHEPERF_VBIF_READ_BEATS_SP = 4, 518 UCHE_UCHEPERF_READ_REQUESTS_TP = 8, 519 UCHE_UCHEPERF_READ_REQUESTS_VFD = 9, 520 UCHE_UCHEPERF_READ_REQUESTS_HLSQ = 10, 521 UCHE_UCHEPERF_READ_REQUESTS_MARB = 11, 522 UCHE_UCHEPERF_READ_REQUESTS_SP = 12, 523 UCHE_UCHEPERF_WRITE_REQUESTS_MARB = 13, 524 UCHE_UCHEPERF_WRITE_REQUESTS_SP = 14, 525 UCHE_UCHEPERF_TAG_CHECK_FAILS = 15, 526 UCHE_UCHEPERF_EVICTS = 16, 527 UCHE_UCHEPERF_FLUSHES = 17, 528 UCHE_UCHEPERF_VBIF_LATENCY_CYCLES = 18, 529 UCHE_UCHEPERF_VBIF_LATENCY_SAMPLES = 19, 530 UCHE_UCHEPERF_ACTIVE_CYCLES = 20, 531 }; 532 533 enum a3xx_intp_mode { 534 SMOOTH = 0, 535 FLAT = 1, 536 ZERO = 2, 537 ONE = 3, 538 }; 539 540 enum a3xx_repl_mode { 541 S = 1, 542 T = 2, 543 ONE_T = 3, 544 }; 545 546 enum a3xx_tex_filter { 547 A3XX_TEX_NEAREST = 0, 548 A3XX_TEX_LINEAR = 1, 549 A3XX_TEX_ANISO = 2, 550 }; 551 552 enum a3xx_tex_clamp { 553 A3XX_TEX_REPEAT = 0, 554 A3XX_TEX_CLAMP_TO_EDGE = 1, 555 A3XX_TEX_MIRROR_REPEAT = 2, 556 A3XX_TEX_CLAMP_TO_BORDER = 3, 557 A3XX_TEX_MIRROR_CLAMP = 4, 558 }; 559 560 enum a3xx_tex_aniso { 561 A3XX_TEX_ANISO_1 = 0, 562 A3XX_TEX_ANISO_2 = 1, 563 A3XX_TEX_ANISO_4 = 2, 564 A3XX_TEX_ANISO_8 = 3, 565 A3XX_TEX_ANISO_16 = 4, 566 }; 567 568 enum a3xx_tex_swiz { 569 A3XX_TEX_X = 0, 570 A3XX_TEX_Y = 1, 571 A3XX_TEX_Z = 2, 572 A3XX_TEX_W = 3, 573 A3XX_TEX_ZERO = 4, 574 A3XX_TEX_ONE = 5, 575 }; 576 577 enum a3xx_tex_type { 578 A3XX_TEX_1D = 0, 579 A3XX_TEX_2D = 1, 580 A3XX_TEX_CUBE = 2, 581 A3XX_TEX_3D = 3, 582 }; 583 584 enum a3xx_tex_msaa { 585 A3XX_TPL1_MSAA1X = 0, 586 A3XX_TPL1_MSAA2X = 1, 587 A3XX_TPL1_MSAA4X = 2, 588 A3XX_TPL1_MSAA8X = 3, 589 }; 590 591 #define A3XX_INT0_RBBM_GPU_IDLE 0x00000001 592 #define A3XX_INT0_RBBM_AHB_ERROR 0x00000002 593 #define A3XX_INT0_RBBM_REG_TIMEOUT 0x00000004 594 #define A3XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 595 #define A3XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 596 #define A3XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020 597 #define A3XX_INT0_VFD_ERROR 0x00000040 598 #define A3XX_INT0_CP_SW_INT 0x00000080 599 #define A3XX_INT0_CP_T0_PACKET_IN_IB 0x00000100 600 #define A3XX_INT0_CP_OPCODE_ERROR 0x00000200 601 #define A3XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400 602 #define A3XX_INT0_CP_HW_FAULT 0x00000800 603 #define A3XX_INT0_CP_DMA 0x00001000 604 #define A3XX_INT0_CP_IB2_INT 0x00002000 605 #define A3XX_INT0_CP_IB1_INT 0x00004000 606 #define A3XX_INT0_CP_RB_INT 0x00008000 607 #define A3XX_INT0_CP_REG_PROTECT_FAULT 0x00010000 608 #define A3XX_INT0_CP_RB_DONE_TS 0x00020000 609 #define A3XX_INT0_CP_VS_DONE_TS 0x00040000 610 #define A3XX_INT0_CP_PS_DONE_TS 0x00080000 611 #define A3XX_INT0_CACHE_FLUSH_TS 0x00100000 612 #define A3XX_INT0_CP_AHB_ERROR_HALT 0x00200000 613 #define A3XX_INT0_MISC_HANG_DETECT 0x01000000 614 #define A3XX_INT0_UCHE_OOB_ACCESS 0x02000000 615 #define REG_A3XX_RBBM_HW_VERSION 0x00000000 616 617 #define REG_A3XX_RBBM_HW_RELEASE 0x00000001 618 619 #define REG_A3XX_RBBM_HW_CONFIGURATION 0x00000002 620 621 #define REG_A3XX_RBBM_CLOCK_CTL 0x00000010 622 623 #define REG_A3XX_RBBM_SP_HYST_CNT 0x00000012 624 625 #define REG_A3XX_RBBM_SW_RESET_CMD 0x00000018 626 627 #define REG_A3XX_RBBM_AHB_CTL0 0x00000020 628 629 #define REG_A3XX_RBBM_AHB_CTL1 0x00000021 630 631 #define REG_A3XX_RBBM_AHB_CMD 0x00000022 632 633 #define REG_A3XX_RBBM_AHB_ERROR_STATUS 0x00000027 634 635 #define REG_A3XX_RBBM_GPR0_CTL 0x0000002e 636 637 #define REG_A3XX_RBBM_STATUS 0x00000030 638 #define A3XX_RBBM_STATUS_HI_BUSY 0x00000001 639 #define A3XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 640 #define A3XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 641 #define A3XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000 642 #define A3XX_RBBM_STATUS_VBIF_BUSY 0x00008000 643 #define A3XX_RBBM_STATUS_TSE_BUSY 0x00010000 644 #define A3XX_RBBM_STATUS_RAS_BUSY 0x00020000 645 #define A3XX_RBBM_STATUS_RB_BUSY 0x00040000 646 #define A3XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 647 #define A3XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 648 #define A3XX_RBBM_STATUS_VFD_BUSY 0x00200000 649 #define A3XX_RBBM_STATUS_VPC_BUSY 0x00400000 650 #define A3XX_RBBM_STATUS_UCHE_BUSY 0x00800000 651 #define A3XX_RBBM_STATUS_SP_BUSY 0x01000000 652 #define A3XX_RBBM_STATUS_TPL1_BUSY 0x02000000 653 #define A3XX_RBBM_STATUS_MARB_BUSY 0x04000000 654 #define A3XX_RBBM_STATUS_VSC_BUSY 0x08000000 655 #define A3XX_RBBM_STATUS_ARB_BUSY 0x10000000 656 #define A3XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 657 #define A3XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000 658 #define A3XX_RBBM_STATUS_GPU_BUSY 0x80000000 659 660 #define REG_A3XX_RBBM_NQWAIT_UNTIL 0x00000040 661 662 #define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x00000033 663 664 #define REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL 0x00000050 665 666 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL0 0x00000051 667 668 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL1 0x00000054 669 670 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL2 0x00000057 671 672 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3 0x0000005a 673 674 #define REG_A3XX_RBBM_INT_SET_CMD 0x00000060 675 676 #define REG_A3XX_RBBM_INT_CLEAR_CMD 0x00000061 677 678 #define REG_A3XX_RBBM_INT_0_MASK 0x00000063 679 680 #define REG_A3XX_RBBM_INT_0_STATUS 0x00000064 681 682 #define REG_A3XX_RBBM_PERFCTR_CTL 0x00000080 683 #define A3XX_RBBM_PERFCTR_CTL_ENABLE 0x00000001 684 685 #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0 0x00000081 686 687 #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD1 0x00000082 688 689 #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000084 690 691 #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000085 692 693 #define REG_A3XX_RBBM_PERFCOUNTER0_SELECT 0x00000086 694 695 #define REG_A3XX_RBBM_PERFCOUNTER1_SELECT 0x00000087 696 697 #define REG_A3XX_RBBM_GPU_BUSY_MASKED 0x00000088 698 699 #define REG_A3XX_RBBM_PERFCTR_CP_0_LO 0x00000090 700 701 #define REG_A3XX_RBBM_PERFCTR_CP_0_HI 0x00000091 702 703 #define REG_A3XX_RBBM_PERFCTR_RBBM_0_LO 0x00000092 704 705 #define REG_A3XX_RBBM_PERFCTR_RBBM_0_HI 0x00000093 706 707 #define REG_A3XX_RBBM_PERFCTR_RBBM_1_LO 0x00000094 708 709 #define REG_A3XX_RBBM_PERFCTR_RBBM_1_HI 0x00000095 710 711 #define REG_A3XX_RBBM_PERFCTR_PC_0_LO 0x00000096 712 713 #define REG_A3XX_RBBM_PERFCTR_PC_0_HI 0x00000097 714 715 #define REG_A3XX_RBBM_PERFCTR_PC_1_LO 0x00000098 716 717 #define REG_A3XX_RBBM_PERFCTR_PC_1_HI 0x00000099 718 719 #define REG_A3XX_RBBM_PERFCTR_PC_2_LO 0x0000009a 720 721 #define REG_A3XX_RBBM_PERFCTR_PC_2_HI 0x0000009b 722 723 #define REG_A3XX_RBBM_PERFCTR_PC_3_LO 0x0000009c 724 725 #define REG_A3XX_RBBM_PERFCTR_PC_3_HI 0x0000009d 726 727 #define REG_A3XX_RBBM_PERFCTR_VFD_0_LO 0x0000009e 728 729 #define REG_A3XX_RBBM_PERFCTR_VFD_0_HI 0x0000009f 730 731 #define REG_A3XX_RBBM_PERFCTR_VFD_1_LO 0x000000a0 732 733 #define REG_A3XX_RBBM_PERFCTR_VFD_1_HI 0x000000a1 734 735 #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000a2 736 737 #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000a3 738 739 #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000a4 740 741 #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000a5 742 743 #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000a6 744 745 #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000a7 746 747 #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000a8 748 749 #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000a9 750 751 #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000aa 752 753 #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000ab 754 755 #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000ac 756 757 #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000ad 758 759 #define REG_A3XX_RBBM_PERFCTR_VPC_0_LO 0x000000ae 760 761 #define REG_A3XX_RBBM_PERFCTR_VPC_0_HI 0x000000af 762 763 #define REG_A3XX_RBBM_PERFCTR_VPC_1_LO 0x000000b0 764 765 #define REG_A3XX_RBBM_PERFCTR_VPC_1_HI 0x000000b1 766 767 #define REG_A3XX_RBBM_PERFCTR_TSE_0_LO 0x000000b2 768 769 #define REG_A3XX_RBBM_PERFCTR_TSE_0_HI 0x000000b3 770 771 #define REG_A3XX_RBBM_PERFCTR_TSE_1_LO 0x000000b4 772 773 #define REG_A3XX_RBBM_PERFCTR_TSE_1_HI 0x000000b5 774 775 #define REG_A3XX_RBBM_PERFCTR_RAS_0_LO 0x000000b6 776 777 #define REG_A3XX_RBBM_PERFCTR_RAS_0_HI 0x000000b7 778 779 #define REG_A3XX_RBBM_PERFCTR_RAS_1_LO 0x000000b8 780 781 #define REG_A3XX_RBBM_PERFCTR_RAS_1_HI 0x000000b9 782 783 #define REG_A3XX_RBBM_PERFCTR_UCHE_0_LO 0x000000ba 784 785 #define REG_A3XX_RBBM_PERFCTR_UCHE_0_HI 0x000000bb 786 787 #define REG_A3XX_RBBM_PERFCTR_UCHE_1_LO 0x000000bc 788 789 #define REG_A3XX_RBBM_PERFCTR_UCHE_1_HI 0x000000bd 790 791 #define REG_A3XX_RBBM_PERFCTR_UCHE_2_LO 0x000000be 792 793 #define REG_A3XX_RBBM_PERFCTR_UCHE_2_HI 0x000000bf 794 795 #define REG_A3XX_RBBM_PERFCTR_UCHE_3_LO 0x000000c0 796 797 #define REG_A3XX_RBBM_PERFCTR_UCHE_3_HI 0x000000c1 798 799 #define REG_A3XX_RBBM_PERFCTR_UCHE_4_LO 0x000000c2 800 801 #define REG_A3XX_RBBM_PERFCTR_UCHE_4_HI 0x000000c3 802 803 #define REG_A3XX_RBBM_PERFCTR_UCHE_5_LO 0x000000c4 804 805 #define REG_A3XX_RBBM_PERFCTR_UCHE_5_HI 0x000000c5 806 807 #define REG_A3XX_RBBM_PERFCTR_TP_0_LO 0x000000c6 808 809 #define REG_A3XX_RBBM_PERFCTR_TP_0_HI 0x000000c7 810 811 #define REG_A3XX_RBBM_PERFCTR_TP_1_LO 0x000000c8 812 813 #define REG_A3XX_RBBM_PERFCTR_TP_1_HI 0x000000c9 814 815 #define REG_A3XX_RBBM_PERFCTR_TP_2_LO 0x000000ca 816 817 #define REG_A3XX_RBBM_PERFCTR_TP_2_HI 0x000000cb 818 819 #define REG_A3XX_RBBM_PERFCTR_TP_3_LO 0x000000cc 820 821 #define REG_A3XX_RBBM_PERFCTR_TP_3_HI 0x000000cd 822 823 #define REG_A3XX_RBBM_PERFCTR_TP_4_LO 0x000000ce 824 825 #define REG_A3XX_RBBM_PERFCTR_TP_4_HI 0x000000cf 826 827 #define REG_A3XX_RBBM_PERFCTR_TP_5_LO 0x000000d0 828 829 #define REG_A3XX_RBBM_PERFCTR_TP_5_HI 0x000000d1 830 831 #define REG_A3XX_RBBM_PERFCTR_SP_0_LO 0x000000d2 832 833 #define REG_A3XX_RBBM_PERFCTR_SP_0_HI 0x000000d3 834 835 #define REG_A3XX_RBBM_PERFCTR_SP_1_LO 0x000000d4 836 837 #define REG_A3XX_RBBM_PERFCTR_SP_1_HI 0x000000d5 838 839 #define REG_A3XX_RBBM_PERFCTR_SP_2_LO 0x000000d6 840 841 #define REG_A3XX_RBBM_PERFCTR_SP_2_HI 0x000000d7 842 843 #define REG_A3XX_RBBM_PERFCTR_SP_3_LO 0x000000d8 844 845 #define REG_A3XX_RBBM_PERFCTR_SP_3_HI 0x000000d9 846 847 #define REG_A3XX_RBBM_PERFCTR_SP_4_LO 0x000000da 848 849 #define REG_A3XX_RBBM_PERFCTR_SP_4_HI 0x000000db 850 851 #define REG_A3XX_RBBM_PERFCTR_SP_5_LO 0x000000dc 852 853 #define REG_A3XX_RBBM_PERFCTR_SP_5_HI 0x000000dd 854 855 #define REG_A3XX_RBBM_PERFCTR_SP_6_LO 0x000000de 856 857 #define REG_A3XX_RBBM_PERFCTR_SP_6_HI 0x000000df 858 859 #define REG_A3XX_RBBM_PERFCTR_SP_7_LO 0x000000e0 860 861 #define REG_A3XX_RBBM_PERFCTR_SP_7_HI 0x000000e1 862 863 #define REG_A3XX_RBBM_PERFCTR_RB_0_LO 0x000000e2 864 865 #define REG_A3XX_RBBM_PERFCTR_RB_0_HI 0x000000e3 866 867 #define REG_A3XX_RBBM_PERFCTR_RB_1_LO 0x000000e4 868 869 #define REG_A3XX_RBBM_PERFCTR_RB_1_HI 0x000000e5 870 871 #define REG_A3XX_RBBM_PERFCTR_PWR_0_LO 0x000000ea 872 873 #define REG_A3XX_RBBM_PERFCTR_PWR_0_HI 0x000000eb 874 875 #define REG_A3XX_RBBM_PERFCTR_PWR_1_LO 0x000000ec 876 877 #define REG_A3XX_RBBM_PERFCTR_PWR_1_HI 0x000000ed 878 879 #define REG_A3XX_RBBM_RBBM_CTL 0x00000100 880 881 #define REG_A3XX_RBBM_DEBUG_BUS_CTL 0x00000111 882 883 #define REG_A3XX_RBBM_DEBUG_BUS_DATA_STATUS 0x00000112 884 885 #define REG_A3XX_CP_PFP_UCODE_ADDR 0x000001c9 886 887 #define REG_A3XX_CP_PFP_UCODE_DATA 0x000001ca 888 889 #define REG_A3XX_CP_ROQ_ADDR 0x000001cc 890 891 #define REG_A3XX_CP_ROQ_DATA 0x000001cd 892 893 #define REG_A3XX_CP_MERCIU_ADDR 0x000001d1 894 895 #define REG_A3XX_CP_MERCIU_DATA 0x000001d2 896 897 #define REG_A3XX_CP_MERCIU_DATA2 0x000001d3 898 899 #define REG_A3XX_CP_MEQ_ADDR 0x000001da 900 901 #define REG_A3XX_CP_MEQ_DATA 0x000001db 902 903 #define REG_A3XX_CP_WFI_PEND_CTR 0x000001f5 904 905 #define REG_A3XX_RBBM_PM_OVERRIDE2 0x0000039d 906 907 #define REG_A3XX_CP_PERFCOUNTER_SELECT 0x00000445 908 909 #define REG_A3XX_CP_HW_FAULT 0x0000045c 910 911 #define REG_A3XX_CP_PROTECT_CTRL 0x0000045e 912 913 #define REG_A3XX_CP_PROTECT_STATUS 0x0000045f 914 915 static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; } 916 917 static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; } 918 919 #define REG_A3XX_CP_AHB_FAULT 0x0000054d 920 921 #define REG_A3XX_SQ_GPR_MANAGEMENT 0x00000d00 922 923 #define REG_A3XX_SQ_INST_STORE_MANAGMENT 0x00000d02 924 925 #define REG_A3XX_TP0_CHICKEN 0x00000e1e 926 927 #define REG_A3XX_SP_GLOBAL_MEM_SIZE 0x00000e22 928 929 #define REG_A3XX_SP_GLOBAL_MEM_ADDR 0x00000e23 930 931 #define REG_A3XX_GRAS_CL_CLIP_CNTL 0x00002040 932 #define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER 0x00001000 933 #define A3XX_GRAS_CL_CLIP_CNTL_IJ_NON_PERSP_CENTER 0x00002000 934 #define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTROID 0x00004000 935 #define A3XX_GRAS_CL_CLIP_CNTL_IJ_NON_PERSP_CENTROID 0x00008000 936 #define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 937 #define A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000 938 #define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE 0x00080000 939 #define A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE 0x00100000 940 #define A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE 0x00200000 941 #define A3XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000 942 #define A3XX_GRAS_CL_CLIP_CNTL_ZCOORD 0x00800000 943 #define A3XX_GRAS_CL_CLIP_CNTL_WCOORD 0x01000000 944 #define A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE 0x02000000 945 #define A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK 0x1c000000 946 #define A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT 26 947 static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val) 948 { 949 return ((val) << A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT) & A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK; 950 } 951 952 #define REG_A3XX_GRAS_CL_GB_CLIP_ADJ 0x00002044 953 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff 954 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0 955 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) 956 { 957 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; 958 } 959 #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00 960 #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10 961 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) 962 { 963 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; 964 } 965 966 #define REG_A3XX_GRAS_CL_VPORT_XOFFSET 0x00002048 967 #define A3XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff 968 #define A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0 969 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) 970 { 971 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK; 972 } 973 974 #define REG_A3XX_GRAS_CL_VPORT_XSCALE 0x00002049 975 #define A3XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff 976 #define A3XX_GRAS_CL_VPORT_XSCALE__SHIFT 0 977 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) 978 { 979 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK; 980 } 981 982 #define REG_A3XX_GRAS_CL_VPORT_YOFFSET 0x0000204a 983 #define A3XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff 984 #define A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0 985 static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val) 986 { 987 return ((fui(val)) << A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_YOFFSET__MASK; 988 } 989 990 #define REG_A3XX_GRAS_CL_VPORT_YSCALE 0x0000204b 991 #define A3XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff 992 #define A3XX_GRAS_CL_VPORT_YSCALE__SHIFT 0 993 static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val) 994 { 995 return ((fui(val)) << A3XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_YSCALE__MASK; 996 } 997 998 #define REG_A3XX_GRAS_CL_VPORT_ZOFFSET 0x0000204c 999 #define A3XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff 1000 #define A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0 1001 static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val) 1002 { 1003 return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_ZOFFSET__MASK; 1004 } 1005 1006 #define REG_A3XX_GRAS_CL_VPORT_ZSCALE 0x0000204d 1007 #define A3XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff 1008 #define A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0 1009 static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val) 1010 { 1011 return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_ZSCALE__MASK; 1012 } 1013 1014 #define REG_A3XX_GRAS_SU_POINT_MINMAX 0x00002068 1015 #define A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 1016 #define A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 1017 static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MIN(float val) 1018 { 1019 return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 1020 } 1021 #define A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 1022 #define A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 1023 static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MAX(float val) 1024 { 1025 return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 1026 } 1027 1028 #define REG_A3XX_GRAS_SU_POINT_SIZE 0x00002069 1029 #define A3XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff 1030 #define A3XX_GRAS_SU_POINT_SIZE__SHIFT 0 1031 static inline uint32_t A3XX_GRAS_SU_POINT_SIZE(float val) 1032 { 1033 return ((((int32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_SIZE__SHIFT) & A3XX_GRAS_SU_POINT_SIZE__MASK; 1034 } 1035 1036 #define REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000206c 1037 #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK 0x00ffffff 1038 #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT 0 1039 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val) 1040 { 1041 return ((((int32_t)(val * 1048576.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK; 1042 } 1043 1044 #define REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000206d 1045 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 1046 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 1047 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 1048 { 1049 return ((((int32_t)(val * 64.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 1050 } 1051 1052 #define REG_A3XX_GRAS_SU_MODE_CONTROL 0x00002070 1053 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001 1054 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002 1055 #define A3XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004 1056 #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8 1057 #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3 1058 static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) 1059 { 1060 return ((((int32_t)(val * 4.0))) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; 1061 } 1062 #define A3XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800 1063 1064 #define REG_A3XX_GRAS_SC_CONTROL 0x00002072 1065 #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x000000f0 1066 #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 4 1067 static inline uint32_t A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) 1068 { 1069 return ((val) << A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK; 1070 } 1071 #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000f00 1072 #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 8 1073 static inline uint32_t A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val) 1074 { 1075 return ((val) << A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK; 1076 } 1077 #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000 1078 #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12 1079 static inline uint32_t A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) 1080 { 1081 return ((val) << A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK; 1082 } 1083 1084 #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL 0x00002074 1085 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 1086 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 1087 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 1088 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 1089 { 1090 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; 1091 } 1092 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 1093 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 1094 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 1095 { 1096 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; 1097 } 1098 1099 #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_BR 0x00002075 1100 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 1101 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 1102 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 1103 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 1104 { 1105 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; 1106 } 1107 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 1108 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 1109 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 1110 { 1111 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; 1112 } 1113 1114 #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL 0x00002079 1115 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 1116 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 1117 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 1118 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 1119 { 1120 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 1121 } 1122 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 1123 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 1124 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 1125 { 1126 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 1127 } 1128 1129 #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000207a 1130 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 1131 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 1132 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 1133 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 1134 { 1135 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 1136 } 1137 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 1138 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 1139 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 1140 { 1141 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 1142 } 1143 1144 #define REG_A3XX_RB_MODE_CONTROL 0x000020c0 1145 #define A3XX_RB_MODE_CONTROL_GMEM_BYPASS 0x00000080 1146 #define A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK 0x00000700 1147 #define A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT 8 1148 static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val) 1149 { 1150 return ((val) << A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT) & A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK; 1151 } 1152 #define A3XX_RB_MODE_CONTROL_MRT__MASK 0x00003000 1153 #define A3XX_RB_MODE_CONTROL_MRT__SHIFT 12 1154 static inline uint32_t A3XX_RB_MODE_CONTROL_MRT(uint32_t val) 1155 { 1156 return ((val) << A3XX_RB_MODE_CONTROL_MRT__SHIFT) & A3XX_RB_MODE_CONTROL_MRT__MASK; 1157 } 1158 #define A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE 0x00008000 1159 #define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE 0x00010000 1160 1161 #define REG_A3XX_RB_RENDER_CONTROL 0x000020c1 1162 #define A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE 0x00000001 1163 #define A3XX_RB_RENDER_CONTROL_YUV_IN_ENABLE 0x00000002 1164 #define A3XX_RB_RENDER_CONTROL_COV_VALUE_INPUT_ENABLE 0x00000004 1165 #define A3XX_RB_RENDER_CONTROL_FACENESS 0x00000008 1166 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK 0x00000ff0 1167 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT 4 1168 static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val) 1169 { 1170 return ((val >> 5) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK; 1171 } 1172 #define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00001000 1173 #define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM 0x00002000 1174 #define A3XX_RB_RENDER_CONTROL_COORD_MASK__MASK 0x0003c000 1175 #define A3XX_RB_RENDER_CONTROL_COORD_MASK__SHIFT 14 1176 static inline uint32_t A3XX_RB_RENDER_CONTROL_COORD_MASK(uint32_t val) 1177 { 1178 return ((val) << A3XX_RB_RENDER_CONTROL_COORD_MASK__SHIFT) & A3XX_RB_RENDER_CONTROL_COORD_MASK__MASK; 1179 } 1180 #define A3XX_RB_RENDER_CONTROL_I_CLAMP_ENABLE 0x00080000 1181 #define A3XX_RB_RENDER_CONTROL_COV_VALUE_OUTPUT_ENABLE 0x00100000 1182 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST 0x00400000 1183 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK 0x07000000 1184 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT 24 1185 static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 1186 { 1187 return ((val) << A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK; 1188 } 1189 #define A3XX_RB_RENDER_CONTROL_ALPHA_TO_COVERAGE 0x40000000 1190 #define A3XX_RB_RENDER_CONTROL_ALPHA_TO_ONE 0x80000000 1191 1192 #define REG_A3XX_RB_MSAA_CONTROL 0x000020c2 1193 #define A3XX_RB_MSAA_CONTROL_DISABLE 0x00000400 1194 #define A3XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000f000 1195 #define A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 12 1196 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val) 1197 { 1198 return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLES__MASK; 1199 } 1200 #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK 0xffff0000 1201 #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT 16 1202 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val) 1203 { 1204 return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK; 1205 } 1206 1207 #define REG_A3XX_RB_ALPHA_REF 0x000020c3 1208 #define A3XX_RB_ALPHA_REF_UINT__MASK 0x0000ff00 1209 #define A3XX_RB_ALPHA_REF_UINT__SHIFT 8 1210 static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val) 1211 { 1212 return ((val) << A3XX_RB_ALPHA_REF_UINT__SHIFT) & A3XX_RB_ALPHA_REF_UINT__MASK; 1213 } 1214 #define A3XX_RB_ALPHA_REF_FLOAT__MASK 0xffff0000 1215 #define A3XX_RB_ALPHA_REF_FLOAT__SHIFT 16 1216 static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val) 1217 { 1218 return ((_mesa_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK; 1219 } 1220 1221 static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; } 1222 1223 static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; } 1224 #define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008 1225 #define A3XX_RB_MRT_CONTROL_BLEND 0x00000010 1226 #define A3XX_RB_MRT_CONTROL_BLEND2 0x00000020 1227 #define A3XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00 1228 #define A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8 1229 static inline uint32_t A3XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) 1230 { 1231 return ((val) << A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A3XX_RB_MRT_CONTROL_ROP_CODE__MASK; 1232 } 1233 #define A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK 0x00003000 1234 #define A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT 12 1235 static inline uint32_t A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) 1236 { 1237 return ((val) << A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT) & A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK; 1238 } 1239 #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000 1240 #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24 1241 static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 1242 { 1243 return ((val) << A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 1244 } 1245 1246 static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; } 1247 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f 1248 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 1249 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val) 1250 { 1251 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 1252 } 1253 #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0 1254 #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6 1255 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val) 1256 { 1257 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 1258 } 1259 #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00000c00 1260 #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 10 1261 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 1262 { 1263 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 1264 } 1265 #define A3XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00004000 1266 #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xfffe0000 1267 #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 17 1268 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) 1269 { 1270 return ((val >> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; 1271 } 1272 1273 static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; } 1274 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK 0xfffffff0 1275 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT 4 1276 static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val) 1277 { 1278 return ((val >> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK; 1279 } 1280 1281 static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; } 1282 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 1283 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 1284 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 1285 { 1286 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 1287 } 1288 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 1289 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 1290 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 1291 { 1292 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 1293 } 1294 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 1295 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 1296 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 1297 { 1298 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 1299 } 1300 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 1301 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 1302 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 1303 { 1304 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 1305 } 1306 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 1307 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 1308 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 1309 { 1310 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 1311 } 1312 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 1313 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 1314 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 1315 { 1316 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 1317 } 1318 #define A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE 0x20000000 1319 1320 #define REG_A3XX_RB_BLEND_RED 0x000020e4 1321 #define A3XX_RB_BLEND_RED_UINT__MASK 0x000000ff 1322 #define A3XX_RB_BLEND_RED_UINT__SHIFT 0 1323 static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val) 1324 { 1325 return ((val) << A3XX_RB_BLEND_RED_UINT__SHIFT) & A3XX_RB_BLEND_RED_UINT__MASK; 1326 } 1327 #define A3XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 1328 #define A3XX_RB_BLEND_RED_FLOAT__SHIFT 16 1329 static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val) 1330 { 1331 return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK; 1332 } 1333 1334 #define REG_A3XX_RB_BLEND_GREEN 0x000020e5 1335 #define A3XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff 1336 #define A3XX_RB_BLEND_GREEN_UINT__SHIFT 0 1337 static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val) 1338 { 1339 return ((val) << A3XX_RB_BLEND_GREEN_UINT__SHIFT) & A3XX_RB_BLEND_GREEN_UINT__MASK; 1340 } 1341 #define A3XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 1342 #define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 1343 static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val) 1344 { 1345 return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK; 1346 } 1347 1348 #define REG_A3XX_RB_BLEND_BLUE 0x000020e6 1349 #define A3XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff 1350 #define A3XX_RB_BLEND_BLUE_UINT__SHIFT 0 1351 static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val) 1352 { 1353 return ((val) << A3XX_RB_BLEND_BLUE_UINT__SHIFT) & A3XX_RB_BLEND_BLUE_UINT__MASK; 1354 } 1355 #define A3XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 1356 #define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 1357 static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val) 1358 { 1359 return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK; 1360 } 1361 1362 #define REG_A3XX_RB_BLEND_ALPHA 0x000020e7 1363 #define A3XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff 1364 #define A3XX_RB_BLEND_ALPHA_UINT__SHIFT 0 1365 static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val) 1366 { 1367 return ((val) << A3XX_RB_BLEND_ALPHA_UINT__SHIFT) & A3XX_RB_BLEND_ALPHA_UINT__MASK; 1368 } 1369 #define A3XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 1370 #define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 1371 static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val) 1372 { 1373 return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK; 1374 } 1375 1376 #define REG_A3XX_RB_CLEAR_COLOR_DW0 0x000020e8 1377 1378 #define REG_A3XX_RB_CLEAR_COLOR_DW1 0x000020e9 1379 1380 #define REG_A3XX_RB_CLEAR_COLOR_DW2 0x000020ea 1381 1382 #define REG_A3XX_RB_CLEAR_COLOR_DW3 0x000020eb 1383 1384 #define REG_A3XX_RB_COPY_CONTROL 0x000020ec 1385 #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003 1386 #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0 1387 static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) 1388 { 1389 return ((val) << A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK; 1390 } 1391 #define A3XX_RB_COPY_CONTROL_DEPTHCLEAR 0x00000008 1392 #define A3XX_RB_COPY_CONTROL_MODE__MASK 0x00000070 1393 #define A3XX_RB_COPY_CONTROL_MODE__SHIFT 4 1394 static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) 1395 { 1396 return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK; 1397 } 1398 #define A3XX_RB_COPY_CONTROL_MSAA_SRGB_DOWNSAMPLE 0x00000080 1399 #define A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00 1400 #define A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8 1401 static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) 1402 { 1403 return ((val) << A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK; 1404 } 1405 #define A3XX_RB_COPY_CONTROL_DEPTH32_RESOLVE 0x00001000 1406 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000 1407 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14 1408 static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) 1409 { 1410 return ((val >> 14) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK; 1411 } 1412 1413 #define REG_A3XX_RB_COPY_DEST_BASE 0x000020ed 1414 #define A3XX_RB_COPY_DEST_BASE_BASE__MASK 0xfffffff0 1415 #define A3XX_RB_COPY_DEST_BASE_BASE__SHIFT 4 1416 static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val) 1417 { 1418 return ((val >> 5) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A3XX_RB_COPY_DEST_BASE_BASE__MASK; 1419 } 1420 1421 #define REG_A3XX_RB_COPY_DEST_PITCH 0x000020ee 1422 #define A3XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff 1423 #define A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0 1424 static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) 1425 { 1426 return ((val >> 5) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK; 1427 } 1428 1429 #define REG_A3XX_RB_COPY_DEST_INFO 0x000020ef 1430 #define A3XX_RB_COPY_DEST_INFO_TILE__MASK 0x00000003 1431 #define A3XX_RB_COPY_DEST_INFO_TILE__SHIFT 0 1432 static inline uint32_t A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val) 1433 { 1434 return ((val) << A3XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A3XX_RB_COPY_DEST_INFO_TILE__MASK; 1435 } 1436 #define A3XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc 1437 #define A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2 1438 static inline uint32_t A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val) 1439 { 1440 return ((val) << A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A3XX_RB_COPY_DEST_INFO_FORMAT__MASK; 1441 } 1442 #define A3XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 1443 #define A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 1444 static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) 1445 { 1446 return ((val) << A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A3XX_RB_COPY_DEST_INFO_SWAP__MASK; 1447 } 1448 #define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 1449 #define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 1450 static inline uint32_t A3XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 1451 { 1452 return ((val) << A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 1453 } 1454 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000 1455 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14 1456 static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) 1457 { 1458 return ((val) << A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK; 1459 } 1460 #define A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000 1461 #define A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18 1462 static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) 1463 { 1464 return ((val) << A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK; 1465 } 1466 1467 #define REG_A3XX_RB_DEPTH_CONTROL 0x00002100 1468 #define A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001 1469 #define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x00000002 1470 #define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004 1471 #define A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00000008 1472 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070 1473 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4 1474 static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) 1475 { 1476 return ((val) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK; 1477 } 1478 #define A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE 0x00000080 1479 #define A3XX_RB_DEPTH_CONTROL_Z_READ_ENABLE 0x80000000 1480 1481 #define REG_A3XX_RB_DEPTH_CLEAR 0x00002101 1482 1483 #define REG_A3XX_RB_DEPTH_INFO 0x00002102 1484 #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003 1485 #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 1486 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) 1487 { 1488 return ((val) << A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 1489 } 1490 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff800 1491 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 11 1492 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 1493 { 1494 return ((val >> 12) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 1495 } 1496 1497 #define REG_A3XX_RB_DEPTH_PITCH 0x00002103 1498 #define A3XX_RB_DEPTH_PITCH__MASK 0xffffffff 1499 #define A3XX_RB_DEPTH_PITCH__SHIFT 0 1500 static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val) 1501 { 1502 return ((val >> 3) << A3XX_RB_DEPTH_PITCH__SHIFT) & A3XX_RB_DEPTH_PITCH__MASK; 1503 } 1504 1505 #define REG_A3XX_RB_STENCIL_CONTROL 0x00002104 1506 #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 1507 #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 1508 #define A3XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 1509 #define A3XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 1510 #define A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 1511 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 1512 { 1513 return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC__MASK; 1514 } 1515 #define A3XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 1516 #define A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 1517 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 1518 { 1519 return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL__MASK; 1520 } 1521 #define A3XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 1522 #define A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 1523 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 1524 { 1525 return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS__MASK; 1526 } 1527 #define A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 1528 #define A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 1529 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 1530 { 1531 return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 1532 } 1533 #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 1534 #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 1535 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 1536 { 1537 return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 1538 } 1539 #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 1540 #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 1541 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 1542 { 1543 return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 1544 } 1545 #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 1546 #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 1547 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 1548 { 1549 return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 1550 } 1551 #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 1552 #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 1553 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 1554 { 1555 return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 1556 } 1557 1558 #define REG_A3XX_RB_STENCIL_CLEAR 0x00002105 1559 1560 #define REG_A3XX_RB_STENCIL_INFO 0x00002106 1561 #define A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff800 1562 #define A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 11 1563 static inline uint32_t A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) 1564 { 1565 return ((val >> 12) << A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK; 1566 } 1567 1568 #define REG_A3XX_RB_STENCIL_PITCH 0x00002107 1569 #define A3XX_RB_STENCIL_PITCH__MASK 0xffffffff 1570 #define A3XX_RB_STENCIL_PITCH__SHIFT 0 1571 static inline uint32_t A3XX_RB_STENCIL_PITCH(uint32_t val) 1572 { 1573 return ((val >> 3) << A3XX_RB_STENCIL_PITCH__SHIFT) & A3XX_RB_STENCIL_PITCH__MASK; 1574 } 1575 1576 #define REG_A3XX_RB_STENCILREFMASK 0x00002108 1577 #define A3XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 1578 #define A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 1579 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 1580 { 1581 return ((val) << A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILREF__MASK; 1582 } 1583 #define A3XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 1584 #define A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 1585 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 1586 { 1587 return ((val) << A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILMASK__MASK; 1588 } 1589 #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 1590 #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 1591 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 1592 { 1593 return ((val) << A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 1594 } 1595 1596 #define REG_A3XX_RB_STENCILREFMASK_BF 0x00002109 1597 #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 1598 #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 1599 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 1600 { 1601 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 1602 } 1603 #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 1604 #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 1605 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 1606 { 1607 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 1608 } 1609 #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 1610 #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 1611 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 1612 { 1613 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 1614 } 1615 1616 #define REG_A3XX_RB_LRZ_VSC_CONTROL 0x0000210c 1617 #define A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE 0x00000002 1618 1619 #define REG_A3XX_RB_WINDOW_OFFSET 0x0000210e 1620 #define A3XX_RB_WINDOW_OFFSET_X__MASK 0x0000ffff 1621 #define A3XX_RB_WINDOW_OFFSET_X__SHIFT 0 1622 static inline uint32_t A3XX_RB_WINDOW_OFFSET_X(uint32_t val) 1623 { 1624 return ((val) << A3XX_RB_WINDOW_OFFSET_X__SHIFT) & A3XX_RB_WINDOW_OFFSET_X__MASK; 1625 } 1626 #define A3XX_RB_WINDOW_OFFSET_Y__MASK 0xffff0000 1627 #define A3XX_RB_WINDOW_OFFSET_Y__SHIFT 16 1628 static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val) 1629 { 1630 return ((val) << A3XX_RB_WINDOW_OFFSET_Y__SHIFT) & A3XX_RB_WINDOW_OFFSET_Y__MASK; 1631 } 1632 1633 #define REG_A3XX_RB_SAMPLE_COUNT_CONTROL 0x00002110 1634 #define A3XX_RB_SAMPLE_COUNT_CONTROL_RESET 0x00000001 1635 #define A3XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 1636 1637 #define REG_A3XX_RB_SAMPLE_COUNT_ADDR 0x00002111 1638 1639 #define REG_A3XX_RB_Z_CLAMP_MIN 0x00002114 1640 1641 #define REG_A3XX_RB_Z_CLAMP_MAX 0x00002115 1642 1643 #define REG_A3XX_VGT_BIN_BASE 0x000021e1 1644 1645 #define REG_A3XX_VGT_BIN_SIZE 0x000021e2 1646 1647 #define REG_A3XX_PC_VSTREAM_CONTROL 0x000021e4 1648 #define A3XX_PC_VSTREAM_CONTROL_SIZE__MASK 0x003f0000 1649 #define A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT 16 1650 static inline uint32_t A3XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val) 1651 { 1652 return ((val) << A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A3XX_PC_VSTREAM_CONTROL_SIZE__MASK; 1653 } 1654 #define A3XX_PC_VSTREAM_CONTROL_N__MASK 0x07c00000 1655 #define A3XX_PC_VSTREAM_CONTROL_N__SHIFT 22 1656 static inline uint32_t A3XX_PC_VSTREAM_CONTROL_N(uint32_t val) 1657 { 1658 return ((val) << A3XX_PC_VSTREAM_CONTROL_N__SHIFT) & A3XX_PC_VSTREAM_CONTROL_N__MASK; 1659 } 1660 1661 #define REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL 0x000021ea 1662 1663 #define REG_A3XX_PC_PRIM_VTX_CNTL 0x000021ec 1664 #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK 0x0000001f 1665 #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT 0 1666 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val) 1667 { 1668 return ((val) << A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK; 1669 } 1670 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK 0x000000e0 1671 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT 5 1672 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 1673 { 1674 return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK; 1675 } 1676 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK 0x00000700 1677 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT 8 1678 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 1679 { 1680 return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK; 1681 } 1682 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_ENABLE 0x00001000 1683 #define A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000 1684 #define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000 1685 #define A3XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000 1686 1687 #define REG_A3XX_PC_RESTART_INDEX 0x000021ed 1688 1689 #define REG_A3XX_HLSQ_CONTROL_0_REG 0x00002200 1690 #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000030 1691 #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4 1692 static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) 1693 { 1694 return ((val) << A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; 1695 } 1696 #define A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040 1697 #define A3XX_HLSQ_CONTROL_0_REG_COMPUTEMODE 0x00000100 1698 #define A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200 1699 #define A3XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400 1700 #define A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__MASK 0x00fff000 1701 #define A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__SHIFT 12 1702 static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC(uint32_t val) 1703 { 1704 return ((val) << A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__MASK; 1705 } 1706 #define A3XX_HLSQ_CONTROL_0_REG_FSONLYTEX 0x02000000 1707 #define A3XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000 1708 #define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000 1709 #define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27 1710 static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) 1711 { 1712 return ((val) << A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK; 1713 } 1714 #define A3XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000 1715 #define A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000 1716 #define A3XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000 1717 #define A3XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000 1718 1719 #define REG_A3XX_HLSQ_CONTROL_1_REG 0x00002201 1720 #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x000000c0 1721 #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6 1722 static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) 1723 { 1724 return ((val) << A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK; 1725 } 1726 #define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100 1727 #define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__MASK 0x00ff0000 1728 #define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__SHIFT 16 1729 static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(uint32_t val) 1730 { 1731 return ((val) << A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__MASK; 1732 } 1733 #define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__MASK 0xff000000 1734 #define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__SHIFT 24 1735 static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(uint32_t val) 1736 { 1737 return ((val) << A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__MASK; 1738 } 1739 1740 #define REG_A3XX_HLSQ_CONTROL_2_REG 0x00002202 1741 #define A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__MASK 0x000003fc 1742 #define A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__SHIFT 2 1743 static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID(uint32_t val) 1744 { 1745 return ((val) << A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__MASK; 1746 } 1747 #define A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__MASK 0x03fc0000 1748 #define A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__SHIFT 18 1749 static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID(uint32_t val) 1750 { 1751 return ((val) << A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__MASK; 1752 } 1753 #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000 1754 #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26 1755 static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) 1756 { 1757 return ((val) << A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK; 1758 } 1759 1760 #define REG_A3XX_HLSQ_CONTROL_3_REG 0x00002203 1761 #define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__MASK 0x000000ff 1762 #define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__SHIFT 0 1763 static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID(uint32_t val) 1764 { 1765 return ((val) << A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__MASK; 1766 } 1767 #define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__MASK 0x0000ff00 1768 #define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__SHIFT 8 1769 static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID(uint32_t val) 1770 { 1771 return ((val) << A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__MASK; 1772 } 1773 #define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__MASK 0x00ff0000 1774 #define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__SHIFT 16 1775 static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID(uint32_t val) 1776 { 1777 return ((val) << A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__MASK; 1778 } 1779 #define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__MASK 0xff000000 1780 #define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__SHIFT 24 1781 static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID(uint32_t val) 1782 { 1783 return ((val) << A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__MASK; 1784 } 1785 1786 #define REG_A3XX_HLSQ_VS_CONTROL_REG 0x00002204 1787 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000003ff 1788 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0 1789 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) 1790 { 1791 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK; 1792 } 1793 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x001ff000 1794 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12 1795 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) 1796 { 1797 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK; 1798 } 1799 #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 1800 #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24 1801 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) 1802 { 1803 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK; 1804 } 1805 1806 #define REG_A3XX_HLSQ_FS_CONTROL_REG 0x00002205 1807 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000003ff 1808 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0 1809 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) 1810 { 1811 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK; 1812 } 1813 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x001ff000 1814 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12 1815 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) 1816 { 1817 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK; 1818 } 1819 #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 1820 #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24 1821 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) 1822 { 1823 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK; 1824 } 1825 1826 #define REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG 0x00002206 1827 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK 0x000001ff 1828 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT 0 1829 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val) 1830 { 1831 return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK; 1832 } 1833 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK 0x01ff0000 1834 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT 16 1835 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val) 1836 { 1837 return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK; 1838 } 1839 1840 #define REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG 0x00002207 1841 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK 0x000001ff 1842 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT 0 1843 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val) 1844 { 1845 return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK; 1846 } 1847 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK 0x01ff0000 1848 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT 16 1849 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val) 1850 { 1851 return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK; 1852 } 1853 1854 #define REG_A3XX_HLSQ_CL_NDRANGE_0_REG 0x0000220a 1855 #define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK 0x00000003 1856 #define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT 0 1857 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM(uint32_t val) 1858 { 1859 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK; 1860 } 1861 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK 0x00000ffc 1862 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT 2 1863 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0(uint32_t val) 1864 { 1865 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK; 1866 } 1867 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK 0x003ff000 1868 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT 12 1869 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1(uint32_t val) 1870 { 1871 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK; 1872 } 1873 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK 0xffc00000 1874 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT 22 1875 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2(uint32_t val) 1876 { 1877 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK; 1878 } 1879 1880 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK(uint32_t i0) { return 0x0000220b + 0x2*i0; } 1881 1882 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0; } 1883 1884 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { return 0x0000220c + 0x2*i0; } 1885 1886 #define REG_A3XX_HLSQ_CL_CONTROL_0_REG 0x00002211 1887 1888 #define REG_A3XX_HLSQ_CL_CONTROL_1_REG 0x00002212 1889 1890 #define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG 0x00002214 1891 1892 static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP(uint32_t i0) { return 0x00002215 + 0x1*i0; } 1893 1894 static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO(uint32_t i0) { return 0x00002215 + 0x1*i0; } 1895 1896 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Y_REG 0x00002216 1897 1898 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG 0x00002217 1899 1900 #define REG_A3XX_HLSQ_CL_WG_OFFSET_REG 0x0000221a 1901 1902 #define REG_A3XX_VFD_CONTROL_0 0x00002240 1903 #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x0003ffff 1904 #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0 1905 static inline uint32_t A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) 1906 { 1907 return ((val) << A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK; 1908 } 1909 #define A3XX_VFD_CONTROL_0_PACKETSIZE__MASK 0x003c0000 1910 #define A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT 18 1911 static inline uint32_t A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val) 1912 { 1913 return ((val) << A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT) & A3XX_VFD_CONTROL_0_PACKETSIZE__MASK; 1914 } 1915 #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x07c00000 1916 #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 22 1917 static inline uint32_t A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) 1918 { 1919 return ((val) << A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK; 1920 } 1921 #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xf8000000 1922 #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 27 1923 static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) 1924 { 1925 return ((val) << A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK; 1926 } 1927 1928 #define REG_A3XX_VFD_CONTROL_1 0x00002241 1929 #define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000000f 1930 #define A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0 1931 static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) 1932 { 1933 return ((val) << A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK; 1934 } 1935 #define A3XX_VFD_CONTROL_1_MAXTHRESHOLD__MASK 0x000000f0 1936 #define A3XX_VFD_CONTROL_1_MAXTHRESHOLD__SHIFT 4 1937 static inline uint32_t A3XX_VFD_CONTROL_1_MAXTHRESHOLD(uint32_t val) 1938 { 1939 return ((val) << A3XX_VFD_CONTROL_1_MAXTHRESHOLD__SHIFT) & A3XX_VFD_CONTROL_1_MAXTHRESHOLD__MASK; 1940 } 1941 #define A3XX_VFD_CONTROL_1_MINTHRESHOLD__MASK 0x00000f00 1942 #define A3XX_VFD_CONTROL_1_MINTHRESHOLD__SHIFT 8 1943 static inline uint32_t A3XX_VFD_CONTROL_1_MINTHRESHOLD(uint32_t val) 1944 { 1945 return ((val) << A3XX_VFD_CONTROL_1_MINTHRESHOLD__SHIFT) & A3XX_VFD_CONTROL_1_MINTHRESHOLD__MASK; 1946 } 1947 #define A3XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000 1948 #define A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16 1949 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 1950 { 1951 return ((val) << A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A3XX_VFD_CONTROL_1_REGID4VTX__MASK; 1952 } 1953 #define A3XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000 1954 #define A3XX_VFD_CONTROL_1_REGID4INST__SHIFT 24 1955 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 1956 { 1957 return ((val) << A3XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A3XX_VFD_CONTROL_1_REGID4INST__MASK; 1958 } 1959 1960 #define REG_A3XX_VFD_INDEX_MIN 0x00002242 1961 1962 #define REG_A3XX_VFD_INDEX_MAX 0x00002243 1963 1964 #define REG_A3XX_VFD_INSTANCEID_OFFSET 0x00002244 1965 1966 #define REG_A3XX_VFD_INDEX_OFFSET 0x00002245 1967 1968 static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0) { return 0x00002246 + 0x2*i0; } 1969 1970 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; } 1971 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f 1972 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0 1973 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) 1974 { 1975 return ((val) << A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK; 1976 } 1977 #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0000ff80 1978 #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7 1979 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) 1980 { 1981 return ((val) << A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK; 1982 } 1983 #define A3XX_VFD_FETCH_INSTR_0_INSTANCED 0x00010000 1984 #define A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00020000 1985 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK 0x00fc0000 1986 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT 18 1987 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val) 1988 { 1989 return ((val) << A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK; 1990 } 1991 #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK 0xff000000 1992 #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT 24 1993 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val) 1994 { 1995 return ((val) << A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK; 1996 } 1997 1998 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x00002247 + 0x2*i0; } 1999 2000 static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0) { return 0x00002266 + 0x1*i0; } 2001 2002 static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x00002266 + 0x1*i0; } 2003 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f 2004 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0 2005 static inline uint32_t A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) 2006 { 2007 return ((val) << A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK; 2008 } 2009 #define A3XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010 2010 #define A3XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0 2011 #define A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6 2012 static inline uint32_t A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val) 2013 { 2014 return ((val) << A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A3XX_VFD_DECODE_INSTR_FORMAT__MASK; 2015 } 2016 #define A3XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000 2017 #define A3XX_VFD_DECODE_INSTR_REGID__SHIFT 12 2018 static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val) 2019 { 2020 return ((val) << A3XX_VFD_DECODE_INSTR_REGID__SHIFT) & A3XX_VFD_DECODE_INSTR_REGID__MASK; 2021 } 2022 #define A3XX_VFD_DECODE_INSTR_INT 0x00100000 2023 #define A3XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000 2024 #define A3XX_VFD_DECODE_INSTR_SWAP__SHIFT 22 2025 static inline uint32_t A3XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 2026 { 2027 return ((val) << A3XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A3XX_VFD_DECODE_INSTR_SWAP__MASK; 2028 } 2029 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000 2030 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24 2031 static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) 2032 { 2033 return ((val) << A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK; 2034 } 2035 #define A3XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000 2036 #define A3XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000 2037 2038 #define REG_A3XX_VFD_VS_THREADING_THRESHOLD 0x0000227e 2039 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK 0x0000000f 2040 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT 0 2041 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val) 2042 { 2043 return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK; 2044 } 2045 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK 0x0000ff00 2046 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT 8 2047 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val) 2048 { 2049 return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK; 2050 } 2051 2052 #define REG_A3XX_VPC_ATTR 0x00002280 2053 #define A3XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff 2054 #define A3XX_VPC_ATTR_TOTALATTR__SHIFT 0 2055 static inline uint32_t A3XX_VPC_ATTR_TOTALATTR(uint32_t val) 2056 { 2057 return ((val) << A3XX_VPC_ATTR_TOTALATTR__SHIFT) & A3XX_VPC_ATTR_TOTALATTR__MASK; 2058 } 2059 #define A3XX_VPC_ATTR_PSIZE 0x00000200 2060 #define A3XX_VPC_ATTR_THRDASSIGN__MASK 0x0ffff000 2061 #define A3XX_VPC_ATTR_THRDASSIGN__SHIFT 12 2062 static inline uint32_t A3XX_VPC_ATTR_THRDASSIGN(uint32_t val) 2063 { 2064 return ((val) << A3XX_VPC_ATTR_THRDASSIGN__SHIFT) & A3XX_VPC_ATTR_THRDASSIGN__MASK; 2065 } 2066 #define A3XX_VPC_ATTR_LMSIZE__MASK 0xf0000000 2067 #define A3XX_VPC_ATTR_LMSIZE__SHIFT 28 2068 static inline uint32_t A3XX_VPC_ATTR_LMSIZE(uint32_t val) 2069 { 2070 return ((val) << A3XX_VPC_ATTR_LMSIZE__SHIFT) & A3XX_VPC_ATTR_LMSIZE__MASK; 2071 } 2072 2073 #define REG_A3XX_VPC_PACK 0x00002281 2074 #define A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00 2075 #define A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8 2076 static inline uint32_t A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) 2077 { 2078 return ((val) << A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK; 2079 } 2080 #define A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000 2081 #define A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16 2082 static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) 2083 { 2084 return ((val) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK; 2085 } 2086 2087 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002282 + 0x1*i0; } 2088 2089 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002282 + 0x1*i0; } 2090 #define A3XX_VPC_VARYING_INTERP_MODE_C0__MASK 0x00000003 2091 #define A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT 0 2092 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C0(enum a3xx_intp_mode val) 2093 { 2094 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C0__MASK; 2095 } 2096 #define A3XX_VPC_VARYING_INTERP_MODE_C1__MASK 0x0000000c 2097 #define A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT 2 2098 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C1(enum a3xx_intp_mode val) 2099 { 2100 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C1__MASK; 2101 } 2102 #define A3XX_VPC_VARYING_INTERP_MODE_C2__MASK 0x00000030 2103 #define A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT 4 2104 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C2(enum a3xx_intp_mode val) 2105 { 2106 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C2__MASK; 2107 } 2108 #define A3XX_VPC_VARYING_INTERP_MODE_C3__MASK 0x000000c0 2109 #define A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT 6 2110 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C3(enum a3xx_intp_mode val) 2111 { 2112 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C3__MASK; 2113 } 2114 #define A3XX_VPC_VARYING_INTERP_MODE_C4__MASK 0x00000300 2115 #define A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT 8 2116 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C4(enum a3xx_intp_mode val) 2117 { 2118 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C4__MASK; 2119 } 2120 #define A3XX_VPC_VARYING_INTERP_MODE_C5__MASK 0x00000c00 2121 #define A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT 10 2122 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C5(enum a3xx_intp_mode val) 2123 { 2124 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C5__MASK; 2125 } 2126 #define A3XX_VPC_VARYING_INTERP_MODE_C6__MASK 0x00003000 2127 #define A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT 12 2128 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C6(enum a3xx_intp_mode val) 2129 { 2130 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C6__MASK; 2131 } 2132 #define A3XX_VPC_VARYING_INTERP_MODE_C7__MASK 0x0000c000 2133 #define A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT 14 2134 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C7(enum a3xx_intp_mode val) 2135 { 2136 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C7__MASK; 2137 } 2138 #define A3XX_VPC_VARYING_INTERP_MODE_C8__MASK 0x00030000 2139 #define A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT 16 2140 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C8(enum a3xx_intp_mode val) 2141 { 2142 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C8__MASK; 2143 } 2144 #define A3XX_VPC_VARYING_INTERP_MODE_C9__MASK 0x000c0000 2145 #define A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT 18 2146 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C9(enum a3xx_intp_mode val) 2147 { 2148 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C9__MASK; 2149 } 2150 #define A3XX_VPC_VARYING_INTERP_MODE_CA__MASK 0x00300000 2151 #define A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT 20 2152 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CA(enum a3xx_intp_mode val) 2153 { 2154 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CA__MASK; 2155 } 2156 #define A3XX_VPC_VARYING_INTERP_MODE_CB__MASK 0x00c00000 2157 #define A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT 22 2158 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CB(enum a3xx_intp_mode val) 2159 { 2160 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CB__MASK; 2161 } 2162 #define A3XX_VPC_VARYING_INTERP_MODE_CC__MASK 0x03000000 2163 #define A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT 24 2164 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CC(enum a3xx_intp_mode val) 2165 { 2166 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CC__MASK; 2167 } 2168 #define A3XX_VPC_VARYING_INTERP_MODE_CD__MASK 0x0c000000 2169 #define A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT 26 2170 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CD(enum a3xx_intp_mode val) 2171 { 2172 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CD__MASK; 2173 } 2174 #define A3XX_VPC_VARYING_INTERP_MODE_CE__MASK 0x30000000 2175 #define A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT 28 2176 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CE(enum a3xx_intp_mode val) 2177 { 2178 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CE__MASK; 2179 } 2180 #define A3XX_VPC_VARYING_INTERP_MODE_CF__MASK 0xc0000000 2181 #define A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT 30 2182 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CF(enum a3xx_intp_mode val) 2183 { 2184 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CF__MASK; 2185 } 2186 2187 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; } 2188 2189 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; } 2190 #define A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK 0x00000003 2191 #define A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT 0 2192 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C0(enum a3xx_repl_mode val) 2193 { 2194 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK; 2195 } 2196 #define A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK 0x0000000c 2197 #define A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT 2 2198 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C1(enum a3xx_repl_mode val) 2199 { 2200 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK; 2201 } 2202 #define A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK 0x00000030 2203 #define A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT 4 2204 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C2(enum a3xx_repl_mode val) 2205 { 2206 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK; 2207 } 2208 #define A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK 0x000000c0 2209 #define A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT 6 2210 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C3(enum a3xx_repl_mode val) 2211 { 2212 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK; 2213 } 2214 #define A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK 0x00000300 2215 #define A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT 8 2216 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C4(enum a3xx_repl_mode val) 2217 { 2218 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK; 2219 } 2220 #define A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK 0x00000c00 2221 #define A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT 10 2222 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C5(enum a3xx_repl_mode val) 2223 { 2224 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK; 2225 } 2226 #define A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK 0x00003000 2227 #define A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT 12 2228 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C6(enum a3xx_repl_mode val) 2229 { 2230 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK; 2231 } 2232 #define A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK 0x0000c000 2233 #define A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT 14 2234 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C7(enum a3xx_repl_mode val) 2235 { 2236 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK; 2237 } 2238 #define A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK 0x00030000 2239 #define A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT 16 2240 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C8(enum a3xx_repl_mode val) 2241 { 2242 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK; 2243 } 2244 #define A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK 0x000c0000 2245 #define A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT 18 2246 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C9(enum a3xx_repl_mode val) 2247 { 2248 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK; 2249 } 2250 #define A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK 0x00300000 2251 #define A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT 20 2252 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CA(enum a3xx_repl_mode val) 2253 { 2254 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK; 2255 } 2256 #define A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK 0x00c00000 2257 #define A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT 22 2258 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CB(enum a3xx_repl_mode val) 2259 { 2260 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK; 2261 } 2262 #define A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK 0x03000000 2263 #define A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT 24 2264 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CC(enum a3xx_repl_mode val) 2265 { 2266 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK; 2267 } 2268 #define A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK 0x0c000000 2269 #define A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT 26 2270 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CD(enum a3xx_repl_mode val) 2271 { 2272 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK; 2273 } 2274 #define A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK 0x30000000 2275 #define A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT 28 2276 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CE(enum a3xx_repl_mode val) 2277 { 2278 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK; 2279 } 2280 #define A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK 0xc0000000 2281 #define A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT 30 2282 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CF(enum a3xx_repl_mode val) 2283 { 2284 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK; 2285 } 2286 2287 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0 0x0000228a 2288 2289 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_1 0x0000228b 2290 2291 #define REG_A3XX_SP_SP_CTRL_REG 0x000022c0 2292 #define A3XX_SP_SP_CTRL_REG_RESOLVE 0x00010000 2293 #define A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK 0x00040000 2294 #define A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT 18 2295 static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val) 2296 { 2297 return ((val) << A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK; 2298 } 2299 #define A3XX_SP_SP_CTRL_REG_BINNING 0x00080000 2300 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK 0x00300000 2301 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT 20 2302 static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val) 2303 { 2304 return ((val) << A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK; 2305 } 2306 #define A3XX_SP_SP_CTRL_REG_L0MODE__MASK 0x00c00000 2307 #define A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT 22 2308 static inline uint32_t A3XX_SP_SP_CTRL_REG_L0MODE(uint32_t val) 2309 { 2310 return ((val) << A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT) & A3XX_SP_SP_CTRL_REG_L0MODE__MASK; 2311 } 2312 2313 #define REG_A3XX_SP_VS_CTRL_REG0 0x000022c4 2314 #define A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 2315 #define A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 2316 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 2317 { 2318 return ((val) << A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK; 2319 } 2320 #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002 2321 #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1 2322 static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) 2323 { 2324 return ((val) << A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK; 2325 } 2326 #define A3XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004 2327 #define A3XX_SP_VS_CTRL_REG0_ALUSCHMODE 0x00000008 2328 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 2329 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 2330 static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 2331 { 2332 return ((val) << A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 2333 } 2334 #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 2335 #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 2336 static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 2337 { 2338 return ((val) << A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 2339 } 2340 #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000 2341 #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20 2342 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 2343 { 2344 return ((val) << A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; 2345 } 2346 #define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000 2347 #define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK 0xff000000 2348 #define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT 24 2349 static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val) 2350 { 2351 return ((val) << A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG0_LENGTH__MASK; 2352 } 2353 2354 #define REG_A3XX_SP_VS_CTRL_REG1 0x000022c5 2355 #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff 2356 #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0 2357 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) 2358 { 2359 return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK; 2360 } 2361 #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00 2362 #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10 2363 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) 2364 { 2365 return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK; 2366 } 2367 #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000 2368 #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24 2369 static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) 2370 { 2371 return ((val) << A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK; 2372 } 2373 2374 #define REG_A3XX_SP_VS_PARAM_REG 0x000022c6 2375 #define A3XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff 2376 #define A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0 2377 static inline uint32_t A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) 2378 { 2379 return ((val) << A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_POSREGID__MASK; 2380 } 2381 #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00 2382 #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8 2383 static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) 2384 { 2385 return ((val) << A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK; 2386 } 2387 #define A3XX_SP_VS_PARAM_REG_POS2DMODE 0x00010000 2388 #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0x01f00000 2389 #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20 2390 static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) 2391 { 2392 return ((val) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; 2393 } 2394 2395 static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 2396 2397 static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 2398 #define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff 2399 #define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 2400 static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 2401 { 2402 return ((val) << A3XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_A_REGID__MASK; 2403 } 2404 #define A3XX_SP_VS_OUT_REG_A_HALF 0x00000100 2405 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00 2406 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9 2407 static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 2408 { 2409 return ((val) << A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 2410 } 2411 #define A3XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000 2412 #define A3XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 2413 static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 2414 { 2415 return ((val) << A3XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_B_REGID__MASK; 2416 } 2417 #define A3XX_SP_VS_OUT_REG_B_HALF 0x01000000 2418 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000 2419 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25 2420 static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 2421 { 2422 return ((val) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 2423 } 2424 2425 static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; } 2426 2427 static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; } 2428 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x0000007f 2429 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 2430 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 2431 { 2432 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 2433 } 2434 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x00007f00 2435 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 2436 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 2437 { 2438 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 2439 } 2440 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x007f0000 2441 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 2442 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 2443 { 2444 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 2445 } 2446 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0x7f000000 2447 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 2448 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 2449 { 2450 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 2451 } 2452 2453 #define REG_A3XX_SP_VS_OBJ_OFFSET_REG 0x000022d4 2454 #define A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK 0x0000ffff 2455 #define A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT 0 2456 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val) 2457 { 2458 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK; 2459 } 2460 #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2461 #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2462 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2463 { 2464 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2465 } 2466 #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2467 #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2468 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2469 { 2470 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2471 } 2472 2473 #define REG_A3XX_SP_VS_OBJ_START_REG 0x000022d5 2474 2475 #define REG_A3XX_SP_VS_PVT_MEM_PARAM_REG 0x000022d6 2476 #define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK 0x000000ff 2477 #define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT 0 2478 static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val) 2479 { 2480 return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK; 2481 } 2482 #define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK 0x00ffff00 2483 #define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT 8 2484 static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val) 2485 { 2486 return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK; 2487 } 2488 #define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK 0xff000000 2489 #define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT 24 2490 static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val) 2491 { 2492 return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK; 2493 } 2494 2495 #define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG 0x000022d7 2496 #define A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__MASK 0x0000001f 2497 #define A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT 0 2498 static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val) 2499 { 2500 return ((val) << A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__MASK; 2501 } 2502 #define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK 0xffffffe0 2503 #define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT 5 2504 static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val) 2505 { 2506 return ((val >> 5) << A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK; 2507 } 2508 2509 #define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG 0x000022d8 2510 2511 #define REG_A3XX_SP_VS_LENGTH_REG 0x000022df 2512 #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff 2513 #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT 0 2514 static inline uint32_t A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val) 2515 { 2516 return ((val) << A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK; 2517 } 2518 2519 #define REG_A3XX_SP_FS_CTRL_REG0 0x000022e0 2520 #define A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 2521 #define A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 2522 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 2523 { 2524 return ((val) << A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK; 2525 } 2526 #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002 2527 #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1 2528 static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) 2529 { 2530 return ((val) << A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK; 2531 } 2532 #define A3XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004 2533 #define A3XX_SP_FS_CTRL_REG0_ALUSCHMODE 0x00000008 2534 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 2535 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 2536 static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 2537 { 2538 return ((val) << A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 2539 } 2540 #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00 2541 #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 2542 static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 2543 { 2544 return ((val) << A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 2545 } 2546 #define A3XX_SP_FS_CTRL_REG0_FSBYPASSENABLE 0x00020000 2547 #define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP 0x00040000 2548 #define A3XX_SP_FS_CTRL_REG0_OUTORDERED 0x00080000 2549 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 2550 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 2551 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 2552 { 2553 return ((val) << A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 2554 } 2555 #define A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000 2556 #define A3XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000 2557 #define A3XX_SP_FS_CTRL_REG0_COMPUTEMODE 0x00800000 2558 #define A3XX_SP_FS_CTRL_REG0_LENGTH__MASK 0xff000000 2559 #define A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT 24 2560 static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val) 2561 { 2562 return ((val) << A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG0_LENGTH__MASK; 2563 } 2564 2565 #define REG_A3XX_SP_FS_CTRL_REG1 0x000022e1 2566 #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff 2567 #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0 2568 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) 2569 { 2570 return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK; 2571 } 2572 #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00 2573 #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10 2574 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) 2575 { 2576 return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK; 2577 } 2578 #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x00f00000 2579 #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 20 2580 static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) 2581 { 2582 return ((val) << A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK; 2583 } 2584 #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK 0x7f000000 2585 #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT 24 2586 static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val) 2587 { 2588 return ((val) << A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT) & A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK; 2589 } 2590 2591 #define REG_A3XX_SP_FS_OBJ_OFFSET_REG 0x000022e2 2592 #define A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK 0x0000ffff 2593 #define A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT 0 2594 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val) 2595 { 2596 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK; 2597 } 2598 #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2599 #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2600 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2601 { 2602 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2603 } 2604 #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2605 #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2606 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2607 { 2608 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2609 } 2610 2611 #define REG_A3XX_SP_FS_OBJ_START_REG 0x000022e3 2612 2613 #define REG_A3XX_SP_FS_PVT_MEM_PARAM_REG 0x000022e4 2614 #define A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK 0x000000ff 2615 #define A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT 0 2616 static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val) 2617 { 2618 return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK; 2619 } 2620 #define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK 0x00ffff00 2621 #define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT 8 2622 static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val) 2623 { 2624 return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK; 2625 } 2626 #define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK 0xff000000 2627 #define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT 24 2628 static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val) 2629 { 2630 return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK; 2631 } 2632 2633 #define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG 0x000022e5 2634 #define A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__MASK 0x0000001f 2635 #define A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT 0 2636 static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val) 2637 { 2638 return ((val) << A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__MASK; 2639 } 2640 #define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK 0xffffffe0 2641 #define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT 5 2642 static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val) 2643 { 2644 return ((val >> 5) << A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK; 2645 } 2646 2647 #define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG 0x000022e6 2648 2649 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0 0x000022e8 2650 2651 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1 0x000022e9 2652 2653 #define REG_A3XX_SP_FS_OUTPUT_REG 0x000022ec 2654 #define A3XX_SP_FS_OUTPUT_REG_MRT__MASK 0x00000003 2655 #define A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0 2656 static inline uint32_t A3XX_SP_FS_OUTPUT_REG_MRT(uint32_t val) 2657 { 2658 return ((val) << A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A3XX_SP_FS_OUTPUT_REG_MRT__MASK; 2659 } 2660 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080 2661 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00 2662 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8 2663 static inline uint32_t A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) 2664 { 2665 return ((val) << A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK; 2666 } 2667 2668 static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0) { return 0x000022f0 + 0x1*i0; } 2669 2670 static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f0 + 0x1*i0; } 2671 #define A3XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff 2672 #define A3XX_SP_FS_MRT_REG_REGID__SHIFT 0 2673 static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val) 2674 { 2675 return ((val) << A3XX_SP_FS_MRT_REG_REGID__SHIFT) & A3XX_SP_FS_MRT_REG_REGID__MASK; 2676 } 2677 #define A3XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100 2678 #define A3XX_SP_FS_MRT_REG_SINT 0x00000400 2679 #define A3XX_SP_FS_MRT_REG_UINT 0x00000800 2680 2681 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0) { return 0x000022f4 + 0x1*i0; } 2682 2683 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0) { return 0x000022f4 + 0x1*i0; } 2684 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK 0x0000003f 2685 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT 0 2686 static inline uint32_t A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val) 2687 { 2688 return ((val) << A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT) & A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK; 2689 } 2690 2691 #define REG_A3XX_SP_FS_LENGTH_REG 0x000022ff 2692 #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff 2693 #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT 0 2694 static inline uint32_t A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val) 2695 { 2696 return ((val) << A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK; 2697 } 2698 2699 #define REG_A3XX_PA_SC_AA_CONFIG 0x00002301 2700 2701 #define REG_A3XX_TPL1_TP_VS_TEX_OFFSET 0x00002340 2702 #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff 2703 #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0 2704 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) 2705 { 2706 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK; 2707 } 2708 #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00 2709 #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8 2710 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) 2711 { 2712 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK; 2713 } 2714 #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000 2715 #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT 16 2716 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val) 2717 { 2718 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK; 2719 } 2720 2721 #define REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002341 2722 2723 #define REG_A3XX_TPL1_TP_FS_TEX_OFFSET 0x00002342 2724 #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff 2725 #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0 2726 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) 2727 { 2728 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK; 2729 } 2730 #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00 2731 #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8 2732 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) 2733 { 2734 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK; 2735 } 2736 #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000 2737 #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT 16 2738 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val) 2739 { 2740 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK; 2741 } 2742 2743 #define REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x00002343 2744 2745 #define REG_A3XX_VBIF_CLKON 0x00003001 2746 2747 #define REG_A3XX_VBIF_FIXED_SORT_EN 0x0000300c 2748 2749 #define REG_A3XX_VBIF_FIXED_SORT_SEL0 0x0000300d 2750 2751 #define REG_A3XX_VBIF_FIXED_SORT_SEL1 0x0000300e 2752 2753 #define REG_A3XX_VBIF_ABIT_SORT 0x0000301c 2754 2755 #define REG_A3XX_VBIF_ABIT_SORT_CONF 0x0000301d 2756 2757 #define REG_A3XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 2758 2759 #define REG_A3XX_VBIF_IN_RD_LIM_CONF0 0x0000302c 2760 2761 #define REG_A3XX_VBIF_IN_RD_LIM_CONF1 0x0000302d 2762 2763 #define REG_A3XX_VBIF_IN_WR_LIM_CONF0 0x00003030 2764 2765 #define REG_A3XX_VBIF_IN_WR_LIM_CONF1 0x00003031 2766 2767 #define REG_A3XX_VBIF_OUT_RD_LIM_CONF0 0x00003034 2768 2769 #define REG_A3XX_VBIF_OUT_WR_LIM_CONF0 0x00003035 2770 2771 #define REG_A3XX_VBIF_DDR_OUT_MAX_BURST 0x00003036 2772 2773 #define REG_A3XX_VBIF_ARB_CTL 0x0000303c 2774 2775 #define REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049 2776 2777 #define REG_A3XX_VBIF_OUT_AXI_AMEMTYPE_CONF0 0x00003058 2778 2779 #define REG_A3XX_VBIF_OUT_AXI_AOOO_EN 0x0000305e 2780 2781 #define REG_A3XX_VBIF_OUT_AXI_AOOO 0x0000305f 2782 2783 #define REG_A3XX_VBIF_PERF_CNT_EN 0x00003070 2784 #define A3XX_VBIF_PERF_CNT_EN_CNT0 0x00000001 2785 #define A3XX_VBIF_PERF_CNT_EN_CNT1 0x00000002 2786 #define A3XX_VBIF_PERF_CNT_EN_PWRCNT0 0x00000004 2787 #define A3XX_VBIF_PERF_CNT_EN_PWRCNT1 0x00000008 2788 #define A3XX_VBIF_PERF_CNT_EN_PWRCNT2 0x00000010 2789 2790 #define REG_A3XX_VBIF_PERF_CNT_CLR 0x00003071 2791 #define A3XX_VBIF_PERF_CNT_CLR_CNT0 0x00000001 2792 #define A3XX_VBIF_PERF_CNT_CLR_CNT1 0x00000002 2793 #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT0 0x00000004 2794 #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT1 0x00000008 2795 #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT2 0x00000010 2796 2797 #define REG_A3XX_VBIF_PERF_CNT_SEL 0x00003072 2798 2799 #define REG_A3XX_VBIF_PERF_CNT0_LO 0x00003073 2800 2801 #define REG_A3XX_VBIF_PERF_CNT0_HI 0x00003074 2802 2803 #define REG_A3XX_VBIF_PERF_CNT1_LO 0x00003075 2804 2805 #define REG_A3XX_VBIF_PERF_CNT1_HI 0x00003076 2806 2807 #define REG_A3XX_VBIF_PERF_PWR_CNT0_LO 0x00003077 2808 2809 #define REG_A3XX_VBIF_PERF_PWR_CNT0_HI 0x00003078 2810 2811 #define REG_A3XX_VBIF_PERF_PWR_CNT1_LO 0x00003079 2812 2813 #define REG_A3XX_VBIF_PERF_PWR_CNT1_HI 0x0000307a 2814 2815 #define REG_A3XX_VBIF_PERF_PWR_CNT2_LO 0x0000307b 2816 2817 #define REG_A3XX_VBIF_PERF_PWR_CNT2_HI 0x0000307c 2818 2819 #define REG_A3XX_VSC_BIN_SIZE 0x00000c01 2820 #define A3XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 2821 #define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 2822 static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 2823 { 2824 return ((val >> 5) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A3XX_VSC_BIN_SIZE_WIDTH__MASK; 2825 } 2826 #define A3XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 2827 #define A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5 2828 static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 2829 { 2830 return ((val >> 5) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK; 2831 } 2832 2833 #define REG_A3XX_VSC_SIZE_ADDRESS 0x00000c02 2834 2835 static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 2836 2837 static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 2838 #define A3XX_VSC_PIPE_CONFIG_X__MASK 0x000003ff 2839 #define A3XX_VSC_PIPE_CONFIG_X__SHIFT 0 2840 static inline uint32_t A3XX_VSC_PIPE_CONFIG_X(uint32_t val) 2841 { 2842 return ((val) << A3XX_VSC_PIPE_CONFIG_X__SHIFT) & A3XX_VSC_PIPE_CONFIG_X__MASK; 2843 } 2844 #define A3XX_VSC_PIPE_CONFIG_Y__MASK 0x000ffc00 2845 #define A3XX_VSC_PIPE_CONFIG_Y__SHIFT 10 2846 static inline uint32_t A3XX_VSC_PIPE_CONFIG_Y(uint32_t val) 2847 { 2848 return ((val) << A3XX_VSC_PIPE_CONFIG_Y__SHIFT) & A3XX_VSC_PIPE_CONFIG_Y__MASK; 2849 } 2850 #define A3XX_VSC_PIPE_CONFIG_W__MASK 0x00f00000 2851 #define A3XX_VSC_PIPE_CONFIG_W__SHIFT 20 2852 static inline uint32_t A3XX_VSC_PIPE_CONFIG_W(uint32_t val) 2853 { 2854 return ((val) << A3XX_VSC_PIPE_CONFIG_W__SHIFT) & A3XX_VSC_PIPE_CONFIG_W__MASK; 2855 } 2856 #define A3XX_VSC_PIPE_CONFIG_H__MASK 0x0f000000 2857 #define A3XX_VSC_PIPE_CONFIG_H__SHIFT 24 2858 static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val) 2859 { 2860 return ((val) << A3XX_VSC_PIPE_CONFIG_H__SHIFT) & A3XX_VSC_PIPE_CONFIG_H__MASK; 2861 } 2862 2863 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } 2864 2865 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } 2866 2867 #define REG_A3XX_VSC_BIN_CONTROL 0x00000c3c 2868 #define A3XX_VSC_BIN_CONTROL_BINNING_ENABLE 0x00000001 2869 2870 #define REG_A3XX_UNKNOWN_0C3D 0x00000c3d 2871 2872 #define REG_A3XX_PC_PERFCOUNTER0_SELECT 0x00000c48 2873 2874 #define REG_A3XX_PC_PERFCOUNTER1_SELECT 0x00000c49 2875 2876 #define REG_A3XX_PC_PERFCOUNTER2_SELECT 0x00000c4a 2877 2878 #define REG_A3XX_PC_PERFCOUNTER3_SELECT 0x00000c4b 2879 2880 #define REG_A3XX_GRAS_TSE_DEBUG_ECO 0x00000c81 2881 2882 #define REG_A3XX_GRAS_PERFCOUNTER0_SELECT 0x00000c88 2883 2884 #define REG_A3XX_GRAS_PERFCOUNTER1_SELECT 0x00000c89 2885 2886 #define REG_A3XX_GRAS_PERFCOUNTER2_SELECT 0x00000c8a 2887 2888 #define REG_A3XX_GRAS_PERFCOUNTER3_SELECT 0x00000c8b 2889 2890 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } 2891 2892 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } 2893 2894 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0) { return 0x00000ca1 + 0x4*i0; } 2895 2896 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0) { return 0x00000ca2 + 0x4*i0; } 2897 2898 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) { return 0x00000ca3 + 0x4*i0; } 2899 2900 #define REG_A3XX_RB_GMEM_BASE_ADDR 0x00000cc0 2901 2902 #define REG_A3XX_RB_DEBUG_ECO_CONTROLS_ADDR 0x00000cc1 2903 2904 #define REG_A3XX_RB_PERFCOUNTER0_SELECT 0x00000cc6 2905 2906 #define REG_A3XX_RB_PERFCOUNTER1_SELECT 0x00000cc7 2907 2908 #define REG_A3XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0 2909 #define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff 2910 #define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0 2911 static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) 2912 { 2913 return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK; 2914 } 2915 #define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x0fffc000 2916 #define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 14 2917 static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) 2918 { 2919 return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK; 2920 } 2921 2922 #define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT 0x00000e00 2923 2924 #define REG_A3XX_HLSQ_PERFCOUNTER1_SELECT 0x00000e01 2925 2926 #define REG_A3XX_HLSQ_PERFCOUNTER2_SELECT 0x00000e02 2927 2928 #define REG_A3XX_HLSQ_PERFCOUNTER3_SELECT 0x00000e03 2929 2930 #define REG_A3XX_HLSQ_PERFCOUNTER4_SELECT 0x00000e04 2931 2932 #define REG_A3XX_HLSQ_PERFCOUNTER5_SELECT 0x00000e05 2933 2934 #define REG_A3XX_UNKNOWN_0E43 0x00000e43 2935 2936 #define REG_A3XX_VFD_PERFCOUNTER0_SELECT 0x00000e44 2937 2938 #define REG_A3XX_VFD_PERFCOUNTER1_SELECT 0x00000e45 2939 2940 #define REG_A3XX_VPC_VPC_DEBUG_RAM_SEL 0x00000e61 2941 2942 #define REG_A3XX_VPC_VPC_DEBUG_RAM_READ 0x00000e62 2943 2944 #define REG_A3XX_VPC_PERFCOUNTER0_SELECT 0x00000e64 2945 2946 #define REG_A3XX_VPC_PERFCOUNTER1_SELECT 0x00000e65 2947 2948 #define REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG 0x00000e82 2949 2950 #define REG_A3XX_UCHE_PERFCOUNTER0_SELECT 0x00000e84 2951 2952 #define REG_A3XX_UCHE_PERFCOUNTER1_SELECT 0x00000e85 2953 2954 #define REG_A3XX_UCHE_PERFCOUNTER2_SELECT 0x00000e86 2955 2956 #define REG_A3XX_UCHE_PERFCOUNTER3_SELECT 0x00000e87 2957 2958 #define REG_A3XX_UCHE_PERFCOUNTER4_SELECT 0x00000e88 2959 2960 #define REG_A3XX_UCHE_PERFCOUNTER5_SELECT 0x00000e89 2961 2962 #define REG_A3XX_UCHE_CACHE_INVALIDATE0_REG 0x00000ea0 2963 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK 0x0fffffff 2964 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT 0 2965 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val) 2966 { 2967 return ((val) << A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK; 2968 } 2969 2970 #define REG_A3XX_UCHE_CACHE_INVALIDATE1_REG 0x00000ea1 2971 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK 0x0fffffff 2972 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT 0 2973 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val) 2974 { 2975 return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK; 2976 } 2977 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK 0x30000000 2978 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT 28 2979 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val) 2980 { 2981 return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK; 2982 } 2983 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE 0x80000000 2984 2985 #define REG_A3XX_UNKNOWN_0EA6 0x00000ea6 2986 2987 #define REG_A3XX_SP_PERFCOUNTER0_SELECT 0x00000ec4 2988 2989 #define REG_A3XX_SP_PERFCOUNTER1_SELECT 0x00000ec5 2990 2991 #define REG_A3XX_SP_PERFCOUNTER2_SELECT 0x00000ec6 2992 2993 #define REG_A3XX_SP_PERFCOUNTER3_SELECT 0x00000ec7 2994 2995 #define REG_A3XX_SP_PERFCOUNTER4_SELECT 0x00000ec8 2996 2997 #define REG_A3XX_SP_PERFCOUNTER5_SELECT 0x00000ec9 2998 2999 #define REG_A3XX_SP_PERFCOUNTER6_SELECT 0x00000eca 3000 3001 #define REG_A3XX_SP_PERFCOUNTER7_SELECT 0x00000ecb 3002 3003 #define REG_A3XX_UNKNOWN_0EE0 0x00000ee0 3004 3005 #define REG_A3XX_UNKNOWN_0F03 0x00000f03 3006 3007 #define REG_A3XX_TP_PERFCOUNTER0_SELECT 0x00000f04 3008 3009 #define REG_A3XX_TP_PERFCOUNTER1_SELECT 0x00000f05 3010 3011 #define REG_A3XX_TP_PERFCOUNTER2_SELECT 0x00000f06 3012 3013 #define REG_A3XX_TP_PERFCOUNTER3_SELECT 0x00000f07 3014 3015 #define REG_A3XX_TP_PERFCOUNTER4_SELECT 0x00000f08 3016 3017 #define REG_A3XX_TP_PERFCOUNTER5_SELECT 0x00000f09 3018 3019 #define REG_A3XX_VGT_CL_INITIATOR 0x000021f0 3020 3021 #define REG_A3XX_VGT_EVENT_INITIATOR 0x000021f9 3022 3023 #define REG_A3XX_VGT_DRAW_INITIATOR 0x000021fc 3024 #define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f 3025 #define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 3026 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) 3027 { 3028 return ((val) << A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK; 3029 } 3030 #define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 3031 #define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 3032 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) 3033 { 3034 return ((val) << A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK; 3035 } 3036 #define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600 3037 #define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9 3038 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) 3039 { 3040 return ((val) << A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK; 3041 } 3042 #define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800 3043 #define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11 3044 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) 3045 { 3046 return ((val) << A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK; 3047 } 3048 #define A3XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000 3049 #define A3XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000 3050 #define A3XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000 3051 #define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK 0xff000000 3052 #define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT 24 3053 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) 3054 { 3055 return ((val) << A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK; 3056 } 3057 3058 #define REG_A3XX_VGT_IMMED_DATA 0x000021fd 3059 3060 #define REG_A3XX_TEX_SAMP_0 0x00000000 3061 #define A3XX_TEX_SAMP_0_CLAMPENABLE 0x00000001 3062 #define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR 0x00000002 3063 #define A3XX_TEX_SAMP_0_XY_MAG__MASK 0x0000000c 3064 #define A3XX_TEX_SAMP_0_XY_MAG__SHIFT 2 3065 static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val) 3066 { 3067 return ((val) << A3XX_TEX_SAMP_0_XY_MAG__SHIFT) & A3XX_TEX_SAMP_0_XY_MAG__MASK; 3068 } 3069 #define A3XX_TEX_SAMP_0_XY_MIN__MASK 0x00000030 3070 #define A3XX_TEX_SAMP_0_XY_MIN__SHIFT 4 3071 static inline uint32_t A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val) 3072 { 3073 return ((val) << A3XX_TEX_SAMP_0_XY_MIN__SHIFT) & A3XX_TEX_SAMP_0_XY_MIN__MASK; 3074 } 3075 #define A3XX_TEX_SAMP_0_WRAP_S__MASK 0x000001c0 3076 #define A3XX_TEX_SAMP_0_WRAP_S__SHIFT 6 3077 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val) 3078 { 3079 return ((val) << A3XX_TEX_SAMP_0_WRAP_S__SHIFT) & A3XX_TEX_SAMP_0_WRAP_S__MASK; 3080 } 3081 #define A3XX_TEX_SAMP_0_WRAP_T__MASK 0x00000e00 3082 #define A3XX_TEX_SAMP_0_WRAP_T__SHIFT 9 3083 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val) 3084 { 3085 return ((val) << A3XX_TEX_SAMP_0_WRAP_T__SHIFT) & A3XX_TEX_SAMP_0_WRAP_T__MASK; 3086 } 3087 #define A3XX_TEX_SAMP_0_WRAP_R__MASK 0x00007000 3088 #define A3XX_TEX_SAMP_0_WRAP_R__SHIFT 12 3089 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val) 3090 { 3091 return ((val) << A3XX_TEX_SAMP_0_WRAP_R__SHIFT) & A3XX_TEX_SAMP_0_WRAP_R__MASK; 3092 } 3093 #define A3XX_TEX_SAMP_0_ANISO__MASK 0x00038000 3094 #define A3XX_TEX_SAMP_0_ANISO__SHIFT 15 3095 static inline uint32_t A3XX_TEX_SAMP_0_ANISO(enum a3xx_tex_aniso val) 3096 { 3097 return ((val) << A3XX_TEX_SAMP_0_ANISO__SHIFT) & A3XX_TEX_SAMP_0_ANISO__MASK; 3098 } 3099 #define A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK 0x00700000 3100 #define A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT 20 3101 static inline uint32_t A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val) 3102 { 3103 return ((val) << A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT) & A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK; 3104 } 3105 #define A3XX_TEX_SAMP_0_CUBEMAPSEAMLESSFILTOFF 0x01000000 3106 #define A3XX_TEX_SAMP_0_UNNORM_COORDS 0x80000000 3107 3108 #define REG_A3XX_TEX_SAMP_1 0x00000001 3109 #define A3XX_TEX_SAMP_1_LOD_BIAS__MASK 0x000007ff 3110 #define A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT 0 3111 static inline uint32_t A3XX_TEX_SAMP_1_LOD_BIAS(float val) 3112 { 3113 return ((((int32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT) & A3XX_TEX_SAMP_1_LOD_BIAS__MASK; 3114 } 3115 #define A3XX_TEX_SAMP_1_MAX_LOD__MASK 0x003ff000 3116 #define A3XX_TEX_SAMP_1_MAX_LOD__SHIFT 12 3117 static inline uint32_t A3XX_TEX_SAMP_1_MAX_LOD(float val) 3118 { 3119 return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A3XX_TEX_SAMP_1_MAX_LOD__MASK; 3120 } 3121 #define A3XX_TEX_SAMP_1_MIN_LOD__MASK 0xffc00000 3122 #define A3XX_TEX_SAMP_1_MIN_LOD__SHIFT 22 3123 static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val) 3124 { 3125 return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A3XX_TEX_SAMP_1_MIN_LOD__MASK; 3126 } 3127 3128 #define REG_A3XX_TEX_CONST_0 0x00000000 3129 #define A3XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003 3130 #define A3XX_TEX_CONST_0_TILE_MODE__SHIFT 0 3131 static inline uint32_t A3XX_TEX_CONST_0_TILE_MODE(enum a3xx_tile_mode val) 3132 { 3133 return ((val) << A3XX_TEX_CONST_0_TILE_MODE__SHIFT) & A3XX_TEX_CONST_0_TILE_MODE__MASK; 3134 } 3135 #define A3XX_TEX_CONST_0_SRGB 0x00000004 3136 #define A3XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 3137 #define A3XX_TEX_CONST_0_SWIZ_X__SHIFT 4 3138 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val) 3139 { 3140 return ((val) << A3XX_TEX_CONST_0_SWIZ_X__SHIFT) & A3XX_TEX_CONST_0_SWIZ_X__MASK; 3141 } 3142 #define A3XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 3143 #define A3XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 3144 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val) 3145 { 3146 return ((val) << A3XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Y__MASK; 3147 } 3148 #define A3XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 3149 #define A3XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 3150 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val) 3151 { 3152 return ((val) << A3XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Z__MASK; 3153 } 3154 #define A3XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 3155 #define A3XX_TEX_CONST_0_SWIZ_W__SHIFT 13 3156 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val) 3157 { 3158 return ((val) << A3XX_TEX_CONST_0_SWIZ_W__SHIFT) & A3XX_TEX_CONST_0_SWIZ_W__MASK; 3159 } 3160 #define A3XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 3161 #define A3XX_TEX_CONST_0_MIPLVLS__SHIFT 16 3162 static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val) 3163 { 3164 return ((val) << A3XX_TEX_CONST_0_MIPLVLS__SHIFT) & A3XX_TEX_CONST_0_MIPLVLS__MASK; 3165 } 3166 #define A3XX_TEX_CONST_0_MSAATEX__MASK 0x00300000 3167 #define A3XX_TEX_CONST_0_MSAATEX__SHIFT 20 3168 static inline uint32_t A3XX_TEX_CONST_0_MSAATEX(enum a3xx_tex_msaa val) 3169 { 3170 return ((val) << A3XX_TEX_CONST_0_MSAATEX__SHIFT) & A3XX_TEX_CONST_0_MSAATEX__MASK; 3171 } 3172 #define A3XX_TEX_CONST_0_FMT__MASK 0x1fc00000 3173 #define A3XX_TEX_CONST_0_FMT__SHIFT 22 3174 static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val) 3175 { 3176 return ((val) << A3XX_TEX_CONST_0_FMT__SHIFT) & A3XX_TEX_CONST_0_FMT__MASK; 3177 } 3178 #define A3XX_TEX_CONST_0_NOCONVERT 0x20000000 3179 #define A3XX_TEX_CONST_0_TYPE__MASK 0xc0000000 3180 #define A3XX_TEX_CONST_0_TYPE__SHIFT 30 3181 static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val) 3182 { 3183 return ((val) << A3XX_TEX_CONST_0_TYPE__SHIFT) & A3XX_TEX_CONST_0_TYPE__MASK; 3184 } 3185 3186 #define REG_A3XX_TEX_CONST_1 0x00000001 3187 #define A3XX_TEX_CONST_1_HEIGHT__MASK 0x00003fff 3188 #define A3XX_TEX_CONST_1_HEIGHT__SHIFT 0 3189 static inline uint32_t A3XX_TEX_CONST_1_HEIGHT(uint32_t val) 3190 { 3191 return ((val) << A3XX_TEX_CONST_1_HEIGHT__SHIFT) & A3XX_TEX_CONST_1_HEIGHT__MASK; 3192 } 3193 #define A3XX_TEX_CONST_1_WIDTH__MASK 0x0fffc000 3194 #define A3XX_TEX_CONST_1_WIDTH__SHIFT 14 3195 static inline uint32_t A3XX_TEX_CONST_1_WIDTH(uint32_t val) 3196 { 3197 return ((val) << A3XX_TEX_CONST_1_WIDTH__SHIFT) & A3XX_TEX_CONST_1_WIDTH__MASK; 3198 } 3199 #define A3XX_TEX_CONST_1_PITCHALIGN__MASK 0xf0000000 3200 #define A3XX_TEX_CONST_1_PITCHALIGN__SHIFT 28 3201 static inline uint32_t A3XX_TEX_CONST_1_PITCHALIGN(uint32_t val) 3202 { 3203 return ((val) << A3XX_TEX_CONST_1_PITCHALIGN__SHIFT) & A3XX_TEX_CONST_1_PITCHALIGN__MASK; 3204 } 3205 3206 #define REG_A3XX_TEX_CONST_2 0x00000002 3207 #define A3XX_TEX_CONST_2_INDX__MASK 0x000001ff 3208 #define A3XX_TEX_CONST_2_INDX__SHIFT 0 3209 static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val) 3210 { 3211 return ((val) << A3XX_TEX_CONST_2_INDX__SHIFT) & A3XX_TEX_CONST_2_INDX__MASK; 3212 } 3213 #define A3XX_TEX_CONST_2_PITCH__MASK 0x3ffff000 3214 #define A3XX_TEX_CONST_2_PITCH__SHIFT 12 3215 static inline uint32_t A3XX_TEX_CONST_2_PITCH(uint32_t val) 3216 { 3217 return ((val) << A3XX_TEX_CONST_2_PITCH__SHIFT) & A3XX_TEX_CONST_2_PITCH__MASK; 3218 } 3219 #define A3XX_TEX_CONST_2_SWAP__MASK 0xc0000000 3220 #define A3XX_TEX_CONST_2_SWAP__SHIFT 30 3221 static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) 3222 { 3223 return ((val) << A3XX_TEX_CONST_2_SWAP__SHIFT) & A3XX_TEX_CONST_2_SWAP__MASK; 3224 } 3225 3226 #define REG_A3XX_TEX_CONST_3 0x00000003 3227 #define A3XX_TEX_CONST_3_LAYERSZ1__MASK 0x0001ffff 3228 #define A3XX_TEX_CONST_3_LAYERSZ1__SHIFT 0 3229 static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val) 3230 { 3231 return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ1__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ1__MASK; 3232 } 3233 #define A3XX_TEX_CONST_3_DEPTH__MASK 0x0ffe0000 3234 #define A3XX_TEX_CONST_3_DEPTH__SHIFT 17 3235 static inline uint32_t A3XX_TEX_CONST_3_DEPTH(uint32_t val) 3236 { 3237 return ((val) << A3XX_TEX_CONST_3_DEPTH__SHIFT) & A3XX_TEX_CONST_3_DEPTH__MASK; 3238 } 3239 #define A3XX_TEX_CONST_3_LAYERSZ2__MASK 0xf0000000 3240 #define A3XX_TEX_CONST_3_LAYERSZ2__SHIFT 28 3241 static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ2(uint32_t val) 3242 { 3243 return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ2__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ2__MASK; 3244 } 3245 3246 3247 #endif /* A3XX_XML */ 3248