1 #ifndef A3XX_XML 2 #define A3XX_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://0x04.net/cgit/index.cgi/rules-ng-ng 8 git clone git://0x04.net/rules-ng-ng 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13 - /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 30005 bytes, from 2013-07-19 21:30:48) 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36) 15 - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9712 bytes, from 2013-05-26 15:22:37) 16 - /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51415 bytes, from 2013-08-03 14:26:05) 17 18 Copyright (C) 2013 by the following authors: 19 - Rob Clark <robdclark@gmail.com> (robclark) 20 21 Permission is hereby granted, free of charge, to any person obtaining 22 a copy of this software and associated documentation files (the 23 "Software"), to deal in the Software without restriction, including 24 without limitation the rights to use, copy, modify, merge, publish, 25 distribute, sublicense, and/or sell copies of the Software, and to 26 permit persons to whom the Software is furnished to do so, subject to 27 the following conditions: 28 29 The above copyright notice and this permission notice (including the 30 next paragraph) shall be included in all copies or substantial 31 portions of the Software. 32 33 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 35 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 36 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 37 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 38 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 39 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 40 */ 41 42 43 enum a3xx_render_mode { 44 RB_RENDERING_PASS = 0, 45 RB_TILING_PASS = 1, 46 RB_RESOLVE_PASS = 2, 47 }; 48 49 enum a3xx_tile_mode { 50 LINEAR = 0, 51 TILE_32X32 = 2, 52 }; 53 54 enum a3xx_threadmode { 55 MULTI = 0, 56 SINGLE = 1, 57 }; 58 59 enum a3xx_instrbuffermode { 60 BUFFER = 1, 61 }; 62 63 enum a3xx_threadsize { 64 TWO_QUADS = 0, 65 FOUR_QUADS = 1, 66 }; 67 68 enum a3xx_state_block_id { 69 HLSQ_BLOCK_ID_TP_TEX = 2, 70 HLSQ_BLOCK_ID_TP_MIPMAP = 3, 71 HLSQ_BLOCK_ID_SP_VS = 4, 72 HLSQ_BLOCK_ID_SP_FS = 6, 73 }; 74 75 enum a3xx_cache_opcode { 76 INVALIDATE = 1, 77 }; 78 79 enum a3xx_vtx_fmt { 80 VFMT_FLOAT_32 = 0, 81 VFMT_FLOAT_32_32 = 1, 82 VFMT_FLOAT_32_32_32 = 2, 83 VFMT_FLOAT_32_32_32_32 = 3, 84 VFMT_FLOAT_16 = 4, 85 VFMT_FLOAT_16_16 = 5, 86 VFMT_FLOAT_16_16_16 = 6, 87 VFMT_FLOAT_16_16_16_16 = 7, 88 VFMT_FIXED_32 = 8, 89 VFMT_FIXED_32_32 = 9, 90 VFMT_FIXED_32_32_32 = 10, 91 VFMT_FIXED_32_32_32_32 = 11, 92 VFMT_SHORT_16 = 16, 93 VFMT_SHORT_16_16 = 17, 94 VFMT_SHORT_16_16_16 = 18, 95 VFMT_SHORT_16_16_16_16 = 19, 96 VFMT_USHORT_16 = 20, 97 VFMT_USHORT_16_16 = 21, 98 VFMT_USHORT_16_16_16 = 22, 99 VFMT_USHORT_16_16_16_16 = 23, 100 VFMT_NORM_SHORT_16 = 24, 101 VFMT_NORM_SHORT_16_16 = 25, 102 VFMT_NORM_SHORT_16_16_16 = 26, 103 VFMT_NORM_SHORT_16_16_16_16 = 27, 104 VFMT_NORM_USHORT_16 = 28, 105 VFMT_NORM_USHORT_16_16 = 29, 106 VFMT_NORM_USHORT_16_16_16 = 30, 107 VFMT_NORM_USHORT_16_16_16_16 = 31, 108 VFMT_UBYTE_8 = 40, 109 VFMT_UBYTE_8_8 = 41, 110 VFMT_UBYTE_8_8_8 = 42, 111 VFMT_UBYTE_8_8_8_8 = 43, 112 VFMT_NORM_UBYTE_8 = 44, 113 VFMT_NORM_UBYTE_8_8 = 45, 114 VFMT_NORM_UBYTE_8_8_8 = 46, 115 VFMT_NORM_UBYTE_8_8_8_8 = 47, 116 VFMT_BYTE_8 = 48, 117 VFMT_BYTE_8_8 = 49, 118 VFMT_BYTE_8_8_8 = 50, 119 VFMT_BYTE_8_8_8_8 = 51, 120 VFMT_NORM_BYTE_8 = 52, 121 VFMT_NORM_BYTE_8_8 = 53, 122 VFMT_NORM_BYTE_8_8_8 = 54, 123 VFMT_NORM_BYTE_8_8_8_8 = 55, 124 VFMT_UINT_10_10_10_2 = 60, 125 VFMT_NORM_UINT_10_10_10_2 = 61, 126 VFMT_INT_10_10_10_2 = 62, 127 VFMT_NORM_INT_10_10_10_2 = 63, 128 }; 129 130 enum a3xx_tex_fmt { 131 TFMT_NORM_USHORT_565 = 4, 132 TFMT_NORM_USHORT_5551 = 6, 133 TFMT_NORM_USHORT_4444 = 7, 134 TFMT_NORM_UINT_X8Z24 = 10, 135 TFMT_NORM_UINT_NV12_UV_TILED = 17, 136 TFMT_NORM_UINT_NV12_Y_TILED = 19, 137 TFMT_NORM_UINT_NV12_UV = 21, 138 TFMT_NORM_UINT_NV12_Y = 23, 139 TFMT_NORM_UINT_I420_Y = 24, 140 TFMT_NORM_UINT_I420_U = 26, 141 TFMT_NORM_UINT_I420_V = 27, 142 TFMT_NORM_UINT_2_10_10_10 = 41, 143 TFMT_NORM_UINT_A8 = 44, 144 TFMT_NORM_UINT_L8_A8 = 47, 145 TFMT_NORM_UINT_8 = 48, 146 TFMT_NORM_UINT_8_8 = 49, 147 TFMT_NORM_UINT_8_8_8 = 50, 148 TFMT_NORM_UINT_8_8_8_8 = 51, 149 TFMT_FLOAT_16 = 64, 150 TFMT_FLOAT_16_16 = 65, 151 TFMT_FLOAT_16_16_16_16 = 67, 152 TFMT_FLOAT_32 = 84, 153 TFMT_FLOAT_32_32 = 85, 154 TFMT_FLOAT_32_32_32_32 = 87, 155 }; 156 157 enum a3xx_tex_fetchsize { 158 TFETCH_DISABLE = 0, 159 TFETCH_1_BYTE = 1, 160 TFETCH_2_BYTE = 2, 161 TFETCH_4_BYTE = 3, 162 TFETCH_8_BYTE = 4, 163 TFETCH_16_BYTE = 5, 164 }; 165 166 enum a3xx_color_fmt { 167 RB_R8G8B8_UNORM = 4, 168 RB_R8G8B8A8_UNORM = 8, 169 RB_Z16_UNORM = 12, 170 RB_A8_UNORM = 20, 171 }; 172 173 enum a3xx_color_swap { 174 WZYX = 0, 175 WXYZ = 1, 176 ZYXW = 2, 177 XYZW = 3, 178 }; 179 180 enum a3xx_msaa_samples { 181 MSAA_ONE = 0, 182 MSAA_TWO = 1, 183 MSAA_FOUR = 2, 184 }; 185 186 enum a3xx_sp_perfcounter_select { 187 SP_FS_CFLOW_INSTRUCTIONS = 12, 188 SP_FS_FULL_ALU_INSTRUCTIONS = 14, 189 SP0_ICL1_MISSES = 26, 190 SP_ALU_ACTIVE_CYCLES = 29, 191 }; 192 193 enum adreno_rb_copy_control_mode { 194 RB_COPY_RESOLVE = 1, 195 RB_COPY_DEPTH_STENCIL = 5, 196 }; 197 198 enum a3xx_tex_filter { 199 A3XX_TEX_NEAREST = 0, 200 A3XX_TEX_LINEAR = 1, 201 }; 202 203 enum a3xx_tex_clamp { 204 A3XX_TEX_REPEAT = 0, 205 A3XX_TEX_CLAMP_TO_EDGE = 1, 206 A3XX_TEX_MIRROR_REPEAT = 2, 207 A3XX_TEX_CLAMP_NONE = 3, 208 }; 209 210 enum a3xx_tex_swiz { 211 A3XX_TEX_X = 0, 212 A3XX_TEX_Y = 1, 213 A3XX_TEX_Z = 2, 214 A3XX_TEX_W = 3, 215 A3XX_TEX_ZERO = 4, 216 A3XX_TEX_ONE = 5, 217 }; 218 219 enum a3xx_tex_type { 220 A3XX_TEX_1D = 0, 221 A3XX_TEX_2D = 1, 222 A3XX_TEX_CUBE = 2, 223 A3XX_TEX_3D = 3, 224 }; 225 226 #define A3XX_INT0_RBBM_GPU_IDLE 0x00000001 227 #define A3XX_INT0_RBBM_AHB_ERROR 0x00000002 228 #define A3XX_INT0_RBBM_REG_TIMEOUT 0x00000004 229 #define A3XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 230 #define A3XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 231 #define A3XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020 232 #define A3XX_INT0_VFD_ERROR 0x00000040 233 #define A3XX_INT0_CP_SW_INT 0x00000080 234 #define A3XX_INT0_CP_T0_PACKET_IN_IB 0x00000100 235 #define A3XX_INT0_CP_OPCODE_ERROR 0x00000200 236 #define A3XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400 237 #define A3XX_INT0_CP_HW_FAULT 0x00000800 238 #define A3XX_INT0_CP_DMA 0x00001000 239 #define A3XX_INT0_CP_IB2_INT 0x00002000 240 #define A3XX_INT0_CP_IB1_INT 0x00004000 241 #define A3XX_INT0_CP_RB_INT 0x00008000 242 #define A3XX_INT0_CP_REG_PROTECT_FAULT 0x00010000 243 #define A3XX_INT0_CP_RB_DONE_TS 0x00020000 244 #define A3XX_INT0_CP_VS_DONE_TS 0x00040000 245 #define A3XX_INT0_CP_PS_DONE_TS 0x00080000 246 #define A3XX_INT0_CACHE_FLUSH_TS 0x00100000 247 #define A3XX_INT0_CP_AHB_ERROR_HALT 0x00200000 248 #define A3XX_INT0_MISC_HANG_DETECT 0x01000000 249 #define A3XX_INT0_UCHE_OOB_ACCESS 0x02000000 250 #define REG_A3XX_RBBM_HW_VERSION 0x00000000 251 252 #define REG_A3XX_RBBM_HW_RELEASE 0x00000001 253 254 #define REG_A3XX_RBBM_HW_CONFIGURATION 0x00000002 255 256 #define REG_A3XX_RBBM_CLOCK_CTL 0x00000010 257 258 #define REG_A3XX_RBBM_SP_HYST_CNT 0x00000012 259 260 #define REG_A3XX_RBBM_SW_RESET_CMD 0x00000018 261 262 #define REG_A3XX_RBBM_AHB_CTL0 0x00000020 263 264 #define REG_A3XX_RBBM_AHB_CTL1 0x00000021 265 266 #define REG_A3XX_RBBM_AHB_CMD 0x00000022 267 268 #define REG_A3XX_RBBM_AHB_ERROR_STATUS 0x00000027 269 270 #define REG_A3XX_RBBM_GPR0_CTL 0x0000002e 271 272 #define REG_A3XX_RBBM_STATUS 0x00000030 273 #define A3XX_RBBM_STATUS_HI_BUSY 0x00000001 274 #define A3XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 275 #define A3XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 276 #define A3XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000 277 #define A3XX_RBBM_STATUS_VBIF_BUSY 0x00008000 278 #define A3XX_RBBM_STATUS_TSE_BUSY 0x00010000 279 #define A3XX_RBBM_STATUS_RAS_BUSY 0x00020000 280 #define A3XX_RBBM_STATUS_RB_BUSY 0x00040000 281 #define A3XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 282 #define A3XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 283 #define A3XX_RBBM_STATUS_VFD_BUSY 0x00200000 284 #define A3XX_RBBM_STATUS_VPC_BUSY 0x00400000 285 #define A3XX_RBBM_STATUS_UCHE_BUSY 0x00800000 286 #define A3XX_RBBM_STATUS_SP_BUSY 0x01000000 287 #define A3XX_RBBM_STATUS_TPL1_BUSY 0x02000000 288 #define A3XX_RBBM_STATUS_MARB_BUSY 0x04000000 289 #define A3XX_RBBM_STATUS_VSC_BUSY 0x08000000 290 #define A3XX_RBBM_STATUS_ARB_BUSY 0x10000000 291 #define A3XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 292 #define A3XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000 293 #define A3XX_RBBM_STATUS_GPU_BUSY 0x80000000 294 295 #define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x00000033 296 297 #define REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL 0x00000050 298 299 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL0 0x00000051 300 301 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL1 0x00000054 302 303 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL2 0x00000057 304 305 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3 0x0000005a 306 307 #define REG_A3XX_RBBM_INT_CLEAR_CMD 0x00000061 308 309 #define REG_A3XX_RBBM_INT_0_MASK 0x00000063 310 311 #define REG_A3XX_RBBM_INT_0_STATUS 0x00000064 312 313 #define REG_A3XX_RBBM_PERFCTR_CTL 0x00000080 314 315 #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0 0x00000081 316 317 #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD1 0x00000082 318 319 #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000084 320 321 #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000085 322 323 #define REG_A3XX_RBBM_PERFCOUNTER0_SELECT 0x00000086 324 325 #define REG_A3XX_RBBM_PERFCOUNTER1_SELECT 0x00000087 326 327 #define REG_A3XX_RBBM_GPU_BUSY_MASKED 0x00000088 328 329 #define REG_A3XX_RBBM_PERFCTR_CP_0_LO 0x00000090 330 331 #define REG_A3XX_RBBM_PERFCTR_CP_0_HI 0x00000091 332 333 #define REG_A3XX_RBBM_PERFCTR_RBBM_0_LO 0x00000092 334 335 #define REG_A3XX_RBBM_PERFCTR_RBBM_0_HI 0x00000093 336 337 #define REG_A3XX_RBBM_PERFCTR_RBBM_1_LO 0x00000094 338 339 #define REG_A3XX_RBBM_PERFCTR_RBBM_1_HI 0x00000095 340 341 #define REG_A3XX_RBBM_PERFCTR_PC_0_LO 0x00000096 342 343 #define REG_A3XX_RBBM_PERFCTR_PC_0_HI 0x00000097 344 345 #define REG_A3XX_RBBM_PERFCTR_PC_1_LO 0x00000098 346 347 #define REG_A3XX_RBBM_PERFCTR_PC_1_HI 0x00000099 348 349 #define REG_A3XX_RBBM_PERFCTR_PC_2_LO 0x0000009a 350 351 #define REG_A3XX_RBBM_PERFCTR_PC_2_HI 0x0000009b 352 353 #define REG_A3XX_RBBM_PERFCTR_PC_3_LO 0x0000009c 354 355 #define REG_A3XX_RBBM_PERFCTR_PC_3_HI 0x0000009d 356 357 #define REG_A3XX_RBBM_PERFCTR_VFD_0_LO 0x0000009e 358 359 #define REG_A3XX_RBBM_PERFCTR_VFD_0_HI 0x0000009f 360 361 #define REG_A3XX_RBBM_PERFCTR_VFD_1_LO 0x000000a0 362 363 #define REG_A3XX_RBBM_PERFCTR_VFD_1_HI 0x000000a1 364 365 #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000a2 366 367 #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000a3 368 369 #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000a4 370 371 #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000a5 372 373 #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000a6 374 375 #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000a7 376 377 #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000a8 378 379 #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000a9 380 381 #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000aa 382 383 #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000ab 384 385 #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000ac 386 387 #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000ad 388 389 #define REG_A3XX_RBBM_PERFCTR_VPC_0_LO 0x000000ae 390 391 #define REG_A3XX_RBBM_PERFCTR_VPC_0_HI 0x000000af 392 393 #define REG_A3XX_RBBM_PERFCTR_VPC_1_LO 0x000000b0 394 395 #define REG_A3XX_RBBM_PERFCTR_VPC_1_HI 0x000000b1 396 397 #define REG_A3XX_RBBM_PERFCTR_TSE_0_LO 0x000000b2 398 399 #define REG_A3XX_RBBM_PERFCTR_TSE_0_HI 0x000000b3 400 401 #define REG_A3XX_RBBM_PERFCTR_TSE_1_LO 0x000000b4 402 403 #define REG_A3XX_RBBM_PERFCTR_TSE_1_HI 0x000000b5 404 405 #define REG_A3XX_RBBM_PERFCTR_RAS_0_LO 0x000000b6 406 407 #define REG_A3XX_RBBM_PERFCTR_RAS_0_HI 0x000000b7 408 409 #define REG_A3XX_RBBM_PERFCTR_RAS_1_LO 0x000000b8 410 411 #define REG_A3XX_RBBM_PERFCTR_RAS_1_HI 0x000000b9 412 413 #define REG_A3XX_RBBM_PERFCTR_UCHE_0_LO 0x000000ba 414 415 #define REG_A3XX_RBBM_PERFCTR_UCHE_0_HI 0x000000bb 416 417 #define REG_A3XX_RBBM_PERFCTR_UCHE_1_LO 0x000000bc 418 419 #define REG_A3XX_RBBM_PERFCTR_UCHE_1_HI 0x000000bd 420 421 #define REG_A3XX_RBBM_PERFCTR_UCHE_2_LO 0x000000be 422 423 #define REG_A3XX_RBBM_PERFCTR_UCHE_2_HI 0x000000bf 424 425 #define REG_A3XX_RBBM_PERFCTR_UCHE_3_LO 0x000000c0 426 427 #define REG_A3XX_RBBM_PERFCTR_UCHE_3_HI 0x000000c1 428 429 #define REG_A3XX_RBBM_PERFCTR_UCHE_4_LO 0x000000c2 430 431 #define REG_A3XX_RBBM_PERFCTR_UCHE_4_HI 0x000000c3 432 433 #define REG_A3XX_RBBM_PERFCTR_UCHE_5_LO 0x000000c4 434 435 #define REG_A3XX_RBBM_PERFCTR_UCHE_5_HI 0x000000c5 436 437 #define REG_A3XX_RBBM_PERFCTR_TP_0_LO 0x000000c6 438 439 #define REG_A3XX_RBBM_PERFCTR_TP_0_HI 0x000000c7 440 441 #define REG_A3XX_RBBM_PERFCTR_TP_1_LO 0x000000c8 442 443 #define REG_A3XX_RBBM_PERFCTR_TP_1_HI 0x000000c9 444 445 #define REG_A3XX_RBBM_PERFCTR_TP_2_LO 0x000000ca 446 447 #define REG_A3XX_RBBM_PERFCTR_TP_2_HI 0x000000cb 448 449 #define REG_A3XX_RBBM_PERFCTR_TP_3_LO 0x000000cc 450 451 #define REG_A3XX_RBBM_PERFCTR_TP_3_HI 0x000000cd 452 453 #define REG_A3XX_RBBM_PERFCTR_TP_4_LO 0x000000ce 454 455 #define REG_A3XX_RBBM_PERFCTR_TP_4_HI 0x000000cf 456 457 #define REG_A3XX_RBBM_PERFCTR_TP_5_LO 0x000000d0 458 459 #define REG_A3XX_RBBM_PERFCTR_TP_5_HI 0x000000d1 460 461 #define REG_A3XX_RBBM_PERFCTR_SP_0_LO 0x000000d2 462 463 #define REG_A3XX_RBBM_PERFCTR_SP_0_HI 0x000000d3 464 465 #define REG_A3XX_RBBM_PERFCTR_SP_1_LO 0x000000d4 466 467 #define REG_A3XX_RBBM_PERFCTR_SP_1_HI 0x000000d5 468 469 #define REG_A3XX_RBBM_PERFCTR_SP_2_LO 0x000000d6 470 471 #define REG_A3XX_RBBM_PERFCTR_SP_2_HI 0x000000d7 472 473 #define REG_A3XX_RBBM_PERFCTR_SP_3_LO 0x000000d8 474 475 #define REG_A3XX_RBBM_PERFCTR_SP_3_HI 0x000000d9 476 477 #define REG_A3XX_RBBM_PERFCTR_SP_4_LO 0x000000da 478 479 #define REG_A3XX_RBBM_PERFCTR_SP_4_HI 0x000000db 480 481 #define REG_A3XX_RBBM_PERFCTR_SP_5_LO 0x000000dc 482 483 #define REG_A3XX_RBBM_PERFCTR_SP_5_HI 0x000000dd 484 485 #define REG_A3XX_RBBM_PERFCTR_SP_6_LO 0x000000de 486 487 #define REG_A3XX_RBBM_PERFCTR_SP_6_HI 0x000000df 488 489 #define REG_A3XX_RBBM_PERFCTR_SP_7_LO 0x000000e0 490 491 #define REG_A3XX_RBBM_PERFCTR_SP_7_HI 0x000000e1 492 493 #define REG_A3XX_RBBM_PERFCTR_RB_0_LO 0x000000e2 494 495 #define REG_A3XX_RBBM_PERFCTR_RB_0_HI 0x000000e3 496 497 #define REG_A3XX_RBBM_PERFCTR_RB_1_LO 0x000000e4 498 499 #define REG_A3XX_RBBM_PERFCTR_RB_1_HI 0x000000e5 500 501 #define REG_A3XX_RBBM_PERFCTR_PWR_0_LO 0x000000ea 502 503 #define REG_A3XX_RBBM_PERFCTR_PWR_0_HI 0x000000eb 504 505 #define REG_A3XX_RBBM_PERFCTR_PWR_1_LO 0x000000ec 506 507 #define REG_A3XX_RBBM_PERFCTR_PWR_1_HI 0x000000ed 508 509 #define REG_A3XX_RBBM_RBBM_CTL 0x00000100 510 511 #define REG_A3XX_RBBM_DEBUG_BUS_CTL 0x00000111 512 513 #define REG_A3XX_RBBM_DEBUG_BUS_DATA_STATUS 0x00000112 514 515 #define REG_A3XX_CP_PFP_UCODE_ADDR 0x000001c9 516 517 #define REG_A3XX_CP_PFP_UCODE_DATA 0x000001ca 518 519 #define REG_A3XX_CP_ROQ_ADDR 0x000001cc 520 521 #define REG_A3XX_CP_ROQ_DATA 0x000001cd 522 523 #define REG_A3XX_CP_MERCIU_ADDR 0x000001d1 524 525 #define REG_A3XX_CP_MERCIU_DATA 0x000001d2 526 527 #define REG_A3XX_CP_MERCIU_DATA2 0x000001d3 528 529 #define REG_A3XX_CP_MEQ_ADDR 0x000001da 530 531 #define REG_A3XX_CP_MEQ_DATA 0x000001db 532 533 #define REG_A3XX_CP_PERFCOUNTER_SELECT 0x00000445 534 535 #define REG_A3XX_CP_HW_FAULT 0x0000045c 536 537 #define REG_A3XX_CP_PROTECT_CTRL 0x0000045e 538 539 #define REG_A3XX_CP_PROTECT_STATUS 0x0000045f 540 541 static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; } 542 543 static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; } 544 545 #define REG_A3XX_CP_AHB_FAULT 0x0000054d 546 547 #define REG_A3XX_GRAS_CL_CLIP_CNTL 0x00002040 548 #define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER 0x00001000 549 #define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 550 #define A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000 551 #define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE 0x00080000 552 #define A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE 0x00100000 553 #define A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE 0x00200000 554 555 #define REG_A3XX_GRAS_CL_GB_CLIP_ADJ 0x00002044 556 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff 557 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0 558 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) 559 { 560 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; 561 } 562 #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00 563 #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10 564 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) 565 { 566 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; 567 } 568 569 #define REG_A3XX_GRAS_CL_VPORT_XOFFSET 0x00002048 570 #define A3XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff 571 #define A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0 572 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) 573 { 574 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK; 575 } 576 577 #define REG_A3XX_GRAS_CL_VPORT_XSCALE 0x00002049 578 #define A3XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff 579 #define A3XX_GRAS_CL_VPORT_XSCALE__SHIFT 0 580 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) 581 { 582 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK; 583 } 584 585 #define REG_A3XX_GRAS_CL_VPORT_YOFFSET 0x0000204a 586 #define A3XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff 587 #define A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0 588 static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val) 589 { 590 return ((fui(val)) << A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_YOFFSET__MASK; 591 } 592 593 #define REG_A3XX_GRAS_CL_VPORT_YSCALE 0x0000204b 594 #define A3XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff 595 #define A3XX_GRAS_CL_VPORT_YSCALE__SHIFT 0 596 static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val) 597 { 598 return ((fui(val)) << A3XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_YSCALE__MASK; 599 } 600 601 #define REG_A3XX_GRAS_CL_VPORT_ZOFFSET 0x0000204c 602 #define A3XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff 603 #define A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0 604 static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val) 605 { 606 return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_ZOFFSET__MASK; 607 } 608 609 #define REG_A3XX_GRAS_CL_VPORT_ZSCALE 0x0000204d 610 #define A3XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff 611 #define A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0 612 static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val) 613 { 614 return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_ZSCALE__MASK; 615 } 616 617 #define REG_A3XX_GRAS_SU_POINT_MINMAX 0x00002068 618 619 #define REG_A3XX_GRAS_SU_POINT_SIZE 0x00002069 620 621 #define REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000206c 622 #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK 0x00ffffff 623 #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT 0 624 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val) 625 { 626 return ((((uint32_t)(val * 40.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK; 627 } 628 629 #define REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000206d 630 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 631 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 632 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 633 { 634 return ((((uint32_t)(val * 44.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 635 } 636 637 #define REG_A3XX_GRAS_SU_MODE_CONTROL 0x00002070 638 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001 639 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002 640 #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007fc 641 #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 2 642 static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(uint32_t val) 643 { 644 return ((val) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; 645 } 646 #define A3XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800 647 648 #define REG_A3XX_GRAS_SC_CONTROL 0x00002072 649 #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x000000f0 650 #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 4 651 static inline uint32_t A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) 652 { 653 return ((val) << A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK; 654 } 655 #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000f00 656 #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 8 657 static inline uint32_t A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val) 658 { 659 return ((val) << A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK; 660 } 661 #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000 662 #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12 663 static inline uint32_t A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) 664 { 665 return ((val) << A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK; 666 } 667 668 #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL 0x00002074 669 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 670 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 671 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 672 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 673 { 674 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; 675 } 676 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 677 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 678 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 679 { 680 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; 681 } 682 683 #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_BR 0x00002075 684 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 685 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 686 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 687 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 688 { 689 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; 690 } 691 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 692 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 693 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 694 { 695 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; 696 } 697 698 #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL 0x00002079 699 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 700 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 701 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 702 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 703 { 704 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 705 } 706 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 707 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 708 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 709 { 710 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 711 } 712 713 #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000207a 714 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 715 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 716 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 717 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 718 { 719 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 720 } 721 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 722 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 723 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 724 { 725 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 726 } 727 728 #define REG_A3XX_RB_MODE_CONTROL 0x000020c0 729 #define A3XX_RB_MODE_CONTROL_GMEM_BYPASS 0x00000080 730 #define A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK 0x00000700 731 #define A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT 8 732 static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val) 733 { 734 return ((val) << A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT) & A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK; 735 } 736 #define A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE 0x00008000 737 #define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE 0x00010000 738 739 #define REG_A3XX_RB_RENDER_CONTROL 0x000020c1 740 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK 0x00000ff0 741 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT 4 742 static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val) 743 { 744 return ((val >> 5) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK; 745 } 746 #define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00001000 747 #define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM 0x00002000 748 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK 0x07000000 749 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT 24 750 static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 751 { 752 return ((val) << A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK; 753 } 754 755 #define REG_A3XX_RB_MSAA_CONTROL 0x000020c2 756 #define A3XX_RB_MSAA_CONTROL_DISABLE 0x00000400 757 #define A3XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000f000 758 #define A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 12 759 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val) 760 { 761 return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLES__MASK; 762 } 763 #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK 0xffff0000 764 #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT 16 765 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val) 766 { 767 return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK; 768 } 769 770 #define REG_A3XX_UNKNOWN_20C3 0x000020c3 771 772 static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; } 773 774 static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; } 775 #define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008 776 #define A3XX_RB_MRT_CONTROL_BLEND 0x00000010 777 #define A3XX_RB_MRT_CONTROL_BLEND2 0x00000020 778 #define A3XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00 779 #define A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8 780 static inline uint32_t A3XX_RB_MRT_CONTROL_ROP_CODE(uint32_t val) 781 { 782 return ((val) << A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A3XX_RB_MRT_CONTROL_ROP_CODE__MASK; 783 } 784 #define A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK 0x00003000 785 #define A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT 12 786 static inline uint32_t A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) 787 { 788 return ((val) << A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT) & A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK; 789 } 790 #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000 791 #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24 792 static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 793 { 794 return ((val) << A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 795 } 796 797 static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; } 798 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f 799 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 800 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val) 801 { 802 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 803 } 804 #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0 805 #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6 806 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val) 807 { 808 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 809 } 810 #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00000c00 811 #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 10 812 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 813 { 814 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 815 } 816 #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xfffe0000 817 #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 17 818 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) 819 { 820 return ((val >> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; 821 } 822 823 static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; } 824 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK 0xfffffff0 825 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT 4 826 static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val) 827 { 828 return ((val >> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK; 829 } 830 831 static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; } 832 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 833 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 834 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 835 { 836 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 837 } 838 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 839 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 840 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum adreno_rb_blend_opcode val) 841 { 842 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 843 } 844 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 845 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 846 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 847 { 848 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 849 } 850 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 851 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 852 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 853 { 854 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 855 } 856 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 857 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 858 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum adreno_rb_blend_opcode val) 859 { 860 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 861 } 862 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 863 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 864 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 865 { 866 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 867 } 868 #define A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE 0x20000000 869 870 #define REG_A3XX_RB_BLEND_RED 0x000020e4 871 #define A3XX_RB_BLEND_RED_UINT__MASK 0x000000ff 872 #define A3XX_RB_BLEND_RED_UINT__SHIFT 0 873 static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val) 874 { 875 return ((val) << A3XX_RB_BLEND_RED_UINT__SHIFT) & A3XX_RB_BLEND_RED_UINT__MASK; 876 } 877 #define A3XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 878 #define A3XX_RB_BLEND_RED_FLOAT__SHIFT 16 879 static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val) 880 { 881 return ((util_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK; 882 } 883 884 #define REG_A3XX_RB_BLEND_GREEN 0x000020e5 885 #define A3XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff 886 #define A3XX_RB_BLEND_GREEN_UINT__SHIFT 0 887 static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val) 888 { 889 return ((val) << A3XX_RB_BLEND_GREEN_UINT__SHIFT) & A3XX_RB_BLEND_GREEN_UINT__MASK; 890 } 891 #define A3XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 892 #define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 893 static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val) 894 { 895 return ((util_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK; 896 } 897 898 #define REG_A3XX_RB_BLEND_BLUE 0x000020e6 899 #define A3XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff 900 #define A3XX_RB_BLEND_BLUE_UINT__SHIFT 0 901 static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val) 902 { 903 return ((val) << A3XX_RB_BLEND_BLUE_UINT__SHIFT) & A3XX_RB_BLEND_BLUE_UINT__MASK; 904 } 905 #define A3XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 906 #define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 907 static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val) 908 { 909 return ((util_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK; 910 } 911 912 #define REG_A3XX_RB_BLEND_ALPHA 0x000020e7 913 #define A3XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff 914 #define A3XX_RB_BLEND_ALPHA_UINT__SHIFT 0 915 static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val) 916 { 917 return ((val) << A3XX_RB_BLEND_ALPHA_UINT__SHIFT) & A3XX_RB_BLEND_ALPHA_UINT__MASK; 918 } 919 #define A3XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 920 #define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 921 static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val) 922 { 923 return ((util_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK; 924 } 925 926 #define REG_A3XX_UNKNOWN_20E8 0x000020e8 927 928 #define REG_A3XX_UNKNOWN_20E9 0x000020e9 929 930 #define REG_A3XX_UNKNOWN_20EA 0x000020ea 931 932 #define REG_A3XX_UNKNOWN_20EB 0x000020eb 933 934 #define REG_A3XX_RB_COPY_CONTROL 0x000020ec 935 #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003 936 #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0 937 static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) 938 { 939 return ((val) << A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK; 940 } 941 #define A3XX_RB_COPY_CONTROL_MODE__MASK 0x00000070 942 #define A3XX_RB_COPY_CONTROL_MODE__SHIFT 4 943 static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) 944 { 945 return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK; 946 } 947 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xfffffc00 948 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 10 949 static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) 950 { 951 return ((val >> 10) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK; 952 } 953 954 #define REG_A3XX_RB_COPY_DEST_BASE 0x000020ed 955 #define A3XX_RB_COPY_DEST_BASE_BASE__MASK 0xfffffff0 956 #define A3XX_RB_COPY_DEST_BASE_BASE__SHIFT 4 957 static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val) 958 { 959 return ((val >> 5) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A3XX_RB_COPY_DEST_BASE_BASE__MASK; 960 } 961 962 #define REG_A3XX_RB_COPY_DEST_PITCH 0x000020ee 963 #define A3XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff 964 #define A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0 965 static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) 966 { 967 return ((val >> 5) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK; 968 } 969 970 #define REG_A3XX_RB_COPY_DEST_INFO 0x000020ef 971 #define A3XX_RB_COPY_DEST_INFO_TILE__MASK 0x00000003 972 #define A3XX_RB_COPY_DEST_INFO_TILE__SHIFT 0 973 static inline uint32_t A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val) 974 { 975 return ((val) << A3XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A3XX_RB_COPY_DEST_INFO_TILE__MASK; 976 } 977 #define A3XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc 978 #define A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2 979 static inline uint32_t A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val) 980 { 981 return ((val) << A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A3XX_RB_COPY_DEST_INFO_FORMAT__MASK; 982 } 983 #define A3XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 984 #define A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 985 static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) 986 { 987 return ((val) << A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A3XX_RB_COPY_DEST_INFO_SWAP__MASK; 988 } 989 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000 990 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14 991 static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) 992 { 993 return ((val) << A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK; 994 } 995 #define A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000 996 #define A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18 997 static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) 998 { 999 return ((val) << A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK; 1000 } 1001 1002 #define REG_A3XX_RB_DEPTH_CONTROL 0x00002100 1003 #define A3XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002 1004 #define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004 1005 #define A3XX_RB_DEPTH_CONTROL_EARLY_Z_ENABLE 0x00000008 1006 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070 1007 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4 1008 static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) 1009 { 1010 return ((val) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK; 1011 } 1012 #define A3XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080 1013 #define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000 1014 1015 #define REG_A3XX_UNKNOWN_2101 0x00002101 1016 1017 #define REG_A3XX_RB_DEPTH_INFO 0x00002102 1018 #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001 1019 #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 1020 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) 1021 { 1022 return ((val) << A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 1023 } 1024 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff800 1025 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 11 1026 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 1027 { 1028 return ((val >> 10) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 1029 } 1030 1031 #define REG_A3XX_RB_DEPTH_PITCH 0x00002103 1032 #define A3XX_RB_DEPTH_PITCH__MASK 0xffffffff 1033 #define A3XX_RB_DEPTH_PITCH__SHIFT 0 1034 static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val) 1035 { 1036 return ((val >> 3) << A3XX_RB_DEPTH_PITCH__SHIFT) & A3XX_RB_DEPTH_PITCH__MASK; 1037 } 1038 1039 #define REG_A3XX_RB_STENCIL_CONTROL 0x00002104 1040 #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 1041 #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000004 1042 #define A3XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 1043 #define A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 1044 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 1045 { 1046 return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC__MASK; 1047 } 1048 #define A3XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 1049 #define A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 1050 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 1051 { 1052 return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL__MASK; 1053 } 1054 #define A3XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 1055 #define A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 1056 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 1057 { 1058 return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS__MASK; 1059 } 1060 #define A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 1061 #define A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 1062 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 1063 { 1064 return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 1065 } 1066 #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 1067 #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 1068 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 1069 { 1070 return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 1071 } 1072 #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 1073 #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 1074 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 1075 { 1076 return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 1077 } 1078 #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 1079 #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 1080 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 1081 { 1082 return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 1083 } 1084 #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 1085 #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 1086 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 1087 { 1088 return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 1089 } 1090 1091 #define REG_A3XX_UNKNOWN_2105 0x00002105 1092 1093 #define REG_A3XX_UNKNOWN_2106 0x00002106 1094 1095 #define REG_A3XX_UNKNOWN_2107 0x00002107 1096 1097 #define REG_A3XX_RB_STENCILREFMASK 0x00002108 1098 #define A3XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 1099 #define A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 1100 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 1101 { 1102 return ((val) << A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILREF__MASK; 1103 } 1104 #define A3XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 1105 #define A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 1106 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 1107 { 1108 return ((val) << A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILMASK__MASK; 1109 } 1110 #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 1111 #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 1112 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 1113 { 1114 return ((val) << A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 1115 } 1116 1117 #define REG_A3XX_RB_STENCILREFMASK_BF 0x00002109 1118 #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 1119 #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 1120 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 1121 { 1122 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 1123 } 1124 #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 1125 #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 1126 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 1127 { 1128 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 1129 } 1130 #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 1131 #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 1132 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 1133 { 1134 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 1135 } 1136 1137 #define REG_A3XX_PA_SC_WINDOW_OFFSET 0x0000210e 1138 #define A3XX_PA_SC_WINDOW_OFFSET_X__MASK 0x0000ffff 1139 #define A3XX_PA_SC_WINDOW_OFFSET_X__SHIFT 0 1140 static inline uint32_t A3XX_PA_SC_WINDOW_OFFSET_X(uint32_t val) 1141 { 1142 return ((val) << A3XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A3XX_PA_SC_WINDOW_OFFSET_X__MASK; 1143 } 1144 #define A3XX_PA_SC_WINDOW_OFFSET_Y__MASK 0xffff0000 1145 #define A3XX_PA_SC_WINDOW_OFFSET_Y__SHIFT 16 1146 static inline uint32_t A3XX_PA_SC_WINDOW_OFFSET_Y(uint32_t val) 1147 { 1148 return ((val) << A3XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A3XX_PA_SC_WINDOW_OFFSET_Y__MASK; 1149 } 1150 1151 #define REG_A3XX_PC_VSTREAM_CONTROL 0x000021e4 1152 1153 #define REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL 0x000021ea 1154 1155 #define REG_A3XX_PC_PRIM_VTX_CNTL 0x000021ec 1156 #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK 0x0000001f 1157 #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT 0 1158 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val) 1159 { 1160 return ((val) << A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK; 1161 } 1162 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK 0x000000e0 1163 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT 5 1164 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 1165 { 1166 return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK; 1167 } 1168 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK 0x00000700 1169 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT 8 1170 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 1171 { 1172 return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK; 1173 } 1174 #define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000 1175 1176 #define REG_A3XX_PC_RESTART_INDEX 0x000021ed 1177 1178 #define REG_A3XX_HLSQ_CONTROL_0_REG 0x00002200 1179 #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010 1180 #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4 1181 static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) 1182 { 1183 return ((val) << A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; 1184 } 1185 #define A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040 1186 #define A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200 1187 #define A3XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400 1188 #define A3XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000 1189 #define A3XX_HLSQ_CONTROL_0_REG_CONSTSWITCHMODE 0x08000000 1190 #define A3XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000 1191 #define A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000 1192 #define A3XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000 1193 #define A3XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000 1194 1195 #define REG_A3XX_HLSQ_CONTROL_1_REG 0x00002201 1196 #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040 1197 #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6 1198 static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) 1199 { 1200 return ((val) << A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK; 1201 } 1202 #define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100 1203 #define A3XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200 1204 1205 #define REG_A3XX_HLSQ_CONTROL_2_REG 0x00002202 1206 #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000 1207 #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26 1208 static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) 1209 { 1210 return ((val) << A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK; 1211 } 1212 1213 #define REG_A3XX_HLSQ_CONTROL_3_REG 0x00002203 1214 1215 #define REG_A3XX_HLSQ_VS_CONTROL_REG 0x00002204 1216 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff 1217 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0 1218 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) 1219 { 1220 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK; 1221 } 1222 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000 1223 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12 1224 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) 1225 { 1226 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK; 1227 } 1228 #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 1229 #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24 1230 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) 1231 { 1232 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK; 1233 } 1234 1235 #define REG_A3XX_HLSQ_FS_CONTROL_REG 0x00002205 1236 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff 1237 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0 1238 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) 1239 { 1240 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK; 1241 } 1242 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000 1243 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12 1244 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) 1245 { 1246 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK; 1247 } 1248 #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 1249 #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24 1250 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) 1251 { 1252 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK; 1253 } 1254 1255 #define REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG 0x00002206 1256 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff 1257 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT 0 1258 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val) 1259 { 1260 return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK; 1261 } 1262 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000 1263 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT 16 1264 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val) 1265 { 1266 return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK; 1267 } 1268 1269 #define REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG 0x00002207 1270 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff 1271 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT 0 1272 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val) 1273 { 1274 return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK; 1275 } 1276 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000 1277 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT 16 1278 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val) 1279 { 1280 return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK; 1281 } 1282 1283 #define REG_A3XX_HLSQ_CL_NDRANGE_0_REG 0x0000220a 1284 1285 #define REG_A3XX_HLSQ_CL_NDRANGE_1_REG 0x0000220b 1286 1287 #define REG_A3XX_HLSQ_CL_NDRANGE_2_REG 0x0000220c 1288 1289 #define REG_A3XX_HLSQ_CL_CONTROL_0_REG 0x00002211 1290 1291 #define REG_A3XX_HLSQ_CL_CONTROL_1_REG 0x00002212 1292 1293 #define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG 0x00002214 1294 1295 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG 0x00002215 1296 1297 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG 0x00002217 1298 1299 #define REG_A3XX_HLSQ_CL_WG_OFFSET_REG 0x0000221a 1300 1301 #define REG_A3XX_VFD_CONTROL_0 0x00002240 1302 #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x0003ffff 1303 #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0 1304 static inline uint32_t A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) 1305 { 1306 return ((val) << A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK; 1307 } 1308 #define A3XX_VFD_CONTROL_0_PACKETSIZE__MASK 0x003c0000 1309 #define A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT 18 1310 static inline uint32_t A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val) 1311 { 1312 return ((val) << A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT) & A3XX_VFD_CONTROL_0_PACKETSIZE__MASK; 1313 } 1314 #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x07c00000 1315 #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 22 1316 static inline uint32_t A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) 1317 { 1318 return ((val) << A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK; 1319 } 1320 #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xf8000000 1321 #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 27 1322 static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) 1323 { 1324 return ((val) << A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK; 1325 } 1326 1327 #define REG_A3XX_VFD_CONTROL_1 0x00002241 1328 #define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff 1329 #define A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0 1330 static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) 1331 { 1332 return ((val) << A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK; 1333 } 1334 #define A3XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000 1335 #define A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16 1336 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 1337 { 1338 return ((val) << A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A3XX_VFD_CONTROL_1_REGID4VTX__MASK; 1339 } 1340 #define A3XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000 1341 #define A3XX_VFD_CONTROL_1_REGID4INST__SHIFT 24 1342 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 1343 { 1344 return ((val) << A3XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A3XX_VFD_CONTROL_1_REGID4INST__MASK; 1345 } 1346 1347 #define REG_A3XX_VFD_INDEX_MIN 0x00002242 1348 1349 #define REG_A3XX_VFD_INDEX_MAX 0x00002243 1350 1351 #define REG_A3XX_VFD_INSTANCEID_OFFSET 0x00002244 1352 1353 #define REG_A3XX_VFD_INDEX_OFFSET 0x00002245 1354 1355 static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0) { return 0x00002246 + 0x2*i0; } 1356 1357 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; } 1358 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f 1359 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0 1360 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) 1361 { 1362 return ((val) << A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK; 1363 } 1364 #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80 1365 #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7 1366 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) 1367 { 1368 return ((val) << A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK; 1369 } 1370 #define A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00020000 1371 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK 0x00fc0000 1372 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT 18 1373 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val) 1374 { 1375 return ((val) << A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK; 1376 } 1377 #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK 0xff000000 1378 #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT 24 1379 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val) 1380 { 1381 return ((val) << A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK; 1382 } 1383 1384 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x00002247 + 0x2*i0; } 1385 1386 static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0) { return 0x00002266 + 0x1*i0; } 1387 1388 static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x00002266 + 0x1*i0; } 1389 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f 1390 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0 1391 static inline uint32_t A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) 1392 { 1393 return ((val) << A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK; 1394 } 1395 #define A3XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010 1396 #define A3XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0 1397 #define A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6 1398 static inline uint32_t A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val) 1399 { 1400 return ((val) << A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A3XX_VFD_DECODE_INSTR_FORMAT__MASK; 1401 } 1402 #define A3XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000 1403 #define A3XX_VFD_DECODE_INSTR_REGID__SHIFT 12 1404 static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val) 1405 { 1406 return ((val) << A3XX_VFD_DECODE_INSTR_REGID__SHIFT) & A3XX_VFD_DECODE_INSTR_REGID__MASK; 1407 } 1408 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000 1409 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24 1410 static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) 1411 { 1412 return ((val) << A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK; 1413 } 1414 #define A3XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000 1415 #define A3XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000 1416 1417 #define REG_A3XX_VFD_VS_THREADING_THRESHOLD 0x0000227e 1418 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK 0x0000000f 1419 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT 0 1420 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val) 1421 { 1422 return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK; 1423 } 1424 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK 0x0000ff00 1425 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT 8 1426 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val) 1427 { 1428 return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK; 1429 } 1430 1431 #define REG_A3XX_VPC_ATTR 0x00002280 1432 #define A3XX_VPC_ATTR_TOTALATTR__MASK 0x00000fff 1433 #define A3XX_VPC_ATTR_TOTALATTR__SHIFT 0 1434 static inline uint32_t A3XX_VPC_ATTR_TOTALATTR(uint32_t val) 1435 { 1436 return ((val) << A3XX_VPC_ATTR_TOTALATTR__SHIFT) & A3XX_VPC_ATTR_TOTALATTR__MASK; 1437 } 1438 #define A3XX_VPC_ATTR_THRDASSIGN__MASK 0x0ffff000 1439 #define A3XX_VPC_ATTR_THRDASSIGN__SHIFT 12 1440 static inline uint32_t A3XX_VPC_ATTR_THRDASSIGN(uint32_t val) 1441 { 1442 return ((val) << A3XX_VPC_ATTR_THRDASSIGN__SHIFT) & A3XX_VPC_ATTR_THRDASSIGN__MASK; 1443 } 1444 #define A3XX_VPC_ATTR_LMSIZE__MASK 0xf0000000 1445 #define A3XX_VPC_ATTR_LMSIZE__SHIFT 28 1446 static inline uint32_t A3XX_VPC_ATTR_LMSIZE(uint32_t val) 1447 { 1448 return ((val) << A3XX_VPC_ATTR_LMSIZE__SHIFT) & A3XX_VPC_ATTR_LMSIZE__MASK; 1449 } 1450 1451 #define REG_A3XX_VPC_PACK 0x00002281 1452 #define A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00 1453 #define A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8 1454 static inline uint32_t A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) 1455 { 1456 return ((val) << A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK; 1457 } 1458 #define A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000 1459 #define A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16 1460 static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) 1461 { 1462 return ((val) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK; 1463 } 1464 1465 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002282 + 0x1*i0; } 1466 1467 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002282 + 0x1*i0; } 1468 1469 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; } 1470 1471 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; } 1472 1473 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0 0x0000228a 1474 1475 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_1 0x0000228b 1476 1477 #define REG_A3XX_SP_SP_CTRL_REG 0x000022c0 1478 #define A3XX_SP_SP_CTRL_REG_RESOLVE 0x00010000 1479 #define A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK 0x000c0000 1480 #define A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT 18 1481 static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val) 1482 { 1483 return ((val) << A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK; 1484 } 1485 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK 0x00300000 1486 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT 20 1487 static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val) 1488 { 1489 return ((val) << A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK; 1490 } 1491 #define A3XX_SP_SP_CTRL_REG_LOMODE__MASK 0x00c00000 1492 #define A3XX_SP_SP_CTRL_REG_LOMODE__SHIFT 22 1493 static inline uint32_t A3XX_SP_SP_CTRL_REG_LOMODE(uint32_t val) 1494 { 1495 return ((val) << A3XX_SP_SP_CTRL_REG_LOMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_LOMODE__MASK; 1496 } 1497 1498 #define REG_A3XX_SP_VS_CTRL_REG0 0x000022c4 1499 #define A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 1500 #define A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 1501 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 1502 { 1503 return ((val) << A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK; 1504 } 1505 #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002 1506 #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1 1507 static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) 1508 { 1509 return ((val) << A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK; 1510 } 1511 #define A3XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004 1512 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 1513 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 1514 static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 1515 { 1516 return ((val) << A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 1517 } 1518 #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 1519 #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 1520 static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 1521 { 1522 return ((val) << A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 1523 } 1524 #define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 1525 #define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 1526 static inline uint32_t A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 1527 { 1528 return ((val) << A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK; 1529 } 1530 #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000 1531 #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20 1532 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 1533 { 1534 return ((val) << A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; 1535 } 1536 #define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000 1537 #define A3XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000 1538 #define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK 0xff000000 1539 #define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT 24 1540 static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val) 1541 { 1542 return ((val) << A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG0_LENGTH__MASK; 1543 } 1544 1545 #define REG_A3XX_SP_VS_CTRL_REG1 0x000022c5 1546 #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff 1547 #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0 1548 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) 1549 { 1550 return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK; 1551 } 1552 #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00 1553 #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10 1554 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) 1555 { 1556 return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK; 1557 } 1558 #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x3f000000 1559 #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24 1560 static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) 1561 { 1562 return ((val) << A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK; 1563 } 1564 1565 #define REG_A3XX_SP_VS_PARAM_REG 0x000022c6 1566 #define A3XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff 1567 #define A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0 1568 static inline uint32_t A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) 1569 { 1570 return ((val) << A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_POSREGID__MASK; 1571 } 1572 #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00 1573 #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8 1574 static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) 1575 { 1576 return ((val) << A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK; 1577 } 1578 #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000 1579 #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20 1580 static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) 1581 { 1582 return ((val) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; 1583 } 1584 1585 static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 1586 1587 static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 1588 #define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff 1589 #define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 1590 static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 1591 { 1592 return ((val) << A3XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_A_REGID__MASK; 1593 } 1594 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00 1595 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9 1596 static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 1597 { 1598 return ((val) << A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 1599 } 1600 #define A3XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000 1601 #define A3XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 1602 static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 1603 { 1604 return ((val) << A3XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_B_REGID__MASK; 1605 } 1606 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000 1607 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25 1608 static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 1609 { 1610 return ((val) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 1611 } 1612 1613 static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; } 1614 1615 static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; } 1616 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 1617 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 1618 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 1619 { 1620 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 1621 } 1622 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 1623 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 1624 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 1625 { 1626 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 1627 } 1628 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 1629 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 1630 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 1631 { 1632 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 1633 } 1634 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 1635 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 1636 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 1637 { 1638 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 1639 } 1640 1641 #define REG_A3XX_SP_VS_OBJ_OFFSET_REG 0x000022d4 1642 #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1643 #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1644 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1645 { 1646 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1647 } 1648 #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1649 #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1650 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1651 { 1652 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1653 } 1654 1655 #define REG_A3XX_SP_VS_OBJ_START_REG 0x000022d5 1656 1657 #define REG_A3XX_SP_VS_PVT_MEM_CTRL_REG 0x000022d6 1658 1659 #define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG 0x000022d7 1660 1661 #define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG 0x000022d8 1662 1663 #define REG_A3XX_SP_VS_LENGTH_REG 0x000022df 1664 #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff 1665 #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT 0 1666 static inline uint32_t A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val) 1667 { 1668 return ((val) << A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK; 1669 } 1670 1671 #define REG_A3XX_SP_FS_CTRL_REG0 0x000022e0 1672 #define A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 1673 #define A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 1674 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 1675 { 1676 return ((val) << A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK; 1677 } 1678 #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002 1679 #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1 1680 static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) 1681 { 1682 return ((val) << A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK; 1683 } 1684 #define A3XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004 1685 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 1686 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 1687 static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 1688 { 1689 return ((val) << A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 1690 } 1691 #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 1692 #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 1693 static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 1694 { 1695 return ((val) << A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 1696 } 1697 #define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 1698 #define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 1699 static inline uint32_t A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 1700 { 1701 return ((val) << A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK; 1702 } 1703 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 1704 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 1705 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 1706 { 1707 return ((val) << A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 1708 } 1709 #define A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000 1710 #define A3XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000 1711 #define A3XX_SP_FS_CTRL_REG0_LENGTH__MASK 0xff000000 1712 #define A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT 24 1713 static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val) 1714 { 1715 return ((val) << A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG0_LENGTH__MASK; 1716 } 1717 1718 #define REG_A3XX_SP_FS_CTRL_REG1 0x000022e1 1719 #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff 1720 #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0 1721 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) 1722 { 1723 return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK; 1724 } 1725 #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00 1726 #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10 1727 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) 1728 { 1729 return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK; 1730 } 1731 #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x00f00000 1732 #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 20 1733 static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) 1734 { 1735 return ((val) << A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK; 1736 } 1737 #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK 0x3f000000 1738 #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT 24 1739 static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val) 1740 { 1741 return ((val) << A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT) & A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK; 1742 } 1743 1744 #define REG_A3XX_SP_FS_OBJ_OFFSET_REG 0x000022e2 1745 #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1746 #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1747 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1748 { 1749 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1750 } 1751 #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1752 #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1753 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1754 { 1755 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1756 } 1757 1758 #define REG_A3XX_SP_FS_OBJ_START_REG 0x000022e3 1759 1760 #define REG_A3XX_SP_FS_PVT_MEM_CTRL_REG 0x000022e4 1761 1762 #define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG 0x000022e5 1763 1764 #define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG 0x000022e6 1765 1766 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0 0x000022e8 1767 1768 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1 0x000022e9 1769 1770 #define REG_A3XX_SP_FS_OUTPUT_REG 0x000022ec 1771 1772 static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0) { return 0x000022f0 + 0x1*i0; } 1773 1774 static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f0 + 0x1*i0; } 1775 #define A3XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff 1776 #define A3XX_SP_FS_MRT_REG_REGID__SHIFT 0 1777 static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val) 1778 { 1779 return ((val) << A3XX_SP_FS_MRT_REG_REGID__SHIFT) & A3XX_SP_FS_MRT_REG_REGID__MASK; 1780 } 1781 #define A3XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100 1782 1783 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0) { return 0x000022f4 + 0x1*i0; } 1784 1785 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0) { return 0x000022f4 + 0x1*i0; } 1786 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK 0x0000003f 1787 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT 0 1788 static inline uint32_t A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val) 1789 { 1790 return ((val) << A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT) & A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK; 1791 } 1792 1793 #define REG_A3XX_SP_FS_LENGTH_REG 0x000022ff 1794 #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff 1795 #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT 0 1796 static inline uint32_t A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val) 1797 { 1798 return ((val) << A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK; 1799 } 1800 1801 #define REG_A3XX_TPL1_TP_VS_TEX_OFFSET 0x00002340 1802 #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff 1803 #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0 1804 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) 1805 { 1806 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK; 1807 } 1808 #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00 1809 #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8 1810 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) 1811 { 1812 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK; 1813 } 1814 #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000 1815 #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT 16 1816 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val) 1817 { 1818 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK; 1819 } 1820 1821 #define REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002341 1822 1823 #define REG_A3XX_TPL1_TP_FS_TEX_OFFSET 0x00002342 1824 #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff 1825 #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0 1826 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) 1827 { 1828 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK; 1829 } 1830 #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00 1831 #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8 1832 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) 1833 { 1834 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK; 1835 } 1836 #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000 1837 #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT 16 1838 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val) 1839 { 1840 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK; 1841 } 1842 1843 #define REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x00002343 1844 1845 #define REG_A3XX_VBIF_CLKON 0x00003001 1846 1847 #define REG_A3XX_VBIF_FIXED_SORT_EN 0x0000300c 1848 1849 #define REG_A3XX_VBIF_FIXED_SORT_SEL0 0x0000300d 1850 1851 #define REG_A3XX_VBIF_FIXED_SORT_SEL1 0x0000300e 1852 1853 #define REG_A3XX_VBIF_ABIT_SORT 0x0000301c 1854 1855 #define REG_A3XX_VBIF_ABIT_SORT_CONF 0x0000301d 1856 1857 #define REG_A3XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 1858 1859 #define REG_A3XX_VBIF_IN_RD_LIM_CONF0 0x0000302c 1860 1861 #define REG_A3XX_VBIF_IN_RD_LIM_CONF1 0x0000302d 1862 1863 #define REG_A3XX_VBIF_IN_WR_LIM_CONF0 0x00003030 1864 1865 #define REG_A3XX_VBIF_IN_WR_LIM_CONF1 0x00003031 1866 1867 #define REG_A3XX_VBIF_OUT_RD_LIM_CONF0 0x00003034 1868 1869 #define REG_A3XX_VBIF_OUT_WR_LIM_CONF0 0x00003035 1870 1871 #define REG_A3XX_VBIF_DDR_OUT_MAX_BURST 0x00003036 1872 1873 #define REG_A3XX_VBIF_ARB_CTL 0x0000303c 1874 1875 #define REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049 1876 1877 #define REG_A3XX_VBIF_OUT_AXI_AMEMTYPE_CONF0 0x00003058 1878 1879 #define REG_A3XX_VBIF_OUT_AXI_AOOO_EN 0x0000305e 1880 1881 #define REG_A3XX_VBIF_OUT_AXI_AOOO 0x0000305f 1882 1883 #define REG_A3XX_VSC_BIN_SIZE 0x00000c01 1884 #define A3XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 1885 #define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 1886 static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 1887 { 1888 return ((val >> 5) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A3XX_VSC_BIN_SIZE_WIDTH__MASK; 1889 } 1890 #define A3XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 1891 #define A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5 1892 static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 1893 { 1894 return ((val >> 5) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK; 1895 } 1896 1897 #define REG_A3XX_VSC_SIZE_ADDRESS 0x00000c02 1898 1899 static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 1900 1901 static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 1902 #define A3XX_VSC_PIPE_CONFIG_X__MASK 0x000003ff 1903 #define A3XX_VSC_PIPE_CONFIG_X__SHIFT 0 1904 static inline uint32_t A3XX_VSC_PIPE_CONFIG_X(uint32_t val) 1905 { 1906 return ((val) << A3XX_VSC_PIPE_CONFIG_X__SHIFT) & A3XX_VSC_PIPE_CONFIG_X__MASK; 1907 } 1908 #define A3XX_VSC_PIPE_CONFIG_Y__MASK 0x000ffc00 1909 #define A3XX_VSC_PIPE_CONFIG_Y__SHIFT 10 1910 static inline uint32_t A3XX_VSC_PIPE_CONFIG_Y(uint32_t val) 1911 { 1912 return ((val) << A3XX_VSC_PIPE_CONFIG_Y__SHIFT) & A3XX_VSC_PIPE_CONFIG_Y__MASK; 1913 } 1914 #define A3XX_VSC_PIPE_CONFIG_W__MASK 0x00f00000 1915 #define A3XX_VSC_PIPE_CONFIG_W__SHIFT 20 1916 static inline uint32_t A3XX_VSC_PIPE_CONFIG_W(uint32_t val) 1917 { 1918 return ((val) << A3XX_VSC_PIPE_CONFIG_W__SHIFT) & A3XX_VSC_PIPE_CONFIG_W__MASK; 1919 } 1920 #define A3XX_VSC_PIPE_CONFIG_H__MASK 0x0f000000 1921 #define A3XX_VSC_PIPE_CONFIG_H__SHIFT 24 1922 static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val) 1923 { 1924 return ((val) << A3XX_VSC_PIPE_CONFIG_H__SHIFT) & A3XX_VSC_PIPE_CONFIG_H__MASK; 1925 } 1926 1927 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } 1928 1929 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } 1930 1931 #define REG_A3XX_UNKNOWN_0C3D 0x00000c3d 1932 1933 #define REG_A3XX_PC_PERFCOUNTER0_SELECT 0x00000c48 1934 1935 #define REG_A3XX_PC_PERFCOUNTER1_SELECT 0x00000c49 1936 1937 #define REG_A3XX_PC_PERFCOUNTER2_SELECT 0x00000c4a 1938 1939 #define REG_A3XX_PC_PERFCOUNTER3_SELECT 0x00000c4b 1940 1941 #define REG_A3XX_UNKNOWN_0C81 0x00000c81 1942 1943 #define REG_A3XX_GRAS_PERFCOUNTER0_SELECT 0x00000c88 1944 1945 #define REG_A3XX_GRAS_PERFCOUNTER1_SELECT 0x00000c89 1946 1947 #define REG_A3XX_GRAS_PERFCOUNTER2_SELECT 0x00000c8a 1948 1949 #define REG_A3XX_GRAS_PERFCOUNTER3_SELECT 0x00000c8b 1950 1951 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } 1952 1953 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } 1954 1955 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0) { return 0x00000ca1 + 0x4*i0; } 1956 1957 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0) { return 0x00000ca2 + 0x4*i0; } 1958 1959 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) { return 0x00000ca3 + 0x4*i0; } 1960 1961 #define REG_A3XX_RB_GMEM_BASE_ADDR 0x00000cc0 1962 1963 #define REG_A3XX_RB_PERFCOUNTER0_SELECT 0x00000cc6 1964 1965 #define REG_A3XX_RB_PERFCOUNTER1_SELECT 0x00000cc7 1966 1967 #define REG_A3XX_RB_WINDOW_SIZE 0x00000ce0 1968 #define A3XX_RB_WINDOW_SIZE_WIDTH__MASK 0x00003fff 1969 #define A3XX_RB_WINDOW_SIZE_WIDTH__SHIFT 0 1970 static inline uint32_t A3XX_RB_WINDOW_SIZE_WIDTH(uint32_t val) 1971 { 1972 return ((val) << A3XX_RB_WINDOW_SIZE_WIDTH__SHIFT) & A3XX_RB_WINDOW_SIZE_WIDTH__MASK; 1973 } 1974 #define A3XX_RB_WINDOW_SIZE_HEIGHT__MASK 0x0fffc000 1975 #define A3XX_RB_WINDOW_SIZE_HEIGHT__SHIFT 14 1976 static inline uint32_t A3XX_RB_WINDOW_SIZE_HEIGHT(uint32_t val) 1977 { 1978 return ((val) << A3XX_RB_WINDOW_SIZE_HEIGHT__SHIFT) & A3XX_RB_WINDOW_SIZE_HEIGHT__MASK; 1979 } 1980 1981 #define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT 0x00000e00 1982 1983 #define REG_A3XX_HLSQ_PERFCOUNTER1_SELECT 0x00000e01 1984 1985 #define REG_A3XX_HLSQ_PERFCOUNTER2_SELECT 0x00000e02 1986 1987 #define REG_A3XX_HLSQ_PERFCOUNTER3_SELECT 0x00000e03 1988 1989 #define REG_A3XX_HLSQ_PERFCOUNTER4_SELECT 0x00000e04 1990 1991 #define REG_A3XX_HLSQ_PERFCOUNTER5_SELECT 0x00000e05 1992 1993 #define REG_A3XX_UNKNOWN_0E43 0x00000e43 1994 1995 #define REG_A3XX_VFD_PERFCOUNTER0_SELECT 0x00000e44 1996 1997 #define REG_A3XX_VFD_PERFCOUNTER1_SELECT 0x00000e45 1998 1999 #define REG_A3XX_VPC_VPC_DEBUG_RAM_SEL 0x00000e61 2000 2001 #define REG_A3XX_VPC_VPC_DEBUG_RAM_READ 0x00000e62 2002 2003 #define REG_A3XX_VPC_PERFCOUNTER0_SELECT 0x00000e64 2004 2005 #define REG_A3XX_VPC_PERFCOUNTER1_SELECT 0x00000e65 2006 2007 #define REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG 0x00000e82 2008 2009 #define REG_A3XX_UCHE_PERFCOUNTER0_SELECT 0x00000e84 2010 2011 #define REG_A3XX_UCHE_PERFCOUNTER1_SELECT 0x00000e85 2012 2013 #define REG_A3XX_UCHE_PERFCOUNTER2_SELECT 0x00000e86 2014 2015 #define REG_A3XX_UCHE_PERFCOUNTER3_SELECT 0x00000e87 2016 2017 #define REG_A3XX_UCHE_PERFCOUNTER4_SELECT 0x00000e88 2018 2019 #define REG_A3XX_UCHE_PERFCOUNTER5_SELECT 0x00000e89 2020 2021 #define REG_A3XX_UCHE_CACHE_INVALIDATE0_REG 0x00000ea0 2022 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK 0x0fffffff 2023 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT 0 2024 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val) 2025 { 2026 return ((val) << A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK; 2027 } 2028 2029 #define REG_A3XX_UCHE_CACHE_INVALIDATE1_REG 0x00000ea1 2030 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK 0x0fffffff 2031 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT 0 2032 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val) 2033 { 2034 return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK; 2035 } 2036 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK 0x30000000 2037 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT 28 2038 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val) 2039 { 2040 return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK; 2041 } 2042 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE 0x80000000 2043 2044 #define REG_A3XX_SP_PERFCOUNTER0_SELECT 0x00000ec4 2045 2046 #define REG_A3XX_SP_PERFCOUNTER1_SELECT 0x00000ec5 2047 2048 #define REG_A3XX_SP_PERFCOUNTER2_SELECT 0x00000ec6 2049 2050 #define REG_A3XX_SP_PERFCOUNTER3_SELECT 0x00000ec7 2051 2052 #define REG_A3XX_SP_PERFCOUNTER4_SELECT 0x00000ec8 2053 2054 #define REG_A3XX_SP_PERFCOUNTER5_SELECT 0x00000ec9 2055 2056 #define REG_A3XX_SP_PERFCOUNTER6_SELECT 0x00000eca 2057 2058 #define REG_A3XX_SP_PERFCOUNTER7_SELECT 0x00000ecb 2059 2060 #define REG_A3XX_UNKNOWN_0EE0 0x00000ee0 2061 2062 #define REG_A3XX_UNKNOWN_0F03 0x00000f03 2063 2064 #define REG_A3XX_TP_PERFCOUNTER0_SELECT 0x00000f04 2065 2066 #define REG_A3XX_TP_PERFCOUNTER1_SELECT 0x00000f05 2067 2068 #define REG_A3XX_TP_PERFCOUNTER2_SELECT 0x00000f06 2069 2070 #define REG_A3XX_TP_PERFCOUNTER3_SELECT 0x00000f07 2071 2072 #define REG_A3XX_TP_PERFCOUNTER4_SELECT 0x00000f08 2073 2074 #define REG_A3XX_TP_PERFCOUNTER5_SELECT 0x00000f09 2075 2076 #define REG_A3XX_TEX_SAMP_0 0x00000000 2077 #define A3XX_TEX_SAMP_0_XY_MAG__MASK 0x0000000c 2078 #define A3XX_TEX_SAMP_0_XY_MAG__SHIFT 2 2079 static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val) 2080 { 2081 return ((val) << A3XX_TEX_SAMP_0_XY_MAG__SHIFT) & A3XX_TEX_SAMP_0_XY_MAG__MASK; 2082 } 2083 #define A3XX_TEX_SAMP_0_XY_MIN__MASK 0x00000030 2084 #define A3XX_TEX_SAMP_0_XY_MIN__SHIFT 4 2085 static inline uint32_t A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val) 2086 { 2087 return ((val) << A3XX_TEX_SAMP_0_XY_MIN__SHIFT) & A3XX_TEX_SAMP_0_XY_MIN__MASK; 2088 } 2089 #define A3XX_TEX_SAMP_0_WRAP_S__MASK 0x000001c0 2090 #define A3XX_TEX_SAMP_0_WRAP_S__SHIFT 6 2091 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val) 2092 { 2093 return ((val) << A3XX_TEX_SAMP_0_WRAP_S__SHIFT) & A3XX_TEX_SAMP_0_WRAP_S__MASK; 2094 } 2095 #define A3XX_TEX_SAMP_0_WRAP_T__MASK 0x00000e00 2096 #define A3XX_TEX_SAMP_0_WRAP_T__SHIFT 9 2097 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val) 2098 { 2099 return ((val) << A3XX_TEX_SAMP_0_WRAP_T__SHIFT) & A3XX_TEX_SAMP_0_WRAP_T__MASK; 2100 } 2101 #define A3XX_TEX_SAMP_0_WRAP_R__MASK 0x00007000 2102 #define A3XX_TEX_SAMP_0_WRAP_R__SHIFT 12 2103 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val) 2104 { 2105 return ((val) << A3XX_TEX_SAMP_0_WRAP_R__SHIFT) & A3XX_TEX_SAMP_0_WRAP_R__MASK; 2106 } 2107 #define A3XX_TEX_SAMP_0_UNNORM_COORDS 0x80000000 2108 2109 #define REG_A3XX_TEX_SAMP_1 0x00000001 2110 2111 #define REG_A3XX_TEX_CONST_0 0x00000000 2112 #define A3XX_TEX_CONST_0_TILED 0x00000001 2113 #define A3XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 2114 #define A3XX_TEX_CONST_0_SWIZ_X__SHIFT 4 2115 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val) 2116 { 2117 return ((val) << A3XX_TEX_CONST_0_SWIZ_X__SHIFT) & A3XX_TEX_CONST_0_SWIZ_X__MASK; 2118 } 2119 #define A3XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 2120 #define A3XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 2121 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val) 2122 { 2123 return ((val) << A3XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Y__MASK; 2124 } 2125 #define A3XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 2126 #define A3XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 2127 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val) 2128 { 2129 return ((val) << A3XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Z__MASK; 2130 } 2131 #define A3XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 2132 #define A3XX_TEX_CONST_0_SWIZ_W__SHIFT 13 2133 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val) 2134 { 2135 return ((val) << A3XX_TEX_CONST_0_SWIZ_W__SHIFT) & A3XX_TEX_CONST_0_SWIZ_W__MASK; 2136 } 2137 #define A3XX_TEX_CONST_0_FMT__MASK 0x1fc00000 2138 #define A3XX_TEX_CONST_0_FMT__SHIFT 22 2139 static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val) 2140 { 2141 return ((val) << A3XX_TEX_CONST_0_FMT__SHIFT) & A3XX_TEX_CONST_0_FMT__MASK; 2142 } 2143 #define A3XX_TEX_CONST_0_TYPE__MASK 0xc0000000 2144 #define A3XX_TEX_CONST_0_TYPE__SHIFT 30 2145 static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val) 2146 { 2147 return ((val) << A3XX_TEX_CONST_0_TYPE__SHIFT) & A3XX_TEX_CONST_0_TYPE__MASK; 2148 } 2149 2150 #define REG_A3XX_TEX_CONST_1 0x00000001 2151 #define A3XX_TEX_CONST_1_HEIGHT__MASK 0x00003fff 2152 #define A3XX_TEX_CONST_1_HEIGHT__SHIFT 0 2153 static inline uint32_t A3XX_TEX_CONST_1_HEIGHT(uint32_t val) 2154 { 2155 return ((val) << A3XX_TEX_CONST_1_HEIGHT__SHIFT) & A3XX_TEX_CONST_1_HEIGHT__MASK; 2156 } 2157 #define A3XX_TEX_CONST_1_WIDTH__MASK 0x0fffc000 2158 #define A3XX_TEX_CONST_1_WIDTH__SHIFT 14 2159 static inline uint32_t A3XX_TEX_CONST_1_WIDTH(uint32_t val) 2160 { 2161 return ((val) << A3XX_TEX_CONST_1_WIDTH__SHIFT) & A3XX_TEX_CONST_1_WIDTH__MASK; 2162 } 2163 #define A3XX_TEX_CONST_1_FETCHSIZE__MASK 0xf0000000 2164 #define A3XX_TEX_CONST_1_FETCHSIZE__SHIFT 28 2165 static inline uint32_t A3XX_TEX_CONST_1_FETCHSIZE(enum a3xx_tex_fetchsize val) 2166 { 2167 return ((val) << A3XX_TEX_CONST_1_FETCHSIZE__SHIFT) & A3XX_TEX_CONST_1_FETCHSIZE__MASK; 2168 } 2169 2170 #define REG_A3XX_TEX_CONST_2 0x00000002 2171 #define A3XX_TEX_CONST_2_INDX__MASK 0x000000ff 2172 #define A3XX_TEX_CONST_2_INDX__SHIFT 0 2173 static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val) 2174 { 2175 return ((val) << A3XX_TEX_CONST_2_INDX__SHIFT) & A3XX_TEX_CONST_2_INDX__MASK; 2176 } 2177 #define A3XX_TEX_CONST_2_PITCH__MASK 0x3ffff000 2178 #define A3XX_TEX_CONST_2_PITCH__SHIFT 12 2179 static inline uint32_t A3XX_TEX_CONST_2_PITCH(uint32_t val) 2180 { 2181 return ((val) << A3XX_TEX_CONST_2_PITCH__SHIFT) & A3XX_TEX_CONST_2_PITCH__MASK; 2182 } 2183 #define A3XX_TEX_CONST_2_SWAP__MASK 0xc0000000 2184 #define A3XX_TEX_CONST_2_SWAP__SHIFT 30 2185 static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) 2186 { 2187 return ((val) << A3XX_TEX_CONST_2_SWAP__SHIFT) & A3XX_TEX_CONST_2_SWAP__MASK; 2188 } 2189 2190 #define REG_A3XX_TEX_CONST_3 0x00000003 2191 2192 2193 #endif /* A3XX_XML */ 2194