1 #ifndef A3XX_XML 2 #define A3XX_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30) 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30) 15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 15053 bytes, from 2014-11-09 15:45:47) 16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 63169 bytes, from 2014-11-13 22:44:18) 17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 49097 bytes, from 2014-11-14 15:38:00) 18 19 Copyright (C) 2013-2014 by the following authors: 20 - Rob Clark <robdclark@gmail.com> (robclark) 21 22 Permission is hereby granted, free of charge, to any person obtaining 23 a copy of this software and associated documentation files (the 24 "Software"), to deal in the Software without restriction, including 25 without limitation the rights to use, copy, modify, merge, publish, 26 distribute, sublicense, and/or sell copies of the Software, and to 27 permit persons to whom the Software is furnished to do so, subject to 28 the following conditions: 29 30 The above copyright notice and this permission notice (including the 31 next paragraph) shall be included in all copies or substantial 32 portions of the Software. 33 34 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 36 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 37 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 38 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 39 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 40 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43 44 enum a3xx_tile_mode { 45 LINEAR = 0, 46 TILE_32X32 = 2, 47 }; 48 49 enum a3xx_state_block_id { 50 HLSQ_BLOCK_ID_TP_TEX = 2, 51 HLSQ_BLOCK_ID_TP_MIPMAP = 3, 52 HLSQ_BLOCK_ID_SP_VS = 4, 53 HLSQ_BLOCK_ID_SP_FS = 6, 54 }; 55 56 enum a3xx_cache_opcode { 57 INVALIDATE = 1, 58 }; 59 60 enum a3xx_vtx_fmt { 61 VFMT_FLOAT_32 = 0, 62 VFMT_FLOAT_32_32 = 1, 63 VFMT_FLOAT_32_32_32 = 2, 64 VFMT_FLOAT_32_32_32_32 = 3, 65 VFMT_FLOAT_16 = 4, 66 VFMT_FLOAT_16_16 = 5, 67 VFMT_FLOAT_16_16_16 = 6, 68 VFMT_FLOAT_16_16_16_16 = 7, 69 VFMT_FIXED_32 = 8, 70 VFMT_FIXED_32_32 = 9, 71 VFMT_FIXED_32_32_32 = 10, 72 VFMT_FIXED_32_32_32_32 = 11, 73 VFMT_SHORT_16 = 16, 74 VFMT_SHORT_16_16 = 17, 75 VFMT_SHORT_16_16_16 = 18, 76 VFMT_SHORT_16_16_16_16 = 19, 77 VFMT_USHORT_16 = 20, 78 VFMT_USHORT_16_16 = 21, 79 VFMT_USHORT_16_16_16 = 22, 80 VFMT_USHORT_16_16_16_16 = 23, 81 VFMT_NORM_SHORT_16 = 24, 82 VFMT_NORM_SHORT_16_16 = 25, 83 VFMT_NORM_SHORT_16_16_16 = 26, 84 VFMT_NORM_SHORT_16_16_16_16 = 27, 85 VFMT_NORM_USHORT_16 = 28, 86 VFMT_NORM_USHORT_16_16 = 29, 87 VFMT_NORM_USHORT_16_16_16 = 30, 88 VFMT_NORM_USHORT_16_16_16_16 = 31, 89 VFMT_UINT_32 = 32, 90 VFMT_UINT_32_32 = 33, 91 VFMT_UINT_32_32_32 = 34, 92 VFMT_UINT_32_32_32_32 = 35, 93 VFMT_INT_32 = 36, 94 VFMT_INT_32_32 = 37, 95 VFMT_INT_32_32_32 = 38, 96 VFMT_INT_32_32_32_32 = 39, 97 VFMT_UBYTE_8 = 40, 98 VFMT_UBYTE_8_8 = 41, 99 VFMT_UBYTE_8_8_8 = 42, 100 VFMT_UBYTE_8_8_8_8 = 43, 101 VFMT_NORM_UBYTE_8 = 44, 102 VFMT_NORM_UBYTE_8_8 = 45, 103 VFMT_NORM_UBYTE_8_8_8 = 46, 104 VFMT_NORM_UBYTE_8_8_8_8 = 47, 105 VFMT_BYTE_8 = 48, 106 VFMT_BYTE_8_8 = 49, 107 VFMT_BYTE_8_8_8 = 50, 108 VFMT_BYTE_8_8_8_8 = 51, 109 VFMT_NORM_BYTE_8 = 52, 110 VFMT_NORM_BYTE_8_8 = 53, 111 VFMT_NORM_BYTE_8_8_8 = 54, 112 VFMT_NORM_BYTE_8_8_8_8 = 55, 113 VFMT_UINT_10_10_10_2 = 60, 114 VFMT_NORM_UINT_10_10_10_2 = 61, 115 VFMT_INT_10_10_10_2 = 62, 116 VFMT_NORM_INT_10_10_10_2 = 63, 117 }; 118 119 enum a3xx_tex_fmt { 120 TFMT_NORM_USHORT_565 = 4, 121 TFMT_NORM_USHORT_5551 = 6, 122 TFMT_NORM_USHORT_4444 = 7, 123 TFMT_NORM_USHORT_Z16 = 9, 124 TFMT_NORM_UINT_X8Z24 = 10, 125 TFMT_FLOAT_Z32 = 11, 126 TFMT_NORM_UINT_NV12_UV_TILED = 17, 127 TFMT_NORM_UINT_NV12_Y_TILED = 19, 128 TFMT_NORM_UINT_NV12_UV = 21, 129 TFMT_NORM_UINT_NV12_Y = 23, 130 TFMT_NORM_UINT_I420_Y = 24, 131 TFMT_NORM_UINT_I420_U = 26, 132 TFMT_NORM_UINT_I420_V = 27, 133 TFMT_NORM_UINT_2_10_10_10 = 41, 134 TFMT_FLOAT_9_9_9_E5 = 42, 135 TFMT_FLOAT_10_11_11 = 43, 136 TFMT_NORM_UINT_A8 = 44, 137 TFMT_NORM_UINT_L8_A8 = 47, 138 TFMT_NORM_UINT_8 = 48, 139 TFMT_NORM_UINT_8_8 = 49, 140 TFMT_NORM_UINT_8_8_8 = 50, 141 TFMT_NORM_UINT_8_8_8_8 = 51, 142 TFMT_NORM_SINT_8_8 = 53, 143 TFMT_NORM_SINT_8_8_8_8 = 55, 144 TFMT_UINT_8_8 = 57, 145 TFMT_UINT_8_8_8_8 = 59, 146 TFMT_SINT_8_8 = 61, 147 TFMT_SINT_8_8_8_8 = 63, 148 TFMT_FLOAT_16 = 64, 149 TFMT_FLOAT_16_16 = 65, 150 TFMT_FLOAT_16_16_16_16 = 67, 151 TFMT_UINT_16 = 68, 152 TFMT_UINT_16_16 = 69, 153 TFMT_UINT_16_16_16_16 = 71, 154 TFMT_SINT_16 = 72, 155 TFMT_SINT_16_16 = 73, 156 TFMT_SINT_16_16_16_16 = 75, 157 TFMT_FLOAT_32 = 84, 158 TFMT_FLOAT_32_32 = 85, 159 TFMT_FLOAT_32_32_32_32 = 87, 160 TFMT_UINT_32 = 88, 161 TFMT_UINT_32_32 = 89, 162 TFMT_UINT_32_32_32_32 = 91, 163 TFMT_SINT_32 = 92, 164 TFMT_SINT_32_32 = 93, 165 TFMT_SINT_32_32_32_32 = 95, 166 }; 167 168 enum a3xx_tex_fetchsize { 169 TFETCH_DISABLE = 0, 170 TFETCH_1_BYTE = 1, 171 TFETCH_2_BYTE = 2, 172 TFETCH_4_BYTE = 3, 173 TFETCH_8_BYTE = 4, 174 TFETCH_16_BYTE = 5, 175 }; 176 177 enum a3xx_color_fmt { 178 RB_R5G6B5_UNORM = 0, 179 RB_R5G5B5A1_UNORM = 1, 180 RB_R4G4B4A4_UNORM = 3, 181 RB_R8G8B8_UNORM = 4, 182 RB_R8G8B8A8_UNORM = 8, 183 RB_R8G8B8A8_UINT = 10, 184 RB_R8G8B8A8_SINT = 11, 185 RB_R8G8_UNORM = 12, 186 RB_R8_UINT = 14, 187 RB_R8_SINT = 15, 188 RB_R10G10B10A2_UNORM = 16, 189 RB_A8_UNORM = 20, 190 RB_R8_UNORM = 21, 191 RB_R16G16B16A16_FLOAT = 27, 192 RB_R11G11B10_FLOAT = 28, 193 RB_R16_SINT = 40, 194 RB_R16G16_SINT = 41, 195 RB_R16G16B16A16_SINT = 43, 196 RB_R16_UINT = 44, 197 RB_R16G16_UINT = 45, 198 RB_R16G16B16A16_UINT = 47, 199 RB_R32G32B32A32_FLOAT = 51, 200 RB_R32_SINT = 52, 201 RB_R32G32_SINT = 53, 202 RB_R32G32B32A32_SINT = 55, 203 RB_R32_UINT = 56, 204 RB_R32G32_UINT = 57, 205 RB_R32G32B32A32_UINT = 59, 206 }; 207 208 enum a3xx_sp_perfcounter_select { 209 SP_FS_CFLOW_INSTRUCTIONS = 12, 210 SP_FS_FULL_ALU_INSTRUCTIONS = 14, 211 SP0_ICL1_MISSES = 26, 212 SP_ALU_ACTIVE_CYCLES = 29, 213 }; 214 215 enum a3xx_rop_code { 216 ROP_CLEAR = 0, 217 ROP_NOR = 1, 218 ROP_AND_INVERTED = 2, 219 ROP_COPY_INVERTED = 3, 220 ROP_AND_REVERSE = 4, 221 ROP_INVERT = 5, 222 ROP_XOR = 6, 223 ROP_NAND = 7, 224 ROP_AND = 8, 225 ROP_EQUIV = 9, 226 ROP_NOOP = 10, 227 ROP_OR_INVERTED = 11, 228 ROP_COPY = 12, 229 ROP_OR_REVERSE = 13, 230 ROP_OR = 14, 231 ROP_SET = 15, 232 }; 233 234 enum a3xx_rb_blend_opcode { 235 BLEND_DST_PLUS_SRC = 0, 236 BLEND_SRC_MINUS_DST = 1, 237 BLEND_DST_MINUS_SRC = 2, 238 BLEND_MIN_DST_SRC = 3, 239 BLEND_MAX_DST_SRC = 4, 240 }; 241 242 enum a3xx_intp_mode { 243 SMOOTH = 0, 244 FLAT = 1, 245 }; 246 247 enum a3xx_tex_filter { 248 A3XX_TEX_NEAREST = 0, 249 A3XX_TEX_LINEAR = 1, 250 A3XX_TEX_ANISO = 2, 251 }; 252 253 enum a3xx_tex_clamp { 254 A3XX_TEX_REPEAT = 0, 255 A3XX_TEX_CLAMP_TO_EDGE = 1, 256 A3XX_TEX_MIRROR_REPEAT = 2, 257 A3XX_TEX_CLAMP_TO_BORDER = 3, 258 A3XX_TEX_MIRROR_CLAMP = 4, 259 }; 260 261 enum a3xx_tex_swiz { 262 A3XX_TEX_X = 0, 263 A3XX_TEX_Y = 1, 264 A3XX_TEX_Z = 2, 265 A3XX_TEX_W = 3, 266 A3XX_TEX_ZERO = 4, 267 A3XX_TEX_ONE = 5, 268 }; 269 270 enum a3xx_tex_type { 271 A3XX_TEX_1D = 0, 272 A3XX_TEX_2D = 1, 273 A3XX_TEX_CUBE = 2, 274 A3XX_TEX_3D = 3, 275 }; 276 277 #define A3XX_INT0_RBBM_GPU_IDLE 0x00000001 278 #define A3XX_INT0_RBBM_AHB_ERROR 0x00000002 279 #define A3XX_INT0_RBBM_REG_TIMEOUT 0x00000004 280 #define A3XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 281 #define A3XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 282 #define A3XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020 283 #define A3XX_INT0_VFD_ERROR 0x00000040 284 #define A3XX_INT0_CP_SW_INT 0x00000080 285 #define A3XX_INT0_CP_T0_PACKET_IN_IB 0x00000100 286 #define A3XX_INT0_CP_OPCODE_ERROR 0x00000200 287 #define A3XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400 288 #define A3XX_INT0_CP_HW_FAULT 0x00000800 289 #define A3XX_INT0_CP_DMA 0x00001000 290 #define A3XX_INT0_CP_IB2_INT 0x00002000 291 #define A3XX_INT0_CP_IB1_INT 0x00004000 292 #define A3XX_INT0_CP_RB_INT 0x00008000 293 #define A3XX_INT0_CP_REG_PROTECT_FAULT 0x00010000 294 #define A3XX_INT0_CP_RB_DONE_TS 0x00020000 295 #define A3XX_INT0_CP_VS_DONE_TS 0x00040000 296 #define A3XX_INT0_CP_PS_DONE_TS 0x00080000 297 #define A3XX_INT0_CACHE_FLUSH_TS 0x00100000 298 #define A3XX_INT0_CP_AHB_ERROR_HALT 0x00200000 299 #define A3XX_INT0_MISC_HANG_DETECT 0x01000000 300 #define A3XX_INT0_UCHE_OOB_ACCESS 0x02000000 301 #define REG_A3XX_RBBM_HW_VERSION 0x00000000 302 303 #define REG_A3XX_RBBM_HW_RELEASE 0x00000001 304 305 #define REG_A3XX_RBBM_HW_CONFIGURATION 0x00000002 306 307 #define REG_A3XX_RBBM_CLOCK_CTL 0x00000010 308 309 #define REG_A3XX_RBBM_SP_HYST_CNT 0x00000012 310 311 #define REG_A3XX_RBBM_SW_RESET_CMD 0x00000018 312 313 #define REG_A3XX_RBBM_AHB_CTL0 0x00000020 314 315 #define REG_A3XX_RBBM_AHB_CTL1 0x00000021 316 317 #define REG_A3XX_RBBM_AHB_CMD 0x00000022 318 319 #define REG_A3XX_RBBM_AHB_ERROR_STATUS 0x00000027 320 321 #define REG_A3XX_RBBM_GPR0_CTL 0x0000002e 322 323 #define REG_A3XX_RBBM_STATUS 0x00000030 324 #define A3XX_RBBM_STATUS_HI_BUSY 0x00000001 325 #define A3XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 326 #define A3XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 327 #define A3XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000 328 #define A3XX_RBBM_STATUS_VBIF_BUSY 0x00008000 329 #define A3XX_RBBM_STATUS_TSE_BUSY 0x00010000 330 #define A3XX_RBBM_STATUS_RAS_BUSY 0x00020000 331 #define A3XX_RBBM_STATUS_RB_BUSY 0x00040000 332 #define A3XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 333 #define A3XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 334 #define A3XX_RBBM_STATUS_VFD_BUSY 0x00200000 335 #define A3XX_RBBM_STATUS_VPC_BUSY 0x00400000 336 #define A3XX_RBBM_STATUS_UCHE_BUSY 0x00800000 337 #define A3XX_RBBM_STATUS_SP_BUSY 0x01000000 338 #define A3XX_RBBM_STATUS_TPL1_BUSY 0x02000000 339 #define A3XX_RBBM_STATUS_MARB_BUSY 0x04000000 340 #define A3XX_RBBM_STATUS_VSC_BUSY 0x08000000 341 #define A3XX_RBBM_STATUS_ARB_BUSY 0x10000000 342 #define A3XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 343 #define A3XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000 344 #define A3XX_RBBM_STATUS_GPU_BUSY 0x80000000 345 346 #define REG_A3XX_RBBM_NQWAIT_UNTIL 0x00000040 347 348 #define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x00000033 349 350 #define REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL 0x00000050 351 352 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL0 0x00000051 353 354 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL1 0x00000054 355 356 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL2 0x00000057 357 358 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3 0x0000005a 359 360 #define REG_A3XX_RBBM_INT_SET_CMD 0x00000060 361 362 #define REG_A3XX_RBBM_INT_CLEAR_CMD 0x00000061 363 364 #define REG_A3XX_RBBM_INT_0_MASK 0x00000063 365 366 #define REG_A3XX_RBBM_INT_0_STATUS 0x00000064 367 368 #define REG_A3XX_RBBM_PERFCTR_CTL 0x00000080 369 #define A3XX_RBBM_PERFCTR_CTL_ENABLE 0x00000001 370 371 #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0 0x00000081 372 373 #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD1 0x00000082 374 375 #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000084 376 377 #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000085 378 379 #define REG_A3XX_RBBM_PERFCOUNTER0_SELECT 0x00000086 380 381 #define REG_A3XX_RBBM_PERFCOUNTER1_SELECT 0x00000087 382 383 #define REG_A3XX_RBBM_GPU_BUSY_MASKED 0x00000088 384 385 #define REG_A3XX_RBBM_PERFCTR_CP_0_LO 0x00000090 386 387 #define REG_A3XX_RBBM_PERFCTR_CP_0_HI 0x00000091 388 389 #define REG_A3XX_RBBM_PERFCTR_RBBM_0_LO 0x00000092 390 391 #define REG_A3XX_RBBM_PERFCTR_RBBM_0_HI 0x00000093 392 393 #define REG_A3XX_RBBM_PERFCTR_RBBM_1_LO 0x00000094 394 395 #define REG_A3XX_RBBM_PERFCTR_RBBM_1_HI 0x00000095 396 397 #define REG_A3XX_RBBM_PERFCTR_PC_0_LO 0x00000096 398 399 #define REG_A3XX_RBBM_PERFCTR_PC_0_HI 0x00000097 400 401 #define REG_A3XX_RBBM_PERFCTR_PC_1_LO 0x00000098 402 403 #define REG_A3XX_RBBM_PERFCTR_PC_1_HI 0x00000099 404 405 #define REG_A3XX_RBBM_PERFCTR_PC_2_LO 0x0000009a 406 407 #define REG_A3XX_RBBM_PERFCTR_PC_2_HI 0x0000009b 408 409 #define REG_A3XX_RBBM_PERFCTR_PC_3_LO 0x0000009c 410 411 #define REG_A3XX_RBBM_PERFCTR_PC_3_HI 0x0000009d 412 413 #define REG_A3XX_RBBM_PERFCTR_VFD_0_LO 0x0000009e 414 415 #define REG_A3XX_RBBM_PERFCTR_VFD_0_HI 0x0000009f 416 417 #define REG_A3XX_RBBM_PERFCTR_VFD_1_LO 0x000000a0 418 419 #define REG_A3XX_RBBM_PERFCTR_VFD_1_HI 0x000000a1 420 421 #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000a2 422 423 #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000a3 424 425 #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000a4 426 427 #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000a5 428 429 #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000a6 430 431 #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000a7 432 433 #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000a8 434 435 #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000a9 436 437 #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000aa 438 439 #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000ab 440 441 #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000ac 442 443 #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000ad 444 445 #define REG_A3XX_RBBM_PERFCTR_VPC_0_LO 0x000000ae 446 447 #define REG_A3XX_RBBM_PERFCTR_VPC_0_HI 0x000000af 448 449 #define REG_A3XX_RBBM_PERFCTR_VPC_1_LO 0x000000b0 450 451 #define REG_A3XX_RBBM_PERFCTR_VPC_1_HI 0x000000b1 452 453 #define REG_A3XX_RBBM_PERFCTR_TSE_0_LO 0x000000b2 454 455 #define REG_A3XX_RBBM_PERFCTR_TSE_0_HI 0x000000b3 456 457 #define REG_A3XX_RBBM_PERFCTR_TSE_1_LO 0x000000b4 458 459 #define REG_A3XX_RBBM_PERFCTR_TSE_1_HI 0x000000b5 460 461 #define REG_A3XX_RBBM_PERFCTR_RAS_0_LO 0x000000b6 462 463 #define REG_A3XX_RBBM_PERFCTR_RAS_0_HI 0x000000b7 464 465 #define REG_A3XX_RBBM_PERFCTR_RAS_1_LO 0x000000b8 466 467 #define REG_A3XX_RBBM_PERFCTR_RAS_1_HI 0x000000b9 468 469 #define REG_A3XX_RBBM_PERFCTR_UCHE_0_LO 0x000000ba 470 471 #define REG_A3XX_RBBM_PERFCTR_UCHE_0_HI 0x000000bb 472 473 #define REG_A3XX_RBBM_PERFCTR_UCHE_1_LO 0x000000bc 474 475 #define REG_A3XX_RBBM_PERFCTR_UCHE_1_HI 0x000000bd 476 477 #define REG_A3XX_RBBM_PERFCTR_UCHE_2_LO 0x000000be 478 479 #define REG_A3XX_RBBM_PERFCTR_UCHE_2_HI 0x000000bf 480 481 #define REG_A3XX_RBBM_PERFCTR_UCHE_3_LO 0x000000c0 482 483 #define REG_A3XX_RBBM_PERFCTR_UCHE_3_HI 0x000000c1 484 485 #define REG_A3XX_RBBM_PERFCTR_UCHE_4_LO 0x000000c2 486 487 #define REG_A3XX_RBBM_PERFCTR_UCHE_4_HI 0x000000c3 488 489 #define REG_A3XX_RBBM_PERFCTR_UCHE_5_LO 0x000000c4 490 491 #define REG_A3XX_RBBM_PERFCTR_UCHE_5_HI 0x000000c5 492 493 #define REG_A3XX_RBBM_PERFCTR_TP_0_LO 0x000000c6 494 495 #define REG_A3XX_RBBM_PERFCTR_TP_0_HI 0x000000c7 496 497 #define REG_A3XX_RBBM_PERFCTR_TP_1_LO 0x000000c8 498 499 #define REG_A3XX_RBBM_PERFCTR_TP_1_HI 0x000000c9 500 501 #define REG_A3XX_RBBM_PERFCTR_TP_2_LO 0x000000ca 502 503 #define REG_A3XX_RBBM_PERFCTR_TP_2_HI 0x000000cb 504 505 #define REG_A3XX_RBBM_PERFCTR_TP_3_LO 0x000000cc 506 507 #define REG_A3XX_RBBM_PERFCTR_TP_3_HI 0x000000cd 508 509 #define REG_A3XX_RBBM_PERFCTR_TP_4_LO 0x000000ce 510 511 #define REG_A3XX_RBBM_PERFCTR_TP_4_HI 0x000000cf 512 513 #define REG_A3XX_RBBM_PERFCTR_TP_5_LO 0x000000d0 514 515 #define REG_A3XX_RBBM_PERFCTR_TP_5_HI 0x000000d1 516 517 #define REG_A3XX_RBBM_PERFCTR_SP_0_LO 0x000000d2 518 519 #define REG_A3XX_RBBM_PERFCTR_SP_0_HI 0x000000d3 520 521 #define REG_A3XX_RBBM_PERFCTR_SP_1_LO 0x000000d4 522 523 #define REG_A3XX_RBBM_PERFCTR_SP_1_HI 0x000000d5 524 525 #define REG_A3XX_RBBM_PERFCTR_SP_2_LO 0x000000d6 526 527 #define REG_A3XX_RBBM_PERFCTR_SP_2_HI 0x000000d7 528 529 #define REG_A3XX_RBBM_PERFCTR_SP_3_LO 0x000000d8 530 531 #define REG_A3XX_RBBM_PERFCTR_SP_3_HI 0x000000d9 532 533 #define REG_A3XX_RBBM_PERFCTR_SP_4_LO 0x000000da 534 535 #define REG_A3XX_RBBM_PERFCTR_SP_4_HI 0x000000db 536 537 #define REG_A3XX_RBBM_PERFCTR_SP_5_LO 0x000000dc 538 539 #define REG_A3XX_RBBM_PERFCTR_SP_5_HI 0x000000dd 540 541 #define REG_A3XX_RBBM_PERFCTR_SP_6_LO 0x000000de 542 543 #define REG_A3XX_RBBM_PERFCTR_SP_6_HI 0x000000df 544 545 #define REG_A3XX_RBBM_PERFCTR_SP_7_LO 0x000000e0 546 547 #define REG_A3XX_RBBM_PERFCTR_SP_7_HI 0x000000e1 548 549 #define REG_A3XX_RBBM_PERFCTR_RB_0_LO 0x000000e2 550 551 #define REG_A3XX_RBBM_PERFCTR_RB_0_HI 0x000000e3 552 553 #define REG_A3XX_RBBM_PERFCTR_RB_1_LO 0x000000e4 554 555 #define REG_A3XX_RBBM_PERFCTR_RB_1_HI 0x000000e5 556 557 #define REG_A3XX_RBBM_PERFCTR_PWR_0_LO 0x000000ea 558 559 #define REG_A3XX_RBBM_PERFCTR_PWR_0_HI 0x000000eb 560 561 #define REG_A3XX_RBBM_PERFCTR_PWR_1_LO 0x000000ec 562 563 #define REG_A3XX_RBBM_PERFCTR_PWR_1_HI 0x000000ed 564 565 #define REG_A3XX_RBBM_RBBM_CTL 0x00000100 566 567 #define REG_A3XX_RBBM_DEBUG_BUS_CTL 0x00000111 568 569 #define REG_A3XX_RBBM_DEBUG_BUS_DATA_STATUS 0x00000112 570 571 #define REG_A3XX_CP_PFP_UCODE_ADDR 0x000001c9 572 573 #define REG_A3XX_CP_PFP_UCODE_DATA 0x000001ca 574 575 #define REG_A3XX_CP_ROQ_ADDR 0x000001cc 576 577 #define REG_A3XX_CP_ROQ_DATA 0x000001cd 578 579 #define REG_A3XX_CP_MERCIU_ADDR 0x000001d1 580 581 #define REG_A3XX_CP_MERCIU_DATA 0x000001d2 582 583 #define REG_A3XX_CP_MERCIU_DATA2 0x000001d3 584 585 #define REG_A3XX_CP_MEQ_ADDR 0x000001da 586 587 #define REG_A3XX_CP_MEQ_DATA 0x000001db 588 589 #define REG_A3XX_CP_WFI_PEND_CTR 0x000001f5 590 591 #define REG_A3XX_RBBM_PM_OVERRIDE2 0x0000039d 592 593 #define REG_A3XX_CP_PERFCOUNTER_SELECT 0x00000445 594 595 #define REG_A3XX_CP_HW_FAULT 0x0000045c 596 597 #define REG_A3XX_CP_PROTECT_CTRL 0x0000045e 598 599 #define REG_A3XX_CP_PROTECT_STATUS 0x0000045f 600 601 static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; } 602 603 static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; } 604 605 #define REG_A3XX_CP_AHB_FAULT 0x0000054d 606 607 #define REG_A3XX_SQ_GPR_MANAGEMENT 0x00000d00 608 609 #define REG_A3XX_SQ_INST_STORE_MANAGMENT 0x00000d02 610 611 #define REG_A3XX_TP0_CHICKEN 0x00000e1e 612 613 #define REG_A3XX_SP_GLOBAL_MEM_SIZE 0x00000e22 614 615 #define REG_A3XX_SP_GLOBAL_MEM_ADDR 0x00000e23 616 617 #define REG_A3XX_GRAS_CL_CLIP_CNTL 0x00002040 618 #define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER 0x00001000 619 #define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 620 #define A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000 621 #define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE 0x00080000 622 #define A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE 0x00100000 623 #define A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE 0x00200000 624 #define A3XX_GRAS_CL_CLIP_CNTL_ZCOORD 0x00800000 625 #define A3XX_GRAS_CL_CLIP_CNTL_WCOORD 0x01000000 626 #define A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE 0x02000000 627 628 #define REG_A3XX_GRAS_CL_GB_CLIP_ADJ 0x00002044 629 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff 630 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0 631 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) 632 { 633 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; 634 } 635 #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00 636 #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10 637 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) 638 { 639 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; 640 } 641 642 #define REG_A3XX_GRAS_CL_VPORT_XOFFSET 0x00002048 643 #define A3XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff 644 #define A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0 645 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) 646 { 647 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK; 648 } 649 650 #define REG_A3XX_GRAS_CL_VPORT_XSCALE 0x00002049 651 #define A3XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff 652 #define A3XX_GRAS_CL_VPORT_XSCALE__SHIFT 0 653 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) 654 { 655 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK; 656 } 657 658 #define REG_A3XX_GRAS_CL_VPORT_YOFFSET 0x0000204a 659 #define A3XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff 660 #define A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0 661 static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val) 662 { 663 return ((fui(val)) << A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_YOFFSET__MASK; 664 } 665 666 #define REG_A3XX_GRAS_CL_VPORT_YSCALE 0x0000204b 667 #define A3XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff 668 #define A3XX_GRAS_CL_VPORT_YSCALE__SHIFT 0 669 static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val) 670 { 671 return ((fui(val)) << A3XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_YSCALE__MASK; 672 } 673 674 #define REG_A3XX_GRAS_CL_VPORT_ZOFFSET 0x0000204c 675 #define A3XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff 676 #define A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0 677 static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val) 678 { 679 return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_ZOFFSET__MASK; 680 } 681 682 #define REG_A3XX_GRAS_CL_VPORT_ZSCALE 0x0000204d 683 #define A3XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff 684 #define A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0 685 static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val) 686 { 687 return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_ZSCALE__MASK; 688 } 689 690 #define REG_A3XX_GRAS_SU_POINT_MINMAX 0x00002068 691 #define A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 692 #define A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 693 static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MIN(float val) 694 { 695 return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 696 } 697 #define A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 698 #define A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 699 static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MAX(float val) 700 { 701 return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 702 } 703 704 #define REG_A3XX_GRAS_SU_POINT_SIZE 0x00002069 705 #define A3XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff 706 #define A3XX_GRAS_SU_POINT_SIZE__SHIFT 0 707 static inline uint32_t A3XX_GRAS_SU_POINT_SIZE(float val) 708 { 709 return ((((int32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_SIZE__SHIFT) & A3XX_GRAS_SU_POINT_SIZE__MASK; 710 } 711 712 #define REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000206c 713 #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK 0x00ffffff 714 #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT 0 715 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val) 716 { 717 return ((((int32_t)(val * 16384.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK; 718 } 719 720 #define REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000206d 721 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 722 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 723 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 724 { 725 return ((((int32_t)(val * 16384.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 726 } 727 728 #define REG_A3XX_GRAS_SU_MODE_CONTROL 0x00002070 729 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001 730 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002 731 #define A3XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004 732 #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8 733 #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3 734 static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) 735 { 736 return ((((int32_t)(val * 4.0))) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; 737 } 738 #define A3XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800 739 740 #define REG_A3XX_GRAS_SC_CONTROL 0x00002072 741 #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x000000f0 742 #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 4 743 static inline uint32_t A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) 744 { 745 return ((val) << A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK; 746 } 747 #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000f00 748 #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 8 749 static inline uint32_t A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val) 750 { 751 return ((val) << A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK; 752 } 753 #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000 754 #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12 755 static inline uint32_t A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) 756 { 757 return ((val) << A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK; 758 } 759 760 #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL 0x00002074 761 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 762 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 763 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 764 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 765 { 766 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; 767 } 768 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 769 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 770 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 771 { 772 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; 773 } 774 775 #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_BR 0x00002075 776 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 777 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 778 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 779 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 780 { 781 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; 782 } 783 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 784 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 785 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 786 { 787 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; 788 } 789 790 #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL 0x00002079 791 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 792 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 793 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 794 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 795 { 796 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 797 } 798 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 799 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 800 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 801 { 802 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 803 } 804 805 #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000207a 806 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 807 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 808 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 809 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 810 { 811 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 812 } 813 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 814 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 815 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 816 { 817 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 818 } 819 820 #define REG_A3XX_RB_MODE_CONTROL 0x000020c0 821 #define A3XX_RB_MODE_CONTROL_GMEM_BYPASS 0x00000080 822 #define A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK 0x00000700 823 #define A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT 8 824 static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val) 825 { 826 return ((val) << A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT) & A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK; 827 } 828 #define A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE 0x00008000 829 #define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE 0x00010000 830 831 #define REG_A3XX_RB_RENDER_CONTROL 0x000020c1 832 #define A3XX_RB_RENDER_CONTROL_FACENESS 0x00000008 833 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK 0x00000ff0 834 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT 4 835 static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val) 836 { 837 return ((val >> 5) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK; 838 } 839 #define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00001000 840 #define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM 0x00002000 841 #define A3XX_RB_RENDER_CONTROL_XCOORD 0x00004000 842 #define A3XX_RB_RENDER_CONTROL_YCOORD 0x00008000 843 #define A3XX_RB_RENDER_CONTROL_ZCOORD 0x00010000 844 #define A3XX_RB_RENDER_CONTROL_WCOORD 0x00020000 845 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST 0x00400000 846 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK 0x07000000 847 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT 24 848 static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 849 { 850 return ((val) << A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK; 851 } 852 853 #define REG_A3XX_RB_MSAA_CONTROL 0x000020c2 854 #define A3XX_RB_MSAA_CONTROL_DISABLE 0x00000400 855 #define A3XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000f000 856 #define A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 12 857 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val) 858 { 859 return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLES__MASK; 860 } 861 #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK 0xffff0000 862 #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT 16 863 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val) 864 { 865 return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK; 866 } 867 868 #define REG_A3XX_RB_ALPHA_REF 0x000020c3 869 #define A3XX_RB_ALPHA_REF_UINT__MASK 0x0000ff00 870 #define A3XX_RB_ALPHA_REF_UINT__SHIFT 8 871 static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val) 872 { 873 return ((val) << A3XX_RB_ALPHA_REF_UINT__SHIFT) & A3XX_RB_ALPHA_REF_UINT__MASK; 874 } 875 #define A3XX_RB_ALPHA_REF_FLOAT__MASK 0xffff0000 876 #define A3XX_RB_ALPHA_REF_FLOAT__SHIFT 16 877 static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val) 878 { 879 return ((util_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK; 880 } 881 882 static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; } 883 884 static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; } 885 #define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008 886 #define A3XX_RB_MRT_CONTROL_BLEND 0x00000010 887 #define A3XX_RB_MRT_CONTROL_BLEND2 0x00000020 888 #define A3XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00 889 #define A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8 890 static inline uint32_t A3XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) 891 { 892 return ((val) << A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A3XX_RB_MRT_CONTROL_ROP_CODE__MASK; 893 } 894 #define A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK 0x00003000 895 #define A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT 12 896 static inline uint32_t A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) 897 { 898 return ((val) << A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT) & A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK; 899 } 900 #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000 901 #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24 902 static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 903 { 904 return ((val) << A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 905 } 906 907 static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; } 908 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f 909 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 910 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val) 911 { 912 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 913 } 914 #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0 915 #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6 916 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val) 917 { 918 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 919 } 920 #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00000c00 921 #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 10 922 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 923 { 924 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 925 } 926 #define A3XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00004000 927 #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xfffe0000 928 #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 17 929 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) 930 { 931 return ((val >> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; 932 } 933 934 static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; } 935 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK 0xfffffff0 936 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT 4 937 static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val) 938 { 939 return ((val >> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK; 940 } 941 942 static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; } 943 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 944 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 945 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 946 { 947 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 948 } 949 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 950 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 951 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 952 { 953 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 954 } 955 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 956 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 957 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 958 { 959 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 960 } 961 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 962 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 963 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 964 { 965 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 966 } 967 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 968 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 969 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 970 { 971 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 972 } 973 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 974 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 975 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 976 { 977 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 978 } 979 #define A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE 0x20000000 980 981 #define REG_A3XX_RB_BLEND_RED 0x000020e4 982 #define A3XX_RB_BLEND_RED_UINT__MASK 0x000000ff 983 #define A3XX_RB_BLEND_RED_UINT__SHIFT 0 984 static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val) 985 { 986 return ((val) << A3XX_RB_BLEND_RED_UINT__SHIFT) & A3XX_RB_BLEND_RED_UINT__MASK; 987 } 988 #define A3XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 989 #define A3XX_RB_BLEND_RED_FLOAT__SHIFT 16 990 static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val) 991 { 992 return ((util_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK; 993 } 994 995 #define REG_A3XX_RB_BLEND_GREEN 0x000020e5 996 #define A3XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff 997 #define A3XX_RB_BLEND_GREEN_UINT__SHIFT 0 998 static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val) 999 { 1000 return ((val) << A3XX_RB_BLEND_GREEN_UINT__SHIFT) & A3XX_RB_BLEND_GREEN_UINT__MASK; 1001 } 1002 #define A3XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 1003 #define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 1004 static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val) 1005 { 1006 return ((util_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK; 1007 } 1008 1009 #define REG_A3XX_RB_BLEND_BLUE 0x000020e6 1010 #define A3XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff 1011 #define A3XX_RB_BLEND_BLUE_UINT__SHIFT 0 1012 static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val) 1013 { 1014 return ((val) << A3XX_RB_BLEND_BLUE_UINT__SHIFT) & A3XX_RB_BLEND_BLUE_UINT__MASK; 1015 } 1016 #define A3XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 1017 #define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 1018 static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val) 1019 { 1020 return ((util_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK; 1021 } 1022 1023 #define REG_A3XX_RB_BLEND_ALPHA 0x000020e7 1024 #define A3XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff 1025 #define A3XX_RB_BLEND_ALPHA_UINT__SHIFT 0 1026 static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val) 1027 { 1028 return ((val) << A3XX_RB_BLEND_ALPHA_UINT__SHIFT) & A3XX_RB_BLEND_ALPHA_UINT__MASK; 1029 } 1030 #define A3XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 1031 #define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 1032 static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val) 1033 { 1034 return ((util_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK; 1035 } 1036 1037 #define REG_A3XX_RB_CLEAR_COLOR_DW0 0x000020e8 1038 1039 #define REG_A3XX_RB_CLEAR_COLOR_DW1 0x000020e9 1040 1041 #define REG_A3XX_RB_CLEAR_COLOR_DW2 0x000020ea 1042 1043 #define REG_A3XX_RB_CLEAR_COLOR_DW3 0x000020eb 1044 1045 #define REG_A3XX_RB_COPY_CONTROL 0x000020ec 1046 #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003 1047 #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0 1048 static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) 1049 { 1050 return ((val) << A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK; 1051 } 1052 #define A3XX_RB_COPY_CONTROL_DEPTHCLEAR 0x00000008 1053 #define A3XX_RB_COPY_CONTROL_MODE__MASK 0x00000070 1054 #define A3XX_RB_COPY_CONTROL_MODE__SHIFT 4 1055 static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) 1056 { 1057 return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK; 1058 } 1059 #define A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00 1060 #define A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8 1061 static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) 1062 { 1063 return ((val) << A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK; 1064 } 1065 #define A3XX_RB_COPY_CONTROL_UNK12 0x00001000 1066 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000 1067 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14 1068 static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) 1069 { 1070 return ((val >> 14) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK; 1071 } 1072 1073 #define REG_A3XX_RB_COPY_DEST_BASE 0x000020ed 1074 #define A3XX_RB_COPY_DEST_BASE_BASE__MASK 0xfffffff0 1075 #define A3XX_RB_COPY_DEST_BASE_BASE__SHIFT 4 1076 static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val) 1077 { 1078 return ((val >> 5) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A3XX_RB_COPY_DEST_BASE_BASE__MASK; 1079 } 1080 1081 #define REG_A3XX_RB_COPY_DEST_PITCH 0x000020ee 1082 #define A3XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff 1083 #define A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0 1084 static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) 1085 { 1086 return ((val >> 5) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK; 1087 } 1088 1089 #define REG_A3XX_RB_COPY_DEST_INFO 0x000020ef 1090 #define A3XX_RB_COPY_DEST_INFO_TILE__MASK 0x00000003 1091 #define A3XX_RB_COPY_DEST_INFO_TILE__SHIFT 0 1092 static inline uint32_t A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val) 1093 { 1094 return ((val) << A3XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A3XX_RB_COPY_DEST_INFO_TILE__MASK; 1095 } 1096 #define A3XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc 1097 #define A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2 1098 static inline uint32_t A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val) 1099 { 1100 return ((val) << A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A3XX_RB_COPY_DEST_INFO_FORMAT__MASK; 1101 } 1102 #define A3XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 1103 #define A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 1104 static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) 1105 { 1106 return ((val) << A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A3XX_RB_COPY_DEST_INFO_SWAP__MASK; 1107 } 1108 #define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 1109 #define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 1110 static inline uint32_t A3XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 1111 { 1112 return ((val) << A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 1113 } 1114 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000 1115 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14 1116 static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) 1117 { 1118 return ((val) << A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK; 1119 } 1120 #define A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000 1121 #define A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18 1122 static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) 1123 { 1124 return ((val) << A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK; 1125 } 1126 1127 #define REG_A3XX_RB_DEPTH_CONTROL 0x00002100 1128 #define A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001 1129 #define A3XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002 1130 #define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004 1131 #define A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00000008 1132 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070 1133 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4 1134 static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) 1135 { 1136 return ((val) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK; 1137 } 1138 #define A3XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080 1139 #define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000 1140 1141 #define REG_A3XX_RB_DEPTH_CLEAR 0x00002101 1142 1143 #define REG_A3XX_RB_DEPTH_INFO 0x00002102 1144 #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003 1145 #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 1146 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) 1147 { 1148 return ((val) << A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 1149 } 1150 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff800 1151 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 11 1152 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 1153 { 1154 return ((val >> 12) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 1155 } 1156 1157 #define REG_A3XX_RB_DEPTH_PITCH 0x00002103 1158 #define A3XX_RB_DEPTH_PITCH__MASK 0xffffffff 1159 #define A3XX_RB_DEPTH_PITCH__SHIFT 0 1160 static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val) 1161 { 1162 return ((val >> 3) << A3XX_RB_DEPTH_PITCH__SHIFT) & A3XX_RB_DEPTH_PITCH__MASK; 1163 } 1164 1165 #define REG_A3XX_RB_STENCIL_CONTROL 0x00002104 1166 #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 1167 #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 1168 #define A3XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 1169 #define A3XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 1170 #define A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 1171 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 1172 { 1173 return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC__MASK; 1174 } 1175 #define A3XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 1176 #define A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 1177 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 1178 { 1179 return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL__MASK; 1180 } 1181 #define A3XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 1182 #define A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 1183 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 1184 { 1185 return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS__MASK; 1186 } 1187 #define A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 1188 #define A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 1189 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 1190 { 1191 return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 1192 } 1193 #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 1194 #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 1195 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 1196 { 1197 return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 1198 } 1199 #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 1200 #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 1201 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 1202 { 1203 return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 1204 } 1205 #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 1206 #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 1207 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 1208 { 1209 return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 1210 } 1211 #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 1212 #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 1213 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 1214 { 1215 return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 1216 } 1217 1218 #define REG_A3XX_RB_STENCIL_CLEAR 0x00002105 1219 1220 #define REG_A3XX_RB_STENCIL_BUF_INFO 0x00002106 1221 1222 #define REG_A3XX_RB_STENCIL_BUF_PITCH 0x00002107 1223 1224 #define REG_A3XX_RB_STENCILREFMASK 0x00002108 1225 #define A3XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 1226 #define A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 1227 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 1228 { 1229 return ((val) << A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILREF__MASK; 1230 } 1231 #define A3XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 1232 #define A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 1233 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 1234 { 1235 return ((val) << A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILMASK__MASK; 1236 } 1237 #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 1238 #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 1239 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 1240 { 1241 return ((val) << A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 1242 } 1243 1244 #define REG_A3XX_RB_STENCILREFMASK_BF 0x00002109 1245 #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 1246 #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 1247 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 1248 { 1249 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 1250 } 1251 #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 1252 #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 1253 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 1254 { 1255 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 1256 } 1257 #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 1258 #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 1259 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 1260 { 1261 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 1262 } 1263 1264 #define REG_A3XX_RB_LRZ_VSC_CONTROL 0x0000210c 1265 #define A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE 0x00000002 1266 1267 #define REG_A3XX_RB_WINDOW_OFFSET 0x0000210e 1268 #define A3XX_RB_WINDOW_OFFSET_X__MASK 0x0000ffff 1269 #define A3XX_RB_WINDOW_OFFSET_X__SHIFT 0 1270 static inline uint32_t A3XX_RB_WINDOW_OFFSET_X(uint32_t val) 1271 { 1272 return ((val) << A3XX_RB_WINDOW_OFFSET_X__SHIFT) & A3XX_RB_WINDOW_OFFSET_X__MASK; 1273 } 1274 #define A3XX_RB_WINDOW_OFFSET_Y__MASK 0xffff0000 1275 #define A3XX_RB_WINDOW_OFFSET_Y__SHIFT 16 1276 static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val) 1277 { 1278 return ((val) << A3XX_RB_WINDOW_OFFSET_Y__SHIFT) & A3XX_RB_WINDOW_OFFSET_Y__MASK; 1279 } 1280 1281 #define REG_A3XX_RB_SAMPLE_COUNT_CONTROL 0x00002110 1282 #define A3XX_RB_SAMPLE_COUNT_CONTROL_RESET 0x00000001 1283 #define A3XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 1284 1285 #define REG_A3XX_RB_SAMPLE_COUNT_ADDR 0x00002111 1286 1287 #define REG_A3XX_RB_Z_CLAMP_MIN 0x00002114 1288 1289 #define REG_A3XX_RB_Z_CLAMP_MAX 0x00002115 1290 1291 #define REG_A3XX_VGT_BIN_BASE 0x000021e1 1292 1293 #define REG_A3XX_VGT_BIN_SIZE 0x000021e2 1294 1295 #define REG_A3XX_PC_VSTREAM_CONTROL 0x000021e4 1296 #define A3XX_PC_VSTREAM_CONTROL_SIZE__MASK 0x003f0000 1297 #define A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT 16 1298 static inline uint32_t A3XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val) 1299 { 1300 return ((val) << A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A3XX_PC_VSTREAM_CONTROL_SIZE__MASK; 1301 } 1302 #define A3XX_PC_VSTREAM_CONTROL_N__MASK 0x07c00000 1303 #define A3XX_PC_VSTREAM_CONTROL_N__SHIFT 22 1304 static inline uint32_t A3XX_PC_VSTREAM_CONTROL_N(uint32_t val) 1305 { 1306 return ((val) << A3XX_PC_VSTREAM_CONTROL_N__SHIFT) & A3XX_PC_VSTREAM_CONTROL_N__MASK; 1307 } 1308 1309 #define REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL 0x000021ea 1310 1311 #define REG_A3XX_PC_PRIM_VTX_CNTL 0x000021ec 1312 #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK 0x0000001f 1313 #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT 0 1314 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val) 1315 { 1316 return ((val) << A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK; 1317 } 1318 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK 0x000000e0 1319 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT 5 1320 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 1321 { 1322 return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK; 1323 } 1324 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK 0x00000700 1325 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT 8 1326 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 1327 { 1328 return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK; 1329 } 1330 #define A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000 1331 #define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000 1332 #define A3XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000 1333 1334 #define REG_A3XX_PC_RESTART_INDEX 0x000021ed 1335 1336 #define REG_A3XX_HLSQ_CONTROL_0_REG 0x00002200 1337 #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010 1338 #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4 1339 static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) 1340 { 1341 return ((val) << A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; 1342 } 1343 #define A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040 1344 #define A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200 1345 #define A3XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400 1346 #define A3XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000 1347 #define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000 1348 #define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27 1349 static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) 1350 { 1351 return ((val) << A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK; 1352 } 1353 #define A3XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000 1354 #define A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000 1355 #define A3XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000 1356 #define A3XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000 1357 1358 #define REG_A3XX_HLSQ_CONTROL_1_REG 0x00002201 1359 #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040 1360 #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6 1361 static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) 1362 { 1363 return ((val) << A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK; 1364 } 1365 #define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100 1366 #define A3XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200 1367 #define A3XX_HLSQ_CONTROL_1_REG_ZWCOORD 0x02000000 1368 1369 #define REG_A3XX_HLSQ_CONTROL_2_REG 0x00002202 1370 #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000 1371 #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26 1372 static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) 1373 { 1374 return ((val) << A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK; 1375 } 1376 1377 #define REG_A3XX_HLSQ_CONTROL_3_REG 0x00002203 1378 #define A3XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff 1379 #define A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0 1380 static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val) 1381 { 1382 return ((val) << A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_REGID__MASK; 1383 } 1384 1385 #define REG_A3XX_HLSQ_VS_CONTROL_REG 0x00002204 1386 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff 1387 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0 1388 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) 1389 { 1390 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK; 1391 } 1392 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000 1393 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12 1394 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) 1395 { 1396 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK; 1397 } 1398 #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 1399 #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24 1400 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) 1401 { 1402 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK; 1403 } 1404 1405 #define REG_A3XX_HLSQ_FS_CONTROL_REG 0x00002205 1406 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff 1407 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0 1408 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) 1409 { 1410 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK; 1411 } 1412 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000 1413 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12 1414 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) 1415 { 1416 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK; 1417 } 1418 #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 1419 #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24 1420 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) 1421 { 1422 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK; 1423 } 1424 1425 #define REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG 0x00002206 1426 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff 1427 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT 0 1428 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val) 1429 { 1430 return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK; 1431 } 1432 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000 1433 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT 16 1434 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val) 1435 { 1436 return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK; 1437 } 1438 1439 #define REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG 0x00002207 1440 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff 1441 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT 0 1442 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val) 1443 { 1444 return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK; 1445 } 1446 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000 1447 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT 16 1448 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val) 1449 { 1450 return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK; 1451 } 1452 1453 #define REG_A3XX_HLSQ_CL_NDRANGE_0_REG 0x0000220a 1454 #define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK 0x00000003 1455 #define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT 0 1456 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM(uint32_t val) 1457 { 1458 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK; 1459 } 1460 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK 0x00000ffc 1461 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT 2 1462 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0(uint32_t val) 1463 { 1464 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK; 1465 } 1466 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK 0x003ff000 1467 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT 12 1468 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1(uint32_t val) 1469 { 1470 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK; 1471 } 1472 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK 0xffc00000 1473 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT 22 1474 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2(uint32_t val) 1475 { 1476 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK; 1477 } 1478 1479 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK(uint32_t i0) { return 0x0000220b + 0x2*i0; } 1480 1481 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0; } 1482 1483 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { return 0x0000220c + 0x2*i0; } 1484 1485 #define REG_A3XX_HLSQ_CL_CONTROL_0_REG 0x00002211 1486 1487 #define REG_A3XX_HLSQ_CL_CONTROL_1_REG 0x00002212 1488 1489 #define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG 0x00002214 1490 1491 static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP(uint32_t i0) { return 0x00002215 + 0x1*i0; } 1492 1493 static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO(uint32_t i0) { return 0x00002215 + 0x1*i0; } 1494 1495 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Y_REG 0x00002216 1496 1497 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG 0x00002217 1498 1499 #define REG_A3XX_HLSQ_CL_WG_OFFSET_REG 0x0000221a 1500 1501 #define REG_A3XX_VFD_CONTROL_0 0x00002240 1502 #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x0003ffff 1503 #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0 1504 static inline uint32_t A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) 1505 { 1506 return ((val) << A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK; 1507 } 1508 #define A3XX_VFD_CONTROL_0_PACKETSIZE__MASK 0x003c0000 1509 #define A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT 18 1510 static inline uint32_t A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val) 1511 { 1512 return ((val) << A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT) & A3XX_VFD_CONTROL_0_PACKETSIZE__MASK; 1513 } 1514 #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x07c00000 1515 #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 22 1516 static inline uint32_t A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) 1517 { 1518 return ((val) << A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK; 1519 } 1520 #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xf8000000 1521 #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 27 1522 static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) 1523 { 1524 return ((val) << A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK; 1525 } 1526 1527 #define REG_A3XX_VFD_CONTROL_1 0x00002241 1528 #define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff 1529 #define A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0 1530 static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) 1531 { 1532 return ((val) << A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK; 1533 } 1534 #define A3XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000 1535 #define A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16 1536 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 1537 { 1538 return ((val) << A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A3XX_VFD_CONTROL_1_REGID4VTX__MASK; 1539 } 1540 #define A3XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000 1541 #define A3XX_VFD_CONTROL_1_REGID4INST__SHIFT 24 1542 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 1543 { 1544 return ((val) << A3XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A3XX_VFD_CONTROL_1_REGID4INST__MASK; 1545 } 1546 1547 #define REG_A3XX_VFD_INDEX_MIN 0x00002242 1548 1549 #define REG_A3XX_VFD_INDEX_MAX 0x00002243 1550 1551 #define REG_A3XX_VFD_INSTANCEID_OFFSET 0x00002244 1552 1553 #define REG_A3XX_VFD_INDEX_OFFSET 0x00002245 1554 1555 #define REG_A3XX_VFD_INDEX_OFFSET 0x00002245 1556 1557 static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0) { return 0x00002246 + 0x2*i0; } 1558 1559 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; } 1560 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f 1561 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0 1562 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) 1563 { 1564 return ((val) << A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK; 1565 } 1566 #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80 1567 #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7 1568 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) 1569 { 1570 return ((val) << A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK; 1571 } 1572 #define A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00020000 1573 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK 0x00fc0000 1574 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT 18 1575 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val) 1576 { 1577 return ((val) << A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK; 1578 } 1579 #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK 0xff000000 1580 #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT 24 1581 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val) 1582 { 1583 return ((val) << A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK; 1584 } 1585 1586 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x00002247 + 0x2*i0; } 1587 1588 static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0) { return 0x00002266 + 0x1*i0; } 1589 1590 static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x00002266 + 0x1*i0; } 1591 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f 1592 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0 1593 static inline uint32_t A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) 1594 { 1595 return ((val) << A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK; 1596 } 1597 #define A3XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010 1598 #define A3XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0 1599 #define A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6 1600 static inline uint32_t A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val) 1601 { 1602 return ((val) << A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A3XX_VFD_DECODE_INSTR_FORMAT__MASK; 1603 } 1604 #define A3XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000 1605 #define A3XX_VFD_DECODE_INSTR_REGID__SHIFT 12 1606 static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val) 1607 { 1608 return ((val) << A3XX_VFD_DECODE_INSTR_REGID__SHIFT) & A3XX_VFD_DECODE_INSTR_REGID__MASK; 1609 } 1610 #define A3XX_VFD_DECODE_INSTR_INT 0x00100000 1611 #define A3XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000 1612 #define A3XX_VFD_DECODE_INSTR_SWAP__SHIFT 22 1613 static inline uint32_t A3XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 1614 { 1615 return ((val) << A3XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A3XX_VFD_DECODE_INSTR_SWAP__MASK; 1616 } 1617 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000 1618 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24 1619 static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) 1620 { 1621 return ((val) << A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK; 1622 } 1623 #define A3XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000 1624 #define A3XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000 1625 1626 #define REG_A3XX_VFD_VS_THREADING_THRESHOLD 0x0000227e 1627 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK 0x0000000f 1628 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT 0 1629 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val) 1630 { 1631 return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK; 1632 } 1633 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK 0x0000ff00 1634 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT 8 1635 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val) 1636 { 1637 return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK; 1638 } 1639 1640 #define REG_A3XX_VPC_ATTR 0x00002280 1641 #define A3XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff 1642 #define A3XX_VPC_ATTR_TOTALATTR__SHIFT 0 1643 static inline uint32_t A3XX_VPC_ATTR_TOTALATTR(uint32_t val) 1644 { 1645 return ((val) << A3XX_VPC_ATTR_TOTALATTR__SHIFT) & A3XX_VPC_ATTR_TOTALATTR__MASK; 1646 } 1647 #define A3XX_VPC_ATTR_PSIZE 0x00000200 1648 #define A3XX_VPC_ATTR_THRDASSIGN__MASK 0x0ffff000 1649 #define A3XX_VPC_ATTR_THRDASSIGN__SHIFT 12 1650 static inline uint32_t A3XX_VPC_ATTR_THRDASSIGN(uint32_t val) 1651 { 1652 return ((val) << A3XX_VPC_ATTR_THRDASSIGN__SHIFT) & A3XX_VPC_ATTR_THRDASSIGN__MASK; 1653 } 1654 #define A3XX_VPC_ATTR_LMSIZE__MASK 0xf0000000 1655 #define A3XX_VPC_ATTR_LMSIZE__SHIFT 28 1656 static inline uint32_t A3XX_VPC_ATTR_LMSIZE(uint32_t val) 1657 { 1658 return ((val) << A3XX_VPC_ATTR_LMSIZE__SHIFT) & A3XX_VPC_ATTR_LMSIZE__MASK; 1659 } 1660 1661 #define REG_A3XX_VPC_PACK 0x00002281 1662 #define A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00 1663 #define A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8 1664 static inline uint32_t A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) 1665 { 1666 return ((val) << A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK; 1667 } 1668 #define A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000 1669 #define A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16 1670 static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) 1671 { 1672 return ((val) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK; 1673 } 1674 1675 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002282 + 0x1*i0; } 1676 1677 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002282 + 0x1*i0; } 1678 #define A3XX_VPC_VARYING_INTERP_MODE_C0__MASK 0x00000003 1679 #define A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT 0 1680 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C0(enum a3xx_intp_mode val) 1681 { 1682 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C0__MASK; 1683 } 1684 #define A3XX_VPC_VARYING_INTERP_MODE_C1__MASK 0x0000000c 1685 #define A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT 2 1686 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C1(enum a3xx_intp_mode val) 1687 { 1688 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C1__MASK; 1689 } 1690 #define A3XX_VPC_VARYING_INTERP_MODE_C2__MASK 0x00000030 1691 #define A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT 4 1692 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C2(enum a3xx_intp_mode val) 1693 { 1694 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C2__MASK; 1695 } 1696 #define A3XX_VPC_VARYING_INTERP_MODE_C3__MASK 0x000000c0 1697 #define A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT 6 1698 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C3(enum a3xx_intp_mode val) 1699 { 1700 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C3__MASK; 1701 } 1702 #define A3XX_VPC_VARYING_INTERP_MODE_C4__MASK 0x00000300 1703 #define A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT 8 1704 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C4(enum a3xx_intp_mode val) 1705 { 1706 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C4__MASK; 1707 } 1708 #define A3XX_VPC_VARYING_INTERP_MODE_C5__MASK 0x00000c00 1709 #define A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT 10 1710 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C5(enum a3xx_intp_mode val) 1711 { 1712 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C5__MASK; 1713 } 1714 #define A3XX_VPC_VARYING_INTERP_MODE_C6__MASK 0x00003000 1715 #define A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT 12 1716 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C6(enum a3xx_intp_mode val) 1717 { 1718 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C6__MASK; 1719 } 1720 #define A3XX_VPC_VARYING_INTERP_MODE_C7__MASK 0x0000c000 1721 #define A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT 14 1722 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C7(enum a3xx_intp_mode val) 1723 { 1724 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C7__MASK; 1725 } 1726 #define A3XX_VPC_VARYING_INTERP_MODE_C8__MASK 0x00030000 1727 #define A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT 16 1728 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C8(enum a3xx_intp_mode val) 1729 { 1730 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C8__MASK; 1731 } 1732 #define A3XX_VPC_VARYING_INTERP_MODE_C9__MASK 0x000c0000 1733 #define A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT 18 1734 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C9(enum a3xx_intp_mode val) 1735 { 1736 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C9__MASK; 1737 } 1738 #define A3XX_VPC_VARYING_INTERP_MODE_CA__MASK 0x00300000 1739 #define A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT 20 1740 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CA(enum a3xx_intp_mode val) 1741 { 1742 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CA__MASK; 1743 } 1744 #define A3XX_VPC_VARYING_INTERP_MODE_CB__MASK 0x00c00000 1745 #define A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT 22 1746 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CB(enum a3xx_intp_mode val) 1747 { 1748 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CB__MASK; 1749 } 1750 #define A3XX_VPC_VARYING_INTERP_MODE_CC__MASK 0x03000000 1751 #define A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT 24 1752 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CC(enum a3xx_intp_mode val) 1753 { 1754 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CC__MASK; 1755 } 1756 #define A3XX_VPC_VARYING_INTERP_MODE_CD__MASK 0x0c000000 1757 #define A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT 26 1758 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CD(enum a3xx_intp_mode val) 1759 { 1760 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CD__MASK; 1761 } 1762 #define A3XX_VPC_VARYING_INTERP_MODE_CE__MASK 0x30000000 1763 #define A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT 28 1764 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CE(enum a3xx_intp_mode val) 1765 { 1766 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CE__MASK; 1767 } 1768 #define A3XX_VPC_VARYING_INTERP_MODE_CF__MASK 0xc0000000 1769 #define A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT 30 1770 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CF(enum a3xx_intp_mode val) 1771 { 1772 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CF__MASK; 1773 } 1774 1775 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; } 1776 1777 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; } 1778 1779 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0 0x0000228a 1780 1781 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_1 0x0000228b 1782 1783 #define REG_A3XX_SP_SP_CTRL_REG 0x000022c0 1784 #define A3XX_SP_SP_CTRL_REG_RESOLVE 0x00010000 1785 #define A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK 0x00040000 1786 #define A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT 18 1787 static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val) 1788 { 1789 return ((val) << A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK; 1790 } 1791 #define A3XX_SP_SP_CTRL_REG_BINNING 0x00080000 1792 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK 0x00300000 1793 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT 20 1794 static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val) 1795 { 1796 return ((val) << A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK; 1797 } 1798 #define A3XX_SP_SP_CTRL_REG_L0MODE__MASK 0x00c00000 1799 #define A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT 22 1800 static inline uint32_t A3XX_SP_SP_CTRL_REG_L0MODE(uint32_t val) 1801 { 1802 return ((val) << A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT) & A3XX_SP_SP_CTRL_REG_L0MODE__MASK; 1803 } 1804 1805 #define REG_A3XX_SP_VS_CTRL_REG0 0x000022c4 1806 #define A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 1807 #define A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 1808 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 1809 { 1810 return ((val) << A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK; 1811 } 1812 #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002 1813 #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1 1814 static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) 1815 { 1816 return ((val) << A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK; 1817 } 1818 #define A3XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004 1819 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 1820 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 1821 static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 1822 { 1823 return ((val) << A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 1824 } 1825 #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 1826 #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 1827 static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 1828 { 1829 return ((val) << A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 1830 } 1831 #define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 1832 #define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 1833 static inline uint32_t A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 1834 { 1835 return ((val) << A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK; 1836 } 1837 #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000 1838 #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20 1839 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 1840 { 1841 return ((val) << A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; 1842 } 1843 #define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000 1844 #define A3XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000 1845 #define A3XX_SP_VS_CTRL_REG0_COMPUTEMODE 0x00800000 1846 #define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK 0xff000000 1847 #define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT 24 1848 static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val) 1849 { 1850 return ((val) << A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG0_LENGTH__MASK; 1851 } 1852 1853 #define REG_A3XX_SP_VS_CTRL_REG1 0x000022c5 1854 #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff 1855 #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0 1856 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) 1857 { 1858 return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK; 1859 } 1860 #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00 1861 #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10 1862 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) 1863 { 1864 return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK; 1865 } 1866 #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000 1867 #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24 1868 static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) 1869 { 1870 return ((val) << A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK; 1871 } 1872 1873 #define REG_A3XX_SP_VS_PARAM_REG 0x000022c6 1874 #define A3XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff 1875 #define A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0 1876 static inline uint32_t A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) 1877 { 1878 return ((val) << A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_POSREGID__MASK; 1879 } 1880 #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00 1881 #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8 1882 static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) 1883 { 1884 return ((val) << A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK; 1885 } 1886 #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000 1887 #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20 1888 static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) 1889 { 1890 return ((val) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; 1891 } 1892 1893 static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 1894 1895 static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 1896 #define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff 1897 #define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 1898 static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 1899 { 1900 return ((val) << A3XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_A_REGID__MASK; 1901 } 1902 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00 1903 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9 1904 static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 1905 { 1906 return ((val) << A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 1907 } 1908 #define A3XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000 1909 #define A3XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 1910 static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 1911 { 1912 return ((val) << A3XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_B_REGID__MASK; 1913 } 1914 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000 1915 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25 1916 static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 1917 { 1918 return ((val) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 1919 } 1920 1921 static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; } 1922 1923 static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; } 1924 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 1925 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 1926 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 1927 { 1928 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 1929 } 1930 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 1931 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 1932 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 1933 { 1934 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 1935 } 1936 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 1937 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 1938 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 1939 { 1940 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 1941 } 1942 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 1943 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 1944 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 1945 { 1946 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 1947 } 1948 1949 #define REG_A3XX_SP_VS_OBJ_OFFSET_REG 0x000022d4 1950 #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1951 #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1952 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1953 { 1954 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1955 } 1956 #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1957 #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1958 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1959 { 1960 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1961 } 1962 1963 #define REG_A3XX_SP_VS_OBJ_START_REG 0x000022d5 1964 1965 #define REG_A3XX_SP_VS_PVT_MEM_PARAM_REG 0x000022d6 1966 1967 #define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG 0x000022d7 1968 1969 #define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG 0x000022d8 1970 1971 #define REG_A3XX_SP_VS_LENGTH_REG 0x000022df 1972 #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff 1973 #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT 0 1974 static inline uint32_t A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val) 1975 { 1976 return ((val) << A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK; 1977 } 1978 1979 #define REG_A3XX_SP_FS_CTRL_REG0 0x000022e0 1980 #define A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 1981 #define A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 1982 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 1983 { 1984 return ((val) << A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK; 1985 } 1986 #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002 1987 #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1 1988 static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) 1989 { 1990 return ((val) << A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK; 1991 } 1992 #define A3XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004 1993 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 1994 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 1995 static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 1996 { 1997 return ((val) << A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 1998 } 1999 #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 2000 #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 2001 static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 2002 { 2003 return ((val) << A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 2004 } 2005 #define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 2006 #define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 2007 static inline uint32_t A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 2008 { 2009 return ((val) << A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK; 2010 } 2011 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 2012 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 2013 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 2014 { 2015 return ((val) << A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 2016 } 2017 #define A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000 2018 #define A3XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000 2019 #define A3XX_SP_FS_CTRL_REG0_COMPUTEMODE 0x00800000 2020 #define A3XX_SP_FS_CTRL_REG0_LENGTH__MASK 0xff000000 2021 #define A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT 24 2022 static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val) 2023 { 2024 return ((val) << A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG0_LENGTH__MASK; 2025 } 2026 2027 #define REG_A3XX_SP_FS_CTRL_REG1 0x000022e1 2028 #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff 2029 #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0 2030 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) 2031 { 2032 return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK; 2033 } 2034 #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00 2035 #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10 2036 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) 2037 { 2038 return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK; 2039 } 2040 #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x00f00000 2041 #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 20 2042 static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) 2043 { 2044 return ((val) << A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK; 2045 } 2046 #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK 0x3f000000 2047 #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT 24 2048 static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val) 2049 { 2050 return ((val) << A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT) & A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK; 2051 } 2052 2053 #define REG_A3XX_SP_FS_OBJ_OFFSET_REG 0x000022e2 2054 #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2055 #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2056 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2057 { 2058 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2059 } 2060 #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2061 #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2062 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2063 { 2064 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2065 } 2066 2067 #define REG_A3XX_SP_FS_OBJ_START_REG 0x000022e3 2068 2069 #define REG_A3XX_SP_FS_PVT_MEM_PARAM_REG 0x000022e4 2070 2071 #define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG 0x000022e5 2072 2073 #define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG 0x000022e6 2074 2075 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0 0x000022e8 2076 2077 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1 0x000022e9 2078 2079 #define REG_A3XX_SP_FS_OUTPUT_REG 0x000022ec 2080 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080 2081 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00 2082 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8 2083 static inline uint32_t A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) 2084 { 2085 return ((val) << A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK; 2086 } 2087 2088 static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0) { return 0x000022f0 + 0x1*i0; } 2089 2090 static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f0 + 0x1*i0; } 2091 #define A3XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff 2092 #define A3XX_SP_FS_MRT_REG_REGID__SHIFT 0 2093 static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val) 2094 { 2095 return ((val) << A3XX_SP_FS_MRT_REG_REGID__SHIFT) & A3XX_SP_FS_MRT_REG_REGID__MASK; 2096 } 2097 #define A3XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100 2098 #define A3XX_SP_FS_MRT_REG_SINT 0x00000400 2099 #define A3XX_SP_FS_MRT_REG_UINT 0x00000800 2100 2101 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0) { return 0x000022f4 + 0x1*i0; } 2102 2103 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0) { return 0x000022f4 + 0x1*i0; } 2104 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK 0x0000003f 2105 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT 0 2106 static inline uint32_t A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val) 2107 { 2108 return ((val) << A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT) & A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK; 2109 } 2110 2111 #define REG_A3XX_SP_FS_LENGTH_REG 0x000022ff 2112 #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff 2113 #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT 0 2114 static inline uint32_t A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val) 2115 { 2116 return ((val) << A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK; 2117 } 2118 2119 #define REG_A3XX_PA_SC_AA_CONFIG 0x00002301 2120 2121 #define REG_A3XX_TPL1_TP_VS_TEX_OFFSET 0x00002340 2122 #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff 2123 #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0 2124 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) 2125 { 2126 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK; 2127 } 2128 #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00 2129 #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8 2130 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) 2131 { 2132 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK; 2133 } 2134 #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000 2135 #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT 16 2136 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val) 2137 { 2138 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK; 2139 } 2140 2141 #define REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002341 2142 2143 #define REG_A3XX_TPL1_TP_FS_TEX_OFFSET 0x00002342 2144 #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff 2145 #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0 2146 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) 2147 { 2148 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK; 2149 } 2150 #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00 2151 #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8 2152 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) 2153 { 2154 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK; 2155 } 2156 #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000 2157 #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT 16 2158 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val) 2159 { 2160 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK; 2161 } 2162 2163 #define REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x00002343 2164 2165 #define REG_A3XX_VBIF_CLKON 0x00003001 2166 2167 #define REG_A3XX_VBIF_FIXED_SORT_EN 0x0000300c 2168 2169 #define REG_A3XX_VBIF_FIXED_SORT_SEL0 0x0000300d 2170 2171 #define REG_A3XX_VBIF_FIXED_SORT_SEL1 0x0000300e 2172 2173 #define REG_A3XX_VBIF_ABIT_SORT 0x0000301c 2174 2175 #define REG_A3XX_VBIF_ABIT_SORT_CONF 0x0000301d 2176 2177 #define REG_A3XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 2178 2179 #define REG_A3XX_VBIF_IN_RD_LIM_CONF0 0x0000302c 2180 2181 #define REG_A3XX_VBIF_IN_RD_LIM_CONF1 0x0000302d 2182 2183 #define REG_A3XX_VBIF_IN_WR_LIM_CONF0 0x00003030 2184 2185 #define REG_A3XX_VBIF_IN_WR_LIM_CONF1 0x00003031 2186 2187 #define REG_A3XX_VBIF_OUT_RD_LIM_CONF0 0x00003034 2188 2189 #define REG_A3XX_VBIF_OUT_WR_LIM_CONF0 0x00003035 2190 2191 #define REG_A3XX_VBIF_DDR_OUT_MAX_BURST 0x00003036 2192 2193 #define REG_A3XX_VBIF_ARB_CTL 0x0000303c 2194 2195 #define REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049 2196 2197 #define REG_A3XX_VBIF_OUT_AXI_AMEMTYPE_CONF0 0x00003058 2198 2199 #define REG_A3XX_VBIF_OUT_AXI_AOOO_EN 0x0000305e 2200 2201 #define REG_A3XX_VBIF_OUT_AXI_AOOO 0x0000305f 2202 2203 #define REG_A3XX_VBIF_PERF_CNT_EN 0x00003070 2204 #define A3XX_VBIF_PERF_CNT_EN_CNT0 0x00000001 2205 #define A3XX_VBIF_PERF_CNT_EN_CNT1 0x00000002 2206 #define A3XX_VBIF_PERF_CNT_EN_PWRCNT0 0x00000004 2207 #define A3XX_VBIF_PERF_CNT_EN_PWRCNT1 0x00000008 2208 #define A3XX_VBIF_PERF_CNT_EN_PWRCNT2 0x00000010 2209 2210 #define REG_A3XX_VBIF_PERF_CNT_CLR 0x00003071 2211 #define A3XX_VBIF_PERF_CNT_CLR_CNT0 0x00000001 2212 #define A3XX_VBIF_PERF_CNT_CLR_CNT1 0x00000002 2213 #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT0 0x00000004 2214 #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT1 0x00000008 2215 #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT2 0x00000010 2216 2217 #define REG_A3XX_VBIF_PERF_CNT_SEL 0x00003072 2218 2219 #define REG_A3XX_VBIF_PERF_CNT0_LO 0x00003073 2220 2221 #define REG_A3XX_VBIF_PERF_CNT0_HI 0x00003074 2222 2223 #define REG_A3XX_VBIF_PERF_CNT1_LO 0x00003075 2224 2225 #define REG_A3XX_VBIF_PERF_CNT1_HI 0x00003076 2226 2227 #define REG_A3XX_VBIF_PERF_PWR_CNT0_LO 0x00003077 2228 2229 #define REG_A3XX_VBIF_PERF_PWR_CNT0_HI 0x00003078 2230 2231 #define REG_A3XX_VBIF_PERF_PWR_CNT1_LO 0x00003079 2232 2233 #define REG_A3XX_VBIF_PERF_PWR_CNT1_HI 0x0000307a 2234 2235 #define REG_A3XX_VBIF_PERF_PWR_CNT2_LO 0x0000307b 2236 2237 #define REG_A3XX_VBIF_PERF_PWR_CNT2_HI 0x0000307c 2238 2239 #define REG_A3XX_VSC_BIN_SIZE 0x00000c01 2240 #define A3XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 2241 #define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 2242 static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 2243 { 2244 return ((val >> 5) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A3XX_VSC_BIN_SIZE_WIDTH__MASK; 2245 } 2246 #define A3XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 2247 #define A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5 2248 static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 2249 { 2250 return ((val >> 5) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK; 2251 } 2252 2253 #define REG_A3XX_VSC_SIZE_ADDRESS 0x00000c02 2254 2255 static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 2256 2257 static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 2258 #define A3XX_VSC_PIPE_CONFIG_X__MASK 0x000003ff 2259 #define A3XX_VSC_PIPE_CONFIG_X__SHIFT 0 2260 static inline uint32_t A3XX_VSC_PIPE_CONFIG_X(uint32_t val) 2261 { 2262 return ((val) << A3XX_VSC_PIPE_CONFIG_X__SHIFT) & A3XX_VSC_PIPE_CONFIG_X__MASK; 2263 } 2264 #define A3XX_VSC_PIPE_CONFIG_Y__MASK 0x000ffc00 2265 #define A3XX_VSC_PIPE_CONFIG_Y__SHIFT 10 2266 static inline uint32_t A3XX_VSC_PIPE_CONFIG_Y(uint32_t val) 2267 { 2268 return ((val) << A3XX_VSC_PIPE_CONFIG_Y__SHIFT) & A3XX_VSC_PIPE_CONFIG_Y__MASK; 2269 } 2270 #define A3XX_VSC_PIPE_CONFIG_W__MASK 0x00f00000 2271 #define A3XX_VSC_PIPE_CONFIG_W__SHIFT 20 2272 static inline uint32_t A3XX_VSC_PIPE_CONFIG_W(uint32_t val) 2273 { 2274 return ((val) << A3XX_VSC_PIPE_CONFIG_W__SHIFT) & A3XX_VSC_PIPE_CONFIG_W__MASK; 2275 } 2276 #define A3XX_VSC_PIPE_CONFIG_H__MASK 0x0f000000 2277 #define A3XX_VSC_PIPE_CONFIG_H__SHIFT 24 2278 static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val) 2279 { 2280 return ((val) << A3XX_VSC_PIPE_CONFIG_H__SHIFT) & A3XX_VSC_PIPE_CONFIG_H__MASK; 2281 } 2282 2283 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } 2284 2285 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } 2286 2287 #define REG_A3XX_VSC_BIN_CONTROL 0x00000c3c 2288 #define A3XX_VSC_BIN_CONTROL_BINNING_ENABLE 0x00000001 2289 2290 #define REG_A3XX_UNKNOWN_0C3D 0x00000c3d 2291 2292 #define REG_A3XX_PC_PERFCOUNTER0_SELECT 0x00000c48 2293 2294 #define REG_A3XX_PC_PERFCOUNTER1_SELECT 0x00000c49 2295 2296 #define REG_A3XX_PC_PERFCOUNTER2_SELECT 0x00000c4a 2297 2298 #define REG_A3XX_PC_PERFCOUNTER3_SELECT 0x00000c4b 2299 2300 #define REG_A3XX_GRAS_TSE_DEBUG_ECO 0x00000c81 2301 2302 #define REG_A3XX_GRAS_PERFCOUNTER0_SELECT 0x00000c88 2303 2304 #define REG_A3XX_GRAS_PERFCOUNTER1_SELECT 0x00000c89 2305 2306 #define REG_A3XX_GRAS_PERFCOUNTER2_SELECT 0x00000c8a 2307 2308 #define REG_A3XX_GRAS_PERFCOUNTER3_SELECT 0x00000c8b 2309 2310 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } 2311 2312 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } 2313 2314 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0) { return 0x00000ca1 + 0x4*i0; } 2315 2316 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0) { return 0x00000ca2 + 0x4*i0; } 2317 2318 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) { return 0x00000ca3 + 0x4*i0; } 2319 2320 #define REG_A3XX_RB_GMEM_BASE_ADDR 0x00000cc0 2321 2322 #define REG_A3XX_RB_DEBUG_ECO_CONTROLS_ADDR 0x00000cc1 2323 2324 #define REG_A3XX_RB_PERFCOUNTER0_SELECT 0x00000cc6 2325 2326 #define REG_A3XX_RB_PERFCOUNTER1_SELECT 0x00000cc7 2327 2328 #define REG_A3XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0 2329 #define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff 2330 #define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0 2331 static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) 2332 { 2333 return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK; 2334 } 2335 #define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x0fffc000 2336 #define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 14 2337 static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) 2338 { 2339 return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK; 2340 } 2341 2342 #define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT 0x00000e00 2343 2344 #define REG_A3XX_HLSQ_PERFCOUNTER1_SELECT 0x00000e01 2345 2346 #define REG_A3XX_HLSQ_PERFCOUNTER2_SELECT 0x00000e02 2347 2348 #define REG_A3XX_HLSQ_PERFCOUNTER3_SELECT 0x00000e03 2349 2350 #define REG_A3XX_HLSQ_PERFCOUNTER4_SELECT 0x00000e04 2351 2352 #define REG_A3XX_HLSQ_PERFCOUNTER5_SELECT 0x00000e05 2353 2354 #define REG_A3XX_UNKNOWN_0E43 0x00000e43 2355 2356 #define REG_A3XX_VFD_PERFCOUNTER0_SELECT 0x00000e44 2357 2358 #define REG_A3XX_VFD_PERFCOUNTER1_SELECT 0x00000e45 2359 2360 #define REG_A3XX_VPC_VPC_DEBUG_RAM_SEL 0x00000e61 2361 2362 #define REG_A3XX_VPC_VPC_DEBUG_RAM_READ 0x00000e62 2363 2364 #define REG_A3XX_VPC_PERFCOUNTER0_SELECT 0x00000e64 2365 2366 #define REG_A3XX_VPC_PERFCOUNTER1_SELECT 0x00000e65 2367 2368 #define REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG 0x00000e82 2369 2370 #define REG_A3XX_UCHE_PERFCOUNTER0_SELECT 0x00000e84 2371 2372 #define REG_A3XX_UCHE_PERFCOUNTER1_SELECT 0x00000e85 2373 2374 #define REG_A3XX_UCHE_PERFCOUNTER2_SELECT 0x00000e86 2375 2376 #define REG_A3XX_UCHE_PERFCOUNTER3_SELECT 0x00000e87 2377 2378 #define REG_A3XX_UCHE_PERFCOUNTER4_SELECT 0x00000e88 2379 2380 #define REG_A3XX_UCHE_PERFCOUNTER5_SELECT 0x00000e89 2381 2382 #define REG_A3XX_UCHE_CACHE_INVALIDATE0_REG 0x00000ea0 2383 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK 0x0fffffff 2384 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT 0 2385 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val) 2386 { 2387 return ((val) << A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK; 2388 } 2389 2390 #define REG_A3XX_UCHE_CACHE_INVALIDATE1_REG 0x00000ea1 2391 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK 0x0fffffff 2392 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT 0 2393 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val) 2394 { 2395 return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK; 2396 } 2397 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK 0x30000000 2398 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT 28 2399 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val) 2400 { 2401 return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK; 2402 } 2403 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE 0x80000000 2404 2405 #define REG_A3XX_UNKNOWN_0EA6 0x00000ea6 2406 2407 #define REG_A3XX_SP_PERFCOUNTER0_SELECT 0x00000ec4 2408 2409 #define REG_A3XX_SP_PERFCOUNTER1_SELECT 0x00000ec5 2410 2411 #define REG_A3XX_SP_PERFCOUNTER2_SELECT 0x00000ec6 2412 2413 #define REG_A3XX_SP_PERFCOUNTER3_SELECT 0x00000ec7 2414 2415 #define REG_A3XX_SP_PERFCOUNTER4_SELECT 0x00000ec8 2416 2417 #define REG_A3XX_SP_PERFCOUNTER5_SELECT 0x00000ec9 2418 2419 #define REG_A3XX_SP_PERFCOUNTER6_SELECT 0x00000eca 2420 2421 #define REG_A3XX_SP_PERFCOUNTER7_SELECT 0x00000ecb 2422 2423 #define REG_A3XX_UNKNOWN_0EE0 0x00000ee0 2424 2425 #define REG_A3XX_UNKNOWN_0F03 0x00000f03 2426 2427 #define REG_A3XX_TP_PERFCOUNTER0_SELECT 0x00000f04 2428 2429 #define REG_A3XX_TP_PERFCOUNTER1_SELECT 0x00000f05 2430 2431 #define REG_A3XX_TP_PERFCOUNTER2_SELECT 0x00000f06 2432 2433 #define REG_A3XX_TP_PERFCOUNTER3_SELECT 0x00000f07 2434 2435 #define REG_A3XX_TP_PERFCOUNTER4_SELECT 0x00000f08 2436 2437 #define REG_A3XX_TP_PERFCOUNTER5_SELECT 0x00000f09 2438 2439 #define REG_A3XX_VGT_CL_INITIATOR 0x000021f0 2440 2441 #define REG_A3XX_VGT_EVENT_INITIATOR 0x000021f9 2442 2443 #define REG_A3XX_VGT_DRAW_INITIATOR 0x000021fc 2444 #define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f 2445 #define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 2446 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) 2447 { 2448 return ((val) << A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK; 2449 } 2450 #define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 2451 #define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 2452 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) 2453 { 2454 return ((val) << A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK; 2455 } 2456 #define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600 2457 #define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9 2458 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) 2459 { 2460 return ((val) << A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK; 2461 } 2462 #define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800 2463 #define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11 2464 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) 2465 { 2466 return ((val) << A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK; 2467 } 2468 #define A3XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000 2469 #define A3XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000 2470 #define A3XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000 2471 #define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK 0xff000000 2472 #define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT 24 2473 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) 2474 { 2475 return ((val) << A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK; 2476 } 2477 2478 #define REG_A3XX_VGT_IMMED_DATA 0x000021fd 2479 2480 #define REG_A3XX_TEX_SAMP_0 0x00000000 2481 #define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR 0x00000002 2482 #define A3XX_TEX_SAMP_0_XY_MAG__MASK 0x0000000c 2483 #define A3XX_TEX_SAMP_0_XY_MAG__SHIFT 2 2484 static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val) 2485 { 2486 return ((val) << A3XX_TEX_SAMP_0_XY_MAG__SHIFT) & A3XX_TEX_SAMP_0_XY_MAG__MASK; 2487 } 2488 #define A3XX_TEX_SAMP_0_XY_MIN__MASK 0x00000030 2489 #define A3XX_TEX_SAMP_0_XY_MIN__SHIFT 4 2490 static inline uint32_t A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val) 2491 { 2492 return ((val) << A3XX_TEX_SAMP_0_XY_MIN__SHIFT) & A3XX_TEX_SAMP_0_XY_MIN__MASK; 2493 } 2494 #define A3XX_TEX_SAMP_0_WRAP_S__MASK 0x000001c0 2495 #define A3XX_TEX_SAMP_0_WRAP_S__SHIFT 6 2496 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val) 2497 { 2498 return ((val) << A3XX_TEX_SAMP_0_WRAP_S__SHIFT) & A3XX_TEX_SAMP_0_WRAP_S__MASK; 2499 } 2500 #define A3XX_TEX_SAMP_0_WRAP_T__MASK 0x00000e00 2501 #define A3XX_TEX_SAMP_0_WRAP_T__SHIFT 9 2502 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val) 2503 { 2504 return ((val) << A3XX_TEX_SAMP_0_WRAP_T__SHIFT) & A3XX_TEX_SAMP_0_WRAP_T__MASK; 2505 } 2506 #define A3XX_TEX_SAMP_0_WRAP_R__MASK 0x00007000 2507 #define A3XX_TEX_SAMP_0_WRAP_R__SHIFT 12 2508 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val) 2509 { 2510 return ((val) << A3XX_TEX_SAMP_0_WRAP_R__SHIFT) & A3XX_TEX_SAMP_0_WRAP_R__MASK; 2511 } 2512 #define A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK 0x00700000 2513 #define A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT 20 2514 static inline uint32_t A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val) 2515 { 2516 return ((val) << A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT) & A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK; 2517 } 2518 #define A3XX_TEX_SAMP_0_UNNORM_COORDS 0x80000000 2519 2520 #define REG_A3XX_TEX_SAMP_1 0x00000001 2521 #define A3XX_TEX_SAMP_1_LOD_BIAS__MASK 0x000007ff 2522 #define A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT 0 2523 static inline uint32_t A3XX_TEX_SAMP_1_LOD_BIAS(float val) 2524 { 2525 return ((((int32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT) & A3XX_TEX_SAMP_1_LOD_BIAS__MASK; 2526 } 2527 #define A3XX_TEX_SAMP_1_MAX_LOD__MASK 0x003ff000 2528 #define A3XX_TEX_SAMP_1_MAX_LOD__SHIFT 12 2529 static inline uint32_t A3XX_TEX_SAMP_1_MAX_LOD(float val) 2530 { 2531 return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A3XX_TEX_SAMP_1_MAX_LOD__MASK; 2532 } 2533 #define A3XX_TEX_SAMP_1_MIN_LOD__MASK 0xffc00000 2534 #define A3XX_TEX_SAMP_1_MIN_LOD__SHIFT 22 2535 static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val) 2536 { 2537 return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A3XX_TEX_SAMP_1_MIN_LOD__MASK; 2538 } 2539 2540 #define REG_A3XX_TEX_CONST_0 0x00000000 2541 #define A3XX_TEX_CONST_0_TILED 0x00000001 2542 #define A3XX_TEX_CONST_0_SRGB 0x00000004 2543 #define A3XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 2544 #define A3XX_TEX_CONST_0_SWIZ_X__SHIFT 4 2545 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val) 2546 { 2547 return ((val) << A3XX_TEX_CONST_0_SWIZ_X__SHIFT) & A3XX_TEX_CONST_0_SWIZ_X__MASK; 2548 } 2549 #define A3XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 2550 #define A3XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 2551 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val) 2552 { 2553 return ((val) << A3XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Y__MASK; 2554 } 2555 #define A3XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 2556 #define A3XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 2557 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val) 2558 { 2559 return ((val) << A3XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Z__MASK; 2560 } 2561 #define A3XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 2562 #define A3XX_TEX_CONST_0_SWIZ_W__SHIFT 13 2563 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val) 2564 { 2565 return ((val) << A3XX_TEX_CONST_0_SWIZ_W__SHIFT) & A3XX_TEX_CONST_0_SWIZ_W__MASK; 2566 } 2567 #define A3XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 2568 #define A3XX_TEX_CONST_0_MIPLVLS__SHIFT 16 2569 static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val) 2570 { 2571 return ((val) << A3XX_TEX_CONST_0_MIPLVLS__SHIFT) & A3XX_TEX_CONST_0_MIPLVLS__MASK; 2572 } 2573 #define A3XX_TEX_CONST_0_FMT__MASK 0x1fc00000 2574 #define A3XX_TEX_CONST_0_FMT__SHIFT 22 2575 static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val) 2576 { 2577 return ((val) << A3XX_TEX_CONST_0_FMT__SHIFT) & A3XX_TEX_CONST_0_FMT__MASK; 2578 } 2579 #define A3XX_TEX_CONST_0_NOCONVERT 0x20000000 2580 #define A3XX_TEX_CONST_0_TYPE__MASK 0xc0000000 2581 #define A3XX_TEX_CONST_0_TYPE__SHIFT 30 2582 static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val) 2583 { 2584 return ((val) << A3XX_TEX_CONST_0_TYPE__SHIFT) & A3XX_TEX_CONST_0_TYPE__MASK; 2585 } 2586 2587 #define REG_A3XX_TEX_CONST_1 0x00000001 2588 #define A3XX_TEX_CONST_1_HEIGHT__MASK 0x00003fff 2589 #define A3XX_TEX_CONST_1_HEIGHT__SHIFT 0 2590 static inline uint32_t A3XX_TEX_CONST_1_HEIGHT(uint32_t val) 2591 { 2592 return ((val) << A3XX_TEX_CONST_1_HEIGHT__SHIFT) & A3XX_TEX_CONST_1_HEIGHT__MASK; 2593 } 2594 #define A3XX_TEX_CONST_1_WIDTH__MASK 0x0fffc000 2595 #define A3XX_TEX_CONST_1_WIDTH__SHIFT 14 2596 static inline uint32_t A3XX_TEX_CONST_1_WIDTH(uint32_t val) 2597 { 2598 return ((val) << A3XX_TEX_CONST_1_WIDTH__SHIFT) & A3XX_TEX_CONST_1_WIDTH__MASK; 2599 } 2600 #define A3XX_TEX_CONST_1_FETCHSIZE__MASK 0xf0000000 2601 #define A3XX_TEX_CONST_1_FETCHSIZE__SHIFT 28 2602 static inline uint32_t A3XX_TEX_CONST_1_FETCHSIZE(enum a3xx_tex_fetchsize val) 2603 { 2604 return ((val) << A3XX_TEX_CONST_1_FETCHSIZE__SHIFT) & A3XX_TEX_CONST_1_FETCHSIZE__MASK; 2605 } 2606 2607 #define REG_A3XX_TEX_CONST_2 0x00000002 2608 #define A3XX_TEX_CONST_2_INDX__MASK 0x000000ff 2609 #define A3XX_TEX_CONST_2_INDX__SHIFT 0 2610 static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val) 2611 { 2612 return ((val) << A3XX_TEX_CONST_2_INDX__SHIFT) & A3XX_TEX_CONST_2_INDX__MASK; 2613 } 2614 #define A3XX_TEX_CONST_2_PITCH__MASK 0x3ffff000 2615 #define A3XX_TEX_CONST_2_PITCH__SHIFT 12 2616 static inline uint32_t A3XX_TEX_CONST_2_PITCH(uint32_t val) 2617 { 2618 return ((val) << A3XX_TEX_CONST_2_PITCH__SHIFT) & A3XX_TEX_CONST_2_PITCH__MASK; 2619 } 2620 #define A3XX_TEX_CONST_2_SWAP__MASK 0xc0000000 2621 #define A3XX_TEX_CONST_2_SWAP__SHIFT 30 2622 static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) 2623 { 2624 return ((val) << A3XX_TEX_CONST_2_SWAP__SHIFT) & A3XX_TEX_CONST_2_SWAP__MASK; 2625 } 2626 2627 #define REG_A3XX_TEX_CONST_3 0x00000003 2628 #define A3XX_TEX_CONST_3_LAYERSZ1__MASK 0x0000000f 2629 #define A3XX_TEX_CONST_3_LAYERSZ1__SHIFT 0 2630 static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val) 2631 { 2632 return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ1__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ1__MASK; 2633 } 2634 #define A3XX_TEX_CONST_3_DEPTH__MASK 0x0ffe0000 2635 #define A3XX_TEX_CONST_3_DEPTH__SHIFT 17 2636 static inline uint32_t A3XX_TEX_CONST_3_DEPTH(uint32_t val) 2637 { 2638 return ((val) << A3XX_TEX_CONST_3_DEPTH__SHIFT) & A3XX_TEX_CONST_3_DEPTH__MASK; 2639 } 2640 #define A3XX_TEX_CONST_3_LAYERSZ2__MASK 0xf0000000 2641 #define A3XX_TEX_CONST_3_LAYERSZ2__SHIFT 28 2642 static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ2(uint32_t val) 2643 { 2644 return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ2__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ2__MASK; 2645 } 2646 2647 2648 #endif /* A3XX_XML */ 2649