1 #ifndef A3XX_XML 2 #define A3XX_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) 13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55) 15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27) 16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55) 17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12) 18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) 19 20 Copyright (C) 2013-2015 by the following authors: 21 - Rob Clark <robdclark@gmail.com> (robclark) 22 23 Permission is hereby granted, free of charge, to any person obtaining 24 a copy of this software and associated documentation files (the 25 "Software"), to deal in the Software without restriction, including 26 without limitation the rights to use, copy, modify, merge, publish, 27 distribute, sublicense, and/or sell copies of the Software, and to 28 permit persons to whom the Software is furnished to do so, subject to 29 the following conditions: 30 31 The above copyright notice and this permission notice (including the 32 next paragraph) shall be included in all copies or substantial 33 portions of the Software. 34 35 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 37 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 38 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 39 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 40 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 41 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 42 */ 43 44 45 enum a3xx_tile_mode { 46 LINEAR = 0, 47 TILE_32X32 = 2, 48 }; 49 50 enum a3xx_state_block_id { 51 HLSQ_BLOCK_ID_TP_TEX = 2, 52 HLSQ_BLOCK_ID_TP_MIPMAP = 3, 53 HLSQ_BLOCK_ID_SP_VS = 4, 54 HLSQ_BLOCK_ID_SP_FS = 6, 55 }; 56 57 enum a3xx_cache_opcode { 58 INVALIDATE = 1, 59 }; 60 61 enum a3xx_vtx_fmt { 62 VFMT_32_FLOAT = 0, 63 VFMT_32_32_FLOAT = 1, 64 VFMT_32_32_32_FLOAT = 2, 65 VFMT_32_32_32_32_FLOAT = 3, 66 VFMT_16_FLOAT = 4, 67 VFMT_16_16_FLOAT = 5, 68 VFMT_16_16_16_FLOAT = 6, 69 VFMT_16_16_16_16_FLOAT = 7, 70 VFMT_32_FIXED = 8, 71 VFMT_32_32_FIXED = 9, 72 VFMT_32_32_32_FIXED = 10, 73 VFMT_32_32_32_32_FIXED = 11, 74 VFMT_16_SINT = 16, 75 VFMT_16_16_SINT = 17, 76 VFMT_16_16_16_SINT = 18, 77 VFMT_16_16_16_16_SINT = 19, 78 VFMT_16_UINT = 20, 79 VFMT_16_16_UINT = 21, 80 VFMT_16_16_16_UINT = 22, 81 VFMT_16_16_16_16_UINT = 23, 82 VFMT_16_SNORM = 24, 83 VFMT_16_16_SNORM = 25, 84 VFMT_16_16_16_SNORM = 26, 85 VFMT_16_16_16_16_SNORM = 27, 86 VFMT_16_UNORM = 28, 87 VFMT_16_16_UNORM = 29, 88 VFMT_16_16_16_UNORM = 30, 89 VFMT_16_16_16_16_UNORM = 31, 90 VFMT_32_UINT = 32, 91 VFMT_32_32_UINT = 33, 92 VFMT_32_32_32_UINT = 34, 93 VFMT_32_32_32_32_UINT = 35, 94 VFMT_32_SINT = 36, 95 VFMT_32_32_SINT = 37, 96 VFMT_32_32_32_SINT = 38, 97 VFMT_32_32_32_32_SINT = 39, 98 VFMT_8_UINT = 40, 99 VFMT_8_8_UINT = 41, 100 VFMT_8_8_8_UINT = 42, 101 VFMT_8_8_8_8_UINT = 43, 102 VFMT_8_UNORM = 44, 103 VFMT_8_8_UNORM = 45, 104 VFMT_8_8_8_UNORM = 46, 105 VFMT_8_8_8_8_UNORM = 47, 106 VFMT_8_SINT = 48, 107 VFMT_8_8_SINT = 49, 108 VFMT_8_8_8_SINT = 50, 109 VFMT_8_8_8_8_SINT = 51, 110 VFMT_8_SNORM = 52, 111 VFMT_8_8_SNORM = 53, 112 VFMT_8_8_8_SNORM = 54, 113 VFMT_8_8_8_8_SNORM = 55, 114 VFMT_10_10_10_2_UINT = 60, 115 VFMT_10_10_10_2_UNORM = 61, 116 VFMT_10_10_10_2_SINT = 62, 117 VFMT_10_10_10_2_SNORM = 63, 118 }; 119 120 enum a3xx_tex_fmt { 121 TFMT_5_6_5_UNORM = 4, 122 TFMT_5_5_5_1_UNORM = 5, 123 TFMT_4_4_4_4_UNORM = 7, 124 TFMT_Z16_UNORM = 9, 125 TFMT_X8Z24_UNORM = 10, 126 TFMT_Z32_FLOAT = 11, 127 TFMT_NV12_UV_TILED = 17, 128 TFMT_NV12_Y_TILED = 19, 129 TFMT_NV12_UV = 21, 130 TFMT_NV12_Y = 23, 131 TFMT_I420_Y = 24, 132 TFMT_I420_U = 26, 133 TFMT_I420_V = 27, 134 TFMT_ATC_RGB = 32, 135 TFMT_ATC_RGBA_EXPLICIT = 33, 136 TFMT_ETC1 = 34, 137 TFMT_ATC_RGBA_INTERPOLATED = 35, 138 TFMT_DXT1 = 36, 139 TFMT_DXT3 = 37, 140 TFMT_DXT5 = 38, 141 TFMT_10_10_10_2_UNORM = 41, 142 TFMT_9_9_9_E5_FLOAT = 42, 143 TFMT_11_11_10_FLOAT = 43, 144 TFMT_A8_UNORM = 44, 145 TFMT_L8_A8_UNORM = 47, 146 TFMT_8_UNORM = 48, 147 TFMT_8_8_UNORM = 49, 148 TFMT_8_8_8_UNORM = 50, 149 TFMT_8_8_8_8_UNORM = 51, 150 TFMT_8_SNORM = 52, 151 TFMT_8_8_SNORM = 53, 152 TFMT_8_8_8_SNORM = 54, 153 TFMT_8_8_8_8_SNORM = 55, 154 TFMT_8_UINT = 56, 155 TFMT_8_8_UINT = 57, 156 TFMT_8_8_8_UINT = 58, 157 TFMT_8_8_8_8_UINT = 59, 158 TFMT_8_SINT = 60, 159 TFMT_8_8_SINT = 61, 160 TFMT_8_8_8_SINT = 62, 161 TFMT_8_8_8_8_SINT = 63, 162 TFMT_16_FLOAT = 64, 163 TFMT_16_16_FLOAT = 65, 164 TFMT_16_16_16_16_FLOAT = 67, 165 TFMT_16_UINT = 68, 166 TFMT_16_16_UINT = 69, 167 TFMT_16_16_16_16_UINT = 71, 168 TFMT_16_SINT = 72, 169 TFMT_16_16_SINT = 73, 170 TFMT_16_16_16_16_SINT = 75, 171 TFMT_16_UNORM = 76, 172 TFMT_16_16_UNORM = 77, 173 TFMT_16_16_16_16_UNORM = 79, 174 TFMT_16_SNORM = 80, 175 TFMT_16_16_SNORM = 81, 176 TFMT_16_16_16_16_SNORM = 83, 177 TFMT_32_FLOAT = 84, 178 TFMT_32_32_FLOAT = 85, 179 TFMT_32_32_32_32_FLOAT = 87, 180 TFMT_32_UINT = 88, 181 TFMT_32_32_UINT = 89, 182 TFMT_32_32_32_32_UINT = 91, 183 TFMT_32_SINT = 92, 184 TFMT_32_32_SINT = 93, 185 TFMT_32_32_32_32_SINT = 95, 186 TFMT_ETC2_RG11_SNORM = 112, 187 TFMT_ETC2_RG11_UNORM = 113, 188 TFMT_ETC2_R11_SNORM = 114, 189 TFMT_ETC2_R11_UNORM = 115, 190 TFMT_ETC2_RGBA8 = 116, 191 TFMT_ETC2_RGB8A1 = 117, 192 TFMT_ETC2_RGB8 = 118, 193 }; 194 195 enum a3xx_tex_fetchsize { 196 TFETCH_DISABLE = 0, 197 TFETCH_1_BYTE = 1, 198 TFETCH_2_BYTE = 2, 199 TFETCH_4_BYTE = 3, 200 TFETCH_8_BYTE = 4, 201 TFETCH_16_BYTE = 5, 202 }; 203 204 enum a3xx_color_fmt { 205 RB_R5G6B5_UNORM = 0, 206 RB_R5G5B5A1_UNORM = 1, 207 RB_R4G4B4A4_UNORM = 3, 208 RB_R8G8B8_UNORM = 4, 209 RB_R8G8B8A8_UNORM = 8, 210 RB_R8G8B8A8_SNORM = 9, 211 RB_R8G8B8A8_UINT = 10, 212 RB_R8G8B8A8_SINT = 11, 213 RB_R8G8_UNORM = 12, 214 RB_R8G8_SNORM = 13, 215 RB_R8_UINT = 14, 216 RB_R8_SINT = 15, 217 RB_R10G10B10A2_UNORM = 16, 218 RB_A8_UNORM = 20, 219 RB_R8_UNORM = 21, 220 RB_R16_FLOAT = 24, 221 RB_R16G16_FLOAT = 25, 222 RB_R16G16B16A16_FLOAT = 27, 223 RB_R11G11B10_FLOAT = 28, 224 RB_R16_SNORM = 32, 225 RB_R16G16_SNORM = 33, 226 RB_R16G16B16A16_SNORM = 35, 227 RB_R16_UNORM = 36, 228 RB_R16G16_UNORM = 37, 229 RB_R16G16B16A16_UNORM = 39, 230 RB_R16_SINT = 40, 231 RB_R16G16_SINT = 41, 232 RB_R16G16B16A16_SINT = 43, 233 RB_R16_UINT = 44, 234 RB_R16G16_UINT = 45, 235 RB_R16G16B16A16_UINT = 47, 236 RB_R32_FLOAT = 48, 237 RB_R32G32_FLOAT = 49, 238 RB_R32G32B32A32_FLOAT = 51, 239 RB_R32_SINT = 52, 240 RB_R32G32_SINT = 53, 241 RB_R32G32B32A32_SINT = 55, 242 RB_R32_UINT = 56, 243 RB_R32G32_UINT = 57, 244 RB_R32G32B32A32_UINT = 59, 245 }; 246 247 enum a3xx_sp_perfcounter_select { 248 SP_FS_CFLOW_INSTRUCTIONS = 12, 249 SP_FS_FULL_ALU_INSTRUCTIONS = 14, 250 SP0_ICL1_MISSES = 26, 251 SP_ALU_ACTIVE_CYCLES = 29, 252 }; 253 254 enum a3xx_rop_code { 255 ROP_CLEAR = 0, 256 ROP_NOR = 1, 257 ROP_AND_INVERTED = 2, 258 ROP_COPY_INVERTED = 3, 259 ROP_AND_REVERSE = 4, 260 ROP_INVERT = 5, 261 ROP_XOR = 6, 262 ROP_NAND = 7, 263 ROP_AND = 8, 264 ROP_EQUIV = 9, 265 ROP_NOOP = 10, 266 ROP_OR_INVERTED = 11, 267 ROP_COPY = 12, 268 ROP_OR_REVERSE = 13, 269 ROP_OR = 14, 270 ROP_SET = 15, 271 }; 272 273 enum a3xx_rb_blend_opcode { 274 BLEND_DST_PLUS_SRC = 0, 275 BLEND_SRC_MINUS_DST = 1, 276 BLEND_DST_MINUS_SRC = 2, 277 BLEND_MIN_DST_SRC = 3, 278 BLEND_MAX_DST_SRC = 4, 279 }; 280 281 enum a3xx_intp_mode { 282 SMOOTH = 0, 283 FLAT = 1, 284 ZERO = 2, 285 ONE = 3, 286 }; 287 288 enum a3xx_repl_mode { 289 S = 1, 290 T = 2, 291 ONE_T = 3, 292 }; 293 294 enum a3xx_tex_filter { 295 A3XX_TEX_NEAREST = 0, 296 A3XX_TEX_LINEAR = 1, 297 A3XX_TEX_ANISO = 2, 298 }; 299 300 enum a3xx_tex_clamp { 301 A3XX_TEX_REPEAT = 0, 302 A3XX_TEX_CLAMP_TO_EDGE = 1, 303 A3XX_TEX_MIRROR_REPEAT = 2, 304 A3XX_TEX_CLAMP_TO_BORDER = 3, 305 A3XX_TEX_MIRROR_CLAMP = 4, 306 }; 307 308 enum a3xx_tex_aniso { 309 A3XX_TEX_ANISO_1 = 0, 310 A3XX_TEX_ANISO_2 = 1, 311 A3XX_TEX_ANISO_4 = 2, 312 A3XX_TEX_ANISO_8 = 3, 313 A3XX_TEX_ANISO_16 = 4, 314 }; 315 316 enum a3xx_tex_swiz { 317 A3XX_TEX_X = 0, 318 A3XX_TEX_Y = 1, 319 A3XX_TEX_Z = 2, 320 A3XX_TEX_W = 3, 321 A3XX_TEX_ZERO = 4, 322 A3XX_TEX_ONE = 5, 323 }; 324 325 enum a3xx_tex_type { 326 A3XX_TEX_1D = 0, 327 A3XX_TEX_2D = 1, 328 A3XX_TEX_CUBE = 2, 329 A3XX_TEX_3D = 3, 330 }; 331 332 enum a3xx_tex_msaa { 333 A3XX_TPL1_MSAA1X = 0, 334 A3XX_TPL1_MSAA2X = 1, 335 A3XX_TPL1_MSAA4X = 2, 336 A3XX_TPL1_MSAA8X = 3, 337 }; 338 339 #define A3XX_INT0_RBBM_GPU_IDLE 0x00000001 340 #define A3XX_INT0_RBBM_AHB_ERROR 0x00000002 341 #define A3XX_INT0_RBBM_REG_TIMEOUT 0x00000004 342 #define A3XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 343 #define A3XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 344 #define A3XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020 345 #define A3XX_INT0_VFD_ERROR 0x00000040 346 #define A3XX_INT0_CP_SW_INT 0x00000080 347 #define A3XX_INT0_CP_T0_PACKET_IN_IB 0x00000100 348 #define A3XX_INT0_CP_OPCODE_ERROR 0x00000200 349 #define A3XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400 350 #define A3XX_INT0_CP_HW_FAULT 0x00000800 351 #define A3XX_INT0_CP_DMA 0x00001000 352 #define A3XX_INT0_CP_IB2_INT 0x00002000 353 #define A3XX_INT0_CP_IB1_INT 0x00004000 354 #define A3XX_INT0_CP_RB_INT 0x00008000 355 #define A3XX_INT0_CP_REG_PROTECT_FAULT 0x00010000 356 #define A3XX_INT0_CP_RB_DONE_TS 0x00020000 357 #define A3XX_INT0_CP_VS_DONE_TS 0x00040000 358 #define A3XX_INT0_CP_PS_DONE_TS 0x00080000 359 #define A3XX_INT0_CACHE_FLUSH_TS 0x00100000 360 #define A3XX_INT0_CP_AHB_ERROR_HALT 0x00200000 361 #define A3XX_INT0_MISC_HANG_DETECT 0x01000000 362 #define A3XX_INT0_UCHE_OOB_ACCESS 0x02000000 363 #define REG_A3XX_RBBM_HW_VERSION 0x00000000 364 365 #define REG_A3XX_RBBM_HW_RELEASE 0x00000001 366 367 #define REG_A3XX_RBBM_HW_CONFIGURATION 0x00000002 368 369 #define REG_A3XX_RBBM_CLOCK_CTL 0x00000010 370 371 #define REG_A3XX_RBBM_SP_HYST_CNT 0x00000012 372 373 #define REG_A3XX_RBBM_SW_RESET_CMD 0x00000018 374 375 #define REG_A3XX_RBBM_AHB_CTL0 0x00000020 376 377 #define REG_A3XX_RBBM_AHB_CTL1 0x00000021 378 379 #define REG_A3XX_RBBM_AHB_CMD 0x00000022 380 381 #define REG_A3XX_RBBM_AHB_ERROR_STATUS 0x00000027 382 383 #define REG_A3XX_RBBM_GPR0_CTL 0x0000002e 384 385 #define REG_A3XX_RBBM_STATUS 0x00000030 386 #define A3XX_RBBM_STATUS_HI_BUSY 0x00000001 387 #define A3XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 388 #define A3XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 389 #define A3XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000 390 #define A3XX_RBBM_STATUS_VBIF_BUSY 0x00008000 391 #define A3XX_RBBM_STATUS_TSE_BUSY 0x00010000 392 #define A3XX_RBBM_STATUS_RAS_BUSY 0x00020000 393 #define A3XX_RBBM_STATUS_RB_BUSY 0x00040000 394 #define A3XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 395 #define A3XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 396 #define A3XX_RBBM_STATUS_VFD_BUSY 0x00200000 397 #define A3XX_RBBM_STATUS_VPC_BUSY 0x00400000 398 #define A3XX_RBBM_STATUS_UCHE_BUSY 0x00800000 399 #define A3XX_RBBM_STATUS_SP_BUSY 0x01000000 400 #define A3XX_RBBM_STATUS_TPL1_BUSY 0x02000000 401 #define A3XX_RBBM_STATUS_MARB_BUSY 0x04000000 402 #define A3XX_RBBM_STATUS_VSC_BUSY 0x08000000 403 #define A3XX_RBBM_STATUS_ARB_BUSY 0x10000000 404 #define A3XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 405 #define A3XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000 406 #define A3XX_RBBM_STATUS_GPU_BUSY 0x80000000 407 408 #define REG_A3XX_RBBM_NQWAIT_UNTIL 0x00000040 409 410 #define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x00000033 411 412 #define REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL 0x00000050 413 414 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL0 0x00000051 415 416 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL1 0x00000054 417 418 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL2 0x00000057 419 420 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3 0x0000005a 421 422 #define REG_A3XX_RBBM_INT_SET_CMD 0x00000060 423 424 #define REG_A3XX_RBBM_INT_CLEAR_CMD 0x00000061 425 426 #define REG_A3XX_RBBM_INT_0_MASK 0x00000063 427 428 #define REG_A3XX_RBBM_INT_0_STATUS 0x00000064 429 430 #define REG_A3XX_RBBM_PERFCTR_CTL 0x00000080 431 #define A3XX_RBBM_PERFCTR_CTL_ENABLE 0x00000001 432 433 #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0 0x00000081 434 435 #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD1 0x00000082 436 437 #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000084 438 439 #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000085 440 441 #define REG_A3XX_RBBM_PERFCOUNTER0_SELECT 0x00000086 442 443 #define REG_A3XX_RBBM_PERFCOUNTER1_SELECT 0x00000087 444 445 #define REG_A3XX_RBBM_GPU_BUSY_MASKED 0x00000088 446 447 #define REG_A3XX_RBBM_PERFCTR_CP_0_LO 0x00000090 448 449 #define REG_A3XX_RBBM_PERFCTR_CP_0_HI 0x00000091 450 451 #define REG_A3XX_RBBM_PERFCTR_RBBM_0_LO 0x00000092 452 453 #define REG_A3XX_RBBM_PERFCTR_RBBM_0_HI 0x00000093 454 455 #define REG_A3XX_RBBM_PERFCTR_RBBM_1_LO 0x00000094 456 457 #define REG_A3XX_RBBM_PERFCTR_RBBM_1_HI 0x00000095 458 459 #define REG_A3XX_RBBM_PERFCTR_PC_0_LO 0x00000096 460 461 #define REG_A3XX_RBBM_PERFCTR_PC_0_HI 0x00000097 462 463 #define REG_A3XX_RBBM_PERFCTR_PC_1_LO 0x00000098 464 465 #define REG_A3XX_RBBM_PERFCTR_PC_1_HI 0x00000099 466 467 #define REG_A3XX_RBBM_PERFCTR_PC_2_LO 0x0000009a 468 469 #define REG_A3XX_RBBM_PERFCTR_PC_2_HI 0x0000009b 470 471 #define REG_A3XX_RBBM_PERFCTR_PC_3_LO 0x0000009c 472 473 #define REG_A3XX_RBBM_PERFCTR_PC_3_HI 0x0000009d 474 475 #define REG_A3XX_RBBM_PERFCTR_VFD_0_LO 0x0000009e 476 477 #define REG_A3XX_RBBM_PERFCTR_VFD_0_HI 0x0000009f 478 479 #define REG_A3XX_RBBM_PERFCTR_VFD_1_LO 0x000000a0 480 481 #define REG_A3XX_RBBM_PERFCTR_VFD_1_HI 0x000000a1 482 483 #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000a2 484 485 #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000a3 486 487 #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000a4 488 489 #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000a5 490 491 #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000a6 492 493 #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000a7 494 495 #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000a8 496 497 #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000a9 498 499 #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000aa 500 501 #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000ab 502 503 #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000ac 504 505 #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000ad 506 507 #define REG_A3XX_RBBM_PERFCTR_VPC_0_LO 0x000000ae 508 509 #define REG_A3XX_RBBM_PERFCTR_VPC_0_HI 0x000000af 510 511 #define REG_A3XX_RBBM_PERFCTR_VPC_1_LO 0x000000b0 512 513 #define REG_A3XX_RBBM_PERFCTR_VPC_1_HI 0x000000b1 514 515 #define REG_A3XX_RBBM_PERFCTR_TSE_0_LO 0x000000b2 516 517 #define REG_A3XX_RBBM_PERFCTR_TSE_0_HI 0x000000b3 518 519 #define REG_A3XX_RBBM_PERFCTR_TSE_1_LO 0x000000b4 520 521 #define REG_A3XX_RBBM_PERFCTR_TSE_1_HI 0x000000b5 522 523 #define REG_A3XX_RBBM_PERFCTR_RAS_0_LO 0x000000b6 524 525 #define REG_A3XX_RBBM_PERFCTR_RAS_0_HI 0x000000b7 526 527 #define REG_A3XX_RBBM_PERFCTR_RAS_1_LO 0x000000b8 528 529 #define REG_A3XX_RBBM_PERFCTR_RAS_1_HI 0x000000b9 530 531 #define REG_A3XX_RBBM_PERFCTR_UCHE_0_LO 0x000000ba 532 533 #define REG_A3XX_RBBM_PERFCTR_UCHE_0_HI 0x000000bb 534 535 #define REG_A3XX_RBBM_PERFCTR_UCHE_1_LO 0x000000bc 536 537 #define REG_A3XX_RBBM_PERFCTR_UCHE_1_HI 0x000000bd 538 539 #define REG_A3XX_RBBM_PERFCTR_UCHE_2_LO 0x000000be 540 541 #define REG_A3XX_RBBM_PERFCTR_UCHE_2_HI 0x000000bf 542 543 #define REG_A3XX_RBBM_PERFCTR_UCHE_3_LO 0x000000c0 544 545 #define REG_A3XX_RBBM_PERFCTR_UCHE_3_HI 0x000000c1 546 547 #define REG_A3XX_RBBM_PERFCTR_UCHE_4_LO 0x000000c2 548 549 #define REG_A3XX_RBBM_PERFCTR_UCHE_4_HI 0x000000c3 550 551 #define REG_A3XX_RBBM_PERFCTR_UCHE_5_LO 0x000000c4 552 553 #define REG_A3XX_RBBM_PERFCTR_UCHE_5_HI 0x000000c5 554 555 #define REG_A3XX_RBBM_PERFCTR_TP_0_LO 0x000000c6 556 557 #define REG_A3XX_RBBM_PERFCTR_TP_0_HI 0x000000c7 558 559 #define REG_A3XX_RBBM_PERFCTR_TP_1_LO 0x000000c8 560 561 #define REG_A3XX_RBBM_PERFCTR_TP_1_HI 0x000000c9 562 563 #define REG_A3XX_RBBM_PERFCTR_TP_2_LO 0x000000ca 564 565 #define REG_A3XX_RBBM_PERFCTR_TP_2_HI 0x000000cb 566 567 #define REG_A3XX_RBBM_PERFCTR_TP_3_LO 0x000000cc 568 569 #define REG_A3XX_RBBM_PERFCTR_TP_3_HI 0x000000cd 570 571 #define REG_A3XX_RBBM_PERFCTR_TP_4_LO 0x000000ce 572 573 #define REG_A3XX_RBBM_PERFCTR_TP_4_HI 0x000000cf 574 575 #define REG_A3XX_RBBM_PERFCTR_TP_5_LO 0x000000d0 576 577 #define REG_A3XX_RBBM_PERFCTR_TP_5_HI 0x000000d1 578 579 #define REG_A3XX_RBBM_PERFCTR_SP_0_LO 0x000000d2 580 581 #define REG_A3XX_RBBM_PERFCTR_SP_0_HI 0x000000d3 582 583 #define REG_A3XX_RBBM_PERFCTR_SP_1_LO 0x000000d4 584 585 #define REG_A3XX_RBBM_PERFCTR_SP_1_HI 0x000000d5 586 587 #define REG_A3XX_RBBM_PERFCTR_SP_2_LO 0x000000d6 588 589 #define REG_A3XX_RBBM_PERFCTR_SP_2_HI 0x000000d7 590 591 #define REG_A3XX_RBBM_PERFCTR_SP_3_LO 0x000000d8 592 593 #define REG_A3XX_RBBM_PERFCTR_SP_3_HI 0x000000d9 594 595 #define REG_A3XX_RBBM_PERFCTR_SP_4_LO 0x000000da 596 597 #define REG_A3XX_RBBM_PERFCTR_SP_4_HI 0x000000db 598 599 #define REG_A3XX_RBBM_PERFCTR_SP_5_LO 0x000000dc 600 601 #define REG_A3XX_RBBM_PERFCTR_SP_5_HI 0x000000dd 602 603 #define REG_A3XX_RBBM_PERFCTR_SP_6_LO 0x000000de 604 605 #define REG_A3XX_RBBM_PERFCTR_SP_6_HI 0x000000df 606 607 #define REG_A3XX_RBBM_PERFCTR_SP_7_LO 0x000000e0 608 609 #define REG_A3XX_RBBM_PERFCTR_SP_7_HI 0x000000e1 610 611 #define REG_A3XX_RBBM_PERFCTR_RB_0_LO 0x000000e2 612 613 #define REG_A3XX_RBBM_PERFCTR_RB_0_HI 0x000000e3 614 615 #define REG_A3XX_RBBM_PERFCTR_RB_1_LO 0x000000e4 616 617 #define REG_A3XX_RBBM_PERFCTR_RB_1_HI 0x000000e5 618 619 #define REG_A3XX_RBBM_PERFCTR_PWR_0_LO 0x000000ea 620 621 #define REG_A3XX_RBBM_PERFCTR_PWR_0_HI 0x000000eb 622 623 #define REG_A3XX_RBBM_PERFCTR_PWR_1_LO 0x000000ec 624 625 #define REG_A3XX_RBBM_PERFCTR_PWR_1_HI 0x000000ed 626 627 #define REG_A3XX_RBBM_RBBM_CTL 0x00000100 628 629 #define REG_A3XX_RBBM_DEBUG_BUS_CTL 0x00000111 630 631 #define REG_A3XX_RBBM_DEBUG_BUS_DATA_STATUS 0x00000112 632 633 #define REG_A3XX_CP_PFP_UCODE_ADDR 0x000001c9 634 635 #define REG_A3XX_CP_PFP_UCODE_DATA 0x000001ca 636 637 #define REG_A3XX_CP_ROQ_ADDR 0x000001cc 638 639 #define REG_A3XX_CP_ROQ_DATA 0x000001cd 640 641 #define REG_A3XX_CP_MERCIU_ADDR 0x000001d1 642 643 #define REG_A3XX_CP_MERCIU_DATA 0x000001d2 644 645 #define REG_A3XX_CP_MERCIU_DATA2 0x000001d3 646 647 #define REG_A3XX_CP_MEQ_ADDR 0x000001da 648 649 #define REG_A3XX_CP_MEQ_DATA 0x000001db 650 651 #define REG_A3XX_CP_WFI_PEND_CTR 0x000001f5 652 653 #define REG_A3XX_RBBM_PM_OVERRIDE2 0x0000039d 654 655 #define REG_A3XX_CP_PERFCOUNTER_SELECT 0x00000445 656 657 #define REG_A3XX_CP_HW_FAULT 0x0000045c 658 659 #define REG_A3XX_CP_PROTECT_CTRL 0x0000045e 660 661 #define REG_A3XX_CP_PROTECT_STATUS 0x0000045f 662 663 static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; } 664 665 static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; } 666 667 #define REG_A3XX_CP_AHB_FAULT 0x0000054d 668 669 #define REG_A3XX_SQ_GPR_MANAGEMENT 0x00000d00 670 671 #define REG_A3XX_SQ_INST_STORE_MANAGMENT 0x00000d02 672 673 #define REG_A3XX_TP0_CHICKEN 0x00000e1e 674 675 #define REG_A3XX_SP_GLOBAL_MEM_SIZE 0x00000e22 676 677 #define REG_A3XX_SP_GLOBAL_MEM_ADDR 0x00000e23 678 679 #define REG_A3XX_GRAS_CL_CLIP_CNTL 0x00002040 680 #define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER 0x00001000 681 #define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 682 #define A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000 683 #define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE 0x00080000 684 #define A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE 0x00100000 685 #define A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE 0x00200000 686 #define A3XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000 687 #define A3XX_GRAS_CL_CLIP_CNTL_ZCOORD 0x00800000 688 #define A3XX_GRAS_CL_CLIP_CNTL_WCOORD 0x01000000 689 #define A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE 0x02000000 690 #define A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK 0x1c000000 691 #define A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT 26 692 static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val) 693 { 694 return ((val) << A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT) & A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK; 695 } 696 697 #define REG_A3XX_GRAS_CL_GB_CLIP_ADJ 0x00002044 698 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff 699 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0 700 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) 701 { 702 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; 703 } 704 #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00 705 #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10 706 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) 707 { 708 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; 709 } 710 711 #define REG_A3XX_GRAS_CL_VPORT_XOFFSET 0x00002048 712 #define A3XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff 713 #define A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0 714 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) 715 { 716 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK; 717 } 718 719 #define REG_A3XX_GRAS_CL_VPORT_XSCALE 0x00002049 720 #define A3XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff 721 #define A3XX_GRAS_CL_VPORT_XSCALE__SHIFT 0 722 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) 723 { 724 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK; 725 } 726 727 #define REG_A3XX_GRAS_CL_VPORT_YOFFSET 0x0000204a 728 #define A3XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff 729 #define A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0 730 static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val) 731 { 732 return ((fui(val)) << A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_YOFFSET__MASK; 733 } 734 735 #define REG_A3XX_GRAS_CL_VPORT_YSCALE 0x0000204b 736 #define A3XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff 737 #define A3XX_GRAS_CL_VPORT_YSCALE__SHIFT 0 738 static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val) 739 { 740 return ((fui(val)) << A3XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_YSCALE__MASK; 741 } 742 743 #define REG_A3XX_GRAS_CL_VPORT_ZOFFSET 0x0000204c 744 #define A3XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff 745 #define A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0 746 static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val) 747 { 748 return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_ZOFFSET__MASK; 749 } 750 751 #define REG_A3XX_GRAS_CL_VPORT_ZSCALE 0x0000204d 752 #define A3XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff 753 #define A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0 754 static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val) 755 { 756 return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_ZSCALE__MASK; 757 } 758 759 #define REG_A3XX_GRAS_SU_POINT_MINMAX 0x00002068 760 #define A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 761 #define A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 762 static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MIN(float val) 763 { 764 return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 765 } 766 #define A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 767 #define A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 768 static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MAX(float val) 769 { 770 return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 771 } 772 773 #define REG_A3XX_GRAS_SU_POINT_SIZE 0x00002069 774 #define A3XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff 775 #define A3XX_GRAS_SU_POINT_SIZE__SHIFT 0 776 static inline uint32_t A3XX_GRAS_SU_POINT_SIZE(float val) 777 { 778 return ((((int32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_SIZE__SHIFT) & A3XX_GRAS_SU_POINT_SIZE__MASK; 779 } 780 781 #define REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000206c 782 #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK 0x00ffffff 783 #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT 0 784 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val) 785 { 786 return ((((int32_t)(val * 1048576.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK; 787 } 788 789 #define REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000206d 790 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 791 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 792 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 793 { 794 return ((((int32_t)(val * 64.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 795 } 796 797 #define REG_A3XX_GRAS_SU_MODE_CONTROL 0x00002070 798 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001 799 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002 800 #define A3XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004 801 #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8 802 #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3 803 static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) 804 { 805 return ((((int32_t)(val * 4.0))) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; 806 } 807 #define A3XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800 808 809 #define REG_A3XX_GRAS_SC_CONTROL 0x00002072 810 #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x000000f0 811 #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 4 812 static inline uint32_t A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) 813 { 814 return ((val) << A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK; 815 } 816 #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000f00 817 #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 8 818 static inline uint32_t A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val) 819 { 820 return ((val) << A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK; 821 } 822 #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000 823 #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12 824 static inline uint32_t A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) 825 { 826 return ((val) << A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK; 827 } 828 829 #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL 0x00002074 830 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 831 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 832 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 833 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 834 { 835 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; 836 } 837 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 838 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 839 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 840 { 841 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; 842 } 843 844 #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_BR 0x00002075 845 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 846 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 847 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 848 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 849 { 850 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; 851 } 852 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 853 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 854 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 855 { 856 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; 857 } 858 859 #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL 0x00002079 860 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 861 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 862 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 863 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 864 { 865 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 866 } 867 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 868 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 869 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 870 { 871 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 872 } 873 874 #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000207a 875 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 876 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 877 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 878 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 879 { 880 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 881 } 882 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 883 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 884 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 885 { 886 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 887 } 888 889 #define REG_A3XX_RB_MODE_CONTROL 0x000020c0 890 #define A3XX_RB_MODE_CONTROL_GMEM_BYPASS 0x00000080 891 #define A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK 0x00000700 892 #define A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT 8 893 static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val) 894 { 895 return ((val) << A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT) & A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK; 896 } 897 #define A3XX_RB_MODE_CONTROL_MRT__MASK 0x00003000 898 #define A3XX_RB_MODE_CONTROL_MRT__SHIFT 12 899 static inline uint32_t A3XX_RB_MODE_CONTROL_MRT(uint32_t val) 900 { 901 return ((val) << A3XX_RB_MODE_CONTROL_MRT__SHIFT) & A3XX_RB_MODE_CONTROL_MRT__MASK; 902 } 903 #define A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE 0x00008000 904 #define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE 0x00010000 905 906 #define REG_A3XX_RB_RENDER_CONTROL 0x000020c1 907 #define A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE 0x00000001 908 #define A3XX_RB_RENDER_CONTROL_YUV_IN_ENABLE 0x00000002 909 #define A3XX_RB_RENDER_CONTROL_COV_VALUE_INPUT_ENABLE 0x00000004 910 #define A3XX_RB_RENDER_CONTROL_FACENESS 0x00000008 911 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK 0x00000ff0 912 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT 4 913 static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val) 914 { 915 return ((val >> 5) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK; 916 } 917 #define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00001000 918 #define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM 0x00002000 919 #define A3XX_RB_RENDER_CONTROL_XCOORD 0x00004000 920 #define A3XX_RB_RENDER_CONTROL_YCOORD 0x00008000 921 #define A3XX_RB_RENDER_CONTROL_ZCOORD 0x00010000 922 #define A3XX_RB_RENDER_CONTROL_WCOORD 0x00020000 923 #define A3XX_RB_RENDER_CONTROL_I_CLAMP_ENABLE 0x00080000 924 #define A3XX_RB_RENDER_CONTROL_COV_VALUE_OUTPUT_ENABLE 0x00100000 925 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST 0x00400000 926 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK 0x07000000 927 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT 24 928 static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 929 { 930 return ((val) << A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK; 931 } 932 #define A3XX_RB_RENDER_CONTROL_ALPHA_TO_COVERAGE 0x40000000 933 #define A3XX_RB_RENDER_CONTROL_ALPHA_TO_ONE 0x80000000 934 935 #define REG_A3XX_RB_MSAA_CONTROL 0x000020c2 936 #define A3XX_RB_MSAA_CONTROL_DISABLE 0x00000400 937 #define A3XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000f000 938 #define A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 12 939 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val) 940 { 941 return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLES__MASK; 942 } 943 #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK 0xffff0000 944 #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT 16 945 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val) 946 { 947 return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK; 948 } 949 950 #define REG_A3XX_RB_ALPHA_REF 0x000020c3 951 #define A3XX_RB_ALPHA_REF_UINT__MASK 0x0000ff00 952 #define A3XX_RB_ALPHA_REF_UINT__SHIFT 8 953 static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val) 954 { 955 return ((val) << A3XX_RB_ALPHA_REF_UINT__SHIFT) & A3XX_RB_ALPHA_REF_UINT__MASK; 956 } 957 #define A3XX_RB_ALPHA_REF_FLOAT__MASK 0xffff0000 958 #define A3XX_RB_ALPHA_REF_FLOAT__SHIFT 16 959 static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val) 960 { 961 return ((util_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK; 962 } 963 964 static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; } 965 966 static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; } 967 #define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008 968 #define A3XX_RB_MRT_CONTROL_BLEND 0x00000010 969 #define A3XX_RB_MRT_CONTROL_BLEND2 0x00000020 970 #define A3XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00 971 #define A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8 972 static inline uint32_t A3XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) 973 { 974 return ((val) << A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A3XX_RB_MRT_CONTROL_ROP_CODE__MASK; 975 } 976 #define A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK 0x00003000 977 #define A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT 12 978 static inline uint32_t A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) 979 { 980 return ((val) << A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT) & A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK; 981 } 982 #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000 983 #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24 984 static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 985 { 986 return ((val) << A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 987 } 988 989 static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; } 990 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f 991 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 992 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val) 993 { 994 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 995 } 996 #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0 997 #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6 998 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val) 999 { 1000 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 1001 } 1002 #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00000c00 1003 #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 10 1004 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 1005 { 1006 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 1007 } 1008 #define A3XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00004000 1009 #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xfffe0000 1010 #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 17 1011 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) 1012 { 1013 return ((val >> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; 1014 } 1015 1016 static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; } 1017 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK 0xfffffff0 1018 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT 4 1019 static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val) 1020 { 1021 return ((val >> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK; 1022 } 1023 1024 static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; } 1025 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 1026 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 1027 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 1028 { 1029 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 1030 } 1031 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 1032 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 1033 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 1034 { 1035 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 1036 } 1037 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 1038 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 1039 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 1040 { 1041 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 1042 } 1043 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 1044 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 1045 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 1046 { 1047 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 1048 } 1049 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 1050 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 1051 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 1052 { 1053 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 1054 } 1055 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 1056 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 1057 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 1058 { 1059 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 1060 } 1061 #define A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE 0x20000000 1062 1063 #define REG_A3XX_RB_BLEND_RED 0x000020e4 1064 #define A3XX_RB_BLEND_RED_UINT__MASK 0x000000ff 1065 #define A3XX_RB_BLEND_RED_UINT__SHIFT 0 1066 static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val) 1067 { 1068 return ((val) << A3XX_RB_BLEND_RED_UINT__SHIFT) & A3XX_RB_BLEND_RED_UINT__MASK; 1069 } 1070 #define A3XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 1071 #define A3XX_RB_BLEND_RED_FLOAT__SHIFT 16 1072 static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val) 1073 { 1074 return ((util_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK; 1075 } 1076 1077 #define REG_A3XX_RB_BLEND_GREEN 0x000020e5 1078 #define A3XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff 1079 #define A3XX_RB_BLEND_GREEN_UINT__SHIFT 0 1080 static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val) 1081 { 1082 return ((val) << A3XX_RB_BLEND_GREEN_UINT__SHIFT) & A3XX_RB_BLEND_GREEN_UINT__MASK; 1083 } 1084 #define A3XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 1085 #define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 1086 static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val) 1087 { 1088 return ((util_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK; 1089 } 1090 1091 #define REG_A3XX_RB_BLEND_BLUE 0x000020e6 1092 #define A3XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff 1093 #define A3XX_RB_BLEND_BLUE_UINT__SHIFT 0 1094 static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val) 1095 { 1096 return ((val) << A3XX_RB_BLEND_BLUE_UINT__SHIFT) & A3XX_RB_BLEND_BLUE_UINT__MASK; 1097 } 1098 #define A3XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 1099 #define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 1100 static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val) 1101 { 1102 return ((util_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK; 1103 } 1104 1105 #define REG_A3XX_RB_BLEND_ALPHA 0x000020e7 1106 #define A3XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff 1107 #define A3XX_RB_BLEND_ALPHA_UINT__SHIFT 0 1108 static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val) 1109 { 1110 return ((val) << A3XX_RB_BLEND_ALPHA_UINT__SHIFT) & A3XX_RB_BLEND_ALPHA_UINT__MASK; 1111 } 1112 #define A3XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 1113 #define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 1114 static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val) 1115 { 1116 return ((util_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK; 1117 } 1118 1119 #define REG_A3XX_RB_CLEAR_COLOR_DW0 0x000020e8 1120 1121 #define REG_A3XX_RB_CLEAR_COLOR_DW1 0x000020e9 1122 1123 #define REG_A3XX_RB_CLEAR_COLOR_DW2 0x000020ea 1124 1125 #define REG_A3XX_RB_CLEAR_COLOR_DW3 0x000020eb 1126 1127 #define REG_A3XX_RB_COPY_CONTROL 0x000020ec 1128 #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003 1129 #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0 1130 static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) 1131 { 1132 return ((val) << A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK; 1133 } 1134 #define A3XX_RB_COPY_CONTROL_DEPTHCLEAR 0x00000008 1135 #define A3XX_RB_COPY_CONTROL_MODE__MASK 0x00000070 1136 #define A3XX_RB_COPY_CONTROL_MODE__SHIFT 4 1137 static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) 1138 { 1139 return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK; 1140 } 1141 #define A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00 1142 #define A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8 1143 static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) 1144 { 1145 return ((val) << A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK; 1146 } 1147 #define A3XX_RB_COPY_CONTROL_UNK12 0x00001000 1148 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000 1149 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14 1150 static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) 1151 { 1152 return ((val >> 14) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK; 1153 } 1154 1155 #define REG_A3XX_RB_COPY_DEST_BASE 0x000020ed 1156 #define A3XX_RB_COPY_DEST_BASE_BASE__MASK 0xfffffff0 1157 #define A3XX_RB_COPY_DEST_BASE_BASE__SHIFT 4 1158 static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val) 1159 { 1160 return ((val >> 5) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A3XX_RB_COPY_DEST_BASE_BASE__MASK; 1161 } 1162 1163 #define REG_A3XX_RB_COPY_DEST_PITCH 0x000020ee 1164 #define A3XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff 1165 #define A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0 1166 static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) 1167 { 1168 return ((val >> 5) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK; 1169 } 1170 1171 #define REG_A3XX_RB_COPY_DEST_INFO 0x000020ef 1172 #define A3XX_RB_COPY_DEST_INFO_TILE__MASK 0x00000003 1173 #define A3XX_RB_COPY_DEST_INFO_TILE__SHIFT 0 1174 static inline uint32_t A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val) 1175 { 1176 return ((val) << A3XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A3XX_RB_COPY_DEST_INFO_TILE__MASK; 1177 } 1178 #define A3XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc 1179 #define A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2 1180 static inline uint32_t A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val) 1181 { 1182 return ((val) << A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A3XX_RB_COPY_DEST_INFO_FORMAT__MASK; 1183 } 1184 #define A3XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 1185 #define A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 1186 static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) 1187 { 1188 return ((val) << A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A3XX_RB_COPY_DEST_INFO_SWAP__MASK; 1189 } 1190 #define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 1191 #define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 1192 static inline uint32_t A3XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 1193 { 1194 return ((val) << A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 1195 } 1196 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000 1197 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14 1198 static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) 1199 { 1200 return ((val) << A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK; 1201 } 1202 #define A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000 1203 #define A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18 1204 static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) 1205 { 1206 return ((val) << A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK; 1207 } 1208 1209 #define REG_A3XX_RB_DEPTH_CONTROL 0x00002100 1210 #define A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001 1211 #define A3XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002 1212 #define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004 1213 #define A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00000008 1214 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070 1215 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4 1216 static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) 1217 { 1218 return ((val) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK; 1219 } 1220 #define A3XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080 1221 #define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000 1222 1223 #define REG_A3XX_RB_DEPTH_CLEAR 0x00002101 1224 1225 #define REG_A3XX_RB_DEPTH_INFO 0x00002102 1226 #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003 1227 #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 1228 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) 1229 { 1230 return ((val) << A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 1231 } 1232 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff800 1233 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 11 1234 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 1235 { 1236 return ((val >> 12) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 1237 } 1238 1239 #define REG_A3XX_RB_DEPTH_PITCH 0x00002103 1240 #define A3XX_RB_DEPTH_PITCH__MASK 0xffffffff 1241 #define A3XX_RB_DEPTH_PITCH__SHIFT 0 1242 static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val) 1243 { 1244 return ((val >> 3) << A3XX_RB_DEPTH_PITCH__SHIFT) & A3XX_RB_DEPTH_PITCH__MASK; 1245 } 1246 1247 #define REG_A3XX_RB_STENCIL_CONTROL 0x00002104 1248 #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 1249 #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 1250 #define A3XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 1251 #define A3XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 1252 #define A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 1253 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 1254 { 1255 return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC__MASK; 1256 } 1257 #define A3XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 1258 #define A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 1259 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 1260 { 1261 return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL__MASK; 1262 } 1263 #define A3XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 1264 #define A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 1265 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 1266 { 1267 return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS__MASK; 1268 } 1269 #define A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 1270 #define A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 1271 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 1272 { 1273 return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 1274 } 1275 #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 1276 #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 1277 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 1278 { 1279 return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 1280 } 1281 #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 1282 #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 1283 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 1284 { 1285 return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 1286 } 1287 #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 1288 #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 1289 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 1290 { 1291 return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 1292 } 1293 #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 1294 #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 1295 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 1296 { 1297 return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 1298 } 1299 1300 #define REG_A3XX_RB_STENCIL_CLEAR 0x00002105 1301 1302 #define REG_A3XX_RB_STENCIL_INFO 0x00002106 1303 #define A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff800 1304 #define A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 11 1305 static inline uint32_t A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) 1306 { 1307 return ((val >> 12) << A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK; 1308 } 1309 1310 #define REG_A3XX_RB_STENCIL_PITCH 0x00002107 1311 #define A3XX_RB_STENCIL_PITCH__MASK 0xffffffff 1312 #define A3XX_RB_STENCIL_PITCH__SHIFT 0 1313 static inline uint32_t A3XX_RB_STENCIL_PITCH(uint32_t val) 1314 { 1315 return ((val >> 3) << A3XX_RB_STENCIL_PITCH__SHIFT) & A3XX_RB_STENCIL_PITCH__MASK; 1316 } 1317 1318 #define REG_A3XX_RB_STENCILREFMASK 0x00002108 1319 #define A3XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 1320 #define A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 1321 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 1322 { 1323 return ((val) << A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILREF__MASK; 1324 } 1325 #define A3XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 1326 #define A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 1327 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 1328 { 1329 return ((val) << A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILMASK__MASK; 1330 } 1331 #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 1332 #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 1333 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 1334 { 1335 return ((val) << A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 1336 } 1337 1338 #define REG_A3XX_RB_STENCILREFMASK_BF 0x00002109 1339 #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 1340 #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 1341 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 1342 { 1343 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 1344 } 1345 #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 1346 #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 1347 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 1348 { 1349 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 1350 } 1351 #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 1352 #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 1353 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 1354 { 1355 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 1356 } 1357 1358 #define REG_A3XX_RB_LRZ_VSC_CONTROL 0x0000210c 1359 #define A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE 0x00000002 1360 1361 #define REG_A3XX_RB_WINDOW_OFFSET 0x0000210e 1362 #define A3XX_RB_WINDOW_OFFSET_X__MASK 0x0000ffff 1363 #define A3XX_RB_WINDOW_OFFSET_X__SHIFT 0 1364 static inline uint32_t A3XX_RB_WINDOW_OFFSET_X(uint32_t val) 1365 { 1366 return ((val) << A3XX_RB_WINDOW_OFFSET_X__SHIFT) & A3XX_RB_WINDOW_OFFSET_X__MASK; 1367 } 1368 #define A3XX_RB_WINDOW_OFFSET_Y__MASK 0xffff0000 1369 #define A3XX_RB_WINDOW_OFFSET_Y__SHIFT 16 1370 static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val) 1371 { 1372 return ((val) << A3XX_RB_WINDOW_OFFSET_Y__SHIFT) & A3XX_RB_WINDOW_OFFSET_Y__MASK; 1373 } 1374 1375 #define REG_A3XX_RB_SAMPLE_COUNT_CONTROL 0x00002110 1376 #define A3XX_RB_SAMPLE_COUNT_CONTROL_RESET 0x00000001 1377 #define A3XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 1378 1379 #define REG_A3XX_RB_SAMPLE_COUNT_ADDR 0x00002111 1380 1381 #define REG_A3XX_RB_Z_CLAMP_MIN 0x00002114 1382 1383 #define REG_A3XX_RB_Z_CLAMP_MAX 0x00002115 1384 1385 #define REG_A3XX_VGT_BIN_BASE 0x000021e1 1386 1387 #define REG_A3XX_VGT_BIN_SIZE 0x000021e2 1388 1389 #define REG_A3XX_PC_VSTREAM_CONTROL 0x000021e4 1390 #define A3XX_PC_VSTREAM_CONTROL_SIZE__MASK 0x003f0000 1391 #define A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT 16 1392 static inline uint32_t A3XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val) 1393 { 1394 return ((val) << A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A3XX_PC_VSTREAM_CONTROL_SIZE__MASK; 1395 } 1396 #define A3XX_PC_VSTREAM_CONTROL_N__MASK 0x07c00000 1397 #define A3XX_PC_VSTREAM_CONTROL_N__SHIFT 22 1398 static inline uint32_t A3XX_PC_VSTREAM_CONTROL_N(uint32_t val) 1399 { 1400 return ((val) << A3XX_PC_VSTREAM_CONTROL_N__SHIFT) & A3XX_PC_VSTREAM_CONTROL_N__MASK; 1401 } 1402 1403 #define REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL 0x000021ea 1404 1405 #define REG_A3XX_PC_PRIM_VTX_CNTL 0x000021ec 1406 #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK 0x0000001f 1407 #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT 0 1408 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val) 1409 { 1410 return ((val) << A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK; 1411 } 1412 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK 0x000000e0 1413 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT 5 1414 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 1415 { 1416 return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK; 1417 } 1418 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK 0x00000700 1419 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT 8 1420 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 1421 { 1422 return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK; 1423 } 1424 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_ENABLE 0x00001000 1425 #define A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000 1426 #define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000 1427 #define A3XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000 1428 1429 #define REG_A3XX_PC_RESTART_INDEX 0x000021ed 1430 1431 #define REG_A3XX_HLSQ_CONTROL_0_REG 0x00002200 1432 #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010 1433 #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4 1434 static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) 1435 { 1436 return ((val) << A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; 1437 } 1438 #define A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040 1439 #define A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200 1440 #define A3XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400 1441 #define A3XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000 1442 #define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000 1443 #define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27 1444 static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) 1445 { 1446 return ((val) << A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK; 1447 } 1448 #define A3XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000 1449 #define A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000 1450 #define A3XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000 1451 #define A3XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000 1452 1453 #define REG_A3XX_HLSQ_CONTROL_1_REG 0x00002201 1454 #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040 1455 #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6 1456 static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) 1457 { 1458 return ((val) << A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK; 1459 } 1460 #define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100 1461 #define A3XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200 1462 #define A3XX_HLSQ_CONTROL_1_REG_ZWCOORD 0x02000000 1463 1464 #define REG_A3XX_HLSQ_CONTROL_2_REG 0x00002202 1465 #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000 1466 #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26 1467 static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) 1468 { 1469 return ((val) << A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK; 1470 } 1471 1472 #define REG_A3XX_HLSQ_CONTROL_3_REG 0x00002203 1473 #define A3XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff 1474 #define A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0 1475 static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val) 1476 { 1477 return ((val) << A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_REGID__MASK; 1478 } 1479 1480 #define REG_A3XX_HLSQ_VS_CONTROL_REG 0x00002204 1481 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff 1482 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0 1483 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) 1484 { 1485 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK; 1486 } 1487 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000 1488 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12 1489 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) 1490 { 1491 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK; 1492 } 1493 #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 1494 #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24 1495 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) 1496 { 1497 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK; 1498 } 1499 1500 #define REG_A3XX_HLSQ_FS_CONTROL_REG 0x00002205 1501 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff 1502 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0 1503 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) 1504 { 1505 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK; 1506 } 1507 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000 1508 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12 1509 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) 1510 { 1511 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK; 1512 } 1513 #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 1514 #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24 1515 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) 1516 { 1517 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK; 1518 } 1519 1520 #define REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG 0x00002206 1521 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff 1522 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT 0 1523 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val) 1524 { 1525 return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK; 1526 } 1527 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000 1528 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT 16 1529 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val) 1530 { 1531 return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK; 1532 } 1533 1534 #define REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG 0x00002207 1535 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff 1536 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT 0 1537 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val) 1538 { 1539 return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK; 1540 } 1541 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000 1542 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT 16 1543 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val) 1544 { 1545 return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK; 1546 } 1547 1548 #define REG_A3XX_HLSQ_CL_NDRANGE_0_REG 0x0000220a 1549 #define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK 0x00000003 1550 #define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT 0 1551 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM(uint32_t val) 1552 { 1553 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK; 1554 } 1555 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK 0x00000ffc 1556 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT 2 1557 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0(uint32_t val) 1558 { 1559 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK; 1560 } 1561 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK 0x003ff000 1562 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT 12 1563 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1(uint32_t val) 1564 { 1565 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK; 1566 } 1567 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK 0xffc00000 1568 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT 22 1569 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2(uint32_t val) 1570 { 1571 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK; 1572 } 1573 1574 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK(uint32_t i0) { return 0x0000220b + 0x2*i0; } 1575 1576 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0; } 1577 1578 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { return 0x0000220c + 0x2*i0; } 1579 1580 #define REG_A3XX_HLSQ_CL_CONTROL_0_REG 0x00002211 1581 1582 #define REG_A3XX_HLSQ_CL_CONTROL_1_REG 0x00002212 1583 1584 #define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG 0x00002214 1585 1586 static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP(uint32_t i0) { return 0x00002215 + 0x1*i0; } 1587 1588 static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO(uint32_t i0) { return 0x00002215 + 0x1*i0; } 1589 1590 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Y_REG 0x00002216 1591 1592 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG 0x00002217 1593 1594 #define REG_A3XX_HLSQ_CL_WG_OFFSET_REG 0x0000221a 1595 1596 #define REG_A3XX_VFD_CONTROL_0 0x00002240 1597 #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x0003ffff 1598 #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0 1599 static inline uint32_t A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) 1600 { 1601 return ((val) << A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK; 1602 } 1603 #define A3XX_VFD_CONTROL_0_PACKETSIZE__MASK 0x003c0000 1604 #define A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT 18 1605 static inline uint32_t A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val) 1606 { 1607 return ((val) << A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT) & A3XX_VFD_CONTROL_0_PACKETSIZE__MASK; 1608 } 1609 #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x07c00000 1610 #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 22 1611 static inline uint32_t A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) 1612 { 1613 return ((val) << A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK; 1614 } 1615 #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xf8000000 1616 #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 27 1617 static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) 1618 { 1619 return ((val) << A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK; 1620 } 1621 1622 #define REG_A3XX_VFD_CONTROL_1 0x00002241 1623 #define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff 1624 #define A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0 1625 static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) 1626 { 1627 return ((val) << A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK; 1628 } 1629 #define A3XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000 1630 #define A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16 1631 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 1632 { 1633 return ((val) << A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A3XX_VFD_CONTROL_1_REGID4VTX__MASK; 1634 } 1635 #define A3XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000 1636 #define A3XX_VFD_CONTROL_1_REGID4INST__SHIFT 24 1637 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 1638 { 1639 return ((val) << A3XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A3XX_VFD_CONTROL_1_REGID4INST__MASK; 1640 } 1641 1642 #define REG_A3XX_VFD_INDEX_MIN 0x00002242 1643 1644 #define REG_A3XX_VFD_INDEX_MAX 0x00002243 1645 1646 #define REG_A3XX_VFD_INSTANCEID_OFFSET 0x00002244 1647 1648 #define REG_A3XX_VFD_INDEX_OFFSET 0x00002245 1649 1650 #define REG_A3XX_VFD_INDEX_OFFSET 0x00002245 1651 1652 static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0) { return 0x00002246 + 0x2*i0; } 1653 1654 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; } 1655 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f 1656 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0 1657 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) 1658 { 1659 return ((val) << A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK; 1660 } 1661 #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0000ff80 1662 #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7 1663 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) 1664 { 1665 return ((val) << A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK; 1666 } 1667 #define A3XX_VFD_FETCH_INSTR_0_INSTANCED 0x00010000 1668 #define A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00020000 1669 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK 0x00fc0000 1670 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT 18 1671 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val) 1672 { 1673 return ((val) << A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK; 1674 } 1675 #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK 0xff000000 1676 #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT 24 1677 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val) 1678 { 1679 return ((val) << A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK; 1680 } 1681 1682 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x00002247 + 0x2*i0; } 1683 1684 static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0) { return 0x00002266 + 0x1*i0; } 1685 1686 static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x00002266 + 0x1*i0; } 1687 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f 1688 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0 1689 static inline uint32_t A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) 1690 { 1691 return ((val) << A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK; 1692 } 1693 #define A3XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010 1694 #define A3XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0 1695 #define A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6 1696 static inline uint32_t A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val) 1697 { 1698 return ((val) << A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A3XX_VFD_DECODE_INSTR_FORMAT__MASK; 1699 } 1700 #define A3XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000 1701 #define A3XX_VFD_DECODE_INSTR_REGID__SHIFT 12 1702 static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val) 1703 { 1704 return ((val) << A3XX_VFD_DECODE_INSTR_REGID__SHIFT) & A3XX_VFD_DECODE_INSTR_REGID__MASK; 1705 } 1706 #define A3XX_VFD_DECODE_INSTR_INT 0x00100000 1707 #define A3XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000 1708 #define A3XX_VFD_DECODE_INSTR_SWAP__SHIFT 22 1709 static inline uint32_t A3XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 1710 { 1711 return ((val) << A3XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A3XX_VFD_DECODE_INSTR_SWAP__MASK; 1712 } 1713 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000 1714 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24 1715 static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) 1716 { 1717 return ((val) << A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK; 1718 } 1719 #define A3XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000 1720 #define A3XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000 1721 1722 #define REG_A3XX_VFD_VS_THREADING_THRESHOLD 0x0000227e 1723 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK 0x0000000f 1724 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT 0 1725 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val) 1726 { 1727 return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK; 1728 } 1729 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK 0x0000ff00 1730 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT 8 1731 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val) 1732 { 1733 return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK; 1734 } 1735 1736 #define REG_A3XX_VPC_ATTR 0x00002280 1737 #define A3XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff 1738 #define A3XX_VPC_ATTR_TOTALATTR__SHIFT 0 1739 static inline uint32_t A3XX_VPC_ATTR_TOTALATTR(uint32_t val) 1740 { 1741 return ((val) << A3XX_VPC_ATTR_TOTALATTR__SHIFT) & A3XX_VPC_ATTR_TOTALATTR__MASK; 1742 } 1743 #define A3XX_VPC_ATTR_PSIZE 0x00000200 1744 #define A3XX_VPC_ATTR_THRDASSIGN__MASK 0x0ffff000 1745 #define A3XX_VPC_ATTR_THRDASSIGN__SHIFT 12 1746 static inline uint32_t A3XX_VPC_ATTR_THRDASSIGN(uint32_t val) 1747 { 1748 return ((val) << A3XX_VPC_ATTR_THRDASSIGN__SHIFT) & A3XX_VPC_ATTR_THRDASSIGN__MASK; 1749 } 1750 #define A3XX_VPC_ATTR_LMSIZE__MASK 0xf0000000 1751 #define A3XX_VPC_ATTR_LMSIZE__SHIFT 28 1752 static inline uint32_t A3XX_VPC_ATTR_LMSIZE(uint32_t val) 1753 { 1754 return ((val) << A3XX_VPC_ATTR_LMSIZE__SHIFT) & A3XX_VPC_ATTR_LMSIZE__MASK; 1755 } 1756 1757 #define REG_A3XX_VPC_PACK 0x00002281 1758 #define A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00 1759 #define A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8 1760 static inline uint32_t A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) 1761 { 1762 return ((val) << A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK; 1763 } 1764 #define A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000 1765 #define A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16 1766 static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) 1767 { 1768 return ((val) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK; 1769 } 1770 1771 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002282 + 0x1*i0; } 1772 1773 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002282 + 0x1*i0; } 1774 #define A3XX_VPC_VARYING_INTERP_MODE_C0__MASK 0x00000003 1775 #define A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT 0 1776 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C0(enum a3xx_intp_mode val) 1777 { 1778 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C0__MASK; 1779 } 1780 #define A3XX_VPC_VARYING_INTERP_MODE_C1__MASK 0x0000000c 1781 #define A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT 2 1782 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C1(enum a3xx_intp_mode val) 1783 { 1784 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C1__MASK; 1785 } 1786 #define A3XX_VPC_VARYING_INTERP_MODE_C2__MASK 0x00000030 1787 #define A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT 4 1788 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C2(enum a3xx_intp_mode val) 1789 { 1790 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C2__MASK; 1791 } 1792 #define A3XX_VPC_VARYING_INTERP_MODE_C3__MASK 0x000000c0 1793 #define A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT 6 1794 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C3(enum a3xx_intp_mode val) 1795 { 1796 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C3__MASK; 1797 } 1798 #define A3XX_VPC_VARYING_INTERP_MODE_C4__MASK 0x00000300 1799 #define A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT 8 1800 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C4(enum a3xx_intp_mode val) 1801 { 1802 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C4__MASK; 1803 } 1804 #define A3XX_VPC_VARYING_INTERP_MODE_C5__MASK 0x00000c00 1805 #define A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT 10 1806 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C5(enum a3xx_intp_mode val) 1807 { 1808 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C5__MASK; 1809 } 1810 #define A3XX_VPC_VARYING_INTERP_MODE_C6__MASK 0x00003000 1811 #define A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT 12 1812 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C6(enum a3xx_intp_mode val) 1813 { 1814 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C6__MASK; 1815 } 1816 #define A3XX_VPC_VARYING_INTERP_MODE_C7__MASK 0x0000c000 1817 #define A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT 14 1818 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C7(enum a3xx_intp_mode val) 1819 { 1820 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C7__MASK; 1821 } 1822 #define A3XX_VPC_VARYING_INTERP_MODE_C8__MASK 0x00030000 1823 #define A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT 16 1824 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C8(enum a3xx_intp_mode val) 1825 { 1826 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C8__MASK; 1827 } 1828 #define A3XX_VPC_VARYING_INTERP_MODE_C9__MASK 0x000c0000 1829 #define A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT 18 1830 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C9(enum a3xx_intp_mode val) 1831 { 1832 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C9__MASK; 1833 } 1834 #define A3XX_VPC_VARYING_INTERP_MODE_CA__MASK 0x00300000 1835 #define A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT 20 1836 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CA(enum a3xx_intp_mode val) 1837 { 1838 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CA__MASK; 1839 } 1840 #define A3XX_VPC_VARYING_INTERP_MODE_CB__MASK 0x00c00000 1841 #define A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT 22 1842 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CB(enum a3xx_intp_mode val) 1843 { 1844 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CB__MASK; 1845 } 1846 #define A3XX_VPC_VARYING_INTERP_MODE_CC__MASK 0x03000000 1847 #define A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT 24 1848 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CC(enum a3xx_intp_mode val) 1849 { 1850 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CC__MASK; 1851 } 1852 #define A3XX_VPC_VARYING_INTERP_MODE_CD__MASK 0x0c000000 1853 #define A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT 26 1854 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CD(enum a3xx_intp_mode val) 1855 { 1856 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CD__MASK; 1857 } 1858 #define A3XX_VPC_VARYING_INTERP_MODE_CE__MASK 0x30000000 1859 #define A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT 28 1860 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CE(enum a3xx_intp_mode val) 1861 { 1862 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CE__MASK; 1863 } 1864 #define A3XX_VPC_VARYING_INTERP_MODE_CF__MASK 0xc0000000 1865 #define A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT 30 1866 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CF(enum a3xx_intp_mode val) 1867 { 1868 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CF__MASK; 1869 } 1870 1871 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; } 1872 1873 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; } 1874 #define A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK 0x00000003 1875 #define A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT 0 1876 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C0(enum a3xx_repl_mode val) 1877 { 1878 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK; 1879 } 1880 #define A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK 0x0000000c 1881 #define A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT 2 1882 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C1(enum a3xx_repl_mode val) 1883 { 1884 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK; 1885 } 1886 #define A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK 0x00000030 1887 #define A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT 4 1888 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C2(enum a3xx_repl_mode val) 1889 { 1890 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK; 1891 } 1892 #define A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK 0x000000c0 1893 #define A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT 6 1894 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C3(enum a3xx_repl_mode val) 1895 { 1896 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK; 1897 } 1898 #define A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK 0x00000300 1899 #define A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT 8 1900 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C4(enum a3xx_repl_mode val) 1901 { 1902 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK; 1903 } 1904 #define A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK 0x00000c00 1905 #define A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT 10 1906 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C5(enum a3xx_repl_mode val) 1907 { 1908 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK; 1909 } 1910 #define A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK 0x00003000 1911 #define A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT 12 1912 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C6(enum a3xx_repl_mode val) 1913 { 1914 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK; 1915 } 1916 #define A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK 0x0000c000 1917 #define A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT 14 1918 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C7(enum a3xx_repl_mode val) 1919 { 1920 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK; 1921 } 1922 #define A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK 0x00030000 1923 #define A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT 16 1924 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C8(enum a3xx_repl_mode val) 1925 { 1926 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK; 1927 } 1928 #define A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK 0x000c0000 1929 #define A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT 18 1930 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C9(enum a3xx_repl_mode val) 1931 { 1932 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK; 1933 } 1934 #define A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK 0x00300000 1935 #define A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT 20 1936 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CA(enum a3xx_repl_mode val) 1937 { 1938 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK; 1939 } 1940 #define A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK 0x00c00000 1941 #define A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT 22 1942 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CB(enum a3xx_repl_mode val) 1943 { 1944 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK; 1945 } 1946 #define A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK 0x03000000 1947 #define A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT 24 1948 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CC(enum a3xx_repl_mode val) 1949 { 1950 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK; 1951 } 1952 #define A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK 0x0c000000 1953 #define A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT 26 1954 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CD(enum a3xx_repl_mode val) 1955 { 1956 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK; 1957 } 1958 #define A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK 0x30000000 1959 #define A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT 28 1960 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CE(enum a3xx_repl_mode val) 1961 { 1962 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK; 1963 } 1964 #define A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK 0xc0000000 1965 #define A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT 30 1966 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CF(enum a3xx_repl_mode val) 1967 { 1968 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK; 1969 } 1970 1971 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0 0x0000228a 1972 1973 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_1 0x0000228b 1974 1975 #define REG_A3XX_SP_SP_CTRL_REG 0x000022c0 1976 #define A3XX_SP_SP_CTRL_REG_RESOLVE 0x00010000 1977 #define A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK 0x00040000 1978 #define A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT 18 1979 static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val) 1980 { 1981 return ((val) << A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK; 1982 } 1983 #define A3XX_SP_SP_CTRL_REG_BINNING 0x00080000 1984 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK 0x00300000 1985 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT 20 1986 static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val) 1987 { 1988 return ((val) << A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK; 1989 } 1990 #define A3XX_SP_SP_CTRL_REG_L0MODE__MASK 0x00c00000 1991 #define A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT 22 1992 static inline uint32_t A3XX_SP_SP_CTRL_REG_L0MODE(uint32_t val) 1993 { 1994 return ((val) << A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT) & A3XX_SP_SP_CTRL_REG_L0MODE__MASK; 1995 } 1996 1997 #define REG_A3XX_SP_VS_CTRL_REG0 0x000022c4 1998 #define A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 1999 #define A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 2000 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 2001 { 2002 return ((val) << A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK; 2003 } 2004 #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002 2005 #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1 2006 static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) 2007 { 2008 return ((val) << A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK; 2009 } 2010 #define A3XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004 2011 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 2012 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 2013 static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 2014 { 2015 return ((val) << A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 2016 } 2017 #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 2018 #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 2019 static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 2020 { 2021 return ((val) << A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 2022 } 2023 #define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 2024 #define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 2025 static inline uint32_t A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 2026 { 2027 return ((val) << A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK; 2028 } 2029 #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000 2030 #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20 2031 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 2032 { 2033 return ((val) << A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; 2034 } 2035 #define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000 2036 #define A3XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000 2037 #define A3XX_SP_VS_CTRL_REG0_COMPUTEMODE 0x00800000 2038 #define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK 0xff000000 2039 #define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT 24 2040 static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val) 2041 { 2042 return ((val) << A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG0_LENGTH__MASK; 2043 } 2044 2045 #define REG_A3XX_SP_VS_CTRL_REG1 0x000022c5 2046 #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff 2047 #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0 2048 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) 2049 { 2050 return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK; 2051 } 2052 #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00 2053 #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10 2054 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) 2055 { 2056 return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK; 2057 } 2058 #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000 2059 #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24 2060 static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) 2061 { 2062 return ((val) << A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK; 2063 } 2064 2065 #define REG_A3XX_SP_VS_PARAM_REG 0x000022c6 2066 #define A3XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff 2067 #define A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0 2068 static inline uint32_t A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) 2069 { 2070 return ((val) << A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_POSREGID__MASK; 2071 } 2072 #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00 2073 #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8 2074 static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) 2075 { 2076 return ((val) << A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK; 2077 } 2078 #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000 2079 #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20 2080 static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) 2081 { 2082 return ((val) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; 2083 } 2084 2085 static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 2086 2087 static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 2088 #define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff 2089 #define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 2090 static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 2091 { 2092 return ((val) << A3XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_A_REGID__MASK; 2093 } 2094 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00 2095 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9 2096 static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 2097 { 2098 return ((val) << A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 2099 } 2100 #define A3XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000 2101 #define A3XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 2102 static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 2103 { 2104 return ((val) << A3XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_B_REGID__MASK; 2105 } 2106 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000 2107 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25 2108 static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 2109 { 2110 return ((val) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 2111 } 2112 2113 static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; } 2114 2115 static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; } 2116 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 2117 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 2118 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 2119 { 2120 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 2121 } 2122 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 2123 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 2124 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 2125 { 2126 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 2127 } 2128 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 2129 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 2130 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 2131 { 2132 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 2133 } 2134 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 2135 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 2136 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 2137 { 2138 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 2139 } 2140 2141 #define REG_A3XX_SP_VS_OBJ_OFFSET_REG 0x000022d4 2142 #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2143 #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2144 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2145 { 2146 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2147 } 2148 #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2149 #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2150 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2151 { 2152 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2153 } 2154 2155 #define REG_A3XX_SP_VS_OBJ_START_REG 0x000022d5 2156 2157 #define REG_A3XX_SP_VS_PVT_MEM_PARAM_REG 0x000022d6 2158 2159 #define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG 0x000022d7 2160 2161 #define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG 0x000022d8 2162 2163 #define REG_A3XX_SP_VS_LENGTH_REG 0x000022df 2164 #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff 2165 #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT 0 2166 static inline uint32_t A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val) 2167 { 2168 return ((val) << A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK; 2169 } 2170 2171 #define REG_A3XX_SP_FS_CTRL_REG0 0x000022e0 2172 #define A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 2173 #define A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 2174 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 2175 { 2176 return ((val) << A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK; 2177 } 2178 #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002 2179 #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1 2180 static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) 2181 { 2182 return ((val) << A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK; 2183 } 2184 #define A3XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004 2185 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 2186 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 2187 static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 2188 { 2189 return ((val) << A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 2190 } 2191 #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 2192 #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 2193 static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 2194 { 2195 return ((val) << A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 2196 } 2197 #define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 2198 #define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 2199 static inline uint32_t A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 2200 { 2201 return ((val) << A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK; 2202 } 2203 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 2204 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 2205 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 2206 { 2207 return ((val) << A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 2208 } 2209 #define A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000 2210 #define A3XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000 2211 #define A3XX_SP_FS_CTRL_REG0_COMPUTEMODE 0x00800000 2212 #define A3XX_SP_FS_CTRL_REG0_LENGTH__MASK 0xff000000 2213 #define A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT 24 2214 static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val) 2215 { 2216 return ((val) << A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG0_LENGTH__MASK; 2217 } 2218 2219 #define REG_A3XX_SP_FS_CTRL_REG1 0x000022e1 2220 #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff 2221 #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0 2222 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) 2223 { 2224 return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK; 2225 } 2226 #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00 2227 #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10 2228 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) 2229 { 2230 return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK; 2231 } 2232 #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x00f00000 2233 #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 20 2234 static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) 2235 { 2236 return ((val) << A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK; 2237 } 2238 #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK 0x3f000000 2239 #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT 24 2240 static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val) 2241 { 2242 return ((val) << A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT) & A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK; 2243 } 2244 2245 #define REG_A3XX_SP_FS_OBJ_OFFSET_REG 0x000022e2 2246 #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2247 #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2248 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2249 { 2250 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2251 } 2252 #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2253 #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2254 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2255 { 2256 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2257 } 2258 2259 #define REG_A3XX_SP_FS_OBJ_START_REG 0x000022e3 2260 2261 #define REG_A3XX_SP_FS_PVT_MEM_PARAM_REG 0x000022e4 2262 2263 #define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG 0x000022e5 2264 2265 #define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG 0x000022e6 2266 2267 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0 0x000022e8 2268 2269 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1 0x000022e9 2270 2271 #define REG_A3XX_SP_FS_OUTPUT_REG 0x000022ec 2272 #define A3XX_SP_FS_OUTPUT_REG_MRT__MASK 0x00000003 2273 #define A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0 2274 static inline uint32_t A3XX_SP_FS_OUTPUT_REG_MRT(uint32_t val) 2275 { 2276 return ((val) << A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A3XX_SP_FS_OUTPUT_REG_MRT__MASK; 2277 } 2278 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080 2279 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00 2280 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8 2281 static inline uint32_t A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) 2282 { 2283 return ((val) << A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK; 2284 } 2285 2286 static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0) { return 0x000022f0 + 0x1*i0; } 2287 2288 static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f0 + 0x1*i0; } 2289 #define A3XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff 2290 #define A3XX_SP_FS_MRT_REG_REGID__SHIFT 0 2291 static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val) 2292 { 2293 return ((val) << A3XX_SP_FS_MRT_REG_REGID__SHIFT) & A3XX_SP_FS_MRT_REG_REGID__MASK; 2294 } 2295 #define A3XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100 2296 #define A3XX_SP_FS_MRT_REG_SINT 0x00000400 2297 #define A3XX_SP_FS_MRT_REG_UINT 0x00000800 2298 2299 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0) { return 0x000022f4 + 0x1*i0; } 2300 2301 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0) { return 0x000022f4 + 0x1*i0; } 2302 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK 0x0000003f 2303 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT 0 2304 static inline uint32_t A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val) 2305 { 2306 return ((val) << A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT) & A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK; 2307 } 2308 2309 #define REG_A3XX_SP_FS_LENGTH_REG 0x000022ff 2310 #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff 2311 #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT 0 2312 static inline uint32_t A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val) 2313 { 2314 return ((val) << A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK; 2315 } 2316 2317 #define REG_A3XX_PA_SC_AA_CONFIG 0x00002301 2318 2319 #define REG_A3XX_TPL1_TP_VS_TEX_OFFSET 0x00002340 2320 #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff 2321 #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0 2322 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) 2323 { 2324 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK; 2325 } 2326 #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00 2327 #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8 2328 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) 2329 { 2330 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK; 2331 } 2332 #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000 2333 #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT 16 2334 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val) 2335 { 2336 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK; 2337 } 2338 2339 #define REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002341 2340 2341 #define REG_A3XX_TPL1_TP_FS_TEX_OFFSET 0x00002342 2342 #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff 2343 #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0 2344 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) 2345 { 2346 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK; 2347 } 2348 #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00 2349 #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8 2350 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) 2351 { 2352 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK; 2353 } 2354 #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000 2355 #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT 16 2356 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val) 2357 { 2358 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK; 2359 } 2360 2361 #define REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x00002343 2362 2363 #define REG_A3XX_VBIF_CLKON 0x00003001 2364 2365 #define REG_A3XX_VBIF_FIXED_SORT_EN 0x0000300c 2366 2367 #define REG_A3XX_VBIF_FIXED_SORT_SEL0 0x0000300d 2368 2369 #define REG_A3XX_VBIF_FIXED_SORT_SEL1 0x0000300e 2370 2371 #define REG_A3XX_VBIF_ABIT_SORT 0x0000301c 2372 2373 #define REG_A3XX_VBIF_ABIT_SORT_CONF 0x0000301d 2374 2375 #define REG_A3XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 2376 2377 #define REG_A3XX_VBIF_IN_RD_LIM_CONF0 0x0000302c 2378 2379 #define REG_A3XX_VBIF_IN_RD_LIM_CONF1 0x0000302d 2380 2381 #define REG_A3XX_VBIF_IN_WR_LIM_CONF0 0x00003030 2382 2383 #define REG_A3XX_VBIF_IN_WR_LIM_CONF1 0x00003031 2384 2385 #define REG_A3XX_VBIF_OUT_RD_LIM_CONF0 0x00003034 2386 2387 #define REG_A3XX_VBIF_OUT_WR_LIM_CONF0 0x00003035 2388 2389 #define REG_A3XX_VBIF_DDR_OUT_MAX_BURST 0x00003036 2390 2391 #define REG_A3XX_VBIF_ARB_CTL 0x0000303c 2392 2393 #define REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049 2394 2395 #define REG_A3XX_VBIF_OUT_AXI_AMEMTYPE_CONF0 0x00003058 2396 2397 #define REG_A3XX_VBIF_OUT_AXI_AOOO_EN 0x0000305e 2398 2399 #define REG_A3XX_VBIF_OUT_AXI_AOOO 0x0000305f 2400 2401 #define REG_A3XX_VBIF_PERF_CNT_EN 0x00003070 2402 #define A3XX_VBIF_PERF_CNT_EN_CNT0 0x00000001 2403 #define A3XX_VBIF_PERF_CNT_EN_CNT1 0x00000002 2404 #define A3XX_VBIF_PERF_CNT_EN_PWRCNT0 0x00000004 2405 #define A3XX_VBIF_PERF_CNT_EN_PWRCNT1 0x00000008 2406 #define A3XX_VBIF_PERF_CNT_EN_PWRCNT2 0x00000010 2407 2408 #define REG_A3XX_VBIF_PERF_CNT_CLR 0x00003071 2409 #define A3XX_VBIF_PERF_CNT_CLR_CNT0 0x00000001 2410 #define A3XX_VBIF_PERF_CNT_CLR_CNT1 0x00000002 2411 #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT0 0x00000004 2412 #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT1 0x00000008 2413 #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT2 0x00000010 2414 2415 #define REG_A3XX_VBIF_PERF_CNT_SEL 0x00003072 2416 2417 #define REG_A3XX_VBIF_PERF_CNT0_LO 0x00003073 2418 2419 #define REG_A3XX_VBIF_PERF_CNT0_HI 0x00003074 2420 2421 #define REG_A3XX_VBIF_PERF_CNT1_LO 0x00003075 2422 2423 #define REG_A3XX_VBIF_PERF_CNT1_HI 0x00003076 2424 2425 #define REG_A3XX_VBIF_PERF_PWR_CNT0_LO 0x00003077 2426 2427 #define REG_A3XX_VBIF_PERF_PWR_CNT0_HI 0x00003078 2428 2429 #define REG_A3XX_VBIF_PERF_PWR_CNT1_LO 0x00003079 2430 2431 #define REG_A3XX_VBIF_PERF_PWR_CNT1_HI 0x0000307a 2432 2433 #define REG_A3XX_VBIF_PERF_PWR_CNT2_LO 0x0000307b 2434 2435 #define REG_A3XX_VBIF_PERF_PWR_CNT2_HI 0x0000307c 2436 2437 #define REG_A3XX_VSC_BIN_SIZE 0x00000c01 2438 #define A3XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 2439 #define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 2440 static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 2441 { 2442 return ((val >> 5) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A3XX_VSC_BIN_SIZE_WIDTH__MASK; 2443 } 2444 #define A3XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 2445 #define A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5 2446 static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 2447 { 2448 return ((val >> 5) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK; 2449 } 2450 2451 #define REG_A3XX_VSC_SIZE_ADDRESS 0x00000c02 2452 2453 static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 2454 2455 static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 2456 #define A3XX_VSC_PIPE_CONFIG_X__MASK 0x000003ff 2457 #define A3XX_VSC_PIPE_CONFIG_X__SHIFT 0 2458 static inline uint32_t A3XX_VSC_PIPE_CONFIG_X(uint32_t val) 2459 { 2460 return ((val) << A3XX_VSC_PIPE_CONFIG_X__SHIFT) & A3XX_VSC_PIPE_CONFIG_X__MASK; 2461 } 2462 #define A3XX_VSC_PIPE_CONFIG_Y__MASK 0x000ffc00 2463 #define A3XX_VSC_PIPE_CONFIG_Y__SHIFT 10 2464 static inline uint32_t A3XX_VSC_PIPE_CONFIG_Y(uint32_t val) 2465 { 2466 return ((val) << A3XX_VSC_PIPE_CONFIG_Y__SHIFT) & A3XX_VSC_PIPE_CONFIG_Y__MASK; 2467 } 2468 #define A3XX_VSC_PIPE_CONFIG_W__MASK 0x00f00000 2469 #define A3XX_VSC_PIPE_CONFIG_W__SHIFT 20 2470 static inline uint32_t A3XX_VSC_PIPE_CONFIG_W(uint32_t val) 2471 { 2472 return ((val) << A3XX_VSC_PIPE_CONFIG_W__SHIFT) & A3XX_VSC_PIPE_CONFIG_W__MASK; 2473 } 2474 #define A3XX_VSC_PIPE_CONFIG_H__MASK 0x0f000000 2475 #define A3XX_VSC_PIPE_CONFIG_H__SHIFT 24 2476 static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val) 2477 { 2478 return ((val) << A3XX_VSC_PIPE_CONFIG_H__SHIFT) & A3XX_VSC_PIPE_CONFIG_H__MASK; 2479 } 2480 2481 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } 2482 2483 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } 2484 2485 #define REG_A3XX_VSC_BIN_CONTROL 0x00000c3c 2486 #define A3XX_VSC_BIN_CONTROL_BINNING_ENABLE 0x00000001 2487 2488 #define REG_A3XX_UNKNOWN_0C3D 0x00000c3d 2489 2490 #define REG_A3XX_PC_PERFCOUNTER0_SELECT 0x00000c48 2491 2492 #define REG_A3XX_PC_PERFCOUNTER1_SELECT 0x00000c49 2493 2494 #define REG_A3XX_PC_PERFCOUNTER2_SELECT 0x00000c4a 2495 2496 #define REG_A3XX_PC_PERFCOUNTER3_SELECT 0x00000c4b 2497 2498 #define REG_A3XX_GRAS_TSE_DEBUG_ECO 0x00000c81 2499 2500 #define REG_A3XX_GRAS_PERFCOUNTER0_SELECT 0x00000c88 2501 2502 #define REG_A3XX_GRAS_PERFCOUNTER1_SELECT 0x00000c89 2503 2504 #define REG_A3XX_GRAS_PERFCOUNTER2_SELECT 0x00000c8a 2505 2506 #define REG_A3XX_GRAS_PERFCOUNTER3_SELECT 0x00000c8b 2507 2508 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } 2509 2510 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } 2511 2512 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0) { return 0x00000ca1 + 0x4*i0; } 2513 2514 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0) { return 0x00000ca2 + 0x4*i0; } 2515 2516 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) { return 0x00000ca3 + 0x4*i0; } 2517 2518 #define REG_A3XX_RB_GMEM_BASE_ADDR 0x00000cc0 2519 2520 #define REG_A3XX_RB_DEBUG_ECO_CONTROLS_ADDR 0x00000cc1 2521 2522 #define REG_A3XX_RB_PERFCOUNTER0_SELECT 0x00000cc6 2523 2524 #define REG_A3XX_RB_PERFCOUNTER1_SELECT 0x00000cc7 2525 2526 #define REG_A3XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0 2527 #define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff 2528 #define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0 2529 static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) 2530 { 2531 return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK; 2532 } 2533 #define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x0fffc000 2534 #define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 14 2535 static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) 2536 { 2537 return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK; 2538 } 2539 2540 #define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT 0x00000e00 2541 2542 #define REG_A3XX_HLSQ_PERFCOUNTER1_SELECT 0x00000e01 2543 2544 #define REG_A3XX_HLSQ_PERFCOUNTER2_SELECT 0x00000e02 2545 2546 #define REG_A3XX_HLSQ_PERFCOUNTER3_SELECT 0x00000e03 2547 2548 #define REG_A3XX_HLSQ_PERFCOUNTER4_SELECT 0x00000e04 2549 2550 #define REG_A3XX_HLSQ_PERFCOUNTER5_SELECT 0x00000e05 2551 2552 #define REG_A3XX_UNKNOWN_0E43 0x00000e43 2553 2554 #define REG_A3XX_VFD_PERFCOUNTER0_SELECT 0x00000e44 2555 2556 #define REG_A3XX_VFD_PERFCOUNTER1_SELECT 0x00000e45 2557 2558 #define REG_A3XX_VPC_VPC_DEBUG_RAM_SEL 0x00000e61 2559 2560 #define REG_A3XX_VPC_VPC_DEBUG_RAM_READ 0x00000e62 2561 2562 #define REG_A3XX_VPC_PERFCOUNTER0_SELECT 0x00000e64 2563 2564 #define REG_A3XX_VPC_PERFCOUNTER1_SELECT 0x00000e65 2565 2566 #define REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG 0x00000e82 2567 2568 #define REG_A3XX_UCHE_PERFCOUNTER0_SELECT 0x00000e84 2569 2570 #define REG_A3XX_UCHE_PERFCOUNTER1_SELECT 0x00000e85 2571 2572 #define REG_A3XX_UCHE_PERFCOUNTER2_SELECT 0x00000e86 2573 2574 #define REG_A3XX_UCHE_PERFCOUNTER3_SELECT 0x00000e87 2575 2576 #define REG_A3XX_UCHE_PERFCOUNTER4_SELECT 0x00000e88 2577 2578 #define REG_A3XX_UCHE_PERFCOUNTER5_SELECT 0x00000e89 2579 2580 #define REG_A3XX_UCHE_CACHE_INVALIDATE0_REG 0x00000ea0 2581 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK 0x0fffffff 2582 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT 0 2583 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val) 2584 { 2585 return ((val) << A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK; 2586 } 2587 2588 #define REG_A3XX_UCHE_CACHE_INVALIDATE1_REG 0x00000ea1 2589 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK 0x0fffffff 2590 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT 0 2591 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val) 2592 { 2593 return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK; 2594 } 2595 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK 0x30000000 2596 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT 28 2597 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val) 2598 { 2599 return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK; 2600 } 2601 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE 0x80000000 2602 2603 #define REG_A3XX_UNKNOWN_0EA6 0x00000ea6 2604 2605 #define REG_A3XX_SP_PERFCOUNTER0_SELECT 0x00000ec4 2606 2607 #define REG_A3XX_SP_PERFCOUNTER1_SELECT 0x00000ec5 2608 2609 #define REG_A3XX_SP_PERFCOUNTER2_SELECT 0x00000ec6 2610 2611 #define REG_A3XX_SP_PERFCOUNTER3_SELECT 0x00000ec7 2612 2613 #define REG_A3XX_SP_PERFCOUNTER4_SELECT 0x00000ec8 2614 2615 #define REG_A3XX_SP_PERFCOUNTER5_SELECT 0x00000ec9 2616 2617 #define REG_A3XX_SP_PERFCOUNTER6_SELECT 0x00000eca 2618 2619 #define REG_A3XX_SP_PERFCOUNTER7_SELECT 0x00000ecb 2620 2621 #define REG_A3XX_UNKNOWN_0EE0 0x00000ee0 2622 2623 #define REG_A3XX_UNKNOWN_0F03 0x00000f03 2624 2625 #define REG_A3XX_TP_PERFCOUNTER0_SELECT 0x00000f04 2626 2627 #define REG_A3XX_TP_PERFCOUNTER1_SELECT 0x00000f05 2628 2629 #define REG_A3XX_TP_PERFCOUNTER2_SELECT 0x00000f06 2630 2631 #define REG_A3XX_TP_PERFCOUNTER3_SELECT 0x00000f07 2632 2633 #define REG_A3XX_TP_PERFCOUNTER4_SELECT 0x00000f08 2634 2635 #define REG_A3XX_TP_PERFCOUNTER5_SELECT 0x00000f09 2636 2637 #define REG_A3XX_VGT_CL_INITIATOR 0x000021f0 2638 2639 #define REG_A3XX_VGT_EVENT_INITIATOR 0x000021f9 2640 2641 #define REG_A3XX_VGT_DRAW_INITIATOR 0x000021fc 2642 #define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f 2643 #define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 2644 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) 2645 { 2646 return ((val) << A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK; 2647 } 2648 #define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 2649 #define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 2650 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) 2651 { 2652 return ((val) << A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK; 2653 } 2654 #define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600 2655 #define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9 2656 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) 2657 { 2658 return ((val) << A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK; 2659 } 2660 #define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800 2661 #define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11 2662 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) 2663 { 2664 return ((val) << A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK; 2665 } 2666 #define A3XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000 2667 #define A3XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000 2668 #define A3XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000 2669 #define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK 0xff000000 2670 #define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT 24 2671 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) 2672 { 2673 return ((val) << A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK; 2674 } 2675 2676 #define REG_A3XX_VGT_IMMED_DATA 0x000021fd 2677 2678 #define REG_A3XX_TEX_SAMP_0 0x00000000 2679 #define A3XX_TEX_SAMP_0_CLAMPENABLE 0x00000001 2680 #define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR 0x00000002 2681 #define A3XX_TEX_SAMP_0_XY_MAG__MASK 0x0000000c 2682 #define A3XX_TEX_SAMP_0_XY_MAG__SHIFT 2 2683 static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val) 2684 { 2685 return ((val) << A3XX_TEX_SAMP_0_XY_MAG__SHIFT) & A3XX_TEX_SAMP_0_XY_MAG__MASK; 2686 } 2687 #define A3XX_TEX_SAMP_0_XY_MIN__MASK 0x00000030 2688 #define A3XX_TEX_SAMP_0_XY_MIN__SHIFT 4 2689 static inline uint32_t A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val) 2690 { 2691 return ((val) << A3XX_TEX_SAMP_0_XY_MIN__SHIFT) & A3XX_TEX_SAMP_0_XY_MIN__MASK; 2692 } 2693 #define A3XX_TEX_SAMP_0_WRAP_S__MASK 0x000001c0 2694 #define A3XX_TEX_SAMP_0_WRAP_S__SHIFT 6 2695 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val) 2696 { 2697 return ((val) << A3XX_TEX_SAMP_0_WRAP_S__SHIFT) & A3XX_TEX_SAMP_0_WRAP_S__MASK; 2698 } 2699 #define A3XX_TEX_SAMP_0_WRAP_T__MASK 0x00000e00 2700 #define A3XX_TEX_SAMP_0_WRAP_T__SHIFT 9 2701 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val) 2702 { 2703 return ((val) << A3XX_TEX_SAMP_0_WRAP_T__SHIFT) & A3XX_TEX_SAMP_0_WRAP_T__MASK; 2704 } 2705 #define A3XX_TEX_SAMP_0_WRAP_R__MASK 0x00007000 2706 #define A3XX_TEX_SAMP_0_WRAP_R__SHIFT 12 2707 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val) 2708 { 2709 return ((val) << A3XX_TEX_SAMP_0_WRAP_R__SHIFT) & A3XX_TEX_SAMP_0_WRAP_R__MASK; 2710 } 2711 #define A3XX_TEX_SAMP_0_ANISO__MASK 0x00038000 2712 #define A3XX_TEX_SAMP_0_ANISO__SHIFT 15 2713 static inline uint32_t A3XX_TEX_SAMP_0_ANISO(enum a3xx_tex_aniso val) 2714 { 2715 return ((val) << A3XX_TEX_SAMP_0_ANISO__SHIFT) & A3XX_TEX_SAMP_0_ANISO__MASK; 2716 } 2717 #define A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK 0x00700000 2718 #define A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT 20 2719 static inline uint32_t A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val) 2720 { 2721 return ((val) << A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT) & A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK; 2722 } 2723 #define A3XX_TEX_SAMP_0_CUBEMAPSEAMLESSFILTOFF 0x01000000 2724 #define A3XX_TEX_SAMP_0_UNNORM_COORDS 0x80000000 2725 2726 #define REG_A3XX_TEX_SAMP_1 0x00000001 2727 #define A3XX_TEX_SAMP_1_LOD_BIAS__MASK 0x000007ff 2728 #define A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT 0 2729 static inline uint32_t A3XX_TEX_SAMP_1_LOD_BIAS(float val) 2730 { 2731 return ((((int32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT) & A3XX_TEX_SAMP_1_LOD_BIAS__MASK; 2732 } 2733 #define A3XX_TEX_SAMP_1_MAX_LOD__MASK 0x003ff000 2734 #define A3XX_TEX_SAMP_1_MAX_LOD__SHIFT 12 2735 static inline uint32_t A3XX_TEX_SAMP_1_MAX_LOD(float val) 2736 { 2737 return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A3XX_TEX_SAMP_1_MAX_LOD__MASK; 2738 } 2739 #define A3XX_TEX_SAMP_1_MIN_LOD__MASK 0xffc00000 2740 #define A3XX_TEX_SAMP_1_MIN_LOD__SHIFT 22 2741 static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val) 2742 { 2743 return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A3XX_TEX_SAMP_1_MIN_LOD__MASK; 2744 } 2745 2746 #define REG_A3XX_TEX_CONST_0 0x00000000 2747 #define A3XX_TEX_CONST_0_TILED 0x00000001 2748 #define A3XX_TEX_CONST_0_SRGB 0x00000004 2749 #define A3XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 2750 #define A3XX_TEX_CONST_0_SWIZ_X__SHIFT 4 2751 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val) 2752 { 2753 return ((val) << A3XX_TEX_CONST_0_SWIZ_X__SHIFT) & A3XX_TEX_CONST_0_SWIZ_X__MASK; 2754 } 2755 #define A3XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 2756 #define A3XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 2757 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val) 2758 { 2759 return ((val) << A3XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Y__MASK; 2760 } 2761 #define A3XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 2762 #define A3XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 2763 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val) 2764 { 2765 return ((val) << A3XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Z__MASK; 2766 } 2767 #define A3XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 2768 #define A3XX_TEX_CONST_0_SWIZ_W__SHIFT 13 2769 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val) 2770 { 2771 return ((val) << A3XX_TEX_CONST_0_SWIZ_W__SHIFT) & A3XX_TEX_CONST_0_SWIZ_W__MASK; 2772 } 2773 #define A3XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 2774 #define A3XX_TEX_CONST_0_MIPLVLS__SHIFT 16 2775 static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val) 2776 { 2777 return ((val) << A3XX_TEX_CONST_0_MIPLVLS__SHIFT) & A3XX_TEX_CONST_0_MIPLVLS__MASK; 2778 } 2779 #define A3XX_TEX_CONST_0_MSAATEX__MASK 0x00300000 2780 #define A3XX_TEX_CONST_0_MSAATEX__SHIFT 20 2781 static inline uint32_t A3XX_TEX_CONST_0_MSAATEX(enum a3xx_tex_msaa val) 2782 { 2783 return ((val) << A3XX_TEX_CONST_0_MSAATEX__SHIFT) & A3XX_TEX_CONST_0_MSAATEX__MASK; 2784 } 2785 #define A3XX_TEX_CONST_0_FMT__MASK 0x1fc00000 2786 #define A3XX_TEX_CONST_0_FMT__SHIFT 22 2787 static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val) 2788 { 2789 return ((val) << A3XX_TEX_CONST_0_FMT__SHIFT) & A3XX_TEX_CONST_0_FMT__MASK; 2790 } 2791 #define A3XX_TEX_CONST_0_NOCONVERT 0x20000000 2792 #define A3XX_TEX_CONST_0_TYPE__MASK 0xc0000000 2793 #define A3XX_TEX_CONST_0_TYPE__SHIFT 30 2794 static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val) 2795 { 2796 return ((val) << A3XX_TEX_CONST_0_TYPE__SHIFT) & A3XX_TEX_CONST_0_TYPE__MASK; 2797 } 2798 2799 #define REG_A3XX_TEX_CONST_1 0x00000001 2800 #define A3XX_TEX_CONST_1_HEIGHT__MASK 0x00003fff 2801 #define A3XX_TEX_CONST_1_HEIGHT__SHIFT 0 2802 static inline uint32_t A3XX_TEX_CONST_1_HEIGHT(uint32_t val) 2803 { 2804 return ((val) << A3XX_TEX_CONST_1_HEIGHT__SHIFT) & A3XX_TEX_CONST_1_HEIGHT__MASK; 2805 } 2806 #define A3XX_TEX_CONST_1_WIDTH__MASK 0x0fffc000 2807 #define A3XX_TEX_CONST_1_WIDTH__SHIFT 14 2808 static inline uint32_t A3XX_TEX_CONST_1_WIDTH(uint32_t val) 2809 { 2810 return ((val) << A3XX_TEX_CONST_1_WIDTH__SHIFT) & A3XX_TEX_CONST_1_WIDTH__MASK; 2811 } 2812 #define A3XX_TEX_CONST_1_FETCHSIZE__MASK 0xf0000000 2813 #define A3XX_TEX_CONST_1_FETCHSIZE__SHIFT 28 2814 static inline uint32_t A3XX_TEX_CONST_1_FETCHSIZE(enum a3xx_tex_fetchsize val) 2815 { 2816 return ((val) << A3XX_TEX_CONST_1_FETCHSIZE__SHIFT) & A3XX_TEX_CONST_1_FETCHSIZE__MASK; 2817 } 2818 2819 #define REG_A3XX_TEX_CONST_2 0x00000002 2820 #define A3XX_TEX_CONST_2_INDX__MASK 0x000001ff 2821 #define A3XX_TEX_CONST_2_INDX__SHIFT 0 2822 static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val) 2823 { 2824 return ((val) << A3XX_TEX_CONST_2_INDX__SHIFT) & A3XX_TEX_CONST_2_INDX__MASK; 2825 } 2826 #define A3XX_TEX_CONST_2_PITCH__MASK 0x3ffff000 2827 #define A3XX_TEX_CONST_2_PITCH__SHIFT 12 2828 static inline uint32_t A3XX_TEX_CONST_2_PITCH(uint32_t val) 2829 { 2830 return ((val) << A3XX_TEX_CONST_2_PITCH__SHIFT) & A3XX_TEX_CONST_2_PITCH__MASK; 2831 } 2832 #define A3XX_TEX_CONST_2_SWAP__MASK 0xc0000000 2833 #define A3XX_TEX_CONST_2_SWAP__SHIFT 30 2834 static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) 2835 { 2836 return ((val) << A3XX_TEX_CONST_2_SWAP__SHIFT) & A3XX_TEX_CONST_2_SWAP__MASK; 2837 } 2838 2839 #define REG_A3XX_TEX_CONST_3 0x00000003 2840 #define A3XX_TEX_CONST_3_LAYERSZ1__MASK 0x0001ffff 2841 #define A3XX_TEX_CONST_3_LAYERSZ1__SHIFT 0 2842 static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val) 2843 { 2844 return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ1__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ1__MASK; 2845 } 2846 #define A3XX_TEX_CONST_3_DEPTH__MASK 0x0ffe0000 2847 #define A3XX_TEX_CONST_3_DEPTH__SHIFT 17 2848 static inline uint32_t A3XX_TEX_CONST_3_DEPTH(uint32_t val) 2849 { 2850 return ((val) << A3XX_TEX_CONST_3_DEPTH__SHIFT) & A3XX_TEX_CONST_3_DEPTH__MASK; 2851 } 2852 #define A3XX_TEX_CONST_3_LAYERSZ2__MASK 0xf0000000 2853 #define A3XX_TEX_CONST_3_LAYERSZ2__SHIFT 28 2854 static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ2(uint32_t val) 2855 { 2856 return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ2__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ2__MASK; 2857 } 2858 2859 2860 #endif /* A3XX_XML */ 2861