1 #ifndef A3XX_XML 2 #define A3XX_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30) 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30) 15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14895 bytes, from 2015-04-19 15:23:28) 16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-04-12 18:16:35) 17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 60633 bytes, from 2015-05-20 14:48:19) 18 19 Copyright (C) 2013-2015 by the following authors: 20 - Rob Clark <robdclark@gmail.com> (robclark) 21 22 Permission is hereby granted, free of charge, to any person obtaining 23 a copy of this software and associated documentation files (the 24 "Software"), to deal in the Software without restriction, including 25 without limitation the rights to use, copy, modify, merge, publish, 26 distribute, sublicense, and/or sell copies of the Software, and to 27 permit persons to whom the Software is furnished to do so, subject to 28 the following conditions: 29 30 The above copyright notice and this permission notice (including the 31 next paragraph) shall be included in all copies or substantial 32 portions of the Software. 33 34 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 36 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 37 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 38 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 39 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 40 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43 44 enum a3xx_tile_mode { 45 LINEAR = 0, 46 TILE_32X32 = 2, 47 }; 48 49 enum a3xx_state_block_id { 50 HLSQ_BLOCK_ID_TP_TEX = 2, 51 HLSQ_BLOCK_ID_TP_MIPMAP = 3, 52 HLSQ_BLOCK_ID_SP_VS = 4, 53 HLSQ_BLOCK_ID_SP_FS = 6, 54 }; 55 56 enum a3xx_cache_opcode { 57 INVALIDATE = 1, 58 }; 59 60 enum a3xx_vtx_fmt { 61 VFMT_32_FLOAT = 0, 62 VFMT_32_32_FLOAT = 1, 63 VFMT_32_32_32_FLOAT = 2, 64 VFMT_32_32_32_32_FLOAT = 3, 65 VFMT_16_FLOAT = 4, 66 VFMT_16_16_FLOAT = 5, 67 VFMT_16_16_16_FLOAT = 6, 68 VFMT_16_16_16_16_FLOAT = 7, 69 VFMT_32_FIXED = 8, 70 VFMT_32_32_FIXED = 9, 71 VFMT_32_32_32_FIXED = 10, 72 VFMT_32_32_32_32_FIXED = 11, 73 VFMT_16_SINT = 16, 74 VFMT_16_16_SINT = 17, 75 VFMT_16_16_16_SINT = 18, 76 VFMT_16_16_16_16_SINT = 19, 77 VFMT_16_UINT = 20, 78 VFMT_16_16_UINT = 21, 79 VFMT_16_16_16_UINT = 22, 80 VFMT_16_16_16_16_UINT = 23, 81 VFMT_16_SNORM = 24, 82 VFMT_16_16_SNORM = 25, 83 VFMT_16_16_16_SNORM = 26, 84 VFMT_16_16_16_16_SNORM = 27, 85 VFMT_16_UNORM = 28, 86 VFMT_16_16_UNORM = 29, 87 VFMT_16_16_16_UNORM = 30, 88 VFMT_16_16_16_16_UNORM = 31, 89 VFMT_32_UINT = 32, 90 VFMT_32_32_UINT = 33, 91 VFMT_32_32_32_UINT = 34, 92 VFMT_32_32_32_32_UINT = 35, 93 VFMT_32_SINT = 36, 94 VFMT_32_32_SINT = 37, 95 VFMT_32_32_32_SINT = 38, 96 VFMT_32_32_32_32_SINT = 39, 97 VFMT_8_UINT = 40, 98 VFMT_8_8_UINT = 41, 99 VFMT_8_8_8_UINT = 42, 100 VFMT_8_8_8_8_UINT = 43, 101 VFMT_8_UNORM = 44, 102 VFMT_8_8_UNORM = 45, 103 VFMT_8_8_8_UNORM = 46, 104 VFMT_8_8_8_8_UNORM = 47, 105 VFMT_8_SINT = 48, 106 VFMT_8_8_SINT = 49, 107 VFMT_8_8_8_SINT = 50, 108 VFMT_8_8_8_8_SINT = 51, 109 VFMT_8_SNORM = 52, 110 VFMT_8_8_SNORM = 53, 111 VFMT_8_8_8_SNORM = 54, 112 VFMT_8_8_8_8_SNORM = 55, 113 VFMT_10_10_10_2_UINT = 60, 114 VFMT_10_10_10_2_UNORM = 61, 115 VFMT_10_10_10_2_SINT = 62, 116 VFMT_10_10_10_2_SNORM = 63, 117 }; 118 119 enum a3xx_tex_fmt { 120 TFMT_5_6_5_UNORM = 4, 121 TFMT_5_5_5_1_UNORM = 5, 122 TFMT_4_4_4_4_UNORM = 7, 123 TFMT_Z16_UNORM = 9, 124 TFMT_X8Z24_UNORM = 10, 125 TFMT_Z32_FLOAT = 11, 126 TFMT_NV12_UV_TILED = 17, 127 TFMT_NV12_Y_TILED = 19, 128 TFMT_NV12_UV = 21, 129 TFMT_NV12_Y = 23, 130 TFMT_I420_Y = 24, 131 TFMT_I420_U = 26, 132 TFMT_I420_V = 27, 133 TFMT_ATC_RGB = 32, 134 TFMT_ATC_RGBA_EXPLICIT = 33, 135 TFMT_ETC1 = 34, 136 TFMT_ATC_RGBA_INTERPOLATED = 35, 137 TFMT_DXT1 = 36, 138 TFMT_DXT3 = 37, 139 TFMT_DXT5 = 38, 140 TFMT_10_10_10_2_UNORM = 41, 141 TFMT_9_9_9_E5_FLOAT = 42, 142 TFMT_11_11_10_FLOAT = 43, 143 TFMT_A8_UNORM = 44, 144 TFMT_L8_A8_UNORM = 47, 145 TFMT_8_UNORM = 48, 146 TFMT_8_8_UNORM = 49, 147 TFMT_8_8_8_UNORM = 50, 148 TFMT_8_8_8_8_UNORM = 51, 149 TFMT_8_SNORM = 52, 150 TFMT_8_8_SNORM = 53, 151 TFMT_8_8_8_SNORM = 54, 152 TFMT_8_8_8_8_SNORM = 55, 153 TFMT_8_UINT = 56, 154 TFMT_8_8_UINT = 57, 155 TFMT_8_8_8_UINT = 58, 156 TFMT_8_8_8_8_UINT = 59, 157 TFMT_8_SINT = 60, 158 TFMT_8_8_SINT = 61, 159 TFMT_8_8_8_SINT = 62, 160 TFMT_8_8_8_8_SINT = 63, 161 TFMT_16_FLOAT = 64, 162 TFMT_16_16_FLOAT = 65, 163 TFMT_16_16_16_16_FLOAT = 67, 164 TFMT_16_UINT = 68, 165 TFMT_16_16_UINT = 69, 166 TFMT_16_16_16_16_UINT = 71, 167 TFMT_16_SINT = 72, 168 TFMT_16_16_SINT = 73, 169 TFMT_16_16_16_16_SINT = 75, 170 TFMT_16_UNORM = 76, 171 TFMT_16_16_UNORM = 77, 172 TFMT_16_16_16_16_UNORM = 79, 173 TFMT_16_SNORM = 80, 174 TFMT_16_16_SNORM = 81, 175 TFMT_16_16_16_16_SNORM = 83, 176 TFMT_32_FLOAT = 84, 177 TFMT_32_32_FLOAT = 85, 178 TFMT_32_32_32_32_FLOAT = 87, 179 TFMT_32_UINT = 88, 180 TFMT_32_32_UINT = 89, 181 TFMT_32_32_32_32_UINT = 91, 182 TFMT_32_SINT = 92, 183 TFMT_32_32_SINT = 93, 184 TFMT_32_32_32_32_SINT = 95, 185 TFMT_ETC2_RG11_SNORM = 112, 186 TFMT_ETC2_RG11_UNORM = 113, 187 TFMT_ETC2_R11_SNORM = 114, 188 TFMT_ETC2_R11_UNORM = 115, 189 TFMT_ETC2_RGBA8 = 116, 190 TFMT_ETC2_RGB8A1 = 117, 191 TFMT_ETC2_RGB8 = 118, 192 }; 193 194 enum a3xx_tex_fetchsize { 195 TFETCH_DISABLE = 0, 196 TFETCH_1_BYTE = 1, 197 TFETCH_2_BYTE = 2, 198 TFETCH_4_BYTE = 3, 199 TFETCH_8_BYTE = 4, 200 TFETCH_16_BYTE = 5, 201 }; 202 203 enum a3xx_color_fmt { 204 RB_R5G6B5_UNORM = 0, 205 RB_R5G5B5A1_UNORM = 1, 206 RB_R4G4B4A4_UNORM = 3, 207 RB_R8G8B8_UNORM = 4, 208 RB_R8G8B8A8_UNORM = 8, 209 RB_R8G8B8A8_SNORM = 9, 210 RB_R8G8B8A8_UINT = 10, 211 RB_R8G8B8A8_SINT = 11, 212 RB_R8G8_UNORM = 12, 213 RB_R8G8_SNORM = 13, 214 RB_R8_UINT = 14, 215 RB_R8_SINT = 15, 216 RB_R10G10B10A2_UNORM = 16, 217 RB_A8_UNORM = 20, 218 RB_R8_UNORM = 21, 219 RB_R16_FLOAT = 24, 220 RB_R16G16_FLOAT = 25, 221 RB_R16G16B16A16_FLOAT = 27, 222 RB_R11G11B10_FLOAT = 28, 223 RB_R16_SNORM = 32, 224 RB_R16G16_SNORM = 33, 225 RB_R16G16B16A16_SNORM = 35, 226 RB_R16_UNORM = 36, 227 RB_R16G16_UNORM = 37, 228 RB_R16G16B16A16_UNORM = 39, 229 RB_R16_SINT = 40, 230 RB_R16G16_SINT = 41, 231 RB_R16G16B16A16_SINT = 43, 232 RB_R16_UINT = 44, 233 RB_R16G16_UINT = 45, 234 RB_R16G16B16A16_UINT = 47, 235 RB_R32_FLOAT = 48, 236 RB_R32G32_FLOAT = 49, 237 RB_R32G32B32A32_FLOAT = 51, 238 RB_R32_SINT = 52, 239 RB_R32G32_SINT = 53, 240 RB_R32G32B32A32_SINT = 55, 241 RB_R32_UINT = 56, 242 RB_R32G32_UINT = 57, 243 RB_R32G32B32A32_UINT = 59, 244 }; 245 246 enum a3xx_sp_perfcounter_select { 247 SP_FS_CFLOW_INSTRUCTIONS = 12, 248 SP_FS_FULL_ALU_INSTRUCTIONS = 14, 249 SP0_ICL1_MISSES = 26, 250 SP_ALU_ACTIVE_CYCLES = 29, 251 }; 252 253 enum a3xx_rop_code { 254 ROP_CLEAR = 0, 255 ROP_NOR = 1, 256 ROP_AND_INVERTED = 2, 257 ROP_COPY_INVERTED = 3, 258 ROP_AND_REVERSE = 4, 259 ROP_INVERT = 5, 260 ROP_XOR = 6, 261 ROP_NAND = 7, 262 ROP_AND = 8, 263 ROP_EQUIV = 9, 264 ROP_NOOP = 10, 265 ROP_OR_INVERTED = 11, 266 ROP_COPY = 12, 267 ROP_OR_REVERSE = 13, 268 ROP_OR = 14, 269 ROP_SET = 15, 270 }; 271 272 enum a3xx_rb_blend_opcode { 273 BLEND_DST_PLUS_SRC = 0, 274 BLEND_SRC_MINUS_DST = 1, 275 BLEND_DST_MINUS_SRC = 2, 276 BLEND_MIN_DST_SRC = 3, 277 BLEND_MAX_DST_SRC = 4, 278 }; 279 280 enum a3xx_intp_mode { 281 SMOOTH = 0, 282 FLAT = 1, 283 }; 284 285 enum a3xx_repl_mode { 286 S = 1, 287 T = 2, 288 ONE_T = 3, 289 }; 290 291 enum a3xx_tex_filter { 292 A3XX_TEX_NEAREST = 0, 293 A3XX_TEX_LINEAR = 1, 294 A3XX_TEX_ANISO = 2, 295 }; 296 297 enum a3xx_tex_clamp { 298 A3XX_TEX_REPEAT = 0, 299 A3XX_TEX_CLAMP_TO_EDGE = 1, 300 A3XX_TEX_MIRROR_REPEAT = 2, 301 A3XX_TEX_CLAMP_TO_BORDER = 3, 302 A3XX_TEX_MIRROR_CLAMP = 4, 303 }; 304 305 enum a3xx_tex_aniso { 306 A3XX_TEX_ANISO_1 = 0, 307 A3XX_TEX_ANISO_2 = 1, 308 A3XX_TEX_ANISO_4 = 2, 309 A3XX_TEX_ANISO_8 = 3, 310 A3XX_TEX_ANISO_16 = 4, 311 }; 312 313 enum a3xx_tex_swiz { 314 A3XX_TEX_X = 0, 315 A3XX_TEX_Y = 1, 316 A3XX_TEX_Z = 2, 317 A3XX_TEX_W = 3, 318 A3XX_TEX_ZERO = 4, 319 A3XX_TEX_ONE = 5, 320 }; 321 322 enum a3xx_tex_type { 323 A3XX_TEX_1D = 0, 324 A3XX_TEX_2D = 1, 325 A3XX_TEX_CUBE = 2, 326 A3XX_TEX_3D = 3, 327 }; 328 329 #define A3XX_INT0_RBBM_GPU_IDLE 0x00000001 330 #define A3XX_INT0_RBBM_AHB_ERROR 0x00000002 331 #define A3XX_INT0_RBBM_REG_TIMEOUT 0x00000004 332 #define A3XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 333 #define A3XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 334 #define A3XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020 335 #define A3XX_INT0_VFD_ERROR 0x00000040 336 #define A3XX_INT0_CP_SW_INT 0x00000080 337 #define A3XX_INT0_CP_T0_PACKET_IN_IB 0x00000100 338 #define A3XX_INT0_CP_OPCODE_ERROR 0x00000200 339 #define A3XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400 340 #define A3XX_INT0_CP_HW_FAULT 0x00000800 341 #define A3XX_INT0_CP_DMA 0x00001000 342 #define A3XX_INT0_CP_IB2_INT 0x00002000 343 #define A3XX_INT0_CP_IB1_INT 0x00004000 344 #define A3XX_INT0_CP_RB_INT 0x00008000 345 #define A3XX_INT0_CP_REG_PROTECT_FAULT 0x00010000 346 #define A3XX_INT0_CP_RB_DONE_TS 0x00020000 347 #define A3XX_INT0_CP_VS_DONE_TS 0x00040000 348 #define A3XX_INT0_CP_PS_DONE_TS 0x00080000 349 #define A3XX_INT0_CACHE_FLUSH_TS 0x00100000 350 #define A3XX_INT0_CP_AHB_ERROR_HALT 0x00200000 351 #define A3XX_INT0_MISC_HANG_DETECT 0x01000000 352 #define A3XX_INT0_UCHE_OOB_ACCESS 0x02000000 353 #define REG_A3XX_RBBM_HW_VERSION 0x00000000 354 355 #define REG_A3XX_RBBM_HW_RELEASE 0x00000001 356 357 #define REG_A3XX_RBBM_HW_CONFIGURATION 0x00000002 358 359 #define REG_A3XX_RBBM_CLOCK_CTL 0x00000010 360 361 #define REG_A3XX_RBBM_SP_HYST_CNT 0x00000012 362 363 #define REG_A3XX_RBBM_SW_RESET_CMD 0x00000018 364 365 #define REG_A3XX_RBBM_AHB_CTL0 0x00000020 366 367 #define REG_A3XX_RBBM_AHB_CTL1 0x00000021 368 369 #define REG_A3XX_RBBM_AHB_CMD 0x00000022 370 371 #define REG_A3XX_RBBM_AHB_ERROR_STATUS 0x00000027 372 373 #define REG_A3XX_RBBM_GPR0_CTL 0x0000002e 374 375 #define REG_A3XX_RBBM_STATUS 0x00000030 376 #define A3XX_RBBM_STATUS_HI_BUSY 0x00000001 377 #define A3XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 378 #define A3XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 379 #define A3XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000 380 #define A3XX_RBBM_STATUS_VBIF_BUSY 0x00008000 381 #define A3XX_RBBM_STATUS_TSE_BUSY 0x00010000 382 #define A3XX_RBBM_STATUS_RAS_BUSY 0x00020000 383 #define A3XX_RBBM_STATUS_RB_BUSY 0x00040000 384 #define A3XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 385 #define A3XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 386 #define A3XX_RBBM_STATUS_VFD_BUSY 0x00200000 387 #define A3XX_RBBM_STATUS_VPC_BUSY 0x00400000 388 #define A3XX_RBBM_STATUS_UCHE_BUSY 0x00800000 389 #define A3XX_RBBM_STATUS_SP_BUSY 0x01000000 390 #define A3XX_RBBM_STATUS_TPL1_BUSY 0x02000000 391 #define A3XX_RBBM_STATUS_MARB_BUSY 0x04000000 392 #define A3XX_RBBM_STATUS_VSC_BUSY 0x08000000 393 #define A3XX_RBBM_STATUS_ARB_BUSY 0x10000000 394 #define A3XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 395 #define A3XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000 396 #define A3XX_RBBM_STATUS_GPU_BUSY 0x80000000 397 398 #define REG_A3XX_RBBM_NQWAIT_UNTIL 0x00000040 399 400 #define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x00000033 401 402 #define REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL 0x00000050 403 404 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL0 0x00000051 405 406 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL1 0x00000054 407 408 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL2 0x00000057 409 410 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3 0x0000005a 411 412 #define REG_A3XX_RBBM_INT_SET_CMD 0x00000060 413 414 #define REG_A3XX_RBBM_INT_CLEAR_CMD 0x00000061 415 416 #define REG_A3XX_RBBM_INT_0_MASK 0x00000063 417 418 #define REG_A3XX_RBBM_INT_0_STATUS 0x00000064 419 420 #define REG_A3XX_RBBM_PERFCTR_CTL 0x00000080 421 #define A3XX_RBBM_PERFCTR_CTL_ENABLE 0x00000001 422 423 #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0 0x00000081 424 425 #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD1 0x00000082 426 427 #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000084 428 429 #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000085 430 431 #define REG_A3XX_RBBM_PERFCOUNTER0_SELECT 0x00000086 432 433 #define REG_A3XX_RBBM_PERFCOUNTER1_SELECT 0x00000087 434 435 #define REG_A3XX_RBBM_GPU_BUSY_MASKED 0x00000088 436 437 #define REG_A3XX_RBBM_PERFCTR_CP_0_LO 0x00000090 438 439 #define REG_A3XX_RBBM_PERFCTR_CP_0_HI 0x00000091 440 441 #define REG_A3XX_RBBM_PERFCTR_RBBM_0_LO 0x00000092 442 443 #define REG_A3XX_RBBM_PERFCTR_RBBM_0_HI 0x00000093 444 445 #define REG_A3XX_RBBM_PERFCTR_RBBM_1_LO 0x00000094 446 447 #define REG_A3XX_RBBM_PERFCTR_RBBM_1_HI 0x00000095 448 449 #define REG_A3XX_RBBM_PERFCTR_PC_0_LO 0x00000096 450 451 #define REG_A3XX_RBBM_PERFCTR_PC_0_HI 0x00000097 452 453 #define REG_A3XX_RBBM_PERFCTR_PC_1_LO 0x00000098 454 455 #define REG_A3XX_RBBM_PERFCTR_PC_1_HI 0x00000099 456 457 #define REG_A3XX_RBBM_PERFCTR_PC_2_LO 0x0000009a 458 459 #define REG_A3XX_RBBM_PERFCTR_PC_2_HI 0x0000009b 460 461 #define REG_A3XX_RBBM_PERFCTR_PC_3_LO 0x0000009c 462 463 #define REG_A3XX_RBBM_PERFCTR_PC_3_HI 0x0000009d 464 465 #define REG_A3XX_RBBM_PERFCTR_VFD_0_LO 0x0000009e 466 467 #define REG_A3XX_RBBM_PERFCTR_VFD_0_HI 0x0000009f 468 469 #define REG_A3XX_RBBM_PERFCTR_VFD_1_LO 0x000000a0 470 471 #define REG_A3XX_RBBM_PERFCTR_VFD_1_HI 0x000000a1 472 473 #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000a2 474 475 #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000a3 476 477 #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000a4 478 479 #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000a5 480 481 #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000a6 482 483 #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000a7 484 485 #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000a8 486 487 #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000a9 488 489 #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000aa 490 491 #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000ab 492 493 #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000ac 494 495 #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000ad 496 497 #define REG_A3XX_RBBM_PERFCTR_VPC_0_LO 0x000000ae 498 499 #define REG_A3XX_RBBM_PERFCTR_VPC_0_HI 0x000000af 500 501 #define REG_A3XX_RBBM_PERFCTR_VPC_1_LO 0x000000b0 502 503 #define REG_A3XX_RBBM_PERFCTR_VPC_1_HI 0x000000b1 504 505 #define REG_A3XX_RBBM_PERFCTR_TSE_0_LO 0x000000b2 506 507 #define REG_A3XX_RBBM_PERFCTR_TSE_0_HI 0x000000b3 508 509 #define REG_A3XX_RBBM_PERFCTR_TSE_1_LO 0x000000b4 510 511 #define REG_A3XX_RBBM_PERFCTR_TSE_1_HI 0x000000b5 512 513 #define REG_A3XX_RBBM_PERFCTR_RAS_0_LO 0x000000b6 514 515 #define REG_A3XX_RBBM_PERFCTR_RAS_0_HI 0x000000b7 516 517 #define REG_A3XX_RBBM_PERFCTR_RAS_1_LO 0x000000b8 518 519 #define REG_A3XX_RBBM_PERFCTR_RAS_1_HI 0x000000b9 520 521 #define REG_A3XX_RBBM_PERFCTR_UCHE_0_LO 0x000000ba 522 523 #define REG_A3XX_RBBM_PERFCTR_UCHE_0_HI 0x000000bb 524 525 #define REG_A3XX_RBBM_PERFCTR_UCHE_1_LO 0x000000bc 526 527 #define REG_A3XX_RBBM_PERFCTR_UCHE_1_HI 0x000000bd 528 529 #define REG_A3XX_RBBM_PERFCTR_UCHE_2_LO 0x000000be 530 531 #define REG_A3XX_RBBM_PERFCTR_UCHE_2_HI 0x000000bf 532 533 #define REG_A3XX_RBBM_PERFCTR_UCHE_3_LO 0x000000c0 534 535 #define REG_A3XX_RBBM_PERFCTR_UCHE_3_HI 0x000000c1 536 537 #define REG_A3XX_RBBM_PERFCTR_UCHE_4_LO 0x000000c2 538 539 #define REG_A3XX_RBBM_PERFCTR_UCHE_4_HI 0x000000c3 540 541 #define REG_A3XX_RBBM_PERFCTR_UCHE_5_LO 0x000000c4 542 543 #define REG_A3XX_RBBM_PERFCTR_UCHE_5_HI 0x000000c5 544 545 #define REG_A3XX_RBBM_PERFCTR_TP_0_LO 0x000000c6 546 547 #define REG_A3XX_RBBM_PERFCTR_TP_0_HI 0x000000c7 548 549 #define REG_A3XX_RBBM_PERFCTR_TP_1_LO 0x000000c8 550 551 #define REG_A3XX_RBBM_PERFCTR_TP_1_HI 0x000000c9 552 553 #define REG_A3XX_RBBM_PERFCTR_TP_2_LO 0x000000ca 554 555 #define REG_A3XX_RBBM_PERFCTR_TP_2_HI 0x000000cb 556 557 #define REG_A3XX_RBBM_PERFCTR_TP_3_LO 0x000000cc 558 559 #define REG_A3XX_RBBM_PERFCTR_TP_3_HI 0x000000cd 560 561 #define REG_A3XX_RBBM_PERFCTR_TP_4_LO 0x000000ce 562 563 #define REG_A3XX_RBBM_PERFCTR_TP_4_HI 0x000000cf 564 565 #define REG_A3XX_RBBM_PERFCTR_TP_5_LO 0x000000d0 566 567 #define REG_A3XX_RBBM_PERFCTR_TP_5_HI 0x000000d1 568 569 #define REG_A3XX_RBBM_PERFCTR_SP_0_LO 0x000000d2 570 571 #define REG_A3XX_RBBM_PERFCTR_SP_0_HI 0x000000d3 572 573 #define REG_A3XX_RBBM_PERFCTR_SP_1_LO 0x000000d4 574 575 #define REG_A3XX_RBBM_PERFCTR_SP_1_HI 0x000000d5 576 577 #define REG_A3XX_RBBM_PERFCTR_SP_2_LO 0x000000d6 578 579 #define REG_A3XX_RBBM_PERFCTR_SP_2_HI 0x000000d7 580 581 #define REG_A3XX_RBBM_PERFCTR_SP_3_LO 0x000000d8 582 583 #define REG_A3XX_RBBM_PERFCTR_SP_3_HI 0x000000d9 584 585 #define REG_A3XX_RBBM_PERFCTR_SP_4_LO 0x000000da 586 587 #define REG_A3XX_RBBM_PERFCTR_SP_4_HI 0x000000db 588 589 #define REG_A3XX_RBBM_PERFCTR_SP_5_LO 0x000000dc 590 591 #define REG_A3XX_RBBM_PERFCTR_SP_5_HI 0x000000dd 592 593 #define REG_A3XX_RBBM_PERFCTR_SP_6_LO 0x000000de 594 595 #define REG_A3XX_RBBM_PERFCTR_SP_6_HI 0x000000df 596 597 #define REG_A3XX_RBBM_PERFCTR_SP_7_LO 0x000000e0 598 599 #define REG_A3XX_RBBM_PERFCTR_SP_7_HI 0x000000e1 600 601 #define REG_A3XX_RBBM_PERFCTR_RB_0_LO 0x000000e2 602 603 #define REG_A3XX_RBBM_PERFCTR_RB_0_HI 0x000000e3 604 605 #define REG_A3XX_RBBM_PERFCTR_RB_1_LO 0x000000e4 606 607 #define REG_A3XX_RBBM_PERFCTR_RB_1_HI 0x000000e5 608 609 #define REG_A3XX_RBBM_PERFCTR_PWR_0_LO 0x000000ea 610 611 #define REG_A3XX_RBBM_PERFCTR_PWR_0_HI 0x000000eb 612 613 #define REG_A3XX_RBBM_PERFCTR_PWR_1_LO 0x000000ec 614 615 #define REG_A3XX_RBBM_PERFCTR_PWR_1_HI 0x000000ed 616 617 #define REG_A3XX_RBBM_RBBM_CTL 0x00000100 618 619 #define REG_A3XX_RBBM_DEBUG_BUS_CTL 0x00000111 620 621 #define REG_A3XX_RBBM_DEBUG_BUS_DATA_STATUS 0x00000112 622 623 #define REG_A3XX_CP_PFP_UCODE_ADDR 0x000001c9 624 625 #define REG_A3XX_CP_PFP_UCODE_DATA 0x000001ca 626 627 #define REG_A3XX_CP_ROQ_ADDR 0x000001cc 628 629 #define REG_A3XX_CP_ROQ_DATA 0x000001cd 630 631 #define REG_A3XX_CP_MERCIU_ADDR 0x000001d1 632 633 #define REG_A3XX_CP_MERCIU_DATA 0x000001d2 634 635 #define REG_A3XX_CP_MERCIU_DATA2 0x000001d3 636 637 #define REG_A3XX_CP_MEQ_ADDR 0x000001da 638 639 #define REG_A3XX_CP_MEQ_DATA 0x000001db 640 641 #define REG_A3XX_CP_WFI_PEND_CTR 0x000001f5 642 643 #define REG_A3XX_RBBM_PM_OVERRIDE2 0x0000039d 644 645 #define REG_A3XX_CP_PERFCOUNTER_SELECT 0x00000445 646 647 #define REG_A3XX_CP_HW_FAULT 0x0000045c 648 649 #define REG_A3XX_CP_PROTECT_CTRL 0x0000045e 650 651 #define REG_A3XX_CP_PROTECT_STATUS 0x0000045f 652 653 static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; } 654 655 static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; } 656 657 #define REG_A3XX_CP_AHB_FAULT 0x0000054d 658 659 #define REG_A3XX_SQ_GPR_MANAGEMENT 0x00000d00 660 661 #define REG_A3XX_SQ_INST_STORE_MANAGMENT 0x00000d02 662 663 #define REG_A3XX_TP0_CHICKEN 0x00000e1e 664 665 #define REG_A3XX_SP_GLOBAL_MEM_SIZE 0x00000e22 666 667 #define REG_A3XX_SP_GLOBAL_MEM_ADDR 0x00000e23 668 669 #define REG_A3XX_GRAS_CL_CLIP_CNTL 0x00002040 670 #define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER 0x00001000 671 #define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 672 #define A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000 673 #define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE 0x00080000 674 #define A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE 0x00100000 675 #define A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE 0x00200000 676 #define A3XX_GRAS_CL_CLIP_CNTL_ZCOORD 0x00800000 677 #define A3XX_GRAS_CL_CLIP_CNTL_WCOORD 0x01000000 678 #define A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE 0x02000000 679 680 #define REG_A3XX_GRAS_CL_GB_CLIP_ADJ 0x00002044 681 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff 682 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0 683 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) 684 { 685 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; 686 } 687 #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00 688 #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10 689 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) 690 { 691 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; 692 } 693 694 #define REG_A3XX_GRAS_CL_VPORT_XOFFSET 0x00002048 695 #define A3XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff 696 #define A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0 697 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) 698 { 699 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK; 700 } 701 702 #define REG_A3XX_GRAS_CL_VPORT_XSCALE 0x00002049 703 #define A3XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff 704 #define A3XX_GRAS_CL_VPORT_XSCALE__SHIFT 0 705 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) 706 { 707 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK; 708 } 709 710 #define REG_A3XX_GRAS_CL_VPORT_YOFFSET 0x0000204a 711 #define A3XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff 712 #define A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0 713 static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val) 714 { 715 return ((fui(val)) << A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_YOFFSET__MASK; 716 } 717 718 #define REG_A3XX_GRAS_CL_VPORT_YSCALE 0x0000204b 719 #define A3XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff 720 #define A3XX_GRAS_CL_VPORT_YSCALE__SHIFT 0 721 static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val) 722 { 723 return ((fui(val)) << A3XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_YSCALE__MASK; 724 } 725 726 #define REG_A3XX_GRAS_CL_VPORT_ZOFFSET 0x0000204c 727 #define A3XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff 728 #define A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0 729 static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val) 730 { 731 return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_ZOFFSET__MASK; 732 } 733 734 #define REG_A3XX_GRAS_CL_VPORT_ZSCALE 0x0000204d 735 #define A3XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff 736 #define A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0 737 static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val) 738 { 739 return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_ZSCALE__MASK; 740 } 741 742 #define REG_A3XX_GRAS_SU_POINT_MINMAX 0x00002068 743 #define A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 744 #define A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 745 static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MIN(float val) 746 { 747 return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 748 } 749 #define A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 750 #define A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 751 static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MAX(float val) 752 { 753 return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 754 } 755 756 #define REG_A3XX_GRAS_SU_POINT_SIZE 0x00002069 757 #define A3XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff 758 #define A3XX_GRAS_SU_POINT_SIZE__SHIFT 0 759 static inline uint32_t A3XX_GRAS_SU_POINT_SIZE(float val) 760 { 761 return ((((int32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_SIZE__SHIFT) & A3XX_GRAS_SU_POINT_SIZE__MASK; 762 } 763 764 #define REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000206c 765 #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK 0x00ffffff 766 #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT 0 767 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val) 768 { 769 return ((((int32_t)(val * 16384.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK; 770 } 771 772 #define REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000206d 773 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 774 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 775 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 776 { 777 return ((((int32_t)(val * 64.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 778 } 779 780 #define REG_A3XX_GRAS_SU_MODE_CONTROL 0x00002070 781 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001 782 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002 783 #define A3XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004 784 #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8 785 #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3 786 static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) 787 { 788 return ((((int32_t)(val * 4.0))) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; 789 } 790 #define A3XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800 791 792 #define REG_A3XX_GRAS_SC_CONTROL 0x00002072 793 #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x000000f0 794 #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 4 795 static inline uint32_t A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) 796 { 797 return ((val) << A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK; 798 } 799 #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000f00 800 #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 8 801 static inline uint32_t A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val) 802 { 803 return ((val) << A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK; 804 } 805 #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000 806 #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12 807 static inline uint32_t A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) 808 { 809 return ((val) << A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK; 810 } 811 812 #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL 0x00002074 813 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 814 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 815 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 816 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 817 { 818 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; 819 } 820 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 821 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 822 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 823 { 824 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; 825 } 826 827 #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_BR 0x00002075 828 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 829 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 830 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 831 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 832 { 833 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; 834 } 835 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 836 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 837 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 838 { 839 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; 840 } 841 842 #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL 0x00002079 843 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 844 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 845 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 846 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 847 { 848 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 849 } 850 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 851 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 852 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 853 { 854 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 855 } 856 857 #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000207a 858 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 859 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 860 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 861 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 862 { 863 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 864 } 865 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 866 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 867 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 868 { 869 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 870 } 871 872 #define REG_A3XX_RB_MODE_CONTROL 0x000020c0 873 #define A3XX_RB_MODE_CONTROL_GMEM_BYPASS 0x00000080 874 #define A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK 0x00000700 875 #define A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT 8 876 static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val) 877 { 878 return ((val) << A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT) & A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK; 879 } 880 #define A3XX_RB_MODE_CONTROL_MRT__MASK 0x00003000 881 #define A3XX_RB_MODE_CONTROL_MRT__SHIFT 12 882 static inline uint32_t A3XX_RB_MODE_CONTROL_MRT(uint32_t val) 883 { 884 return ((val) << A3XX_RB_MODE_CONTROL_MRT__SHIFT) & A3XX_RB_MODE_CONTROL_MRT__MASK; 885 } 886 #define A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE 0x00008000 887 #define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE 0x00010000 888 889 #define REG_A3XX_RB_RENDER_CONTROL 0x000020c1 890 #define A3XX_RB_RENDER_CONTROL_FACENESS 0x00000008 891 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK 0x00000ff0 892 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT 4 893 static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val) 894 { 895 return ((val >> 5) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK; 896 } 897 #define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00001000 898 #define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM 0x00002000 899 #define A3XX_RB_RENDER_CONTROL_XCOORD 0x00004000 900 #define A3XX_RB_RENDER_CONTROL_YCOORD 0x00008000 901 #define A3XX_RB_RENDER_CONTROL_ZCOORD 0x00010000 902 #define A3XX_RB_RENDER_CONTROL_WCOORD 0x00020000 903 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST 0x00400000 904 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK 0x07000000 905 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT 24 906 static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 907 { 908 return ((val) << A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK; 909 } 910 911 #define REG_A3XX_RB_MSAA_CONTROL 0x000020c2 912 #define A3XX_RB_MSAA_CONTROL_DISABLE 0x00000400 913 #define A3XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000f000 914 #define A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 12 915 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val) 916 { 917 return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLES__MASK; 918 } 919 #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK 0xffff0000 920 #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT 16 921 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val) 922 { 923 return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK; 924 } 925 926 #define REG_A3XX_RB_ALPHA_REF 0x000020c3 927 #define A3XX_RB_ALPHA_REF_UINT__MASK 0x0000ff00 928 #define A3XX_RB_ALPHA_REF_UINT__SHIFT 8 929 static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val) 930 { 931 return ((val) << A3XX_RB_ALPHA_REF_UINT__SHIFT) & A3XX_RB_ALPHA_REF_UINT__MASK; 932 } 933 #define A3XX_RB_ALPHA_REF_FLOAT__MASK 0xffff0000 934 #define A3XX_RB_ALPHA_REF_FLOAT__SHIFT 16 935 static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val) 936 { 937 return ((util_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK; 938 } 939 940 static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; } 941 942 static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; } 943 #define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008 944 #define A3XX_RB_MRT_CONTROL_BLEND 0x00000010 945 #define A3XX_RB_MRT_CONTROL_BLEND2 0x00000020 946 #define A3XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00 947 #define A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8 948 static inline uint32_t A3XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) 949 { 950 return ((val) << A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A3XX_RB_MRT_CONTROL_ROP_CODE__MASK; 951 } 952 #define A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK 0x00003000 953 #define A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT 12 954 static inline uint32_t A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) 955 { 956 return ((val) << A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT) & A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK; 957 } 958 #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000 959 #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24 960 static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 961 { 962 return ((val) << A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 963 } 964 965 static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; } 966 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f 967 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 968 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val) 969 { 970 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 971 } 972 #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0 973 #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6 974 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val) 975 { 976 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 977 } 978 #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00000c00 979 #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 10 980 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 981 { 982 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 983 } 984 #define A3XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00004000 985 #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xfffe0000 986 #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 17 987 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) 988 { 989 return ((val >> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; 990 } 991 992 static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; } 993 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK 0xfffffff0 994 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT 4 995 static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val) 996 { 997 return ((val >> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK; 998 } 999 1000 static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; } 1001 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 1002 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 1003 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 1004 { 1005 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 1006 } 1007 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 1008 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 1009 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 1010 { 1011 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 1012 } 1013 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 1014 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 1015 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 1016 { 1017 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 1018 } 1019 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 1020 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 1021 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 1022 { 1023 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 1024 } 1025 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 1026 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 1027 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 1028 { 1029 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 1030 } 1031 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 1032 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 1033 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 1034 { 1035 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 1036 } 1037 #define A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE 0x20000000 1038 1039 #define REG_A3XX_RB_BLEND_RED 0x000020e4 1040 #define A3XX_RB_BLEND_RED_UINT__MASK 0x000000ff 1041 #define A3XX_RB_BLEND_RED_UINT__SHIFT 0 1042 static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val) 1043 { 1044 return ((val) << A3XX_RB_BLEND_RED_UINT__SHIFT) & A3XX_RB_BLEND_RED_UINT__MASK; 1045 } 1046 #define A3XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 1047 #define A3XX_RB_BLEND_RED_FLOAT__SHIFT 16 1048 static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val) 1049 { 1050 return ((util_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK; 1051 } 1052 1053 #define REG_A3XX_RB_BLEND_GREEN 0x000020e5 1054 #define A3XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff 1055 #define A3XX_RB_BLEND_GREEN_UINT__SHIFT 0 1056 static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val) 1057 { 1058 return ((val) << A3XX_RB_BLEND_GREEN_UINT__SHIFT) & A3XX_RB_BLEND_GREEN_UINT__MASK; 1059 } 1060 #define A3XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 1061 #define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 1062 static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val) 1063 { 1064 return ((util_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK; 1065 } 1066 1067 #define REG_A3XX_RB_BLEND_BLUE 0x000020e6 1068 #define A3XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff 1069 #define A3XX_RB_BLEND_BLUE_UINT__SHIFT 0 1070 static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val) 1071 { 1072 return ((val) << A3XX_RB_BLEND_BLUE_UINT__SHIFT) & A3XX_RB_BLEND_BLUE_UINT__MASK; 1073 } 1074 #define A3XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 1075 #define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 1076 static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val) 1077 { 1078 return ((util_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK; 1079 } 1080 1081 #define REG_A3XX_RB_BLEND_ALPHA 0x000020e7 1082 #define A3XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff 1083 #define A3XX_RB_BLEND_ALPHA_UINT__SHIFT 0 1084 static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val) 1085 { 1086 return ((val) << A3XX_RB_BLEND_ALPHA_UINT__SHIFT) & A3XX_RB_BLEND_ALPHA_UINT__MASK; 1087 } 1088 #define A3XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 1089 #define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 1090 static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val) 1091 { 1092 return ((util_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK; 1093 } 1094 1095 #define REG_A3XX_RB_CLEAR_COLOR_DW0 0x000020e8 1096 1097 #define REG_A3XX_RB_CLEAR_COLOR_DW1 0x000020e9 1098 1099 #define REG_A3XX_RB_CLEAR_COLOR_DW2 0x000020ea 1100 1101 #define REG_A3XX_RB_CLEAR_COLOR_DW3 0x000020eb 1102 1103 #define REG_A3XX_RB_COPY_CONTROL 0x000020ec 1104 #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003 1105 #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0 1106 static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) 1107 { 1108 return ((val) << A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK; 1109 } 1110 #define A3XX_RB_COPY_CONTROL_DEPTHCLEAR 0x00000008 1111 #define A3XX_RB_COPY_CONTROL_MODE__MASK 0x00000070 1112 #define A3XX_RB_COPY_CONTROL_MODE__SHIFT 4 1113 static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) 1114 { 1115 return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK; 1116 } 1117 #define A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00 1118 #define A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8 1119 static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) 1120 { 1121 return ((val) << A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK; 1122 } 1123 #define A3XX_RB_COPY_CONTROL_UNK12 0x00001000 1124 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000 1125 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14 1126 static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) 1127 { 1128 return ((val >> 14) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK; 1129 } 1130 1131 #define REG_A3XX_RB_COPY_DEST_BASE 0x000020ed 1132 #define A3XX_RB_COPY_DEST_BASE_BASE__MASK 0xfffffff0 1133 #define A3XX_RB_COPY_DEST_BASE_BASE__SHIFT 4 1134 static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val) 1135 { 1136 return ((val >> 5) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A3XX_RB_COPY_DEST_BASE_BASE__MASK; 1137 } 1138 1139 #define REG_A3XX_RB_COPY_DEST_PITCH 0x000020ee 1140 #define A3XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff 1141 #define A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0 1142 static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) 1143 { 1144 return ((val >> 5) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK; 1145 } 1146 1147 #define REG_A3XX_RB_COPY_DEST_INFO 0x000020ef 1148 #define A3XX_RB_COPY_DEST_INFO_TILE__MASK 0x00000003 1149 #define A3XX_RB_COPY_DEST_INFO_TILE__SHIFT 0 1150 static inline uint32_t A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val) 1151 { 1152 return ((val) << A3XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A3XX_RB_COPY_DEST_INFO_TILE__MASK; 1153 } 1154 #define A3XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc 1155 #define A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2 1156 static inline uint32_t A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val) 1157 { 1158 return ((val) << A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A3XX_RB_COPY_DEST_INFO_FORMAT__MASK; 1159 } 1160 #define A3XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 1161 #define A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 1162 static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) 1163 { 1164 return ((val) << A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A3XX_RB_COPY_DEST_INFO_SWAP__MASK; 1165 } 1166 #define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 1167 #define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 1168 static inline uint32_t A3XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 1169 { 1170 return ((val) << A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 1171 } 1172 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000 1173 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14 1174 static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) 1175 { 1176 return ((val) << A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK; 1177 } 1178 #define A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000 1179 #define A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18 1180 static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) 1181 { 1182 return ((val) << A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK; 1183 } 1184 1185 #define REG_A3XX_RB_DEPTH_CONTROL 0x00002100 1186 #define A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001 1187 #define A3XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002 1188 #define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004 1189 #define A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00000008 1190 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070 1191 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4 1192 static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) 1193 { 1194 return ((val) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK; 1195 } 1196 #define A3XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080 1197 #define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000 1198 1199 #define REG_A3XX_RB_DEPTH_CLEAR 0x00002101 1200 1201 #define REG_A3XX_RB_DEPTH_INFO 0x00002102 1202 #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003 1203 #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 1204 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) 1205 { 1206 return ((val) << A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 1207 } 1208 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff800 1209 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 11 1210 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 1211 { 1212 return ((val >> 12) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 1213 } 1214 1215 #define REG_A3XX_RB_DEPTH_PITCH 0x00002103 1216 #define A3XX_RB_DEPTH_PITCH__MASK 0xffffffff 1217 #define A3XX_RB_DEPTH_PITCH__SHIFT 0 1218 static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val) 1219 { 1220 return ((val >> 3) << A3XX_RB_DEPTH_PITCH__SHIFT) & A3XX_RB_DEPTH_PITCH__MASK; 1221 } 1222 1223 #define REG_A3XX_RB_STENCIL_CONTROL 0x00002104 1224 #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 1225 #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 1226 #define A3XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 1227 #define A3XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 1228 #define A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 1229 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 1230 { 1231 return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC__MASK; 1232 } 1233 #define A3XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 1234 #define A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 1235 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 1236 { 1237 return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL__MASK; 1238 } 1239 #define A3XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 1240 #define A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 1241 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 1242 { 1243 return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS__MASK; 1244 } 1245 #define A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 1246 #define A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 1247 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 1248 { 1249 return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 1250 } 1251 #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 1252 #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 1253 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 1254 { 1255 return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 1256 } 1257 #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 1258 #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 1259 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 1260 { 1261 return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 1262 } 1263 #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 1264 #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 1265 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 1266 { 1267 return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 1268 } 1269 #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 1270 #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 1271 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 1272 { 1273 return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 1274 } 1275 1276 #define REG_A3XX_RB_STENCIL_CLEAR 0x00002105 1277 1278 #define REG_A3XX_RB_STENCIL_INFO 0x00002106 1279 #define A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff800 1280 #define A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 11 1281 static inline uint32_t A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) 1282 { 1283 return ((val >> 12) << A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK; 1284 } 1285 1286 #define REG_A3XX_RB_STENCIL_PITCH 0x00002107 1287 #define A3XX_RB_STENCIL_PITCH__MASK 0xffffffff 1288 #define A3XX_RB_STENCIL_PITCH__SHIFT 0 1289 static inline uint32_t A3XX_RB_STENCIL_PITCH(uint32_t val) 1290 { 1291 return ((val >> 3) << A3XX_RB_STENCIL_PITCH__SHIFT) & A3XX_RB_STENCIL_PITCH__MASK; 1292 } 1293 1294 #define REG_A3XX_RB_STENCILREFMASK 0x00002108 1295 #define A3XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 1296 #define A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 1297 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 1298 { 1299 return ((val) << A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILREF__MASK; 1300 } 1301 #define A3XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 1302 #define A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 1303 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 1304 { 1305 return ((val) << A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILMASK__MASK; 1306 } 1307 #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 1308 #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 1309 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 1310 { 1311 return ((val) << A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 1312 } 1313 1314 #define REG_A3XX_RB_STENCILREFMASK_BF 0x00002109 1315 #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 1316 #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 1317 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 1318 { 1319 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 1320 } 1321 #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 1322 #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 1323 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 1324 { 1325 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 1326 } 1327 #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 1328 #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 1329 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 1330 { 1331 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 1332 } 1333 1334 #define REG_A3XX_RB_LRZ_VSC_CONTROL 0x0000210c 1335 #define A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE 0x00000002 1336 1337 #define REG_A3XX_RB_WINDOW_OFFSET 0x0000210e 1338 #define A3XX_RB_WINDOW_OFFSET_X__MASK 0x0000ffff 1339 #define A3XX_RB_WINDOW_OFFSET_X__SHIFT 0 1340 static inline uint32_t A3XX_RB_WINDOW_OFFSET_X(uint32_t val) 1341 { 1342 return ((val) << A3XX_RB_WINDOW_OFFSET_X__SHIFT) & A3XX_RB_WINDOW_OFFSET_X__MASK; 1343 } 1344 #define A3XX_RB_WINDOW_OFFSET_Y__MASK 0xffff0000 1345 #define A3XX_RB_WINDOW_OFFSET_Y__SHIFT 16 1346 static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val) 1347 { 1348 return ((val) << A3XX_RB_WINDOW_OFFSET_Y__SHIFT) & A3XX_RB_WINDOW_OFFSET_Y__MASK; 1349 } 1350 1351 #define REG_A3XX_RB_SAMPLE_COUNT_CONTROL 0x00002110 1352 #define A3XX_RB_SAMPLE_COUNT_CONTROL_RESET 0x00000001 1353 #define A3XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 1354 1355 #define REG_A3XX_RB_SAMPLE_COUNT_ADDR 0x00002111 1356 1357 #define REG_A3XX_RB_Z_CLAMP_MIN 0x00002114 1358 1359 #define REG_A3XX_RB_Z_CLAMP_MAX 0x00002115 1360 1361 #define REG_A3XX_VGT_BIN_BASE 0x000021e1 1362 1363 #define REG_A3XX_VGT_BIN_SIZE 0x000021e2 1364 1365 #define REG_A3XX_PC_VSTREAM_CONTROL 0x000021e4 1366 #define A3XX_PC_VSTREAM_CONTROL_SIZE__MASK 0x003f0000 1367 #define A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT 16 1368 static inline uint32_t A3XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val) 1369 { 1370 return ((val) << A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A3XX_PC_VSTREAM_CONTROL_SIZE__MASK; 1371 } 1372 #define A3XX_PC_VSTREAM_CONTROL_N__MASK 0x07c00000 1373 #define A3XX_PC_VSTREAM_CONTROL_N__SHIFT 22 1374 static inline uint32_t A3XX_PC_VSTREAM_CONTROL_N(uint32_t val) 1375 { 1376 return ((val) << A3XX_PC_VSTREAM_CONTROL_N__SHIFT) & A3XX_PC_VSTREAM_CONTROL_N__MASK; 1377 } 1378 1379 #define REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL 0x000021ea 1380 1381 #define REG_A3XX_PC_PRIM_VTX_CNTL 0x000021ec 1382 #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK 0x0000001f 1383 #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT 0 1384 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val) 1385 { 1386 return ((val) << A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK; 1387 } 1388 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK 0x000000e0 1389 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT 5 1390 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 1391 { 1392 return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK; 1393 } 1394 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK 0x00000700 1395 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT 8 1396 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 1397 { 1398 return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK; 1399 } 1400 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_ENABLE 0x00001000 1401 #define A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000 1402 #define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000 1403 #define A3XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000 1404 1405 #define REG_A3XX_PC_RESTART_INDEX 0x000021ed 1406 1407 #define REG_A3XX_HLSQ_CONTROL_0_REG 0x00002200 1408 #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010 1409 #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4 1410 static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) 1411 { 1412 return ((val) << A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; 1413 } 1414 #define A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040 1415 #define A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200 1416 #define A3XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400 1417 #define A3XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000 1418 #define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000 1419 #define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27 1420 static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) 1421 { 1422 return ((val) << A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK; 1423 } 1424 #define A3XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000 1425 #define A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000 1426 #define A3XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000 1427 #define A3XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000 1428 1429 #define REG_A3XX_HLSQ_CONTROL_1_REG 0x00002201 1430 #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040 1431 #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6 1432 static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) 1433 { 1434 return ((val) << A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK; 1435 } 1436 #define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100 1437 #define A3XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200 1438 #define A3XX_HLSQ_CONTROL_1_REG_ZWCOORD 0x02000000 1439 1440 #define REG_A3XX_HLSQ_CONTROL_2_REG 0x00002202 1441 #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000 1442 #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26 1443 static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) 1444 { 1445 return ((val) << A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK; 1446 } 1447 1448 #define REG_A3XX_HLSQ_CONTROL_3_REG 0x00002203 1449 #define A3XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff 1450 #define A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0 1451 static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val) 1452 { 1453 return ((val) << A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_REGID__MASK; 1454 } 1455 1456 #define REG_A3XX_HLSQ_VS_CONTROL_REG 0x00002204 1457 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff 1458 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0 1459 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) 1460 { 1461 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK; 1462 } 1463 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000 1464 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12 1465 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) 1466 { 1467 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK; 1468 } 1469 #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 1470 #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24 1471 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) 1472 { 1473 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK; 1474 } 1475 1476 #define REG_A3XX_HLSQ_FS_CONTROL_REG 0x00002205 1477 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff 1478 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0 1479 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) 1480 { 1481 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK; 1482 } 1483 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000 1484 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12 1485 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) 1486 { 1487 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK; 1488 } 1489 #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 1490 #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24 1491 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) 1492 { 1493 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK; 1494 } 1495 1496 #define REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG 0x00002206 1497 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff 1498 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT 0 1499 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val) 1500 { 1501 return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK; 1502 } 1503 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000 1504 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT 16 1505 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val) 1506 { 1507 return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK; 1508 } 1509 1510 #define REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG 0x00002207 1511 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff 1512 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT 0 1513 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val) 1514 { 1515 return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK; 1516 } 1517 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000 1518 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT 16 1519 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val) 1520 { 1521 return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK; 1522 } 1523 1524 #define REG_A3XX_HLSQ_CL_NDRANGE_0_REG 0x0000220a 1525 #define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK 0x00000003 1526 #define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT 0 1527 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM(uint32_t val) 1528 { 1529 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK; 1530 } 1531 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK 0x00000ffc 1532 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT 2 1533 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0(uint32_t val) 1534 { 1535 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK; 1536 } 1537 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK 0x003ff000 1538 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT 12 1539 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1(uint32_t val) 1540 { 1541 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK; 1542 } 1543 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK 0xffc00000 1544 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT 22 1545 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2(uint32_t val) 1546 { 1547 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK; 1548 } 1549 1550 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK(uint32_t i0) { return 0x0000220b + 0x2*i0; } 1551 1552 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0; } 1553 1554 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { return 0x0000220c + 0x2*i0; } 1555 1556 #define REG_A3XX_HLSQ_CL_CONTROL_0_REG 0x00002211 1557 1558 #define REG_A3XX_HLSQ_CL_CONTROL_1_REG 0x00002212 1559 1560 #define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG 0x00002214 1561 1562 static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP(uint32_t i0) { return 0x00002215 + 0x1*i0; } 1563 1564 static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO(uint32_t i0) { return 0x00002215 + 0x1*i0; } 1565 1566 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Y_REG 0x00002216 1567 1568 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG 0x00002217 1569 1570 #define REG_A3XX_HLSQ_CL_WG_OFFSET_REG 0x0000221a 1571 1572 #define REG_A3XX_VFD_CONTROL_0 0x00002240 1573 #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x0003ffff 1574 #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0 1575 static inline uint32_t A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) 1576 { 1577 return ((val) << A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK; 1578 } 1579 #define A3XX_VFD_CONTROL_0_PACKETSIZE__MASK 0x003c0000 1580 #define A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT 18 1581 static inline uint32_t A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val) 1582 { 1583 return ((val) << A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT) & A3XX_VFD_CONTROL_0_PACKETSIZE__MASK; 1584 } 1585 #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x07c00000 1586 #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 22 1587 static inline uint32_t A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) 1588 { 1589 return ((val) << A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK; 1590 } 1591 #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xf8000000 1592 #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 27 1593 static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) 1594 { 1595 return ((val) << A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK; 1596 } 1597 1598 #define REG_A3XX_VFD_CONTROL_1 0x00002241 1599 #define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff 1600 #define A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0 1601 static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) 1602 { 1603 return ((val) << A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK; 1604 } 1605 #define A3XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000 1606 #define A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16 1607 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 1608 { 1609 return ((val) << A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A3XX_VFD_CONTROL_1_REGID4VTX__MASK; 1610 } 1611 #define A3XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000 1612 #define A3XX_VFD_CONTROL_1_REGID4INST__SHIFT 24 1613 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 1614 { 1615 return ((val) << A3XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A3XX_VFD_CONTROL_1_REGID4INST__MASK; 1616 } 1617 1618 #define REG_A3XX_VFD_INDEX_MIN 0x00002242 1619 1620 #define REG_A3XX_VFD_INDEX_MAX 0x00002243 1621 1622 #define REG_A3XX_VFD_INSTANCEID_OFFSET 0x00002244 1623 1624 #define REG_A3XX_VFD_INDEX_OFFSET 0x00002245 1625 1626 #define REG_A3XX_VFD_INDEX_OFFSET 0x00002245 1627 1628 static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0) { return 0x00002246 + 0x2*i0; } 1629 1630 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; } 1631 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f 1632 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0 1633 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) 1634 { 1635 return ((val) << A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK; 1636 } 1637 #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0000ff80 1638 #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7 1639 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) 1640 { 1641 return ((val) << A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK; 1642 } 1643 #define A3XX_VFD_FETCH_INSTR_0_INSTANCED 0x00010000 1644 #define A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00020000 1645 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK 0x00fc0000 1646 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT 18 1647 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val) 1648 { 1649 return ((val) << A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK; 1650 } 1651 #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK 0xff000000 1652 #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT 24 1653 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val) 1654 { 1655 return ((val) << A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK; 1656 } 1657 1658 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x00002247 + 0x2*i0; } 1659 1660 static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0) { return 0x00002266 + 0x1*i0; } 1661 1662 static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x00002266 + 0x1*i0; } 1663 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f 1664 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0 1665 static inline uint32_t A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) 1666 { 1667 return ((val) << A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK; 1668 } 1669 #define A3XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010 1670 #define A3XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0 1671 #define A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6 1672 static inline uint32_t A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val) 1673 { 1674 return ((val) << A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A3XX_VFD_DECODE_INSTR_FORMAT__MASK; 1675 } 1676 #define A3XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000 1677 #define A3XX_VFD_DECODE_INSTR_REGID__SHIFT 12 1678 static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val) 1679 { 1680 return ((val) << A3XX_VFD_DECODE_INSTR_REGID__SHIFT) & A3XX_VFD_DECODE_INSTR_REGID__MASK; 1681 } 1682 #define A3XX_VFD_DECODE_INSTR_INT 0x00100000 1683 #define A3XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000 1684 #define A3XX_VFD_DECODE_INSTR_SWAP__SHIFT 22 1685 static inline uint32_t A3XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 1686 { 1687 return ((val) << A3XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A3XX_VFD_DECODE_INSTR_SWAP__MASK; 1688 } 1689 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000 1690 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24 1691 static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) 1692 { 1693 return ((val) << A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK; 1694 } 1695 #define A3XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000 1696 #define A3XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000 1697 1698 #define REG_A3XX_VFD_VS_THREADING_THRESHOLD 0x0000227e 1699 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK 0x0000000f 1700 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT 0 1701 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val) 1702 { 1703 return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK; 1704 } 1705 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK 0x0000ff00 1706 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT 8 1707 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val) 1708 { 1709 return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK; 1710 } 1711 1712 #define REG_A3XX_VPC_ATTR 0x00002280 1713 #define A3XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff 1714 #define A3XX_VPC_ATTR_TOTALATTR__SHIFT 0 1715 static inline uint32_t A3XX_VPC_ATTR_TOTALATTR(uint32_t val) 1716 { 1717 return ((val) << A3XX_VPC_ATTR_TOTALATTR__SHIFT) & A3XX_VPC_ATTR_TOTALATTR__MASK; 1718 } 1719 #define A3XX_VPC_ATTR_PSIZE 0x00000200 1720 #define A3XX_VPC_ATTR_THRDASSIGN__MASK 0x0ffff000 1721 #define A3XX_VPC_ATTR_THRDASSIGN__SHIFT 12 1722 static inline uint32_t A3XX_VPC_ATTR_THRDASSIGN(uint32_t val) 1723 { 1724 return ((val) << A3XX_VPC_ATTR_THRDASSIGN__SHIFT) & A3XX_VPC_ATTR_THRDASSIGN__MASK; 1725 } 1726 #define A3XX_VPC_ATTR_LMSIZE__MASK 0xf0000000 1727 #define A3XX_VPC_ATTR_LMSIZE__SHIFT 28 1728 static inline uint32_t A3XX_VPC_ATTR_LMSIZE(uint32_t val) 1729 { 1730 return ((val) << A3XX_VPC_ATTR_LMSIZE__SHIFT) & A3XX_VPC_ATTR_LMSIZE__MASK; 1731 } 1732 1733 #define REG_A3XX_VPC_PACK 0x00002281 1734 #define A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00 1735 #define A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8 1736 static inline uint32_t A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) 1737 { 1738 return ((val) << A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK; 1739 } 1740 #define A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000 1741 #define A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16 1742 static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) 1743 { 1744 return ((val) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK; 1745 } 1746 1747 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002282 + 0x1*i0; } 1748 1749 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002282 + 0x1*i0; } 1750 #define A3XX_VPC_VARYING_INTERP_MODE_C0__MASK 0x00000003 1751 #define A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT 0 1752 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C0(enum a3xx_intp_mode val) 1753 { 1754 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C0__MASK; 1755 } 1756 #define A3XX_VPC_VARYING_INTERP_MODE_C1__MASK 0x0000000c 1757 #define A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT 2 1758 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C1(enum a3xx_intp_mode val) 1759 { 1760 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C1__MASK; 1761 } 1762 #define A3XX_VPC_VARYING_INTERP_MODE_C2__MASK 0x00000030 1763 #define A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT 4 1764 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C2(enum a3xx_intp_mode val) 1765 { 1766 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C2__MASK; 1767 } 1768 #define A3XX_VPC_VARYING_INTERP_MODE_C3__MASK 0x000000c0 1769 #define A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT 6 1770 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C3(enum a3xx_intp_mode val) 1771 { 1772 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C3__MASK; 1773 } 1774 #define A3XX_VPC_VARYING_INTERP_MODE_C4__MASK 0x00000300 1775 #define A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT 8 1776 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C4(enum a3xx_intp_mode val) 1777 { 1778 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C4__MASK; 1779 } 1780 #define A3XX_VPC_VARYING_INTERP_MODE_C5__MASK 0x00000c00 1781 #define A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT 10 1782 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C5(enum a3xx_intp_mode val) 1783 { 1784 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C5__MASK; 1785 } 1786 #define A3XX_VPC_VARYING_INTERP_MODE_C6__MASK 0x00003000 1787 #define A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT 12 1788 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C6(enum a3xx_intp_mode val) 1789 { 1790 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C6__MASK; 1791 } 1792 #define A3XX_VPC_VARYING_INTERP_MODE_C7__MASK 0x0000c000 1793 #define A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT 14 1794 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C7(enum a3xx_intp_mode val) 1795 { 1796 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C7__MASK; 1797 } 1798 #define A3XX_VPC_VARYING_INTERP_MODE_C8__MASK 0x00030000 1799 #define A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT 16 1800 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C8(enum a3xx_intp_mode val) 1801 { 1802 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C8__MASK; 1803 } 1804 #define A3XX_VPC_VARYING_INTERP_MODE_C9__MASK 0x000c0000 1805 #define A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT 18 1806 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C9(enum a3xx_intp_mode val) 1807 { 1808 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C9__MASK; 1809 } 1810 #define A3XX_VPC_VARYING_INTERP_MODE_CA__MASK 0x00300000 1811 #define A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT 20 1812 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CA(enum a3xx_intp_mode val) 1813 { 1814 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CA__MASK; 1815 } 1816 #define A3XX_VPC_VARYING_INTERP_MODE_CB__MASK 0x00c00000 1817 #define A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT 22 1818 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CB(enum a3xx_intp_mode val) 1819 { 1820 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CB__MASK; 1821 } 1822 #define A3XX_VPC_VARYING_INTERP_MODE_CC__MASK 0x03000000 1823 #define A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT 24 1824 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CC(enum a3xx_intp_mode val) 1825 { 1826 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CC__MASK; 1827 } 1828 #define A3XX_VPC_VARYING_INTERP_MODE_CD__MASK 0x0c000000 1829 #define A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT 26 1830 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CD(enum a3xx_intp_mode val) 1831 { 1832 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CD__MASK; 1833 } 1834 #define A3XX_VPC_VARYING_INTERP_MODE_CE__MASK 0x30000000 1835 #define A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT 28 1836 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CE(enum a3xx_intp_mode val) 1837 { 1838 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CE__MASK; 1839 } 1840 #define A3XX_VPC_VARYING_INTERP_MODE_CF__MASK 0xc0000000 1841 #define A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT 30 1842 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CF(enum a3xx_intp_mode val) 1843 { 1844 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CF__MASK; 1845 } 1846 1847 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; } 1848 1849 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; } 1850 #define A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK 0x00000003 1851 #define A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT 0 1852 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C0(enum a3xx_repl_mode val) 1853 { 1854 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK; 1855 } 1856 #define A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK 0x0000000c 1857 #define A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT 2 1858 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C1(enum a3xx_repl_mode val) 1859 { 1860 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK; 1861 } 1862 #define A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK 0x00000030 1863 #define A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT 4 1864 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C2(enum a3xx_repl_mode val) 1865 { 1866 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK; 1867 } 1868 #define A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK 0x000000c0 1869 #define A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT 6 1870 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C3(enum a3xx_repl_mode val) 1871 { 1872 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK; 1873 } 1874 #define A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK 0x00000300 1875 #define A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT 8 1876 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C4(enum a3xx_repl_mode val) 1877 { 1878 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK; 1879 } 1880 #define A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK 0x00000c00 1881 #define A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT 10 1882 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C5(enum a3xx_repl_mode val) 1883 { 1884 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK; 1885 } 1886 #define A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK 0x00003000 1887 #define A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT 12 1888 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C6(enum a3xx_repl_mode val) 1889 { 1890 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK; 1891 } 1892 #define A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK 0x0000c000 1893 #define A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT 14 1894 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C7(enum a3xx_repl_mode val) 1895 { 1896 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK; 1897 } 1898 #define A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK 0x00030000 1899 #define A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT 16 1900 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C8(enum a3xx_repl_mode val) 1901 { 1902 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK; 1903 } 1904 #define A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK 0x000c0000 1905 #define A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT 18 1906 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C9(enum a3xx_repl_mode val) 1907 { 1908 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK; 1909 } 1910 #define A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK 0x00300000 1911 #define A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT 20 1912 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CA(enum a3xx_repl_mode val) 1913 { 1914 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK; 1915 } 1916 #define A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK 0x00c00000 1917 #define A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT 22 1918 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CB(enum a3xx_repl_mode val) 1919 { 1920 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK; 1921 } 1922 #define A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK 0x03000000 1923 #define A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT 24 1924 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CC(enum a3xx_repl_mode val) 1925 { 1926 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK; 1927 } 1928 #define A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK 0x0c000000 1929 #define A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT 26 1930 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CD(enum a3xx_repl_mode val) 1931 { 1932 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK; 1933 } 1934 #define A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK 0x30000000 1935 #define A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT 28 1936 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CE(enum a3xx_repl_mode val) 1937 { 1938 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK; 1939 } 1940 #define A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK 0xc0000000 1941 #define A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT 30 1942 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CF(enum a3xx_repl_mode val) 1943 { 1944 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK; 1945 } 1946 1947 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0 0x0000228a 1948 1949 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_1 0x0000228b 1950 1951 #define REG_A3XX_SP_SP_CTRL_REG 0x000022c0 1952 #define A3XX_SP_SP_CTRL_REG_RESOLVE 0x00010000 1953 #define A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK 0x00040000 1954 #define A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT 18 1955 static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val) 1956 { 1957 return ((val) << A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK; 1958 } 1959 #define A3XX_SP_SP_CTRL_REG_BINNING 0x00080000 1960 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK 0x00300000 1961 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT 20 1962 static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val) 1963 { 1964 return ((val) << A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK; 1965 } 1966 #define A3XX_SP_SP_CTRL_REG_L0MODE__MASK 0x00c00000 1967 #define A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT 22 1968 static inline uint32_t A3XX_SP_SP_CTRL_REG_L0MODE(uint32_t val) 1969 { 1970 return ((val) << A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT) & A3XX_SP_SP_CTRL_REG_L0MODE__MASK; 1971 } 1972 1973 #define REG_A3XX_SP_VS_CTRL_REG0 0x000022c4 1974 #define A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 1975 #define A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 1976 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 1977 { 1978 return ((val) << A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK; 1979 } 1980 #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002 1981 #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1 1982 static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) 1983 { 1984 return ((val) << A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK; 1985 } 1986 #define A3XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004 1987 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 1988 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 1989 static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 1990 { 1991 return ((val) << A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 1992 } 1993 #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 1994 #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 1995 static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 1996 { 1997 return ((val) << A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 1998 } 1999 #define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 2000 #define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 2001 static inline uint32_t A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 2002 { 2003 return ((val) << A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK; 2004 } 2005 #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000 2006 #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20 2007 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 2008 { 2009 return ((val) << A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; 2010 } 2011 #define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000 2012 #define A3XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000 2013 #define A3XX_SP_VS_CTRL_REG0_COMPUTEMODE 0x00800000 2014 #define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK 0xff000000 2015 #define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT 24 2016 static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val) 2017 { 2018 return ((val) << A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG0_LENGTH__MASK; 2019 } 2020 2021 #define REG_A3XX_SP_VS_CTRL_REG1 0x000022c5 2022 #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff 2023 #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0 2024 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) 2025 { 2026 return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK; 2027 } 2028 #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00 2029 #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10 2030 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) 2031 { 2032 return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK; 2033 } 2034 #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000 2035 #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24 2036 static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) 2037 { 2038 return ((val) << A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK; 2039 } 2040 2041 #define REG_A3XX_SP_VS_PARAM_REG 0x000022c6 2042 #define A3XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff 2043 #define A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0 2044 static inline uint32_t A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) 2045 { 2046 return ((val) << A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_POSREGID__MASK; 2047 } 2048 #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00 2049 #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8 2050 static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) 2051 { 2052 return ((val) << A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK; 2053 } 2054 #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000 2055 #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20 2056 static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) 2057 { 2058 return ((val) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; 2059 } 2060 2061 static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 2062 2063 static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 2064 #define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff 2065 #define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 2066 static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 2067 { 2068 return ((val) << A3XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_A_REGID__MASK; 2069 } 2070 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00 2071 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9 2072 static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 2073 { 2074 return ((val) << A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 2075 } 2076 #define A3XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000 2077 #define A3XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 2078 static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 2079 { 2080 return ((val) << A3XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_B_REGID__MASK; 2081 } 2082 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000 2083 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25 2084 static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 2085 { 2086 return ((val) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 2087 } 2088 2089 static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; } 2090 2091 static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; } 2092 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 2093 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 2094 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 2095 { 2096 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 2097 } 2098 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 2099 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 2100 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 2101 { 2102 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 2103 } 2104 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 2105 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 2106 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 2107 { 2108 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 2109 } 2110 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 2111 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 2112 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 2113 { 2114 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 2115 } 2116 2117 #define REG_A3XX_SP_VS_OBJ_OFFSET_REG 0x000022d4 2118 #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2119 #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2120 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2121 { 2122 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2123 } 2124 #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2125 #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2126 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2127 { 2128 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2129 } 2130 2131 #define REG_A3XX_SP_VS_OBJ_START_REG 0x000022d5 2132 2133 #define REG_A3XX_SP_VS_PVT_MEM_PARAM_REG 0x000022d6 2134 2135 #define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG 0x000022d7 2136 2137 #define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG 0x000022d8 2138 2139 #define REG_A3XX_SP_VS_LENGTH_REG 0x000022df 2140 #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff 2141 #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT 0 2142 static inline uint32_t A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val) 2143 { 2144 return ((val) << A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK; 2145 } 2146 2147 #define REG_A3XX_SP_FS_CTRL_REG0 0x000022e0 2148 #define A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 2149 #define A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 2150 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 2151 { 2152 return ((val) << A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK; 2153 } 2154 #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002 2155 #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1 2156 static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) 2157 { 2158 return ((val) << A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK; 2159 } 2160 #define A3XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004 2161 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 2162 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 2163 static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 2164 { 2165 return ((val) << A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 2166 } 2167 #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 2168 #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 2169 static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 2170 { 2171 return ((val) << A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 2172 } 2173 #define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 2174 #define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 2175 static inline uint32_t A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 2176 { 2177 return ((val) << A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK; 2178 } 2179 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 2180 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 2181 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 2182 { 2183 return ((val) << A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 2184 } 2185 #define A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000 2186 #define A3XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000 2187 #define A3XX_SP_FS_CTRL_REG0_COMPUTEMODE 0x00800000 2188 #define A3XX_SP_FS_CTRL_REG0_LENGTH__MASK 0xff000000 2189 #define A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT 24 2190 static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val) 2191 { 2192 return ((val) << A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG0_LENGTH__MASK; 2193 } 2194 2195 #define REG_A3XX_SP_FS_CTRL_REG1 0x000022e1 2196 #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff 2197 #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0 2198 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) 2199 { 2200 return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK; 2201 } 2202 #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00 2203 #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10 2204 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) 2205 { 2206 return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK; 2207 } 2208 #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x00f00000 2209 #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 20 2210 static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) 2211 { 2212 return ((val) << A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK; 2213 } 2214 #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK 0x3f000000 2215 #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT 24 2216 static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val) 2217 { 2218 return ((val) << A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT) & A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK; 2219 } 2220 2221 #define REG_A3XX_SP_FS_OBJ_OFFSET_REG 0x000022e2 2222 #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2223 #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2224 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2225 { 2226 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2227 } 2228 #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2229 #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2230 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2231 { 2232 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2233 } 2234 2235 #define REG_A3XX_SP_FS_OBJ_START_REG 0x000022e3 2236 2237 #define REG_A3XX_SP_FS_PVT_MEM_PARAM_REG 0x000022e4 2238 2239 #define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG 0x000022e5 2240 2241 #define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG 0x000022e6 2242 2243 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0 0x000022e8 2244 2245 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1 0x000022e9 2246 2247 #define REG_A3XX_SP_FS_OUTPUT_REG 0x000022ec 2248 #define A3XX_SP_FS_OUTPUT_REG_MRT__MASK 0x00000003 2249 #define A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0 2250 static inline uint32_t A3XX_SP_FS_OUTPUT_REG_MRT(uint32_t val) 2251 { 2252 return ((val) << A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A3XX_SP_FS_OUTPUT_REG_MRT__MASK; 2253 } 2254 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080 2255 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00 2256 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8 2257 static inline uint32_t A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) 2258 { 2259 return ((val) << A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK; 2260 } 2261 2262 static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0) { return 0x000022f0 + 0x1*i0; } 2263 2264 static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f0 + 0x1*i0; } 2265 #define A3XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff 2266 #define A3XX_SP_FS_MRT_REG_REGID__SHIFT 0 2267 static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val) 2268 { 2269 return ((val) << A3XX_SP_FS_MRT_REG_REGID__SHIFT) & A3XX_SP_FS_MRT_REG_REGID__MASK; 2270 } 2271 #define A3XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100 2272 #define A3XX_SP_FS_MRT_REG_SINT 0x00000400 2273 #define A3XX_SP_FS_MRT_REG_UINT 0x00000800 2274 2275 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0) { return 0x000022f4 + 0x1*i0; } 2276 2277 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0) { return 0x000022f4 + 0x1*i0; } 2278 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK 0x0000003f 2279 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT 0 2280 static inline uint32_t A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val) 2281 { 2282 return ((val) << A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT) & A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK; 2283 } 2284 2285 #define REG_A3XX_SP_FS_LENGTH_REG 0x000022ff 2286 #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff 2287 #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT 0 2288 static inline uint32_t A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val) 2289 { 2290 return ((val) << A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK; 2291 } 2292 2293 #define REG_A3XX_PA_SC_AA_CONFIG 0x00002301 2294 2295 #define REG_A3XX_TPL1_TP_VS_TEX_OFFSET 0x00002340 2296 #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff 2297 #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0 2298 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) 2299 { 2300 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK; 2301 } 2302 #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00 2303 #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8 2304 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) 2305 { 2306 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK; 2307 } 2308 #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000 2309 #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT 16 2310 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val) 2311 { 2312 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK; 2313 } 2314 2315 #define REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002341 2316 2317 #define REG_A3XX_TPL1_TP_FS_TEX_OFFSET 0x00002342 2318 #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff 2319 #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0 2320 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) 2321 { 2322 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK; 2323 } 2324 #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00 2325 #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8 2326 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) 2327 { 2328 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK; 2329 } 2330 #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000 2331 #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT 16 2332 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val) 2333 { 2334 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK; 2335 } 2336 2337 #define REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x00002343 2338 2339 #define REG_A3XX_VBIF_CLKON 0x00003001 2340 2341 #define REG_A3XX_VBIF_FIXED_SORT_EN 0x0000300c 2342 2343 #define REG_A3XX_VBIF_FIXED_SORT_SEL0 0x0000300d 2344 2345 #define REG_A3XX_VBIF_FIXED_SORT_SEL1 0x0000300e 2346 2347 #define REG_A3XX_VBIF_ABIT_SORT 0x0000301c 2348 2349 #define REG_A3XX_VBIF_ABIT_SORT_CONF 0x0000301d 2350 2351 #define REG_A3XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 2352 2353 #define REG_A3XX_VBIF_IN_RD_LIM_CONF0 0x0000302c 2354 2355 #define REG_A3XX_VBIF_IN_RD_LIM_CONF1 0x0000302d 2356 2357 #define REG_A3XX_VBIF_IN_WR_LIM_CONF0 0x00003030 2358 2359 #define REG_A3XX_VBIF_IN_WR_LIM_CONF1 0x00003031 2360 2361 #define REG_A3XX_VBIF_OUT_RD_LIM_CONF0 0x00003034 2362 2363 #define REG_A3XX_VBIF_OUT_WR_LIM_CONF0 0x00003035 2364 2365 #define REG_A3XX_VBIF_DDR_OUT_MAX_BURST 0x00003036 2366 2367 #define REG_A3XX_VBIF_ARB_CTL 0x0000303c 2368 2369 #define REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049 2370 2371 #define REG_A3XX_VBIF_OUT_AXI_AMEMTYPE_CONF0 0x00003058 2372 2373 #define REG_A3XX_VBIF_OUT_AXI_AOOO_EN 0x0000305e 2374 2375 #define REG_A3XX_VBIF_OUT_AXI_AOOO 0x0000305f 2376 2377 #define REG_A3XX_VBIF_PERF_CNT_EN 0x00003070 2378 #define A3XX_VBIF_PERF_CNT_EN_CNT0 0x00000001 2379 #define A3XX_VBIF_PERF_CNT_EN_CNT1 0x00000002 2380 #define A3XX_VBIF_PERF_CNT_EN_PWRCNT0 0x00000004 2381 #define A3XX_VBIF_PERF_CNT_EN_PWRCNT1 0x00000008 2382 #define A3XX_VBIF_PERF_CNT_EN_PWRCNT2 0x00000010 2383 2384 #define REG_A3XX_VBIF_PERF_CNT_CLR 0x00003071 2385 #define A3XX_VBIF_PERF_CNT_CLR_CNT0 0x00000001 2386 #define A3XX_VBIF_PERF_CNT_CLR_CNT1 0x00000002 2387 #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT0 0x00000004 2388 #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT1 0x00000008 2389 #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT2 0x00000010 2390 2391 #define REG_A3XX_VBIF_PERF_CNT_SEL 0x00003072 2392 2393 #define REG_A3XX_VBIF_PERF_CNT0_LO 0x00003073 2394 2395 #define REG_A3XX_VBIF_PERF_CNT0_HI 0x00003074 2396 2397 #define REG_A3XX_VBIF_PERF_CNT1_LO 0x00003075 2398 2399 #define REG_A3XX_VBIF_PERF_CNT1_HI 0x00003076 2400 2401 #define REG_A3XX_VBIF_PERF_PWR_CNT0_LO 0x00003077 2402 2403 #define REG_A3XX_VBIF_PERF_PWR_CNT0_HI 0x00003078 2404 2405 #define REG_A3XX_VBIF_PERF_PWR_CNT1_LO 0x00003079 2406 2407 #define REG_A3XX_VBIF_PERF_PWR_CNT1_HI 0x0000307a 2408 2409 #define REG_A3XX_VBIF_PERF_PWR_CNT2_LO 0x0000307b 2410 2411 #define REG_A3XX_VBIF_PERF_PWR_CNT2_HI 0x0000307c 2412 2413 #define REG_A3XX_VSC_BIN_SIZE 0x00000c01 2414 #define A3XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 2415 #define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 2416 static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 2417 { 2418 return ((val >> 5) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A3XX_VSC_BIN_SIZE_WIDTH__MASK; 2419 } 2420 #define A3XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 2421 #define A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5 2422 static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 2423 { 2424 return ((val >> 5) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK; 2425 } 2426 2427 #define REG_A3XX_VSC_SIZE_ADDRESS 0x00000c02 2428 2429 static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 2430 2431 static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 2432 #define A3XX_VSC_PIPE_CONFIG_X__MASK 0x000003ff 2433 #define A3XX_VSC_PIPE_CONFIG_X__SHIFT 0 2434 static inline uint32_t A3XX_VSC_PIPE_CONFIG_X(uint32_t val) 2435 { 2436 return ((val) << A3XX_VSC_PIPE_CONFIG_X__SHIFT) & A3XX_VSC_PIPE_CONFIG_X__MASK; 2437 } 2438 #define A3XX_VSC_PIPE_CONFIG_Y__MASK 0x000ffc00 2439 #define A3XX_VSC_PIPE_CONFIG_Y__SHIFT 10 2440 static inline uint32_t A3XX_VSC_PIPE_CONFIG_Y(uint32_t val) 2441 { 2442 return ((val) << A3XX_VSC_PIPE_CONFIG_Y__SHIFT) & A3XX_VSC_PIPE_CONFIG_Y__MASK; 2443 } 2444 #define A3XX_VSC_PIPE_CONFIG_W__MASK 0x00f00000 2445 #define A3XX_VSC_PIPE_CONFIG_W__SHIFT 20 2446 static inline uint32_t A3XX_VSC_PIPE_CONFIG_W(uint32_t val) 2447 { 2448 return ((val) << A3XX_VSC_PIPE_CONFIG_W__SHIFT) & A3XX_VSC_PIPE_CONFIG_W__MASK; 2449 } 2450 #define A3XX_VSC_PIPE_CONFIG_H__MASK 0x0f000000 2451 #define A3XX_VSC_PIPE_CONFIG_H__SHIFT 24 2452 static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val) 2453 { 2454 return ((val) << A3XX_VSC_PIPE_CONFIG_H__SHIFT) & A3XX_VSC_PIPE_CONFIG_H__MASK; 2455 } 2456 2457 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } 2458 2459 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } 2460 2461 #define REG_A3XX_VSC_BIN_CONTROL 0x00000c3c 2462 #define A3XX_VSC_BIN_CONTROL_BINNING_ENABLE 0x00000001 2463 2464 #define REG_A3XX_UNKNOWN_0C3D 0x00000c3d 2465 2466 #define REG_A3XX_PC_PERFCOUNTER0_SELECT 0x00000c48 2467 2468 #define REG_A3XX_PC_PERFCOUNTER1_SELECT 0x00000c49 2469 2470 #define REG_A3XX_PC_PERFCOUNTER2_SELECT 0x00000c4a 2471 2472 #define REG_A3XX_PC_PERFCOUNTER3_SELECT 0x00000c4b 2473 2474 #define REG_A3XX_GRAS_TSE_DEBUG_ECO 0x00000c81 2475 2476 #define REG_A3XX_GRAS_PERFCOUNTER0_SELECT 0x00000c88 2477 2478 #define REG_A3XX_GRAS_PERFCOUNTER1_SELECT 0x00000c89 2479 2480 #define REG_A3XX_GRAS_PERFCOUNTER2_SELECT 0x00000c8a 2481 2482 #define REG_A3XX_GRAS_PERFCOUNTER3_SELECT 0x00000c8b 2483 2484 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } 2485 2486 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } 2487 2488 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0) { return 0x00000ca1 + 0x4*i0; } 2489 2490 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0) { return 0x00000ca2 + 0x4*i0; } 2491 2492 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) { return 0x00000ca3 + 0x4*i0; } 2493 2494 #define REG_A3XX_RB_GMEM_BASE_ADDR 0x00000cc0 2495 2496 #define REG_A3XX_RB_DEBUG_ECO_CONTROLS_ADDR 0x00000cc1 2497 2498 #define REG_A3XX_RB_PERFCOUNTER0_SELECT 0x00000cc6 2499 2500 #define REG_A3XX_RB_PERFCOUNTER1_SELECT 0x00000cc7 2501 2502 #define REG_A3XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0 2503 #define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff 2504 #define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0 2505 static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) 2506 { 2507 return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK; 2508 } 2509 #define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x0fffc000 2510 #define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 14 2511 static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) 2512 { 2513 return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK; 2514 } 2515 2516 #define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT 0x00000e00 2517 2518 #define REG_A3XX_HLSQ_PERFCOUNTER1_SELECT 0x00000e01 2519 2520 #define REG_A3XX_HLSQ_PERFCOUNTER2_SELECT 0x00000e02 2521 2522 #define REG_A3XX_HLSQ_PERFCOUNTER3_SELECT 0x00000e03 2523 2524 #define REG_A3XX_HLSQ_PERFCOUNTER4_SELECT 0x00000e04 2525 2526 #define REG_A3XX_HLSQ_PERFCOUNTER5_SELECT 0x00000e05 2527 2528 #define REG_A3XX_UNKNOWN_0E43 0x00000e43 2529 2530 #define REG_A3XX_VFD_PERFCOUNTER0_SELECT 0x00000e44 2531 2532 #define REG_A3XX_VFD_PERFCOUNTER1_SELECT 0x00000e45 2533 2534 #define REG_A3XX_VPC_VPC_DEBUG_RAM_SEL 0x00000e61 2535 2536 #define REG_A3XX_VPC_VPC_DEBUG_RAM_READ 0x00000e62 2537 2538 #define REG_A3XX_VPC_PERFCOUNTER0_SELECT 0x00000e64 2539 2540 #define REG_A3XX_VPC_PERFCOUNTER1_SELECT 0x00000e65 2541 2542 #define REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG 0x00000e82 2543 2544 #define REG_A3XX_UCHE_PERFCOUNTER0_SELECT 0x00000e84 2545 2546 #define REG_A3XX_UCHE_PERFCOUNTER1_SELECT 0x00000e85 2547 2548 #define REG_A3XX_UCHE_PERFCOUNTER2_SELECT 0x00000e86 2549 2550 #define REG_A3XX_UCHE_PERFCOUNTER3_SELECT 0x00000e87 2551 2552 #define REG_A3XX_UCHE_PERFCOUNTER4_SELECT 0x00000e88 2553 2554 #define REG_A3XX_UCHE_PERFCOUNTER5_SELECT 0x00000e89 2555 2556 #define REG_A3XX_UCHE_CACHE_INVALIDATE0_REG 0x00000ea0 2557 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK 0x0fffffff 2558 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT 0 2559 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val) 2560 { 2561 return ((val) << A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK; 2562 } 2563 2564 #define REG_A3XX_UCHE_CACHE_INVALIDATE1_REG 0x00000ea1 2565 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK 0x0fffffff 2566 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT 0 2567 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val) 2568 { 2569 return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK; 2570 } 2571 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK 0x30000000 2572 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT 28 2573 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val) 2574 { 2575 return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK; 2576 } 2577 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE 0x80000000 2578 2579 #define REG_A3XX_UNKNOWN_0EA6 0x00000ea6 2580 2581 #define REG_A3XX_SP_PERFCOUNTER0_SELECT 0x00000ec4 2582 2583 #define REG_A3XX_SP_PERFCOUNTER1_SELECT 0x00000ec5 2584 2585 #define REG_A3XX_SP_PERFCOUNTER2_SELECT 0x00000ec6 2586 2587 #define REG_A3XX_SP_PERFCOUNTER3_SELECT 0x00000ec7 2588 2589 #define REG_A3XX_SP_PERFCOUNTER4_SELECT 0x00000ec8 2590 2591 #define REG_A3XX_SP_PERFCOUNTER5_SELECT 0x00000ec9 2592 2593 #define REG_A3XX_SP_PERFCOUNTER6_SELECT 0x00000eca 2594 2595 #define REG_A3XX_SP_PERFCOUNTER7_SELECT 0x00000ecb 2596 2597 #define REG_A3XX_UNKNOWN_0EE0 0x00000ee0 2598 2599 #define REG_A3XX_UNKNOWN_0F03 0x00000f03 2600 2601 #define REG_A3XX_TP_PERFCOUNTER0_SELECT 0x00000f04 2602 2603 #define REG_A3XX_TP_PERFCOUNTER1_SELECT 0x00000f05 2604 2605 #define REG_A3XX_TP_PERFCOUNTER2_SELECT 0x00000f06 2606 2607 #define REG_A3XX_TP_PERFCOUNTER3_SELECT 0x00000f07 2608 2609 #define REG_A3XX_TP_PERFCOUNTER4_SELECT 0x00000f08 2610 2611 #define REG_A3XX_TP_PERFCOUNTER5_SELECT 0x00000f09 2612 2613 #define REG_A3XX_VGT_CL_INITIATOR 0x000021f0 2614 2615 #define REG_A3XX_VGT_EVENT_INITIATOR 0x000021f9 2616 2617 #define REG_A3XX_VGT_DRAW_INITIATOR 0x000021fc 2618 #define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f 2619 #define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 2620 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) 2621 { 2622 return ((val) << A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK; 2623 } 2624 #define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 2625 #define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 2626 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) 2627 { 2628 return ((val) << A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK; 2629 } 2630 #define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600 2631 #define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9 2632 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) 2633 { 2634 return ((val) << A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK; 2635 } 2636 #define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800 2637 #define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11 2638 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) 2639 { 2640 return ((val) << A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK; 2641 } 2642 #define A3XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000 2643 #define A3XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000 2644 #define A3XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000 2645 #define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK 0xff000000 2646 #define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT 24 2647 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) 2648 { 2649 return ((val) << A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK; 2650 } 2651 2652 #define REG_A3XX_VGT_IMMED_DATA 0x000021fd 2653 2654 #define REG_A3XX_TEX_SAMP_0 0x00000000 2655 #define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR 0x00000002 2656 #define A3XX_TEX_SAMP_0_XY_MAG__MASK 0x0000000c 2657 #define A3XX_TEX_SAMP_0_XY_MAG__SHIFT 2 2658 static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val) 2659 { 2660 return ((val) << A3XX_TEX_SAMP_0_XY_MAG__SHIFT) & A3XX_TEX_SAMP_0_XY_MAG__MASK; 2661 } 2662 #define A3XX_TEX_SAMP_0_XY_MIN__MASK 0x00000030 2663 #define A3XX_TEX_SAMP_0_XY_MIN__SHIFT 4 2664 static inline uint32_t A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val) 2665 { 2666 return ((val) << A3XX_TEX_SAMP_0_XY_MIN__SHIFT) & A3XX_TEX_SAMP_0_XY_MIN__MASK; 2667 } 2668 #define A3XX_TEX_SAMP_0_WRAP_S__MASK 0x000001c0 2669 #define A3XX_TEX_SAMP_0_WRAP_S__SHIFT 6 2670 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val) 2671 { 2672 return ((val) << A3XX_TEX_SAMP_0_WRAP_S__SHIFT) & A3XX_TEX_SAMP_0_WRAP_S__MASK; 2673 } 2674 #define A3XX_TEX_SAMP_0_WRAP_T__MASK 0x00000e00 2675 #define A3XX_TEX_SAMP_0_WRAP_T__SHIFT 9 2676 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val) 2677 { 2678 return ((val) << A3XX_TEX_SAMP_0_WRAP_T__SHIFT) & A3XX_TEX_SAMP_0_WRAP_T__MASK; 2679 } 2680 #define A3XX_TEX_SAMP_0_WRAP_R__MASK 0x00007000 2681 #define A3XX_TEX_SAMP_0_WRAP_R__SHIFT 12 2682 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val) 2683 { 2684 return ((val) << A3XX_TEX_SAMP_0_WRAP_R__SHIFT) & A3XX_TEX_SAMP_0_WRAP_R__MASK; 2685 } 2686 #define A3XX_TEX_SAMP_0_ANISO__MASK 0x00038000 2687 #define A3XX_TEX_SAMP_0_ANISO__SHIFT 15 2688 static inline uint32_t A3XX_TEX_SAMP_0_ANISO(enum a3xx_tex_aniso val) 2689 { 2690 return ((val) << A3XX_TEX_SAMP_0_ANISO__SHIFT) & A3XX_TEX_SAMP_0_ANISO__MASK; 2691 } 2692 #define A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK 0x00700000 2693 #define A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT 20 2694 static inline uint32_t A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val) 2695 { 2696 return ((val) << A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT) & A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK; 2697 } 2698 #define A3XX_TEX_SAMP_0_UNNORM_COORDS 0x80000000 2699 2700 #define REG_A3XX_TEX_SAMP_1 0x00000001 2701 #define A3XX_TEX_SAMP_1_LOD_BIAS__MASK 0x000007ff 2702 #define A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT 0 2703 static inline uint32_t A3XX_TEX_SAMP_1_LOD_BIAS(float val) 2704 { 2705 return ((((int32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT) & A3XX_TEX_SAMP_1_LOD_BIAS__MASK; 2706 } 2707 #define A3XX_TEX_SAMP_1_MAX_LOD__MASK 0x003ff000 2708 #define A3XX_TEX_SAMP_1_MAX_LOD__SHIFT 12 2709 static inline uint32_t A3XX_TEX_SAMP_1_MAX_LOD(float val) 2710 { 2711 return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A3XX_TEX_SAMP_1_MAX_LOD__MASK; 2712 } 2713 #define A3XX_TEX_SAMP_1_MIN_LOD__MASK 0xffc00000 2714 #define A3XX_TEX_SAMP_1_MIN_LOD__SHIFT 22 2715 static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val) 2716 { 2717 return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A3XX_TEX_SAMP_1_MIN_LOD__MASK; 2718 } 2719 2720 #define REG_A3XX_TEX_CONST_0 0x00000000 2721 #define A3XX_TEX_CONST_0_TILED 0x00000001 2722 #define A3XX_TEX_CONST_0_SRGB 0x00000004 2723 #define A3XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 2724 #define A3XX_TEX_CONST_0_SWIZ_X__SHIFT 4 2725 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val) 2726 { 2727 return ((val) << A3XX_TEX_CONST_0_SWIZ_X__SHIFT) & A3XX_TEX_CONST_0_SWIZ_X__MASK; 2728 } 2729 #define A3XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 2730 #define A3XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 2731 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val) 2732 { 2733 return ((val) << A3XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Y__MASK; 2734 } 2735 #define A3XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 2736 #define A3XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 2737 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val) 2738 { 2739 return ((val) << A3XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Z__MASK; 2740 } 2741 #define A3XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 2742 #define A3XX_TEX_CONST_0_SWIZ_W__SHIFT 13 2743 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val) 2744 { 2745 return ((val) << A3XX_TEX_CONST_0_SWIZ_W__SHIFT) & A3XX_TEX_CONST_0_SWIZ_W__MASK; 2746 } 2747 #define A3XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 2748 #define A3XX_TEX_CONST_0_MIPLVLS__SHIFT 16 2749 static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val) 2750 { 2751 return ((val) << A3XX_TEX_CONST_0_MIPLVLS__SHIFT) & A3XX_TEX_CONST_0_MIPLVLS__MASK; 2752 } 2753 #define A3XX_TEX_CONST_0_FMT__MASK 0x1fc00000 2754 #define A3XX_TEX_CONST_0_FMT__SHIFT 22 2755 static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val) 2756 { 2757 return ((val) << A3XX_TEX_CONST_0_FMT__SHIFT) & A3XX_TEX_CONST_0_FMT__MASK; 2758 } 2759 #define A3XX_TEX_CONST_0_NOCONVERT 0x20000000 2760 #define A3XX_TEX_CONST_0_TYPE__MASK 0xc0000000 2761 #define A3XX_TEX_CONST_0_TYPE__SHIFT 30 2762 static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val) 2763 { 2764 return ((val) << A3XX_TEX_CONST_0_TYPE__SHIFT) & A3XX_TEX_CONST_0_TYPE__MASK; 2765 } 2766 2767 #define REG_A3XX_TEX_CONST_1 0x00000001 2768 #define A3XX_TEX_CONST_1_HEIGHT__MASK 0x00003fff 2769 #define A3XX_TEX_CONST_1_HEIGHT__SHIFT 0 2770 static inline uint32_t A3XX_TEX_CONST_1_HEIGHT(uint32_t val) 2771 { 2772 return ((val) << A3XX_TEX_CONST_1_HEIGHT__SHIFT) & A3XX_TEX_CONST_1_HEIGHT__MASK; 2773 } 2774 #define A3XX_TEX_CONST_1_WIDTH__MASK 0x0fffc000 2775 #define A3XX_TEX_CONST_1_WIDTH__SHIFT 14 2776 static inline uint32_t A3XX_TEX_CONST_1_WIDTH(uint32_t val) 2777 { 2778 return ((val) << A3XX_TEX_CONST_1_WIDTH__SHIFT) & A3XX_TEX_CONST_1_WIDTH__MASK; 2779 } 2780 #define A3XX_TEX_CONST_1_FETCHSIZE__MASK 0xf0000000 2781 #define A3XX_TEX_CONST_1_FETCHSIZE__SHIFT 28 2782 static inline uint32_t A3XX_TEX_CONST_1_FETCHSIZE(enum a3xx_tex_fetchsize val) 2783 { 2784 return ((val) << A3XX_TEX_CONST_1_FETCHSIZE__SHIFT) & A3XX_TEX_CONST_1_FETCHSIZE__MASK; 2785 } 2786 2787 #define REG_A3XX_TEX_CONST_2 0x00000002 2788 #define A3XX_TEX_CONST_2_INDX__MASK 0x000000ff 2789 #define A3XX_TEX_CONST_2_INDX__SHIFT 0 2790 static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val) 2791 { 2792 return ((val) << A3XX_TEX_CONST_2_INDX__SHIFT) & A3XX_TEX_CONST_2_INDX__MASK; 2793 } 2794 #define A3XX_TEX_CONST_2_PITCH__MASK 0x3ffff000 2795 #define A3XX_TEX_CONST_2_PITCH__SHIFT 12 2796 static inline uint32_t A3XX_TEX_CONST_2_PITCH(uint32_t val) 2797 { 2798 return ((val) << A3XX_TEX_CONST_2_PITCH__SHIFT) & A3XX_TEX_CONST_2_PITCH__MASK; 2799 } 2800 #define A3XX_TEX_CONST_2_SWAP__MASK 0xc0000000 2801 #define A3XX_TEX_CONST_2_SWAP__SHIFT 30 2802 static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) 2803 { 2804 return ((val) << A3XX_TEX_CONST_2_SWAP__SHIFT) & A3XX_TEX_CONST_2_SWAP__MASK; 2805 } 2806 2807 #define REG_A3XX_TEX_CONST_3 0x00000003 2808 #define A3XX_TEX_CONST_3_LAYERSZ1__MASK 0x00007fff 2809 #define A3XX_TEX_CONST_3_LAYERSZ1__SHIFT 0 2810 static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val) 2811 { 2812 return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ1__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ1__MASK; 2813 } 2814 #define A3XX_TEX_CONST_3_DEPTH__MASK 0x0ffe0000 2815 #define A3XX_TEX_CONST_3_DEPTH__SHIFT 17 2816 static inline uint32_t A3XX_TEX_CONST_3_DEPTH(uint32_t val) 2817 { 2818 return ((val) << A3XX_TEX_CONST_3_DEPTH__SHIFT) & A3XX_TEX_CONST_3_DEPTH__MASK; 2819 } 2820 #define A3XX_TEX_CONST_3_LAYERSZ2__MASK 0xf0000000 2821 #define A3XX_TEX_CONST_3_LAYERSZ2__SHIFT 28 2822 static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ2(uint32_t val) 2823 { 2824 return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ2__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ2__MASK; 2825 } 2826 2827 2828 #endif /* A3XX_XML */ 2829