1 #ifndef A3XX_XML 2 #define A3XX_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30) 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 9859 bytes, from 2014-06-02 15:21:30) 15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14477 bytes, from 2014-05-16 11:51:57) 16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 58020 bytes, from 2014-06-25 12:57:16) 17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 26602 bytes, from 2014-06-25 12:57:16) 18 19 Copyright (C) 2013-2014 by the following authors: 20 - Rob Clark <robdclark@gmail.com> (robclark) 21 22 Permission is hereby granted, free of charge, to any person obtaining 23 a copy of this software and associated documentation files (the 24 "Software"), to deal in the Software without restriction, including 25 without limitation the rights to use, copy, modify, merge, publish, 26 distribute, sublicense, and/or sell copies of the Software, and to 27 permit persons to whom the Software is furnished to do so, subject to 28 the following conditions: 29 30 The above copyright notice and this permission notice (including the 31 next paragraph) shall be included in all copies or substantial 32 portions of the Software. 33 34 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 36 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 37 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 38 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 39 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 40 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43 44 enum a3xx_tile_mode { 45 LINEAR = 0, 46 TILE_32X32 = 2, 47 }; 48 49 enum a3xx_state_block_id { 50 HLSQ_BLOCK_ID_TP_TEX = 2, 51 HLSQ_BLOCK_ID_TP_MIPMAP = 3, 52 HLSQ_BLOCK_ID_SP_VS = 4, 53 HLSQ_BLOCK_ID_SP_FS = 6, 54 }; 55 56 enum a3xx_cache_opcode { 57 INVALIDATE = 1, 58 }; 59 60 enum a3xx_vtx_fmt { 61 VFMT_FLOAT_32 = 0, 62 VFMT_FLOAT_32_32 = 1, 63 VFMT_FLOAT_32_32_32 = 2, 64 VFMT_FLOAT_32_32_32_32 = 3, 65 VFMT_FLOAT_16 = 4, 66 VFMT_FLOAT_16_16 = 5, 67 VFMT_FLOAT_16_16_16 = 6, 68 VFMT_FLOAT_16_16_16_16 = 7, 69 VFMT_FIXED_32 = 8, 70 VFMT_FIXED_32_32 = 9, 71 VFMT_FIXED_32_32_32 = 10, 72 VFMT_FIXED_32_32_32_32 = 11, 73 VFMT_SHORT_16 = 16, 74 VFMT_SHORT_16_16 = 17, 75 VFMT_SHORT_16_16_16 = 18, 76 VFMT_SHORT_16_16_16_16 = 19, 77 VFMT_USHORT_16 = 20, 78 VFMT_USHORT_16_16 = 21, 79 VFMT_USHORT_16_16_16 = 22, 80 VFMT_USHORT_16_16_16_16 = 23, 81 VFMT_NORM_SHORT_16 = 24, 82 VFMT_NORM_SHORT_16_16 = 25, 83 VFMT_NORM_SHORT_16_16_16 = 26, 84 VFMT_NORM_SHORT_16_16_16_16 = 27, 85 VFMT_NORM_USHORT_16 = 28, 86 VFMT_NORM_USHORT_16_16 = 29, 87 VFMT_NORM_USHORT_16_16_16 = 30, 88 VFMT_NORM_USHORT_16_16_16_16 = 31, 89 VFMT_UBYTE_8 = 40, 90 VFMT_UBYTE_8_8 = 41, 91 VFMT_UBYTE_8_8_8 = 42, 92 VFMT_UBYTE_8_8_8_8 = 43, 93 VFMT_NORM_UBYTE_8 = 44, 94 VFMT_NORM_UBYTE_8_8 = 45, 95 VFMT_NORM_UBYTE_8_8_8 = 46, 96 VFMT_NORM_UBYTE_8_8_8_8 = 47, 97 VFMT_BYTE_8 = 48, 98 VFMT_BYTE_8_8 = 49, 99 VFMT_BYTE_8_8_8 = 50, 100 VFMT_BYTE_8_8_8_8 = 51, 101 VFMT_NORM_BYTE_8 = 52, 102 VFMT_NORM_BYTE_8_8 = 53, 103 VFMT_NORM_BYTE_8_8_8 = 54, 104 VFMT_NORM_BYTE_8_8_8_8 = 55, 105 VFMT_UINT_10_10_10_2 = 60, 106 VFMT_NORM_UINT_10_10_10_2 = 61, 107 VFMT_INT_10_10_10_2 = 62, 108 VFMT_NORM_INT_10_10_10_2 = 63, 109 }; 110 111 enum a3xx_tex_fmt { 112 TFMT_NORM_USHORT_565 = 4, 113 TFMT_NORM_USHORT_5551 = 6, 114 TFMT_NORM_USHORT_4444 = 7, 115 TFMT_NORM_UINT_X8Z24 = 10, 116 TFMT_NORM_UINT_NV12_UV_TILED = 17, 117 TFMT_NORM_UINT_NV12_Y_TILED = 19, 118 TFMT_NORM_UINT_NV12_UV = 21, 119 TFMT_NORM_UINT_NV12_Y = 23, 120 TFMT_NORM_UINT_I420_Y = 24, 121 TFMT_NORM_UINT_I420_U = 26, 122 TFMT_NORM_UINT_I420_V = 27, 123 TFMT_NORM_UINT_2_10_10_10 = 41, 124 TFMT_NORM_UINT_A8 = 44, 125 TFMT_NORM_UINT_L8_A8 = 47, 126 TFMT_NORM_UINT_8 = 48, 127 TFMT_NORM_UINT_8_8 = 49, 128 TFMT_NORM_UINT_8_8_8 = 50, 129 TFMT_NORM_UINT_8_8_8_8 = 51, 130 TFMT_FLOAT_16 = 64, 131 TFMT_FLOAT_16_16 = 65, 132 TFMT_FLOAT_16_16_16_16 = 67, 133 TFMT_FLOAT_32 = 84, 134 TFMT_FLOAT_32_32 = 85, 135 TFMT_FLOAT_32_32_32_32 = 87, 136 }; 137 138 enum a3xx_tex_fetchsize { 139 TFETCH_DISABLE = 0, 140 TFETCH_1_BYTE = 1, 141 TFETCH_2_BYTE = 2, 142 TFETCH_4_BYTE = 3, 143 TFETCH_8_BYTE = 4, 144 TFETCH_16_BYTE = 5, 145 }; 146 147 enum a3xx_color_fmt { 148 RB_R8G8B8_UNORM = 4, 149 RB_R8G8B8A8_UNORM = 8, 150 RB_Z16_UNORM = 12, 151 RB_A8_UNORM = 20, 152 RB_R16G16B16A16_FLOAT = 27, 153 RB_R32G32B32A32_FLOAT = 51, 154 }; 155 156 enum a3xx_color_swap { 157 WZYX = 0, 158 WXYZ = 1, 159 ZYXW = 2, 160 XYZW = 3, 161 }; 162 163 enum a3xx_sp_perfcounter_select { 164 SP_FS_CFLOW_INSTRUCTIONS = 12, 165 SP_FS_FULL_ALU_INSTRUCTIONS = 14, 166 SP0_ICL1_MISSES = 26, 167 SP_ALU_ACTIVE_CYCLES = 29, 168 }; 169 170 enum a3xx_rop_code { 171 ROP_CLEAR = 0, 172 ROP_NOR = 1, 173 ROP_AND_INVERTED = 2, 174 ROP_COPY_INVERTED = 3, 175 ROP_AND_REVERSE = 4, 176 ROP_INVERT = 5, 177 ROP_XOR = 6, 178 ROP_NAND = 7, 179 ROP_AND = 8, 180 ROP_EQUIV = 9, 181 ROP_NOOP = 10, 182 ROP_OR_INVERTED = 11, 183 ROP_COPY = 12, 184 ROP_OR_REVERSE = 13, 185 ROP_OR = 14, 186 ROP_SET = 15, 187 }; 188 189 enum a3xx_rb_blend_opcode { 190 BLEND_DST_PLUS_SRC = 0, 191 BLEND_SRC_MINUS_DST = 1, 192 BLEND_DST_MINUS_SRC = 2, 193 BLEND_MIN_DST_SRC = 3, 194 BLEND_MAX_DST_SRC = 4, 195 }; 196 197 enum a3xx_tex_filter { 198 A3XX_TEX_NEAREST = 0, 199 A3XX_TEX_LINEAR = 1, 200 A3XX_TEX_ANISO = 2, 201 }; 202 203 enum a3xx_tex_clamp { 204 A3XX_TEX_REPEAT = 0, 205 A3XX_TEX_CLAMP_TO_EDGE = 1, 206 A3XX_TEX_MIRROR_REPEAT = 2, 207 A3XX_TEX_CLAMP_TO_BORDER = 3, 208 A3XX_TEX_MIRROR_CLAMP = 4, 209 }; 210 211 enum a3xx_tex_swiz { 212 A3XX_TEX_X = 0, 213 A3XX_TEX_Y = 1, 214 A3XX_TEX_Z = 2, 215 A3XX_TEX_W = 3, 216 A3XX_TEX_ZERO = 4, 217 A3XX_TEX_ONE = 5, 218 }; 219 220 enum a3xx_tex_type { 221 A3XX_TEX_1D = 0, 222 A3XX_TEX_2D = 1, 223 A3XX_TEX_CUBE = 2, 224 A3XX_TEX_3D = 3, 225 }; 226 227 #define A3XX_INT0_RBBM_GPU_IDLE 0x00000001 228 #define A3XX_INT0_RBBM_AHB_ERROR 0x00000002 229 #define A3XX_INT0_RBBM_REG_TIMEOUT 0x00000004 230 #define A3XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 231 #define A3XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 232 #define A3XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020 233 #define A3XX_INT0_VFD_ERROR 0x00000040 234 #define A3XX_INT0_CP_SW_INT 0x00000080 235 #define A3XX_INT0_CP_T0_PACKET_IN_IB 0x00000100 236 #define A3XX_INT0_CP_OPCODE_ERROR 0x00000200 237 #define A3XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400 238 #define A3XX_INT0_CP_HW_FAULT 0x00000800 239 #define A3XX_INT0_CP_DMA 0x00001000 240 #define A3XX_INT0_CP_IB2_INT 0x00002000 241 #define A3XX_INT0_CP_IB1_INT 0x00004000 242 #define A3XX_INT0_CP_RB_INT 0x00008000 243 #define A3XX_INT0_CP_REG_PROTECT_FAULT 0x00010000 244 #define A3XX_INT0_CP_RB_DONE_TS 0x00020000 245 #define A3XX_INT0_CP_VS_DONE_TS 0x00040000 246 #define A3XX_INT0_CP_PS_DONE_TS 0x00080000 247 #define A3XX_INT0_CACHE_FLUSH_TS 0x00100000 248 #define A3XX_INT0_CP_AHB_ERROR_HALT 0x00200000 249 #define A3XX_INT0_MISC_HANG_DETECT 0x01000000 250 #define A3XX_INT0_UCHE_OOB_ACCESS 0x02000000 251 #define REG_A3XX_RBBM_HW_VERSION 0x00000000 252 253 #define REG_A3XX_RBBM_HW_RELEASE 0x00000001 254 255 #define REG_A3XX_RBBM_HW_CONFIGURATION 0x00000002 256 257 #define REG_A3XX_RBBM_CLOCK_CTL 0x00000010 258 259 #define REG_A3XX_RBBM_SP_HYST_CNT 0x00000012 260 261 #define REG_A3XX_RBBM_SW_RESET_CMD 0x00000018 262 263 #define REG_A3XX_RBBM_AHB_CTL0 0x00000020 264 265 #define REG_A3XX_RBBM_AHB_CTL1 0x00000021 266 267 #define REG_A3XX_RBBM_AHB_CMD 0x00000022 268 269 #define REG_A3XX_RBBM_AHB_ERROR_STATUS 0x00000027 270 271 #define REG_A3XX_RBBM_GPR0_CTL 0x0000002e 272 273 #define REG_A3XX_RBBM_STATUS 0x00000030 274 #define A3XX_RBBM_STATUS_HI_BUSY 0x00000001 275 #define A3XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 276 #define A3XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 277 #define A3XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000 278 #define A3XX_RBBM_STATUS_VBIF_BUSY 0x00008000 279 #define A3XX_RBBM_STATUS_TSE_BUSY 0x00010000 280 #define A3XX_RBBM_STATUS_RAS_BUSY 0x00020000 281 #define A3XX_RBBM_STATUS_RB_BUSY 0x00040000 282 #define A3XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 283 #define A3XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 284 #define A3XX_RBBM_STATUS_VFD_BUSY 0x00200000 285 #define A3XX_RBBM_STATUS_VPC_BUSY 0x00400000 286 #define A3XX_RBBM_STATUS_UCHE_BUSY 0x00800000 287 #define A3XX_RBBM_STATUS_SP_BUSY 0x01000000 288 #define A3XX_RBBM_STATUS_TPL1_BUSY 0x02000000 289 #define A3XX_RBBM_STATUS_MARB_BUSY 0x04000000 290 #define A3XX_RBBM_STATUS_VSC_BUSY 0x08000000 291 #define A3XX_RBBM_STATUS_ARB_BUSY 0x10000000 292 #define A3XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 293 #define A3XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000 294 #define A3XX_RBBM_STATUS_GPU_BUSY 0x80000000 295 296 #define REG_A3XX_RBBM_NQWAIT_UNTIL 0x00000040 297 298 #define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x00000033 299 300 #define REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL 0x00000050 301 302 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL0 0x00000051 303 304 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL1 0x00000054 305 306 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL2 0x00000057 307 308 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3 0x0000005a 309 310 #define REG_A3XX_RBBM_INT_SET_CMD 0x00000060 311 312 #define REG_A3XX_RBBM_INT_CLEAR_CMD 0x00000061 313 314 #define REG_A3XX_RBBM_INT_0_MASK 0x00000063 315 316 #define REG_A3XX_RBBM_INT_0_STATUS 0x00000064 317 318 #define REG_A3XX_RBBM_PERFCTR_CTL 0x00000080 319 #define A3XX_RBBM_PERFCTR_CTL_ENABLE 0x00000001 320 321 #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0 0x00000081 322 323 #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD1 0x00000082 324 325 #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000084 326 327 #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000085 328 329 #define REG_A3XX_RBBM_PERFCOUNTER0_SELECT 0x00000086 330 331 #define REG_A3XX_RBBM_PERFCOUNTER1_SELECT 0x00000087 332 333 #define REG_A3XX_RBBM_GPU_BUSY_MASKED 0x00000088 334 335 #define REG_A3XX_RBBM_PERFCTR_CP_0_LO 0x00000090 336 337 #define REG_A3XX_RBBM_PERFCTR_CP_0_HI 0x00000091 338 339 #define REG_A3XX_RBBM_PERFCTR_RBBM_0_LO 0x00000092 340 341 #define REG_A3XX_RBBM_PERFCTR_RBBM_0_HI 0x00000093 342 343 #define REG_A3XX_RBBM_PERFCTR_RBBM_1_LO 0x00000094 344 345 #define REG_A3XX_RBBM_PERFCTR_RBBM_1_HI 0x00000095 346 347 #define REG_A3XX_RBBM_PERFCTR_PC_0_LO 0x00000096 348 349 #define REG_A3XX_RBBM_PERFCTR_PC_0_HI 0x00000097 350 351 #define REG_A3XX_RBBM_PERFCTR_PC_1_LO 0x00000098 352 353 #define REG_A3XX_RBBM_PERFCTR_PC_1_HI 0x00000099 354 355 #define REG_A3XX_RBBM_PERFCTR_PC_2_LO 0x0000009a 356 357 #define REG_A3XX_RBBM_PERFCTR_PC_2_HI 0x0000009b 358 359 #define REG_A3XX_RBBM_PERFCTR_PC_3_LO 0x0000009c 360 361 #define REG_A3XX_RBBM_PERFCTR_PC_3_HI 0x0000009d 362 363 #define REG_A3XX_RBBM_PERFCTR_VFD_0_LO 0x0000009e 364 365 #define REG_A3XX_RBBM_PERFCTR_VFD_0_HI 0x0000009f 366 367 #define REG_A3XX_RBBM_PERFCTR_VFD_1_LO 0x000000a0 368 369 #define REG_A3XX_RBBM_PERFCTR_VFD_1_HI 0x000000a1 370 371 #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000a2 372 373 #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000a3 374 375 #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000a4 376 377 #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000a5 378 379 #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000a6 380 381 #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000a7 382 383 #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000a8 384 385 #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000a9 386 387 #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000aa 388 389 #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000ab 390 391 #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000ac 392 393 #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000ad 394 395 #define REG_A3XX_RBBM_PERFCTR_VPC_0_LO 0x000000ae 396 397 #define REG_A3XX_RBBM_PERFCTR_VPC_0_HI 0x000000af 398 399 #define REG_A3XX_RBBM_PERFCTR_VPC_1_LO 0x000000b0 400 401 #define REG_A3XX_RBBM_PERFCTR_VPC_1_HI 0x000000b1 402 403 #define REG_A3XX_RBBM_PERFCTR_TSE_0_LO 0x000000b2 404 405 #define REG_A3XX_RBBM_PERFCTR_TSE_0_HI 0x000000b3 406 407 #define REG_A3XX_RBBM_PERFCTR_TSE_1_LO 0x000000b4 408 409 #define REG_A3XX_RBBM_PERFCTR_TSE_1_HI 0x000000b5 410 411 #define REG_A3XX_RBBM_PERFCTR_RAS_0_LO 0x000000b6 412 413 #define REG_A3XX_RBBM_PERFCTR_RAS_0_HI 0x000000b7 414 415 #define REG_A3XX_RBBM_PERFCTR_RAS_1_LO 0x000000b8 416 417 #define REG_A3XX_RBBM_PERFCTR_RAS_1_HI 0x000000b9 418 419 #define REG_A3XX_RBBM_PERFCTR_UCHE_0_LO 0x000000ba 420 421 #define REG_A3XX_RBBM_PERFCTR_UCHE_0_HI 0x000000bb 422 423 #define REG_A3XX_RBBM_PERFCTR_UCHE_1_LO 0x000000bc 424 425 #define REG_A3XX_RBBM_PERFCTR_UCHE_1_HI 0x000000bd 426 427 #define REG_A3XX_RBBM_PERFCTR_UCHE_2_LO 0x000000be 428 429 #define REG_A3XX_RBBM_PERFCTR_UCHE_2_HI 0x000000bf 430 431 #define REG_A3XX_RBBM_PERFCTR_UCHE_3_LO 0x000000c0 432 433 #define REG_A3XX_RBBM_PERFCTR_UCHE_3_HI 0x000000c1 434 435 #define REG_A3XX_RBBM_PERFCTR_UCHE_4_LO 0x000000c2 436 437 #define REG_A3XX_RBBM_PERFCTR_UCHE_4_HI 0x000000c3 438 439 #define REG_A3XX_RBBM_PERFCTR_UCHE_5_LO 0x000000c4 440 441 #define REG_A3XX_RBBM_PERFCTR_UCHE_5_HI 0x000000c5 442 443 #define REG_A3XX_RBBM_PERFCTR_TP_0_LO 0x000000c6 444 445 #define REG_A3XX_RBBM_PERFCTR_TP_0_HI 0x000000c7 446 447 #define REG_A3XX_RBBM_PERFCTR_TP_1_LO 0x000000c8 448 449 #define REG_A3XX_RBBM_PERFCTR_TP_1_HI 0x000000c9 450 451 #define REG_A3XX_RBBM_PERFCTR_TP_2_LO 0x000000ca 452 453 #define REG_A3XX_RBBM_PERFCTR_TP_2_HI 0x000000cb 454 455 #define REG_A3XX_RBBM_PERFCTR_TP_3_LO 0x000000cc 456 457 #define REG_A3XX_RBBM_PERFCTR_TP_3_HI 0x000000cd 458 459 #define REG_A3XX_RBBM_PERFCTR_TP_4_LO 0x000000ce 460 461 #define REG_A3XX_RBBM_PERFCTR_TP_4_HI 0x000000cf 462 463 #define REG_A3XX_RBBM_PERFCTR_TP_5_LO 0x000000d0 464 465 #define REG_A3XX_RBBM_PERFCTR_TP_5_HI 0x000000d1 466 467 #define REG_A3XX_RBBM_PERFCTR_SP_0_LO 0x000000d2 468 469 #define REG_A3XX_RBBM_PERFCTR_SP_0_HI 0x000000d3 470 471 #define REG_A3XX_RBBM_PERFCTR_SP_1_LO 0x000000d4 472 473 #define REG_A3XX_RBBM_PERFCTR_SP_1_HI 0x000000d5 474 475 #define REG_A3XX_RBBM_PERFCTR_SP_2_LO 0x000000d6 476 477 #define REG_A3XX_RBBM_PERFCTR_SP_2_HI 0x000000d7 478 479 #define REG_A3XX_RBBM_PERFCTR_SP_3_LO 0x000000d8 480 481 #define REG_A3XX_RBBM_PERFCTR_SP_3_HI 0x000000d9 482 483 #define REG_A3XX_RBBM_PERFCTR_SP_4_LO 0x000000da 484 485 #define REG_A3XX_RBBM_PERFCTR_SP_4_HI 0x000000db 486 487 #define REG_A3XX_RBBM_PERFCTR_SP_5_LO 0x000000dc 488 489 #define REG_A3XX_RBBM_PERFCTR_SP_5_HI 0x000000dd 490 491 #define REG_A3XX_RBBM_PERFCTR_SP_6_LO 0x000000de 492 493 #define REG_A3XX_RBBM_PERFCTR_SP_6_HI 0x000000df 494 495 #define REG_A3XX_RBBM_PERFCTR_SP_7_LO 0x000000e0 496 497 #define REG_A3XX_RBBM_PERFCTR_SP_7_HI 0x000000e1 498 499 #define REG_A3XX_RBBM_PERFCTR_RB_0_LO 0x000000e2 500 501 #define REG_A3XX_RBBM_PERFCTR_RB_0_HI 0x000000e3 502 503 #define REG_A3XX_RBBM_PERFCTR_RB_1_LO 0x000000e4 504 505 #define REG_A3XX_RBBM_PERFCTR_RB_1_HI 0x000000e5 506 507 #define REG_A3XX_RBBM_PERFCTR_PWR_0_LO 0x000000ea 508 509 #define REG_A3XX_RBBM_PERFCTR_PWR_0_HI 0x000000eb 510 511 #define REG_A3XX_RBBM_PERFCTR_PWR_1_LO 0x000000ec 512 513 #define REG_A3XX_RBBM_PERFCTR_PWR_1_HI 0x000000ed 514 515 #define REG_A3XX_RBBM_RBBM_CTL 0x00000100 516 517 #define REG_A3XX_RBBM_DEBUG_BUS_CTL 0x00000111 518 519 #define REG_A3XX_RBBM_DEBUG_BUS_DATA_STATUS 0x00000112 520 521 #define REG_A3XX_CP_PFP_UCODE_ADDR 0x000001c9 522 523 #define REG_A3XX_CP_PFP_UCODE_DATA 0x000001ca 524 525 #define REG_A3XX_CP_ROQ_ADDR 0x000001cc 526 527 #define REG_A3XX_CP_ROQ_DATA 0x000001cd 528 529 #define REG_A3XX_CP_MERCIU_ADDR 0x000001d1 530 531 #define REG_A3XX_CP_MERCIU_DATA 0x000001d2 532 533 #define REG_A3XX_CP_MERCIU_DATA2 0x000001d3 534 535 #define REG_A3XX_CP_MEQ_ADDR 0x000001da 536 537 #define REG_A3XX_CP_MEQ_DATA 0x000001db 538 539 #define REG_A3XX_CP_PERFCOUNTER_SELECT 0x00000445 540 541 #define REG_A3XX_CP_HW_FAULT 0x0000045c 542 543 #define REG_A3XX_CP_PROTECT_CTRL 0x0000045e 544 545 #define REG_A3XX_CP_PROTECT_STATUS 0x0000045f 546 547 static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; } 548 549 static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; } 550 551 #define REG_A3XX_CP_AHB_FAULT 0x0000054d 552 553 #define REG_A3XX_SP_GLOBAL_MEM_SIZE 0x00000e22 554 555 #define REG_A3XX_SP_GLOBAL_MEM_ADDR 0x00000e23 556 557 #define REG_A3XX_GRAS_CL_CLIP_CNTL 0x00002040 558 #define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER 0x00001000 559 #define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 560 #define A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000 561 #define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE 0x00080000 562 #define A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE 0x00100000 563 #define A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE 0x00200000 564 #define A3XX_GRAS_CL_CLIP_CNTL_ZCOORD 0x00800000 565 #define A3XX_GRAS_CL_CLIP_CNTL_WCOORD 0x01000000 566 #define A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE 0x02000000 567 568 #define REG_A3XX_GRAS_CL_GB_CLIP_ADJ 0x00002044 569 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff 570 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0 571 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) 572 { 573 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; 574 } 575 #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00 576 #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10 577 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) 578 { 579 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; 580 } 581 582 #define REG_A3XX_GRAS_CL_VPORT_XOFFSET 0x00002048 583 #define A3XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff 584 #define A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0 585 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) 586 { 587 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK; 588 } 589 590 #define REG_A3XX_GRAS_CL_VPORT_XSCALE 0x00002049 591 #define A3XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff 592 #define A3XX_GRAS_CL_VPORT_XSCALE__SHIFT 0 593 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) 594 { 595 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK; 596 } 597 598 #define REG_A3XX_GRAS_CL_VPORT_YOFFSET 0x0000204a 599 #define A3XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff 600 #define A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0 601 static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val) 602 { 603 return ((fui(val)) << A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_YOFFSET__MASK; 604 } 605 606 #define REG_A3XX_GRAS_CL_VPORT_YSCALE 0x0000204b 607 #define A3XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff 608 #define A3XX_GRAS_CL_VPORT_YSCALE__SHIFT 0 609 static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val) 610 { 611 return ((fui(val)) << A3XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_YSCALE__MASK; 612 } 613 614 #define REG_A3XX_GRAS_CL_VPORT_ZOFFSET 0x0000204c 615 #define A3XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff 616 #define A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0 617 static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val) 618 { 619 return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_ZOFFSET__MASK; 620 } 621 622 #define REG_A3XX_GRAS_CL_VPORT_ZSCALE 0x0000204d 623 #define A3XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff 624 #define A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0 625 static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val) 626 { 627 return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_ZSCALE__MASK; 628 } 629 630 #define REG_A3XX_GRAS_SU_POINT_MINMAX 0x00002068 631 #define A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 632 #define A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 633 static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MIN(float val) 634 { 635 return ((((uint32_t)(val * 8.0))) << A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 636 } 637 #define A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 638 #define A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 639 static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MAX(float val) 640 { 641 return ((((uint32_t)(val * 8.0))) << A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 642 } 643 644 #define REG_A3XX_GRAS_SU_POINT_SIZE 0x00002069 645 #define A3XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff 646 #define A3XX_GRAS_SU_POINT_SIZE__SHIFT 0 647 static inline uint32_t A3XX_GRAS_SU_POINT_SIZE(float val) 648 { 649 return ((((uint32_t)(val * 8.0))) << A3XX_GRAS_SU_POINT_SIZE__SHIFT) & A3XX_GRAS_SU_POINT_SIZE__MASK; 650 } 651 652 #define REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000206c 653 #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK 0x00ffffff 654 #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT 0 655 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val) 656 { 657 return ((((uint32_t)(val * 40.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK; 658 } 659 660 #define REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000206d 661 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 662 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 663 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 664 { 665 return ((((uint32_t)(val * 44.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 666 } 667 668 #define REG_A3XX_GRAS_SU_MODE_CONTROL 0x00002070 669 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001 670 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002 671 #define A3XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004 672 #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8 673 #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3 674 static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) 675 { 676 return ((((uint32_t)(val * 4.0))) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; 677 } 678 #define A3XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800 679 680 #define REG_A3XX_GRAS_SC_CONTROL 0x00002072 681 #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x000000f0 682 #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 4 683 static inline uint32_t A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) 684 { 685 return ((val) << A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK; 686 } 687 #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000f00 688 #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 8 689 static inline uint32_t A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val) 690 { 691 return ((val) << A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK; 692 } 693 #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000 694 #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12 695 static inline uint32_t A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) 696 { 697 return ((val) << A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK; 698 } 699 700 #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL 0x00002074 701 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 702 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 703 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 704 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 705 { 706 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; 707 } 708 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 709 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 710 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 711 { 712 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; 713 } 714 715 #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_BR 0x00002075 716 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 717 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 718 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 719 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 720 { 721 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; 722 } 723 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 724 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 725 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 726 { 727 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; 728 } 729 730 #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL 0x00002079 731 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 732 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 733 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 734 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 735 { 736 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 737 } 738 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 739 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 740 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 741 { 742 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 743 } 744 745 #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000207a 746 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 747 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 748 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 749 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 750 { 751 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 752 } 753 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 754 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 755 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 756 { 757 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 758 } 759 760 #define REG_A3XX_RB_MODE_CONTROL 0x000020c0 761 #define A3XX_RB_MODE_CONTROL_GMEM_BYPASS 0x00000080 762 #define A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK 0x00000700 763 #define A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT 8 764 static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val) 765 { 766 return ((val) << A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT) & A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK; 767 } 768 #define A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE 0x00008000 769 #define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE 0x00010000 770 771 #define REG_A3XX_RB_RENDER_CONTROL 0x000020c1 772 #define A3XX_RB_RENDER_CONTROL_FACENESS 0x00000008 773 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK 0x00000ff0 774 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT 4 775 static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val) 776 { 777 return ((val >> 5) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK; 778 } 779 #define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00001000 780 #define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM 0x00002000 781 #define A3XX_RB_RENDER_CONTROL_XCOORD 0x00004000 782 #define A3XX_RB_RENDER_CONTROL_YCOORD 0x00008000 783 #define A3XX_RB_RENDER_CONTROL_ZCOORD 0x00010000 784 #define A3XX_RB_RENDER_CONTROL_WCOORD 0x00020000 785 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST 0x00400000 786 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK 0x07000000 787 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT 24 788 static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 789 { 790 return ((val) << A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK; 791 } 792 793 #define REG_A3XX_RB_MSAA_CONTROL 0x000020c2 794 #define A3XX_RB_MSAA_CONTROL_DISABLE 0x00000400 795 #define A3XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000f000 796 #define A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 12 797 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val) 798 { 799 return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLES__MASK; 800 } 801 #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK 0xffff0000 802 #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT 16 803 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val) 804 { 805 return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK; 806 } 807 808 #define REG_A3XX_RB_ALPHA_REF 0x000020c3 809 #define A3XX_RB_ALPHA_REF_UINT__MASK 0x0000ff00 810 #define A3XX_RB_ALPHA_REF_UINT__SHIFT 8 811 static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val) 812 { 813 return ((val) << A3XX_RB_ALPHA_REF_UINT__SHIFT) & A3XX_RB_ALPHA_REF_UINT__MASK; 814 } 815 #define A3XX_RB_ALPHA_REF_FLOAT__MASK 0xffff0000 816 #define A3XX_RB_ALPHA_REF_FLOAT__SHIFT 16 817 static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val) 818 { 819 return ((util_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK; 820 } 821 822 static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; } 823 824 static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; } 825 #define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008 826 #define A3XX_RB_MRT_CONTROL_BLEND 0x00000010 827 #define A3XX_RB_MRT_CONTROL_BLEND2 0x00000020 828 #define A3XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00 829 #define A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8 830 static inline uint32_t A3XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) 831 { 832 return ((val) << A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A3XX_RB_MRT_CONTROL_ROP_CODE__MASK; 833 } 834 #define A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK 0x00003000 835 #define A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT 12 836 static inline uint32_t A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) 837 { 838 return ((val) << A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT) & A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK; 839 } 840 #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000 841 #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24 842 static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 843 { 844 return ((val) << A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 845 } 846 847 static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; } 848 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f 849 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 850 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val) 851 { 852 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 853 } 854 #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0 855 #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6 856 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val) 857 { 858 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 859 } 860 #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00000c00 861 #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 10 862 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 863 { 864 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 865 } 866 #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xfffe0000 867 #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 17 868 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) 869 { 870 return ((val >> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; 871 } 872 873 static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; } 874 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK 0xfffffff0 875 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT 4 876 static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val) 877 { 878 return ((val >> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK; 879 } 880 881 static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; } 882 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 883 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 884 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 885 { 886 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 887 } 888 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 889 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 890 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 891 { 892 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 893 } 894 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 895 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 896 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 897 { 898 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 899 } 900 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 901 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 902 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 903 { 904 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 905 } 906 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 907 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 908 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 909 { 910 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 911 } 912 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 913 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 914 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 915 { 916 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 917 } 918 #define A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE 0x20000000 919 920 #define REG_A3XX_RB_BLEND_RED 0x000020e4 921 #define A3XX_RB_BLEND_RED_UINT__MASK 0x000000ff 922 #define A3XX_RB_BLEND_RED_UINT__SHIFT 0 923 static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val) 924 { 925 return ((val) << A3XX_RB_BLEND_RED_UINT__SHIFT) & A3XX_RB_BLEND_RED_UINT__MASK; 926 } 927 #define A3XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 928 #define A3XX_RB_BLEND_RED_FLOAT__SHIFT 16 929 static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val) 930 { 931 return ((util_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK; 932 } 933 934 #define REG_A3XX_RB_BLEND_GREEN 0x000020e5 935 #define A3XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff 936 #define A3XX_RB_BLEND_GREEN_UINT__SHIFT 0 937 static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val) 938 { 939 return ((val) << A3XX_RB_BLEND_GREEN_UINT__SHIFT) & A3XX_RB_BLEND_GREEN_UINT__MASK; 940 } 941 #define A3XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 942 #define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 943 static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val) 944 { 945 return ((util_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK; 946 } 947 948 #define REG_A3XX_RB_BLEND_BLUE 0x000020e6 949 #define A3XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff 950 #define A3XX_RB_BLEND_BLUE_UINT__SHIFT 0 951 static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val) 952 { 953 return ((val) << A3XX_RB_BLEND_BLUE_UINT__SHIFT) & A3XX_RB_BLEND_BLUE_UINT__MASK; 954 } 955 #define A3XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 956 #define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 957 static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val) 958 { 959 return ((util_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK; 960 } 961 962 #define REG_A3XX_RB_BLEND_ALPHA 0x000020e7 963 #define A3XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff 964 #define A3XX_RB_BLEND_ALPHA_UINT__SHIFT 0 965 static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val) 966 { 967 return ((val) << A3XX_RB_BLEND_ALPHA_UINT__SHIFT) & A3XX_RB_BLEND_ALPHA_UINT__MASK; 968 } 969 #define A3XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 970 #define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 971 static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val) 972 { 973 return ((util_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK; 974 } 975 976 #define REG_A3XX_RB_CLEAR_COLOR_DW0 0x000020e8 977 978 #define REG_A3XX_RB_CLEAR_COLOR_DW1 0x000020e9 979 980 #define REG_A3XX_RB_CLEAR_COLOR_DW2 0x000020ea 981 982 #define REG_A3XX_RB_CLEAR_COLOR_DW3 0x000020eb 983 984 #define REG_A3XX_RB_COPY_CONTROL 0x000020ec 985 #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003 986 #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0 987 static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) 988 { 989 return ((val) << A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK; 990 } 991 #define A3XX_RB_COPY_CONTROL_DEPTHCLEAR 0x00000008 992 #define A3XX_RB_COPY_CONTROL_MODE__MASK 0x00000070 993 #define A3XX_RB_COPY_CONTROL_MODE__SHIFT 4 994 static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) 995 { 996 return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK; 997 } 998 #define A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00 999 #define A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8 1000 static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) 1001 { 1002 return ((val) << A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK; 1003 } 1004 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000 1005 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14 1006 static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) 1007 { 1008 return ((val >> 14) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK; 1009 } 1010 1011 #define REG_A3XX_RB_COPY_DEST_BASE 0x000020ed 1012 #define A3XX_RB_COPY_DEST_BASE_BASE__MASK 0xfffffff0 1013 #define A3XX_RB_COPY_DEST_BASE_BASE__SHIFT 4 1014 static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val) 1015 { 1016 return ((val >> 5) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A3XX_RB_COPY_DEST_BASE_BASE__MASK; 1017 } 1018 1019 #define REG_A3XX_RB_COPY_DEST_PITCH 0x000020ee 1020 #define A3XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff 1021 #define A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0 1022 static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) 1023 { 1024 return ((val >> 5) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK; 1025 } 1026 1027 #define REG_A3XX_RB_COPY_DEST_INFO 0x000020ef 1028 #define A3XX_RB_COPY_DEST_INFO_TILE__MASK 0x00000003 1029 #define A3XX_RB_COPY_DEST_INFO_TILE__SHIFT 0 1030 static inline uint32_t A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val) 1031 { 1032 return ((val) << A3XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A3XX_RB_COPY_DEST_INFO_TILE__MASK; 1033 } 1034 #define A3XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc 1035 #define A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2 1036 static inline uint32_t A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val) 1037 { 1038 return ((val) << A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A3XX_RB_COPY_DEST_INFO_FORMAT__MASK; 1039 } 1040 #define A3XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 1041 #define A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 1042 static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) 1043 { 1044 return ((val) << A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A3XX_RB_COPY_DEST_INFO_SWAP__MASK; 1045 } 1046 #define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 1047 #define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 1048 static inline uint32_t A3XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 1049 { 1050 return ((val) << A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 1051 } 1052 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000 1053 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14 1054 static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) 1055 { 1056 return ((val) << A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK; 1057 } 1058 #define A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000 1059 #define A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18 1060 static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) 1061 { 1062 return ((val) << A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK; 1063 } 1064 1065 #define REG_A3XX_RB_DEPTH_CONTROL 0x00002100 1066 #define A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001 1067 #define A3XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002 1068 #define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004 1069 #define A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00000008 1070 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070 1071 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4 1072 static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) 1073 { 1074 return ((val) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK; 1075 } 1076 #define A3XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080 1077 #define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000 1078 1079 #define REG_A3XX_RB_DEPTH_CLEAR 0x00002101 1080 1081 #define REG_A3XX_RB_DEPTH_INFO 0x00002102 1082 #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001 1083 #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 1084 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) 1085 { 1086 return ((val) << A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 1087 } 1088 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff800 1089 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 11 1090 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 1091 { 1092 return ((val >> 12) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 1093 } 1094 1095 #define REG_A3XX_RB_DEPTH_PITCH 0x00002103 1096 #define A3XX_RB_DEPTH_PITCH__MASK 0xffffffff 1097 #define A3XX_RB_DEPTH_PITCH__SHIFT 0 1098 static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val) 1099 { 1100 return ((val >> 3) << A3XX_RB_DEPTH_PITCH__SHIFT) & A3XX_RB_DEPTH_PITCH__MASK; 1101 } 1102 1103 #define REG_A3XX_RB_STENCIL_CONTROL 0x00002104 1104 #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 1105 #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 1106 #define A3XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 1107 #define A3XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 1108 #define A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 1109 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 1110 { 1111 return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC__MASK; 1112 } 1113 #define A3XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 1114 #define A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 1115 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 1116 { 1117 return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL__MASK; 1118 } 1119 #define A3XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 1120 #define A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 1121 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 1122 { 1123 return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS__MASK; 1124 } 1125 #define A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 1126 #define A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 1127 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 1128 { 1129 return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 1130 } 1131 #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 1132 #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 1133 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 1134 { 1135 return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 1136 } 1137 #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 1138 #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 1139 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 1140 { 1141 return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 1142 } 1143 #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 1144 #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 1145 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 1146 { 1147 return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 1148 } 1149 #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 1150 #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 1151 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 1152 { 1153 return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 1154 } 1155 1156 #define REG_A3XX_RB_STENCIL_CLEAR 0x00002105 1157 1158 #define REG_A3XX_RB_STENCIL_BUF_INFO 0x00002106 1159 1160 #define REG_A3XX_RB_STENCIL_BUF_PITCH 0x00002107 1161 1162 #define REG_A3XX_RB_STENCILREFMASK 0x00002108 1163 #define A3XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 1164 #define A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 1165 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 1166 { 1167 return ((val) << A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILREF__MASK; 1168 } 1169 #define A3XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 1170 #define A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 1171 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 1172 { 1173 return ((val) << A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILMASK__MASK; 1174 } 1175 #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 1176 #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 1177 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 1178 { 1179 return ((val) << A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 1180 } 1181 1182 #define REG_A3XX_RB_STENCILREFMASK_BF 0x00002109 1183 #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 1184 #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 1185 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 1186 { 1187 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 1188 } 1189 #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 1190 #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 1191 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 1192 { 1193 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 1194 } 1195 #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 1196 #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 1197 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 1198 { 1199 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 1200 } 1201 1202 #define REG_A3XX_RB_LRZ_VSC_CONTROL 0x0000210c 1203 #define A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE 0x00000002 1204 1205 #define REG_A3XX_RB_WINDOW_OFFSET 0x0000210e 1206 #define A3XX_RB_WINDOW_OFFSET_X__MASK 0x0000ffff 1207 #define A3XX_RB_WINDOW_OFFSET_X__SHIFT 0 1208 static inline uint32_t A3XX_RB_WINDOW_OFFSET_X(uint32_t val) 1209 { 1210 return ((val) << A3XX_RB_WINDOW_OFFSET_X__SHIFT) & A3XX_RB_WINDOW_OFFSET_X__MASK; 1211 } 1212 #define A3XX_RB_WINDOW_OFFSET_Y__MASK 0xffff0000 1213 #define A3XX_RB_WINDOW_OFFSET_Y__SHIFT 16 1214 static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val) 1215 { 1216 return ((val) << A3XX_RB_WINDOW_OFFSET_Y__SHIFT) & A3XX_RB_WINDOW_OFFSET_Y__MASK; 1217 } 1218 1219 #define REG_A3XX_RB_SAMPLE_COUNT_CONTROL 0x00002110 1220 #define A3XX_RB_SAMPLE_COUNT_CONTROL_RESET 0x00000001 1221 #define A3XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 1222 1223 #define REG_A3XX_RB_SAMPLE_COUNT_ADDR 0x00002111 1224 1225 #define REG_A3XX_RB_Z_CLAMP_MIN 0x00002114 1226 1227 #define REG_A3XX_RB_Z_CLAMP_MAX 0x00002115 1228 1229 #define REG_A3XX_VGT_BIN_BASE 0x000021e1 1230 1231 #define REG_A3XX_VGT_BIN_SIZE 0x000021e2 1232 1233 #define REG_A3XX_PC_VSTREAM_CONTROL 0x000021e4 1234 #define A3XX_PC_VSTREAM_CONTROL_SIZE__MASK 0x003f0000 1235 #define A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT 16 1236 static inline uint32_t A3XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val) 1237 { 1238 return ((val) << A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A3XX_PC_VSTREAM_CONTROL_SIZE__MASK; 1239 } 1240 #define A3XX_PC_VSTREAM_CONTROL_N__MASK 0x07c00000 1241 #define A3XX_PC_VSTREAM_CONTROL_N__SHIFT 22 1242 static inline uint32_t A3XX_PC_VSTREAM_CONTROL_N(uint32_t val) 1243 { 1244 return ((val) << A3XX_PC_VSTREAM_CONTROL_N__SHIFT) & A3XX_PC_VSTREAM_CONTROL_N__MASK; 1245 } 1246 1247 #define REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL 0x000021ea 1248 1249 #define REG_A3XX_PC_PRIM_VTX_CNTL 0x000021ec 1250 #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK 0x0000001f 1251 #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT 0 1252 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val) 1253 { 1254 return ((val) << A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK; 1255 } 1256 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK 0x000000e0 1257 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT 5 1258 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 1259 { 1260 return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK; 1261 } 1262 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK 0x00000700 1263 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT 8 1264 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 1265 { 1266 return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK; 1267 } 1268 #define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000 1269 #define A3XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000 1270 1271 #define REG_A3XX_PC_RESTART_INDEX 0x000021ed 1272 1273 #define REG_A3XX_HLSQ_CONTROL_0_REG 0x00002200 1274 #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010 1275 #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4 1276 static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) 1277 { 1278 return ((val) << A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; 1279 } 1280 #define A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040 1281 #define A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200 1282 #define A3XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400 1283 #define A3XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000 1284 #define A3XX_HLSQ_CONTROL_0_REG_CONSTSWITCHMODE 0x08000000 1285 #define A3XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000 1286 #define A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000 1287 #define A3XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000 1288 #define A3XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000 1289 1290 #define REG_A3XX_HLSQ_CONTROL_1_REG 0x00002201 1291 #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040 1292 #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6 1293 static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) 1294 { 1295 return ((val) << A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK; 1296 } 1297 #define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100 1298 #define A3XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200 1299 #define A3XX_HLSQ_CONTROL_1_REG_ZWCOORD 0x02000000 1300 1301 #define REG_A3XX_HLSQ_CONTROL_2_REG 0x00002202 1302 #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000 1303 #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26 1304 static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) 1305 { 1306 return ((val) << A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK; 1307 } 1308 1309 #define REG_A3XX_HLSQ_CONTROL_3_REG 0x00002203 1310 #define A3XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff 1311 #define A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0 1312 static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val) 1313 { 1314 return ((val) << A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_REGID__MASK; 1315 } 1316 1317 #define REG_A3XX_HLSQ_VS_CONTROL_REG 0x00002204 1318 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff 1319 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0 1320 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) 1321 { 1322 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK; 1323 } 1324 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000 1325 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12 1326 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) 1327 { 1328 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK; 1329 } 1330 #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 1331 #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24 1332 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) 1333 { 1334 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK; 1335 } 1336 1337 #define REG_A3XX_HLSQ_FS_CONTROL_REG 0x00002205 1338 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff 1339 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0 1340 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) 1341 { 1342 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK; 1343 } 1344 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000 1345 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12 1346 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) 1347 { 1348 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK; 1349 } 1350 #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 1351 #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24 1352 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) 1353 { 1354 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK; 1355 } 1356 1357 #define REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG 0x00002206 1358 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff 1359 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT 0 1360 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val) 1361 { 1362 return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK; 1363 } 1364 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000 1365 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT 16 1366 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val) 1367 { 1368 return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK; 1369 } 1370 1371 #define REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG 0x00002207 1372 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff 1373 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT 0 1374 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val) 1375 { 1376 return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK; 1377 } 1378 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000 1379 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT 16 1380 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val) 1381 { 1382 return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK; 1383 } 1384 1385 #define REG_A3XX_HLSQ_CL_NDRANGE_0_REG 0x0000220a 1386 #define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK 0x00000003 1387 #define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT 0 1388 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM(uint32_t val) 1389 { 1390 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK; 1391 } 1392 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK 0x00000ffc 1393 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT 2 1394 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0(uint32_t val) 1395 { 1396 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK; 1397 } 1398 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK 0x003ff000 1399 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT 12 1400 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1(uint32_t val) 1401 { 1402 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK; 1403 } 1404 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK 0xffc00000 1405 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT 22 1406 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2(uint32_t val) 1407 { 1408 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK; 1409 } 1410 1411 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK(uint32_t i0) { return 0x0000220b + 0x2*i0; } 1412 1413 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0; } 1414 1415 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { return 0x0000220c + 0x2*i0; } 1416 1417 #define REG_A3XX_HLSQ_CL_CONTROL_0_REG 0x00002211 1418 1419 #define REG_A3XX_HLSQ_CL_CONTROL_1_REG 0x00002212 1420 1421 #define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG 0x00002214 1422 1423 static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP(uint32_t i0) { return 0x00002215 + 0x1*i0; } 1424 1425 static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO(uint32_t i0) { return 0x00002215 + 0x1*i0; } 1426 1427 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Y_REG 0x00002216 1428 1429 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG 0x00002217 1430 1431 #define REG_A3XX_HLSQ_CL_WG_OFFSET_REG 0x0000221a 1432 1433 #define REG_A3XX_VFD_CONTROL_0 0x00002240 1434 #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x0003ffff 1435 #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0 1436 static inline uint32_t A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) 1437 { 1438 return ((val) << A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK; 1439 } 1440 #define A3XX_VFD_CONTROL_0_PACKETSIZE__MASK 0x003c0000 1441 #define A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT 18 1442 static inline uint32_t A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val) 1443 { 1444 return ((val) << A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT) & A3XX_VFD_CONTROL_0_PACKETSIZE__MASK; 1445 } 1446 #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x07c00000 1447 #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 22 1448 static inline uint32_t A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) 1449 { 1450 return ((val) << A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK; 1451 } 1452 #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xf8000000 1453 #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 27 1454 static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) 1455 { 1456 return ((val) << A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK; 1457 } 1458 1459 #define REG_A3XX_VFD_CONTROL_1 0x00002241 1460 #define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff 1461 #define A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0 1462 static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) 1463 { 1464 return ((val) << A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK; 1465 } 1466 #define A3XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000 1467 #define A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16 1468 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 1469 { 1470 return ((val) << A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A3XX_VFD_CONTROL_1_REGID4VTX__MASK; 1471 } 1472 #define A3XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000 1473 #define A3XX_VFD_CONTROL_1_REGID4INST__SHIFT 24 1474 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 1475 { 1476 return ((val) << A3XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A3XX_VFD_CONTROL_1_REGID4INST__MASK; 1477 } 1478 1479 #define REG_A3XX_VFD_INDEX_MIN 0x00002242 1480 1481 #define REG_A3XX_VFD_INDEX_MAX 0x00002243 1482 1483 #define REG_A3XX_VFD_INSTANCEID_OFFSET 0x00002244 1484 1485 #define REG_A3XX_VFD_INDEX_OFFSET 0x00002245 1486 1487 static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0) { return 0x00002246 + 0x2*i0; } 1488 1489 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; } 1490 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f 1491 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0 1492 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) 1493 { 1494 return ((val) << A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK; 1495 } 1496 #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80 1497 #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7 1498 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) 1499 { 1500 return ((val) << A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK; 1501 } 1502 #define A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00020000 1503 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK 0x00fc0000 1504 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT 18 1505 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val) 1506 { 1507 return ((val) << A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK; 1508 } 1509 #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK 0xff000000 1510 #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT 24 1511 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val) 1512 { 1513 return ((val) << A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK; 1514 } 1515 1516 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x00002247 + 0x2*i0; } 1517 1518 static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0) { return 0x00002266 + 0x1*i0; } 1519 1520 static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x00002266 + 0x1*i0; } 1521 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f 1522 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0 1523 static inline uint32_t A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) 1524 { 1525 return ((val) << A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK; 1526 } 1527 #define A3XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010 1528 #define A3XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0 1529 #define A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6 1530 static inline uint32_t A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val) 1531 { 1532 return ((val) << A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A3XX_VFD_DECODE_INSTR_FORMAT__MASK; 1533 } 1534 #define A3XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000 1535 #define A3XX_VFD_DECODE_INSTR_REGID__SHIFT 12 1536 static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val) 1537 { 1538 return ((val) << A3XX_VFD_DECODE_INSTR_REGID__SHIFT) & A3XX_VFD_DECODE_INSTR_REGID__MASK; 1539 } 1540 #define A3XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000 1541 #define A3XX_VFD_DECODE_INSTR_SWAP__SHIFT 22 1542 static inline uint32_t A3XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 1543 { 1544 return ((val) << A3XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A3XX_VFD_DECODE_INSTR_SWAP__MASK; 1545 } 1546 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000 1547 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24 1548 static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) 1549 { 1550 return ((val) << A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK; 1551 } 1552 #define A3XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000 1553 #define A3XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000 1554 1555 #define REG_A3XX_VFD_VS_THREADING_THRESHOLD 0x0000227e 1556 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK 0x0000000f 1557 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT 0 1558 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val) 1559 { 1560 return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK; 1561 } 1562 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK 0x0000ff00 1563 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT 8 1564 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val) 1565 { 1566 return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK; 1567 } 1568 1569 #define REG_A3XX_VPC_ATTR 0x00002280 1570 #define A3XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff 1571 #define A3XX_VPC_ATTR_TOTALATTR__SHIFT 0 1572 static inline uint32_t A3XX_VPC_ATTR_TOTALATTR(uint32_t val) 1573 { 1574 return ((val) << A3XX_VPC_ATTR_TOTALATTR__SHIFT) & A3XX_VPC_ATTR_TOTALATTR__MASK; 1575 } 1576 #define A3XX_VPC_ATTR_PSIZE 0x00000200 1577 #define A3XX_VPC_ATTR_THRDASSIGN__MASK 0x0ffff000 1578 #define A3XX_VPC_ATTR_THRDASSIGN__SHIFT 12 1579 static inline uint32_t A3XX_VPC_ATTR_THRDASSIGN(uint32_t val) 1580 { 1581 return ((val) << A3XX_VPC_ATTR_THRDASSIGN__SHIFT) & A3XX_VPC_ATTR_THRDASSIGN__MASK; 1582 } 1583 #define A3XX_VPC_ATTR_LMSIZE__MASK 0xf0000000 1584 #define A3XX_VPC_ATTR_LMSIZE__SHIFT 28 1585 static inline uint32_t A3XX_VPC_ATTR_LMSIZE(uint32_t val) 1586 { 1587 return ((val) << A3XX_VPC_ATTR_LMSIZE__SHIFT) & A3XX_VPC_ATTR_LMSIZE__MASK; 1588 } 1589 1590 #define REG_A3XX_VPC_PACK 0x00002281 1591 #define A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00 1592 #define A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8 1593 static inline uint32_t A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) 1594 { 1595 return ((val) << A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK; 1596 } 1597 #define A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000 1598 #define A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16 1599 static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) 1600 { 1601 return ((val) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK; 1602 } 1603 1604 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002282 + 0x1*i0; } 1605 1606 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002282 + 0x1*i0; } 1607 1608 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; } 1609 1610 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; } 1611 1612 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0 0x0000228a 1613 1614 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_1 0x0000228b 1615 1616 #define REG_A3XX_SP_SP_CTRL_REG 0x000022c0 1617 #define A3XX_SP_SP_CTRL_REG_RESOLVE 0x00010000 1618 #define A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK 0x00040000 1619 #define A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT 18 1620 static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val) 1621 { 1622 return ((val) << A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK; 1623 } 1624 #define A3XX_SP_SP_CTRL_REG_BINNING 0x00080000 1625 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK 0x00300000 1626 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT 20 1627 static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val) 1628 { 1629 return ((val) << A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK; 1630 } 1631 #define A3XX_SP_SP_CTRL_REG_L0MODE__MASK 0x00c00000 1632 #define A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT 22 1633 static inline uint32_t A3XX_SP_SP_CTRL_REG_L0MODE(uint32_t val) 1634 { 1635 return ((val) << A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT) & A3XX_SP_SP_CTRL_REG_L0MODE__MASK; 1636 } 1637 1638 #define REG_A3XX_SP_VS_CTRL_REG0 0x000022c4 1639 #define A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 1640 #define A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 1641 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 1642 { 1643 return ((val) << A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK; 1644 } 1645 #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002 1646 #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1 1647 static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) 1648 { 1649 return ((val) << A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK; 1650 } 1651 #define A3XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004 1652 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 1653 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 1654 static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 1655 { 1656 return ((val) << A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 1657 } 1658 #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 1659 #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 1660 static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 1661 { 1662 return ((val) << A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 1663 } 1664 #define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 1665 #define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 1666 static inline uint32_t A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 1667 { 1668 return ((val) << A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK; 1669 } 1670 #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000 1671 #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20 1672 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 1673 { 1674 return ((val) << A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; 1675 } 1676 #define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000 1677 #define A3XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000 1678 #define A3XX_SP_VS_CTRL_REG0_COMPUTEMODE 0x00800000 1679 #define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK 0xff000000 1680 #define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT 24 1681 static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val) 1682 { 1683 return ((val) << A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG0_LENGTH__MASK; 1684 } 1685 1686 #define REG_A3XX_SP_VS_CTRL_REG1 0x000022c5 1687 #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff 1688 #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0 1689 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) 1690 { 1691 return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK; 1692 } 1693 #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00 1694 #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10 1695 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) 1696 { 1697 return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK; 1698 } 1699 #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x3f000000 1700 #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24 1701 static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) 1702 { 1703 return ((val) << A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK; 1704 } 1705 1706 #define REG_A3XX_SP_VS_PARAM_REG 0x000022c6 1707 #define A3XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff 1708 #define A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0 1709 static inline uint32_t A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) 1710 { 1711 return ((val) << A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_POSREGID__MASK; 1712 } 1713 #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00 1714 #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8 1715 static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) 1716 { 1717 return ((val) << A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK; 1718 } 1719 #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000 1720 #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20 1721 static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) 1722 { 1723 return ((val) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; 1724 } 1725 1726 static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 1727 1728 static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 1729 #define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff 1730 #define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 1731 static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 1732 { 1733 return ((val) << A3XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_A_REGID__MASK; 1734 } 1735 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00 1736 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9 1737 static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 1738 { 1739 return ((val) << A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 1740 } 1741 #define A3XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000 1742 #define A3XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 1743 static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 1744 { 1745 return ((val) << A3XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_B_REGID__MASK; 1746 } 1747 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000 1748 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25 1749 static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 1750 { 1751 return ((val) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 1752 } 1753 1754 static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; } 1755 1756 static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; } 1757 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 1758 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 1759 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 1760 { 1761 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 1762 } 1763 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 1764 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 1765 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 1766 { 1767 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 1768 } 1769 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 1770 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 1771 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 1772 { 1773 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 1774 } 1775 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 1776 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 1777 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 1778 { 1779 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 1780 } 1781 1782 #define REG_A3XX_SP_VS_OBJ_OFFSET_REG 0x000022d4 1783 #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1784 #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1785 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1786 { 1787 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1788 } 1789 #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1790 #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1791 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1792 { 1793 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1794 } 1795 1796 #define REG_A3XX_SP_VS_OBJ_START_REG 0x000022d5 1797 1798 #define REG_A3XX_SP_VS_PVT_MEM_PARAM_REG 0x000022d6 1799 1800 #define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG 0x000022d7 1801 1802 #define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG 0x000022d8 1803 1804 #define REG_A3XX_SP_VS_LENGTH_REG 0x000022df 1805 #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff 1806 #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT 0 1807 static inline uint32_t A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val) 1808 { 1809 return ((val) << A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK; 1810 } 1811 1812 #define REG_A3XX_SP_FS_CTRL_REG0 0x000022e0 1813 #define A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 1814 #define A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 1815 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 1816 { 1817 return ((val) << A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK; 1818 } 1819 #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002 1820 #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1 1821 static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) 1822 { 1823 return ((val) << A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK; 1824 } 1825 #define A3XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004 1826 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 1827 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 1828 static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 1829 { 1830 return ((val) << A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 1831 } 1832 #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 1833 #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 1834 static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 1835 { 1836 return ((val) << A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 1837 } 1838 #define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 1839 #define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 1840 static inline uint32_t A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 1841 { 1842 return ((val) << A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK; 1843 } 1844 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 1845 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 1846 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 1847 { 1848 return ((val) << A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 1849 } 1850 #define A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000 1851 #define A3XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000 1852 #define A3XX_SP_FS_CTRL_REG0_COMPUTEMODE 0x00800000 1853 #define A3XX_SP_FS_CTRL_REG0_LENGTH__MASK 0xff000000 1854 #define A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT 24 1855 static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val) 1856 { 1857 return ((val) << A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG0_LENGTH__MASK; 1858 } 1859 1860 #define REG_A3XX_SP_FS_CTRL_REG1 0x000022e1 1861 #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff 1862 #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0 1863 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) 1864 { 1865 return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK; 1866 } 1867 #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00 1868 #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10 1869 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) 1870 { 1871 return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK; 1872 } 1873 #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x00f00000 1874 #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 20 1875 static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) 1876 { 1877 return ((val) << A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK; 1878 } 1879 #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK 0x3f000000 1880 #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT 24 1881 static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val) 1882 { 1883 return ((val) << A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT) & A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK; 1884 } 1885 1886 #define REG_A3XX_SP_FS_OBJ_OFFSET_REG 0x000022e2 1887 #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1888 #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1889 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1890 { 1891 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1892 } 1893 #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1894 #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1895 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1896 { 1897 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1898 } 1899 1900 #define REG_A3XX_SP_FS_OBJ_START_REG 0x000022e3 1901 1902 #define REG_A3XX_SP_FS_PVT_MEM_PARAM_REG 0x000022e4 1903 1904 #define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG 0x000022e5 1905 1906 #define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG 0x000022e6 1907 1908 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0 0x000022e8 1909 1910 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1 0x000022e9 1911 1912 #define REG_A3XX_SP_FS_OUTPUT_REG 0x000022ec 1913 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080 1914 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00 1915 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8 1916 static inline uint32_t A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) 1917 { 1918 return ((val) << A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK; 1919 } 1920 1921 static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0) { return 0x000022f0 + 0x1*i0; } 1922 1923 static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f0 + 0x1*i0; } 1924 #define A3XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff 1925 #define A3XX_SP_FS_MRT_REG_REGID__SHIFT 0 1926 static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val) 1927 { 1928 return ((val) << A3XX_SP_FS_MRT_REG_REGID__SHIFT) & A3XX_SP_FS_MRT_REG_REGID__MASK; 1929 } 1930 #define A3XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100 1931 1932 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0) { return 0x000022f4 + 0x1*i0; } 1933 1934 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0) { return 0x000022f4 + 0x1*i0; } 1935 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK 0x0000003f 1936 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT 0 1937 static inline uint32_t A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val) 1938 { 1939 return ((val) << A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT) & A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK; 1940 } 1941 1942 #define REG_A3XX_SP_FS_LENGTH_REG 0x000022ff 1943 #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff 1944 #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT 0 1945 static inline uint32_t A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val) 1946 { 1947 return ((val) << A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK; 1948 } 1949 1950 #define REG_A3XX_TPL1_TP_VS_TEX_OFFSET 0x00002340 1951 #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff 1952 #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0 1953 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) 1954 { 1955 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK; 1956 } 1957 #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00 1958 #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8 1959 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) 1960 { 1961 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK; 1962 } 1963 #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000 1964 #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT 16 1965 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val) 1966 { 1967 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK; 1968 } 1969 1970 #define REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002341 1971 1972 #define REG_A3XX_TPL1_TP_FS_TEX_OFFSET 0x00002342 1973 #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff 1974 #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0 1975 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) 1976 { 1977 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK; 1978 } 1979 #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00 1980 #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8 1981 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) 1982 { 1983 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK; 1984 } 1985 #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000 1986 #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT 16 1987 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val) 1988 { 1989 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK; 1990 } 1991 1992 #define REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x00002343 1993 1994 #define REG_A3XX_VBIF_CLKON 0x00003001 1995 1996 #define REG_A3XX_VBIF_FIXED_SORT_EN 0x0000300c 1997 1998 #define REG_A3XX_VBIF_FIXED_SORT_SEL0 0x0000300d 1999 2000 #define REG_A3XX_VBIF_FIXED_SORT_SEL1 0x0000300e 2001 2002 #define REG_A3XX_VBIF_ABIT_SORT 0x0000301c 2003 2004 #define REG_A3XX_VBIF_ABIT_SORT_CONF 0x0000301d 2005 2006 #define REG_A3XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 2007 2008 #define REG_A3XX_VBIF_IN_RD_LIM_CONF0 0x0000302c 2009 2010 #define REG_A3XX_VBIF_IN_RD_LIM_CONF1 0x0000302d 2011 2012 #define REG_A3XX_VBIF_IN_WR_LIM_CONF0 0x00003030 2013 2014 #define REG_A3XX_VBIF_IN_WR_LIM_CONF1 0x00003031 2015 2016 #define REG_A3XX_VBIF_OUT_RD_LIM_CONF0 0x00003034 2017 2018 #define REG_A3XX_VBIF_OUT_WR_LIM_CONF0 0x00003035 2019 2020 #define REG_A3XX_VBIF_DDR_OUT_MAX_BURST 0x00003036 2021 2022 #define REG_A3XX_VBIF_ARB_CTL 0x0000303c 2023 2024 #define REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049 2025 2026 #define REG_A3XX_VBIF_OUT_AXI_AMEMTYPE_CONF0 0x00003058 2027 2028 #define REG_A3XX_VBIF_OUT_AXI_AOOO_EN 0x0000305e 2029 2030 #define REG_A3XX_VBIF_OUT_AXI_AOOO 0x0000305f 2031 2032 #define REG_A3XX_VBIF_PERF_CNT_EN 0x00003070 2033 #define A3XX_VBIF_PERF_CNT_EN_CNT0 0x00000001 2034 #define A3XX_VBIF_PERF_CNT_EN_CNT1 0x00000002 2035 #define A3XX_VBIF_PERF_CNT_EN_PWRCNT0 0x00000004 2036 #define A3XX_VBIF_PERF_CNT_EN_PWRCNT1 0x00000008 2037 #define A3XX_VBIF_PERF_CNT_EN_PWRCNT2 0x00000010 2038 2039 #define REG_A3XX_VBIF_PERF_CNT_CLR 0x00003071 2040 #define A3XX_VBIF_PERF_CNT_CLR_CNT0 0x00000001 2041 #define A3XX_VBIF_PERF_CNT_CLR_CNT1 0x00000002 2042 #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT0 0x00000004 2043 #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT1 0x00000008 2044 #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT2 0x00000010 2045 2046 #define REG_A3XX_VBIF_PERF_CNT_SEL 0x00003072 2047 2048 #define REG_A3XX_VBIF_PERF_CNT0_LO 0x00003073 2049 2050 #define REG_A3XX_VBIF_PERF_CNT0_HI 0x00003074 2051 2052 #define REG_A3XX_VBIF_PERF_CNT1_LO 0x00003075 2053 2054 #define REG_A3XX_VBIF_PERF_CNT1_HI 0x00003076 2055 2056 #define REG_A3XX_VBIF_PERF_PWR_CNT0_LO 0x00003077 2057 2058 #define REG_A3XX_VBIF_PERF_PWR_CNT0_HI 0x00003078 2059 2060 #define REG_A3XX_VBIF_PERF_PWR_CNT1_LO 0x00003079 2061 2062 #define REG_A3XX_VBIF_PERF_PWR_CNT1_HI 0x0000307a 2063 2064 #define REG_A3XX_VBIF_PERF_PWR_CNT2_LO 0x0000307b 2065 2066 #define REG_A3XX_VBIF_PERF_PWR_CNT2_HI 0x0000307c 2067 2068 #define REG_A3XX_VSC_BIN_SIZE 0x00000c01 2069 #define A3XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 2070 #define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 2071 static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 2072 { 2073 return ((val >> 5) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A3XX_VSC_BIN_SIZE_WIDTH__MASK; 2074 } 2075 #define A3XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 2076 #define A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5 2077 static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 2078 { 2079 return ((val >> 5) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK; 2080 } 2081 2082 #define REG_A3XX_VSC_SIZE_ADDRESS 0x00000c02 2083 2084 static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 2085 2086 static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 2087 #define A3XX_VSC_PIPE_CONFIG_X__MASK 0x000003ff 2088 #define A3XX_VSC_PIPE_CONFIG_X__SHIFT 0 2089 static inline uint32_t A3XX_VSC_PIPE_CONFIG_X(uint32_t val) 2090 { 2091 return ((val) << A3XX_VSC_PIPE_CONFIG_X__SHIFT) & A3XX_VSC_PIPE_CONFIG_X__MASK; 2092 } 2093 #define A3XX_VSC_PIPE_CONFIG_Y__MASK 0x000ffc00 2094 #define A3XX_VSC_PIPE_CONFIG_Y__SHIFT 10 2095 static inline uint32_t A3XX_VSC_PIPE_CONFIG_Y(uint32_t val) 2096 { 2097 return ((val) << A3XX_VSC_PIPE_CONFIG_Y__SHIFT) & A3XX_VSC_PIPE_CONFIG_Y__MASK; 2098 } 2099 #define A3XX_VSC_PIPE_CONFIG_W__MASK 0x00f00000 2100 #define A3XX_VSC_PIPE_CONFIG_W__SHIFT 20 2101 static inline uint32_t A3XX_VSC_PIPE_CONFIG_W(uint32_t val) 2102 { 2103 return ((val) << A3XX_VSC_PIPE_CONFIG_W__SHIFT) & A3XX_VSC_PIPE_CONFIG_W__MASK; 2104 } 2105 #define A3XX_VSC_PIPE_CONFIG_H__MASK 0x0f000000 2106 #define A3XX_VSC_PIPE_CONFIG_H__SHIFT 24 2107 static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val) 2108 { 2109 return ((val) << A3XX_VSC_PIPE_CONFIG_H__SHIFT) & A3XX_VSC_PIPE_CONFIG_H__MASK; 2110 } 2111 2112 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } 2113 2114 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } 2115 2116 #define REG_A3XX_VSC_BIN_CONTROL 0x00000c3c 2117 #define A3XX_VSC_BIN_CONTROL_BINNING_ENABLE 0x00000001 2118 2119 #define REG_A3XX_UNKNOWN_0C3D 0x00000c3d 2120 2121 #define REG_A3XX_PC_PERFCOUNTER0_SELECT 0x00000c48 2122 2123 #define REG_A3XX_PC_PERFCOUNTER1_SELECT 0x00000c49 2124 2125 #define REG_A3XX_PC_PERFCOUNTER2_SELECT 0x00000c4a 2126 2127 #define REG_A3XX_PC_PERFCOUNTER3_SELECT 0x00000c4b 2128 2129 #define REG_A3XX_GRAS_TSE_DEBUG_ECO 0x00000c81 2130 2131 #define REG_A3XX_GRAS_PERFCOUNTER0_SELECT 0x00000c88 2132 2133 #define REG_A3XX_GRAS_PERFCOUNTER1_SELECT 0x00000c89 2134 2135 #define REG_A3XX_GRAS_PERFCOUNTER2_SELECT 0x00000c8a 2136 2137 #define REG_A3XX_GRAS_PERFCOUNTER3_SELECT 0x00000c8b 2138 2139 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } 2140 2141 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } 2142 2143 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0) { return 0x00000ca1 + 0x4*i0; } 2144 2145 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0) { return 0x00000ca2 + 0x4*i0; } 2146 2147 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) { return 0x00000ca3 + 0x4*i0; } 2148 2149 #define REG_A3XX_RB_GMEM_BASE_ADDR 0x00000cc0 2150 2151 #define REG_A3XX_RB_DEBUG_ECO_CONTROLS_ADDR 0x00000cc1 2152 2153 #define REG_A3XX_RB_PERFCOUNTER0_SELECT 0x00000cc6 2154 2155 #define REG_A3XX_RB_PERFCOUNTER1_SELECT 0x00000cc7 2156 2157 #define REG_A3XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0 2158 #define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff 2159 #define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0 2160 static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) 2161 { 2162 return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK; 2163 } 2164 #define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x0fffc000 2165 #define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 14 2166 static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) 2167 { 2168 return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK; 2169 } 2170 2171 #define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT 0x00000e00 2172 2173 #define REG_A3XX_HLSQ_PERFCOUNTER1_SELECT 0x00000e01 2174 2175 #define REG_A3XX_HLSQ_PERFCOUNTER2_SELECT 0x00000e02 2176 2177 #define REG_A3XX_HLSQ_PERFCOUNTER3_SELECT 0x00000e03 2178 2179 #define REG_A3XX_HLSQ_PERFCOUNTER4_SELECT 0x00000e04 2180 2181 #define REG_A3XX_HLSQ_PERFCOUNTER5_SELECT 0x00000e05 2182 2183 #define REG_A3XX_UNKNOWN_0E43 0x00000e43 2184 2185 #define REG_A3XX_VFD_PERFCOUNTER0_SELECT 0x00000e44 2186 2187 #define REG_A3XX_VFD_PERFCOUNTER1_SELECT 0x00000e45 2188 2189 #define REG_A3XX_VPC_VPC_DEBUG_RAM_SEL 0x00000e61 2190 2191 #define REG_A3XX_VPC_VPC_DEBUG_RAM_READ 0x00000e62 2192 2193 #define REG_A3XX_VPC_PERFCOUNTER0_SELECT 0x00000e64 2194 2195 #define REG_A3XX_VPC_PERFCOUNTER1_SELECT 0x00000e65 2196 2197 #define REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG 0x00000e82 2198 2199 #define REG_A3XX_UCHE_PERFCOUNTER0_SELECT 0x00000e84 2200 2201 #define REG_A3XX_UCHE_PERFCOUNTER1_SELECT 0x00000e85 2202 2203 #define REG_A3XX_UCHE_PERFCOUNTER2_SELECT 0x00000e86 2204 2205 #define REG_A3XX_UCHE_PERFCOUNTER3_SELECT 0x00000e87 2206 2207 #define REG_A3XX_UCHE_PERFCOUNTER4_SELECT 0x00000e88 2208 2209 #define REG_A3XX_UCHE_PERFCOUNTER5_SELECT 0x00000e89 2210 2211 #define REG_A3XX_UCHE_CACHE_INVALIDATE0_REG 0x00000ea0 2212 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK 0x0fffffff 2213 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT 0 2214 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val) 2215 { 2216 return ((val) << A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK; 2217 } 2218 2219 #define REG_A3XX_UCHE_CACHE_INVALIDATE1_REG 0x00000ea1 2220 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK 0x0fffffff 2221 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT 0 2222 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val) 2223 { 2224 return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK; 2225 } 2226 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK 0x30000000 2227 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT 28 2228 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val) 2229 { 2230 return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK; 2231 } 2232 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE 0x80000000 2233 2234 #define REG_A3XX_UNKNOWN_0EA6 0x00000ea6 2235 2236 #define REG_A3XX_SP_PERFCOUNTER0_SELECT 0x00000ec4 2237 2238 #define REG_A3XX_SP_PERFCOUNTER1_SELECT 0x00000ec5 2239 2240 #define REG_A3XX_SP_PERFCOUNTER2_SELECT 0x00000ec6 2241 2242 #define REG_A3XX_SP_PERFCOUNTER3_SELECT 0x00000ec7 2243 2244 #define REG_A3XX_SP_PERFCOUNTER4_SELECT 0x00000ec8 2245 2246 #define REG_A3XX_SP_PERFCOUNTER5_SELECT 0x00000ec9 2247 2248 #define REG_A3XX_SP_PERFCOUNTER6_SELECT 0x00000eca 2249 2250 #define REG_A3XX_SP_PERFCOUNTER7_SELECT 0x00000ecb 2251 2252 #define REG_A3XX_UNKNOWN_0EE0 0x00000ee0 2253 2254 #define REG_A3XX_UNKNOWN_0F03 0x00000f03 2255 2256 #define REG_A3XX_TP_PERFCOUNTER0_SELECT 0x00000f04 2257 2258 #define REG_A3XX_TP_PERFCOUNTER1_SELECT 0x00000f05 2259 2260 #define REG_A3XX_TP_PERFCOUNTER2_SELECT 0x00000f06 2261 2262 #define REG_A3XX_TP_PERFCOUNTER3_SELECT 0x00000f07 2263 2264 #define REG_A3XX_TP_PERFCOUNTER4_SELECT 0x00000f08 2265 2266 #define REG_A3XX_TP_PERFCOUNTER5_SELECT 0x00000f09 2267 2268 #define REG_A3XX_VGT_CL_INITIATOR 0x000021f0 2269 2270 #define REG_A3XX_VGT_EVENT_INITIATOR 0x000021f9 2271 2272 #define REG_A3XX_VGT_DRAW_INITIATOR 0x000021fc 2273 #define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f 2274 #define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 2275 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) 2276 { 2277 return ((val) << A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK; 2278 } 2279 #define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 2280 #define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 2281 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) 2282 { 2283 return ((val) << A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK; 2284 } 2285 #define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600 2286 #define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9 2287 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) 2288 { 2289 return ((val) << A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK; 2290 } 2291 #define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800 2292 #define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11 2293 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) 2294 { 2295 return ((val) << A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK; 2296 } 2297 #define A3XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000 2298 #define A3XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000 2299 #define A3XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000 2300 #define A3XX_VGT_DRAW_INITIATOR_NUM_INDICES__MASK 0xffff0000 2301 #define A3XX_VGT_DRAW_INITIATOR_NUM_INDICES__SHIFT 16 2302 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_NUM_INDICES(uint32_t val) 2303 { 2304 return ((val) << A3XX_VGT_DRAW_INITIATOR_NUM_INDICES__SHIFT) & A3XX_VGT_DRAW_INITIATOR_NUM_INDICES__MASK; 2305 } 2306 2307 #define REG_A3XX_VGT_IMMED_DATA 0x000021fd 2308 2309 #define REG_A3XX_TEX_SAMP_0 0x00000000 2310 #define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR 0x00000002 2311 #define A3XX_TEX_SAMP_0_XY_MAG__MASK 0x0000000c 2312 #define A3XX_TEX_SAMP_0_XY_MAG__SHIFT 2 2313 static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val) 2314 { 2315 return ((val) << A3XX_TEX_SAMP_0_XY_MAG__SHIFT) & A3XX_TEX_SAMP_0_XY_MAG__MASK; 2316 } 2317 #define A3XX_TEX_SAMP_0_XY_MIN__MASK 0x00000030 2318 #define A3XX_TEX_SAMP_0_XY_MIN__SHIFT 4 2319 static inline uint32_t A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val) 2320 { 2321 return ((val) << A3XX_TEX_SAMP_0_XY_MIN__SHIFT) & A3XX_TEX_SAMP_0_XY_MIN__MASK; 2322 } 2323 #define A3XX_TEX_SAMP_0_WRAP_S__MASK 0x000001c0 2324 #define A3XX_TEX_SAMP_0_WRAP_S__SHIFT 6 2325 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val) 2326 { 2327 return ((val) << A3XX_TEX_SAMP_0_WRAP_S__SHIFT) & A3XX_TEX_SAMP_0_WRAP_S__MASK; 2328 } 2329 #define A3XX_TEX_SAMP_0_WRAP_T__MASK 0x00000e00 2330 #define A3XX_TEX_SAMP_0_WRAP_T__SHIFT 9 2331 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val) 2332 { 2333 return ((val) << A3XX_TEX_SAMP_0_WRAP_T__SHIFT) & A3XX_TEX_SAMP_0_WRAP_T__MASK; 2334 } 2335 #define A3XX_TEX_SAMP_0_WRAP_R__MASK 0x00007000 2336 #define A3XX_TEX_SAMP_0_WRAP_R__SHIFT 12 2337 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val) 2338 { 2339 return ((val) << A3XX_TEX_SAMP_0_WRAP_R__SHIFT) & A3XX_TEX_SAMP_0_WRAP_R__MASK; 2340 } 2341 #define A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK 0x00700000 2342 #define A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT 20 2343 static inline uint32_t A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val) 2344 { 2345 return ((val) << A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT) & A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK; 2346 } 2347 #define A3XX_TEX_SAMP_0_UNNORM_COORDS 0x80000000 2348 2349 #define REG_A3XX_TEX_SAMP_1 0x00000001 2350 #define A3XX_TEX_SAMP_1_MAX_LOD__MASK 0x003ff000 2351 #define A3XX_TEX_SAMP_1_MAX_LOD__SHIFT 12 2352 static inline uint32_t A3XX_TEX_SAMP_1_MAX_LOD(float val) 2353 { 2354 return ((((uint32_t)(val * 12.0))) << A3XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A3XX_TEX_SAMP_1_MAX_LOD__MASK; 2355 } 2356 #define A3XX_TEX_SAMP_1_MIN_LOD__MASK 0xffc00000 2357 #define A3XX_TEX_SAMP_1_MIN_LOD__SHIFT 22 2358 static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val) 2359 { 2360 return ((((uint32_t)(val * 12.0))) << A3XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A3XX_TEX_SAMP_1_MIN_LOD__MASK; 2361 } 2362 2363 #define REG_A3XX_TEX_CONST_0 0x00000000 2364 #define A3XX_TEX_CONST_0_TILED 0x00000001 2365 #define A3XX_TEX_CONST_0_SRGB 0x00000004 2366 #define A3XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 2367 #define A3XX_TEX_CONST_0_SWIZ_X__SHIFT 4 2368 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val) 2369 { 2370 return ((val) << A3XX_TEX_CONST_0_SWIZ_X__SHIFT) & A3XX_TEX_CONST_0_SWIZ_X__MASK; 2371 } 2372 #define A3XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 2373 #define A3XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 2374 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val) 2375 { 2376 return ((val) << A3XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Y__MASK; 2377 } 2378 #define A3XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 2379 #define A3XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 2380 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val) 2381 { 2382 return ((val) << A3XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Z__MASK; 2383 } 2384 #define A3XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 2385 #define A3XX_TEX_CONST_0_SWIZ_W__SHIFT 13 2386 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val) 2387 { 2388 return ((val) << A3XX_TEX_CONST_0_SWIZ_W__SHIFT) & A3XX_TEX_CONST_0_SWIZ_W__MASK; 2389 } 2390 #define A3XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 2391 #define A3XX_TEX_CONST_0_MIPLVLS__SHIFT 16 2392 static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val) 2393 { 2394 return ((val) << A3XX_TEX_CONST_0_MIPLVLS__SHIFT) & A3XX_TEX_CONST_0_MIPLVLS__MASK; 2395 } 2396 #define A3XX_TEX_CONST_0_FMT__MASK 0x1fc00000 2397 #define A3XX_TEX_CONST_0_FMT__SHIFT 22 2398 static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val) 2399 { 2400 return ((val) << A3XX_TEX_CONST_0_FMT__SHIFT) & A3XX_TEX_CONST_0_FMT__MASK; 2401 } 2402 #define A3XX_TEX_CONST_0_NOCONVERT 0x20000000 2403 #define A3XX_TEX_CONST_0_TYPE__MASK 0xc0000000 2404 #define A3XX_TEX_CONST_0_TYPE__SHIFT 30 2405 static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val) 2406 { 2407 return ((val) << A3XX_TEX_CONST_0_TYPE__SHIFT) & A3XX_TEX_CONST_0_TYPE__MASK; 2408 } 2409 2410 #define REG_A3XX_TEX_CONST_1 0x00000001 2411 #define A3XX_TEX_CONST_1_HEIGHT__MASK 0x00003fff 2412 #define A3XX_TEX_CONST_1_HEIGHT__SHIFT 0 2413 static inline uint32_t A3XX_TEX_CONST_1_HEIGHT(uint32_t val) 2414 { 2415 return ((val) << A3XX_TEX_CONST_1_HEIGHT__SHIFT) & A3XX_TEX_CONST_1_HEIGHT__MASK; 2416 } 2417 #define A3XX_TEX_CONST_1_WIDTH__MASK 0x0fffc000 2418 #define A3XX_TEX_CONST_1_WIDTH__SHIFT 14 2419 static inline uint32_t A3XX_TEX_CONST_1_WIDTH(uint32_t val) 2420 { 2421 return ((val) << A3XX_TEX_CONST_1_WIDTH__SHIFT) & A3XX_TEX_CONST_1_WIDTH__MASK; 2422 } 2423 #define A3XX_TEX_CONST_1_FETCHSIZE__MASK 0xf0000000 2424 #define A3XX_TEX_CONST_1_FETCHSIZE__SHIFT 28 2425 static inline uint32_t A3XX_TEX_CONST_1_FETCHSIZE(enum a3xx_tex_fetchsize val) 2426 { 2427 return ((val) << A3XX_TEX_CONST_1_FETCHSIZE__SHIFT) & A3XX_TEX_CONST_1_FETCHSIZE__MASK; 2428 } 2429 2430 #define REG_A3XX_TEX_CONST_2 0x00000002 2431 #define A3XX_TEX_CONST_2_INDX__MASK 0x000000ff 2432 #define A3XX_TEX_CONST_2_INDX__SHIFT 0 2433 static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val) 2434 { 2435 return ((val) << A3XX_TEX_CONST_2_INDX__SHIFT) & A3XX_TEX_CONST_2_INDX__MASK; 2436 } 2437 #define A3XX_TEX_CONST_2_PITCH__MASK 0x3ffff000 2438 #define A3XX_TEX_CONST_2_PITCH__SHIFT 12 2439 static inline uint32_t A3XX_TEX_CONST_2_PITCH(uint32_t val) 2440 { 2441 return ((val) << A3XX_TEX_CONST_2_PITCH__SHIFT) & A3XX_TEX_CONST_2_PITCH__MASK; 2442 } 2443 #define A3XX_TEX_CONST_2_SWAP__MASK 0xc0000000 2444 #define A3XX_TEX_CONST_2_SWAP__SHIFT 30 2445 static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) 2446 { 2447 return ((val) << A3XX_TEX_CONST_2_SWAP__SHIFT) & A3XX_TEX_CONST_2_SWAP__MASK; 2448 } 2449 2450 #define REG_A3XX_TEX_CONST_3 0x00000003 2451 2452 2453 #endif /* A3XX_XML */ 2454