1 #ifndef A3XX_XML 2 #define A3XX_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32814 bytes, from 2013-11-30 15:07:33) 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 8900 bytes, from 2013-10-22 23:57:49) 15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 10574 bytes, from 2013-11-13 05:44:45) 16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 53644 bytes, from 2013-11-30 15:07:33) 17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 8344 bytes, from 2013-11-30 14:49:47) 18 19 Copyright (C) 2013 by the following authors: 20 - Rob Clark <robdclark@gmail.com> (robclark) 21 22 Permission is hereby granted, free of charge, to any person obtaining 23 a copy of this software and associated documentation files (the 24 "Software"), to deal in the Software without restriction, including 25 without limitation the rights to use, copy, modify, merge, publish, 26 distribute, sublicense, and/or sell copies of the Software, and to 27 permit persons to whom the Software is furnished to do so, subject to 28 the following conditions: 29 30 The above copyright notice and this permission notice (including the 31 next paragraph) shall be included in all copies or substantial 32 portions of the Software. 33 34 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 36 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 37 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 38 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 39 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 40 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43 44 enum a3xx_render_mode { 45 RB_RENDERING_PASS = 0, 46 RB_TILING_PASS = 1, 47 RB_RESOLVE_PASS = 2, 48 }; 49 50 enum a3xx_tile_mode { 51 LINEAR = 0, 52 TILE_32X32 = 2, 53 }; 54 55 enum a3xx_threadmode { 56 MULTI = 0, 57 SINGLE = 1, 58 }; 59 60 enum a3xx_instrbuffermode { 61 BUFFER = 1, 62 }; 63 64 enum a3xx_threadsize { 65 TWO_QUADS = 0, 66 FOUR_QUADS = 1, 67 }; 68 69 enum a3xx_state_block_id { 70 HLSQ_BLOCK_ID_TP_TEX = 2, 71 HLSQ_BLOCK_ID_TP_MIPMAP = 3, 72 HLSQ_BLOCK_ID_SP_VS = 4, 73 HLSQ_BLOCK_ID_SP_FS = 6, 74 }; 75 76 enum a3xx_cache_opcode { 77 INVALIDATE = 1, 78 }; 79 80 enum a3xx_vtx_fmt { 81 VFMT_FLOAT_32 = 0, 82 VFMT_FLOAT_32_32 = 1, 83 VFMT_FLOAT_32_32_32 = 2, 84 VFMT_FLOAT_32_32_32_32 = 3, 85 VFMT_FLOAT_16 = 4, 86 VFMT_FLOAT_16_16 = 5, 87 VFMT_FLOAT_16_16_16 = 6, 88 VFMT_FLOAT_16_16_16_16 = 7, 89 VFMT_FIXED_32 = 8, 90 VFMT_FIXED_32_32 = 9, 91 VFMT_FIXED_32_32_32 = 10, 92 VFMT_FIXED_32_32_32_32 = 11, 93 VFMT_SHORT_16 = 16, 94 VFMT_SHORT_16_16 = 17, 95 VFMT_SHORT_16_16_16 = 18, 96 VFMT_SHORT_16_16_16_16 = 19, 97 VFMT_USHORT_16 = 20, 98 VFMT_USHORT_16_16 = 21, 99 VFMT_USHORT_16_16_16 = 22, 100 VFMT_USHORT_16_16_16_16 = 23, 101 VFMT_NORM_SHORT_16 = 24, 102 VFMT_NORM_SHORT_16_16 = 25, 103 VFMT_NORM_SHORT_16_16_16 = 26, 104 VFMT_NORM_SHORT_16_16_16_16 = 27, 105 VFMT_NORM_USHORT_16 = 28, 106 VFMT_NORM_USHORT_16_16 = 29, 107 VFMT_NORM_USHORT_16_16_16 = 30, 108 VFMT_NORM_USHORT_16_16_16_16 = 31, 109 VFMT_UBYTE_8 = 40, 110 VFMT_UBYTE_8_8 = 41, 111 VFMT_UBYTE_8_8_8 = 42, 112 VFMT_UBYTE_8_8_8_8 = 43, 113 VFMT_NORM_UBYTE_8 = 44, 114 VFMT_NORM_UBYTE_8_8 = 45, 115 VFMT_NORM_UBYTE_8_8_8 = 46, 116 VFMT_NORM_UBYTE_8_8_8_8 = 47, 117 VFMT_BYTE_8 = 48, 118 VFMT_BYTE_8_8 = 49, 119 VFMT_BYTE_8_8_8 = 50, 120 VFMT_BYTE_8_8_8_8 = 51, 121 VFMT_NORM_BYTE_8 = 52, 122 VFMT_NORM_BYTE_8_8 = 53, 123 VFMT_NORM_BYTE_8_8_8 = 54, 124 VFMT_NORM_BYTE_8_8_8_8 = 55, 125 VFMT_UINT_10_10_10_2 = 60, 126 VFMT_NORM_UINT_10_10_10_2 = 61, 127 VFMT_INT_10_10_10_2 = 62, 128 VFMT_NORM_INT_10_10_10_2 = 63, 129 }; 130 131 enum a3xx_tex_fmt { 132 TFMT_NORM_USHORT_565 = 4, 133 TFMT_NORM_USHORT_5551 = 6, 134 TFMT_NORM_USHORT_4444 = 7, 135 TFMT_NORM_UINT_X8Z24 = 10, 136 TFMT_NORM_UINT_NV12_UV_TILED = 17, 137 TFMT_NORM_UINT_NV12_Y_TILED = 19, 138 TFMT_NORM_UINT_NV12_UV = 21, 139 TFMT_NORM_UINT_NV12_Y = 23, 140 TFMT_NORM_UINT_I420_Y = 24, 141 TFMT_NORM_UINT_I420_U = 26, 142 TFMT_NORM_UINT_I420_V = 27, 143 TFMT_NORM_UINT_2_10_10_10 = 41, 144 TFMT_NORM_UINT_A8 = 44, 145 TFMT_NORM_UINT_L8_A8 = 47, 146 TFMT_NORM_UINT_8 = 48, 147 TFMT_NORM_UINT_8_8 = 49, 148 TFMT_NORM_UINT_8_8_8 = 50, 149 TFMT_NORM_UINT_8_8_8_8 = 51, 150 TFMT_FLOAT_16 = 64, 151 TFMT_FLOAT_16_16 = 65, 152 TFMT_FLOAT_16_16_16_16 = 67, 153 TFMT_FLOAT_32 = 84, 154 TFMT_FLOAT_32_32 = 85, 155 TFMT_FLOAT_32_32_32_32 = 87, 156 }; 157 158 enum a3xx_tex_fetchsize { 159 TFETCH_DISABLE = 0, 160 TFETCH_1_BYTE = 1, 161 TFETCH_2_BYTE = 2, 162 TFETCH_4_BYTE = 3, 163 TFETCH_8_BYTE = 4, 164 TFETCH_16_BYTE = 5, 165 }; 166 167 enum a3xx_color_fmt { 168 RB_R8G8B8_UNORM = 4, 169 RB_R8G8B8A8_UNORM = 8, 170 RB_Z16_UNORM = 12, 171 RB_A8_UNORM = 20, 172 }; 173 174 enum a3xx_color_swap { 175 WZYX = 0, 176 WXYZ = 1, 177 ZYXW = 2, 178 XYZW = 3, 179 }; 180 181 enum a3xx_msaa_samples { 182 MSAA_ONE = 0, 183 MSAA_TWO = 1, 184 MSAA_FOUR = 2, 185 }; 186 187 enum a3xx_sp_perfcounter_select { 188 SP_FS_CFLOW_INSTRUCTIONS = 12, 189 SP_FS_FULL_ALU_INSTRUCTIONS = 14, 190 SP0_ICL1_MISSES = 26, 191 SP_ALU_ACTIVE_CYCLES = 29, 192 }; 193 194 enum adreno_rb_copy_control_mode { 195 RB_COPY_RESOLVE = 1, 196 RB_COPY_DEPTH_STENCIL = 5, 197 }; 198 199 enum a3xx_tex_filter { 200 A3XX_TEX_NEAREST = 0, 201 A3XX_TEX_LINEAR = 1, 202 }; 203 204 enum a3xx_tex_clamp { 205 A3XX_TEX_REPEAT = 0, 206 A3XX_TEX_CLAMP_TO_EDGE = 1, 207 A3XX_TEX_MIRROR_REPEAT = 2, 208 A3XX_TEX_CLAMP_NONE = 3, 209 }; 210 211 enum a3xx_tex_swiz { 212 A3XX_TEX_X = 0, 213 A3XX_TEX_Y = 1, 214 A3XX_TEX_Z = 2, 215 A3XX_TEX_W = 3, 216 A3XX_TEX_ZERO = 4, 217 A3XX_TEX_ONE = 5, 218 }; 219 220 enum a3xx_tex_type { 221 A3XX_TEX_1D = 0, 222 A3XX_TEX_2D = 1, 223 A3XX_TEX_CUBE = 2, 224 A3XX_TEX_3D = 3, 225 }; 226 227 #define A3XX_INT0_RBBM_GPU_IDLE 0x00000001 228 #define A3XX_INT0_RBBM_AHB_ERROR 0x00000002 229 #define A3XX_INT0_RBBM_REG_TIMEOUT 0x00000004 230 #define A3XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 231 #define A3XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 232 #define A3XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020 233 #define A3XX_INT0_VFD_ERROR 0x00000040 234 #define A3XX_INT0_CP_SW_INT 0x00000080 235 #define A3XX_INT0_CP_T0_PACKET_IN_IB 0x00000100 236 #define A3XX_INT0_CP_OPCODE_ERROR 0x00000200 237 #define A3XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400 238 #define A3XX_INT0_CP_HW_FAULT 0x00000800 239 #define A3XX_INT0_CP_DMA 0x00001000 240 #define A3XX_INT0_CP_IB2_INT 0x00002000 241 #define A3XX_INT0_CP_IB1_INT 0x00004000 242 #define A3XX_INT0_CP_RB_INT 0x00008000 243 #define A3XX_INT0_CP_REG_PROTECT_FAULT 0x00010000 244 #define A3XX_INT0_CP_RB_DONE_TS 0x00020000 245 #define A3XX_INT0_CP_VS_DONE_TS 0x00040000 246 #define A3XX_INT0_CP_PS_DONE_TS 0x00080000 247 #define A3XX_INT0_CACHE_FLUSH_TS 0x00100000 248 #define A3XX_INT0_CP_AHB_ERROR_HALT 0x00200000 249 #define A3XX_INT0_MISC_HANG_DETECT 0x01000000 250 #define A3XX_INT0_UCHE_OOB_ACCESS 0x02000000 251 #define REG_A3XX_RBBM_HW_VERSION 0x00000000 252 253 #define REG_A3XX_RBBM_HW_RELEASE 0x00000001 254 255 #define REG_A3XX_RBBM_HW_CONFIGURATION 0x00000002 256 257 #define REG_A3XX_RBBM_CLOCK_CTL 0x00000010 258 259 #define REG_A3XX_RBBM_SP_HYST_CNT 0x00000012 260 261 #define REG_A3XX_RBBM_SW_RESET_CMD 0x00000018 262 263 #define REG_A3XX_RBBM_AHB_CTL0 0x00000020 264 265 #define REG_A3XX_RBBM_AHB_CTL1 0x00000021 266 267 #define REG_A3XX_RBBM_AHB_CMD 0x00000022 268 269 #define REG_A3XX_RBBM_AHB_ERROR_STATUS 0x00000027 270 271 #define REG_A3XX_RBBM_GPR0_CTL 0x0000002e 272 273 #define REG_A3XX_RBBM_STATUS 0x00000030 274 #define A3XX_RBBM_STATUS_HI_BUSY 0x00000001 275 #define A3XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 276 #define A3XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 277 #define A3XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000 278 #define A3XX_RBBM_STATUS_VBIF_BUSY 0x00008000 279 #define A3XX_RBBM_STATUS_TSE_BUSY 0x00010000 280 #define A3XX_RBBM_STATUS_RAS_BUSY 0x00020000 281 #define A3XX_RBBM_STATUS_RB_BUSY 0x00040000 282 #define A3XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 283 #define A3XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 284 #define A3XX_RBBM_STATUS_VFD_BUSY 0x00200000 285 #define A3XX_RBBM_STATUS_VPC_BUSY 0x00400000 286 #define A3XX_RBBM_STATUS_UCHE_BUSY 0x00800000 287 #define A3XX_RBBM_STATUS_SP_BUSY 0x01000000 288 #define A3XX_RBBM_STATUS_TPL1_BUSY 0x02000000 289 #define A3XX_RBBM_STATUS_MARB_BUSY 0x04000000 290 #define A3XX_RBBM_STATUS_VSC_BUSY 0x08000000 291 #define A3XX_RBBM_STATUS_ARB_BUSY 0x10000000 292 #define A3XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 293 #define A3XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000 294 #define A3XX_RBBM_STATUS_GPU_BUSY 0x80000000 295 296 #define REG_A3XX_RBBM_NQWAIT_UNTIL 0x00000040 297 298 #define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x00000033 299 300 #define REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL 0x00000050 301 302 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL0 0x00000051 303 304 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL1 0x00000054 305 306 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL2 0x00000057 307 308 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3 0x0000005a 309 310 #define REG_A3XX_RBBM_INT_SET_CMD 0x00000060 311 312 #define REG_A3XX_RBBM_INT_CLEAR_CMD 0x00000061 313 314 #define REG_A3XX_RBBM_INT_0_MASK 0x00000063 315 316 #define REG_A3XX_RBBM_INT_0_STATUS 0x00000064 317 318 #define REG_A3XX_RBBM_PERFCTR_CTL 0x00000080 319 320 #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0 0x00000081 321 322 #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD1 0x00000082 323 324 #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000084 325 326 #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000085 327 328 #define REG_A3XX_RBBM_PERFCOUNTER0_SELECT 0x00000086 329 330 #define REG_A3XX_RBBM_PERFCOUNTER1_SELECT 0x00000087 331 332 #define REG_A3XX_RBBM_GPU_BUSY_MASKED 0x00000088 333 334 #define REG_A3XX_RBBM_PERFCTR_CP_0_LO 0x00000090 335 336 #define REG_A3XX_RBBM_PERFCTR_CP_0_HI 0x00000091 337 338 #define REG_A3XX_RBBM_PERFCTR_RBBM_0_LO 0x00000092 339 340 #define REG_A3XX_RBBM_PERFCTR_RBBM_0_HI 0x00000093 341 342 #define REG_A3XX_RBBM_PERFCTR_RBBM_1_LO 0x00000094 343 344 #define REG_A3XX_RBBM_PERFCTR_RBBM_1_HI 0x00000095 345 346 #define REG_A3XX_RBBM_PERFCTR_PC_0_LO 0x00000096 347 348 #define REG_A3XX_RBBM_PERFCTR_PC_0_HI 0x00000097 349 350 #define REG_A3XX_RBBM_PERFCTR_PC_1_LO 0x00000098 351 352 #define REG_A3XX_RBBM_PERFCTR_PC_1_HI 0x00000099 353 354 #define REG_A3XX_RBBM_PERFCTR_PC_2_LO 0x0000009a 355 356 #define REG_A3XX_RBBM_PERFCTR_PC_2_HI 0x0000009b 357 358 #define REG_A3XX_RBBM_PERFCTR_PC_3_LO 0x0000009c 359 360 #define REG_A3XX_RBBM_PERFCTR_PC_3_HI 0x0000009d 361 362 #define REG_A3XX_RBBM_PERFCTR_VFD_0_LO 0x0000009e 363 364 #define REG_A3XX_RBBM_PERFCTR_VFD_0_HI 0x0000009f 365 366 #define REG_A3XX_RBBM_PERFCTR_VFD_1_LO 0x000000a0 367 368 #define REG_A3XX_RBBM_PERFCTR_VFD_1_HI 0x000000a1 369 370 #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000a2 371 372 #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000a3 373 374 #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000a4 375 376 #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000a5 377 378 #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000a6 379 380 #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000a7 381 382 #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000a8 383 384 #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000a9 385 386 #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000aa 387 388 #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000ab 389 390 #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000ac 391 392 #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000ad 393 394 #define REG_A3XX_RBBM_PERFCTR_VPC_0_LO 0x000000ae 395 396 #define REG_A3XX_RBBM_PERFCTR_VPC_0_HI 0x000000af 397 398 #define REG_A3XX_RBBM_PERFCTR_VPC_1_LO 0x000000b0 399 400 #define REG_A3XX_RBBM_PERFCTR_VPC_1_HI 0x000000b1 401 402 #define REG_A3XX_RBBM_PERFCTR_TSE_0_LO 0x000000b2 403 404 #define REG_A3XX_RBBM_PERFCTR_TSE_0_HI 0x000000b3 405 406 #define REG_A3XX_RBBM_PERFCTR_TSE_1_LO 0x000000b4 407 408 #define REG_A3XX_RBBM_PERFCTR_TSE_1_HI 0x000000b5 409 410 #define REG_A3XX_RBBM_PERFCTR_RAS_0_LO 0x000000b6 411 412 #define REG_A3XX_RBBM_PERFCTR_RAS_0_HI 0x000000b7 413 414 #define REG_A3XX_RBBM_PERFCTR_RAS_1_LO 0x000000b8 415 416 #define REG_A3XX_RBBM_PERFCTR_RAS_1_HI 0x000000b9 417 418 #define REG_A3XX_RBBM_PERFCTR_UCHE_0_LO 0x000000ba 419 420 #define REG_A3XX_RBBM_PERFCTR_UCHE_0_HI 0x000000bb 421 422 #define REG_A3XX_RBBM_PERFCTR_UCHE_1_LO 0x000000bc 423 424 #define REG_A3XX_RBBM_PERFCTR_UCHE_1_HI 0x000000bd 425 426 #define REG_A3XX_RBBM_PERFCTR_UCHE_2_LO 0x000000be 427 428 #define REG_A3XX_RBBM_PERFCTR_UCHE_2_HI 0x000000bf 429 430 #define REG_A3XX_RBBM_PERFCTR_UCHE_3_LO 0x000000c0 431 432 #define REG_A3XX_RBBM_PERFCTR_UCHE_3_HI 0x000000c1 433 434 #define REG_A3XX_RBBM_PERFCTR_UCHE_4_LO 0x000000c2 435 436 #define REG_A3XX_RBBM_PERFCTR_UCHE_4_HI 0x000000c3 437 438 #define REG_A3XX_RBBM_PERFCTR_UCHE_5_LO 0x000000c4 439 440 #define REG_A3XX_RBBM_PERFCTR_UCHE_5_HI 0x000000c5 441 442 #define REG_A3XX_RBBM_PERFCTR_TP_0_LO 0x000000c6 443 444 #define REG_A3XX_RBBM_PERFCTR_TP_0_HI 0x000000c7 445 446 #define REG_A3XX_RBBM_PERFCTR_TP_1_LO 0x000000c8 447 448 #define REG_A3XX_RBBM_PERFCTR_TP_1_HI 0x000000c9 449 450 #define REG_A3XX_RBBM_PERFCTR_TP_2_LO 0x000000ca 451 452 #define REG_A3XX_RBBM_PERFCTR_TP_2_HI 0x000000cb 453 454 #define REG_A3XX_RBBM_PERFCTR_TP_3_LO 0x000000cc 455 456 #define REG_A3XX_RBBM_PERFCTR_TP_3_HI 0x000000cd 457 458 #define REG_A3XX_RBBM_PERFCTR_TP_4_LO 0x000000ce 459 460 #define REG_A3XX_RBBM_PERFCTR_TP_4_HI 0x000000cf 461 462 #define REG_A3XX_RBBM_PERFCTR_TP_5_LO 0x000000d0 463 464 #define REG_A3XX_RBBM_PERFCTR_TP_5_HI 0x000000d1 465 466 #define REG_A3XX_RBBM_PERFCTR_SP_0_LO 0x000000d2 467 468 #define REG_A3XX_RBBM_PERFCTR_SP_0_HI 0x000000d3 469 470 #define REG_A3XX_RBBM_PERFCTR_SP_1_LO 0x000000d4 471 472 #define REG_A3XX_RBBM_PERFCTR_SP_1_HI 0x000000d5 473 474 #define REG_A3XX_RBBM_PERFCTR_SP_2_LO 0x000000d6 475 476 #define REG_A3XX_RBBM_PERFCTR_SP_2_HI 0x000000d7 477 478 #define REG_A3XX_RBBM_PERFCTR_SP_3_LO 0x000000d8 479 480 #define REG_A3XX_RBBM_PERFCTR_SP_3_HI 0x000000d9 481 482 #define REG_A3XX_RBBM_PERFCTR_SP_4_LO 0x000000da 483 484 #define REG_A3XX_RBBM_PERFCTR_SP_4_HI 0x000000db 485 486 #define REG_A3XX_RBBM_PERFCTR_SP_5_LO 0x000000dc 487 488 #define REG_A3XX_RBBM_PERFCTR_SP_5_HI 0x000000dd 489 490 #define REG_A3XX_RBBM_PERFCTR_SP_6_LO 0x000000de 491 492 #define REG_A3XX_RBBM_PERFCTR_SP_6_HI 0x000000df 493 494 #define REG_A3XX_RBBM_PERFCTR_SP_7_LO 0x000000e0 495 496 #define REG_A3XX_RBBM_PERFCTR_SP_7_HI 0x000000e1 497 498 #define REG_A3XX_RBBM_PERFCTR_RB_0_LO 0x000000e2 499 500 #define REG_A3XX_RBBM_PERFCTR_RB_0_HI 0x000000e3 501 502 #define REG_A3XX_RBBM_PERFCTR_RB_1_LO 0x000000e4 503 504 #define REG_A3XX_RBBM_PERFCTR_RB_1_HI 0x000000e5 505 506 #define REG_A3XX_RBBM_PERFCTR_PWR_0_LO 0x000000ea 507 508 #define REG_A3XX_RBBM_PERFCTR_PWR_0_HI 0x000000eb 509 510 #define REG_A3XX_RBBM_PERFCTR_PWR_1_LO 0x000000ec 511 512 #define REG_A3XX_RBBM_PERFCTR_PWR_1_HI 0x000000ed 513 514 #define REG_A3XX_RBBM_RBBM_CTL 0x00000100 515 516 #define REG_A3XX_RBBM_DEBUG_BUS_CTL 0x00000111 517 518 #define REG_A3XX_RBBM_DEBUG_BUS_DATA_STATUS 0x00000112 519 520 #define REG_A3XX_CP_PFP_UCODE_ADDR 0x000001c9 521 522 #define REG_A3XX_CP_PFP_UCODE_DATA 0x000001ca 523 524 #define REG_A3XX_CP_ROQ_ADDR 0x000001cc 525 526 #define REG_A3XX_CP_ROQ_DATA 0x000001cd 527 528 #define REG_A3XX_CP_MERCIU_ADDR 0x000001d1 529 530 #define REG_A3XX_CP_MERCIU_DATA 0x000001d2 531 532 #define REG_A3XX_CP_MERCIU_DATA2 0x000001d3 533 534 #define REG_A3XX_CP_MEQ_ADDR 0x000001da 535 536 #define REG_A3XX_CP_MEQ_DATA 0x000001db 537 538 #define REG_A3XX_CP_PERFCOUNTER_SELECT 0x00000445 539 540 #define REG_A3XX_CP_HW_FAULT 0x0000045c 541 542 #define REG_A3XX_CP_PROTECT_CTRL 0x0000045e 543 544 #define REG_A3XX_CP_PROTECT_STATUS 0x0000045f 545 546 static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; } 547 548 static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; } 549 550 #define REG_A3XX_CP_AHB_FAULT 0x0000054d 551 552 #define REG_A3XX_GRAS_CL_CLIP_CNTL 0x00002040 553 #define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER 0x00001000 554 #define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 555 #define A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000 556 #define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE 0x00080000 557 #define A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE 0x00100000 558 #define A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE 0x00200000 559 560 #define REG_A3XX_GRAS_CL_GB_CLIP_ADJ 0x00002044 561 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff 562 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0 563 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) 564 { 565 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; 566 } 567 #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00 568 #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10 569 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) 570 { 571 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; 572 } 573 574 #define REG_A3XX_GRAS_CL_VPORT_XOFFSET 0x00002048 575 #define A3XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff 576 #define A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0 577 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) 578 { 579 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK; 580 } 581 582 #define REG_A3XX_GRAS_CL_VPORT_XSCALE 0x00002049 583 #define A3XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff 584 #define A3XX_GRAS_CL_VPORT_XSCALE__SHIFT 0 585 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) 586 { 587 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK; 588 } 589 590 #define REG_A3XX_GRAS_CL_VPORT_YOFFSET 0x0000204a 591 #define A3XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff 592 #define A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0 593 static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val) 594 { 595 return ((fui(val)) << A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_YOFFSET__MASK; 596 } 597 598 #define REG_A3XX_GRAS_CL_VPORT_YSCALE 0x0000204b 599 #define A3XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff 600 #define A3XX_GRAS_CL_VPORT_YSCALE__SHIFT 0 601 static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val) 602 { 603 return ((fui(val)) << A3XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_YSCALE__MASK; 604 } 605 606 #define REG_A3XX_GRAS_CL_VPORT_ZOFFSET 0x0000204c 607 #define A3XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff 608 #define A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0 609 static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val) 610 { 611 return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_ZOFFSET__MASK; 612 } 613 614 #define REG_A3XX_GRAS_CL_VPORT_ZSCALE 0x0000204d 615 #define A3XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff 616 #define A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0 617 static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val) 618 { 619 return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_ZSCALE__MASK; 620 } 621 622 #define REG_A3XX_GRAS_SU_POINT_MINMAX 0x00002068 623 624 #define REG_A3XX_GRAS_SU_POINT_SIZE 0x00002069 625 626 #define REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000206c 627 #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK 0x00ffffff 628 #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT 0 629 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val) 630 { 631 return ((((uint32_t)(val * 40.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK; 632 } 633 634 #define REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000206d 635 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 636 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 637 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 638 { 639 return ((((uint32_t)(val * 44.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 640 } 641 642 #define REG_A3XX_GRAS_SU_MODE_CONTROL 0x00002070 643 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001 644 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002 645 #define A3XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004 646 #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8 647 #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3 648 static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) 649 { 650 return ((((uint32_t)(val * 4.0))) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; 651 } 652 #define A3XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800 653 654 #define REG_A3XX_GRAS_SC_CONTROL 0x00002072 655 #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x000000f0 656 #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 4 657 static inline uint32_t A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) 658 { 659 return ((val) << A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK; 660 } 661 #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000f00 662 #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 8 663 static inline uint32_t A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val) 664 { 665 return ((val) << A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK; 666 } 667 #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000 668 #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12 669 static inline uint32_t A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) 670 { 671 return ((val) << A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK; 672 } 673 674 #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL 0x00002074 675 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 676 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 677 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 678 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 679 { 680 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; 681 } 682 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 683 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 684 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 685 { 686 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; 687 } 688 689 #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_BR 0x00002075 690 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 691 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 692 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 693 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 694 { 695 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; 696 } 697 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 698 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 699 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 700 { 701 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; 702 } 703 704 #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL 0x00002079 705 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 706 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 707 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 708 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 709 { 710 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 711 } 712 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 713 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 714 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 715 { 716 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 717 } 718 719 #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000207a 720 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 721 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 722 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 723 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 724 { 725 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 726 } 727 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 728 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 729 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 730 { 731 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 732 } 733 734 #define REG_A3XX_RB_MODE_CONTROL 0x000020c0 735 #define A3XX_RB_MODE_CONTROL_GMEM_BYPASS 0x00000080 736 #define A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK 0x00000700 737 #define A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT 8 738 static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val) 739 { 740 return ((val) << A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT) & A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK; 741 } 742 #define A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE 0x00008000 743 #define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE 0x00010000 744 745 #define REG_A3XX_RB_RENDER_CONTROL 0x000020c1 746 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK 0x00000ff0 747 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT 4 748 static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val) 749 { 750 return ((val >> 5) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK; 751 } 752 #define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00001000 753 #define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM 0x00002000 754 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST 0x00400000 755 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK 0x07000000 756 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT 24 757 static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 758 { 759 return ((val) << A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK; 760 } 761 762 #define REG_A3XX_RB_MSAA_CONTROL 0x000020c2 763 #define A3XX_RB_MSAA_CONTROL_DISABLE 0x00000400 764 #define A3XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000f000 765 #define A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 12 766 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val) 767 { 768 return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLES__MASK; 769 } 770 #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK 0xffff0000 771 #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT 16 772 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val) 773 { 774 return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK; 775 } 776 777 #define REG_A3XX_RB_ALPHA_REF 0x000020c3 778 #define A3XX_RB_ALPHA_REF_UINT__MASK 0x0000ff00 779 #define A3XX_RB_ALPHA_REF_UINT__SHIFT 8 780 static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val) 781 { 782 return ((val) << A3XX_RB_ALPHA_REF_UINT__SHIFT) & A3XX_RB_ALPHA_REF_UINT__MASK; 783 } 784 #define A3XX_RB_ALPHA_REF_FLOAT__MASK 0xffff0000 785 #define A3XX_RB_ALPHA_REF_FLOAT__SHIFT 16 786 static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val) 787 { 788 return ((util_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK; 789 } 790 791 static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; } 792 793 static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; } 794 #define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008 795 #define A3XX_RB_MRT_CONTROL_BLEND 0x00000010 796 #define A3XX_RB_MRT_CONTROL_BLEND2 0x00000020 797 #define A3XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00 798 #define A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8 799 static inline uint32_t A3XX_RB_MRT_CONTROL_ROP_CODE(uint32_t val) 800 { 801 return ((val) << A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A3XX_RB_MRT_CONTROL_ROP_CODE__MASK; 802 } 803 #define A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK 0x00003000 804 #define A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT 12 805 static inline uint32_t A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) 806 { 807 return ((val) << A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT) & A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK; 808 } 809 #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000 810 #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24 811 static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 812 { 813 return ((val) << A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 814 } 815 816 static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; } 817 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f 818 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 819 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val) 820 { 821 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 822 } 823 #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0 824 #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6 825 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val) 826 { 827 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 828 } 829 #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00000c00 830 #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 10 831 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 832 { 833 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 834 } 835 #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xfffe0000 836 #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 17 837 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) 838 { 839 return ((val >> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; 840 } 841 842 static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; } 843 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK 0xfffffff0 844 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT 4 845 static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val) 846 { 847 return ((val >> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK; 848 } 849 850 static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; } 851 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 852 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 853 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 854 { 855 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 856 } 857 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 858 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 859 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum adreno_rb_blend_opcode val) 860 { 861 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 862 } 863 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 864 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 865 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 866 { 867 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 868 } 869 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 870 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 871 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 872 { 873 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 874 } 875 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 876 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 877 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum adreno_rb_blend_opcode val) 878 { 879 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 880 } 881 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 882 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 883 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 884 { 885 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 886 } 887 #define A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE 0x20000000 888 889 #define REG_A3XX_RB_BLEND_RED 0x000020e4 890 #define A3XX_RB_BLEND_RED_UINT__MASK 0x000000ff 891 #define A3XX_RB_BLEND_RED_UINT__SHIFT 0 892 static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val) 893 { 894 return ((val) << A3XX_RB_BLEND_RED_UINT__SHIFT) & A3XX_RB_BLEND_RED_UINT__MASK; 895 } 896 #define A3XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 897 #define A3XX_RB_BLEND_RED_FLOAT__SHIFT 16 898 static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val) 899 { 900 return ((util_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK; 901 } 902 903 #define REG_A3XX_RB_BLEND_GREEN 0x000020e5 904 #define A3XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff 905 #define A3XX_RB_BLEND_GREEN_UINT__SHIFT 0 906 static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val) 907 { 908 return ((val) << A3XX_RB_BLEND_GREEN_UINT__SHIFT) & A3XX_RB_BLEND_GREEN_UINT__MASK; 909 } 910 #define A3XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 911 #define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 912 static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val) 913 { 914 return ((util_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK; 915 } 916 917 #define REG_A3XX_RB_BLEND_BLUE 0x000020e6 918 #define A3XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff 919 #define A3XX_RB_BLEND_BLUE_UINT__SHIFT 0 920 static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val) 921 { 922 return ((val) << A3XX_RB_BLEND_BLUE_UINT__SHIFT) & A3XX_RB_BLEND_BLUE_UINT__MASK; 923 } 924 #define A3XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 925 #define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 926 static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val) 927 { 928 return ((util_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK; 929 } 930 931 #define REG_A3XX_RB_BLEND_ALPHA 0x000020e7 932 #define A3XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff 933 #define A3XX_RB_BLEND_ALPHA_UINT__SHIFT 0 934 static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val) 935 { 936 return ((val) << A3XX_RB_BLEND_ALPHA_UINT__SHIFT) & A3XX_RB_BLEND_ALPHA_UINT__MASK; 937 } 938 #define A3XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 939 #define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 940 static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val) 941 { 942 return ((util_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK; 943 } 944 945 #define REG_A3XX_RB_CLEAR_COLOR_DW0 0x000020e8 946 947 #define REG_A3XX_RB_CLEAR_COLOR_DW1 0x000020e9 948 949 #define REG_A3XX_RB_CLEAR_COLOR_DW2 0x000020ea 950 951 #define REG_A3XX_RB_CLEAR_COLOR_DW3 0x000020eb 952 953 #define REG_A3XX_RB_COPY_CONTROL 0x000020ec 954 #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003 955 #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0 956 static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) 957 { 958 return ((val) << A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK; 959 } 960 #define A3XX_RB_COPY_CONTROL_MODE__MASK 0x00000070 961 #define A3XX_RB_COPY_CONTROL_MODE__SHIFT 4 962 static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) 963 { 964 return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK; 965 } 966 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xfffffc00 967 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 10 968 static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) 969 { 970 return ((val >> 10) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK; 971 } 972 973 #define REG_A3XX_RB_COPY_DEST_BASE 0x000020ed 974 #define A3XX_RB_COPY_DEST_BASE_BASE__MASK 0xfffffff0 975 #define A3XX_RB_COPY_DEST_BASE_BASE__SHIFT 4 976 static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val) 977 { 978 return ((val >> 5) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A3XX_RB_COPY_DEST_BASE_BASE__MASK; 979 } 980 981 #define REG_A3XX_RB_COPY_DEST_PITCH 0x000020ee 982 #define A3XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff 983 #define A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0 984 static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) 985 { 986 return ((val >> 5) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK; 987 } 988 989 #define REG_A3XX_RB_COPY_DEST_INFO 0x000020ef 990 #define A3XX_RB_COPY_DEST_INFO_TILE__MASK 0x00000003 991 #define A3XX_RB_COPY_DEST_INFO_TILE__SHIFT 0 992 static inline uint32_t A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val) 993 { 994 return ((val) << A3XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A3XX_RB_COPY_DEST_INFO_TILE__MASK; 995 } 996 #define A3XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc 997 #define A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2 998 static inline uint32_t A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val) 999 { 1000 return ((val) << A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A3XX_RB_COPY_DEST_INFO_FORMAT__MASK; 1001 } 1002 #define A3XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 1003 #define A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 1004 static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) 1005 { 1006 return ((val) << A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A3XX_RB_COPY_DEST_INFO_SWAP__MASK; 1007 } 1008 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000 1009 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14 1010 static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) 1011 { 1012 return ((val) << A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK; 1013 } 1014 #define A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000 1015 #define A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18 1016 static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) 1017 { 1018 return ((val) << A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK; 1019 } 1020 1021 #define REG_A3XX_RB_DEPTH_CONTROL 0x00002100 1022 #define A3XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002 1023 #define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004 1024 #define A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00000008 1025 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070 1026 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4 1027 static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) 1028 { 1029 return ((val) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK; 1030 } 1031 #define A3XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080 1032 #define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000 1033 1034 #define REG_A3XX_RB_DEPTH_CLEAR 0x00002101 1035 1036 #define REG_A3XX_RB_DEPTH_INFO 0x00002102 1037 #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001 1038 #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 1039 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) 1040 { 1041 return ((val) << A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 1042 } 1043 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff800 1044 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 11 1045 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 1046 { 1047 return ((val >> 10) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 1048 } 1049 1050 #define REG_A3XX_RB_DEPTH_PITCH 0x00002103 1051 #define A3XX_RB_DEPTH_PITCH__MASK 0xffffffff 1052 #define A3XX_RB_DEPTH_PITCH__SHIFT 0 1053 static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val) 1054 { 1055 return ((val >> 3) << A3XX_RB_DEPTH_PITCH__SHIFT) & A3XX_RB_DEPTH_PITCH__MASK; 1056 } 1057 1058 #define REG_A3XX_RB_STENCIL_CONTROL 0x00002104 1059 #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 1060 #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 1061 #define A3XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 1062 #define A3XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 1063 #define A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 1064 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 1065 { 1066 return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC__MASK; 1067 } 1068 #define A3XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 1069 #define A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 1070 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 1071 { 1072 return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL__MASK; 1073 } 1074 #define A3XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 1075 #define A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 1076 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 1077 { 1078 return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS__MASK; 1079 } 1080 #define A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 1081 #define A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 1082 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 1083 { 1084 return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 1085 } 1086 #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 1087 #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 1088 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 1089 { 1090 return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 1091 } 1092 #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 1093 #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 1094 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 1095 { 1096 return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 1097 } 1098 #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 1099 #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 1100 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 1101 { 1102 return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 1103 } 1104 #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 1105 #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 1106 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 1107 { 1108 return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 1109 } 1110 1111 #define REG_A3XX_RB_STENCIL_CLEAR 0x00002105 1112 1113 #define REG_A3XX_RB_STENCIL_BUF_INFO 0x00002106 1114 1115 #define REG_A3XX_RB_STENCIL_BUF_PITCH 0x00002107 1116 1117 #define REG_A3XX_RB_STENCILREFMASK 0x00002108 1118 #define A3XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 1119 #define A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 1120 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 1121 { 1122 return ((val) << A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILREF__MASK; 1123 } 1124 #define A3XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 1125 #define A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 1126 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 1127 { 1128 return ((val) << A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILMASK__MASK; 1129 } 1130 #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 1131 #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 1132 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 1133 { 1134 return ((val) << A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 1135 } 1136 1137 #define REG_A3XX_RB_STENCILREFMASK_BF 0x00002109 1138 #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 1139 #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 1140 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 1141 { 1142 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 1143 } 1144 #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 1145 #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 1146 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 1147 { 1148 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 1149 } 1150 #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 1151 #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 1152 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 1153 { 1154 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 1155 } 1156 1157 #define REG_A3XX_RB_LRZ_VSC_CONTROL 0x0000210c 1158 #define A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE 0x00000002 1159 1160 #define REG_A3XX_RB_WINDOW_OFFSET 0x0000210e 1161 #define A3XX_RB_WINDOW_OFFSET_X__MASK 0x0000ffff 1162 #define A3XX_RB_WINDOW_OFFSET_X__SHIFT 0 1163 static inline uint32_t A3XX_RB_WINDOW_OFFSET_X(uint32_t val) 1164 { 1165 return ((val) << A3XX_RB_WINDOW_OFFSET_X__SHIFT) & A3XX_RB_WINDOW_OFFSET_X__MASK; 1166 } 1167 #define A3XX_RB_WINDOW_OFFSET_Y__MASK 0xffff0000 1168 #define A3XX_RB_WINDOW_OFFSET_Y__SHIFT 16 1169 static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val) 1170 { 1171 return ((val) << A3XX_RB_WINDOW_OFFSET_Y__SHIFT) & A3XX_RB_WINDOW_OFFSET_Y__MASK; 1172 } 1173 1174 #define REG_A3XX_RB_SAMPLE_COUNT_CONTROL 0x00002110 1175 1176 #define REG_A3XX_RB_SAMPLE_COUNT_ADDR 0x00002111 1177 1178 #define REG_A3XX_RB_Z_CLAMP_MIN 0x00002114 1179 1180 #define REG_A3XX_RB_Z_CLAMP_MAX 0x00002115 1181 1182 #define REG_A3XX_PC_VSTREAM_CONTROL 0x000021e4 1183 1184 #define REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL 0x000021ea 1185 1186 #define REG_A3XX_PC_PRIM_VTX_CNTL 0x000021ec 1187 #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK 0x0000001f 1188 #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT 0 1189 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val) 1190 { 1191 return ((val) << A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK; 1192 } 1193 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK 0x000000e0 1194 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT 5 1195 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 1196 { 1197 return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK; 1198 } 1199 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK 0x00000700 1200 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT 8 1201 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 1202 { 1203 return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK; 1204 } 1205 #define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000 1206 1207 #define REG_A3XX_PC_RESTART_INDEX 0x000021ed 1208 1209 #define REG_A3XX_HLSQ_CONTROL_0_REG 0x00002200 1210 #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010 1211 #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4 1212 static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) 1213 { 1214 return ((val) << A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; 1215 } 1216 #define A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040 1217 #define A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200 1218 #define A3XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400 1219 #define A3XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000 1220 #define A3XX_HLSQ_CONTROL_0_REG_CONSTSWITCHMODE 0x08000000 1221 #define A3XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000 1222 #define A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000 1223 #define A3XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000 1224 #define A3XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000 1225 1226 #define REG_A3XX_HLSQ_CONTROL_1_REG 0x00002201 1227 #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040 1228 #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6 1229 static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) 1230 { 1231 return ((val) << A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK; 1232 } 1233 #define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100 1234 #define A3XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200 1235 1236 #define REG_A3XX_HLSQ_CONTROL_2_REG 0x00002202 1237 #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000 1238 #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26 1239 static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) 1240 { 1241 return ((val) << A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK; 1242 } 1243 1244 #define REG_A3XX_HLSQ_CONTROL_3_REG 0x00002203 1245 1246 #define REG_A3XX_HLSQ_VS_CONTROL_REG 0x00002204 1247 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff 1248 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0 1249 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) 1250 { 1251 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK; 1252 } 1253 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000 1254 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12 1255 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) 1256 { 1257 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK; 1258 } 1259 #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 1260 #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24 1261 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) 1262 { 1263 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK; 1264 } 1265 1266 #define REG_A3XX_HLSQ_FS_CONTROL_REG 0x00002205 1267 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff 1268 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0 1269 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) 1270 { 1271 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK; 1272 } 1273 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000 1274 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12 1275 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) 1276 { 1277 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK; 1278 } 1279 #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 1280 #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24 1281 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) 1282 { 1283 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK; 1284 } 1285 1286 #define REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG 0x00002206 1287 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff 1288 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT 0 1289 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val) 1290 { 1291 return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK; 1292 } 1293 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000 1294 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT 16 1295 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val) 1296 { 1297 return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK; 1298 } 1299 1300 #define REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG 0x00002207 1301 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff 1302 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT 0 1303 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val) 1304 { 1305 return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK; 1306 } 1307 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000 1308 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT 16 1309 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val) 1310 { 1311 return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK; 1312 } 1313 1314 #define REG_A3XX_HLSQ_CL_NDRANGE_0_REG 0x0000220a 1315 1316 #define REG_A3XX_HLSQ_CL_NDRANGE_1_REG 0x0000220b 1317 1318 #define REG_A3XX_HLSQ_CL_NDRANGE_2_REG 0x0000220c 1319 1320 #define REG_A3XX_HLSQ_CL_CONTROL_0_REG 0x00002211 1321 1322 #define REG_A3XX_HLSQ_CL_CONTROL_1_REG 0x00002212 1323 1324 #define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG 0x00002214 1325 1326 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG 0x00002215 1327 1328 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Y_REG 0x00002216 1329 1330 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG 0x00002217 1331 1332 #define REG_A3XX_HLSQ_CL_WG_OFFSET_REG 0x0000221a 1333 1334 #define REG_A3XX_VFD_CONTROL_0 0x00002240 1335 #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x0003ffff 1336 #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0 1337 static inline uint32_t A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) 1338 { 1339 return ((val) << A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK; 1340 } 1341 #define A3XX_VFD_CONTROL_0_PACKETSIZE__MASK 0x003c0000 1342 #define A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT 18 1343 static inline uint32_t A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val) 1344 { 1345 return ((val) << A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT) & A3XX_VFD_CONTROL_0_PACKETSIZE__MASK; 1346 } 1347 #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x07c00000 1348 #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 22 1349 static inline uint32_t A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) 1350 { 1351 return ((val) << A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK; 1352 } 1353 #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xf8000000 1354 #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 27 1355 static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) 1356 { 1357 return ((val) << A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK; 1358 } 1359 1360 #define REG_A3XX_VFD_CONTROL_1 0x00002241 1361 #define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff 1362 #define A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0 1363 static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) 1364 { 1365 return ((val) << A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK; 1366 } 1367 #define A3XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000 1368 #define A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16 1369 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 1370 { 1371 return ((val) << A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A3XX_VFD_CONTROL_1_REGID4VTX__MASK; 1372 } 1373 #define A3XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000 1374 #define A3XX_VFD_CONTROL_1_REGID4INST__SHIFT 24 1375 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 1376 { 1377 return ((val) << A3XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A3XX_VFD_CONTROL_1_REGID4INST__MASK; 1378 } 1379 1380 #define REG_A3XX_VFD_INDEX_MIN 0x00002242 1381 1382 #define REG_A3XX_VFD_INDEX_MAX 0x00002243 1383 1384 #define REG_A3XX_VFD_INSTANCEID_OFFSET 0x00002244 1385 1386 #define REG_A3XX_VFD_INDEX_OFFSET 0x00002245 1387 1388 static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0) { return 0x00002246 + 0x2*i0; } 1389 1390 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; } 1391 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f 1392 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0 1393 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) 1394 { 1395 return ((val) << A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK; 1396 } 1397 #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80 1398 #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7 1399 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) 1400 { 1401 return ((val) << A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK; 1402 } 1403 #define A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00020000 1404 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK 0x00fc0000 1405 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT 18 1406 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val) 1407 { 1408 return ((val) << A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK; 1409 } 1410 #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK 0xff000000 1411 #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT 24 1412 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val) 1413 { 1414 return ((val) << A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK; 1415 } 1416 1417 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x00002247 + 0x2*i0; } 1418 1419 static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0) { return 0x00002266 + 0x1*i0; } 1420 1421 static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x00002266 + 0x1*i0; } 1422 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f 1423 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0 1424 static inline uint32_t A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) 1425 { 1426 return ((val) << A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK; 1427 } 1428 #define A3XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010 1429 #define A3XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0 1430 #define A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6 1431 static inline uint32_t A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val) 1432 { 1433 return ((val) << A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A3XX_VFD_DECODE_INSTR_FORMAT__MASK; 1434 } 1435 #define A3XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000 1436 #define A3XX_VFD_DECODE_INSTR_REGID__SHIFT 12 1437 static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val) 1438 { 1439 return ((val) << A3XX_VFD_DECODE_INSTR_REGID__SHIFT) & A3XX_VFD_DECODE_INSTR_REGID__MASK; 1440 } 1441 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000 1442 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24 1443 static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) 1444 { 1445 return ((val) << A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK; 1446 } 1447 #define A3XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000 1448 #define A3XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000 1449 1450 #define REG_A3XX_VFD_VS_THREADING_THRESHOLD 0x0000227e 1451 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK 0x0000000f 1452 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT 0 1453 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val) 1454 { 1455 return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK; 1456 } 1457 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK 0x0000ff00 1458 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT 8 1459 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val) 1460 { 1461 return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK; 1462 } 1463 1464 #define REG_A3XX_VPC_ATTR 0x00002280 1465 #define A3XX_VPC_ATTR_TOTALATTR__MASK 0x00000fff 1466 #define A3XX_VPC_ATTR_TOTALATTR__SHIFT 0 1467 static inline uint32_t A3XX_VPC_ATTR_TOTALATTR(uint32_t val) 1468 { 1469 return ((val) << A3XX_VPC_ATTR_TOTALATTR__SHIFT) & A3XX_VPC_ATTR_TOTALATTR__MASK; 1470 } 1471 #define A3XX_VPC_ATTR_THRDASSIGN__MASK 0x0ffff000 1472 #define A3XX_VPC_ATTR_THRDASSIGN__SHIFT 12 1473 static inline uint32_t A3XX_VPC_ATTR_THRDASSIGN(uint32_t val) 1474 { 1475 return ((val) << A3XX_VPC_ATTR_THRDASSIGN__SHIFT) & A3XX_VPC_ATTR_THRDASSIGN__MASK; 1476 } 1477 #define A3XX_VPC_ATTR_LMSIZE__MASK 0xf0000000 1478 #define A3XX_VPC_ATTR_LMSIZE__SHIFT 28 1479 static inline uint32_t A3XX_VPC_ATTR_LMSIZE(uint32_t val) 1480 { 1481 return ((val) << A3XX_VPC_ATTR_LMSIZE__SHIFT) & A3XX_VPC_ATTR_LMSIZE__MASK; 1482 } 1483 1484 #define REG_A3XX_VPC_PACK 0x00002281 1485 #define A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00 1486 #define A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8 1487 static inline uint32_t A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) 1488 { 1489 return ((val) << A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK; 1490 } 1491 #define A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000 1492 #define A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16 1493 static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) 1494 { 1495 return ((val) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK; 1496 } 1497 1498 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002282 + 0x1*i0; } 1499 1500 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002282 + 0x1*i0; } 1501 1502 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; } 1503 1504 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; } 1505 1506 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0 0x0000228a 1507 1508 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_1 0x0000228b 1509 1510 #define REG_A3XX_SP_SP_CTRL_REG 0x000022c0 1511 #define A3XX_SP_SP_CTRL_REG_RESOLVE 0x00010000 1512 #define A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK 0x00040000 1513 #define A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT 18 1514 static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val) 1515 { 1516 return ((val) << A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK; 1517 } 1518 #define A3XX_SP_SP_CTRL_REG_BINNING 0x00080000 1519 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK 0x00300000 1520 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT 20 1521 static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val) 1522 { 1523 return ((val) << A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK; 1524 } 1525 #define A3XX_SP_SP_CTRL_REG_LOMODE__MASK 0x00c00000 1526 #define A3XX_SP_SP_CTRL_REG_LOMODE__SHIFT 22 1527 static inline uint32_t A3XX_SP_SP_CTRL_REG_LOMODE(uint32_t val) 1528 { 1529 return ((val) << A3XX_SP_SP_CTRL_REG_LOMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_LOMODE__MASK; 1530 } 1531 1532 #define REG_A3XX_SP_VS_CTRL_REG0 0x000022c4 1533 #define A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 1534 #define A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 1535 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 1536 { 1537 return ((val) << A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK; 1538 } 1539 #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002 1540 #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1 1541 static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) 1542 { 1543 return ((val) << A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK; 1544 } 1545 #define A3XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004 1546 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 1547 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 1548 static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 1549 { 1550 return ((val) << A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 1551 } 1552 #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 1553 #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 1554 static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 1555 { 1556 return ((val) << A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 1557 } 1558 #define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 1559 #define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 1560 static inline uint32_t A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 1561 { 1562 return ((val) << A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK; 1563 } 1564 #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000 1565 #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20 1566 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 1567 { 1568 return ((val) << A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; 1569 } 1570 #define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000 1571 #define A3XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000 1572 #define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK 0xff000000 1573 #define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT 24 1574 static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val) 1575 { 1576 return ((val) << A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG0_LENGTH__MASK; 1577 } 1578 1579 #define REG_A3XX_SP_VS_CTRL_REG1 0x000022c5 1580 #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff 1581 #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0 1582 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) 1583 { 1584 return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK; 1585 } 1586 #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00 1587 #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10 1588 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) 1589 { 1590 return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK; 1591 } 1592 #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x3f000000 1593 #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24 1594 static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) 1595 { 1596 return ((val) << A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK; 1597 } 1598 1599 #define REG_A3XX_SP_VS_PARAM_REG 0x000022c6 1600 #define A3XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff 1601 #define A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0 1602 static inline uint32_t A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) 1603 { 1604 return ((val) << A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_POSREGID__MASK; 1605 } 1606 #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00 1607 #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8 1608 static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) 1609 { 1610 return ((val) << A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK; 1611 } 1612 #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000 1613 #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20 1614 static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) 1615 { 1616 return ((val) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; 1617 } 1618 1619 static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 1620 1621 static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 1622 #define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff 1623 #define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 1624 static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 1625 { 1626 return ((val) << A3XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_A_REGID__MASK; 1627 } 1628 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00 1629 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9 1630 static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 1631 { 1632 return ((val) << A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 1633 } 1634 #define A3XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000 1635 #define A3XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 1636 static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 1637 { 1638 return ((val) << A3XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_B_REGID__MASK; 1639 } 1640 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000 1641 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25 1642 static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 1643 { 1644 return ((val) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 1645 } 1646 1647 static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; } 1648 1649 static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; } 1650 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 1651 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 1652 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 1653 { 1654 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 1655 } 1656 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 1657 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 1658 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 1659 { 1660 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 1661 } 1662 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 1663 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 1664 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 1665 { 1666 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 1667 } 1668 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 1669 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 1670 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 1671 { 1672 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 1673 } 1674 1675 #define REG_A3XX_SP_VS_OBJ_OFFSET_REG 0x000022d4 1676 #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1677 #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1678 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1679 { 1680 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1681 } 1682 #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1683 #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1684 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1685 { 1686 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1687 } 1688 1689 #define REG_A3XX_SP_VS_OBJ_START_REG 0x000022d5 1690 1691 #define REG_A3XX_SP_VS_PVT_MEM_PARAM_REG 0x000022d6 1692 1693 #define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG 0x000022d7 1694 1695 #define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG 0x000022d8 1696 1697 #define REG_A3XX_SP_VS_LENGTH_REG 0x000022df 1698 #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff 1699 #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT 0 1700 static inline uint32_t A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val) 1701 { 1702 return ((val) << A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK; 1703 } 1704 1705 #define REG_A3XX_SP_FS_CTRL_REG0 0x000022e0 1706 #define A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 1707 #define A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 1708 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 1709 { 1710 return ((val) << A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK; 1711 } 1712 #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002 1713 #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1 1714 static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) 1715 { 1716 return ((val) << A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK; 1717 } 1718 #define A3XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004 1719 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 1720 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 1721 static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 1722 { 1723 return ((val) << A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 1724 } 1725 #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 1726 #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 1727 static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 1728 { 1729 return ((val) << A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 1730 } 1731 #define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 1732 #define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 1733 static inline uint32_t A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 1734 { 1735 return ((val) << A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK; 1736 } 1737 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 1738 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 1739 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 1740 { 1741 return ((val) << A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 1742 } 1743 #define A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000 1744 #define A3XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000 1745 #define A3XX_SP_FS_CTRL_REG0_LENGTH__MASK 0xff000000 1746 #define A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT 24 1747 static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val) 1748 { 1749 return ((val) << A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG0_LENGTH__MASK; 1750 } 1751 1752 #define REG_A3XX_SP_FS_CTRL_REG1 0x000022e1 1753 #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff 1754 #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0 1755 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) 1756 { 1757 return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK; 1758 } 1759 #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00 1760 #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10 1761 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) 1762 { 1763 return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK; 1764 } 1765 #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x00f00000 1766 #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 20 1767 static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) 1768 { 1769 return ((val) << A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK; 1770 } 1771 #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK 0x3f000000 1772 #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT 24 1773 static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val) 1774 { 1775 return ((val) << A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT) & A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK; 1776 } 1777 1778 #define REG_A3XX_SP_FS_OBJ_OFFSET_REG 0x000022e2 1779 #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1780 #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1781 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1782 { 1783 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1784 } 1785 #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1786 #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1787 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1788 { 1789 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1790 } 1791 1792 #define REG_A3XX_SP_FS_OBJ_START_REG 0x000022e3 1793 1794 #define REG_A3XX_SP_FS_PVT_MEM_PARAM_REG 0x000022e4 1795 1796 #define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG 0x000022e5 1797 1798 #define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG 0x000022e6 1799 1800 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0 0x000022e8 1801 1802 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1 0x000022e9 1803 1804 #define REG_A3XX_SP_FS_OUTPUT_REG 0x000022ec 1805 1806 static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0) { return 0x000022f0 + 0x1*i0; } 1807 1808 static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f0 + 0x1*i0; } 1809 #define A3XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff 1810 #define A3XX_SP_FS_MRT_REG_REGID__SHIFT 0 1811 static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val) 1812 { 1813 return ((val) << A3XX_SP_FS_MRT_REG_REGID__SHIFT) & A3XX_SP_FS_MRT_REG_REGID__MASK; 1814 } 1815 #define A3XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100 1816 1817 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0) { return 0x000022f4 + 0x1*i0; } 1818 1819 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0) { return 0x000022f4 + 0x1*i0; } 1820 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK 0x0000003f 1821 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT 0 1822 static inline uint32_t A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val) 1823 { 1824 return ((val) << A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT) & A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK; 1825 } 1826 1827 #define REG_A3XX_SP_FS_LENGTH_REG 0x000022ff 1828 #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff 1829 #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT 0 1830 static inline uint32_t A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val) 1831 { 1832 return ((val) << A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK; 1833 } 1834 1835 #define REG_A3XX_TPL1_TP_VS_TEX_OFFSET 0x00002340 1836 #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff 1837 #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0 1838 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) 1839 { 1840 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK; 1841 } 1842 #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00 1843 #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8 1844 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) 1845 { 1846 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK; 1847 } 1848 #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000 1849 #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT 16 1850 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val) 1851 { 1852 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK; 1853 } 1854 1855 #define REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002341 1856 1857 #define REG_A3XX_TPL1_TP_FS_TEX_OFFSET 0x00002342 1858 #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff 1859 #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0 1860 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) 1861 { 1862 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK; 1863 } 1864 #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00 1865 #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8 1866 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) 1867 { 1868 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK; 1869 } 1870 #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000 1871 #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT 16 1872 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val) 1873 { 1874 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK; 1875 } 1876 1877 #define REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x00002343 1878 1879 #define REG_A3XX_VBIF_CLKON 0x00003001 1880 1881 #define REG_A3XX_VBIF_FIXED_SORT_EN 0x0000300c 1882 1883 #define REG_A3XX_VBIF_FIXED_SORT_SEL0 0x0000300d 1884 1885 #define REG_A3XX_VBIF_FIXED_SORT_SEL1 0x0000300e 1886 1887 #define REG_A3XX_VBIF_ABIT_SORT 0x0000301c 1888 1889 #define REG_A3XX_VBIF_ABIT_SORT_CONF 0x0000301d 1890 1891 #define REG_A3XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 1892 1893 #define REG_A3XX_VBIF_IN_RD_LIM_CONF0 0x0000302c 1894 1895 #define REG_A3XX_VBIF_IN_RD_LIM_CONF1 0x0000302d 1896 1897 #define REG_A3XX_VBIF_IN_WR_LIM_CONF0 0x00003030 1898 1899 #define REG_A3XX_VBIF_IN_WR_LIM_CONF1 0x00003031 1900 1901 #define REG_A3XX_VBIF_OUT_RD_LIM_CONF0 0x00003034 1902 1903 #define REG_A3XX_VBIF_OUT_WR_LIM_CONF0 0x00003035 1904 1905 #define REG_A3XX_VBIF_DDR_OUT_MAX_BURST 0x00003036 1906 1907 #define REG_A3XX_VBIF_ARB_CTL 0x0000303c 1908 1909 #define REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049 1910 1911 #define REG_A3XX_VBIF_OUT_AXI_AMEMTYPE_CONF0 0x00003058 1912 1913 #define REG_A3XX_VBIF_OUT_AXI_AOOO_EN 0x0000305e 1914 1915 #define REG_A3XX_VBIF_OUT_AXI_AOOO 0x0000305f 1916 1917 #define REG_A3XX_VSC_BIN_SIZE 0x00000c01 1918 #define A3XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 1919 #define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 1920 static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 1921 { 1922 return ((val >> 5) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A3XX_VSC_BIN_SIZE_WIDTH__MASK; 1923 } 1924 #define A3XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 1925 #define A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5 1926 static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 1927 { 1928 return ((val >> 5) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK; 1929 } 1930 1931 #define REG_A3XX_VSC_SIZE_ADDRESS 0x00000c02 1932 1933 static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 1934 1935 static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 1936 #define A3XX_VSC_PIPE_CONFIG_X__MASK 0x000003ff 1937 #define A3XX_VSC_PIPE_CONFIG_X__SHIFT 0 1938 static inline uint32_t A3XX_VSC_PIPE_CONFIG_X(uint32_t val) 1939 { 1940 return ((val) << A3XX_VSC_PIPE_CONFIG_X__SHIFT) & A3XX_VSC_PIPE_CONFIG_X__MASK; 1941 } 1942 #define A3XX_VSC_PIPE_CONFIG_Y__MASK 0x000ffc00 1943 #define A3XX_VSC_PIPE_CONFIG_Y__SHIFT 10 1944 static inline uint32_t A3XX_VSC_PIPE_CONFIG_Y(uint32_t val) 1945 { 1946 return ((val) << A3XX_VSC_PIPE_CONFIG_Y__SHIFT) & A3XX_VSC_PIPE_CONFIG_Y__MASK; 1947 } 1948 #define A3XX_VSC_PIPE_CONFIG_W__MASK 0x00f00000 1949 #define A3XX_VSC_PIPE_CONFIG_W__SHIFT 20 1950 static inline uint32_t A3XX_VSC_PIPE_CONFIG_W(uint32_t val) 1951 { 1952 return ((val) << A3XX_VSC_PIPE_CONFIG_W__SHIFT) & A3XX_VSC_PIPE_CONFIG_W__MASK; 1953 } 1954 #define A3XX_VSC_PIPE_CONFIG_H__MASK 0x0f000000 1955 #define A3XX_VSC_PIPE_CONFIG_H__SHIFT 24 1956 static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val) 1957 { 1958 return ((val) << A3XX_VSC_PIPE_CONFIG_H__SHIFT) & A3XX_VSC_PIPE_CONFIG_H__MASK; 1959 } 1960 1961 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } 1962 1963 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } 1964 1965 #define REG_A3XX_VSC_BIN_CONTROL 0x00000c3c 1966 #define A3XX_VSC_BIN_CONTROL_BINNING_ENABLE 0x00000001 1967 1968 #define REG_A3XX_UNKNOWN_0C3D 0x00000c3d 1969 1970 #define REG_A3XX_PC_PERFCOUNTER0_SELECT 0x00000c48 1971 1972 #define REG_A3XX_PC_PERFCOUNTER1_SELECT 0x00000c49 1973 1974 #define REG_A3XX_PC_PERFCOUNTER2_SELECT 0x00000c4a 1975 1976 #define REG_A3XX_PC_PERFCOUNTER3_SELECT 0x00000c4b 1977 1978 #define REG_A3XX_GRAS_TSE_DEBUG_ECO 0x00000c81 1979 1980 #define REG_A3XX_GRAS_PERFCOUNTER0_SELECT 0x00000c88 1981 1982 #define REG_A3XX_GRAS_PERFCOUNTER1_SELECT 0x00000c89 1983 1984 #define REG_A3XX_GRAS_PERFCOUNTER2_SELECT 0x00000c8a 1985 1986 #define REG_A3XX_GRAS_PERFCOUNTER3_SELECT 0x00000c8b 1987 1988 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } 1989 1990 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } 1991 1992 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0) { return 0x00000ca1 + 0x4*i0; } 1993 1994 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0) { return 0x00000ca2 + 0x4*i0; } 1995 1996 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) { return 0x00000ca3 + 0x4*i0; } 1997 1998 #define REG_A3XX_RB_GMEM_BASE_ADDR 0x00000cc0 1999 2000 #define REG_A3XX_RB_DEBUG_ECO_CONTROLS_ADDR 0x00000cc1 2001 2002 #define REG_A3XX_RB_PERFCOUNTER0_SELECT 0x00000cc6 2003 2004 #define REG_A3XX_RB_PERFCOUNTER1_SELECT 0x00000cc7 2005 2006 #define REG_A3XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0 2007 #define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff 2008 #define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0 2009 static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) 2010 { 2011 return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK; 2012 } 2013 #define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x0fffc000 2014 #define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 14 2015 static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) 2016 { 2017 return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK; 2018 } 2019 2020 #define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT 0x00000e00 2021 2022 #define REG_A3XX_HLSQ_PERFCOUNTER1_SELECT 0x00000e01 2023 2024 #define REG_A3XX_HLSQ_PERFCOUNTER2_SELECT 0x00000e02 2025 2026 #define REG_A3XX_HLSQ_PERFCOUNTER3_SELECT 0x00000e03 2027 2028 #define REG_A3XX_HLSQ_PERFCOUNTER4_SELECT 0x00000e04 2029 2030 #define REG_A3XX_HLSQ_PERFCOUNTER5_SELECT 0x00000e05 2031 2032 #define REG_A3XX_UNKNOWN_0E43 0x00000e43 2033 2034 #define REG_A3XX_VFD_PERFCOUNTER0_SELECT 0x00000e44 2035 2036 #define REG_A3XX_VFD_PERFCOUNTER1_SELECT 0x00000e45 2037 2038 #define REG_A3XX_VPC_VPC_DEBUG_RAM_SEL 0x00000e61 2039 2040 #define REG_A3XX_VPC_VPC_DEBUG_RAM_READ 0x00000e62 2041 2042 #define REG_A3XX_VPC_PERFCOUNTER0_SELECT 0x00000e64 2043 2044 #define REG_A3XX_VPC_PERFCOUNTER1_SELECT 0x00000e65 2045 2046 #define REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG 0x00000e82 2047 2048 #define REG_A3XX_UCHE_PERFCOUNTER0_SELECT 0x00000e84 2049 2050 #define REG_A3XX_UCHE_PERFCOUNTER1_SELECT 0x00000e85 2051 2052 #define REG_A3XX_UCHE_PERFCOUNTER2_SELECT 0x00000e86 2053 2054 #define REG_A3XX_UCHE_PERFCOUNTER3_SELECT 0x00000e87 2055 2056 #define REG_A3XX_UCHE_PERFCOUNTER4_SELECT 0x00000e88 2057 2058 #define REG_A3XX_UCHE_PERFCOUNTER5_SELECT 0x00000e89 2059 2060 #define REG_A3XX_UCHE_CACHE_INVALIDATE0_REG 0x00000ea0 2061 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK 0x0fffffff 2062 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT 0 2063 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val) 2064 { 2065 return ((val) << A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK; 2066 } 2067 2068 #define REG_A3XX_UCHE_CACHE_INVALIDATE1_REG 0x00000ea1 2069 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK 0x0fffffff 2070 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT 0 2071 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val) 2072 { 2073 return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK; 2074 } 2075 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK 0x30000000 2076 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT 28 2077 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val) 2078 { 2079 return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK; 2080 } 2081 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE 0x80000000 2082 2083 #define REG_A3XX_SP_PERFCOUNTER0_SELECT 0x00000ec4 2084 2085 #define REG_A3XX_SP_PERFCOUNTER1_SELECT 0x00000ec5 2086 2087 #define REG_A3XX_SP_PERFCOUNTER2_SELECT 0x00000ec6 2088 2089 #define REG_A3XX_SP_PERFCOUNTER3_SELECT 0x00000ec7 2090 2091 #define REG_A3XX_SP_PERFCOUNTER4_SELECT 0x00000ec8 2092 2093 #define REG_A3XX_SP_PERFCOUNTER5_SELECT 0x00000ec9 2094 2095 #define REG_A3XX_SP_PERFCOUNTER6_SELECT 0x00000eca 2096 2097 #define REG_A3XX_SP_PERFCOUNTER7_SELECT 0x00000ecb 2098 2099 #define REG_A3XX_UNKNOWN_0EE0 0x00000ee0 2100 2101 #define REG_A3XX_UNKNOWN_0F03 0x00000f03 2102 2103 #define REG_A3XX_TP_PERFCOUNTER0_SELECT 0x00000f04 2104 2105 #define REG_A3XX_TP_PERFCOUNTER1_SELECT 0x00000f05 2106 2107 #define REG_A3XX_TP_PERFCOUNTER2_SELECT 0x00000f06 2108 2109 #define REG_A3XX_TP_PERFCOUNTER3_SELECT 0x00000f07 2110 2111 #define REG_A3XX_TP_PERFCOUNTER4_SELECT 0x00000f08 2112 2113 #define REG_A3XX_TP_PERFCOUNTER5_SELECT 0x00000f09 2114 2115 #define REG_A3XX_VGT_CL_INITIATOR 0x000021f0 2116 2117 #define REG_A3XX_VGT_EVENT_INITIATOR 0x000021f9 2118 2119 #define REG_A3XX_VGT_DRAW_INITIATOR 0x000021fc 2120 2121 #define REG_A3XX_VGT_IMMED_DATA 0x000021fd 2122 2123 #define REG_A3XX_TEX_SAMP_0 0x00000000 2124 #define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR 0x00000002 2125 #define A3XX_TEX_SAMP_0_XY_MAG__MASK 0x0000000c 2126 #define A3XX_TEX_SAMP_0_XY_MAG__SHIFT 2 2127 static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val) 2128 { 2129 return ((val) << A3XX_TEX_SAMP_0_XY_MAG__SHIFT) & A3XX_TEX_SAMP_0_XY_MAG__MASK; 2130 } 2131 #define A3XX_TEX_SAMP_0_XY_MIN__MASK 0x00000030 2132 #define A3XX_TEX_SAMP_0_XY_MIN__SHIFT 4 2133 static inline uint32_t A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val) 2134 { 2135 return ((val) << A3XX_TEX_SAMP_0_XY_MIN__SHIFT) & A3XX_TEX_SAMP_0_XY_MIN__MASK; 2136 } 2137 #define A3XX_TEX_SAMP_0_WRAP_S__MASK 0x000001c0 2138 #define A3XX_TEX_SAMP_0_WRAP_S__SHIFT 6 2139 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val) 2140 { 2141 return ((val) << A3XX_TEX_SAMP_0_WRAP_S__SHIFT) & A3XX_TEX_SAMP_0_WRAP_S__MASK; 2142 } 2143 #define A3XX_TEX_SAMP_0_WRAP_T__MASK 0x00000e00 2144 #define A3XX_TEX_SAMP_0_WRAP_T__SHIFT 9 2145 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val) 2146 { 2147 return ((val) << A3XX_TEX_SAMP_0_WRAP_T__SHIFT) & A3XX_TEX_SAMP_0_WRAP_T__MASK; 2148 } 2149 #define A3XX_TEX_SAMP_0_WRAP_R__MASK 0x00007000 2150 #define A3XX_TEX_SAMP_0_WRAP_R__SHIFT 12 2151 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val) 2152 { 2153 return ((val) << A3XX_TEX_SAMP_0_WRAP_R__SHIFT) & A3XX_TEX_SAMP_0_WRAP_R__MASK; 2154 } 2155 #define A3XX_TEX_SAMP_0_UNNORM_COORDS 0x80000000 2156 2157 #define REG_A3XX_TEX_SAMP_1 0x00000001 2158 #define A3XX_TEX_SAMP_1_MAX_LOD__MASK 0x003ff000 2159 #define A3XX_TEX_SAMP_1_MAX_LOD__SHIFT 12 2160 static inline uint32_t A3XX_TEX_SAMP_1_MAX_LOD(float val) 2161 { 2162 return ((((uint32_t)(val * 12.0))) << A3XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A3XX_TEX_SAMP_1_MAX_LOD__MASK; 2163 } 2164 #define A3XX_TEX_SAMP_1_MIN_LOD__MASK 0xffc00000 2165 #define A3XX_TEX_SAMP_1_MIN_LOD__SHIFT 22 2166 static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val) 2167 { 2168 return ((((uint32_t)(val * 12.0))) << A3XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A3XX_TEX_SAMP_1_MIN_LOD__MASK; 2169 } 2170 2171 #define REG_A3XX_TEX_CONST_0 0x00000000 2172 #define A3XX_TEX_CONST_0_TILED 0x00000001 2173 #define A3XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 2174 #define A3XX_TEX_CONST_0_SWIZ_X__SHIFT 4 2175 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val) 2176 { 2177 return ((val) << A3XX_TEX_CONST_0_SWIZ_X__SHIFT) & A3XX_TEX_CONST_0_SWIZ_X__MASK; 2178 } 2179 #define A3XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 2180 #define A3XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 2181 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val) 2182 { 2183 return ((val) << A3XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Y__MASK; 2184 } 2185 #define A3XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 2186 #define A3XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 2187 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val) 2188 { 2189 return ((val) << A3XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Z__MASK; 2190 } 2191 #define A3XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 2192 #define A3XX_TEX_CONST_0_SWIZ_W__SHIFT 13 2193 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val) 2194 { 2195 return ((val) << A3XX_TEX_CONST_0_SWIZ_W__SHIFT) & A3XX_TEX_CONST_0_SWIZ_W__MASK; 2196 } 2197 #define A3XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 2198 #define A3XX_TEX_CONST_0_MIPLVLS__SHIFT 16 2199 static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val) 2200 { 2201 return ((val) << A3XX_TEX_CONST_0_MIPLVLS__SHIFT) & A3XX_TEX_CONST_0_MIPLVLS__MASK; 2202 } 2203 #define A3XX_TEX_CONST_0_FMT__MASK 0x1fc00000 2204 #define A3XX_TEX_CONST_0_FMT__SHIFT 22 2205 static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val) 2206 { 2207 return ((val) << A3XX_TEX_CONST_0_FMT__SHIFT) & A3XX_TEX_CONST_0_FMT__MASK; 2208 } 2209 #define A3XX_TEX_CONST_0_TYPE__MASK 0xc0000000 2210 #define A3XX_TEX_CONST_0_TYPE__SHIFT 30 2211 static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val) 2212 { 2213 return ((val) << A3XX_TEX_CONST_0_TYPE__SHIFT) & A3XX_TEX_CONST_0_TYPE__MASK; 2214 } 2215 2216 #define REG_A3XX_TEX_CONST_1 0x00000001 2217 #define A3XX_TEX_CONST_1_HEIGHT__MASK 0x00003fff 2218 #define A3XX_TEX_CONST_1_HEIGHT__SHIFT 0 2219 static inline uint32_t A3XX_TEX_CONST_1_HEIGHT(uint32_t val) 2220 { 2221 return ((val) << A3XX_TEX_CONST_1_HEIGHT__SHIFT) & A3XX_TEX_CONST_1_HEIGHT__MASK; 2222 } 2223 #define A3XX_TEX_CONST_1_WIDTH__MASK 0x0fffc000 2224 #define A3XX_TEX_CONST_1_WIDTH__SHIFT 14 2225 static inline uint32_t A3XX_TEX_CONST_1_WIDTH(uint32_t val) 2226 { 2227 return ((val) << A3XX_TEX_CONST_1_WIDTH__SHIFT) & A3XX_TEX_CONST_1_WIDTH__MASK; 2228 } 2229 #define A3XX_TEX_CONST_1_FETCHSIZE__MASK 0xf0000000 2230 #define A3XX_TEX_CONST_1_FETCHSIZE__SHIFT 28 2231 static inline uint32_t A3XX_TEX_CONST_1_FETCHSIZE(enum a3xx_tex_fetchsize val) 2232 { 2233 return ((val) << A3XX_TEX_CONST_1_FETCHSIZE__SHIFT) & A3XX_TEX_CONST_1_FETCHSIZE__MASK; 2234 } 2235 2236 #define REG_A3XX_TEX_CONST_2 0x00000002 2237 #define A3XX_TEX_CONST_2_INDX__MASK 0x000000ff 2238 #define A3XX_TEX_CONST_2_INDX__SHIFT 0 2239 static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val) 2240 { 2241 return ((val) << A3XX_TEX_CONST_2_INDX__SHIFT) & A3XX_TEX_CONST_2_INDX__MASK; 2242 } 2243 #define A3XX_TEX_CONST_2_PITCH__MASK 0x3ffff000 2244 #define A3XX_TEX_CONST_2_PITCH__SHIFT 12 2245 static inline uint32_t A3XX_TEX_CONST_2_PITCH(uint32_t val) 2246 { 2247 return ((val) << A3XX_TEX_CONST_2_PITCH__SHIFT) & A3XX_TEX_CONST_2_PITCH__MASK; 2248 } 2249 #define A3XX_TEX_CONST_2_SWAP__MASK 0xc0000000 2250 #define A3XX_TEX_CONST_2_SWAP__SHIFT 30 2251 static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) 2252 { 2253 return ((val) << A3XX_TEX_CONST_2_SWAP__SHIFT) & A3XX_TEX_CONST_2_SWAP__MASK; 2254 } 2255 2256 #define REG_A3XX_TEX_CONST_3 0x00000003 2257 2258 2259 #endif /* A3XX_XML */ 2260