1 #ifndef A2XX_XML 2 #define A2XX_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://0x04.net/cgit/index.cgi/rules-ng-ng 8 git clone git://0x04.net/rules-ng-ng 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13 - /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 30005 bytes, from 2013-07-19 21:30:48) 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36) 15 - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9712 bytes, from 2013-05-26 15:22:37) 16 - /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51415 bytes, from 2013-08-03 14:26:05) 17 18 Copyright (C) 2013 by the following authors: 19 - Rob Clark <robdclark@gmail.com> (robclark) 20 21 Permission is hereby granted, free of charge, to any person obtaining 22 a copy of this software and associated documentation files (the 23 "Software"), to deal in the Software without restriction, including 24 without limitation the rights to use, copy, modify, merge, publish, 25 distribute, sublicense, and/or sell copies of the Software, and to 26 permit persons to whom the Software is furnished to do so, subject to 27 the following conditions: 28 29 The above copyright notice and this permission notice (including the 30 next paragraph) shall be included in all copies or substantial 31 portions of the Software. 32 33 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 35 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 36 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 37 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 38 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 39 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 40 */ 41 42 43 enum a2xx_rb_dither_type { 44 DITHER_PIXEL = 0, 45 DITHER_SUBPIXEL = 1, 46 }; 47 48 enum a2xx_colorformatx { 49 COLORX_4_4_4_4 = 0, 50 COLORX_1_5_5_5 = 1, 51 COLORX_5_6_5 = 2, 52 COLORX_8 = 3, 53 COLORX_8_8 = 4, 54 COLORX_8_8_8_8 = 5, 55 COLORX_S8_8_8_8 = 6, 56 COLORX_16_FLOAT = 7, 57 COLORX_16_16_FLOAT = 8, 58 COLORX_16_16_16_16_FLOAT = 9, 59 COLORX_32_FLOAT = 10, 60 COLORX_32_32_FLOAT = 11, 61 COLORX_32_32_32_32_FLOAT = 12, 62 COLORX_2_3_3 = 13, 63 COLORX_8_8_8 = 14, 64 }; 65 66 enum a2xx_sq_surfaceformat { 67 FMT_1_REVERSE = 0, 68 FMT_1 = 1, 69 FMT_8 = 2, 70 FMT_1_5_5_5 = 3, 71 FMT_5_6_5 = 4, 72 FMT_6_5_5 = 5, 73 FMT_8_8_8_8 = 6, 74 FMT_2_10_10_10 = 7, 75 FMT_8_A = 8, 76 FMT_8_B = 9, 77 FMT_8_8 = 10, 78 FMT_Cr_Y1_Cb_Y0 = 11, 79 FMT_Y1_Cr_Y0_Cb = 12, 80 FMT_5_5_5_1 = 13, 81 FMT_8_8_8_8_A = 14, 82 FMT_4_4_4_4 = 15, 83 FMT_10_11_11 = 16, 84 FMT_11_11_10 = 17, 85 FMT_DXT1 = 18, 86 FMT_DXT2_3 = 19, 87 FMT_DXT4_5 = 20, 88 FMT_24_8 = 22, 89 FMT_24_8_FLOAT = 23, 90 FMT_16 = 24, 91 FMT_16_16 = 25, 92 FMT_16_16_16_16 = 26, 93 FMT_16_EXPAND = 27, 94 FMT_16_16_EXPAND = 28, 95 FMT_16_16_16_16_EXPAND = 29, 96 FMT_16_FLOAT = 30, 97 FMT_16_16_FLOAT = 31, 98 FMT_16_16_16_16_FLOAT = 32, 99 FMT_32 = 33, 100 FMT_32_32 = 34, 101 FMT_32_32_32_32 = 35, 102 FMT_32_FLOAT = 36, 103 FMT_32_32_FLOAT = 37, 104 FMT_32_32_32_32_FLOAT = 38, 105 FMT_32_AS_8 = 39, 106 FMT_32_AS_8_8 = 40, 107 FMT_16_MPEG = 41, 108 FMT_16_16_MPEG = 42, 109 FMT_8_INTERLACED = 43, 110 FMT_32_AS_8_INTERLACED = 44, 111 FMT_32_AS_8_8_INTERLACED = 45, 112 FMT_16_INTERLACED = 46, 113 FMT_16_MPEG_INTERLACED = 47, 114 FMT_16_16_MPEG_INTERLACED = 48, 115 FMT_DXN = 49, 116 FMT_8_8_8_8_AS_16_16_16_16 = 50, 117 FMT_DXT1_AS_16_16_16_16 = 51, 118 FMT_DXT2_3_AS_16_16_16_16 = 52, 119 FMT_DXT4_5_AS_16_16_16_16 = 53, 120 FMT_2_10_10_10_AS_16_16_16_16 = 54, 121 FMT_10_11_11_AS_16_16_16_16 = 55, 122 FMT_11_11_10_AS_16_16_16_16 = 56, 123 FMT_32_32_32_FLOAT = 57, 124 FMT_DXT3A = 58, 125 FMT_DXT5A = 59, 126 FMT_CTX1 = 60, 127 FMT_DXT3A_AS_1_1_1_1 = 61, 128 }; 129 130 enum a2xx_sq_ps_vtx_mode { 131 POSITION_1_VECTOR = 0, 132 POSITION_2_VECTORS_UNUSED = 1, 133 POSITION_2_VECTORS_SPRITE = 2, 134 POSITION_2_VECTORS_EDGE = 3, 135 POSITION_2_VECTORS_KILL = 4, 136 POSITION_2_VECTORS_SPRITE_KILL = 5, 137 POSITION_2_VECTORS_EDGE_KILL = 6, 138 MULTIPASS = 7, 139 }; 140 141 enum a2xx_sq_sample_cntl { 142 CENTROIDS_ONLY = 0, 143 CENTERS_ONLY = 1, 144 CENTROIDS_AND_CENTERS = 2, 145 }; 146 147 enum a2xx_dx_clip_space { 148 DXCLIP_OPENGL = 0, 149 DXCLIP_DIRECTX = 1, 150 }; 151 152 enum a2xx_pa_su_sc_polymode { 153 POLY_DISABLED = 0, 154 POLY_DUALMODE = 1, 155 }; 156 157 enum a2xx_rb_edram_mode { 158 EDRAM_NOP = 0, 159 COLOR_DEPTH = 4, 160 DEPTH_ONLY = 5, 161 EDRAM_COPY = 6, 162 }; 163 164 enum a2xx_pa_sc_pattern_bit_order { 165 LITTLE = 0, 166 BIG = 1, 167 }; 168 169 enum a2xx_pa_sc_auto_reset_cntl { 170 NEVER = 0, 171 EACH_PRIMITIVE = 1, 172 EACH_PACKET = 2, 173 }; 174 175 enum a2xx_pa_pixcenter { 176 PIXCENTER_D3D = 0, 177 PIXCENTER_OGL = 1, 178 }; 179 180 enum a2xx_pa_roundmode { 181 TRUNCATE = 0, 182 ROUND = 1, 183 ROUNDTOEVEN = 2, 184 ROUNDTOODD = 3, 185 }; 186 187 enum a2xx_pa_quantmode { 188 ONE_SIXTEENTH = 0, 189 ONE_EIGTH = 1, 190 ONE_QUARTER = 2, 191 ONE_HALF = 3, 192 ONE = 4, 193 }; 194 195 enum a2xx_rb_copy_sample_select { 196 SAMPLE_0 = 0, 197 SAMPLE_1 = 1, 198 SAMPLE_2 = 2, 199 SAMPLE_3 = 3, 200 SAMPLE_01 = 4, 201 SAMPLE_23 = 5, 202 SAMPLE_0123 = 6, 203 }; 204 205 enum sq_tex_clamp { 206 SQ_TEX_WRAP = 0, 207 SQ_TEX_MIRROR = 1, 208 SQ_TEX_CLAMP_LAST_TEXEL = 2, 209 SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3, 210 SQ_TEX_CLAMP_HALF_BORDER = 4, 211 SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5, 212 SQ_TEX_CLAMP_BORDER = 6, 213 SQ_TEX_MIRROR_ONCE_BORDER = 7, 214 }; 215 216 enum sq_tex_swiz { 217 SQ_TEX_X = 0, 218 SQ_TEX_Y = 1, 219 SQ_TEX_Z = 2, 220 SQ_TEX_W = 3, 221 SQ_TEX_ZERO = 4, 222 SQ_TEX_ONE = 5, 223 }; 224 225 enum sq_tex_filter { 226 SQ_TEX_FILTER_POINT = 0, 227 SQ_TEX_FILTER_BILINEAR = 1, 228 SQ_TEX_FILTER_BICUBIC = 2, 229 }; 230 231 #define REG_A2XX_RBBM_PATCH_RELEASE 0x00000001 232 233 #define REG_A2XX_RBBM_CNTL 0x0000003b 234 235 #define REG_A2XX_RBBM_SOFT_RESET 0x0000003c 236 237 #define REG_A2XX_CP_PFP_UCODE_ADDR 0x000000c0 238 239 #define REG_A2XX_CP_PFP_UCODE_DATA 0x000000c1 240 241 #define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395 242 243 #define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397 244 245 #define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x00000398 246 247 #define REG_A2XX_RBBM_DEBUG 0x0000039b 248 249 #define REG_A2XX_RBBM_PM_OVERRIDE1 0x0000039c 250 251 #define REG_A2XX_RBBM_PM_OVERRIDE2 0x0000039d 252 253 #define REG_A2XX_RBBM_DEBUG_OUT 0x000003a0 254 255 #define REG_A2XX_RBBM_DEBUG_CNTL 0x000003a1 256 257 #define REG_A2XX_RBBM_READ_ERROR 0x000003b3 258 259 #define REG_A2XX_RBBM_INT_CNTL 0x000003b4 260 261 #define REG_A2XX_RBBM_INT_STATUS 0x000003b5 262 263 #define REG_A2XX_RBBM_INT_ACK 0x000003b6 264 265 #define REG_A2XX_MASTER_INT_SIGNAL 0x000003b7 266 267 #define REG_A2XX_RBBM_PERIPHID1 0x000003f9 268 269 #define REG_A2XX_RBBM_PERIPHID2 0x000003fa 270 271 #define REG_A2XX_CP_PERFMON_CNTL 0x00000444 272 273 #define REG_A2XX_CP_PERFCOUNTER_SELECT 0x00000445 274 275 #define REG_A2XX_CP_PERFCOUNTER_LO 0x00000446 276 277 #define REG_A2XX_CP_PERFCOUNTER_HI 0x00000447 278 279 #define REG_A2XX_CP_ST_BASE 0x0000044d 280 281 #define REG_A2XX_CP_ST_BUFSZ 0x0000044e 282 283 #define REG_A2XX_CP_IB1_BASE 0x00000458 284 285 #define REG_A2XX_CP_IB1_BUFSZ 0x00000459 286 287 #define REG_A2XX_CP_IB2_BASE 0x0000045a 288 289 #define REG_A2XX_CP_IB2_BUFSZ 0x0000045b 290 291 #define REG_A2XX_CP_STAT 0x0000047f 292 293 #define REG_A2XX_RBBM_STATUS 0x000005d0 294 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK 0x0000001f 295 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT 0 296 static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val) 297 { 298 return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK; 299 } 300 #define A2XX_RBBM_STATUS_TC_BUSY 0x00000020 301 #define A2XX_RBBM_STATUS_HIRQ_PENDING 0x00000100 302 #define A2XX_RBBM_STATUS_CPRQ_PENDING 0x00000200 303 #define A2XX_RBBM_STATUS_CFRQ_PENDING 0x00000400 304 #define A2XX_RBBM_STATUS_PFRQ_PENDING 0x00000800 305 #define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA 0x00001000 306 #define A2XX_RBBM_STATUS_RBBM_WU_BUSY 0x00004000 307 #define A2XX_RBBM_STATUS_CP_NRT_BUSY 0x00010000 308 #define A2XX_RBBM_STATUS_MH_BUSY 0x00040000 309 #define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY 0x00080000 310 #define A2XX_RBBM_STATUS_SX_BUSY 0x00200000 311 #define A2XX_RBBM_STATUS_TPC_BUSY 0x00400000 312 #define A2XX_RBBM_STATUS_SC_CNTX_BUSY 0x01000000 313 #define A2XX_RBBM_STATUS_PA_BUSY 0x02000000 314 #define A2XX_RBBM_STATUS_VGT_BUSY 0x04000000 315 #define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY 0x08000000 316 #define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY 0x10000000 317 #define A2XX_RBBM_STATUS_RB_CNTX_BUSY 0x40000000 318 #define A2XX_RBBM_STATUS_GUI_ACTIVE 0x80000000 319 320 #define REG_A2XX_A220_VSC_BIN_SIZE 0x00000c01 321 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 322 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT 0 323 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val) 324 { 325 return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK; 326 } 327 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 328 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT 5 329 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val) 330 { 331 return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK; 332 } 333 334 static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 335 336 static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 337 338 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } 339 340 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } 341 342 #define REG_A2XX_PC_DEBUG_CNTL 0x00000c38 343 344 #define REG_A2XX_PC_DEBUG_DATA 0x00000c39 345 346 #define REG_A2XX_PA_SC_VIZ_QUERY_STATUS 0x00000c44 347 348 #define REG_A2XX_GRAS_DEBUG_CNTL 0x00000c80 349 350 #define REG_A2XX_PA_SU_DEBUG_CNTL 0x00000c80 351 352 #define REG_A2XX_GRAS_DEBUG_DATA 0x00000c81 353 354 #define REG_A2XX_PA_SU_DEBUG_DATA 0x00000c81 355 356 #define REG_A2XX_PA_SU_FACE_DATA 0x00000c86 357 358 #define REG_A2XX_SQ_GPR_MANAGEMENT 0x00000d00 359 360 #define REG_A2XX_SQ_FLOW_CONTROL 0x00000d01 361 362 #define REG_A2XX_SQ_INST_STORE_MANAGMENT 0x00000d02 363 364 #define REG_A2XX_SQ_DEBUG_MISC 0x00000d05 365 366 #define REG_A2XX_SQ_INT_CNTL 0x00000d34 367 368 #define REG_A2XX_SQ_INT_STATUS 0x00000d35 369 370 #define REG_A2XX_SQ_INT_ACK 0x00000d36 371 372 #define REG_A2XX_SQ_DEBUG_INPUT_FSM 0x00000dae 373 374 #define REG_A2XX_SQ_DEBUG_CONST_MGR_FSM 0x00000daf 375 376 #define REG_A2XX_SQ_DEBUG_TP_FSM 0x00000db0 377 378 #define REG_A2XX_SQ_DEBUG_FSM_ALU_0 0x00000db1 379 380 #define REG_A2XX_SQ_DEBUG_FSM_ALU_1 0x00000db2 381 382 #define REG_A2XX_SQ_DEBUG_EXP_ALLOC 0x00000db3 383 384 #define REG_A2XX_SQ_DEBUG_PTR_BUFF 0x00000db4 385 386 #define REG_A2XX_SQ_DEBUG_GPR_VTX 0x00000db5 387 388 #define REG_A2XX_SQ_DEBUG_GPR_PIX 0x00000db6 389 390 #define REG_A2XX_SQ_DEBUG_TB_STATUS_SEL 0x00000db7 391 392 #define REG_A2XX_SQ_DEBUG_VTX_TB_0 0x00000db8 393 394 #define REG_A2XX_SQ_DEBUG_VTX_TB_1 0x00000db9 395 396 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG 0x00000dba 397 398 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM 0x00000dbb 399 400 #define REG_A2XX_SQ_DEBUG_PIX_TB_0 0x00000dbc 401 402 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0 0x00000dbd 403 404 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1 0x00000dbe 405 406 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2 0x00000dbf 407 408 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3 0x00000dc0 409 410 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM 0x00000dc1 411 412 #define REG_A2XX_TC_CNTL_STATUS 0x00000e00 413 #define A2XX_TC_CNTL_STATUS_L2_INVALIDATE 0x00000001 414 415 #define REG_A2XX_TP0_CHICKEN 0x00000e1e 416 417 #define REG_A2XX_RB_BC_CONTROL 0x00000f01 418 #define A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE 0x00000001 419 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK 0x00000006 420 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT 1 421 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val) 422 { 423 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK; 424 } 425 #define A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM 0x00000008 426 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010 427 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP 0x00000020 428 #define A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP 0x00000040 429 #define A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE 0x00000080 430 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK 0x00001f00 431 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT 8 432 static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val) 433 { 434 return ((val) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK; 435 } 436 #define A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE 0x00004000 437 #define A2XX_RB_BC_CONTROL_CRC_MODE 0x00008000 438 #define A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS 0x00010000 439 #define A2XX_RB_BC_CONTROL_DISABLE_ACCUM 0x00020000 440 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK 0x003c0000 441 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT 18 442 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val) 443 { 444 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK; 445 } 446 #define A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE 0x00400000 447 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK 0x07800000 448 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT 23 449 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val) 450 { 451 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK; 452 } 453 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK 0x18000000 454 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT 27 455 static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val) 456 { 457 return ((val) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK; 458 } 459 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000 460 #define A2XX_RB_BC_CONTROL_CRC_SYSTEM 0x40000000 461 #define A2XX_RB_BC_CONTROL_RESERVED6 0x80000000 462 463 #define REG_A2XX_RB_EDRAM_INFO 0x00000f02 464 465 #define REG_A2XX_RB_DEBUG_CNTL 0x00000f26 466 467 #define REG_A2XX_RB_DEBUG_DATA 0x00000f27 468 469 #define REG_A2XX_RB_SURFACE_INFO 0x00002000 470 471 #define REG_A2XX_RB_COLOR_INFO 0x00002001 472 #define A2XX_RB_COLOR_INFO_FORMAT__MASK 0x0000000f 473 #define A2XX_RB_COLOR_INFO_FORMAT__SHIFT 0 474 static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val) 475 { 476 return ((val) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT) & A2XX_RB_COLOR_INFO_FORMAT__MASK; 477 } 478 #define A2XX_RB_COLOR_INFO_ROUND_MODE__MASK 0x00000030 479 #define A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT 4 480 static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val) 481 { 482 return ((val) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK; 483 } 484 #define A2XX_RB_COLOR_INFO_LINEAR 0x00000040 485 #define A2XX_RB_COLOR_INFO_ENDIAN__MASK 0x00000180 486 #define A2XX_RB_COLOR_INFO_ENDIAN__SHIFT 7 487 static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val) 488 { 489 return ((val) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT) & A2XX_RB_COLOR_INFO_ENDIAN__MASK; 490 } 491 #define A2XX_RB_COLOR_INFO_SWAP__MASK 0x00000600 492 #define A2XX_RB_COLOR_INFO_SWAP__SHIFT 9 493 static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val) 494 { 495 return ((val) << A2XX_RB_COLOR_INFO_SWAP__SHIFT) & A2XX_RB_COLOR_INFO_SWAP__MASK; 496 } 497 #define A2XX_RB_COLOR_INFO_BASE__MASK 0xfffff000 498 #define A2XX_RB_COLOR_INFO_BASE__SHIFT 12 499 static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val) 500 { 501 return ((val >> 10) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK; 502 } 503 504 #define REG_A2XX_RB_DEPTH_INFO 0x00002002 505 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001 506 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 507 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) 508 { 509 return ((val) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 510 } 511 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 512 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 513 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 514 { 515 return ((val >> 10) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 516 } 517 518 #define REG_A2XX_A225_RB_COLOR_INFO3 0x00002005 519 520 #define REG_A2XX_COHER_DEST_BASE_0 0x00002006 521 522 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_TL 0x0000200e 523 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 524 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 525 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 526 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 527 { 528 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK; 529 } 530 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 531 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 532 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 533 { 534 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK; 535 } 536 537 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_BR 0x0000200f 538 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 539 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 540 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 541 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 542 { 543 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK; 544 } 545 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 546 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 547 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 548 { 549 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK; 550 } 551 552 #define REG_A2XX_PA_SC_WINDOW_OFFSET 0x00002080 553 #define A2XX_PA_SC_WINDOW_OFFSET_X__MASK 0x00007fff 554 #define A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT 0 555 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val) 556 { 557 return ((val) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK; 558 } 559 #define A2XX_PA_SC_WINDOW_OFFSET_Y__MASK 0x7fff0000 560 #define A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT 16 561 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val) 562 { 563 return ((val) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK; 564 } 565 #define A2XX_PA_SC_WINDOW_OFFSET_DISABLE 0x80000000 566 567 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_TL 0x00002081 568 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 569 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 570 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 571 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 572 { 573 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK; 574 } 575 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 576 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 577 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 578 { 579 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK; 580 } 581 582 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_BR 0x00002082 583 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 584 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 585 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 586 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 587 { 588 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK; 589 } 590 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 591 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 592 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 593 { 594 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK; 595 } 596 597 #define REG_A2XX_UNKNOWN_2010 0x00002010 598 599 #define REG_A2XX_VGT_MAX_VTX_INDX 0x00002100 600 601 #define REG_A2XX_VGT_MIN_VTX_INDX 0x00002101 602 603 #define REG_A2XX_VGT_INDX_OFFSET 0x00002102 604 605 #define REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX 0x00002103 606 607 #define REG_A2XX_RB_COLOR_MASK 0x00002104 608 #define A2XX_RB_COLOR_MASK_WRITE_RED 0x00000001 609 #define A2XX_RB_COLOR_MASK_WRITE_GREEN 0x00000002 610 #define A2XX_RB_COLOR_MASK_WRITE_BLUE 0x00000004 611 #define A2XX_RB_COLOR_MASK_WRITE_ALPHA 0x00000008 612 613 #define REG_A2XX_RB_BLEND_RED 0x00002105 614 615 #define REG_A2XX_RB_BLEND_GREEN 0x00002106 616 617 #define REG_A2XX_RB_BLEND_BLUE 0x00002107 618 619 #define REG_A2XX_RB_BLEND_ALPHA 0x00002108 620 621 #define REG_A2XX_RB_FOG_COLOR 0x00002109 622 623 #define REG_A2XX_RB_STENCILREFMASK_BF 0x0000210c 624 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 625 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 626 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 627 { 628 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 629 } 630 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 631 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 632 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 633 { 634 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 635 } 636 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 637 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 638 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 639 { 640 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 641 } 642 643 #define REG_A2XX_RB_STENCILREFMASK 0x0000210d 644 #define A2XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 645 #define A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 646 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 647 { 648 return ((val) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK; 649 } 650 #define A2XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 651 #define A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 652 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 653 { 654 return ((val) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK; 655 } 656 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 657 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 658 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 659 { 660 return ((val) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 661 } 662 663 #define REG_A2XX_RB_ALPHA_REF 0x0000210e 664 665 #define REG_A2XX_PA_CL_VPORT_XSCALE 0x0000210f 666 #define A2XX_PA_CL_VPORT_XSCALE__MASK 0xffffffff 667 #define A2XX_PA_CL_VPORT_XSCALE__SHIFT 0 668 static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val) 669 { 670 return ((fui(val)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT) & A2XX_PA_CL_VPORT_XSCALE__MASK; 671 } 672 673 #define REG_A2XX_PA_CL_VPORT_XOFFSET 0x00002110 674 #define A2XX_PA_CL_VPORT_XOFFSET__MASK 0xffffffff 675 #define A2XX_PA_CL_VPORT_XOFFSET__SHIFT 0 676 static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val) 677 { 678 return ((fui(val)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT) & A2XX_PA_CL_VPORT_XOFFSET__MASK; 679 } 680 681 #define REG_A2XX_PA_CL_VPORT_YSCALE 0x00002111 682 #define A2XX_PA_CL_VPORT_YSCALE__MASK 0xffffffff 683 #define A2XX_PA_CL_VPORT_YSCALE__SHIFT 0 684 static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val) 685 { 686 return ((fui(val)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT) & A2XX_PA_CL_VPORT_YSCALE__MASK; 687 } 688 689 #define REG_A2XX_PA_CL_VPORT_YOFFSET 0x00002112 690 #define A2XX_PA_CL_VPORT_YOFFSET__MASK 0xffffffff 691 #define A2XX_PA_CL_VPORT_YOFFSET__SHIFT 0 692 static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val) 693 { 694 return ((fui(val)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT) & A2XX_PA_CL_VPORT_YOFFSET__MASK; 695 } 696 697 #define REG_A2XX_PA_CL_VPORT_ZSCALE 0x00002113 698 #define A2XX_PA_CL_VPORT_ZSCALE__MASK 0xffffffff 699 #define A2XX_PA_CL_VPORT_ZSCALE__SHIFT 0 700 static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val) 701 { 702 return ((fui(val)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT) & A2XX_PA_CL_VPORT_ZSCALE__MASK; 703 } 704 705 #define REG_A2XX_PA_CL_VPORT_ZOFFSET 0x00002114 706 #define A2XX_PA_CL_VPORT_ZOFFSET__MASK 0xffffffff 707 #define A2XX_PA_CL_VPORT_ZOFFSET__SHIFT 0 708 static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val) 709 { 710 return ((fui(val)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT) & A2XX_PA_CL_VPORT_ZOFFSET__MASK; 711 } 712 713 #define REG_A2XX_SQ_PROGRAM_CNTL 0x00002180 714 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK 0x000000ff 715 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT 0 716 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val) 717 { 718 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK; 719 } 720 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK 0x0000ff00 721 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT 8 722 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val) 723 { 724 return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK; 725 } 726 #define A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE 0x00010000 727 #define A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE 0x00020000 728 #define A2XX_SQ_PROGRAM_CNTL_PARAM_GEN 0x00040000 729 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX 0x00080000 730 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK 0x00f00000 731 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT 20 732 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val) 733 { 734 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK; 735 } 736 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK 0x07000000 737 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT 24 738 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val) 739 { 740 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK; 741 } 742 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK 0x78000000 743 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT 27 744 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val) 745 { 746 return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK; 747 } 748 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX 0x80000000 749 750 #define REG_A2XX_SQ_CONTEXT_MISC 0x00002181 751 #define A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE 0x00000001 752 #define A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY 0x00000002 753 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK 0x0000000c 754 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT 2 755 static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val) 756 { 757 return ((val) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK; 758 } 759 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK 0x0000ff00 760 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT 8 761 static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val) 762 { 763 return ((val) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK; 764 } 765 #define A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF 0x00010000 766 #define A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE 0x00020000 767 #define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL 0x00040000 768 769 #define REG_A2XX_SQ_INTERPOLATOR_CNTL 0x00002182 770 771 #define REG_A2XX_SQ_WRAPPING_0 0x00002183 772 773 #define REG_A2XX_SQ_WRAPPING_1 0x00002184 774 775 #define REG_A2XX_SQ_PS_PROGRAM 0x000021f6 776 777 #define REG_A2XX_SQ_VS_PROGRAM 0x000021f7 778 779 #define REG_A2XX_RB_DEPTHCONTROL 0x00002200 780 #define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE 0x00000001 781 #define A2XX_RB_DEPTHCONTROL_Z_ENABLE 0x00000002 782 #define A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE 0x00000004 783 #define A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE 0x00000008 784 #define A2XX_RB_DEPTHCONTROL_ZFUNC__MASK 0x00000070 785 #define A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT 4 786 static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val) 787 { 788 return ((val) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK; 789 } 790 #define A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE 0x00000080 791 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK 0x00000700 792 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT 8 793 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val) 794 { 795 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK; 796 } 797 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK 0x00003800 798 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT 11 799 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val) 800 { 801 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK; 802 } 803 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK 0x0001c000 804 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT 14 805 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val) 806 { 807 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK; 808 } 809 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK 0x000e0000 810 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT 17 811 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val) 812 { 813 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK; 814 } 815 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK 0x00700000 816 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT 20 817 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val) 818 { 819 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK; 820 } 821 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK 0x03800000 822 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT 23 823 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val) 824 { 825 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK; 826 } 827 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK 0x1c000000 828 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT 26 829 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val) 830 { 831 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK; 832 } 833 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK 0xe0000000 834 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT 29 835 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val) 836 { 837 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK; 838 } 839 840 #define REG_A2XX_RB_BLEND_CONTROL 0x00002201 841 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK 0x0000001f 842 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT 0 843 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val) 844 { 845 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK; 846 } 847 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK 0x000000e0 848 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT 5 849 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum adreno_rb_blend_opcode val) 850 { 851 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK; 852 } 853 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK 0x00001f00 854 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT 8 855 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val) 856 { 857 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK; 858 } 859 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK 0x001f0000 860 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT 16 861 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val) 862 { 863 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK; 864 } 865 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK 0x00e00000 866 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT 21 867 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum adreno_rb_blend_opcode val) 868 { 869 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK; 870 } 871 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK 0x1f000000 872 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT 24 873 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val) 874 { 875 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK; 876 } 877 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE 0x20000000 878 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE 0x40000000 879 880 #define REG_A2XX_RB_COLORCONTROL 0x00002202 881 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK 0x00000007 882 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT 0 883 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val) 884 { 885 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK; 886 } 887 #define A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE 0x00000008 888 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE 0x00000010 889 #define A2XX_RB_COLORCONTROL_BLEND_DISABLE 0x00000020 890 #define A2XX_RB_COLORCONTROL_VOB_ENABLE 0x00000040 891 #define A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG 0x00000080 892 #define A2XX_RB_COLORCONTROL_ROP_CODE__MASK 0x00000f00 893 #define A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT 8 894 static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val) 895 { 896 return ((val) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK; 897 } 898 #define A2XX_RB_COLORCONTROL_DITHER_MODE__MASK 0x00003000 899 #define A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT 12 900 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) 901 { 902 return ((val) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK; 903 } 904 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK 0x0000c000 905 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT 14 906 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val) 907 { 908 return ((val) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK; 909 } 910 #define A2XX_RB_COLORCONTROL_PIXEL_FOG 0x00010000 911 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK 0x03000000 912 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT 24 913 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val) 914 { 915 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK; 916 } 917 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK 0x0c000000 918 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT 26 919 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val) 920 { 921 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK; 922 } 923 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK 0x30000000 924 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT 28 925 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val) 926 { 927 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK; 928 } 929 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK 0xc0000000 930 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT 30 931 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val) 932 { 933 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK; 934 } 935 936 #define REG_A2XX_VGT_CURRENT_BIN_ID_MAX 0x00002203 937 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK 0x00000007 938 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT 0 939 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val) 940 { 941 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK; 942 } 943 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK 0x00000038 944 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT 3 945 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val) 946 { 947 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK; 948 } 949 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK 0x000001c0 950 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT 6 951 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val) 952 { 953 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK; 954 } 955 956 #define REG_A2XX_PA_CL_CLIP_CNTL 0x00002204 957 #define A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 958 #define A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA 0x00040000 959 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK 0x00080000 960 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT 19 961 static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val) 962 { 963 return ((val) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK; 964 } 965 #define A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT 0x00100000 966 #define A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR 0x00200000 967 #define A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN 0x00400000 968 #define A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN 0x00800000 969 #define A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN 0x01000000 970 971 #define REG_A2XX_PA_SU_SC_MODE_CNTL 0x00002205 972 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT 0x00000001 973 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK 0x00000002 974 #define A2XX_PA_SU_SC_MODE_CNTL_FACE 0x00000004 975 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK 0x00000018 976 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT 3 977 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val) 978 { 979 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK; 980 } 981 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK 0x000000e0 982 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT 5 983 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 984 { 985 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK; 986 } 987 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK 0x00000700 988 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT 8 989 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 990 { 991 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK; 992 } 993 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE 0x00000800 994 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE 0x00001000 995 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE 0x00002000 996 #define A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE 0x00008000 997 #define A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE 0x00010000 998 #define A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE 0x00040000 999 #define A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST 0x00080000 1000 #define A2XX_PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS 0x00100000 1001 #define A2XX_PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA 0x00200000 1002 #define A2XX_PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE 0x00800000 1003 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI 0x02000000 1004 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000 1005 #define A2XX_PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS 0x10000000 1006 #define A2XX_PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS 0x20000000 1007 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE 0x40000000 1008 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE 0x80000000 1009 1010 #define REG_A2XX_PA_CL_VTE_CNTL 0x00002206 1011 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA 0x00000001 1012 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA 0x00000002 1013 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA 0x00000004 1014 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA 0x00000008 1015 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA 0x00000010 1016 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA 0x00000020 1017 #define A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT 0x00000100 1018 #define A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT 0x00000200 1019 #define A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT 0x00000400 1020 #define A2XX_PA_CL_VTE_CNTL_PERFCOUNTER_REF 0x00000800 1021 1022 #define REG_A2XX_VGT_CURRENT_BIN_ID_MIN 0x00002207 1023 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK 0x00000007 1024 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT 0 1025 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val) 1026 { 1027 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK; 1028 } 1029 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK 0x00000038 1030 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT 3 1031 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val) 1032 { 1033 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK; 1034 } 1035 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK 0x000001c0 1036 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT 6 1037 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val) 1038 { 1039 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK; 1040 } 1041 1042 #define REG_A2XX_RB_MODECONTROL 0x00002208 1043 #define A2XX_RB_MODECONTROL_EDRAM_MODE__MASK 0x00000007 1044 #define A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT 0 1045 static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val) 1046 { 1047 return ((val) << A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT) & A2XX_RB_MODECONTROL_EDRAM_MODE__MASK; 1048 } 1049 1050 #define REG_A2XX_A220_RB_LRZ_VSC_CONTROL 0x00002209 1051 1052 #define REG_A2XX_RB_SAMPLE_POS 0x0000220a 1053 1054 #define REG_A2XX_CLEAR_COLOR 0x0000220b 1055 #define A2XX_CLEAR_COLOR_RED__MASK 0x000000ff 1056 #define A2XX_CLEAR_COLOR_RED__SHIFT 0 1057 static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val) 1058 { 1059 return ((val) << A2XX_CLEAR_COLOR_RED__SHIFT) & A2XX_CLEAR_COLOR_RED__MASK; 1060 } 1061 #define A2XX_CLEAR_COLOR_GREEN__MASK 0x0000ff00 1062 #define A2XX_CLEAR_COLOR_GREEN__SHIFT 8 1063 static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val) 1064 { 1065 return ((val) << A2XX_CLEAR_COLOR_GREEN__SHIFT) & A2XX_CLEAR_COLOR_GREEN__MASK; 1066 } 1067 #define A2XX_CLEAR_COLOR_BLUE__MASK 0x00ff0000 1068 #define A2XX_CLEAR_COLOR_BLUE__SHIFT 16 1069 static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val) 1070 { 1071 return ((val) << A2XX_CLEAR_COLOR_BLUE__SHIFT) & A2XX_CLEAR_COLOR_BLUE__MASK; 1072 } 1073 #define A2XX_CLEAR_COLOR_ALPHA__MASK 0xff000000 1074 #define A2XX_CLEAR_COLOR_ALPHA__SHIFT 24 1075 static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val) 1076 { 1077 return ((val) << A2XX_CLEAR_COLOR_ALPHA__SHIFT) & A2XX_CLEAR_COLOR_ALPHA__MASK; 1078 } 1079 1080 #define REG_A2XX_A220_GRAS_CONTROL 0x00002210 1081 1082 #define REG_A2XX_PA_SU_POINT_SIZE 0x00002280 1083 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK 0x0000ffff 1084 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT 0 1085 static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val) 1086 { 1087 return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK; 1088 } 1089 #define A2XX_PA_SU_POINT_SIZE_WIDTH__MASK 0xffff0000 1090 #define A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT 16 1091 static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val) 1092 { 1093 return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK; 1094 } 1095 1096 #define REG_A2XX_PA_SU_POINT_MINMAX 0x00002281 1097 #define A2XX_PA_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 1098 #define A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT 0 1099 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val) 1100 { 1101 return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK; 1102 } 1103 #define A2XX_PA_SU_POINT_MINMAX_MAX__MASK 0xffff0000 1104 #define A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT 16 1105 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val) 1106 { 1107 return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK; 1108 } 1109 1110 #define REG_A2XX_PA_SU_LINE_CNTL 0x00002282 1111 #define A2XX_PA_SU_LINE_CNTL_WIDTH__MASK 0x0000ffff 1112 #define A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT 0 1113 static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val) 1114 { 1115 return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK; 1116 } 1117 1118 #define REG_A2XX_PA_SC_LINE_STIPPLE 0x00002283 1119 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK 0x0000ffff 1120 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT 0 1121 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val) 1122 { 1123 return ((val) << A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK; 1124 } 1125 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK 0x00ff0000 1126 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT 16 1127 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val) 1128 { 1129 return ((val) << A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK; 1130 } 1131 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK 0x10000000 1132 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT 28 1133 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val) 1134 { 1135 return ((val) << A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK; 1136 } 1137 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK 0x60000000 1138 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT 29 1139 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val) 1140 { 1141 return ((val) << A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK; 1142 } 1143 1144 #define REG_A2XX_PA_SC_VIZ_QUERY 0x00002293 1145 1146 #define REG_A2XX_VGT_ENHANCE 0x00002294 1147 1148 #define REG_A2XX_PA_SC_LINE_CNTL 0x00002300 1149 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK 0x0000ffff 1150 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT 0 1151 static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val) 1152 { 1153 return ((val) << A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT) & A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK; 1154 } 1155 #define A2XX_PA_SC_LINE_CNTL_USE_BRES_CNTL 0x00000100 1156 #define A2XX_PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH 0x00000200 1157 #define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL 0x00000400 1158 1159 #define REG_A2XX_PA_SC_AA_CONFIG 0x00002301 1160 1161 #define REG_A2XX_PA_SU_VTX_CNTL 0x00002302 1162 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK 0x00000001 1163 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT 0 1164 static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val) 1165 { 1166 return ((val) << A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT) & A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK; 1167 } 1168 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK 0x00000006 1169 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT 1 1170 static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val) 1171 { 1172 return ((val) << A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK; 1173 } 1174 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK 0x00000380 1175 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT 7 1176 static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val) 1177 { 1178 return ((val) << A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK; 1179 } 1180 1181 #define REG_A2XX_PA_CL_GB_VERT_CLIP_ADJ 0x00002303 1182 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK 0xffffffff 1183 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT 0 1184 static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val) 1185 { 1186 return ((fui(val)) << A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK; 1187 } 1188 1189 #define REG_A2XX_PA_CL_GB_VERT_DISC_ADJ 0x00002304 1190 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK 0xffffffff 1191 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT 0 1192 static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val) 1193 { 1194 return ((fui(val)) << A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK; 1195 } 1196 1197 #define REG_A2XX_PA_CL_GB_HORZ_CLIP_ADJ 0x00002305 1198 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK 0xffffffff 1199 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT 0 1200 static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val) 1201 { 1202 return ((fui(val)) << A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK; 1203 } 1204 1205 #define REG_A2XX_PA_CL_GB_HORZ_DISC_ADJ 0x00002306 1206 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK 0xffffffff 1207 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT 0 1208 static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val) 1209 { 1210 return ((fui(val)) << A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK; 1211 } 1212 1213 #define REG_A2XX_SQ_VS_CONST 0x00002307 1214 #define A2XX_SQ_VS_CONST_BASE__MASK 0x000001ff 1215 #define A2XX_SQ_VS_CONST_BASE__SHIFT 0 1216 static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val) 1217 { 1218 return ((val) << A2XX_SQ_VS_CONST_BASE__SHIFT) & A2XX_SQ_VS_CONST_BASE__MASK; 1219 } 1220 #define A2XX_SQ_VS_CONST_SIZE__MASK 0x001ff000 1221 #define A2XX_SQ_VS_CONST_SIZE__SHIFT 12 1222 static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val) 1223 { 1224 return ((val) << A2XX_SQ_VS_CONST_SIZE__SHIFT) & A2XX_SQ_VS_CONST_SIZE__MASK; 1225 } 1226 1227 #define REG_A2XX_SQ_PS_CONST 0x00002308 1228 #define A2XX_SQ_PS_CONST_BASE__MASK 0x000001ff 1229 #define A2XX_SQ_PS_CONST_BASE__SHIFT 0 1230 static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val) 1231 { 1232 return ((val) << A2XX_SQ_PS_CONST_BASE__SHIFT) & A2XX_SQ_PS_CONST_BASE__MASK; 1233 } 1234 #define A2XX_SQ_PS_CONST_SIZE__MASK 0x001ff000 1235 #define A2XX_SQ_PS_CONST_SIZE__SHIFT 12 1236 static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val) 1237 { 1238 return ((val) << A2XX_SQ_PS_CONST_SIZE__SHIFT) & A2XX_SQ_PS_CONST_SIZE__MASK; 1239 } 1240 1241 #define REG_A2XX_SQ_DEBUG_MISC_0 0x00002309 1242 1243 #define REG_A2XX_SQ_DEBUG_MISC_1 0x0000230a 1244 1245 #define REG_A2XX_PA_SC_AA_MASK 0x00002312 1246 1247 #define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL 0x00002316 1248 1249 #define REG_A2XX_VGT_OUT_DEALLOC_CNTL 0x00002317 1250 1251 #define REG_A2XX_RB_COPY_CONTROL 0x00002318 1252 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK 0x00000007 1253 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT 0 1254 static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val) 1255 { 1256 return ((val) << A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT) & A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK; 1257 } 1258 #define A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE 0x00000008 1259 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK 0x000000f0 1260 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT 4 1261 static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val) 1262 { 1263 return ((val) << A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT) & A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK; 1264 } 1265 1266 #define REG_A2XX_RB_COPY_DEST_BASE 0x00002319 1267 1268 #define REG_A2XX_RB_COPY_DEST_PITCH 0x0000231a 1269 #define A2XX_RB_COPY_DEST_PITCH__MASK 0xffffffff 1270 #define A2XX_RB_COPY_DEST_PITCH__SHIFT 0 1271 static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val) 1272 { 1273 return ((val >> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK; 1274 } 1275 1276 #define REG_A2XX_RB_COPY_DEST_INFO 0x0000231b 1277 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK 0x00000007 1278 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT 0 1279 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val) 1280 { 1281 return ((val) << A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT) & A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK; 1282 } 1283 #define A2XX_RB_COPY_DEST_INFO_LINEAR 0x00000008 1284 #define A2XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000f0 1285 #define A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 4 1286 static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val) 1287 { 1288 return ((val) << A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A2XX_RB_COPY_DEST_INFO_FORMAT__MASK; 1289 } 1290 #define A2XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 1291 #define A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 1292 static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val) 1293 { 1294 return ((val) << A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A2XX_RB_COPY_DEST_INFO_SWAP__MASK; 1295 } 1296 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 1297 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 1298 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 1299 { 1300 return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 1301 } 1302 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK 0x00003000 1303 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT 12 1304 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val) 1305 { 1306 return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK; 1307 } 1308 #define A2XX_RB_COPY_DEST_INFO_WRITE_RED 0x00004000 1309 #define A2XX_RB_COPY_DEST_INFO_WRITE_GREEN 0x00008000 1310 #define A2XX_RB_COPY_DEST_INFO_WRITE_BLUE 0x00010000 1311 #define A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA 0x00020000 1312 1313 #define REG_A2XX_RB_COPY_DEST_OFFSET 0x0000231c 1314 #define A2XX_RB_COPY_DEST_OFFSET_X__MASK 0x00001fff 1315 #define A2XX_RB_COPY_DEST_OFFSET_X__SHIFT 0 1316 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val) 1317 { 1318 return ((val) << A2XX_RB_COPY_DEST_OFFSET_X__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_X__MASK; 1319 } 1320 #define A2XX_RB_COPY_DEST_OFFSET_Y__MASK 0x03ffe000 1321 #define A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT 13 1322 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val) 1323 { 1324 return ((val) << A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_Y__MASK; 1325 } 1326 1327 #define REG_A2XX_RB_DEPTH_CLEAR 0x0000231d 1328 1329 #define REG_A2XX_RB_SAMPLE_COUNT_CTL 0x00002324 1330 1331 #define REG_A2XX_RB_COLOR_DEST_MASK 0x00002326 1332 1333 #define REG_A2XX_A225_GRAS_UCP0X 0x00002340 1334 1335 #define REG_A2XX_A225_GRAS_UCP5W 0x00002357 1336 1337 #define REG_A2XX_A225_GRAS_UCP_ENABLED 0x00002360 1338 1339 #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE 0x00002380 1340 1341 #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET 0x00002383 1342 1343 #define REG_A2XX_SQ_CONSTANT_0 0x00004000 1344 1345 #define REG_A2XX_SQ_FETCH_0 0x00004800 1346 1347 #define REG_A2XX_SQ_CF_BOOLEANS 0x00004900 1348 1349 #define REG_A2XX_SQ_CF_LOOP 0x00004908 1350 1351 #define REG_A2XX_COHER_SIZE_PM4 0x00000a29 1352 1353 #define REG_A2XX_COHER_BASE_PM4 0x00000a2a 1354 1355 #define REG_A2XX_COHER_STATUS_PM4 0x00000a2b 1356 1357 #define REG_A2XX_SQ_TEX_0 0x00000000 1358 #define A2XX_SQ_TEX_0_CLAMP_X__MASK 0x00001c00 1359 #define A2XX_SQ_TEX_0_CLAMP_X__SHIFT 10 1360 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val) 1361 { 1362 return ((val) << A2XX_SQ_TEX_0_CLAMP_X__SHIFT) & A2XX_SQ_TEX_0_CLAMP_X__MASK; 1363 } 1364 #define A2XX_SQ_TEX_0_CLAMP_Y__MASK 0x0000e000 1365 #define A2XX_SQ_TEX_0_CLAMP_Y__SHIFT 13 1366 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val) 1367 { 1368 return ((val) << A2XX_SQ_TEX_0_CLAMP_Y__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Y__MASK; 1369 } 1370 #define A2XX_SQ_TEX_0_CLAMP_Z__MASK 0x00070000 1371 #define A2XX_SQ_TEX_0_CLAMP_Z__SHIFT 16 1372 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val) 1373 { 1374 return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK; 1375 } 1376 #define A2XX_SQ_TEX_0_PITCH__MASK 0xffc00000 1377 #define A2XX_SQ_TEX_0_PITCH__SHIFT 22 1378 static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val) 1379 { 1380 return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK; 1381 } 1382 1383 #define REG_A2XX_SQ_TEX_1 0x00000001 1384 1385 #define REG_A2XX_SQ_TEX_2 0x00000002 1386 #define A2XX_SQ_TEX_2_WIDTH__MASK 0x00001fff 1387 #define A2XX_SQ_TEX_2_WIDTH__SHIFT 0 1388 static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val) 1389 { 1390 return ((val) << A2XX_SQ_TEX_2_WIDTH__SHIFT) & A2XX_SQ_TEX_2_WIDTH__MASK; 1391 } 1392 #define A2XX_SQ_TEX_2_HEIGHT__MASK 0x03ffe000 1393 #define A2XX_SQ_TEX_2_HEIGHT__SHIFT 13 1394 static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val) 1395 { 1396 return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK; 1397 } 1398 1399 #define REG_A2XX_SQ_TEX_3 0x00000003 1400 #define A2XX_SQ_TEX_3_SWIZ_X__MASK 0x0000000e 1401 #define A2XX_SQ_TEX_3_SWIZ_X__SHIFT 1 1402 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val) 1403 { 1404 return ((val) << A2XX_SQ_TEX_3_SWIZ_X__SHIFT) & A2XX_SQ_TEX_3_SWIZ_X__MASK; 1405 } 1406 #define A2XX_SQ_TEX_3_SWIZ_Y__MASK 0x00000070 1407 #define A2XX_SQ_TEX_3_SWIZ_Y__SHIFT 4 1408 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val) 1409 { 1410 return ((val) << A2XX_SQ_TEX_3_SWIZ_Y__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Y__MASK; 1411 } 1412 #define A2XX_SQ_TEX_3_SWIZ_Z__MASK 0x00000380 1413 #define A2XX_SQ_TEX_3_SWIZ_Z__SHIFT 7 1414 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val) 1415 { 1416 return ((val) << A2XX_SQ_TEX_3_SWIZ_Z__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Z__MASK; 1417 } 1418 #define A2XX_SQ_TEX_3_SWIZ_W__MASK 0x00001c00 1419 #define A2XX_SQ_TEX_3_SWIZ_W__SHIFT 10 1420 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val) 1421 { 1422 return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK; 1423 } 1424 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK 0x00180000 1425 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT 19 1426 static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val) 1427 { 1428 return ((val) << A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK; 1429 } 1430 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK 0x00600000 1431 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT 21 1432 static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val) 1433 { 1434 return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK; 1435 } 1436 1437 1438 #endif /* A2XX_XML */ 1439