1 #ifndef A2XX_XML 2 #define A2XX_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14) 12 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14) 13 - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14) 14 - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14) 15 - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14) 16 - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14) 17 - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14) 18 - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14) 19 - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14) 20 - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14) 21 - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14) 22 - /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14) 23 - /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14) 24 25 Copyright (C) 2013-2020 by the following authors: 26 - Rob Clark <robdclark@gmail.com> (robclark) 27 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 28 29 Permission is hereby granted, free of charge, to any person obtaining 30 a copy of this software and associated documentation files (the 31 "Software"), to deal in the Software without restriction, including 32 without limitation the rights to use, copy, modify, merge, publish, 33 distribute, sublicense, and/or sell copies of the Software, and to 34 permit persons to whom the Software is furnished to do so, subject to 35 the following conditions: 36 37 The above copyright notice and this permission notice (including the 38 next paragraph) shall be included in all copies or substantial 39 portions of the Software. 40 41 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 42 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 43 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 44 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 45 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 46 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 47 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 48 */ 49 50 51 enum a2xx_rb_dither_type { 52 DITHER_PIXEL = 0, 53 DITHER_SUBPIXEL = 1, 54 }; 55 56 enum a2xx_colorformatx { 57 COLORX_4_4_4_4 = 0, 58 COLORX_1_5_5_5 = 1, 59 COLORX_5_6_5 = 2, 60 COLORX_8 = 3, 61 COLORX_8_8 = 4, 62 COLORX_8_8_8_8 = 5, 63 COLORX_S8_8_8_8 = 6, 64 COLORX_16_FLOAT = 7, 65 COLORX_16_16_FLOAT = 8, 66 COLORX_16_16_16_16_FLOAT = 9, 67 COLORX_32_FLOAT = 10, 68 COLORX_32_32_FLOAT = 11, 69 COLORX_32_32_32_32_FLOAT = 12, 70 COLORX_2_3_3 = 13, 71 COLORX_8_8_8 = 14, 72 }; 73 74 enum a2xx_sq_surfaceformat { 75 FMT_1_REVERSE = 0, 76 FMT_1 = 1, 77 FMT_8 = 2, 78 FMT_1_5_5_5 = 3, 79 FMT_5_6_5 = 4, 80 FMT_6_5_5 = 5, 81 FMT_8_8_8_8 = 6, 82 FMT_2_10_10_10 = 7, 83 FMT_8_A = 8, 84 FMT_8_B = 9, 85 FMT_8_8 = 10, 86 FMT_Cr_Y1_Cb_Y0 = 11, 87 FMT_Y1_Cr_Y0_Cb = 12, 88 FMT_5_5_5_1 = 13, 89 FMT_8_8_8_8_A = 14, 90 FMT_4_4_4_4 = 15, 91 FMT_8_8_8 = 16, 92 FMT_DXT1 = 18, 93 FMT_DXT2_3 = 19, 94 FMT_DXT4_5 = 20, 95 FMT_10_10_10_2 = 21, 96 FMT_24_8 = 22, 97 FMT_16 = 24, 98 FMT_16_16 = 25, 99 FMT_16_16_16_16 = 26, 100 FMT_16_EXPAND = 27, 101 FMT_16_16_EXPAND = 28, 102 FMT_16_16_16_16_EXPAND = 29, 103 FMT_16_FLOAT = 30, 104 FMT_16_16_FLOAT = 31, 105 FMT_16_16_16_16_FLOAT = 32, 106 FMT_32 = 33, 107 FMT_32_32 = 34, 108 FMT_32_32_32_32 = 35, 109 FMT_32_FLOAT = 36, 110 FMT_32_32_FLOAT = 37, 111 FMT_32_32_32_32_FLOAT = 38, 112 FMT_ATI_TC_RGB = 39, 113 FMT_ATI_TC_RGBA = 40, 114 FMT_ATI_TC_555_565_RGB = 41, 115 FMT_ATI_TC_555_565_RGBA = 42, 116 FMT_ATI_TC_RGBA_INTERP = 43, 117 FMT_ATI_TC_555_565_RGBA_INTERP = 44, 118 FMT_ETC1_RGBA_INTERP = 46, 119 FMT_ETC1_RGB = 47, 120 FMT_ETC1_RGBA = 48, 121 FMT_DXN = 49, 122 FMT_2_3_3 = 51, 123 FMT_2_10_10_10_AS_16_16_16_16 = 54, 124 FMT_10_10_10_2_AS_16_16_16_16 = 55, 125 FMT_32_32_32_FLOAT = 57, 126 FMT_DXT3A = 58, 127 FMT_DXT5A = 59, 128 FMT_CTX1 = 60, 129 }; 130 131 enum a2xx_sq_ps_vtx_mode { 132 POSITION_1_VECTOR = 0, 133 POSITION_2_VECTORS_UNUSED = 1, 134 POSITION_2_VECTORS_SPRITE = 2, 135 POSITION_2_VECTORS_EDGE = 3, 136 POSITION_2_VECTORS_KILL = 4, 137 POSITION_2_VECTORS_SPRITE_KILL = 5, 138 POSITION_2_VECTORS_EDGE_KILL = 6, 139 MULTIPASS = 7, 140 }; 141 142 enum a2xx_sq_sample_cntl { 143 CENTROIDS_ONLY = 0, 144 CENTERS_ONLY = 1, 145 CENTROIDS_AND_CENTERS = 2, 146 }; 147 148 enum a2xx_dx_clip_space { 149 DXCLIP_OPENGL = 0, 150 DXCLIP_DIRECTX = 1, 151 }; 152 153 enum a2xx_pa_su_sc_polymode { 154 POLY_DISABLED = 0, 155 POLY_DUALMODE = 1, 156 }; 157 158 enum a2xx_rb_edram_mode { 159 EDRAM_NOP = 0, 160 COLOR_DEPTH = 4, 161 DEPTH_ONLY = 5, 162 EDRAM_COPY = 6, 163 }; 164 165 enum a2xx_pa_sc_pattern_bit_order { 166 LITTLE = 0, 167 BIG = 1, 168 }; 169 170 enum a2xx_pa_sc_auto_reset_cntl { 171 NEVER = 0, 172 EACH_PRIMITIVE = 1, 173 EACH_PACKET = 2, 174 }; 175 176 enum a2xx_pa_pixcenter { 177 PIXCENTER_D3D = 0, 178 PIXCENTER_OGL = 1, 179 }; 180 181 enum a2xx_pa_roundmode { 182 TRUNCATE = 0, 183 ROUND = 1, 184 ROUNDTOEVEN = 2, 185 ROUNDTOODD = 3, 186 }; 187 188 enum a2xx_pa_quantmode { 189 ONE_SIXTEENTH = 0, 190 ONE_EIGTH = 1, 191 ONE_QUARTER = 2, 192 ONE_HALF = 3, 193 ONE = 4, 194 }; 195 196 enum a2xx_rb_copy_sample_select { 197 SAMPLE_0 = 0, 198 SAMPLE_1 = 1, 199 SAMPLE_2 = 2, 200 SAMPLE_3 = 3, 201 SAMPLE_01 = 4, 202 SAMPLE_23 = 5, 203 SAMPLE_0123 = 6, 204 }; 205 206 enum a2xx_rb_blend_opcode { 207 BLEND2_DST_PLUS_SRC = 0, 208 BLEND2_SRC_MINUS_DST = 1, 209 BLEND2_MIN_DST_SRC = 2, 210 BLEND2_MAX_DST_SRC = 3, 211 BLEND2_DST_MINUS_SRC = 4, 212 BLEND2_DST_PLUS_SRC_BIAS = 5, 213 }; 214 215 enum a2xx_su_perfcnt_select { 216 PERF_PAPC_PASX_REQ = 0, 217 PERF_PAPC_PASX_FIRST_VECTOR = 2, 218 PERF_PAPC_PASX_SECOND_VECTOR = 3, 219 PERF_PAPC_PASX_FIRST_DEAD = 4, 220 PERF_PAPC_PASX_SECOND_DEAD = 5, 221 PERF_PAPC_PASX_VTX_KILL_DISCARD = 6, 222 PERF_PAPC_PASX_VTX_NAN_DISCARD = 7, 223 PERF_PAPC_PA_INPUT_PRIM = 8, 224 PERF_PAPC_PA_INPUT_NULL_PRIM = 9, 225 PERF_PAPC_PA_INPUT_EVENT_FLAG = 10, 226 PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11, 227 PERF_PAPC_PA_INPUT_END_OF_PACKET = 12, 228 PERF_PAPC_CLPR_CULL_PRIM = 13, 229 PERF_PAPC_CLPR_VV_CULL_PRIM = 15, 230 PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17, 231 PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18, 232 PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19, 233 PERF_PAPC_CLPR_VV_CLIP_PRIM = 21, 234 PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23, 235 PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24, 236 PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25, 237 PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26, 238 PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27, 239 PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28, 240 PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29, 241 PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30, 242 PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31, 243 PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32, 244 PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33, 245 PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34, 246 PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35, 247 PERF_PAPC_CLSM_NULL_PRIM = 36, 248 PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37, 249 PERF_PAPC_CLSM_CLIP_PRIM = 38, 250 PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39, 251 PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40, 252 PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41, 253 PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42, 254 PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43, 255 PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44, 256 PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45, 257 PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46, 258 PERF_PAPC_SU_INPUT_PRIM = 47, 259 PERF_PAPC_SU_INPUT_CLIP_PRIM = 48, 260 PERF_PAPC_SU_INPUT_NULL_PRIM = 49, 261 PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50, 262 PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51, 263 PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52, 264 PERF_PAPC_SU_POLYMODE_FACE_CULL = 53, 265 PERF_PAPC_SU_POLYMODE_BACK_CULL = 54, 266 PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55, 267 PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56, 268 PERF_PAPC_SU_OUTPUT_PRIM = 57, 269 PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58, 270 PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59, 271 PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60, 272 PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61, 273 PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62, 274 PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63, 275 PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64, 276 PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65, 277 PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66, 278 PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67, 279 PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68, 280 PERF_PAPC_PASX_REQ_IDLE = 69, 281 PERF_PAPC_PASX_REQ_BUSY = 70, 282 PERF_PAPC_PASX_REQ_STALLED = 71, 283 PERF_PAPC_PASX_REC_IDLE = 72, 284 PERF_PAPC_PASX_REC_BUSY = 73, 285 PERF_PAPC_PASX_REC_STARVED_SX = 74, 286 PERF_PAPC_PASX_REC_STALLED = 75, 287 PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76, 288 PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77, 289 PERF_PAPC_CCGSM_IDLE = 78, 290 PERF_PAPC_CCGSM_BUSY = 79, 291 PERF_PAPC_CCGSM_STALLED = 80, 292 PERF_PAPC_CLPRIM_IDLE = 81, 293 PERF_PAPC_CLPRIM_BUSY = 82, 294 PERF_PAPC_CLPRIM_STALLED = 83, 295 PERF_PAPC_CLPRIM_STARVED_CCGSM = 84, 296 PERF_PAPC_CLIPSM_IDLE = 85, 297 PERF_PAPC_CLIPSM_BUSY = 86, 298 PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87, 299 PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88, 300 PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89, 301 PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90, 302 PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91, 303 PERF_PAPC_CLIPGA_IDLE = 92, 304 PERF_PAPC_CLIPGA_BUSY = 93, 305 PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94, 306 PERF_PAPC_CLIPGA_STALLED = 95, 307 PERF_PAPC_CLIP_IDLE = 96, 308 PERF_PAPC_CLIP_BUSY = 97, 309 PERF_PAPC_SU_IDLE = 98, 310 PERF_PAPC_SU_BUSY = 99, 311 PERF_PAPC_SU_STARVED_CLIP = 100, 312 PERF_PAPC_SU_STALLED_SC = 101, 313 PERF_PAPC_SU_FACENESS_CULL = 102, 314 }; 315 316 enum a2xx_sc_perfcnt_select { 317 SC_SR_WINDOW_VALID = 0, 318 SC_CW_WINDOW_VALID = 1, 319 SC_QM_WINDOW_VALID = 2, 320 SC_FW_WINDOW_VALID = 3, 321 SC_EZ_WINDOW_VALID = 4, 322 SC_IT_WINDOW_VALID = 5, 323 SC_STARVED_BY_PA = 6, 324 SC_STALLED_BY_RB_TILE = 7, 325 SC_STALLED_BY_RB_SAMP = 8, 326 SC_STARVED_BY_RB_EZ = 9, 327 SC_STALLED_BY_SAMPLE_FF = 10, 328 SC_STALLED_BY_SQ = 11, 329 SC_STALLED_BY_SP = 12, 330 SC_TOTAL_NO_PRIMS = 13, 331 SC_NON_EMPTY_PRIMS = 14, 332 SC_NO_TILES_PASSING_QM = 15, 333 SC_NO_PIXELS_PRE_EZ = 16, 334 SC_NO_PIXELS_POST_EZ = 17, 335 }; 336 337 enum a2xx_vgt_perfcount_select { 338 VGT_SQ_EVENT_WINDOW_ACTIVE = 0, 339 VGT_SQ_SEND = 1, 340 VGT_SQ_STALLED = 2, 341 VGT_SQ_STARVED_BUSY = 3, 342 VGT_SQ_STARVED_IDLE = 4, 343 VGT_SQ_STATIC = 5, 344 VGT_PA_EVENT_WINDOW_ACTIVE = 6, 345 VGT_PA_CLIP_V_SEND = 7, 346 VGT_PA_CLIP_V_STALLED = 8, 347 VGT_PA_CLIP_V_STARVED_BUSY = 9, 348 VGT_PA_CLIP_V_STARVED_IDLE = 10, 349 VGT_PA_CLIP_V_STATIC = 11, 350 VGT_PA_CLIP_P_SEND = 12, 351 VGT_PA_CLIP_P_STALLED = 13, 352 VGT_PA_CLIP_P_STARVED_BUSY = 14, 353 VGT_PA_CLIP_P_STARVED_IDLE = 15, 354 VGT_PA_CLIP_P_STATIC = 16, 355 VGT_PA_CLIP_S_SEND = 17, 356 VGT_PA_CLIP_S_STALLED = 18, 357 VGT_PA_CLIP_S_STARVED_BUSY = 19, 358 VGT_PA_CLIP_S_STARVED_IDLE = 20, 359 VGT_PA_CLIP_S_STATIC = 21, 360 RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22, 361 RBIU_IMMED_DATA_FIFO_STARVED = 23, 362 RBIU_IMMED_DATA_FIFO_STALLED = 24, 363 RBIU_DMA_REQUEST_FIFO_STARVED = 25, 364 RBIU_DMA_REQUEST_FIFO_STALLED = 26, 365 RBIU_DRAW_INITIATOR_FIFO_STARVED = 27, 366 RBIU_DRAW_INITIATOR_FIFO_STALLED = 28, 367 BIN_PRIM_NEAR_CULL = 29, 368 BIN_PRIM_ZERO_CULL = 30, 369 BIN_PRIM_FAR_CULL = 31, 370 BIN_PRIM_BIN_CULL = 32, 371 BIN_PRIM_FACE_CULL = 33, 372 SPARE34 = 34, 373 SPARE35 = 35, 374 SPARE36 = 36, 375 SPARE37 = 37, 376 SPARE38 = 38, 377 SPARE39 = 39, 378 TE_SU_IN_VALID = 40, 379 TE_SU_IN_READ = 41, 380 TE_SU_IN_PRIM = 42, 381 TE_SU_IN_EOP = 43, 382 TE_SU_IN_NULL_PRIM = 44, 383 TE_WK_IN_VALID = 45, 384 TE_WK_IN_READ = 46, 385 TE_OUT_PRIM_VALID = 47, 386 TE_OUT_PRIM_READ = 48, 387 }; 388 389 enum a2xx_tcr_perfcount_select { 390 DGMMPD_IPMUX0_STALL = 0, 391 DGMMPD_IPMUX_ALL_STALL = 4, 392 OPMUX0_L2_WRITES = 5, 393 }; 394 395 enum a2xx_tp_perfcount_select { 396 POINT_QUADS = 0, 397 BILIN_QUADS = 1, 398 ANISO_QUADS = 2, 399 MIP_QUADS = 3, 400 VOL_QUADS = 4, 401 MIP_VOL_QUADS = 5, 402 MIP_ANISO_QUADS = 6, 403 VOL_ANISO_QUADS = 7, 404 ANISO_2_1_QUADS = 8, 405 ANISO_4_1_QUADS = 9, 406 ANISO_6_1_QUADS = 10, 407 ANISO_8_1_QUADS = 11, 408 ANISO_10_1_QUADS = 12, 409 ANISO_12_1_QUADS = 13, 410 ANISO_14_1_QUADS = 14, 411 ANISO_16_1_QUADS = 15, 412 MIP_VOL_ANISO_QUADS = 16, 413 ALIGN_2_QUADS = 17, 414 ALIGN_4_QUADS = 18, 415 PIX_0_QUAD = 19, 416 PIX_1_QUAD = 20, 417 PIX_2_QUAD = 21, 418 PIX_3_QUAD = 22, 419 PIX_4_QUAD = 23, 420 TP_MIPMAP_LOD0 = 24, 421 TP_MIPMAP_LOD1 = 25, 422 TP_MIPMAP_LOD2 = 26, 423 TP_MIPMAP_LOD3 = 27, 424 TP_MIPMAP_LOD4 = 28, 425 TP_MIPMAP_LOD5 = 29, 426 TP_MIPMAP_LOD6 = 30, 427 TP_MIPMAP_LOD7 = 31, 428 TP_MIPMAP_LOD8 = 32, 429 TP_MIPMAP_LOD9 = 33, 430 TP_MIPMAP_LOD10 = 34, 431 TP_MIPMAP_LOD11 = 35, 432 TP_MIPMAP_LOD12 = 36, 433 TP_MIPMAP_LOD13 = 37, 434 TP_MIPMAP_LOD14 = 38, 435 }; 436 437 enum a2xx_tcm_perfcount_select { 438 QUAD0_RD_LAT_FIFO_EMPTY = 0, 439 QUAD0_RD_LAT_FIFO_4TH_FULL = 3, 440 QUAD0_RD_LAT_FIFO_HALF_FULL = 4, 441 QUAD0_RD_LAT_FIFO_FULL = 5, 442 QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6, 443 READ_STARVED_QUAD0 = 28, 444 READ_STARVED = 32, 445 READ_STALLED_QUAD0 = 33, 446 READ_STALLED = 37, 447 VALID_READ_QUAD0 = 38, 448 TC_TP_STARVED_QUAD0 = 42, 449 TC_TP_STARVED = 46, 450 }; 451 452 enum a2xx_tcf_perfcount_select { 453 VALID_CYCLES = 0, 454 SINGLE_PHASES = 1, 455 ANISO_PHASES = 2, 456 MIP_PHASES = 3, 457 VOL_PHASES = 4, 458 MIP_VOL_PHASES = 5, 459 MIP_ANISO_PHASES = 6, 460 VOL_ANISO_PHASES = 7, 461 ANISO_2_1_PHASES = 8, 462 ANISO_4_1_PHASES = 9, 463 ANISO_6_1_PHASES = 10, 464 ANISO_8_1_PHASES = 11, 465 ANISO_10_1_PHASES = 12, 466 ANISO_12_1_PHASES = 13, 467 ANISO_14_1_PHASES = 14, 468 ANISO_16_1_PHASES = 15, 469 MIP_VOL_ANISO_PHASES = 16, 470 ALIGN_2_PHASES = 17, 471 ALIGN_4_PHASES = 18, 472 TPC_BUSY = 19, 473 TPC_STALLED = 20, 474 TPC_STARVED = 21, 475 TPC_WORKING = 22, 476 TPC_WALKER_BUSY = 23, 477 TPC_WALKER_STALLED = 24, 478 TPC_WALKER_WORKING = 25, 479 TPC_ALIGNER_BUSY = 26, 480 TPC_ALIGNER_STALLED = 27, 481 TPC_ALIGNER_STALLED_BY_BLEND = 28, 482 TPC_ALIGNER_STALLED_BY_CACHE = 29, 483 TPC_ALIGNER_WORKING = 30, 484 TPC_BLEND_BUSY = 31, 485 TPC_BLEND_SYNC = 32, 486 TPC_BLEND_STARVED = 33, 487 TPC_BLEND_WORKING = 34, 488 OPCODE_0x00 = 35, 489 OPCODE_0x01 = 36, 490 OPCODE_0x04 = 37, 491 OPCODE_0x10 = 38, 492 OPCODE_0x11 = 39, 493 OPCODE_0x12 = 40, 494 OPCODE_0x13 = 41, 495 OPCODE_0x18 = 42, 496 OPCODE_0x19 = 43, 497 OPCODE_0x1A = 44, 498 OPCODE_OTHER = 45, 499 IN_FIFO_0_EMPTY = 56, 500 IN_FIFO_0_LT_HALF_FULL = 57, 501 IN_FIFO_0_HALF_FULL = 58, 502 IN_FIFO_0_FULL = 59, 503 IN_FIFO_TPC_EMPTY = 72, 504 IN_FIFO_TPC_LT_HALF_FULL = 73, 505 IN_FIFO_TPC_HALF_FULL = 74, 506 IN_FIFO_TPC_FULL = 75, 507 TPC_TC_XFC = 76, 508 TPC_TC_STATE = 77, 509 TC_STALL = 78, 510 QUAD0_TAPS = 79, 511 QUADS = 83, 512 TCA_SYNC_STALL = 84, 513 TAG_STALL = 85, 514 TCB_SYNC_STALL = 88, 515 TCA_VALID = 89, 516 PROBES_VALID = 90, 517 MISS_STALL = 91, 518 FETCH_FIFO_STALL = 92, 519 TCO_STALL = 93, 520 ANY_STALL = 94, 521 TAG_MISSES = 95, 522 TAG_HITS = 96, 523 SUB_TAG_MISSES = 97, 524 SET0_INVALIDATES = 98, 525 SET1_INVALIDATES = 99, 526 SET2_INVALIDATES = 100, 527 SET3_INVALIDATES = 101, 528 SET0_TAG_MISSES = 102, 529 SET1_TAG_MISSES = 103, 530 SET2_TAG_MISSES = 104, 531 SET3_TAG_MISSES = 105, 532 SET0_TAG_HITS = 106, 533 SET1_TAG_HITS = 107, 534 SET2_TAG_HITS = 108, 535 SET3_TAG_HITS = 109, 536 SET0_SUB_TAG_MISSES = 110, 537 SET1_SUB_TAG_MISSES = 111, 538 SET2_SUB_TAG_MISSES = 112, 539 SET3_SUB_TAG_MISSES = 113, 540 SET0_EVICT1 = 114, 541 SET0_EVICT2 = 115, 542 SET0_EVICT3 = 116, 543 SET0_EVICT4 = 117, 544 SET0_EVICT5 = 118, 545 SET0_EVICT6 = 119, 546 SET0_EVICT7 = 120, 547 SET0_EVICT8 = 121, 548 SET1_EVICT1 = 130, 549 SET1_EVICT2 = 131, 550 SET1_EVICT3 = 132, 551 SET1_EVICT4 = 133, 552 SET1_EVICT5 = 134, 553 SET1_EVICT6 = 135, 554 SET1_EVICT7 = 136, 555 SET1_EVICT8 = 137, 556 SET2_EVICT1 = 146, 557 SET2_EVICT2 = 147, 558 SET2_EVICT3 = 148, 559 SET2_EVICT4 = 149, 560 SET2_EVICT5 = 150, 561 SET2_EVICT6 = 151, 562 SET2_EVICT7 = 152, 563 SET2_EVICT8 = 153, 564 SET3_EVICT1 = 162, 565 SET3_EVICT2 = 163, 566 SET3_EVICT3 = 164, 567 SET3_EVICT4 = 165, 568 SET3_EVICT5 = 166, 569 SET3_EVICT6 = 167, 570 SET3_EVICT7 = 168, 571 SET3_EVICT8 = 169, 572 FF_EMPTY = 178, 573 FF_LT_HALF_FULL = 179, 574 FF_HALF_FULL = 180, 575 FF_FULL = 181, 576 FF_XFC = 182, 577 FF_STALLED = 183, 578 FG_MASKS = 184, 579 FG_LEFT_MASKS = 185, 580 FG_LEFT_MASK_STALLED = 186, 581 FG_LEFT_NOT_DONE_STALL = 187, 582 FG_LEFT_FG_STALL = 188, 583 FG_LEFT_SECTORS = 189, 584 FG0_REQUESTS = 195, 585 FG0_STALLED = 196, 586 MEM_REQ512 = 199, 587 MEM_REQ_SENT = 200, 588 MEM_LOCAL_READ_REQ = 202, 589 TC0_MH_STALLED = 203, 590 }; 591 592 enum a2xx_sq_perfcnt_select { 593 SQ_PIXEL_VECTORS_SUB = 0, 594 SQ_VERTEX_VECTORS_SUB = 1, 595 SQ_ALU0_ACTIVE_VTX_SIMD0 = 2, 596 SQ_ALU1_ACTIVE_VTX_SIMD0 = 3, 597 SQ_ALU0_ACTIVE_PIX_SIMD0 = 4, 598 SQ_ALU1_ACTIVE_PIX_SIMD0 = 5, 599 SQ_ALU0_ACTIVE_VTX_SIMD1 = 6, 600 SQ_ALU1_ACTIVE_VTX_SIMD1 = 7, 601 SQ_ALU0_ACTIVE_PIX_SIMD1 = 8, 602 SQ_ALU1_ACTIVE_PIX_SIMD1 = 9, 603 SQ_EXPORT_CYCLES = 10, 604 SQ_ALU_CST_WRITTEN = 11, 605 SQ_TEX_CST_WRITTEN = 12, 606 SQ_ALU_CST_STALL = 13, 607 SQ_ALU_TEX_STALL = 14, 608 SQ_INST_WRITTEN = 15, 609 SQ_BOOLEAN_WRITTEN = 16, 610 SQ_LOOPS_WRITTEN = 17, 611 SQ_PIXEL_SWAP_IN = 18, 612 SQ_PIXEL_SWAP_OUT = 19, 613 SQ_VERTEX_SWAP_IN = 20, 614 SQ_VERTEX_SWAP_OUT = 21, 615 SQ_ALU_VTX_INST_ISSUED = 22, 616 SQ_TEX_VTX_INST_ISSUED = 23, 617 SQ_VC_VTX_INST_ISSUED = 24, 618 SQ_CF_VTX_INST_ISSUED = 25, 619 SQ_ALU_PIX_INST_ISSUED = 26, 620 SQ_TEX_PIX_INST_ISSUED = 27, 621 SQ_VC_PIX_INST_ISSUED = 28, 622 SQ_CF_PIX_INST_ISSUED = 29, 623 SQ_ALU0_FIFO_EMPTY_SIMD0 = 30, 624 SQ_ALU1_FIFO_EMPTY_SIMD0 = 31, 625 SQ_ALU0_FIFO_EMPTY_SIMD1 = 32, 626 SQ_ALU1_FIFO_EMPTY_SIMD1 = 33, 627 SQ_ALU_NOPS = 34, 628 SQ_PRED_SKIP = 35, 629 SQ_SYNC_ALU_STALL_SIMD0_VTX = 36, 630 SQ_SYNC_ALU_STALL_SIMD1_VTX = 37, 631 SQ_SYNC_TEX_STALL_VTX = 38, 632 SQ_SYNC_VC_STALL_VTX = 39, 633 SQ_CONSTANTS_USED_SIMD0 = 40, 634 SQ_CONSTANTS_SENT_SP_SIMD0 = 41, 635 SQ_GPR_STALL_VTX = 42, 636 SQ_GPR_STALL_PIX = 43, 637 SQ_VTX_RS_STALL = 44, 638 SQ_PIX_RS_STALL = 45, 639 SQ_SX_PC_FULL = 46, 640 SQ_SX_EXP_BUFF_FULL = 47, 641 SQ_SX_POS_BUFF_FULL = 48, 642 SQ_INTERP_QUADS = 49, 643 SQ_INTERP_ACTIVE = 50, 644 SQ_IN_PIXEL_STALL = 51, 645 SQ_IN_VTX_STALL = 52, 646 SQ_VTX_CNT = 53, 647 SQ_VTX_VECTOR2 = 54, 648 SQ_VTX_VECTOR3 = 55, 649 SQ_VTX_VECTOR4 = 56, 650 SQ_PIXEL_VECTOR1 = 57, 651 SQ_PIXEL_VECTOR23 = 58, 652 SQ_PIXEL_VECTOR4 = 59, 653 SQ_CONSTANTS_USED_SIMD1 = 60, 654 SQ_CONSTANTS_SENT_SP_SIMD1 = 61, 655 SQ_SX_MEM_EXP_FULL = 62, 656 SQ_ALU0_ACTIVE_VTX_SIMD2 = 63, 657 SQ_ALU1_ACTIVE_VTX_SIMD2 = 64, 658 SQ_ALU0_ACTIVE_PIX_SIMD2 = 65, 659 SQ_ALU1_ACTIVE_PIX_SIMD2 = 66, 660 SQ_ALU0_ACTIVE_VTX_SIMD3 = 67, 661 SQ_PERFCOUNT_VTX_QUAL_TP_DONE = 68, 662 SQ_ALU0_ACTIVE_PIX_SIMD3 = 69, 663 SQ_PERFCOUNT_PIX_QUAL_TP_DONE = 70, 664 SQ_ALU0_FIFO_EMPTY_SIMD2 = 71, 665 SQ_ALU1_FIFO_EMPTY_SIMD2 = 72, 666 SQ_ALU0_FIFO_EMPTY_SIMD3 = 73, 667 SQ_ALU1_FIFO_EMPTY_SIMD3 = 74, 668 SQ_SYNC_ALU_STALL_SIMD2_VTX = 75, 669 SQ_PERFCOUNT_VTX_POP_THREAD = 76, 670 SQ_SYNC_ALU_STALL_SIMD0_PIX = 77, 671 SQ_SYNC_ALU_STALL_SIMD1_PIX = 78, 672 SQ_SYNC_ALU_STALL_SIMD2_PIX = 79, 673 SQ_PERFCOUNT_PIX_POP_THREAD = 80, 674 SQ_SYNC_TEX_STALL_PIX = 81, 675 SQ_SYNC_VC_STALL_PIX = 82, 676 SQ_CONSTANTS_USED_SIMD2 = 83, 677 SQ_CONSTANTS_SENT_SP_SIMD2 = 84, 678 SQ_PERFCOUNT_VTX_DEALLOC_ACK = 85, 679 SQ_PERFCOUNT_PIX_DEALLOC_ACK = 86, 680 SQ_ALU0_FIFO_FULL_SIMD0 = 87, 681 SQ_ALU1_FIFO_FULL_SIMD0 = 88, 682 SQ_ALU0_FIFO_FULL_SIMD1 = 89, 683 SQ_ALU1_FIFO_FULL_SIMD1 = 90, 684 SQ_ALU0_FIFO_FULL_SIMD2 = 91, 685 SQ_ALU1_FIFO_FULL_SIMD2 = 92, 686 SQ_ALU0_FIFO_FULL_SIMD3 = 93, 687 SQ_ALU1_FIFO_FULL_SIMD3 = 94, 688 VC_PERF_STATIC = 95, 689 VC_PERF_STALLED = 96, 690 VC_PERF_STARVED = 97, 691 VC_PERF_SEND = 98, 692 VC_PERF_ACTUAL_STARVED = 99, 693 PIXEL_THREAD_0_ACTIVE = 100, 694 VERTEX_THREAD_0_ACTIVE = 101, 695 PIXEL_THREAD_0_NUMBER = 102, 696 VERTEX_THREAD_0_NUMBER = 103, 697 VERTEX_EVENT_NUMBER = 104, 698 PIXEL_EVENT_NUMBER = 105, 699 PTRBUFF_EF_PUSH = 106, 700 PTRBUFF_EF_POP_EVENT = 107, 701 PTRBUFF_EF_POP_NEW_VTX = 108, 702 PTRBUFF_EF_POP_DEALLOC = 109, 703 PTRBUFF_EF_POP_PVECTOR = 110, 704 PTRBUFF_EF_POP_PVECTOR_X = 111, 705 PTRBUFF_EF_POP_PVECTOR_VNZ = 112, 706 PTRBUFF_PB_DEALLOC = 113, 707 PTRBUFF_PI_STATE_PPB_POP = 114, 708 PTRBUFF_PI_RTR = 115, 709 PTRBUFF_PI_READ_EN = 116, 710 PTRBUFF_PI_BUFF_SWAP = 117, 711 PTRBUFF_SQ_FREE_BUFF = 118, 712 PTRBUFF_SQ_DEC = 119, 713 PTRBUFF_SC_VALID_CNTL_EVENT = 120, 714 PTRBUFF_SC_VALID_IJ_XFER = 121, 715 PTRBUFF_SC_NEW_VECTOR_1_Q = 122, 716 PTRBUFF_QUAL_NEW_VECTOR = 123, 717 PTRBUFF_QUAL_EVENT = 124, 718 PTRBUFF_END_BUFFER = 125, 719 PTRBUFF_FILL_QUAD = 126, 720 VERTS_WRITTEN_SPI = 127, 721 TP_FETCH_INSTR_EXEC = 128, 722 TP_FETCH_INSTR_REQ = 129, 723 TP_DATA_RETURN = 130, 724 SPI_WRITE_CYCLES_SP = 131, 725 SPI_WRITES_SP = 132, 726 SP_ALU_INSTR_EXEC = 133, 727 SP_CONST_ADDR_TO_SQ = 134, 728 SP_PRED_KILLS_TO_SQ = 135, 729 SP_EXPORT_CYCLES_TO_SX = 136, 730 SP_EXPORTS_TO_SX = 137, 731 SQ_CYCLES_ELAPSED = 138, 732 SQ_TCFS_OPT_ALLOC_EXEC = 139, 733 SQ_TCFS_NO_OPT_ALLOC = 140, 734 SQ_ALU0_NO_OPT_ALLOC = 141, 735 SQ_ALU1_NO_OPT_ALLOC = 142, 736 SQ_TCFS_ARB_XFC_CNT = 143, 737 SQ_ALU0_ARB_XFC_CNT = 144, 738 SQ_ALU1_ARB_XFC_CNT = 145, 739 SQ_TCFS_CFS_UPDATE_CNT = 146, 740 SQ_ALU0_CFS_UPDATE_CNT = 147, 741 SQ_ALU1_CFS_UPDATE_CNT = 148, 742 SQ_VTX_PUSH_THREAD_CNT = 149, 743 SQ_VTX_POP_THREAD_CNT = 150, 744 SQ_PIX_PUSH_THREAD_CNT = 151, 745 SQ_PIX_POP_THREAD_CNT = 152, 746 SQ_PIX_TOTAL = 153, 747 SQ_PIX_KILLED = 154, 748 }; 749 750 enum a2xx_sx_perfcnt_select { 751 SX_EXPORT_VECTORS = 0, 752 SX_DUMMY_QUADS = 1, 753 SX_ALPHA_FAIL = 2, 754 SX_RB_QUAD_BUSY = 3, 755 SX_RB_COLOR_BUSY = 4, 756 SX_RB_QUAD_STALL = 5, 757 SX_RB_COLOR_STALL = 6, 758 }; 759 760 enum a2xx_rbbm_perfcount1_sel { 761 RBBM1_COUNT = 0, 762 RBBM1_NRT_BUSY = 1, 763 RBBM1_RB_BUSY = 2, 764 RBBM1_SQ_CNTX0_BUSY = 3, 765 RBBM1_SQ_CNTX17_BUSY = 4, 766 RBBM1_VGT_BUSY = 5, 767 RBBM1_VGT_NODMA_BUSY = 6, 768 RBBM1_PA_BUSY = 7, 769 RBBM1_SC_CNTX_BUSY = 8, 770 RBBM1_TPC_BUSY = 9, 771 RBBM1_TC_BUSY = 10, 772 RBBM1_SX_BUSY = 11, 773 RBBM1_CP_COHER_BUSY = 12, 774 RBBM1_CP_NRT_BUSY = 13, 775 RBBM1_GFX_IDLE_STALL = 14, 776 RBBM1_INTERRUPT = 15, 777 }; 778 779 enum a2xx_cp_perfcount_sel { 780 ALWAYS_COUNT = 0, 781 TRANS_FIFO_FULL = 1, 782 TRANS_FIFO_AF = 2, 783 RCIU_PFPTRANS_WAIT = 3, 784 RCIU_NRTTRANS_WAIT = 6, 785 CSF_NRT_READ_WAIT = 8, 786 CSF_I1_FIFO_FULL = 9, 787 CSF_I2_FIFO_FULL = 10, 788 CSF_ST_FIFO_FULL = 11, 789 CSF_RING_ROQ_FULL = 13, 790 CSF_I1_ROQ_FULL = 14, 791 CSF_I2_ROQ_FULL = 15, 792 CSF_ST_ROQ_FULL = 16, 793 MIU_TAG_MEM_FULL = 18, 794 MIU_WRITECLEAN = 19, 795 MIU_NRT_WRITE_STALLED = 22, 796 MIU_NRT_READ_STALLED = 23, 797 ME_WRITE_CONFIRM_FIFO_FULL = 24, 798 ME_VS_DEALLOC_FIFO_FULL = 25, 799 ME_PS_DEALLOC_FIFO_FULL = 26, 800 ME_REGS_VS_EVENT_FIFO_FULL = 27, 801 ME_REGS_PS_EVENT_FIFO_FULL = 28, 802 ME_REGS_CF_EVENT_FIFO_FULL = 29, 803 ME_MICRO_RB_STARVED = 30, 804 ME_MICRO_I1_STARVED = 31, 805 ME_MICRO_I2_STARVED = 32, 806 ME_MICRO_ST_STARVED = 33, 807 RCIU_RBBM_DWORD_SENT = 40, 808 ME_BUSY_CLOCKS = 41, 809 ME_WAIT_CONTEXT_AVAIL = 42, 810 PFP_TYPE0_PACKET = 43, 811 PFP_TYPE3_PACKET = 44, 812 CSF_RB_WPTR_NEQ_RPTR = 45, 813 CSF_I1_SIZE_NEQ_ZERO = 46, 814 CSF_I2_SIZE_NEQ_ZERO = 47, 815 CSF_RBI1I2_FETCHING = 48, 816 }; 817 818 enum a2xx_rb_perfcnt_select { 819 RBPERF_CNTX_BUSY = 0, 820 RBPERF_CNTX_BUSY_MAX = 1, 821 RBPERF_SX_QUAD_STARVED = 2, 822 RBPERF_SX_QUAD_STARVED_MAX = 3, 823 RBPERF_GA_GC_CH0_SYS_REQ = 4, 824 RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5, 825 RBPERF_GA_GC_CH1_SYS_REQ = 6, 826 RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7, 827 RBPERF_MH_STARVED = 8, 828 RBPERF_MH_STARVED_MAX = 9, 829 RBPERF_AZ_BC_COLOR_BUSY = 10, 830 RBPERF_AZ_BC_COLOR_BUSY_MAX = 11, 831 RBPERF_AZ_BC_Z_BUSY = 12, 832 RBPERF_AZ_BC_Z_BUSY_MAX = 13, 833 RBPERF_RB_SC_TILE_RTR_N = 14, 834 RBPERF_RB_SC_TILE_RTR_N_MAX = 15, 835 RBPERF_RB_SC_SAMP_RTR_N = 16, 836 RBPERF_RB_SC_SAMP_RTR_N_MAX = 17, 837 RBPERF_RB_SX_QUAD_RTR_N = 18, 838 RBPERF_RB_SX_QUAD_RTR_N_MAX = 19, 839 RBPERF_RB_SX_COLOR_RTR_N = 20, 840 RBPERF_RB_SX_COLOR_RTR_N_MAX = 21, 841 RBPERF_RB_SC_SAMP_LZ_BUSY = 22, 842 RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23, 843 RBPERF_ZXP_STALL = 24, 844 RBPERF_ZXP_STALL_MAX = 25, 845 RBPERF_EVENT_PENDING = 26, 846 RBPERF_EVENT_PENDING_MAX = 27, 847 RBPERF_RB_MH_VALID = 28, 848 RBPERF_RB_MH_VALID_MAX = 29, 849 RBPERF_SX_RB_QUAD_SEND = 30, 850 RBPERF_SX_RB_COLOR_SEND = 31, 851 RBPERF_SC_RB_TILE_SEND = 32, 852 RBPERF_SC_RB_SAMPLE_SEND = 33, 853 RBPERF_SX_RB_MEM_EXPORT = 34, 854 RBPERF_SX_RB_QUAD_EVENT = 35, 855 RBPERF_SC_RB_TILE_EVENT_FILTERED = 36, 856 RBPERF_SC_RB_TILE_EVENT_ALL = 37, 857 RBPERF_RB_SC_EZ_SEND = 38, 858 RBPERF_RB_SX_INDEX_SEND = 39, 859 RBPERF_GMEM_INTFO_RD = 40, 860 RBPERF_GMEM_INTF1_RD = 41, 861 RBPERF_GMEM_INTFO_WR = 42, 862 RBPERF_GMEM_INTF1_WR = 43, 863 RBPERF_RB_CP_CONTEXT_DONE = 44, 864 RBPERF_RB_CP_CACHE_FLUSH = 45, 865 RBPERF_ZPASS_DONE = 46, 866 RBPERF_ZCMD_VALID = 47, 867 RBPERF_CCMD_VALID = 48, 868 RBPERF_ACCUM_GRANT = 49, 869 RBPERF_ACCUM_C0_GRANT = 50, 870 RBPERF_ACCUM_C1_GRANT = 51, 871 RBPERF_ACCUM_FULL_BE_WR = 52, 872 RBPERF_ACCUM_REQUEST_NO_GRANT = 53, 873 RBPERF_ACCUM_TIMEOUT_PULSE = 54, 874 RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55, 875 RBPERF_ACCUM_CAM_HIT_FLUSHING = 56, 876 }; 877 878 enum a2xx_mh_perfcnt_select { 879 CP_R0_REQUESTS = 0, 880 CP_R1_REQUESTS = 1, 881 CP_R2_REQUESTS = 2, 882 CP_R3_REQUESTS = 3, 883 CP_R4_REQUESTS = 4, 884 CP_TOTAL_READ_REQUESTS = 5, 885 CP_TOTAL_WRITE_REQUESTS = 6, 886 CP_TOTAL_REQUESTS = 7, 887 CP_DATA_BYTES_WRITTEN = 8, 888 CP_WRITE_CLEAN_RESPONSES = 9, 889 CP_R0_READ_BURSTS_RECEIVED = 10, 890 CP_R1_READ_BURSTS_RECEIVED = 11, 891 CP_R2_READ_BURSTS_RECEIVED = 12, 892 CP_R3_READ_BURSTS_RECEIVED = 13, 893 CP_R4_READ_BURSTS_RECEIVED = 14, 894 CP_TOTAL_READ_BURSTS_RECEIVED = 15, 895 CP_R0_DATA_BEATS_READ = 16, 896 CP_R1_DATA_BEATS_READ = 17, 897 CP_R2_DATA_BEATS_READ = 18, 898 CP_R3_DATA_BEATS_READ = 19, 899 CP_R4_DATA_BEATS_READ = 20, 900 CP_TOTAL_DATA_BEATS_READ = 21, 901 VGT_R0_REQUESTS = 22, 902 VGT_R1_REQUESTS = 23, 903 VGT_TOTAL_REQUESTS = 24, 904 VGT_R0_READ_BURSTS_RECEIVED = 25, 905 VGT_R1_READ_BURSTS_RECEIVED = 26, 906 VGT_TOTAL_READ_BURSTS_RECEIVED = 27, 907 VGT_R0_DATA_BEATS_READ = 28, 908 VGT_R1_DATA_BEATS_READ = 29, 909 VGT_TOTAL_DATA_BEATS_READ = 30, 910 TC_TOTAL_REQUESTS = 31, 911 TC_ROQ_REQUESTS = 32, 912 TC_INFO_SENT = 33, 913 TC_READ_BURSTS_RECEIVED = 34, 914 TC_DATA_BEATS_READ = 35, 915 TCD_BURSTS_READ = 36, 916 RB_REQUESTS = 37, 917 RB_DATA_BYTES_WRITTEN = 38, 918 RB_WRITE_CLEAN_RESPONSES = 39, 919 AXI_READ_REQUESTS_ID_0 = 40, 920 AXI_READ_REQUESTS_ID_1 = 41, 921 AXI_READ_REQUESTS_ID_2 = 42, 922 AXI_READ_REQUESTS_ID_3 = 43, 923 AXI_READ_REQUESTS_ID_4 = 44, 924 AXI_READ_REQUESTS_ID_5 = 45, 925 AXI_READ_REQUESTS_ID_6 = 46, 926 AXI_READ_REQUESTS_ID_7 = 47, 927 AXI_TOTAL_READ_REQUESTS = 48, 928 AXI_WRITE_REQUESTS_ID_0 = 49, 929 AXI_WRITE_REQUESTS_ID_1 = 50, 930 AXI_WRITE_REQUESTS_ID_2 = 51, 931 AXI_WRITE_REQUESTS_ID_3 = 52, 932 AXI_WRITE_REQUESTS_ID_4 = 53, 933 AXI_WRITE_REQUESTS_ID_5 = 54, 934 AXI_WRITE_REQUESTS_ID_6 = 55, 935 AXI_WRITE_REQUESTS_ID_7 = 56, 936 AXI_TOTAL_WRITE_REQUESTS = 57, 937 AXI_TOTAL_REQUESTS_ID_0 = 58, 938 AXI_TOTAL_REQUESTS_ID_1 = 59, 939 AXI_TOTAL_REQUESTS_ID_2 = 60, 940 AXI_TOTAL_REQUESTS_ID_3 = 61, 941 AXI_TOTAL_REQUESTS_ID_4 = 62, 942 AXI_TOTAL_REQUESTS_ID_5 = 63, 943 AXI_TOTAL_REQUESTS_ID_6 = 64, 944 AXI_TOTAL_REQUESTS_ID_7 = 65, 945 AXI_TOTAL_REQUESTS = 66, 946 AXI_READ_CHANNEL_BURSTS_ID_0 = 67, 947 AXI_READ_CHANNEL_BURSTS_ID_1 = 68, 948 AXI_READ_CHANNEL_BURSTS_ID_2 = 69, 949 AXI_READ_CHANNEL_BURSTS_ID_3 = 70, 950 AXI_READ_CHANNEL_BURSTS_ID_4 = 71, 951 AXI_READ_CHANNEL_BURSTS_ID_5 = 72, 952 AXI_READ_CHANNEL_BURSTS_ID_6 = 73, 953 AXI_READ_CHANNEL_BURSTS_ID_7 = 74, 954 AXI_READ_CHANNEL_TOTAL_BURSTS = 75, 955 AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0 = 76, 956 AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1 = 77, 957 AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2 = 78, 958 AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3 = 79, 959 AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4 = 80, 960 AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5 = 81, 961 AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6 = 82, 962 AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7 = 83, 963 AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ = 84, 964 AXI_WRITE_CHANNEL_BURSTS_ID_0 = 85, 965 AXI_WRITE_CHANNEL_BURSTS_ID_1 = 86, 966 AXI_WRITE_CHANNEL_BURSTS_ID_2 = 87, 967 AXI_WRITE_CHANNEL_BURSTS_ID_3 = 88, 968 AXI_WRITE_CHANNEL_BURSTS_ID_4 = 89, 969 AXI_WRITE_CHANNEL_BURSTS_ID_5 = 90, 970 AXI_WRITE_CHANNEL_BURSTS_ID_6 = 91, 971 AXI_WRITE_CHANNEL_BURSTS_ID_7 = 92, 972 AXI_WRITE_CHANNEL_TOTAL_BURSTS = 93, 973 AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0 = 94, 974 AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1 = 95, 975 AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2 = 96, 976 AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3 = 97, 977 AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4 = 98, 978 AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5 = 99, 979 AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6 = 100, 980 AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7 = 101, 981 AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN = 102, 982 AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0 = 103, 983 AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1 = 104, 984 AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2 = 105, 985 AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3 = 106, 986 AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4 = 107, 987 AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5 = 108, 988 AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6 = 109, 989 AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7 = 110, 990 AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES = 111, 991 TOTAL_MMU_MISSES = 112, 992 MMU_READ_MISSES = 113, 993 MMU_WRITE_MISSES = 114, 994 TOTAL_MMU_HITS = 115, 995 MMU_READ_HITS = 116, 996 MMU_WRITE_HITS = 117, 997 SPLIT_MODE_TC_HITS = 118, 998 SPLIT_MODE_TC_MISSES = 119, 999 SPLIT_MODE_NON_TC_HITS = 120, 1000 SPLIT_MODE_NON_TC_MISSES = 121, 1001 STALL_AWAITING_TLB_MISS_FETCH = 122, 1002 MMU_TLB_MISS_READ_BURSTS_RECEIVED = 123, 1003 MMU_TLB_MISS_DATA_BEATS_READ = 124, 1004 CP_CYCLES_HELD_OFF = 125, 1005 VGT_CYCLES_HELD_OFF = 126, 1006 TC_CYCLES_HELD_OFF = 127, 1007 TC_ROQ_CYCLES_HELD_OFF = 128, 1008 TC_CYCLES_HELD_OFF_TCD_FULL = 129, 1009 RB_CYCLES_HELD_OFF = 130, 1010 TOTAL_CYCLES_ANY_CLNT_HELD_OFF = 131, 1011 TLB_MISS_CYCLES_HELD_OFF = 132, 1012 AXI_READ_REQUEST_HELD_OFF = 133, 1013 AXI_WRITE_REQUEST_HELD_OFF = 134, 1014 AXI_REQUEST_HELD_OFF = 135, 1015 AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT = 136, 1016 AXI_WRITE_DATA_HELD_OFF = 137, 1017 CP_SAME_PAGE_BANK_REQUESTS = 138, 1018 VGT_SAME_PAGE_BANK_REQUESTS = 139, 1019 TC_SAME_PAGE_BANK_REQUESTS = 140, 1020 TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS = 141, 1021 RB_SAME_PAGE_BANK_REQUESTS = 142, 1022 TOTAL_SAME_PAGE_BANK_REQUESTS = 143, 1023 CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 144, 1024 VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 145, 1025 TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 146, 1026 RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 147, 1027 TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT = 148, 1028 TOTAL_MH_READ_REQUESTS = 149, 1029 TOTAL_MH_WRITE_REQUESTS = 150, 1030 TOTAL_MH_REQUESTS = 151, 1031 MH_BUSY = 152, 1032 CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 153, 1033 VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 154, 1034 TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 155, 1035 RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 156, 1036 TC_ROQ_N_VALID_ENTRIES = 157, 1037 ARQ_N_ENTRIES = 158, 1038 WDB_N_ENTRIES = 159, 1039 MH_READ_LATENCY_OUTST_REQ_SUM = 160, 1040 MC_READ_LATENCY_OUTST_REQ_SUM = 161, 1041 MC_TOTAL_READ_REQUESTS = 162, 1042 ELAPSED_CYCLES_MH_GATED_CLK = 163, 1043 ELAPSED_CLK_CYCLES = 164, 1044 CP_W_16B_REQUESTS = 165, 1045 CP_W_32B_REQUESTS = 166, 1046 TC_16B_REQUESTS = 167, 1047 TC_32B_REQUESTS = 168, 1048 PA_REQUESTS = 169, 1049 PA_DATA_BYTES_WRITTEN = 170, 1050 PA_WRITE_CLEAN_RESPONSES = 171, 1051 PA_CYCLES_HELD_OFF = 172, 1052 AXI_READ_REQUEST_DATA_BEATS_ID_0 = 173, 1053 AXI_READ_REQUEST_DATA_BEATS_ID_1 = 174, 1054 AXI_READ_REQUEST_DATA_BEATS_ID_2 = 175, 1055 AXI_READ_REQUEST_DATA_BEATS_ID_3 = 176, 1056 AXI_READ_REQUEST_DATA_BEATS_ID_4 = 177, 1057 AXI_READ_REQUEST_DATA_BEATS_ID_5 = 178, 1058 AXI_READ_REQUEST_DATA_BEATS_ID_6 = 179, 1059 AXI_READ_REQUEST_DATA_BEATS_ID_7 = 180, 1060 AXI_TOTAL_READ_REQUEST_DATA_BEATS = 181, 1061 }; 1062 1063 enum adreno_mmu_clnt_beh { 1064 BEH_NEVR = 0, 1065 BEH_TRAN_RNG = 1, 1066 BEH_TRAN_FLT = 2, 1067 }; 1068 1069 enum sq_tex_clamp { 1070 SQ_TEX_WRAP = 0, 1071 SQ_TEX_MIRROR = 1, 1072 SQ_TEX_CLAMP_LAST_TEXEL = 2, 1073 SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3, 1074 SQ_TEX_CLAMP_HALF_BORDER = 4, 1075 SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5, 1076 SQ_TEX_CLAMP_BORDER = 6, 1077 SQ_TEX_MIRROR_ONCE_BORDER = 7, 1078 }; 1079 1080 enum sq_tex_swiz { 1081 SQ_TEX_X = 0, 1082 SQ_TEX_Y = 1, 1083 SQ_TEX_Z = 2, 1084 SQ_TEX_W = 3, 1085 SQ_TEX_ZERO = 4, 1086 SQ_TEX_ONE = 5, 1087 }; 1088 1089 enum sq_tex_filter { 1090 SQ_TEX_FILTER_POINT = 0, 1091 SQ_TEX_FILTER_BILINEAR = 1, 1092 SQ_TEX_FILTER_BASEMAP = 2, 1093 SQ_TEX_FILTER_USE_FETCH_CONST = 3, 1094 }; 1095 1096 enum sq_tex_aniso_filter { 1097 SQ_TEX_ANISO_FILTER_DISABLED = 0, 1098 SQ_TEX_ANISO_FILTER_MAX_1_1 = 1, 1099 SQ_TEX_ANISO_FILTER_MAX_2_1 = 2, 1100 SQ_TEX_ANISO_FILTER_MAX_4_1 = 3, 1101 SQ_TEX_ANISO_FILTER_MAX_8_1 = 4, 1102 SQ_TEX_ANISO_FILTER_MAX_16_1 = 5, 1103 SQ_TEX_ANISO_FILTER_USE_FETCH_CONST = 7, 1104 }; 1105 1106 enum sq_tex_dimension { 1107 SQ_TEX_DIMENSION_1D = 0, 1108 SQ_TEX_DIMENSION_2D = 1, 1109 SQ_TEX_DIMENSION_3D = 2, 1110 SQ_TEX_DIMENSION_CUBE = 3, 1111 }; 1112 1113 enum sq_tex_border_color { 1114 SQ_TEX_BORDER_COLOR_BLACK = 0, 1115 SQ_TEX_BORDER_COLOR_WHITE = 1, 1116 SQ_TEX_BORDER_COLOR_ACBYCR_BLACK = 2, 1117 SQ_TEX_BORDER_COLOR_ACBCRY_BLACK = 3, 1118 }; 1119 1120 enum sq_tex_sign { 1121 SQ_TEX_SIGN_UNSIGNED = 0, 1122 SQ_TEX_SIGN_SIGNED = 1, 1123 SQ_TEX_SIGN_UNSIGNED_BIASED = 2, 1124 SQ_TEX_SIGN_GAMMA = 3, 1125 }; 1126 1127 enum sq_tex_endian { 1128 SQ_TEX_ENDIAN_NONE = 0, 1129 SQ_TEX_ENDIAN_8IN16 = 1, 1130 SQ_TEX_ENDIAN_8IN32 = 2, 1131 SQ_TEX_ENDIAN_16IN32 = 3, 1132 }; 1133 1134 enum sq_tex_clamp_policy { 1135 SQ_TEX_CLAMP_POLICY_D3D = 0, 1136 SQ_TEX_CLAMP_POLICY_OGL = 1, 1137 }; 1138 1139 enum sq_tex_num_format { 1140 SQ_TEX_NUM_FORMAT_FRAC = 0, 1141 SQ_TEX_NUM_FORMAT_INT = 1, 1142 }; 1143 1144 enum sq_tex_type { 1145 SQ_TEX_TYPE_0 = 0, 1146 SQ_TEX_TYPE_1 = 1, 1147 SQ_TEX_TYPE_2 = 2, 1148 SQ_TEX_TYPE_3 = 3, 1149 }; 1150 1151 #define REG_A2XX_RBBM_PATCH_RELEASE 0x00000001 1152 1153 #define REG_A2XX_RBBM_CNTL 0x0000003b 1154 1155 #define REG_A2XX_RBBM_SOFT_RESET 0x0000003c 1156 1157 #define REG_A2XX_CP_PFP_UCODE_ADDR 0x000000c0 1158 1159 #define REG_A2XX_CP_PFP_UCODE_DATA 0x000000c1 1160 1161 #define REG_A2XX_MH_MMU_CONFIG 0x00000040 1162 #define A2XX_MH_MMU_CONFIG_MMU_ENABLE 0x00000001 1163 #define A2XX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE 0x00000002 1164 #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK 0x00000030 1165 #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT 4 1166 static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1167 { 1168 return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK; 1169 } 1170 #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK 0x000000c0 1171 #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT 6 1172 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1173 { 1174 return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK; 1175 } 1176 #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK 0x00000300 1177 #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT 8 1178 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1179 { 1180 return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK; 1181 } 1182 #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK 0x00000c00 1183 #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT 10 1184 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1185 { 1186 return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK; 1187 } 1188 #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK 0x00003000 1189 #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT 12 1190 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1191 { 1192 return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK; 1193 } 1194 #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK 0x0000c000 1195 #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT 14 1196 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1197 { 1198 return ((val) << A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK; 1199 } 1200 #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK 0x00030000 1201 #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT 16 1202 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1203 { 1204 return ((val) << A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK; 1205 } 1206 #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK 0x000c0000 1207 #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT 18 1208 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1209 { 1210 return ((val) << A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK; 1211 } 1212 #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK 0x00300000 1213 #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT 20 1214 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1215 { 1216 return ((val) << A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK; 1217 } 1218 #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK 0x00c00000 1219 #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT 22 1220 static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1221 { 1222 return ((val) << A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK; 1223 } 1224 #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK 0x03000000 1225 #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT 24 1226 static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1227 { 1228 return ((val) << A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK; 1229 } 1230 1231 #define REG_A2XX_MH_MMU_VA_RANGE 0x00000041 1232 #define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK 0x00000fff 1233 #define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT 0 1234 static inline uint32_t A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS(uint32_t val) 1235 { 1236 return ((val) << A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT) & A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK; 1237 } 1238 #define A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK 0xfffff000 1239 #define A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT 12 1240 static inline uint32_t A2XX_MH_MMU_VA_RANGE_VA_BASE(uint32_t val) 1241 { 1242 return ((val) << A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT) & A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK; 1243 } 1244 1245 #define REG_A2XX_MH_MMU_PT_BASE 0x00000042 1246 1247 #define REG_A2XX_MH_MMU_PAGE_FAULT 0x00000043 1248 1249 #define REG_A2XX_MH_MMU_TRAN_ERROR 0x00000044 1250 1251 #define REG_A2XX_MH_MMU_INVALIDATE 0x00000045 1252 #define A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL 0x00000001 1253 #define A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC 0x00000002 1254 1255 #define REG_A2XX_MH_MMU_MPU_BASE 0x00000046 1256 1257 #define REG_A2XX_MH_MMU_MPU_END 0x00000047 1258 1259 #define REG_A2XX_NQWAIT_UNTIL 0x00000394 1260 1261 #define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395 1262 1263 #define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397 1264 1265 #define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x00000398 1266 1267 #define REG_A2XX_RBBM_DEBUG 0x0000039b 1268 1269 #define REG_A2XX_RBBM_PM_OVERRIDE1 0x0000039c 1270 #define A2XX_RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE 0x00000001 1271 #define A2XX_RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE 0x00000002 1272 #define A2XX_RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE 0x00000004 1273 #define A2XX_RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE 0x00000008 1274 #define A2XX_RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE 0x00000010 1275 #define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE 0x00000020 1276 #define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE 0x00000040 1277 #define A2XX_RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE 0x00000080 1278 #define A2XX_RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE 0x00000100 1279 #define A2XX_RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE 0x00000200 1280 #define A2XX_RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE 0x00000400 1281 #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE 0x00000800 1282 #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE 0x00001000 1283 #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE 0x00002000 1284 #define A2XX_RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE 0x00004000 1285 #define A2XX_RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE 0x00008000 1286 #define A2XX_RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE 0x00010000 1287 #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE 0x00020000 1288 #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE 0x00040000 1289 #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE 0x00080000 1290 #define A2XX_RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE 0x00100000 1291 #define A2XX_RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE 0x00200000 1292 #define A2XX_RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE 0x00400000 1293 #define A2XX_RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE 0x00800000 1294 #define A2XX_RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE 0x01000000 1295 #define A2XX_RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE 0x02000000 1296 #define A2XX_RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE 0x04000000 1297 #define A2XX_RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE 0x08000000 1298 #define A2XX_RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE 0x10000000 1299 #define A2XX_RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE 0x20000000 1300 #define A2XX_RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE 0x40000000 1301 #define A2XX_RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE 0x80000000 1302 1303 #define REG_A2XX_RBBM_PM_OVERRIDE2 0x0000039d 1304 1305 #define REG_A2XX_RBBM_DEBUG_OUT 0x000003a0 1306 1307 #define REG_A2XX_RBBM_DEBUG_CNTL 0x000003a1 1308 1309 #define REG_A2XX_RBBM_READ_ERROR 0x000003b3 1310 1311 #define REG_A2XX_RBBM_INT_CNTL 0x000003b4 1312 #define A2XX_RBBM_INT_CNTL_RDERR_INT_MASK 0x00000001 1313 #define A2XX_RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK 0x00000002 1314 #define A2XX_RBBM_INT_CNTL_GUI_IDLE_INT_MASK 0x00080000 1315 1316 #define REG_A2XX_RBBM_INT_STATUS 0x000003b5 1317 1318 #define REG_A2XX_RBBM_INT_ACK 0x000003b6 1319 1320 #define REG_A2XX_MASTER_INT_SIGNAL 0x000003b7 1321 #define A2XX_MASTER_INT_SIGNAL_MH_INT_STAT 0x00000020 1322 #define A2XX_MASTER_INT_SIGNAL_SQ_INT_STAT 0x04000000 1323 #define A2XX_MASTER_INT_SIGNAL_CP_INT_STAT 0x40000000 1324 #define A2XX_MASTER_INT_SIGNAL_RBBM_INT_STAT 0x80000000 1325 1326 #define REG_A2XX_RBBM_PERIPHID1 0x000003f9 1327 1328 #define REG_A2XX_RBBM_PERIPHID2 0x000003fa 1329 1330 #define REG_A2XX_CP_PERFMON_CNTL 0x00000444 1331 1332 #define REG_A2XX_CP_PERFCOUNTER_SELECT 0x00000445 1333 1334 #define REG_A2XX_CP_PERFCOUNTER_LO 0x00000446 1335 1336 #define REG_A2XX_CP_PERFCOUNTER_HI 0x00000447 1337 1338 #define REG_A2XX_RBBM_STATUS 0x000005d0 1339 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK 0x0000001f 1340 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT 0 1341 static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val) 1342 { 1343 return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK; 1344 } 1345 #define A2XX_RBBM_STATUS_TC_BUSY 0x00000020 1346 #define A2XX_RBBM_STATUS_HIRQ_PENDING 0x00000100 1347 #define A2XX_RBBM_STATUS_CPRQ_PENDING 0x00000200 1348 #define A2XX_RBBM_STATUS_CFRQ_PENDING 0x00000400 1349 #define A2XX_RBBM_STATUS_PFRQ_PENDING 0x00000800 1350 #define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA 0x00001000 1351 #define A2XX_RBBM_STATUS_RBBM_WU_BUSY 0x00004000 1352 #define A2XX_RBBM_STATUS_CP_NRT_BUSY 0x00010000 1353 #define A2XX_RBBM_STATUS_MH_BUSY 0x00040000 1354 #define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY 0x00080000 1355 #define A2XX_RBBM_STATUS_SX_BUSY 0x00200000 1356 #define A2XX_RBBM_STATUS_TPC_BUSY 0x00400000 1357 #define A2XX_RBBM_STATUS_SC_CNTX_BUSY 0x01000000 1358 #define A2XX_RBBM_STATUS_PA_BUSY 0x02000000 1359 #define A2XX_RBBM_STATUS_VGT_BUSY 0x04000000 1360 #define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY 0x08000000 1361 #define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY 0x10000000 1362 #define A2XX_RBBM_STATUS_RB_CNTX_BUSY 0x40000000 1363 #define A2XX_RBBM_STATUS_GUI_ACTIVE 0x80000000 1364 1365 #define REG_A2XX_MH_ARBITER_CONFIG 0x00000a40 1366 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK 0x0000003f 1367 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT 0 1368 static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val) 1369 { 1370 return ((val) << A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK; 1371 } 1372 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY 0x00000040 1373 #define A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE 0x00000080 1374 #define A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE 0x00000100 1375 #define A2XX_MH_ARBITER_CONFIG_L2_ARB_CONTROL 0x00000200 1376 #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK 0x00001c00 1377 #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT 10 1378 static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val) 1379 { 1380 return ((val) << A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT) & A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK; 1381 } 1382 #define A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00002000 1383 #define A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE 0x00004000 1384 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE 0x00008000 1385 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK 0x003f0000 1386 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT 16 1387 static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val) 1388 { 1389 return ((val) << A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK; 1390 } 1391 #define A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE 0x00400000 1392 #define A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE 0x00800000 1393 #define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE 0x01000000 1394 #define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE 0x02000000 1395 #define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE 0x04000000 1396 1397 #define REG_A2XX_MH_INTERRUPT_MASK 0x00000a42 1398 #define A2XX_MH_INTERRUPT_MASK_AXI_READ_ERROR 0x00000001 1399 #define A2XX_MH_INTERRUPT_MASK_AXI_WRITE_ERROR 0x00000002 1400 #define A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT 0x00000004 1401 1402 #define REG_A2XX_MH_INTERRUPT_STATUS 0x00000a43 1403 1404 #define REG_A2XX_MH_INTERRUPT_CLEAR 0x00000a44 1405 1406 #define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1 0x00000a54 1407 1408 #define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG2 0x00000a55 1409 1410 #define REG_A2XX_A220_VSC_BIN_SIZE 0x00000c01 1411 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 1412 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT 0 1413 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val) 1414 { 1415 return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK; 1416 } 1417 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 1418 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT 5 1419 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val) 1420 { 1421 return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK; 1422 } 1423 1424 static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 1425 1426 static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 1427 1428 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } 1429 1430 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } 1431 1432 #define REG_A2XX_PC_DEBUG_CNTL 0x00000c38 1433 1434 #define REG_A2XX_PC_DEBUG_DATA 0x00000c39 1435 1436 #define REG_A2XX_PA_SC_VIZ_QUERY_STATUS 0x00000c44 1437 1438 #define REG_A2XX_GRAS_DEBUG_CNTL 0x00000c80 1439 1440 #define REG_A2XX_PA_SU_DEBUG_CNTL 0x00000c80 1441 1442 #define REG_A2XX_GRAS_DEBUG_DATA 0x00000c81 1443 1444 #define REG_A2XX_PA_SU_DEBUG_DATA 0x00000c81 1445 1446 #define REG_A2XX_PA_SU_FACE_DATA 0x00000c86 1447 #define A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK 0xffffffe0 1448 #define A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT 5 1449 static inline uint32_t A2XX_PA_SU_FACE_DATA_BASE_ADDR(uint32_t val) 1450 { 1451 return ((val) << A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT) & A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK; 1452 } 1453 1454 #define REG_A2XX_SQ_GPR_MANAGEMENT 0x00000d00 1455 #define A2XX_SQ_GPR_MANAGEMENT_REG_DYNAMIC 0x00000001 1456 #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK 0x00000ff0 1457 #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT 4 1458 static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX(uint32_t val) 1459 { 1460 return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK; 1461 } 1462 #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK 0x000ff000 1463 #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT 12 1464 static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX(uint32_t val) 1465 { 1466 return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK; 1467 } 1468 1469 #define REG_A2XX_SQ_FLOW_CONTROL 0x00000d01 1470 1471 #define REG_A2XX_SQ_INST_STORE_MANAGMENT 0x00000d02 1472 #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK 0x00000fff 1473 #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT 0 1474 static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX(uint32_t val) 1475 { 1476 return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK; 1477 } 1478 #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK 0x0fff0000 1479 #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT 16 1480 static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX(uint32_t val) 1481 { 1482 return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK; 1483 } 1484 1485 #define REG_A2XX_SQ_DEBUG_MISC 0x00000d05 1486 1487 #define REG_A2XX_SQ_INT_CNTL 0x00000d34 1488 1489 #define REG_A2XX_SQ_INT_STATUS 0x00000d35 1490 1491 #define REG_A2XX_SQ_INT_ACK 0x00000d36 1492 1493 #define REG_A2XX_SQ_DEBUG_INPUT_FSM 0x00000dae 1494 1495 #define REG_A2XX_SQ_DEBUG_CONST_MGR_FSM 0x00000daf 1496 1497 #define REG_A2XX_SQ_DEBUG_TP_FSM 0x00000db0 1498 1499 #define REG_A2XX_SQ_DEBUG_FSM_ALU_0 0x00000db1 1500 1501 #define REG_A2XX_SQ_DEBUG_FSM_ALU_1 0x00000db2 1502 1503 #define REG_A2XX_SQ_DEBUG_EXP_ALLOC 0x00000db3 1504 1505 #define REG_A2XX_SQ_DEBUG_PTR_BUFF 0x00000db4 1506 1507 #define REG_A2XX_SQ_DEBUG_GPR_VTX 0x00000db5 1508 1509 #define REG_A2XX_SQ_DEBUG_GPR_PIX 0x00000db6 1510 1511 #define REG_A2XX_SQ_DEBUG_TB_STATUS_SEL 0x00000db7 1512 1513 #define REG_A2XX_SQ_DEBUG_VTX_TB_0 0x00000db8 1514 1515 #define REG_A2XX_SQ_DEBUG_VTX_TB_1 0x00000db9 1516 1517 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG 0x00000dba 1518 1519 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM 0x00000dbb 1520 1521 #define REG_A2XX_SQ_DEBUG_PIX_TB_0 0x00000dbc 1522 1523 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0 0x00000dbd 1524 1525 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1 0x00000dbe 1526 1527 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2 0x00000dbf 1528 1529 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3 0x00000dc0 1530 1531 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM 0x00000dc1 1532 1533 #define REG_A2XX_TC_CNTL_STATUS 0x00000e00 1534 #define A2XX_TC_CNTL_STATUS_L2_INVALIDATE 0x00000001 1535 1536 #define REG_A2XX_TP0_CHICKEN 0x00000e1e 1537 1538 #define REG_A2XX_RB_BC_CONTROL 0x00000f01 1539 #define A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE 0x00000001 1540 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK 0x00000006 1541 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT 1 1542 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val) 1543 { 1544 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK; 1545 } 1546 #define A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM 0x00000008 1547 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010 1548 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP 0x00000020 1549 #define A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP 0x00000040 1550 #define A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE 0x00000080 1551 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK 0x00001f00 1552 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT 8 1553 static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val) 1554 { 1555 return ((val) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK; 1556 } 1557 #define A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE 0x00004000 1558 #define A2XX_RB_BC_CONTROL_CRC_MODE 0x00008000 1559 #define A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS 0x00010000 1560 #define A2XX_RB_BC_CONTROL_DISABLE_ACCUM 0x00020000 1561 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK 0x003c0000 1562 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT 18 1563 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val) 1564 { 1565 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK; 1566 } 1567 #define A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE 0x00400000 1568 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK 0x07800000 1569 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT 23 1570 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val) 1571 { 1572 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK; 1573 } 1574 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK 0x18000000 1575 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT 27 1576 static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val) 1577 { 1578 return ((val) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK; 1579 } 1580 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000 1581 #define A2XX_RB_BC_CONTROL_CRC_SYSTEM 0x40000000 1582 #define A2XX_RB_BC_CONTROL_RESERVED6 0x80000000 1583 1584 #define REG_A2XX_RB_EDRAM_INFO 0x00000f02 1585 1586 #define REG_A2XX_RB_DEBUG_CNTL 0x00000f26 1587 1588 #define REG_A2XX_RB_DEBUG_DATA 0x00000f27 1589 1590 #define REG_A2XX_RB_SURFACE_INFO 0x00002000 1591 #define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK 0x00003fff 1592 #define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT 0 1593 static inline uint32_t A2XX_RB_SURFACE_INFO_SURFACE_PITCH(uint32_t val) 1594 { 1595 return ((val) << A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT) & A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK; 1596 } 1597 #define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK 0x0000c000 1598 #define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT 14 1599 static inline uint32_t A2XX_RB_SURFACE_INFO_MSAA_SAMPLES(uint32_t val) 1600 { 1601 return ((val) << A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT) & A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK; 1602 } 1603 1604 #define REG_A2XX_RB_COLOR_INFO 0x00002001 1605 #define A2XX_RB_COLOR_INFO_FORMAT__MASK 0x0000000f 1606 #define A2XX_RB_COLOR_INFO_FORMAT__SHIFT 0 1607 static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val) 1608 { 1609 return ((val) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT) & A2XX_RB_COLOR_INFO_FORMAT__MASK; 1610 } 1611 #define A2XX_RB_COLOR_INFO_ROUND_MODE__MASK 0x00000030 1612 #define A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT 4 1613 static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val) 1614 { 1615 return ((val) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK; 1616 } 1617 #define A2XX_RB_COLOR_INFO_LINEAR 0x00000040 1618 #define A2XX_RB_COLOR_INFO_ENDIAN__MASK 0x00000180 1619 #define A2XX_RB_COLOR_INFO_ENDIAN__SHIFT 7 1620 static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val) 1621 { 1622 return ((val) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT) & A2XX_RB_COLOR_INFO_ENDIAN__MASK; 1623 } 1624 #define A2XX_RB_COLOR_INFO_SWAP__MASK 0x00000600 1625 #define A2XX_RB_COLOR_INFO_SWAP__SHIFT 9 1626 static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val) 1627 { 1628 return ((val) << A2XX_RB_COLOR_INFO_SWAP__SHIFT) & A2XX_RB_COLOR_INFO_SWAP__MASK; 1629 } 1630 #define A2XX_RB_COLOR_INFO_BASE__MASK 0xfffff000 1631 #define A2XX_RB_COLOR_INFO_BASE__SHIFT 12 1632 static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val) 1633 { 1634 return ((val >> 12) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK; 1635 } 1636 1637 #define REG_A2XX_RB_DEPTH_INFO 0x00002002 1638 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001 1639 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 1640 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) 1641 { 1642 return ((val) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 1643 } 1644 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 1645 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 1646 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 1647 { 1648 return ((val >> 12) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 1649 } 1650 1651 #define REG_A2XX_A225_RB_COLOR_INFO3 0x00002005 1652 1653 #define REG_A2XX_COHER_DEST_BASE_0 0x00002006 1654 1655 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_TL 0x0000200e 1656 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 1657 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 1658 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 1659 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 1660 { 1661 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK; 1662 } 1663 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 1664 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 1665 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 1666 { 1667 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK; 1668 } 1669 1670 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_BR 0x0000200f 1671 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 1672 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 1673 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 1674 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 1675 { 1676 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK; 1677 } 1678 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 1679 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 1680 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 1681 { 1682 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK; 1683 } 1684 1685 #define REG_A2XX_PA_SC_WINDOW_OFFSET 0x00002080 1686 #define A2XX_PA_SC_WINDOW_OFFSET_X__MASK 0x00007fff 1687 #define A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT 0 1688 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val) 1689 { 1690 return ((val) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK; 1691 } 1692 #define A2XX_PA_SC_WINDOW_OFFSET_Y__MASK 0x7fff0000 1693 #define A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT 16 1694 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val) 1695 { 1696 return ((val) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK; 1697 } 1698 #define A2XX_PA_SC_WINDOW_OFFSET_DISABLE 0x80000000 1699 1700 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_TL 0x00002081 1701 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 1702 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 1703 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 1704 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 1705 { 1706 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK; 1707 } 1708 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 1709 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 1710 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 1711 { 1712 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK; 1713 } 1714 1715 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_BR 0x00002082 1716 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 1717 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 1718 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 1719 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 1720 { 1721 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK; 1722 } 1723 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 1724 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 1725 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 1726 { 1727 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK; 1728 } 1729 1730 #define REG_A2XX_UNKNOWN_2010 0x00002010 1731 1732 #define REG_A2XX_VGT_MAX_VTX_INDX 0x00002100 1733 1734 #define REG_A2XX_VGT_MIN_VTX_INDX 0x00002101 1735 1736 #define REG_A2XX_VGT_INDX_OFFSET 0x00002102 1737 1738 #define REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX 0x00002103 1739 1740 #define REG_A2XX_RB_COLOR_MASK 0x00002104 1741 #define A2XX_RB_COLOR_MASK_WRITE_RED 0x00000001 1742 #define A2XX_RB_COLOR_MASK_WRITE_GREEN 0x00000002 1743 #define A2XX_RB_COLOR_MASK_WRITE_BLUE 0x00000004 1744 #define A2XX_RB_COLOR_MASK_WRITE_ALPHA 0x00000008 1745 1746 #define REG_A2XX_RB_BLEND_RED 0x00002105 1747 1748 #define REG_A2XX_RB_BLEND_GREEN 0x00002106 1749 1750 #define REG_A2XX_RB_BLEND_BLUE 0x00002107 1751 1752 #define REG_A2XX_RB_BLEND_ALPHA 0x00002108 1753 1754 #define REG_A2XX_RB_FOG_COLOR 0x00002109 1755 #define A2XX_RB_FOG_COLOR_FOG_RED__MASK 0x000000ff 1756 #define A2XX_RB_FOG_COLOR_FOG_RED__SHIFT 0 1757 static inline uint32_t A2XX_RB_FOG_COLOR_FOG_RED(uint32_t val) 1758 { 1759 return ((val) << A2XX_RB_FOG_COLOR_FOG_RED__SHIFT) & A2XX_RB_FOG_COLOR_FOG_RED__MASK; 1760 } 1761 #define A2XX_RB_FOG_COLOR_FOG_GREEN__MASK 0x0000ff00 1762 #define A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT 8 1763 static inline uint32_t A2XX_RB_FOG_COLOR_FOG_GREEN(uint32_t val) 1764 { 1765 return ((val) << A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT) & A2XX_RB_FOG_COLOR_FOG_GREEN__MASK; 1766 } 1767 #define A2XX_RB_FOG_COLOR_FOG_BLUE__MASK 0x00ff0000 1768 #define A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT 16 1769 static inline uint32_t A2XX_RB_FOG_COLOR_FOG_BLUE(uint32_t val) 1770 { 1771 return ((val) << A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT) & A2XX_RB_FOG_COLOR_FOG_BLUE__MASK; 1772 } 1773 1774 #define REG_A2XX_RB_STENCILREFMASK_BF 0x0000210c 1775 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 1776 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 1777 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 1778 { 1779 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 1780 } 1781 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 1782 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 1783 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 1784 { 1785 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 1786 } 1787 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 1788 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 1789 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 1790 { 1791 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 1792 } 1793 1794 #define REG_A2XX_RB_STENCILREFMASK 0x0000210d 1795 #define A2XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 1796 #define A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 1797 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 1798 { 1799 return ((val) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK; 1800 } 1801 #define A2XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 1802 #define A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 1803 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 1804 { 1805 return ((val) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK; 1806 } 1807 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 1808 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 1809 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 1810 { 1811 return ((val) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 1812 } 1813 1814 #define REG_A2XX_RB_ALPHA_REF 0x0000210e 1815 1816 #define REG_A2XX_PA_CL_VPORT_XSCALE 0x0000210f 1817 #define A2XX_PA_CL_VPORT_XSCALE__MASK 0xffffffff 1818 #define A2XX_PA_CL_VPORT_XSCALE__SHIFT 0 1819 static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val) 1820 { 1821 return ((fui(val)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT) & A2XX_PA_CL_VPORT_XSCALE__MASK; 1822 } 1823 1824 #define REG_A2XX_PA_CL_VPORT_XOFFSET 0x00002110 1825 #define A2XX_PA_CL_VPORT_XOFFSET__MASK 0xffffffff 1826 #define A2XX_PA_CL_VPORT_XOFFSET__SHIFT 0 1827 static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val) 1828 { 1829 return ((fui(val)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT) & A2XX_PA_CL_VPORT_XOFFSET__MASK; 1830 } 1831 1832 #define REG_A2XX_PA_CL_VPORT_YSCALE 0x00002111 1833 #define A2XX_PA_CL_VPORT_YSCALE__MASK 0xffffffff 1834 #define A2XX_PA_CL_VPORT_YSCALE__SHIFT 0 1835 static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val) 1836 { 1837 return ((fui(val)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT) & A2XX_PA_CL_VPORT_YSCALE__MASK; 1838 } 1839 1840 #define REG_A2XX_PA_CL_VPORT_YOFFSET 0x00002112 1841 #define A2XX_PA_CL_VPORT_YOFFSET__MASK 0xffffffff 1842 #define A2XX_PA_CL_VPORT_YOFFSET__SHIFT 0 1843 static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val) 1844 { 1845 return ((fui(val)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT) & A2XX_PA_CL_VPORT_YOFFSET__MASK; 1846 } 1847 1848 #define REG_A2XX_PA_CL_VPORT_ZSCALE 0x00002113 1849 #define A2XX_PA_CL_VPORT_ZSCALE__MASK 0xffffffff 1850 #define A2XX_PA_CL_VPORT_ZSCALE__SHIFT 0 1851 static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val) 1852 { 1853 return ((fui(val)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT) & A2XX_PA_CL_VPORT_ZSCALE__MASK; 1854 } 1855 1856 #define REG_A2XX_PA_CL_VPORT_ZOFFSET 0x00002114 1857 #define A2XX_PA_CL_VPORT_ZOFFSET__MASK 0xffffffff 1858 #define A2XX_PA_CL_VPORT_ZOFFSET__SHIFT 0 1859 static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val) 1860 { 1861 return ((fui(val)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT) & A2XX_PA_CL_VPORT_ZOFFSET__MASK; 1862 } 1863 1864 #define REG_A2XX_SQ_PROGRAM_CNTL 0x00002180 1865 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK 0x000000ff 1866 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT 0 1867 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val) 1868 { 1869 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK; 1870 } 1871 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK 0x0000ff00 1872 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT 8 1873 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val) 1874 { 1875 return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK; 1876 } 1877 #define A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE 0x00010000 1878 #define A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE 0x00020000 1879 #define A2XX_SQ_PROGRAM_CNTL_PARAM_GEN 0x00040000 1880 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX 0x00080000 1881 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK 0x00f00000 1882 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT 20 1883 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val) 1884 { 1885 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK; 1886 } 1887 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK 0x07000000 1888 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT 24 1889 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val) 1890 { 1891 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK; 1892 } 1893 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK 0x78000000 1894 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT 27 1895 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val) 1896 { 1897 return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK; 1898 } 1899 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX 0x80000000 1900 1901 #define REG_A2XX_SQ_CONTEXT_MISC 0x00002181 1902 #define A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE 0x00000001 1903 #define A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY 0x00000002 1904 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK 0x0000000c 1905 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT 2 1906 static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val) 1907 { 1908 return ((val) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK; 1909 } 1910 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK 0x0000ff00 1911 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT 8 1912 static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val) 1913 { 1914 return ((val) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK; 1915 } 1916 #define A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF 0x00010000 1917 #define A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE 0x00020000 1918 #define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL 0x00040000 1919 1920 #define REG_A2XX_SQ_INTERPOLATOR_CNTL 0x00002182 1921 #define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK 0x0000ffff 1922 #define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT 0 1923 static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE(uint32_t val) 1924 { 1925 return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK; 1926 } 1927 #define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK 0xffff0000 1928 #define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT 16 1929 static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN(uint32_t val) 1930 { 1931 return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK; 1932 } 1933 1934 #define REG_A2XX_SQ_WRAPPING_0 0x00002183 1935 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK 0x0000000f 1936 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT 0 1937 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_0(uint32_t val) 1938 { 1939 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK; 1940 } 1941 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK 0x000000f0 1942 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT 4 1943 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_1(uint32_t val) 1944 { 1945 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK; 1946 } 1947 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK 0x00000f00 1948 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT 8 1949 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_2(uint32_t val) 1950 { 1951 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK; 1952 } 1953 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK 0x0000f000 1954 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT 12 1955 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_3(uint32_t val) 1956 { 1957 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK; 1958 } 1959 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK 0x000f0000 1960 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT 16 1961 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_4(uint32_t val) 1962 { 1963 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK; 1964 } 1965 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK 0x00f00000 1966 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT 20 1967 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_5(uint32_t val) 1968 { 1969 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK; 1970 } 1971 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK 0x0f000000 1972 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT 24 1973 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_6(uint32_t val) 1974 { 1975 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK; 1976 } 1977 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK 0xf0000000 1978 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT 28 1979 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_7(uint32_t val) 1980 { 1981 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK; 1982 } 1983 1984 #define REG_A2XX_SQ_WRAPPING_1 0x00002184 1985 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK 0x0000000f 1986 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT 0 1987 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_8(uint32_t val) 1988 { 1989 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK; 1990 } 1991 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK 0x000000f0 1992 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT 4 1993 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_9(uint32_t val) 1994 { 1995 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK; 1996 } 1997 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK 0x00000f00 1998 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT 8 1999 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_10(uint32_t val) 2000 { 2001 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK; 2002 } 2003 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK 0x0000f000 2004 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT 12 2005 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_11(uint32_t val) 2006 { 2007 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK; 2008 } 2009 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK 0x000f0000 2010 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT 16 2011 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_12(uint32_t val) 2012 { 2013 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK; 2014 } 2015 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK 0x00f00000 2016 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT 20 2017 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_13(uint32_t val) 2018 { 2019 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK; 2020 } 2021 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK 0x0f000000 2022 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT 24 2023 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_14(uint32_t val) 2024 { 2025 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK; 2026 } 2027 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK 0xf0000000 2028 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT 28 2029 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_15(uint32_t val) 2030 { 2031 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK; 2032 } 2033 2034 #define REG_A2XX_SQ_PS_PROGRAM 0x000021f6 2035 #define A2XX_SQ_PS_PROGRAM_BASE__MASK 0x00000fff 2036 #define A2XX_SQ_PS_PROGRAM_BASE__SHIFT 0 2037 static inline uint32_t A2XX_SQ_PS_PROGRAM_BASE(uint32_t val) 2038 { 2039 return ((val) << A2XX_SQ_PS_PROGRAM_BASE__SHIFT) & A2XX_SQ_PS_PROGRAM_BASE__MASK; 2040 } 2041 #define A2XX_SQ_PS_PROGRAM_SIZE__MASK 0x00fff000 2042 #define A2XX_SQ_PS_PROGRAM_SIZE__SHIFT 12 2043 static inline uint32_t A2XX_SQ_PS_PROGRAM_SIZE(uint32_t val) 2044 { 2045 return ((val) << A2XX_SQ_PS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_PS_PROGRAM_SIZE__MASK; 2046 } 2047 2048 #define REG_A2XX_SQ_VS_PROGRAM 0x000021f7 2049 #define A2XX_SQ_VS_PROGRAM_BASE__MASK 0x00000fff 2050 #define A2XX_SQ_VS_PROGRAM_BASE__SHIFT 0 2051 static inline uint32_t A2XX_SQ_VS_PROGRAM_BASE(uint32_t val) 2052 { 2053 return ((val) << A2XX_SQ_VS_PROGRAM_BASE__SHIFT) & A2XX_SQ_VS_PROGRAM_BASE__MASK; 2054 } 2055 #define A2XX_SQ_VS_PROGRAM_SIZE__MASK 0x00fff000 2056 #define A2XX_SQ_VS_PROGRAM_SIZE__SHIFT 12 2057 static inline uint32_t A2XX_SQ_VS_PROGRAM_SIZE(uint32_t val) 2058 { 2059 return ((val) << A2XX_SQ_VS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_VS_PROGRAM_SIZE__MASK; 2060 } 2061 2062 #define REG_A2XX_VGT_EVENT_INITIATOR 0x000021f9 2063 2064 #define REG_A2XX_VGT_DRAW_INITIATOR 0x000021fc 2065 #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f 2066 #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 2067 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) 2068 { 2069 return ((val) << A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK; 2070 } 2071 #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 2072 #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 2073 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) 2074 { 2075 return ((val) << A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK; 2076 } 2077 #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600 2078 #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9 2079 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) 2080 { 2081 return ((val) << A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK; 2082 } 2083 #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800 2084 #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11 2085 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) 2086 { 2087 return ((val) << A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK; 2088 } 2089 #define A2XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000 2090 #define A2XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000 2091 #define A2XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000 2092 #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK 0xff000000 2093 #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT 24 2094 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) 2095 { 2096 return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK; 2097 } 2098 2099 #define REG_A2XX_VGT_IMMED_DATA 0x000021fd 2100 2101 #define REG_A2XX_RB_DEPTHCONTROL 0x00002200 2102 #define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE 0x00000001 2103 #define A2XX_RB_DEPTHCONTROL_Z_ENABLE 0x00000002 2104 #define A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE 0x00000004 2105 #define A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE 0x00000008 2106 #define A2XX_RB_DEPTHCONTROL_ZFUNC__MASK 0x00000070 2107 #define A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT 4 2108 static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val) 2109 { 2110 return ((val) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK; 2111 } 2112 #define A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE 0x00000080 2113 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK 0x00000700 2114 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT 8 2115 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val) 2116 { 2117 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK; 2118 } 2119 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK 0x00003800 2120 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT 11 2121 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val) 2122 { 2123 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK; 2124 } 2125 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK 0x0001c000 2126 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT 14 2127 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val) 2128 { 2129 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK; 2130 } 2131 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK 0x000e0000 2132 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT 17 2133 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val) 2134 { 2135 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK; 2136 } 2137 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK 0x00700000 2138 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT 20 2139 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val) 2140 { 2141 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK; 2142 } 2143 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK 0x03800000 2144 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT 23 2145 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val) 2146 { 2147 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK; 2148 } 2149 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK 0x1c000000 2150 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT 26 2151 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val) 2152 { 2153 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK; 2154 } 2155 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK 0xe0000000 2156 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT 29 2157 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val) 2158 { 2159 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK; 2160 } 2161 2162 #define REG_A2XX_RB_BLEND_CONTROL 0x00002201 2163 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK 0x0000001f 2164 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT 0 2165 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val) 2166 { 2167 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK; 2168 } 2169 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK 0x000000e0 2170 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT 5 2171 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val) 2172 { 2173 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK; 2174 } 2175 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK 0x00001f00 2176 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT 8 2177 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val) 2178 { 2179 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK; 2180 } 2181 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK 0x001f0000 2182 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT 16 2183 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val) 2184 { 2185 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK; 2186 } 2187 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK 0x00e00000 2188 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT 21 2189 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val) 2190 { 2191 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK; 2192 } 2193 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK 0x1f000000 2194 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT 24 2195 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val) 2196 { 2197 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK; 2198 } 2199 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE 0x20000000 2200 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE 0x40000000 2201 2202 #define REG_A2XX_RB_COLORCONTROL 0x00002202 2203 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK 0x00000007 2204 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT 0 2205 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val) 2206 { 2207 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK; 2208 } 2209 #define A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE 0x00000008 2210 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE 0x00000010 2211 #define A2XX_RB_COLORCONTROL_BLEND_DISABLE 0x00000020 2212 #define A2XX_RB_COLORCONTROL_VOB_ENABLE 0x00000040 2213 #define A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG 0x00000080 2214 #define A2XX_RB_COLORCONTROL_ROP_CODE__MASK 0x00000f00 2215 #define A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT 8 2216 static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val) 2217 { 2218 return ((val) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK; 2219 } 2220 #define A2XX_RB_COLORCONTROL_DITHER_MODE__MASK 0x00003000 2221 #define A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT 12 2222 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) 2223 { 2224 return ((val) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK; 2225 } 2226 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK 0x0000c000 2227 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT 14 2228 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val) 2229 { 2230 return ((val) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK; 2231 } 2232 #define A2XX_RB_COLORCONTROL_PIXEL_FOG 0x00010000 2233 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK 0x03000000 2234 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT 24 2235 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val) 2236 { 2237 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK; 2238 } 2239 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK 0x0c000000 2240 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT 26 2241 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val) 2242 { 2243 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK; 2244 } 2245 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK 0x30000000 2246 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT 28 2247 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val) 2248 { 2249 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK; 2250 } 2251 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK 0xc0000000 2252 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT 30 2253 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val) 2254 { 2255 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK; 2256 } 2257 2258 #define REG_A2XX_VGT_CURRENT_BIN_ID_MAX 0x00002203 2259 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK 0x00000007 2260 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT 0 2261 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val) 2262 { 2263 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK; 2264 } 2265 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK 0x00000038 2266 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT 3 2267 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val) 2268 { 2269 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK; 2270 } 2271 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK 0x000001c0 2272 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT 6 2273 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val) 2274 { 2275 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK; 2276 } 2277 2278 #define REG_A2XX_PA_CL_CLIP_CNTL 0x00002204 2279 #define A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 2280 #define A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA 0x00040000 2281 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK 0x00080000 2282 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT 19 2283 static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val) 2284 { 2285 return ((val) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK; 2286 } 2287 #define A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT 0x00100000 2288 #define A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR 0x00200000 2289 #define A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN 0x00400000 2290 #define A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN 0x00800000 2291 #define A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN 0x01000000 2292 2293 #define REG_A2XX_PA_SU_SC_MODE_CNTL 0x00002205 2294 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT 0x00000001 2295 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK 0x00000002 2296 #define A2XX_PA_SU_SC_MODE_CNTL_FACE 0x00000004 2297 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK 0x00000018 2298 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT 3 2299 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val) 2300 { 2301 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK; 2302 } 2303 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK 0x000000e0 2304 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT 5 2305 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 2306 { 2307 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK; 2308 } 2309 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK 0x00000700 2310 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT 8 2311 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 2312 { 2313 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK; 2314 } 2315 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE 0x00000800 2316 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE 0x00001000 2317 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE 0x00002000 2318 #define A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE 0x00008000 2319 #define A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE 0x00010000 2320 #define A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE 0x00040000 2321 #define A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST 0x00080000 2322 #define A2XX_PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS 0x00100000 2323 #define A2XX_PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA 0x00200000 2324 #define A2XX_PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE 0x00800000 2325 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI 0x02000000 2326 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000 2327 #define A2XX_PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS 0x10000000 2328 #define A2XX_PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS 0x20000000 2329 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE 0x40000000 2330 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE 0x80000000 2331 2332 #define REG_A2XX_PA_CL_VTE_CNTL 0x00002206 2333 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA 0x00000001 2334 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA 0x00000002 2335 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA 0x00000004 2336 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA 0x00000008 2337 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA 0x00000010 2338 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA 0x00000020 2339 #define A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT 0x00000100 2340 #define A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT 0x00000200 2341 #define A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT 0x00000400 2342 #define A2XX_PA_CL_VTE_CNTL_PERFCOUNTER_REF 0x00000800 2343 2344 #define REG_A2XX_VGT_CURRENT_BIN_ID_MIN 0x00002207 2345 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK 0x00000007 2346 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT 0 2347 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val) 2348 { 2349 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK; 2350 } 2351 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK 0x00000038 2352 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT 3 2353 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val) 2354 { 2355 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK; 2356 } 2357 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK 0x000001c0 2358 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT 6 2359 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val) 2360 { 2361 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK; 2362 } 2363 2364 #define REG_A2XX_RB_MODECONTROL 0x00002208 2365 #define A2XX_RB_MODECONTROL_EDRAM_MODE__MASK 0x00000007 2366 #define A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT 0 2367 static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val) 2368 { 2369 return ((val) << A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT) & A2XX_RB_MODECONTROL_EDRAM_MODE__MASK; 2370 } 2371 2372 #define REG_A2XX_A220_RB_LRZ_VSC_CONTROL 0x00002209 2373 2374 #define REG_A2XX_RB_SAMPLE_POS 0x0000220a 2375 2376 #define REG_A2XX_CLEAR_COLOR 0x0000220b 2377 #define A2XX_CLEAR_COLOR_RED__MASK 0x000000ff 2378 #define A2XX_CLEAR_COLOR_RED__SHIFT 0 2379 static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val) 2380 { 2381 return ((val) << A2XX_CLEAR_COLOR_RED__SHIFT) & A2XX_CLEAR_COLOR_RED__MASK; 2382 } 2383 #define A2XX_CLEAR_COLOR_GREEN__MASK 0x0000ff00 2384 #define A2XX_CLEAR_COLOR_GREEN__SHIFT 8 2385 static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val) 2386 { 2387 return ((val) << A2XX_CLEAR_COLOR_GREEN__SHIFT) & A2XX_CLEAR_COLOR_GREEN__MASK; 2388 } 2389 #define A2XX_CLEAR_COLOR_BLUE__MASK 0x00ff0000 2390 #define A2XX_CLEAR_COLOR_BLUE__SHIFT 16 2391 static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val) 2392 { 2393 return ((val) << A2XX_CLEAR_COLOR_BLUE__SHIFT) & A2XX_CLEAR_COLOR_BLUE__MASK; 2394 } 2395 #define A2XX_CLEAR_COLOR_ALPHA__MASK 0xff000000 2396 #define A2XX_CLEAR_COLOR_ALPHA__SHIFT 24 2397 static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val) 2398 { 2399 return ((val) << A2XX_CLEAR_COLOR_ALPHA__SHIFT) & A2XX_CLEAR_COLOR_ALPHA__MASK; 2400 } 2401 2402 #define REG_A2XX_A220_GRAS_CONTROL 0x00002210 2403 2404 #define REG_A2XX_PA_SU_POINT_SIZE 0x00002280 2405 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK 0x0000ffff 2406 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT 0 2407 static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val) 2408 { 2409 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK; 2410 } 2411 #define A2XX_PA_SU_POINT_SIZE_WIDTH__MASK 0xffff0000 2412 #define A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT 16 2413 static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val) 2414 { 2415 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK; 2416 } 2417 2418 #define REG_A2XX_PA_SU_POINT_MINMAX 0x00002281 2419 #define A2XX_PA_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 2420 #define A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT 0 2421 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val) 2422 { 2423 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK; 2424 } 2425 #define A2XX_PA_SU_POINT_MINMAX_MAX__MASK 0xffff0000 2426 #define A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT 16 2427 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val) 2428 { 2429 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK; 2430 } 2431 2432 #define REG_A2XX_PA_SU_LINE_CNTL 0x00002282 2433 #define A2XX_PA_SU_LINE_CNTL_WIDTH__MASK 0x0000ffff 2434 #define A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT 0 2435 static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val) 2436 { 2437 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK; 2438 } 2439 2440 #define REG_A2XX_PA_SC_LINE_STIPPLE 0x00002283 2441 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK 0x0000ffff 2442 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT 0 2443 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val) 2444 { 2445 return ((val) << A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK; 2446 } 2447 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK 0x00ff0000 2448 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT 16 2449 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val) 2450 { 2451 return ((val) << A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK; 2452 } 2453 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK 0x10000000 2454 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT 28 2455 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val) 2456 { 2457 return ((val) << A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK; 2458 } 2459 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK 0x60000000 2460 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT 29 2461 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val) 2462 { 2463 return ((val) << A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK; 2464 } 2465 2466 #define REG_A2XX_PA_SC_VIZ_QUERY 0x00002293 2467 #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ENA 0x00000001 2468 #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK 0x0000007e 2469 #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT 1 2470 static inline uint32_t A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID(uint32_t val) 2471 { 2472 return ((val) << A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT) & A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK; 2473 } 2474 #define A2XX_PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z 0x00000100 2475 2476 #define REG_A2XX_VGT_ENHANCE 0x00002294 2477 2478 #define REG_A2XX_PA_SC_LINE_CNTL 0x00002300 2479 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK 0x0000ffff 2480 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT 0 2481 static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val) 2482 { 2483 return ((val) << A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT) & A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK; 2484 } 2485 #define A2XX_PA_SC_LINE_CNTL_USE_BRES_CNTL 0x00000100 2486 #define A2XX_PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH 0x00000200 2487 #define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL 0x00000400 2488 2489 #define REG_A2XX_PA_SC_AA_CONFIG 0x00002301 2490 #define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK 0x00000007 2491 #define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT 0 2492 static inline uint32_t A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES(uint32_t val) 2493 { 2494 return ((val) << A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT) & A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK; 2495 } 2496 #define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK 0x0001e000 2497 #define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT 13 2498 static inline uint32_t A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST(uint32_t val) 2499 { 2500 return ((val) << A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT) & A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK; 2501 } 2502 2503 #define REG_A2XX_PA_SU_VTX_CNTL 0x00002302 2504 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK 0x00000001 2505 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT 0 2506 static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val) 2507 { 2508 return ((val) << A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT) & A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK; 2509 } 2510 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK 0x00000006 2511 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT 1 2512 static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val) 2513 { 2514 return ((val) << A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK; 2515 } 2516 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK 0x00000380 2517 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT 7 2518 static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val) 2519 { 2520 return ((val) << A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK; 2521 } 2522 2523 #define REG_A2XX_PA_CL_GB_VERT_CLIP_ADJ 0x00002303 2524 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK 0xffffffff 2525 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT 0 2526 static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val) 2527 { 2528 return ((fui(val)) << A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK; 2529 } 2530 2531 #define REG_A2XX_PA_CL_GB_VERT_DISC_ADJ 0x00002304 2532 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK 0xffffffff 2533 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT 0 2534 static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val) 2535 { 2536 return ((fui(val)) << A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK; 2537 } 2538 2539 #define REG_A2XX_PA_CL_GB_HORZ_CLIP_ADJ 0x00002305 2540 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK 0xffffffff 2541 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT 0 2542 static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val) 2543 { 2544 return ((fui(val)) << A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK; 2545 } 2546 2547 #define REG_A2XX_PA_CL_GB_HORZ_DISC_ADJ 0x00002306 2548 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK 0xffffffff 2549 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT 0 2550 static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val) 2551 { 2552 return ((fui(val)) << A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK; 2553 } 2554 2555 #define REG_A2XX_SQ_VS_CONST 0x00002307 2556 #define A2XX_SQ_VS_CONST_BASE__MASK 0x000001ff 2557 #define A2XX_SQ_VS_CONST_BASE__SHIFT 0 2558 static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val) 2559 { 2560 return ((val) << A2XX_SQ_VS_CONST_BASE__SHIFT) & A2XX_SQ_VS_CONST_BASE__MASK; 2561 } 2562 #define A2XX_SQ_VS_CONST_SIZE__MASK 0x001ff000 2563 #define A2XX_SQ_VS_CONST_SIZE__SHIFT 12 2564 static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val) 2565 { 2566 return ((val) << A2XX_SQ_VS_CONST_SIZE__SHIFT) & A2XX_SQ_VS_CONST_SIZE__MASK; 2567 } 2568 2569 #define REG_A2XX_SQ_PS_CONST 0x00002308 2570 #define A2XX_SQ_PS_CONST_BASE__MASK 0x000001ff 2571 #define A2XX_SQ_PS_CONST_BASE__SHIFT 0 2572 static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val) 2573 { 2574 return ((val) << A2XX_SQ_PS_CONST_BASE__SHIFT) & A2XX_SQ_PS_CONST_BASE__MASK; 2575 } 2576 #define A2XX_SQ_PS_CONST_SIZE__MASK 0x001ff000 2577 #define A2XX_SQ_PS_CONST_SIZE__SHIFT 12 2578 static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val) 2579 { 2580 return ((val) << A2XX_SQ_PS_CONST_SIZE__SHIFT) & A2XX_SQ_PS_CONST_SIZE__MASK; 2581 } 2582 2583 #define REG_A2XX_SQ_DEBUG_MISC_0 0x00002309 2584 2585 #define REG_A2XX_SQ_DEBUG_MISC_1 0x0000230a 2586 2587 #define REG_A2XX_PA_SC_AA_MASK 0x00002312 2588 2589 #define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL 0x00002316 2590 #define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK 0x00000007 2591 #define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT 0 2592 static inline uint32_t A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH(uint32_t val) 2593 { 2594 return ((val) << A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT) & A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK; 2595 } 2596 2597 #define REG_A2XX_VGT_OUT_DEALLOC_CNTL 0x00002317 2598 #define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK 0x00000003 2599 #define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT 0 2600 static inline uint32_t A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST(uint32_t val) 2601 { 2602 return ((val) << A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT) & A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK; 2603 } 2604 2605 #define REG_A2XX_RB_COPY_CONTROL 0x00002318 2606 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK 0x00000007 2607 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT 0 2608 static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val) 2609 { 2610 return ((val) << A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT) & A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK; 2611 } 2612 #define A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE 0x00000008 2613 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK 0x000000f0 2614 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT 4 2615 static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val) 2616 { 2617 return ((val) << A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT) & A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK; 2618 } 2619 2620 #define REG_A2XX_RB_COPY_DEST_BASE 0x00002319 2621 2622 #define REG_A2XX_RB_COPY_DEST_PITCH 0x0000231a 2623 #define A2XX_RB_COPY_DEST_PITCH__MASK 0xffffffff 2624 #define A2XX_RB_COPY_DEST_PITCH__SHIFT 0 2625 static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val) 2626 { 2627 return ((val >> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK; 2628 } 2629 2630 #define REG_A2XX_RB_COPY_DEST_INFO 0x0000231b 2631 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK 0x00000007 2632 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT 0 2633 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val) 2634 { 2635 return ((val) << A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT) & A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK; 2636 } 2637 #define A2XX_RB_COPY_DEST_INFO_LINEAR 0x00000008 2638 #define A2XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000f0 2639 #define A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 4 2640 static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val) 2641 { 2642 return ((val) << A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A2XX_RB_COPY_DEST_INFO_FORMAT__MASK; 2643 } 2644 #define A2XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 2645 #define A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 2646 static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val) 2647 { 2648 return ((val) << A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A2XX_RB_COPY_DEST_INFO_SWAP__MASK; 2649 } 2650 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 2651 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 2652 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 2653 { 2654 return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 2655 } 2656 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK 0x00003000 2657 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT 12 2658 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val) 2659 { 2660 return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK; 2661 } 2662 #define A2XX_RB_COPY_DEST_INFO_WRITE_RED 0x00004000 2663 #define A2XX_RB_COPY_DEST_INFO_WRITE_GREEN 0x00008000 2664 #define A2XX_RB_COPY_DEST_INFO_WRITE_BLUE 0x00010000 2665 #define A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA 0x00020000 2666 2667 #define REG_A2XX_RB_COPY_DEST_OFFSET 0x0000231c 2668 #define A2XX_RB_COPY_DEST_OFFSET_X__MASK 0x00001fff 2669 #define A2XX_RB_COPY_DEST_OFFSET_X__SHIFT 0 2670 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val) 2671 { 2672 return ((val) << A2XX_RB_COPY_DEST_OFFSET_X__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_X__MASK; 2673 } 2674 #define A2XX_RB_COPY_DEST_OFFSET_Y__MASK 0x03ffe000 2675 #define A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT 13 2676 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val) 2677 { 2678 return ((val) << A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_Y__MASK; 2679 } 2680 2681 #define REG_A2XX_RB_DEPTH_CLEAR 0x0000231d 2682 2683 #define REG_A2XX_RB_SAMPLE_COUNT_CTL 0x00002324 2684 2685 #define REG_A2XX_RB_COLOR_DEST_MASK 0x00002326 2686 2687 #define REG_A2XX_A225_GRAS_UCP0X 0x00002340 2688 2689 #define REG_A2XX_A225_GRAS_UCP5W 0x00002357 2690 2691 #define REG_A2XX_A225_GRAS_UCP_ENABLED 0x00002360 2692 2693 #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE 0x00002380 2694 2695 #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_OFFSET 0x00002381 2696 2697 #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_SCALE 0x00002382 2698 2699 #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET 0x00002383 2700 2701 #define REG_A2XX_SQ_CONSTANT_0 0x00004000 2702 2703 #define REG_A2XX_SQ_FETCH_0 0x00004800 2704 2705 #define REG_A2XX_SQ_CF_BOOLEANS 0x00004900 2706 2707 #define REG_A2XX_SQ_CF_LOOP 0x00004908 2708 2709 #define REG_A2XX_COHER_SIZE_PM4 0x00000a29 2710 2711 #define REG_A2XX_COHER_BASE_PM4 0x00000a2a 2712 2713 #define REG_A2XX_COHER_STATUS_PM4 0x00000a2b 2714 2715 #define REG_A2XX_PA_SU_PERFCOUNTER0_SELECT 0x00000c88 2716 2717 #define REG_A2XX_PA_SU_PERFCOUNTER1_SELECT 0x00000c89 2718 2719 #define REG_A2XX_PA_SU_PERFCOUNTER2_SELECT 0x00000c8a 2720 2721 #define REG_A2XX_PA_SU_PERFCOUNTER3_SELECT 0x00000c8b 2722 2723 #define REG_A2XX_PA_SU_PERFCOUNTER0_LOW 0x00000c8c 2724 2725 #define REG_A2XX_PA_SU_PERFCOUNTER0_HI 0x00000c8d 2726 2727 #define REG_A2XX_PA_SU_PERFCOUNTER1_LOW 0x00000c8e 2728 2729 #define REG_A2XX_PA_SU_PERFCOUNTER1_HI 0x00000c8f 2730 2731 #define REG_A2XX_PA_SU_PERFCOUNTER2_LOW 0x00000c90 2732 2733 #define REG_A2XX_PA_SU_PERFCOUNTER2_HI 0x00000c91 2734 2735 #define REG_A2XX_PA_SU_PERFCOUNTER3_LOW 0x00000c92 2736 2737 #define REG_A2XX_PA_SU_PERFCOUNTER3_HI 0x00000c93 2738 2739 #define REG_A2XX_PA_SC_PERFCOUNTER0_SELECT 0x00000c98 2740 2741 #define REG_A2XX_PA_SC_PERFCOUNTER0_LOW 0x00000c99 2742 2743 #define REG_A2XX_PA_SC_PERFCOUNTER0_HI 0x00000c9a 2744 2745 #define REG_A2XX_VGT_PERFCOUNTER0_SELECT 0x00000c48 2746 2747 #define REG_A2XX_VGT_PERFCOUNTER1_SELECT 0x00000c49 2748 2749 #define REG_A2XX_VGT_PERFCOUNTER2_SELECT 0x00000c4a 2750 2751 #define REG_A2XX_VGT_PERFCOUNTER3_SELECT 0x00000c4b 2752 2753 #define REG_A2XX_VGT_PERFCOUNTER0_LOW 0x00000c4c 2754 2755 #define REG_A2XX_VGT_PERFCOUNTER1_LOW 0x00000c4e 2756 2757 #define REG_A2XX_VGT_PERFCOUNTER2_LOW 0x00000c50 2758 2759 #define REG_A2XX_VGT_PERFCOUNTER3_LOW 0x00000c52 2760 2761 #define REG_A2XX_VGT_PERFCOUNTER0_HI 0x00000c4d 2762 2763 #define REG_A2XX_VGT_PERFCOUNTER1_HI 0x00000c4f 2764 2765 #define REG_A2XX_VGT_PERFCOUNTER2_HI 0x00000c51 2766 2767 #define REG_A2XX_VGT_PERFCOUNTER3_HI 0x00000c53 2768 2769 #define REG_A2XX_TCR_PERFCOUNTER0_SELECT 0x00000e05 2770 2771 #define REG_A2XX_TCR_PERFCOUNTER1_SELECT 0x00000e08 2772 2773 #define REG_A2XX_TCR_PERFCOUNTER0_HI 0x00000e06 2774 2775 #define REG_A2XX_TCR_PERFCOUNTER1_HI 0x00000e09 2776 2777 #define REG_A2XX_TCR_PERFCOUNTER0_LOW 0x00000e07 2778 2779 #define REG_A2XX_TCR_PERFCOUNTER1_LOW 0x00000e0a 2780 2781 #define REG_A2XX_TP0_PERFCOUNTER0_SELECT 0x00000e1f 2782 2783 #define REG_A2XX_TP0_PERFCOUNTER0_HI 0x00000e20 2784 2785 #define REG_A2XX_TP0_PERFCOUNTER0_LOW 0x00000e21 2786 2787 #define REG_A2XX_TP0_PERFCOUNTER1_SELECT 0x00000e22 2788 2789 #define REG_A2XX_TP0_PERFCOUNTER1_HI 0x00000e23 2790 2791 #define REG_A2XX_TP0_PERFCOUNTER1_LOW 0x00000e24 2792 2793 #define REG_A2XX_TCM_PERFCOUNTER0_SELECT 0x00000e54 2794 2795 #define REG_A2XX_TCM_PERFCOUNTER1_SELECT 0x00000e57 2796 2797 #define REG_A2XX_TCM_PERFCOUNTER0_HI 0x00000e55 2798 2799 #define REG_A2XX_TCM_PERFCOUNTER1_HI 0x00000e58 2800 2801 #define REG_A2XX_TCM_PERFCOUNTER0_LOW 0x00000e56 2802 2803 #define REG_A2XX_TCM_PERFCOUNTER1_LOW 0x00000e59 2804 2805 #define REG_A2XX_TCF_PERFCOUNTER0_SELECT 0x00000e5a 2806 2807 #define REG_A2XX_TCF_PERFCOUNTER1_SELECT 0x00000e5d 2808 2809 #define REG_A2XX_TCF_PERFCOUNTER2_SELECT 0x00000e60 2810 2811 #define REG_A2XX_TCF_PERFCOUNTER3_SELECT 0x00000e63 2812 2813 #define REG_A2XX_TCF_PERFCOUNTER4_SELECT 0x00000e66 2814 2815 #define REG_A2XX_TCF_PERFCOUNTER5_SELECT 0x00000e69 2816 2817 #define REG_A2XX_TCF_PERFCOUNTER6_SELECT 0x00000e6c 2818 2819 #define REG_A2XX_TCF_PERFCOUNTER7_SELECT 0x00000e6f 2820 2821 #define REG_A2XX_TCF_PERFCOUNTER8_SELECT 0x00000e72 2822 2823 #define REG_A2XX_TCF_PERFCOUNTER9_SELECT 0x00000e75 2824 2825 #define REG_A2XX_TCF_PERFCOUNTER10_SELECT 0x00000e78 2826 2827 #define REG_A2XX_TCF_PERFCOUNTER11_SELECT 0x00000e7b 2828 2829 #define REG_A2XX_TCF_PERFCOUNTER0_HI 0x00000e5b 2830 2831 #define REG_A2XX_TCF_PERFCOUNTER1_HI 0x00000e5e 2832 2833 #define REG_A2XX_TCF_PERFCOUNTER2_HI 0x00000e61 2834 2835 #define REG_A2XX_TCF_PERFCOUNTER3_HI 0x00000e64 2836 2837 #define REG_A2XX_TCF_PERFCOUNTER4_HI 0x00000e67 2838 2839 #define REG_A2XX_TCF_PERFCOUNTER5_HI 0x00000e6a 2840 2841 #define REG_A2XX_TCF_PERFCOUNTER6_HI 0x00000e6d 2842 2843 #define REG_A2XX_TCF_PERFCOUNTER7_HI 0x00000e70 2844 2845 #define REG_A2XX_TCF_PERFCOUNTER8_HI 0x00000e73 2846 2847 #define REG_A2XX_TCF_PERFCOUNTER9_HI 0x00000e76 2848 2849 #define REG_A2XX_TCF_PERFCOUNTER10_HI 0x00000e79 2850 2851 #define REG_A2XX_TCF_PERFCOUNTER11_HI 0x00000e7c 2852 2853 #define REG_A2XX_TCF_PERFCOUNTER0_LOW 0x00000e5c 2854 2855 #define REG_A2XX_TCF_PERFCOUNTER1_LOW 0x00000e5f 2856 2857 #define REG_A2XX_TCF_PERFCOUNTER2_LOW 0x00000e62 2858 2859 #define REG_A2XX_TCF_PERFCOUNTER3_LOW 0x00000e65 2860 2861 #define REG_A2XX_TCF_PERFCOUNTER4_LOW 0x00000e68 2862 2863 #define REG_A2XX_TCF_PERFCOUNTER5_LOW 0x00000e6b 2864 2865 #define REG_A2XX_TCF_PERFCOUNTER6_LOW 0x00000e6e 2866 2867 #define REG_A2XX_TCF_PERFCOUNTER7_LOW 0x00000e71 2868 2869 #define REG_A2XX_TCF_PERFCOUNTER8_LOW 0x00000e74 2870 2871 #define REG_A2XX_TCF_PERFCOUNTER9_LOW 0x00000e77 2872 2873 #define REG_A2XX_TCF_PERFCOUNTER10_LOW 0x00000e7a 2874 2875 #define REG_A2XX_TCF_PERFCOUNTER11_LOW 0x00000e7d 2876 2877 #define REG_A2XX_SQ_PERFCOUNTER0_SELECT 0x00000dc8 2878 2879 #define REG_A2XX_SQ_PERFCOUNTER1_SELECT 0x00000dc9 2880 2881 #define REG_A2XX_SQ_PERFCOUNTER2_SELECT 0x00000dca 2882 2883 #define REG_A2XX_SQ_PERFCOUNTER3_SELECT 0x00000dcb 2884 2885 #define REG_A2XX_SQ_PERFCOUNTER0_LOW 0x00000dcc 2886 2887 #define REG_A2XX_SQ_PERFCOUNTER0_HI 0x00000dcd 2888 2889 #define REG_A2XX_SQ_PERFCOUNTER1_LOW 0x00000dce 2890 2891 #define REG_A2XX_SQ_PERFCOUNTER1_HI 0x00000dcf 2892 2893 #define REG_A2XX_SQ_PERFCOUNTER2_LOW 0x00000dd0 2894 2895 #define REG_A2XX_SQ_PERFCOUNTER2_HI 0x00000dd1 2896 2897 #define REG_A2XX_SQ_PERFCOUNTER3_LOW 0x00000dd2 2898 2899 #define REG_A2XX_SQ_PERFCOUNTER3_HI 0x00000dd3 2900 2901 #define REG_A2XX_SX_PERFCOUNTER0_SELECT 0x00000dd4 2902 2903 #define REG_A2XX_SX_PERFCOUNTER0_LOW 0x00000dd8 2904 2905 #define REG_A2XX_SX_PERFCOUNTER0_HI 0x00000dd9 2906 2907 #define REG_A2XX_MH_PERFCOUNTER0_SELECT 0x00000a46 2908 2909 #define REG_A2XX_MH_PERFCOUNTER1_SELECT 0x00000a4a 2910 2911 #define REG_A2XX_MH_PERFCOUNTER0_CONFIG 0x00000a47 2912 2913 #define REG_A2XX_MH_PERFCOUNTER1_CONFIG 0x00000a4b 2914 2915 #define REG_A2XX_MH_PERFCOUNTER0_LOW 0x00000a48 2916 2917 #define REG_A2XX_MH_PERFCOUNTER1_LOW 0x00000a4c 2918 2919 #define REG_A2XX_MH_PERFCOUNTER0_HI 0x00000a49 2920 2921 #define REG_A2XX_MH_PERFCOUNTER1_HI 0x00000a4d 2922 2923 #define REG_A2XX_RB_PERFCOUNTER0_SELECT 0x00000f04 2924 2925 #define REG_A2XX_RB_PERFCOUNTER0_LOW 0x00000f08 2926 2927 #define REG_A2XX_RB_PERFCOUNTER0_HI 0x00000f09 2928 2929 #define REG_A2XX_SQ_TEX_0 0x00000000 2930 #define A2XX_SQ_TEX_0_TYPE__MASK 0x00000003 2931 #define A2XX_SQ_TEX_0_TYPE__SHIFT 0 2932 static inline uint32_t A2XX_SQ_TEX_0_TYPE(enum sq_tex_type val) 2933 { 2934 return ((val) << A2XX_SQ_TEX_0_TYPE__SHIFT) & A2XX_SQ_TEX_0_TYPE__MASK; 2935 } 2936 #define A2XX_SQ_TEX_0_SIGN_X__MASK 0x0000000c 2937 #define A2XX_SQ_TEX_0_SIGN_X__SHIFT 2 2938 static inline uint32_t A2XX_SQ_TEX_0_SIGN_X(enum sq_tex_sign val) 2939 { 2940 return ((val) << A2XX_SQ_TEX_0_SIGN_X__SHIFT) & A2XX_SQ_TEX_0_SIGN_X__MASK; 2941 } 2942 #define A2XX_SQ_TEX_0_SIGN_Y__MASK 0x00000030 2943 #define A2XX_SQ_TEX_0_SIGN_Y__SHIFT 4 2944 static inline uint32_t A2XX_SQ_TEX_0_SIGN_Y(enum sq_tex_sign val) 2945 { 2946 return ((val) << A2XX_SQ_TEX_0_SIGN_Y__SHIFT) & A2XX_SQ_TEX_0_SIGN_Y__MASK; 2947 } 2948 #define A2XX_SQ_TEX_0_SIGN_Z__MASK 0x000000c0 2949 #define A2XX_SQ_TEX_0_SIGN_Z__SHIFT 6 2950 static inline uint32_t A2XX_SQ_TEX_0_SIGN_Z(enum sq_tex_sign val) 2951 { 2952 return ((val) << A2XX_SQ_TEX_0_SIGN_Z__SHIFT) & A2XX_SQ_TEX_0_SIGN_Z__MASK; 2953 } 2954 #define A2XX_SQ_TEX_0_SIGN_W__MASK 0x00000300 2955 #define A2XX_SQ_TEX_0_SIGN_W__SHIFT 8 2956 static inline uint32_t A2XX_SQ_TEX_0_SIGN_W(enum sq_tex_sign val) 2957 { 2958 return ((val) << A2XX_SQ_TEX_0_SIGN_W__SHIFT) & A2XX_SQ_TEX_0_SIGN_W__MASK; 2959 } 2960 #define A2XX_SQ_TEX_0_CLAMP_X__MASK 0x00001c00 2961 #define A2XX_SQ_TEX_0_CLAMP_X__SHIFT 10 2962 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val) 2963 { 2964 return ((val) << A2XX_SQ_TEX_0_CLAMP_X__SHIFT) & A2XX_SQ_TEX_0_CLAMP_X__MASK; 2965 } 2966 #define A2XX_SQ_TEX_0_CLAMP_Y__MASK 0x0000e000 2967 #define A2XX_SQ_TEX_0_CLAMP_Y__SHIFT 13 2968 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val) 2969 { 2970 return ((val) << A2XX_SQ_TEX_0_CLAMP_Y__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Y__MASK; 2971 } 2972 #define A2XX_SQ_TEX_0_CLAMP_Z__MASK 0x00070000 2973 #define A2XX_SQ_TEX_0_CLAMP_Z__SHIFT 16 2974 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val) 2975 { 2976 return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK; 2977 } 2978 #define A2XX_SQ_TEX_0_PITCH__MASK 0x7fc00000 2979 #define A2XX_SQ_TEX_0_PITCH__SHIFT 22 2980 static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val) 2981 { 2982 return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK; 2983 } 2984 #define A2XX_SQ_TEX_0_TILED 0x80000000 2985 2986 #define REG_A2XX_SQ_TEX_1 0x00000001 2987 #define A2XX_SQ_TEX_1_FORMAT__MASK 0x0000003f 2988 #define A2XX_SQ_TEX_1_FORMAT__SHIFT 0 2989 static inline uint32_t A2XX_SQ_TEX_1_FORMAT(enum a2xx_sq_surfaceformat val) 2990 { 2991 return ((val) << A2XX_SQ_TEX_1_FORMAT__SHIFT) & A2XX_SQ_TEX_1_FORMAT__MASK; 2992 } 2993 #define A2XX_SQ_TEX_1_ENDIANNESS__MASK 0x000000c0 2994 #define A2XX_SQ_TEX_1_ENDIANNESS__SHIFT 6 2995 static inline uint32_t A2XX_SQ_TEX_1_ENDIANNESS(enum sq_tex_endian val) 2996 { 2997 return ((val) << A2XX_SQ_TEX_1_ENDIANNESS__SHIFT) & A2XX_SQ_TEX_1_ENDIANNESS__MASK; 2998 } 2999 #define A2XX_SQ_TEX_1_REQUEST_SIZE__MASK 0x00000300 3000 #define A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT 8 3001 static inline uint32_t A2XX_SQ_TEX_1_REQUEST_SIZE(uint32_t val) 3002 { 3003 return ((val) << A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT) & A2XX_SQ_TEX_1_REQUEST_SIZE__MASK; 3004 } 3005 #define A2XX_SQ_TEX_1_STACKED 0x00000400 3006 #define A2XX_SQ_TEX_1_CLAMP_POLICY__MASK 0x00000800 3007 #define A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT 11 3008 static inline uint32_t A2XX_SQ_TEX_1_CLAMP_POLICY(enum sq_tex_clamp_policy val) 3009 { 3010 return ((val) << A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT) & A2XX_SQ_TEX_1_CLAMP_POLICY__MASK; 3011 } 3012 #define A2XX_SQ_TEX_1_BASE_ADDRESS__MASK 0xfffff000 3013 #define A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT 12 3014 static inline uint32_t A2XX_SQ_TEX_1_BASE_ADDRESS(uint32_t val) 3015 { 3016 return ((val >> 12) << A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT) & A2XX_SQ_TEX_1_BASE_ADDRESS__MASK; 3017 } 3018 3019 #define REG_A2XX_SQ_TEX_2 0x00000002 3020 #define A2XX_SQ_TEX_2_WIDTH__MASK 0x00001fff 3021 #define A2XX_SQ_TEX_2_WIDTH__SHIFT 0 3022 static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val) 3023 { 3024 return ((val) << A2XX_SQ_TEX_2_WIDTH__SHIFT) & A2XX_SQ_TEX_2_WIDTH__MASK; 3025 } 3026 #define A2XX_SQ_TEX_2_HEIGHT__MASK 0x03ffe000 3027 #define A2XX_SQ_TEX_2_HEIGHT__SHIFT 13 3028 static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val) 3029 { 3030 return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK; 3031 } 3032 #define A2XX_SQ_TEX_2_DEPTH__MASK 0xfc000000 3033 #define A2XX_SQ_TEX_2_DEPTH__SHIFT 26 3034 static inline uint32_t A2XX_SQ_TEX_2_DEPTH(uint32_t val) 3035 { 3036 return ((val) << A2XX_SQ_TEX_2_DEPTH__SHIFT) & A2XX_SQ_TEX_2_DEPTH__MASK; 3037 } 3038 3039 #define REG_A2XX_SQ_TEX_3 0x00000003 3040 #define A2XX_SQ_TEX_3_NUM_FORMAT__MASK 0x00000001 3041 #define A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT 0 3042 static inline uint32_t A2XX_SQ_TEX_3_NUM_FORMAT(enum sq_tex_num_format val) 3043 { 3044 return ((val) << A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT) & A2XX_SQ_TEX_3_NUM_FORMAT__MASK; 3045 } 3046 #define A2XX_SQ_TEX_3_SWIZ_X__MASK 0x0000000e 3047 #define A2XX_SQ_TEX_3_SWIZ_X__SHIFT 1 3048 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val) 3049 { 3050 return ((val) << A2XX_SQ_TEX_3_SWIZ_X__SHIFT) & A2XX_SQ_TEX_3_SWIZ_X__MASK; 3051 } 3052 #define A2XX_SQ_TEX_3_SWIZ_Y__MASK 0x00000070 3053 #define A2XX_SQ_TEX_3_SWIZ_Y__SHIFT 4 3054 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val) 3055 { 3056 return ((val) << A2XX_SQ_TEX_3_SWIZ_Y__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Y__MASK; 3057 } 3058 #define A2XX_SQ_TEX_3_SWIZ_Z__MASK 0x00000380 3059 #define A2XX_SQ_TEX_3_SWIZ_Z__SHIFT 7 3060 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val) 3061 { 3062 return ((val) << A2XX_SQ_TEX_3_SWIZ_Z__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Z__MASK; 3063 } 3064 #define A2XX_SQ_TEX_3_SWIZ_W__MASK 0x00001c00 3065 #define A2XX_SQ_TEX_3_SWIZ_W__SHIFT 10 3066 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val) 3067 { 3068 return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK; 3069 } 3070 #define A2XX_SQ_TEX_3_EXP_ADJUST__MASK 0x0007e000 3071 #define A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT 13 3072 static inline uint32_t A2XX_SQ_TEX_3_EXP_ADJUST(int32_t val) 3073 { 3074 return ((val) << A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT) & A2XX_SQ_TEX_3_EXP_ADJUST__MASK; 3075 } 3076 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK 0x00180000 3077 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT 19 3078 static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val) 3079 { 3080 return ((val) << A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK; 3081 } 3082 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK 0x00600000 3083 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT 21 3084 static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val) 3085 { 3086 return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK; 3087 } 3088 #define A2XX_SQ_TEX_3_MIP_FILTER__MASK 0x01800000 3089 #define A2XX_SQ_TEX_3_MIP_FILTER__SHIFT 23 3090 static inline uint32_t A2XX_SQ_TEX_3_MIP_FILTER(enum sq_tex_filter val) 3091 { 3092 return ((val) << A2XX_SQ_TEX_3_MIP_FILTER__SHIFT) & A2XX_SQ_TEX_3_MIP_FILTER__MASK; 3093 } 3094 #define A2XX_SQ_TEX_3_ANISO_FILTER__MASK 0x0e000000 3095 #define A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT 25 3096 static inline uint32_t A2XX_SQ_TEX_3_ANISO_FILTER(enum sq_tex_aniso_filter val) 3097 { 3098 return ((val) << A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT) & A2XX_SQ_TEX_3_ANISO_FILTER__MASK; 3099 } 3100 #define A2XX_SQ_TEX_3_BORDER_SIZE__MASK 0x80000000 3101 #define A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT 31 3102 static inline uint32_t A2XX_SQ_TEX_3_BORDER_SIZE(uint32_t val) 3103 { 3104 return ((val) << A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT) & A2XX_SQ_TEX_3_BORDER_SIZE__MASK; 3105 } 3106 3107 #define REG_A2XX_SQ_TEX_4 0x00000004 3108 #define A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK 0x00000001 3109 #define A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT 0 3110 static inline uint32_t A2XX_SQ_TEX_4_VOL_MAG_FILTER(enum sq_tex_filter val) 3111 { 3112 return ((val) << A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK; 3113 } 3114 #define A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK 0x00000002 3115 #define A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT 1 3116 static inline uint32_t A2XX_SQ_TEX_4_VOL_MIN_FILTER(enum sq_tex_filter val) 3117 { 3118 return ((val) << A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK; 3119 } 3120 #define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK 0x0000003c 3121 #define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT 2 3122 static inline uint32_t A2XX_SQ_TEX_4_MIP_MIN_LEVEL(uint32_t val) 3123 { 3124 return ((val) << A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT) & A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK; 3125 } 3126 #define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK 0x000003c0 3127 #define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT 6 3128 static inline uint32_t A2XX_SQ_TEX_4_MIP_MAX_LEVEL(uint32_t val) 3129 { 3130 return ((val) << A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT) & A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK; 3131 } 3132 #define A2XX_SQ_TEX_4_MAX_ANISO_WALK 0x00000400 3133 #define A2XX_SQ_TEX_4_MIN_ANISO_WALK 0x00000800 3134 #define A2XX_SQ_TEX_4_LOD_BIAS__MASK 0x003ff000 3135 #define A2XX_SQ_TEX_4_LOD_BIAS__SHIFT 12 3136 static inline uint32_t A2XX_SQ_TEX_4_LOD_BIAS(float val) 3137 { 3138 return ((((int32_t)(val * 32.0))) << A2XX_SQ_TEX_4_LOD_BIAS__SHIFT) & A2XX_SQ_TEX_4_LOD_BIAS__MASK; 3139 } 3140 #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK 0x07c00000 3141 #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT 22 3142 static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H(uint32_t val) 3143 { 3144 return ((val) << A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT) & A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK; 3145 } 3146 #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK 0xf8000000 3147 #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT 27 3148 static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V(uint32_t val) 3149 { 3150 return ((val) << A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT) & A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK; 3151 } 3152 3153 #define REG_A2XX_SQ_TEX_5 0x00000005 3154 #define A2XX_SQ_TEX_5_BORDER_COLOR__MASK 0x00000003 3155 #define A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT 0 3156 static inline uint32_t A2XX_SQ_TEX_5_BORDER_COLOR(enum sq_tex_border_color val) 3157 { 3158 return ((val) << A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT) & A2XX_SQ_TEX_5_BORDER_COLOR__MASK; 3159 } 3160 #define A2XX_SQ_TEX_5_FORCE_BCW_MAX 0x00000004 3161 #define A2XX_SQ_TEX_5_TRI_CLAMP__MASK 0x00000018 3162 #define A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT 3 3163 static inline uint32_t A2XX_SQ_TEX_5_TRI_CLAMP(uint32_t val) 3164 { 3165 return ((val) << A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT) & A2XX_SQ_TEX_5_TRI_CLAMP__MASK; 3166 } 3167 #define A2XX_SQ_TEX_5_ANISO_BIAS__MASK 0x000001e0 3168 #define A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT 5 3169 static inline uint32_t A2XX_SQ_TEX_5_ANISO_BIAS(float val) 3170 { 3171 return ((((int32_t)(val * 1.0))) << A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT) & A2XX_SQ_TEX_5_ANISO_BIAS__MASK; 3172 } 3173 #define A2XX_SQ_TEX_5_DIMENSION__MASK 0x00000600 3174 #define A2XX_SQ_TEX_5_DIMENSION__SHIFT 9 3175 static inline uint32_t A2XX_SQ_TEX_5_DIMENSION(enum sq_tex_dimension val) 3176 { 3177 return ((val) << A2XX_SQ_TEX_5_DIMENSION__SHIFT) & A2XX_SQ_TEX_5_DIMENSION__MASK; 3178 } 3179 #define A2XX_SQ_TEX_5_PACKED_MIPS 0x00000800 3180 #define A2XX_SQ_TEX_5_MIP_ADDRESS__MASK 0xfffff000 3181 #define A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT 12 3182 static inline uint32_t A2XX_SQ_TEX_5_MIP_ADDRESS(uint32_t val) 3183 { 3184 return ((val >> 12) << A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT) & A2XX_SQ_TEX_5_MIP_ADDRESS__MASK; 3185 } 3186 3187 3188 #endif /* A2XX_XML */ 3189