1 #ifndef A2XX_XML 2 #define A2XX_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32814 bytes, from 2013-11-30 15:07:33) 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 8900 bytes, from 2013-10-22 23:57:49) 15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 10574 bytes, from 2013-11-13 05:44:45) 16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 53644 bytes, from 2013-11-30 15:07:33) 17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 8344 bytes, from 2013-11-30 14:49:47) 18 19 Copyright (C) 2013 by the following authors: 20 - Rob Clark <robdclark@gmail.com> (robclark) 21 22 Permission is hereby granted, free of charge, to any person obtaining 23 a copy of this software and associated documentation files (the 24 "Software"), to deal in the Software without restriction, including 25 without limitation the rights to use, copy, modify, merge, publish, 26 distribute, sublicense, and/or sell copies of the Software, and to 27 permit persons to whom the Software is furnished to do so, subject to 28 the following conditions: 29 30 The above copyright notice and this permission notice (including the 31 next paragraph) shall be included in all copies or substantial 32 portions of the Software. 33 34 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 36 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 37 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 38 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 39 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 40 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43 44 enum a2xx_rb_dither_type { 45 DITHER_PIXEL = 0, 46 DITHER_SUBPIXEL = 1, 47 }; 48 49 enum a2xx_colorformatx { 50 COLORX_4_4_4_4 = 0, 51 COLORX_1_5_5_5 = 1, 52 COLORX_5_6_5 = 2, 53 COLORX_8 = 3, 54 COLORX_8_8 = 4, 55 COLORX_8_8_8_8 = 5, 56 COLORX_S8_8_8_8 = 6, 57 COLORX_16_FLOAT = 7, 58 COLORX_16_16_FLOAT = 8, 59 COLORX_16_16_16_16_FLOAT = 9, 60 COLORX_32_FLOAT = 10, 61 COLORX_32_32_FLOAT = 11, 62 COLORX_32_32_32_32_FLOAT = 12, 63 COLORX_2_3_3 = 13, 64 COLORX_8_8_8 = 14, 65 }; 66 67 enum a2xx_sq_surfaceformat { 68 FMT_1_REVERSE = 0, 69 FMT_1 = 1, 70 FMT_8 = 2, 71 FMT_1_5_5_5 = 3, 72 FMT_5_6_5 = 4, 73 FMT_6_5_5 = 5, 74 FMT_8_8_8_8 = 6, 75 FMT_2_10_10_10 = 7, 76 FMT_8_A = 8, 77 FMT_8_B = 9, 78 FMT_8_8 = 10, 79 FMT_Cr_Y1_Cb_Y0 = 11, 80 FMT_Y1_Cr_Y0_Cb = 12, 81 FMT_5_5_5_1 = 13, 82 FMT_8_8_8_8_A = 14, 83 FMT_4_4_4_4 = 15, 84 FMT_10_11_11 = 16, 85 FMT_11_11_10 = 17, 86 FMT_DXT1 = 18, 87 FMT_DXT2_3 = 19, 88 FMT_DXT4_5 = 20, 89 FMT_24_8 = 22, 90 FMT_24_8_FLOAT = 23, 91 FMT_16 = 24, 92 FMT_16_16 = 25, 93 FMT_16_16_16_16 = 26, 94 FMT_16_EXPAND = 27, 95 FMT_16_16_EXPAND = 28, 96 FMT_16_16_16_16_EXPAND = 29, 97 FMT_16_FLOAT = 30, 98 FMT_16_16_FLOAT = 31, 99 FMT_16_16_16_16_FLOAT = 32, 100 FMT_32 = 33, 101 FMT_32_32 = 34, 102 FMT_32_32_32_32 = 35, 103 FMT_32_FLOAT = 36, 104 FMT_32_32_FLOAT = 37, 105 FMT_32_32_32_32_FLOAT = 38, 106 FMT_32_AS_8 = 39, 107 FMT_32_AS_8_8 = 40, 108 FMT_16_MPEG = 41, 109 FMT_16_16_MPEG = 42, 110 FMT_8_INTERLACED = 43, 111 FMT_32_AS_8_INTERLACED = 44, 112 FMT_32_AS_8_8_INTERLACED = 45, 113 FMT_16_INTERLACED = 46, 114 FMT_16_MPEG_INTERLACED = 47, 115 FMT_16_16_MPEG_INTERLACED = 48, 116 FMT_DXN = 49, 117 FMT_8_8_8_8_AS_16_16_16_16 = 50, 118 FMT_DXT1_AS_16_16_16_16 = 51, 119 FMT_DXT2_3_AS_16_16_16_16 = 52, 120 FMT_DXT4_5_AS_16_16_16_16 = 53, 121 FMT_2_10_10_10_AS_16_16_16_16 = 54, 122 FMT_10_11_11_AS_16_16_16_16 = 55, 123 FMT_11_11_10_AS_16_16_16_16 = 56, 124 FMT_32_32_32_FLOAT = 57, 125 FMT_DXT3A = 58, 126 FMT_DXT5A = 59, 127 FMT_CTX1 = 60, 128 FMT_DXT3A_AS_1_1_1_1 = 61, 129 }; 130 131 enum a2xx_sq_ps_vtx_mode { 132 POSITION_1_VECTOR = 0, 133 POSITION_2_VECTORS_UNUSED = 1, 134 POSITION_2_VECTORS_SPRITE = 2, 135 POSITION_2_VECTORS_EDGE = 3, 136 POSITION_2_VECTORS_KILL = 4, 137 POSITION_2_VECTORS_SPRITE_KILL = 5, 138 POSITION_2_VECTORS_EDGE_KILL = 6, 139 MULTIPASS = 7, 140 }; 141 142 enum a2xx_sq_sample_cntl { 143 CENTROIDS_ONLY = 0, 144 CENTERS_ONLY = 1, 145 CENTROIDS_AND_CENTERS = 2, 146 }; 147 148 enum a2xx_dx_clip_space { 149 DXCLIP_OPENGL = 0, 150 DXCLIP_DIRECTX = 1, 151 }; 152 153 enum a2xx_pa_su_sc_polymode { 154 POLY_DISABLED = 0, 155 POLY_DUALMODE = 1, 156 }; 157 158 enum a2xx_rb_edram_mode { 159 EDRAM_NOP = 0, 160 COLOR_DEPTH = 4, 161 DEPTH_ONLY = 5, 162 EDRAM_COPY = 6, 163 }; 164 165 enum a2xx_pa_sc_pattern_bit_order { 166 LITTLE = 0, 167 BIG = 1, 168 }; 169 170 enum a2xx_pa_sc_auto_reset_cntl { 171 NEVER = 0, 172 EACH_PRIMITIVE = 1, 173 EACH_PACKET = 2, 174 }; 175 176 enum a2xx_pa_pixcenter { 177 PIXCENTER_D3D = 0, 178 PIXCENTER_OGL = 1, 179 }; 180 181 enum a2xx_pa_roundmode { 182 TRUNCATE = 0, 183 ROUND = 1, 184 ROUNDTOEVEN = 2, 185 ROUNDTOODD = 3, 186 }; 187 188 enum a2xx_pa_quantmode { 189 ONE_SIXTEENTH = 0, 190 ONE_EIGTH = 1, 191 ONE_QUARTER = 2, 192 ONE_HALF = 3, 193 ONE = 4, 194 }; 195 196 enum a2xx_rb_copy_sample_select { 197 SAMPLE_0 = 0, 198 SAMPLE_1 = 1, 199 SAMPLE_2 = 2, 200 SAMPLE_3 = 3, 201 SAMPLE_01 = 4, 202 SAMPLE_23 = 5, 203 SAMPLE_0123 = 6, 204 }; 205 206 enum adreno_mmu_clnt_beh { 207 BEH_NEVR = 0, 208 BEH_TRAN_RNG = 1, 209 BEH_TRAN_FLT = 2, 210 }; 211 212 enum sq_tex_clamp { 213 SQ_TEX_WRAP = 0, 214 SQ_TEX_MIRROR = 1, 215 SQ_TEX_CLAMP_LAST_TEXEL = 2, 216 SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3, 217 SQ_TEX_CLAMP_HALF_BORDER = 4, 218 SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5, 219 SQ_TEX_CLAMP_BORDER = 6, 220 SQ_TEX_MIRROR_ONCE_BORDER = 7, 221 }; 222 223 enum sq_tex_swiz { 224 SQ_TEX_X = 0, 225 SQ_TEX_Y = 1, 226 SQ_TEX_Z = 2, 227 SQ_TEX_W = 3, 228 SQ_TEX_ZERO = 4, 229 SQ_TEX_ONE = 5, 230 }; 231 232 enum sq_tex_filter { 233 SQ_TEX_FILTER_POINT = 0, 234 SQ_TEX_FILTER_BILINEAR = 1, 235 SQ_TEX_FILTER_BICUBIC = 2, 236 }; 237 238 #define REG_A2XX_RBBM_PATCH_RELEASE 0x00000001 239 240 #define REG_A2XX_RBBM_CNTL 0x0000003b 241 242 #define REG_A2XX_RBBM_SOFT_RESET 0x0000003c 243 244 #define REG_A2XX_CP_PFP_UCODE_ADDR 0x000000c0 245 246 #define REG_A2XX_CP_PFP_UCODE_DATA 0x000000c1 247 248 #define REG_A2XX_MH_MMU_CONFIG 0x00000040 249 #define A2XX_MH_MMU_CONFIG_MMU_ENABLE 0x00000001 250 #define A2XX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE 0x00000002 251 #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK 0x00000030 252 #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT 4 253 static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 254 { 255 return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK; 256 } 257 #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK 0x000000c0 258 #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT 6 259 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 260 { 261 return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK; 262 } 263 #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK 0x00000300 264 #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT 8 265 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 266 { 267 return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK; 268 } 269 #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK 0x00000c00 270 #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT 10 271 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 272 { 273 return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK; 274 } 275 #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK 0x00003000 276 #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT 12 277 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 278 { 279 return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK; 280 } 281 #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK 0x0000c000 282 #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT 14 283 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 284 { 285 return ((val) << A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK; 286 } 287 #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK 0x00030000 288 #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT 16 289 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 290 { 291 return ((val) << A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK; 292 } 293 #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK 0x000c0000 294 #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT 18 295 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 296 { 297 return ((val) << A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK; 298 } 299 #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK 0x00300000 300 #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT 20 301 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 302 { 303 return ((val) << A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK; 304 } 305 #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK 0x00c00000 306 #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT 22 307 static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 308 { 309 return ((val) << A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK; 310 } 311 #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK 0x03000000 312 #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT 24 313 static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 314 { 315 return ((val) << A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK; 316 } 317 318 #define REG_A2XX_MH_MMU_VA_RANGE 0x00000041 319 320 #define REG_A2XX_MH_MMU_PT_BASE 0x00000042 321 322 #define REG_A2XX_MH_MMU_PAGE_FAULT 0x00000043 323 324 #define REG_A2XX_MH_MMU_TRAN_ERROR 0x00000044 325 326 #define REG_A2XX_MH_MMU_INVALIDATE 0x00000045 327 328 #define REG_A2XX_MH_MMU_MPU_BASE 0x00000046 329 330 #define REG_A2XX_MH_MMU_MPU_END 0x00000047 331 332 #define REG_A2XX_NQWAIT_UNTIL 0x00000394 333 334 #define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395 335 336 #define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397 337 338 #define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x00000398 339 340 #define REG_A2XX_RBBM_DEBUG 0x0000039b 341 342 #define REG_A2XX_RBBM_PM_OVERRIDE1 0x0000039c 343 344 #define REG_A2XX_RBBM_PM_OVERRIDE2 0x0000039d 345 346 #define REG_A2XX_RBBM_DEBUG_OUT 0x000003a0 347 348 #define REG_A2XX_RBBM_DEBUG_CNTL 0x000003a1 349 350 #define REG_A2XX_RBBM_READ_ERROR 0x000003b3 351 352 #define REG_A2XX_RBBM_INT_CNTL 0x000003b4 353 354 #define REG_A2XX_RBBM_INT_STATUS 0x000003b5 355 356 #define REG_A2XX_RBBM_INT_ACK 0x000003b6 357 358 #define REG_A2XX_MASTER_INT_SIGNAL 0x000003b7 359 360 #define REG_A2XX_RBBM_PERIPHID1 0x000003f9 361 362 #define REG_A2XX_RBBM_PERIPHID2 0x000003fa 363 364 #define REG_A2XX_CP_PERFMON_CNTL 0x00000444 365 366 #define REG_A2XX_CP_PERFCOUNTER_SELECT 0x00000445 367 368 #define REG_A2XX_CP_PERFCOUNTER_LO 0x00000446 369 370 #define REG_A2XX_CP_PERFCOUNTER_HI 0x00000447 371 372 #define REG_A2XX_RBBM_STATUS 0x000005d0 373 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK 0x0000001f 374 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT 0 375 static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val) 376 { 377 return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK; 378 } 379 #define A2XX_RBBM_STATUS_TC_BUSY 0x00000020 380 #define A2XX_RBBM_STATUS_HIRQ_PENDING 0x00000100 381 #define A2XX_RBBM_STATUS_CPRQ_PENDING 0x00000200 382 #define A2XX_RBBM_STATUS_CFRQ_PENDING 0x00000400 383 #define A2XX_RBBM_STATUS_PFRQ_PENDING 0x00000800 384 #define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA 0x00001000 385 #define A2XX_RBBM_STATUS_RBBM_WU_BUSY 0x00004000 386 #define A2XX_RBBM_STATUS_CP_NRT_BUSY 0x00010000 387 #define A2XX_RBBM_STATUS_MH_BUSY 0x00040000 388 #define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY 0x00080000 389 #define A2XX_RBBM_STATUS_SX_BUSY 0x00200000 390 #define A2XX_RBBM_STATUS_TPC_BUSY 0x00400000 391 #define A2XX_RBBM_STATUS_SC_CNTX_BUSY 0x01000000 392 #define A2XX_RBBM_STATUS_PA_BUSY 0x02000000 393 #define A2XX_RBBM_STATUS_VGT_BUSY 0x04000000 394 #define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY 0x08000000 395 #define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY 0x10000000 396 #define A2XX_RBBM_STATUS_RB_CNTX_BUSY 0x40000000 397 #define A2XX_RBBM_STATUS_GUI_ACTIVE 0x80000000 398 399 #define REG_A2XX_MH_ARBITER_CONFIG 0x00000a40 400 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK 0x0000003f 401 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT 0 402 static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val) 403 { 404 return ((val) << A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK; 405 } 406 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY 0x00000040 407 #define A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE 0x00000080 408 #define A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE 0x00000100 409 #define A2XX_MH_ARBITER_CONFIG_L2_ARB_CONTROL 0x00000200 410 #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK 0x00001c00 411 #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT 10 412 static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val) 413 { 414 return ((val) << A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT) & A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK; 415 } 416 #define A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00002000 417 #define A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE 0x00004000 418 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE 0x00008000 419 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK 0x003f0000 420 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT 16 421 static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val) 422 { 423 return ((val) << A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK; 424 } 425 #define A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE 0x00400000 426 #define A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE 0x00800000 427 #define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE 0x01000000 428 #define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE 0x02000000 429 #define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE 0x04000000 430 431 #define REG_A2XX_A220_VSC_BIN_SIZE 0x00000c01 432 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 433 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT 0 434 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val) 435 { 436 return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK; 437 } 438 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 439 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT 5 440 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val) 441 { 442 return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK; 443 } 444 445 static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 446 447 static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 448 449 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } 450 451 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } 452 453 #define REG_A2XX_PC_DEBUG_CNTL 0x00000c38 454 455 #define REG_A2XX_PC_DEBUG_DATA 0x00000c39 456 457 #define REG_A2XX_PA_SC_VIZ_QUERY_STATUS 0x00000c44 458 459 #define REG_A2XX_GRAS_DEBUG_CNTL 0x00000c80 460 461 #define REG_A2XX_PA_SU_DEBUG_CNTL 0x00000c80 462 463 #define REG_A2XX_GRAS_DEBUG_DATA 0x00000c81 464 465 #define REG_A2XX_PA_SU_DEBUG_DATA 0x00000c81 466 467 #define REG_A2XX_PA_SU_FACE_DATA 0x00000c86 468 469 #define REG_A2XX_SQ_GPR_MANAGEMENT 0x00000d00 470 471 #define REG_A2XX_SQ_FLOW_CONTROL 0x00000d01 472 473 #define REG_A2XX_SQ_INST_STORE_MANAGMENT 0x00000d02 474 475 #define REG_A2XX_SQ_DEBUG_MISC 0x00000d05 476 477 #define REG_A2XX_SQ_INT_CNTL 0x00000d34 478 479 #define REG_A2XX_SQ_INT_STATUS 0x00000d35 480 481 #define REG_A2XX_SQ_INT_ACK 0x00000d36 482 483 #define REG_A2XX_SQ_DEBUG_INPUT_FSM 0x00000dae 484 485 #define REG_A2XX_SQ_DEBUG_CONST_MGR_FSM 0x00000daf 486 487 #define REG_A2XX_SQ_DEBUG_TP_FSM 0x00000db0 488 489 #define REG_A2XX_SQ_DEBUG_FSM_ALU_0 0x00000db1 490 491 #define REG_A2XX_SQ_DEBUG_FSM_ALU_1 0x00000db2 492 493 #define REG_A2XX_SQ_DEBUG_EXP_ALLOC 0x00000db3 494 495 #define REG_A2XX_SQ_DEBUG_PTR_BUFF 0x00000db4 496 497 #define REG_A2XX_SQ_DEBUG_GPR_VTX 0x00000db5 498 499 #define REG_A2XX_SQ_DEBUG_GPR_PIX 0x00000db6 500 501 #define REG_A2XX_SQ_DEBUG_TB_STATUS_SEL 0x00000db7 502 503 #define REG_A2XX_SQ_DEBUG_VTX_TB_0 0x00000db8 504 505 #define REG_A2XX_SQ_DEBUG_VTX_TB_1 0x00000db9 506 507 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG 0x00000dba 508 509 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM 0x00000dbb 510 511 #define REG_A2XX_SQ_DEBUG_PIX_TB_0 0x00000dbc 512 513 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0 0x00000dbd 514 515 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1 0x00000dbe 516 517 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2 0x00000dbf 518 519 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3 0x00000dc0 520 521 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM 0x00000dc1 522 523 #define REG_A2XX_TC_CNTL_STATUS 0x00000e00 524 #define A2XX_TC_CNTL_STATUS_L2_INVALIDATE 0x00000001 525 526 #define REG_A2XX_TP0_CHICKEN 0x00000e1e 527 528 #define REG_A2XX_RB_BC_CONTROL 0x00000f01 529 #define A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE 0x00000001 530 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK 0x00000006 531 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT 1 532 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val) 533 { 534 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK; 535 } 536 #define A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM 0x00000008 537 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010 538 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP 0x00000020 539 #define A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP 0x00000040 540 #define A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE 0x00000080 541 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK 0x00001f00 542 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT 8 543 static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val) 544 { 545 return ((val) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK; 546 } 547 #define A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE 0x00004000 548 #define A2XX_RB_BC_CONTROL_CRC_MODE 0x00008000 549 #define A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS 0x00010000 550 #define A2XX_RB_BC_CONTROL_DISABLE_ACCUM 0x00020000 551 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK 0x003c0000 552 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT 18 553 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val) 554 { 555 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK; 556 } 557 #define A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE 0x00400000 558 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK 0x07800000 559 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT 23 560 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val) 561 { 562 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK; 563 } 564 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK 0x18000000 565 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT 27 566 static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val) 567 { 568 return ((val) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK; 569 } 570 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000 571 #define A2XX_RB_BC_CONTROL_CRC_SYSTEM 0x40000000 572 #define A2XX_RB_BC_CONTROL_RESERVED6 0x80000000 573 574 #define REG_A2XX_RB_EDRAM_INFO 0x00000f02 575 576 #define REG_A2XX_RB_DEBUG_CNTL 0x00000f26 577 578 #define REG_A2XX_RB_DEBUG_DATA 0x00000f27 579 580 #define REG_A2XX_RB_SURFACE_INFO 0x00002000 581 582 #define REG_A2XX_RB_COLOR_INFO 0x00002001 583 #define A2XX_RB_COLOR_INFO_FORMAT__MASK 0x0000000f 584 #define A2XX_RB_COLOR_INFO_FORMAT__SHIFT 0 585 static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val) 586 { 587 return ((val) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT) & A2XX_RB_COLOR_INFO_FORMAT__MASK; 588 } 589 #define A2XX_RB_COLOR_INFO_ROUND_MODE__MASK 0x00000030 590 #define A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT 4 591 static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val) 592 { 593 return ((val) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK; 594 } 595 #define A2XX_RB_COLOR_INFO_LINEAR 0x00000040 596 #define A2XX_RB_COLOR_INFO_ENDIAN__MASK 0x00000180 597 #define A2XX_RB_COLOR_INFO_ENDIAN__SHIFT 7 598 static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val) 599 { 600 return ((val) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT) & A2XX_RB_COLOR_INFO_ENDIAN__MASK; 601 } 602 #define A2XX_RB_COLOR_INFO_SWAP__MASK 0x00000600 603 #define A2XX_RB_COLOR_INFO_SWAP__SHIFT 9 604 static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val) 605 { 606 return ((val) << A2XX_RB_COLOR_INFO_SWAP__SHIFT) & A2XX_RB_COLOR_INFO_SWAP__MASK; 607 } 608 #define A2XX_RB_COLOR_INFO_BASE__MASK 0xfffff000 609 #define A2XX_RB_COLOR_INFO_BASE__SHIFT 12 610 static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val) 611 { 612 return ((val >> 10) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK; 613 } 614 615 #define REG_A2XX_RB_DEPTH_INFO 0x00002002 616 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001 617 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 618 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) 619 { 620 return ((val) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 621 } 622 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 623 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 624 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 625 { 626 return ((val >> 10) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 627 } 628 629 #define REG_A2XX_A225_RB_COLOR_INFO3 0x00002005 630 631 #define REG_A2XX_COHER_DEST_BASE_0 0x00002006 632 633 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_TL 0x0000200e 634 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 635 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 636 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 637 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 638 { 639 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK; 640 } 641 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 642 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 643 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 644 { 645 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK; 646 } 647 648 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_BR 0x0000200f 649 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 650 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 651 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 652 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 653 { 654 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK; 655 } 656 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 657 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 658 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 659 { 660 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK; 661 } 662 663 #define REG_A2XX_PA_SC_WINDOW_OFFSET 0x00002080 664 #define A2XX_PA_SC_WINDOW_OFFSET_X__MASK 0x00007fff 665 #define A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT 0 666 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val) 667 { 668 return ((val) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK; 669 } 670 #define A2XX_PA_SC_WINDOW_OFFSET_Y__MASK 0x7fff0000 671 #define A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT 16 672 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val) 673 { 674 return ((val) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK; 675 } 676 #define A2XX_PA_SC_WINDOW_OFFSET_DISABLE 0x80000000 677 678 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_TL 0x00002081 679 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 680 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 681 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 682 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 683 { 684 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK; 685 } 686 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 687 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 688 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 689 { 690 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK; 691 } 692 693 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_BR 0x00002082 694 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 695 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 696 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 697 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 698 { 699 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK; 700 } 701 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 702 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 703 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 704 { 705 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK; 706 } 707 708 #define REG_A2XX_UNKNOWN_2010 0x00002010 709 710 #define REG_A2XX_VGT_MAX_VTX_INDX 0x00002100 711 712 #define REG_A2XX_VGT_MIN_VTX_INDX 0x00002101 713 714 #define REG_A2XX_VGT_INDX_OFFSET 0x00002102 715 716 #define REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX 0x00002103 717 718 #define REG_A2XX_RB_COLOR_MASK 0x00002104 719 #define A2XX_RB_COLOR_MASK_WRITE_RED 0x00000001 720 #define A2XX_RB_COLOR_MASK_WRITE_GREEN 0x00000002 721 #define A2XX_RB_COLOR_MASK_WRITE_BLUE 0x00000004 722 #define A2XX_RB_COLOR_MASK_WRITE_ALPHA 0x00000008 723 724 #define REG_A2XX_RB_BLEND_RED 0x00002105 725 726 #define REG_A2XX_RB_BLEND_GREEN 0x00002106 727 728 #define REG_A2XX_RB_BLEND_BLUE 0x00002107 729 730 #define REG_A2XX_RB_BLEND_ALPHA 0x00002108 731 732 #define REG_A2XX_RB_FOG_COLOR 0x00002109 733 734 #define REG_A2XX_RB_STENCILREFMASK_BF 0x0000210c 735 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 736 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 737 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 738 { 739 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 740 } 741 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 742 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 743 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 744 { 745 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 746 } 747 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 748 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 749 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 750 { 751 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 752 } 753 754 #define REG_A2XX_RB_STENCILREFMASK 0x0000210d 755 #define A2XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 756 #define A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 757 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 758 { 759 return ((val) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK; 760 } 761 #define A2XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 762 #define A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 763 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 764 { 765 return ((val) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK; 766 } 767 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 768 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 769 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 770 { 771 return ((val) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 772 } 773 774 #define REG_A2XX_RB_ALPHA_REF 0x0000210e 775 776 #define REG_A2XX_PA_CL_VPORT_XSCALE 0x0000210f 777 #define A2XX_PA_CL_VPORT_XSCALE__MASK 0xffffffff 778 #define A2XX_PA_CL_VPORT_XSCALE__SHIFT 0 779 static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val) 780 { 781 return ((fui(val)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT) & A2XX_PA_CL_VPORT_XSCALE__MASK; 782 } 783 784 #define REG_A2XX_PA_CL_VPORT_XOFFSET 0x00002110 785 #define A2XX_PA_CL_VPORT_XOFFSET__MASK 0xffffffff 786 #define A2XX_PA_CL_VPORT_XOFFSET__SHIFT 0 787 static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val) 788 { 789 return ((fui(val)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT) & A2XX_PA_CL_VPORT_XOFFSET__MASK; 790 } 791 792 #define REG_A2XX_PA_CL_VPORT_YSCALE 0x00002111 793 #define A2XX_PA_CL_VPORT_YSCALE__MASK 0xffffffff 794 #define A2XX_PA_CL_VPORT_YSCALE__SHIFT 0 795 static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val) 796 { 797 return ((fui(val)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT) & A2XX_PA_CL_VPORT_YSCALE__MASK; 798 } 799 800 #define REG_A2XX_PA_CL_VPORT_YOFFSET 0x00002112 801 #define A2XX_PA_CL_VPORT_YOFFSET__MASK 0xffffffff 802 #define A2XX_PA_CL_VPORT_YOFFSET__SHIFT 0 803 static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val) 804 { 805 return ((fui(val)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT) & A2XX_PA_CL_VPORT_YOFFSET__MASK; 806 } 807 808 #define REG_A2XX_PA_CL_VPORT_ZSCALE 0x00002113 809 #define A2XX_PA_CL_VPORT_ZSCALE__MASK 0xffffffff 810 #define A2XX_PA_CL_VPORT_ZSCALE__SHIFT 0 811 static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val) 812 { 813 return ((fui(val)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT) & A2XX_PA_CL_VPORT_ZSCALE__MASK; 814 } 815 816 #define REG_A2XX_PA_CL_VPORT_ZOFFSET 0x00002114 817 #define A2XX_PA_CL_VPORT_ZOFFSET__MASK 0xffffffff 818 #define A2XX_PA_CL_VPORT_ZOFFSET__SHIFT 0 819 static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val) 820 { 821 return ((fui(val)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT) & A2XX_PA_CL_VPORT_ZOFFSET__MASK; 822 } 823 824 #define REG_A2XX_SQ_PROGRAM_CNTL 0x00002180 825 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK 0x000000ff 826 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT 0 827 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val) 828 { 829 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK; 830 } 831 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK 0x0000ff00 832 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT 8 833 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val) 834 { 835 return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK; 836 } 837 #define A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE 0x00010000 838 #define A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE 0x00020000 839 #define A2XX_SQ_PROGRAM_CNTL_PARAM_GEN 0x00040000 840 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX 0x00080000 841 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK 0x00f00000 842 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT 20 843 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val) 844 { 845 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK; 846 } 847 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK 0x07000000 848 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT 24 849 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val) 850 { 851 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK; 852 } 853 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK 0x78000000 854 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT 27 855 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val) 856 { 857 return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK; 858 } 859 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX 0x80000000 860 861 #define REG_A2XX_SQ_CONTEXT_MISC 0x00002181 862 #define A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE 0x00000001 863 #define A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY 0x00000002 864 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK 0x0000000c 865 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT 2 866 static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val) 867 { 868 return ((val) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK; 869 } 870 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK 0x0000ff00 871 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT 8 872 static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val) 873 { 874 return ((val) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK; 875 } 876 #define A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF 0x00010000 877 #define A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE 0x00020000 878 #define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL 0x00040000 879 880 #define REG_A2XX_SQ_INTERPOLATOR_CNTL 0x00002182 881 882 #define REG_A2XX_SQ_WRAPPING_0 0x00002183 883 884 #define REG_A2XX_SQ_WRAPPING_1 0x00002184 885 886 #define REG_A2XX_SQ_PS_PROGRAM 0x000021f6 887 888 #define REG_A2XX_SQ_VS_PROGRAM 0x000021f7 889 890 #define REG_A2XX_VGT_EVENT_INITIATOR 0x000021f9 891 892 #define REG_A2XX_VGT_DRAW_INITIATOR 0x000021fc 893 894 #define REG_A2XX_VGT_IMMED_DATA 0x000021fd 895 896 #define REG_A2XX_RB_DEPTHCONTROL 0x00002200 897 #define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE 0x00000001 898 #define A2XX_RB_DEPTHCONTROL_Z_ENABLE 0x00000002 899 #define A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE 0x00000004 900 #define A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE 0x00000008 901 #define A2XX_RB_DEPTHCONTROL_ZFUNC__MASK 0x00000070 902 #define A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT 4 903 static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val) 904 { 905 return ((val) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK; 906 } 907 #define A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE 0x00000080 908 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK 0x00000700 909 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT 8 910 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val) 911 { 912 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK; 913 } 914 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK 0x00003800 915 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT 11 916 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val) 917 { 918 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK; 919 } 920 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK 0x0001c000 921 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT 14 922 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val) 923 { 924 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK; 925 } 926 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK 0x000e0000 927 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT 17 928 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val) 929 { 930 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK; 931 } 932 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK 0x00700000 933 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT 20 934 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val) 935 { 936 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK; 937 } 938 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK 0x03800000 939 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT 23 940 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val) 941 { 942 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK; 943 } 944 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK 0x1c000000 945 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT 26 946 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val) 947 { 948 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK; 949 } 950 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK 0xe0000000 951 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT 29 952 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val) 953 { 954 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK; 955 } 956 957 #define REG_A2XX_RB_BLEND_CONTROL 0x00002201 958 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK 0x0000001f 959 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT 0 960 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val) 961 { 962 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK; 963 } 964 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK 0x000000e0 965 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT 5 966 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum adreno_rb_blend_opcode val) 967 { 968 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK; 969 } 970 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK 0x00001f00 971 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT 8 972 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val) 973 { 974 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK; 975 } 976 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK 0x001f0000 977 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT 16 978 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val) 979 { 980 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK; 981 } 982 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK 0x00e00000 983 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT 21 984 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum adreno_rb_blend_opcode val) 985 { 986 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK; 987 } 988 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK 0x1f000000 989 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT 24 990 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val) 991 { 992 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK; 993 } 994 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE 0x20000000 995 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE 0x40000000 996 997 #define REG_A2XX_RB_COLORCONTROL 0x00002202 998 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK 0x00000007 999 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT 0 1000 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val) 1001 { 1002 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK; 1003 } 1004 #define A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE 0x00000008 1005 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE 0x00000010 1006 #define A2XX_RB_COLORCONTROL_BLEND_DISABLE 0x00000020 1007 #define A2XX_RB_COLORCONTROL_VOB_ENABLE 0x00000040 1008 #define A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG 0x00000080 1009 #define A2XX_RB_COLORCONTROL_ROP_CODE__MASK 0x00000f00 1010 #define A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT 8 1011 static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val) 1012 { 1013 return ((val) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK; 1014 } 1015 #define A2XX_RB_COLORCONTROL_DITHER_MODE__MASK 0x00003000 1016 #define A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT 12 1017 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) 1018 { 1019 return ((val) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK; 1020 } 1021 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK 0x0000c000 1022 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT 14 1023 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val) 1024 { 1025 return ((val) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK; 1026 } 1027 #define A2XX_RB_COLORCONTROL_PIXEL_FOG 0x00010000 1028 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK 0x03000000 1029 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT 24 1030 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val) 1031 { 1032 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK; 1033 } 1034 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK 0x0c000000 1035 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT 26 1036 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val) 1037 { 1038 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK; 1039 } 1040 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK 0x30000000 1041 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT 28 1042 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val) 1043 { 1044 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK; 1045 } 1046 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK 0xc0000000 1047 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT 30 1048 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val) 1049 { 1050 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK; 1051 } 1052 1053 #define REG_A2XX_VGT_CURRENT_BIN_ID_MAX 0x00002203 1054 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK 0x00000007 1055 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT 0 1056 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val) 1057 { 1058 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK; 1059 } 1060 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK 0x00000038 1061 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT 3 1062 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val) 1063 { 1064 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK; 1065 } 1066 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK 0x000001c0 1067 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT 6 1068 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val) 1069 { 1070 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK; 1071 } 1072 1073 #define REG_A2XX_PA_CL_CLIP_CNTL 0x00002204 1074 #define A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 1075 #define A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA 0x00040000 1076 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK 0x00080000 1077 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT 19 1078 static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val) 1079 { 1080 return ((val) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK; 1081 } 1082 #define A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT 0x00100000 1083 #define A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR 0x00200000 1084 #define A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN 0x00400000 1085 #define A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN 0x00800000 1086 #define A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN 0x01000000 1087 1088 #define REG_A2XX_PA_SU_SC_MODE_CNTL 0x00002205 1089 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT 0x00000001 1090 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK 0x00000002 1091 #define A2XX_PA_SU_SC_MODE_CNTL_FACE 0x00000004 1092 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK 0x00000018 1093 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT 3 1094 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val) 1095 { 1096 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK; 1097 } 1098 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK 0x000000e0 1099 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT 5 1100 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 1101 { 1102 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK; 1103 } 1104 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK 0x00000700 1105 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT 8 1106 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 1107 { 1108 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK; 1109 } 1110 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE 0x00000800 1111 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE 0x00001000 1112 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE 0x00002000 1113 #define A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE 0x00008000 1114 #define A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE 0x00010000 1115 #define A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE 0x00040000 1116 #define A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST 0x00080000 1117 #define A2XX_PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS 0x00100000 1118 #define A2XX_PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA 0x00200000 1119 #define A2XX_PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE 0x00800000 1120 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI 0x02000000 1121 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000 1122 #define A2XX_PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS 0x10000000 1123 #define A2XX_PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS 0x20000000 1124 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE 0x40000000 1125 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE 0x80000000 1126 1127 #define REG_A2XX_PA_CL_VTE_CNTL 0x00002206 1128 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA 0x00000001 1129 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA 0x00000002 1130 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA 0x00000004 1131 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA 0x00000008 1132 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA 0x00000010 1133 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA 0x00000020 1134 #define A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT 0x00000100 1135 #define A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT 0x00000200 1136 #define A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT 0x00000400 1137 #define A2XX_PA_CL_VTE_CNTL_PERFCOUNTER_REF 0x00000800 1138 1139 #define REG_A2XX_VGT_CURRENT_BIN_ID_MIN 0x00002207 1140 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK 0x00000007 1141 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT 0 1142 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val) 1143 { 1144 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK; 1145 } 1146 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK 0x00000038 1147 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT 3 1148 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val) 1149 { 1150 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK; 1151 } 1152 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK 0x000001c0 1153 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT 6 1154 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val) 1155 { 1156 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK; 1157 } 1158 1159 #define REG_A2XX_RB_MODECONTROL 0x00002208 1160 #define A2XX_RB_MODECONTROL_EDRAM_MODE__MASK 0x00000007 1161 #define A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT 0 1162 static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val) 1163 { 1164 return ((val) << A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT) & A2XX_RB_MODECONTROL_EDRAM_MODE__MASK; 1165 } 1166 1167 #define REG_A2XX_A220_RB_LRZ_VSC_CONTROL 0x00002209 1168 1169 #define REG_A2XX_RB_SAMPLE_POS 0x0000220a 1170 1171 #define REG_A2XX_CLEAR_COLOR 0x0000220b 1172 #define A2XX_CLEAR_COLOR_RED__MASK 0x000000ff 1173 #define A2XX_CLEAR_COLOR_RED__SHIFT 0 1174 static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val) 1175 { 1176 return ((val) << A2XX_CLEAR_COLOR_RED__SHIFT) & A2XX_CLEAR_COLOR_RED__MASK; 1177 } 1178 #define A2XX_CLEAR_COLOR_GREEN__MASK 0x0000ff00 1179 #define A2XX_CLEAR_COLOR_GREEN__SHIFT 8 1180 static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val) 1181 { 1182 return ((val) << A2XX_CLEAR_COLOR_GREEN__SHIFT) & A2XX_CLEAR_COLOR_GREEN__MASK; 1183 } 1184 #define A2XX_CLEAR_COLOR_BLUE__MASK 0x00ff0000 1185 #define A2XX_CLEAR_COLOR_BLUE__SHIFT 16 1186 static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val) 1187 { 1188 return ((val) << A2XX_CLEAR_COLOR_BLUE__SHIFT) & A2XX_CLEAR_COLOR_BLUE__MASK; 1189 } 1190 #define A2XX_CLEAR_COLOR_ALPHA__MASK 0xff000000 1191 #define A2XX_CLEAR_COLOR_ALPHA__SHIFT 24 1192 static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val) 1193 { 1194 return ((val) << A2XX_CLEAR_COLOR_ALPHA__SHIFT) & A2XX_CLEAR_COLOR_ALPHA__MASK; 1195 } 1196 1197 #define REG_A2XX_A220_GRAS_CONTROL 0x00002210 1198 1199 #define REG_A2XX_PA_SU_POINT_SIZE 0x00002280 1200 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK 0x0000ffff 1201 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT 0 1202 static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val) 1203 { 1204 return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK; 1205 } 1206 #define A2XX_PA_SU_POINT_SIZE_WIDTH__MASK 0xffff0000 1207 #define A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT 16 1208 static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val) 1209 { 1210 return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK; 1211 } 1212 1213 #define REG_A2XX_PA_SU_POINT_MINMAX 0x00002281 1214 #define A2XX_PA_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 1215 #define A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT 0 1216 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val) 1217 { 1218 return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK; 1219 } 1220 #define A2XX_PA_SU_POINT_MINMAX_MAX__MASK 0xffff0000 1221 #define A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT 16 1222 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val) 1223 { 1224 return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK; 1225 } 1226 1227 #define REG_A2XX_PA_SU_LINE_CNTL 0x00002282 1228 #define A2XX_PA_SU_LINE_CNTL_WIDTH__MASK 0x0000ffff 1229 #define A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT 0 1230 static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val) 1231 { 1232 return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK; 1233 } 1234 1235 #define REG_A2XX_PA_SC_LINE_STIPPLE 0x00002283 1236 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK 0x0000ffff 1237 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT 0 1238 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val) 1239 { 1240 return ((val) << A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK; 1241 } 1242 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK 0x00ff0000 1243 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT 16 1244 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val) 1245 { 1246 return ((val) << A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK; 1247 } 1248 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK 0x10000000 1249 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT 28 1250 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val) 1251 { 1252 return ((val) << A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK; 1253 } 1254 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK 0x60000000 1255 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT 29 1256 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val) 1257 { 1258 return ((val) << A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK; 1259 } 1260 1261 #define REG_A2XX_PA_SC_VIZ_QUERY 0x00002293 1262 1263 #define REG_A2XX_VGT_ENHANCE 0x00002294 1264 1265 #define REG_A2XX_PA_SC_LINE_CNTL 0x00002300 1266 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK 0x0000ffff 1267 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT 0 1268 static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val) 1269 { 1270 return ((val) << A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT) & A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK; 1271 } 1272 #define A2XX_PA_SC_LINE_CNTL_USE_BRES_CNTL 0x00000100 1273 #define A2XX_PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH 0x00000200 1274 #define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL 0x00000400 1275 1276 #define REG_A2XX_PA_SC_AA_CONFIG 0x00002301 1277 1278 #define REG_A2XX_PA_SU_VTX_CNTL 0x00002302 1279 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK 0x00000001 1280 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT 0 1281 static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val) 1282 { 1283 return ((val) << A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT) & A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK; 1284 } 1285 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK 0x00000006 1286 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT 1 1287 static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val) 1288 { 1289 return ((val) << A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK; 1290 } 1291 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK 0x00000380 1292 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT 7 1293 static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val) 1294 { 1295 return ((val) << A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK; 1296 } 1297 1298 #define REG_A2XX_PA_CL_GB_VERT_CLIP_ADJ 0x00002303 1299 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK 0xffffffff 1300 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT 0 1301 static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val) 1302 { 1303 return ((fui(val)) << A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK; 1304 } 1305 1306 #define REG_A2XX_PA_CL_GB_VERT_DISC_ADJ 0x00002304 1307 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK 0xffffffff 1308 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT 0 1309 static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val) 1310 { 1311 return ((fui(val)) << A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK; 1312 } 1313 1314 #define REG_A2XX_PA_CL_GB_HORZ_CLIP_ADJ 0x00002305 1315 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK 0xffffffff 1316 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT 0 1317 static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val) 1318 { 1319 return ((fui(val)) << A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK; 1320 } 1321 1322 #define REG_A2XX_PA_CL_GB_HORZ_DISC_ADJ 0x00002306 1323 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK 0xffffffff 1324 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT 0 1325 static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val) 1326 { 1327 return ((fui(val)) << A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK; 1328 } 1329 1330 #define REG_A2XX_SQ_VS_CONST 0x00002307 1331 #define A2XX_SQ_VS_CONST_BASE__MASK 0x000001ff 1332 #define A2XX_SQ_VS_CONST_BASE__SHIFT 0 1333 static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val) 1334 { 1335 return ((val) << A2XX_SQ_VS_CONST_BASE__SHIFT) & A2XX_SQ_VS_CONST_BASE__MASK; 1336 } 1337 #define A2XX_SQ_VS_CONST_SIZE__MASK 0x001ff000 1338 #define A2XX_SQ_VS_CONST_SIZE__SHIFT 12 1339 static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val) 1340 { 1341 return ((val) << A2XX_SQ_VS_CONST_SIZE__SHIFT) & A2XX_SQ_VS_CONST_SIZE__MASK; 1342 } 1343 1344 #define REG_A2XX_SQ_PS_CONST 0x00002308 1345 #define A2XX_SQ_PS_CONST_BASE__MASK 0x000001ff 1346 #define A2XX_SQ_PS_CONST_BASE__SHIFT 0 1347 static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val) 1348 { 1349 return ((val) << A2XX_SQ_PS_CONST_BASE__SHIFT) & A2XX_SQ_PS_CONST_BASE__MASK; 1350 } 1351 #define A2XX_SQ_PS_CONST_SIZE__MASK 0x001ff000 1352 #define A2XX_SQ_PS_CONST_SIZE__SHIFT 12 1353 static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val) 1354 { 1355 return ((val) << A2XX_SQ_PS_CONST_SIZE__SHIFT) & A2XX_SQ_PS_CONST_SIZE__MASK; 1356 } 1357 1358 #define REG_A2XX_SQ_DEBUG_MISC_0 0x00002309 1359 1360 #define REG_A2XX_SQ_DEBUG_MISC_1 0x0000230a 1361 1362 #define REG_A2XX_PA_SC_AA_MASK 0x00002312 1363 1364 #define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL 0x00002316 1365 1366 #define REG_A2XX_VGT_OUT_DEALLOC_CNTL 0x00002317 1367 1368 #define REG_A2XX_RB_COPY_CONTROL 0x00002318 1369 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK 0x00000007 1370 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT 0 1371 static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val) 1372 { 1373 return ((val) << A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT) & A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK; 1374 } 1375 #define A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE 0x00000008 1376 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK 0x000000f0 1377 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT 4 1378 static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val) 1379 { 1380 return ((val) << A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT) & A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK; 1381 } 1382 1383 #define REG_A2XX_RB_COPY_DEST_BASE 0x00002319 1384 1385 #define REG_A2XX_RB_COPY_DEST_PITCH 0x0000231a 1386 #define A2XX_RB_COPY_DEST_PITCH__MASK 0xffffffff 1387 #define A2XX_RB_COPY_DEST_PITCH__SHIFT 0 1388 static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val) 1389 { 1390 return ((val >> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK; 1391 } 1392 1393 #define REG_A2XX_RB_COPY_DEST_INFO 0x0000231b 1394 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK 0x00000007 1395 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT 0 1396 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val) 1397 { 1398 return ((val) << A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT) & A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK; 1399 } 1400 #define A2XX_RB_COPY_DEST_INFO_LINEAR 0x00000008 1401 #define A2XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000f0 1402 #define A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 4 1403 static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val) 1404 { 1405 return ((val) << A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A2XX_RB_COPY_DEST_INFO_FORMAT__MASK; 1406 } 1407 #define A2XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 1408 #define A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 1409 static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val) 1410 { 1411 return ((val) << A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A2XX_RB_COPY_DEST_INFO_SWAP__MASK; 1412 } 1413 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 1414 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 1415 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 1416 { 1417 return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 1418 } 1419 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK 0x00003000 1420 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT 12 1421 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val) 1422 { 1423 return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK; 1424 } 1425 #define A2XX_RB_COPY_DEST_INFO_WRITE_RED 0x00004000 1426 #define A2XX_RB_COPY_DEST_INFO_WRITE_GREEN 0x00008000 1427 #define A2XX_RB_COPY_DEST_INFO_WRITE_BLUE 0x00010000 1428 #define A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA 0x00020000 1429 1430 #define REG_A2XX_RB_COPY_DEST_OFFSET 0x0000231c 1431 #define A2XX_RB_COPY_DEST_OFFSET_X__MASK 0x00001fff 1432 #define A2XX_RB_COPY_DEST_OFFSET_X__SHIFT 0 1433 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val) 1434 { 1435 return ((val) << A2XX_RB_COPY_DEST_OFFSET_X__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_X__MASK; 1436 } 1437 #define A2XX_RB_COPY_DEST_OFFSET_Y__MASK 0x03ffe000 1438 #define A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT 13 1439 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val) 1440 { 1441 return ((val) << A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_Y__MASK; 1442 } 1443 1444 #define REG_A2XX_RB_DEPTH_CLEAR 0x0000231d 1445 1446 #define REG_A2XX_RB_SAMPLE_COUNT_CTL 0x00002324 1447 1448 #define REG_A2XX_RB_COLOR_DEST_MASK 0x00002326 1449 1450 #define REG_A2XX_A225_GRAS_UCP0X 0x00002340 1451 1452 #define REG_A2XX_A225_GRAS_UCP5W 0x00002357 1453 1454 #define REG_A2XX_A225_GRAS_UCP_ENABLED 0x00002360 1455 1456 #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE 0x00002380 1457 1458 #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET 0x00002383 1459 1460 #define REG_A2XX_SQ_CONSTANT_0 0x00004000 1461 1462 #define REG_A2XX_SQ_FETCH_0 0x00004800 1463 1464 #define REG_A2XX_SQ_CF_BOOLEANS 0x00004900 1465 1466 #define REG_A2XX_SQ_CF_LOOP 0x00004908 1467 1468 #define REG_A2XX_COHER_SIZE_PM4 0x00000a29 1469 1470 #define REG_A2XX_COHER_BASE_PM4 0x00000a2a 1471 1472 #define REG_A2XX_COHER_STATUS_PM4 0x00000a2b 1473 1474 #define REG_A2XX_SQ_TEX_0 0x00000000 1475 #define A2XX_SQ_TEX_0_CLAMP_X__MASK 0x00001c00 1476 #define A2XX_SQ_TEX_0_CLAMP_X__SHIFT 10 1477 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val) 1478 { 1479 return ((val) << A2XX_SQ_TEX_0_CLAMP_X__SHIFT) & A2XX_SQ_TEX_0_CLAMP_X__MASK; 1480 } 1481 #define A2XX_SQ_TEX_0_CLAMP_Y__MASK 0x0000e000 1482 #define A2XX_SQ_TEX_0_CLAMP_Y__SHIFT 13 1483 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val) 1484 { 1485 return ((val) << A2XX_SQ_TEX_0_CLAMP_Y__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Y__MASK; 1486 } 1487 #define A2XX_SQ_TEX_0_CLAMP_Z__MASK 0x00070000 1488 #define A2XX_SQ_TEX_0_CLAMP_Z__SHIFT 16 1489 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val) 1490 { 1491 return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK; 1492 } 1493 #define A2XX_SQ_TEX_0_PITCH__MASK 0xffc00000 1494 #define A2XX_SQ_TEX_0_PITCH__SHIFT 22 1495 static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val) 1496 { 1497 return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK; 1498 } 1499 1500 #define REG_A2XX_SQ_TEX_1 0x00000001 1501 1502 #define REG_A2XX_SQ_TEX_2 0x00000002 1503 #define A2XX_SQ_TEX_2_WIDTH__MASK 0x00001fff 1504 #define A2XX_SQ_TEX_2_WIDTH__SHIFT 0 1505 static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val) 1506 { 1507 return ((val) << A2XX_SQ_TEX_2_WIDTH__SHIFT) & A2XX_SQ_TEX_2_WIDTH__MASK; 1508 } 1509 #define A2XX_SQ_TEX_2_HEIGHT__MASK 0x03ffe000 1510 #define A2XX_SQ_TEX_2_HEIGHT__SHIFT 13 1511 static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val) 1512 { 1513 return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK; 1514 } 1515 1516 #define REG_A2XX_SQ_TEX_3 0x00000003 1517 #define A2XX_SQ_TEX_3_SWIZ_X__MASK 0x0000000e 1518 #define A2XX_SQ_TEX_3_SWIZ_X__SHIFT 1 1519 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val) 1520 { 1521 return ((val) << A2XX_SQ_TEX_3_SWIZ_X__SHIFT) & A2XX_SQ_TEX_3_SWIZ_X__MASK; 1522 } 1523 #define A2XX_SQ_TEX_3_SWIZ_Y__MASK 0x00000070 1524 #define A2XX_SQ_TEX_3_SWIZ_Y__SHIFT 4 1525 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val) 1526 { 1527 return ((val) << A2XX_SQ_TEX_3_SWIZ_Y__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Y__MASK; 1528 } 1529 #define A2XX_SQ_TEX_3_SWIZ_Z__MASK 0x00000380 1530 #define A2XX_SQ_TEX_3_SWIZ_Z__SHIFT 7 1531 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val) 1532 { 1533 return ((val) << A2XX_SQ_TEX_3_SWIZ_Z__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Z__MASK; 1534 } 1535 #define A2XX_SQ_TEX_3_SWIZ_W__MASK 0x00001c00 1536 #define A2XX_SQ_TEX_3_SWIZ_W__SHIFT 10 1537 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val) 1538 { 1539 return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK; 1540 } 1541 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK 0x00180000 1542 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT 19 1543 static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val) 1544 { 1545 return ((val) << A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK; 1546 } 1547 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK 0x00600000 1548 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT 21 1549 static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val) 1550 { 1551 return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK; 1552 } 1553 1554 1555 #endif /* A2XX_XML */ 1556