1 #ifndef A2XX_XML 2 #define A2XX_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13 - /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 31003 bytes, from 2013-09-19 18:50:16) 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36) 15 - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9759 bytes, from 2013-09-10 00:52:33) 16 - /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51983 bytes, from 2013-09-10 00:52:32) 17 18 Copyright (C) 2013 by the following authors: 19 - Rob Clark <robdclark@gmail.com> (robclark) 20 21 Permission is hereby granted, free of charge, to any person obtaining 22 a copy of this software and associated documentation files (the 23 "Software"), to deal in the Software without restriction, including 24 without limitation the rights to use, copy, modify, merge, publish, 25 distribute, sublicense, and/or sell copies of the Software, and to 26 permit persons to whom the Software is furnished to do so, subject to 27 the following conditions: 28 29 The above copyright notice and this permission notice (including the 30 next paragraph) shall be included in all copies or substantial 31 portions of the Software. 32 33 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 35 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 36 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 37 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 38 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 39 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 40 */ 41 42 43 enum a2xx_rb_dither_type { 44 DITHER_PIXEL = 0, 45 DITHER_SUBPIXEL = 1, 46 }; 47 48 enum a2xx_colorformatx { 49 COLORX_4_4_4_4 = 0, 50 COLORX_1_5_5_5 = 1, 51 COLORX_5_6_5 = 2, 52 COLORX_8 = 3, 53 COLORX_8_8 = 4, 54 COLORX_8_8_8_8 = 5, 55 COLORX_S8_8_8_8 = 6, 56 COLORX_16_FLOAT = 7, 57 COLORX_16_16_FLOAT = 8, 58 COLORX_16_16_16_16_FLOAT = 9, 59 COLORX_32_FLOAT = 10, 60 COLORX_32_32_FLOAT = 11, 61 COLORX_32_32_32_32_FLOAT = 12, 62 COLORX_2_3_3 = 13, 63 COLORX_8_8_8 = 14, 64 }; 65 66 enum a2xx_sq_surfaceformat { 67 FMT_1_REVERSE = 0, 68 FMT_1 = 1, 69 FMT_8 = 2, 70 FMT_1_5_5_5 = 3, 71 FMT_5_6_5 = 4, 72 FMT_6_5_5 = 5, 73 FMT_8_8_8_8 = 6, 74 FMT_2_10_10_10 = 7, 75 FMT_8_A = 8, 76 FMT_8_B = 9, 77 FMT_8_8 = 10, 78 FMT_Cr_Y1_Cb_Y0 = 11, 79 FMT_Y1_Cr_Y0_Cb = 12, 80 FMT_5_5_5_1 = 13, 81 FMT_8_8_8_8_A = 14, 82 FMT_4_4_4_4 = 15, 83 FMT_10_11_11 = 16, 84 FMT_11_11_10 = 17, 85 FMT_DXT1 = 18, 86 FMT_DXT2_3 = 19, 87 FMT_DXT4_5 = 20, 88 FMT_24_8 = 22, 89 FMT_24_8_FLOAT = 23, 90 FMT_16 = 24, 91 FMT_16_16 = 25, 92 FMT_16_16_16_16 = 26, 93 FMT_16_EXPAND = 27, 94 FMT_16_16_EXPAND = 28, 95 FMT_16_16_16_16_EXPAND = 29, 96 FMT_16_FLOAT = 30, 97 FMT_16_16_FLOAT = 31, 98 FMT_16_16_16_16_FLOAT = 32, 99 FMT_32 = 33, 100 FMT_32_32 = 34, 101 FMT_32_32_32_32 = 35, 102 FMT_32_FLOAT = 36, 103 FMT_32_32_FLOAT = 37, 104 FMT_32_32_32_32_FLOAT = 38, 105 FMT_32_AS_8 = 39, 106 FMT_32_AS_8_8 = 40, 107 FMT_16_MPEG = 41, 108 FMT_16_16_MPEG = 42, 109 FMT_8_INTERLACED = 43, 110 FMT_32_AS_8_INTERLACED = 44, 111 FMT_32_AS_8_8_INTERLACED = 45, 112 FMT_16_INTERLACED = 46, 113 FMT_16_MPEG_INTERLACED = 47, 114 FMT_16_16_MPEG_INTERLACED = 48, 115 FMT_DXN = 49, 116 FMT_8_8_8_8_AS_16_16_16_16 = 50, 117 FMT_DXT1_AS_16_16_16_16 = 51, 118 FMT_DXT2_3_AS_16_16_16_16 = 52, 119 FMT_DXT4_5_AS_16_16_16_16 = 53, 120 FMT_2_10_10_10_AS_16_16_16_16 = 54, 121 FMT_10_11_11_AS_16_16_16_16 = 55, 122 FMT_11_11_10_AS_16_16_16_16 = 56, 123 FMT_32_32_32_FLOAT = 57, 124 FMT_DXT3A = 58, 125 FMT_DXT5A = 59, 126 FMT_CTX1 = 60, 127 FMT_DXT3A_AS_1_1_1_1 = 61, 128 }; 129 130 enum a2xx_sq_ps_vtx_mode { 131 POSITION_1_VECTOR = 0, 132 POSITION_2_VECTORS_UNUSED = 1, 133 POSITION_2_VECTORS_SPRITE = 2, 134 POSITION_2_VECTORS_EDGE = 3, 135 POSITION_2_VECTORS_KILL = 4, 136 POSITION_2_VECTORS_SPRITE_KILL = 5, 137 POSITION_2_VECTORS_EDGE_KILL = 6, 138 MULTIPASS = 7, 139 }; 140 141 enum a2xx_sq_sample_cntl { 142 CENTROIDS_ONLY = 0, 143 CENTERS_ONLY = 1, 144 CENTROIDS_AND_CENTERS = 2, 145 }; 146 147 enum a2xx_dx_clip_space { 148 DXCLIP_OPENGL = 0, 149 DXCLIP_DIRECTX = 1, 150 }; 151 152 enum a2xx_pa_su_sc_polymode { 153 POLY_DISABLED = 0, 154 POLY_DUALMODE = 1, 155 }; 156 157 enum a2xx_rb_edram_mode { 158 EDRAM_NOP = 0, 159 COLOR_DEPTH = 4, 160 DEPTH_ONLY = 5, 161 EDRAM_COPY = 6, 162 }; 163 164 enum a2xx_pa_sc_pattern_bit_order { 165 LITTLE = 0, 166 BIG = 1, 167 }; 168 169 enum a2xx_pa_sc_auto_reset_cntl { 170 NEVER = 0, 171 EACH_PRIMITIVE = 1, 172 EACH_PACKET = 2, 173 }; 174 175 enum a2xx_pa_pixcenter { 176 PIXCENTER_D3D = 0, 177 PIXCENTER_OGL = 1, 178 }; 179 180 enum a2xx_pa_roundmode { 181 TRUNCATE = 0, 182 ROUND = 1, 183 ROUNDTOEVEN = 2, 184 ROUNDTOODD = 3, 185 }; 186 187 enum a2xx_pa_quantmode { 188 ONE_SIXTEENTH = 0, 189 ONE_EIGTH = 1, 190 ONE_QUARTER = 2, 191 ONE_HALF = 3, 192 ONE = 4, 193 }; 194 195 enum a2xx_rb_copy_sample_select { 196 SAMPLE_0 = 0, 197 SAMPLE_1 = 1, 198 SAMPLE_2 = 2, 199 SAMPLE_3 = 3, 200 SAMPLE_01 = 4, 201 SAMPLE_23 = 5, 202 SAMPLE_0123 = 6, 203 }; 204 205 enum sq_tex_clamp { 206 SQ_TEX_WRAP = 0, 207 SQ_TEX_MIRROR = 1, 208 SQ_TEX_CLAMP_LAST_TEXEL = 2, 209 SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3, 210 SQ_TEX_CLAMP_HALF_BORDER = 4, 211 SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5, 212 SQ_TEX_CLAMP_BORDER = 6, 213 SQ_TEX_MIRROR_ONCE_BORDER = 7, 214 }; 215 216 enum sq_tex_swiz { 217 SQ_TEX_X = 0, 218 SQ_TEX_Y = 1, 219 SQ_TEX_Z = 2, 220 SQ_TEX_W = 3, 221 SQ_TEX_ZERO = 4, 222 SQ_TEX_ONE = 5, 223 }; 224 225 enum sq_tex_filter { 226 SQ_TEX_FILTER_POINT = 0, 227 SQ_TEX_FILTER_BILINEAR = 1, 228 SQ_TEX_FILTER_BICUBIC = 2, 229 }; 230 231 #define REG_A2XX_RBBM_PATCH_RELEASE 0x00000001 232 233 #define REG_A2XX_RBBM_CNTL 0x0000003b 234 235 #define REG_A2XX_RBBM_SOFT_RESET 0x0000003c 236 237 #define REG_A2XX_CP_PFP_UCODE_ADDR 0x000000c0 238 239 #define REG_A2XX_CP_PFP_UCODE_DATA 0x000000c1 240 241 #define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395 242 243 #define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397 244 245 #define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x00000398 246 247 #define REG_A2XX_RBBM_DEBUG 0x0000039b 248 249 #define REG_A2XX_RBBM_PM_OVERRIDE1 0x0000039c 250 251 #define REG_A2XX_RBBM_PM_OVERRIDE2 0x0000039d 252 253 #define REG_A2XX_RBBM_DEBUG_OUT 0x000003a0 254 255 #define REG_A2XX_RBBM_DEBUG_CNTL 0x000003a1 256 257 #define REG_A2XX_RBBM_READ_ERROR 0x000003b3 258 259 #define REG_A2XX_RBBM_INT_CNTL 0x000003b4 260 261 #define REG_A2XX_RBBM_INT_STATUS 0x000003b5 262 263 #define REG_A2XX_RBBM_INT_ACK 0x000003b6 264 265 #define REG_A2XX_MASTER_INT_SIGNAL 0x000003b7 266 267 #define REG_A2XX_RBBM_PERIPHID1 0x000003f9 268 269 #define REG_A2XX_RBBM_PERIPHID2 0x000003fa 270 271 #define REG_A2XX_CP_PERFMON_CNTL 0x00000444 272 273 #define REG_A2XX_CP_PERFCOUNTER_SELECT 0x00000445 274 275 #define REG_A2XX_CP_PERFCOUNTER_LO 0x00000446 276 277 #define REG_A2XX_CP_PERFCOUNTER_HI 0x00000447 278 279 #define REG_A2XX_CP_ST_BASE 0x0000044d 280 281 #define REG_A2XX_CP_ST_BUFSZ 0x0000044e 282 283 #define REG_A2XX_CP_IB1_BASE 0x00000458 284 285 #define REG_A2XX_CP_IB1_BUFSZ 0x00000459 286 287 #define REG_A2XX_CP_IB2_BASE 0x0000045a 288 289 #define REG_A2XX_CP_IB2_BUFSZ 0x0000045b 290 291 #define REG_A2XX_CP_STAT 0x0000047f 292 293 #define REG_A2XX_RBBM_STATUS 0x000005d0 294 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK 0x0000001f 295 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT 0 296 static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val) 297 { 298 return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK; 299 } 300 #define A2XX_RBBM_STATUS_TC_BUSY 0x00000020 301 #define A2XX_RBBM_STATUS_HIRQ_PENDING 0x00000100 302 #define A2XX_RBBM_STATUS_CPRQ_PENDING 0x00000200 303 #define A2XX_RBBM_STATUS_CFRQ_PENDING 0x00000400 304 #define A2XX_RBBM_STATUS_PFRQ_PENDING 0x00000800 305 #define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA 0x00001000 306 #define A2XX_RBBM_STATUS_RBBM_WU_BUSY 0x00004000 307 #define A2XX_RBBM_STATUS_CP_NRT_BUSY 0x00010000 308 #define A2XX_RBBM_STATUS_MH_BUSY 0x00040000 309 #define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY 0x00080000 310 #define A2XX_RBBM_STATUS_SX_BUSY 0x00200000 311 #define A2XX_RBBM_STATUS_TPC_BUSY 0x00400000 312 #define A2XX_RBBM_STATUS_SC_CNTX_BUSY 0x01000000 313 #define A2XX_RBBM_STATUS_PA_BUSY 0x02000000 314 #define A2XX_RBBM_STATUS_VGT_BUSY 0x04000000 315 #define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY 0x08000000 316 #define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY 0x10000000 317 #define A2XX_RBBM_STATUS_RB_CNTX_BUSY 0x40000000 318 #define A2XX_RBBM_STATUS_GUI_ACTIVE 0x80000000 319 320 #define REG_A2XX_MH_ARBITER_CONFIG 0x00000a40 321 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK 0x0000003f 322 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT 0 323 static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val) 324 { 325 return ((val) << A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK; 326 } 327 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY 0x00000040 328 #define A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE 0x00000080 329 #define A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE 0x00000100 330 #define A2XX_MH_ARBITER_CONFIG_L2_ARB_CONTROL 0x00000200 331 #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK 0x00001c00 332 #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT 10 333 static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val) 334 { 335 return ((val) << A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT) & A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK; 336 } 337 #define A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00002000 338 #define A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE 0x00004000 339 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE 0x00008000 340 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK 0x003f0000 341 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT 16 342 static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val) 343 { 344 return ((val) << A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK; 345 } 346 #define A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE 0x00400000 347 #define A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE 0x00800000 348 #define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE 0x01000000 349 #define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE 0x02000000 350 #define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE 0x04000000 351 352 #define REG_A2XX_A220_VSC_BIN_SIZE 0x00000c01 353 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 354 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT 0 355 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val) 356 { 357 return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK; 358 } 359 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 360 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT 5 361 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val) 362 { 363 return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK; 364 } 365 366 static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 367 368 static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 369 370 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } 371 372 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } 373 374 #define REG_A2XX_PC_DEBUG_CNTL 0x00000c38 375 376 #define REG_A2XX_PC_DEBUG_DATA 0x00000c39 377 378 #define REG_A2XX_PA_SC_VIZ_QUERY_STATUS 0x00000c44 379 380 #define REG_A2XX_GRAS_DEBUG_CNTL 0x00000c80 381 382 #define REG_A2XX_PA_SU_DEBUG_CNTL 0x00000c80 383 384 #define REG_A2XX_GRAS_DEBUG_DATA 0x00000c81 385 386 #define REG_A2XX_PA_SU_DEBUG_DATA 0x00000c81 387 388 #define REG_A2XX_PA_SU_FACE_DATA 0x00000c86 389 390 #define REG_A2XX_SQ_GPR_MANAGEMENT 0x00000d00 391 392 #define REG_A2XX_SQ_FLOW_CONTROL 0x00000d01 393 394 #define REG_A2XX_SQ_INST_STORE_MANAGMENT 0x00000d02 395 396 #define REG_A2XX_SQ_DEBUG_MISC 0x00000d05 397 398 #define REG_A2XX_SQ_INT_CNTL 0x00000d34 399 400 #define REG_A2XX_SQ_INT_STATUS 0x00000d35 401 402 #define REG_A2XX_SQ_INT_ACK 0x00000d36 403 404 #define REG_A2XX_SQ_DEBUG_INPUT_FSM 0x00000dae 405 406 #define REG_A2XX_SQ_DEBUG_CONST_MGR_FSM 0x00000daf 407 408 #define REG_A2XX_SQ_DEBUG_TP_FSM 0x00000db0 409 410 #define REG_A2XX_SQ_DEBUG_FSM_ALU_0 0x00000db1 411 412 #define REG_A2XX_SQ_DEBUG_FSM_ALU_1 0x00000db2 413 414 #define REG_A2XX_SQ_DEBUG_EXP_ALLOC 0x00000db3 415 416 #define REG_A2XX_SQ_DEBUG_PTR_BUFF 0x00000db4 417 418 #define REG_A2XX_SQ_DEBUG_GPR_VTX 0x00000db5 419 420 #define REG_A2XX_SQ_DEBUG_GPR_PIX 0x00000db6 421 422 #define REG_A2XX_SQ_DEBUG_TB_STATUS_SEL 0x00000db7 423 424 #define REG_A2XX_SQ_DEBUG_VTX_TB_0 0x00000db8 425 426 #define REG_A2XX_SQ_DEBUG_VTX_TB_1 0x00000db9 427 428 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG 0x00000dba 429 430 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM 0x00000dbb 431 432 #define REG_A2XX_SQ_DEBUG_PIX_TB_0 0x00000dbc 433 434 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0 0x00000dbd 435 436 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1 0x00000dbe 437 438 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2 0x00000dbf 439 440 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3 0x00000dc0 441 442 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM 0x00000dc1 443 444 #define REG_A2XX_TC_CNTL_STATUS 0x00000e00 445 #define A2XX_TC_CNTL_STATUS_L2_INVALIDATE 0x00000001 446 447 #define REG_A2XX_TP0_CHICKEN 0x00000e1e 448 449 #define REG_A2XX_RB_BC_CONTROL 0x00000f01 450 #define A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE 0x00000001 451 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK 0x00000006 452 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT 1 453 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val) 454 { 455 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK; 456 } 457 #define A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM 0x00000008 458 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010 459 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP 0x00000020 460 #define A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP 0x00000040 461 #define A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE 0x00000080 462 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK 0x00001f00 463 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT 8 464 static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val) 465 { 466 return ((val) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK; 467 } 468 #define A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE 0x00004000 469 #define A2XX_RB_BC_CONTROL_CRC_MODE 0x00008000 470 #define A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS 0x00010000 471 #define A2XX_RB_BC_CONTROL_DISABLE_ACCUM 0x00020000 472 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK 0x003c0000 473 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT 18 474 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val) 475 { 476 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK; 477 } 478 #define A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE 0x00400000 479 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK 0x07800000 480 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT 23 481 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val) 482 { 483 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK; 484 } 485 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK 0x18000000 486 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT 27 487 static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val) 488 { 489 return ((val) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK; 490 } 491 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000 492 #define A2XX_RB_BC_CONTROL_CRC_SYSTEM 0x40000000 493 #define A2XX_RB_BC_CONTROL_RESERVED6 0x80000000 494 495 #define REG_A2XX_RB_EDRAM_INFO 0x00000f02 496 497 #define REG_A2XX_RB_DEBUG_CNTL 0x00000f26 498 499 #define REG_A2XX_RB_DEBUG_DATA 0x00000f27 500 501 #define REG_A2XX_RB_SURFACE_INFO 0x00002000 502 503 #define REG_A2XX_RB_COLOR_INFO 0x00002001 504 #define A2XX_RB_COLOR_INFO_FORMAT__MASK 0x0000000f 505 #define A2XX_RB_COLOR_INFO_FORMAT__SHIFT 0 506 static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val) 507 { 508 return ((val) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT) & A2XX_RB_COLOR_INFO_FORMAT__MASK; 509 } 510 #define A2XX_RB_COLOR_INFO_ROUND_MODE__MASK 0x00000030 511 #define A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT 4 512 static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val) 513 { 514 return ((val) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK; 515 } 516 #define A2XX_RB_COLOR_INFO_LINEAR 0x00000040 517 #define A2XX_RB_COLOR_INFO_ENDIAN__MASK 0x00000180 518 #define A2XX_RB_COLOR_INFO_ENDIAN__SHIFT 7 519 static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val) 520 { 521 return ((val) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT) & A2XX_RB_COLOR_INFO_ENDIAN__MASK; 522 } 523 #define A2XX_RB_COLOR_INFO_SWAP__MASK 0x00000600 524 #define A2XX_RB_COLOR_INFO_SWAP__SHIFT 9 525 static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val) 526 { 527 return ((val) << A2XX_RB_COLOR_INFO_SWAP__SHIFT) & A2XX_RB_COLOR_INFO_SWAP__MASK; 528 } 529 #define A2XX_RB_COLOR_INFO_BASE__MASK 0xfffff000 530 #define A2XX_RB_COLOR_INFO_BASE__SHIFT 12 531 static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val) 532 { 533 return ((val >> 10) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK; 534 } 535 536 #define REG_A2XX_RB_DEPTH_INFO 0x00002002 537 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001 538 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 539 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) 540 { 541 return ((val) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 542 } 543 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 544 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 545 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 546 { 547 return ((val >> 10) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 548 } 549 550 #define REG_A2XX_A225_RB_COLOR_INFO3 0x00002005 551 552 #define REG_A2XX_COHER_DEST_BASE_0 0x00002006 553 554 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_TL 0x0000200e 555 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 556 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 557 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 558 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 559 { 560 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK; 561 } 562 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 563 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 564 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 565 { 566 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK; 567 } 568 569 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_BR 0x0000200f 570 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 571 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 572 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 573 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 574 { 575 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK; 576 } 577 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 578 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 579 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 580 { 581 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK; 582 } 583 584 #define REG_A2XX_PA_SC_WINDOW_OFFSET 0x00002080 585 #define A2XX_PA_SC_WINDOW_OFFSET_X__MASK 0x00007fff 586 #define A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT 0 587 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val) 588 { 589 return ((val) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK; 590 } 591 #define A2XX_PA_SC_WINDOW_OFFSET_Y__MASK 0x7fff0000 592 #define A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT 16 593 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val) 594 { 595 return ((val) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK; 596 } 597 #define A2XX_PA_SC_WINDOW_OFFSET_DISABLE 0x80000000 598 599 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_TL 0x00002081 600 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 601 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 602 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 603 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 604 { 605 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK; 606 } 607 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 608 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 609 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 610 { 611 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK; 612 } 613 614 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_BR 0x00002082 615 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 616 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 617 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 618 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 619 { 620 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK; 621 } 622 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 623 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 624 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 625 { 626 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK; 627 } 628 629 #define REG_A2XX_UNKNOWN_2010 0x00002010 630 631 #define REG_A2XX_VGT_MAX_VTX_INDX 0x00002100 632 633 #define REG_A2XX_VGT_MIN_VTX_INDX 0x00002101 634 635 #define REG_A2XX_VGT_INDX_OFFSET 0x00002102 636 637 #define REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX 0x00002103 638 639 #define REG_A2XX_RB_COLOR_MASK 0x00002104 640 #define A2XX_RB_COLOR_MASK_WRITE_RED 0x00000001 641 #define A2XX_RB_COLOR_MASK_WRITE_GREEN 0x00000002 642 #define A2XX_RB_COLOR_MASK_WRITE_BLUE 0x00000004 643 #define A2XX_RB_COLOR_MASK_WRITE_ALPHA 0x00000008 644 645 #define REG_A2XX_RB_BLEND_RED 0x00002105 646 647 #define REG_A2XX_RB_BLEND_GREEN 0x00002106 648 649 #define REG_A2XX_RB_BLEND_BLUE 0x00002107 650 651 #define REG_A2XX_RB_BLEND_ALPHA 0x00002108 652 653 #define REG_A2XX_RB_FOG_COLOR 0x00002109 654 655 #define REG_A2XX_RB_STENCILREFMASK_BF 0x0000210c 656 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 657 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 658 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 659 { 660 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 661 } 662 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 663 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 664 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 665 { 666 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 667 } 668 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 669 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 670 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 671 { 672 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 673 } 674 675 #define REG_A2XX_RB_STENCILREFMASK 0x0000210d 676 #define A2XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 677 #define A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 678 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 679 { 680 return ((val) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK; 681 } 682 #define A2XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 683 #define A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 684 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 685 { 686 return ((val) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK; 687 } 688 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 689 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 690 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 691 { 692 return ((val) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 693 } 694 695 #define REG_A2XX_RB_ALPHA_REF 0x0000210e 696 697 #define REG_A2XX_PA_CL_VPORT_XSCALE 0x0000210f 698 #define A2XX_PA_CL_VPORT_XSCALE__MASK 0xffffffff 699 #define A2XX_PA_CL_VPORT_XSCALE__SHIFT 0 700 static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val) 701 { 702 return ((fui(val)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT) & A2XX_PA_CL_VPORT_XSCALE__MASK; 703 } 704 705 #define REG_A2XX_PA_CL_VPORT_XOFFSET 0x00002110 706 #define A2XX_PA_CL_VPORT_XOFFSET__MASK 0xffffffff 707 #define A2XX_PA_CL_VPORT_XOFFSET__SHIFT 0 708 static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val) 709 { 710 return ((fui(val)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT) & A2XX_PA_CL_VPORT_XOFFSET__MASK; 711 } 712 713 #define REG_A2XX_PA_CL_VPORT_YSCALE 0x00002111 714 #define A2XX_PA_CL_VPORT_YSCALE__MASK 0xffffffff 715 #define A2XX_PA_CL_VPORT_YSCALE__SHIFT 0 716 static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val) 717 { 718 return ((fui(val)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT) & A2XX_PA_CL_VPORT_YSCALE__MASK; 719 } 720 721 #define REG_A2XX_PA_CL_VPORT_YOFFSET 0x00002112 722 #define A2XX_PA_CL_VPORT_YOFFSET__MASK 0xffffffff 723 #define A2XX_PA_CL_VPORT_YOFFSET__SHIFT 0 724 static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val) 725 { 726 return ((fui(val)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT) & A2XX_PA_CL_VPORT_YOFFSET__MASK; 727 } 728 729 #define REG_A2XX_PA_CL_VPORT_ZSCALE 0x00002113 730 #define A2XX_PA_CL_VPORT_ZSCALE__MASK 0xffffffff 731 #define A2XX_PA_CL_VPORT_ZSCALE__SHIFT 0 732 static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val) 733 { 734 return ((fui(val)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT) & A2XX_PA_CL_VPORT_ZSCALE__MASK; 735 } 736 737 #define REG_A2XX_PA_CL_VPORT_ZOFFSET 0x00002114 738 #define A2XX_PA_CL_VPORT_ZOFFSET__MASK 0xffffffff 739 #define A2XX_PA_CL_VPORT_ZOFFSET__SHIFT 0 740 static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val) 741 { 742 return ((fui(val)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT) & A2XX_PA_CL_VPORT_ZOFFSET__MASK; 743 } 744 745 #define REG_A2XX_SQ_PROGRAM_CNTL 0x00002180 746 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK 0x000000ff 747 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT 0 748 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val) 749 { 750 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK; 751 } 752 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK 0x0000ff00 753 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT 8 754 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val) 755 { 756 return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK; 757 } 758 #define A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE 0x00010000 759 #define A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE 0x00020000 760 #define A2XX_SQ_PROGRAM_CNTL_PARAM_GEN 0x00040000 761 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX 0x00080000 762 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK 0x00f00000 763 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT 20 764 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val) 765 { 766 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK; 767 } 768 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK 0x07000000 769 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT 24 770 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val) 771 { 772 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK; 773 } 774 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK 0x78000000 775 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT 27 776 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val) 777 { 778 return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK; 779 } 780 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX 0x80000000 781 782 #define REG_A2XX_SQ_CONTEXT_MISC 0x00002181 783 #define A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE 0x00000001 784 #define A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY 0x00000002 785 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK 0x0000000c 786 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT 2 787 static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val) 788 { 789 return ((val) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK; 790 } 791 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK 0x0000ff00 792 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT 8 793 static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val) 794 { 795 return ((val) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK; 796 } 797 #define A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF 0x00010000 798 #define A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE 0x00020000 799 #define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL 0x00040000 800 801 #define REG_A2XX_SQ_INTERPOLATOR_CNTL 0x00002182 802 803 #define REG_A2XX_SQ_WRAPPING_0 0x00002183 804 805 #define REG_A2XX_SQ_WRAPPING_1 0x00002184 806 807 #define REG_A2XX_SQ_PS_PROGRAM 0x000021f6 808 809 #define REG_A2XX_SQ_VS_PROGRAM 0x000021f7 810 811 #define REG_A2XX_RB_DEPTHCONTROL 0x00002200 812 #define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE 0x00000001 813 #define A2XX_RB_DEPTHCONTROL_Z_ENABLE 0x00000002 814 #define A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE 0x00000004 815 #define A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE 0x00000008 816 #define A2XX_RB_DEPTHCONTROL_ZFUNC__MASK 0x00000070 817 #define A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT 4 818 static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val) 819 { 820 return ((val) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK; 821 } 822 #define A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE 0x00000080 823 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK 0x00000700 824 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT 8 825 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val) 826 { 827 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK; 828 } 829 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK 0x00003800 830 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT 11 831 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val) 832 { 833 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK; 834 } 835 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK 0x0001c000 836 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT 14 837 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val) 838 { 839 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK; 840 } 841 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK 0x000e0000 842 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT 17 843 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val) 844 { 845 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK; 846 } 847 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK 0x00700000 848 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT 20 849 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val) 850 { 851 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK; 852 } 853 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK 0x03800000 854 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT 23 855 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val) 856 { 857 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK; 858 } 859 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK 0x1c000000 860 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT 26 861 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val) 862 { 863 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK; 864 } 865 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK 0xe0000000 866 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT 29 867 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val) 868 { 869 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK; 870 } 871 872 #define REG_A2XX_RB_BLEND_CONTROL 0x00002201 873 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK 0x0000001f 874 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT 0 875 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val) 876 { 877 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK; 878 } 879 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK 0x000000e0 880 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT 5 881 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum adreno_rb_blend_opcode val) 882 { 883 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK; 884 } 885 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK 0x00001f00 886 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT 8 887 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val) 888 { 889 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK; 890 } 891 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK 0x001f0000 892 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT 16 893 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val) 894 { 895 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK; 896 } 897 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK 0x00e00000 898 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT 21 899 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum adreno_rb_blend_opcode val) 900 { 901 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK; 902 } 903 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK 0x1f000000 904 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT 24 905 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val) 906 { 907 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK; 908 } 909 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE 0x20000000 910 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE 0x40000000 911 912 #define REG_A2XX_RB_COLORCONTROL 0x00002202 913 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK 0x00000007 914 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT 0 915 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val) 916 { 917 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK; 918 } 919 #define A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE 0x00000008 920 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE 0x00000010 921 #define A2XX_RB_COLORCONTROL_BLEND_DISABLE 0x00000020 922 #define A2XX_RB_COLORCONTROL_VOB_ENABLE 0x00000040 923 #define A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG 0x00000080 924 #define A2XX_RB_COLORCONTROL_ROP_CODE__MASK 0x00000f00 925 #define A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT 8 926 static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val) 927 { 928 return ((val) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK; 929 } 930 #define A2XX_RB_COLORCONTROL_DITHER_MODE__MASK 0x00003000 931 #define A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT 12 932 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) 933 { 934 return ((val) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK; 935 } 936 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK 0x0000c000 937 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT 14 938 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val) 939 { 940 return ((val) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK; 941 } 942 #define A2XX_RB_COLORCONTROL_PIXEL_FOG 0x00010000 943 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK 0x03000000 944 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT 24 945 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val) 946 { 947 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK; 948 } 949 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK 0x0c000000 950 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT 26 951 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val) 952 { 953 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK; 954 } 955 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK 0x30000000 956 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT 28 957 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val) 958 { 959 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK; 960 } 961 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK 0xc0000000 962 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT 30 963 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val) 964 { 965 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK; 966 } 967 968 #define REG_A2XX_VGT_CURRENT_BIN_ID_MAX 0x00002203 969 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK 0x00000007 970 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT 0 971 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val) 972 { 973 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK; 974 } 975 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK 0x00000038 976 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT 3 977 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val) 978 { 979 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK; 980 } 981 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK 0x000001c0 982 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT 6 983 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val) 984 { 985 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK; 986 } 987 988 #define REG_A2XX_PA_CL_CLIP_CNTL 0x00002204 989 #define A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 990 #define A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA 0x00040000 991 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK 0x00080000 992 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT 19 993 static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val) 994 { 995 return ((val) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK; 996 } 997 #define A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT 0x00100000 998 #define A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR 0x00200000 999 #define A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN 0x00400000 1000 #define A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN 0x00800000 1001 #define A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN 0x01000000 1002 1003 #define REG_A2XX_PA_SU_SC_MODE_CNTL 0x00002205 1004 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT 0x00000001 1005 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK 0x00000002 1006 #define A2XX_PA_SU_SC_MODE_CNTL_FACE 0x00000004 1007 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK 0x00000018 1008 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT 3 1009 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val) 1010 { 1011 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK; 1012 } 1013 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK 0x000000e0 1014 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT 5 1015 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 1016 { 1017 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK; 1018 } 1019 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK 0x00000700 1020 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT 8 1021 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 1022 { 1023 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK; 1024 } 1025 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE 0x00000800 1026 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE 0x00001000 1027 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE 0x00002000 1028 #define A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE 0x00008000 1029 #define A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE 0x00010000 1030 #define A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE 0x00040000 1031 #define A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST 0x00080000 1032 #define A2XX_PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS 0x00100000 1033 #define A2XX_PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA 0x00200000 1034 #define A2XX_PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE 0x00800000 1035 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI 0x02000000 1036 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000 1037 #define A2XX_PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS 0x10000000 1038 #define A2XX_PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS 0x20000000 1039 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE 0x40000000 1040 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE 0x80000000 1041 1042 #define REG_A2XX_PA_CL_VTE_CNTL 0x00002206 1043 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA 0x00000001 1044 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA 0x00000002 1045 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA 0x00000004 1046 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA 0x00000008 1047 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA 0x00000010 1048 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA 0x00000020 1049 #define A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT 0x00000100 1050 #define A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT 0x00000200 1051 #define A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT 0x00000400 1052 #define A2XX_PA_CL_VTE_CNTL_PERFCOUNTER_REF 0x00000800 1053 1054 #define REG_A2XX_VGT_CURRENT_BIN_ID_MIN 0x00002207 1055 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK 0x00000007 1056 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT 0 1057 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val) 1058 { 1059 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK; 1060 } 1061 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK 0x00000038 1062 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT 3 1063 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val) 1064 { 1065 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK; 1066 } 1067 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK 0x000001c0 1068 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT 6 1069 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val) 1070 { 1071 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK; 1072 } 1073 1074 #define REG_A2XX_RB_MODECONTROL 0x00002208 1075 #define A2XX_RB_MODECONTROL_EDRAM_MODE__MASK 0x00000007 1076 #define A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT 0 1077 static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val) 1078 { 1079 return ((val) << A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT) & A2XX_RB_MODECONTROL_EDRAM_MODE__MASK; 1080 } 1081 1082 #define REG_A2XX_A220_RB_LRZ_VSC_CONTROL 0x00002209 1083 1084 #define REG_A2XX_RB_SAMPLE_POS 0x0000220a 1085 1086 #define REG_A2XX_CLEAR_COLOR 0x0000220b 1087 #define A2XX_CLEAR_COLOR_RED__MASK 0x000000ff 1088 #define A2XX_CLEAR_COLOR_RED__SHIFT 0 1089 static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val) 1090 { 1091 return ((val) << A2XX_CLEAR_COLOR_RED__SHIFT) & A2XX_CLEAR_COLOR_RED__MASK; 1092 } 1093 #define A2XX_CLEAR_COLOR_GREEN__MASK 0x0000ff00 1094 #define A2XX_CLEAR_COLOR_GREEN__SHIFT 8 1095 static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val) 1096 { 1097 return ((val) << A2XX_CLEAR_COLOR_GREEN__SHIFT) & A2XX_CLEAR_COLOR_GREEN__MASK; 1098 } 1099 #define A2XX_CLEAR_COLOR_BLUE__MASK 0x00ff0000 1100 #define A2XX_CLEAR_COLOR_BLUE__SHIFT 16 1101 static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val) 1102 { 1103 return ((val) << A2XX_CLEAR_COLOR_BLUE__SHIFT) & A2XX_CLEAR_COLOR_BLUE__MASK; 1104 } 1105 #define A2XX_CLEAR_COLOR_ALPHA__MASK 0xff000000 1106 #define A2XX_CLEAR_COLOR_ALPHA__SHIFT 24 1107 static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val) 1108 { 1109 return ((val) << A2XX_CLEAR_COLOR_ALPHA__SHIFT) & A2XX_CLEAR_COLOR_ALPHA__MASK; 1110 } 1111 1112 #define REG_A2XX_A220_GRAS_CONTROL 0x00002210 1113 1114 #define REG_A2XX_PA_SU_POINT_SIZE 0x00002280 1115 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK 0x0000ffff 1116 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT 0 1117 static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val) 1118 { 1119 return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK; 1120 } 1121 #define A2XX_PA_SU_POINT_SIZE_WIDTH__MASK 0xffff0000 1122 #define A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT 16 1123 static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val) 1124 { 1125 return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK; 1126 } 1127 1128 #define REG_A2XX_PA_SU_POINT_MINMAX 0x00002281 1129 #define A2XX_PA_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 1130 #define A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT 0 1131 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val) 1132 { 1133 return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK; 1134 } 1135 #define A2XX_PA_SU_POINT_MINMAX_MAX__MASK 0xffff0000 1136 #define A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT 16 1137 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val) 1138 { 1139 return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK; 1140 } 1141 1142 #define REG_A2XX_PA_SU_LINE_CNTL 0x00002282 1143 #define A2XX_PA_SU_LINE_CNTL_WIDTH__MASK 0x0000ffff 1144 #define A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT 0 1145 static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val) 1146 { 1147 return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK; 1148 } 1149 1150 #define REG_A2XX_PA_SC_LINE_STIPPLE 0x00002283 1151 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK 0x0000ffff 1152 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT 0 1153 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val) 1154 { 1155 return ((val) << A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK; 1156 } 1157 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK 0x00ff0000 1158 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT 16 1159 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val) 1160 { 1161 return ((val) << A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK; 1162 } 1163 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK 0x10000000 1164 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT 28 1165 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val) 1166 { 1167 return ((val) << A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK; 1168 } 1169 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK 0x60000000 1170 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT 29 1171 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val) 1172 { 1173 return ((val) << A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK; 1174 } 1175 1176 #define REG_A2XX_PA_SC_VIZ_QUERY 0x00002293 1177 1178 #define REG_A2XX_VGT_ENHANCE 0x00002294 1179 1180 #define REG_A2XX_PA_SC_LINE_CNTL 0x00002300 1181 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK 0x0000ffff 1182 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT 0 1183 static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val) 1184 { 1185 return ((val) << A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT) & A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK; 1186 } 1187 #define A2XX_PA_SC_LINE_CNTL_USE_BRES_CNTL 0x00000100 1188 #define A2XX_PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH 0x00000200 1189 #define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL 0x00000400 1190 1191 #define REG_A2XX_PA_SC_AA_CONFIG 0x00002301 1192 1193 #define REG_A2XX_PA_SU_VTX_CNTL 0x00002302 1194 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK 0x00000001 1195 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT 0 1196 static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val) 1197 { 1198 return ((val) << A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT) & A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK; 1199 } 1200 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK 0x00000006 1201 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT 1 1202 static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val) 1203 { 1204 return ((val) << A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK; 1205 } 1206 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK 0x00000380 1207 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT 7 1208 static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val) 1209 { 1210 return ((val) << A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK; 1211 } 1212 1213 #define REG_A2XX_PA_CL_GB_VERT_CLIP_ADJ 0x00002303 1214 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK 0xffffffff 1215 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT 0 1216 static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val) 1217 { 1218 return ((fui(val)) << A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK; 1219 } 1220 1221 #define REG_A2XX_PA_CL_GB_VERT_DISC_ADJ 0x00002304 1222 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK 0xffffffff 1223 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT 0 1224 static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val) 1225 { 1226 return ((fui(val)) << A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK; 1227 } 1228 1229 #define REG_A2XX_PA_CL_GB_HORZ_CLIP_ADJ 0x00002305 1230 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK 0xffffffff 1231 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT 0 1232 static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val) 1233 { 1234 return ((fui(val)) << A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK; 1235 } 1236 1237 #define REG_A2XX_PA_CL_GB_HORZ_DISC_ADJ 0x00002306 1238 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK 0xffffffff 1239 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT 0 1240 static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val) 1241 { 1242 return ((fui(val)) << A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK; 1243 } 1244 1245 #define REG_A2XX_SQ_VS_CONST 0x00002307 1246 #define A2XX_SQ_VS_CONST_BASE__MASK 0x000001ff 1247 #define A2XX_SQ_VS_CONST_BASE__SHIFT 0 1248 static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val) 1249 { 1250 return ((val) << A2XX_SQ_VS_CONST_BASE__SHIFT) & A2XX_SQ_VS_CONST_BASE__MASK; 1251 } 1252 #define A2XX_SQ_VS_CONST_SIZE__MASK 0x001ff000 1253 #define A2XX_SQ_VS_CONST_SIZE__SHIFT 12 1254 static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val) 1255 { 1256 return ((val) << A2XX_SQ_VS_CONST_SIZE__SHIFT) & A2XX_SQ_VS_CONST_SIZE__MASK; 1257 } 1258 1259 #define REG_A2XX_SQ_PS_CONST 0x00002308 1260 #define A2XX_SQ_PS_CONST_BASE__MASK 0x000001ff 1261 #define A2XX_SQ_PS_CONST_BASE__SHIFT 0 1262 static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val) 1263 { 1264 return ((val) << A2XX_SQ_PS_CONST_BASE__SHIFT) & A2XX_SQ_PS_CONST_BASE__MASK; 1265 } 1266 #define A2XX_SQ_PS_CONST_SIZE__MASK 0x001ff000 1267 #define A2XX_SQ_PS_CONST_SIZE__SHIFT 12 1268 static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val) 1269 { 1270 return ((val) << A2XX_SQ_PS_CONST_SIZE__SHIFT) & A2XX_SQ_PS_CONST_SIZE__MASK; 1271 } 1272 1273 #define REG_A2XX_SQ_DEBUG_MISC_0 0x00002309 1274 1275 #define REG_A2XX_SQ_DEBUG_MISC_1 0x0000230a 1276 1277 #define REG_A2XX_PA_SC_AA_MASK 0x00002312 1278 1279 #define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL 0x00002316 1280 1281 #define REG_A2XX_VGT_OUT_DEALLOC_CNTL 0x00002317 1282 1283 #define REG_A2XX_RB_COPY_CONTROL 0x00002318 1284 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK 0x00000007 1285 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT 0 1286 static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val) 1287 { 1288 return ((val) << A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT) & A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK; 1289 } 1290 #define A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE 0x00000008 1291 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK 0x000000f0 1292 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT 4 1293 static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val) 1294 { 1295 return ((val) << A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT) & A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK; 1296 } 1297 1298 #define REG_A2XX_RB_COPY_DEST_BASE 0x00002319 1299 1300 #define REG_A2XX_RB_COPY_DEST_PITCH 0x0000231a 1301 #define A2XX_RB_COPY_DEST_PITCH__MASK 0xffffffff 1302 #define A2XX_RB_COPY_DEST_PITCH__SHIFT 0 1303 static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val) 1304 { 1305 return ((val >> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK; 1306 } 1307 1308 #define REG_A2XX_RB_COPY_DEST_INFO 0x0000231b 1309 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK 0x00000007 1310 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT 0 1311 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val) 1312 { 1313 return ((val) << A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT) & A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK; 1314 } 1315 #define A2XX_RB_COPY_DEST_INFO_LINEAR 0x00000008 1316 #define A2XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000f0 1317 #define A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 4 1318 static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val) 1319 { 1320 return ((val) << A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A2XX_RB_COPY_DEST_INFO_FORMAT__MASK; 1321 } 1322 #define A2XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 1323 #define A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 1324 static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val) 1325 { 1326 return ((val) << A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A2XX_RB_COPY_DEST_INFO_SWAP__MASK; 1327 } 1328 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 1329 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 1330 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 1331 { 1332 return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 1333 } 1334 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK 0x00003000 1335 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT 12 1336 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val) 1337 { 1338 return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK; 1339 } 1340 #define A2XX_RB_COPY_DEST_INFO_WRITE_RED 0x00004000 1341 #define A2XX_RB_COPY_DEST_INFO_WRITE_GREEN 0x00008000 1342 #define A2XX_RB_COPY_DEST_INFO_WRITE_BLUE 0x00010000 1343 #define A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA 0x00020000 1344 1345 #define REG_A2XX_RB_COPY_DEST_OFFSET 0x0000231c 1346 #define A2XX_RB_COPY_DEST_OFFSET_X__MASK 0x00001fff 1347 #define A2XX_RB_COPY_DEST_OFFSET_X__SHIFT 0 1348 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val) 1349 { 1350 return ((val) << A2XX_RB_COPY_DEST_OFFSET_X__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_X__MASK; 1351 } 1352 #define A2XX_RB_COPY_DEST_OFFSET_Y__MASK 0x03ffe000 1353 #define A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT 13 1354 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val) 1355 { 1356 return ((val) << A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_Y__MASK; 1357 } 1358 1359 #define REG_A2XX_RB_DEPTH_CLEAR 0x0000231d 1360 1361 #define REG_A2XX_RB_SAMPLE_COUNT_CTL 0x00002324 1362 1363 #define REG_A2XX_RB_COLOR_DEST_MASK 0x00002326 1364 1365 #define REG_A2XX_A225_GRAS_UCP0X 0x00002340 1366 1367 #define REG_A2XX_A225_GRAS_UCP5W 0x00002357 1368 1369 #define REG_A2XX_A225_GRAS_UCP_ENABLED 0x00002360 1370 1371 #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE 0x00002380 1372 1373 #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET 0x00002383 1374 1375 #define REG_A2XX_SQ_CONSTANT_0 0x00004000 1376 1377 #define REG_A2XX_SQ_FETCH_0 0x00004800 1378 1379 #define REG_A2XX_SQ_CF_BOOLEANS 0x00004900 1380 1381 #define REG_A2XX_SQ_CF_LOOP 0x00004908 1382 1383 #define REG_A2XX_COHER_SIZE_PM4 0x00000a29 1384 1385 #define REG_A2XX_COHER_BASE_PM4 0x00000a2a 1386 1387 #define REG_A2XX_COHER_STATUS_PM4 0x00000a2b 1388 1389 #define REG_A2XX_SQ_TEX_0 0x00000000 1390 #define A2XX_SQ_TEX_0_CLAMP_X__MASK 0x00001c00 1391 #define A2XX_SQ_TEX_0_CLAMP_X__SHIFT 10 1392 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val) 1393 { 1394 return ((val) << A2XX_SQ_TEX_0_CLAMP_X__SHIFT) & A2XX_SQ_TEX_0_CLAMP_X__MASK; 1395 } 1396 #define A2XX_SQ_TEX_0_CLAMP_Y__MASK 0x0000e000 1397 #define A2XX_SQ_TEX_0_CLAMP_Y__SHIFT 13 1398 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val) 1399 { 1400 return ((val) << A2XX_SQ_TEX_0_CLAMP_Y__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Y__MASK; 1401 } 1402 #define A2XX_SQ_TEX_0_CLAMP_Z__MASK 0x00070000 1403 #define A2XX_SQ_TEX_0_CLAMP_Z__SHIFT 16 1404 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val) 1405 { 1406 return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK; 1407 } 1408 #define A2XX_SQ_TEX_0_PITCH__MASK 0xffc00000 1409 #define A2XX_SQ_TEX_0_PITCH__SHIFT 22 1410 static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val) 1411 { 1412 return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK; 1413 } 1414 1415 #define REG_A2XX_SQ_TEX_1 0x00000001 1416 1417 #define REG_A2XX_SQ_TEX_2 0x00000002 1418 #define A2XX_SQ_TEX_2_WIDTH__MASK 0x00001fff 1419 #define A2XX_SQ_TEX_2_WIDTH__SHIFT 0 1420 static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val) 1421 { 1422 return ((val) << A2XX_SQ_TEX_2_WIDTH__SHIFT) & A2XX_SQ_TEX_2_WIDTH__MASK; 1423 } 1424 #define A2XX_SQ_TEX_2_HEIGHT__MASK 0x03ffe000 1425 #define A2XX_SQ_TEX_2_HEIGHT__SHIFT 13 1426 static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val) 1427 { 1428 return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK; 1429 } 1430 1431 #define REG_A2XX_SQ_TEX_3 0x00000003 1432 #define A2XX_SQ_TEX_3_SWIZ_X__MASK 0x0000000e 1433 #define A2XX_SQ_TEX_3_SWIZ_X__SHIFT 1 1434 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val) 1435 { 1436 return ((val) << A2XX_SQ_TEX_3_SWIZ_X__SHIFT) & A2XX_SQ_TEX_3_SWIZ_X__MASK; 1437 } 1438 #define A2XX_SQ_TEX_3_SWIZ_Y__MASK 0x00000070 1439 #define A2XX_SQ_TEX_3_SWIZ_Y__SHIFT 4 1440 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val) 1441 { 1442 return ((val) << A2XX_SQ_TEX_3_SWIZ_Y__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Y__MASK; 1443 } 1444 #define A2XX_SQ_TEX_3_SWIZ_Z__MASK 0x00000380 1445 #define A2XX_SQ_TEX_3_SWIZ_Z__SHIFT 7 1446 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val) 1447 { 1448 return ((val) << A2XX_SQ_TEX_3_SWIZ_Z__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Z__MASK; 1449 } 1450 #define A2XX_SQ_TEX_3_SWIZ_W__MASK 0x00001c00 1451 #define A2XX_SQ_TEX_3_SWIZ_W__SHIFT 10 1452 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val) 1453 { 1454 return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK; 1455 } 1456 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK 0x00180000 1457 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT 19 1458 static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val) 1459 { 1460 return ((val) << A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK; 1461 } 1462 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK 0x00600000 1463 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT 21 1464 static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val) 1465 { 1466 return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK; 1467 } 1468 1469 1470 #endif /* A2XX_XML */ 1471