xref: /openbmc/linux/drivers/gpu/drm/msm/adreno/a2xx.xml.h (revision 791d3ef2)
1 #ifndef A2XX_XML
2 #define A2XX_XML
3 
4 /* Autogenerated file, DO NOT EDIT manually!
5 
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9 
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    431 bytes, from 2017-05-17 13:21:27)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2017-05-17 13:21:27)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  37162 bytes, from 2017-05-17 13:21:27)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  13324 bytes, from 2017-05-17 13:21:27)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  31866 bytes, from 2017-06-06 18:26:14)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2017-05-17 13:21:27)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 111898 bytes, from 2017-06-06 18:23:59)
18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml          ( 139480 bytes, from 2017-06-16 12:44:39)
19 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2017-05-17 13:21:27)
20 
21 Copyright (C) 2013-2017 by the following authors:
22 - Rob Clark <robdclark@gmail.com> (robclark)
23 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
24 
25 Permission is hereby granted, free of charge, to any person obtaining
26 a copy of this software and associated documentation files (the
27 "Software"), to deal in the Software without restriction, including
28 without limitation the rights to use, copy, modify, merge, publish,
29 distribute, sublicense, and/or sell copies of the Software, and to
30 permit persons to whom the Software is furnished to do so, subject to
31 the following conditions:
32 
33 The above copyright notice and this permission notice (including the
34 next paragraph) shall be included in all copies or substantial
35 portions of the Software.
36 
37 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
39 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
40 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
41 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
42 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
43 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
44 */
45 
46 
47 enum a2xx_rb_dither_type {
48 	DITHER_PIXEL = 0,
49 	DITHER_SUBPIXEL = 1,
50 };
51 
52 enum a2xx_colorformatx {
53 	COLORX_4_4_4_4 = 0,
54 	COLORX_1_5_5_5 = 1,
55 	COLORX_5_6_5 = 2,
56 	COLORX_8 = 3,
57 	COLORX_8_8 = 4,
58 	COLORX_8_8_8_8 = 5,
59 	COLORX_S8_8_8_8 = 6,
60 	COLORX_16_FLOAT = 7,
61 	COLORX_16_16_FLOAT = 8,
62 	COLORX_16_16_16_16_FLOAT = 9,
63 	COLORX_32_FLOAT = 10,
64 	COLORX_32_32_FLOAT = 11,
65 	COLORX_32_32_32_32_FLOAT = 12,
66 	COLORX_2_3_3 = 13,
67 	COLORX_8_8_8 = 14,
68 };
69 
70 enum a2xx_sq_surfaceformat {
71 	FMT_1_REVERSE = 0,
72 	FMT_1 = 1,
73 	FMT_8 = 2,
74 	FMT_1_5_5_5 = 3,
75 	FMT_5_6_5 = 4,
76 	FMT_6_5_5 = 5,
77 	FMT_8_8_8_8 = 6,
78 	FMT_2_10_10_10 = 7,
79 	FMT_8_A = 8,
80 	FMT_8_B = 9,
81 	FMT_8_8 = 10,
82 	FMT_Cr_Y1_Cb_Y0 = 11,
83 	FMT_Y1_Cr_Y0_Cb = 12,
84 	FMT_5_5_5_1 = 13,
85 	FMT_8_8_8_8_A = 14,
86 	FMT_4_4_4_4 = 15,
87 	FMT_10_11_11 = 16,
88 	FMT_11_11_10 = 17,
89 	FMT_DXT1 = 18,
90 	FMT_DXT2_3 = 19,
91 	FMT_DXT4_5 = 20,
92 	FMT_24_8 = 22,
93 	FMT_24_8_FLOAT = 23,
94 	FMT_16 = 24,
95 	FMT_16_16 = 25,
96 	FMT_16_16_16_16 = 26,
97 	FMT_16_EXPAND = 27,
98 	FMT_16_16_EXPAND = 28,
99 	FMT_16_16_16_16_EXPAND = 29,
100 	FMT_16_FLOAT = 30,
101 	FMT_16_16_FLOAT = 31,
102 	FMT_16_16_16_16_FLOAT = 32,
103 	FMT_32 = 33,
104 	FMT_32_32 = 34,
105 	FMT_32_32_32_32 = 35,
106 	FMT_32_FLOAT = 36,
107 	FMT_32_32_FLOAT = 37,
108 	FMT_32_32_32_32_FLOAT = 38,
109 	FMT_32_AS_8 = 39,
110 	FMT_32_AS_8_8 = 40,
111 	FMT_16_MPEG = 41,
112 	FMT_16_16_MPEG = 42,
113 	FMT_8_INTERLACED = 43,
114 	FMT_32_AS_8_INTERLACED = 44,
115 	FMT_32_AS_8_8_INTERLACED = 45,
116 	FMT_16_INTERLACED = 46,
117 	FMT_16_MPEG_INTERLACED = 47,
118 	FMT_16_16_MPEG_INTERLACED = 48,
119 	FMT_DXN = 49,
120 	FMT_8_8_8_8_AS_16_16_16_16 = 50,
121 	FMT_DXT1_AS_16_16_16_16 = 51,
122 	FMT_DXT2_3_AS_16_16_16_16 = 52,
123 	FMT_DXT4_5_AS_16_16_16_16 = 53,
124 	FMT_2_10_10_10_AS_16_16_16_16 = 54,
125 	FMT_10_11_11_AS_16_16_16_16 = 55,
126 	FMT_11_11_10_AS_16_16_16_16 = 56,
127 	FMT_32_32_32_FLOAT = 57,
128 	FMT_DXT3A = 58,
129 	FMT_DXT5A = 59,
130 	FMT_CTX1 = 60,
131 	FMT_DXT3A_AS_1_1_1_1 = 61,
132 };
133 
134 enum a2xx_sq_ps_vtx_mode {
135 	POSITION_1_VECTOR = 0,
136 	POSITION_2_VECTORS_UNUSED = 1,
137 	POSITION_2_VECTORS_SPRITE = 2,
138 	POSITION_2_VECTORS_EDGE = 3,
139 	POSITION_2_VECTORS_KILL = 4,
140 	POSITION_2_VECTORS_SPRITE_KILL = 5,
141 	POSITION_2_VECTORS_EDGE_KILL = 6,
142 	MULTIPASS = 7,
143 };
144 
145 enum a2xx_sq_sample_cntl {
146 	CENTROIDS_ONLY = 0,
147 	CENTERS_ONLY = 1,
148 	CENTROIDS_AND_CENTERS = 2,
149 };
150 
151 enum a2xx_dx_clip_space {
152 	DXCLIP_OPENGL = 0,
153 	DXCLIP_DIRECTX = 1,
154 };
155 
156 enum a2xx_pa_su_sc_polymode {
157 	POLY_DISABLED = 0,
158 	POLY_DUALMODE = 1,
159 };
160 
161 enum a2xx_rb_edram_mode {
162 	EDRAM_NOP = 0,
163 	COLOR_DEPTH = 4,
164 	DEPTH_ONLY = 5,
165 	EDRAM_COPY = 6,
166 };
167 
168 enum a2xx_pa_sc_pattern_bit_order {
169 	LITTLE = 0,
170 	BIG = 1,
171 };
172 
173 enum a2xx_pa_sc_auto_reset_cntl {
174 	NEVER = 0,
175 	EACH_PRIMITIVE = 1,
176 	EACH_PACKET = 2,
177 };
178 
179 enum a2xx_pa_pixcenter {
180 	PIXCENTER_D3D = 0,
181 	PIXCENTER_OGL = 1,
182 };
183 
184 enum a2xx_pa_roundmode {
185 	TRUNCATE = 0,
186 	ROUND = 1,
187 	ROUNDTOEVEN = 2,
188 	ROUNDTOODD = 3,
189 };
190 
191 enum a2xx_pa_quantmode {
192 	ONE_SIXTEENTH = 0,
193 	ONE_EIGTH = 1,
194 	ONE_QUARTER = 2,
195 	ONE_HALF = 3,
196 	ONE = 4,
197 };
198 
199 enum a2xx_rb_copy_sample_select {
200 	SAMPLE_0 = 0,
201 	SAMPLE_1 = 1,
202 	SAMPLE_2 = 2,
203 	SAMPLE_3 = 3,
204 	SAMPLE_01 = 4,
205 	SAMPLE_23 = 5,
206 	SAMPLE_0123 = 6,
207 };
208 
209 enum a2xx_rb_blend_opcode {
210 	BLEND2_DST_PLUS_SRC = 0,
211 	BLEND2_SRC_MINUS_DST = 1,
212 	BLEND2_MIN_DST_SRC = 2,
213 	BLEND2_MAX_DST_SRC = 3,
214 	BLEND2_DST_MINUS_SRC = 4,
215 	BLEND2_DST_PLUS_SRC_BIAS = 5,
216 };
217 
218 enum adreno_mmu_clnt_beh {
219 	BEH_NEVR = 0,
220 	BEH_TRAN_RNG = 1,
221 	BEH_TRAN_FLT = 2,
222 };
223 
224 enum sq_tex_clamp {
225 	SQ_TEX_WRAP = 0,
226 	SQ_TEX_MIRROR = 1,
227 	SQ_TEX_CLAMP_LAST_TEXEL = 2,
228 	SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3,
229 	SQ_TEX_CLAMP_HALF_BORDER = 4,
230 	SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5,
231 	SQ_TEX_CLAMP_BORDER = 6,
232 	SQ_TEX_MIRROR_ONCE_BORDER = 7,
233 };
234 
235 enum sq_tex_swiz {
236 	SQ_TEX_X = 0,
237 	SQ_TEX_Y = 1,
238 	SQ_TEX_Z = 2,
239 	SQ_TEX_W = 3,
240 	SQ_TEX_ZERO = 4,
241 	SQ_TEX_ONE = 5,
242 };
243 
244 enum sq_tex_filter {
245 	SQ_TEX_FILTER_POINT = 0,
246 	SQ_TEX_FILTER_BILINEAR = 1,
247 	SQ_TEX_FILTER_BICUBIC = 2,
248 };
249 
250 #define REG_A2XX_RBBM_PATCH_RELEASE				0x00000001
251 
252 #define REG_A2XX_RBBM_CNTL					0x0000003b
253 
254 #define REG_A2XX_RBBM_SOFT_RESET				0x0000003c
255 
256 #define REG_A2XX_CP_PFP_UCODE_ADDR				0x000000c0
257 
258 #define REG_A2XX_CP_PFP_UCODE_DATA				0x000000c1
259 
260 #define REG_A2XX_MH_MMU_CONFIG					0x00000040
261 #define A2XX_MH_MMU_CONFIG_MMU_ENABLE				0x00000001
262 #define A2XX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE			0x00000002
263 #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK		0x00000030
264 #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT		4
265 static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
266 {
267 	return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK;
268 }
269 #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK		0x000000c0
270 #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT		6
271 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
272 {
273 	return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK;
274 }
275 #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK		0x00000300
276 #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT		8
277 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
278 {
279 	return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK;
280 }
281 #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK		0x00000c00
282 #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT		10
283 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
284 {
285 	return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK;
286 }
287 #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK		0x00003000
288 #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT		12
289 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
290 {
291 	return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK;
292 }
293 #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK		0x0000c000
294 #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT		14
295 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
296 {
297 	return ((val) << A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK;
298 }
299 #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK		0x00030000
300 #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT		16
301 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
302 {
303 	return ((val) << A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK;
304 }
305 #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK		0x000c0000
306 #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT		18
307 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
308 {
309 	return ((val) << A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK;
310 }
311 #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK		0x00300000
312 #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT		20
313 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
314 {
315 	return ((val) << A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK;
316 }
317 #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK		0x00c00000
318 #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT		22
319 static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
320 {
321 	return ((val) << A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK;
322 }
323 #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK		0x03000000
324 #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT		24
325 static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
326 {
327 	return ((val) << A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK;
328 }
329 
330 #define REG_A2XX_MH_MMU_VA_RANGE				0x00000041
331 
332 #define REG_A2XX_MH_MMU_PT_BASE					0x00000042
333 
334 #define REG_A2XX_MH_MMU_PAGE_FAULT				0x00000043
335 
336 #define REG_A2XX_MH_MMU_TRAN_ERROR				0x00000044
337 
338 #define REG_A2XX_MH_MMU_INVALIDATE				0x00000045
339 
340 #define REG_A2XX_MH_MMU_MPU_BASE				0x00000046
341 
342 #define REG_A2XX_MH_MMU_MPU_END					0x00000047
343 
344 #define REG_A2XX_NQWAIT_UNTIL					0x00000394
345 
346 #define REG_A2XX_RBBM_PERFCOUNTER1_SELECT			0x00000395
347 
348 #define REG_A2XX_RBBM_PERFCOUNTER1_LO				0x00000397
349 
350 #define REG_A2XX_RBBM_PERFCOUNTER1_HI				0x00000398
351 
352 #define REG_A2XX_RBBM_DEBUG					0x0000039b
353 
354 #define REG_A2XX_RBBM_PM_OVERRIDE1				0x0000039c
355 #define A2XX_RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE		0x00000001
356 #define A2XX_RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE		0x00000002
357 #define A2XX_RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE		0x00000004
358 #define A2XX_RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE		0x00000008
359 #define A2XX_RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE		0x00000010
360 #define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE		0x00000020
361 #define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE	0x00000040
362 #define A2XX_RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE	0x00000080
363 #define A2XX_RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE		0x00000100
364 #define A2XX_RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE		0x00000200
365 #define A2XX_RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE		0x00000400
366 #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE		0x00000800
367 #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE		0x00001000
368 #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE		0x00002000
369 #define A2XX_RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE		0x00004000
370 #define A2XX_RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE		0x00008000
371 #define A2XX_RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE		0x00010000
372 #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE		0x00020000
373 #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE		0x00040000
374 #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE	0x00080000
375 #define A2XX_RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE		0x00100000
376 #define A2XX_RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE		0x00200000
377 #define A2XX_RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE		0x00400000
378 #define A2XX_RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE		0x00800000
379 #define A2XX_RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE	0x01000000
380 #define A2XX_RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE		0x02000000
381 #define A2XX_RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE		0x04000000
382 #define A2XX_RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE		0x08000000
383 #define A2XX_RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE		0x10000000
384 #define A2XX_RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE		0x20000000
385 #define A2XX_RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE		0x40000000
386 #define A2XX_RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE	0x80000000
387 
388 #define REG_A2XX_RBBM_PM_OVERRIDE2				0x0000039d
389 
390 #define REG_A2XX_RBBM_DEBUG_OUT					0x000003a0
391 
392 #define REG_A2XX_RBBM_DEBUG_CNTL				0x000003a1
393 
394 #define REG_A2XX_RBBM_READ_ERROR				0x000003b3
395 
396 #define REG_A2XX_RBBM_INT_CNTL					0x000003b4
397 
398 #define REG_A2XX_RBBM_INT_STATUS				0x000003b5
399 
400 #define REG_A2XX_RBBM_INT_ACK					0x000003b6
401 
402 #define REG_A2XX_MASTER_INT_SIGNAL				0x000003b7
403 
404 #define REG_A2XX_RBBM_PERIPHID1					0x000003f9
405 
406 #define REG_A2XX_RBBM_PERIPHID2					0x000003fa
407 
408 #define REG_A2XX_CP_PERFMON_CNTL				0x00000444
409 
410 #define REG_A2XX_CP_PERFCOUNTER_SELECT				0x00000445
411 
412 #define REG_A2XX_CP_PERFCOUNTER_LO				0x00000446
413 
414 #define REG_A2XX_CP_PERFCOUNTER_HI				0x00000447
415 
416 #define REG_A2XX_RBBM_STATUS					0x000005d0
417 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK			0x0000001f
418 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT			0
419 static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val)
420 {
421 	return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK;
422 }
423 #define A2XX_RBBM_STATUS_TC_BUSY				0x00000020
424 #define A2XX_RBBM_STATUS_HIRQ_PENDING				0x00000100
425 #define A2XX_RBBM_STATUS_CPRQ_PENDING				0x00000200
426 #define A2XX_RBBM_STATUS_CFRQ_PENDING				0x00000400
427 #define A2XX_RBBM_STATUS_PFRQ_PENDING				0x00000800
428 #define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA			0x00001000
429 #define A2XX_RBBM_STATUS_RBBM_WU_BUSY				0x00004000
430 #define A2XX_RBBM_STATUS_CP_NRT_BUSY				0x00010000
431 #define A2XX_RBBM_STATUS_MH_BUSY				0x00040000
432 #define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY			0x00080000
433 #define A2XX_RBBM_STATUS_SX_BUSY				0x00200000
434 #define A2XX_RBBM_STATUS_TPC_BUSY				0x00400000
435 #define A2XX_RBBM_STATUS_SC_CNTX_BUSY				0x01000000
436 #define A2XX_RBBM_STATUS_PA_BUSY				0x02000000
437 #define A2XX_RBBM_STATUS_VGT_BUSY				0x04000000
438 #define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY				0x08000000
439 #define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY				0x10000000
440 #define A2XX_RBBM_STATUS_RB_CNTX_BUSY				0x40000000
441 #define A2XX_RBBM_STATUS_GUI_ACTIVE				0x80000000
442 
443 #define REG_A2XX_MH_ARBITER_CONFIG				0x00000a40
444 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK		0x0000003f
445 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT		0
446 static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val)
447 {
448 	return ((val) << A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK;
449 }
450 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY		0x00000040
451 #define A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE			0x00000080
452 #define A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE		0x00000100
453 #define A2XX_MH_ARBITER_CONFIG_L2_ARB_CONTROL			0x00000200
454 #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK			0x00001c00
455 #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT			10
456 static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val)
457 {
458 	return ((val) << A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT) & A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK;
459 }
460 #define A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE		0x00002000
461 #define A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE		0x00004000
462 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE		0x00008000
463 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK		0x003f0000
464 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT		16
465 static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val)
466 {
467 	return ((val) << A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK;
468 }
469 #define A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE			0x00400000
470 #define A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE			0x00800000
471 #define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE			0x01000000
472 #define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE			0x02000000
473 #define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE			0x04000000
474 
475 #define REG_A2XX_A220_VSC_BIN_SIZE				0x00000c01
476 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK			0x0000001f
477 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT			0
478 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val)
479 {
480 	return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK;
481 }
482 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK			0x000003e0
483 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT			5
484 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val)
485 {
486 	return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK;
487 }
488 
489 static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
490 
491 static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
492 
493 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; }
494 
495 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; }
496 
497 #define REG_A2XX_PC_DEBUG_CNTL					0x00000c38
498 
499 #define REG_A2XX_PC_DEBUG_DATA					0x00000c39
500 
501 #define REG_A2XX_PA_SC_VIZ_QUERY_STATUS				0x00000c44
502 
503 #define REG_A2XX_GRAS_DEBUG_CNTL				0x00000c80
504 
505 #define REG_A2XX_PA_SU_DEBUG_CNTL				0x00000c80
506 
507 #define REG_A2XX_GRAS_DEBUG_DATA				0x00000c81
508 
509 #define REG_A2XX_PA_SU_DEBUG_DATA				0x00000c81
510 
511 #define REG_A2XX_PA_SU_FACE_DATA				0x00000c86
512 #define A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK			0xffffffe0
513 #define A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT			5
514 static inline uint32_t A2XX_PA_SU_FACE_DATA_BASE_ADDR(uint32_t val)
515 {
516 	return ((val) << A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT) & A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK;
517 }
518 
519 #define REG_A2XX_SQ_GPR_MANAGEMENT				0x00000d00
520 #define A2XX_SQ_GPR_MANAGEMENT_REG_DYNAMIC			0x00000001
521 #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK		0x00000ff0
522 #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT		4
523 static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX(uint32_t val)
524 {
525 	return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK;
526 }
527 #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK		0x000ff000
528 #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT		12
529 static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX(uint32_t val)
530 {
531 	return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK;
532 }
533 
534 #define REG_A2XX_SQ_FLOW_CONTROL				0x00000d01
535 
536 #define REG_A2XX_SQ_INST_STORE_MANAGMENT			0x00000d02
537 #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK	0x00000fff
538 #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT	0
539 static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX(uint32_t val)
540 {
541 	return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK;
542 }
543 #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK	0x0fff0000
544 #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT	16
545 static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX(uint32_t val)
546 {
547 	return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK;
548 }
549 
550 #define REG_A2XX_SQ_DEBUG_MISC					0x00000d05
551 
552 #define REG_A2XX_SQ_INT_CNTL					0x00000d34
553 
554 #define REG_A2XX_SQ_INT_STATUS					0x00000d35
555 
556 #define REG_A2XX_SQ_INT_ACK					0x00000d36
557 
558 #define REG_A2XX_SQ_DEBUG_INPUT_FSM				0x00000dae
559 
560 #define REG_A2XX_SQ_DEBUG_CONST_MGR_FSM				0x00000daf
561 
562 #define REG_A2XX_SQ_DEBUG_TP_FSM				0x00000db0
563 
564 #define REG_A2XX_SQ_DEBUG_FSM_ALU_0				0x00000db1
565 
566 #define REG_A2XX_SQ_DEBUG_FSM_ALU_1				0x00000db2
567 
568 #define REG_A2XX_SQ_DEBUG_EXP_ALLOC				0x00000db3
569 
570 #define REG_A2XX_SQ_DEBUG_PTR_BUFF				0x00000db4
571 
572 #define REG_A2XX_SQ_DEBUG_GPR_VTX				0x00000db5
573 
574 #define REG_A2XX_SQ_DEBUG_GPR_PIX				0x00000db6
575 
576 #define REG_A2XX_SQ_DEBUG_TB_STATUS_SEL				0x00000db7
577 
578 #define REG_A2XX_SQ_DEBUG_VTX_TB_0				0x00000db8
579 
580 #define REG_A2XX_SQ_DEBUG_VTX_TB_1				0x00000db9
581 
582 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG			0x00000dba
583 
584 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM			0x00000dbb
585 
586 #define REG_A2XX_SQ_DEBUG_PIX_TB_0				0x00000dbc
587 
588 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0			0x00000dbd
589 
590 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1			0x00000dbe
591 
592 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2			0x00000dbf
593 
594 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3			0x00000dc0
595 
596 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM			0x00000dc1
597 
598 #define REG_A2XX_TC_CNTL_STATUS					0x00000e00
599 #define A2XX_TC_CNTL_STATUS_L2_INVALIDATE			0x00000001
600 
601 #define REG_A2XX_TP0_CHICKEN					0x00000e1e
602 
603 #define REG_A2XX_RB_BC_CONTROL					0x00000f01
604 #define A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE		0x00000001
605 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK		0x00000006
606 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT		1
607 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val)
608 {
609 	return ((val) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK;
610 }
611 #define A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM			0x00000008
612 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH	0x00000010
613 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP		0x00000020
614 #define A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP		0x00000040
615 #define A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE			0x00000080
616 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK		0x00001f00
617 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT		8
618 static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val)
619 {
620 	return ((val) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK;
621 }
622 #define A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE			0x00004000
623 #define A2XX_RB_BC_CONTROL_CRC_MODE				0x00008000
624 #define A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS		0x00010000
625 #define A2XX_RB_BC_CONTROL_DISABLE_ACCUM			0x00020000
626 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK		0x003c0000
627 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT		18
628 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val)
629 {
630 	return ((val) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK;
631 }
632 #define A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE		0x00400000
633 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK		0x07800000
634 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT		23
635 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val)
636 {
637 	return ((val) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK;
638 }
639 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK	0x18000000
640 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT	27
641 static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val)
642 {
643 	return ((val) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK;
644 }
645 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE	0x20000000
646 #define A2XX_RB_BC_CONTROL_CRC_SYSTEM				0x40000000
647 #define A2XX_RB_BC_CONTROL_RESERVED6				0x80000000
648 
649 #define REG_A2XX_RB_EDRAM_INFO					0x00000f02
650 
651 #define REG_A2XX_RB_DEBUG_CNTL					0x00000f26
652 
653 #define REG_A2XX_RB_DEBUG_DATA					0x00000f27
654 
655 #define REG_A2XX_RB_SURFACE_INFO				0x00002000
656 
657 #define REG_A2XX_RB_COLOR_INFO					0x00002001
658 #define A2XX_RB_COLOR_INFO_FORMAT__MASK				0x0000000f
659 #define A2XX_RB_COLOR_INFO_FORMAT__SHIFT			0
660 static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val)
661 {
662 	return ((val) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT) & A2XX_RB_COLOR_INFO_FORMAT__MASK;
663 }
664 #define A2XX_RB_COLOR_INFO_ROUND_MODE__MASK			0x00000030
665 #define A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT			4
666 static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val)
667 {
668 	return ((val) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK;
669 }
670 #define A2XX_RB_COLOR_INFO_LINEAR				0x00000040
671 #define A2XX_RB_COLOR_INFO_ENDIAN__MASK				0x00000180
672 #define A2XX_RB_COLOR_INFO_ENDIAN__SHIFT			7
673 static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val)
674 {
675 	return ((val) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT) & A2XX_RB_COLOR_INFO_ENDIAN__MASK;
676 }
677 #define A2XX_RB_COLOR_INFO_SWAP__MASK				0x00000600
678 #define A2XX_RB_COLOR_INFO_SWAP__SHIFT				9
679 static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val)
680 {
681 	return ((val) << A2XX_RB_COLOR_INFO_SWAP__SHIFT) & A2XX_RB_COLOR_INFO_SWAP__MASK;
682 }
683 #define A2XX_RB_COLOR_INFO_BASE__MASK				0xfffff000
684 #define A2XX_RB_COLOR_INFO_BASE__SHIFT				12
685 static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val)
686 {
687 	return ((val >> 10) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK;
688 }
689 
690 #define REG_A2XX_RB_DEPTH_INFO					0x00002002
691 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK			0x00000001
692 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT			0
693 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val)
694 {
695 	return ((val) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
696 }
697 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK			0xfffff000
698 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT			12
699 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
700 {
701 	return ((val >> 10) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
702 }
703 
704 #define REG_A2XX_A225_RB_COLOR_INFO3				0x00002005
705 
706 #define REG_A2XX_COHER_DEST_BASE_0				0x00002006
707 
708 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_TL			0x0000200e
709 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE	0x80000000
710 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK			0x00007fff
711 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT			0
712 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
713 {
714 	return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK;
715 }
716 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK			0x7fff0000
717 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT			16
718 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
719 {
720 	return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK;
721 }
722 
723 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_BR			0x0000200f
724 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE	0x80000000
725 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK			0x00007fff
726 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT			0
727 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
728 {
729 	return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK;
730 }
731 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK			0x7fff0000
732 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT			16
733 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
734 {
735 	return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK;
736 }
737 
738 #define REG_A2XX_PA_SC_WINDOW_OFFSET				0x00002080
739 #define A2XX_PA_SC_WINDOW_OFFSET_X__MASK			0x00007fff
740 #define A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT			0
741 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val)
742 {
743 	return ((val) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK;
744 }
745 #define A2XX_PA_SC_WINDOW_OFFSET_Y__MASK			0x7fff0000
746 #define A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT			16
747 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val)
748 {
749 	return ((val) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK;
750 }
751 #define A2XX_PA_SC_WINDOW_OFFSET_DISABLE			0x80000000
752 
753 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_TL			0x00002081
754 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE	0x80000000
755 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK			0x00007fff
756 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT			0
757 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
758 {
759 	return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK;
760 }
761 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK			0x7fff0000
762 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT			16
763 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
764 {
765 	return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK;
766 }
767 
768 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_BR			0x00002082
769 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE	0x80000000
770 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK			0x00007fff
771 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT			0
772 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
773 {
774 	return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK;
775 }
776 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK			0x7fff0000
777 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT			16
778 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
779 {
780 	return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK;
781 }
782 
783 #define REG_A2XX_UNKNOWN_2010					0x00002010
784 
785 #define REG_A2XX_VGT_MAX_VTX_INDX				0x00002100
786 
787 #define REG_A2XX_VGT_MIN_VTX_INDX				0x00002101
788 
789 #define REG_A2XX_VGT_INDX_OFFSET				0x00002102
790 
791 #define REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX		0x00002103
792 
793 #define REG_A2XX_RB_COLOR_MASK					0x00002104
794 #define A2XX_RB_COLOR_MASK_WRITE_RED				0x00000001
795 #define A2XX_RB_COLOR_MASK_WRITE_GREEN				0x00000002
796 #define A2XX_RB_COLOR_MASK_WRITE_BLUE				0x00000004
797 #define A2XX_RB_COLOR_MASK_WRITE_ALPHA				0x00000008
798 
799 #define REG_A2XX_RB_BLEND_RED					0x00002105
800 
801 #define REG_A2XX_RB_BLEND_GREEN					0x00002106
802 
803 #define REG_A2XX_RB_BLEND_BLUE					0x00002107
804 
805 #define REG_A2XX_RB_BLEND_ALPHA					0x00002108
806 
807 #define REG_A2XX_RB_FOG_COLOR					0x00002109
808 #define A2XX_RB_FOG_COLOR_FOG_RED__MASK				0x000000ff
809 #define A2XX_RB_FOG_COLOR_FOG_RED__SHIFT			0
810 static inline uint32_t A2XX_RB_FOG_COLOR_FOG_RED(uint32_t val)
811 {
812 	return ((val) << A2XX_RB_FOG_COLOR_FOG_RED__SHIFT) & A2XX_RB_FOG_COLOR_FOG_RED__MASK;
813 }
814 #define A2XX_RB_FOG_COLOR_FOG_GREEN__MASK			0x0000ff00
815 #define A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT			8
816 static inline uint32_t A2XX_RB_FOG_COLOR_FOG_GREEN(uint32_t val)
817 {
818 	return ((val) << A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT) & A2XX_RB_FOG_COLOR_FOG_GREEN__MASK;
819 }
820 #define A2XX_RB_FOG_COLOR_FOG_BLUE__MASK			0x00ff0000
821 #define A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT			16
822 static inline uint32_t A2XX_RB_FOG_COLOR_FOG_BLUE(uint32_t val)
823 {
824 	return ((val) << A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT) & A2XX_RB_FOG_COLOR_FOG_BLUE__MASK;
825 }
826 
827 #define REG_A2XX_RB_STENCILREFMASK_BF				0x0000210c
828 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK		0x000000ff
829 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT		0
830 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
831 {
832 	return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
833 }
834 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK		0x0000ff00
835 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT		8
836 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
837 {
838 	return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
839 }
840 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK	0x00ff0000
841 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT	16
842 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
843 {
844 	return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
845 }
846 
847 #define REG_A2XX_RB_STENCILREFMASK				0x0000210d
848 #define A2XX_RB_STENCILREFMASK_STENCILREF__MASK			0x000000ff
849 #define A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT		0
850 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
851 {
852 	return ((val) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK;
853 }
854 #define A2XX_RB_STENCILREFMASK_STENCILMASK__MASK		0x0000ff00
855 #define A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT		8
856 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
857 {
858 	return ((val) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK;
859 }
860 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK		0x00ff0000
861 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT		16
862 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
863 {
864 	return ((val) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
865 }
866 
867 #define REG_A2XX_RB_ALPHA_REF					0x0000210e
868 
869 #define REG_A2XX_PA_CL_VPORT_XSCALE				0x0000210f
870 #define A2XX_PA_CL_VPORT_XSCALE__MASK				0xffffffff
871 #define A2XX_PA_CL_VPORT_XSCALE__SHIFT				0
872 static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val)
873 {
874 	return ((fui(val)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT) & A2XX_PA_CL_VPORT_XSCALE__MASK;
875 }
876 
877 #define REG_A2XX_PA_CL_VPORT_XOFFSET				0x00002110
878 #define A2XX_PA_CL_VPORT_XOFFSET__MASK				0xffffffff
879 #define A2XX_PA_CL_VPORT_XOFFSET__SHIFT				0
880 static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val)
881 {
882 	return ((fui(val)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT) & A2XX_PA_CL_VPORT_XOFFSET__MASK;
883 }
884 
885 #define REG_A2XX_PA_CL_VPORT_YSCALE				0x00002111
886 #define A2XX_PA_CL_VPORT_YSCALE__MASK				0xffffffff
887 #define A2XX_PA_CL_VPORT_YSCALE__SHIFT				0
888 static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val)
889 {
890 	return ((fui(val)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT) & A2XX_PA_CL_VPORT_YSCALE__MASK;
891 }
892 
893 #define REG_A2XX_PA_CL_VPORT_YOFFSET				0x00002112
894 #define A2XX_PA_CL_VPORT_YOFFSET__MASK				0xffffffff
895 #define A2XX_PA_CL_VPORT_YOFFSET__SHIFT				0
896 static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val)
897 {
898 	return ((fui(val)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT) & A2XX_PA_CL_VPORT_YOFFSET__MASK;
899 }
900 
901 #define REG_A2XX_PA_CL_VPORT_ZSCALE				0x00002113
902 #define A2XX_PA_CL_VPORT_ZSCALE__MASK				0xffffffff
903 #define A2XX_PA_CL_VPORT_ZSCALE__SHIFT				0
904 static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val)
905 {
906 	return ((fui(val)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT) & A2XX_PA_CL_VPORT_ZSCALE__MASK;
907 }
908 
909 #define REG_A2XX_PA_CL_VPORT_ZOFFSET				0x00002114
910 #define A2XX_PA_CL_VPORT_ZOFFSET__MASK				0xffffffff
911 #define A2XX_PA_CL_VPORT_ZOFFSET__SHIFT				0
912 static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val)
913 {
914 	return ((fui(val)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT) & A2XX_PA_CL_VPORT_ZOFFSET__MASK;
915 }
916 
917 #define REG_A2XX_SQ_PROGRAM_CNTL				0x00002180
918 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK			0x000000ff
919 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT			0
920 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val)
921 {
922 	return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK;
923 }
924 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK			0x0000ff00
925 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT			8
926 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val)
927 {
928 	return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK;
929 }
930 #define A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE			0x00010000
931 #define A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE			0x00020000
932 #define A2XX_SQ_PROGRAM_CNTL_PARAM_GEN				0x00040000
933 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX			0x00080000
934 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK		0x00f00000
935 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT		20
936 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val)
937 {
938 	return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK;
939 }
940 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK		0x07000000
941 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT		24
942 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val)
943 {
944 	return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK;
945 }
946 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK		0x78000000
947 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT		27
948 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val)
949 {
950 	return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK;
951 }
952 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX			0x80000000
953 
954 #define REG_A2XX_SQ_CONTEXT_MISC				0x00002181
955 #define A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE			0x00000001
956 #define A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY		0x00000002
957 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK		0x0000000c
958 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT		2
959 static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val)
960 {
961 	return ((val) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK;
962 }
963 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK		0x0000ff00
964 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT		8
965 static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val)
966 {
967 	return ((val) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK;
968 }
969 #define A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF			0x00010000
970 #define A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE			0x00020000
971 #define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL			0x00040000
972 
973 #define REG_A2XX_SQ_INTERPOLATOR_CNTL				0x00002182
974 #define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK		0x0000ffff
975 #define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT		0
976 static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE(uint32_t val)
977 {
978 	return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK;
979 }
980 #define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK	0xffff0000
981 #define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT	16
982 static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN(uint32_t val)
983 {
984 	return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK;
985 }
986 
987 #define REG_A2XX_SQ_WRAPPING_0					0x00002183
988 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK			0x0000000f
989 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT			0
990 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_0(uint32_t val)
991 {
992 	return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK;
993 }
994 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK			0x000000f0
995 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT			4
996 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_1(uint32_t val)
997 {
998 	return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK;
999 }
1000 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK			0x00000f00
1001 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT			8
1002 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_2(uint32_t val)
1003 {
1004 	return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK;
1005 }
1006 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK			0x0000f000
1007 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT			12
1008 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_3(uint32_t val)
1009 {
1010 	return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK;
1011 }
1012 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK			0x000f0000
1013 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT			16
1014 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_4(uint32_t val)
1015 {
1016 	return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK;
1017 }
1018 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK			0x00f00000
1019 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT			20
1020 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_5(uint32_t val)
1021 {
1022 	return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK;
1023 }
1024 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK			0x0f000000
1025 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT			24
1026 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_6(uint32_t val)
1027 {
1028 	return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK;
1029 }
1030 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK			0xf0000000
1031 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT			28
1032 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_7(uint32_t val)
1033 {
1034 	return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK;
1035 }
1036 
1037 #define REG_A2XX_SQ_WRAPPING_1					0x00002184
1038 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK			0x0000000f
1039 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT			0
1040 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_8(uint32_t val)
1041 {
1042 	return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK;
1043 }
1044 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK			0x000000f0
1045 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT			4
1046 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_9(uint32_t val)
1047 {
1048 	return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK;
1049 }
1050 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK			0x00000f00
1051 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT			8
1052 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_10(uint32_t val)
1053 {
1054 	return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK;
1055 }
1056 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK			0x0000f000
1057 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT			12
1058 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_11(uint32_t val)
1059 {
1060 	return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK;
1061 }
1062 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK			0x000f0000
1063 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT			16
1064 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_12(uint32_t val)
1065 {
1066 	return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK;
1067 }
1068 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK			0x00f00000
1069 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT			20
1070 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_13(uint32_t val)
1071 {
1072 	return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK;
1073 }
1074 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK			0x0f000000
1075 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT			24
1076 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_14(uint32_t val)
1077 {
1078 	return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK;
1079 }
1080 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK			0xf0000000
1081 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT			28
1082 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_15(uint32_t val)
1083 {
1084 	return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK;
1085 }
1086 
1087 #define REG_A2XX_SQ_PS_PROGRAM					0x000021f6
1088 #define A2XX_SQ_PS_PROGRAM_BASE__MASK				0x00000fff
1089 #define A2XX_SQ_PS_PROGRAM_BASE__SHIFT				0
1090 static inline uint32_t A2XX_SQ_PS_PROGRAM_BASE(uint32_t val)
1091 {
1092 	return ((val) << A2XX_SQ_PS_PROGRAM_BASE__SHIFT) & A2XX_SQ_PS_PROGRAM_BASE__MASK;
1093 }
1094 #define A2XX_SQ_PS_PROGRAM_SIZE__MASK				0x00fff000
1095 #define A2XX_SQ_PS_PROGRAM_SIZE__SHIFT				12
1096 static inline uint32_t A2XX_SQ_PS_PROGRAM_SIZE(uint32_t val)
1097 {
1098 	return ((val) << A2XX_SQ_PS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_PS_PROGRAM_SIZE__MASK;
1099 }
1100 
1101 #define REG_A2XX_SQ_VS_PROGRAM					0x000021f7
1102 #define A2XX_SQ_VS_PROGRAM_BASE__MASK				0x00000fff
1103 #define A2XX_SQ_VS_PROGRAM_BASE__SHIFT				0
1104 static inline uint32_t A2XX_SQ_VS_PROGRAM_BASE(uint32_t val)
1105 {
1106 	return ((val) << A2XX_SQ_VS_PROGRAM_BASE__SHIFT) & A2XX_SQ_VS_PROGRAM_BASE__MASK;
1107 }
1108 #define A2XX_SQ_VS_PROGRAM_SIZE__MASK				0x00fff000
1109 #define A2XX_SQ_VS_PROGRAM_SIZE__SHIFT				12
1110 static inline uint32_t A2XX_SQ_VS_PROGRAM_SIZE(uint32_t val)
1111 {
1112 	return ((val) << A2XX_SQ_VS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_VS_PROGRAM_SIZE__MASK;
1113 }
1114 
1115 #define REG_A2XX_VGT_EVENT_INITIATOR				0x000021f9
1116 
1117 #define REG_A2XX_VGT_DRAW_INITIATOR				0x000021fc
1118 #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK			0x0000003f
1119 #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT		0
1120 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
1121 {
1122 	return ((val) << A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK;
1123 }
1124 #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK		0x000000c0
1125 #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT		6
1126 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
1127 {
1128 	return ((val) << A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK;
1129 }
1130 #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK			0x00000600
1131 #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT			9
1132 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
1133 {
1134 	return ((val) << A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK;
1135 }
1136 #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK		0x00000800
1137 #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT		11
1138 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val)
1139 {
1140 	return ((val) << A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK;
1141 }
1142 #define A2XX_VGT_DRAW_INITIATOR_NOT_EOP				0x00001000
1143 #define A2XX_VGT_DRAW_INITIATOR_SMALL_INDEX			0x00002000
1144 #define A2XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE	0x00004000
1145 #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK		0xff000000
1146 #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT		24
1147 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val)
1148 {
1149 	return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK;
1150 }
1151 
1152 #define REG_A2XX_VGT_IMMED_DATA					0x000021fd
1153 
1154 #define REG_A2XX_RB_DEPTHCONTROL				0x00002200
1155 #define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE			0x00000001
1156 #define A2XX_RB_DEPTHCONTROL_Z_ENABLE				0x00000002
1157 #define A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE			0x00000004
1158 #define A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE			0x00000008
1159 #define A2XX_RB_DEPTHCONTROL_ZFUNC__MASK			0x00000070
1160 #define A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT			4
1161 static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val)
1162 {
1163 	return ((val) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK;
1164 }
1165 #define A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE			0x00000080
1166 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK			0x00000700
1167 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT			8
1168 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val)
1169 {
1170 	return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK;
1171 }
1172 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK			0x00003800
1173 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT			11
1174 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val)
1175 {
1176 	return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK;
1177 }
1178 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK			0x0001c000
1179 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT		14
1180 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val)
1181 {
1182 	return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK;
1183 }
1184 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK			0x000e0000
1185 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT		17
1186 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val)
1187 {
1188 	return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK;
1189 }
1190 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK		0x00700000
1191 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT		20
1192 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val)
1193 {
1194 	return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK;
1195 }
1196 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK		0x03800000
1197 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT		23
1198 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val)
1199 {
1200 	return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK;
1201 }
1202 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK		0x1c000000
1203 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT		26
1204 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val)
1205 {
1206 	return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK;
1207 }
1208 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK		0xe0000000
1209 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT		29
1210 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val)
1211 {
1212 	return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK;
1213 }
1214 
1215 #define REG_A2XX_RB_BLEND_CONTROL				0x00002201
1216 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK		0x0000001f
1217 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT		0
1218 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val)
1219 {
1220 	return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK;
1221 }
1222 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK		0x000000e0
1223 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT		5
1224 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val)
1225 {
1226 	return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK;
1227 }
1228 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK		0x00001f00
1229 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT		8
1230 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val)
1231 {
1232 	return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK;
1233 }
1234 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK		0x001f0000
1235 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT		16
1236 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val)
1237 {
1238 	return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK;
1239 }
1240 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK		0x00e00000
1241 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT		21
1242 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val)
1243 {
1244 	return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK;
1245 }
1246 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK		0x1f000000
1247 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT		24
1248 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val)
1249 {
1250 	return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK;
1251 }
1252 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE		0x20000000
1253 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE			0x40000000
1254 
1255 #define REG_A2XX_RB_COLORCONTROL				0x00002202
1256 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK			0x00000007
1257 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT			0
1258 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val)
1259 {
1260 	return ((val) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK;
1261 }
1262 #define A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE			0x00000008
1263 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE		0x00000010
1264 #define A2XX_RB_COLORCONTROL_BLEND_DISABLE			0x00000020
1265 #define A2XX_RB_COLORCONTROL_VOB_ENABLE				0x00000040
1266 #define A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG			0x00000080
1267 #define A2XX_RB_COLORCONTROL_ROP_CODE__MASK			0x00000f00
1268 #define A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT			8
1269 static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val)
1270 {
1271 	return ((val) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK;
1272 }
1273 #define A2XX_RB_COLORCONTROL_DITHER_MODE__MASK			0x00003000
1274 #define A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT			12
1275 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val)
1276 {
1277 	return ((val) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK;
1278 }
1279 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK			0x0000c000
1280 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT			14
1281 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val)
1282 {
1283 	return ((val) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK;
1284 }
1285 #define A2XX_RB_COLORCONTROL_PIXEL_FOG				0x00010000
1286 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK	0x03000000
1287 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT	24
1288 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val)
1289 {
1290 	return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK;
1291 }
1292 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK	0x0c000000
1293 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT	26
1294 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val)
1295 {
1296 	return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK;
1297 }
1298 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK	0x30000000
1299 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT	28
1300 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val)
1301 {
1302 	return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK;
1303 }
1304 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK	0xc0000000
1305 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT	30
1306 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val)
1307 {
1308 	return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK;
1309 }
1310 
1311 #define REG_A2XX_VGT_CURRENT_BIN_ID_MAX				0x00002203
1312 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK		0x00000007
1313 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT		0
1314 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val)
1315 {
1316 	return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK;
1317 }
1318 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK			0x00000038
1319 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT			3
1320 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val)
1321 {
1322 	return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK;
1323 }
1324 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK	0x000001c0
1325 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT	6
1326 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val)
1327 {
1328 	return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK;
1329 }
1330 
1331 #define REG_A2XX_PA_CL_CLIP_CNTL				0x00002204
1332 #define A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE			0x00010000
1333 #define A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA		0x00040000
1334 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK		0x00080000
1335 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT		19
1336 static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val)
1337 {
1338 	return ((val) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK;
1339 }
1340 #define A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT		0x00100000
1341 #define A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR			0x00200000
1342 #define A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN			0x00400000
1343 #define A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN			0x00800000
1344 #define A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN			0x01000000
1345 
1346 #define REG_A2XX_PA_SU_SC_MODE_CNTL				0x00002205
1347 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT			0x00000001
1348 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK			0x00000002
1349 #define A2XX_PA_SU_SC_MODE_CNTL_FACE				0x00000004
1350 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK			0x00000018
1351 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT			3
1352 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val)
1353 {
1354 	return ((val) << A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK;
1355 }
1356 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK		0x000000e0
1357 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT		5
1358 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
1359 {
1360 	return ((val) << A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK;
1361 }
1362 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK		0x00000700
1363 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT		8
1364 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
1365 {
1366 	return ((val) << A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK;
1367 }
1368 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE	0x00000800
1369 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE		0x00001000
1370 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE		0x00002000
1371 #define A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE			0x00008000
1372 #define A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE	0x00010000
1373 #define A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE		0x00040000
1374 #define A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST		0x00080000
1375 #define A2XX_PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS			0x00100000
1376 #define A2XX_PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA		0x00200000
1377 #define A2XX_PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE		0x00800000
1378 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI		0x02000000
1379 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE	0x04000000
1380 #define A2XX_PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS		0x10000000
1381 #define A2XX_PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS		0x20000000
1382 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE		0x40000000
1383 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE		0x80000000
1384 
1385 #define REG_A2XX_PA_CL_VTE_CNTL					0x00002206
1386 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA			0x00000001
1387 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA			0x00000002
1388 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA			0x00000004
1389 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA			0x00000008
1390 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA			0x00000010
1391 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA			0x00000020
1392 #define A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT				0x00000100
1393 #define A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT				0x00000200
1394 #define A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT				0x00000400
1395 #define A2XX_PA_CL_VTE_CNTL_PERFCOUNTER_REF			0x00000800
1396 
1397 #define REG_A2XX_VGT_CURRENT_BIN_ID_MIN				0x00002207
1398 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK		0x00000007
1399 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT		0
1400 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val)
1401 {
1402 	return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK;
1403 }
1404 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK			0x00000038
1405 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT			3
1406 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val)
1407 {
1408 	return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK;
1409 }
1410 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK	0x000001c0
1411 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT	6
1412 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val)
1413 {
1414 	return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK;
1415 }
1416 
1417 #define REG_A2XX_RB_MODECONTROL					0x00002208
1418 #define A2XX_RB_MODECONTROL_EDRAM_MODE__MASK			0x00000007
1419 #define A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT			0
1420 static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val)
1421 {
1422 	return ((val) << A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT) & A2XX_RB_MODECONTROL_EDRAM_MODE__MASK;
1423 }
1424 
1425 #define REG_A2XX_A220_RB_LRZ_VSC_CONTROL			0x00002209
1426 
1427 #define REG_A2XX_RB_SAMPLE_POS					0x0000220a
1428 
1429 #define REG_A2XX_CLEAR_COLOR					0x0000220b
1430 #define A2XX_CLEAR_COLOR_RED__MASK				0x000000ff
1431 #define A2XX_CLEAR_COLOR_RED__SHIFT				0
1432 static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val)
1433 {
1434 	return ((val) << A2XX_CLEAR_COLOR_RED__SHIFT) & A2XX_CLEAR_COLOR_RED__MASK;
1435 }
1436 #define A2XX_CLEAR_COLOR_GREEN__MASK				0x0000ff00
1437 #define A2XX_CLEAR_COLOR_GREEN__SHIFT				8
1438 static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val)
1439 {
1440 	return ((val) << A2XX_CLEAR_COLOR_GREEN__SHIFT) & A2XX_CLEAR_COLOR_GREEN__MASK;
1441 }
1442 #define A2XX_CLEAR_COLOR_BLUE__MASK				0x00ff0000
1443 #define A2XX_CLEAR_COLOR_BLUE__SHIFT				16
1444 static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val)
1445 {
1446 	return ((val) << A2XX_CLEAR_COLOR_BLUE__SHIFT) & A2XX_CLEAR_COLOR_BLUE__MASK;
1447 }
1448 #define A2XX_CLEAR_COLOR_ALPHA__MASK				0xff000000
1449 #define A2XX_CLEAR_COLOR_ALPHA__SHIFT				24
1450 static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val)
1451 {
1452 	return ((val) << A2XX_CLEAR_COLOR_ALPHA__SHIFT) & A2XX_CLEAR_COLOR_ALPHA__MASK;
1453 }
1454 
1455 #define REG_A2XX_A220_GRAS_CONTROL				0x00002210
1456 
1457 #define REG_A2XX_PA_SU_POINT_SIZE				0x00002280
1458 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK			0x0000ffff
1459 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT			0
1460 static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val)
1461 {
1462 	return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK;
1463 }
1464 #define A2XX_PA_SU_POINT_SIZE_WIDTH__MASK			0xffff0000
1465 #define A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT			16
1466 static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val)
1467 {
1468 	return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK;
1469 }
1470 
1471 #define REG_A2XX_PA_SU_POINT_MINMAX				0x00002281
1472 #define A2XX_PA_SU_POINT_MINMAX_MIN__MASK			0x0000ffff
1473 #define A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT			0
1474 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val)
1475 {
1476 	return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK;
1477 }
1478 #define A2XX_PA_SU_POINT_MINMAX_MAX__MASK			0xffff0000
1479 #define A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT			16
1480 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val)
1481 {
1482 	return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK;
1483 }
1484 
1485 #define REG_A2XX_PA_SU_LINE_CNTL				0x00002282
1486 #define A2XX_PA_SU_LINE_CNTL_WIDTH__MASK			0x0000ffff
1487 #define A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT			0
1488 static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val)
1489 {
1490 	return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK;
1491 }
1492 
1493 #define REG_A2XX_PA_SC_LINE_STIPPLE				0x00002283
1494 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK		0x0000ffff
1495 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT		0
1496 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val)
1497 {
1498 	return ((val) << A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK;
1499 }
1500 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK		0x00ff0000
1501 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT		16
1502 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val)
1503 {
1504 	return ((val) << A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK;
1505 }
1506 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK		0x10000000
1507 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT	28
1508 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val)
1509 {
1510 	return ((val) << A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK;
1511 }
1512 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK		0x60000000
1513 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT		29
1514 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val)
1515 {
1516 	return ((val) << A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK;
1517 }
1518 
1519 #define REG_A2XX_PA_SC_VIZ_QUERY				0x00002293
1520 #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ENA			0x00000001
1521 #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK			0x0000007e
1522 #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT		1
1523 static inline uint32_t A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID(uint32_t val)
1524 {
1525 	return ((val) << A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT) & A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK;
1526 }
1527 #define A2XX_PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z		0x00000100
1528 
1529 #define REG_A2XX_VGT_ENHANCE					0x00002294
1530 
1531 #define REG_A2XX_PA_SC_LINE_CNTL				0x00002300
1532 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK			0x0000ffff
1533 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT			0
1534 static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val)
1535 {
1536 	return ((val) << A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT) & A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK;
1537 }
1538 #define A2XX_PA_SC_LINE_CNTL_USE_BRES_CNTL			0x00000100
1539 #define A2XX_PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH			0x00000200
1540 #define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL				0x00000400
1541 
1542 #define REG_A2XX_PA_SC_AA_CONFIG				0x00002301
1543 #define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK		0x00000007
1544 #define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT		0
1545 static inline uint32_t A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES(uint32_t val)
1546 {
1547 	return ((val) << A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT) & A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK;
1548 }
1549 #define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK		0x0001e000
1550 #define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT		13
1551 static inline uint32_t A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST(uint32_t val)
1552 {
1553 	return ((val) << A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT) & A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK;
1554 }
1555 
1556 #define REG_A2XX_PA_SU_VTX_CNTL					0x00002302
1557 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK			0x00000001
1558 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT			0
1559 static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val)
1560 {
1561 	return ((val) << A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT) & A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK;
1562 }
1563 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK			0x00000006
1564 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT			1
1565 static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val)
1566 {
1567 	return ((val) << A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK;
1568 }
1569 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK			0x00000380
1570 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT			7
1571 static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val)
1572 {
1573 	return ((val) << A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK;
1574 }
1575 
1576 #define REG_A2XX_PA_CL_GB_VERT_CLIP_ADJ				0x00002303
1577 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK			0xffffffff
1578 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT			0
1579 static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val)
1580 {
1581 	return ((fui(val)) << A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK;
1582 }
1583 
1584 #define REG_A2XX_PA_CL_GB_VERT_DISC_ADJ				0x00002304
1585 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK			0xffffffff
1586 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT			0
1587 static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val)
1588 {
1589 	return ((fui(val)) << A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK;
1590 }
1591 
1592 #define REG_A2XX_PA_CL_GB_HORZ_CLIP_ADJ				0x00002305
1593 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK			0xffffffff
1594 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT			0
1595 static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val)
1596 {
1597 	return ((fui(val)) << A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK;
1598 }
1599 
1600 #define REG_A2XX_PA_CL_GB_HORZ_DISC_ADJ				0x00002306
1601 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK			0xffffffff
1602 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT			0
1603 static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val)
1604 {
1605 	return ((fui(val)) << A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK;
1606 }
1607 
1608 #define REG_A2XX_SQ_VS_CONST					0x00002307
1609 #define A2XX_SQ_VS_CONST_BASE__MASK				0x000001ff
1610 #define A2XX_SQ_VS_CONST_BASE__SHIFT				0
1611 static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val)
1612 {
1613 	return ((val) << A2XX_SQ_VS_CONST_BASE__SHIFT) & A2XX_SQ_VS_CONST_BASE__MASK;
1614 }
1615 #define A2XX_SQ_VS_CONST_SIZE__MASK				0x001ff000
1616 #define A2XX_SQ_VS_CONST_SIZE__SHIFT				12
1617 static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val)
1618 {
1619 	return ((val) << A2XX_SQ_VS_CONST_SIZE__SHIFT) & A2XX_SQ_VS_CONST_SIZE__MASK;
1620 }
1621 
1622 #define REG_A2XX_SQ_PS_CONST					0x00002308
1623 #define A2XX_SQ_PS_CONST_BASE__MASK				0x000001ff
1624 #define A2XX_SQ_PS_CONST_BASE__SHIFT				0
1625 static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val)
1626 {
1627 	return ((val) << A2XX_SQ_PS_CONST_BASE__SHIFT) & A2XX_SQ_PS_CONST_BASE__MASK;
1628 }
1629 #define A2XX_SQ_PS_CONST_SIZE__MASK				0x001ff000
1630 #define A2XX_SQ_PS_CONST_SIZE__SHIFT				12
1631 static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val)
1632 {
1633 	return ((val) << A2XX_SQ_PS_CONST_SIZE__SHIFT) & A2XX_SQ_PS_CONST_SIZE__MASK;
1634 }
1635 
1636 #define REG_A2XX_SQ_DEBUG_MISC_0				0x00002309
1637 
1638 #define REG_A2XX_SQ_DEBUG_MISC_1				0x0000230a
1639 
1640 #define REG_A2XX_PA_SC_AA_MASK					0x00002312
1641 
1642 #define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL			0x00002316
1643 #define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK	0x00000007
1644 #define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT	0
1645 static inline uint32_t A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH(uint32_t val)
1646 {
1647 	return ((val) << A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT) & A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK;
1648 }
1649 
1650 #define REG_A2XX_VGT_OUT_DEALLOC_CNTL				0x00002317
1651 #define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK		0x00000003
1652 #define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT		0
1653 static inline uint32_t A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST(uint32_t val)
1654 {
1655 	return ((val) << A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT) & A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK;
1656 }
1657 
1658 #define REG_A2XX_RB_COPY_CONTROL				0x00002318
1659 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK		0x00000007
1660 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT		0
1661 static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val)
1662 {
1663 	return ((val) << A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT) & A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK;
1664 }
1665 #define A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE			0x00000008
1666 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK			0x000000f0
1667 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT			4
1668 static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val)
1669 {
1670 	return ((val) << A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT) & A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK;
1671 }
1672 
1673 #define REG_A2XX_RB_COPY_DEST_BASE				0x00002319
1674 
1675 #define REG_A2XX_RB_COPY_DEST_PITCH				0x0000231a
1676 #define A2XX_RB_COPY_DEST_PITCH__MASK				0xffffffff
1677 #define A2XX_RB_COPY_DEST_PITCH__SHIFT				0
1678 static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val)
1679 {
1680 	return ((val >> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK;
1681 }
1682 
1683 #define REG_A2XX_RB_COPY_DEST_INFO				0x0000231b
1684 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK		0x00000007
1685 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT		0
1686 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val)
1687 {
1688 	return ((val) << A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT) & A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK;
1689 }
1690 #define A2XX_RB_COPY_DEST_INFO_LINEAR				0x00000008
1691 #define A2XX_RB_COPY_DEST_INFO_FORMAT__MASK			0x000000f0
1692 #define A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT			4
1693 static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val)
1694 {
1695 	return ((val) << A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A2XX_RB_COPY_DEST_INFO_FORMAT__MASK;
1696 }
1697 #define A2XX_RB_COPY_DEST_INFO_SWAP__MASK			0x00000300
1698 #define A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT			8
1699 static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val)
1700 {
1701 	return ((val) << A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A2XX_RB_COPY_DEST_INFO_SWAP__MASK;
1702 }
1703 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK		0x00000c00
1704 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT		10
1705 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
1706 {
1707 	return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
1708 }
1709 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK		0x00003000
1710 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT		12
1711 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val)
1712 {
1713 	return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK;
1714 }
1715 #define A2XX_RB_COPY_DEST_INFO_WRITE_RED			0x00004000
1716 #define A2XX_RB_COPY_DEST_INFO_WRITE_GREEN			0x00008000
1717 #define A2XX_RB_COPY_DEST_INFO_WRITE_BLUE			0x00010000
1718 #define A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA			0x00020000
1719 
1720 #define REG_A2XX_RB_COPY_DEST_OFFSET				0x0000231c
1721 #define A2XX_RB_COPY_DEST_OFFSET_X__MASK			0x00001fff
1722 #define A2XX_RB_COPY_DEST_OFFSET_X__SHIFT			0
1723 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val)
1724 {
1725 	return ((val) << A2XX_RB_COPY_DEST_OFFSET_X__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_X__MASK;
1726 }
1727 #define A2XX_RB_COPY_DEST_OFFSET_Y__MASK			0x03ffe000
1728 #define A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT			13
1729 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val)
1730 {
1731 	return ((val) << A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_Y__MASK;
1732 }
1733 
1734 #define REG_A2XX_RB_DEPTH_CLEAR					0x0000231d
1735 
1736 #define REG_A2XX_RB_SAMPLE_COUNT_CTL				0x00002324
1737 
1738 #define REG_A2XX_RB_COLOR_DEST_MASK				0x00002326
1739 
1740 #define REG_A2XX_A225_GRAS_UCP0X				0x00002340
1741 
1742 #define REG_A2XX_A225_GRAS_UCP5W				0x00002357
1743 
1744 #define REG_A2XX_A225_GRAS_UCP_ENABLED				0x00002360
1745 
1746 #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE			0x00002380
1747 
1748 #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET			0x00002383
1749 
1750 #define REG_A2XX_SQ_CONSTANT_0					0x00004000
1751 
1752 #define REG_A2XX_SQ_FETCH_0					0x00004800
1753 
1754 #define REG_A2XX_SQ_CF_BOOLEANS					0x00004900
1755 
1756 #define REG_A2XX_SQ_CF_LOOP					0x00004908
1757 
1758 #define REG_A2XX_COHER_SIZE_PM4					0x00000a29
1759 
1760 #define REG_A2XX_COHER_BASE_PM4					0x00000a2a
1761 
1762 #define REG_A2XX_COHER_STATUS_PM4				0x00000a2b
1763 
1764 #define REG_A2XX_SQ_TEX_0					0x00000000
1765 #define A2XX_SQ_TEX_0_CLAMP_X__MASK				0x00001c00
1766 #define A2XX_SQ_TEX_0_CLAMP_X__SHIFT				10
1767 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val)
1768 {
1769 	return ((val) << A2XX_SQ_TEX_0_CLAMP_X__SHIFT) & A2XX_SQ_TEX_0_CLAMP_X__MASK;
1770 }
1771 #define A2XX_SQ_TEX_0_CLAMP_Y__MASK				0x0000e000
1772 #define A2XX_SQ_TEX_0_CLAMP_Y__SHIFT				13
1773 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val)
1774 {
1775 	return ((val) << A2XX_SQ_TEX_0_CLAMP_Y__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Y__MASK;
1776 }
1777 #define A2XX_SQ_TEX_0_CLAMP_Z__MASK				0x00070000
1778 #define A2XX_SQ_TEX_0_CLAMP_Z__SHIFT				16
1779 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val)
1780 {
1781 	return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK;
1782 }
1783 #define A2XX_SQ_TEX_0_PITCH__MASK				0xffc00000
1784 #define A2XX_SQ_TEX_0_PITCH__SHIFT				22
1785 static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val)
1786 {
1787 	return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK;
1788 }
1789 
1790 #define REG_A2XX_SQ_TEX_1					0x00000001
1791 
1792 #define REG_A2XX_SQ_TEX_2					0x00000002
1793 #define A2XX_SQ_TEX_2_WIDTH__MASK				0x00001fff
1794 #define A2XX_SQ_TEX_2_WIDTH__SHIFT				0
1795 static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val)
1796 {
1797 	return ((val) << A2XX_SQ_TEX_2_WIDTH__SHIFT) & A2XX_SQ_TEX_2_WIDTH__MASK;
1798 }
1799 #define A2XX_SQ_TEX_2_HEIGHT__MASK				0x03ffe000
1800 #define A2XX_SQ_TEX_2_HEIGHT__SHIFT				13
1801 static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val)
1802 {
1803 	return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK;
1804 }
1805 
1806 #define REG_A2XX_SQ_TEX_3					0x00000003
1807 #define A2XX_SQ_TEX_3_SWIZ_X__MASK				0x0000000e
1808 #define A2XX_SQ_TEX_3_SWIZ_X__SHIFT				1
1809 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val)
1810 {
1811 	return ((val) << A2XX_SQ_TEX_3_SWIZ_X__SHIFT) & A2XX_SQ_TEX_3_SWIZ_X__MASK;
1812 }
1813 #define A2XX_SQ_TEX_3_SWIZ_Y__MASK				0x00000070
1814 #define A2XX_SQ_TEX_3_SWIZ_Y__SHIFT				4
1815 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val)
1816 {
1817 	return ((val) << A2XX_SQ_TEX_3_SWIZ_Y__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Y__MASK;
1818 }
1819 #define A2XX_SQ_TEX_3_SWIZ_Z__MASK				0x00000380
1820 #define A2XX_SQ_TEX_3_SWIZ_Z__SHIFT				7
1821 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val)
1822 {
1823 	return ((val) << A2XX_SQ_TEX_3_SWIZ_Z__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Z__MASK;
1824 }
1825 #define A2XX_SQ_TEX_3_SWIZ_W__MASK				0x00001c00
1826 #define A2XX_SQ_TEX_3_SWIZ_W__SHIFT				10
1827 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val)
1828 {
1829 	return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK;
1830 }
1831 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK			0x00180000
1832 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT			19
1833 static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val)
1834 {
1835 	return ((val) << A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK;
1836 }
1837 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK			0x00600000
1838 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT			21
1839 static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val)
1840 {
1841 	return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK;
1842 }
1843 
1844 
1845 #endif /* A2XX_XML */
1846