1 #ifndef A2XX_XML 2 #define A2XX_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) 13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25) 15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31) 16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21) 17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109916 bytes, from 2016-02-20 18:44:48) 18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) 19 20 Copyright (C) 2013-2015 by the following authors: 21 - Rob Clark <robdclark@gmail.com> (robclark) 22 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 23 24 Permission is hereby granted, free of charge, to any person obtaining 25 a copy of this software and associated documentation files (the 26 "Software"), to deal in the Software without restriction, including 27 without limitation the rights to use, copy, modify, merge, publish, 28 distribute, sublicense, and/or sell copies of the Software, and to 29 permit persons to whom the Software is furnished to do so, subject to 30 the following conditions: 31 32 The above copyright notice and this permission notice (including the 33 next paragraph) shall be included in all copies or substantial 34 portions of the Software. 35 36 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 37 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 38 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 39 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 40 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 41 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 42 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45 46 enum a2xx_rb_dither_type { 47 DITHER_PIXEL = 0, 48 DITHER_SUBPIXEL = 1, 49 }; 50 51 enum a2xx_colorformatx { 52 COLORX_4_4_4_4 = 0, 53 COLORX_1_5_5_5 = 1, 54 COLORX_5_6_5 = 2, 55 COLORX_8 = 3, 56 COLORX_8_8 = 4, 57 COLORX_8_8_8_8 = 5, 58 COLORX_S8_8_8_8 = 6, 59 COLORX_16_FLOAT = 7, 60 COLORX_16_16_FLOAT = 8, 61 COLORX_16_16_16_16_FLOAT = 9, 62 COLORX_32_FLOAT = 10, 63 COLORX_32_32_FLOAT = 11, 64 COLORX_32_32_32_32_FLOAT = 12, 65 COLORX_2_3_3 = 13, 66 COLORX_8_8_8 = 14, 67 }; 68 69 enum a2xx_sq_surfaceformat { 70 FMT_1_REVERSE = 0, 71 FMT_1 = 1, 72 FMT_8 = 2, 73 FMT_1_5_5_5 = 3, 74 FMT_5_6_5 = 4, 75 FMT_6_5_5 = 5, 76 FMT_8_8_8_8 = 6, 77 FMT_2_10_10_10 = 7, 78 FMT_8_A = 8, 79 FMT_8_B = 9, 80 FMT_8_8 = 10, 81 FMT_Cr_Y1_Cb_Y0 = 11, 82 FMT_Y1_Cr_Y0_Cb = 12, 83 FMT_5_5_5_1 = 13, 84 FMT_8_8_8_8_A = 14, 85 FMT_4_4_4_4 = 15, 86 FMT_10_11_11 = 16, 87 FMT_11_11_10 = 17, 88 FMT_DXT1 = 18, 89 FMT_DXT2_3 = 19, 90 FMT_DXT4_5 = 20, 91 FMT_24_8 = 22, 92 FMT_24_8_FLOAT = 23, 93 FMT_16 = 24, 94 FMT_16_16 = 25, 95 FMT_16_16_16_16 = 26, 96 FMT_16_EXPAND = 27, 97 FMT_16_16_EXPAND = 28, 98 FMT_16_16_16_16_EXPAND = 29, 99 FMT_16_FLOAT = 30, 100 FMT_16_16_FLOAT = 31, 101 FMT_16_16_16_16_FLOAT = 32, 102 FMT_32 = 33, 103 FMT_32_32 = 34, 104 FMT_32_32_32_32 = 35, 105 FMT_32_FLOAT = 36, 106 FMT_32_32_FLOAT = 37, 107 FMT_32_32_32_32_FLOAT = 38, 108 FMT_32_AS_8 = 39, 109 FMT_32_AS_8_8 = 40, 110 FMT_16_MPEG = 41, 111 FMT_16_16_MPEG = 42, 112 FMT_8_INTERLACED = 43, 113 FMT_32_AS_8_INTERLACED = 44, 114 FMT_32_AS_8_8_INTERLACED = 45, 115 FMT_16_INTERLACED = 46, 116 FMT_16_MPEG_INTERLACED = 47, 117 FMT_16_16_MPEG_INTERLACED = 48, 118 FMT_DXN = 49, 119 FMT_8_8_8_8_AS_16_16_16_16 = 50, 120 FMT_DXT1_AS_16_16_16_16 = 51, 121 FMT_DXT2_3_AS_16_16_16_16 = 52, 122 FMT_DXT4_5_AS_16_16_16_16 = 53, 123 FMT_2_10_10_10_AS_16_16_16_16 = 54, 124 FMT_10_11_11_AS_16_16_16_16 = 55, 125 FMT_11_11_10_AS_16_16_16_16 = 56, 126 FMT_32_32_32_FLOAT = 57, 127 FMT_DXT3A = 58, 128 FMT_DXT5A = 59, 129 FMT_CTX1 = 60, 130 FMT_DXT3A_AS_1_1_1_1 = 61, 131 }; 132 133 enum a2xx_sq_ps_vtx_mode { 134 POSITION_1_VECTOR = 0, 135 POSITION_2_VECTORS_UNUSED = 1, 136 POSITION_2_VECTORS_SPRITE = 2, 137 POSITION_2_VECTORS_EDGE = 3, 138 POSITION_2_VECTORS_KILL = 4, 139 POSITION_2_VECTORS_SPRITE_KILL = 5, 140 POSITION_2_VECTORS_EDGE_KILL = 6, 141 MULTIPASS = 7, 142 }; 143 144 enum a2xx_sq_sample_cntl { 145 CENTROIDS_ONLY = 0, 146 CENTERS_ONLY = 1, 147 CENTROIDS_AND_CENTERS = 2, 148 }; 149 150 enum a2xx_dx_clip_space { 151 DXCLIP_OPENGL = 0, 152 DXCLIP_DIRECTX = 1, 153 }; 154 155 enum a2xx_pa_su_sc_polymode { 156 POLY_DISABLED = 0, 157 POLY_DUALMODE = 1, 158 }; 159 160 enum a2xx_rb_edram_mode { 161 EDRAM_NOP = 0, 162 COLOR_DEPTH = 4, 163 DEPTH_ONLY = 5, 164 EDRAM_COPY = 6, 165 }; 166 167 enum a2xx_pa_sc_pattern_bit_order { 168 LITTLE = 0, 169 BIG = 1, 170 }; 171 172 enum a2xx_pa_sc_auto_reset_cntl { 173 NEVER = 0, 174 EACH_PRIMITIVE = 1, 175 EACH_PACKET = 2, 176 }; 177 178 enum a2xx_pa_pixcenter { 179 PIXCENTER_D3D = 0, 180 PIXCENTER_OGL = 1, 181 }; 182 183 enum a2xx_pa_roundmode { 184 TRUNCATE = 0, 185 ROUND = 1, 186 ROUNDTOEVEN = 2, 187 ROUNDTOODD = 3, 188 }; 189 190 enum a2xx_pa_quantmode { 191 ONE_SIXTEENTH = 0, 192 ONE_EIGTH = 1, 193 ONE_QUARTER = 2, 194 ONE_HALF = 3, 195 ONE = 4, 196 }; 197 198 enum a2xx_rb_copy_sample_select { 199 SAMPLE_0 = 0, 200 SAMPLE_1 = 1, 201 SAMPLE_2 = 2, 202 SAMPLE_3 = 3, 203 SAMPLE_01 = 4, 204 SAMPLE_23 = 5, 205 SAMPLE_0123 = 6, 206 }; 207 208 enum a2xx_rb_blend_opcode { 209 BLEND_DST_PLUS_SRC = 0, 210 BLEND_SRC_MINUS_DST = 1, 211 BLEND_MIN_DST_SRC = 2, 212 BLEND_MAX_DST_SRC = 3, 213 BLEND_DST_MINUS_SRC = 4, 214 BLEND_DST_PLUS_SRC_BIAS = 5, 215 }; 216 217 enum adreno_mmu_clnt_beh { 218 BEH_NEVR = 0, 219 BEH_TRAN_RNG = 1, 220 BEH_TRAN_FLT = 2, 221 }; 222 223 enum sq_tex_clamp { 224 SQ_TEX_WRAP = 0, 225 SQ_TEX_MIRROR = 1, 226 SQ_TEX_CLAMP_LAST_TEXEL = 2, 227 SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3, 228 SQ_TEX_CLAMP_HALF_BORDER = 4, 229 SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5, 230 SQ_TEX_CLAMP_BORDER = 6, 231 SQ_TEX_MIRROR_ONCE_BORDER = 7, 232 }; 233 234 enum sq_tex_swiz { 235 SQ_TEX_X = 0, 236 SQ_TEX_Y = 1, 237 SQ_TEX_Z = 2, 238 SQ_TEX_W = 3, 239 SQ_TEX_ZERO = 4, 240 SQ_TEX_ONE = 5, 241 }; 242 243 enum sq_tex_filter { 244 SQ_TEX_FILTER_POINT = 0, 245 SQ_TEX_FILTER_BILINEAR = 1, 246 SQ_TEX_FILTER_BICUBIC = 2, 247 }; 248 249 #define REG_A2XX_RBBM_PATCH_RELEASE 0x00000001 250 251 #define REG_A2XX_RBBM_CNTL 0x0000003b 252 253 #define REG_A2XX_RBBM_SOFT_RESET 0x0000003c 254 255 #define REG_A2XX_CP_PFP_UCODE_ADDR 0x000000c0 256 257 #define REG_A2XX_CP_PFP_UCODE_DATA 0x000000c1 258 259 #define REG_A2XX_MH_MMU_CONFIG 0x00000040 260 #define A2XX_MH_MMU_CONFIG_MMU_ENABLE 0x00000001 261 #define A2XX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE 0x00000002 262 #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK 0x00000030 263 #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT 4 264 static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 265 { 266 return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK; 267 } 268 #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK 0x000000c0 269 #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT 6 270 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 271 { 272 return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK; 273 } 274 #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK 0x00000300 275 #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT 8 276 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 277 { 278 return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK; 279 } 280 #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK 0x00000c00 281 #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT 10 282 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 283 { 284 return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK; 285 } 286 #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK 0x00003000 287 #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT 12 288 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 289 { 290 return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK; 291 } 292 #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK 0x0000c000 293 #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT 14 294 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 295 { 296 return ((val) << A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK; 297 } 298 #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK 0x00030000 299 #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT 16 300 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 301 { 302 return ((val) << A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK; 303 } 304 #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK 0x000c0000 305 #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT 18 306 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 307 { 308 return ((val) << A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK; 309 } 310 #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK 0x00300000 311 #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT 20 312 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 313 { 314 return ((val) << A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK; 315 } 316 #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK 0x00c00000 317 #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT 22 318 static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 319 { 320 return ((val) << A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK; 321 } 322 #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK 0x03000000 323 #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT 24 324 static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 325 { 326 return ((val) << A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK; 327 } 328 329 #define REG_A2XX_MH_MMU_VA_RANGE 0x00000041 330 331 #define REG_A2XX_MH_MMU_PT_BASE 0x00000042 332 333 #define REG_A2XX_MH_MMU_PAGE_FAULT 0x00000043 334 335 #define REG_A2XX_MH_MMU_TRAN_ERROR 0x00000044 336 337 #define REG_A2XX_MH_MMU_INVALIDATE 0x00000045 338 339 #define REG_A2XX_MH_MMU_MPU_BASE 0x00000046 340 341 #define REG_A2XX_MH_MMU_MPU_END 0x00000047 342 343 #define REG_A2XX_NQWAIT_UNTIL 0x00000394 344 345 #define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395 346 347 #define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397 348 349 #define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x00000398 350 351 #define REG_A2XX_RBBM_DEBUG 0x0000039b 352 353 #define REG_A2XX_RBBM_PM_OVERRIDE1 0x0000039c 354 355 #define REG_A2XX_RBBM_PM_OVERRIDE2 0x0000039d 356 357 #define REG_A2XX_RBBM_DEBUG_OUT 0x000003a0 358 359 #define REG_A2XX_RBBM_DEBUG_CNTL 0x000003a1 360 361 #define REG_A2XX_RBBM_READ_ERROR 0x000003b3 362 363 #define REG_A2XX_RBBM_INT_CNTL 0x000003b4 364 365 #define REG_A2XX_RBBM_INT_STATUS 0x000003b5 366 367 #define REG_A2XX_RBBM_INT_ACK 0x000003b6 368 369 #define REG_A2XX_MASTER_INT_SIGNAL 0x000003b7 370 371 #define REG_A2XX_RBBM_PERIPHID1 0x000003f9 372 373 #define REG_A2XX_RBBM_PERIPHID2 0x000003fa 374 375 #define REG_A2XX_CP_PERFMON_CNTL 0x00000444 376 377 #define REG_A2XX_CP_PERFCOUNTER_SELECT 0x00000445 378 379 #define REG_A2XX_CP_PERFCOUNTER_LO 0x00000446 380 381 #define REG_A2XX_CP_PERFCOUNTER_HI 0x00000447 382 383 #define REG_A2XX_RBBM_STATUS 0x000005d0 384 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK 0x0000001f 385 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT 0 386 static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val) 387 { 388 return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK; 389 } 390 #define A2XX_RBBM_STATUS_TC_BUSY 0x00000020 391 #define A2XX_RBBM_STATUS_HIRQ_PENDING 0x00000100 392 #define A2XX_RBBM_STATUS_CPRQ_PENDING 0x00000200 393 #define A2XX_RBBM_STATUS_CFRQ_PENDING 0x00000400 394 #define A2XX_RBBM_STATUS_PFRQ_PENDING 0x00000800 395 #define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA 0x00001000 396 #define A2XX_RBBM_STATUS_RBBM_WU_BUSY 0x00004000 397 #define A2XX_RBBM_STATUS_CP_NRT_BUSY 0x00010000 398 #define A2XX_RBBM_STATUS_MH_BUSY 0x00040000 399 #define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY 0x00080000 400 #define A2XX_RBBM_STATUS_SX_BUSY 0x00200000 401 #define A2XX_RBBM_STATUS_TPC_BUSY 0x00400000 402 #define A2XX_RBBM_STATUS_SC_CNTX_BUSY 0x01000000 403 #define A2XX_RBBM_STATUS_PA_BUSY 0x02000000 404 #define A2XX_RBBM_STATUS_VGT_BUSY 0x04000000 405 #define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY 0x08000000 406 #define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY 0x10000000 407 #define A2XX_RBBM_STATUS_RB_CNTX_BUSY 0x40000000 408 #define A2XX_RBBM_STATUS_GUI_ACTIVE 0x80000000 409 410 #define REG_A2XX_MH_ARBITER_CONFIG 0x00000a40 411 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK 0x0000003f 412 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT 0 413 static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val) 414 { 415 return ((val) << A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK; 416 } 417 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY 0x00000040 418 #define A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE 0x00000080 419 #define A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE 0x00000100 420 #define A2XX_MH_ARBITER_CONFIG_L2_ARB_CONTROL 0x00000200 421 #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK 0x00001c00 422 #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT 10 423 static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val) 424 { 425 return ((val) << A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT) & A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK; 426 } 427 #define A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00002000 428 #define A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE 0x00004000 429 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE 0x00008000 430 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK 0x003f0000 431 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT 16 432 static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val) 433 { 434 return ((val) << A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK; 435 } 436 #define A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE 0x00400000 437 #define A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE 0x00800000 438 #define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE 0x01000000 439 #define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE 0x02000000 440 #define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE 0x04000000 441 442 #define REG_A2XX_A220_VSC_BIN_SIZE 0x00000c01 443 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 444 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT 0 445 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val) 446 { 447 return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK; 448 } 449 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 450 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT 5 451 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val) 452 { 453 return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK; 454 } 455 456 static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 457 458 static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 459 460 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } 461 462 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } 463 464 #define REG_A2XX_PC_DEBUG_CNTL 0x00000c38 465 466 #define REG_A2XX_PC_DEBUG_DATA 0x00000c39 467 468 #define REG_A2XX_PA_SC_VIZ_QUERY_STATUS 0x00000c44 469 470 #define REG_A2XX_GRAS_DEBUG_CNTL 0x00000c80 471 472 #define REG_A2XX_PA_SU_DEBUG_CNTL 0x00000c80 473 474 #define REG_A2XX_GRAS_DEBUG_DATA 0x00000c81 475 476 #define REG_A2XX_PA_SU_DEBUG_DATA 0x00000c81 477 478 #define REG_A2XX_PA_SU_FACE_DATA 0x00000c86 479 480 #define REG_A2XX_SQ_GPR_MANAGEMENT 0x00000d00 481 482 #define REG_A2XX_SQ_FLOW_CONTROL 0x00000d01 483 484 #define REG_A2XX_SQ_INST_STORE_MANAGMENT 0x00000d02 485 486 #define REG_A2XX_SQ_DEBUG_MISC 0x00000d05 487 488 #define REG_A2XX_SQ_INT_CNTL 0x00000d34 489 490 #define REG_A2XX_SQ_INT_STATUS 0x00000d35 491 492 #define REG_A2XX_SQ_INT_ACK 0x00000d36 493 494 #define REG_A2XX_SQ_DEBUG_INPUT_FSM 0x00000dae 495 496 #define REG_A2XX_SQ_DEBUG_CONST_MGR_FSM 0x00000daf 497 498 #define REG_A2XX_SQ_DEBUG_TP_FSM 0x00000db0 499 500 #define REG_A2XX_SQ_DEBUG_FSM_ALU_0 0x00000db1 501 502 #define REG_A2XX_SQ_DEBUG_FSM_ALU_1 0x00000db2 503 504 #define REG_A2XX_SQ_DEBUG_EXP_ALLOC 0x00000db3 505 506 #define REG_A2XX_SQ_DEBUG_PTR_BUFF 0x00000db4 507 508 #define REG_A2XX_SQ_DEBUG_GPR_VTX 0x00000db5 509 510 #define REG_A2XX_SQ_DEBUG_GPR_PIX 0x00000db6 511 512 #define REG_A2XX_SQ_DEBUG_TB_STATUS_SEL 0x00000db7 513 514 #define REG_A2XX_SQ_DEBUG_VTX_TB_0 0x00000db8 515 516 #define REG_A2XX_SQ_DEBUG_VTX_TB_1 0x00000db9 517 518 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG 0x00000dba 519 520 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM 0x00000dbb 521 522 #define REG_A2XX_SQ_DEBUG_PIX_TB_0 0x00000dbc 523 524 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0 0x00000dbd 525 526 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1 0x00000dbe 527 528 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2 0x00000dbf 529 530 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3 0x00000dc0 531 532 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM 0x00000dc1 533 534 #define REG_A2XX_TC_CNTL_STATUS 0x00000e00 535 #define A2XX_TC_CNTL_STATUS_L2_INVALIDATE 0x00000001 536 537 #define REG_A2XX_TP0_CHICKEN 0x00000e1e 538 539 #define REG_A2XX_RB_BC_CONTROL 0x00000f01 540 #define A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE 0x00000001 541 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK 0x00000006 542 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT 1 543 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val) 544 { 545 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK; 546 } 547 #define A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM 0x00000008 548 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010 549 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP 0x00000020 550 #define A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP 0x00000040 551 #define A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE 0x00000080 552 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK 0x00001f00 553 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT 8 554 static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val) 555 { 556 return ((val) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK; 557 } 558 #define A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE 0x00004000 559 #define A2XX_RB_BC_CONTROL_CRC_MODE 0x00008000 560 #define A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS 0x00010000 561 #define A2XX_RB_BC_CONTROL_DISABLE_ACCUM 0x00020000 562 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK 0x003c0000 563 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT 18 564 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val) 565 { 566 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK; 567 } 568 #define A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE 0x00400000 569 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK 0x07800000 570 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT 23 571 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val) 572 { 573 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK; 574 } 575 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK 0x18000000 576 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT 27 577 static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val) 578 { 579 return ((val) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK; 580 } 581 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000 582 #define A2XX_RB_BC_CONTROL_CRC_SYSTEM 0x40000000 583 #define A2XX_RB_BC_CONTROL_RESERVED6 0x80000000 584 585 #define REG_A2XX_RB_EDRAM_INFO 0x00000f02 586 587 #define REG_A2XX_RB_DEBUG_CNTL 0x00000f26 588 589 #define REG_A2XX_RB_DEBUG_DATA 0x00000f27 590 591 #define REG_A2XX_RB_SURFACE_INFO 0x00002000 592 593 #define REG_A2XX_RB_COLOR_INFO 0x00002001 594 #define A2XX_RB_COLOR_INFO_FORMAT__MASK 0x0000000f 595 #define A2XX_RB_COLOR_INFO_FORMAT__SHIFT 0 596 static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val) 597 { 598 return ((val) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT) & A2XX_RB_COLOR_INFO_FORMAT__MASK; 599 } 600 #define A2XX_RB_COLOR_INFO_ROUND_MODE__MASK 0x00000030 601 #define A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT 4 602 static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val) 603 { 604 return ((val) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK; 605 } 606 #define A2XX_RB_COLOR_INFO_LINEAR 0x00000040 607 #define A2XX_RB_COLOR_INFO_ENDIAN__MASK 0x00000180 608 #define A2XX_RB_COLOR_INFO_ENDIAN__SHIFT 7 609 static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val) 610 { 611 return ((val) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT) & A2XX_RB_COLOR_INFO_ENDIAN__MASK; 612 } 613 #define A2XX_RB_COLOR_INFO_SWAP__MASK 0x00000600 614 #define A2XX_RB_COLOR_INFO_SWAP__SHIFT 9 615 static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val) 616 { 617 return ((val) << A2XX_RB_COLOR_INFO_SWAP__SHIFT) & A2XX_RB_COLOR_INFO_SWAP__MASK; 618 } 619 #define A2XX_RB_COLOR_INFO_BASE__MASK 0xfffff000 620 #define A2XX_RB_COLOR_INFO_BASE__SHIFT 12 621 static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val) 622 { 623 return ((val >> 10) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK; 624 } 625 626 #define REG_A2XX_RB_DEPTH_INFO 0x00002002 627 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001 628 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 629 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) 630 { 631 return ((val) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 632 } 633 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 634 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 635 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 636 { 637 return ((val >> 10) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 638 } 639 640 #define REG_A2XX_A225_RB_COLOR_INFO3 0x00002005 641 642 #define REG_A2XX_COHER_DEST_BASE_0 0x00002006 643 644 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_TL 0x0000200e 645 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 646 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 647 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 648 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 649 { 650 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK; 651 } 652 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 653 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 654 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 655 { 656 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK; 657 } 658 659 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_BR 0x0000200f 660 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 661 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 662 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 663 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 664 { 665 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK; 666 } 667 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 668 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 669 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 670 { 671 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK; 672 } 673 674 #define REG_A2XX_PA_SC_WINDOW_OFFSET 0x00002080 675 #define A2XX_PA_SC_WINDOW_OFFSET_X__MASK 0x00007fff 676 #define A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT 0 677 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val) 678 { 679 return ((val) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK; 680 } 681 #define A2XX_PA_SC_WINDOW_OFFSET_Y__MASK 0x7fff0000 682 #define A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT 16 683 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val) 684 { 685 return ((val) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK; 686 } 687 #define A2XX_PA_SC_WINDOW_OFFSET_DISABLE 0x80000000 688 689 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_TL 0x00002081 690 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 691 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 692 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 693 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 694 { 695 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK; 696 } 697 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 698 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 699 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 700 { 701 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK; 702 } 703 704 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_BR 0x00002082 705 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 706 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 707 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 708 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 709 { 710 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK; 711 } 712 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 713 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 714 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 715 { 716 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK; 717 } 718 719 #define REG_A2XX_UNKNOWN_2010 0x00002010 720 721 #define REG_A2XX_VGT_MAX_VTX_INDX 0x00002100 722 723 #define REG_A2XX_VGT_MIN_VTX_INDX 0x00002101 724 725 #define REG_A2XX_VGT_INDX_OFFSET 0x00002102 726 727 #define REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX 0x00002103 728 729 #define REG_A2XX_RB_COLOR_MASK 0x00002104 730 #define A2XX_RB_COLOR_MASK_WRITE_RED 0x00000001 731 #define A2XX_RB_COLOR_MASK_WRITE_GREEN 0x00000002 732 #define A2XX_RB_COLOR_MASK_WRITE_BLUE 0x00000004 733 #define A2XX_RB_COLOR_MASK_WRITE_ALPHA 0x00000008 734 735 #define REG_A2XX_RB_BLEND_RED 0x00002105 736 737 #define REG_A2XX_RB_BLEND_GREEN 0x00002106 738 739 #define REG_A2XX_RB_BLEND_BLUE 0x00002107 740 741 #define REG_A2XX_RB_BLEND_ALPHA 0x00002108 742 743 #define REG_A2XX_RB_FOG_COLOR 0x00002109 744 745 #define REG_A2XX_RB_STENCILREFMASK_BF 0x0000210c 746 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 747 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 748 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 749 { 750 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 751 } 752 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 753 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 754 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 755 { 756 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 757 } 758 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 759 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 760 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 761 { 762 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 763 } 764 765 #define REG_A2XX_RB_STENCILREFMASK 0x0000210d 766 #define A2XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 767 #define A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 768 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 769 { 770 return ((val) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK; 771 } 772 #define A2XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 773 #define A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 774 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 775 { 776 return ((val) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK; 777 } 778 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 779 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 780 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 781 { 782 return ((val) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 783 } 784 785 #define REG_A2XX_RB_ALPHA_REF 0x0000210e 786 787 #define REG_A2XX_PA_CL_VPORT_XSCALE 0x0000210f 788 #define A2XX_PA_CL_VPORT_XSCALE__MASK 0xffffffff 789 #define A2XX_PA_CL_VPORT_XSCALE__SHIFT 0 790 static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val) 791 { 792 return ((fui(val)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT) & A2XX_PA_CL_VPORT_XSCALE__MASK; 793 } 794 795 #define REG_A2XX_PA_CL_VPORT_XOFFSET 0x00002110 796 #define A2XX_PA_CL_VPORT_XOFFSET__MASK 0xffffffff 797 #define A2XX_PA_CL_VPORT_XOFFSET__SHIFT 0 798 static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val) 799 { 800 return ((fui(val)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT) & A2XX_PA_CL_VPORT_XOFFSET__MASK; 801 } 802 803 #define REG_A2XX_PA_CL_VPORT_YSCALE 0x00002111 804 #define A2XX_PA_CL_VPORT_YSCALE__MASK 0xffffffff 805 #define A2XX_PA_CL_VPORT_YSCALE__SHIFT 0 806 static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val) 807 { 808 return ((fui(val)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT) & A2XX_PA_CL_VPORT_YSCALE__MASK; 809 } 810 811 #define REG_A2XX_PA_CL_VPORT_YOFFSET 0x00002112 812 #define A2XX_PA_CL_VPORT_YOFFSET__MASK 0xffffffff 813 #define A2XX_PA_CL_VPORT_YOFFSET__SHIFT 0 814 static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val) 815 { 816 return ((fui(val)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT) & A2XX_PA_CL_VPORT_YOFFSET__MASK; 817 } 818 819 #define REG_A2XX_PA_CL_VPORT_ZSCALE 0x00002113 820 #define A2XX_PA_CL_VPORT_ZSCALE__MASK 0xffffffff 821 #define A2XX_PA_CL_VPORT_ZSCALE__SHIFT 0 822 static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val) 823 { 824 return ((fui(val)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT) & A2XX_PA_CL_VPORT_ZSCALE__MASK; 825 } 826 827 #define REG_A2XX_PA_CL_VPORT_ZOFFSET 0x00002114 828 #define A2XX_PA_CL_VPORT_ZOFFSET__MASK 0xffffffff 829 #define A2XX_PA_CL_VPORT_ZOFFSET__SHIFT 0 830 static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val) 831 { 832 return ((fui(val)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT) & A2XX_PA_CL_VPORT_ZOFFSET__MASK; 833 } 834 835 #define REG_A2XX_SQ_PROGRAM_CNTL 0x00002180 836 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK 0x000000ff 837 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT 0 838 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val) 839 { 840 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK; 841 } 842 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK 0x0000ff00 843 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT 8 844 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val) 845 { 846 return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK; 847 } 848 #define A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE 0x00010000 849 #define A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE 0x00020000 850 #define A2XX_SQ_PROGRAM_CNTL_PARAM_GEN 0x00040000 851 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX 0x00080000 852 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK 0x00f00000 853 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT 20 854 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val) 855 { 856 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK; 857 } 858 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK 0x07000000 859 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT 24 860 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val) 861 { 862 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK; 863 } 864 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK 0x78000000 865 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT 27 866 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val) 867 { 868 return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK; 869 } 870 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX 0x80000000 871 872 #define REG_A2XX_SQ_CONTEXT_MISC 0x00002181 873 #define A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE 0x00000001 874 #define A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY 0x00000002 875 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK 0x0000000c 876 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT 2 877 static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val) 878 { 879 return ((val) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK; 880 } 881 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK 0x0000ff00 882 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT 8 883 static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val) 884 { 885 return ((val) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK; 886 } 887 #define A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF 0x00010000 888 #define A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE 0x00020000 889 #define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL 0x00040000 890 891 #define REG_A2XX_SQ_INTERPOLATOR_CNTL 0x00002182 892 893 #define REG_A2XX_SQ_WRAPPING_0 0x00002183 894 895 #define REG_A2XX_SQ_WRAPPING_1 0x00002184 896 897 #define REG_A2XX_SQ_PS_PROGRAM 0x000021f6 898 899 #define REG_A2XX_SQ_VS_PROGRAM 0x000021f7 900 901 #define REG_A2XX_VGT_EVENT_INITIATOR 0x000021f9 902 903 #define REG_A2XX_VGT_DRAW_INITIATOR 0x000021fc 904 #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f 905 #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 906 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) 907 { 908 return ((val) << A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK; 909 } 910 #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 911 #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 912 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) 913 { 914 return ((val) << A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK; 915 } 916 #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600 917 #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9 918 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) 919 { 920 return ((val) << A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK; 921 } 922 #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800 923 #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11 924 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) 925 { 926 return ((val) << A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK; 927 } 928 #define A2XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000 929 #define A2XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000 930 #define A2XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000 931 #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK 0xff000000 932 #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT 24 933 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) 934 { 935 return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK; 936 } 937 938 #define REG_A2XX_VGT_IMMED_DATA 0x000021fd 939 940 #define REG_A2XX_RB_DEPTHCONTROL 0x00002200 941 #define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE 0x00000001 942 #define A2XX_RB_DEPTHCONTROL_Z_ENABLE 0x00000002 943 #define A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE 0x00000004 944 #define A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE 0x00000008 945 #define A2XX_RB_DEPTHCONTROL_ZFUNC__MASK 0x00000070 946 #define A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT 4 947 static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val) 948 { 949 return ((val) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK; 950 } 951 #define A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE 0x00000080 952 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK 0x00000700 953 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT 8 954 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val) 955 { 956 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK; 957 } 958 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK 0x00003800 959 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT 11 960 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val) 961 { 962 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK; 963 } 964 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK 0x0001c000 965 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT 14 966 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val) 967 { 968 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK; 969 } 970 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK 0x000e0000 971 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT 17 972 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val) 973 { 974 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK; 975 } 976 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK 0x00700000 977 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT 20 978 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val) 979 { 980 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK; 981 } 982 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK 0x03800000 983 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT 23 984 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val) 985 { 986 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK; 987 } 988 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK 0x1c000000 989 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT 26 990 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val) 991 { 992 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK; 993 } 994 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK 0xe0000000 995 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT 29 996 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val) 997 { 998 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK; 999 } 1000 1001 #define REG_A2XX_RB_BLEND_CONTROL 0x00002201 1002 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK 0x0000001f 1003 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT 0 1004 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val) 1005 { 1006 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK; 1007 } 1008 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK 0x000000e0 1009 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT 5 1010 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val) 1011 { 1012 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK; 1013 } 1014 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK 0x00001f00 1015 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT 8 1016 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val) 1017 { 1018 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK; 1019 } 1020 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK 0x001f0000 1021 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT 16 1022 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val) 1023 { 1024 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK; 1025 } 1026 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK 0x00e00000 1027 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT 21 1028 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val) 1029 { 1030 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK; 1031 } 1032 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK 0x1f000000 1033 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT 24 1034 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val) 1035 { 1036 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK; 1037 } 1038 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE 0x20000000 1039 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE 0x40000000 1040 1041 #define REG_A2XX_RB_COLORCONTROL 0x00002202 1042 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK 0x00000007 1043 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT 0 1044 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val) 1045 { 1046 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK; 1047 } 1048 #define A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE 0x00000008 1049 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE 0x00000010 1050 #define A2XX_RB_COLORCONTROL_BLEND_DISABLE 0x00000020 1051 #define A2XX_RB_COLORCONTROL_VOB_ENABLE 0x00000040 1052 #define A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG 0x00000080 1053 #define A2XX_RB_COLORCONTROL_ROP_CODE__MASK 0x00000f00 1054 #define A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT 8 1055 static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val) 1056 { 1057 return ((val) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK; 1058 } 1059 #define A2XX_RB_COLORCONTROL_DITHER_MODE__MASK 0x00003000 1060 #define A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT 12 1061 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) 1062 { 1063 return ((val) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK; 1064 } 1065 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK 0x0000c000 1066 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT 14 1067 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val) 1068 { 1069 return ((val) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK; 1070 } 1071 #define A2XX_RB_COLORCONTROL_PIXEL_FOG 0x00010000 1072 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK 0x03000000 1073 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT 24 1074 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val) 1075 { 1076 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK; 1077 } 1078 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK 0x0c000000 1079 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT 26 1080 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val) 1081 { 1082 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK; 1083 } 1084 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK 0x30000000 1085 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT 28 1086 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val) 1087 { 1088 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK; 1089 } 1090 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK 0xc0000000 1091 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT 30 1092 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val) 1093 { 1094 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK; 1095 } 1096 1097 #define REG_A2XX_VGT_CURRENT_BIN_ID_MAX 0x00002203 1098 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK 0x00000007 1099 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT 0 1100 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val) 1101 { 1102 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK; 1103 } 1104 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK 0x00000038 1105 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT 3 1106 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val) 1107 { 1108 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK; 1109 } 1110 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK 0x000001c0 1111 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT 6 1112 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val) 1113 { 1114 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK; 1115 } 1116 1117 #define REG_A2XX_PA_CL_CLIP_CNTL 0x00002204 1118 #define A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 1119 #define A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA 0x00040000 1120 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK 0x00080000 1121 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT 19 1122 static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val) 1123 { 1124 return ((val) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK; 1125 } 1126 #define A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT 0x00100000 1127 #define A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR 0x00200000 1128 #define A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN 0x00400000 1129 #define A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN 0x00800000 1130 #define A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN 0x01000000 1131 1132 #define REG_A2XX_PA_SU_SC_MODE_CNTL 0x00002205 1133 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT 0x00000001 1134 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK 0x00000002 1135 #define A2XX_PA_SU_SC_MODE_CNTL_FACE 0x00000004 1136 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK 0x00000018 1137 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT 3 1138 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val) 1139 { 1140 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK; 1141 } 1142 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK 0x000000e0 1143 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT 5 1144 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 1145 { 1146 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK; 1147 } 1148 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK 0x00000700 1149 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT 8 1150 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 1151 { 1152 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK; 1153 } 1154 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE 0x00000800 1155 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE 0x00001000 1156 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE 0x00002000 1157 #define A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE 0x00008000 1158 #define A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE 0x00010000 1159 #define A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE 0x00040000 1160 #define A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST 0x00080000 1161 #define A2XX_PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS 0x00100000 1162 #define A2XX_PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA 0x00200000 1163 #define A2XX_PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE 0x00800000 1164 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI 0x02000000 1165 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000 1166 #define A2XX_PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS 0x10000000 1167 #define A2XX_PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS 0x20000000 1168 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE 0x40000000 1169 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE 0x80000000 1170 1171 #define REG_A2XX_PA_CL_VTE_CNTL 0x00002206 1172 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA 0x00000001 1173 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA 0x00000002 1174 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA 0x00000004 1175 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA 0x00000008 1176 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA 0x00000010 1177 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA 0x00000020 1178 #define A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT 0x00000100 1179 #define A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT 0x00000200 1180 #define A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT 0x00000400 1181 #define A2XX_PA_CL_VTE_CNTL_PERFCOUNTER_REF 0x00000800 1182 1183 #define REG_A2XX_VGT_CURRENT_BIN_ID_MIN 0x00002207 1184 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK 0x00000007 1185 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT 0 1186 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val) 1187 { 1188 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK; 1189 } 1190 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK 0x00000038 1191 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT 3 1192 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val) 1193 { 1194 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK; 1195 } 1196 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK 0x000001c0 1197 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT 6 1198 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val) 1199 { 1200 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK; 1201 } 1202 1203 #define REG_A2XX_RB_MODECONTROL 0x00002208 1204 #define A2XX_RB_MODECONTROL_EDRAM_MODE__MASK 0x00000007 1205 #define A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT 0 1206 static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val) 1207 { 1208 return ((val) << A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT) & A2XX_RB_MODECONTROL_EDRAM_MODE__MASK; 1209 } 1210 1211 #define REG_A2XX_A220_RB_LRZ_VSC_CONTROL 0x00002209 1212 1213 #define REG_A2XX_RB_SAMPLE_POS 0x0000220a 1214 1215 #define REG_A2XX_CLEAR_COLOR 0x0000220b 1216 #define A2XX_CLEAR_COLOR_RED__MASK 0x000000ff 1217 #define A2XX_CLEAR_COLOR_RED__SHIFT 0 1218 static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val) 1219 { 1220 return ((val) << A2XX_CLEAR_COLOR_RED__SHIFT) & A2XX_CLEAR_COLOR_RED__MASK; 1221 } 1222 #define A2XX_CLEAR_COLOR_GREEN__MASK 0x0000ff00 1223 #define A2XX_CLEAR_COLOR_GREEN__SHIFT 8 1224 static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val) 1225 { 1226 return ((val) << A2XX_CLEAR_COLOR_GREEN__SHIFT) & A2XX_CLEAR_COLOR_GREEN__MASK; 1227 } 1228 #define A2XX_CLEAR_COLOR_BLUE__MASK 0x00ff0000 1229 #define A2XX_CLEAR_COLOR_BLUE__SHIFT 16 1230 static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val) 1231 { 1232 return ((val) << A2XX_CLEAR_COLOR_BLUE__SHIFT) & A2XX_CLEAR_COLOR_BLUE__MASK; 1233 } 1234 #define A2XX_CLEAR_COLOR_ALPHA__MASK 0xff000000 1235 #define A2XX_CLEAR_COLOR_ALPHA__SHIFT 24 1236 static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val) 1237 { 1238 return ((val) << A2XX_CLEAR_COLOR_ALPHA__SHIFT) & A2XX_CLEAR_COLOR_ALPHA__MASK; 1239 } 1240 1241 #define REG_A2XX_A220_GRAS_CONTROL 0x00002210 1242 1243 #define REG_A2XX_PA_SU_POINT_SIZE 0x00002280 1244 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK 0x0000ffff 1245 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT 0 1246 static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val) 1247 { 1248 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK; 1249 } 1250 #define A2XX_PA_SU_POINT_SIZE_WIDTH__MASK 0xffff0000 1251 #define A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT 16 1252 static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val) 1253 { 1254 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK; 1255 } 1256 1257 #define REG_A2XX_PA_SU_POINT_MINMAX 0x00002281 1258 #define A2XX_PA_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 1259 #define A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT 0 1260 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val) 1261 { 1262 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK; 1263 } 1264 #define A2XX_PA_SU_POINT_MINMAX_MAX__MASK 0xffff0000 1265 #define A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT 16 1266 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val) 1267 { 1268 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK; 1269 } 1270 1271 #define REG_A2XX_PA_SU_LINE_CNTL 0x00002282 1272 #define A2XX_PA_SU_LINE_CNTL_WIDTH__MASK 0x0000ffff 1273 #define A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT 0 1274 static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val) 1275 { 1276 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK; 1277 } 1278 1279 #define REG_A2XX_PA_SC_LINE_STIPPLE 0x00002283 1280 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK 0x0000ffff 1281 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT 0 1282 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val) 1283 { 1284 return ((val) << A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK; 1285 } 1286 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK 0x00ff0000 1287 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT 16 1288 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val) 1289 { 1290 return ((val) << A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK; 1291 } 1292 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK 0x10000000 1293 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT 28 1294 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val) 1295 { 1296 return ((val) << A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK; 1297 } 1298 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK 0x60000000 1299 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT 29 1300 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val) 1301 { 1302 return ((val) << A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK; 1303 } 1304 1305 #define REG_A2XX_PA_SC_VIZ_QUERY 0x00002293 1306 1307 #define REG_A2XX_VGT_ENHANCE 0x00002294 1308 1309 #define REG_A2XX_PA_SC_LINE_CNTL 0x00002300 1310 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK 0x0000ffff 1311 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT 0 1312 static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val) 1313 { 1314 return ((val) << A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT) & A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK; 1315 } 1316 #define A2XX_PA_SC_LINE_CNTL_USE_BRES_CNTL 0x00000100 1317 #define A2XX_PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH 0x00000200 1318 #define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL 0x00000400 1319 1320 #define REG_A2XX_PA_SC_AA_CONFIG 0x00002301 1321 1322 #define REG_A2XX_PA_SU_VTX_CNTL 0x00002302 1323 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK 0x00000001 1324 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT 0 1325 static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val) 1326 { 1327 return ((val) << A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT) & A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK; 1328 } 1329 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK 0x00000006 1330 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT 1 1331 static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val) 1332 { 1333 return ((val) << A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK; 1334 } 1335 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK 0x00000380 1336 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT 7 1337 static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val) 1338 { 1339 return ((val) << A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK; 1340 } 1341 1342 #define REG_A2XX_PA_CL_GB_VERT_CLIP_ADJ 0x00002303 1343 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK 0xffffffff 1344 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT 0 1345 static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val) 1346 { 1347 return ((fui(val)) << A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK; 1348 } 1349 1350 #define REG_A2XX_PA_CL_GB_VERT_DISC_ADJ 0x00002304 1351 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK 0xffffffff 1352 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT 0 1353 static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val) 1354 { 1355 return ((fui(val)) << A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK; 1356 } 1357 1358 #define REG_A2XX_PA_CL_GB_HORZ_CLIP_ADJ 0x00002305 1359 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK 0xffffffff 1360 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT 0 1361 static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val) 1362 { 1363 return ((fui(val)) << A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK; 1364 } 1365 1366 #define REG_A2XX_PA_CL_GB_HORZ_DISC_ADJ 0x00002306 1367 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK 0xffffffff 1368 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT 0 1369 static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val) 1370 { 1371 return ((fui(val)) << A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK; 1372 } 1373 1374 #define REG_A2XX_SQ_VS_CONST 0x00002307 1375 #define A2XX_SQ_VS_CONST_BASE__MASK 0x000001ff 1376 #define A2XX_SQ_VS_CONST_BASE__SHIFT 0 1377 static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val) 1378 { 1379 return ((val) << A2XX_SQ_VS_CONST_BASE__SHIFT) & A2XX_SQ_VS_CONST_BASE__MASK; 1380 } 1381 #define A2XX_SQ_VS_CONST_SIZE__MASK 0x001ff000 1382 #define A2XX_SQ_VS_CONST_SIZE__SHIFT 12 1383 static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val) 1384 { 1385 return ((val) << A2XX_SQ_VS_CONST_SIZE__SHIFT) & A2XX_SQ_VS_CONST_SIZE__MASK; 1386 } 1387 1388 #define REG_A2XX_SQ_PS_CONST 0x00002308 1389 #define A2XX_SQ_PS_CONST_BASE__MASK 0x000001ff 1390 #define A2XX_SQ_PS_CONST_BASE__SHIFT 0 1391 static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val) 1392 { 1393 return ((val) << A2XX_SQ_PS_CONST_BASE__SHIFT) & A2XX_SQ_PS_CONST_BASE__MASK; 1394 } 1395 #define A2XX_SQ_PS_CONST_SIZE__MASK 0x001ff000 1396 #define A2XX_SQ_PS_CONST_SIZE__SHIFT 12 1397 static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val) 1398 { 1399 return ((val) << A2XX_SQ_PS_CONST_SIZE__SHIFT) & A2XX_SQ_PS_CONST_SIZE__MASK; 1400 } 1401 1402 #define REG_A2XX_SQ_DEBUG_MISC_0 0x00002309 1403 1404 #define REG_A2XX_SQ_DEBUG_MISC_1 0x0000230a 1405 1406 #define REG_A2XX_PA_SC_AA_MASK 0x00002312 1407 1408 #define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL 0x00002316 1409 1410 #define REG_A2XX_VGT_OUT_DEALLOC_CNTL 0x00002317 1411 1412 #define REG_A2XX_RB_COPY_CONTROL 0x00002318 1413 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK 0x00000007 1414 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT 0 1415 static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val) 1416 { 1417 return ((val) << A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT) & A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK; 1418 } 1419 #define A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE 0x00000008 1420 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK 0x000000f0 1421 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT 4 1422 static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val) 1423 { 1424 return ((val) << A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT) & A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK; 1425 } 1426 1427 #define REG_A2XX_RB_COPY_DEST_BASE 0x00002319 1428 1429 #define REG_A2XX_RB_COPY_DEST_PITCH 0x0000231a 1430 #define A2XX_RB_COPY_DEST_PITCH__MASK 0xffffffff 1431 #define A2XX_RB_COPY_DEST_PITCH__SHIFT 0 1432 static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val) 1433 { 1434 return ((val >> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK; 1435 } 1436 1437 #define REG_A2XX_RB_COPY_DEST_INFO 0x0000231b 1438 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK 0x00000007 1439 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT 0 1440 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val) 1441 { 1442 return ((val) << A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT) & A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK; 1443 } 1444 #define A2XX_RB_COPY_DEST_INFO_LINEAR 0x00000008 1445 #define A2XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000f0 1446 #define A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 4 1447 static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val) 1448 { 1449 return ((val) << A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A2XX_RB_COPY_DEST_INFO_FORMAT__MASK; 1450 } 1451 #define A2XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 1452 #define A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 1453 static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val) 1454 { 1455 return ((val) << A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A2XX_RB_COPY_DEST_INFO_SWAP__MASK; 1456 } 1457 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 1458 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 1459 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 1460 { 1461 return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 1462 } 1463 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK 0x00003000 1464 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT 12 1465 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val) 1466 { 1467 return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK; 1468 } 1469 #define A2XX_RB_COPY_DEST_INFO_WRITE_RED 0x00004000 1470 #define A2XX_RB_COPY_DEST_INFO_WRITE_GREEN 0x00008000 1471 #define A2XX_RB_COPY_DEST_INFO_WRITE_BLUE 0x00010000 1472 #define A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA 0x00020000 1473 1474 #define REG_A2XX_RB_COPY_DEST_OFFSET 0x0000231c 1475 #define A2XX_RB_COPY_DEST_OFFSET_X__MASK 0x00001fff 1476 #define A2XX_RB_COPY_DEST_OFFSET_X__SHIFT 0 1477 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val) 1478 { 1479 return ((val) << A2XX_RB_COPY_DEST_OFFSET_X__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_X__MASK; 1480 } 1481 #define A2XX_RB_COPY_DEST_OFFSET_Y__MASK 0x03ffe000 1482 #define A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT 13 1483 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val) 1484 { 1485 return ((val) << A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_Y__MASK; 1486 } 1487 1488 #define REG_A2XX_RB_DEPTH_CLEAR 0x0000231d 1489 1490 #define REG_A2XX_RB_SAMPLE_COUNT_CTL 0x00002324 1491 1492 #define REG_A2XX_RB_COLOR_DEST_MASK 0x00002326 1493 1494 #define REG_A2XX_A225_GRAS_UCP0X 0x00002340 1495 1496 #define REG_A2XX_A225_GRAS_UCP5W 0x00002357 1497 1498 #define REG_A2XX_A225_GRAS_UCP_ENABLED 0x00002360 1499 1500 #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE 0x00002380 1501 1502 #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET 0x00002383 1503 1504 #define REG_A2XX_SQ_CONSTANT_0 0x00004000 1505 1506 #define REG_A2XX_SQ_FETCH_0 0x00004800 1507 1508 #define REG_A2XX_SQ_CF_BOOLEANS 0x00004900 1509 1510 #define REG_A2XX_SQ_CF_LOOP 0x00004908 1511 1512 #define REG_A2XX_COHER_SIZE_PM4 0x00000a29 1513 1514 #define REG_A2XX_COHER_BASE_PM4 0x00000a2a 1515 1516 #define REG_A2XX_COHER_STATUS_PM4 0x00000a2b 1517 1518 #define REG_A2XX_SQ_TEX_0 0x00000000 1519 #define A2XX_SQ_TEX_0_CLAMP_X__MASK 0x00001c00 1520 #define A2XX_SQ_TEX_0_CLAMP_X__SHIFT 10 1521 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val) 1522 { 1523 return ((val) << A2XX_SQ_TEX_0_CLAMP_X__SHIFT) & A2XX_SQ_TEX_0_CLAMP_X__MASK; 1524 } 1525 #define A2XX_SQ_TEX_0_CLAMP_Y__MASK 0x0000e000 1526 #define A2XX_SQ_TEX_0_CLAMP_Y__SHIFT 13 1527 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val) 1528 { 1529 return ((val) << A2XX_SQ_TEX_0_CLAMP_Y__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Y__MASK; 1530 } 1531 #define A2XX_SQ_TEX_0_CLAMP_Z__MASK 0x00070000 1532 #define A2XX_SQ_TEX_0_CLAMP_Z__SHIFT 16 1533 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val) 1534 { 1535 return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK; 1536 } 1537 #define A2XX_SQ_TEX_0_PITCH__MASK 0xffc00000 1538 #define A2XX_SQ_TEX_0_PITCH__SHIFT 22 1539 static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val) 1540 { 1541 return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK; 1542 } 1543 1544 #define REG_A2XX_SQ_TEX_1 0x00000001 1545 1546 #define REG_A2XX_SQ_TEX_2 0x00000002 1547 #define A2XX_SQ_TEX_2_WIDTH__MASK 0x00001fff 1548 #define A2XX_SQ_TEX_2_WIDTH__SHIFT 0 1549 static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val) 1550 { 1551 return ((val) << A2XX_SQ_TEX_2_WIDTH__SHIFT) & A2XX_SQ_TEX_2_WIDTH__MASK; 1552 } 1553 #define A2XX_SQ_TEX_2_HEIGHT__MASK 0x03ffe000 1554 #define A2XX_SQ_TEX_2_HEIGHT__SHIFT 13 1555 static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val) 1556 { 1557 return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK; 1558 } 1559 1560 #define REG_A2XX_SQ_TEX_3 0x00000003 1561 #define A2XX_SQ_TEX_3_SWIZ_X__MASK 0x0000000e 1562 #define A2XX_SQ_TEX_3_SWIZ_X__SHIFT 1 1563 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val) 1564 { 1565 return ((val) << A2XX_SQ_TEX_3_SWIZ_X__SHIFT) & A2XX_SQ_TEX_3_SWIZ_X__MASK; 1566 } 1567 #define A2XX_SQ_TEX_3_SWIZ_Y__MASK 0x00000070 1568 #define A2XX_SQ_TEX_3_SWIZ_Y__SHIFT 4 1569 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val) 1570 { 1571 return ((val) << A2XX_SQ_TEX_3_SWIZ_Y__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Y__MASK; 1572 } 1573 #define A2XX_SQ_TEX_3_SWIZ_Z__MASK 0x00000380 1574 #define A2XX_SQ_TEX_3_SWIZ_Z__SHIFT 7 1575 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val) 1576 { 1577 return ((val) << A2XX_SQ_TEX_3_SWIZ_Z__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Z__MASK; 1578 } 1579 #define A2XX_SQ_TEX_3_SWIZ_W__MASK 0x00001c00 1580 #define A2XX_SQ_TEX_3_SWIZ_W__SHIFT 10 1581 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val) 1582 { 1583 return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK; 1584 } 1585 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK 0x00180000 1586 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT 19 1587 static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val) 1588 { 1589 return ((val) << A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK; 1590 } 1591 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK 0x00600000 1592 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT 21 1593 static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val) 1594 { 1595 return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK; 1596 } 1597 1598 1599 #endif /* A2XX_XML */ 1600