1 #ifndef A2XX_XML 2 #define A2XX_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13) 12 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13) 13 - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03) 14 - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14201 bytes, from 2018-12-02 17:29:54) 15 - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-02 17:29:54) 16 - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13) 17 - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13) 18 - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54) 19 - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54) 20 - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07) 21 - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13) 22 23 Copyright (C) 2013-2018 by the following authors: 24 - Rob Clark <robdclark@gmail.com> (robclark) 25 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 26 27 Permission is hereby granted, free of charge, to any person obtaining 28 a copy of this software and associated documentation files (the 29 "Software"), to deal in the Software without restriction, including 30 without limitation the rights to use, copy, modify, merge, publish, 31 distribute, sublicense, and/or sell copies of the Software, and to 32 permit persons to whom the Software is furnished to do so, subject to 33 the following conditions: 34 35 The above copyright notice and this permission notice (including the 36 next paragraph) shall be included in all copies or substantial 37 portions of the Software. 38 39 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 40 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 41 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 42 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 43 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 44 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 45 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48 49 enum a2xx_rb_dither_type { 50 DITHER_PIXEL = 0, 51 DITHER_SUBPIXEL = 1, 52 }; 53 54 enum a2xx_colorformatx { 55 COLORX_4_4_4_4 = 0, 56 COLORX_1_5_5_5 = 1, 57 COLORX_5_6_5 = 2, 58 COLORX_8 = 3, 59 COLORX_8_8 = 4, 60 COLORX_8_8_8_8 = 5, 61 COLORX_S8_8_8_8 = 6, 62 COLORX_16_FLOAT = 7, 63 COLORX_16_16_FLOAT = 8, 64 COLORX_16_16_16_16_FLOAT = 9, 65 COLORX_32_FLOAT = 10, 66 COLORX_32_32_FLOAT = 11, 67 COLORX_32_32_32_32_FLOAT = 12, 68 COLORX_2_3_3 = 13, 69 COLORX_8_8_8 = 14, 70 }; 71 72 enum a2xx_sq_surfaceformat { 73 FMT_1_REVERSE = 0, 74 FMT_1 = 1, 75 FMT_8 = 2, 76 FMT_1_5_5_5 = 3, 77 FMT_5_6_5 = 4, 78 FMT_6_5_5 = 5, 79 FMT_8_8_8_8 = 6, 80 FMT_2_10_10_10 = 7, 81 FMT_8_A = 8, 82 FMT_8_B = 9, 83 FMT_8_8 = 10, 84 FMT_Cr_Y1_Cb_Y0 = 11, 85 FMT_Y1_Cr_Y0_Cb = 12, 86 FMT_5_5_5_1 = 13, 87 FMT_8_8_8_8_A = 14, 88 FMT_4_4_4_4 = 15, 89 FMT_8_8_8 = 16, 90 FMT_DXT1 = 18, 91 FMT_DXT2_3 = 19, 92 FMT_DXT4_5 = 20, 93 FMT_10_10_10_2 = 21, 94 FMT_24_8 = 22, 95 FMT_16 = 24, 96 FMT_16_16 = 25, 97 FMT_16_16_16_16 = 26, 98 FMT_16_EXPAND = 27, 99 FMT_16_16_EXPAND = 28, 100 FMT_16_16_16_16_EXPAND = 29, 101 FMT_16_FLOAT = 30, 102 FMT_16_16_FLOAT = 31, 103 FMT_16_16_16_16_FLOAT = 32, 104 FMT_32 = 33, 105 FMT_32_32 = 34, 106 FMT_32_32_32_32 = 35, 107 FMT_32_FLOAT = 36, 108 FMT_32_32_FLOAT = 37, 109 FMT_32_32_32_32_FLOAT = 38, 110 FMT_ATI_TC_RGB = 39, 111 FMT_ATI_TC_RGBA = 40, 112 FMT_ATI_TC_555_565_RGB = 41, 113 FMT_ATI_TC_555_565_RGBA = 42, 114 FMT_ATI_TC_RGBA_INTERP = 43, 115 FMT_ATI_TC_555_565_RGBA_INTERP = 44, 116 FMT_ETC1_RGBA_INTERP = 46, 117 FMT_ETC1_RGB = 47, 118 FMT_ETC1_RGBA = 48, 119 FMT_DXN = 49, 120 FMT_2_3_3 = 51, 121 FMT_2_10_10_10_AS_16_16_16_16 = 54, 122 FMT_10_10_10_2_AS_16_16_16_16 = 55, 123 FMT_32_32_32_FLOAT = 57, 124 FMT_DXT3A = 58, 125 FMT_DXT5A = 59, 126 FMT_CTX1 = 60, 127 }; 128 129 enum a2xx_sq_ps_vtx_mode { 130 POSITION_1_VECTOR = 0, 131 POSITION_2_VECTORS_UNUSED = 1, 132 POSITION_2_VECTORS_SPRITE = 2, 133 POSITION_2_VECTORS_EDGE = 3, 134 POSITION_2_VECTORS_KILL = 4, 135 POSITION_2_VECTORS_SPRITE_KILL = 5, 136 POSITION_2_VECTORS_EDGE_KILL = 6, 137 MULTIPASS = 7, 138 }; 139 140 enum a2xx_sq_sample_cntl { 141 CENTROIDS_ONLY = 0, 142 CENTERS_ONLY = 1, 143 CENTROIDS_AND_CENTERS = 2, 144 }; 145 146 enum a2xx_dx_clip_space { 147 DXCLIP_OPENGL = 0, 148 DXCLIP_DIRECTX = 1, 149 }; 150 151 enum a2xx_pa_su_sc_polymode { 152 POLY_DISABLED = 0, 153 POLY_DUALMODE = 1, 154 }; 155 156 enum a2xx_rb_edram_mode { 157 EDRAM_NOP = 0, 158 COLOR_DEPTH = 4, 159 DEPTH_ONLY = 5, 160 EDRAM_COPY = 6, 161 }; 162 163 enum a2xx_pa_sc_pattern_bit_order { 164 LITTLE = 0, 165 BIG = 1, 166 }; 167 168 enum a2xx_pa_sc_auto_reset_cntl { 169 NEVER = 0, 170 EACH_PRIMITIVE = 1, 171 EACH_PACKET = 2, 172 }; 173 174 enum a2xx_pa_pixcenter { 175 PIXCENTER_D3D = 0, 176 PIXCENTER_OGL = 1, 177 }; 178 179 enum a2xx_pa_roundmode { 180 TRUNCATE = 0, 181 ROUND = 1, 182 ROUNDTOEVEN = 2, 183 ROUNDTOODD = 3, 184 }; 185 186 enum a2xx_pa_quantmode { 187 ONE_SIXTEENTH = 0, 188 ONE_EIGTH = 1, 189 ONE_QUARTER = 2, 190 ONE_HALF = 3, 191 ONE = 4, 192 }; 193 194 enum a2xx_rb_copy_sample_select { 195 SAMPLE_0 = 0, 196 SAMPLE_1 = 1, 197 SAMPLE_2 = 2, 198 SAMPLE_3 = 3, 199 SAMPLE_01 = 4, 200 SAMPLE_23 = 5, 201 SAMPLE_0123 = 6, 202 }; 203 204 enum a2xx_rb_blend_opcode { 205 BLEND2_DST_PLUS_SRC = 0, 206 BLEND2_SRC_MINUS_DST = 1, 207 BLEND2_MIN_DST_SRC = 2, 208 BLEND2_MAX_DST_SRC = 3, 209 BLEND2_DST_MINUS_SRC = 4, 210 BLEND2_DST_PLUS_SRC_BIAS = 5, 211 }; 212 213 enum adreno_mmu_clnt_beh { 214 BEH_NEVR = 0, 215 BEH_TRAN_RNG = 1, 216 BEH_TRAN_FLT = 2, 217 }; 218 219 enum sq_tex_clamp { 220 SQ_TEX_WRAP = 0, 221 SQ_TEX_MIRROR = 1, 222 SQ_TEX_CLAMP_LAST_TEXEL = 2, 223 SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3, 224 SQ_TEX_CLAMP_HALF_BORDER = 4, 225 SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5, 226 SQ_TEX_CLAMP_BORDER = 6, 227 SQ_TEX_MIRROR_ONCE_BORDER = 7, 228 }; 229 230 enum sq_tex_swiz { 231 SQ_TEX_X = 0, 232 SQ_TEX_Y = 1, 233 SQ_TEX_Z = 2, 234 SQ_TEX_W = 3, 235 SQ_TEX_ZERO = 4, 236 SQ_TEX_ONE = 5, 237 }; 238 239 enum sq_tex_filter { 240 SQ_TEX_FILTER_POINT = 0, 241 SQ_TEX_FILTER_BILINEAR = 1, 242 SQ_TEX_FILTER_BASEMAP = 2, 243 SQ_TEX_FILTER_USE_FETCH_CONST = 3, 244 }; 245 246 enum sq_tex_aniso_filter { 247 SQ_TEX_ANISO_FILTER_DISABLED = 0, 248 SQ_TEX_ANISO_FILTER_MAX_1_1 = 1, 249 SQ_TEX_ANISO_FILTER_MAX_2_1 = 2, 250 SQ_TEX_ANISO_FILTER_MAX_4_1 = 3, 251 SQ_TEX_ANISO_FILTER_MAX_8_1 = 4, 252 SQ_TEX_ANISO_FILTER_MAX_16_1 = 5, 253 SQ_TEX_ANISO_FILTER_USE_FETCH_CONST = 7, 254 }; 255 256 enum sq_tex_dimension { 257 SQ_TEX_DIMENSION_1D = 0, 258 SQ_TEX_DIMENSION_2D = 1, 259 SQ_TEX_DIMENSION_3D = 2, 260 SQ_TEX_DIMENSION_CUBE = 3, 261 }; 262 263 enum sq_tex_border_color { 264 SQ_TEX_BORDER_COLOR_BLACK = 0, 265 SQ_TEX_BORDER_COLOR_WHITE = 1, 266 SQ_TEX_BORDER_COLOR_ACBYCR_BLACK = 2, 267 SQ_TEX_BORDER_COLOR_ACBCRY_BLACK = 3, 268 }; 269 270 enum sq_tex_sign { 271 SQ_TEX_SIGN_UNISIGNED = 0, 272 SQ_TEX_SIGN_SIGNED = 1, 273 SQ_TEX_SIGN_UNISIGNED_BIASED = 2, 274 SQ_TEX_SIGN_GAMMA = 3, 275 }; 276 277 enum sq_tex_endian { 278 SQ_TEX_ENDIAN_NONE = 0, 279 SQ_TEX_ENDIAN_8IN16 = 1, 280 SQ_TEX_ENDIAN_8IN32 = 2, 281 SQ_TEX_ENDIAN_16IN32 = 3, 282 }; 283 284 enum sq_tex_clamp_policy { 285 SQ_TEX_CLAMP_POLICY_D3D = 0, 286 SQ_TEX_CLAMP_POLICY_OGL = 1, 287 }; 288 289 enum sq_tex_num_format { 290 SQ_TEX_NUM_FORMAT_FRAC = 0, 291 SQ_TEX_NUM_FORMAT_INT = 1, 292 }; 293 294 enum sq_tex_type { 295 SQ_TEX_TYPE_0 = 0, 296 SQ_TEX_TYPE_1 = 1, 297 SQ_TEX_TYPE_2 = 2, 298 SQ_TEX_TYPE_3 = 3, 299 }; 300 301 #define REG_A2XX_RBBM_PATCH_RELEASE 0x00000001 302 303 #define REG_A2XX_RBBM_CNTL 0x0000003b 304 305 #define REG_A2XX_RBBM_SOFT_RESET 0x0000003c 306 307 #define REG_A2XX_CP_PFP_UCODE_ADDR 0x000000c0 308 309 #define REG_A2XX_CP_PFP_UCODE_DATA 0x000000c1 310 311 #define REG_A2XX_MH_MMU_CONFIG 0x00000040 312 #define A2XX_MH_MMU_CONFIG_MMU_ENABLE 0x00000001 313 #define A2XX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE 0x00000002 314 #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK 0x00000030 315 #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT 4 316 static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 317 { 318 return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK; 319 } 320 #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK 0x000000c0 321 #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT 6 322 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 323 { 324 return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK; 325 } 326 #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK 0x00000300 327 #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT 8 328 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 329 { 330 return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK; 331 } 332 #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK 0x00000c00 333 #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT 10 334 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 335 { 336 return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK; 337 } 338 #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK 0x00003000 339 #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT 12 340 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 341 { 342 return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK; 343 } 344 #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK 0x0000c000 345 #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT 14 346 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 347 { 348 return ((val) << A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK; 349 } 350 #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK 0x00030000 351 #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT 16 352 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 353 { 354 return ((val) << A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK; 355 } 356 #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK 0x000c0000 357 #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT 18 358 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 359 { 360 return ((val) << A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK; 361 } 362 #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK 0x00300000 363 #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT 20 364 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 365 { 366 return ((val) << A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK; 367 } 368 #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK 0x00c00000 369 #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT 22 370 static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 371 { 372 return ((val) << A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK; 373 } 374 #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK 0x03000000 375 #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT 24 376 static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 377 { 378 return ((val) << A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK; 379 } 380 381 #define REG_A2XX_MH_MMU_VA_RANGE 0x00000041 382 #define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK 0x00000fff 383 #define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT 0 384 static inline uint32_t A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS(uint32_t val) 385 { 386 return ((val) << A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT) & A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK; 387 } 388 #define A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK 0xfffff000 389 #define A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT 12 390 static inline uint32_t A2XX_MH_MMU_VA_RANGE_VA_BASE(uint32_t val) 391 { 392 return ((val) << A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT) & A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK; 393 } 394 395 #define REG_A2XX_MH_MMU_PT_BASE 0x00000042 396 397 #define REG_A2XX_MH_MMU_PAGE_FAULT 0x00000043 398 399 #define REG_A2XX_MH_MMU_TRAN_ERROR 0x00000044 400 401 #define REG_A2XX_MH_MMU_INVALIDATE 0x00000045 402 #define A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL 0x00000001 403 #define A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC 0x00000002 404 405 #define REG_A2XX_MH_MMU_MPU_BASE 0x00000046 406 407 #define REG_A2XX_MH_MMU_MPU_END 0x00000047 408 409 #define REG_A2XX_NQWAIT_UNTIL 0x00000394 410 411 #define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395 412 413 #define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397 414 415 #define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x00000398 416 417 #define REG_A2XX_RBBM_DEBUG 0x0000039b 418 419 #define REG_A2XX_RBBM_PM_OVERRIDE1 0x0000039c 420 #define A2XX_RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE 0x00000001 421 #define A2XX_RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE 0x00000002 422 #define A2XX_RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE 0x00000004 423 #define A2XX_RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE 0x00000008 424 #define A2XX_RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE 0x00000010 425 #define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE 0x00000020 426 #define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE 0x00000040 427 #define A2XX_RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE 0x00000080 428 #define A2XX_RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE 0x00000100 429 #define A2XX_RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE 0x00000200 430 #define A2XX_RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE 0x00000400 431 #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE 0x00000800 432 #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE 0x00001000 433 #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE 0x00002000 434 #define A2XX_RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE 0x00004000 435 #define A2XX_RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE 0x00008000 436 #define A2XX_RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE 0x00010000 437 #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE 0x00020000 438 #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE 0x00040000 439 #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE 0x00080000 440 #define A2XX_RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE 0x00100000 441 #define A2XX_RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE 0x00200000 442 #define A2XX_RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE 0x00400000 443 #define A2XX_RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE 0x00800000 444 #define A2XX_RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE 0x01000000 445 #define A2XX_RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE 0x02000000 446 #define A2XX_RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE 0x04000000 447 #define A2XX_RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE 0x08000000 448 #define A2XX_RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE 0x10000000 449 #define A2XX_RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE 0x20000000 450 #define A2XX_RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE 0x40000000 451 #define A2XX_RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE 0x80000000 452 453 #define REG_A2XX_RBBM_PM_OVERRIDE2 0x0000039d 454 455 #define REG_A2XX_RBBM_DEBUG_OUT 0x000003a0 456 457 #define REG_A2XX_RBBM_DEBUG_CNTL 0x000003a1 458 459 #define REG_A2XX_RBBM_READ_ERROR 0x000003b3 460 461 #define REG_A2XX_RBBM_INT_CNTL 0x000003b4 462 #define A2XX_RBBM_INT_CNTL_RDERR_INT_MASK 0x00000001 463 #define A2XX_RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK 0x00000002 464 #define A2XX_RBBM_INT_CNTL_GUI_IDLE_INT_MASK 0x00080000 465 466 #define REG_A2XX_RBBM_INT_STATUS 0x000003b5 467 468 #define REG_A2XX_RBBM_INT_ACK 0x000003b6 469 470 #define REG_A2XX_MASTER_INT_SIGNAL 0x000003b7 471 #define A2XX_MASTER_INT_SIGNAL_MH_INT_STAT 0x00000020 472 #define A2XX_MASTER_INT_SIGNAL_SQ_INT_STAT 0x04000000 473 #define A2XX_MASTER_INT_SIGNAL_CP_INT_STAT 0x40000000 474 #define A2XX_MASTER_INT_SIGNAL_RBBM_INT_STAT 0x80000000 475 476 #define REG_A2XX_RBBM_PERIPHID1 0x000003f9 477 478 #define REG_A2XX_RBBM_PERIPHID2 0x000003fa 479 480 #define REG_A2XX_CP_PERFMON_CNTL 0x00000444 481 482 #define REG_A2XX_CP_PERFCOUNTER_SELECT 0x00000445 483 484 #define REG_A2XX_CP_PERFCOUNTER_LO 0x00000446 485 486 #define REG_A2XX_CP_PERFCOUNTER_HI 0x00000447 487 488 #define REG_A2XX_RBBM_STATUS 0x000005d0 489 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK 0x0000001f 490 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT 0 491 static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val) 492 { 493 return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK; 494 } 495 #define A2XX_RBBM_STATUS_TC_BUSY 0x00000020 496 #define A2XX_RBBM_STATUS_HIRQ_PENDING 0x00000100 497 #define A2XX_RBBM_STATUS_CPRQ_PENDING 0x00000200 498 #define A2XX_RBBM_STATUS_CFRQ_PENDING 0x00000400 499 #define A2XX_RBBM_STATUS_PFRQ_PENDING 0x00000800 500 #define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA 0x00001000 501 #define A2XX_RBBM_STATUS_RBBM_WU_BUSY 0x00004000 502 #define A2XX_RBBM_STATUS_CP_NRT_BUSY 0x00010000 503 #define A2XX_RBBM_STATUS_MH_BUSY 0x00040000 504 #define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY 0x00080000 505 #define A2XX_RBBM_STATUS_SX_BUSY 0x00200000 506 #define A2XX_RBBM_STATUS_TPC_BUSY 0x00400000 507 #define A2XX_RBBM_STATUS_SC_CNTX_BUSY 0x01000000 508 #define A2XX_RBBM_STATUS_PA_BUSY 0x02000000 509 #define A2XX_RBBM_STATUS_VGT_BUSY 0x04000000 510 #define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY 0x08000000 511 #define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY 0x10000000 512 #define A2XX_RBBM_STATUS_RB_CNTX_BUSY 0x40000000 513 #define A2XX_RBBM_STATUS_GUI_ACTIVE 0x80000000 514 515 #define REG_A2XX_MH_ARBITER_CONFIG 0x00000a40 516 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK 0x0000003f 517 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT 0 518 static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val) 519 { 520 return ((val) << A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK; 521 } 522 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY 0x00000040 523 #define A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE 0x00000080 524 #define A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE 0x00000100 525 #define A2XX_MH_ARBITER_CONFIG_L2_ARB_CONTROL 0x00000200 526 #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK 0x00001c00 527 #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT 10 528 static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val) 529 { 530 return ((val) << A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT) & A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK; 531 } 532 #define A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00002000 533 #define A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE 0x00004000 534 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE 0x00008000 535 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK 0x003f0000 536 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT 16 537 static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val) 538 { 539 return ((val) << A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK; 540 } 541 #define A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE 0x00400000 542 #define A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE 0x00800000 543 #define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE 0x01000000 544 #define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE 0x02000000 545 #define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE 0x04000000 546 547 #define REG_A2XX_MH_INTERRUPT_MASK 0x00000a42 548 #define A2XX_MH_INTERRUPT_MASK_AXI_READ_ERROR 0x00000001 549 #define A2XX_MH_INTERRUPT_MASK_AXI_WRITE_ERROR 0x00000002 550 #define A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT 0x00000004 551 552 #define REG_A2XX_MH_INTERRUPT_STATUS 0x00000a43 553 554 #define REG_A2XX_MH_INTERRUPT_CLEAR 0x00000a44 555 556 #define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1 0x00000a54 557 558 #define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG2 0x00000a55 559 560 #define REG_A2XX_A220_VSC_BIN_SIZE 0x00000c01 561 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 562 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT 0 563 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val) 564 { 565 return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK; 566 } 567 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 568 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT 5 569 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val) 570 { 571 return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK; 572 } 573 574 static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 575 576 static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 577 578 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } 579 580 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } 581 582 #define REG_A2XX_PC_DEBUG_CNTL 0x00000c38 583 584 #define REG_A2XX_PC_DEBUG_DATA 0x00000c39 585 586 #define REG_A2XX_PA_SC_VIZ_QUERY_STATUS 0x00000c44 587 588 #define REG_A2XX_GRAS_DEBUG_CNTL 0x00000c80 589 590 #define REG_A2XX_PA_SU_DEBUG_CNTL 0x00000c80 591 592 #define REG_A2XX_GRAS_DEBUG_DATA 0x00000c81 593 594 #define REG_A2XX_PA_SU_DEBUG_DATA 0x00000c81 595 596 #define REG_A2XX_PA_SU_FACE_DATA 0x00000c86 597 #define A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK 0xffffffe0 598 #define A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT 5 599 static inline uint32_t A2XX_PA_SU_FACE_DATA_BASE_ADDR(uint32_t val) 600 { 601 return ((val) << A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT) & A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK; 602 } 603 604 #define REG_A2XX_SQ_GPR_MANAGEMENT 0x00000d00 605 #define A2XX_SQ_GPR_MANAGEMENT_REG_DYNAMIC 0x00000001 606 #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK 0x00000ff0 607 #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT 4 608 static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX(uint32_t val) 609 { 610 return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK; 611 } 612 #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK 0x000ff000 613 #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT 12 614 static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX(uint32_t val) 615 { 616 return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK; 617 } 618 619 #define REG_A2XX_SQ_FLOW_CONTROL 0x00000d01 620 621 #define REG_A2XX_SQ_INST_STORE_MANAGMENT 0x00000d02 622 #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK 0x00000fff 623 #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT 0 624 static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX(uint32_t val) 625 { 626 return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK; 627 } 628 #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK 0x0fff0000 629 #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT 16 630 static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX(uint32_t val) 631 { 632 return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK; 633 } 634 635 #define REG_A2XX_SQ_DEBUG_MISC 0x00000d05 636 637 #define REG_A2XX_SQ_INT_CNTL 0x00000d34 638 639 #define REG_A2XX_SQ_INT_STATUS 0x00000d35 640 641 #define REG_A2XX_SQ_INT_ACK 0x00000d36 642 643 #define REG_A2XX_SQ_DEBUG_INPUT_FSM 0x00000dae 644 645 #define REG_A2XX_SQ_DEBUG_CONST_MGR_FSM 0x00000daf 646 647 #define REG_A2XX_SQ_DEBUG_TP_FSM 0x00000db0 648 649 #define REG_A2XX_SQ_DEBUG_FSM_ALU_0 0x00000db1 650 651 #define REG_A2XX_SQ_DEBUG_FSM_ALU_1 0x00000db2 652 653 #define REG_A2XX_SQ_DEBUG_EXP_ALLOC 0x00000db3 654 655 #define REG_A2XX_SQ_DEBUG_PTR_BUFF 0x00000db4 656 657 #define REG_A2XX_SQ_DEBUG_GPR_VTX 0x00000db5 658 659 #define REG_A2XX_SQ_DEBUG_GPR_PIX 0x00000db6 660 661 #define REG_A2XX_SQ_DEBUG_TB_STATUS_SEL 0x00000db7 662 663 #define REG_A2XX_SQ_DEBUG_VTX_TB_0 0x00000db8 664 665 #define REG_A2XX_SQ_DEBUG_VTX_TB_1 0x00000db9 666 667 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG 0x00000dba 668 669 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM 0x00000dbb 670 671 #define REG_A2XX_SQ_DEBUG_PIX_TB_0 0x00000dbc 672 673 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0 0x00000dbd 674 675 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1 0x00000dbe 676 677 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2 0x00000dbf 678 679 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3 0x00000dc0 680 681 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM 0x00000dc1 682 683 #define REG_A2XX_TC_CNTL_STATUS 0x00000e00 684 #define A2XX_TC_CNTL_STATUS_L2_INVALIDATE 0x00000001 685 686 #define REG_A2XX_TP0_CHICKEN 0x00000e1e 687 688 #define REG_A2XX_RB_BC_CONTROL 0x00000f01 689 #define A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE 0x00000001 690 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK 0x00000006 691 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT 1 692 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val) 693 { 694 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK; 695 } 696 #define A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM 0x00000008 697 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010 698 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP 0x00000020 699 #define A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP 0x00000040 700 #define A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE 0x00000080 701 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK 0x00001f00 702 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT 8 703 static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val) 704 { 705 return ((val) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK; 706 } 707 #define A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE 0x00004000 708 #define A2XX_RB_BC_CONTROL_CRC_MODE 0x00008000 709 #define A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS 0x00010000 710 #define A2XX_RB_BC_CONTROL_DISABLE_ACCUM 0x00020000 711 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK 0x003c0000 712 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT 18 713 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val) 714 { 715 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK; 716 } 717 #define A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE 0x00400000 718 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK 0x07800000 719 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT 23 720 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val) 721 { 722 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK; 723 } 724 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK 0x18000000 725 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT 27 726 static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val) 727 { 728 return ((val) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK; 729 } 730 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000 731 #define A2XX_RB_BC_CONTROL_CRC_SYSTEM 0x40000000 732 #define A2XX_RB_BC_CONTROL_RESERVED6 0x80000000 733 734 #define REG_A2XX_RB_EDRAM_INFO 0x00000f02 735 736 #define REG_A2XX_RB_DEBUG_CNTL 0x00000f26 737 738 #define REG_A2XX_RB_DEBUG_DATA 0x00000f27 739 740 #define REG_A2XX_RB_SURFACE_INFO 0x00002000 741 #define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK 0x00003fff 742 #define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT 0 743 static inline uint32_t A2XX_RB_SURFACE_INFO_SURFACE_PITCH(uint32_t val) 744 { 745 return ((val) << A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT) & A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK; 746 } 747 #define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK 0x0000c000 748 #define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT 14 749 static inline uint32_t A2XX_RB_SURFACE_INFO_MSAA_SAMPLES(uint32_t val) 750 { 751 return ((val) << A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT) & A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK; 752 } 753 754 #define REG_A2XX_RB_COLOR_INFO 0x00002001 755 #define A2XX_RB_COLOR_INFO_FORMAT__MASK 0x0000000f 756 #define A2XX_RB_COLOR_INFO_FORMAT__SHIFT 0 757 static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val) 758 { 759 return ((val) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT) & A2XX_RB_COLOR_INFO_FORMAT__MASK; 760 } 761 #define A2XX_RB_COLOR_INFO_ROUND_MODE__MASK 0x00000030 762 #define A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT 4 763 static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val) 764 { 765 return ((val) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK; 766 } 767 #define A2XX_RB_COLOR_INFO_LINEAR 0x00000040 768 #define A2XX_RB_COLOR_INFO_ENDIAN__MASK 0x00000180 769 #define A2XX_RB_COLOR_INFO_ENDIAN__SHIFT 7 770 static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val) 771 { 772 return ((val) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT) & A2XX_RB_COLOR_INFO_ENDIAN__MASK; 773 } 774 #define A2XX_RB_COLOR_INFO_SWAP__MASK 0x00000600 775 #define A2XX_RB_COLOR_INFO_SWAP__SHIFT 9 776 static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val) 777 { 778 return ((val) << A2XX_RB_COLOR_INFO_SWAP__SHIFT) & A2XX_RB_COLOR_INFO_SWAP__MASK; 779 } 780 #define A2XX_RB_COLOR_INFO_BASE__MASK 0xfffff000 781 #define A2XX_RB_COLOR_INFO_BASE__SHIFT 12 782 static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val) 783 { 784 return ((val >> 12) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK; 785 } 786 787 #define REG_A2XX_RB_DEPTH_INFO 0x00002002 788 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001 789 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 790 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) 791 { 792 return ((val) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 793 } 794 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 795 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 796 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 797 { 798 return ((val >> 12) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 799 } 800 801 #define REG_A2XX_A225_RB_COLOR_INFO3 0x00002005 802 803 #define REG_A2XX_COHER_DEST_BASE_0 0x00002006 804 805 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_TL 0x0000200e 806 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 807 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 808 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 809 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 810 { 811 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK; 812 } 813 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 814 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 815 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 816 { 817 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK; 818 } 819 820 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_BR 0x0000200f 821 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 822 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 823 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 824 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 825 { 826 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK; 827 } 828 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 829 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 830 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 831 { 832 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK; 833 } 834 835 #define REG_A2XX_PA_SC_WINDOW_OFFSET 0x00002080 836 #define A2XX_PA_SC_WINDOW_OFFSET_X__MASK 0x00007fff 837 #define A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT 0 838 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val) 839 { 840 return ((val) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK; 841 } 842 #define A2XX_PA_SC_WINDOW_OFFSET_Y__MASK 0x7fff0000 843 #define A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT 16 844 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val) 845 { 846 return ((val) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK; 847 } 848 #define A2XX_PA_SC_WINDOW_OFFSET_DISABLE 0x80000000 849 850 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_TL 0x00002081 851 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 852 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 853 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 854 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 855 { 856 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK; 857 } 858 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 859 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 860 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 861 { 862 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK; 863 } 864 865 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_BR 0x00002082 866 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 867 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 868 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 869 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 870 { 871 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK; 872 } 873 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 874 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 875 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 876 { 877 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK; 878 } 879 880 #define REG_A2XX_UNKNOWN_2010 0x00002010 881 882 #define REG_A2XX_VGT_MAX_VTX_INDX 0x00002100 883 884 #define REG_A2XX_VGT_MIN_VTX_INDX 0x00002101 885 886 #define REG_A2XX_VGT_INDX_OFFSET 0x00002102 887 888 #define REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX 0x00002103 889 890 #define REG_A2XX_RB_COLOR_MASK 0x00002104 891 #define A2XX_RB_COLOR_MASK_WRITE_RED 0x00000001 892 #define A2XX_RB_COLOR_MASK_WRITE_GREEN 0x00000002 893 #define A2XX_RB_COLOR_MASK_WRITE_BLUE 0x00000004 894 #define A2XX_RB_COLOR_MASK_WRITE_ALPHA 0x00000008 895 896 #define REG_A2XX_RB_BLEND_RED 0x00002105 897 898 #define REG_A2XX_RB_BLEND_GREEN 0x00002106 899 900 #define REG_A2XX_RB_BLEND_BLUE 0x00002107 901 902 #define REG_A2XX_RB_BLEND_ALPHA 0x00002108 903 904 #define REG_A2XX_RB_FOG_COLOR 0x00002109 905 #define A2XX_RB_FOG_COLOR_FOG_RED__MASK 0x000000ff 906 #define A2XX_RB_FOG_COLOR_FOG_RED__SHIFT 0 907 static inline uint32_t A2XX_RB_FOG_COLOR_FOG_RED(uint32_t val) 908 { 909 return ((val) << A2XX_RB_FOG_COLOR_FOG_RED__SHIFT) & A2XX_RB_FOG_COLOR_FOG_RED__MASK; 910 } 911 #define A2XX_RB_FOG_COLOR_FOG_GREEN__MASK 0x0000ff00 912 #define A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT 8 913 static inline uint32_t A2XX_RB_FOG_COLOR_FOG_GREEN(uint32_t val) 914 { 915 return ((val) << A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT) & A2XX_RB_FOG_COLOR_FOG_GREEN__MASK; 916 } 917 #define A2XX_RB_FOG_COLOR_FOG_BLUE__MASK 0x00ff0000 918 #define A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT 16 919 static inline uint32_t A2XX_RB_FOG_COLOR_FOG_BLUE(uint32_t val) 920 { 921 return ((val) << A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT) & A2XX_RB_FOG_COLOR_FOG_BLUE__MASK; 922 } 923 924 #define REG_A2XX_RB_STENCILREFMASK_BF 0x0000210c 925 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 926 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 927 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 928 { 929 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 930 } 931 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 932 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 933 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 934 { 935 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 936 } 937 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 938 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 939 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 940 { 941 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 942 } 943 944 #define REG_A2XX_RB_STENCILREFMASK 0x0000210d 945 #define A2XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 946 #define A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 947 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 948 { 949 return ((val) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK; 950 } 951 #define A2XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 952 #define A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 953 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 954 { 955 return ((val) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK; 956 } 957 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 958 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 959 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 960 { 961 return ((val) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 962 } 963 964 #define REG_A2XX_RB_ALPHA_REF 0x0000210e 965 966 #define REG_A2XX_PA_CL_VPORT_XSCALE 0x0000210f 967 #define A2XX_PA_CL_VPORT_XSCALE__MASK 0xffffffff 968 #define A2XX_PA_CL_VPORT_XSCALE__SHIFT 0 969 static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val) 970 { 971 return ((fui(val)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT) & A2XX_PA_CL_VPORT_XSCALE__MASK; 972 } 973 974 #define REG_A2XX_PA_CL_VPORT_XOFFSET 0x00002110 975 #define A2XX_PA_CL_VPORT_XOFFSET__MASK 0xffffffff 976 #define A2XX_PA_CL_VPORT_XOFFSET__SHIFT 0 977 static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val) 978 { 979 return ((fui(val)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT) & A2XX_PA_CL_VPORT_XOFFSET__MASK; 980 } 981 982 #define REG_A2XX_PA_CL_VPORT_YSCALE 0x00002111 983 #define A2XX_PA_CL_VPORT_YSCALE__MASK 0xffffffff 984 #define A2XX_PA_CL_VPORT_YSCALE__SHIFT 0 985 static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val) 986 { 987 return ((fui(val)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT) & A2XX_PA_CL_VPORT_YSCALE__MASK; 988 } 989 990 #define REG_A2XX_PA_CL_VPORT_YOFFSET 0x00002112 991 #define A2XX_PA_CL_VPORT_YOFFSET__MASK 0xffffffff 992 #define A2XX_PA_CL_VPORT_YOFFSET__SHIFT 0 993 static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val) 994 { 995 return ((fui(val)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT) & A2XX_PA_CL_VPORT_YOFFSET__MASK; 996 } 997 998 #define REG_A2XX_PA_CL_VPORT_ZSCALE 0x00002113 999 #define A2XX_PA_CL_VPORT_ZSCALE__MASK 0xffffffff 1000 #define A2XX_PA_CL_VPORT_ZSCALE__SHIFT 0 1001 static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val) 1002 { 1003 return ((fui(val)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT) & A2XX_PA_CL_VPORT_ZSCALE__MASK; 1004 } 1005 1006 #define REG_A2XX_PA_CL_VPORT_ZOFFSET 0x00002114 1007 #define A2XX_PA_CL_VPORT_ZOFFSET__MASK 0xffffffff 1008 #define A2XX_PA_CL_VPORT_ZOFFSET__SHIFT 0 1009 static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val) 1010 { 1011 return ((fui(val)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT) & A2XX_PA_CL_VPORT_ZOFFSET__MASK; 1012 } 1013 1014 #define REG_A2XX_SQ_PROGRAM_CNTL 0x00002180 1015 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK 0x000000ff 1016 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT 0 1017 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val) 1018 { 1019 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK; 1020 } 1021 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK 0x0000ff00 1022 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT 8 1023 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val) 1024 { 1025 return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK; 1026 } 1027 #define A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE 0x00010000 1028 #define A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE 0x00020000 1029 #define A2XX_SQ_PROGRAM_CNTL_PARAM_GEN 0x00040000 1030 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX 0x00080000 1031 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK 0x00f00000 1032 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT 20 1033 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val) 1034 { 1035 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK; 1036 } 1037 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK 0x07000000 1038 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT 24 1039 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val) 1040 { 1041 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK; 1042 } 1043 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK 0x78000000 1044 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT 27 1045 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val) 1046 { 1047 return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK; 1048 } 1049 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX 0x80000000 1050 1051 #define REG_A2XX_SQ_CONTEXT_MISC 0x00002181 1052 #define A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE 0x00000001 1053 #define A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY 0x00000002 1054 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK 0x0000000c 1055 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT 2 1056 static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val) 1057 { 1058 return ((val) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK; 1059 } 1060 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK 0x0000ff00 1061 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT 8 1062 static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val) 1063 { 1064 return ((val) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK; 1065 } 1066 #define A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF 0x00010000 1067 #define A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE 0x00020000 1068 #define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL 0x00040000 1069 1070 #define REG_A2XX_SQ_INTERPOLATOR_CNTL 0x00002182 1071 #define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK 0x0000ffff 1072 #define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT 0 1073 static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE(uint32_t val) 1074 { 1075 return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK; 1076 } 1077 #define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK 0xffff0000 1078 #define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT 16 1079 static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN(uint32_t val) 1080 { 1081 return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK; 1082 } 1083 1084 #define REG_A2XX_SQ_WRAPPING_0 0x00002183 1085 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK 0x0000000f 1086 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT 0 1087 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_0(uint32_t val) 1088 { 1089 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK; 1090 } 1091 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK 0x000000f0 1092 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT 4 1093 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_1(uint32_t val) 1094 { 1095 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK; 1096 } 1097 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK 0x00000f00 1098 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT 8 1099 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_2(uint32_t val) 1100 { 1101 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK; 1102 } 1103 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK 0x0000f000 1104 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT 12 1105 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_3(uint32_t val) 1106 { 1107 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK; 1108 } 1109 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK 0x000f0000 1110 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT 16 1111 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_4(uint32_t val) 1112 { 1113 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK; 1114 } 1115 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK 0x00f00000 1116 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT 20 1117 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_5(uint32_t val) 1118 { 1119 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK; 1120 } 1121 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK 0x0f000000 1122 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT 24 1123 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_6(uint32_t val) 1124 { 1125 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK; 1126 } 1127 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK 0xf0000000 1128 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT 28 1129 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_7(uint32_t val) 1130 { 1131 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK; 1132 } 1133 1134 #define REG_A2XX_SQ_WRAPPING_1 0x00002184 1135 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK 0x0000000f 1136 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT 0 1137 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_8(uint32_t val) 1138 { 1139 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK; 1140 } 1141 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK 0x000000f0 1142 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT 4 1143 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_9(uint32_t val) 1144 { 1145 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK; 1146 } 1147 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK 0x00000f00 1148 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT 8 1149 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_10(uint32_t val) 1150 { 1151 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK; 1152 } 1153 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK 0x0000f000 1154 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT 12 1155 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_11(uint32_t val) 1156 { 1157 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK; 1158 } 1159 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK 0x000f0000 1160 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT 16 1161 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_12(uint32_t val) 1162 { 1163 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK; 1164 } 1165 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK 0x00f00000 1166 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT 20 1167 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_13(uint32_t val) 1168 { 1169 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK; 1170 } 1171 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK 0x0f000000 1172 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT 24 1173 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_14(uint32_t val) 1174 { 1175 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK; 1176 } 1177 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK 0xf0000000 1178 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT 28 1179 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_15(uint32_t val) 1180 { 1181 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK; 1182 } 1183 1184 #define REG_A2XX_SQ_PS_PROGRAM 0x000021f6 1185 #define A2XX_SQ_PS_PROGRAM_BASE__MASK 0x00000fff 1186 #define A2XX_SQ_PS_PROGRAM_BASE__SHIFT 0 1187 static inline uint32_t A2XX_SQ_PS_PROGRAM_BASE(uint32_t val) 1188 { 1189 return ((val) << A2XX_SQ_PS_PROGRAM_BASE__SHIFT) & A2XX_SQ_PS_PROGRAM_BASE__MASK; 1190 } 1191 #define A2XX_SQ_PS_PROGRAM_SIZE__MASK 0x00fff000 1192 #define A2XX_SQ_PS_PROGRAM_SIZE__SHIFT 12 1193 static inline uint32_t A2XX_SQ_PS_PROGRAM_SIZE(uint32_t val) 1194 { 1195 return ((val) << A2XX_SQ_PS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_PS_PROGRAM_SIZE__MASK; 1196 } 1197 1198 #define REG_A2XX_SQ_VS_PROGRAM 0x000021f7 1199 #define A2XX_SQ_VS_PROGRAM_BASE__MASK 0x00000fff 1200 #define A2XX_SQ_VS_PROGRAM_BASE__SHIFT 0 1201 static inline uint32_t A2XX_SQ_VS_PROGRAM_BASE(uint32_t val) 1202 { 1203 return ((val) << A2XX_SQ_VS_PROGRAM_BASE__SHIFT) & A2XX_SQ_VS_PROGRAM_BASE__MASK; 1204 } 1205 #define A2XX_SQ_VS_PROGRAM_SIZE__MASK 0x00fff000 1206 #define A2XX_SQ_VS_PROGRAM_SIZE__SHIFT 12 1207 static inline uint32_t A2XX_SQ_VS_PROGRAM_SIZE(uint32_t val) 1208 { 1209 return ((val) << A2XX_SQ_VS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_VS_PROGRAM_SIZE__MASK; 1210 } 1211 1212 #define REG_A2XX_VGT_EVENT_INITIATOR 0x000021f9 1213 1214 #define REG_A2XX_VGT_DRAW_INITIATOR 0x000021fc 1215 #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f 1216 #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 1217 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) 1218 { 1219 return ((val) << A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK; 1220 } 1221 #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 1222 #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 1223 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) 1224 { 1225 return ((val) << A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK; 1226 } 1227 #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600 1228 #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9 1229 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) 1230 { 1231 return ((val) << A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK; 1232 } 1233 #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800 1234 #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11 1235 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) 1236 { 1237 return ((val) << A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK; 1238 } 1239 #define A2XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000 1240 #define A2XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000 1241 #define A2XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000 1242 #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK 0xff000000 1243 #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT 24 1244 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) 1245 { 1246 return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK; 1247 } 1248 1249 #define REG_A2XX_VGT_IMMED_DATA 0x000021fd 1250 1251 #define REG_A2XX_RB_DEPTHCONTROL 0x00002200 1252 #define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE 0x00000001 1253 #define A2XX_RB_DEPTHCONTROL_Z_ENABLE 0x00000002 1254 #define A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE 0x00000004 1255 #define A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE 0x00000008 1256 #define A2XX_RB_DEPTHCONTROL_ZFUNC__MASK 0x00000070 1257 #define A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT 4 1258 static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val) 1259 { 1260 return ((val) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK; 1261 } 1262 #define A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE 0x00000080 1263 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK 0x00000700 1264 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT 8 1265 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val) 1266 { 1267 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK; 1268 } 1269 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK 0x00003800 1270 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT 11 1271 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val) 1272 { 1273 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK; 1274 } 1275 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK 0x0001c000 1276 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT 14 1277 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val) 1278 { 1279 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK; 1280 } 1281 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK 0x000e0000 1282 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT 17 1283 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val) 1284 { 1285 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK; 1286 } 1287 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK 0x00700000 1288 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT 20 1289 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val) 1290 { 1291 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK; 1292 } 1293 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK 0x03800000 1294 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT 23 1295 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val) 1296 { 1297 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK; 1298 } 1299 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK 0x1c000000 1300 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT 26 1301 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val) 1302 { 1303 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK; 1304 } 1305 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK 0xe0000000 1306 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT 29 1307 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val) 1308 { 1309 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK; 1310 } 1311 1312 #define REG_A2XX_RB_BLEND_CONTROL 0x00002201 1313 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK 0x0000001f 1314 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT 0 1315 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val) 1316 { 1317 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK; 1318 } 1319 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK 0x000000e0 1320 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT 5 1321 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val) 1322 { 1323 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK; 1324 } 1325 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK 0x00001f00 1326 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT 8 1327 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val) 1328 { 1329 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK; 1330 } 1331 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK 0x001f0000 1332 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT 16 1333 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val) 1334 { 1335 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK; 1336 } 1337 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK 0x00e00000 1338 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT 21 1339 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val) 1340 { 1341 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK; 1342 } 1343 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK 0x1f000000 1344 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT 24 1345 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val) 1346 { 1347 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK; 1348 } 1349 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE 0x20000000 1350 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE 0x40000000 1351 1352 #define REG_A2XX_RB_COLORCONTROL 0x00002202 1353 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK 0x00000007 1354 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT 0 1355 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val) 1356 { 1357 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK; 1358 } 1359 #define A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE 0x00000008 1360 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE 0x00000010 1361 #define A2XX_RB_COLORCONTROL_BLEND_DISABLE 0x00000020 1362 #define A2XX_RB_COLORCONTROL_VOB_ENABLE 0x00000040 1363 #define A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG 0x00000080 1364 #define A2XX_RB_COLORCONTROL_ROP_CODE__MASK 0x00000f00 1365 #define A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT 8 1366 static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val) 1367 { 1368 return ((val) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK; 1369 } 1370 #define A2XX_RB_COLORCONTROL_DITHER_MODE__MASK 0x00003000 1371 #define A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT 12 1372 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) 1373 { 1374 return ((val) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK; 1375 } 1376 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK 0x0000c000 1377 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT 14 1378 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val) 1379 { 1380 return ((val) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK; 1381 } 1382 #define A2XX_RB_COLORCONTROL_PIXEL_FOG 0x00010000 1383 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK 0x03000000 1384 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT 24 1385 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val) 1386 { 1387 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK; 1388 } 1389 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK 0x0c000000 1390 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT 26 1391 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val) 1392 { 1393 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK; 1394 } 1395 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK 0x30000000 1396 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT 28 1397 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val) 1398 { 1399 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK; 1400 } 1401 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK 0xc0000000 1402 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT 30 1403 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val) 1404 { 1405 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK; 1406 } 1407 1408 #define REG_A2XX_VGT_CURRENT_BIN_ID_MAX 0x00002203 1409 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK 0x00000007 1410 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT 0 1411 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val) 1412 { 1413 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK; 1414 } 1415 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK 0x00000038 1416 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT 3 1417 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val) 1418 { 1419 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK; 1420 } 1421 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK 0x000001c0 1422 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT 6 1423 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val) 1424 { 1425 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK; 1426 } 1427 1428 #define REG_A2XX_PA_CL_CLIP_CNTL 0x00002204 1429 #define A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 1430 #define A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA 0x00040000 1431 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK 0x00080000 1432 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT 19 1433 static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val) 1434 { 1435 return ((val) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK; 1436 } 1437 #define A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT 0x00100000 1438 #define A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR 0x00200000 1439 #define A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN 0x00400000 1440 #define A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN 0x00800000 1441 #define A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN 0x01000000 1442 1443 #define REG_A2XX_PA_SU_SC_MODE_CNTL 0x00002205 1444 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT 0x00000001 1445 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK 0x00000002 1446 #define A2XX_PA_SU_SC_MODE_CNTL_FACE 0x00000004 1447 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK 0x00000018 1448 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT 3 1449 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val) 1450 { 1451 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK; 1452 } 1453 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK 0x000000e0 1454 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT 5 1455 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 1456 { 1457 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK; 1458 } 1459 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK 0x00000700 1460 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT 8 1461 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 1462 { 1463 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK; 1464 } 1465 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE 0x00000800 1466 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE 0x00001000 1467 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE 0x00002000 1468 #define A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE 0x00008000 1469 #define A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE 0x00010000 1470 #define A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE 0x00040000 1471 #define A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST 0x00080000 1472 #define A2XX_PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS 0x00100000 1473 #define A2XX_PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA 0x00200000 1474 #define A2XX_PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE 0x00800000 1475 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI 0x02000000 1476 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000 1477 #define A2XX_PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS 0x10000000 1478 #define A2XX_PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS 0x20000000 1479 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE 0x40000000 1480 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE 0x80000000 1481 1482 #define REG_A2XX_PA_CL_VTE_CNTL 0x00002206 1483 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA 0x00000001 1484 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA 0x00000002 1485 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA 0x00000004 1486 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA 0x00000008 1487 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA 0x00000010 1488 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA 0x00000020 1489 #define A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT 0x00000100 1490 #define A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT 0x00000200 1491 #define A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT 0x00000400 1492 #define A2XX_PA_CL_VTE_CNTL_PERFCOUNTER_REF 0x00000800 1493 1494 #define REG_A2XX_VGT_CURRENT_BIN_ID_MIN 0x00002207 1495 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK 0x00000007 1496 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT 0 1497 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val) 1498 { 1499 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK; 1500 } 1501 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK 0x00000038 1502 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT 3 1503 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val) 1504 { 1505 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK; 1506 } 1507 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK 0x000001c0 1508 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT 6 1509 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val) 1510 { 1511 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK; 1512 } 1513 1514 #define REG_A2XX_RB_MODECONTROL 0x00002208 1515 #define A2XX_RB_MODECONTROL_EDRAM_MODE__MASK 0x00000007 1516 #define A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT 0 1517 static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val) 1518 { 1519 return ((val) << A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT) & A2XX_RB_MODECONTROL_EDRAM_MODE__MASK; 1520 } 1521 1522 #define REG_A2XX_A220_RB_LRZ_VSC_CONTROL 0x00002209 1523 1524 #define REG_A2XX_RB_SAMPLE_POS 0x0000220a 1525 1526 #define REG_A2XX_CLEAR_COLOR 0x0000220b 1527 #define A2XX_CLEAR_COLOR_RED__MASK 0x000000ff 1528 #define A2XX_CLEAR_COLOR_RED__SHIFT 0 1529 static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val) 1530 { 1531 return ((val) << A2XX_CLEAR_COLOR_RED__SHIFT) & A2XX_CLEAR_COLOR_RED__MASK; 1532 } 1533 #define A2XX_CLEAR_COLOR_GREEN__MASK 0x0000ff00 1534 #define A2XX_CLEAR_COLOR_GREEN__SHIFT 8 1535 static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val) 1536 { 1537 return ((val) << A2XX_CLEAR_COLOR_GREEN__SHIFT) & A2XX_CLEAR_COLOR_GREEN__MASK; 1538 } 1539 #define A2XX_CLEAR_COLOR_BLUE__MASK 0x00ff0000 1540 #define A2XX_CLEAR_COLOR_BLUE__SHIFT 16 1541 static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val) 1542 { 1543 return ((val) << A2XX_CLEAR_COLOR_BLUE__SHIFT) & A2XX_CLEAR_COLOR_BLUE__MASK; 1544 } 1545 #define A2XX_CLEAR_COLOR_ALPHA__MASK 0xff000000 1546 #define A2XX_CLEAR_COLOR_ALPHA__SHIFT 24 1547 static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val) 1548 { 1549 return ((val) << A2XX_CLEAR_COLOR_ALPHA__SHIFT) & A2XX_CLEAR_COLOR_ALPHA__MASK; 1550 } 1551 1552 #define REG_A2XX_A220_GRAS_CONTROL 0x00002210 1553 1554 #define REG_A2XX_PA_SU_POINT_SIZE 0x00002280 1555 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK 0x0000ffff 1556 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT 0 1557 static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val) 1558 { 1559 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK; 1560 } 1561 #define A2XX_PA_SU_POINT_SIZE_WIDTH__MASK 0xffff0000 1562 #define A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT 16 1563 static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val) 1564 { 1565 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK; 1566 } 1567 1568 #define REG_A2XX_PA_SU_POINT_MINMAX 0x00002281 1569 #define A2XX_PA_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 1570 #define A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT 0 1571 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val) 1572 { 1573 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK; 1574 } 1575 #define A2XX_PA_SU_POINT_MINMAX_MAX__MASK 0xffff0000 1576 #define A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT 16 1577 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val) 1578 { 1579 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK; 1580 } 1581 1582 #define REG_A2XX_PA_SU_LINE_CNTL 0x00002282 1583 #define A2XX_PA_SU_LINE_CNTL_WIDTH__MASK 0x0000ffff 1584 #define A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT 0 1585 static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val) 1586 { 1587 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK; 1588 } 1589 1590 #define REG_A2XX_PA_SC_LINE_STIPPLE 0x00002283 1591 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK 0x0000ffff 1592 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT 0 1593 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val) 1594 { 1595 return ((val) << A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK; 1596 } 1597 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK 0x00ff0000 1598 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT 16 1599 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val) 1600 { 1601 return ((val) << A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK; 1602 } 1603 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK 0x10000000 1604 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT 28 1605 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val) 1606 { 1607 return ((val) << A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK; 1608 } 1609 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK 0x60000000 1610 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT 29 1611 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val) 1612 { 1613 return ((val) << A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK; 1614 } 1615 1616 #define REG_A2XX_PA_SC_VIZ_QUERY 0x00002293 1617 #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ENA 0x00000001 1618 #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK 0x0000007e 1619 #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT 1 1620 static inline uint32_t A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID(uint32_t val) 1621 { 1622 return ((val) << A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT) & A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK; 1623 } 1624 #define A2XX_PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z 0x00000100 1625 1626 #define REG_A2XX_VGT_ENHANCE 0x00002294 1627 1628 #define REG_A2XX_PA_SC_LINE_CNTL 0x00002300 1629 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK 0x0000ffff 1630 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT 0 1631 static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val) 1632 { 1633 return ((val) << A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT) & A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK; 1634 } 1635 #define A2XX_PA_SC_LINE_CNTL_USE_BRES_CNTL 0x00000100 1636 #define A2XX_PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH 0x00000200 1637 #define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL 0x00000400 1638 1639 #define REG_A2XX_PA_SC_AA_CONFIG 0x00002301 1640 #define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK 0x00000007 1641 #define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT 0 1642 static inline uint32_t A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES(uint32_t val) 1643 { 1644 return ((val) << A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT) & A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK; 1645 } 1646 #define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK 0x0001e000 1647 #define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT 13 1648 static inline uint32_t A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST(uint32_t val) 1649 { 1650 return ((val) << A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT) & A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK; 1651 } 1652 1653 #define REG_A2XX_PA_SU_VTX_CNTL 0x00002302 1654 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK 0x00000001 1655 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT 0 1656 static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val) 1657 { 1658 return ((val) << A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT) & A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK; 1659 } 1660 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK 0x00000006 1661 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT 1 1662 static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val) 1663 { 1664 return ((val) << A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK; 1665 } 1666 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK 0x00000380 1667 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT 7 1668 static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val) 1669 { 1670 return ((val) << A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK; 1671 } 1672 1673 #define REG_A2XX_PA_CL_GB_VERT_CLIP_ADJ 0x00002303 1674 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK 0xffffffff 1675 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT 0 1676 static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val) 1677 { 1678 return ((fui(val)) << A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK; 1679 } 1680 1681 #define REG_A2XX_PA_CL_GB_VERT_DISC_ADJ 0x00002304 1682 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK 0xffffffff 1683 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT 0 1684 static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val) 1685 { 1686 return ((fui(val)) << A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK; 1687 } 1688 1689 #define REG_A2XX_PA_CL_GB_HORZ_CLIP_ADJ 0x00002305 1690 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK 0xffffffff 1691 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT 0 1692 static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val) 1693 { 1694 return ((fui(val)) << A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK; 1695 } 1696 1697 #define REG_A2XX_PA_CL_GB_HORZ_DISC_ADJ 0x00002306 1698 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK 0xffffffff 1699 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT 0 1700 static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val) 1701 { 1702 return ((fui(val)) << A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK; 1703 } 1704 1705 #define REG_A2XX_SQ_VS_CONST 0x00002307 1706 #define A2XX_SQ_VS_CONST_BASE__MASK 0x000001ff 1707 #define A2XX_SQ_VS_CONST_BASE__SHIFT 0 1708 static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val) 1709 { 1710 return ((val) << A2XX_SQ_VS_CONST_BASE__SHIFT) & A2XX_SQ_VS_CONST_BASE__MASK; 1711 } 1712 #define A2XX_SQ_VS_CONST_SIZE__MASK 0x001ff000 1713 #define A2XX_SQ_VS_CONST_SIZE__SHIFT 12 1714 static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val) 1715 { 1716 return ((val) << A2XX_SQ_VS_CONST_SIZE__SHIFT) & A2XX_SQ_VS_CONST_SIZE__MASK; 1717 } 1718 1719 #define REG_A2XX_SQ_PS_CONST 0x00002308 1720 #define A2XX_SQ_PS_CONST_BASE__MASK 0x000001ff 1721 #define A2XX_SQ_PS_CONST_BASE__SHIFT 0 1722 static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val) 1723 { 1724 return ((val) << A2XX_SQ_PS_CONST_BASE__SHIFT) & A2XX_SQ_PS_CONST_BASE__MASK; 1725 } 1726 #define A2XX_SQ_PS_CONST_SIZE__MASK 0x001ff000 1727 #define A2XX_SQ_PS_CONST_SIZE__SHIFT 12 1728 static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val) 1729 { 1730 return ((val) << A2XX_SQ_PS_CONST_SIZE__SHIFT) & A2XX_SQ_PS_CONST_SIZE__MASK; 1731 } 1732 1733 #define REG_A2XX_SQ_DEBUG_MISC_0 0x00002309 1734 1735 #define REG_A2XX_SQ_DEBUG_MISC_1 0x0000230a 1736 1737 #define REG_A2XX_PA_SC_AA_MASK 0x00002312 1738 1739 #define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL 0x00002316 1740 #define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK 0x00000007 1741 #define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT 0 1742 static inline uint32_t A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH(uint32_t val) 1743 { 1744 return ((val) << A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT) & A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK; 1745 } 1746 1747 #define REG_A2XX_VGT_OUT_DEALLOC_CNTL 0x00002317 1748 #define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK 0x00000003 1749 #define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT 0 1750 static inline uint32_t A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST(uint32_t val) 1751 { 1752 return ((val) << A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT) & A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK; 1753 } 1754 1755 #define REG_A2XX_RB_COPY_CONTROL 0x00002318 1756 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK 0x00000007 1757 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT 0 1758 static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val) 1759 { 1760 return ((val) << A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT) & A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK; 1761 } 1762 #define A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE 0x00000008 1763 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK 0x000000f0 1764 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT 4 1765 static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val) 1766 { 1767 return ((val) << A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT) & A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK; 1768 } 1769 1770 #define REG_A2XX_RB_COPY_DEST_BASE 0x00002319 1771 1772 #define REG_A2XX_RB_COPY_DEST_PITCH 0x0000231a 1773 #define A2XX_RB_COPY_DEST_PITCH__MASK 0xffffffff 1774 #define A2XX_RB_COPY_DEST_PITCH__SHIFT 0 1775 static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val) 1776 { 1777 return ((val >> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK; 1778 } 1779 1780 #define REG_A2XX_RB_COPY_DEST_INFO 0x0000231b 1781 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK 0x00000007 1782 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT 0 1783 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val) 1784 { 1785 return ((val) << A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT) & A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK; 1786 } 1787 #define A2XX_RB_COPY_DEST_INFO_LINEAR 0x00000008 1788 #define A2XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000f0 1789 #define A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 4 1790 static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val) 1791 { 1792 return ((val) << A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A2XX_RB_COPY_DEST_INFO_FORMAT__MASK; 1793 } 1794 #define A2XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 1795 #define A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 1796 static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val) 1797 { 1798 return ((val) << A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A2XX_RB_COPY_DEST_INFO_SWAP__MASK; 1799 } 1800 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 1801 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 1802 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 1803 { 1804 return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 1805 } 1806 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK 0x00003000 1807 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT 12 1808 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val) 1809 { 1810 return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK; 1811 } 1812 #define A2XX_RB_COPY_DEST_INFO_WRITE_RED 0x00004000 1813 #define A2XX_RB_COPY_DEST_INFO_WRITE_GREEN 0x00008000 1814 #define A2XX_RB_COPY_DEST_INFO_WRITE_BLUE 0x00010000 1815 #define A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA 0x00020000 1816 1817 #define REG_A2XX_RB_COPY_DEST_OFFSET 0x0000231c 1818 #define A2XX_RB_COPY_DEST_OFFSET_X__MASK 0x00001fff 1819 #define A2XX_RB_COPY_DEST_OFFSET_X__SHIFT 0 1820 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val) 1821 { 1822 return ((val) << A2XX_RB_COPY_DEST_OFFSET_X__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_X__MASK; 1823 } 1824 #define A2XX_RB_COPY_DEST_OFFSET_Y__MASK 0x03ffe000 1825 #define A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT 13 1826 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val) 1827 { 1828 return ((val) << A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_Y__MASK; 1829 } 1830 1831 #define REG_A2XX_RB_DEPTH_CLEAR 0x0000231d 1832 1833 #define REG_A2XX_RB_SAMPLE_COUNT_CTL 0x00002324 1834 1835 #define REG_A2XX_RB_COLOR_DEST_MASK 0x00002326 1836 1837 #define REG_A2XX_A225_GRAS_UCP0X 0x00002340 1838 1839 #define REG_A2XX_A225_GRAS_UCP5W 0x00002357 1840 1841 #define REG_A2XX_A225_GRAS_UCP_ENABLED 0x00002360 1842 1843 #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE 0x00002380 1844 1845 #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET 0x00002383 1846 1847 #define REG_A2XX_SQ_CONSTANT_0 0x00004000 1848 1849 #define REG_A2XX_SQ_FETCH_0 0x00004800 1850 1851 #define REG_A2XX_SQ_CF_BOOLEANS 0x00004900 1852 1853 #define REG_A2XX_SQ_CF_LOOP 0x00004908 1854 1855 #define REG_A2XX_COHER_SIZE_PM4 0x00000a29 1856 1857 #define REG_A2XX_COHER_BASE_PM4 0x00000a2a 1858 1859 #define REG_A2XX_COHER_STATUS_PM4 0x00000a2b 1860 1861 #define REG_A2XX_SQ_TEX_0 0x00000000 1862 #define A2XX_SQ_TEX_0_TYPE__MASK 0x00000003 1863 #define A2XX_SQ_TEX_0_TYPE__SHIFT 0 1864 static inline uint32_t A2XX_SQ_TEX_0_TYPE(enum sq_tex_type val) 1865 { 1866 return ((val) << A2XX_SQ_TEX_0_TYPE__SHIFT) & A2XX_SQ_TEX_0_TYPE__MASK; 1867 } 1868 #define A2XX_SQ_TEX_0_SIGN_X__MASK 0x0000000c 1869 #define A2XX_SQ_TEX_0_SIGN_X__SHIFT 2 1870 static inline uint32_t A2XX_SQ_TEX_0_SIGN_X(enum sq_tex_sign val) 1871 { 1872 return ((val) << A2XX_SQ_TEX_0_SIGN_X__SHIFT) & A2XX_SQ_TEX_0_SIGN_X__MASK; 1873 } 1874 #define A2XX_SQ_TEX_0_SIGN_Y__MASK 0x00000030 1875 #define A2XX_SQ_TEX_0_SIGN_Y__SHIFT 4 1876 static inline uint32_t A2XX_SQ_TEX_0_SIGN_Y(enum sq_tex_sign val) 1877 { 1878 return ((val) << A2XX_SQ_TEX_0_SIGN_Y__SHIFT) & A2XX_SQ_TEX_0_SIGN_Y__MASK; 1879 } 1880 #define A2XX_SQ_TEX_0_SIGN_Z__MASK 0x000000c0 1881 #define A2XX_SQ_TEX_0_SIGN_Z__SHIFT 6 1882 static inline uint32_t A2XX_SQ_TEX_0_SIGN_Z(enum sq_tex_sign val) 1883 { 1884 return ((val) << A2XX_SQ_TEX_0_SIGN_Z__SHIFT) & A2XX_SQ_TEX_0_SIGN_Z__MASK; 1885 } 1886 #define A2XX_SQ_TEX_0_SIGN_W__MASK 0x00000300 1887 #define A2XX_SQ_TEX_0_SIGN_W__SHIFT 8 1888 static inline uint32_t A2XX_SQ_TEX_0_SIGN_W(enum sq_tex_sign val) 1889 { 1890 return ((val) << A2XX_SQ_TEX_0_SIGN_W__SHIFT) & A2XX_SQ_TEX_0_SIGN_W__MASK; 1891 } 1892 #define A2XX_SQ_TEX_0_CLAMP_X__MASK 0x00001c00 1893 #define A2XX_SQ_TEX_0_CLAMP_X__SHIFT 10 1894 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val) 1895 { 1896 return ((val) << A2XX_SQ_TEX_0_CLAMP_X__SHIFT) & A2XX_SQ_TEX_0_CLAMP_X__MASK; 1897 } 1898 #define A2XX_SQ_TEX_0_CLAMP_Y__MASK 0x0000e000 1899 #define A2XX_SQ_TEX_0_CLAMP_Y__SHIFT 13 1900 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val) 1901 { 1902 return ((val) << A2XX_SQ_TEX_0_CLAMP_Y__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Y__MASK; 1903 } 1904 #define A2XX_SQ_TEX_0_CLAMP_Z__MASK 0x00070000 1905 #define A2XX_SQ_TEX_0_CLAMP_Z__SHIFT 16 1906 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val) 1907 { 1908 return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK; 1909 } 1910 #define A2XX_SQ_TEX_0_PITCH__MASK 0x7fc00000 1911 #define A2XX_SQ_TEX_0_PITCH__SHIFT 22 1912 static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val) 1913 { 1914 return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK; 1915 } 1916 #define A2XX_SQ_TEX_0_TILED 0x00000002 1917 1918 #define REG_A2XX_SQ_TEX_1 0x00000001 1919 #define A2XX_SQ_TEX_1_FORMAT__MASK 0x0000003f 1920 #define A2XX_SQ_TEX_1_FORMAT__SHIFT 0 1921 static inline uint32_t A2XX_SQ_TEX_1_FORMAT(enum a2xx_sq_surfaceformat val) 1922 { 1923 return ((val) << A2XX_SQ_TEX_1_FORMAT__SHIFT) & A2XX_SQ_TEX_1_FORMAT__MASK; 1924 } 1925 #define A2XX_SQ_TEX_1_ENDIANNESS__MASK 0x000000c0 1926 #define A2XX_SQ_TEX_1_ENDIANNESS__SHIFT 6 1927 static inline uint32_t A2XX_SQ_TEX_1_ENDIANNESS(enum sq_tex_endian val) 1928 { 1929 return ((val) << A2XX_SQ_TEX_1_ENDIANNESS__SHIFT) & A2XX_SQ_TEX_1_ENDIANNESS__MASK; 1930 } 1931 #define A2XX_SQ_TEX_1_REQUEST_SIZE__MASK 0x00000300 1932 #define A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT 8 1933 static inline uint32_t A2XX_SQ_TEX_1_REQUEST_SIZE(uint32_t val) 1934 { 1935 return ((val) << A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT) & A2XX_SQ_TEX_1_REQUEST_SIZE__MASK; 1936 } 1937 #define A2XX_SQ_TEX_1_STACKED 0x00000400 1938 #define A2XX_SQ_TEX_1_CLAMP_POLICY__MASK 0x00000800 1939 #define A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT 11 1940 static inline uint32_t A2XX_SQ_TEX_1_CLAMP_POLICY(enum sq_tex_clamp_policy val) 1941 { 1942 return ((val) << A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT) & A2XX_SQ_TEX_1_CLAMP_POLICY__MASK; 1943 } 1944 #define A2XX_SQ_TEX_1_BASE_ADDRESS__MASK 0xfffff000 1945 #define A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT 12 1946 static inline uint32_t A2XX_SQ_TEX_1_BASE_ADDRESS(uint32_t val) 1947 { 1948 return ((val >> 12) << A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT) & A2XX_SQ_TEX_1_BASE_ADDRESS__MASK; 1949 } 1950 1951 #define REG_A2XX_SQ_TEX_2 0x00000002 1952 #define A2XX_SQ_TEX_2_WIDTH__MASK 0x00001fff 1953 #define A2XX_SQ_TEX_2_WIDTH__SHIFT 0 1954 static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val) 1955 { 1956 return ((val) << A2XX_SQ_TEX_2_WIDTH__SHIFT) & A2XX_SQ_TEX_2_WIDTH__MASK; 1957 } 1958 #define A2XX_SQ_TEX_2_HEIGHT__MASK 0x03ffe000 1959 #define A2XX_SQ_TEX_2_HEIGHT__SHIFT 13 1960 static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val) 1961 { 1962 return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK; 1963 } 1964 #define A2XX_SQ_TEX_2_DEPTH__MASK 0xfc000000 1965 #define A2XX_SQ_TEX_2_DEPTH__SHIFT 26 1966 static inline uint32_t A2XX_SQ_TEX_2_DEPTH(uint32_t val) 1967 { 1968 return ((val) << A2XX_SQ_TEX_2_DEPTH__SHIFT) & A2XX_SQ_TEX_2_DEPTH__MASK; 1969 } 1970 1971 #define REG_A2XX_SQ_TEX_3 0x00000003 1972 #define A2XX_SQ_TEX_3_NUM_FORMAT__MASK 0x00000001 1973 #define A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT 0 1974 static inline uint32_t A2XX_SQ_TEX_3_NUM_FORMAT(enum sq_tex_num_format val) 1975 { 1976 return ((val) << A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT) & A2XX_SQ_TEX_3_NUM_FORMAT__MASK; 1977 } 1978 #define A2XX_SQ_TEX_3_SWIZ_X__MASK 0x0000000e 1979 #define A2XX_SQ_TEX_3_SWIZ_X__SHIFT 1 1980 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val) 1981 { 1982 return ((val) << A2XX_SQ_TEX_3_SWIZ_X__SHIFT) & A2XX_SQ_TEX_3_SWIZ_X__MASK; 1983 } 1984 #define A2XX_SQ_TEX_3_SWIZ_Y__MASK 0x00000070 1985 #define A2XX_SQ_TEX_3_SWIZ_Y__SHIFT 4 1986 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val) 1987 { 1988 return ((val) << A2XX_SQ_TEX_3_SWIZ_Y__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Y__MASK; 1989 } 1990 #define A2XX_SQ_TEX_3_SWIZ_Z__MASK 0x00000380 1991 #define A2XX_SQ_TEX_3_SWIZ_Z__SHIFT 7 1992 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val) 1993 { 1994 return ((val) << A2XX_SQ_TEX_3_SWIZ_Z__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Z__MASK; 1995 } 1996 #define A2XX_SQ_TEX_3_SWIZ_W__MASK 0x00001c00 1997 #define A2XX_SQ_TEX_3_SWIZ_W__SHIFT 10 1998 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val) 1999 { 2000 return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK; 2001 } 2002 #define A2XX_SQ_TEX_3_EXP_ADJUST__MASK 0x0007e000 2003 #define A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT 13 2004 static inline uint32_t A2XX_SQ_TEX_3_EXP_ADJUST(uint32_t val) 2005 { 2006 return ((val) << A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT) & A2XX_SQ_TEX_3_EXP_ADJUST__MASK; 2007 } 2008 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK 0x00180000 2009 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT 19 2010 static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val) 2011 { 2012 return ((val) << A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK; 2013 } 2014 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK 0x00600000 2015 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT 21 2016 static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val) 2017 { 2018 return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK; 2019 } 2020 #define A2XX_SQ_TEX_3_MIP_FILTER__MASK 0x01800000 2021 #define A2XX_SQ_TEX_3_MIP_FILTER__SHIFT 23 2022 static inline uint32_t A2XX_SQ_TEX_3_MIP_FILTER(enum sq_tex_filter val) 2023 { 2024 return ((val) << A2XX_SQ_TEX_3_MIP_FILTER__SHIFT) & A2XX_SQ_TEX_3_MIP_FILTER__MASK; 2025 } 2026 #define A2XX_SQ_TEX_3_ANISO_FILTER__MASK 0x0e000000 2027 #define A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT 25 2028 static inline uint32_t A2XX_SQ_TEX_3_ANISO_FILTER(enum sq_tex_aniso_filter val) 2029 { 2030 return ((val) << A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT) & A2XX_SQ_TEX_3_ANISO_FILTER__MASK; 2031 } 2032 #define A2XX_SQ_TEX_3_BORDER_SIZE__MASK 0x80000000 2033 #define A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT 31 2034 static inline uint32_t A2XX_SQ_TEX_3_BORDER_SIZE(uint32_t val) 2035 { 2036 return ((val) << A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT) & A2XX_SQ_TEX_3_BORDER_SIZE__MASK; 2037 } 2038 2039 #define REG_A2XX_SQ_TEX_4 0x00000004 2040 #define A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK 0x00000001 2041 #define A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT 0 2042 static inline uint32_t A2XX_SQ_TEX_4_VOL_MAG_FILTER(enum sq_tex_filter val) 2043 { 2044 return ((val) << A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK; 2045 } 2046 #define A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK 0x00000002 2047 #define A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT 1 2048 static inline uint32_t A2XX_SQ_TEX_4_VOL_MIN_FILTER(enum sq_tex_filter val) 2049 { 2050 return ((val) << A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK; 2051 } 2052 #define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK 0x0000003c 2053 #define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT 2 2054 static inline uint32_t A2XX_SQ_TEX_4_MIP_MIN_LEVEL(uint32_t val) 2055 { 2056 return ((val) << A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT) & A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK; 2057 } 2058 #define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK 0x000003c0 2059 #define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT 6 2060 static inline uint32_t A2XX_SQ_TEX_4_MIP_MAX_LEVEL(uint32_t val) 2061 { 2062 return ((val) << A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT) & A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK; 2063 } 2064 #define A2XX_SQ_TEX_4_MAX_ANISO_WALK 0x00000400 2065 #define A2XX_SQ_TEX_4_MIN_ANISO_WALK 0x00000800 2066 #define A2XX_SQ_TEX_4_LOD_BIAS__MASK 0x003ff000 2067 #define A2XX_SQ_TEX_4_LOD_BIAS__SHIFT 12 2068 static inline uint32_t A2XX_SQ_TEX_4_LOD_BIAS(float val) 2069 { 2070 return ((((int32_t)(val * 32.0))) << A2XX_SQ_TEX_4_LOD_BIAS__SHIFT) & A2XX_SQ_TEX_4_LOD_BIAS__MASK; 2071 } 2072 #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK 0x07c00000 2073 #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT 22 2074 static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H(uint32_t val) 2075 { 2076 return ((val) << A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT) & A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK; 2077 } 2078 #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK 0xf8000000 2079 #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT 27 2080 static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V(uint32_t val) 2081 { 2082 return ((val) << A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT) & A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK; 2083 } 2084 2085 #define REG_A2XX_SQ_TEX_5 0x00000005 2086 #define A2XX_SQ_TEX_5_BORDER_COLOR__MASK 0x00000003 2087 #define A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT 0 2088 static inline uint32_t A2XX_SQ_TEX_5_BORDER_COLOR(enum sq_tex_border_color val) 2089 { 2090 return ((val) << A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT) & A2XX_SQ_TEX_5_BORDER_COLOR__MASK; 2091 } 2092 #define A2XX_SQ_TEX_5_FORCE_BCW_MAX 0x00000004 2093 #define A2XX_SQ_TEX_5_TRI_CLAMP__MASK 0x00000018 2094 #define A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT 3 2095 static inline uint32_t A2XX_SQ_TEX_5_TRI_CLAMP(uint32_t val) 2096 { 2097 return ((val) << A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT) & A2XX_SQ_TEX_5_TRI_CLAMP__MASK; 2098 } 2099 #define A2XX_SQ_TEX_5_ANISO_BIAS__MASK 0x000001e0 2100 #define A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT 5 2101 static inline uint32_t A2XX_SQ_TEX_5_ANISO_BIAS(float val) 2102 { 2103 return ((((int32_t)(val * 1.0))) << A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT) & A2XX_SQ_TEX_5_ANISO_BIAS__MASK; 2104 } 2105 #define A2XX_SQ_TEX_5_DIMENSION__MASK 0x00000600 2106 #define A2XX_SQ_TEX_5_DIMENSION__SHIFT 9 2107 static inline uint32_t A2XX_SQ_TEX_5_DIMENSION(enum sq_tex_dimension val) 2108 { 2109 return ((val) << A2XX_SQ_TEX_5_DIMENSION__SHIFT) & A2XX_SQ_TEX_5_DIMENSION__MASK; 2110 } 2111 #define A2XX_SQ_TEX_5_PACKED_MIPS 0x00000800 2112 #define A2XX_SQ_TEX_5_MIP_ADDRESS__MASK 0xfffff000 2113 #define A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT 12 2114 static inline uint32_t A2XX_SQ_TEX_5_MIP_ADDRESS(uint32_t val) 2115 { 2116 return ((val >> 12) << A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT) & A2XX_SQ_TEX_5_MIP_ADDRESS__MASK; 2117 } 2118 2119 2120 #endif /* A2XX_XML */ 2121