1 #ifndef A2XX_XML 2 #define A2XX_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44) 12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) 13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08) 14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08) 15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08) 16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08) 17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48) 18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05) 19 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) 20 21 Copyright (C) 2013-2016 by the following authors: 22 - Rob Clark <robdclark@gmail.com> (robclark) 23 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 24 25 Permission is hereby granted, free of charge, to any person obtaining 26 a copy of this software and associated documentation files (the 27 "Software"), to deal in the Software without restriction, including 28 without limitation the rights to use, copy, modify, merge, publish, 29 distribute, sublicense, and/or sell copies of the Software, and to 30 permit persons to whom the Software is furnished to do so, subject to 31 the following conditions: 32 33 The above copyright notice and this permission notice (including the 34 next paragraph) shall be included in all copies or substantial 35 portions of the Software. 36 37 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 38 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 39 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 40 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 41 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 42 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 43 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 44 */ 45 46 47 enum a2xx_rb_dither_type { 48 DITHER_PIXEL = 0, 49 DITHER_SUBPIXEL = 1, 50 }; 51 52 enum a2xx_colorformatx { 53 COLORX_4_4_4_4 = 0, 54 COLORX_1_5_5_5 = 1, 55 COLORX_5_6_5 = 2, 56 COLORX_8 = 3, 57 COLORX_8_8 = 4, 58 COLORX_8_8_8_8 = 5, 59 COLORX_S8_8_8_8 = 6, 60 COLORX_16_FLOAT = 7, 61 COLORX_16_16_FLOAT = 8, 62 COLORX_16_16_16_16_FLOAT = 9, 63 COLORX_32_FLOAT = 10, 64 COLORX_32_32_FLOAT = 11, 65 COLORX_32_32_32_32_FLOAT = 12, 66 COLORX_2_3_3 = 13, 67 COLORX_8_8_8 = 14, 68 }; 69 70 enum a2xx_sq_surfaceformat { 71 FMT_1_REVERSE = 0, 72 FMT_1 = 1, 73 FMT_8 = 2, 74 FMT_1_5_5_5 = 3, 75 FMT_5_6_5 = 4, 76 FMT_6_5_5 = 5, 77 FMT_8_8_8_8 = 6, 78 FMT_2_10_10_10 = 7, 79 FMT_8_A = 8, 80 FMT_8_B = 9, 81 FMT_8_8 = 10, 82 FMT_Cr_Y1_Cb_Y0 = 11, 83 FMT_Y1_Cr_Y0_Cb = 12, 84 FMT_5_5_5_1 = 13, 85 FMT_8_8_8_8_A = 14, 86 FMT_4_4_4_4 = 15, 87 FMT_10_11_11 = 16, 88 FMT_11_11_10 = 17, 89 FMT_DXT1 = 18, 90 FMT_DXT2_3 = 19, 91 FMT_DXT4_5 = 20, 92 FMT_24_8 = 22, 93 FMT_24_8_FLOAT = 23, 94 FMT_16 = 24, 95 FMT_16_16 = 25, 96 FMT_16_16_16_16 = 26, 97 FMT_16_EXPAND = 27, 98 FMT_16_16_EXPAND = 28, 99 FMT_16_16_16_16_EXPAND = 29, 100 FMT_16_FLOAT = 30, 101 FMT_16_16_FLOAT = 31, 102 FMT_16_16_16_16_FLOAT = 32, 103 FMT_32 = 33, 104 FMT_32_32 = 34, 105 FMT_32_32_32_32 = 35, 106 FMT_32_FLOAT = 36, 107 FMT_32_32_FLOAT = 37, 108 FMT_32_32_32_32_FLOAT = 38, 109 FMT_32_AS_8 = 39, 110 FMT_32_AS_8_8 = 40, 111 FMT_16_MPEG = 41, 112 FMT_16_16_MPEG = 42, 113 FMT_8_INTERLACED = 43, 114 FMT_32_AS_8_INTERLACED = 44, 115 FMT_32_AS_8_8_INTERLACED = 45, 116 FMT_16_INTERLACED = 46, 117 FMT_16_MPEG_INTERLACED = 47, 118 FMT_16_16_MPEG_INTERLACED = 48, 119 FMT_DXN = 49, 120 FMT_8_8_8_8_AS_16_16_16_16 = 50, 121 FMT_DXT1_AS_16_16_16_16 = 51, 122 FMT_DXT2_3_AS_16_16_16_16 = 52, 123 FMT_DXT4_5_AS_16_16_16_16 = 53, 124 FMT_2_10_10_10_AS_16_16_16_16 = 54, 125 FMT_10_11_11_AS_16_16_16_16 = 55, 126 FMT_11_11_10_AS_16_16_16_16 = 56, 127 FMT_32_32_32_FLOAT = 57, 128 FMT_DXT3A = 58, 129 FMT_DXT5A = 59, 130 FMT_CTX1 = 60, 131 FMT_DXT3A_AS_1_1_1_1 = 61, 132 }; 133 134 enum a2xx_sq_ps_vtx_mode { 135 POSITION_1_VECTOR = 0, 136 POSITION_2_VECTORS_UNUSED = 1, 137 POSITION_2_VECTORS_SPRITE = 2, 138 POSITION_2_VECTORS_EDGE = 3, 139 POSITION_2_VECTORS_KILL = 4, 140 POSITION_2_VECTORS_SPRITE_KILL = 5, 141 POSITION_2_VECTORS_EDGE_KILL = 6, 142 MULTIPASS = 7, 143 }; 144 145 enum a2xx_sq_sample_cntl { 146 CENTROIDS_ONLY = 0, 147 CENTERS_ONLY = 1, 148 CENTROIDS_AND_CENTERS = 2, 149 }; 150 151 enum a2xx_dx_clip_space { 152 DXCLIP_OPENGL = 0, 153 DXCLIP_DIRECTX = 1, 154 }; 155 156 enum a2xx_pa_su_sc_polymode { 157 POLY_DISABLED = 0, 158 POLY_DUALMODE = 1, 159 }; 160 161 enum a2xx_rb_edram_mode { 162 EDRAM_NOP = 0, 163 COLOR_DEPTH = 4, 164 DEPTH_ONLY = 5, 165 EDRAM_COPY = 6, 166 }; 167 168 enum a2xx_pa_sc_pattern_bit_order { 169 LITTLE = 0, 170 BIG = 1, 171 }; 172 173 enum a2xx_pa_sc_auto_reset_cntl { 174 NEVER = 0, 175 EACH_PRIMITIVE = 1, 176 EACH_PACKET = 2, 177 }; 178 179 enum a2xx_pa_pixcenter { 180 PIXCENTER_D3D = 0, 181 PIXCENTER_OGL = 1, 182 }; 183 184 enum a2xx_pa_roundmode { 185 TRUNCATE = 0, 186 ROUND = 1, 187 ROUNDTOEVEN = 2, 188 ROUNDTOODD = 3, 189 }; 190 191 enum a2xx_pa_quantmode { 192 ONE_SIXTEENTH = 0, 193 ONE_EIGTH = 1, 194 ONE_QUARTER = 2, 195 ONE_HALF = 3, 196 ONE = 4, 197 }; 198 199 enum a2xx_rb_copy_sample_select { 200 SAMPLE_0 = 0, 201 SAMPLE_1 = 1, 202 SAMPLE_2 = 2, 203 SAMPLE_3 = 3, 204 SAMPLE_01 = 4, 205 SAMPLE_23 = 5, 206 SAMPLE_0123 = 6, 207 }; 208 209 enum a2xx_rb_blend_opcode { 210 BLEND2_DST_PLUS_SRC = 0, 211 BLEND2_SRC_MINUS_DST = 1, 212 BLEND2_MIN_DST_SRC = 2, 213 BLEND2_MAX_DST_SRC = 3, 214 BLEND2_DST_MINUS_SRC = 4, 215 BLEND2_DST_PLUS_SRC_BIAS = 5, 216 }; 217 218 enum adreno_mmu_clnt_beh { 219 BEH_NEVR = 0, 220 BEH_TRAN_RNG = 1, 221 BEH_TRAN_FLT = 2, 222 }; 223 224 enum sq_tex_clamp { 225 SQ_TEX_WRAP = 0, 226 SQ_TEX_MIRROR = 1, 227 SQ_TEX_CLAMP_LAST_TEXEL = 2, 228 SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3, 229 SQ_TEX_CLAMP_HALF_BORDER = 4, 230 SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5, 231 SQ_TEX_CLAMP_BORDER = 6, 232 SQ_TEX_MIRROR_ONCE_BORDER = 7, 233 }; 234 235 enum sq_tex_swiz { 236 SQ_TEX_X = 0, 237 SQ_TEX_Y = 1, 238 SQ_TEX_Z = 2, 239 SQ_TEX_W = 3, 240 SQ_TEX_ZERO = 4, 241 SQ_TEX_ONE = 5, 242 }; 243 244 enum sq_tex_filter { 245 SQ_TEX_FILTER_POINT = 0, 246 SQ_TEX_FILTER_BILINEAR = 1, 247 SQ_TEX_FILTER_BICUBIC = 2, 248 }; 249 250 #define REG_A2XX_RBBM_PATCH_RELEASE 0x00000001 251 252 #define REG_A2XX_RBBM_CNTL 0x0000003b 253 254 #define REG_A2XX_RBBM_SOFT_RESET 0x0000003c 255 256 #define REG_A2XX_CP_PFP_UCODE_ADDR 0x000000c0 257 258 #define REG_A2XX_CP_PFP_UCODE_DATA 0x000000c1 259 260 #define REG_A2XX_MH_MMU_CONFIG 0x00000040 261 #define A2XX_MH_MMU_CONFIG_MMU_ENABLE 0x00000001 262 #define A2XX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE 0x00000002 263 #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK 0x00000030 264 #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT 4 265 static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 266 { 267 return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK; 268 } 269 #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK 0x000000c0 270 #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT 6 271 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 272 { 273 return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK; 274 } 275 #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK 0x00000300 276 #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT 8 277 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 278 { 279 return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK; 280 } 281 #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK 0x00000c00 282 #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT 10 283 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 284 { 285 return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK; 286 } 287 #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK 0x00003000 288 #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT 12 289 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 290 { 291 return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK; 292 } 293 #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK 0x0000c000 294 #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT 14 295 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 296 { 297 return ((val) << A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK; 298 } 299 #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK 0x00030000 300 #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT 16 301 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 302 { 303 return ((val) << A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK; 304 } 305 #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK 0x000c0000 306 #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT 18 307 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 308 { 309 return ((val) << A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK; 310 } 311 #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK 0x00300000 312 #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT 20 313 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 314 { 315 return ((val) << A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK; 316 } 317 #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK 0x00c00000 318 #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT 22 319 static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 320 { 321 return ((val) << A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK; 322 } 323 #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK 0x03000000 324 #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT 24 325 static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 326 { 327 return ((val) << A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK; 328 } 329 330 #define REG_A2XX_MH_MMU_VA_RANGE 0x00000041 331 332 #define REG_A2XX_MH_MMU_PT_BASE 0x00000042 333 334 #define REG_A2XX_MH_MMU_PAGE_FAULT 0x00000043 335 336 #define REG_A2XX_MH_MMU_TRAN_ERROR 0x00000044 337 338 #define REG_A2XX_MH_MMU_INVALIDATE 0x00000045 339 340 #define REG_A2XX_MH_MMU_MPU_BASE 0x00000046 341 342 #define REG_A2XX_MH_MMU_MPU_END 0x00000047 343 344 #define REG_A2XX_NQWAIT_UNTIL 0x00000394 345 346 #define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395 347 348 #define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397 349 350 #define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x00000398 351 352 #define REG_A2XX_RBBM_DEBUG 0x0000039b 353 354 #define REG_A2XX_RBBM_PM_OVERRIDE1 0x0000039c 355 356 #define REG_A2XX_RBBM_PM_OVERRIDE2 0x0000039d 357 358 #define REG_A2XX_RBBM_DEBUG_OUT 0x000003a0 359 360 #define REG_A2XX_RBBM_DEBUG_CNTL 0x000003a1 361 362 #define REG_A2XX_RBBM_READ_ERROR 0x000003b3 363 364 #define REG_A2XX_RBBM_INT_CNTL 0x000003b4 365 366 #define REG_A2XX_RBBM_INT_STATUS 0x000003b5 367 368 #define REG_A2XX_RBBM_INT_ACK 0x000003b6 369 370 #define REG_A2XX_MASTER_INT_SIGNAL 0x000003b7 371 372 #define REG_A2XX_RBBM_PERIPHID1 0x000003f9 373 374 #define REG_A2XX_RBBM_PERIPHID2 0x000003fa 375 376 #define REG_A2XX_CP_PERFMON_CNTL 0x00000444 377 378 #define REG_A2XX_CP_PERFCOUNTER_SELECT 0x00000445 379 380 #define REG_A2XX_CP_PERFCOUNTER_LO 0x00000446 381 382 #define REG_A2XX_CP_PERFCOUNTER_HI 0x00000447 383 384 #define REG_A2XX_RBBM_STATUS 0x000005d0 385 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK 0x0000001f 386 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT 0 387 static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val) 388 { 389 return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK; 390 } 391 #define A2XX_RBBM_STATUS_TC_BUSY 0x00000020 392 #define A2XX_RBBM_STATUS_HIRQ_PENDING 0x00000100 393 #define A2XX_RBBM_STATUS_CPRQ_PENDING 0x00000200 394 #define A2XX_RBBM_STATUS_CFRQ_PENDING 0x00000400 395 #define A2XX_RBBM_STATUS_PFRQ_PENDING 0x00000800 396 #define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA 0x00001000 397 #define A2XX_RBBM_STATUS_RBBM_WU_BUSY 0x00004000 398 #define A2XX_RBBM_STATUS_CP_NRT_BUSY 0x00010000 399 #define A2XX_RBBM_STATUS_MH_BUSY 0x00040000 400 #define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY 0x00080000 401 #define A2XX_RBBM_STATUS_SX_BUSY 0x00200000 402 #define A2XX_RBBM_STATUS_TPC_BUSY 0x00400000 403 #define A2XX_RBBM_STATUS_SC_CNTX_BUSY 0x01000000 404 #define A2XX_RBBM_STATUS_PA_BUSY 0x02000000 405 #define A2XX_RBBM_STATUS_VGT_BUSY 0x04000000 406 #define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY 0x08000000 407 #define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY 0x10000000 408 #define A2XX_RBBM_STATUS_RB_CNTX_BUSY 0x40000000 409 #define A2XX_RBBM_STATUS_GUI_ACTIVE 0x80000000 410 411 #define REG_A2XX_MH_ARBITER_CONFIG 0x00000a40 412 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK 0x0000003f 413 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT 0 414 static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val) 415 { 416 return ((val) << A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK; 417 } 418 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY 0x00000040 419 #define A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE 0x00000080 420 #define A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE 0x00000100 421 #define A2XX_MH_ARBITER_CONFIG_L2_ARB_CONTROL 0x00000200 422 #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK 0x00001c00 423 #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT 10 424 static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val) 425 { 426 return ((val) << A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT) & A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK; 427 } 428 #define A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00002000 429 #define A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE 0x00004000 430 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE 0x00008000 431 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK 0x003f0000 432 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT 16 433 static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val) 434 { 435 return ((val) << A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK; 436 } 437 #define A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE 0x00400000 438 #define A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE 0x00800000 439 #define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE 0x01000000 440 #define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE 0x02000000 441 #define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE 0x04000000 442 443 #define REG_A2XX_A220_VSC_BIN_SIZE 0x00000c01 444 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 445 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT 0 446 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val) 447 { 448 return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK; 449 } 450 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 451 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT 5 452 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val) 453 { 454 return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK; 455 } 456 457 static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 458 459 static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 460 461 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } 462 463 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } 464 465 #define REG_A2XX_PC_DEBUG_CNTL 0x00000c38 466 467 #define REG_A2XX_PC_DEBUG_DATA 0x00000c39 468 469 #define REG_A2XX_PA_SC_VIZ_QUERY_STATUS 0x00000c44 470 471 #define REG_A2XX_GRAS_DEBUG_CNTL 0x00000c80 472 473 #define REG_A2XX_PA_SU_DEBUG_CNTL 0x00000c80 474 475 #define REG_A2XX_GRAS_DEBUG_DATA 0x00000c81 476 477 #define REG_A2XX_PA_SU_DEBUG_DATA 0x00000c81 478 479 #define REG_A2XX_PA_SU_FACE_DATA 0x00000c86 480 481 #define REG_A2XX_SQ_GPR_MANAGEMENT 0x00000d00 482 483 #define REG_A2XX_SQ_FLOW_CONTROL 0x00000d01 484 485 #define REG_A2XX_SQ_INST_STORE_MANAGMENT 0x00000d02 486 487 #define REG_A2XX_SQ_DEBUG_MISC 0x00000d05 488 489 #define REG_A2XX_SQ_INT_CNTL 0x00000d34 490 491 #define REG_A2XX_SQ_INT_STATUS 0x00000d35 492 493 #define REG_A2XX_SQ_INT_ACK 0x00000d36 494 495 #define REG_A2XX_SQ_DEBUG_INPUT_FSM 0x00000dae 496 497 #define REG_A2XX_SQ_DEBUG_CONST_MGR_FSM 0x00000daf 498 499 #define REG_A2XX_SQ_DEBUG_TP_FSM 0x00000db0 500 501 #define REG_A2XX_SQ_DEBUG_FSM_ALU_0 0x00000db1 502 503 #define REG_A2XX_SQ_DEBUG_FSM_ALU_1 0x00000db2 504 505 #define REG_A2XX_SQ_DEBUG_EXP_ALLOC 0x00000db3 506 507 #define REG_A2XX_SQ_DEBUG_PTR_BUFF 0x00000db4 508 509 #define REG_A2XX_SQ_DEBUG_GPR_VTX 0x00000db5 510 511 #define REG_A2XX_SQ_DEBUG_GPR_PIX 0x00000db6 512 513 #define REG_A2XX_SQ_DEBUG_TB_STATUS_SEL 0x00000db7 514 515 #define REG_A2XX_SQ_DEBUG_VTX_TB_0 0x00000db8 516 517 #define REG_A2XX_SQ_DEBUG_VTX_TB_1 0x00000db9 518 519 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG 0x00000dba 520 521 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM 0x00000dbb 522 523 #define REG_A2XX_SQ_DEBUG_PIX_TB_0 0x00000dbc 524 525 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0 0x00000dbd 526 527 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1 0x00000dbe 528 529 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2 0x00000dbf 530 531 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3 0x00000dc0 532 533 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM 0x00000dc1 534 535 #define REG_A2XX_TC_CNTL_STATUS 0x00000e00 536 #define A2XX_TC_CNTL_STATUS_L2_INVALIDATE 0x00000001 537 538 #define REG_A2XX_TP0_CHICKEN 0x00000e1e 539 540 #define REG_A2XX_RB_BC_CONTROL 0x00000f01 541 #define A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE 0x00000001 542 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK 0x00000006 543 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT 1 544 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val) 545 { 546 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK; 547 } 548 #define A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM 0x00000008 549 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010 550 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP 0x00000020 551 #define A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP 0x00000040 552 #define A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE 0x00000080 553 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK 0x00001f00 554 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT 8 555 static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val) 556 { 557 return ((val) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK; 558 } 559 #define A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE 0x00004000 560 #define A2XX_RB_BC_CONTROL_CRC_MODE 0x00008000 561 #define A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS 0x00010000 562 #define A2XX_RB_BC_CONTROL_DISABLE_ACCUM 0x00020000 563 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK 0x003c0000 564 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT 18 565 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val) 566 { 567 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK; 568 } 569 #define A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE 0x00400000 570 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK 0x07800000 571 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT 23 572 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val) 573 { 574 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK; 575 } 576 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK 0x18000000 577 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT 27 578 static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val) 579 { 580 return ((val) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK; 581 } 582 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000 583 #define A2XX_RB_BC_CONTROL_CRC_SYSTEM 0x40000000 584 #define A2XX_RB_BC_CONTROL_RESERVED6 0x80000000 585 586 #define REG_A2XX_RB_EDRAM_INFO 0x00000f02 587 588 #define REG_A2XX_RB_DEBUG_CNTL 0x00000f26 589 590 #define REG_A2XX_RB_DEBUG_DATA 0x00000f27 591 592 #define REG_A2XX_RB_SURFACE_INFO 0x00002000 593 594 #define REG_A2XX_RB_COLOR_INFO 0x00002001 595 #define A2XX_RB_COLOR_INFO_FORMAT__MASK 0x0000000f 596 #define A2XX_RB_COLOR_INFO_FORMAT__SHIFT 0 597 static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val) 598 { 599 return ((val) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT) & A2XX_RB_COLOR_INFO_FORMAT__MASK; 600 } 601 #define A2XX_RB_COLOR_INFO_ROUND_MODE__MASK 0x00000030 602 #define A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT 4 603 static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val) 604 { 605 return ((val) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK; 606 } 607 #define A2XX_RB_COLOR_INFO_LINEAR 0x00000040 608 #define A2XX_RB_COLOR_INFO_ENDIAN__MASK 0x00000180 609 #define A2XX_RB_COLOR_INFO_ENDIAN__SHIFT 7 610 static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val) 611 { 612 return ((val) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT) & A2XX_RB_COLOR_INFO_ENDIAN__MASK; 613 } 614 #define A2XX_RB_COLOR_INFO_SWAP__MASK 0x00000600 615 #define A2XX_RB_COLOR_INFO_SWAP__SHIFT 9 616 static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val) 617 { 618 return ((val) << A2XX_RB_COLOR_INFO_SWAP__SHIFT) & A2XX_RB_COLOR_INFO_SWAP__MASK; 619 } 620 #define A2XX_RB_COLOR_INFO_BASE__MASK 0xfffff000 621 #define A2XX_RB_COLOR_INFO_BASE__SHIFT 12 622 static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val) 623 { 624 return ((val >> 10) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK; 625 } 626 627 #define REG_A2XX_RB_DEPTH_INFO 0x00002002 628 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001 629 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 630 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) 631 { 632 return ((val) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 633 } 634 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 635 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 636 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 637 { 638 return ((val >> 10) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 639 } 640 641 #define REG_A2XX_A225_RB_COLOR_INFO3 0x00002005 642 643 #define REG_A2XX_COHER_DEST_BASE_0 0x00002006 644 645 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_TL 0x0000200e 646 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 647 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 648 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 649 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 650 { 651 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK; 652 } 653 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 654 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 655 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 656 { 657 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK; 658 } 659 660 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_BR 0x0000200f 661 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 662 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 663 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 664 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 665 { 666 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK; 667 } 668 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 669 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 670 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 671 { 672 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK; 673 } 674 675 #define REG_A2XX_PA_SC_WINDOW_OFFSET 0x00002080 676 #define A2XX_PA_SC_WINDOW_OFFSET_X__MASK 0x00007fff 677 #define A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT 0 678 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val) 679 { 680 return ((val) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK; 681 } 682 #define A2XX_PA_SC_WINDOW_OFFSET_Y__MASK 0x7fff0000 683 #define A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT 16 684 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val) 685 { 686 return ((val) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK; 687 } 688 #define A2XX_PA_SC_WINDOW_OFFSET_DISABLE 0x80000000 689 690 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_TL 0x00002081 691 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 692 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 693 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 694 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 695 { 696 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK; 697 } 698 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 699 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 700 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 701 { 702 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK; 703 } 704 705 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_BR 0x00002082 706 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 707 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 708 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 709 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 710 { 711 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK; 712 } 713 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 714 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 715 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 716 { 717 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK; 718 } 719 720 #define REG_A2XX_UNKNOWN_2010 0x00002010 721 722 #define REG_A2XX_VGT_MAX_VTX_INDX 0x00002100 723 724 #define REG_A2XX_VGT_MIN_VTX_INDX 0x00002101 725 726 #define REG_A2XX_VGT_INDX_OFFSET 0x00002102 727 728 #define REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX 0x00002103 729 730 #define REG_A2XX_RB_COLOR_MASK 0x00002104 731 #define A2XX_RB_COLOR_MASK_WRITE_RED 0x00000001 732 #define A2XX_RB_COLOR_MASK_WRITE_GREEN 0x00000002 733 #define A2XX_RB_COLOR_MASK_WRITE_BLUE 0x00000004 734 #define A2XX_RB_COLOR_MASK_WRITE_ALPHA 0x00000008 735 736 #define REG_A2XX_RB_BLEND_RED 0x00002105 737 738 #define REG_A2XX_RB_BLEND_GREEN 0x00002106 739 740 #define REG_A2XX_RB_BLEND_BLUE 0x00002107 741 742 #define REG_A2XX_RB_BLEND_ALPHA 0x00002108 743 744 #define REG_A2XX_RB_FOG_COLOR 0x00002109 745 746 #define REG_A2XX_RB_STENCILREFMASK_BF 0x0000210c 747 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 748 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 749 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 750 { 751 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 752 } 753 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 754 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 755 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 756 { 757 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 758 } 759 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 760 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 761 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 762 { 763 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 764 } 765 766 #define REG_A2XX_RB_STENCILREFMASK 0x0000210d 767 #define A2XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 768 #define A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 769 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 770 { 771 return ((val) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK; 772 } 773 #define A2XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 774 #define A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 775 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 776 { 777 return ((val) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK; 778 } 779 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 780 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 781 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 782 { 783 return ((val) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 784 } 785 786 #define REG_A2XX_RB_ALPHA_REF 0x0000210e 787 788 #define REG_A2XX_PA_CL_VPORT_XSCALE 0x0000210f 789 #define A2XX_PA_CL_VPORT_XSCALE__MASK 0xffffffff 790 #define A2XX_PA_CL_VPORT_XSCALE__SHIFT 0 791 static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val) 792 { 793 return ((fui(val)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT) & A2XX_PA_CL_VPORT_XSCALE__MASK; 794 } 795 796 #define REG_A2XX_PA_CL_VPORT_XOFFSET 0x00002110 797 #define A2XX_PA_CL_VPORT_XOFFSET__MASK 0xffffffff 798 #define A2XX_PA_CL_VPORT_XOFFSET__SHIFT 0 799 static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val) 800 { 801 return ((fui(val)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT) & A2XX_PA_CL_VPORT_XOFFSET__MASK; 802 } 803 804 #define REG_A2XX_PA_CL_VPORT_YSCALE 0x00002111 805 #define A2XX_PA_CL_VPORT_YSCALE__MASK 0xffffffff 806 #define A2XX_PA_CL_VPORT_YSCALE__SHIFT 0 807 static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val) 808 { 809 return ((fui(val)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT) & A2XX_PA_CL_VPORT_YSCALE__MASK; 810 } 811 812 #define REG_A2XX_PA_CL_VPORT_YOFFSET 0x00002112 813 #define A2XX_PA_CL_VPORT_YOFFSET__MASK 0xffffffff 814 #define A2XX_PA_CL_VPORT_YOFFSET__SHIFT 0 815 static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val) 816 { 817 return ((fui(val)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT) & A2XX_PA_CL_VPORT_YOFFSET__MASK; 818 } 819 820 #define REG_A2XX_PA_CL_VPORT_ZSCALE 0x00002113 821 #define A2XX_PA_CL_VPORT_ZSCALE__MASK 0xffffffff 822 #define A2XX_PA_CL_VPORT_ZSCALE__SHIFT 0 823 static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val) 824 { 825 return ((fui(val)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT) & A2XX_PA_CL_VPORT_ZSCALE__MASK; 826 } 827 828 #define REG_A2XX_PA_CL_VPORT_ZOFFSET 0x00002114 829 #define A2XX_PA_CL_VPORT_ZOFFSET__MASK 0xffffffff 830 #define A2XX_PA_CL_VPORT_ZOFFSET__SHIFT 0 831 static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val) 832 { 833 return ((fui(val)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT) & A2XX_PA_CL_VPORT_ZOFFSET__MASK; 834 } 835 836 #define REG_A2XX_SQ_PROGRAM_CNTL 0x00002180 837 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK 0x000000ff 838 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT 0 839 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val) 840 { 841 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK; 842 } 843 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK 0x0000ff00 844 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT 8 845 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val) 846 { 847 return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK; 848 } 849 #define A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE 0x00010000 850 #define A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE 0x00020000 851 #define A2XX_SQ_PROGRAM_CNTL_PARAM_GEN 0x00040000 852 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX 0x00080000 853 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK 0x00f00000 854 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT 20 855 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val) 856 { 857 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK; 858 } 859 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK 0x07000000 860 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT 24 861 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val) 862 { 863 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK; 864 } 865 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK 0x78000000 866 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT 27 867 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val) 868 { 869 return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK; 870 } 871 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX 0x80000000 872 873 #define REG_A2XX_SQ_CONTEXT_MISC 0x00002181 874 #define A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE 0x00000001 875 #define A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY 0x00000002 876 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK 0x0000000c 877 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT 2 878 static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val) 879 { 880 return ((val) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK; 881 } 882 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK 0x0000ff00 883 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT 8 884 static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val) 885 { 886 return ((val) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK; 887 } 888 #define A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF 0x00010000 889 #define A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE 0x00020000 890 #define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL 0x00040000 891 892 #define REG_A2XX_SQ_INTERPOLATOR_CNTL 0x00002182 893 894 #define REG_A2XX_SQ_WRAPPING_0 0x00002183 895 896 #define REG_A2XX_SQ_WRAPPING_1 0x00002184 897 898 #define REG_A2XX_SQ_PS_PROGRAM 0x000021f6 899 900 #define REG_A2XX_SQ_VS_PROGRAM 0x000021f7 901 902 #define REG_A2XX_VGT_EVENT_INITIATOR 0x000021f9 903 904 #define REG_A2XX_VGT_DRAW_INITIATOR 0x000021fc 905 #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f 906 #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 907 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) 908 { 909 return ((val) << A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK; 910 } 911 #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 912 #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 913 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) 914 { 915 return ((val) << A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK; 916 } 917 #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600 918 #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9 919 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) 920 { 921 return ((val) << A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK; 922 } 923 #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800 924 #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11 925 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) 926 { 927 return ((val) << A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK; 928 } 929 #define A2XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000 930 #define A2XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000 931 #define A2XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000 932 #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK 0xff000000 933 #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT 24 934 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) 935 { 936 return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK; 937 } 938 939 #define REG_A2XX_VGT_IMMED_DATA 0x000021fd 940 941 #define REG_A2XX_RB_DEPTHCONTROL 0x00002200 942 #define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE 0x00000001 943 #define A2XX_RB_DEPTHCONTROL_Z_ENABLE 0x00000002 944 #define A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE 0x00000004 945 #define A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE 0x00000008 946 #define A2XX_RB_DEPTHCONTROL_ZFUNC__MASK 0x00000070 947 #define A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT 4 948 static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val) 949 { 950 return ((val) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK; 951 } 952 #define A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE 0x00000080 953 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK 0x00000700 954 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT 8 955 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val) 956 { 957 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK; 958 } 959 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK 0x00003800 960 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT 11 961 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val) 962 { 963 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK; 964 } 965 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK 0x0001c000 966 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT 14 967 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val) 968 { 969 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK; 970 } 971 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK 0x000e0000 972 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT 17 973 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val) 974 { 975 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK; 976 } 977 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK 0x00700000 978 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT 20 979 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val) 980 { 981 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK; 982 } 983 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK 0x03800000 984 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT 23 985 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val) 986 { 987 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK; 988 } 989 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK 0x1c000000 990 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT 26 991 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val) 992 { 993 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK; 994 } 995 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK 0xe0000000 996 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT 29 997 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val) 998 { 999 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK; 1000 } 1001 1002 #define REG_A2XX_RB_BLEND_CONTROL 0x00002201 1003 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK 0x0000001f 1004 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT 0 1005 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val) 1006 { 1007 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK; 1008 } 1009 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK 0x000000e0 1010 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT 5 1011 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val) 1012 { 1013 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK; 1014 } 1015 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK 0x00001f00 1016 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT 8 1017 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val) 1018 { 1019 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK; 1020 } 1021 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK 0x001f0000 1022 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT 16 1023 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val) 1024 { 1025 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK; 1026 } 1027 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK 0x00e00000 1028 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT 21 1029 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val) 1030 { 1031 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK; 1032 } 1033 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK 0x1f000000 1034 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT 24 1035 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val) 1036 { 1037 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK; 1038 } 1039 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE 0x20000000 1040 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE 0x40000000 1041 1042 #define REG_A2XX_RB_COLORCONTROL 0x00002202 1043 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK 0x00000007 1044 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT 0 1045 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val) 1046 { 1047 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK; 1048 } 1049 #define A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE 0x00000008 1050 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE 0x00000010 1051 #define A2XX_RB_COLORCONTROL_BLEND_DISABLE 0x00000020 1052 #define A2XX_RB_COLORCONTROL_VOB_ENABLE 0x00000040 1053 #define A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG 0x00000080 1054 #define A2XX_RB_COLORCONTROL_ROP_CODE__MASK 0x00000f00 1055 #define A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT 8 1056 static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val) 1057 { 1058 return ((val) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK; 1059 } 1060 #define A2XX_RB_COLORCONTROL_DITHER_MODE__MASK 0x00003000 1061 #define A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT 12 1062 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) 1063 { 1064 return ((val) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK; 1065 } 1066 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK 0x0000c000 1067 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT 14 1068 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val) 1069 { 1070 return ((val) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK; 1071 } 1072 #define A2XX_RB_COLORCONTROL_PIXEL_FOG 0x00010000 1073 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK 0x03000000 1074 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT 24 1075 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val) 1076 { 1077 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK; 1078 } 1079 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK 0x0c000000 1080 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT 26 1081 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val) 1082 { 1083 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK; 1084 } 1085 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK 0x30000000 1086 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT 28 1087 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val) 1088 { 1089 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK; 1090 } 1091 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK 0xc0000000 1092 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT 30 1093 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val) 1094 { 1095 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK; 1096 } 1097 1098 #define REG_A2XX_VGT_CURRENT_BIN_ID_MAX 0x00002203 1099 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK 0x00000007 1100 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT 0 1101 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val) 1102 { 1103 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK; 1104 } 1105 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK 0x00000038 1106 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT 3 1107 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val) 1108 { 1109 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK; 1110 } 1111 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK 0x000001c0 1112 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT 6 1113 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val) 1114 { 1115 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK; 1116 } 1117 1118 #define REG_A2XX_PA_CL_CLIP_CNTL 0x00002204 1119 #define A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 1120 #define A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA 0x00040000 1121 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK 0x00080000 1122 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT 19 1123 static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val) 1124 { 1125 return ((val) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK; 1126 } 1127 #define A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT 0x00100000 1128 #define A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR 0x00200000 1129 #define A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN 0x00400000 1130 #define A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN 0x00800000 1131 #define A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN 0x01000000 1132 1133 #define REG_A2XX_PA_SU_SC_MODE_CNTL 0x00002205 1134 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT 0x00000001 1135 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK 0x00000002 1136 #define A2XX_PA_SU_SC_MODE_CNTL_FACE 0x00000004 1137 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK 0x00000018 1138 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT 3 1139 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val) 1140 { 1141 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK; 1142 } 1143 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK 0x000000e0 1144 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT 5 1145 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 1146 { 1147 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK; 1148 } 1149 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK 0x00000700 1150 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT 8 1151 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 1152 { 1153 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK; 1154 } 1155 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE 0x00000800 1156 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE 0x00001000 1157 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE 0x00002000 1158 #define A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE 0x00008000 1159 #define A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE 0x00010000 1160 #define A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE 0x00040000 1161 #define A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST 0x00080000 1162 #define A2XX_PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS 0x00100000 1163 #define A2XX_PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA 0x00200000 1164 #define A2XX_PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE 0x00800000 1165 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI 0x02000000 1166 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000 1167 #define A2XX_PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS 0x10000000 1168 #define A2XX_PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS 0x20000000 1169 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE 0x40000000 1170 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE 0x80000000 1171 1172 #define REG_A2XX_PA_CL_VTE_CNTL 0x00002206 1173 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA 0x00000001 1174 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA 0x00000002 1175 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA 0x00000004 1176 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA 0x00000008 1177 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA 0x00000010 1178 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA 0x00000020 1179 #define A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT 0x00000100 1180 #define A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT 0x00000200 1181 #define A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT 0x00000400 1182 #define A2XX_PA_CL_VTE_CNTL_PERFCOUNTER_REF 0x00000800 1183 1184 #define REG_A2XX_VGT_CURRENT_BIN_ID_MIN 0x00002207 1185 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK 0x00000007 1186 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT 0 1187 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val) 1188 { 1189 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK; 1190 } 1191 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK 0x00000038 1192 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT 3 1193 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val) 1194 { 1195 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK; 1196 } 1197 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK 0x000001c0 1198 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT 6 1199 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val) 1200 { 1201 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK; 1202 } 1203 1204 #define REG_A2XX_RB_MODECONTROL 0x00002208 1205 #define A2XX_RB_MODECONTROL_EDRAM_MODE__MASK 0x00000007 1206 #define A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT 0 1207 static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val) 1208 { 1209 return ((val) << A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT) & A2XX_RB_MODECONTROL_EDRAM_MODE__MASK; 1210 } 1211 1212 #define REG_A2XX_A220_RB_LRZ_VSC_CONTROL 0x00002209 1213 1214 #define REG_A2XX_RB_SAMPLE_POS 0x0000220a 1215 1216 #define REG_A2XX_CLEAR_COLOR 0x0000220b 1217 #define A2XX_CLEAR_COLOR_RED__MASK 0x000000ff 1218 #define A2XX_CLEAR_COLOR_RED__SHIFT 0 1219 static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val) 1220 { 1221 return ((val) << A2XX_CLEAR_COLOR_RED__SHIFT) & A2XX_CLEAR_COLOR_RED__MASK; 1222 } 1223 #define A2XX_CLEAR_COLOR_GREEN__MASK 0x0000ff00 1224 #define A2XX_CLEAR_COLOR_GREEN__SHIFT 8 1225 static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val) 1226 { 1227 return ((val) << A2XX_CLEAR_COLOR_GREEN__SHIFT) & A2XX_CLEAR_COLOR_GREEN__MASK; 1228 } 1229 #define A2XX_CLEAR_COLOR_BLUE__MASK 0x00ff0000 1230 #define A2XX_CLEAR_COLOR_BLUE__SHIFT 16 1231 static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val) 1232 { 1233 return ((val) << A2XX_CLEAR_COLOR_BLUE__SHIFT) & A2XX_CLEAR_COLOR_BLUE__MASK; 1234 } 1235 #define A2XX_CLEAR_COLOR_ALPHA__MASK 0xff000000 1236 #define A2XX_CLEAR_COLOR_ALPHA__SHIFT 24 1237 static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val) 1238 { 1239 return ((val) << A2XX_CLEAR_COLOR_ALPHA__SHIFT) & A2XX_CLEAR_COLOR_ALPHA__MASK; 1240 } 1241 1242 #define REG_A2XX_A220_GRAS_CONTROL 0x00002210 1243 1244 #define REG_A2XX_PA_SU_POINT_SIZE 0x00002280 1245 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK 0x0000ffff 1246 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT 0 1247 static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val) 1248 { 1249 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK; 1250 } 1251 #define A2XX_PA_SU_POINT_SIZE_WIDTH__MASK 0xffff0000 1252 #define A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT 16 1253 static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val) 1254 { 1255 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK; 1256 } 1257 1258 #define REG_A2XX_PA_SU_POINT_MINMAX 0x00002281 1259 #define A2XX_PA_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 1260 #define A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT 0 1261 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val) 1262 { 1263 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK; 1264 } 1265 #define A2XX_PA_SU_POINT_MINMAX_MAX__MASK 0xffff0000 1266 #define A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT 16 1267 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val) 1268 { 1269 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK; 1270 } 1271 1272 #define REG_A2XX_PA_SU_LINE_CNTL 0x00002282 1273 #define A2XX_PA_SU_LINE_CNTL_WIDTH__MASK 0x0000ffff 1274 #define A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT 0 1275 static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val) 1276 { 1277 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK; 1278 } 1279 1280 #define REG_A2XX_PA_SC_LINE_STIPPLE 0x00002283 1281 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK 0x0000ffff 1282 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT 0 1283 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val) 1284 { 1285 return ((val) << A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK; 1286 } 1287 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK 0x00ff0000 1288 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT 16 1289 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val) 1290 { 1291 return ((val) << A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK; 1292 } 1293 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK 0x10000000 1294 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT 28 1295 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val) 1296 { 1297 return ((val) << A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK; 1298 } 1299 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK 0x60000000 1300 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT 29 1301 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val) 1302 { 1303 return ((val) << A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK; 1304 } 1305 1306 #define REG_A2XX_PA_SC_VIZ_QUERY 0x00002293 1307 1308 #define REG_A2XX_VGT_ENHANCE 0x00002294 1309 1310 #define REG_A2XX_PA_SC_LINE_CNTL 0x00002300 1311 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK 0x0000ffff 1312 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT 0 1313 static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val) 1314 { 1315 return ((val) << A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT) & A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK; 1316 } 1317 #define A2XX_PA_SC_LINE_CNTL_USE_BRES_CNTL 0x00000100 1318 #define A2XX_PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH 0x00000200 1319 #define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL 0x00000400 1320 1321 #define REG_A2XX_PA_SC_AA_CONFIG 0x00002301 1322 1323 #define REG_A2XX_PA_SU_VTX_CNTL 0x00002302 1324 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK 0x00000001 1325 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT 0 1326 static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val) 1327 { 1328 return ((val) << A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT) & A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK; 1329 } 1330 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK 0x00000006 1331 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT 1 1332 static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val) 1333 { 1334 return ((val) << A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK; 1335 } 1336 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK 0x00000380 1337 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT 7 1338 static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val) 1339 { 1340 return ((val) << A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK; 1341 } 1342 1343 #define REG_A2XX_PA_CL_GB_VERT_CLIP_ADJ 0x00002303 1344 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK 0xffffffff 1345 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT 0 1346 static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val) 1347 { 1348 return ((fui(val)) << A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK; 1349 } 1350 1351 #define REG_A2XX_PA_CL_GB_VERT_DISC_ADJ 0x00002304 1352 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK 0xffffffff 1353 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT 0 1354 static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val) 1355 { 1356 return ((fui(val)) << A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK; 1357 } 1358 1359 #define REG_A2XX_PA_CL_GB_HORZ_CLIP_ADJ 0x00002305 1360 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK 0xffffffff 1361 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT 0 1362 static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val) 1363 { 1364 return ((fui(val)) << A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK; 1365 } 1366 1367 #define REG_A2XX_PA_CL_GB_HORZ_DISC_ADJ 0x00002306 1368 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK 0xffffffff 1369 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT 0 1370 static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val) 1371 { 1372 return ((fui(val)) << A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK; 1373 } 1374 1375 #define REG_A2XX_SQ_VS_CONST 0x00002307 1376 #define A2XX_SQ_VS_CONST_BASE__MASK 0x000001ff 1377 #define A2XX_SQ_VS_CONST_BASE__SHIFT 0 1378 static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val) 1379 { 1380 return ((val) << A2XX_SQ_VS_CONST_BASE__SHIFT) & A2XX_SQ_VS_CONST_BASE__MASK; 1381 } 1382 #define A2XX_SQ_VS_CONST_SIZE__MASK 0x001ff000 1383 #define A2XX_SQ_VS_CONST_SIZE__SHIFT 12 1384 static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val) 1385 { 1386 return ((val) << A2XX_SQ_VS_CONST_SIZE__SHIFT) & A2XX_SQ_VS_CONST_SIZE__MASK; 1387 } 1388 1389 #define REG_A2XX_SQ_PS_CONST 0x00002308 1390 #define A2XX_SQ_PS_CONST_BASE__MASK 0x000001ff 1391 #define A2XX_SQ_PS_CONST_BASE__SHIFT 0 1392 static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val) 1393 { 1394 return ((val) << A2XX_SQ_PS_CONST_BASE__SHIFT) & A2XX_SQ_PS_CONST_BASE__MASK; 1395 } 1396 #define A2XX_SQ_PS_CONST_SIZE__MASK 0x001ff000 1397 #define A2XX_SQ_PS_CONST_SIZE__SHIFT 12 1398 static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val) 1399 { 1400 return ((val) << A2XX_SQ_PS_CONST_SIZE__SHIFT) & A2XX_SQ_PS_CONST_SIZE__MASK; 1401 } 1402 1403 #define REG_A2XX_SQ_DEBUG_MISC_0 0x00002309 1404 1405 #define REG_A2XX_SQ_DEBUG_MISC_1 0x0000230a 1406 1407 #define REG_A2XX_PA_SC_AA_MASK 0x00002312 1408 1409 #define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL 0x00002316 1410 1411 #define REG_A2XX_VGT_OUT_DEALLOC_CNTL 0x00002317 1412 1413 #define REG_A2XX_RB_COPY_CONTROL 0x00002318 1414 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK 0x00000007 1415 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT 0 1416 static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val) 1417 { 1418 return ((val) << A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT) & A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK; 1419 } 1420 #define A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE 0x00000008 1421 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK 0x000000f0 1422 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT 4 1423 static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val) 1424 { 1425 return ((val) << A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT) & A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK; 1426 } 1427 1428 #define REG_A2XX_RB_COPY_DEST_BASE 0x00002319 1429 1430 #define REG_A2XX_RB_COPY_DEST_PITCH 0x0000231a 1431 #define A2XX_RB_COPY_DEST_PITCH__MASK 0xffffffff 1432 #define A2XX_RB_COPY_DEST_PITCH__SHIFT 0 1433 static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val) 1434 { 1435 return ((val >> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK; 1436 } 1437 1438 #define REG_A2XX_RB_COPY_DEST_INFO 0x0000231b 1439 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK 0x00000007 1440 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT 0 1441 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val) 1442 { 1443 return ((val) << A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT) & A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK; 1444 } 1445 #define A2XX_RB_COPY_DEST_INFO_LINEAR 0x00000008 1446 #define A2XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000f0 1447 #define A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 4 1448 static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val) 1449 { 1450 return ((val) << A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A2XX_RB_COPY_DEST_INFO_FORMAT__MASK; 1451 } 1452 #define A2XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 1453 #define A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 1454 static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val) 1455 { 1456 return ((val) << A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A2XX_RB_COPY_DEST_INFO_SWAP__MASK; 1457 } 1458 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 1459 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 1460 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 1461 { 1462 return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 1463 } 1464 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK 0x00003000 1465 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT 12 1466 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val) 1467 { 1468 return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK; 1469 } 1470 #define A2XX_RB_COPY_DEST_INFO_WRITE_RED 0x00004000 1471 #define A2XX_RB_COPY_DEST_INFO_WRITE_GREEN 0x00008000 1472 #define A2XX_RB_COPY_DEST_INFO_WRITE_BLUE 0x00010000 1473 #define A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA 0x00020000 1474 1475 #define REG_A2XX_RB_COPY_DEST_OFFSET 0x0000231c 1476 #define A2XX_RB_COPY_DEST_OFFSET_X__MASK 0x00001fff 1477 #define A2XX_RB_COPY_DEST_OFFSET_X__SHIFT 0 1478 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val) 1479 { 1480 return ((val) << A2XX_RB_COPY_DEST_OFFSET_X__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_X__MASK; 1481 } 1482 #define A2XX_RB_COPY_DEST_OFFSET_Y__MASK 0x03ffe000 1483 #define A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT 13 1484 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val) 1485 { 1486 return ((val) << A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_Y__MASK; 1487 } 1488 1489 #define REG_A2XX_RB_DEPTH_CLEAR 0x0000231d 1490 1491 #define REG_A2XX_RB_SAMPLE_COUNT_CTL 0x00002324 1492 1493 #define REG_A2XX_RB_COLOR_DEST_MASK 0x00002326 1494 1495 #define REG_A2XX_A225_GRAS_UCP0X 0x00002340 1496 1497 #define REG_A2XX_A225_GRAS_UCP5W 0x00002357 1498 1499 #define REG_A2XX_A225_GRAS_UCP_ENABLED 0x00002360 1500 1501 #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE 0x00002380 1502 1503 #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET 0x00002383 1504 1505 #define REG_A2XX_SQ_CONSTANT_0 0x00004000 1506 1507 #define REG_A2XX_SQ_FETCH_0 0x00004800 1508 1509 #define REG_A2XX_SQ_CF_BOOLEANS 0x00004900 1510 1511 #define REG_A2XX_SQ_CF_LOOP 0x00004908 1512 1513 #define REG_A2XX_COHER_SIZE_PM4 0x00000a29 1514 1515 #define REG_A2XX_COHER_BASE_PM4 0x00000a2a 1516 1517 #define REG_A2XX_COHER_STATUS_PM4 0x00000a2b 1518 1519 #define REG_A2XX_SQ_TEX_0 0x00000000 1520 #define A2XX_SQ_TEX_0_CLAMP_X__MASK 0x00001c00 1521 #define A2XX_SQ_TEX_0_CLAMP_X__SHIFT 10 1522 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val) 1523 { 1524 return ((val) << A2XX_SQ_TEX_0_CLAMP_X__SHIFT) & A2XX_SQ_TEX_0_CLAMP_X__MASK; 1525 } 1526 #define A2XX_SQ_TEX_0_CLAMP_Y__MASK 0x0000e000 1527 #define A2XX_SQ_TEX_0_CLAMP_Y__SHIFT 13 1528 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val) 1529 { 1530 return ((val) << A2XX_SQ_TEX_0_CLAMP_Y__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Y__MASK; 1531 } 1532 #define A2XX_SQ_TEX_0_CLAMP_Z__MASK 0x00070000 1533 #define A2XX_SQ_TEX_0_CLAMP_Z__SHIFT 16 1534 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val) 1535 { 1536 return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK; 1537 } 1538 #define A2XX_SQ_TEX_0_PITCH__MASK 0xffc00000 1539 #define A2XX_SQ_TEX_0_PITCH__SHIFT 22 1540 static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val) 1541 { 1542 return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK; 1543 } 1544 1545 #define REG_A2XX_SQ_TEX_1 0x00000001 1546 1547 #define REG_A2XX_SQ_TEX_2 0x00000002 1548 #define A2XX_SQ_TEX_2_WIDTH__MASK 0x00001fff 1549 #define A2XX_SQ_TEX_2_WIDTH__SHIFT 0 1550 static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val) 1551 { 1552 return ((val) << A2XX_SQ_TEX_2_WIDTH__SHIFT) & A2XX_SQ_TEX_2_WIDTH__MASK; 1553 } 1554 #define A2XX_SQ_TEX_2_HEIGHT__MASK 0x03ffe000 1555 #define A2XX_SQ_TEX_2_HEIGHT__SHIFT 13 1556 static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val) 1557 { 1558 return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK; 1559 } 1560 1561 #define REG_A2XX_SQ_TEX_3 0x00000003 1562 #define A2XX_SQ_TEX_3_SWIZ_X__MASK 0x0000000e 1563 #define A2XX_SQ_TEX_3_SWIZ_X__SHIFT 1 1564 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val) 1565 { 1566 return ((val) << A2XX_SQ_TEX_3_SWIZ_X__SHIFT) & A2XX_SQ_TEX_3_SWIZ_X__MASK; 1567 } 1568 #define A2XX_SQ_TEX_3_SWIZ_Y__MASK 0x00000070 1569 #define A2XX_SQ_TEX_3_SWIZ_Y__SHIFT 4 1570 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val) 1571 { 1572 return ((val) << A2XX_SQ_TEX_3_SWIZ_Y__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Y__MASK; 1573 } 1574 #define A2XX_SQ_TEX_3_SWIZ_Z__MASK 0x00000380 1575 #define A2XX_SQ_TEX_3_SWIZ_Z__SHIFT 7 1576 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val) 1577 { 1578 return ((val) << A2XX_SQ_TEX_3_SWIZ_Z__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Z__MASK; 1579 } 1580 #define A2XX_SQ_TEX_3_SWIZ_W__MASK 0x00001c00 1581 #define A2XX_SQ_TEX_3_SWIZ_W__SHIFT 10 1582 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val) 1583 { 1584 return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK; 1585 } 1586 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK 0x00180000 1587 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT 19 1588 static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val) 1589 { 1590 return ((val) << A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK; 1591 } 1592 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK 0x00600000 1593 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT 21 1594 static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val) 1595 { 1596 return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK; 1597 } 1598 1599 1600 #endif /* A2XX_XML */ 1601