1 #ifndef A2XX_XML 2 #define A2XX_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://github.com/freedreno/envytools/ 8 git clone https://github.com/freedreno/envytools.git 9 10 The rules-ng-ng source files this header was generated from are: 11 - /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13) 12 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13) 13 - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13) 14 - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13) 15 - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42393 bytes, from 2018-08-06 18:45:45) 16 - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13) 17 - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13) 18 - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-08-06 18:45:45) 19 - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 101627 bytes, from 2018-08-06 18:45:45) 20 - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-07-03 19:37:13) 21 - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13) 22 23 Copyright (C) 2013-2018 by the following authors: 24 - Rob Clark <robdclark@gmail.com> (robclark) 25 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 26 27 Permission is hereby granted, free of charge, to any person obtaining 28 a copy of this software and associated documentation files (the 29 "Software"), to deal in the Software without restriction, including 30 without limitation the rights to use, copy, modify, merge, publish, 31 distribute, sublicense, and/or sell copies of the Software, and to 32 permit persons to whom the Software is furnished to do so, subject to 33 the following conditions: 34 35 The above copyright notice and this permission notice (including the 36 next paragraph) shall be included in all copies or substantial 37 portions of the Software. 38 39 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 40 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 41 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 42 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 43 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 44 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 45 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48 49 enum a2xx_rb_dither_type { 50 DITHER_PIXEL = 0, 51 DITHER_SUBPIXEL = 1, 52 }; 53 54 enum a2xx_colorformatx { 55 COLORX_4_4_4_4 = 0, 56 COLORX_1_5_5_5 = 1, 57 COLORX_5_6_5 = 2, 58 COLORX_8 = 3, 59 COLORX_8_8 = 4, 60 COLORX_8_8_8_8 = 5, 61 COLORX_S8_8_8_8 = 6, 62 COLORX_16_FLOAT = 7, 63 COLORX_16_16_FLOAT = 8, 64 COLORX_16_16_16_16_FLOAT = 9, 65 COLORX_32_FLOAT = 10, 66 COLORX_32_32_FLOAT = 11, 67 COLORX_32_32_32_32_FLOAT = 12, 68 COLORX_2_3_3 = 13, 69 COLORX_8_8_8 = 14, 70 }; 71 72 enum a2xx_sq_surfaceformat { 73 FMT_1_REVERSE = 0, 74 FMT_1 = 1, 75 FMT_8 = 2, 76 FMT_1_5_5_5 = 3, 77 FMT_5_6_5 = 4, 78 FMT_6_5_5 = 5, 79 FMT_8_8_8_8 = 6, 80 FMT_2_10_10_10 = 7, 81 FMT_8_A = 8, 82 FMT_8_B = 9, 83 FMT_8_8 = 10, 84 FMT_Cr_Y1_Cb_Y0 = 11, 85 FMT_Y1_Cr_Y0_Cb = 12, 86 FMT_5_5_5_1 = 13, 87 FMT_8_8_8_8_A = 14, 88 FMT_4_4_4_4 = 15, 89 FMT_8_8_8 = 16, 90 FMT_DXT1 = 18, 91 FMT_DXT2_3 = 19, 92 FMT_DXT4_5 = 20, 93 FMT_10_10_10_2 = 21, 94 FMT_24_8 = 22, 95 FMT_16 = 24, 96 FMT_16_16 = 25, 97 FMT_16_16_16_16 = 26, 98 FMT_16_EXPAND = 27, 99 FMT_16_16_EXPAND = 28, 100 FMT_16_16_16_16_EXPAND = 29, 101 FMT_16_FLOAT = 30, 102 FMT_16_16_FLOAT = 31, 103 FMT_16_16_16_16_FLOAT = 32, 104 FMT_32 = 33, 105 FMT_32_32 = 34, 106 FMT_32_32_32_32 = 35, 107 FMT_32_FLOAT = 36, 108 FMT_32_32_FLOAT = 37, 109 FMT_32_32_32_32_FLOAT = 38, 110 FMT_ATI_TC_RGB = 39, 111 FMT_ATI_TC_RGBA = 40, 112 FMT_ATI_TC_555_565_RGB = 41, 113 FMT_ATI_TC_555_565_RGBA = 42, 114 FMT_ATI_TC_RGBA_INTERP = 43, 115 FMT_ATI_TC_555_565_RGBA_INTERP = 44, 116 FMT_ETC1_RGBA_INTERP = 46, 117 FMT_ETC1_RGB = 47, 118 FMT_ETC1_RGBA = 48, 119 FMT_DXN = 49, 120 FMT_2_3_3 = 51, 121 FMT_2_10_10_10_AS_16_16_16_16 = 54, 122 FMT_10_10_10_2_AS_16_16_16_16 = 55, 123 FMT_32_32_32_FLOAT = 57, 124 FMT_DXT3A = 58, 125 FMT_DXT5A = 59, 126 FMT_CTX1 = 60, 127 }; 128 129 enum a2xx_sq_ps_vtx_mode { 130 POSITION_1_VECTOR = 0, 131 POSITION_2_VECTORS_UNUSED = 1, 132 POSITION_2_VECTORS_SPRITE = 2, 133 POSITION_2_VECTORS_EDGE = 3, 134 POSITION_2_VECTORS_KILL = 4, 135 POSITION_2_VECTORS_SPRITE_KILL = 5, 136 POSITION_2_VECTORS_EDGE_KILL = 6, 137 MULTIPASS = 7, 138 }; 139 140 enum a2xx_sq_sample_cntl { 141 CENTROIDS_ONLY = 0, 142 CENTERS_ONLY = 1, 143 CENTROIDS_AND_CENTERS = 2, 144 }; 145 146 enum a2xx_dx_clip_space { 147 DXCLIP_OPENGL = 0, 148 DXCLIP_DIRECTX = 1, 149 }; 150 151 enum a2xx_pa_su_sc_polymode { 152 POLY_DISABLED = 0, 153 POLY_DUALMODE = 1, 154 }; 155 156 enum a2xx_rb_edram_mode { 157 EDRAM_NOP = 0, 158 COLOR_DEPTH = 4, 159 DEPTH_ONLY = 5, 160 EDRAM_COPY = 6, 161 }; 162 163 enum a2xx_pa_sc_pattern_bit_order { 164 LITTLE = 0, 165 BIG = 1, 166 }; 167 168 enum a2xx_pa_sc_auto_reset_cntl { 169 NEVER = 0, 170 EACH_PRIMITIVE = 1, 171 EACH_PACKET = 2, 172 }; 173 174 enum a2xx_pa_pixcenter { 175 PIXCENTER_D3D = 0, 176 PIXCENTER_OGL = 1, 177 }; 178 179 enum a2xx_pa_roundmode { 180 TRUNCATE = 0, 181 ROUND = 1, 182 ROUNDTOEVEN = 2, 183 ROUNDTOODD = 3, 184 }; 185 186 enum a2xx_pa_quantmode { 187 ONE_SIXTEENTH = 0, 188 ONE_EIGTH = 1, 189 ONE_QUARTER = 2, 190 ONE_HALF = 3, 191 ONE = 4, 192 }; 193 194 enum a2xx_rb_copy_sample_select { 195 SAMPLE_0 = 0, 196 SAMPLE_1 = 1, 197 SAMPLE_2 = 2, 198 SAMPLE_3 = 3, 199 SAMPLE_01 = 4, 200 SAMPLE_23 = 5, 201 SAMPLE_0123 = 6, 202 }; 203 204 enum a2xx_rb_blend_opcode { 205 BLEND2_DST_PLUS_SRC = 0, 206 BLEND2_SRC_MINUS_DST = 1, 207 BLEND2_MIN_DST_SRC = 2, 208 BLEND2_MAX_DST_SRC = 3, 209 BLEND2_DST_MINUS_SRC = 4, 210 BLEND2_DST_PLUS_SRC_BIAS = 5, 211 }; 212 213 enum adreno_mmu_clnt_beh { 214 BEH_NEVR = 0, 215 BEH_TRAN_RNG = 1, 216 BEH_TRAN_FLT = 2, 217 }; 218 219 enum sq_tex_clamp { 220 SQ_TEX_WRAP = 0, 221 SQ_TEX_MIRROR = 1, 222 SQ_TEX_CLAMP_LAST_TEXEL = 2, 223 SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3, 224 SQ_TEX_CLAMP_HALF_BORDER = 4, 225 SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5, 226 SQ_TEX_CLAMP_BORDER = 6, 227 SQ_TEX_MIRROR_ONCE_BORDER = 7, 228 }; 229 230 enum sq_tex_swiz { 231 SQ_TEX_X = 0, 232 SQ_TEX_Y = 1, 233 SQ_TEX_Z = 2, 234 SQ_TEX_W = 3, 235 SQ_TEX_ZERO = 4, 236 SQ_TEX_ONE = 5, 237 }; 238 239 enum sq_tex_filter { 240 SQ_TEX_FILTER_POINT = 0, 241 SQ_TEX_FILTER_BILINEAR = 1, 242 SQ_TEX_FILTER_BICUBIC = 2, 243 }; 244 245 #define REG_A2XX_RBBM_PATCH_RELEASE 0x00000001 246 247 #define REG_A2XX_RBBM_CNTL 0x0000003b 248 249 #define REG_A2XX_RBBM_SOFT_RESET 0x0000003c 250 251 #define REG_A2XX_CP_PFP_UCODE_ADDR 0x000000c0 252 253 #define REG_A2XX_CP_PFP_UCODE_DATA 0x000000c1 254 255 #define REG_A2XX_MH_MMU_CONFIG 0x00000040 256 #define A2XX_MH_MMU_CONFIG_MMU_ENABLE 0x00000001 257 #define A2XX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE 0x00000002 258 #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK 0x00000030 259 #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT 4 260 static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 261 { 262 return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK; 263 } 264 #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK 0x000000c0 265 #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT 6 266 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 267 { 268 return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK; 269 } 270 #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK 0x00000300 271 #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT 8 272 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 273 { 274 return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK; 275 } 276 #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK 0x00000c00 277 #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT 10 278 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 279 { 280 return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK; 281 } 282 #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK 0x00003000 283 #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT 12 284 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 285 { 286 return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK; 287 } 288 #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK 0x0000c000 289 #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT 14 290 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 291 { 292 return ((val) << A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK; 293 } 294 #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK 0x00030000 295 #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT 16 296 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 297 { 298 return ((val) << A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK; 299 } 300 #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK 0x000c0000 301 #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT 18 302 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 303 { 304 return ((val) << A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK; 305 } 306 #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK 0x00300000 307 #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT 20 308 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 309 { 310 return ((val) << A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK; 311 } 312 #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK 0x00c00000 313 #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT 22 314 static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 315 { 316 return ((val) << A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK; 317 } 318 #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK 0x03000000 319 #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT 24 320 static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 321 { 322 return ((val) << A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK; 323 } 324 325 #define REG_A2XX_MH_MMU_VA_RANGE 0x00000041 326 327 #define REG_A2XX_MH_MMU_PT_BASE 0x00000042 328 329 #define REG_A2XX_MH_MMU_PAGE_FAULT 0x00000043 330 331 #define REG_A2XX_MH_MMU_TRAN_ERROR 0x00000044 332 333 #define REG_A2XX_MH_MMU_INVALIDATE 0x00000045 334 335 #define REG_A2XX_MH_MMU_MPU_BASE 0x00000046 336 337 #define REG_A2XX_MH_MMU_MPU_END 0x00000047 338 339 #define REG_A2XX_NQWAIT_UNTIL 0x00000394 340 341 #define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395 342 343 #define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397 344 345 #define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x00000398 346 347 #define REG_A2XX_RBBM_DEBUG 0x0000039b 348 349 #define REG_A2XX_RBBM_PM_OVERRIDE1 0x0000039c 350 #define A2XX_RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE 0x00000001 351 #define A2XX_RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE 0x00000002 352 #define A2XX_RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE 0x00000004 353 #define A2XX_RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE 0x00000008 354 #define A2XX_RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE 0x00000010 355 #define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE 0x00000020 356 #define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE 0x00000040 357 #define A2XX_RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE 0x00000080 358 #define A2XX_RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE 0x00000100 359 #define A2XX_RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE 0x00000200 360 #define A2XX_RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE 0x00000400 361 #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE 0x00000800 362 #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE 0x00001000 363 #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE 0x00002000 364 #define A2XX_RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE 0x00004000 365 #define A2XX_RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE 0x00008000 366 #define A2XX_RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE 0x00010000 367 #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE 0x00020000 368 #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE 0x00040000 369 #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE 0x00080000 370 #define A2XX_RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE 0x00100000 371 #define A2XX_RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE 0x00200000 372 #define A2XX_RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE 0x00400000 373 #define A2XX_RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE 0x00800000 374 #define A2XX_RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE 0x01000000 375 #define A2XX_RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE 0x02000000 376 #define A2XX_RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE 0x04000000 377 #define A2XX_RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE 0x08000000 378 #define A2XX_RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE 0x10000000 379 #define A2XX_RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE 0x20000000 380 #define A2XX_RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE 0x40000000 381 #define A2XX_RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE 0x80000000 382 383 #define REG_A2XX_RBBM_PM_OVERRIDE2 0x0000039d 384 385 #define REG_A2XX_RBBM_DEBUG_OUT 0x000003a0 386 387 #define REG_A2XX_RBBM_DEBUG_CNTL 0x000003a1 388 389 #define REG_A2XX_RBBM_READ_ERROR 0x000003b3 390 391 #define REG_A2XX_RBBM_INT_CNTL 0x000003b4 392 393 #define REG_A2XX_RBBM_INT_STATUS 0x000003b5 394 395 #define REG_A2XX_RBBM_INT_ACK 0x000003b6 396 397 #define REG_A2XX_MASTER_INT_SIGNAL 0x000003b7 398 399 #define REG_A2XX_RBBM_PERIPHID1 0x000003f9 400 401 #define REG_A2XX_RBBM_PERIPHID2 0x000003fa 402 403 #define REG_A2XX_CP_PERFMON_CNTL 0x00000444 404 405 #define REG_A2XX_CP_PERFCOUNTER_SELECT 0x00000445 406 407 #define REG_A2XX_CP_PERFCOUNTER_LO 0x00000446 408 409 #define REG_A2XX_CP_PERFCOUNTER_HI 0x00000447 410 411 #define REG_A2XX_RBBM_STATUS 0x000005d0 412 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK 0x0000001f 413 #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT 0 414 static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val) 415 { 416 return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK; 417 } 418 #define A2XX_RBBM_STATUS_TC_BUSY 0x00000020 419 #define A2XX_RBBM_STATUS_HIRQ_PENDING 0x00000100 420 #define A2XX_RBBM_STATUS_CPRQ_PENDING 0x00000200 421 #define A2XX_RBBM_STATUS_CFRQ_PENDING 0x00000400 422 #define A2XX_RBBM_STATUS_PFRQ_PENDING 0x00000800 423 #define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA 0x00001000 424 #define A2XX_RBBM_STATUS_RBBM_WU_BUSY 0x00004000 425 #define A2XX_RBBM_STATUS_CP_NRT_BUSY 0x00010000 426 #define A2XX_RBBM_STATUS_MH_BUSY 0x00040000 427 #define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY 0x00080000 428 #define A2XX_RBBM_STATUS_SX_BUSY 0x00200000 429 #define A2XX_RBBM_STATUS_TPC_BUSY 0x00400000 430 #define A2XX_RBBM_STATUS_SC_CNTX_BUSY 0x01000000 431 #define A2XX_RBBM_STATUS_PA_BUSY 0x02000000 432 #define A2XX_RBBM_STATUS_VGT_BUSY 0x04000000 433 #define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY 0x08000000 434 #define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY 0x10000000 435 #define A2XX_RBBM_STATUS_RB_CNTX_BUSY 0x40000000 436 #define A2XX_RBBM_STATUS_GUI_ACTIVE 0x80000000 437 438 #define REG_A2XX_MH_ARBITER_CONFIG 0x00000a40 439 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK 0x0000003f 440 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT 0 441 static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val) 442 { 443 return ((val) << A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK; 444 } 445 #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY 0x00000040 446 #define A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE 0x00000080 447 #define A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE 0x00000100 448 #define A2XX_MH_ARBITER_CONFIG_L2_ARB_CONTROL 0x00000200 449 #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK 0x00001c00 450 #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT 10 451 static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val) 452 { 453 return ((val) << A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT) & A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK; 454 } 455 #define A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00002000 456 #define A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE 0x00004000 457 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE 0x00008000 458 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK 0x003f0000 459 #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT 16 460 static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val) 461 { 462 return ((val) << A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK; 463 } 464 #define A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE 0x00400000 465 #define A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE 0x00800000 466 #define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE 0x01000000 467 #define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE 0x02000000 468 #define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE 0x04000000 469 470 #define REG_A2XX_A220_VSC_BIN_SIZE 0x00000c01 471 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 472 #define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT 0 473 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val) 474 { 475 return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK; 476 } 477 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 478 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT 5 479 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val) 480 { 481 return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK; 482 } 483 484 static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 485 486 static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 487 488 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } 489 490 static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } 491 492 #define REG_A2XX_PC_DEBUG_CNTL 0x00000c38 493 494 #define REG_A2XX_PC_DEBUG_DATA 0x00000c39 495 496 #define REG_A2XX_PA_SC_VIZ_QUERY_STATUS 0x00000c44 497 498 #define REG_A2XX_GRAS_DEBUG_CNTL 0x00000c80 499 500 #define REG_A2XX_PA_SU_DEBUG_CNTL 0x00000c80 501 502 #define REG_A2XX_GRAS_DEBUG_DATA 0x00000c81 503 504 #define REG_A2XX_PA_SU_DEBUG_DATA 0x00000c81 505 506 #define REG_A2XX_PA_SU_FACE_DATA 0x00000c86 507 #define A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK 0xffffffe0 508 #define A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT 5 509 static inline uint32_t A2XX_PA_SU_FACE_DATA_BASE_ADDR(uint32_t val) 510 { 511 return ((val) << A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT) & A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK; 512 } 513 514 #define REG_A2XX_SQ_GPR_MANAGEMENT 0x00000d00 515 #define A2XX_SQ_GPR_MANAGEMENT_REG_DYNAMIC 0x00000001 516 #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK 0x00000ff0 517 #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT 4 518 static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX(uint32_t val) 519 { 520 return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK; 521 } 522 #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK 0x000ff000 523 #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT 12 524 static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX(uint32_t val) 525 { 526 return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK; 527 } 528 529 #define REG_A2XX_SQ_FLOW_CONTROL 0x00000d01 530 531 #define REG_A2XX_SQ_INST_STORE_MANAGMENT 0x00000d02 532 #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK 0x00000fff 533 #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT 0 534 static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX(uint32_t val) 535 { 536 return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK; 537 } 538 #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK 0x0fff0000 539 #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT 16 540 static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX(uint32_t val) 541 { 542 return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK; 543 } 544 545 #define REG_A2XX_SQ_DEBUG_MISC 0x00000d05 546 547 #define REG_A2XX_SQ_INT_CNTL 0x00000d34 548 549 #define REG_A2XX_SQ_INT_STATUS 0x00000d35 550 551 #define REG_A2XX_SQ_INT_ACK 0x00000d36 552 553 #define REG_A2XX_SQ_DEBUG_INPUT_FSM 0x00000dae 554 555 #define REG_A2XX_SQ_DEBUG_CONST_MGR_FSM 0x00000daf 556 557 #define REG_A2XX_SQ_DEBUG_TP_FSM 0x00000db0 558 559 #define REG_A2XX_SQ_DEBUG_FSM_ALU_0 0x00000db1 560 561 #define REG_A2XX_SQ_DEBUG_FSM_ALU_1 0x00000db2 562 563 #define REG_A2XX_SQ_DEBUG_EXP_ALLOC 0x00000db3 564 565 #define REG_A2XX_SQ_DEBUG_PTR_BUFF 0x00000db4 566 567 #define REG_A2XX_SQ_DEBUG_GPR_VTX 0x00000db5 568 569 #define REG_A2XX_SQ_DEBUG_GPR_PIX 0x00000db6 570 571 #define REG_A2XX_SQ_DEBUG_TB_STATUS_SEL 0x00000db7 572 573 #define REG_A2XX_SQ_DEBUG_VTX_TB_0 0x00000db8 574 575 #define REG_A2XX_SQ_DEBUG_VTX_TB_1 0x00000db9 576 577 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG 0x00000dba 578 579 #define REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM 0x00000dbb 580 581 #define REG_A2XX_SQ_DEBUG_PIX_TB_0 0x00000dbc 582 583 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0 0x00000dbd 584 585 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1 0x00000dbe 586 587 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2 0x00000dbf 588 589 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3 0x00000dc0 590 591 #define REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM 0x00000dc1 592 593 #define REG_A2XX_TC_CNTL_STATUS 0x00000e00 594 #define A2XX_TC_CNTL_STATUS_L2_INVALIDATE 0x00000001 595 596 #define REG_A2XX_TP0_CHICKEN 0x00000e1e 597 598 #define REG_A2XX_RB_BC_CONTROL 0x00000f01 599 #define A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE 0x00000001 600 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK 0x00000006 601 #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT 1 602 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val) 603 { 604 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK; 605 } 606 #define A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM 0x00000008 607 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010 608 #define A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP 0x00000020 609 #define A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP 0x00000040 610 #define A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE 0x00000080 611 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK 0x00001f00 612 #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT 8 613 static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val) 614 { 615 return ((val) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK; 616 } 617 #define A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE 0x00004000 618 #define A2XX_RB_BC_CONTROL_CRC_MODE 0x00008000 619 #define A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS 0x00010000 620 #define A2XX_RB_BC_CONTROL_DISABLE_ACCUM 0x00020000 621 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK 0x003c0000 622 #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT 18 623 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val) 624 { 625 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK; 626 } 627 #define A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE 0x00400000 628 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK 0x07800000 629 #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT 23 630 static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val) 631 { 632 return ((val) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK; 633 } 634 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK 0x18000000 635 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT 27 636 static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val) 637 { 638 return ((val) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK; 639 } 640 #define A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000 641 #define A2XX_RB_BC_CONTROL_CRC_SYSTEM 0x40000000 642 #define A2XX_RB_BC_CONTROL_RESERVED6 0x80000000 643 644 #define REG_A2XX_RB_EDRAM_INFO 0x00000f02 645 646 #define REG_A2XX_RB_DEBUG_CNTL 0x00000f26 647 648 #define REG_A2XX_RB_DEBUG_DATA 0x00000f27 649 650 #define REG_A2XX_RB_SURFACE_INFO 0x00002000 651 652 #define REG_A2XX_RB_COLOR_INFO 0x00002001 653 #define A2XX_RB_COLOR_INFO_FORMAT__MASK 0x0000000f 654 #define A2XX_RB_COLOR_INFO_FORMAT__SHIFT 0 655 static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val) 656 { 657 return ((val) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT) & A2XX_RB_COLOR_INFO_FORMAT__MASK; 658 } 659 #define A2XX_RB_COLOR_INFO_ROUND_MODE__MASK 0x00000030 660 #define A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT 4 661 static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val) 662 { 663 return ((val) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK; 664 } 665 #define A2XX_RB_COLOR_INFO_LINEAR 0x00000040 666 #define A2XX_RB_COLOR_INFO_ENDIAN__MASK 0x00000180 667 #define A2XX_RB_COLOR_INFO_ENDIAN__SHIFT 7 668 static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val) 669 { 670 return ((val) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT) & A2XX_RB_COLOR_INFO_ENDIAN__MASK; 671 } 672 #define A2XX_RB_COLOR_INFO_SWAP__MASK 0x00000600 673 #define A2XX_RB_COLOR_INFO_SWAP__SHIFT 9 674 static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val) 675 { 676 return ((val) << A2XX_RB_COLOR_INFO_SWAP__SHIFT) & A2XX_RB_COLOR_INFO_SWAP__MASK; 677 } 678 #define A2XX_RB_COLOR_INFO_BASE__MASK 0xfffff000 679 #define A2XX_RB_COLOR_INFO_BASE__SHIFT 12 680 static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val) 681 { 682 return ((val >> 10) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK; 683 } 684 685 #define REG_A2XX_RB_DEPTH_INFO 0x00002002 686 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001 687 #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 688 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) 689 { 690 return ((val) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 691 } 692 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 693 #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 694 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 695 { 696 return ((val >> 10) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 697 } 698 699 #define REG_A2XX_A225_RB_COLOR_INFO3 0x00002005 700 701 #define REG_A2XX_COHER_DEST_BASE_0 0x00002006 702 703 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_TL 0x0000200e 704 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 705 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 706 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 707 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 708 { 709 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK; 710 } 711 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 712 #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 713 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 714 { 715 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK; 716 } 717 718 #define REG_A2XX_PA_SC_SCREEN_SCISSOR_BR 0x0000200f 719 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 720 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 721 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 722 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 723 { 724 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK; 725 } 726 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 727 #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 728 static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 729 { 730 return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK; 731 } 732 733 #define REG_A2XX_PA_SC_WINDOW_OFFSET 0x00002080 734 #define A2XX_PA_SC_WINDOW_OFFSET_X__MASK 0x00007fff 735 #define A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT 0 736 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val) 737 { 738 return ((val) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK; 739 } 740 #define A2XX_PA_SC_WINDOW_OFFSET_Y__MASK 0x7fff0000 741 #define A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT 16 742 static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val) 743 { 744 return ((val) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK; 745 } 746 #define A2XX_PA_SC_WINDOW_OFFSET_DISABLE 0x80000000 747 748 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_TL 0x00002081 749 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 750 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 751 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 752 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 753 { 754 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK; 755 } 756 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 757 #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 758 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 759 { 760 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK; 761 } 762 763 #define REG_A2XX_PA_SC_WINDOW_SCISSOR_BR 0x00002082 764 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 765 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 766 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 767 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 768 { 769 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK; 770 } 771 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 772 #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 773 static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 774 { 775 return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK; 776 } 777 778 #define REG_A2XX_UNKNOWN_2010 0x00002010 779 780 #define REG_A2XX_VGT_MAX_VTX_INDX 0x00002100 781 782 #define REG_A2XX_VGT_MIN_VTX_INDX 0x00002101 783 784 #define REG_A2XX_VGT_INDX_OFFSET 0x00002102 785 786 #define REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX 0x00002103 787 788 #define REG_A2XX_RB_COLOR_MASK 0x00002104 789 #define A2XX_RB_COLOR_MASK_WRITE_RED 0x00000001 790 #define A2XX_RB_COLOR_MASK_WRITE_GREEN 0x00000002 791 #define A2XX_RB_COLOR_MASK_WRITE_BLUE 0x00000004 792 #define A2XX_RB_COLOR_MASK_WRITE_ALPHA 0x00000008 793 794 #define REG_A2XX_RB_BLEND_RED 0x00002105 795 796 #define REG_A2XX_RB_BLEND_GREEN 0x00002106 797 798 #define REG_A2XX_RB_BLEND_BLUE 0x00002107 799 800 #define REG_A2XX_RB_BLEND_ALPHA 0x00002108 801 802 #define REG_A2XX_RB_FOG_COLOR 0x00002109 803 #define A2XX_RB_FOG_COLOR_FOG_RED__MASK 0x000000ff 804 #define A2XX_RB_FOG_COLOR_FOG_RED__SHIFT 0 805 static inline uint32_t A2XX_RB_FOG_COLOR_FOG_RED(uint32_t val) 806 { 807 return ((val) << A2XX_RB_FOG_COLOR_FOG_RED__SHIFT) & A2XX_RB_FOG_COLOR_FOG_RED__MASK; 808 } 809 #define A2XX_RB_FOG_COLOR_FOG_GREEN__MASK 0x0000ff00 810 #define A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT 8 811 static inline uint32_t A2XX_RB_FOG_COLOR_FOG_GREEN(uint32_t val) 812 { 813 return ((val) << A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT) & A2XX_RB_FOG_COLOR_FOG_GREEN__MASK; 814 } 815 #define A2XX_RB_FOG_COLOR_FOG_BLUE__MASK 0x00ff0000 816 #define A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT 16 817 static inline uint32_t A2XX_RB_FOG_COLOR_FOG_BLUE(uint32_t val) 818 { 819 return ((val) << A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT) & A2XX_RB_FOG_COLOR_FOG_BLUE__MASK; 820 } 821 822 #define REG_A2XX_RB_STENCILREFMASK_BF 0x0000210c 823 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 824 #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 825 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 826 { 827 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 828 } 829 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 830 #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 831 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 832 { 833 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 834 } 835 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 836 #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 837 static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 838 { 839 return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 840 } 841 842 #define REG_A2XX_RB_STENCILREFMASK 0x0000210d 843 #define A2XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 844 #define A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 845 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 846 { 847 return ((val) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK; 848 } 849 #define A2XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 850 #define A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 851 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 852 { 853 return ((val) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK; 854 } 855 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 856 #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 857 static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 858 { 859 return ((val) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 860 } 861 862 #define REG_A2XX_RB_ALPHA_REF 0x0000210e 863 864 #define REG_A2XX_PA_CL_VPORT_XSCALE 0x0000210f 865 #define A2XX_PA_CL_VPORT_XSCALE__MASK 0xffffffff 866 #define A2XX_PA_CL_VPORT_XSCALE__SHIFT 0 867 static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val) 868 { 869 return ((fui(val)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT) & A2XX_PA_CL_VPORT_XSCALE__MASK; 870 } 871 872 #define REG_A2XX_PA_CL_VPORT_XOFFSET 0x00002110 873 #define A2XX_PA_CL_VPORT_XOFFSET__MASK 0xffffffff 874 #define A2XX_PA_CL_VPORT_XOFFSET__SHIFT 0 875 static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val) 876 { 877 return ((fui(val)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT) & A2XX_PA_CL_VPORT_XOFFSET__MASK; 878 } 879 880 #define REG_A2XX_PA_CL_VPORT_YSCALE 0x00002111 881 #define A2XX_PA_CL_VPORT_YSCALE__MASK 0xffffffff 882 #define A2XX_PA_CL_VPORT_YSCALE__SHIFT 0 883 static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val) 884 { 885 return ((fui(val)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT) & A2XX_PA_CL_VPORT_YSCALE__MASK; 886 } 887 888 #define REG_A2XX_PA_CL_VPORT_YOFFSET 0x00002112 889 #define A2XX_PA_CL_VPORT_YOFFSET__MASK 0xffffffff 890 #define A2XX_PA_CL_VPORT_YOFFSET__SHIFT 0 891 static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val) 892 { 893 return ((fui(val)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT) & A2XX_PA_CL_VPORT_YOFFSET__MASK; 894 } 895 896 #define REG_A2XX_PA_CL_VPORT_ZSCALE 0x00002113 897 #define A2XX_PA_CL_VPORT_ZSCALE__MASK 0xffffffff 898 #define A2XX_PA_CL_VPORT_ZSCALE__SHIFT 0 899 static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val) 900 { 901 return ((fui(val)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT) & A2XX_PA_CL_VPORT_ZSCALE__MASK; 902 } 903 904 #define REG_A2XX_PA_CL_VPORT_ZOFFSET 0x00002114 905 #define A2XX_PA_CL_VPORT_ZOFFSET__MASK 0xffffffff 906 #define A2XX_PA_CL_VPORT_ZOFFSET__SHIFT 0 907 static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val) 908 { 909 return ((fui(val)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT) & A2XX_PA_CL_VPORT_ZOFFSET__MASK; 910 } 911 912 #define REG_A2XX_SQ_PROGRAM_CNTL 0x00002180 913 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK 0x000000ff 914 #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT 0 915 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val) 916 { 917 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK; 918 } 919 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK 0x0000ff00 920 #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT 8 921 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val) 922 { 923 return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK; 924 } 925 #define A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE 0x00010000 926 #define A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE 0x00020000 927 #define A2XX_SQ_PROGRAM_CNTL_PARAM_GEN 0x00040000 928 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX 0x00080000 929 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK 0x00f00000 930 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT 20 931 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val) 932 { 933 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK; 934 } 935 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK 0x07000000 936 #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT 24 937 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val) 938 { 939 return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK; 940 } 941 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK 0x78000000 942 #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT 27 943 static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val) 944 { 945 return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK; 946 } 947 #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX 0x80000000 948 949 #define REG_A2XX_SQ_CONTEXT_MISC 0x00002181 950 #define A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE 0x00000001 951 #define A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY 0x00000002 952 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK 0x0000000c 953 #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT 2 954 static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val) 955 { 956 return ((val) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK; 957 } 958 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK 0x0000ff00 959 #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT 8 960 static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val) 961 { 962 return ((val) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK; 963 } 964 #define A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF 0x00010000 965 #define A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE 0x00020000 966 #define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL 0x00040000 967 968 #define REG_A2XX_SQ_INTERPOLATOR_CNTL 0x00002182 969 #define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK 0x0000ffff 970 #define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT 0 971 static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE(uint32_t val) 972 { 973 return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK; 974 } 975 #define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK 0xffff0000 976 #define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT 16 977 static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN(uint32_t val) 978 { 979 return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK; 980 } 981 982 #define REG_A2XX_SQ_WRAPPING_0 0x00002183 983 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK 0x0000000f 984 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT 0 985 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_0(uint32_t val) 986 { 987 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK; 988 } 989 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK 0x000000f0 990 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT 4 991 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_1(uint32_t val) 992 { 993 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK; 994 } 995 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK 0x00000f00 996 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT 8 997 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_2(uint32_t val) 998 { 999 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK; 1000 } 1001 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK 0x0000f000 1002 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT 12 1003 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_3(uint32_t val) 1004 { 1005 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK; 1006 } 1007 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK 0x000f0000 1008 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT 16 1009 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_4(uint32_t val) 1010 { 1011 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK; 1012 } 1013 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK 0x00f00000 1014 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT 20 1015 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_5(uint32_t val) 1016 { 1017 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK; 1018 } 1019 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK 0x0f000000 1020 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT 24 1021 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_6(uint32_t val) 1022 { 1023 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK; 1024 } 1025 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK 0xf0000000 1026 #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT 28 1027 static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_7(uint32_t val) 1028 { 1029 return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK; 1030 } 1031 1032 #define REG_A2XX_SQ_WRAPPING_1 0x00002184 1033 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK 0x0000000f 1034 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT 0 1035 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_8(uint32_t val) 1036 { 1037 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK; 1038 } 1039 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK 0x000000f0 1040 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT 4 1041 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_9(uint32_t val) 1042 { 1043 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK; 1044 } 1045 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK 0x00000f00 1046 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT 8 1047 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_10(uint32_t val) 1048 { 1049 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK; 1050 } 1051 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK 0x0000f000 1052 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT 12 1053 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_11(uint32_t val) 1054 { 1055 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK; 1056 } 1057 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK 0x000f0000 1058 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT 16 1059 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_12(uint32_t val) 1060 { 1061 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK; 1062 } 1063 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK 0x00f00000 1064 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT 20 1065 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_13(uint32_t val) 1066 { 1067 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK; 1068 } 1069 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK 0x0f000000 1070 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT 24 1071 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_14(uint32_t val) 1072 { 1073 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK; 1074 } 1075 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK 0xf0000000 1076 #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT 28 1077 static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_15(uint32_t val) 1078 { 1079 return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK; 1080 } 1081 1082 #define REG_A2XX_SQ_PS_PROGRAM 0x000021f6 1083 #define A2XX_SQ_PS_PROGRAM_BASE__MASK 0x00000fff 1084 #define A2XX_SQ_PS_PROGRAM_BASE__SHIFT 0 1085 static inline uint32_t A2XX_SQ_PS_PROGRAM_BASE(uint32_t val) 1086 { 1087 return ((val) << A2XX_SQ_PS_PROGRAM_BASE__SHIFT) & A2XX_SQ_PS_PROGRAM_BASE__MASK; 1088 } 1089 #define A2XX_SQ_PS_PROGRAM_SIZE__MASK 0x00fff000 1090 #define A2XX_SQ_PS_PROGRAM_SIZE__SHIFT 12 1091 static inline uint32_t A2XX_SQ_PS_PROGRAM_SIZE(uint32_t val) 1092 { 1093 return ((val) << A2XX_SQ_PS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_PS_PROGRAM_SIZE__MASK; 1094 } 1095 1096 #define REG_A2XX_SQ_VS_PROGRAM 0x000021f7 1097 #define A2XX_SQ_VS_PROGRAM_BASE__MASK 0x00000fff 1098 #define A2XX_SQ_VS_PROGRAM_BASE__SHIFT 0 1099 static inline uint32_t A2XX_SQ_VS_PROGRAM_BASE(uint32_t val) 1100 { 1101 return ((val) << A2XX_SQ_VS_PROGRAM_BASE__SHIFT) & A2XX_SQ_VS_PROGRAM_BASE__MASK; 1102 } 1103 #define A2XX_SQ_VS_PROGRAM_SIZE__MASK 0x00fff000 1104 #define A2XX_SQ_VS_PROGRAM_SIZE__SHIFT 12 1105 static inline uint32_t A2XX_SQ_VS_PROGRAM_SIZE(uint32_t val) 1106 { 1107 return ((val) << A2XX_SQ_VS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_VS_PROGRAM_SIZE__MASK; 1108 } 1109 1110 #define REG_A2XX_VGT_EVENT_INITIATOR 0x000021f9 1111 1112 #define REG_A2XX_VGT_DRAW_INITIATOR 0x000021fc 1113 #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f 1114 #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 1115 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) 1116 { 1117 return ((val) << A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK; 1118 } 1119 #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 1120 #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 1121 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) 1122 { 1123 return ((val) << A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK; 1124 } 1125 #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600 1126 #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9 1127 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) 1128 { 1129 return ((val) << A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK; 1130 } 1131 #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800 1132 #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11 1133 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) 1134 { 1135 return ((val) << A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK; 1136 } 1137 #define A2XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000 1138 #define A2XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000 1139 #define A2XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000 1140 #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK 0xff000000 1141 #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT 24 1142 static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) 1143 { 1144 return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK; 1145 } 1146 1147 #define REG_A2XX_VGT_IMMED_DATA 0x000021fd 1148 1149 #define REG_A2XX_RB_DEPTHCONTROL 0x00002200 1150 #define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE 0x00000001 1151 #define A2XX_RB_DEPTHCONTROL_Z_ENABLE 0x00000002 1152 #define A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE 0x00000004 1153 #define A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE 0x00000008 1154 #define A2XX_RB_DEPTHCONTROL_ZFUNC__MASK 0x00000070 1155 #define A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT 4 1156 static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val) 1157 { 1158 return ((val) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK; 1159 } 1160 #define A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE 0x00000080 1161 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK 0x00000700 1162 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT 8 1163 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val) 1164 { 1165 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK; 1166 } 1167 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK 0x00003800 1168 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT 11 1169 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val) 1170 { 1171 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK; 1172 } 1173 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK 0x0001c000 1174 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT 14 1175 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val) 1176 { 1177 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK; 1178 } 1179 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK 0x000e0000 1180 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT 17 1181 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val) 1182 { 1183 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK; 1184 } 1185 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK 0x00700000 1186 #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT 20 1187 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val) 1188 { 1189 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK; 1190 } 1191 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK 0x03800000 1192 #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT 23 1193 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val) 1194 { 1195 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK; 1196 } 1197 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK 0x1c000000 1198 #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT 26 1199 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val) 1200 { 1201 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK; 1202 } 1203 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK 0xe0000000 1204 #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT 29 1205 static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val) 1206 { 1207 return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK; 1208 } 1209 1210 #define REG_A2XX_RB_BLEND_CONTROL 0x00002201 1211 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK 0x0000001f 1212 #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT 0 1213 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val) 1214 { 1215 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK; 1216 } 1217 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK 0x000000e0 1218 #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT 5 1219 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val) 1220 { 1221 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK; 1222 } 1223 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK 0x00001f00 1224 #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT 8 1225 static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val) 1226 { 1227 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK; 1228 } 1229 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK 0x001f0000 1230 #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT 16 1231 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val) 1232 { 1233 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK; 1234 } 1235 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK 0x00e00000 1236 #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT 21 1237 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val) 1238 { 1239 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK; 1240 } 1241 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK 0x1f000000 1242 #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT 24 1243 static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val) 1244 { 1245 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK; 1246 } 1247 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE 0x20000000 1248 #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE 0x40000000 1249 1250 #define REG_A2XX_RB_COLORCONTROL 0x00002202 1251 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK 0x00000007 1252 #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT 0 1253 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val) 1254 { 1255 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK; 1256 } 1257 #define A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE 0x00000008 1258 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE 0x00000010 1259 #define A2XX_RB_COLORCONTROL_BLEND_DISABLE 0x00000020 1260 #define A2XX_RB_COLORCONTROL_VOB_ENABLE 0x00000040 1261 #define A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG 0x00000080 1262 #define A2XX_RB_COLORCONTROL_ROP_CODE__MASK 0x00000f00 1263 #define A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT 8 1264 static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val) 1265 { 1266 return ((val) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK; 1267 } 1268 #define A2XX_RB_COLORCONTROL_DITHER_MODE__MASK 0x00003000 1269 #define A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT 12 1270 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) 1271 { 1272 return ((val) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK; 1273 } 1274 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK 0x0000c000 1275 #define A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT 14 1276 static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val) 1277 { 1278 return ((val) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK; 1279 } 1280 #define A2XX_RB_COLORCONTROL_PIXEL_FOG 0x00010000 1281 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK 0x03000000 1282 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT 24 1283 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val) 1284 { 1285 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK; 1286 } 1287 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK 0x0c000000 1288 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT 26 1289 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val) 1290 { 1291 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK; 1292 } 1293 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK 0x30000000 1294 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT 28 1295 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val) 1296 { 1297 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK; 1298 } 1299 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK 0xc0000000 1300 #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT 30 1301 static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val) 1302 { 1303 return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK; 1304 } 1305 1306 #define REG_A2XX_VGT_CURRENT_BIN_ID_MAX 0x00002203 1307 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK 0x00000007 1308 #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT 0 1309 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val) 1310 { 1311 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK; 1312 } 1313 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK 0x00000038 1314 #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT 3 1315 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val) 1316 { 1317 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK; 1318 } 1319 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK 0x000001c0 1320 #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT 6 1321 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val) 1322 { 1323 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK; 1324 } 1325 1326 #define REG_A2XX_PA_CL_CLIP_CNTL 0x00002204 1327 #define A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 1328 #define A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA 0x00040000 1329 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK 0x00080000 1330 #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT 19 1331 static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val) 1332 { 1333 return ((val) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK; 1334 } 1335 #define A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT 0x00100000 1336 #define A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR 0x00200000 1337 #define A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN 0x00400000 1338 #define A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN 0x00800000 1339 #define A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN 0x01000000 1340 1341 #define REG_A2XX_PA_SU_SC_MODE_CNTL 0x00002205 1342 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT 0x00000001 1343 #define A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK 0x00000002 1344 #define A2XX_PA_SU_SC_MODE_CNTL_FACE 0x00000004 1345 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK 0x00000018 1346 #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT 3 1347 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val) 1348 { 1349 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK; 1350 } 1351 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK 0x000000e0 1352 #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT 5 1353 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 1354 { 1355 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK; 1356 } 1357 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK 0x00000700 1358 #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT 8 1359 static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 1360 { 1361 return ((val) << A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK; 1362 } 1363 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE 0x00000800 1364 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE 0x00001000 1365 #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE 0x00002000 1366 #define A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE 0x00008000 1367 #define A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE 0x00010000 1368 #define A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE 0x00040000 1369 #define A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST 0x00080000 1370 #define A2XX_PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS 0x00100000 1371 #define A2XX_PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA 0x00200000 1372 #define A2XX_PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE 0x00800000 1373 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI 0x02000000 1374 #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000 1375 #define A2XX_PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS 0x10000000 1376 #define A2XX_PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS 0x20000000 1377 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE 0x40000000 1378 #define A2XX_PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE 0x80000000 1379 1380 #define REG_A2XX_PA_CL_VTE_CNTL 0x00002206 1381 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA 0x00000001 1382 #define A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA 0x00000002 1383 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA 0x00000004 1384 #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA 0x00000008 1385 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA 0x00000010 1386 #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA 0x00000020 1387 #define A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT 0x00000100 1388 #define A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT 0x00000200 1389 #define A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT 0x00000400 1390 #define A2XX_PA_CL_VTE_CNTL_PERFCOUNTER_REF 0x00000800 1391 1392 #define REG_A2XX_VGT_CURRENT_BIN_ID_MIN 0x00002207 1393 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK 0x00000007 1394 #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT 0 1395 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val) 1396 { 1397 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK; 1398 } 1399 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK 0x00000038 1400 #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT 3 1401 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val) 1402 { 1403 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK; 1404 } 1405 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK 0x000001c0 1406 #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT 6 1407 static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val) 1408 { 1409 return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK; 1410 } 1411 1412 #define REG_A2XX_RB_MODECONTROL 0x00002208 1413 #define A2XX_RB_MODECONTROL_EDRAM_MODE__MASK 0x00000007 1414 #define A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT 0 1415 static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val) 1416 { 1417 return ((val) << A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT) & A2XX_RB_MODECONTROL_EDRAM_MODE__MASK; 1418 } 1419 1420 #define REG_A2XX_A220_RB_LRZ_VSC_CONTROL 0x00002209 1421 1422 #define REG_A2XX_RB_SAMPLE_POS 0x0000220a 1423 1424 #define REG_A2XX_CLEAR_COLOR 0x0000220b 1425 #define A2XX_CLEAR_COLOR_RED__MASK 0x000000ff 1426 #define A2XX_CLEAR_COLOR_RED__SHIFT 0 1427 static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val) 1428 { 1429 return ((val) << A2XX_CLEAR_COLOR_RED__SHIFT) & A2XX_CLEAR_COLOR_RED__MASK; 1430 } 1431 #define A2XX_CLEAR_COLOR_GREEN__MASK 0x0000ff00 1432 #define A2XX_CLEAR_COLOR_GREEN__SHIFT 8 1433 static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val) 1434 { 1435 return ((val) << A2XX_CLEAR_COLOR_GREEN__SHIFT) & A2XX_CLEAR_COLOR_GREEN__MASK; 1436 } 1437 #define A2XX_CLEAR_COLOR_BLUE__MASK 0x00ff0000 1438 #define A2XX_CLEAR_COLOR_BLUE__SHIFT 16 1439 static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val) 1440 { 1441 return ((val) << A2XX_CLEAR_COLOR_BLUE__SHIFT) & A2XX_CLEAR_COLOR_BLUE__MASK; 1442 } 1443 #define A2XX_CLEAR_COLOR_ALPHA__MASK 0xff000000 1444 #define A2XX_CLEAR_COLOR_ALPHA__SHIFT 24 1445 static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val) 1446 { 1447 return ((val) << A2XX_CLEAR_COLOR_ALPHA__SHIFT) & A2XX_CLEAR_COLOR_ALPHA__MASK; 1448 } 1449 1450 #define REG_A2XX_A220_GRAS_CONTROL 0x00002210 1451 1452 #define REG_A2XX_PA_SU_POINT_SIZE 0x00002280 1453 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK 0x0000ffff 1454 #define A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT 0 1455 static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val) 1456 { 1457 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK; 1458 } 1459 #define A2XX_PA_SU_POINT_SIZE_WIDTH__MASK 0xffff0000 1460 #define A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT 16 1461 static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val) 1462 { 1463 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK; 1464 } 1465 1466 #define REG_A2XX_PA_SU_POINT_MINMAX 0x00002281 1467 #define A2XX_PA_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 1468 #define A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT 0 1469 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val) 1470 { 1471 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK; 1472 } 1473 #define A2XX_PA_SU_POINT_MINMAX_MAX__MASK 0xffff0000 1474 #define A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT 16 1475 static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val) 1476 { 1477 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK; 1478 } 1479 1480 #define REG_A2XX_PA_SU_LINE_CNTL 0x00002282 1481 #define A2XX_PA_SU_LINE_CNTL_WIDTH__MASK 0x0000ffff 1482 #define A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT 0 1483 static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val) 1484 { 1485 return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK; 1486 } 1487 1488 #define REG_A2XX_PA_SC_LINE_STIPPLE 0x00002283 1489 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK 0x0000ffff 1490 #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT 0 1491 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val) 1492 { 1493 return ((val) << A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK; 1494 } 1495 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK 0x00ff0000 1496 #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT 16 1497 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val) 1498 { 1499 return ((val) << A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK; 1500 } 1501 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK 0x10000000 1502 #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT 28 1503 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val) 1504 { 1505 return ((val) << A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK; 1506 } 1507 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK 0x60000000 1508 #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT 29 1509 static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val) 1510 { 1511 return ((val) << A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK; 1512 } 1513 1514 #define REG_A2XX_PA_SC_VIZ_QUERY 0x00002293 1515 #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ENA 0x00000001 1516 #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK 0x0000007e 1517 #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT 1 1518 static inline uint32_t A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID(uint32_t val) 1519 { 1520 return ((val) << A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT) & A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK; 1521 } 1522 #define A2XX_PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z 0x00000100 1523 1524 #define REG_A2XX_VGT_ENHANCE 0x00002294 1525 1526 #define REG_A2XX_PA_SC_LINE_CNTL 0x00002300 1527 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK 0x0000ffff 1528 #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT 0 1529 static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val) 1530 { 1531 return ((val) << A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT) & A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK; 1532 } 1533 #define A2XX_PA_SC_LINE_CNTL_USE_BRES_CNTL 0x00000100 1534 #define A2XX_PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH 0x00000200 1535 #define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL 0x00000400 1536 1537 #define REG_A2XX_PA_SC_AA_CONFIG 0x00002301 1538 #define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK 0x00000007 1539 #define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT 0 1540 static inline uint32_t A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES(uint32_t val) 1541 { 1542 return ((val) << A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT) & A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK; 1543 } 1544 #define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK 0x0001e000 1545 #define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT 13 1546 static inline uint32_t A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST(uint32_t val) 1547 { 1548 return ((val) << A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT) & A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK; 1549 } 1550 1551 #define REG_A2XX_PA_SU_VTX_CNTL 0x00002302 1552 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK 0x00000001 1553 #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT 0 1554 static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val) 1555 { 1556 return ((val) << A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT) & A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK; 1557 } 1558 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK 0x00000006 1559 #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT 1 1560 static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val) 1561 { 1562 return ((val) << A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK; 1563 } 1564 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK 0x00000380 1565 #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT 7 1566 static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val) 1567 { 1568 return ((val) << A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK; 1569 } 1570 1571 #define REG_A2XX_PA_CL_GB_VERT_CLIP_ADJ 0x00002303 1572 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK 0xffffffff 1573 #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT 0 1574 static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val) 1575 { 1576 return ((fui(val)) << A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK; 1577 } 1578 1579 #define REG_A2XX_PA_CL_GB_VERT_DISC_ADJ 0x00002304 1580 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK 0xffffffff 1581 #define A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT 0 1582 static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val) 1583 { 1584 return ((fui(val)) << A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK; 1585 } 1586 1587 #define REG_A2XX_PA_CL_GB_HORZ_CLIP_ADJ 0x00002305 1588 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK 0xffffffff 1589 #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT 0 1590 static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val) 1591 { 1592 return ((fui(val)) << A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK; 1593 } 1594 1595 #define REG_A2XX_PA_CL_GB_HORZ_DISC_ADJ 0x00002306 1596 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK 0xffffffff 1597 #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT 0 1598 static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val) 1599 { 1600 return ((fui(val)) << A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK; 1601 } 1602 1603 #define REG_A2XX_SQ_VS_CONST 0x00002307 1604 #define A2XX_SQ_VS_CONST_BASE__MASK 0x000001ff 1605 #define A2XX_SQ_VS_CONST_BASE__SHIFT 0 1606 static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val) 1607 { 1608 return ((val) << A2XX_SQ_VS_CONST_BASE__SHIFT) & A2XX_SQ_VS_CONST_BASE__MASK; 1609 } 1610 #define A2XX_SQ_VS_CONST_SIZE__MASK 0x001ff000 1611 #define A2XX_SQ_VS_CONST_SIZE__SHIFT 12 1612 static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val) 1613 { 1614 return ((val) << A2XX_SQ_VS_CONST_SIZE__SHIFT) & A2XX_SQ_VS_CONST_SIZE__MASK; 1615 } 1616 1617 #define REG_A2XX_SQ_PS_CONST 0x00002308 1618 #define A2XX_SQ_PS_CONST_BASE__MASK 0x000001ff 1619 #define A2XX_SQ_PS_CONST_BASE__SHIFT 0 1620 static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val) 1621 { 1622 return ((val) << A2XX_SQ_PS_CONST_BASE__SHIFT) & A2XX_SQ_PS_CONST_BASE__MASK; 1623 } 1624 #define A2XX_SQ_PS_CONST_SIZE__MASK 0x001ff000 1625 #define A2XX_SQ_PS_CONST_SIZE__SHIFT 12 1626 static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val) 1627 { 1628 return ((val) << A2XX_SQ_PS_CONST_SIZE__SHIFT) & A2XX_SQ_PS_CONST_SIZE__MASK; 1629 } 1630 1631 #define REG_A2XX_SQ_DEBUG_MISC_0 0x00002309 1632 1633 #define REG_A2XX_SQ_DEBUG_MISC_1 0x0000230a 1634 1635 #define REG_A2XX_PA_SC_AA_MASK 0x00002312 1636 1637 #define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL 0x00002316 1638 #define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK 0x00000007 1639 #define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT 0 1640 static inline uint32_t A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH(uint32_t val) 1641 { 1642 return ((val) << A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT) & A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK; 1643 } 1644 1645 #define REG_A2XX_VGT_OUT_DEALLOC_CNTL 0x00002317 1646 #define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK 0x00000003 1647 #define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT 0 1648 static inline uint32_t A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST(uint32_t val) 1649 { 1650 return ((val) << A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT) & A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK; 1651 } 1652 1653 #define REG_A2XX_RB_COPY_CONTROL 0x00002318 1654 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK 0x00000007 1655 #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT 0 1656 static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val) 1657 { 1658 return ((val) << A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT) & A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK; 1659 } 1660 #define A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE 0x00000008 1661 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK 0x000000f0 1662 #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT 4 1663 static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val) 1664 { 1665 return ((val) << A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT) & A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK; 1666 } 1667 1668 #define REG_A2XX_RB_COPY_DEST_BASE 0x00002319 1669 1670 #define REG_A2XX_RB_COPY_DEST_PITCH 0x0000231a 1671 #define A2XX_RB_COPY_DEST_PITCH__MASK 0xffffffff 1672 #define A2XX_RB_COPY_DEST_PITCH__SHIFT 0 1673 static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val) 1674 { 1675 return ((val >> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK; 1676 } 1677 1678 #define REG_A2XX_RB_COPY_DEST_INFO 0x0000231b 1679 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK 0x00000007 1680 #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT 0 1681 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val) 1682 { 1683 return ((val) << A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT) & A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK; 1684 } 1685 #define A2XX_RB_COPY_DEST_INFO_LINEAR 0x00000008 1686 #define A2XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000f0 1687 #define A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 4 1688 static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val) 1689 { 1690 return ((val) << A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A2XX_RB_COPY_DEST_INFO_FORMAT__MASK; 1691 } 1692 #define A2XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 1693 #define A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 1694 static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val) 1695 { 1696 return ((val) << A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A2XX_RB_COPY_DEST_INFO_SWAP__MASK; 1697 } 1698 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 1699 #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 1700 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 1701 { 1702 return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 1703 } 1704 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK 0x00003000 1705 #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT 12 1706 static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val) 1707 { 1708 return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK; 1709 } 1710 #define A2XX_RB_COPY_DEST_INFO_WRITE_RED 0x00004000 1711 #define A2XX_RB_COPY_DEST_INFO_WRITE_GREEN 0x00008000 1712 #define A2XX_RB_COPY_DEST_INFO_WRITE_BLUE 0x00010000 1713 #define A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA 0x00020000 1714 1715 #define REG_A2XX_RB_COPY_DEST_OFFSET 0x0000231c 1716 #define A2XX_RB_COPY_DEST_OFFSET_X__MASK 0x00001fff 1717 #define A2XX_RB_COPY_DEST_OFFSET_X__SHIFT 0 1718 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val) 1719 { 1720 return ((val) << A2XX_RB_COPY_DEST_OFFSET_X__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_X__MASK; 1721 } 1722 #define A2XX_RB_COPY_DEST_OFFSET_Y__MASK 0x03ffe000 1723 #define A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT 13 1724 static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val) 1725 { 1726 return ((val) << A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_Y__MASK; 1727 } 1728 1729 #define REG_A2XX_RB_DEPTH_CLEAR 0x0000231d 1730 1731 #define REG_A2XX_RB_SAMPLE_COUNT_CTL 0x00002324 1732 1733 #define REG_A2XX_RB_COLOR_DEST_MASK 0x00002326 1734 1735 #define REG_A2XX_A225_GRAS_UCP0X 0x00002340 1736 1737 #define REG_A2XX_A225_GRAS_UCP5W 0x00002357 1738 1739 #define REG_A2XX_A225_GRAS_UCP_ENABLED 0x00002360 1740 1741 #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE 0x00002380 1742 1743 #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET 0x00002383 1744 1745 #define REG_A2XX_SQ_CONSTANT_0 0x00004000 1746 1747 #define REG_A2XX_SQ_FETCH_0 0x00004800 1748 1749 #define REG_A2XX_SQ_CF_BOOLEANS 0x00004900 1750 1751 #define REG_A2XX_SQ_CF_LOOP 0x00004908 1752 1753 #define REG_A2XX_COHER_SIZE_PM4 0x00000a29 1754 1755 #define REG_A2XX_COHER_BASE_PM4 0x00000a2a 1756 1757 #define REG_A2XX_COHER_STATUS_PM4 0x00000a2b 1758 1759 #define REG_A2XX_SQ_TEX_0 0x00000000 1760 #define A2XX_SQ_TEX_0_CLAMP_X__MASK 0x00001c00 1761 #define A2XX_SQ_TEX_0_CLAMP_X__SHIFT 10 1762 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val) 1763 { 1764 return ((val) << A2XX_SQ_TEX_0_CLAMP_X__SHIFT) & A2XX_SQ_TEX_0_CLAMP_X__MASK; 1765 } 1766 #define A2XX_SQ_TEX_0_CLAMP_Y__MASK 0x0000e000 1767 #define A2XX_SQ_TEX_0_CLAMP_Y__SHIFT 13 1768 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val) 1769 { 1770 return ((val) << A2XX_SQ_TEX_0_CLAMP_Y__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Y__MASK; 1771 } 1772 #define A2XX_SQ_TEX_0_CLAMP_Z__MASK 0x00070000 1773 #define A2XX_SQ_TEX_0_CLAMP_Z__SHIFT 16 1774 static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val) 1775 { 1776 return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK; 1777 } 1778 #define A2XX_SQ_TEX_0_PITCH__MASK 0xffc00000 1779 #define A2XX_SQ_TEX_0_PITCH__SHIFT 22 1780 static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val) 1781 { 1782 return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK; 1783 } 1784 1785 #define REG_A2XX_SQ_TEX_1 0x00000001 1786 1787 #define REG_A2XX_SQ_TEX_2 0x00000002 1788 #define A2XX_SQ_TEX_2_WIDTH__MASK 0x00001fff 1789 #define A2XX_SQ_TEX_2_WIDTH__SHIFT 0 1790 static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val) 1791 { 1792 return ((val) << A2XX_SQ_TEX_2_WIDTH__SHIFT) & A2XX_SQ_TEX_2_WIDTH__MASK; 1793 } 1794 #define A2XX_SQ_TEX_2_HEIGHT__MASK 0x03ffe000 1795 #define A2XX_SQ_TEX_2_HEIGHT__SHIFT 13 1796 static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val) 1797 { 1798 return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK; 1799 } 1800 1801 #define REG_A2XX_SQ_TEX_3 0x00000003 1802 #define A2XX_SQ_TEX_3_SWIZ_X__MASK 0x0000000e 1803 #define A2XX_SQ_TEX_3_SWIZ_X__SHIFT 1 1804 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val) 1805 { 1806 return ((val) << A2XX_SQ_TEX_3_SWIZ_X__SHIFT) & A2XX_SQ_TEX_3_SWIZ_X__MASK; 1807 } 1808 #define A2XX_SQ_TEX_3_SWIZ_Y__MASK 0x00000070 1809 #define A2XX_SQ_TEX_3_SWIZ_Y__SHIFT 4 1810 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val) 1811 { 1812 return ((val) << A2XX_SQ_TEX_3_SWIZ_Y__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Y__MASK; 1813 } 1814 #define A2XX_SQ_TEX_3_SWIZ_Z__MASK 0x00000380 1815 #define A2XX_SQ_TEX_3_SWIZ_Z__SHIFT 7 1816 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val) 1817 { 1818 return ((val) << A2XX_SQ_TEX_3_SWIZ_Z__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Z__MASK; 1819 } 1820 #define A2XX_SQ_TEX_3_SWIZ_W__MASK 0x00001c00 1821 #define A2XX_SQ_TEX_3_SWIZ_W__SHIFT 10 1822 static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val) 1823 { 1824 return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK; 1825 } 1826 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK 0x00180000 1827 #define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT 19 1828 static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val) 1829 { 1830 return ((val) << A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK; 1831 } 1832 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK 0x00600000 1833 #define A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT 21 1834 static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val) 1835 { 1836 return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK; 1837 } 1838 1839 1840 #endif /* A2XX_XML */ 1841