1902e6eb8SRob Clark #ifndef A2XX_XML 2902e6eb8SRob Clark #define A2XX_XML 3902e6eb8SRob Clark 4902e6eb8SRob Clark /* Autogenerated file, DO NOT EDIT manually! 5902e6eb8SRob Clark 6902e6eb8SRob Clark This file was generated by the rules-ng-ng headergen tool in this git repository: 722ba8b6bSRob Clark http://github.com/freedreno/envytools/ 822ba8b6bSRob Clark git clone https://github.com/freedreno/envytools.git 9902e6eb8SRob Clark 10902e6eb8SRob Clark The rules-ng-ng source files this header was generated from are: 112d756322SRob Clark - /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13) 122d756322SRob Clark - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13) 13ccdf7e28SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03) 14ccdf7e28SRob Clark - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14201 bytes, from 2018-12-02 17:29:54) 15ccdf7e28SRob Clark - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-02 17:29:54) 162d756322SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13) 172d756322SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13) 18ccdf7e28SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54) 19ccdf7e28SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54) 20a69c5ed2SRob Clark - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07) 212d756322SRob Clark - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13) 22902e6eb8SRob Clark 232d756322SRob Clark Copyright (C) 2013-2018 by the following authors: 24902e6eb8SRob Clark - Rob Clark <robdclark@gmail.com> (robclark) 25a2272e48SRob Clark - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 26902e6eb8SRob Clark 27902e6eb8SRob Clark Permission is hereby granted, free of charge, to any person obtaining 28902e6eb8SRob Clark a copy of this software and associated documentation files (the 29902e6eb8SRob Clark "Software"), to deal in the Software without restriction, including 30902e6eb8SRob Clark without limitation the rights to use, copy, modify, merge, publish, 31902e6eb8SRob Clark distribute, sublicense, and/or sell copies of the Software, and to 32902e6eb8SRob Clark permit persons to whom the Software is furnished to do so, subject to 33902e6eb8SRob Clark the following conditions: 34902e6eb8SRob Clark 35902e6eb8SRob Clark The above copyright notice and this permission notice (including the 36902e6eb8SRob Clark next paragraph) shall be included in all copies or substantial 37902e6eb8SRob Clark portions of the Software. 38902e6eb8SRob Clark 39902e6eb8SRob Clark THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 40902e6eb8SRob Clark EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 41902e6eb8SRob Clark MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 42902e6eb8SRob Clark IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 43902e6eb8SRob Clark LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 44902e6eb8SRob Clark OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 45902e6eb8SRob Clark WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 46902e6eb8SRob Clark */ 47902e6eb8SRob Clark 48902e6eb8SRob Clark 49902e6eb8SRob Clark enum a2xx_rb_dither_type { 50902e6eb8SRob Clark DITHER_PIXEL = 0, 51902e6eb8SRob Clark DITHER_SUBPIXEL = 1, 52902e6eb8SRob Clark }; 53902e6eb8SRob Clark 54902e6eb8SRob Clark enum a2xx_colorformatx { 55902e6eb8SRob Clark COLORX_4_4_4_4 = 0, 56902e6eb8SRob Clark COLORX_1_5_5_5 = 1, 57902e6eb8SRob Clark COLORX_5_6_5 = 2, 58902e6eb8SRob Clark COLORX_8 = 3, 59902e6eb8SRob Clark COLORX_8_8 = 4, 60902e6eb8SRob Clark COLORX_8_8_8_8 = 5, 61902e6eb8SRob Clark COLORX_S8_8_8_8 = 6, 62902e6eb8SRob Clark COLORX_16_FLOAT = 7, 63902e6eb8SRob Clark COLORX_16_16_FLOAT = 8, 64902e6eb8SRob Clark COLORX_16_16_16_16_FLOAT = 9, 65902e6eb8SRob Clark COLORX_32_FLOAT = 10, 66902e6eb8SRob Clark COLORX_32_32_FLOAT = 11, 67902e6eb8SRob Clark COLORX_32_32_32_32_FLOAT = 12, 68902e6eb8SRob Clark COLORX_2_3_3 = 13, 69902e6eb8SRob Clark COLORX_8_8_8 = 14, 70902e6eb8SRob Clark }; 71902e6eb8SRob Clark 72902e6eb8SRob Clark enum a2xx_sq_surfaceformat { 73902e6eb8SRob Clark FMT_1_REVERSE = 0, 74902e6eb8SRob Clark FMT_1 = 1, 75902e6eb8SRob Clark FMT_8 = 2, 76902e6eb8SRob Clark FMT_1_5_5_5 = 3, 77902e6eb8SRob Clark FMT_5_6_5 = 4, 78902e6eb8SRob Clark FMT_6_5_5 = 5, 79902e6eb8SRob Clark FMT_8_8_8_8 = 6, 80902e6eb8SRob Clark FMT_2_10_10_10 = 7, 81902e6eb8SRob Clark FMT_8_A = 8, 82902e6eb8SRob Clark FMT_8_B = 9, 83902e6eb8SRob Clark FMT_8_8 = 10, 84902e6eb8SRob Clark FMT_Cr_Y1_Cb_Y0 = 11, 85902e6eb8SRob Clark FMT_Y1_Cr_Y0_Cb = 12, 86902e6eb8SRob Clark FMT_5_5_5_1 = 13, 87902e6eb8SRob Clark FMT_8_8_8_8_A = 14, 88902e6eb8SRob Clark FMT_4_4_4_4 = 15, 892d756322SRob Clark FMT_8_8_8 = 16, 90902e6eb8SRob Clark FMT_DXT1 = 18, 91902e6eb8SRob Clark FMT_DXT2_3 = 19, 92902e6eb8SRob Clark FMT_DXT4_5 = 20, 932d756322SRob Clark FMT_10_10_10_2 = 21, 94902e6eb8SRob Clark FMT_24_8 = 22, 95902e6eb8SRob Clark FMT_16 = 24, 96902e6eb8SRob Clark FMT_16_16 = 25, 97902e6eb8SRob Clark FMT_16_16_16_16 = 26, 98902e6eb8SRob Clark FMT_16_EXPAND = 27, 99902e6eb8SRob Clark FMT_16_16_EXPAND = 28, 100902e6eb8SRob Clark FMT_16_16_16_16_EXPAND = 29, 101902e6eb8SRob Clark FMT_16_FLOAT = 30, 102902e6eb8SRob Clark FMT_16_16_FLOAT = 31, 103902e6eb8SRob Clark FMT_16_16_16_16_FLOAT = 32, 104902e6eb8SRob Clark FMT_32 = 33, 105902e6eb8SRob Clark FMT_32_32 = 34, 106902e6eb8SRob Clark FMT_32_32_32_32 = 35, 107902e6eb8SRob Clark FMT_32_FLOAT = 36, 108902e6eb8SRob Clark FMT_32_32_FLOAT = 37, 109902e6eb8SRob Clark FMT_32_32_32_32_FLOAT = 38, 1102d756322SRob Clark FMT_ATI_TC_RGB = 39, 1112d756322SRob Clark FMT_ATI_TC_RGBA = 40, 1122d756322SRob Clark FMT_ATI_TC_555_565_RGB = 41, 1132d756322SRob Clark FMT_ATI_TC_555_565_RGBA = 42, 1142d756322SRob Clark FMT_ATI_TC_RGBA_INTERP = 43, 1152d756322SRob Clark FMT_ATI_TC_555_565_RGBA_INTERP = 44, 1162d756322SRob Clark FMT_ETC1_RGBA_INTERP = 46, 1172d756322SRob Clark FMT_ETC1_RGB = 47, 1182d756322SRob Clark FMT_ETC1_RGBA = 48, 119902e6eb8SRob Clark FMT_DXN = 49, 1202d756322SRob Clark FMT_2_3_3 = 51, 121902e6eb8SRob Clark FMT_2_10_10_10_AS_16_16_16_16 = 54, 1222d756322SRob Clark FMT_10_10_10_2_AS_16_16_16_16 = 55, 123902e6eb8SRob Clark FMT_32_32_32_FLOAT = 57, 124902e6eb8SRob Clark FMT_DXT3A = 58, 125902e6eb8SRob Clark FMT_DXT5A = 59, 126902e6eb8SRob Clark FMT_CTX1 = 60, 127902e6eb8SRob Clark }; 128902e6eb8SRob Clark 129902e6eb8SRob Clark enum a2xx_sq_ps_vtx_mode { 130902e6eb8SRob Clark POSITION_1_VECTOR = 0, 131902e6eb8SRob Clark POSITION_2_VECTORS_UNUSED = 1, 132902e6eb8SRob Clark POSITION_2_VECTORS_SPRITE = 2, 133902e6eb8SRob Clark POSITION_2_VECTORS_EDGE = 3, 134902e6eb8SRob Clark POSITION_2_VECTORS_KILL = 4, 135902e6eb8SRob Clark POSITION_2_VECTORS_SPRITE_KILL = 5, 136902e6eb8SRob Clark POSITION_2_VECTORS_EDGE_KILL = 6, 137902e6eb8SRob Clark MULTIPASS = 7, 138902e6eb8SRob Clark }; 139902e6eb8SRob Clark 140902e6eb8SRob Clark enum a2xx_sq_sample_cntl { 141902e6eb8SRob Clark CENTROIDS_ONLY = 0, 142902e6eb8SRob Clark CENTERS_ONLY = 1, 143902e6eb8SRob Clark CENTROIDS_AND_CENTERS = 2, 144902e6eb8SRob Clark }; 145902e6eb8SRob Clark 146902e6eb8SRob Clark enum a2xx_dx_clip_space { 147902e6eb8SRob Clark DXCLIP_OPENGL = 0, 148902e6eb8SRob Clark DXCLIP_DIRECTX = 1, 149902e6eb8SRob Clark }; 150902e6eb8SRob Clark 151902e6eb8SRob Clark enum a2xx_pa_su_sc_polymode { 152902e6eb8SRob Clark POLY_DISABLED = 0, 153902e6eb8SRob Clark POLY_DUALMODE = 1, 154902e6eb8SRob Clark }; 155902e6eb8SRob Clark 156902e6eb8SRob Clark enum a2xx_rb_edram_mode { 157902e6eb8SRob Clark EDRAM_NOP = 0, 158902e6eb8SRob Clark COLOR_DEPTH = 4, 159902e6eb8SRob Clark DEPTH_ONLY = 5, 160902e6eb8SRob Clark EDRAM_COPY = 6, 161902e6eb8SRob Clark }; 162902e6eb8SRob Clark 163902e6eb8SRob Clark enum a2xx_pa_sc_pattern_bit_order { 164902e6eb8SRob Clark LITTLE = 0, 165902e6eb8SRob Clark BIG = 1, 166902e6eb8SRob Clark }; 167902e6eb8SRob Clark 168902e6eb8SRob Clark enum a2xx_pa_sc_auto_reset_cntl { 169902e6eb8SRob Clark NEVER = 0, 170902e6eb8SRob Clark EACH_PRIMITIVE = 1, 171902e6eb8SRob Clark EACH_PACKET = 2, 172902e6eb8SRob Clark }; 173902e6eb8SRob Clark 174902e6eb8SRob Clark enum a2xx_pa_pixcenter { 175902e6eb8SRob Clark PIXCENTER_D3D = 0, 176902e6eb8SRob Clark PIXCENTER_OGL = 1, 177902e6eb8SRob Clark }; 178902e6eb8SRob Clark 179902e6eb8SRob Clark enum a2xx_pa_roundmode { 180902e6eb8SRob Clark TRUNCATE = 0, 181902e6eb8SRob Clark ROUND = 1, 182902e6eb8SRob Clark ROUNDTOEVEN = 2, 183902e6eb8SRob Clark ROUNDTOODD = 3, 184902e6eb8SRob Clark }; 185902e6eb8SRob Clark 186902e6eb8SRob Clark enum a2xx_pa_quantmode { 187902e6eb8SRob Clark ONE_SIXTEENTH = 0, 188902e6eb8SRob Clark ONE_EIGTH = 1, 189902e6eb8SRob Clark ONE_QUARTER = 2, 190902e6eb8SRob Clark ONE_HALF = 3, 191902e6eb8SRob Clark ONE = 4, 192902e6eb8SRob Clark }; 193902e6eb8SRob Clark 194902e6eb8SRob Clark enum a2xx_rb_copy_sample_select { 195902e6eb8SRob Clark SAMPLE_0 = 0, 196902e6eb8SRob Clark SAMPLE_1 = 1, 197902e6eb8SRob Clark SAMPLE_2 = 2, 198902e6eb8SRob Clark SAMPLE_3 = 3, 199902e6eb8SRob Clark SAMPLE_01 = 4, 200902e6eb8SRob Clark SAMPLE_23 = 5, 201902e6eb8SRob Clark SAMPLE_0123 = 6, 202902e6eb8SRob Clark }; 203902e6eb8SRob Clark 20489301471SRob Clark enum a2xx_rb_blend_opcode { 205a26ae754SRob Clark BLEND2_DST_PLUS_SRC = 0, 206a26ae754SRob Clark BLEND2_SRC_MINUS_DST = 1, 207a26ae754SRob Clark BLEND2_MIN_DST_SRC = 2, 208a26ae754SRob Clark BLEND2_MAX_DST_SRC = 3, 209a26ae754SRob Clark BLEND2_DST_MINUS_SRC = 4, 210a26ae754SRob Clark BLEND2_DST_PLUS_SRC_BIAS = 5, 21189301471SRob Clark }; 21289301471SRob Clark 213facb4f4eSRob Clark enum adreno_mmu_clnt_beh { 214facb4f4eSRob Clark BEH_NEVR = 0, 215facb4f4eSRob Clark BEH_TRAN_RNG = 1, 216facb4f4eSRob Clark BEH_TRAN_FLT = 2, 217facb4f4eSRob Clark }; 218facb4f4eSRob Clark 219902e6eb8SRob Clark enum sq_tex_clamp { 220902e6eb8SRob Clark SQ_TEX_WRAP = 0, 221902e6eb8SRob Clark SQ_TEX_MIRROR = 1, 222902e6eb8SRob Clark SQ_TEX_CLAMP_LAST_TEXEL = 2, 223902e6eb8SRob Clark SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3, 224902e6eb8SRob Clark SQ_TEX_CLAMP_HALF_BORDER = 4, 225902e6eb8SRob Clark SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5, 226902e6eb8SRob Clark SQ_TEX_CLAMP_BORDER = 6, 227902e6eb8SRob Clark SQ_TEX_MIRROR_ONCE_BORDER = 7, 228902e6eb8SRob Clark }; 229902e6eb8SRob Clark 230902e6eb8SRob Clark enum sq_tex_swiz { 231902e6eb8SRob Clark SQ_TEX_X = 0, 232902e6eb8SRob Clark SQ_TEX_Y = 1, 233902e6eb8SRob Clark SQ_TEX_Z = 2, 234902e6eb8SRob Clark SQ_TEX_W = 3, 235902e6eb8SRob Clark SQ_TEX_ZERO = 4, 236902e6eb8SRob Clark SQ_TEX_ONE = 5, 237902e6eb8SRob Clark }; 238902e6eb8SRob Clark 239902e6eb8SRob Clark enum sq_tex_filter { 240902e6eb8SRob Clark SQ_TEX_FILTER_POINT = 0, 241902e6eb8SRob Clark SQ_TEX_FILTER_BILINEAR = 1, 242ccdf7e28SRob Clark SQ_TEX_FILTER_BASEMAP = 2, 243ccdf7e28SRob Clark SQ_TEX_FILTER_USE_FETCH_CONST = 3, 244ccdf7e28SRob Clark }; 245ccdf7e28SRob Clark 246ccdf7e28SRob Clark enum sq_tex_aniso_filter { 247ccdf7e28SRob Clark SQ_TEX_ANISO_FILTER_DISABLED = 0, 248ccdf7e28SRob Clark SQ_TEX_ANISO_FILTER_MAX_1_1 = 1, 249ccdf7e28SRob Clark SQ_TEX_ANISO_FILTER_MAX_2_1 = 2, 250ccdf7e28SRob Clark SQ_TEX_ANISO_FILTER_MAX_4_1 = 3, 251ccdf7e28SRob Clark SQ_TEX_ANISO_FILTER_MAX_8_1 = 4, 252ccdf7e28SRob Clark SQ_TEX_ANISO_FILTER_MAX_16_1 = 5, 253ccdf7e28SRob Clark SQ_TEX_ANISO_FILTER_USE_FETCH_CONST = 7, 254ccdf7e28SRob Clark }; 255ccdf7e28SRob Clark 256ccdf7e28SRob Clark enum sq_tex_dimension { 257ccdf7e28SRob Clark SQ_TEX_DIMENSION_1D = 0, 258ccdf7e28SRob Clark SQ_TEX_DIMENSION_2D = 1, 259ccdf7e28SRob Clark SQ_TEX_DIMENSION_3D = 2, 260ccdf7e28SRob Clark SQ_TEX_DIMENSION_CUBE = 3, 261ccdf7e28SRob Clark }; 262ccdf7e28SRob Clark 263ccdf7e28SRob Clark enum sq_tex_border_color { 264ccdf7e28SRob Clark SQ_TEX_BORDER_COLOR_BLACK = 0, 265ccdf7e28SRob Clark SQ_TEX_BORDER_COLOR_WHITE = 1, 266ccdf7e28SRob Clark SQ_TEX_BORDER_COLOR_ACBYCR_BLACK = 2, 267ccdf7e28SRob Clark SQ_TEX_BORDER_COLOR_ACBCRY_BLACK = 3, 268ccdf7e28SRob Clark }; 269ccdf7e28SRob Clark 270ccdf7e28SRob Clark enum sq_tex_sign { 271ccdf7e28SRob Clark SQ_TEX_SIGN_UNISIGNED = 0, 272ccdf7e28SRob Clark SQ_TEX_SIGN_SIGNED = 1, 273ccdf7e28SRob Clark SQ_TEX_SIGN_UNISIGNED_BIASED = 2, 274ccdf7e28SRob Clark SQ_TEX_SIGN_GAMMA = 3, 275ccdf7e28SRob Clark }; 276ccdf7e28SRob Clark 277ccdf7e28SRob Clark enum sq_tex_endian { 278ccdf7e28SRob Clark SQ_TEX_ENDIAN_NONE = 0, 279ccdf7e28SRob Clark SQ_TEX_ENDIAN_8IN16 = 1, 280ccdf7e28SRob Clark SQ_TEX_ENDIAN_8IN32 = 2, 281ccdf7e28SRob Clark SQ_TEX_ENDIAN_16IN32 = 3, 282ccdf7e28SRob Clark }; 283ccdf7e28SRob Clark 284ccdf7e28SRob Clark enum sq_tex_clamp_policy { 285ccdf7e28SRob Clark SQ_TEX_CLAMP_POLICY_D3D = 0, 286ccdf7e28SRob Clark SQ_TEX_CLAMP_POLICY_OGL = 1, 287ccdf7e28SRob Clark }; 288ccdf7e28SRob Clark 289ccdf7e28SRob Clark enum sq_tex_num_format { 290ccdf7e28SRob Clark SQ_TEX_NUM_FORMAT_FRAC = 0, 291ccdf7e28SRob Clark SQ_TEX_NUM_FORMAT_INT = 1, 292ccdf7e28SRob Clark }; 293ccdf7e28SRob Clark 294ccdf7e28SRob Clark enum sq_tex_type { 295ccdf7e28SRob Clark SQ_TEX_TYPE_0 = 0, 296ccdf7e28SRob Clark SQ_TEX_TYPE_1 = 1, 297ccdf7e28SRob Clark SQ_TEX_TYPE_2 = 2, 298ccdf7e28SRob Clark SQ_TEX_TYPE_3 = 3, 299902e6eb8SRob Clark }; 300902e6eb8SRob Clark 301902e6eb8SRob Clark #define REG_A2XX_RBBM_PATCH_RELEASE 0x00000001 302902e6eb8SRob Clark 303902e6eb8SRob Clark #define REG_A2XX_RBBM_CNTL 0x0000003b 304902e6eb8SRob Clark 305902e6eb8SRob Clark #define REG_A2XX_RBBM_SOFT_RESET 0x0000003c 306902e6eb8SRob Clark 307902e6eb8SRob Clark #define REG_A2XX_CP_PFP_UCODE_ADDR 0x000000c0 308902e6eb8SRob Clark 309902e6eb8SRob Clark #define REG_A2XX_CP_PFP_UCODE_DATA 0x000000c1 310902e6eb8SRob Clark 311facb4f4eSRob Clark #define REG_A2XX_MH_MMU_CONFIG 0x00000040 312facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_MMU_ENABLE 0x00000001 313facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE 0x00000002 314facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK 0x00000030 315facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT 4 316facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 317facb4f4eSRob Clark { 318facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK; 319facb4f4eSRob Clark } 320facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK 0x000000c0 321facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT 6 322facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 323facb4f4eSRob Clark { 324facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK; 325facb4f4eSRob Clark } 326facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK 0x00000300 327facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT 8 328facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 329facb4f4eSRob Clark { 330facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK; 331facb4f4eSRob Clark } 332facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK 0x00000c00 333facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT 10 334facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 335facb4f4eSRob Clark { 336facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK; 337facb4f4eSRob Clark } 338facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK 0x00003000 339facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT 12 340facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 341facb4f4eSRob Clark { 342facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK; 343facb4f4eSRob Clark } 344facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK 0x0000c000 345facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT 14 346facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 347facb4f4eSRob Clark { 348facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK; 349facb4f4eSRob Clark } 350facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK 0x00030000 351facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT 16 352facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 353facb4f4eSRob Clark { 354facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK; 355facb4f4eSRob Clark } 356facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK 0x000c0000 357facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT 18 358facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 359facb4f4eSRob Clark { 360facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK; 361facb4f4eSRob Clark } 362facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK 0x00300000 363facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT 20 364facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 365facb4f4eSRob Clark { 366facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK; 367facb4f4eSRob Clark } 368facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK 0x00c00000 369facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT 22 370facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 371facb4f4eSRob Clark { 372facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK; 373facb4f4eSRob Clark } 374facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK 0x03000000 375facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT 24 376facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 377facb4f4eSRob Clark { 378facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK; 379facb4f4eSRob Clark } 380facb4f4eSRob Clark 381facb4f4eSRob Clark #define REG_A2XX_MH_MMU_VA_RANGE 0x00000041 382ccdf7e28SRob Clark #define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK 0x00000fff 383ccdf7e28SRob Clark #define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT 0 384ccdf7e28SRob Clark static inline uint32_t A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS(uint32_t val) 385ccdf7e28SRob Clark { 386ccdf7e28SRob Clark return ((val) << A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT) & A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK; 387ccdf7e28SRob Clark } 388ccdf7e28SRob Clark #define A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK 0xfffff000 389ccdf7e28SRob Clark #define A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT 12 390ccdf7e28SRob Clark static inline uint32_t A2XX_MH_MMU_VA_RANGE_VA_BASE(uint32_t val) 391ccdf7e28SRob Clark { 392ccdf7e28SRob Clark return ((val) << A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT) & A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK; 393ccdf7e28SRob Clark } 394facb4f4eSRob Clark 395facb4f4eSRob Clark #define REG_A2XX_MH_MMU_PT_BASE 0x00000042 396facb4f4eSRob Clark 397facb4f4eSRob Clark #define REG_A2XX_MH_MMU_PAGE_FAULT 0x00000043 398facb4f4eSRob Clark 399facb4f4eSRob Clark #define REG_A2XX_MH_MMU_TRAN_ERROR 0x00000044 400facb4f4eSRob Clark 401facb4f4eSRob Clark #define REG_A2XX_MH_MMU_INVALIDATE 0x00000045 402ccdf7e28SRob Clark #define A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL 0x00000001 403ccdf7e28SRob Clark #define A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC 0x00000002 404facb4f4eSRob Clark 405facb4f4eSRob Clark #define REG_A2XX_MH_MMU_MPU_BASE 0x00000046 406facb4f4eSRob Clark 407facb4f4eSRob Clark #define REG_A2XX_MH_MMU_MPU_END 0x00000047 408facb4f4eSRob Clark 409facb4f4eSRob Clark #define REG_A2XX_NQWAIT_UNTIL 0x00000394 410facb4f4eSRob Clark 411902e6eb8SRob Clark #define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395 412902e6eb8SRob Clark 413902e6eb8SRob Clark #define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397 414902e6eb8SRob Clark 415902e6eb8SRob Clark #define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x00000398 416902e6eb8SRob Clark 417902e6eb8SRob Clark #define REG_A2XX_RBBM_DEBUG 0x0000039b 418902e6eb8SRob Clark 419902e6eb8SRob Clark #define REG_A2XX_RBBM_PM_OVERRIDE1 0x0000039c 42052260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE 0x00000001 42152260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE 0x00000002 42252260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE 0x00000004 42352260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE 0x00000008 42452260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE 0x00000010 42552260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE 0x00000020 42652260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE 0x00000040 42752260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE 0x00000080 42852260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE 0x00000100 42952260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE 0x00000200 43052260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE 0x00000400 43152260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE 0x00000800 43252260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE 0x00001000 43352260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE 0x00002000 43452260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE 0x00004000 43552260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE 0x00008000 43652260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE 0x00010000 43752260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE 0x00020000 43852260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE 0x00040000 43952260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE 0x00080000 44052260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE 0x00100000 44152260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE 0x00200000 44252260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE 0x00400000 44352260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE 0x00800000 44452260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE 0x01000000 44552260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE 0x02000000 44652260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE 0x04000000 44752260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE 0x08000000 44852260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE 0x10000000 44952260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE 0x20000000 45052260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE 0x40000000 45152260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE 0x80000000 452902e6eb8SRob Clark 453902e6eb8SRob Clark #define REG_A2XX_RBBM_PM_OVERRIDE2 0x0000039d 454902e6eb8SRob Clark 455902e6eb8SRob Clark #define REG_A2XX_RBBM_DEBUG_OUT 0x000003a0 456902e6eb8SRob Clark 457902e6eb8SRob Clark #define REG_A2XX_RBBM_DEBUG_CNTL 0x000003a1 458902e6eb8SRob Clark 459902e6eb8SRob Clark #define REG_A2XX_RBBM_READ_ERROR 0x000003b3 460902e6eb8SRob Clark 461902e6eb8SRob Clark #define REG_A2XX_RBBM_INT_CNTL 0x000003b4 462ccdf7e28SRob Clark #define A2XX_RBBM_INT_CNTL_RDERR_INT_MASK 0x00000001 463ccdf7e28SRob Clark #define A2XX_RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK 0x00000002 464ccdf7e28SRob Clark #define A2XX_RBBM_INT_CNTL_GUI_IDLE_INT_MASK 0x00080000 465902e6eb8SRob Clark 466902e6eb8SRob Clark #define REG_A2XX_RBBM_INT_STATUS 0x000003b5 467902e6eb8SRob Clark 468902e6eb8SRob Clark #define REG_A2XX_RBBM_INT_ACK 0x000003b6 469902e6eb8SRob Clark 470902e6eb8SRob Clark #define REG_A2XX_MASTER_INT_SIGNAL 0x000003b7 471ccdf7e28SRob Clark #define A2XX_MASTER_INT_SIGNAL_MH_INT_STAT 0x00000020 472ccdf7e28SRob Clark #define A2XX_MASTER_INT_SIGNAL_SQ_INT_STAT 0x04000000 473ccdf7e28SRob Clark #define A2XX_MASTER_INT_SIGNAL_CP_INT_STAT 0x40000000 474ccdf7e28SRob Clark #define A2XX_MASTER_INT_SIGNAL_RBBM_INT_STAT 0x80000000 475902e6eb8SRob Clark 476902e6eb8SRob Clark #define REG_A2XX_RBBM_PERIPHID1 0x000003f9 477902e6eb8SRob Clark 478902e6eb8SRob Clark #define REG_A2XX_RBBM_PERIPHID2 0x000003fa 479902e6eb8SRob Clark 480902e6eb8SRob Clark #define REG_A2XX_CP_PERFMON_CNTL 0x00000444 481902e6eb8SRob Clark 482902e6eb8SRob Clark #define REG_A2XX_CP_PERFCOUNTER_SELECT 0x00000445 483902e6eb8SRob Clark 484902e6eb8SRob Clark #define REG_A2XX_CP_PERFCOUNTER_LO 0x00000446 485902e6eb8SRob Clark 486902e6eb8SRob Clark #define REG_A2XX_CP_PERFCOUNTER_HI 0x00000447 487902e6eb8SRob Clark 488902e6eb8SRob Clark #define REG_A2XX_RBBM_STATUS 0x000005d0 489902e6eb8SRob Clark #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK 0x0000001f 490902e6eb8SRob Clark #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT 0 491902e6eb8SRob Clark static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val) 492902e6eb8SRob Clark { 493902e6eb8SRob Clark return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK; 494902e6eb8SRob Clark } 495902e6eb8SRob Clark #define A2XX_RBBM_STATUS_TC_BUSY 0x00000020 496902e6eb8SRob Clark #define A2XX_RBBM_STATUS_HIRQ_PENDING 0x00000100 497902e6eb8SRob Clark #define A2XX_RBBM_STATUS_CPRQ_PENDING 0x00000200 498902e6eb8SRob Clark #define A2XX_RBBM_STATUS_CFRQ_PENDING 0x00000400 499902e6eb8SRob Clark #define A2XX_RBBM_STATUS_PFRQ_PENDING 0x00000800 500902e6eb8SRob Clark #define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA 0x00001000 501902e6eb8SRob Clark #define A2XX_RBBM_STATUS_RBBM_WU_BUSY 0x00004000 502902e6eb8SRob Clark #define A2XX_RBBM_STATUS_CP_NRT_BUSY 0x00010000 503902e6eb8SRob Clark #define A2XX_RBBM_STATUS_MH_BUSY 0x00040000 504902e6eb8SRob Clark #define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY 0x00080000 505902e6eb8SRob Clark #define A2XX_RBBM_STATUS_SX_BUSY 0x00200000 506902e6eb8SRob Clark #define A2XX_RBBM_STATUS_TPC_BUSY 0x00400000 507902e6eb8SRob Clark #define A2XX_RBBM_STATUS_SC_CNTX_BUSY 0x01000000 508902e6eb8SRob Clark #define A2XX_RBBM_STATUS_PA_BUSY 0x02000000 509902e6eb8SRob Clark #define A2XX_RBBM_STATUS_VGT_BUSY 0x04000000 510902e6eb8SRob Clark #define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY 0x08000000 511902e6eb8SRob Clark #define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY 0x10000000 512902e6eb8SRob Clark #define A2XX_RBBM_STATUS_RB_CNTX_BUSY 0x40000000 513902e6eb8SRob Clark #define A2XX_RBBM_STATUS_GUI_ACTIVE 0x80000000 514902e6eb8SRob Clark 51522ba8b6bSRob Clark #define REG_A2XX_MH_ARBITER_CONFIG 0x00000a40 51622ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK 0x0000003f 51722ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT 0 51822ba8b6bSRob Clark static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val) 51922ba8b6bSRob Clark { 52022ba8b6bSRob Clark return ((val) << A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK; 52122ba8b6bSRob Clark } 52222ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY 0x00000040 52322ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE 0x00000080 52422ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE 0x00000100 52522ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_L2_ARB_CONTROL 0x00000200 52622ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK 0x00001c00 52722ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT 10 52822ba8b6bSRob Clark static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val) 52922ba8b6bSRob Clark { 53022ba8b6bSRob Clark return ((val) << A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT) & A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK; 53122ba8b6bSRob Clark } 53222ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00002000 53322ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE 0x00004000 53422ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE 0x00008000 53522ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK 0x003f0000 53622ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT 16 53722ba8b6bSRob Clark static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val) 53822ba8b6bSRob Clark { 53922ba8b6bSRob Clark return ((val) << A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK; 54022ba8b6bSRob Clark } 54122ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE 0x00400000 54222ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE 0x00800000 54322ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE 0x01000000 54422ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE 0x02000000 54522ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE 0x04000000 54622ba8b6bSRob Clark 547ccdf7e28SRob Clark #define REG_A2XX_MH_INTERRUPT_MASK 0x00000a42 548ccdf7e28SRob Clark #define A2XX_MH_INTERRUPT_MASK_AXI_READ_ERROR 0x00000001 549ccdf7e28SRob Clark #define A2XX_MH_INTERRUPT_MASK_AXI_WRITE_ERROR 0x00000002 550ccdf7e28SRob Clark #define A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT 0x00000004 551ccdf7e28SRob Clark 552ccdf7e28SRob Clark #define REG_A2XX_MH_INTERRUPT_STATUS 0x00000a43 553ccdf7e28SRob Clark 554ccdf7e28SRob Clark #define REG_A2XX_MH_INTERRUPT_CLEAR 0x00000a44 555ccdf7e28SRob Clark 556ccdf7e28SRob Clark #define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1 0x00000a54 557ccdf7e28SRob Clark 558ccdf7e28SRob Clark #define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG2 0x00000a55 559ccdf7e28SRob Clark 560902e6eb8SRob Clark #define REG_A2XX_A220_VSC_BIN_SIZE 0x00000c01 561902e6eb8SRob Clark #define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 562902e6eb8SRob Clark #define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT 0 563902e6eb8SRob Clark static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val) 564902e6eb8SRob Clark { 565902e6eb8SRob Clark return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK; 566902e6eb8SRob Clark } 567902e6eb8SRob Clark #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 568902e6eb8SRob Clark #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT 5 569902e6eb8SRob Clark static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val) 570902e6eb8SRob Clark { 571902e6eb8SRob Clark return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK; 572902e6eb8SRob Clark } 573902e6eb8SRob Clark 574902e6eb8SRob Clark static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 575902e6eb8SRob Clark 576902e6eb8SRob Clark static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 577902e6eb8SRob Clark 578902e6eb8SRob Clark static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } 579902e6eb8SRob Clark 580902e6eb8SRob Clark static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } 581902e6eb8SRob Clark 582902e6eb8SRob Clark #define REG_A2XX_PC_DEBUG_CNTL 0x00000c38 583902e6eb8SRob Clark 584902e6eb8SRob Clark #define REG_A2XX_PC_DEBUG_DATA 0x00000c39 585902e6eb8SRob Clark 586902e6eb8SRob Clark #define REG_A2XX_PA_SC_VIZ_QUERY_STATUS 0x00000c44 587902e6eb8SRob Clark 588902e6eb8SRob Clark #define REG_A2XX_GRAS_DEBUG_CNTL 0x00000c80 589902e6eb8SRob Clark 590902e6eb8SRob Clark #define REG_A2XX_PA_SU_DEBUG_CNTL 0x00000c80 591902e6eb8SRob Clark 592902e6eb8SRob Clark #define REG_A2XX_GRAS_DEBUG_DATA 0x00000c81 593902e6eb8SRob Clark 594902e6eb8SRob Clark #define REG_A2XX_PA_SU_DEBUG_DATA 0x00000c81 595902e6eb8SRob Clark 596902e6eb8SRob Clark #define REG_A2XX_PA_SU_FACE_DATA 0x00000c86 59752260ae4SRob Clark #define A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK 0xffffffe0 59852260ae4SRob Clark #define A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT 5 59952260ae4SRob Clark static inline uint32_t A2XX_PA_SU_FACE_DATA_BASE_ADDR(uint32_t val) 60052260ae4SRob Clark { 60152260ae4SRob Clark return ((val) << A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT) & A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK; 60252260ae4SRob Clark } 603902e6eb8SRob Clark 604902e6eb8SRob Clark #define REG_A2XX_SQ_GPR_MANAGEMENT 0x00000d00 60552260ae4SRob Clark #define A2XX_SQ_GPR_MANAGEMENT_REG_DYNAMIC 0x00000001 60652260ae4SRob Clark #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK 0x00000ff0 60752260ae4SRob Clark #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT 4 60852260ae4SRob Clark static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX(uint32_t val) 60952260ae4SRob Clark { 61052260ae4SRob Clark return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK; 61152260ae4SRob Clark } 61252260ae4SRob Clark #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK 0x000ff000 61352260ae4SRob Clark #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT 12 61452260ae4SRob Clark static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX(uint32_t val) 61552260ae4SRob Clark { 61652260ae4SRob Clark return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK; 61752260ae4SRob Clark } 618902e6eb8SRob Clark 619902e6eb8SRob Clark #define REG_A2XX_SQ_FLOW_CONTROL 0x00000d01 620902e6eb8SRob Clark 621902e6eb8SRob Clark #define REG_A2XX_SQ_INST_STORE_MANAGMENT 0x00000d02 62252260ae4SRob Clark #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK 0x00000fff 62352260ae4SRob Clark #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT 0 62452260ae4SRob Clark static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX(uint32_t val) 62552260ae4SRob Clark { 62652260ae4SRob Clark return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK; 62752260ae4SRob Clark } 62852260ae4SRob Clark #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK 0x0fff0000 62952260ae4SRob Clark #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT 16 63052260ae4SRob Clark static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX(uint32_t val) 63152260ae4SRob Clark { 63252260ae4SRob Clark return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK; 63352260ae4SRob Clark } 634902e6eb8SRob Clark 635902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_MISC 0x00000d05 636902e6eb8SRob Clark 637902e6eb8SRob Clark #define REG_A2XX_SQ_INT_CNTL 0x00000d34 638902e6eb8SRob Clark 639902e6eb8SRob Clark #define REG_A2XX_SQ_INT_STATUS 0x00000d35 640902e6eb8SRob Clark 641902e6eb8SRob Clark #define REG_A2XX_SQ_INT_ACK 0x00000d36 642902e6eb8SRob Clark 643902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_INPUT_FSM 0x00000dae 644902e6eb8SRob Clark 645902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_CONST_MGR_FSM 0x00000daf 646902e6eb8SRob Clark 647902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_TP_FSM 0x00000db0 648902e6eb8SRob Clark 649902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_FSM_ALU_0 0x00000db1 650902e6eb8SRob Clark 651902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_FSM_ALU_1 0x00000db2 652902e6eb8SRob Clark 653902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_EXP_ALLOC 0x00000db3 654902e6eb8SRob Clark 655902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_PTR_BUFF 0x00000db4 656902e6eb8SRob Clark 657902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_GPR_VTX 0x00000db5 658902e6eb8SRob Clark 659902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_GPR_PIX 0x00000db6 660902e6eb8SRob Clark 661902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_TB_STATUS_SEL 0x00000db7 662902e6eb8SRob Clark 663902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_VTX_TB_0 0x00000db8 664902e6eb8SRob Clark 665902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_VTX_TB_1 0x00000db9 666902e6eb8SRob Clark 667902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG 0x00000dba 668902e6eb8SRob Clark 669902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM 0x00000dbb 670902e6eb8SRob Clark 671902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_PIX_TB_0 0x00000dbc 672902e6eb8SRob Clark 673902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0 0x00000dbd 674902e6eb8SRob Clark 675902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1 0x00000dbe 676902e6eb8SRob Clark 677902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2 0x00000dbf 678902e6eb8SRob Clark 679902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3 0x00000dc0 680902e6eb8SRob Clark 681902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM 0x00000dc1 682902e6eb8SRob Clark 683902e6eb8SRob Clark #define REG_A2XX_TC_CNTL_STATUS 0x00000e00 684902e6eb8SRob Clark #define A2XX_TC_CNTL_STATUS_L2_INVALIDATE 0x00000001 685902e6eb8SRob Clark 686902e6eb8SRob Clark #define REG_A2XX_TP0_CHICKEN 0x00000e1e 687902e6eb8SRob Clark 688902e6eb8SRob Clark #define REG_A2XX_RB_BC_CONTROL 0x00000f01 689902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE 0x00000001 690902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK 0x00000006 691902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT 1 692902e6eb8SRob Clark static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val) 693902e6eb8SRob Clark { 694902e6eb8SRob Clark return ((val) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK; 695902e6eb8SRob Clark } 696902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM 0x00000008 697902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010 698902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP 0x00000020 699902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP 0x00000040 700902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE 0x00000080 701902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK 0x00001f00 702902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT 8 703902e6eb8SRob Clark static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val) 704902e6eb8SRob Clark { 705902e6eb8SRob Clark return ((val) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK; 706902e6eb8SRob Clark } 707902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE 0x00004000 708902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_CRC_MODE 0x00008000 709902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS 0x00010000 710902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_DISABLE_ACCUM 0x00020000 711902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK 0x003c0000 712902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT 18 713902e6eb8SRob Clark static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val) 714902e6eb8SRob Clark { 715902e6eb8SRob Clark return ((val) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK; 716902e6eb8SRob Clark } 717902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE 0x00400000 718902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK 0x07800000 719902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT 23 720902e6eb8SRob Clark static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val) 721902e6eb8SRob Clark { 722902e6eb8SRob Clark return ((val) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK; 723902e6eb8SRob Clark } 724902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK 0x18000000 725902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT 27 726902e6eb8SRob Clark static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val) 727902e6eb8SRob Clark { 728902e6eb8SRob Clark return ((val) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK; 729902e6eb8SRob Clark } 730902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000 731902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_CRC_SYSTEM 0x40000000 732902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_RESERVED6 0x80000000 733902e6eb8SRob Clark 734902e6eb8SRob Clark #define REG_A2XX_RB_EDRAM_INFO 0x00000f02 735902e6eb8SRob Clark 736902e6eb8SRob Clark #define REG_A2XX_RB_DEBUG_CNTL 0x00000f26 737902e6eb8SRob Clark 738902e6eb8SRob Clark #define REG_A2XX_RB_DEBUG_DATA 0x00000f27 739902e6eb8SRob Clark 740902e6eb8SRob Clark #define REG_A2XX_RB_SURFACE_INFO 0x00002000 741ccdf7e28SRob Clark #define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK 0x00003fff 742ccdf7e28SRob Clark #define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT 0 743ccdf7e28SRob Clark static inline uint32_t A2XX_RB_SURFACE_INFO_SURFACE_PITCH(uint32_t val) 744ccdf7e28SRob Clark { 745ccdf7e28SRob Clark return ((val) << A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT) & A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK; 746ccdf7e28SRob Clark } 747ccdf7e28SRob Clark #define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK 0x0000c000 748ccdf7e28SRob Clark #define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT 14 749ccdf7e28SRob Clark static inline uint32_t A2XX_RB_SURFACE_INFO_MSAA_SAMPLES(uint32_t val) 750ccdf7e28SRob Clark { 751ccdf7e28SRob Clark return ((val) << A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT) & A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK; 752ccdf7e28SRob Clark } 753902e6eb8SRob Clark 754902e6eb8SRob Clark #define REG_A2XX_RB_COLOR_INFO 0x00002001 755902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_FORMAT__MASK 0x0000000f 756902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_FORMAT__SHIFT 0 757902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val) 758902e6eb8SRob Clark { 759902e6eb8SRob Clark return ((val) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT) & A2XX_RB_COLOR_INFO_FORMAT__MASK; 760902e6eb8SRob Clark } 761902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_ROUND_MODE__MASK 0x00000030 762902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT 4 763902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val) 764902e6eb8SRob Clark { 765902e6eb8SRob Clark return ((val) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK; 766902e6eb8SRob Clark } 767902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_LINEAR 0x00000040 768902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_ENDIAN__MASK 0x00000180 769902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_ENDIAN__SHIFT 7 770902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val) 771902e6eb8SRob Clark { 772902e6eb8SRob Clark return ((val) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT) & A2XX_RB_COLOR_INFO_ENDIAN__MASK; 773902e6eb8SRob Clark } 774902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_SWAP__MASK 0x00000600 775902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_SWAP__SHIFT 9 776902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val) 777902e6eb8SRob Clark { 778902e6eb8SRob Clark return ((val) << A2XX_RB_COLOR_INFO_SWAP__SHIFT) & A2XX_RB_COLOR_INFO_SWAP__MASK; 779902e6eb8SRob Clark } 780902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_BASE__MASK 0xfffff000 781902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_BASE__SHIFT 12 782902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val) 783902e6eb8SRob Clark { 784ccdf7e28SRob Clark return ((val >> 12) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK; 785902e6eb8SRob Clark } 786902e6eb8SRob Clark 787902e6eb8SRob Clark #define REG_A2XX_RB_DEPTH_INFO 0x00002002 788902e6eb8SRob Clark #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001 789902e6eb8SRob Clark #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 790902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) 791902e6eb8SRob Clark { 792902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 793902e6eb8SRob Clark } 794902e6eb8SRob Clark #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 795902e6eb8SRob Clark #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 796902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 797902e6eb8SRob Clark { 798ccdf7e28SRob Clark return ((val >> 12) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 799902e6eb8SRob Clark } 800902e6eb8SRob Clark 801902e6eb8SRob Clark #define REG_A2XX_A225_RB_COLOR_INFO3 0x00002005 802902e6eb8SRob Clark 803902e6eb8SRob Clark #define REG_A2XX_COHER_DEST_BASE_0 0x00002006 804902e6eb8SRob Clark 805902e6eb8SRob Clark #define REG_A2XX_PA_SC_SCREEN_SCISSOR_TL 0x0000200e 806902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 807902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 808902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 809902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 810902e6eb8SRob Clark { 811902e6eb8SRob Clark return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK; 812902e6eb8SRob Clark } 813902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 814902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 815902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 816902e6eb8SRob Clark { 817902e6eb8SRob Clark return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK; 818902e6eb8SRob Clark } 819902e6eb8SRob Clark 820902e6eb8SRob Clark #define REG_A2XX_PA_SC_SCREEN_SCISSOR_BR 0x0000200f 821902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 822902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 823902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 824902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 825902e6eb8SRob Clark { 826902e6eb8SRob Clark return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK; 827902e6eb8SRob Clark } 828902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 829902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 830902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 831902e6eb8SRob Clark { 832902e6eb8SRob Clark return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK; 833902e6eb8SRob Clark } 834902e6eb8SRob Clark 835902e6eb8SRob Clark #define REG_A2XX_PA_SC_WINDOW_OFFSET 0x00002080 836902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_OFFSET_X__MASK 0x00007fff 837902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT 0 838902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val) 839902e6eb8SRob Clark { 840902e6eb8SRob Clark return ((val) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK; 841902e6eb8SRob Clark } 842902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_OFFSET_Y__MASK 0x7fff0000 843902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT 16 844902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val) 845902e6eb8SRob Clark { 846902e6eb8SRob Clark return ((val) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK; 847902e6eb8SRob Clark } 848902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_OFFSET_DISABLE 0x80000000 849902e6eb8SRob Clark 850902e6eb8SRob Clark #define REG_A2XX_PA_SC_WINDOW_SCISSOR_TL 0x00002081 851902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 852902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 853902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 854902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 855902e6eb8SRob Clark { 856902e6eb8SRob Clark return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK; 857902e6eb8SRob Clark } 858902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 859902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 860902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 861902e6eb8SRob Clark { 862902e6eb8SRob Clark return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK; 863902e6eb8SRob Clark } 864902e6eb8SRob Clark 865902e6eb8SRob Clark #define REG_A2XX_PA_SC_WINDOW_SCISSOR_BR 0x00002082 866902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 867902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 868902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 869902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 870902e6eb8SRob Clark { 871902e6eb8SRob Clark return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK; 872902e6eb8SRob Clark } 873902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 874902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 875902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 876902e6eb8SRob Clark { 877902e6eb8SRob Clark return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK; 878902e6eb8SRob Clark } 879902e6eb8SRob Clark 880902e6eb8SRob Clark #define REG_A2XX_UNKNOWN_2010 0x00002010 881902e6eb8SRob Clark 882902e6eb8SRob Clark #define REG_A2XX_VGT_MAX_VTX_INDX 0x00002100 883902e6eb8SRob Clark 884902e6eb8SRob Clark #define REG_A2XX_VGT_MIN_VTX_INDX 0x00002101 885902e6eb8SRob Clark 886902e6eb8SRob Clark #define REG_A2XX_VGT_INDX_OFFSET 0x00002102 887902e6eb8SRob Clark 888902e6eb8SRob Clark #define REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX 0x00002103 889902e6eb8SRob Clark 890902e6eb8SRob Clark #define REG_A2XX_RB_COLOR_MASK 0x00002104 891902e6eb8SRob Clark #define A2XX_RB_COLOR_MASK_WRITE_RED 0x00000001 892902e6eb8SRob Clark #define A2XX_RB_COLOR_MASK_WRITE_GREEN 0x00000002 893902e6eb8SRob Clark #define A2XX_RB_COLOR_MASK_WRITE_BLUE 0x00000004 894902e6eb8SRob Clark #define A2XX_RB_COLOR_MASK_WRITE_ALPHA 0x00000008 895902e6eb8SRob Clark 896902e6eb8SRob Clark #define REG_A2XX_RB_BLEND_RED 0x00002105 897902e6eb8SRob Clark 898902e6eb8SRob Clark #define REG_A2XX_RB_BLEND_GREEN 0x00002106 899902e6eb8SRob Clark 900902e6eb8SRob Clark #define REG_A2XX_RB_BLEND_BLUE 0x00002107 901902e6eb8SRob Clark 902902e6eb8SRob Clark #define REG_A2XX_RB_BLEND_ALPHA 0x00002108 903902e6eb8SRob Clark 904902e6eb8SRob Clark #define REG_A2XX_RB_FOG_COLOR 0x00002109 90552260ae4SRob Clark #define A2XX_RB_FOG_COLOR_FOG_RED__MASK 0x000000ff 90652260ae4SRob Clark #define A2XX_RB_FOG_COLOR_FOG_RED__SHIFT 0 90752260ae4SRob Clark static inline uint32_t A2XX_RB_FOG_COLOR_FOG_RED(uint32_t val) 90852260ae4SRob Clark { 90952260ae4SRob Clark return ((val) << A2XX_RB_FOG_COLOR_FOG_RED__SHIFT) & A2XX_RB_FOG_COLOR_FOG_RED__MASK; 91052260ae4SRob Clark } 91152260ae4SRob Clark #define A2XX_RB_FOG_COLOR_FOG_GREEN__MASK 0x0000ff00 91252260ae4SRob Clark #define A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT 8 91352260ae4SRob Clark static inline uint32_t A2XX_RB_FOG_COLOR_FOG_GREEN(uint32_t val) 91452260ae4SRob Clark { 91552260ae4SRob Clark return ((val) << A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT) & A2XX_RB_FOG_COLOR_FOG_GREEN__MASK; 91652260ae4SRob Clark } 91752260ae4SRob Clark #define A2XX_RB_FOG_COLOR_FOG_BLUE__MASK 0x00ff0000 91852260ae4SRob Clark #define A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT 16 91952260ae4SRob Clark static inline uint32_t A2XX_RB_FOG_COLOR_FOG_BLUE(uint32_t val) 92052260ae4SRob Clark { 92152260ae4SRob Clark return ((val) << A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT) & A2XX_RB_FOG_COLOR_FOG_BLUE__MASK; 92252260ae4SRob Clark } 923902e6eb8SRob Clark 924902e6eb8SRob Clark #define REG_A2XX_RB_STENCILREFMASK_BF 0x0000210c 925902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 926902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 927902e6eb8SRob Clark static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 928902e6eb8SRob Clark { 929902e6eb8SRob Clark return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 930902e6eb8SRob Clark } 931902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 932902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 933902e6eb8SRob Clark static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 934902e6eb8SRob Clark { 935902e6eb8SRob Clark return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 936902e6eb8SRob Clark } 937902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 938902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 939902e6eb8SRob Clark static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 940902e6eb8SRob Clark { 941902e6eb8SRob Clark return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 942902e6eb8SRob Clark } 943902e6eb8SRob Clark 944902e6eb8SRob Clark #define REG_A2XX_RB_STENCILREFMASK 0x0000210d 945902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 946902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 947902e6eb8SRob Clark static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 948902e6eb8SRob Clark { 949902e6eb8SRob Clark return ((val) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK; 950902e6eb8SRob Clark } 951902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 952902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 953902e6eb8SRob Clark static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 954902e6eb8SRob Clark { 955902e6eb8SRob Clark return ((val) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK; 956902e6eb8SRob Clark } 957902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 958902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 959902e6eb8SRob Clark static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 960902e6eb8SRob Clark { 961902e6eb8SRob Clark return ((val) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 962902e6eb8SRob Clark } 963902e6eb8SRob Clark 964902e6eb8SRob Clark #define REG_A2XX_RB_ALPHA_REF 0x0000210e 965902e6eb8SRob Clark 966902e6eb8SRob Clark #define REG_A2XX_PA_CL_VPORT_XSCALE 0x0000210f 967902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_XSCALE__MASK 0xffffffff 968902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_XSCALE__SHIFT 0 969902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val) 970902e6eb8SRob Clark { 971902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT) & A2XX_PA_CL_VPORT_XSCALE__MASK; 972902e6eb8SRob Clark } 973902e6eb8SRob Clark 974902e6eb8SRob Clark #define REG_A2XX_PA_CL_VPORT_XOFFSET 0x00002110 975902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_XOFFSET__MASK 0xffffffff 976902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_XOFFSET__SHIFT 0 977902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val) 978902e6eb8SRob Clark { 979902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT) & A2XX_PA_CL_VPORT_XOFFSET__MASK; 980902e6eb8SRob Clark } 981902e6eb8SRob Clark 982902e6eb8SRob Clark #define REG_A2XX_PA_CL_VPORT_YSCALE 0x00002111 983902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_YSCALE__MASK 0xffffffff 984902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_YSCALE__SHIFT 0 985902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val) 986902e6eb8SRob Clark { 987902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT) & A2XX_PA_CL_VPORT_YSCALE__MASK; 988902e6eb8SRob Clark } 989902e6eb8SRob Clark 990902e6eb8SRob Clark #define REG_A2XX_PA_CL_VPORT_YOFFSET 0x00002112 991902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_YOFFSET__MASK 0xffffffff 992902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_YOFFSET__SHIFT 0 993902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val) 994902e6eb8SRob Clark { 995902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT) & A2XX_PA_CL_VPORT_YOFFSET__MASK; 996902e6eb8SRob Clark } 997902e6eb8SRob Clark 998902e6eb8SRob Clark #define REG_A2XX_PA_CL_VPORT_ZSCALE 0x00002113 999902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_ZSCALE__MASK 0xffffffff 1000902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_ZSCALE__SHIFT 0 1001902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val) 1002902e6eb8SRob Clark { 1003902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT) & A2XX_PA_CL_VPORT_ZSCALE__MASK; 1004902e6eb8SRob Clark } 1005902e6eb8SRob Clark 1006902e6eb8SRob Clark #define REG_A2XX_PA_CL_VPORT_ZOFFSET 0x00002114 1007902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_ZOFFSET__MASK 0xffffffff 1008902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_ZOFFSET__SHIFT 0 1009902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val) 1010902e6eb8SRob Clark { 1011902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT) & A2XX_PA_CL_VPORT_ZOFFSET__MASK; 1012902e6eb8SRob Clark } 1013902e6eb8SRob Clark 1014902e6eb8SRob Clark #define REG_A2XX_SQ_PROGRAM_CNTL 0x00002180 1015902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK 0x000000ff 1016902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT 0 1017902e6eb8SRob Clark static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val) 1018902e6eb8SRob Clark { 1019902e6eb8SRob Clark return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK; 1020902e6eb8SRob Clark } 1021902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK 0x0000ff00 1022902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT 8 1023902e6eb8SRob Clark static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val) 1024902e6eb8SRob Clark { 1025902e6eb8SRob Clark return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK; 1026902e6eb8SRob Clark } 1027902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE 0x00010000 1028902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE 0x00020000 1029902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_PARAM_GEN 0x00040000 1030902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX 0x00080000 1031902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK 0x00f00000 1032902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT 20 1033902e6eb8SRob Clark static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val) 1034902e6eb8SRob Clark { 1035902e6eb8SRob Clark return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK; 1036902e6eb8SRob Clark } 1037902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK 0x07000000 1038902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT 24 1039902e6eb8SRob Clark static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val) 1040902e6eb8SRob Clark { 1041902e6eb8SRob Clark return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK; 1042902e6eb8SRob Clark } 1043902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK 0x78000000 1044902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT 27 1045902e6eb8SRob Clark static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val) 1046902e6eb8SRob Clark { 1047902e6eb8SRob Clark return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK; 1048902e6eb8SRob Clark } 1049902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX 0x80000000 1050902e6eb8SRob Clark 1051902e6eb8SRob Clark #define REG_A2XX_SQ_CONTEXT_MISC 0x00002181 1052902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE 0x00000001 1053902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY 0x00000002 1054902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK 0x0000000c 1055902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT 2 1056902e6eb8SRob Clark static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val) 1057902e6eb8SRob Clark { 1058902e6eb8SRob Clark return ((val) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK; 1059902e6eb8SRob Clark } 1060902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK 0x0000ff00 1061902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT 8 1062902e6eb8SRob Clark static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val) 1063902e6eb8SRob Clark { 1064902e6eb8SRob Clark return ((val) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK; 1065902e6eb8SRob Clark } 1066902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF 0x00010000 1067902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE 0x00020000 1068902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL 0x00040000 1069902e6eb8SRob Clark 1070902e6eb8SRob Clark #define REG_A2XX_SQ_INTERPOLATOR_CNTL 0x00002182 107152260ae4SRob Clark #define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK 0x0000ffff 107252260ae4SRob Clark #define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT 0 107352260ae4SRob Clark static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE(uint32_t val) 107452260ae4SRob Clark { 107552260ae4SRob Clark return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK; 107652260ae4SRob Clark } 107752260ae4SRob Clark #define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK 0xffff0000 107852260ae4SRob Clark #define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT 16 107952260ae4SRob Clark static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN(uint32_t val) 108052260ae4SRob Clark { 108152260ae4SRob Clark return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK; 108252260ae4SRob Clark } 1083902e6eb8SRob Clark 1084902e6eb8SRob Clark #define REG_A2XX_SQ_WRAPPING_0 0x00002183 108552260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK 0x0000000f 108652260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT 0 108752260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_0(uint32_t val) 108852260ae4SRob Clark { 108952260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK; 109052260ae4SRob Clark } 109152260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK 0x000000f0 109252260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT 4 109352260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_1(uint32_t val) 109452260ae4SRob Clark { 109552260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK; 109652260ae4SRob Clark } 109752260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK 0x00000f00 109852260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT 8 109952260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_2(uint32_t val) 110052260ae4SRob Clark { 110152260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK; 110252260ae4SRob Clark } 110352260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK 0x0000f000 110452260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT 12 110552260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_3(uint32_t val) 110652260ae4SRob Clark { 110752260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK; 110852260ae4SRob Clark } 110952260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK 0x000f0000 111052260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT 16 111152260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_4(uint32_t val) 111252260ae4SRob Clark { 111352260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK; 111452260ae4SRob Clark } 111552260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK 0x00f00000 111652260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT 20 111752260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_5(uint32_t val) 111852260ae4SRob Clark { 111952260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK; 112052260ae4SRob Clark } 112152260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK 0x0f000000 112252260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT 24 112352260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_6(uint32_t val) 112452260ae4SRob Clark { 112552260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK; 112652260ae4SRob Clark } 112752260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK 0xf0000000 112852260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT 28 112952260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_7(uint32_t val) 113052260ae4SRob Clark { 113152260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK; 113252260ae4SRob Clark } 1133902e6eb8SRob Clark 1134902e6eb8SRob Clark #define REG_A2XX_SQ_WRAPPING_1 0x00002184 113552260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK 0x0000000f 113652260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT 0 113752260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_8(uint32_t val) 113852260ae4SRob Clark { 113952260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK; 114052260ae4SRob Clark } 114152260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK 0x000000f0 114252260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT 4 114352260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_9(uint32_t val) 114452260ae4SRob Clark { 114552260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK; 114652260ae4SRob Clark } 114752260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK 0x00000f00 114852260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT 8 114952260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_10(uint32_t val) 115052260ae4SRob Clark { 115152260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK; 115252260ae4SRob Clark } 115352260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK 0x0000f000 115452260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT 12 115552260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_11(uint32_t val) 115652260ae4SRob Clark { 115752260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK; 115852260ae4SRob Clark } 115952260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK 0x000f0000 116052260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT 16 116152260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_12(uint32_t val) 116252260ae4SRob Clark { 116352260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK; 116452260ae4SRob Clark } 116552260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK 0x00f00000 116652260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT 20 116752260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_13(uint32_t val) 116852260ae4SRob Clark { 116952260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK; 117052260ae4SRob Clark } 117152260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK 0x0f000000 117252260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT 24 117352260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_14(uint32_t val) 117452260ae4SRob Clark { 117552260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK; 117652260ae4SRob Clark } 117752260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK 0xf0000000 117852260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT 28 117952260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_15(uint32_t val) 118052260ae4SRob Clark { 118152260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK; 118252260ae4SRob Clark } 1183902e6eb8SRob Clark 1184902e6eb8SRob Clark #define REG_A2XX_SQ_PS_PROGRAM 0x000021f6 118552260ae4SRob Clark #define A2XX_SQ_PS_PROGRAM_BASE__MASK 0x00000fff 118652260ae4SRob Clark #define A2XX_SQ_PS_PROGRAM_BASE__SHIFT 0 118752260ae4SRob Clark static inline uint32_t A2XX_SQ_PS_PROGRAM_BASE(uint32_t val) 118852260ae4SRob Clark { 118952260ae4SRob Clark return ((val) << A2XX_SQ_PS_PROGRAM_BASE__SHIFT) & A2XX_SQ_PS_PROGRAM_BASE__MASK; 119052260ae4SRob Clark } 119152260ae4SRob Clark #define A2XX_SQ_PS_PROGRAM_SIZE__MASK 0x00fff000 119252260ae4SRob Clark #define A2XX_SQ_PS_PROGRAM_SIZE__SHIFT 12 119352260ae4SRob Clark static inline uint32_t A2XX_SQ_PS_PROGRAM_SIZE(uint32_t val) 119452260ae4SRob Clark { 119552260ae4SRob Clark return ((val) << A2XX_SQ_PS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_PS_PROGRAM_SIZE__MASK; 119652260ae4SRob Clark } 1197902e6eb8SRob Clark 1198902e6eb8SRob Clark #define REG_A2XX_SQ_VS_PROGRAM 0x000021f7 119952260ae4SRob Clark #define A2XX_SQ_VS_PROGRAM_BASE__MASK 0x00000fff 120052260ae4SRob Clark #define A2XX_SQ_VS_PROGRAM_BASE__SHIFT 0 120152260ae4SRob Clark static inline uint32_t A2XX_SQ_VS_PROGRAM_BASE(uint32_t val) 120252260ae4SRob Clark { 120352260ae4SRob Clark return ((val) << A2XX_SQ_VS_PROGRAM_BASE__SHIFT) & A2XX_SQ_VS_PROGRAM_BASE__MASK; 120452260ae4SRob Clark } 120552260ae4SRob Clark #define A2XX_SQ_VS_PROGRAM_SIZE__MASK 0x00fff000 120652260ae4SRob Clark #define A2XX_SQ_VS_PROGRAM_SIZE__SHIFT 12 120752260ae4SRob Clark static inline uint32_t A2XX_SQ_VS_PROGRAM_SIZE(uint32_t val) 120852260ae4SRob Clark { 120952260ae4SRob Clark return ((val) << A2XX_SQ_VS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_VS_PROGRAM_SIZE__MASK; 121052260ae4SRob Clark } 1211902e6eb8SRob Clark 1212facb4f4eSRob Clark #define REG_A2XX_VGT_EVENT_INITIATOR 0x000021f9 1213facb4f4eSRob Clark 1214facb4f4eSRob Clark #define REG_A2XX_VGT_DRAW_INITIATOR 0x000021fc 121589301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f 121689301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 121789301471SRob Clark static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) 121889301471SRob Clark { 121989301471SRob Clark return ((val) << A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK; 122089301471SRob Clark } 122189301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 122289301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 122389301471SRob Clark static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) 122489301471SRob Clark { 122589301471SRob Clark return ((val) << A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK; 122689301471SRob Clark } 122789301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600 122889301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9 122989301471SRob Clark static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) 123089301471SRob Clark { 123189301471SRob Clark return ((val) << A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK; 123289301471SRob Clark } 123389301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800 123489301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11 123589301471SRob Clark static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) 123689301471SRob Clark { 123789301471SRob Clark return ((val) << A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK; 123889301471SRob Clark } 123989301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000 124089301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000 124189301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000 1242bc00ae02SRob Clark #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK 0xff000000 1243bc00ae02SRob Clark #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT 24 1244bc00ae02SRob Clark static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) 124589301471SRob Clark { 1246bc00ae02SRob Clark return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK; 124789301471SRob Clark } 1248facb4f4eSRob Clark 1249facb4f4eSRob Clark #define REG_A2XX_VGT_IMMED_DATA 0x000021fd 1250facb4f4eSRob Clark 1251902e6eb8SRob Clark #define REG_A2XX_RB_DEPTHCONTROL 0x00002200 1252902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE 0x00000001 1253902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_Z_ENABLE 0x00000002 1254902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE 0x00000004 1255902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE 0x00000008 1256902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_ZFUNC__MASK 0x00000070 1257902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT 4 1258902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val) 1259902e6eb8SRob Clark { 1260902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK; 1261902e6eb8SRob Clark } 1262902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE 0x00000080 1263902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK 0x00000700 1264902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT 8 1265902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val) 1266902e6eb8SRob Clark { 1267902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK; 1268902e6eb8SRob Clark } 1269902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK 0x00003800 1270902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT 11 1271902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val) 1272902e6eb8SRob Clark { 1273902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK; 1274902e6eb8SRob Clark } 1275902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK 0x0001c000 1276902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT 14 1277902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val) 1278902e6eb8SRob Clark { 1279902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK; 1280902e6eb8SRob Clark } 1281902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK 0x000e0000 1282902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT 17 1283902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val) 1284902e6eb8SRob Clark { 1285902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK; 1286902e6eb8SRob Clark } 1287902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK 0x00700000 1288902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT 20 1289902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val) 1290902e6eb8SRob Clark { 1291902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK; 1292902e6eb8SRob Clark } 1293902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK 0x03800000 1294902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT 23 1295902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val) 1296902e6eb8SRob Clark { 1297902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK; 1298902e6eb8SRob Clark } 1299902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK 0x1c000000 1300902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT 26 1301902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val) 1302902e6eb8SRob Clark { 1303902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK; 1304902e6eb8SRob Clark } 1305902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK 0xe0000000 1306902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT 29 1307902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val) 1308902e6eb8SRob Clark { 1309902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK; 1310902e6eb8SRob Clark } 1311902e6eb8SRob Clark 1312902e6eb8SRob Clark #define REG_A2XX_RB_BLEND_CONTROL 0x00002201 1313902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK 0x0000001f 1314902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT 0 1315902e6eb8SRob Clark static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val) 1316902e6eb8SRob Clark { 1317902e6eb8SRob Clark return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK; 1318902e6eb8SRob Clark } 1319902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK 0x000000e0 1320902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT 5 132189301471SRob Clark static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val) 1322902e6eb8SRob Clark { 1323902e6eb8SRob Clark return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK; 1324902e6eb8SRob Clark } 1325902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK 0x00001f00 1326902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT 8 1327902e6eb8SRob Clark static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val) 1328902e6eb8SRob Clark { 1329902e6eb8SRob Clark return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK; 1330902e6eb8SRob Clark } 1331902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK 0x001f0000 1332902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT 16 1333902e6eb8SRob Clark static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val) 1334902e6eb8SRob Clark { 1335902e6eb8SRob Clark return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK; 1336902e6eb8SRob Clark } 1337902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK 0x00e00000 1338902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT 21 133989301471SRob Clark static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val) 1340902e6eb8SRob Clark { 1341902e6eb8SRob Clark return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK; 1342902e6eb8SRob Clark } 1343902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK 0x1f000000 1344902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT 24 1345902e6eb8SRob Clark static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val) 1346902e6eb8SRob Clark { 1347902e6eb8SRob Clark return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK; 1348902e6eb8SRob Clark } 1349902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE 0x20000000 1350902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE 0x40000000 1351902e6eb8SRob Clark 1352902e6eb8SRob Clark #define REG_A2XX_RB_COLORCONTROL 0x00002202 1353902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK 0x00000007 1354902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT 0 1355902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val) 1356902e6eb8SRob Clark { 1357902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK; 1358902e6eb8SRob Clark } 1359902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE 0x00000008 1360902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE 0x00000010 1361902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_BLEND_DISABLE 0x00000020 1362902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_VOB_ENABLE 0x00000040 1363902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG 0x00000080 1364902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ROP_CODE__MASK 0x00000f00 1365902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT 8 1366902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val) 1367902e6eb8SRob Clark { 1368902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK; 1369902e6eb8SRob Clark } 1370902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_DITHER_MODE__MASK 0x00003000 1371902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT 12 1372902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) 1373902e6eb8SRob Clark { 1374902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK; 1375902e6eb8SRob Clark } 1376902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK 0x0000c000 1377902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT 14 1378902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val) 1379902e6eb8SRob Clark { 1380902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK; 1381902e6eb8SRob Clark } 1382902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_PIXEL_FOG 0x00010000 1383902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK 0x03000000 1384902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT 24 1385902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val) 1386902e6eb8SRob Clark { 1387902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK; 1388902e6eb8SRob Clark } 1389902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK 0x0c000000 1390902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT 26 1391902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val) 1392902e6eb8SRob Clark { 1393902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK; 1394902e6eb8SRob Clark } 1395902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK 0x30000000 1396902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT 28 1397902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val) 1398902e6eb8SRob Clark { 1399902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK; 1400902e6eb8SRob Clark } 1401902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK 0xc0000000 1402902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT 30 1403902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val) 1404902e6eb8SRob Clark { 1405902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK; 1406902e6eb8SRob Clark } 1407902e6eb8SRob Clark 1408902e6eb8SRob Clark #define REG_A2XX_VGT_CURRENT_BIN_ID_MAX 0x00002203 1409902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK 0x00000007 1410902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT 0 1411902e6eb8SRob Clark static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val) 1412902e6eb8SRob Clark { 1413902e6eb8SRob Clark return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK; 1414902e6eb8SRob Clark } 1415902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK 0x00000038 1416902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT 3 1417902e6eb8SRob Clark static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val) 1418902e6eb8SRob Clark { 1419902e6eb8SRob Clark return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK; 1420902e6eb8SRob Clark } 1421902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK 0x000001c0 1422902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT 6 1423902e6eb8SRob Clark static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val) 1424902e6eb8SRob Clark { 1425902e6eb8SRob Clark return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK; 1426902e6eb8SRob Clark } 1427902e6eb8SRob Clark 1428902e6eb8SRob Clark #define REG_A2XX_PA_CL_CLIP_CNTL 0x00002204 1429902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 1430902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA 0x00040000 1431902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK 0x00080000 1432902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT 19 1433902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val) 1434902e6eb8SRob Clark { 1435902e6eb8SRob Clark return ((val) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK; 1436902e6eb8SRob Clark } 1437902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT 0x00100000 1438902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR 0x00200000 1439902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN 0x00400000 1440902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN 0x00800000 1441902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN 0x01000000 1442902e6eb8SRob Clark 1443902e6eb8SRob Clark #define REG_A2XX_PA_SU_SC_MODE_CNTL 0x00002205 1444902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT 0x00000001 1445902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK 0x00000002 1446902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_FACE 0x00000004 1447902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK 0x00000018 1448902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT 3 1449902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val) 1450902e6eb8SRob Clark { 1451902e6eb8SRob Clark return ((val) << A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK; 1452902e6eb8SRob Clark } 1453902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK 0x000000e0 1454902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT 5 1455902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 1456902e6eb8SRob Clark { 1457902e6eb8SRob Clark return ((val) << A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK; 1458902e6eb8SRob Clark } 1459902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK 0x00000700 1460902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT 8 1461902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 1462902e6eb8SRob Clark { 1463902e6eb8SRob Clark return ((val) << A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK; 1464902e6eb8SRob Clark } 1465902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE 0x00000800 1466902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE 0x00001000 1467902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE 0x00002000 1468902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE 0x00008000 1469902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE 0x00010000 1470902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE 0x00040000 1471902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST 0x00080000 1472902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS 0x00100000 1473902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA 0x00200000 1474902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE 0x00800000 1475902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI 0x02000000 1476902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000 1477902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS 0x10000000 1478902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS 0x20000000 1479902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE 0x40000000 1480902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE 0x80000000 1481902e6eb8SRob Clark 1482902e6eb8SRob Clark #define REG_A2XX_PA_CL_VTE_CNTL 0x00002206 1483902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA 0x00000001 1484902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA 0x00000002 1485902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA 0x00000004 1486902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA 0x00000008 1487902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA 0x00000010 1488902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA 0x00000020 1489902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT 0x00000100 1490902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT 0x00000200 1491902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT 0x00000400 1492902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_PERFCOUNTER_REF 0x00000800 1493902e6eb8SRob Clark 1494902e6eb8SRob Clark #define REG_A2XX_VGT_CURRENT_BIN_ID_MIN 0x00002207 1495902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK 0x00000007 1496902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT 0 1497902e6eb8SRob Clark static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val) 1498902e6eb8SRob Clark { 1499902e6eb8SRob Clark return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK; 1500902e6eb8SRob Clark } 1501902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK 0x00000038 1502902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT 3 1503902e6eb8SRob Clark static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val) 1504902e6eb8SRob Clark { 1505902e6eb8SRob Clark return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK; 1506902e6eb8SRob Clark } 1507902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK 0x000001c0 1508902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT 6 1509902e6eb8SRob Clark static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val) 1510902e6eb8SRob Clark { 1511902e6eb8SRob Clark return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK; 1512902e6eb8SRob Clark } 1513902e6eb8SRob Clark 1514902e6eb8SRob Clark #define REG_A2XX_RB_MODECONTROL 0x00002208 1515902e6eb8SRob Clark #define A2XX_RB_MODECONTROL_EDRAM_MODE__MASK 0x00000007 1516902e6eb8SRob Clark #define A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT 0 1517902e6eb8SRob Clark static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val) 1518902e6eb8SRob Clark { 1519902e6eb8SRob Clark return ((val) << A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT) & A2XX_RB_MODECONTROL_EDRAM_MODE__MASK; 1520902e6eb8SRob Clark } 1521902e6eb8SRob Clark 1522902e6eb8SRob Clark #define REG_A2XX_A220_RB_LRZ_VSC_CONTROL 0x00002209 1523902e6eb8SRob Clark 1524902e6eb8SRob Clark #define REG_A2XX_RB_SAMPLE_POS 0x0000220a 1525902e6eb8SRob Clark 1526902e6eb8SRob Clark #define REG_A2XX_CLEAR_COLOR 0x0000220b 1527902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_RED__MASK 0x000000ff 1528902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_RED__SHIFT 0 1529902e6eb8SRob Clark static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val) 1530902e6eb8SRob Clark { 1531902e6eb8SRob Clark return ((val) << A2XX_CLEAR_COLOR_RED__SHIFT) & A2XX_CLEAR_COLOR_RED__MASK; 1532902e6eb8SRob Clark } 1533902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_GREEN__MASK 0x0000ff00 1534902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_GREEN__SHIFT 8 1535902e6eb8SRob Clark static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val) 1536902e6eb8SRob Clark { 1537902e6eb8SRob Clark return ((val) << A2XX_CLEAR_COLOR_GREEN__SHIFT) & A2XX_CLEAR_COLOR_GREEN__MASK; 1538902e6eb8SRob Clark } 1539902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_BLUE__MASK 0x00ff0000 1540902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_BLUE__SHIFT 16 1541902e6eb8SRob Clark static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val) 1542902e6eb8SRob Clark { 1543902e6eb8SRob Clark return ((val) << A2XX_CLEAR_COLOR_BLUE__SHIFT) & A2XX_CLEAR_COLOR_BLUE__MASK; 1544902e6eb8SRob Clark } 1545902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_ALPHA__MASK 0xff000000 1546902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_ALPHA__SHIFT 24 1547902e6eb8SRob Clark static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val) 1548902e6eb8SRob Clark { 1549902e6eb8SRob Clark return ((val) << A2XX_CLEAR_COLOR_ALPHA__SHIFT) & A2XX_CLEAR_COLOR_ALPHA__MASK; 1550902e6eb8SRob Clark } 1551902e6eb8SRob Clark 1552902e6eb8SRob Clark #define REG_A2XX_A220_GRAS_CONTROL 0x00002210 1553902e6eb8SRob Clark 1554902e6eb8SRob Clark #define REG_A2XX_PA_SU_POINT_SIZE 0x00002280 1555902e6eb8SRob Clark #define A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK 0x0000ffff 1556902e6eb8SRob Clark #define A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT 0 1557902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val) 1558902e6eb8SRob Clark { 1559bc00ae02SRob Clark return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK; 1560902e6eb8SRob Clark } 1561902e6eb8SRob Clark #define A2XX_PA_SU_POINT_SIZE_WIDTH__MASK 0xffff0000 1562902e6eb8SRob Clark #define A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT 16 1563902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val) 1564902e6eb8SRob Clark { 1565bc00ae02SRob Clark return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK; 1566902e6eb8SRob Clark } 1567902e6eb8SRob Clark 1568902e6eb8SRob Clark #define REG_A2XX_PA_SU_POINT_MINMAX 0x00002281 1569902e6eb8SRob Clark #define A2XX_PA_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 1570902e6eb8SRob Clark #define A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT 0 1571902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val) 1572902e6eb8SRob Clark { 1573bc00ae02SRob Clark return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK; 1574902e6eb8SRob Clark } 1575902e6eb8SRob Clark #define A2XX_PA_SU_POINT_MINMAX_MAX__MASK 0xffff0000 1576902e6eb8SRob Clark #define A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT 16 1577902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val) 1578902e6eb8SRob Clark { 1579bc00ae02SRob Clark return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK; 1580902e6eb8SRob Clark } 1581902e6eb8SRob Clark 1582902e6eb8SRob Clark #define REG_A2XX_PA_SU_LINE_CNTL 0x00002282 1583902e6eb8SRob Clark #define A2XX_PA_SU_LINE_CNTL_WIDTH__MASK 0x0000ffff 1584902e6eb8SRob Clark #define A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT 0 1585902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val) 1586902e6eb8SRob Clark { 1587bc00ae02SRob Clark return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK; 1588902e6eb8SRob Clark } 1589902e6eb8SRob Clark 1590902e6eb8SRob Clark #define REG_A2XX_PA_SC_LINE_STIPPLE 0x00002283 1591902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK 0x0000ffff 1592902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT 0 1593902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val) 1594902e6eb8SRob Clark { 1595902e6eb8SRob Clark return ((val) << A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK; 1596902e6eb8SRob Clark } 1597902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK 0x00ff0000 1598902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT 16 1599902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val) 1600902e6eb8SRob Clark { 1601902e6eb8SRob Clark return ((val) << A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK; 1602902e6eb8SRob Clark } 1603902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK 0x10000000 1604902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT 28 1605902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val) 1606902e6eb8SRob Clark { 1607902e6eb8SRob Clark return ((val) << A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK; 1608902e6eb8SRob Clark } 1609902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK 0x60000000 1610902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT 29 1611902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val) 1612902e6eb8SRob Clark { 1613902e6eb8SRob Clark return ((val) << A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK; 1614902e6eb8SRob Clark } 1615902e6eb8SRob Clark 1616902e6eb8SRob Clark #define REG_A2XX_PA_SC_VIZ_QUERY 0x00002293 161752260ae4SRob Clark #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ENA 0x00000001 161852260ae4SRob Clark #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK 0x0000007e 161952260ae4SRob Clark #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT 1 162052260ae4SRob Clark static inline uint32_t A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID(uint32_t val) 162152260ae4SRob Clark { 162252260ae4SRob Clark return ((val) << A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT) & A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK; 162352260ae4SRob Clark } 162452260ae4SRob Clark #define A2XX_PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z 0x00000100 1625902e6eb8SRob Clark 1626902e6eb8SRob Clark #define REG_A2XX_VGT_ENHANCE 0x00002294 1627902e6eb8SRob Clark 1628902e6eb8SRob Clark #define REG_A2XX_PA_SC_LINE_CNTL 0x00002300 1629902e6eb8SRob Clark #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK 0x0000ffff 1630902e6eb8SRob Clark #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT 0 1631902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val) 1632902e6eb8SRob Clark { 1633902e6eb8SRob Clark return ((val) << A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT) & A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK; 1634902e6eb8SRob Clark } 1635902e6eb8SRob Clark #define A2XX_PA_SC_LINE_CNTL_USE_BRES_CNTL 0x00000100 1636902e6eb8SRob Clark #define A2XX_PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH 0x00000200 1637902e6eb8SRob Clark #define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL 0x00000400 1638902e6eb8SRob Clark 1639902e6eb8SRob Clark #define REG_A2XX_PA_SC_AA_CONFIG 0x00002301 164052260ae4SRob Clark #define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK 0x00000007 164152260ae4SRob Clark #define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT 0 164252260ae4SRob Clark static inline uint32_t A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES(uint32_t val) 164352260ae4SRob Clark { 164452260ae4SRob Clark return ((val) << A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT) & A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK; 164552260ae4SRob Clark } 164652260ae4SRob Clark #define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK 0x0001e000 164752260ae4SRob Clark #define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT 13 164852260ae4SRob Clark static inline uint32_t A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST(uint32_t val) 164952260ae4SRob Clark { 165052260ae4SRob Clark return ((val) << A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT) & A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK; 165152260ae4SRob Clark } 1652902e6eb8SRob Clark 1653902e6eb8SRob Clark #define REG_A2XX_PA_SU_VTX_CNTL 0x00002302 1654902e6eb8SRob Clark #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK 0x00000001 1655902e6eb8SRob Clark #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT 0 1656902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val) 1657902e6eb8SRob Clark { 1658902e6eb8SRob Clark return ((val) << A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT) & A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK; 1659902e6eb8SRob Clark } 1660902e6eb8SRob Clark #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK 0x00000006 1661902e6eb8SRob Clark #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT 1 1662902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val) 1663902e6eb8SRob Clark { 1664902e6eb8SRob Clark return ((val) << A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK; 1665902e6eb8SRob Clark } 1666902e6eb8SRob Clark #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK 0x00000380 1667902e6eb8SRob Clark #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT 7 1668902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val) 1669902e6eb8SRob Clark { 1670902e6eb8SRob Clark return ((val) << A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK; 1671902e6eb8SRob Clark } 1672902e6eb8SRob Clark 1673902e6eb8SRob Clark #define REG_A2XX_PA_CL_GB_VERT_CLIP_ADJ 0x00002303 1674902e6eb8SRob Clark #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK 0xffffffff 1675902e6eb8SRob Clark #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT 0 1676902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val) 1677902e6eb8SRob Clark { 1678902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK; 1679902e6eb8SRob Clark } 1680902e6eb8SRob Clark 1681902e6eb8SRob Clark #define REG_A2XX_PA_CL_GB_VERT_DISC_ADJ 0x00002304 1682902e6eb8SRob Clark #define A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK 0xffffffff 1683902e6eb8SRob Clark #define A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT 0 1684902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val) 1685902e6eb8SRob Clark { 1686902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK; 1687902e6eb8SRob Clark } 1688902e6eb8SRob Clark 1689902e6eb8SRob Clark #define REG_A2XX_PA_CL_GB_HORZ_CLIP_ADJ 0x00002305 1690902e6eb8SRob Clark #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK 0xffffffff 1691902e6eb8SRob Clark #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT 0 1692902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val) 1693902e6eb8SRob Clark { 1694902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK; 1695902e6eb8SRob Clark } 1696902e6eb8SRob Clark 1697902e6eb8SRob Clark #define REG_A2XX_PA_CL_GB_HORZ_DISC_ADJ 0x00002306 1698902e6eb8SRob Clark #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK 0xffffffff 1699902e6eb8SRob Clark #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT 0 1700902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val) 1701902e6eb8SRob Clark { 1702902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK; 1703902e6eb8SRob Clark } 1704902e6eb8SRob Clark 1705902e6eb8SRob Clark #define REG_A2XX_SQ_VS_CONST 0x00002307 1706902e6eb8SRob Clark #define A2XX_SQ_VS_CONST_BASE__MASK 0x000001ff 1707902e6eb8SRob Clark #define A2XX_SQ_VS_CONST_BASE__SHIFT 0 1708902e6eb8SRob Clark static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val) 1709902e6eb8SRob Clark { 1710902e6eb8SRob Clark return ((val) << A2XX_SQ_VS_CONST_BASE__SHIFT) & A2XX_SQ_VS_CONST_BASE__MASK; 1711902e6eb8SRob Clark } 1712902e6eb8SRob Clark #define A2XX_SQ_VS_CONST_SIZE__MASK 0x001ff000 1713902e6eb8SRob Clark #define A2XX_SQ_VS_CONST_SIZE__SHIFT 12 1714902e6eb8SRob Clark static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val) 1715902e6eb8SRob Clark { 1716902e6eb8SRob Clark return ((val) << A2XX_SQ_VS_CONST_SIZE__SHIFT) & A2XX_SQ_VS_CONST_SIZE__MASK; 1717902e6eb8SRob Clark } 1718902e6eb8SRob Clark 1719902e6eb8SRob Clark #define REG_A2XX_SQ_PS_CONST 0x00002308 1720902e6eb8SRob Clark #define A2XX_SQ_PS_CONST_BASE__MASK 0x000001ff 1721902e6eb8SRob Clark #define A2XX_SQ_PS_CONST_BASE__SHIFT 0 1722902e6eb8SRob Clark static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val) 1723902e6eb8SRob Clark { 1724902e6eb8SRob Clark return ((val) << A2XX_SQ_PS_CONST_BASE__SHIFT) & A2XX_SQ_PS_CONST_BASE__MASK; 1725902e6eb8SRob Clark } 1726902e6eb8SRob Clark #define A2XX_SQ_PS_CONST_SIZE__MASK 0x001ff000 1727902e6eb8SRob Clark #define A2XX_SQ_PS_CONST_SIZE__SHIFT 12 1728902e6eb8SRob Clark static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val) 1729902e6eb8SRob Clark { 1730902e6eb8SRob Clark return ((val) << A2XX_SQ_PS_CONST_SIZE__SHIFT) & A2XX_SQ_PS_CONST_SIZE__MASK; 1731902e6eb8SRob Clark } 1732902e6eb8SRob Clark 1733902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_MISC_0 0x00002309 1734902e6eb8SRob Clark 1735902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_MISC_1 0x0000230a 1736902e6eb8SRob Clark 1737902e6eb8SRob Clark #define REG_A2XX_PA_SC_AA_MASK 0x00002312 1738902e6eb8SRob Clark 1739902e6eb8SRob Clark #define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL 0x00002316 174052260ae4SRob Clark #define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK 0x00000007 174152260ae4SRob Clark #define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT 0 174252260ae4SRob Clark static inline uint32_t A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH(uint32_t val) 174352260ae4SRob Clark { 174452260ae4SRob Clark return ((val) << A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT) & A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK; 174552260ae4SRob Clark } 1746902e6eb8SRob Clark 1747902e6eb8SRob Clark #define REG_A2XX_VGT_OUT_DEALLOC_CNTL 0x00002317 174852260ae4SRob Clark #define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK 0x00000003 174952260ae4SRob Clark #define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT 0 175052260ae4SRob Clark static inline uint32_t A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST(uint32_t val) 175152260ae4SRob Clark { 175252260ae4SRob Clark return ((val) << A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT) & A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK; 175352260ae4SRob Clark } 1754902e6eb8SRob Clark 1755902e6eb8SRob Clark #define REG_A2XX_RB_COPY_CONTROL 0x00002318 1756902e6eb8SRob Clark #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK 0x00000007 1757902e6eb8SRob Clark #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT 0 1758902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val) 1759902e6eb8SRob Clark { 1760902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT) & A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK; 1761902e6eb8SRob Clark } 1762902e6eb8SRob Clark #define A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE 0x00000008 1763902e6eb8SRob Clark #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK 0x000000f0 1764902e6eb8SRob Clark #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT 4 1765902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val) 1766902e6eb8SRob Clark { 1767902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT) & A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK; 1768902e6eb8SRob Clark } 1769902e6eb8SRob Clark 1770902e6eb8SRob Clark #define REG_A2XX_RB_COPY_DEST_BASE 0x00002319 1771902e6eb8SRob Clark 1772902e6eb8SRob Clark #define REG_A2XX_RB_COPY_DEST_PITCH 0x0000231a 1773902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_PITCH__MASK 0xffffffff 1774902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_PITCH__SHIFT 0 1775902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val) 1776902e6eb8SRob Clark { 1777902e6eb8SRob Clark return ((val >> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK; 1778902e6eb8SRob Clark } 1779902e6eb8SRob Clark 1780902e6eb8SRob Clark #define REG_A2XX_RB_COPY_DEST_INFO 0x0000231b 1781902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK 0x00000007 1782902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT 0 1783902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val) 1784902e6eb8SRob Clark { 1785902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT) & A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK; 1786902e6eb8SRob Clark } 1787902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_LINEAR 0x00000008 1788902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000f0 1789902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 4 1790902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val) 1791902e6eb8SRob Clark { 1792902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A2XX_RB_COPY_DEST_INFO_FORMAT__MASK; 1793902e6eb8SRob Clark } 1794902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 1795902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 1796902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val) 1797902e6eb8SRob Clark { 1798902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A2XX_RB_COPY_DEST_INFO_SWAP__MASK; 1799902e6eb8SRob Clark } 1800902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 1801902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 1802902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 1803902e6eb8SRob Clark { 1804902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 1805902e6eb8SRob Clark } 1806902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK 0x00003000 1807902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT 12 1808902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val) 1809902e6eb8SRob Clark { 1810902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK; 1811902e6eb8SRob Clark } 1812902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_WRITE_RED 0x00004000 1813902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_WRITE_GREEN 0x00008000 1814902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_WRITE_BLUE 0x00010000 1815902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA 0x00020000 1816902e6eb8SRob Clark 1817902e6eb8SRob Clark #define REG_A2XX_RB_COPY_DEST_OFFSET 0x0000231c 1818902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_OFFSET_X__MASK 0x00001fff 1819902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_OFFSET_X__SHIFT 0 1820902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val) 1821902e6eb8SRob Clark { 1822902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_DEST_OFFSET_X__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_X__MASK; 1823902e6eb8SRob Clark } 1824902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_OFFSET_Y__MASK 0x03ffe000 1825902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT 13 1826902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val) 1827902e6eb8SRob Clark { 1828902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_Y__MASK; 1829902e6eb8SRob Clark } 1830902e6eb8SRob Clark 1831902e6eb8SRob Clark #define REG_A2XX_RB_DEPTH_CLEAR 0x0000231d 1832902e6eb8SRob Clark 1833902e6eb8SRob Clark #define REG_A2XX_RB_SAMPLE_COUNT_CTL 0x00002324 1834902e6eb8SRob Clark 1835902e6eb8SRob Clark #define REG_A2XX_RB_COLOR_DEST_MASK 0x00002326 1836902e6eb8SRob Clark 1837902e6eb8SRob Clark #define REG_A2XX_A225_GRAS_UCP0X 0x00002340 1838902e6eb8SRob Clark 1839902e6eb8SRob Clark #define REG_A2XX_A225_GRAS_UCP5W 0x00002357 1840902e6eb8SRob Clark 1841902e6eb8SRob Clark #define REG_A2XX_A225_GRAS_UCP_ENABLED 0x00002360 1842902e6eb8SRob Clark 1843902e6eb8SRob Clark #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE 0x00002380 1844902e6eb8SRob Clark 1845902e6eb8SRob Clark #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET 0x00002383 1846902e6eb8SRob Clark 1847902e6eb8SRob Clark #define REG_A2XX_SQ_CONSTANT_0 0x00004000 1848902e6eb8SRob Clark 1849902e6eb8SRob Clark #define REG_A2XX_SQ_FETCH_0 0x00004800 1850902e6eb8SRob Clark 1851902e6eb8SRob Clark #define REG_A2XX_SQ_CF_BOOLEANS 0x00004900 1852902e6eb8SRob Clark 1853902e6eb8SRob Clark #define REG_A2XX_SQ_CF_LOOP 0x00004908 1854902e6eb8SRob Clark 1855902e6eb8SRob Clark #define REG_A2XX_COHER_SIZE_PM4 0x00000a29 1856902e6eb8SRob Clark 1857902e6eb8SRob Clark #define REG_A2XX_COHER_BASE_PM4 0x00000a2a 1858902e6eb8SRob Clark 1859902e6eb8SRob Clark #define REG_A2XX_COHER_STATUS_PM4 0x00000a2b 1860902e6eb8SRob Clark 1861902e6eb8SRob Clark #define REG_A2XX_SQ_TEX_0 0x00000000 1862ccdf7e28SRob Clark #define A2XX_SQ_TEX_0_TYPE__MASK 0x00000003 1863ccdf7e28SRob Clark #define A2XX_SQ_TEX_0_TYPE__SHIFT 0 1864ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_0_TYPE(enum sq_tex_type val) 1865ccdf7e28SRob Clark { 1866ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_0_TYPE__SHIFT) & A2XX_SQ_TEX_0_TYPE__MASK; 1867ccdf7e28SRob Clark } 1868ccdf7e28SRob Clark #define A2XX_SQ_TEX_0_SIGN_X__MASK 0x0000000c 1869ccdf7e28SRob Clark #define A2XX_SQ_TEX_0_SIGN_X__SHIFT 2 1870ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_0_SIGN_X(enum sq_tex_sign val) 1871ccdf7e28SRob Clark { 1872ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_0_SIGN_X__SHIFT) & A2XX_SQ_TEX_0_SIGN_X__MASK; 1873ccdf7e28SRob Clark } 1874ccdf7e28SRob Clark #define A2XX_SQ_TEX_0_SIGN_Y__MASK 0x00000030 1875ccdf7e28SRob Clark #define A2XX_SQ_TEX_0_SIGN_Y__SHIFT 4 1876ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_0_SIGN_Y(enum sq_tex_sign val) 1877ccdf7e28SRob Clark { 1878ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_0_SIGN_Y__SHIFT) & A2XX_SQ_TEX_0_SIGN_Y__MASK; 1879ccdf7e28SRob Clark } 1880ccdf7e28SRob Clark #define A2XX_SQ_TEX_0_SIGN_Z__MASK 0x000000c0 1881ccdf7e28SRob Clark #define A2XX_SQ_TEX_0_SIGN_Z__SHIFT 6 1882ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_0_SIGN_Z(enum sq_tex_sign val) 1883ccdf7e28SRob Clark { 1884ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_0_SIGN_Z__SHIFT) & A2XX_SQ_TEX_0_SIGN_Z__MASK; 1885ccdf7e28SRob Clark } 1886ccdf7e28SRob Clark #define A2XX_SQ_TEX_0_SIGN_W__MASK 0x00000300 1887ccdf7e28SRob Clark #define A2XX_SQ_TEX_0_SIGN_W__SHIFT 8 1888ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_0_SIGN_W(enum sq_tex_sign val) 1889ccdf7e28SRob Clark { 1890ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_0_SIGN_W__SHIFT) & A2XX_SQ_TEX_0_SIGN_W__MASK; 1891ccdf7e28SRob Clark } 1892902e6eb8SRob Clark #define A2XX_SQ_TEX_0_CLAMP_X__MASK 0x00001c00 1893902e6eb8SRob Clark #define A2XX_SQ_TEX_0_CLAMP_X__SHIFT 10 1894902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val) 1895902e6eb8SRob Clark { 1896902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_0_CLAMP_X__SHIFT) & A2XX_SQ_TEX_0_CLAMP_X__MASK; 1897902e6eb8SRob Clark } 1898902e6eb8SRob Clark #define A2XX_SQ_TEX_0_CLAMP_Y__MASK 0x0000e000 1899902e6eb8SRob Clark #define A2XX_SQ_TEX_0_CLAMP_Y__SHIFT 13 1900902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val) 1901902e6eb8SRob Clark { 1902902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_0_CLAMP_Y__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Y__MASK; 1903902e6eb8SRob Clark } 1904902e6eb8SRob Clark #define A2XX_SQ_TEX_0_CLAMP_Z__MASK 0x00070000 1905902e6eb8SRob Clark #define A2XX_SQ_TEX_0_CLAMP_Z__SHIFT 16 1906902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val) 1907902e6eb8SRob Clark { 1908902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK; 1909902e6eb8SRob Clark } 1910ccdf7e28SRob Clark #define A2XX_SQ_TEX_0_PITCH__MASK 0x7fc00000 1911902e6eb8SRob Clark #define A2XX_SQ_TEX_0_PITCH__SHIFT 22 1912902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val) 1913902e6eb8SRob Clark { 1914902e6eb8SRob Clark return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK; 1915902e6eb8SRob Clark } 1916ccdf7e28SRob Clark #define A2XX_SQ_TEX_0_TILED 0x00000002 1917902e6eb8SRob Clark 1918902e6eb8SRob Clark #define REG_A2XX_SQ_TEX_1 0x00000001 1919ccdf7e28SRob Clark #define A2XX_SQ_TEX_1_FORMAT__MASK 0x0000003f 1920ccdf7e28SRob Clark #define A2XX_SQ_TEX_1_FORMAT__SHIFT 0 1921ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_1_FORMAT(enum a2xx_sq_surfaceformat val) 1922ccdf7e28SRob Clark { 1923ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_1_FORMAT__SHIFT) & A2XX_SQ_TEX_1_FORMAT__MASK; 1924ccdf7e28SRob Clark } 1925ccdf7e28SRob Clark #define A2XX_SQ_TEX_1_ENDIANNESS__MASK 0x000000c0 1926ccdf7e28SRob Clark #define A2XX_SQ_TEX_1_ENDIANNESS__SHIFT 6 1927ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_1_ENDIANNESS(enum sq_tex_endian val) 1928ccdf7e28SRob Clark { 1929ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_1_ENDIANNESS__SHIFT) & A2XX_SQ_TEX_1_ENDIANNESS__MASK; 1930ccdf7e28SRob Clark } 1931ccdf7e28SRob Clark #define A2XX_SQ_TEX_1_REQUEST_SIZE__MASK 0x00000300 1932ccdf7e28SRob Clark #define A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT 8 1933ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_1_REQUEST_SIZE(uint32_t val) 1934ccdf7e28SRob Clark { 1935ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT) & A2XX_SQ_TEX_1_REQUEST_SIZE__MASK; 1936ccdf7e28SRob Clark } 1937ccdf7e28SRob Clark #define A2XX_SQ_TEX_1_STACKED 0x00000400 1938ccdf7e28SRob Clark #define A2XX_SQ_TEX_1_CLAMP_POLICY__MASK 0x00000800 1939ccdf7e28SRob Clark #define A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT 11 1940ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_1_CLAMP_POLICY(enum sq_tex_clamp_policy val) 1941ccdf7e28SRob Clark { 1942ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT) & A2XX_SQ_TEX_1_CLAMP_POLICY__MASK; 1943ccdf7e28SRob Clark } 1944ccdf7e28SRob Clark #define A2XX_SQ_TEX_1_BASE_ADDRESS__MASK 0xfffff000 1945ccdf7e28SRob Clark #define A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT 12 1946ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_1_BASE_ADDRESS(uint32_t val) 1947ccdf7e28SRob Clark { 1948ccdf7e28SRob Clark return ((val >> 12) << A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT) & A2XX_SQ_TEX_1_BASE_ADDRESS__MASK; 1949ccdf7e28SRob Clark } 1950902e6eb8SRob Clark 1951902e6eb8SRob Clark #define REG_A2XX_SQ_TEX_2 0x00000002 1952902e6eb8SRob Clark #define A2XX_SQ_TEX_2_WIDTH__MASK 0x00001fff 1953902e6eb8SRob Clark #define A2XX_SQ_TEX_2_WIDTH__SHIFT 0 1954902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val) 1955902e6eb8SRob Clark { 1956902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_2_WIDTH__SHIFT) & A2XX_SQ_TEX_2_WIDTH__MASK; 1957902e6eb8SRob Clark } 1958902e6eb8SRob Clark #define A2XX_SQ_TEX_2_HEIGHT__MASK 0x03ffe000 1959902e6eb8SRob Clark #define A2XX_SQ_TEX_2_HEIGHT__SHIFT 13 1960902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val) 1961902e6eb8SRob Clark { 1962902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK; 1963902e6eb8SRob Clark } 1964ccdf7e28SRob Clark #define A2XX_SQ_TEX_2_DEPTH__MASK 0xfc000000 1965ccdf7e28SRob Clark #define A2XX_SQ_TEX_2_DEPTH__SHIFT 26 1966ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_2_DEPTH(uint32_t val) 1967ccdf7e28SRob Clark { 1968ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_2_DEPTH__SHIFT) & A2XX_SQ_TEX_2_DEPTH__MASK; 1969ccdf7e28SRob Clark } 1970902e6eb8SRob Clark 1971902e6eb8SRob Clark #define REG_A2XX_SQ_TEX_3 0x00000003 1972ccdf7e28SRob Clark #define A2XX_SQ_TEX_3_NUM_FORMAT__MASK 0x00000001 1973ccdf7e28SRob Clark #define A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT 0 1974ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_3_NUM_FORMAT(enum sq_tex_num_format val) 1975ccdf7e28SRob Clark { 1976ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT) & A2XX_SQ_TEX_3_NUM_FORMAT__MASK; 1977ccdf7e28SRob Clark } 1978902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_X__MASK 0x0000000e 1979902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_X__SHIFT 1 1980902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val) 1981902e6eb8SRob Clark { 1982902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_3_SWIZ_X__SHIFT) & A2XX_SQ_TEX_3_SWIZ_X__MASK; 1983902e6eb8SRob Clark } 1984902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_Y__MASK 0x00000070 1985902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_Y__SHIFT 4 1986902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val) 1987902e6eb8SRob Clark { 1988902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_3_SWIZ_Y__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Y__MASK; 1989902e6eb8SRob Clark } 1990902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_Z__MASK 0x00000380 1991902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_Z__SHIFT 7 1992902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val) 1993902e6eb8SRob Clark { 1994902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_3_SWIZ_Z__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Z__MASK; 1995902e6eb8SRob Clark } 1996902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_W__MASK 0x00001c00 1997902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_W__SHIFT 10 1998902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val) 1999902e6eb8SRob Clark { 2000902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK; 2001902e6eb8SRob Clark } 2002ccdf7e28SRob Clark #define A2XX_SQ_TEX_3_EXP_ADJUST__MASK 0x0007e000 2003ccdf7e28SRob Clark #define A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT 13 2004ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_3_EXP_ADJUST(uint32_t val) 2005ccdf7e28SRob Clark { 2006ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT) & A2XX_SQ_TEX_3_EXP_ADJUST__MASK; 2007ccdf7e28SRob Clark } 2008902e6eb8SRob Clark #define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK 0x00180000 2009902e6eb8SRob Clark #define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT 19 2010902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val) 2011902e6eb8SRob Clark { 2012902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK; 2013902e6eb8SRob Clark } 2014902e6eb8SRob Clark #define A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK 0x00600000 2015902e6eb8SRob Clark #define A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT 21 2016902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val) 2017902e6eb8SRob Clark { 2018902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK; 2019902e6eb8SRob Clark } 2020ccdf7e28SRob Clark #define A2XX_SQ_TEX_3_MIP_FILTER__MASK 0x01800000 2021ccdf7e28SRob Clark #define A2XX_SQ_TEX_3_MIP_FILTER__SHIFT 23 2022ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_3_MIP_FILTER(enum sq_tex_filter val) 2023ccdf7e28SRob Clark { 2024ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_3_MIP_FILTER__SHIFT) & A2XX_SQ_TEX_3_MIP_FILTER__MASK; 2025ccdf7e28SRob Clark } 2026ccdf7e28SRob Clark #define A2XX_SQ_TEX_3_ANISO_FILTER__MASK 0x0e000000 2027ccdf7e28SRob Clark #define A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT 25 2028ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_3_ANISO_FILTER(enum sq_tex_aniso_filter val) 2029ccdf7e28SRob Clark { 2030ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT) & A2XX_SQ_TEX_3_ANISO_FILTER__MASK; 2031ccdf7e28SRob Clark } 2032ccdf7e28SRob Clark #define A2XX_SQ_TEX_3_BORDER_SIZE__MASK 0x80000000 2033ccdf7e28SRob Clark #define A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT 31 2034ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_3_BORDER_SIZE(uint32_t val) 2035ccdf7e28SRob Clark { 2036ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT) & A2XX_SQ_TEX_3_BORDER_SIZE__MASK; 2037ccdf7e28SRob Clark } 2038ccdf7e28SRob Clark 2039ccdf7e28SRob Clark #define REG_A2XX_SQ_TEX_4 0x00000004 2040ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK 0x00000001 2041ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT 0 2042ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_4_VOL_MAG_FILTER(enum sq_tex_filter val) 2043ccdf7e28SRob Clark { 2044ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK; 2045ccdf7e28SRob Clark } 2046ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK 0x00000002 2047ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT 1 2048ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_4_VOL_MIN_FILTER(enum sq_tex_filter val) 2049ccdf7e28SRob Clark { 2050ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK; 2051ccdf7e28SRob Clark } 2052ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK 0x0000003c 2053ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT 2 2054ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_4_MIP_MIN_LEVEL(uint32_t val) 2055ccdf7e28SRob Clark { 2056ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT) & A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK; 2057ccdf7e28SRob Clark } 2058ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK 0x000003c0 2059ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT 6 2060ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_4_MIP_MAX_LEVEL(uint32_t val) 2061ccdf7e28SRob Clark { 2062ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT) & A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK; 2063ccdf7e28SRob Clark } 2064ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_MAX_ANISO_WALK 0x00000400 2065ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_MIN_ANISO_WALK 0x00000800 2066ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_LOD_BIAS__MASK 0x003ff000 2067ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_LOD_BIAS__SHIFT 12 2068ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_4_LOD_BIAS(float val) 2069ccdf7e28SRob Clark { 2070ccdf7e28SRob Clark return ((((int32_t)(val * 32.0))) << A2XX_SQ_TEX_4_LOD_BIAS__SHIFT) & A2XX_SQ_TEX_4_LOD_BIAS__MASK; 2071ccdf7e28SRob Clark } 2072ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK 0x07c00000 2073ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT 22 2074ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H(uint32_t val) 2075ccdf7e28SRob Clark { 2076ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT) & A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK; 2077ccdf7e28SRob Clark } 2078ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK 0xf8000000 2079ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT 27 2080ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V(uint32_t val) 2081ccdf7e28SRob Clark { 2082ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT) & A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK; 2083ccdf7e28SRob Clark } 2084ccdf7e28SRob Clark 2085ccdf7e28SRob Clark #define REG_A2XX_SQ_TEX_5 0x00000005 2086ccdf7e28SRob Clark #define A2XX_SQ_TEX_5_BORDER_COLOR__MASK 0x00000003 2087ccdf7e28SRob Clark #define A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT 0 2088ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_5_BORDER_COLOR(enum sq_tex_border_color val) 2089ccdf7e28SRob Clark { 2090ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT) & A2XX_SQ_TEX_5_BORDER_COLOR__MASK; 2091ccdf7e28SRob Clark } 2092ccdf7e28SRob Clark #define A2XX_SQ_TEX_5_FORCE_BCW_MAX 0x00000004 2093ccdf7e28SRob Clark #define A2XX_SQ_TEX_5_TRI_CLAMP__MASK 0x00000018 2094ccdf7e28SRob Clark #define A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT 3 2095ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_5_TRI_CLAMP(uint32_t val) 2096ccdf7e28SRob Clark { 2097ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT) & A2XX_SQ_TEX_5_TRI_CLAMP__MASK; 2098ccdf7e28SRob Clark } 2099ccdf7e28SRob Clark #define A2XX_SQ_TEX_5_ANISO_BIAS__MASK 0x000001e0 2100ccdf7e28SRob Clark #define A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT 5 2101ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_5_ANISO_BIAS(float val) 2102ccdf7e28SRob Clark { 2103ccdf7e28SRob Clark return ((((int32_t)(val * 1.0))) << A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT) & A2XX_SQ_TEX_5_ANISO_BIAS__MASK; 2104ccdf7e28SRob Clark } 2105ccdf7e28SRob Clark #define A2XX_SQ_TEX_5_DIMENSION__MASK 0x00000600 2106ccdf7e28SRob Clark #define A2XX_SQ_TEX_5_DIMENSION__SHIFT 9 2107ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_5_DIMENSION(enum sq_tex_dimension val) 2108ccdf7e28SRob Clark { 2109ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_5_DIMENSION__SHIFT) & A2XX_SQ_TEX_5_DIMENSION__MASK; 2110ccdf7e28SRob Clark } 2111ccdf7e28SRob Clark #define A2XX_SQ_TEX_5_PACKED_MIPS 0x00000800 2112ccdf7e28SRob Clark #define A2XX_SQ_TEX_5_MIP_ADDRESS__MASK 0xfffff000 2113ccdf7e28SRob Clark #define A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT 12 2114ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_5_MIP_ADDRESS(uint32_t val) 2115ccdf7e28SRob Clark { 2116ccdf7e28SRob Clark return ((val >> 12) << A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT) & A2XX_SQ_TEX_5_MIP_ADDRESS__MASK; 2117ccdf7e28SRob Clark } 2118902e6eb8SRob Clark 2119902e6eb8SRob Clark 2120902e6eb8SRob Clark #endif /* A2XX_XML */ 2121