1902e6eb8SRob Clark #ifndef A2XX_XML 2902e6eb8SRob Clark #define A2XX_XML 3902e6eb8SRob Clark 4902e6eb8SRob Clark /* Autogenerated file, DO NOT EDIT manually! 5902e6eb8SRob Clark 6902e6eb8SRob Clark This file was generated by the rules-ng-ng headergen tool in this git repository: 722ba8b6bSRob Clark http://github.com/freedreno/envytools/ 822ba8b6bSRob Clark git clone https://github.com/freedreno/envytools.git 9902e6eb8SRob Clark 10902e6eb8SRob Clark The rules-ng-ng source files this header was generated from are: 11*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44) 12*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44) 13*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44) 14*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44) 15*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57) 16*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44) 17*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44) 18*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02) 19*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19) 20*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08) 21*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44) 22*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36) 23*cc4c26d4SRob Clark - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13) 24902e6eb8SRob Clark 25*cc4c26d4SRob Clark Copyright (C) 2013-2021 by the following authors: 26902e6eb8SRob Clark - Rob Clark <robdclark@gmail.com> (robclark) 27a2272e48SRob Clark - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 28902e6eb8SRob Clark 29902e6eb8SRob Clark Permission is hereby granted, free of charge, to any person obtaining 30902e6eb8SRob Clark a copy of this software and associated documentation files (the 31902e6eb8SRob Clark "Software"), to deal in the Software without restriction, including 32902e6eb8SRob Clark without limitation the rights to use, copy, modify, merge, publish, 33902e6eb8SRob Clark distribute, sublicense, and/or sell copies of the Software, and to 34902e6eb8SRob Clark permit persons to whom the Software is furnished to do so, subject to 35902e6eb8SRob Clark the following conditions: 36902e6eb8SRob Clark 37902e6eb8SRob Clark The above copyright notice and this permission notice (including the 38902e6eb8SRob Clark next paragraph) shall be included in all copies or substantial 39902e6eb8SRob Clark portions of the Software. 40902e6eb8SRob Clark 41902e6eb8SRob Clark THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 42902e6eb8SRob Clark EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 43902e6eb8SRob Clark MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 44902e6eb8SRob Clark IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 45902e6eb8SRob Clark LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 46902e6eb8SRob Clark OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 47902e6eb8SRob Clark WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 48902e6eb8SRob Clark */ 49902e6eb8SRob Clark 50902e6eb8SRob Clark 51902e6eb8SRob Clark enum a2xx_rb_dither_type { 52902e6eb8SRob Clark DITHER_PIXEL = 0, 53902e6eb8SRob Clark DITHER_SUBPIXEL = 1, 54902e6eb8SRob Clark }; 55902e6eb8SRob Clark 56902e6eb8SRob Clark enum a2xx_colorformatx { 57902e6eb8SRob Clark COLORX_4_4_4_4 = 0, 58902e6eb8SRob Clark COLORX_1_5_5_5 = 1, 59902e6eb8SRob Clark COLORX_5_6_5 = 2, 60902e6eb8SRob Clark COLORX_8 = 3, 61902e6eb8SRob Clark COLORX_8_8 = 4, 62902e6eb8SRob Clark COLORX_8_8_8_8 = 5, 63902e6eb8SRob Clark COLORX_S8_8_8_8 = 6, 64902e6eb8SRob Clark COLORX_16_FLOAT = 7, 65902e6eb8SRob Clark COLORX_16_16_FLOAT = 8, 66902e6eb8SRob Clark COLORX_16_16_16_16_FLOAT = 9, 67902e6eb8SRob Clark COLORX_32_FLOAT = 10, 68902e6eb8SRob Clark COLORX_32_32_FLOAT = 11, 69902e6eb8SRob Clark COLORX_32_32_32_32_FLOAT = 12, 70902e6eb8SRob Clark COLORX_2_3_3 = 13, 71902e6eb8SRob Clark COLORX_8_8_8 = 14, 72902e6eb8SRob Clark }; 73902e6eb8SRob Clark 74902e6eb8SRob Clark enum a2xx_sq_surfaceformat { 75902e6eb8SRob Clark FMT_1_REVERSE = 0, 76902e6eb8SRob Clark FMT_1 = 1, 77902e6eb8SRob Clark FMT_8 = 2, 78902e6eb8SRob Clark FMT_1_5_5_5 = 3, 79902e6eb8SRob Clark FMT_5_6_5 = 4, 80902e6eb8SRob Clark FMT_6_5_5 = 5, 81902e6eb8SRob Clark FMT_8_8_8_8 = 6, 82902e6eb8SRob Clark FMT_2_10_10_10 = 7, 83902e6eb8SRob Clark FMT_8_A = 8, 84902e6eb8SRob Clark FMT_8_B = 9, 85902e6eb8SRob Clark FMT_8_8 = 10, 86902e6eb8SRob Clark FMT_Cr_Y1_Cb_Y0 = 11, 87902e6eb8SRob Clark FMT_Y1_Cr_Y0_Cb = 12, 88902e6eb8SRob Clark FMT_5_5_5_1 = 13, 89902e6eb8SRob Clark FMT_8_8_8_8_A = 14, 90902e6eb8SRob Clark FMT_4_4_4_4 = 15, 912d756322SRob Clark FMT_8_8_8 = 16, 92902e6eb8SRob Clark FMT_DXT1 = 18, 93902e6eb8SRob Clark FMT_DXT2_3 = 19, 94902e6eb8SRob Clark FMT_DXT4_5 = 20, 952d756322SRob Clark FMT_10_10_10_2 = 21, 96902e6eb8SRob Clark FMT_24_8 = 22, 97902e6eb8SRob Clark FMT_16 = 24, 98902e6eb8SRob Clark FMT_16_16 = 25, 99902e6eb8SRob Clark FMT_16_16_16_16 = 26, 100902e6eb8SRob Clark FMT_16_EXPAND = 27, 101902e6eb8SRob Clark FMT_16_16_EXPAND = 28, 102902e6eb8SRob Clark FMT_16_16_16_16_EXPAND = 29, 103902e6eb8SRob Clark FMT_16_FLOAT = 30, 104902e6eb8SRob Clark FMT_16_16_FLOAT = 31, 105902e6eb8SRob Clark FMT_16_16_16_16_FLOAT = 32, 106902e6eb8SRob Clark FMT_32 = 33, 107902e6eb8SRob Clark FMT_32_32 = 34, 108902e6eb8SRob Clark FMT_32_32_32_32 = 35, 109902e6eb8SRob Clark FMT_32_FLOAT = 36, 110902e6eb8SRob Clark FMT_32_32_FLOAT = 37, 111902e6eb8SRob Clark FMT_32_32_32_32_FLOAT = 38, 1122d756322SRob Clark FMT_ATI_TC_RGB = 39, 1132d756322SRob Clark FMT_ATI_TC_RGBA = 40, 1142d756322SRob Clark FMT_ATI_TC_555_565_RGB = 41, 1152d756322SRob Clark FMT_ATI_TC_555_565_RGBA = 42, 1162d756322SRob Clark FMT_ATI_TC_RGBA_INTERP = 43, 1172d756322SRob Clark FMT_ATI_TC_555_565_RGBA_INTERP = 44, 1182d756322SRob Clark FMT_ETC1_RGBA_INTERP = 46, 1192d756322SRob Clark FMT_ETC1_RGB = 47, 1202d756322SRob Clark FMT_ETC1_RGBA = 48, 121902e6eb8SRob Clark FMT_DXN = 49, 1222d756322SRob Clark FMT_2_3_3 = 51, 123902e6eb8SRob Clark FMT_2_10_10_10_AS_16_16_16_16 = 54, 1242d756322SRob Clark FMT_10_10_10_2_AS_16_16_16_16 = 55, 125902e6eb8SRob Clark FMT_32_32_32_FLOAT = 57, 126902e6eb8SRob Clark FMT_DXT3A = 58, 127902e6eb8SRob Clark FMT_DXT5A = 59, 128902e6eb8SRob Clark FMT_CTX1 = 60, 129902e6eb8SRob Clark }; 130902e6eb8SRob Clark 131902e6eb8SRob Clark enum a2xx_sq_ps_vtx_mode { 132902e6eb8SRob Clark POSITION_1_VECTOR = 0, 133902e6eb8SRob Clark POSITION_2_VECTORS_UNUSED = 1, 134902e6eb8SRob Clark POSITION_2_VECTORS_SPRITE = 2, 135902e6eb8SRob Clark POSITION_2_VECTORS_EDGE = 3, 136902e6eb8SRob Clark POSITION_2_VECTORS_KILL = 4, 137902e6eb8SRob Clark POSITION_2_VECTORS_SPRITE_KILL = 5, 138902e6eb8SRob Clark POSITION_2_VECTORS_EDGE_KILL = 6, 139902e6eb8SRob Clark MULTIPASS = 7, 140902e6eb8SRob Clark }; 141902e6eb8SRob Clark 142902e6eb8SRob Clark enum a2xx_sq_sample_cntl { 143902e6eb8SRob Clark CENTROIDS_ONLY = 0, 144902e6eb8SRob Clark CENTERS_ONLY = 1, 145902e6eb8SRob Clark CENTROIDS_AND_CENTERS = 2, 146902e6eb8SRob Clark }; 147902e6eb8SRob Clark 148902e6eb8SRob Clark enum a2xx_dx_clip_space { 149902e6eb8SRob Clark DXCLIP_OPENGL = 0, 150902e6eb8SRob Clark DXCLIP_DIRECTX = 1, 151902e6eb8SRob Clark }; 152902e6eb8SRob Clark 153902e6eb8SRob Clark enum a2xx_pa_su_sc_polymode { 154902e6eb8SRob Clark POLY_DISABLED = 0, 155902e6eb8SRob Clark POLY_DUALMODE = 1, 156902e6eb8SRob Clark }; 157902e6eb8SRob Clark 158902e6eb8SRob Clark enum a2xx_rb_edram_mode { 159902e6eb8SRob Clark EDRAM_NOP = 0, 160902e6eb8SRob Clark COLOR_DEPTH = 4, 161902e6eb8SRob Clark DEPTH_ONLY = 5, 162902e6eb8SRob Clark EDRAM_COPY = 6, 163902e6eb8SRob Clark }; 164902e6eb8SRob Clark 165902e6eb8SRob Clark enum a2xx_pa_sc_pattern_bit_order { 166902e6eb8SRob Clark LITTLE = 0, 167902e6eb8SRob Clark BIG = 1, 168902e6eb8SRob Clark }; 169902e6eb8SRob Clark 170902e6eb8SRob Clark enum a2xx_pa_sc_auto_reset_cntl { 171902e6eb8SRob Clark NEVER = 0, 172902e6eb8SRob Clark EACH_PRIMITIVE = 1, 173902e6eb8SRob Clark EACH_PACKET = 2, 174902e6eb8SRob Clark }; 175902e6eb8SRob Clark 176902e6eb8SRob Clark enum a2xx_pa_pixcenter { 177902e6eb8SRob Clark PIXCENTER_D3D = 0, 178902e6eb8SRob Clark PIXCENTER_OGL = 1, 179902e6eb8SRob Clark }; 180902e6eb8SRob Clark 181902e6eb8SRob Clark enum a2xx_pa_roundmode { 182902e6eb8SRob Clark TRUNCATE = 0, 183902e6eb8SRob Clark ROUND = 1, 184902e6eb8SRob Clark ROUNDTOEVEN = 2, 185902e6eb8SRob Clark ROUNDTOODD = 3, 186902e6eb8SRob Clark }; 187902e6eb8SRob Clark 188902e6eb8SRob Clark enum a2xx_pa_quantmode { 189902e6eb8SRob Clark ONE_SIXTEENTH = 0, 190902e6eb8SRob Clark ONE_EIGTH = 1, 191902e6eb8SRob Clark ONE_QUARTER = 2, 192902e6eb8SRob Clark ONE_HALF = 3, 193902e6eb8SRob Clark ONE = 4, 194902e6eb8SRob Clark }; 195902e6eb8SRob Clark 196902e6eb8SRob Clark enum a2xx_rb_copy_sample_select { 197902e6eb8SRob Clark SAMPLE_0 = 0, 198902e6eb8SRob Clark SAMPLE_1 = 1, 199902e6eb8SRob Clark SAMPLE_2 = 2, 200902e6eb8SRob Clark SAMPLE_3 = 3, 201902e6eb8SRob Clark SAMPLE_01 = 4, 202902e6eb8SRob Clark SAMPLE_23 = 5, 203902e6eb8SRob Clark SAMPLE_0123 = 6, 204902e6eb8SRob Clark }; 205902e6eb8SRob Clark 20689301471SRob Clark enum a2xx_rb_blend_opcode { 207a26ae754SRob Clark BLEND2_DST_PLUS_SRC = 0, 208a26ae754SRob Clark BLEND2_SRC_MINUS_DST = 1, 209a26ae754SRob Clark BLEND2_MIN_DST_SRC = 2, 210a26ae754SRob Clark BLEND2_MAX_DST_SRC = 3, 211a26ae754SRob Clark BLEND2_DST_MINUS_SRC = 4, 212a26ae754SRob Clark BLEND2_DST_PLUS_SRC_BIAS = 5, 21389301471SRob Clark }; 21489301471SRob Clark 215c28c82e9SRob Clark enum a2xx_su_perfcnt_select { 216c28c82e9SRob Clark PERF_PAPC_PASX_REQ = 0, 217c28c82e9SRob Clark PERF_PAPC_PASX_FIRST_VECTOR = 2, 218c28c82e9SRob Clark PERF_PAPC_PASX_SECOND_VECTOR = 3, 219c28c82e9SRob Clark PERF_PAPC_PASX_FIRST_DEAD = 4, 220c28c82e9SRob Clark PERF_PAPC_PASX_SECOND_DEAD = 5, 221c28c82e9SRob Clark PERF_PAPC_PASX_VTX_KILL_DISCARD = 6, 222c28c82e9SRob Clark PERF_PAPC_PASX_VTX_NAN_DISCARD = 7, 223c28c82e9SRob Clark PERF_PAPC_PA_INPUT_PRIM = 8, 224c28c82e9SRob Clark PERF_PAPC_PA_INPUT_NULL_PRIM = 9, 225c28c82e9SRob Clark PERF_PAPC_PA_INPUT_EVENT_FLAG = 10, 226c28c82e9SRob Clark PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11, 227c28c82e9SRob Clark PERF_PAPC_PA_INPUT_END_OF_PACKET = 12, 228c28c82e9SRob Clark PERF_PAPC_CLPR_CULL_PRIM = 13, 229c28c82e9SRob Clark PERF_PAPC_CLPR_VV_CULL_PRIM = 15, 230c28c82e9SRob Clark PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17, 231c28c82e9SRob Clark PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18, 232c28c82e9SRob Clark PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19, 233c28c82e9SRob Clark PERF_PAPC_CLPR_VV_CLIP_PRIM = 21, 234c28c82e9SRob Clark PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23, 235c28c82e9SRob Clark PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24, 236c28c82e9SRob Clark PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25, 237c28c82e9SRob Clark PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26, 238c28c82e9SRob Clark PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27, 239c28c82e9SRob Clark PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28, 240c28c82e9SRob Clark PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29, 241c28c82e9SRob Clark PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30, 242c28c82e9SRob Clark PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31, 243c28c82e9SRob Clark PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32, 244c28c82e9SRob Clark PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33, 245c28c82e9SRob Clark PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34, 246c28c82e9SRob Clark PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35, 247c28c82e9SRob Clark PERF_PAPC_CLSM_NULL_PRIM = 36, 248c28c82e9SRob Clark PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37, 249c28c82e9SRob Clark PERF_PAPC_CLSM_CLIP_PRIM = 38, 250c28c82e9SRob Clark PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39, 251c28c82e9SRob Clark PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40, 252c28c82e9SRob Clark PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41, 253c28c82e9SRob Clark PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42, 254c28c82e9SRob Clark PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43, 255c28c82e9SRob Clark PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44, 256c28c82e9SRob Clark PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45, 257c28c82e9SRob Clark PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46, 258c28c82e9SRob Clark PERF_PAPC_SU_INPUT_PRIM = 47, 259c28c82e9SRob Clark PERF_PAPC_SU_INPUT_CLIP_PRIM = 48, 260c28c82e9SRob Clark PERF_PAPC_SU_INPUT_NULL_PRIM = 49, 261c28c82e9SRob Clark PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50, 262c28c82e9SRob Clark PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51, 263c28c82e9SRob Clark PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52, 264c28c82e9SRob Clark PERF_PAPC_SU_POLYMODE_FACE_CULL = 53, 265c28c82e9SRob Clark PERF_PAPC_SU_POLYMODE_BACK_CULL = 54, 266c28c82e9SRob Clark PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55, 267c28c82e9SRob Clark PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56, 268c28c82e9SRob Clark PERF_PAPC_SU_OUTPUT_PRIM = 57, 269c28c82e9SRob Clark PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58, 270c28c82e9SRob Clark PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59, 271c28c82e9SRob Clark PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60, 272c28c82e9SRob Clark PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61, 273c28c82e9SRob Clark PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62, 274c28c82e9SRob Clark PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63, 275c28c82e9SRob Clark PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64, 276c28c82e9SRob Clark PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65, 277c28c82e9SRob Clark PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66, 278c28c82e9SRob Clark PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67, 279c28c82e9SRob Clark PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68, 280c28c82e9SRob Clark PERF_PAPC_PASX_REQ_IDLE = 69, 281c28c82e9SRob Clark PERF_PAPC_PASX_REQ_BUSY = 70, 282c28c82e9SRob Clark PERF_PAPC_PASX_REQ_STALLED = 71, 283c28c82e9SRob Clark PERF_PAPC_PASX_REC_IDLE = 72, 284c28c82e9SRob Clark PERF_PAPC_PASX_REC_BUSY = 73, 285c28c82e9SRob Clark PERF_PAPC_PASX_REC_STARVED_SX = 74, 286c28c82e9SRob Clark PERF_PAPC_PASX_REC_STALLED = 75, 287c28c82e9SRob Clark PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76, 288c28c82e9SRob Clark PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77, 289c28c82e9SRob Clark PERF_PAPC_CCGSM_IDLE = 78, 290c28c82e9SRob Clark PERF_PAPC_CCGSM_BUSY = 79, 291c28c82e9SRob Clark PERF_PAPC_CCGSM_STALLED = 80, 292c28c82e9SRob Clark PERF_PAPC_CLPRIM_IDLE = 81, 293c28c82e9SRob Clark PERF_PAPC_CLPRIM_BUSY = 82, 294c28c82e9SRob Clark PERF_PAPC_CLPRIM_STALLED = 83, 295c28c82e9SRob Clark PERF_PAPC_CLPRIM_STARVED_CCGSM = 84, 296c28c82e9SRob Clark PERF_PAPC_CLIPSM_IDLE = 85, 297c28c82e9SRob Clark PERF_PAPC_CLIPSM_BUSY = 86, 298c28c82e9SRob Clark PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87, 299c28c82e9SRob Clark PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88, 300c28c82e9SRob Clark PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89, 301c28c82e9SRob Clark PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90, 302c28c82e9SRob Clark PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91, 303c28c82e9SRob Clark PERF_PAPC_CLIPGA_IDLE = 92, 304c28c82e9SRob Clark PERF_PAPC_CLIPGA_BUSY = 93, 305c28c82e9SRob Clark PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94, 306c28c82e9SRob Clark PERF_PAPC_CLIPGA_STALLED = 95, 307c28c82e9SRob Clark PERF_PAPC_CLIP_IDLE = 96, 308c28c82e9SRob Clark PERF_PAPC_CLIP_BUSY = 97, 309c28c82e9SRob Clark PERF_PAPC_SU_IDLE = 98, 310c28c82e9SRob Clark PERF_PAPC_SU_BUSY = 99, 311c28c82e9SRob Clark PERF_PAPC_SU_STARVED_CLIP = 100, 312c28c82e9SRob Clark PERF_PAPC_SU_STALLED_SC = 101, 313c28c82e9SRob Clark PERF_PAPC_SU_FACENESS_CULL = 102, 314c28c82e9SRob Clark }; 315c28c82e9SRob Clark 316c28c82e9SRob Clark enum a2xx_sc_perfcnt_select { 317c28c82e9SRob Clark SC_SR_WINDOW_VALID = 0, 318c28c82e9SRob Clark SC_CW_WINDOW_VALID = 1, 319c28c82e9SRob Clark SC_QM_WINDOW_VALID = 2, 320c28c82e9SRob Clark SC_FW_WINDOW_VALID = 3, 321c28c82e9SRob Clark SC_EZ_WINDOW_VALID = 4, 322c28c82e9SRob Clark SC_IT_WINDOW_VALID = 5, 323c28c82e9SRob Clark SC_STARVED_BY_PA = 6, 324c28c82e9SRob Clark SC_STALLED_BY_RB_TILE = 7, 325c28c82e9SRob Clark SC_STALLED_BY_RB_SAMP = 8, 326c28c82e9SRob Clark SC_STARVED_BY_RB_EZ = 9, 327c28c82e9SRob Clark SC_STALLED_BY_SAMPLE_FF = 10, 328c28c82e9SRob Clark SC_STALLED_BY_SQ = 11, 329c28c82e9SRob Clark SC_STALLED_BY_SP = 12, 330c28c82e9SRob Clark SC_TOTAL_NO_PRIMS = 13, 331c28c82e9SRob Clark SC_NON_EMPTY_PRIMS = 14, 332c28c82e9SRob Clark SC_NO_TILES_PASSING_QM = 15, 333c28c82e9SRob Clark SC_NO_PIXELS_PRE_EZ = 16, 334c28c82e9SRob Clark SC_NO_PIXELS_POST_EZ = 17, 335c28c82e9SRob Clark }; 336c28c82e9SRob Clark 337c28c82e9SRob Clark enum a2xx_vgt_perfcount_select { 338c28c82e9SRob Clark VGT_SQ_EVENT_WINDOW_ACTIVE = 0, 339c28c82e9SRob Clark VGT_SQ_SEND = 1, 340c28c82e9SRob Clark VGT_SQ_STALLED = 2, 341c28c82e9SRob Clark VGT_SQ_STARVED_BUSY = 3, 342c28c82e9SRob Clark VGT_SQ_STARVED_IDLE = 4, 343c28c82e9SRob Clark VGT_SQ_STATIC = 5, 344c28c82e9SRob Clark VGT_PA_EVENT_WINDOW_ACTIVE = 6, 345c28c82e9SRob Clark VGT_PA_CLIP_V_SEND = 7, 346c28c82e9SRob Clark VGT_PA_CLIP_V_STALLED = 8, 347c28c82e9SRob Clark VGT_PA_CLIP_V_STARVED_BUSY = 9, 348c28c82e9SRob Clark VGT_PA_CLIP_V_STARVED_IDLE = 10, 349c28c82e9SRob Clark VGT_PA_CLIP_V_STATIC = 11, 350c28c82e9SRob Clark VGT_PA_CLIP_P_SEND = 12, 351c28c82e9SRob Clark VGT_PA_CLIP_P_STALLED = 13, 352c28c82e9SRob Clark VGT_PA_CLIP_P_STARVED_BUSY = 14, 353c28c82e9SRob Clark VGT_PA_CLIP_P_STARVED_IDLE = 15, 354c28c82e9SRob Clark VGT_PA_CLIP_P_STATIC = 16, 355c28c82e9SRob Clark VGT_PA_CLIP_S_SEND = 17, 356c28c82e9SRob Clark VGT_PA_CLIP_S_STALLED = 18, 357c28c82e9SRob Clark VGT_PA_CLIP_S_STARVED_BUSY = 19, 358c28c82e9SRob Clark VGT_PA_CLIP_S_STARVED_IDLE = 20, 359c28c82e9SRob Clark VGT_PA_CLIP_S_STATIC = 21, 360c28c82e9SRob Clark RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22, 361c28c82e9SRob Clark RBIU_IMMED_DATA_FIFO_STARVED = 23, 362c28c82e9SRob Clark RBIU_IMMED_DATA_FIFO_STALLED = 24, 363c28c82e9SRob Clark RBIU_DMA_REQUEST_FIFO_STARVED = 25, 364c28c82e9SRob Clark RBIU_DMA_REQUEST_FIFO_STALLED = 26, 365c28c82e9SRob Clark RBIU_DRAW_INITIATOR_FIFO_STARVED = 27, 366c28c82e9SRob Clark RBIU_DRAW_INITIATOR_FIFO_STALLED = 28, 367c28c82e9SRob Clark BIN_PRIM_NEAR_CULL = 29, 368c28c82e9SRob Clark BIN_PRIM_ZERO_CULL = 30, 369c28c82e9SRob Clark BIN_PRIM_FAR_CULL = 31, 370c28c82e9SRob Clark BIN_PRIM_BIN_CULL = 32, 371c28c82e9SRob Clark BIN_PRIM_FACE_CULL = 33, 372c28c82e9SRob Clark SPARE34 = 34, 373c28c82e9SRob Clark SPARE35 = 35, 374c28c82e9SRob Clark SPARE36 = 36, 375c28c82e9SRob Clark SPARE37 = 37, 376c28c82e9SRob Clark SPARE38 = 38, 377c28c82e9SRob Clark SPARE39 = 39, 378c28c82e9SRob Clark TE_SU_IN_VALID = 40, 379c28c82e9SRob Clark TE_SU_IN_READ = 41, 380c28c82e9SRob Clark TE_SU_IN_PRIM = 42, 381c28c82e9SRob Clark TE_SU_IN_EOP = 43, 382c28c82e9SRob Clark TE_SU_IN_NULL_PRIM = 44, 383c28c82e9SRob Clark TE_WK_IN_VALID = 45, 384c28c82e9SRob Clark TE_WK_IN_READ = 46, 385c28c82e9SRob Clark TE_OUT_PRIM_VALID = 47, 386c28c82e9SRob Clark TE_OUT_PRIM_READ = 48, 387c28c82e9SRob Clark }; 388c28c82e9SRob Clark 389c28c82e9SRob Clark enum a2xx_tcr_perfcount_select { 390c28c82e9SRob Clark DGMMPD_IPMUX0_STALL = 0, 391c28c82e9SRob Clark DGMMPD_IPMUX_ALL_STALL = 4, 392c28c82e9SRob Clark OPMUX0_L2_WRITES = 5, 393c28c82e9SRob Clark }; 394c28c82e9SRob Clark 395c28c82e9SRob Clark enum a2xx_tp_perfcount_select { 396c28c82e9SRob Clark POINT_QUADS = 0, 397c28c82e9SRob Clark BILIN_QUADS = 1, 398c28c82e9SRob Clark ANISO_QUADS = 2, 399c28c82e9SRob Clark MIP_QUADS = 3, 400c28c82e9SRob Clark VOL_QUADS = 4, 401c28c82e9SRob Clark MIP_VOL_QUADS = 5, 402c28c82e9SRob Clark MIP_ANISO_QUADS = 6, 403c28c82e9SRob Clark VOL_ANISO_QUADS = 7, 404c28c82e9SRob Clark ANISO_2_1_QUADS = 8, 405c28c82e9SRob Clark ANISO_4_1_QUADS = 9, 406c28c82e9SRob Clark ANISO_6_1_QUADS = 10, 407c28c82e9SRob Clark ANISO_8_1_QUADS = 11, 408c28c82e9SRob Clark ANISO_10_1_QUADS = 12, 409c28c82e9SRob Clark ANISO_12_1_QUADS = 13, 410c28c82e9SRob Clark ANISO_14_1_QUADS = 14, 411c28c82e9SRob Clark ANISO_16_1_QUADS = 15, 412c28c82e9SRob Clark MIP_VOL_ANISO_QUADS = 16, 413c28c82e9SRob Clark ALIGN_2_QUADS = 17, 414c28c82e9SRob Clark ALIGN_4_QUADS = 18, 415c28c82e9SRob Clark PIX_0_QUAD = 19, 416c28c82e9SRob Clark PIX_1_QUAD = 20, 417c28c82e9SRob Clark PIX_2_QUAD = 21, 418c28c82e9SRob Clark PIX_3_QUAD = 22, 419c28c82e9SRob Clark PIX_4_QUAD = 23, 420c28c82e9SRob Clark TP_MIPMAP_LOD0 = 24, 421c28c82e9SRob Clark TP_MIPMAP_LOD1 = 25, 422c28c82e9SRob Clark TP_MIPMAP_LOD2 = 26, 423c28c82e9SRob Clark TP_MIPMAP_LOD3 = 27, 424c28c82e9SRob Clark TP_MIPMAP_LOD4 = 28, 425c28c82e9SRob Clark TP_MIPMAP_LOD5 = 29, 426c28c82e9SRob Clark TP_MIPMAP_LOD6 = 30, 427c28c82e9SRob Clark TP_MIPMAP_LOD7 = 31, 428c28c82e9SRob Clark TP_MIPMAP_LOD8 = 32, 429c28c82e9SRob Clark TP_MIPMAP_LOD9 = 33, 430c28c82e9SRob Clark TP_MIPMAP_LOD10 = 34, 431c28c82e9SRob Clark TP_MIPMAP_LOD11 = 35, 432c28c82e9SRob Clark TP_MIPMAP_LOD12 = 36, 433c28c82e9SRob Clark TP_MIPMAP_LOD13 = 37, 434c28c82e9SRob Clark TP_MIPMAP_LOD14 = 38, 435c28c82e9SRob Clark }; 436c28c82e9SRob Clark 437c28c82e9SRob Clark enum a2xx_tcm_perfcount_select { 438c28c82e9SRob Clark QUAD0_RD_LAT_FIFO_EMPTY = 0, 439c28c82e9SRob Clark QUAD0_RD_LAT_FIFO_4TH_FULL = 3, 440c28c82e9SRob Clark QUAD0_RD_LAT_FIFO_HALF_FULL = 4, 441c28c82e9SRob Clark QUAD0_RD_LAT_FIFO_FULL = 5, 442c28c82e9SRob Clark QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6, 443c28c82e9SRob Clark READ_STARVED_QUAD0 = 28, 444c28c82e9SRob Clark READ_STARVED = 32, 445c28c82e9SRob Clark READ_STALLED_QUAD0 = 33, 446c28c82e9SRob Clark READ_STALLED = 37, 447c28c82e9SRob Clark VALID_READ_QUAD0 = 38, 448c28c82e9SRob Clark TC_TP_STARVED_QUAD0 = 42, 449c28c82e9SRob Clark TC_TP_STARVED = 46, 450c28c82e9SRob Clark }; 451c28c82e9SRob Clark 452c28c82e9SRob Clark enum a2xx_tcf_perfcount_select { 453c28c82e9SRob Clark VALID_CYCLES = 0, 454c28c82e9SRob Clark SINGLE_PHASES = 1, 455c28c82e9SRob Clark ANISO_PHASES = 2, 456c28c82e9SRob Clark MIP_PHASES = 3, 457c28c82e9SRob Clark VOL_PHASES = 4, 458c28c82e9SRob Clark MIP_VOL_PHASES = 5, 459c28c82e9SRob Clark MIP_ANISO_PHASES = 6, 460c28c82e9SRob Clark VOL_ANISO_PHASES = 7, 461c28c82e9SRob Clark ANISO_2_1_PHASES = 8, 462c28c82e9SRob Clark ANISO_4_1_PHASES = 9, 463c28c82e9SRob Clark ANISO_6_1_PHASES = 10, 464c28c82e9SRob Clark ANISO_8_1_PHASES = 11, 465c28c82e9SRob Clark ANISO_10_1_PHASES = 12, 466c28c82e9SRob Clark ANISO_12_1_PHASES = 13, 467c28c82e9SRob Clark ANISO_14_1_PHASES = 14, 468c28c82e9SRob Clark ANISO_16_1_PHASES = 15, 469c28c82e9SRob Clark MIP_VOL_ANISO_PHASES = 16, 470c28c82e9SRob Clark ALIGN_2_PHASES = 17, 471c28c82e9SRob Clark ALIGN_4_PHASES = 18, 472c28c82e9SRob Clark TPC_BUSY = 19, 473c28c82e9SRob Clark TPC_STALLED = 20, 474c28c82e9SRob Clark TPC_STARVED = 21, 475c28c82e9SRob Clark TPC_WORKING = 22, 476c28c82e9SRob Clark TPC_WALKER_BUSY = 23, 477c28c82e9SRob Clark TPC_WALKER_STALLED = 24, 478c28c82e9SRob Clark TPC_WALKER_WORKING = 25, 479c28c82e9SRob Clark TPC_ALIGNER_BUSY = 26, 480c28c82e9SRob Clark TPC_ALIGNER_STALLED = 27, 481c28c82e9SRob Clark TPC_ALIGNER_STALLED_BY_BLEND = 28, 482c28c82e9SRob Clark TPC_ALIGNER_STALLED_BY_CACHE = 29, 483c28c82e9SRob Clark TPC_ALIGNER_WORKING = 30, 484c28c82e9SRob Clark TPC_BLEND_BUSY = 31, 485c28c82e9SRob Clark TPC_BLEND_SYNC = 32, 486c28c82e9SRob Clark TPC_BLEND_STARVED = 33, 487c28c82e9SRob Clark TPC_BLEND_WORKING = 34, 488c28c82e9SRob Clark OPCODE_0x00 = 35, 489c28c82e9SRob Clark OPCODE_0x01 = 36, 490c28c82e9SRob Clark OPCODE_0x04 = 37, 491c28c82e9SRob Clark OPCODE_0x10 = 38, 492c28c82e9SRob Clark OPCODE_0x11 = 39, 493c28c82e9SRob Clark OPCODE_0x12 = 40, 494c28c82e9SRob Clark OPCODE_0x13 = 41, 495c28c82e9SRob Clark OPCODE_0x18 = 42, 496c28c82e9SRob Clark OPCODE_0x19 = 43, 497c28c82e9SRob Clark OPCODE_0x1A = 44, 498c28c82e9SRob Clark OPCODE_OTHER = 45, 499c28c82e9SRob Clark IN_FIFO_0_EMPTY = 56, 500c28c82e9SRob Clark IN_FIFO_0_LT_HALF_FULL = 57, 501c28c82e9SRob Clark IN_FIFO_0_HALF_FULL = 58, 502c28c82e9SRob Clark IN_FIFO_0_FULL = 59, 503c28c82e9SRob Clark IN_FIFO_TPC_EMPTY = 72, 504c28c82e9SRob Clark IN_FIFO_TPC_LT_HALF_FULL = 73, 505c28c82e9SRob Clark IN_FIFO_TPC_HALF_FULL = 74, 506c28c82e9SRob Clark IN_FIFO_TPC_FULL = 75, 507c28c82e9SRob Clark TPC_TC_XFC = 76, 508c28c82e9SRob Clark TPC_TC_STATE = 77, 509c28c82e9SRob Clark TC_STALL = 78, 510c28c82e9SRob Clark QUAD0_TAPS = 79, 511c28c82e9SRob Clark QUADS = 83, 512c28c82e9SRob Clark TCA_SYNC_STALL = 84, 513c28c82e9SRob Clark TAG_STALL = 85, 514c28c82e9SRob Clark TCB_SYNC_STALL = 88, 515c28c82e9SRob Clark TCA_VALID = 89, 516c28c82e9SRob Clark PROBES_VALID = 90, 517c28c82e9SRob Clark MISS_STALL = 91, 518c28c82e9SRob Clark FETCH_FIFO_STALL = 92, 519c28c82e9SRob Clark TCO_STALL = 93, 520c28c82e9SRob Clark ANY_STALL = 94, 521c28c82e9SRob Clark TAG_MISSES = 95, 522c28c82e9SRob Clark TAG_HITS = 96, 523c28c82e9SRob Clark SUB_TAG_MISSES = 97, 524c28c82e9SRob Clark SET0_INVALIDATES = 98, 525c28c82e9SRob Clark SET1_INVALIDATES = 99, 526c28c82e9SRob Clark SET2_INVALIDATES = 100, 527c28c82e9SRob Clark SET3_INVALIDATES = 101, 528c28c82e9SRob Clark SET0_TAG_MISSES = 102, 529c28c82e9SRob Clark SET1_TAG_MISSES = 103, 530c28c82e9SRob Clark SET2_TAG_MISSES = 104, 531c28c82e9SRob Clark SET3_TAG_MISSES = 105, 532c28c82e9SRob Clark SET0_TAG_HITS = 106, 533c28c82e9SRob Clark SET1_TAG_HITS = 107, 534c28c82e9SRob Clark SET2_TAG_HITS = 108, 535c28c82e9SRob Clark SET3_TAG_HITS = 109, 536c28c82e9SRob Clark SET0_SUB_TAG_MISSES = 110, 537c28c82e9SRob Clark SET1_SUB_TAG_MISSES = 111, 538c28c82e9SRob Clark SET2_SUB_TAG_MISSES = 112, 539c28c82e9SRob Clark SET3_SUB_TAG_MISSES = 113, 540c28c82e9SRob Clark SET0_EVICT1 = 114, 541c28c82e9SRob Clark SET0_EVICT2 = 115, 542c28c82e9SRob Clark SET0_EVICT3 = 116, 543c28c82e9SRob Clark SET0_EVICT4 = 117, 544c28c82e9SRob Clark SET0_EVICT5 = 118, 545c28c82e9SRob Clark SET0_EVICT6 = 119, 546c28c82e9SRob Clark SET0_EVICT7 = 120, 547c28c82e9SRob Clark SET0_EVICT8 = 121, 548c28c82e9SRob Clark SET1_EVICT1 = 130, 549c28c82e9SRob Clark SET1_EVICT2 = 131, 550c28c82e9SRob Clark SET1_EVICT3 = 132, 551c28c82e9SRob Clark SET1_EVICT4 = 133, 552c28c82e9SRob Clark SET1_EVICT5 = 134, 553c28c82e9SRob Clark SET1_EVICT6 = 135, 554c28c82e9SRob Clark SET1_EVICT7 = 136, 555c28c82e9SRob Clark SET1_EVICT8 = 137, 556c28c82e9SRob Clark SET2_EVICT1 = 146, 557c28c82e9SRob Clark SET2_EVICT2 = 147, 558c28c82e9SRob Clark SET2_EVICT3 = 148, 559c28c82e9SRob Clark SET2_EVICT4 = 149, 560c28c82e9SRob Clark SET2_EVICT5 = 150, 561c28c82e9SRob Clark SET2_EVICT6 = 151, 562c28c82e9SRob Clark SET2_EVICT7 = 152, 563c28c82e9SRob Clark SET2_EVICT8 = 153, 564c28c82e9SRob Clark SET3_EVICT1 = 162, 565c28c82e9SRob Clark SET3_EVICT2 = 163, 566c28c82e9SRob Clark SET3_EVICT3 = 164, 567c28c82e9SRob Clark SET3_EVICT4 = 165, 568c28c82e9SRob Clark SET3_EVICT5 = 166, 569c28c82e9SRob Clark SET3_EVICT6 = 167, 570c28c82e9SRob Clark SET3_EVICT7 = 168, 571c28c82e9SRob Clark SET3_EVICT8 = 169, 572c28c82e9SRob Clark FF_EMPTY = 178, 573c28c82e9SRob Clark FF_LT_HALF_FULL = 179, 574c28c82e9SRob Clark FF_HALF_FULL = 180, 575c28c82e9SRob Clark FF_FULL = 181, 576c28c82e9SRob Clark FF_XFC = 182, 577c28c82e9SRob Clark FF_STALLED = 183, 578c28c82e9SRob Clark FG_MASKS = 184, 579c28c82e9SRob Clark FG_LEFT_MASKS = 185, 580c28c82e9SRob Clark FG_LEFT_MASK_STALLED = 186, 581c28c82e9SRob Clark FG_LEFT_NOT_DONE_STALL = 187, 582c28c82e9SRob Clark FG_LEFT_FG_STALL = 188, 583c28c82e9SRob Clark FG_LEFT_SECTORS = 189, 584c28c82e9SRob Clark FG0_REQUESTS = 195, 585c28c82e9SRob Clark FG0_STALLED = 196, 586c28c82e9SRob Clark MEM_REQ512 = 199, 587c28c82e9SRob Clark MEM_REQ_SENT = 200, 588c28c82e9SRob Clark MEM_LOCAL_READ_REQ = 202, 589c28c82e9SRob Clark TC0_MH_STALLED = 203, 590c28c82e9SRob Clark }; 591c28c82e9SRob Clark 592c28c82e9SRob Clark enum a2xx_sq_perfcnt_select { 593c28c82e9SRob Clark SQ_PIXEL_VECTORS_SUB = 0, 594c28c82e9SRob Clark SQ_VERTEX_VECTORS_SUB = 1, 595c28c82e9SRob Clark SQ_ALU0_ACTIVE_VTX_SIMD0 = 2, 596c28c82e9SRob Clark SQ_ALU1_ACTIVE_VTX_SIMD0 = 3, 597c28c82e9SRob Clark SQ_ALU0_ACTIVE_PIX_SIMD0 = 4, 598c28c82e9SRob Clark SQ_ALU1_ACTIVE_PIX_SIMD0 = 5, 599c28c82e9SRob Clark SQ_ALU0_ACTIVE_VTX_SIMD1 = 6, 600c28c82e9SRob Clark SQ_ALU1_ACTIVE_VTX_SIMD1 = 7, 601c28c82e9SRob Clark SQ_ALU0_ACTIVE_PIX_SIMD1 = 8, 602c28c82e9SRob Clark SQ_ALU1_ACTIVE_PIX_SIMD1 = 9, 603c28c82e9SRob Clark SQ_EXPORT_CYCLES = 10, 604c28c82e9SRob Clark SQ_ALU_CST_WRITTEN = 11, 605c28c82e9SRob Clark SQ_TEX_CST_WRITTEN = 12, 606c28c82e9SRob Clark SQ_ALU_CST_STALL = 13, 607c28c82e9SRob Clark SQ_ALU_TEX_STALL = 14, 608c28c82e9SRob Clark SQ_INST_WRITTEN = 15, 609c28c82e9SRob Clark SQ_BOOLEAN_WRITTEN = 16, 610c28c82e9SRob Clark SQ_LOOPS_WRITTEN = 17, 611c28c82e9SRob Clark SQ_PIXEL_SWAP_IN = 18, 612c28c82e9SRob Clark SQ_PIXEL_SWAP_OUT = 19, 613c28c82e9SRob Clark SQ_VERTEX_SWAP_IN = 20, 614c28c82e9SRob Clark SQ_VERTEX_SWAP_OUT = 21, 615c28c82e9SRob Clark SQ_ALU_VTX_INST_ISSUED = 22, 616c28c82e9SRob Clark SQ_TEX_VTX_INST_ISSUED = 23, 617c28c82e9SRob Clark SQ_VC_VTX_INST_ISSUED = 24, 618c28c82e9SRob Clark SQ_CF_VTX_INST_ISSUED = 25, 619c28c82e9SRob Clark SQ_ALU_PIX_INST_ISSUED = 26, 620c28c82e9SRob Clark SQ_TEX_PIX_INST_ISSUED = 27, 621c28c82e9SRob Clark SQ_VC_PIX_INST_ISSUED = 28, 622c28c82e9SRob Clark SQ_CF_PIX_INST_ISSUED = 29, 623c28c82e9SRob Clark SQ_ALU0_FIFO_EMPTY_SIMD0 = 30, 624c28c82e9SRob Clark SQ_ALU1_FIFO_EMPTY_SIMD0 = 31, 625c28c82e9SRob Clark SQ_ALU0_FIFO_EMPTY_SIMD1 = 32, 626c28c82e9SRob Clark SQ_ALU1_FIFO_EMPTY_SIMD1 = 33, 627c28c82e9SRob Clark SQ_ALU_NOPS = 34, 628c28c82e9SRob Clark SQ_PRED_SKIP = 35, 629c28c82e9SRob Clark SQ_SYNC_ALU_STALL_SIMD0_VTX = 36, 630c28c82e9SRob Clark SQ_SYNC_ALU_STALL_SIMD1_VTX = 37, 631c28c82e9SRob Clark SQ_SYNC_TEX_STALL_VTX = 38, 632c28c82e9SRob Clark SQ_SYNC_VC_STALL_VTX = 39, 633c28c82e9SRob Clark SQ_CONSTANTS_USED_SIMD0 = 40, 634c28c82e9SRob Clark SQ_CONSTANTS_SENT_SP_SIMD0 = 41, 635c28c82e9SRob Clark SQ_GPR_STALL_VTX = 42, 636c28c82e9SRob Clark SQ_GPR_STALL_PIX = 43, 637c28c82e9SRob Clark SQ_VTX_RS_STALL = 44, 638c28c82e9SRob Clark SQ_PIX_RS_STALL = 45, 639c28c82e9SRob Clark SQ_SX_PC_FULL = 46, 640c28c82e9SRob Clark SQ_SX_EXP_BUFF_FULL = 47, 641c28c82e9SRob Clark SQ_SX_POS_BUFF_FULL = 48, 642c28c82e9SRob Clark SQ_INTERP_QUADS = 49, 643c28c82e9SRob Clark SQ_INTERP_ACTIVE = 50, 644c28c82e9SRob Clark SQ_IN_PIXEL_STALL = 51, 645c28c82e9SRob Clark SQ_IN_VTX_STALL = 52, 646c28c82e9SRob Clark SQ_VTX_CNT = 53, 647c28c82e9SRob Clark SQ_VTX_VECTOR2 = 54, 648c28c82e9SRob Clark SQ_VTX_VECTOR3 = 55, 649c28c82e9SRob Clark SQ_VTX_VECTOR4 = 56, 650c28c82e9SRob Clark SQ_PIXEL_VECTOR1 = 57, 651c28c82e9SRob Clark SQ_PIXEL_VECTOR23 = 58, 652c28c82e9SRob Clark SQ_PIXEL_VECTOR4 = 59, 653c28c82e9SRob Clark SQ_CONSTANTS_USED_SIMD1 = 60, 654c28c82e9SRob Clark SQ_CONSTANTS_SENT_SP_SIMD1 = 61, 655c28c82e9SRob Clark SQ_SX_MEM_EXP_FULL = 62, 656c28c82e9SRob Clark SQ_ALU0_ACTIVE_VTX_SIMD2 = 63, 657c28c82e9SRob Clark SQ_ALU1_ACTIVE_VTX_SIMD2 = 64, 658c28c82e9SRob Clark SQ_ALU0_ACTIVE_PIX_SIMD2 = 65, 659c28c82e9SRob Clark SQ_ALU1_ACTIVE_PIX_SIMD2 = 66, 660c28c82e9SRob Clark SQ_ALU0_ACTIVE_VTX_SIMD3 = 67, 661c28c82e9SRob Clark SQ_PERFCOUNT_VTX_QUAL_TP_DONE = 68, 662c28c82e9SRob Clark SQ_ALU0_ACTIVE_PIX_SIMD3 = 69, 663c28c82e9SRob Clark SQ_PERFCOUNT_PIX_QUAL_TP_DONE = 70, 664c28c82e9SRob Clark SQ_ALU0_FIFO_EMPTY_SIMD2 = 71, 665c28c82e9SRob Clark SQ_ALU1_FIFO_EMPTY_SIMD2 = 72, 666c28c82e9SRob Clark SQ_ALU0_FIFO_EMPTY_SIMD3 = 73, 667c28c82e9SRob Clark SQ_ALU1_FIFO_EMPTY_SIMD3 = 74, 668c28c82e9SRob Clark SQ_SYNC_ALU_STALL_SIMD2_VTX = 75, 669c28c82e9SRob Clark SQ_PERFCOUNT_VTX_POP_THREAD = 76, 670c28c82e9SRob Clark SQ_SYNC_ALU_STALL_SIMD0_PIX = 77, 671c28c82e9SRob Clark SQ_SYNC_ALU_STALL_SIMD1_PIX = 78, 672c28c82e9SRob Clark SQ_SYNC_ALU_STALL_SIMD2_PIX = 79, 673c28c82e9SRob Clark SQ_PERFCOUNT_PIX_POP_THREAD = 80, 674c28c82e9SRob Clark SQ_SYNC_TEX_STALL_PIX = 81, 675c28c82e9SRob Clark SQ_SYNC_VC_STALL_PIX = 82, 676c28c82e9SRob Clark SQ_CONSTANTS_USED_SIMD2 = 83, 677c28c82e9SRob Clark SQ_CONSTANTS_SENT_SP_SIMD2 = 84, 678c28c82e9SRob Clark SQ_PERFCOUNT_VTX_DEALLOC_ACK = 85, 679c28c82e9SRob Clark SQ_PERFCOUNT_PIX_DEALLOC_ACK = 86, 680c28c82e9SRob Clark SQ_ALU0_FIFO_FULL_SIMD0 = 87, 681c28c82e9SRob Clark SQ_ALU1_FIFO_FULL_SIMD0 = 88, 682c28c82e9SRob Clark SQ_ALU0_FIFO_FULL_SIMD1 = 89, 683c28c82e9SRob Clark SQ_ALU1_FIFO_FULL_SIMD1 = 90, 684c28c82e9SRob Clark SQ_ALU0_FIFO_FULL_SIMD2 = 91, 685c28c82e9SRob Clark SQ_ALU1_FIFO_FULL_SIMD2 = 92, 686c28c82e9SRob Clark SQ_ALU0_FIFO_FULL_SIMD3 = 93, 687c28c82e9SRob Clark SQ_ALU1_FIFO_FULL_SIMD3 = 94, 688c28c82e9SRob Clark VC_PERF_STATIC = 95, 689c28c82e9SRob Clark VC_PERF_STALLED = 96, 690c28c82e9SRob Clark VC_PERF_STARVED = 97, 691c28c82e9SRob Clark VC_PERF_SEND = 98, 692c28c82e9SRob Clark VC_PERF_ACTUAL_STARVED = 99, 693c28c82e9SRob Clark PIXEL_THREAD_0_ACTIVE = 100, 694c28c82e9SRob Clark VERTEX_THREAD_0_ACTIVE = 101, 695c28c82e9SRob Clark PIXEL_THREAD_0_NUMBER = 102, 696c28c82e9SRob Clark VERTEX_THREAD_0_NUMBER = 103, 697c28c82e9SRob Clark VERTEX_EVENT_NUMBER = 104, 698c28c82e9SRob Clark PIXEL_EVENT_NUMBER = 105, 699c28c82e9SRob Clark PTRBUFF_EF_PUSH = 106, 700c28c82e9SRob Clark PTRBUFF_EF_POP_EVENT = 107, 701c28c82e9SRob Clark PTRBUFF_EF_POP_NEW_VTX = 108, 702c28c82e9SRob Clark PTRBUFF_EF_POP_DEALLOC = 109, 703c28c82e9SRob Clark PTRBUFF_EF_POP_PVECTOR = 110, 704c28c82e9SRob Clark PTRBUFF_EF_POP_PVECTOR_X = 111, 705c28c82e9SRob Clark PTRBUFF_EF_POP_PVECTOR_VNZ = 112, 706c28c82e9SRob Clark PTRBUFF_PB_DEALLOC = 113, 707c28c82e9SRob Clark PTRBUFF_PI_STATE_PPB_POP = 114, 708c28c82e9SRob Clark PTRBUFF_PI_RTR = 115, 709c28c82e9SRob Clark PTRBUFF_PI_READ_EN = 116, 710c28c82e9SRob Clark PTRBUFF_PI_BUFF_SWAP = 117, 711c28c82e9SRob Clark PTRBUFF_SQ_FREE_BUFF = 118, 712c28c82e9SRob Clark PTRBUFF_SQ_DEC = 119, 713c28c82e9SRob Clark PTRBUFF_SC_VALID_CNTL_EVENT = 120, 714c28c82e9SRob Clark PTRBUFF_SC_VALID_IJ_XFER = 121, 715c28c82e9SRob Clark PTRBUFF_SC_NEW_VECTOR_1_Q = 122, 716c28c82e9SRob Clark PTRBUFF_QUAL_NEW_VECTOR = 123, 717c28c82e9SRob Clark PTRBUFF_QUAL_EVENT = 124, 718c28c82e9SRob Clark PTRBUFF_END_BUFFER = 125, 719c28c82e9SRob Clark PTRBUFF_FILL_QUAD = 126, 720c28c82e9SRob Clark VERTS_WRITTEN_SPI = 127, 721c28c82e9SRob Clark TP_FETCH_INSTR_EXEC = 128, 722c28c82e9SRob Clark TP_FETCH_INSTR_REQ = 129, 723c28c82e9SRob Clark TP_DATA_RETURN = 130, 724c28c82e9SRob Clark SPI_WRITE_CYCLES_SP = 131, 725c28c82e9SRob Clark SPI_WRITES_SP = 132, 726c28c82e9SRob Clark SP_ALU_INSTR_EXEC = 133, 727c28c82e9SRob Clark SP_CONST_ADDR_TO_SQ = 134, 728c28c82e9SRob Clark SP_PRED_KILLS_TO_SQ = 135, 729c28c82e9SRob Clark SP_EXPORT_CYCLES_TO_SX = 136, 730c28c82e9SRob Clark SP_EXPORTS_TO_SX = 137, 731c28c82e9SRob Clark SQ_CYCLES_ELAPSED = 138, 732c28c82e9SRob Clark SQ_TCFS_OPT_ALLOC_EXEC = 139, 733c28c82e9SRob Clark SQ_TCFS_NO_OPT_ALLOC = 140, 734c28c82e9SRob Clark SQ_ALU0_NO_OPT_ALLOC = 141, 735c28c82e9SRob Clark SQ_ALU1_NO_OPT_ALLOC = 142, 736c28c82e9SRob Clark SQ_TCFS_ARB_XFC_CNT = 143, 737c28c82e9SRob Clark SQ_ALU0_ARB_XFC_CNT = 144, 738c28c82e9SRob Clark SQ_ALU1_ARB_XFC_CNT = 145, 739c28c82e9SRob Clark SQ_TCFS_CFS_UPDATE_CNT = 146, 740c28c82e9SRob Clark SQ_ALU0_CFS_UPDATE_CNT = 147, 741c28c82e9SRob Clark SQ_ALU1_CFS_UPDATE_CNT = 148, 742c28c82e9SRob Clark SQ_VTX_PUSH_THREAD_CNT = 149, 743c28c82e9SRob Clark SQ_VTX_POP_THREAD_CNT = 150, 744c28c82e9SRob Clark SQ_PIX_PUSH_THREAD_CNT = 151, 745c28c82e9SRob Clark SQ_PIX_POP_THREAD_CNT = 152, 746c28c82e9SRob Clark SQ_PIX_TOTAL = 153, 747c28c82e9SRob Clark SQ_PIX_KILLED = 154, 748c28c82e9SRob Clark }; 749c28c82e9SRob Clark 750c28c82e9SRob Clark enum a2xx_sx_perfcnt_select { 751c28c82e9SRob Clark SX_EXPORT_VECTORS = 0, 752c28c82e9SRob Clark SX_DUMMY_QUADS = 1, 753c28c82e9SRob Clark SX_ALPHA_FAIL = 2, 754c28c82e9SRob Clark SX_RB_QUAD_BUSY = 3, 755c28c82e9SRob Clark SX_RB_COLOR_BUSY = 4, 756c28c82e9SRob Clark SX_RB_QUAD_STALL = 5, 757c28c82e9SRob Clark SX_RB_COLOR_STALL = 6, 758c28c82e9SRob Clark }; 759c28c82e9SRob Clark 760c28c82e9SRob Clark enum a2xx_rbbm_perfcount1_sel { 761c28c82e9SRob Clark RBBM1_COUNT = 0, 762c28c82e9SRob Clark RBBM1_NRT_BUSY = 1, 763c28c82e9SRob Clark RBBM1_RB_BUSY = 2, 764c28c82e9SRob Clark RBBM1_SQ_CNTX0_BUSY = 3, 765c28c82e9SRob Clark RBBM1_SQ_CNTX17_BUSY = 4, 766c28c82e9SRob Clark RBBM1_VGT_BUSY = 5, 767c28c82e9SRob Clark RBBM1_VGT_NODMA_BUSY = 6, 768c28c82e9SRob Clark RBBM1_PA_BUSY = 7, 769c28c82e9SRob Clark RBBM1_SC_CNTX_BUSY = 8, 770c28c82e9SRob Clark RBBM1_TPC_BUSY = 9, 771c28c82e9SRob Clark RBBM1_TC_BUSY = 10, 772c28c82e9SRob Clark RBBM1_SX_BUSY = 11, 773c28c82e9SRob Clark RBBM1_CP_COHER_BUSY = 12, 774c28c82e9SRob Clark RBBM1_CP_NRT_BUSY = 13, 775c28c82e9SRob Clark RBBM1_GFX_IDLE_STALL = 14, 776c28c82e9SRob Clark RBBM1_INTERRUPT = 15, 777c28c82e9SRob Clark }; 778c28c82e9SRob Clark 779c28c82e9SRob Clark enum a2xx_cp_perfcount_sel { 780c28c82e9SRob Clark ALWAYS_COUNT = 0, 781c28c82e9SRob Clark TRANS_FIFO_FULL = 1, 782c28c82e9SRob Clark TRANS_FIFO_AF = 2, 783c28c82e9SRob Clark RCIU_PFPTRANS_WAIT = 3, 784c28c82e9SRob Clark RCIU_NRTTRANS_WAIT = 6, 785c28c82e9SRob Clark CSF_NRT_READ_WAIT = 8, 786c28c82e9SRob Clark CSF_I1_FIFO_FULL = 9, 787c28c82e9SRob Clark CSF_I2_FIFO_FULL = 10, 788c28c82e9SRob Clark CSF_ST_FIFO_FULL = 11, 789c28c82e9SRob Clark CSF_RING_ROQ_FULL = 13, 790c28c82e9SRob Clark CSF_I1_ROQ_FULL = 14, 791c28c82e9SRob Clark CSF_I2_ROQ_FULL = 15, 792c28c82e9SRob Clark CSF_ST_ROQ_FULL = 16, 793c28c82e9SRob Clark MIU_TAG_MEM_FULL = 18, 794c28c82e9SRob Clark MIU_WRITECLEAN = 19, 795c28c82e9SRob Clark MIU_NRT_WRITE_STALLED = 22, 796c28c82e9SRob Clark MIU_NRT_READ_STALLED = 23, 797c28c82e9SRob Clark ME_WRITE_CONFIRM_FIFO_FULL = 24, 798c28c82e9SRob Clark ME_VS_DEALLOC_FIFO_FULL = 25, 799c28c82e9SRob Clark ME_PS_DEALLOC_FIFO_FULL = 26, 800c28c82e9SRob Clark ME_REGS_VS_EVENT_FIFO_FULL = 27, 801c28c82e9SRob Clark ME_REGS_PS_EVENT_FIFO_FULL = 28, 802c28c82e9SRob Clark ME_REGS_CF_EVENT_FIFO_FULL = 29, 803c28c82e9SRob Clark ME_MICRO_RB_STARVED = 30, 804c28c82e9SRob Clark ME_MICRO_I1_STARVED = 31, 805c28c82e9SRob Clark ME_MICRO_I2_STARVED = 32, 806c28c82e9SRob Clark ME_MICRO_ST_STARVED = 33, 807c28c82e9SRob Clark RCIU_RBBM_DWORD_SENT = 40, 808c28c82e9SRob Clark ME_BUSY_CLOCKS = 41, 809c28c82e9SRob Clark ME_WAIT_CONTEXT_AVAIL = 42, 810c28c82e9SRob Clark PFP_TYPE0_PACKET = 43, 811c28c82e9SRob Clark PFP_TYPE3_PACKET = 44, 812c28c82e9SRob Clark CSF_RB_WPTR_NEQ_RPTR = 45, 813c28c82e9SRob Clark CSF_I1_SIZE_NEQ_ZERO = 46, 814c28c82e9SRob Clark CSF_I2_SIZE_NEQ_ZERO = 47, 815c28c82e9SRob Clark CSF_RBI1I2_FETCHING = 48, 816c28c82e9SRob Clark }; 817c28c82e9SRob Clark 818c28c82e9SRob Clark enum a2xx_rb_perfcnt_select { 819c28c82e9SRob Clark RBPERF_CNTX_BUSY = 0, 820c28c82e9SRob Clark RBPERF_CNTX_BUSY_MAX = 1, 821c28c82e9SRob Clark RBPERF_SX_QUAD_STARVED = 2, 822c28c82e9SRob Clark RBPERF_SX_QUAD_STARVED_MAX = 3, 823c28c82e9SRob Clark RBPERF_GA_GC_CH0_SYS_REQ = 4, 824c28c82e9SRob Clark RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5, 825c28c82e9SRob Clark RBPERF_GA_GC_CH1_SYS_REQ = 6, 826c28c82e9SRob Clark RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7, 827c28c82e9SRob Clark RBPERF_MH_STARVED = 8, 828c28c82e9SRob Clark RBPERF_MH_STARVED_MAX = 9, 829c28c82e9SRob Clark RBPERF_AZ_BC_COLOR_BUSY = 10, 830c28c82e9SRob Clark RBPERF_AZ_BC_COLOR_BUSY_MAX = 11, 831c28c82e9SRob Clark RBPERF_AZ_BC_Z_BUSY = 12, 832c28c82e9SRob Clark RBPERF_AZ_BC_Z_BUSY_MAX = 13, 833c28c82e9SRob Clark RBPERF_RB_SC_TILE_RTR_N = 14, 834c28c82e9SRob Clark RBPERF_RB_SC_TILE_RTR_N_MAX = 15, 835c28c82e9SRob Clark RBPERF_RB_SC_SAMP_RTR_N = 16, 836c28c82e9SRob Clark RBPERF_RB_SC_SAMP_RTR_N_MAX = 17, 837c28c82e9SRob Clark RBPERF_RB_SX_QUAD_RTR_N = 18, 838c28c82e9SRob Clark RBPERF_RB_SX_QUAD_RTR_N_MAX = 19, 839c28c82e9SRob Clark RBPERF_RB_SX_COLOR_RTR_N = 20, 840c28c82e9SRob Clark RBPERF_RB_SX_COLOR_RTR_N_MAX = 21, 841c28c82e9SRob Clark RBPERF_RB_SC_SAMP_LZ_BUSY = 22, 842c28c82e9SRob Clark RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23, 843c28c82e9SRob Clark RBPERF_ZXP_STALL = 24, 844c28c82e9SRob Clark RBPERF_ZXP_STALL_MAX = 25, 845c28c82e9SRob Clark RBPERF_EVENT_PENDING = 26, 846c28c82e9SRob Clark RBPERF_EVENT_PENDING_MAX = 27, 847c28c82e9SRob Clark RBPERF_RB_MH_VALID = 28, 848c28c82e9SRob Clark RBPERF_RB_MH_VALID_MAX = 29, 849c28c82e9SRob Clark RBPERF_SX_RB_QUAD_SEND = 30, 850c28c82e9SRob Clark RBPERF_SX_RB_COLOR_SEND = 31, 851c28c82e9SRob Clark RBPERF_SC_RB_TILE_SEND = 32, 852c28c82e9SRob Clark RBPERF_SC_RB_SAMPLE_SEND = 33, 853c28c82e9SRob Clark RBPERF_SX_RB_MEM_EXPORT = 34, 854c28c82e9SRob Clark RBPERF_SX_RB_QUAD_EVENT = 35, 855c28c82e9SRob Clark RBPERF_SC_RB_TILE_EVENT_FILTERED = 36, 856c28c82e9SRob Clark RBPERF_SC_RB_TILE_EVENT_ALL = 37, 857c28c82e9SRob Clark RBPERF_RB_SC_EZ_SEND = 38, 858c28c82e9SRob Clark RBPERF_RB_SX_INDEX_SEND = 39, 859c28c82e9SRob Clark RBPERF_GMEM_INTFO_RD = 40, 860c28c82e9SRob Clark RBPERF_GMEM_INTF1_RD = 41, 861c28c82e9SRob Clark RBPERF_GMEM_INTFO_WR = 42, 862c28c82e9SRob Clark RBPERF_GMEM_INTF1_WR = 43, 863c28c82e9SRob Clark RBPERF_RB_CP_CONTEXT_DONE = 44, 864c28c82e9SRob Clark RBPERF_RB_CP_CACHE_FLUSH = 45, 865c28c82e9SRob Clark RBPERF_ZPASS_DONE = 46, 866c28c82e9SRob Clark RBPERF_ZCMD_VALID = 47, 867c28c82e9SRob Clark RBPERF_CCMD_VALID = 48, 868c28c82e9SRob Clark RBPERF_ACCUM_GRANT = 49, 869c28c82e9SRob Clark RBPERF_ACCUM_C0_GRANT = 50, 870c28c82e9SRob Clark RBPERF_ACCUM_C1_GRANT = 51, 871c28c82e9SRob Clark RBPERF_ACCUM_FULL_BE_WR = 52, 872c28c82e9SRob Clark RBPERF_ACCUM_REQUEST_NO_GRANT = 53, 873c28c82e9SRob Clark RBPERF_ACCUM_TIMEOUT_PULSE = 54, 874c28c82e9SRob Clark RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55, 875c28c82e9SRob Clark RBPERF_ACCUM_CAM_HIT_FLUSHING = 56, 876c28c82e9SRob Clark }; 877c28c82e9SRob Clark 878c28c82e9SRob Clark enum a2xx_mh_perfcnt_select { 879c28c82e9SRob Clark CP_R0_REQUESTS = 0, 880c28c82e9SRob Clark CP_R1_REQUESTS = 1, 881c28c82e9SRob Clark CP_R2_REQUESTS = 2, 882c28c82e9SRob Clark CP_R3_REQUESTS = 3, 883c28c82e9SRob Clark CP_R4_REQUESTS = 4, 884c28c82e9SRob Clark CP_TOTAL_READ_REQUESTS = 5, 885c28c82e9SRob Clark CP_TOTAL_WRITE_REQUESTS = 6, 886c28c82e9SRob Clark CP_TOTAL_REQUESTS = 7, 887c28c82e9SRob Clark CP_DATA_BYTES_WRITTEN = 8, 888c28c82e9SRob Clark CP_WRITE_CLEAN_RESPONSES = 9, 889c28c82e9SRob Clark CP_R0_READ_BURSTS_RECEIVED = 10, 890c28c82e9SRob Clark CP_R1_READ_BURSTS_RECEIVED = 11, 891c28c82e9SRob Clark CP_R2_READ_BURSTS_RECEIVED = 12, 892c28c82e9SRob Clark CP_R3_READ_BURSTS_RECEIVED = 13, 893c28c82e9SRob Clark CP_R4_READ_BURSTS_RECEIVED = 14, 894c28c82e9SRob Clark CP_TOTAL_READ_BURSTS_RECEIVED = 15, 895c28c82e9SRob Clark CP_R0_DATA_BEATS_READ = 16, 896c28c82e9SRob Clark CP_R1_DATA_BEATS_READ = 17, 897c28c82e9SRob Clark CP_R2_DATA_BEATS_READ = 18, 898c28c82e9SRob Clark CP_R3_DATA_BEATS_READ = 19, 899c28c82e9SRob Clark CP_R4_DATA_BEATS_READ = 20, 900c28c82e9SRob Clark CP_TOTAL_DATA_BEATS_READ = 21, 901c28c82e9SRob Clark VGT_R0_REQUESTS = 22, 902c28c82e9SRob Clark VGT_R1_REQUESTS = 23, 903c28c82e9SRob Clark VGT_TOTAL_REQUESTS = 24, 904c28c82e9SRob Clark VGT_R0_READ_BURSTS_RECEIVED = 25, 905c28c82e9SRob Clark VGT_R1_READ_BURSTS_RECEIVED = 26, 906c28c82e9SRob Clark VGT_TOTAL_READ_BURSTS_RECEIVED = 27, 907c28c82e9SRob Clark VGT_R0_DATA_BEATS_READ = 28, 908c28c82e9SRob Clark VGT_R1_DATA_BEATS_READ = 29, 909c28c82e9SRob Clark VGT_TOTAL_DATA_BEATS_READ = 30, 910c28c82e9SRob Clark TC_TOTAL_REQUESTS = 31, 911c28c82e9SRob Clark TC_ROQ_REQUESTS = 32, 912c28c82e9SRob Clark TC_INFO_SENT = 33, 913c28c82e9SRob Clark TC_READ_BURSTS_RECEIVED = 34, 914c28c82e9SRob Clark TC_DATA_BEATS_READ = 35, 915c28c82e9SRob Clark TCD_BURSTS_READ = 36, 916c28c82e9SRob Clark RB_REQUESTS = 37, 917c28c82e9SRob Clark RB_DATA_BYTES_WRITTEN = 38, 918c28c82e9SRob Clark RB_WRITE_CLEAN_RESPONSES = 39, 919c28c82e9SRob Clark AXI_READ_REQUESTS_ID_0 = 40, 920c28c82e9SRob Clark AXI_READ_REQUESTS_ID_1 = 41, 921c28c82e9SRob Clark AXI_READ_REQUESTS_ID_2 = 42, 922c28c82e9SRob Clark AXI_READ_REQUESTS_ID_3 = 43, 923c28c82e9SRob Clark AXI_READ_REQUESTS_ID_4 = 44, 924c28c82e9SRob Clark AXI_READ_REQUESTS_ID_5 = 45, 925c28c82e9SRob Clark AXI_READ_REQUESTS_ID_6 = 46, 926c28c82e9SRob Clark AXI_READ_REQUESTS_ID_7 = 47, 927c28c82e9SRob Clark AXI_TOTAL_READ_REQUESTS = 48, 928c28c82e9SRob Clark AXI_WRITE_REQUESTS_ID_0 = 49, 929c28c82e9SRob Clark AXI_WRITE_REQUESTS_ID_1 = 50, 930c28c82e9SRob Clark AXI_WRITE_REQUESTS_ID_2 = 51, 931c28c82e9SRob Clark AXI_WRITE_REQUESTS_ID_3 = 52, 932c28c82e9SRob Clark AXI_WRITE_REQUESTS_ID_4 = 53, 933c28c82e9SRob Clark AXI_WRITE_REQUESTS_ID_5 = 54, 934c28c82e9SRob Clark AXI_WRITE_REQUESTS_ID_6 = 55, 935c28c82e9SRob Clark AXI_WRITE_REQUESTS_ID_7 = 56, 936c28c82e9SRob Clark AXI_TOTAL_WRITE_REQUESTS = 57, 937c28c82e9SRob Clark AXI_TOTAL_REQUESTS_ID_0 = 58, 938c28c82e9SRob Clark AXI_TOTAL_REQUESTS_ID_1 = 59, 939c28c82e9SRob Clark AXI_TOTAL_REQUESTS_ID_2 = 60, 940c28c82e9SRob Clark AXI_TOTAL_REQUESTS_ID_3 = 61, 941c28c82e9SRob Clark AXI_TOTAL_REQUESTS_ID_4 = 62, 942c28c82e9SRob Clark AXI_TOTAL_REQUESTS_ID_5 = 63, 943c28c82e9SRob Clark AXI_TOTAL_REQUESTS_ID_6 = 64, 944c28c82e9SRob Clark AXI_TOTAL_REQUESTS_ID_7 = 65, 945c28c82e9SRob Clark AXI_TOTAL_REQUESTS = 66, 946c28c82e9SRob Clark AXI_READ_CHANNEL_BURSTS_ID_0 = 67, 947c28c82e9SRob Clark AXI_READ_CHANNEL_BURSTS_ID_1 = 68, 948c28c82e9SRob Clark AXI_READ_CHANNEL_BURSTS_ID_2 = 69, 949c28c82e9SRob Clark AXI_READ_CHANNEL_BURSTS_ID_3 = 70, 950c28c82e9SRob Clark AXI_READ_CHANNEL_BURSTS_ID_4 = 71, 951c28c82e9SRob Clark AXI_READ_CHANNEL_BURSTS_ID_5 = 72, 952c28c82e9SRob Clark AXI_READ_CHANNEL_BURSTS_ID_6 = 73, 953c28c82e9SRob Clark AXI_READ_CHANNEL_BURSTS_ID_7 = 74, 954c28c82e9SRob Clark AXI_READ_CHANNEL_TOTAL_BURSTS = 75, 955c28c82e9SRob Clark AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0 = 76, 956c28c82e9SRob Clark AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1 = 77, 957c28c82e9SRob Clark AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2 = 78, 958c28c82e9SRob Clark AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3 = 79, 959c28c82e9SRob Clark AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4 = 80, 960c28c82e9SRob Clark AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5 = 81, 961c28c82e9SRob Clark AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6 = 82, 962c28c82e9SRob Clark AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7 = 83, 963c28c82e9SRob Clark AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ = 84, 964c28c82e9SRob Clark AXI_WRITE_CHANNEL_BURSTS_ID_0 = 85, 965c28c82e9SRob Clark AXI_WRITE_CHANNEL_BURSTS_ID_1 = 86, 966c28c82e9SRob Clark AXI_WRITE_CHANNEL_BURSTS_ID_2 = 87, 967c28c82e9SRob Clark AXI_WRITE_CHANNEL_BURSTS_ID_3 = 88, 968c28c82e9SRob Clark AXI_WRITE_CHANNEL_BURSTS_ID_4 = 89, 969c28c82e9SRob Clark AXI_WRITE_CHANNEL_BURSTS_ID_5 = 90, 970c28c82e9SRob Clark AXI_WRITE_CHANNEL_BURSTS_ID_6 = 91, 971c28c82e9SRob Clark AXI_WRITE_CHANNEL_BURSTS_ID_7 = 92, 972c28c82e9SRob Clark AXI_WRITE_CHANNEL_TOTAL_BURSTS = 93, 973c28c82e9SRob Clark AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0 = 94, 974c28c82e9SRob Clark AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1 = 95, 975c28c82e9SRob Clark AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2 = 96, 976c28c82e9SRob Clark AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3 = 97, 977c28c82e9SRob Clark AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4 = 98, 978c28c82e9SRob Clark AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5 = 99, 979c28c82e9SRob Clark AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6 = 100, 980c28c82e9SRob Clark AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7 = 101, 981c28c82e9SRob Clark AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN = 102, 982c28c82e9SRob Clark AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0 = 103, 983c28c82e9SRob Clark AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1 = 104, 984c28c82e9SRob Clark AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2 = 105, 985c28c82e9SRob Clark AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3 = 106, 986c28c82e9SRob Clark AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4 = 107, 987c28c82e9SRob Clark AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5 = 108, 988c28c82e9SRob Clark AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6 = 109, 989c28c82e9SRob Clark AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7 = 110, 990c28c82e9SRob Clark AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES = 111, 991c28c82e9SRob Clark TOTAL_MMU_MISSES = 112, 992c28c82e9SRob Clark MMU_READ_MISSES = 113, 993c28c82e9SRob Clark MMU_WRITE_MISSES = 114, 994c28c82e9SRob Clark TOTAL_MMU_HITS = 115, 995c28c82e9SRob Clark MMU_READ_HITS = 116, 996c28c82e9SRob Clark MMU_WRITE_HITS = 117, 997c28c82e9SRob Clark SPLIT_MODE_TC_HITS = 118, 998c28c82e9SRob Clark SPLIT_MODE_TC_MISSES = 119, 999c28c82e9SRob Clark SPLIT_MODE_NON_TC_HITS = 120, 1000c28c82e9SRob Clark SPLIT_MODE_NON_TC_MISSES = 121, 1001c28c82e9SRob Clark STALL_AWAITING_TLB_MISS_FETCH = 122, 1002c28c82e9SRob Clark MMU_TLB_MISS_READ_BURSTS_RECEIVED = 123, 1003c28c82e9SRob Clark MMU_TLB_MISS_DATA_BEATS_READ = 124, 1004c28c82e9SRob Clark CP_CYCLES_HELD_OFF = 125, 1005c28c82e9SRob Clark VGT_CYCLES_HELD_OFF = 126, 1006c28c82e9SRob Clark TC_CYCLES_HELD_OFF = 127, 1007c28c82e9SRob Clark TC_ROQ_CYCLES_HELD_OFF = 128, 1008c28c82e9SRob Clark TC_CYCLES_HELD_OFF_TCD_FULL = 129, 1009c28c82e9SRob Clark RB_CYCLES_HELD_OFF = 130, 1010c28c82e9SRob Clark TOTAL_CYCLES_ANY_CLNT_HELD_OFF = 131, 1011c28c82e9SRob Clark TLB_MISS_CYCLES_HELD_OFF = 132, 1012c28c82e9SRob Clark AXI_READ_REQUEST_HELD_OFF = 133, 1013c28c82e9SRob Clark AXI_WRITE_REQUEST_HELD_OFF = 134, 1014c28c82e9SRob Clark AXI_REQUEST_HELD_OFF = 135, 1015c28c82e9SRob Clark AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT = 136, 1016c28c82e9SRob Clark AXI_WRITE_DATA_HELD_OFF = 137, 1017c28c82e9SRob Clark CP_SAME_PAGE_BANK_REQUESTS = 138, 1018c28c82e9SRob Clark VGT_SAME_PAGE_BANK_REQUESTS = 139, 1019c28c82e9SRob Clark TC_SAME_PAGE_BANK_REQUESTS = 140, 1020c28c82e9SRob Clark TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS = 141, 1021c28c82e9SRob Clark RB_SAME_PAGE_BANK_REQUESTS = 142, 1022c28c82e9SRob Clark TOTAL_SAME_PAGE_BANK_REQUESTS = 143, 1023c28c82e9SRob Clark CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 144, 1024c28c82e9SRob Clark VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 145, 1025c28c82e9SRob Clark TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 146, 1026c28c82e9SRob Clark RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 147, 1027c28c82e9SRob Clark TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT = 148, 1028c28c82e9SRob Clark TOTAL_MH_READ_REQUESTS = 149, 1029c28c82e9SRob Clark TOTAL_MH_WRITE_REQUESTS = 150, 1030c28c82e9SRob Clark TOTAL_MH_REQUESTS = 151, 1031c28c82e9SRob Clark MH_BUSY = 152, 1032c28c82e9SRob Clark CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 153, 1033c28c82e9SRob Clark VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 154, 1034c28c82e9SRob Clark TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 155, 1035c28c82e9SRob Clark RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 156, 1036c28c82e9SRob Clark TC_ROQ_N_VALID_ENTRIES = 157, 1037c28c82e9SRob Clark ARQ_N_ENTRIES = 158, 1038c28c82e9SRob Clark WDB_N_ENTRIES = 159, 1039c28c82e9SRob Clark MH_READ_LATENCY_OUTST_REQ_SUM = 160, 1040c28c82e9SRob Clark MC_READ_LATENCY_OUTST_REQ_SUM = 161, 1041c28c82e9SRob Clark MC_TOTAL_READ_REQUESTS = 162, 1042c28c82e9SRob Clark ELAPSED_CYCLES_MH_GATED_CLK = 163, 1043c28c82e9SRob Clark ELAPSED_CLK_CYCLES = 164, 1044c28c82e9SRob Clark CP_W_16B_REQUESTS = 165, 1045c28c82e9SRob Clark CP_W_32B_REQUESTS = 166, 1046c28c82e9SRob Clark TC_16B_REQUESTS = 167, 1047c28c82e9SRob Clark TC_32B_REQUESTS = 168, 1048c28c82e9SRob Clark PA_REQUESTS = 169, 1049c28c82e9SRob Clark PA_DATA_BYTES_WRITTEN = 170, 1050c28c82e9SRob Clark PA_WRITE_CLEAN_RESPONSES = 171, 1051c28c82e9SRob Clark PA_CYCLES_HELD_OFF = 172, 1052c28c82e9SRob Clark AXI_READ_REQUEST_DATA_BEATS_ID_0 = 173, 1053c28c82e9SRob Clark AXI_READ_REQUEST_DATA_BEATS_ID_1 = 174, 1054c28c82e9SRob Clark AXI_READ_REQUEST_DATA_BEATS_ID_2 = 175, 1055c28c82e9SRob Clark AXI_READ_REQUEST_DATA_BEATS_ID_3 = 176, 1056c28c82e9SRob Clark AXI_READ_REQUEST_DATA_BEATS_ID_4 = 177, 1057c28c82e9SRob Clark AXI_READ_REQUEST_DATA_BEATS_ID_5 = 178, 1058c28c82e9SRob Clark AXI_READ_REQUEST_DATA_BEATS_ID_6 = 179, 1059c28c82e9SRob Clark AXI_READ_REQUEST_DATA_BEATS_ID_7 = 180, 1060c28c82e9SRob Clark AXI_TOTAL_READ_REQUEST_DATA_BEATS = 181, 1061c28c82e9SRob Clark }; 1062c28c82e9SRob Clark 1063facb4f4eSRob Clark enum adreno_mmu_clnt_beh { 1064facb4f4eSRob Clark BEH_NEVR = 0, 1065facb4f4eSRob Clark BEH_TRAN_RNG = 1, 1066facb4f4eSRob Clark BEH_TRAN_FLT = 2, 1067facb4f4eSRob Clark }; 1068facb4f4eSRob Clark 1069902e6eb8SRob Clark enum sq_tex_clamp { 1070902e6eb8SRob Clark SQ_TEX_WRAP = 0, 1071902e6eb8SRob Clark SQ_TEX_MIRROR = 1, 1072902e6eb8SRob Clark SQ_TEX_CLAMP_LAST_TEXEL = 2, 1073902e6eb8SRob Clark SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3, 1074902e6eb8SRob Clark SQ_TEX_CLAMP_HALF_BORDER = 4, 1075902e6eb8SRob Clark SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5, 1076902e6eb8SRob Clark SQ_TEX_CLAMP_BORDER = 6, 1077902e6eb8SRob Clark SQ_TEX_MIRROR_ONCE_BORDER = 7, 1078902e6eb8SRob Clark }; 1079902e6eb8SRob Clark 1080902e6eb8SRob Clark enum sq_tex_swiz { 1081902e6eb8SRob Clark SQ_TEX_X = 0, 1082902e6eb8SRob Clark SQ_TEX_Y = 1, 1083902e6eb8SRob Clark SQ_TEX_Z = 2, 1084902e6eb8SRob Clark SQ_TEX_W = 3, 1085902e6eb8SRob Clark SQ_TEX_ZERO = 4, 1086902e6eb8SRob Clark SQ_TEX_ONE = 5, 1087902e6eb8SRob Clark }; 1088902e6eb8SRob Clark 1089902e6eb8SRob Clark enum sq_tex_filter { 1090902e6eb8SRob Clark SQ_TEX_FILTER_POINT = 0, 1091902e6eb8SRob Clark SQ_TEX_FILTER_BILINEAR = 1, 1092ccdf7e28SRob Clark SQ_TEX_FILTER_BASEMAP = 2, 1093ccdf7e28SRob Clark SQ_TEX_FILTER_USE_FETCH_CONST = 3, 1094ccdf7e28SRob Clark }; 1095ccdf7e28SRob Clark 1096ccdf7e28SRob Clark enum sq_tex_aniso_filter { 1097ccdf7e28SRob Clark SQ_TEX_ANISO_FILTER_DISABLED = 0, 1098ccdf7e28SRob Clark SQ_TEX_ANISO_FILTER_MAX_1_1 = 1, 1099ccdf7e28SRob Clark SQ_TEX_ANISO_FILTER_MAX_2_1 = 2, 1100ccdf7e28SRob Clark SQ_TEX_ANISO_FILTER_MAX_4_1 = 3, 1101ccdf7e28SRob Clark SQ_TEX_ANISO_FILTER_MAX_8_1 = 4, 1102ccdf7e28SRob Clark SQ_TEX_ANISO_FILTER_MAX_16_1 = 5, 1103ccdf7e28SRob Clark SQ_TEX_ANISO_FILTER_USE_FETCH_CONST = 7, 1104ccdf7e28SRob Clark }; 1105ccdf7e28SRob Clark 1106ccdf7e28SRob Clark enum sq_tex_dimension { 1107ccdf7e28SRob Clark SQ_TEX_DIMENSION_1D = 0, 1108ccdf7e28SRob Clark SQ_TEX_DIMENSION_2D = 1, 1109ccdf7e28SRob Clark SQ_TEX_DIMENSION_3D = 2, 1110ccdf7e28SRob Clark SQ_TEX_DIMENSION_CUBE = 3, 1111ccdf7e28SRob Clark }; 1112ccdf7e28SRob Clark 1113ccdf7e28SRob Clark enum sq_tex_border_color { 1114ccdf7e28SRob Clark SQ_TEX_BORDER_COLOR_BLACK = 0, 1115ccdf7e28SRob Clark SQ_TEX_BORDER_COLOR_WHITE = 1, 1116ccdf7e28SRob Clark SQ_TEX_BORDER_COLOR_ACBYCR_BLACK = 2, 1117ccdf7e28SRob Clark SQ_TEX_BORDER_COLOR_ACBCRY_BLACK = 3, 1118ccdf7e28SRob Clark }; 1119ccdf7e28SRob Clark 1120ccdf7e28SRob Clark enum sq_tex_sign { 1121c28c82e9SRob Clark SQ_TEX_SIGN_UNSIGNED = 0, 1122ccdf7e28SRob Clark SQ_TEX_SIGN_SIGNED = 1, 1123c28c82e9SRob Clark SQ_TEX_SIGN_UNSIGNED_BIASED = 2, 1124ccdf7e28SRob Clark SQ_TEX_SIGN_GAMMA = 3, 1125ccdf7e28SRob Clark }; 1126ccdf7e28SRob Clark 1127ccdf7e28SRob Clark enum sq_tex_endian { 1128ccdf7e28SRob Clark SQ_TEX_ENDIAN_NONE = 0, 1129ccdf7e28SRob Clark SQ_TEX_ENDIAN_8IN16 = 1, 1130ccdf7e28SRob Clark SQ_TEX_ENDIAN_8IN32 = 2, 1131ccdf7e28SRob Clark SQ_TEX_ENDIAN_16IN32 = 3, 1132ccdf7e28SRob Clark }; 1133ccdf7e28SRob Clark 1134ccdf7e28SRob Clark enum sq_tex_clamp_policy { 1135ccdf7e28SRob Clark SQ_TEX_CLAMP_POLICY_D3D = 0, 1136ccdf7e28SRob Clark SQ_TEX_CLAMP_POLICY_OGL = 1, 1137ccdf7e28SRob Clark }; 1138ccdf7e28SRob Clark 1139ccdf7e28SRob Clark enum sq_tex_num_format { 1140ccdf7e28SRob Clark SQ_TEX_NUM_FORMAT_FRAC = 0, 1141ccdf7e28SRob Clark SQ_TEX_NUM_FORMAT_INT = 1, 1142ccdf7e28SRob Clark }; 1143ccdf7e28SRob Clark 1144ccdf7e28SRob Clark enum sq_tex_type { 1145ccdf7e28SRob Clark SQ_TEX_TYPE_0 = 0, 1146ccdf7e28SRob Clark SQ_TEX_TYPE_1 = 1, 1147ccdf7e28SRob Clark SQ_TEX_TYPE_2 = 2, 1148ccdf7e28SRob Clark SQ_TEX_TYPE_3 = 3, 1149902e6eb8SRob Clark }; 1150902e6eb8SRob Clark 1151902e6eb8SRob Clark #define REG_A2XX_RBBM_PATCH_RELEASE 0x00000001 1152902e6eb8SRob Clark 1153902e6eb8SRob Clark #define REG_A2XX_RBBM_CNTL 0x0000003b 1154902e6eb8SRob Clark 1155902e6eb8SRob Clark #define REG_A2XX_RBBM_SOFT_RESET 0x0000003c 1156902e6eb8SRob Clark 1157902e6eb8SRob Clark #define REG_A2XX_CP_PFP_UCODE_ADDR 0x000000c0 1158902e6eb8SRob Clark 1159902e6eb8SRob Clark #define REG_A2XX_CP_PFP_UCODE_DATA 0x000000c1 1160902e6eb8SRob Clark 1161facb4f4eSRob Clark #define REG_A2XX_MH_MMU_CONFIG 0x00000040 1162facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_MMU_ENABLE 0x00000001 1163facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE 0x00000002 1164facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK 0x00000030 1165facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT 4 1166facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1167facb4f4eSRob Clark { 1168facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK; 1169facb4f4eSRob Clark } 1170facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK 0x000000c0 1171facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT 6 1172facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1173facb4f4eSRob Clark { 1174facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK; 1175facb4f4eSRob Clark } 1176facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK 0x00000300 1177facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT 8 1178facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1179facb4f4eSRob Clark { 1180facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK; 1181facb4f4eSRob Clark } 1182facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK 0x00000c00 1183facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT 10 1184facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1185facb4f4eSRob Clark { 1186facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK; 1187facb4f4eSRob Clark } 1188facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK 0x00003000 1189facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT 12 1190facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1191facb4f4eSRob Clark { 1192facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK; 1193facb4f4eSRob Clark } 1194facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK 0x0000c000 1195facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT 14 1196facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1197facb4f4eSRob Clark { 1198facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK; 1199facb4f4eSRob Clark } 1200facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK 0x00030000 1201facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT 16 1202facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1203facb4f4eSRob Clark { 1204facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK; 1205facb4f4eSRob Clark } 1206facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK 0x000c0000 1207facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT 18 1208facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1209facb4f4eSRob Clark { 1210facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK; 1211facb4f4eSRob Clark } 1212facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK 0x00300000 1213facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT 20 1214facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1215facb4f4eSRob Clark { 1216facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK; 1217facb4f4eSRob Clark } 1218facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK 0x00c00000 1219facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT 22 1220facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1221facb4f4eSRob Clark { 1222facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK; 1223facb4f4eSRob Clark } 1224facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK 0x03000000 1225facb4f4eSRob Clark #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT 24 1226facb4f4eSRob Clark static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1227facb4f4eSRob Clark { 1228facb4f4eSRob Clark return ((val) << A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK; 1229facb4f4eSRob Clark } 1230facb4f4eSRob Clark 1231facb4f4eSRob Clark #define REG_A2XX_MH_MMU_VA_RANGE 0x00000041 1232ccdf7e28SRob Clark #define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK 0x00000fff 1233ccdf7e28SRob Clark #define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT 0 1234ccdf7e28SRob Clark static inline uint32_t A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS(uint32_t val) 1235ccdf7e28SRob Clark { 1236ccdf7e28SRob Clark return ((val) << A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT) & A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK; 1237ccdf7e28SRob Clark } 1238ccdf7e28SRob Clark #define A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK 0xfffff000 1239ccdf7e28SRob Clark #define A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT 12 1240ccdf7e28SRob Clark static inline uint32_t A2XX_MH_MMU_VA_RANGE_VA_BASE(uint32_t val) 1241ccdf7e28SRob Clark { 1242ccdf7e28SRob Clark return ((val) << A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT) & A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK; 1243ccdf7e28SRob Clark } 1244facb4f4eSRob Clark 1245facb4f4eSRob Clark #define REG_A2XX_MH_MMU_PT_BASE 0x00000042 1246facb4f4eSRob Clark 1247facb4f4eSRob Clark #define REG_A2XX_MH_MMU_PAGE_FAULT 0x00000043 1248facb4f4eSRob Clark 1249facb4f4eSRob Clark #define REG_A2XX_MH_MMU_TRAN_ERROR 0x00000044 1250facb4f4eSRob Clark 1251facb4f4eSRob Clark #define REG_A2XX_MH_MMU_INVALIDATE 0x00000045 1252ccdf7e28SRob Clark #define A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL 0x00000001 1253ccdf7e28SRob Clark #define A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC 0x00000002 1254facb4f4eSRob Clark 1255facb4f4eSRob Clark #define REG_A2XX_MH_MMU_MPU_BASE 0x00000046 1256facb4f4eSRob Clark 1257facb4f4eSRob Clark #define REG_A2XX_MH_MMU_MPU_END 0x00000047 1258facb4f4eSRob Clark 1259facb4f4eSRob Clark #define REG_A2XX_NQWAIT_UNTIL 0x00000394 1260facb4f4eSRob Clark 1261*cc4c26d4SRob Clark #define REG_A2XX_RBBM_PERFCOUNTER0_SELECT 0x00000395 1262902e6eb8SRob Clark 1263*cc4c26d4SRob Clark #define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000396 1264902e6eb8SRob Clark 1265*cc4c26d4SRob Clark #define REG_A2XX_RBBM_PERFCOUNTER0_LO 0x00000397 1266*cc4c26d4SRob Clark 1267*cc4c26d4SRob Clark #define REG_A2XX_RBBM_PERFCOUNTER0_HI 0x00000398 1268*cc4c26d4SRob Clark 1269*cc4c26d4SRob Clark #define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000399 1270*cc4c26d4SRob Clark 1271*cc4c26d4SRob Clark #define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x0000039a 1272902e6eb8SRob Clark 1273902e6eb8SRob Clark #define REG_A2XX_RBBM_DEBUG 0x0000039b 1274902e6eb8SRob Clark 1275902e6eb8SRob Clark #define REG_A2XX_RBBM_PM_OVERRIDE1 0x0000039c 127652260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE 0x00000001 127752260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE 0x00000002 127852260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE 0x00000004 127952260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE 0x00000008 128052260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE 0x00000010 128152260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE 0x00000020 128252260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE 0x00000040 128352260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE 0x00000080 128452260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE 0x00000100 128552260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE 0x00000200 128652260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE 0x00000400 128752260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE 0x00000800 128852260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE 0x00001000 128952260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE 0x00002000 129052260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE 0x00004000 129152260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE 0x00008000 129252260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE 0x00010000 129352260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE 0x00020000 129452260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE 0x00040000 129552260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE 0x00080000 129652260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE 0x00100000 129752260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE 0x00200000 129852260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE 0x00400000 129952260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE 0x00800000 130052260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE 0x01000000 130152260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE 0x02000000 130252260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE 0x04000000 130352260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE 0x08000000 130452260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE 0x10000000 130552260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE 0x20000000 130652260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE 0x40000000 130752260ae4SRob Clark #define A2XX_RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE 0x80000000 1308902e6eb8SRob Clark 1309902e6eb8SRob Clark #define REG_A2XX_RBBM_PM_OVERRIDE2 0x0000039d 1310902e6eb8SRob Clark 1311902e6eb8SRob Clark #define REG_A2XX_RBBM_DEBUG_OUT 0x000003a0 1312902e6eb8SRob Clark 1313902e6eb8SRob Clark #define REG_A2XX_RBBM_DEBUG_CNTL 0x000003a1 1314902e6eb8SRob Clark 1315902e6eb8SRob Clark #define REG_A2XX_RBBM_READ_ERROR 0x000003b3 1316902e6eb8SRob Clark 1317902e6eb8SRob Clark #define REG_A2XX_RBBM_INT_CNTL 0x000003b4 1318ccdf7e28SRob Clark #define A2XX_RBBM_INT_CNTL_RDERR_INT_MASK 0x00000001 1319ccdf7e28SRob Clark #define A2XX_RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK 0x00000002 1320ccdf7e28SRob Clark #define A2XX_RBBM_INT_CNTL_GUI_IDLE_INT_MASK 0x00080000 1321902e6eb8SRob Clark 1322902e6eb8SRob Clark #define REG_A2XX_RBBM_INT_STATUS 0x000003b5 1323902e6eb8SRob Clark 1324902e6eb8SRob Clark #define REG_A2XX_RBBM_INT_ACK 0x000003b6 1325902e6eb8SRob Clark 1326902e6eb8SRob Clark #define REG_A2XX_MASTER_INT_SIGNAL 0x000003b7 1327ccdf7e28SRob Clark #define A2XX_MASTER_INT_SIGNAL_MH_INT_STAT 0x00000020 1328ccdf7e28SRob Clark #define A2XX_MASTER_INT_SIGNAL_SQ_INT_STAT 0x04000000 1329ccdf7e28SRob Clark #define A2XX_MASTER_INT_SIGNAL_CP_INT_STAT 0x40000000 1330ccdf7e28SRob Clark #define A2XX_MASTER_INT_SIGNAL_RBBM_INT_STAT 0x80000000 1331902e6eb8SRob Clark 1332902e6eb8SRob Clark #define REG_A2XX_RBBM_PERIPHID1 0x000003f9 1333902e6eb8SRob Clark 1334902e6eb8SRob Clark #define REG_A2XX_RBBM_PERIPHID2 0x000003fa 1335902e6eb8SRob Clark 1336902e6eb8SRob Clark #define REG_A2XX_CP_PERFMON_CNTL 0x00000444 1337902e6eb8SRob Clark 1338902e6eb8SRob Clark #define REG_A2XX_CP_PERFCOUNTER_SELECT 0x00000445 1339902e6eb8SRob Clark 1340902e6eb8SRob Clark #define REG_A2XX_CP_PERFCOUNTER_LO 0x00000446 1341902e6eb8SRob Clark 1342902e6eb8SRob Clark #define REG_A2XX_CP_PERFCOUNTER_HI 0x00000447 1343902e6eb8SRob Clark 1344902e6eb8SRob Clark #define REG_A2XX_RBBM_STATUS 0x000005d0 1345902e6eb8SRob Clark #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK 0x0000001f 1346902e6eb8SRob Clark #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT 0 1347902e6eb8SRob Clark static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val) 1348902e6eb8SRob Clark { 1349902e6eb8SRob Clark return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK; 1350902e6eb8SRob Clark } 1351902e6eb8SRob Clark #define A2XX_RBBM_STATUS_TC_BUSY 0x00000020 1352902e6eb8SRob Clark #define A2XX_RBBM_STATUS_HIRQ_PENDING 0x00000100 1353902e6eb8SRob Clark #define A2XX_RBBM_STATUS_CPRQ_PENDING 0x00000200 1354902e6eb8SRob Clark #define A2XX_RBBM_STATUS_CFRQ_PENDING 0x00000400 1355902e6eb8SRob Clark #define A2XX_RBBM_STATUS_PFRQ_PENDING 0x00000800 1356902e6eb8SRob Clark #define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA 0x00001000 1357902e6eb8SRob Clark #define A2XX_RBBM_STATUS_RBBM_WU_BUSY 0x00004000 1358902e6eb8SRob Clark #define A2XX_RBBM_STATUS_CP_NRT_BUSY 0x00010000 1359902e6eb8SRob Clark #define A2XX_RBBM_STATUS_MH_BUSY 0x00040000 1360902e6eb8SRob Clark #define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY 0x00080000 1361902e6eb8SRob Clark #define A2XX_RBBM_STATUS_SX_BUSY 0x00200000 1362902e6eb8SRob Clark #define A2XX_RBBM_STATUS_TPC_BUSY 0x00400000 1363902e6eb8SRob Clark #define A2XX_RBBM_STATUS_SC_CNTX_BUSY 0x01000000 1364902e6eb8SRob Clark #define A2XX_RBBM_STATUS_PA_BUSY 0x02000000 1365902e6eb8SRob Clark #define A2XX_RBBM_STATUS_VGT_BUSY 0x04000000 1366902e6eb8SRob Clark #define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY 0x08000000 1367902e6eb8SRob Clark #define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY 0x10000000 1368902e6eb8SRob Clark #define A2XX_RBBM_STATUS_RB_CNTX_BUSY 0x40000000 1369902e6eb8SRob Clark #define A2XX_RBBM_STATUS_GUI_ACTIVE 0x80000000 1370902e6eb8SRob Clark 137122ba8b6bSRob Clark #define REG_A2XX_MH_ARBITER_CONFIG 0x00000a40 137222ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK 0x0000003f 137322ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT 0 137422ba8b6bSRob Clark static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val) 137522ba8b6bSRob Clark { 137622ba8b6bSRob Clark return ((val) << A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK; 137722ba8b6bSRob Clark } 137822ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY 0x00000040 137922ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE 0x00000080 138022ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE 0x00000100 138122ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_L2_ARB_CONTROL 0x00000200 138222ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK 0x00001c00 138322ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT 10 138422ba8b6bSRob Clark static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val) 138522ba8b6bSRob Clark { 138622ba8b6bSRob Clark return ((val) << A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT) & A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK; 138722ba8b6bSRob Clark } 138822ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00002000 138922ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE 0x00004000 139022ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE 0x00008000 139122ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK 0x003f0000 139222ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT 16 139322ba8b6bSRob Clark static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val) 139422ba8b6bSRob Clark { 139522ba8b6bSRob Clark return ((val) << A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK; 139622ba8b6bSRob Clark } 139722ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE 0x00400000 139822ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE 0x00800000 139922ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE 0x01000000 140022ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE 0x02000000 140122ba8b6bSRob Clark #define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE 0x04000000 140222ba8b6bSRob Clark 1403ccdf7e28SRob Clark #define REG_A2XX_MH_INTERRUPT_MASK 0x00000a42 1404ccdf7e28SRob Clark #define A2XX_MH_INTERRUPT_MASK_AXI_READ_ERROR 0x00000001 1405ccdf7e28SRob Clark #define A2XX_MH_INTERRUPT_MASK_AXI_WRITE_ERROR 0x00000002 1406ccdf7e28SRob Clark #define A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT 0x00000004 1407ccdf7e28SRob Clark 1408ccdf7e28SRob Clark #define REG_A2XX_MH_INTERRUPT_STATUS 0x00000a43 1409ccdf7e28SRob Clark 1410ccdf7e28SRob Clark #define REG_A2XX_MH_INTERRUPT_CLEAR 0x00000a44 1411ccdf7e28SRob Clark 1412ccdf7e28SRob Clark #define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1 0x00000a54 1413ccdf7e28SRob Clark 1414ccdf7e28SRob Clark #define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG2 0x00000a55 1415ccdf7e28SRob Clark 1416902e6eb8SRob Clark #define REG_A2XX_A220_VSC_BIN_SIZE 0x00000c01 1417902e6eb8SRob Clark #define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 1418902e6eb8SRob Clark #define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT 0 1419902e6eb8SRob Clark static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val) 1420902e6eb8SRob Clark { 1421902e6eb8SRob Clark return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK; 1422902e6eb8SRob Clark } 1423902e6eb8SRob Clark #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 1424902e6eb8SRob Clark #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT 5 1425902e6eb8SRob Clark static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val) 1426902e6eb8SRob Clark { 1427902e6eb8SRob Clark return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK; 1428902e6eb8SRob Clark } 1429902e6eb8SRob Clark 1430902e6eb8SRob Clark static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 1431902e6eb8SRob Clark 1432902e6eb8SRob Clark static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 1433902e6eb8SRob Clark 1434902e6eb8SRob Clark static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } 1435902e6eb8SRob Clark 1436902e6eb8SRob Clark static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } 1437902e6eb8SRob Clark 1438902e6eb8SRob Clark #define REG_A2XX_PC_DEBUG_CNTL 0x00000c38 1439902e6eb8SRob Clark 1440902e6eb8SRob Clark #define REG_A2XX_PC_DEBUG_DATA 0x00000c39 1441902e6eb8SRob Clark 1442902e6eb8SRob Clark #define REG_A2XX_PA_SC_VIZ_QUERY_STATUS 0x00000c44 1443902e6eb8SRob Clark 1444902e6eb8SRob Clark #define REG_A2XX_GRAS_DEBUG_CNTL 0x00000c80 1445902e6eb8SRob Clark 1446902e6eb8SRob Clark #define REG_A2XX_PA_SU_DEBUG_CNTL 0x00000c80 1447902e6eb8SRob Clark 1448902e6eb8SRob Clark #define REG_A2XX_GRAS_DEBUG_DATA 0x00000c81 1449902e6eb8SRob Clark 1450902e6eb8SRob Clark #define REG_A2XX_PA_SU_DEBUG_DATA 0x00000c81 1451902e6eb8SRob Clark 1452902e6eb8SRob Clark #define REG_A2XX_PA_SU_FACE_DATA 0x00000c86 145352260ae4SRob Clark #define A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK 0xffffffe0 145452260ae4SRob Clark #define A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT 5 145552260ae4SRob Clark static inline uint32_t A2XX_PA_SU_FACE_DATA_BASE_ADDR(uint32_t val) 145652260ae4SRob Clark { 145752260ae4SRob Clark return ((val) << A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT) & A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK; 145852260ae4SRob Clark } 1459902e6eb8SRob Clark 1460902e6eb8SRob Clark #define REG_A2XX_SQ_GPR_MANAGEMENT 0x00000d00 146152260ae4SRob Clark #define A2XX_SQ_GPR_MANAGEMENT_REG_DYNAMIC 0x00000001 146252260ae4SRob Clark #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK 0x00000ff0 146352260ae4SRob Clark #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT 4 146452260ae4SRob Clark static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX(uint32_t val) 146552260ae4SRob Clark { 146652260ae4SRob Clark return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK; 146752260ae4SRob Clark } 146852260ae4SRob Clark #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK 0x000ff000 146952260ae4SRob Clark #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT 12 147052260ae4SRob Clark static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX(uint32_t val) 147152260ae4SRob Clark { 147252260ae4SRob Clark return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK; 147352260ae4SRob Clark } 1474902e6eb8SRob Clark 1475902e6eb8SRob Clark #define REG_A2XX_SQ_FLOW_CONTROL 0x00000d01 1476902e6eb8SRob Clark 1477902e6eb8SRob Clark #define REG_A2XX_SQ_INST_STORE_MANAGMENT 0x00000d02 147852260ae4SRob Clark #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK 0x00000fff 147952260ae4SRob Clark #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT 0 148052260ae4SRob Clark static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX(uint32_t val) 148152260ae4SRob Clark { 148252260ae4SRob Clark return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK; 148352260ae4SRob Clark } 148452260ae4SRob Clark #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK 0x0fff0000 148552260ae4SRob Clark #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT 16 148652260ae4SRob Clark static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX(uint32_t val) 148752260ae4SRob Clark { 148852260ae4SRob Clark return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK; 148952260ae4SRob Clark } 1490902e6eb8SRob Clark 1491902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_MISC 0x00000d05 1492902e6eb8SRob Clark 1493902e6eb8SRob Clark #define REG_A2XX_SQ_INT_CNTL 0x00000d34 1494902e6eb8SRob Clark 1495902e6eb8SRob Clark #define REG_A2XX_SQ_INT_STATUS 0x00000d35 1496902e6eb8SRob Clark 1497902e6eb8SRob Clark #define REG_A2XX_SQ_INT_ACK 0x00000d36 1498902e6eb8SRob Clark 1499902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_INPUT_FSM 0x00000dae 1500902e6eb8SRob Clark 1501902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_CONST_MGR_FSM 0x00000daf 1502902e6eb8SRob Clark 1503902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_TP_FSM 0x00000db0 1504902e6eb8SRob Clark 1505902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_FSM_ALU_0 0x00000db1 1506902e6eb8SRob Clark 1507902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_FSM_ALU_1 0x00000db2 1508902e6eb8SRob Clark 1509902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_EXP_ALLOC 0x00000db3 1510902e6eb8SRob Clark 1511902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_PTR_BUFF 0x00000db4 1512902e6eb8SRob Clark 1513902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_GPR_VTX 0x00000db5 1514902e6eb8SRob Clark 1515902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_GPR_PIX 0x00000db6 1516902e6eb8SRob Clark 1517902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_TB_STATUS_SEL 0x00000db7 1518902e6eb8SRob Clark 1519902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_VTX_TB_0 0x00000db8 1520902e6eb8SRob Clark 1521902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_VTX_TB_1 0x00000db9 1522902e6eb8SRob Clark 1523902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG 0x00000dba 1524902e6eb8SRob Clark 1525902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM 0x00000dbb 1526902e6eb8SRob Clark 1527902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_PIX_TB_0 0x00000dbc 1528902e6eb8SRob Clark 1529902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0 0x00000dbd 1530902e6eb8SRob Clark 1531902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1 0x00000dbe 1532902e6eb8SRob Clark 1533902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2 0x00000dbf 1534902e6eb8SRob Clark 1535902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3 0x00000dc0 1536902e6eb8SRob Clark 1537902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM 0x00000dc1 1538902e6eb8SRob Clark 1539902e6eb8SRob Clark #define REG_A2XX_TC_CNTL_STATUS 0x00000e00 1540902e6eb8SRob Clark #define A2XX_TC_CNTL_STATUS_L2_INVALIDATE 0x00000001 1541902e6eb8SRob Clark 1542902e6eb8SRob Clark #define REG_A2XX_TP0_CHICKEN 0x00000e1e 1543902e6eb8SRob Clark 1544902e6eb8SRob Clark #define REG_A2XX_RB_BC_CONTROL 0x00000f01 1545902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE 0x00000001 1546902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK 0x00000006 1547902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT 1 1548902e6eb8SRob Clark static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val) 1549902e6eb8SRob Clark { 1550902e6eb8SRob Clark return ((val) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK; 1551902e6eb8SRob Clark } 1552902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM 0x00000008 1553902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010 1554902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP 0x00000020 1555902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP 0x00000040 1556902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE 0x00000080 1557902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK 0x00001f00 1558902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT 8 1559902e6eb8SRob Clark static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val) 1560902e6eb8SRob Clark { 1561902e6eb8SRob Clark return ((val) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK; 1562902e6eb8SRob Clark } 1563902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE 0x00004000 1564902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_CRC_MODE 0x00008000 1565902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS 0x00010000 1566902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_DISABLE_ACCUM 0x00020000 1567902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK 0x003c0000 1568902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT 18 1569902e6eb8SRob Clark static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val) 1570902e6eb8SRob Clark { 1571902e6eb8SRob Clark return ((val) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK; 1572902e6eb8SRob Clark } 1573902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE 0x00400000 1574902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK 0x07800000 1575902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT 23 1576902e6eb8SRob Clark static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val) 1577902e6eb8SRob Clark { 1578902e6eb8SRob Clark return ((val) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK; 1579902e6eb8SRob Clark } 1580902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK 0x18000000 1581902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT 27 1582902e6eb8SRob Clark static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val) 1583902e6eb8SRob Clark { 1584902e6eb8SRob Clark return ((val) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK; 1585902e6eb8SRob Clark } 1586902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000 1587902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_CRC_SYSTEM 0x40000000 1588902e6eb8SRob Clark #define A2XX_RB_BC_CONTROL_RESERVED6 0x80000000 1589902e6eb8SRob Clark 1590902e6eb8SRob Clark #define REG_A2XX_RB_EDRAM_INFO 0x00000f02 1591902e6eb8SRob Clark 1592902e6eb8SRob Clark #define REG_A2XX_RB_DEBUG_CNTL 0x00000f26 1593902e6eb8SRob Clark 1594902e6eb8SRob Clark #define REG_A2XX_RB_DEBUG_DATA 0x00000f27 1595902e6eb8SRob Clark 1596902e6eb8SRob Clark #define REG_A2XX_RB_SURFACE_INFO 0x00002000 1597ccdf7e28SRob Clark #define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK 0x00003fff 1598ccdf7e28SRob Clark #define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT 0 1599ccdf7e28SRob Clark static inline uint32_t A2XX_RB_SURFACE_INFO_SURFACE_PITCH(uint32_t val) 1600ccdf7e28SRob Clark { 1601ccdf7e28SRob Clark return ((val) << A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT) & A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK; 1602ccdf7e28SRob Clark } 1603ccdf7e28SRob Clark #define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK 0x0000c000 1604ccdf7e28SRob Clark #define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT 14 1605ccdf7e28SRob Clark static inline uint32_t A2XX_RB_SURFACE_INFO_MSAA_SAMPLES(uint32_t val) 1606ccdf7e28SRob Clark { 1607ccdf7e28SRob Clark return ((val) << A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT) & A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK; 1608ccdf7e28SRob Clark } 1609902e6eb8SRob Clark 1610902e6eb8SRob Clark #define REG_A2XX_RB_COLOR_INFO 0x00002001 1611902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_FORMAT__MASK 0x0000000f 1612902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_FORMAT__SHIFT 0 1613902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val) 1614902e6eb8SRob Clark { 1615902e6eb8SRob Clark return ((val) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT) & A2XX_RB_COLOR_INFO_FORMAT__MASK; 1616902e6eb8SRob Clark } 1617902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_ROUND_MODE__MASK 0x00000030 1618902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT 4 1619902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val) 1620902e6eb8SRob Clark { 1621902e6eb8SRob Clark return ((val) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK; 1622902e6eb8SRob Clark } 1623902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_LINEAR 0x00000040 1624902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_ENDIAN__MASK 0x00000180 1625902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_ENDIAN__SHIFT 7 1626902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val) 1627902e6eb8SRob Clark { 1628902e6eb8SRob Clark return ((val) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT) & A2XX_RB_COLOR_INFO_ENDIAN__MASK; 1629902e6eb8SRob Clark } 1630902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_SWAP__MASK 0x00000600 1631902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_SWAP__SHIFT 9 1632902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val) 1633902e6eb8SRob Clark { 1634902e6eb8SRob Clark return ((val) << A2XX_RB_COLOR_INFO_SWAP__SHIFT) & A2XX_RB_COLOR_INFO_SWAP__MASK; 1635902e6eb8SRob Clark } 1636902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_BASE__MASK 0xfffff000 1637902e6eb8SRob Clark #define A2XX_RB_COLOR_INFO_BASE__SHIFT 12 1638902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val) 1639902e6eb8SRob Clark { 1640ccdf7e28SRob Clark return ((val >> 12) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK; 1641902e6eb8SRob Clark } 1642902e6eb8SRob Clark 1643902e6eb8SRob Clark #define REG_A2XX_RB_DEPTH_INFO 0x00002002 1644902e6eb8SRob Clark #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001 1645902e6eb8SRob Clark #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 1646902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) 1647902e6eb8SRob Clark { 1648902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 1649902e6eb8SRob Clark } 1650902e6eb8SRob Clark #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 1651902e6eb8SRob Clark #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 1652902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 1653902e6eb8SRob Clark { 1654ccdf7e28SRob Clark return ((val >> 12) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 1655902e6eb8SRob Clark } 1656902e6eb8SRob Clark 1657902e6eb8SRob Clark #define REG_A2XX_A225_RB_COLOR_INFO3 0x00002005 1658902e6eb8SRob Clark 1659902e6eb8SRob Clark #define REG_A2XX_COHER_DEST_BASE_0 0x00002006 1660902e6eb8SRob Clark 1661902e6eb8SRob Clark #define REG_A2XX_PA_SC_SCREEN_SCISSOR_TL 0x0000200e 1662902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 1663902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 1664902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 1665902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 1666902e6eb8SRob Clark { 1667902e6eb8SRob Clark return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK; 1668902e6eb8SRob Clark } 1669902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 1670902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 1671902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 1672902e6eb8SRob Clark { 1673902e6eb8SRob Clark return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK; 1674902e6eb8SRob Clark } 1675902e6eb8SRob Clark 1676902e6eb8SRob Clark #define REG_A2XX_PA_SC_SCREEN_SCISSOR_BR 0x0000200f 1677902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 1678902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 1679902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 1680902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 1681902e6eb8SRob Clark { 1682902e6eb8SRob Clark return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK; 1683902e6eb8SRob Clark } 1684902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 1685902e6eb8SRob Clark #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 1686902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 1687902e6eb8SRob Clark { 1688902e6eb8SRob Clark return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK; 1689902e6eb8SRob Clark } 1690902e6eb8SRob Clark 1691902e6eb8SRob Clark #define REG_A2XX_PA_SC_WINDOW_OFFSET 0x00002080 1692902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_OFFSET_X__MASK 0x00007fff 1693902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT 0 1694902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val) 1695902e6eb8SRob Clark { 1696902e6eb8SRob Clark return ((val) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK; 1697902e6eb8SRob Clark } 1698902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_OFFSET_Y__MASK 0x7fff0000 1699902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT 16 1700902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val) 1701902e6eb8SRob Clark { 1702902e6eb8SRob Clark return ((val) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK; 1703902e6eb8SRob Clark } 1704902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_OFFSET_DISABLE 0x80000000 1705902e6eb8SRob Clark 1706902e6eb8SRob Clark #define REG_A2XX_PA_SC_WINDOW_SCISSOR_TL 0x00002081 1707902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 1708902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 1709902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 1710902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 1711902e6eb8SRob Clark { 1712902e6eb8SRob Clark return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK; 1713902e6eb8SRob Clark } 1714902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 1715902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 1716902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 1717902e6eb8SRob Clark { 1718902e6eb8SRob Clark return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK; 1719902e6eb8SRob Clark } 1720902e6eb8SRob Clark 1721902e6eb8SRob Clark #define REG_A2XX_PA_SC_WINDOW_SCISSOR_BR 0x00002082 1722902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 1723902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 1724902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 1725902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 1726902e6eb8SRob Clark { 1727902e6eb8SRob Clark return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK; 1728902e6eb8SRob Clark } 1729902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 1730902e6eb8SRob Clark #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 1731902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 1732902e6eb8SRob Clark { 1733902e6eb8SRob Clark return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK; 1734902e6eb8SRob Clark } 1735902e6eb8SRob Clark 1736902e6eb8SRob Clark #define REG_A2XX_UNKNOWN_2010 0x00002010 1737902e6eb8SRob Clark 1738902e6eb8SRob Clark #define REG_A2XX_VGT_MAX_VTX_INDX 0x00002100 1739902e6eb8SRob Clark 1740902e6eb8SRob Clark #define REG_A2XX_VGT_MIN_VTX_INDX 0x00002101 1741902e6eb8SRob Clark 1742902e6eb8SRob Clark #define REG_A2XX_VGT_INDX_OFFSET 0x00002102 1743902e6eb8SRob Clark 1744902e6eb8SRob Clark #define REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX 0x00002103 1745902e6eb8SRob Clark 1746902e6eb8SRob Clark #define REG_A2XX_RB_COLOR_MASK 0x00002104 1747902e6eb8SRob Clark #define A2XX_RB_COLOR_MASK_WRITE_RED 0x00000001 1748902e6eb8SRob Clark #define A2XX_RB_COLOR_MASK_WRITE_GREEN 0x00000002 1749902e6eb8SRob Clark #define A2XX_RB_COLOR_MASK_WRITE_BLUE 0x00000004 1750902e6eb8SRob Clark #define A2XX_RB_COLOR_MASK_WRITE_ALPHA 0x00000008 1751902e6eb8SRob Clark 1752902e6eb8SRob Clark #define REG_A2XX_RB_BLEND_RED 0x00002105 1753902e6eb8SRob Clark 1754902e6eb8SRob Clark #define REG_A2XX_RB_BLEND_GREEN 0x00002106 1755902e6eb8SRob Clark 1756902e6eb8SRob Clark #define REG_A2XX_RB_BLEND_BLUE 0x00002107 1757902e6eb8SRob Clark 1758902e6eb8SRob Clark #define REG_A2XX_RB_BLEND_ALPHA 0x00002108 1759902e6eb8SRob Clark 1760902e6eb8SRob Clark #define REG_A2XX_RB_FOG_COLOR 0x00002109 176152260ae4SRob Clark #define A2XX_RB_FOG_COLOR_FOG_RED__MASK 0x000000ff 176252260ae4SRob Clark #define A2XX_RB_FOG_COLOR_FOG_RED__SHIFT 0 176352260ae4SRob Clark static inline uint32_t A2XX_RB_FOG_COLOR_FOG_RED(uint32_t val) 176452260ae4SRob Clark { 176552260ae4SRob Clark return ((val) << A2XX_RB_FOG_COLOR_FOG_RED__SHIFT) & A2XX_RB_FOG_COLOR_FOG_RED__MASK; 176652260ae4SRob Clark } 176752260ae4SRob Clark #define A2XX_RB_FOG_COLOR_FOG_GREEN__MASK 0x0000ff00 176852260ae4SRob Clark #define A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT 8 176952260ae4SRob Clark static inline uint32_t A2XX_RB_FOG_COLOR_FOG_GREEN(uint32_t val) 177052260ae4SRob Clark { 177152260ae4SRob Clark return ((val) << A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT) & A2XX_RB_FOG_COLOR_FOG_GREEN__MASK; 177252260ae4SRob Clark } 177352260ae4SRob Clark #define A2XX_RB_FOG_COLOR_FOG_BLUE__MASK 0x00ff0000 177452260ae4SRob Clark #define A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT 16 177552260ae4SRob Clark static inline uint32_t A2XX_RB_FOG_COLOR_FOG_BLUE(uint32_t val) 177652260ae4SRob Clark { 177752260ae4SRob Clark return ((val) << A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT) & A2XX_RB_FOG_COLOR_FOG_BLUE__MASK; 177852260ae4SRob Clark } 1779902e6eb8SRob Clark 1780902e6eb8SRob Clark #define REG_A2XX_RB_STENCILREFMASK_BF 0x0000210c 1781902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 1782902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 1783902e6eb8SRob Clark static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 1784902e6eb8SRob Clark { 1785902e6eb8SRob Clark return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 1786902e6eb8SRob Clark } 1787902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 1788902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 1789902e6eb8SRob Clark static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 1790902e6eb8SRob Clark { 1791902e6eb8SRob Clark return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 1792902e6eb8SRob Clark } 1793902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 1794902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 1795902e6eb8SRob Clark static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 1796902e6eb8SRob Clark { 1797902e6eb8SRob Clark return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 1798902e6eb8SRob Clark } 1799902e6eb8SRob Clark 1800902e6eb8SRob Clark #define REG_A2XX_RB_STENCILREFMASK 0x0000210d 1801902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 1802902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 1803902e6eb8SRob Clark static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 1804902e6eb8SRob Clark { 1805902e6eb8SRob Clark return ((val) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK; 1806902e6eb8SRob Clark } 1807902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 1808902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 1809902e6eb8SRob Clark static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 1810902e6eb8SRob Clark { 1811902e6eb8SRob Clark return ((val) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK; 1812902e6eb8SRob Clark } 1813902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 1814902e6eb8SRob Clark #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 1815902e6eb8SRob Clark static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 1816902e6eb8SRob Clark { 1817902e6eb8SRob Clark return ((val) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 1818902e6eb8SRob Clark } 1819902e6eb8SRob Clark 1820902e6eb8SRob Clark #define REG_A2XX_RB_ALPHA_REF 0x0000210e 1821902e6eb8SRob Clark 1822902e6eb8SRob Clark #define REG_A2XX_PA_CL_VPORT_XSCALE 0x0000210f 1823902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_XSCALE__MASK 0xffffffff 1824902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_XSCALE__SHIFT 0 1825902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val) 1826902e6eb8SRob Clark { 1827902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT) & A2XX_PA_CL_VPORT_XSCALE__MASK; 1828902e6eb8SRob Clark } 1829902e6eb8SRob Clark 1830902e6eb8SRob Clark #define REG_A2XX_PA_CL_VPORT_XOFFSET 0x00002110 1831902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_XOFFSET__MASK 0xffffffff 1832902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_XOFFSET__SHIFT 0 1833902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val) 1834902e6eb8SRob Clark { 1835902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT) & A2XX_PA_CL_VPORT_XOFFSET__MASK; 1836902e6eb8SRob Clark } 1837902e6eb8SRob Clark 1838902e6eb8SRob Clark #define REG_A2XX_PA_CL_VPORT_YSCALE 0x00002111 1839902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_YSCALE__MASK 0xffffffff 1840902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_YSCALE__SHIFT 0 1841902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val) 1842902e6eb8SRob Clark { 1843902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT) & A2XX_PA_CL_VPORT_YSCALE__MASK; 1844902e6eb8SRob Clark } 1845902e6eb8SRob Clark 1846902e6eb8SRob Clark #define REG_A2XX_PA_CL_VPORT_YOFFSET 0x00002112 1847902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_YOFFSET__MASK 0xffffffff 1848902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_YOFFSET__SHIFT 0 1849902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val) 1850902e6eb8SRob Clark { 1851902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT) & A2XX_PA_CL_VPORT_YOFFSET__MASK; 1852902e6eb8SRob Clark } 1853902e6eb8SRob Clark 1854902e6eb8SRob Clark #define REG_A2XX_PA_CL_VPORT_ZSCALE 0x00002113 1855902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_ZSCALE__MASK 0xffffffff 1856902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_ZSCALE__SHIFT 0 1857902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val) 1858902e6eb8SRob Clark { 1859902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT) & A2XX_PA_CL_VPORT_ZSCALE__MASK; 1860902e6eb8SRob Clark } 1861902e6eb8SRob Clark 1862902e6eb8SRob Clark #define REG_A2XX_PA_CL_VPORT_ZOFFSET 0x00002114 1863902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_ZOFFSET__MASK 0xffffffff 1864902e6eb8SRob Clark #define A2XX_PA_CL_VPORT_ZOFFSET__SHIFT 0 1865902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val) 1866902e6eb8SRob Clark { 1867902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT) & A2XX_PA_CL_VPORT_ZOFFSET__MASK; 1868902e6eb8SRob Clark } 1869902e6eb8SRob Clark 1870902e6eb8SRob Clark #define REG_A2XX_SQ_PROGRAM_CNTL 0x00002180 1871902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK 0x000000ff 1872902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT 0 1873902e6eb8SRob Clark static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val) 1874902e6eb8SRob Clark { 1875902e6eb8SRob Clark return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK; 1876902e6eb8SRob Clark } 1877902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK 0x0000ff00 1878902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT 8 1879902e6eb8SRob Clark static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val) 1880902e6eb8SRob Clark { 1881902e6eb8SRob Clark return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK; 1882902e6eb8SRob Clark } 1883902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE 0x00010000 1884902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE 0x00020000 1885902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_PARAM_GEN 0x00040000 1886902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX 0x00080000 1887902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK 0x00f00000 1888902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT 20 1889902e6eb8SRob Clark static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val) 1890902e6eb8SRob Clark { 1891902e6eb8SRob Clark return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK; 1892902e6eb8SRob Clark } 1893902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK 0x07000000 1894902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT 24 1895902e6eb8SRob Clark static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val) 1896902e6eb8SRob Clark { 1897902e6eb8SRob Clark return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK; 1898902e6eb8SRob Clark } 1899902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK 0x78000000 1900902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT 27 1901902e6eb8SRob Clark static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val) 1902902e6eb8SRob Clark { 1903902e6eb8SRob Clark return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK; 1904902e6eb8SRob Clark } 1905902e6eb8SRob Clark #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX 0x80000000 1906902e6eb8SRob Clark 1907902e6eb8SRob Clark #define REG_A2XX_SQ_CONTEXT_MISC 0x00002181 1908902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE 0x00000001 1909902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY 0x00000002 1910902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK 0x0000000c 1911902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT 2 1912902e6eb8SRob Clark static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val) 1913902e6eb8SRob Clark { 1914902e6eb8SRob Clark return ((val) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK; 1915902e6eb8SRob Clark } 1916902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK 0x0000ff00 1917902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT 8 1918902e6eb8SRob Clark static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val) 1919902e6eb8SRob Clark { 1920902e6eb8SRob Clark return ((val) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK; 1921902e6eb8SRob Clark } 1922902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF 0x00010000 1923902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE 0x00020000 1924902e6eb8SRob Clark #define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL 0x00040000 1925902e6eb8SRob Clark 1926902e6eb8SRob Clark #define REG_A2XX_SQ_INTERPOLATOR_CNTL 0x00002182 192752260ae4SRob Clark #define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK 0x0000ffff 192852260ae4SRob Clark #define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT 0 192952260ae4SRob Clark static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE(uint32_t val) 193052260ae4SRob Clark { 193152260ae4SRob Clark return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK; 193252260ae4SRob Clark } 193352260ae4SRob Clark #define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK 0xffff0000 193452260ae4SRob Clark #define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT 16 193552260ae4SRob Clark static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN(uint32_t val) 193652260ae4SRob Clark { 193752260ae4SRob Clark return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK; 193852260ae4SRob Clark } 1939902e6eb8SRob Clark 1940902e6eb8SRob Clark #define REG_A2XX_SQ_WRAPPING_0 0x00002183 194152260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK 0x0000000f 194252260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT 0 194352260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_0(uint32_t val) 194452260ae4SRob Clark { 194552260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK; 194652260ae4SRob Clark } 194752260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK 0x000000f0 194852260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT 4 194952260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_1(uint32_t val) 195052260ae4SRob Clark { 195152260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK; 195252260ae4SRob Clark } 195352260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK 0x00000f00 195452260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT 8 195552260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_2(uint32_t val) 195652260ae4SRob Clark { 195752260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK; 195852260ae4SRob Clark } 195952260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK 0x0000f000 196052260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT 12 196152260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_3(uint32_t val) 196252260ae4SRob Clark { 196352260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK; 196452260ae4SRob Clark } 196552260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK 0x000f0000 196652260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT 16 196752260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_4(uint32_t val) 196852260ae4SRob Clark { 196952260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK; 197052260ae4SRob Clark } 197152260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK 0x00f00000 197252260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT 20 197352260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_5(uint32_t val) 197452260ae4SRob Clark { 197552260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK; 197652260ae4SRob Clark } 197752260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK 0x0f000000 197852260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT 24 197952260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_6(uint32_t val) 198052260ae4SRob Clark { 198152260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK; 198252260ae4SRob Clark } 198352260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK 0xf0000000 198452260ae4SRob Clark #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT 28 198552260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_7(uint32_t val) 198652260ae4SRob Clark { 198752260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK; 198852260ae4SRob Clark } 1989902e6eb8SRob Clark 1990902e6eb8SRob Clark #define REG_A2XX_SQ_WRAPPING_1 0x00002184 199152260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK 0x0000000f 199252260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT 0 199352260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_8(uint32_t val) 199452260ae4SRob Clark { 199552260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK; 199652260ae4SRob Clark } 199752260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK 0x000000f0 199852260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT 4 199952260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_9(uint32_t val) 200052260ae4SRob Clark { 200152260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK; 200252260ae4SRob Clark } 200352260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK 0x00000f00 200452260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT 8 200552260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_10(uint32_t val) 200652260ae4SRob Clark { 200752260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK; 200852260ae4SRob Clark } 200952260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK 0x0000f000 201052260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT 12 201152260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_11(uint32_t val) 201252260ae4SRob Clark { 201352260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK; 201452260ae4SRob Clark } 201552260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK 0x000f0000 201652260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT 16 201752260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_12(uint32_t val) 201852260ae4SRob Clark { 201952260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK; 202052260ae4SRob Clark } 202152260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK 0x00f00000 202252260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT 20 202352260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_13(uint32_t val) 202452260ae4SRob Clark { 202552260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK; 202652260ae4SRob Clark } 202752260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK 0x0f000000 202852260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT 24 202952260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_14(uint32_t val) 203052260ae4SRob Clark { 203152260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK; 203252260ae4SRob Clark } 203352260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK 0xf0000000 203452260ae4SRob Clark #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT 28 203552260ae4SRob Clark static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_15(uint32_t val) 203652260ae4SRob Clark { 203752260ae4SRob Clark return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK; 203852260ae4SRob Clark } 2039902e6eb8SRob Clark 2040902e6eb8SRob Clark #define REG_A2XX_SQ_PS_PROGRAM 0x000021f6 204152260ae4SRob Clark #define A2XX_SQ_PS_PROGRAM_BASE__MASK 0x00000fff 204252260ae4SRob Clark #define A2XX_SQ_PS_PROGRAM_BASE__SHIFT 0 204352260ae4SRob Clark static inline uint32_t A2XX_SQ_PS_PROGRAM_BASE(uint32_t val) 204452260ae4SRob Clark { 204552260ae4SRob Clark return ((val) << A2XX_SQ_PS_PROGRAM_BASE__SHIFT) & A2XX_SQ_PS_PROGRAM_BASE__MASK; 204652260ae4SRob Clark } 204752260ae4SRob Clark #define A2XX_SQ_PS_PROGRAM_SIZE__MASK 0x00fff000 204852260ae4SRob Clark #define A2XX_SQ_PS_PROGRAM_SIZE__SHIFT 12 204952260ae4SRob Clark static inline uint32_t A2XX_SQ_PS_PROGRAM_SIZE(uint32_t val) 205052260ae4SRob Clark { 205152260ae4SRob Clark return ((val) << A2XX_SQ_PS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_PS_PROGRAM_SIZE__MASK; 205252260ae4SRob Clark } 2053902e6eb8SRob Clark 2054902e6eb8SRob Clark #define REG_A2XX_SQ_VS_PROGRAM 0x000021f7 205552260ae4SRob Clark #define A2XX_SQ_VS_PROGRAM_BASE__MASK 0x00000fff 205652260ae4SRob Clark #define A2XX_SQ_VS_PROGRAM_BASE__SHIFT 0 205752260ae4SRob Clark static inline uint32_t A2XX_SQ_VS_PROGRAM_BASE(uint32_t val) 205852260ae4SRob Clark { 205952260ae4SRob Clark return ((val) << A2XX_SQ_VS_PROGRAM_BASE__SHIFT) & A2XX_SQ_VS_PROGRAM_BASE__MASK; 206052260ae4SRob Clark } 206152260ae4SRob Clark #define A2XX_SQ_VS_PROGRAM_SIZE__MASK 0x00fff000 206252260ae4SRob Clark #define A2XX_SQ_VS_PROGRAM_SIZE__SHIFT 12 206352260ae4SRob Clark static inline uint32_t A2XX_SQ_VS_PROGRAM_SIZE(uint32_t val) 206452260ae4SRob Clark { 206552260ae4SRob Clark return ((val) << A2XX_SQ_VS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_VS_PROGRAM_SIZE__MASK; 206652260ae4SRob Clark } 2067902e6eb8SRob Clark 2068facb4f4eSRob Clark #define REG_A2XX_VGT_EVENT_INITIATOR 0x000021f9 2069facb4f4eSRob Clark 2070facb4f4eSRob Clark #define REG_A2XX_VGT_DRAW_INITIATOR 0x000021fc 207189301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f 207289301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 207389301471SRob Clark static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) 207489301471SRob Clark { 207589301471SRob Clark return ((val) << A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK; 207689301471SRob Clark } 207789301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 207889301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 207989301471SRob Clark static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) 208089301471SRob Clark { 208189301471SRob Clark return ((val) << A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK; 208289301471SRob Clark } 208389301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600 208489301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9 208589301471SRob Clark static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) 208689301471SRob Clark { 208789301471SRob Clark return ((val) << A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK; 208889301471SRob Clark } 208989301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800 209089301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11 209189301471SRob Clark static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) 209289301471SRob Clark { 209389301471SRob Clark return ((val) << A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK; 209489301471SRob Clark } 209589301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000 209689301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000 209789301471SRob Clark #define A2XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000 2098bc00ae02SRob Clark #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK 0xff000000 2099bc00ae02SRob Clark #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT 24 2100bc00ae02SRob Clark static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) 210189301471SRob Clark { 2102bc00ae02SRob Clark return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK; 210389301471SRob Clark } 2104facb4f4eSRob Clark 2105facb4f4eSRob Clark #define REG_A2XX_VGT_IMMED_DATA 0x000021fd 2106facb4f4eSRob Clark 2107902e6eb8SRob Clark #define REG_A2XX_RB_DEPTHCONTROL 0x00002200 2108902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE 0x00000001 2109902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_Z_ENABLE 0x00000002 2110902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE 0x00000004 2111902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE 0x00000008 2112902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_ZFUNC__MASK 0x00000070 2113902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT 4 2114902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val) 2115902e6eb8SRob Clark { 2116902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK; 2117902e6eb8SRob Clark } 2118902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE 0x00000080 2119902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK 0x00000700 2120902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT 8 2121902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val) 2122902e6eb8SRob Clark { 2123902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK; 2124902e6eb8SRob Clark } 2125902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK 0x00003800 2126902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT 11 2127902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val) 2128902e6eb8SRob Clark { 2129902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK; 2130902e6eb8SRob Clark } 2131902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK 0x0001c000 2132902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT 14 2133902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val) 2134902e6eb8SRob Clark { 2135902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK; 2136902e6eb8SRob Clark } 2137902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK 0x000e0000 2138902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT 17 2139902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val) 2140902e6eb8SRob Clark { 2141902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK; 2142902e6eb8SRob Clark } 2143902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK 0x00700000 2144902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT 20 2145902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val) 2146902e6eb8SRob Clark { 2147902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK; 2148902e6eb8SRob Clark } 2149902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK 0x03800000 2150902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT 23 2151902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val) 2152902e6eb8SRob Clark { 2153902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK; 2154902e6eb8SRob Clark } 2155902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK 0x1c000000 2156902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT 26 2157902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val) 2158902e6eb8SRob Clark { 2159902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK; 2160902e6eb8SRob Clark } 2161902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK 0xe0000000 2162902e6eb8SRob Clark #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT 29 2163902e6eb8SRob Clark static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val) 2164902e6eb8SRob Clark { 2165902e6eb8SRob Clark return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK; 2166902e6eb8SRob Clark } 2167902e6eb8SRob Clark 2168902e6eb8SRob Clark #define REG_A2XX_RB_BLEND_CONTROL 0x00002201 2169902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK 0x0000001f 2170902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT 0 2171902e6eb8SRob Clark static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val) 2172902e6eb8SRob Clark { 2173902e6eb8SRob Clark return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK; 2174902e6eb8SRob Clark } 2175902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK 0x000000e0 2176902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT 5 217789301471SRob Clark static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val) 2178902e6eb8SRob Clark { 2179902e6eb8SRob Clark return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK; 2180902e6eb8SRob Clark } 2181902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK 0x00001f00 2182902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT 8 2183902e6eb8SRob Clark static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val) 2184902e6eb8SRob Clark { 2185902e6eb8SRob Clark return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK; 2186902e6eb8SRob Clark } 2187902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK 0x001f0000 2188902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT 16 2189902e6eb8SRob Clark static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val) 2190902e6eb8SRob Clark { 2191902e6eb8SRob Clark return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK; 2192902e6eb8SRob Clark } 2193902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK 0x00e00000 2194902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT 21 219589301471SRob Clark static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val) 2196902e6eb8SRob Clark { 2197902e6eb8SRob Clark return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK; 2198902e6eb8SRob Clark } 2199902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK 0x1f000000 2200902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT 24 2201902e6eb8SRob Clark static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val) 2202902e6eb8SRob Clark { 2203902e6eb8SRob Clark return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK; 2204902e6eb8SRob Clark } 2205902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE 0x20000000 2206902e6eb8SRob Clark #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE 0x40000000 2207902e6eb8SRob Clark 2208902e6eb8SRob Clark #define REG_A2XX_RB_COLORCONTROL 0x00002202 2209902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK 0x00000007 2210902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT 0 2211902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val) 2212902e6eb8SRob Clark { 2213902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK; 2214902e6eb8SRob Clark } 2215902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE 0x00000008 2216902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE 0x00000010 2217902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_BLEND_DISABLE 0x00000020 2218902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_VOB_ENABLE 0x00000040 2219902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG 0x00000080 2220902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ROP_CODE__MASK 0x00000f00 2221902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT 8 2222902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val) 2223902e6eb8SRob Clark { 2224902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK; 2225902e6eb8SRob Clark } 2226902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_DITHER_MODE__MASK 0x00003000 2227902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT 12 2228902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) 2229902e6eb8SRob Clark { 2230902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK; 2231902e6eb8SRob Clark } 2232902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK 0x0000c000 2233902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT 14 2234902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val) 2235902e6eb8SRob Clark { 2236902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK; 2237902e6eb8SRob Clark } 2238902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_PIXEL_FOG 0x00010000 2239902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK 0x03000000 2240902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT 24 2241902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val) 2242902e6eb8SRob Clark { 2243902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK; 2244902e6eb8SRob Clark } 2245902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK 0x0c000000 2246902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT 26 2247902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val) 2248902e6eb8SRob Clark { 2249902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK; 2250902e6eb8SRob Clark } 2251902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK 0x30000000 2252902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT 28 2253902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val) 2254902e6eb8SRob Clark { 2255902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK; 2256902e6eb8SRob Clark } 2257902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK 0xc0000000 2258902e6eb8SRob Clark #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT 30 2259902e6eb8SRob Clark static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val) 2260902e6eb8SRob Clark { 2261902e6eb8SRob Clark return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK; 2262902e6eb8SRob Clark } 2263902e6eb8SRob Clark 2264902e6eb8SRob Clark #define REG_A2XX_VGT_CURRENT_BIN_ID_MAX 0x00002203 2265902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK 0x00000007 2266902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT 0 2267902e6eb8SRob Clark static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val) 2268902e6eb8SRob Clark { 2269902e6eb8SRob Clark return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK; 2270902e6eb8SRob Clark } 2271902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK 0x00000038 2272902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT 3 2273902e6eb8SRob Clark static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val) 2274902e6eb8SRob Clark { 2275902e6eb8SRob Clark return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK; 2276902e6eb8SRob Clark } 2277902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK 0x000001c0 2278902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT 6 2279902e6eb8SRob Clark static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val) 2280902e6eb8SRob Clark { 2281902e6eb8SRob Clark return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK; 2282902e6eb8SRob Clark } 2283902e6eb8SRob Clark 2284902e6eb8SRob Clark #define REG_A2XX_PA_CL_CLIP_CNTL 0x00002204 2285902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 2286902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA 0x00040000 2287902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK 0x00080000 2288902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT 19 2289902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val) 2290902e6eb8SRob Clark { 2291902e6eb8SRob Clark return ((val) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK; 2292902e6eb8SRob Clark } 2293902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT 0x00100000 2294902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR 0x00200000 2295902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN 0x00400000 2296902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN 0x00800000 2297902e6eb8SRob Clark #define A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN 0x01000000 2298902e6eb8SRob Clark 2299902e6eb8SRob Clark #define REG_A2XX_PA_SU_SC_MODE_CNTL 0x00002205 2300902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT 0x00000001 2301902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK 0x00000002 2302902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_FACE 0x00000004 2303902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK 0x00000018 2304902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT 3 2305902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val) 2306902e6eb8SRob Clark { 2307902e6eb8SRob Clark return ((val) << A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK; 2308902e6eb8SRob Clark } 2309902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK 0x000000e0 2310902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT 5 2311902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 2312902e6eb8SRob Clark { 2313902e6eb8SRob Clark return ((val) << A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK; 2314902e6eb8SRob Clark } 2315902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK 0x00000700 2316902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT 8 2317902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 2318902e6eb8SRob Clark { 2319902e6eb8SRob Clark return ((val) << A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK; 2320902e6eb8SRob Clark } 2321902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE 0x00000800 2322902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE 0x00001000 2323902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE 0x00002000 2324902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE 0x00008000 2325902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE 0x00010000 2326902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE 0x00040000 2327902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST 0x00080000 2328902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS 0x00100000 2329902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA 0x00200000 2330902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE 0x00800000 2331902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI 0x02000000 2332902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000 2333902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS 0x10000000 2334902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS 0x20000000 2335902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE 0x40000000 2336902e6eb8SRob Clark #define A2XX_PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE 0x80000000 2337902e6eb8SRob Clark 2338902e6eb8SRob Clark #define REG_A2XX_PA_CL_VTE_CNTL 0x00002206 2339902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA 0x00000001 2340902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA 0x00000002 2341902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA 0x00000004 2342902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA 0x00000008 2343902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA 0x00000010 2344902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA 0x00000020 2345902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT 0x00000100 2346902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT 0x00000200 2347902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT 0x00000400 2348902e6eb8SRob Clark #define A2XX_PA_CL_VTE_CNTL_PERFCOUNTER_REF 0x00000800 2349902e6eb8SRob Clark 2350902e6eb8SRob Clark #define REG_A2XX_VGT_CURRENT_BIN_ID_MIN 0x00002207 2351902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK 0x00000007 2352902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT 0 2353902e6eb8SRob Clark static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val) 2354902e6eb8SRob Clark { 2355902e6eb8SRob Clark return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK; 2356902e6eb8SRob Clark } 2357902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK 0x00000038 2358902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT 3 2359902e6eb8SRob Clark static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val) 2360902e6eb8SRob Clark { 2361902e6eb8SRob Clark return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK; 2362902e6eb8SRob Clark } 2363902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK 0x000001c0 2364902e6eb8SRob Clark #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT 6 2365902e6eb8SRob Clark static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val) 2366902e6eb8SRob Clark { 2367902e6eb8SRob Clark return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK; 2368902e6eb8SRob Clark } 2369902e6eb8SRob Clark 2370902e6eb8SRob Clark #define REG_A2XX_RB_MODECONTROL 0x00002208 2371902e6eb8SRob Clark #define A2XX_RB_MODECONTROL_EDRAM_MODE__MASK 0x00000007 2372902e6eb8SRob Clark #define A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT 0 2373902e6eb8SRob Clark static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val) 2374902e6eb8SRob Clark { 2375902e6eb8SRob Clark return ((val) << A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT) & A2XX_RB_MODECONTROL_EDRAM_MODE__MASK; 2376902e6eb8SRob Clark } 2377902e6eb8SRob Clark 2378902e6eb8SRob Clark #define REG_A2XX_A220_RB_LRZ_VSC_CONTROL 0x00002209 2379902e6eb8SRob Clark 2380902e6eb8SRob Clark #define REG_A2XX_RB_SAMPLE_POS 0x0000220a 2381902e6eb8SRob Clark 2382902e6eb8SRob Clark #define REG_A2XX_CLEAR_COLOR 0x0000220b 2383902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_RED__MASK 0x000000ff 2384902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_RED__SHIFT 0 2385902e6eb8SRob Clark static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val) 2386902e6eb8SRob Clark { 2387902e6eb8SRob Clark return ((val) << A2XX_CLEAR_COLOR_RED__SHIFT) & A2XX_CLEAR_COLOR_RED__MASK; 2388902e6eb8SRob Clark } 2389902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_GREEN__MASK 0x0000ff00 2390902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_GREEN__SHIFT 8 2391902e6eb8SRob Clark static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val) 2392902e6eb8SRob Clark { 2393902e6eb8SRob Clark return ((val) << A2XX_CLEAR_COLOR_GREEN__SHIFT) & A2XX_CLEAR_COLOR_GREEN__MASK; 2394902e6eb8SRob Clark } 2395902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_BLUE__MASK 0x00ff0000 2396902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_BLUE__SHIFT 16 2397902e6eb8SRob Clark static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val) 2398902e6eb8SRob Clark { 2399902e6eb8SRob Clark return ((val) << A2XX_CLEAR_COLOR_BLUE__SHIFT) & A2XX_CLEAR_COLOR_BLUE__MASK; 2400902e6eb8SRob Clark } 2401902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_ALPHA__MASK 0xff000000 2402902e6eb8SRob Clark #define A2XX_CLEAR_COLOR_ALPHA__SHIFT 24 2403902e6eb8SRob Clark static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val) 2404902e6eb8SRob Clark { 2405902e6eb8SRob Clark return ((val) << A2XX_CLEAR_COLOR_ALPHA__SHIFT) & A2XX_CLEAR_COLOR_ALPHA__MASK; 2406902e6eb8SRob Clark } 2407902e6eb8SRob Clark 2408902e6eb8SRob Clark #define REG_A2XX_A220_GRAS_CONTROL 0x00002210 2409902e6eb8SRob Clark 2410902e6eb8SRob Clark #define REG_A2XX_PA_SU_POINT_SIZE 0x00002280 2411902e6eb8SRob Clark #define A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK 0x0000ffff 2412902e6eb8SRob Clark #define A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT 0 2413902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val) 2414902e6eb8SRob Clark { 2415bc00ae02SRob Clark return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK; 2416902e6eb8SRob Clark } 2417902e6eb8SRob Clark #define A2XX_PA_SU_POINT_SIZE_WIDTH__MASK 0xffff0000 2418902e6eb8SRob Clark #define A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT 16 2419902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val) 2420902e6eb8SRob Clark { 2421bc00ae02SRob Clark return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK; 2422902e6eb8SRob Clark } 2423902e6eb8SRob Clark 2424902e6eb8SRob Clark #define REG_A2XX_PA_SU_POINT_MINMAX 0x00002281 2425902e6eb8SRob Clark #define A2XX_PA_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 2426902e6eb8SRob Clark #define A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT 0 2427902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val) 2428902e6eb8SRob Clark { 2429bc00ae02SRob Clark return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK; 2430902e6eb8SRob Clark } 2431902e6eb8SRob Clark #define A2XX_PA_SU_POINT_MINMAX_MAX__MASK 0xffff0000 2432902e6eb8SRob Clark #define A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT 16 2433902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val) 2434902e6eb8SRob Clark { 2435bc00ae02SRob Clark return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK; 2436902e6eb8SRob Clark } 2437902e6eb8SRob Clark 2438902e6eb8SRob Clark #define REG_A2XX_PA_SU_LINE_CNTL 0x00002282 2439902e6eb8SRob Clark #define A2XX_PA_SU_LINE_CNTL_WIDTH__MASK 0x0000ffff 2440902e6eb8SRob Clark #define A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT 0 2441902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val) 2442902e6eb8SRob Clark { 2443bc00ae02SRob Clark return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK; 2444902e6eb8SRob Clark } 2445902e6eb8SRob Clark 2446902e6eb8SRob Clark #define REG_A2XX_PA_SC_LINE_STIPPLE 0x00002283 2447902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK 0x0000ffff 2448902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT 0 2449902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val) 2450902e6eb8SRob Clark { 2451902e6eb8SRob Clark return ((val) << A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK; 2452902e6eb8SRob Clark } 2453902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK 0x00ff0000 2454902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT 16 2455902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val) 2456902e6eb8SRob Clark { 2457902e6eb8SRob Clark return ((val) << A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK; 2458902e6eb8SRob Clark } 2459902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK 0x10000000 2460902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT 28 2461902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val) 2462902e6eb8SRob Clark { 2463902e6eb8SRob Clark return ((val) << A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK; 2464902e6eb8SRob Clark } 2465902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK 0x60000000 2466902e6eb8SRob Clark #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT 29 2467902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val) 2468902e6eb8SRob Clark { 2469902e6eb8SRob Clark return ((val) << A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK; 2470902e6eb8SRob Clark } 2471902e6eb8SRob Clark 2472902e6eb8SRob Clark #define REG_A2XX_PA_SC_VIZ_QUERY 0x00002293 247352260ae4SRob Clark #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ENA 0x00000001 247452260ae4SRob Clark #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK 0x0000007e 247552260ae4SRob Clark #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT 1 247652260ae4SRob Clark static inline uint32_t A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID(uint32_t val) 247752260ae4SRob Clark { 247852260ae4SRob Clark return ((val) << A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT) & A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK; 247952260ae4SRob Clark } 248052260ae4SRob Clark #define A2XX_PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z 0x00000100 2481902e6eb8SRob Clark 2482902e6eb8SRob Clark #define REG_A2XX_VGT_ENHANCE 0x00002294 2483902e6eb8SRob Clark 2484902e6eb8SRob Clark #define REG_A2XX_PA_SC_LINE_CNTL 0x00002300 2485902e6eb8SRob Clark #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK 0x0000ffff 2486902e6eb8SRob Clark #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT 0 2487902e6eb8SRob Clark static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val) 2488902e6eb8SRob Clark { 2489902e6eb8SRob Clark return ((val) << A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT) & A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK; 2490902e6eb8SRob Clark } 2491902e6eb8SRob Clark #define A2XX_PA_SC_LINE_CNTL_USE_BRES_CNTL 0x00000100 2492902e6eb8SRob Clark #define A2XX_PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH 0x00000200 2493902e6eb8SRob Clark #define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL 0x00000400 2494902e6eb8SRob Clark 2495902e6eb8SRob Clark #define REG_A2XX_PA_SC_AA_CONFIG 0x00002301 249652260ae4SRob Clark #define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK 0x00000007 249752260ae4SRob Clark #define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT 0 249852260ae4SRob Clark static inline uint32_t A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES(uint32_t val) 249952260ae4SRob Clark { 250052260ae4SRob Clark return ((val) << A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT) & A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK; 250152260ae4SRob Clark } 250252260ae4SRob Clark #define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK 0x0001e000 250352260ae4SRob Clark #define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT 13 250452260ae4SRob Clark static inline uint32_t A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST(uint32_t val) 250552260ae4SRob Clark { 250652260ae4SRob Clark return ((val) << A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT) & A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK; 250752260ae4SRob Clark } 2508902e6eb8SRob Clark 2509902e6eb8SRob Clark #define REG_A2XX_PA_SU_VTX_CNTL 0x00002302 2510902e6eb8SRob Clark #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK 0x00000001 2511902e6eb8SRob Clark #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT 0 2512902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val) 2513902e6eb8SRob Clark { 2514902e6eb8SRob Clark return ((val) << A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT) & A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK; 2515902e6eb8SRob Clark } 2516902e6eb8SRob Clark #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK 0x00000006 2517902e6eb8SRob Clark #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT 1 2518902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val) 2519902e6eb8SRob Clark { 2520902e6eb8SRob Clark return ((val) << A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK; 2521902e6eb8SRob Clark } 2522902e6eb8SRob Clark #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK 0x00000380 2523902e6eb8SRob Clark #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT 7 2524902e6eb8SRob Clark static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val) 2525902e6eb8SRob Clark { 2526902e6eb8SRob Clark return ((val) << A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK; 2527902e6eb8SRob Clark } 2528902e6eb8SRob Clark 2529902e6eb8SRob Clark #define REG_A2XX_PA_CL_GB_VERT_CLIP_ADJ 0x00002303 2530902e6eb8SRob Clark #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK 0xffffffff 2531902e6eb8SRob Clark #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT 0 2532902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val) 2533902e6eb8SRob Clark { 2534902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK; 2535902e6eb8SRob Clark } 2536902e6eb8SRob Clark 2537902e6eb8SRob Clark #define REG_A2XX_PA_CL_GB_VERT_DISC_ADJ 0x00002304 2538902e6eb8SRob Clark #define A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK 0xffffffff 2539902e6eb8SRob Clark #define A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT 0 2540902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val) 2541902e6eb8SRob Clark { 2542902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK; 2543902e6eb8SRob Clark } 2544902e6eb8SRob Clark 2545902e6eb8SRob Clark #define REG_A2XX_PA_CL_GB_HORZ_CLIP_ADJ 0x00002305 2546902e6eb8SRob Clark #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK 0xffffffff 2547902e6eb8SRob Clark #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT 0 2548902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val) 2549902e6eb8SRob Clark { 2550902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK; 2551902e6eb8SRob Clark } 2552902e6eb8SRob Clark 2553902e6eb8SRob Clark #define REG_A2XX_PA_CL_GB_HORZ_DISC_ADJ 0x00002306 2554902e6eb8SRob Clark #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK 0xffffffff 2555902e6eb8SRob Clark #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT 0 2556902e6eb8SRob Clark static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val) 2557902e6eb8SRob Clark { 2558902e6eb8SRob Clark return ((fui(val)) << A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK; 2559902e6eb8SRob Clark } 2560902e6eb8SRob Clark 2561902e6eb8SRob Clark #define REG_A2XX_SQ_VS_CONST 0x00002307 2562902e6eb8SRob Clark #define A2XX_SQ_VS_CONST_BASE__MASK 0x000001ff 2563902e6eb8SRob Clark #define A2XX_SQ_VS_CONST_BASE__SHIFT 0 2564902e6eb8SRob Clark static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val) 2565902e6eb8SRob Clark { 2566902e6eb8SRob Clark return ((val) << A2XX_SQ_VS_CONST_BASE__SHIFT) & A2XX_SQ_VS_CONST_BASE__MASK; 2567902e6eb8SRob Clark } 2568902e6eb8SRob Clark #define A2XX_SQ_VS_CONST_SIZE__MASK 0x001ff000 2569902e6eb8SRob Clark #define A2XX_SQ_VS_CONST_SIZE__SHIFT 12 2570902e6eb8SRob Clark static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val) 2571902e6eb8SRob Clark { 2572902e6eb8SRob Clark return ((val) << A2XX_SQ_VS_CONST_SIZE__SHIFT) & A2XX_SQ_VS_CONST_SIZE__MASK; 2573902e6eb8SRob Clark } 2574902e6eb8SRob Clark 2575902e6eb8SRob Clark #define REG_A2XX_SQ_PS_CONST 0x00002308 2576902e6eb8SRob Clark #define A2XX_SQ_PS_CONST_BASE__MASK 0x000001ff 2577902e6eb8SRob Clark #define A2XX_SQ_PS_CONST_BASE__SHIFT 0 2578902e6eb8SRob Clark static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val) 2579902e6eb8SRob Clark { 2580902e6eb8SRob Clark return ((val) << A2XX_SQ_PS_CONST_BASE__SHIFT) & A2XX_SQ_PS_CONST_BASE__MASK; 2581902e6eb8SRob Clark } 2582902e6eb8SRob Clark #define A2XX_SQ_PS_CONST_SIZE__MASK 0x001ff000 2583902e6eb8SRob Clark #define A2XX_SQ_PS_CONST_SIZE__SHIFT 12 2584902e6eb8SRob Clark static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val) 2585902e6eb8SRob Clark { 2586902e6eb8SRob Clark return ((val) << A2XX_SQ_PS_CONST_SIZE__SHIFT) & A2XX_SQ_PS_CONST_SIZE__MASK; 2587902e6eb8SRob Clark } 2588902e6eb8SRob Clark 2589902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_MISC_0 0x00002309 2590902e6eb8SRob Clark 2591902e6eb8SRob Clark #define REG_A2XX_SQ_DEBUG_MISC_1 0x0000230a 2592902e6eb8SRob Clark 2593902e6eb8SRob Clark #define REG_A2XX_PA_SC_AA_MASK 0x00002312 2594902e6eb8SRob Clark 2595902e6eb8SRob Clark #define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL 0x00002316 259652260ae4SRob Clark #define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK 0x00000007 259752260ae4SRob Clark #define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT 0 259852260ae4SRob Clark static inline uint32_t A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH(uint32_t val) 259952260ae4SRob Clark { 260052260ae4SRob Clark return ((val) << A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT) & A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK; 260152260ae4SRob Clark } 2602902e6eb8SRob Clark 2603902e6eb8SRob Clark #define REG_A2XX_VGT_OUT_DEALLOC_CNTL 0x00002317 260452260ae4SRob Clark #define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK 0x00000003 260552260ae4SRob Clark #define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT 0 260652260ae4SRob Clark static inline uint32_t A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST(uint32_t val) 260752260ae4SRob Clark { 260852260ae4SRob Clark return ((val) << A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT) & A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK; 260952260ae4SRob Clark } 2610902e6eb8SRob Clark 2611902e6eb8SRob Clark #define REG_A2XX_RB_COPY_CONTROL 0x00002318 2612902e6eb8SRob Clark #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK 0x00000007 2613902e6eb8SRob Clark #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT 0 2614902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val) 2615902e6eb8SRob Clark { 2616902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT) & A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK; 2617902e6eb8SRob Clark } 2618902e6eb8SRob Clark #define A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE 0x00000008 2619902e6eb8SRob Clark #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK 0x000000f0 2620902e6eb8SRob Clark #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT 4 2621902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val) 2622902e6eb8SRob Clark { 2623902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT) & A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK; 2624902e6eb8SRob Clark } 2625902e6eb8SRob Clark 2626902e6eb8SRob Clark #define REG_A2XX_RB_COPY_DEST_BASE 0x00002319 2627902e6eb8SRob Clark 2628902e6eb8SRob Clark #define REG_A2XX_RB_COPY_DEST_PITCH 0x0000231a 2629902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_PITCH__MASK 0xffffffff 2630902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_PITCH__SHIFT 0 2631902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val) 2632902e6eb8SRob Clark { 2633902e6eb8SRob Clark return ((val >> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK; 2634902e6eb8SRob Clark } 2635902e6eb8SRob Clark 2636902e6eb8SRob Clark #define REG_A2XX_RB_COPY_DEST_INFO 0x0000231b 2637902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK 0x00000007 2638902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT 0 2639902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val) 2640902e6eb8SRob Clark { 2641902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT) & A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK; 2642902e6eb8SRob Clark } 2643902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_LINEAR 0x00000008 2644902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000f0 2645902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 4 2646902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val) 2647902e6eb8SRob Clark { 2648902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A2XX_RB_COPY_DEST_INFO_FORMAT__MASK; 2649902e6eb8SRob Clark } 2650902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 2651902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 2652902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val) 2653902e6eb8SRob Clark { 2654902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A2XX_RB_COPY_DEST_INFO_SWAP__MASK; 2655902e6eb8SRob Clark } 2656902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 2657902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 2658902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 2659902e6eb8SRob Clark { 2660902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 2661902e6eb8SRob Clark } 2662902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK 0x00003000 2663902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT 12 2664902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val) 2665902e6eb8SRob Clark { 2666902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK; 2667902e6eb8SRob Clark } 2668902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_WRITE_RED 0x00004000 2669902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_WRITE_GREEN 0x00008000 2670902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_WRITE_BLUE 0x00010000 2671902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA 0x00020000 2672902e6eb8SRob Clark 2673902e6eb8SRob Clark #define REG_A2XX_RB_COPY_DEST_OFFSET 0x0000231c 2674902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_OFFSET_X__MASK 0x00001fff 2675902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_OFFSET_X__SHIFT 0 2676902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val) 2677902e6eb8SRob Clark { 2678902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_DEST_OFFSET_X__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_X__MASK; 2679902e6eb8SRob Clark } 2680902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_OFFSET_Y__MASK 0x03ffe000 2681902e6eb8SRob Clark #define A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT 13 2682902e6eb8SRob Clark static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val) 2683902e6eb8SRob Clark { 2684902e6eb8SRob Clark return ((val) << A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_Y__MASK; 2685902e6eb8SRob Clark } 2686902e6eb8SRob Clark 2687902e6eb8SRob Clark #define REG_A2XX_RB_DEPTH_CLEAR 0x0000231d 2688902e6eb8SRob Clark 2689902e6eb8SRob Clark #define REG_A2XX_RB_SAMPLE_COUNT_CTL 0x00002324 2690902e6eb8SRob Clark 2691902e6eb8SRob Clark #define REG_A2XX_RB_COLOR_DEST_MASK 0x00002326 2692902e6eb8SRob Clark 2693902e6eb8SRob Clark #define REG_A2XX_A225_GRAS_UCP0X 0x00002340 2694902e6eb8SRob Clark 2695902e6eb8SRob Clark #define REG_A2XX_A225_GRAS_UCP5W 0x00002357 2696902e6eb8SRob Clark 2697902e6eb8SRob Clark #define REG_A2XX_A225_GRAS_UCP_ENABLED 0x00002360 2698902e6eb8SRob Clark 2699902e6eb8SRob Clark #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE 0x00002380 2700902e6eb8SRob Clark 2701c28c82e9SRob Clark #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_OFFSET 0x00002381 2702c28c82e9SRob Clark 2703c28c82e9SRob Clark #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_SCALE 0x00002382 2704c28c82e9SRob Clark 2705902e6eb8SRob Clark #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET 0x00002383 2706902e6eb8SRob Clark 2707902e6eb8SRob Clark #define REG_A2XX_SQ_CONSTANT_0 0x00004000 2708902e6eb8SRob Clark 2709902e6eb8SRob Clark #define REG_A2XX_SQ_FETCH_0 0x00004800 2710902e6eb8SRob Clark 2711902e6eb8SRob Clark #define REG_A2XX_SQ_CF_BOOLEANS 0x00004900 2712902e6eb8SRob Clark 2713902e6eb8SRob Clark #define REG_A2XX_SQ_CF_LOOP 0x00004908 2714902e6eb8SRob Clark 2715902e6eb8SRob Clark #define REG_A2XX_COHER_SIZE_PM4 0x00000a29 2716902e6eb8SRob Clark 2717902e6eb8SRob Clark #define REG_A2XX_COHER_BASE_PM4 0x00000a2a 2718902e6eb8SRob Clark 2719902e6eb8SRob Clark #define REG_A2XX_COHER_STATUS_PM4 0x00000a2b 2720902e6eb8SRob Clark 2721c28c82e9SRob Clark #define REG_A2XX_PA_SU_PERFCOUNTER0_SELECT 0x00000c88 2722c28c82e9SRob Clark 2723c28c82e9SRob Clark #define REG_A2XX_PA_SU_PERFCOUNTER1_SELECT 0x00000c89 2724c28c82e9SRob Clark 2725c28c82e9SRob Clark #define REG_A2XX_PA_SU_PERFCOUNTER2_SELECT 0x00000c8a 2726c28c82e9SRob Clark 2727c28c82e9SRob Clark #define REG_A2XX_PA_SU_PERFCOUNTER3_SELECT 0x00000c8b 2728c28c82e9SRob Clark 2729c28c82e9SRob Clark #define REG_A2XX_PA_SU_PERFCOUNTER0_LOW 0x00000c8c 2730c28c82e9SRob Clark 2731c28c82e9SRob Clark #define REG_A2XX_PA_SU_PERFCOUNTER0_HI 0x00000c8d 2732c28c82e9SRob Clark 2733c28c82e9SRob Clark #define REG_A2XX_PA_SU_PERFCOUNTER1_LOW 0x00000c8e 2734c28c82e9SRob Clark 2735c28c82e9SRob Clark #define REG_A2XX_PA_SU_PERFCOUNTER1_HI 0x00000c8f 2736c28c82e9SRob Clark 2737c28c82e9SRob Clark #define REG_A2XX_PA_SU_PERFCOUNTER2_LOW 0x00000c90 2738c28c82e9SRob Clark 2739c28c82e9SRob Clark #define REG_A2XX_PA_SU_PERFCOUNTER2_HI 0x00000c91 2740c28c82e9SRob Clark 2741c28c82e9SRob Clark #define REG_A2XX_PA_SU_PERFCOUNTER3_LOW 0x00000c92 2742c28c82e9SRob Clark 2743c28c82e9SRob Clark #define REG_A2XX_PA_SU_PERFCOUNTER3_HI 0x00000c93 2744c28c82e9SRob Clark 2745c28c82e9SRob Clark #define REG_A2XX_PA_SC_PERFCOUNTER0_SELECT 0x00000c98 2746c28c82e9SRob Clark 2747c28c82e9SRob Clark #define REG_A2XX_PA_SC_PERFCOUNTER0_LOW 0x00000c99 2748c28c82e9SRob Clark 2749c28c82e9SRob Clark #define REG_A2XX_PA_SC_PERFCOUNTER0_HI 0x00000c9a 2750c28c82e9SRob Clark 2751c28c82e9SRob Clark #define REG_A2XX_VGT_PERFCOUNTER0_SELECT 0x00000c48 2752c28c82e9SRob Clark 2753c28c82e9SRob Clark #define REG_A2XX_VGT_PERFCOUNTER1_SELECT 0x00000c49 2754c28c82e9SRob Clark 2755c28c82e9SRob Clark #define REG_A2XX_VGT_PERFCOUNTER2_SELECT 0x00000c4a 2756c28c82e9SRob Clark 2757c28c82e9SRob Clark #define REG_A2XX_VGT_PERFCOUNTER3_SELECT 0x00000c4b 2758c28c82e9SRob Clark 2759c28c82e9SRob Clark #define REG_A2XX_VGT_PERFCOUNTER0_LOW 0x00000c4c 2760c28c82e9SRob Clark 2761c28c82e9SRob Clark #define REG_A2XX_VGT_PERFCOUNTER1_LOW 0x00000c4e 2762c28c82e9SRob Clark 2763c28c82e9SRob Clark #define REG_A2XX_VGT_PERFCOUNTER2_LOW 0x00000c50 2764c28c82e9SRob Clark 2765c28c82e9SRob Clark #define REG_A2XX_VGT_PERFCOUNTER3_LOW 0x00000c52 2766c28c82e9SRob Clark 2767c28c82e9SRob Clark #define REG_A2XX_VGT_PERFCOUNTER0_HI 0x00000c4d 2768c28c82e9SRob Clark 2769c28c82e9SRob Clark #define REG_A2XX_VGT_PERFCOUNTER1_HI 0x00000c4f 2770c28c82e9SRob Clark 2771c28c82e9SRob Clark #define REG_A2XX_VGT_PERFCOUNTER2_HI 0x00000c51 2772c28c82e9SRob Clark 2773c28c82e9SRob Clark #define REG_A2XX_VGT_PERFCOUNTER3_HI 0x00000c53 2774c28c82e9SRob Clark 2775c28c82e9SRob Clark #define REG_A2XX_TCR_PERFCOUNTER0_SELECT 0x00000e05 2776c28c82e9SRob Clark 2777c28c82e9SRob Clark #define REG_A2XX_TCR_PERFCOUNTER1_SELECT 0x00000e08 2778c28c82e9SRob Clark 2779c28c82e9SRob Clark #define REG_A2XX_TCR_PERFCOUNTER0_HI 0x00000e06 2780c28c82e9SRob Clark 2781c28c82e9SRob Clark #define REG_A2XX_TCR_PERFCOUNTER1_HI 0x00000e09 2782c28c82e9SRob Clark 2783c28c82e9SRob Clark #define REG_A2XX_TCR_PERFCOUNTER0_LOW 0x00000e07 2784c28c82e9SRob Clark 2785c28c82e9SRob Clark #define REG_A2XX_TCR_PERFCOUNTER1_LOW 0x00000e0a 2786c28c82e9SRob Clark 2787c28c82e9SRob Clark #define REG_A2XX_TP0_PERFCOUNTER0_SELECT 0x00000e1f 2788c28c82e9SRob Clark 2789c28c82e9SRob Clark #define REG_A2XX_TP0_PERFCOUNTER0_HI 0x00000e20 2790c28c82e9SRob Clark 2791c28c82e9SRob Clark #define REG_A2XX_TP0_PERFCOUNTER0_LOW 0x00000e21 2792c28c82e9SRob Clark 2793c28c82e9SRob Clark #define REG_A2XX_TP0_PERFCOUNTER1_SELECT 0x00000e22 2794c28c82e9SRob Clark 2795c28c82e9SRob Clark #define REG_A2XX_TP0_PERFCOUNTER1_HI 0x00000e23 2796c28c82e9SRob Clark 2797c28c82e9SRob Clark #define REG_A2XX_TP0_PERFCOUNTER1_LOW 0x00000e24 2798c28c82e9SRob Clark 2799c28c82e9SRob Clark #define REG_A2XX_TCM_PERFCOUNTER0_SELECT 0x00000e54 2800c28c82e9SRob Clark 2801c28c82e9SRob Clark #define REG_A2XX_TCM_PERFCOUNTER1_SELECT 0x00000e57 2802c28c82e9SRob Clark 2803c28c82e9SRob Clark #define REG_A2XX_TCM_PERFCOUNTER0_HI 0x00000e55 2804c28c82e9SRob Clark 2805c28c82e9SRob Clark #define REG_A2XX_TCM_PERFCOUNTER1_HI 0x00000e58 2806c28c82e9SRob Clark 2807c28c82e9SRob Clark #define REG_A2XX_TCM_PERFCOUNTER0_LOW 0x00000e56 2808c28c82e9SRob Clark 2809c28c82e9SRob Clark #define REG_A2XX_TCM_PERFCOUNTER1_LOW 0x00000e59 2810c28c82e9SRob Clark 2811c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER0_SELECT 0x00000e5a 2812c28c82e9SRob Clark 2813c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER1_SELECT 0x00000e5d 2814c28c82e9SRob Clark 2815c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER2_SELECT 0x00000e60 2816c28c82e9SRob Clark 2817c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER3_SELECT 0x00000e63 2818c28c82e9SRob Clark 2819c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER4_SELECT 0x00000e66 2820c28c82e9SRob Clark 2821c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER5_SELECT 0x00000e69 2822c28c82e9SRob Clark 2823c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER6_SELECT 0x00000e6c 2824c28c82e9SRob Clark 2825c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER7_SELECT 0x00000e6f 2826c28c82e9SRob Clark 2827c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER8_SELECT 0x00000e72 2828c28c82e9SRob Clark 2829c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER9_SELECT 0x00000e75 2830c28c82e9SRob Clark 2831c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER10_SELECT 0x00000e78 2832c28c82e9SRob Clark 2833c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER11_SELECT 0x00000e7b 2834c28c82e9SRob Clark 2835c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER0_HI 0x00000e5b 2836c28c82e9SRob Clark 2837c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER1_HI 0x00000e5e 2838c28c82e9SRob Clark 2839c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER2_HI 0x00000e61 2840c28c82e9SRob Clark 2841c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER3_HI 0x00000e64 2842c28c82e9SRob Clark 2843c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER4_HI 0x00000e67 2844c28c82e9SRob Clark 2845c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER5_HI 0x00000e6a 2846c28c82e9SRob Clark 2847c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER6_HI 0x00000e6d 2848c28c82e9SRob Clark 2849c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER7_HI 0x00000e70 2850c28c82e9SRob Clark 2851c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER8_HI 0x00000e73 2852c28c82e9SRob Clark 2853c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER9_HI 0x00000e76 2854c28c82e9SRob Clark 2855c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER10_HI 0x00000e79 2856c28c82e9SRob Clark 2857c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER11_HI 0x00000e7c 2858c28c82e9SRob Clark 2859c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER0_LOW 0x00000e5c 2860c28c82e9SRob Clark 2861c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER1_LOW 0x00000e5f 2862c28c82e9SRob Clark 2863c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER2_LOW 0x00000e62 2864c28c82e9SRob Clark 2865c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER3_LOW 0x00000e65 2866c28c82e9SRob Clark 2867c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER4_LOW 0x00000e68 2868c28c82e9SRob Clark 2869c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER5_LOW 0x00000e6b 2870c28c82e9SRob Clark 2871c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER6_LOW 0x00000e6e 2872c28c82e9SRob Clark 2873c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER7_LOW 0x00000e71 2874c28c82e9SRob Clark 2875c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER8_LOW 0x00000e74 2876c28c82e9SRob Clark 2877c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER9_LOW 0x00000e77 2878c28c82e9SRob Clark 2879c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER10_LOW 0x00000e7a 2880c28c82e9SRob Clark 2881c28c82e9SRob Clark #define REG_A2XX_TCF_PERFCOUNTER11_LOW 0x00000e7d 2882c28c82e9SRob Clark 2883c28c82e9SRob Clark #define REG_A2XX_SQ_PERFCOUNTER0_SELECT 0x00000dc8 2884c28c82e9SRob Clark 2885c28c82e9SRob Clark #define REG_A2XX_SQ_PERFCOUNTER1_SELECT 0x00000dc9 2886c28c82e9SRob Clark 2887c28c82e9SRob Clark #define REG_A2XX_SQ_PERFCOUNTER2_SELECT 0x00000dca 2888c28c82e9SRob Clark 2889c28c82e9SRob Clark #define REG_A2XX_SQ_PERFCOUNTER3_SELECT 0x00000dcb 2890c28c82e9SRob Clark 2891c28c82e9SRob Clark #define REG_A2XX_SQ_PERFCOUNTER0_LOW 0x00000dcc 2892c28c82e9SRob Clark 2893c28c82e9SRob Clark #define REG_A2XX_SQ_PERFCOUNTER0_HI 0x00000dcd 2894c28c82e9SRob Clark 2895c28c82e9SRob Clark #define REG_A2XX_SQ_PERFCOUNTER1_LOW 0x00000dce 2896c28c82e9SRob Clark 2897c28c82e9SRob Clark #define REG_A2XX_SQ_PERFCOUNTER1_HI 0x00000dcf 2898c28c82e9SRob Clark 2899c28c82e9SRob Clark #define REG_A2XX_SQ_PERFCOUNTER2_LOW 0x00000dd0 2900c28c82e9SRob Clark 2901c28c82e9SRob Clark #define REG_A2XX_SQ_PERFCOUNTER2_HI 0x00000dd1 2902c28c82e9SRob Clark 2903c28c82e9SRob Clark #define REG_A2XX_SQ_PERFCOUNTER3_LOW 0x00000dd2 2904c28c82e9SRob Clark 2905c28c82e9SRob Clark #define REG_A2XX_SQ_PERFCOUNTER3_HI 0x00000dd3 2906c28c82e9SRob Clark 2907c28c82e9SRob Clark #define REG_A2XX_SX_PERFCOUNTER0_SELECT 0x00000dd4 2908c28c82e9SRob Clark 2909c28c82e9SRob Clark #define REG_A2XX_SX_PERFCOUNTER0_LOW 0x00000dd8 2910c28c82e9SRob Clark 2911c28c82e9SRob Clark #define REG_A2XX_SX_PERFCOUNTER0_HI 0x00000dd9 2912c28c82e9SRob Clark 2913c28c82e9SRob Clark #define REG_A2XX_MH_PERFCOUNTER0_SELECT 0x00000a46 2914c28c82e9SRob Clark 2915c28c82e9SRob Clark #define REG_A2XX_MH_PERFCOUNTER1_SELECT 0x00000a4a 2916c28c82e9SRob Clark 2917c28c82e9SRob Clark #define REG_A2XX_MH_PERFCOUNTER0_CONFIG 0x00000a47 2918c28c82e9SRob Clark 2919c28c82e9SRob Clark #define REG_A2XX_MH_PERFCOUNTER1_CONFIG 0x00000a4b 2920c28c82e9SRob Clark 2921c28c82e9SRob Clark #define REG_A2XX_MH_PERFCOUNTER0_LOW 0x00000a48 2922c28c82e9SRob Clark 2923c28c82e9SRob Clark #define REG_A2XX_MH_PERFCOUNTER1_LOW 0x00000a4c 2924c28c82e9SRob Clark 2925c28c82e9SRob Clark #define REG_A2XX_MH_PERFCOUNTER0_HI 0x00000a49 2926c28c82e9SRob Clark 2927c28c82e9SRob Clark #define REG_A2XX_MH_PERFCOUNTER1_HI 0x00000a4d 2928c28c82e9SRob Clark 2929c28c82e9SRob Clark #define REG_A2XX_RB_PERFCOUNTER0_SELECT 0x00000f04 2930c28c82e9SRob Clark 2931*cc4c26d4SRob Clark #define REG_A2XX_RB_PERFCOUNTER1_SELECT 0x00000f05 2932*cc4c26d4SRob Clark 2933*cc4c26d4SRob Clark #define REG_A2XX_RB_PERFCOUNTER2_SELECT 0x00000f06 2934*cc4c26d4SRob Clark 2935*cc4c26d4SRob Clark #define REG_A2XX_RB_PERFCOUNTER3_SELECT 0x00000f07 2936*cc4c26d4SRob Clark 2937c28c82e9SRob Clark #define REG_A2XX_RB_PERFCOUNTER0_LOW 0x00000f08 2938c28c82e9SRob Clark 2939c28c82e9SRob Clark #define REG_A2XX_RB_PERFCOUNTER0_HI 0x00000f09 2940c28c82e9SRob Clark 2941*cc4c26d4SRob Clark #define REG_A2XX_RB_PERFCOUNTER1_LOW 0x00000f0a 2942*cc4c26d4SRob Clark 2943*cc4c26d4SRob Clark #define REG_A2XX_RB_PERFCOUNTER1_HI 0x00000f0b 2944*cc4c26d4SRob Clark 2945*cc4c26d4SRob Clark #define REG_A2XX_RB_PERFCOUNTER2_LOW 0x00000f0c 2946*cc4c26d4SRob Clark 2947*cc4c26d4SRob Clark #define REG_A2XX_RB_PERFCOUNTER2_HI 0x00000f0d 2948*cc4c26d4SRob Clark 2949*cc4c26d4SRob Clark #define REG_A2XX_RB_PERFCOUNTER3_LOW 0x00000f0e 2950*cc4c26d4SRob Clark 2951*cc4c26d4SRob Clark #define REG_A2XX_RB_PERFCOUNTER3_HI 0x00000f0f 2952*cc4c26d4SRob Clark 2953902e6eb8SRob Clark #define REG_A2XX_SQ_TEX_0 0x00000000 2954ccdf7e28SRob Clark #define A2XX_SQ_TEX_0_TYPE__MASK 0x00000003 2955ccdf7e28SRob Clark #define A2XX_SQ_TEX_0_TYPE__SHIFT 0 2956ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_0_TYPE(enum sq_tex_type val) 2957ccdf7e28SRob Clark { 2958ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_0_TYPE__SHIFT) & A2XX_SQ_TEX_0_TYPE__MASK; 2959ccdf7e28SRob Clark } 2960ccdf7e28SRob Clark #define A2XX_SQ_TEX_0_SIGN_X__MASK 0x0000000c 2961ccdf7e28SRob Clark #define A2XX_SQ_TEX_0_SIGN_X__SHIFT 2 2962ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_0_SIGN_X(enum sq_tex_sign val) 2963ccdf7e28SRob Clark { 2964ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_0_SIGN_X__SHIFT) & A2XX_SQ_TEX_0_SIGN_X__MASK; 2965ccdf7e28SRob Clark } 2966ccdf7e28SRob Clark #define A2XX_SQ_TEX_0_SIGN_Y__MASK 0x00000030 2967ccdf7e28SRob Clark #define A2XX_SQ_TEX_0_SIGN_Y__SHIFT 4 2968ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_0_SIGN_Y(enum sq_tex_sign val) 2969ccdf7e28SRob Clark { 2970ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_0_SIGN_Y__SHIFT) & A2XX_SQ_TEX_0_SIGN_Y__MASK; 2971ccdf7e28SRob Clark } 2972ccdf7e28SRob Clark #define A2XX_SQ_TEX_0_SIGN_Z__MASK 0x000000c0 2973ccdf7e28SRob Clark #define A2XX_SQ_TEX_0_SIGN_Z__SHIFT 6 2974ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_0_SIGN_Z(enum sq_tex_sign val) 2975ccdf7e28SRob Clark { 2976ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_0_SIGN_Z__SHIFT) & A2XX_SQ_TEX_0_SIGN_Z__MASK; 2977ccdf7e28SRob Clark } 2978ccdf7e28SRob Clark #define A2XX_SQ_TEX_0_SIGN_W__MASK 0x00000300 2979ccdf7e28SRob Clark #define A2XX_SQ_TEX_0_SIGN_W__SHIFT 8 2980ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_0_SIGN_W(enum sq_tex_sign val) 2981ccdf7e28SRob Clark { 2982ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_0_SIGN_W__SHIFT) & A2XX_SQ_TEX_0_SIGN_W__MASK; 2983ccdf7e28SRob Clark } 2984902e6eb8SRob Clark #define A2XX_SQ_TEX_0_CLAMP_X__MASK 0x00001c00 2985902e6eb8SRob Clark #define A2XX_SQ_TEX_0_CLAMP_X__SHIFT 10 2986902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val) 2987902e6eb8SRob Clark { 2988902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_0_CLAMP_X__SHIFT) & A2XX_SQ_TEX_0_CLAMP_X__MASK; 2989902e6eb8SRob Clark } 2990902e6eb8SRob Clark #define A2XX_SQ_TEX_0_CLAMP_Y__MASK 0x0000e000 2991902e6eb8SRob Clark #define A2XX_SQ_TEX_0_CLAMP_Y__SHIFT 13 2992902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val) 2993902e6eb8SRob Clark { 2994902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_0_CLAMP_Y__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Y__MASK; 2995902e6eb8SRob Clark } 2996902e6eb8SRob Clark #define A2XX_SQ_TEX_0_CLAMP_Z__MASK 0x00070000 2997902e6eb8SRob Clark #define A2XX_SQ_TEX_0_CLAMP_Z__SHIFT 16 2998902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val) 2999902e6eb8SRob Clark { 3000902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK; 3001902e6eb8SRob Clark } 3002ccdf7e28SRob Clark #define A2XX_SQ_TEX_0_PITCH__MASK 0x7fc00000 3003902e6eb8SRob Clark #define A2XX_SQ_TEX_0_PITCH__SHIFT 22 3004902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val) 3005902e6eb8SRob Clark { 3006902e6eb8SRob Clark return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK; 3007902e6eb8SRob Clark } 3008c28c82e9SRob Clark #define A2XX_SQ_TEX_0_TILED 0x80000000 3009902e6eb8SRob Clark 3010902e6eb8SRob Clark #define REG_A2XX_SQ_TEX_1 0x00000001 3011ccdf7e28SRob Clark #define A2XX_SQ_TEX_1_FORMAT__MASK 0x0000003f 3012ccdf7e28SRob Clark #define A2XX_SQ_TEX_1_FORMAT__SHIFT 0 3013ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_1_FORMAT(enum a2xx_sq_surfaceformat val) 3014ccdf7e28SRob Clark { 3015ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_1_FORMAT__SHIFT) & A2XX_SQ_TEX_1_FORMAT__MASK; 3016ccdf7e28SRob Clark } 3017ccdf7e28SRob Clark #define A2XX_SQ_TEX_1_ENDIANNESS__MASK 0x000000c0 3018ccdf7e28SRob Clark #define A2XX_SQ_TEX_1_ENDIANNESS__SHIFT 6 3019ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_1_ENDIANNESS(enum sq_tex_endian val) 3020ccdf7e28SRob Clark { 3021ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_1_ENDIANNESS__SHIFT) & A2XX_SQ_TEX_1_ENDIANNESS__MASK; 3022ccdf7e28SRob Clark } 3023ccdf7e28SRob Clark #define A2XX_SQ_TEX_1_REQUEST_SIZE__MASK 0x00000300 3024ccdf7e28SRob Clark #define A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT 8 3025ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_1_REQUEST_SIZE(uint32_t val) 3026ccdf7e28SRob Clark { 3027ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT) & A2XX_SQ_TEX_1_REQUEST_SIZE__MASK; 3028ccdf7e28SRob Clark } 3029ccdf7e28SRob Clark #define A2XX_SQ_TEX_1_STACKED 0x00000400 3030ccdf7e28SRob Clark #define A2XX_SQ_TEX_1_CLAMP_POLICY__MASK 0x00000800 3031ccdf7e28SRob Clark #define A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT 11 3032ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_1_CLAMP_POLICY(enum sq_tex_clamp_policy val) 3033ccdf7e28SRob Clark { 3034ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT) & A2XX_SQ_TEX_1_CLAMP_POLICY__MASK; 3035ccdf7e28SRob Clark } 3036ccdf7e28SRob Clark #define A2XX_SQ_TEX_1_BASE_ADDRESS__MASK 0xfffff000 3037ccdf7e28SRob Clark #define A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT 12 3038ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_1_BASE_ADDRESS(uint32_t val) 3039ccdf7e28SRob Clark { 3040ccdf7e28SRob Clark return ((val >> 12) << A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT) & A2XX_SQ_TEX_1_BASE_ADDRESS__MASK; 3041ccdf7e28SRob Clark } 3042902e6eb8SRob Clark 3043902e6eb8SRob Clark #define REG_A2XX_SQ_TEX_2 0x00000002 3044902e6eb8SRob Clark #define A2XX_SQ_TEX_2_WIDTH__MASK 0x00001fff 3045902e6eb8SRob Clark #define A2XX_SQ_TEX_2_WIDTH__SHIFT 0 3046902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val) 3047902e6eb8SRob Clark { 3048902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_2_WIDTH__SHIFT) & A2XX_SQ_TEX_2_WIDTH__MASK; 3049902e6eb8SRob Clark } 3050902e6eb8SRob Clark #define A2XX_SQ_TEX_2_HEIGHT__MASK 0x03ffe000 3051902e6eb8SRob Clark #define A2XX_SQ_TEX_2_HEIGHT__SHIFT 13 3052902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val) 3053902e6eb8SRob Clark { 3054902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK; 3055902e6eb8SRob Clark } 3056ccdf7e28SRob Clark #define A2XX_SQ_TEX_2_DEPTH__MASK 0xfc000000 3057ccdf7e28SRob Clark #define A2XX_SQ_TEX_2_DEPTH__SHIFT 26 3058ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_2_DEPTH(uint32_t val) 3059ccdf7e28SRob Clark { 3060ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_2_DEPTH__SHIFT) & A2XX_SQ_TEX_2_DEPTH__MASK; 3061ccdf7e28SRob Clark } 3062902e6eb8SRob Clark 3063902e6eb8SRob Clark #define REG_A2XX_SQ_TEX_3 0x00000003 3064ccdf7e28SRob Clark #define A2XX_SQ_TEX_3_NUM_FORMAT__MASK 0x00000001 3065ccdf7e28SRob Clark #define A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT 0 3066ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_3_NUM_FORMAT(enum sq_tex_num_format val) 3067ccdf7e28SRob Clark { 3068ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT) & A2XX_SQ_TEX_3_NUM_FORMAT__MASK; 3069ccdf7e28SRob Clark } 3070902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_X__MASK 0x0000000e 3071902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_X__SHIFT 1 3072902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val) 3073902e6eb8SRob Clark { 3074902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_3_SWIZ_X__SHIFT) & A2XX_SQ_TEX_3_SWIZ_X__MASK; 3075902e6eb8SRob Clark } 3076902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_Y__MASK 0x00000070 3077902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_Y__SHIFT 4 3078902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val) 3079902e6eb8SRob Clark { 3080902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_3_SWIZ_Y__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Y__MASK; 3081902e6eb8SRob Clark } 3082902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_Z__MASK 0x00000380 3083902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_Z__SHIFT 7 3084902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val) 3085902e6eb8SRob Clark { 3086902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_3_SWIZ_Z__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Z__MASK; 3087902e6eb8SRob Clark } 3088902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_W__MASK 0x00001c00 3089902e6eb8SRob Clark #define A2XX_SQ_TEX_3_SWIZ_W__SHIFT 10 3090902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val) 3091902e6eb8SRob Clark { 3092902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK; 3093902e6eb8SRob Clark } 3094ccdf7e28SRob Clark #define A2XX_SQ_TEX_3_EXP_ADJUST__MASK 0x0007e000 3095ccdf7e28SRob Clark #define A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT 13 3096c28c82e9SRob Clark static inline uint32_t A2XX_SQ_TEX_3_EXP_ADJUST(int32_t val) 3097ccdf7e28SRob Clark { 3098ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT) & A2XX_SQ_TEX_3_EXP_ADJUST__MASK; 3099ccdf7e28SRob Clark } 3100902e6eb8SRob Clark #define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK 0x00180000 3101902e6eb8SRob Clark #define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT 19 3102902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val) 3103902e6eb8SRob Clark { 3104902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK; 3105902e6eb8SRob Clark } 3106902e6eb8SRob Clark #define A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK 0x00600000 3107902e6eb8SRob Clark #define A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT 21 3108902e6eb8SRob Clark static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val) 3109902e6eb8SRob Clark { 3110902e6eb8SRob Clark return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK; 3111902e6eb8SRob Clark } 3112ccdf7e28SRob Clark #define A2XX_SQ_TEX_3_MIP_FILTER__MASK 0x01800000 3113ccdf7e28SRob Clark #define A2XX_SQ_TEX_3_MIP_FILTER__SHIFT 23 3114ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_3_MIP_FILTER(enum sq_tex_filter val) 3115ccdf7e28SRob Clark { 3116ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_3_MIP_FILTER__SHIFT) & A2XX_SQ_TEX_3_MIP_FILTER__MASK; 3117ccdf7e28SRob Clark } 3118ccdf7e28SRob Clark #define A2XX_SQ_TEX_3_ANISO_FILTER__MASK 0x0e000000 3119ccdf7e28SRob Clark #define A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT 25 3120ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_3_ANISO_FILTER(enum sq_tex_aniso_filter val) 3121ccdf7e28SRob Clark { 3122ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT) & A2XX_SQ_TEX_3_ANISO_FILTER__MASK; 3123ccdf7e28SRob Clark } 3124ccdf7e28SRob Clark #define A2XX_SQ_TEX_3_BORDER_SIZE__MASK 0x80000000 3125ccdf7e28SRob Clark #define A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT 31 3126ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_3_BORDER_SIZE(uint32_t val) 3127ccdf7e28SRob Clark { 3128ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT) & A2XX_SQ_TEX_3_BORDER_SIZE__MASK; 3129ccdf7e28SRob Clark } 3130ccdf7e28SRob Clark 3131ccdf7e28SRob Clark #define REG_A2XX_SQ_TEX_4 0x00000004 3132ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK 0x00000001 3133ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT 0 3134ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_4_VOL_MAG_FILTER(enum sq_tex_filter val) 3135ccdf7e28SRob Clark { 3136ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK; 3137ccdf7e28SRob Clark } 3138ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK 0x00000002 3139ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT 1 3140ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_4_VOL_MIN_FILTER(enum sq_tex_filter val) 3141ccdf7e28SRob Clark { 3142ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK; 3143ccdf7e28SRob Clark } 3144ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK 0x0000003c 3145ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT 2 3146ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_4_MIP_MIN_LEVEL(uint32_t val) 3147ccdf7e28SRob Clark { 3148ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT) & A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK; 3149ccdf7e28SRob Clark } 3150ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK 0x000003c0 3151ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT 6 3152ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_4_MIP_MAX_LEVEL(uint32_t val) 3153ccdf7e28SRob Clark { 3154ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT) & A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK; 3155ccdf7e28SRob Clark } 3156ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_MAX_ANISO_WALK 0x00000400 3157ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_MIN_ANISO_WALK 0x00000800 3158ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_LOD_BIAS__MASK 0x003ff000 3159ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_LOD_BIAS__SHIFT 12 3160ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_4_LOD_BIAS(float val) 3161ccdf7e28SRob Clark { 3162ccdf7e28SRob Clark return ((((int32_t)(val * 32.0))) << A2XX_SQ_TEX_4_LOD_BIAS__SHIFT) & A2XX_SQ_TEX_4_LOD_BIAS__MASK; 3163ccdf7e28SRob Clark } 3164ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK 0x07c00000 3165ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT 22 3166ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H(uint32_t val) 3167ccdf7e28SRob Clark { 3168ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT) & A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK; 3169ccdf7e28SRob Clark } 3170ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK 0xf8000000 3171ccdf7e28SRob Clark #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT 27 3172ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V(uint32_t val) 3173ccdf7e28SRob Clark { 3174ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT) & A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK; 3175ccdf7e28SRob Clark } 3176ccdf7e28SRob Clark 3177ccdf7e28SRob Clark #define REG_A2XX_SQ_TEX_5 0x00000005 3178ccdf7e28SRob Clark #define A2XX_SQ_TEX_5_BORDER_COLOR__MASK 0x00000003 3179ccdf7e28SRob Clark #define A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT 0 3180ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_5_BORDER_COLOR(enum sq_tex_border_color val) 3181ccdf7e28SRob Clark { 3182ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT) & A2XX_SQ_TEX_5_BORDER_COLOR__MASK; 3183ccdf7e28SRob Clark } 3184ccdf7e28SRob Clark #define A2XX_SQ_TEX_5_FORCE_BCW_MAX 0x00000004 3185ccdf7e28SRob Clark #define A2XX_SQ_TEX_5_TRI_CLAMP__MASK 0x00000018 3186ccdf7e28SRob Clark #define A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT 3 3187ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_5_TRI_CLAMP(uint32_t val) 3188ccdf7e28SRob Clark { 3189ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT) & A2XX_SQ_TEX_5_TRI_CLAMP__MASK; 3190ccdf7e28SRob Clark } 3191ccdf7e28SRob Clark #define A2XX_SQ_TEX_5_ANISO_BIAS__MASK 0x000001e0 3192ccdf7e28SRob Clark #define A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT 5 3193ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_5_ANISO_BIAS(float val) 3194ccdf7e28SRob Clark { 3195ccdf7e28SRob Clark return ((((int32_t)(val * 1.0))) << A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT) & A2XX_SQ_TEX_5_ANISO_BIAS__MASK; 3196ccdf7e28SRob Clark } 3197ccdf7e28SRob Clark #define A2XX_SQ_TEX_5_DIMENSION__MASK 0x00000600 3198ccdf7e28SRob Clark #define A2XX_SQ_TEX_5_DIMENSION__SHIFT 9 3199ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_5_DIMENSION(enum sq_tex_dimension val) 3200ccdf7e28SRob Clark { 3201ccdf7e28SRob Clark return ((val) << A2XX_SQ_TEX_5_DIMENSION__SHIFT) & A2XX_SQ_TEX_5_DIMENSION__MASK; 3202ccdf7e28SRob Clark } 3203ccdf7e28SRob Clark #define A2XX_SQ_TEX_5_PACKED_MIPS 0x00000800 3204ccdf7e28SRob Clark #define A2XX_SQ_TEX_5_MIP_ADDRESS__MASK 0xfffff000 3205ccdf7e28SRob Clark #define A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT 12 3206ccdf7e28SRob Clark static inline uint32_t A2XX_SQ_TEX_5_MIP_ADDRESS(uint32_t val) 3207ccdf7e28SRob Clark { 3208ccdf7e28SRob Clark return ((val >> 12) << A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT) & A2XX_SQ_TEX_5_MIP_ADDRESS__MASK; 3209ccdf7e28SRob Clark } 3210902e6eb8SRob Clark 3211902e6eb8SRob Clark 3212902e6eb8SRob Clark #endif /* A2XX_XML */ 3213